| blob | 0cd80b206a895894eb9daa91760d25ee428d4a18 |
1 /* Definitions of target machine for GNU compiler, Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* Things to do:
23 - longlong.h?
24 */
26 #undef SWITCH_TAKES_ARG
27 #undef WORD_SWITCH_TAKES_ARG
28 #undef HANDLE_SYSV_PRAGMA
29 #undef SIZE_TYPE
30 #undef PTRDIFF_TYPE
31 #undef WCHAR_TYPE
32 #undef WCHAR_TYPE_SIZE
33 #undef ASM_OUTPUT_EXTERNAL_LIBCALL
34 #undef TARGET_VERSION
35 #undef CPP_SPEC
36 #undef ASM_SPEC
37 #undef LINK_SPEC
38 #undef STARTFILE_SPEC
39 #undef ENDFILE_SPEC
40 #undef SUBTARGET_SWITCHES
42 #undef ASM_APP_ON
43 #undef ASM_APP_OFF
44 \f
46 /* M32R/X overrides. */
47 /* Print subsidiary information on the compiler version in use. */
50 /* Additional flags for the preprocessor. */
52 %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \
53 %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \
54 "
56 /* Assembler switches. */
57 #define ASM_CPU_SPEC \
58 "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
60 /* Use m32rx specific crt0/crtinit/crtfini files. */
61 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
64 /* Extra machine dependent switches. */
65 #define SUBTARGET_SWITCHES \
70 /* Define this macro as a C expression for the initializer of an array of
71 strings to tell the driver program which options are defaults for this
72 target and thus do not need to be handled specially when using
73 `MULTILIB_OPTIONS'. */
76 /* Number of additional registers the subtarget defines. */
77 #define SUBTARGET_NUM_REGISTERS 1
79 /* 1 for registers that cannot be allocated. */
80 #define SUBTARGET_FIXED_REGISTERS , 1
82 /* 1 for registers that are not available across function calls. */
83 #define SUBTARGET_CALL_USED_REGISTERS , 1
85 /* Order to allocate model specific registers. */
86 #define SUBTARGET_REG_ALLOC_ORDER , 19
88 /* Registers which are accumulators. */
89 #define SUBTARGET_REG_CLASS_ACCUM 0x80000
91 /* All registers added. */
92 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
94 /* Additional accumulator registers. */
95 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
97 /* Define additional register names. */
99 /* end M32R/X overrides. */
101 /* Print subsidiary information on the compiler version in use. */
102 #ifndef TARGET_VERSION
104 #endif
106 /* Switch Recognition by gcc.c. Add -G xx support. */
108 #undef SWITCH_TAKES_ARG
109 #define SWITCH_TAKES_ARG(CHAR) \
112 /* Names to predefine in the preprocessor for this target machine. */
113 /* __M32R__ is defined by the existing compiler so we use that. */
114 #define TARGET_CPU_CPP_BUILTINS() \
115 do \
116 { \
121 builtin_define (TARGET_BIG_ENDIAN \
123 if (flag_pic) \
124 { \
127 } \
128 } \
129 while (0)
131 /* This macro defines names of additional specifications to put in the specs
132 that can be used in various specifications like CC1_SPEC. Its definition
133 is an initializer with a subgrouping for each command option.
135 Each subgrouping contains a string constant, that defines the
136 specification name, and a string constant that used by the GCC driver
137 program.
139 Do not define this macro if it does not need to do anything. */
141 #ifndef SUBTARGET_EXTRA_SPECS
142 #define SUBTARGET_EXTRA_SPECS
143 #endif
145 #ifndef ASM_CPU_SPEC
147 #endif
149 #ifndef CPP_CPU_SPEC
151 #endif
153 #ifndef CC1_CPU_SPEC
155 #endif
157 #ifndef LINK_CPU_SPEC
159 #endif
161 #ifndef STARTFILE_CPU_SPEC
163 #endif
165 #ifndef ENDFILE_CPU_SPEC
167 #endif
169 #ifndef RELAX_SPEC
172 #else
174 #endif
175 #endif
177 #define EXTRA_SPECS \
185 SUBTARGET_EXTRA_SPECS
189 #undef CC1_SPEC
192 /* Options to pass on to the assembler. */
193 #undef ASM_SPEC
198 #undef STARTFILE_SPEC
201 #undef ENDFILE_SPEC
204 #undef LIB_SPEC
205 \f
206 /* Run-time compilation parameters selecting different hardware subsets. */
210 /* If nonzero, tell the linker to do relaxing.
211 We don't do anything with the option, other than recognize it.
212 LINK_SPEC handles passing -relax to the linker.
213 This can cause incorrect debugging information as line numbers may
214 turn out wrong. This shouldn't be specified unless accompanied with -O2
215 [where the user expects debugging information to be less accurate]. */
216 #define TARGET_RELAX_MASK (1 << 0)
218 /* For miscellaneous debugging purposes. */
219 #define TARGET_DEBUG_MASK (1 << 1)
220 #define TARGET_DEBUG (target_flags & TARGET_DEBUG_MASK)
222 /* Align loops to 32 byte boundaries (cache line size). */
223 /* ??? This option is experimental and is not documented. */
224 #define TARGET_ALIGN_LOOPS_MASK (1 << 2)
225 #define TARGET_ALIGN_LOOPS (target_flags & TARGET_ALIGN_LOOPS_MASK)
227 /* Change issue rate. */
228 #define TARGET_LOW_ISSUE_RATE_MASK (1 << 3)
229 #define TARGET_LOW_ISSUE_RATE (target_flags & TARGET_LOW_ISSUE_RATE_MASK)
231 /* Change branch cost */
232 #define TARGET_BRANCH_COST_MASK (1 << 4)
233 #define TARGET_BRANCH_COST (target_flags & TARGET_BRANCH_COST_MASK)
235 /* Target machine to compile for. */
236 #define TARGET_M32R 1
238 /* Support extended instruction set. */
239 #define TARGET_M32RX_MASK (1 << 5)
240 #define TARGET_M32RX (target_flags & TARGET_M32RX_MASK)
241 #undef TARGET_M32R
242 #define TARGET_M32R (! TARGET_M32RX)
244 /* Support extended instruction set of m32r2. */
245 #define TARGET_M32R2_MASK (1 << 6)
246 #define TARGET_M32R2 (target_flags & TARGET_M32R2_MASK)
247 #undef TARGET_M32R
248 #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2)
250 /* Big Endian Flag. */
251 #define BIG_ENDIAN_BIT (1 << 7)
252 #define TARGET_BIG_ENDIAN (target_flags & BIG_ENDIAN_BIT)
254 /* Little Endian Flag. */
255 #define LITTLE_ENDIAN_BIT (1 << 8)
257 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
258 #endif
260 /* Macro to define tables used to set the flags.
261 This is a list in braces of pairs in braces,
262 each pair being { "NAME", VALUE }
263 where VALUE is the bits to set or minus the bits to clear.
264 An empty string NAME is used to identify the default VALUE. */
266 #ifndef SUBTARGET_SWITCHES
267 #define SUBTARGET_SWITCHES
268 #endif
270 #ifndef TARGET_DEFAULT
271 #define TARGET_DEFAULT 0
272 #endif
274 #define TARGET_SWITCHES \
275 { \
276 /* { "relax", TARGET_RELAX_MASK, "" }, \
289 SUBTARGET_SWITCHES \
291 }
296 /* Cache-flush support. */
301 #ifndef SUBTARGET_OPTIONS
302 #define SUBTARGET_OPTIONS
303 #endif
305 #define TARGET_OPTIONS \
306 { \
319 SUBTARGET_OPTIONS \
320 }
322 /* Code Models
324 Code models are used to select between two choices of two separate
325 possibilities (address space size, call insn to use):
327 small: addresses use 24 bits, use bl to make calls
328 medium: addresses use 32 bits, use bl to make calls (*1)
329 large: addresses use 32 bits, use seth/add3/jl to make calls (*2)
331 The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but
332 using this one doesn't make much sense.
334 (*1) The linker may eventually be able to relax seth/add3 -> ld24.
335 (*2) The linker may eventually be able to relax seth/add3/jl -> bl.
337 Internally these are recorded as TARGET_ADDR{24,32} and
338 TARGET_CALL{26,32}.
340 The __model__ attribute can be used to select the code model to use when
341 accessing particular objects. */
346 #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL)
347 #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM)
348 #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE)
349 #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL)
350 #define TARGET_ADDR32 (! TARGET_ADDR24)
351 #define TARGET_CALL26 (! TARGET_CALL32)
352 #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE)
354 /* The default is the small model. */
355 #ifndef M32R_MODEL_DEFAULT
357 #endif
359 /* Small Data Area
361 The SDA consists of sections .sdata, .sbss, and .scommon.
362 .scommon isn't a real section, symbols in it have their section index
363 set to SHN_M32R_SCOMMON, though support for it exists in the linker script.
365 Two switches control the SDA:
367 -G NNN - specifies the maximum size of variable to go in the SDA
369 -msdata=foo - specifies how such variables are handled
371 -msdata=none - small data area is disabled
373 -msdata=sdata - small data goes in the SDA, special code isn't
374 generated to use it, and special relocs aren't
375 generated
377 -msdata=use - small data goes in the SDA, special code is generated
378 to use the SDA and special relocs are generated
380 The SDA is not multilib'd, it isn't necessary.
381 MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd
382 libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use
383 -msdata=use will successfully link with them (references in header files
384 will cause the compiler to emit code that refers to library objects in
385 .data). ??? There can be a problem if the user passes a -G value greater
386 than the default and a library object in a header file is that size.
387 The default is 8 so this should be rare - if it occurs the user
388 is required to rebuild the libraries or use a smaller value for -G. */
390 /* Maximum size of variables that go in .sdata/.sbss.
391 The -msdata=foo switch also controls how small variables are handled. */
392 #ifndef SDATA_DEFAULT_SIZE
393 #define SDATA_DEFAULT_SIZE 8
394 #endif
399 #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE)
400 #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA)
401 #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE)
403 /* Default is to disable the SDA
404 [for upward compatibility with previous toolchains]. */
405 #ifndef M32R_SDATA_DEFAULT
407 #endif
409 /* Define this macro as a C expression for the initializer of an array of
410 strings to tell the driver program which options are defaults for this
411 target and thus do not need to be handled specially when using
412 `MULTILIB_OPTIONS'. */
413 #ifndef SUBTARGET_MULTILIB_DEFAULTS
414 #define SUBTARGET_MULTILIB_DEFAULTS
415 #endif
417 #ifndef MULTILIB_DEFAULTS
419 #endif
421 /* Sometimes certain combinations of command options do not make
422 sense on a particular target machine. You can define a macro
423 `OVERRIDE_OPTIONS' to take account of this. This macro, if
424 defined, is executed once just after all the command options have
425 been parsed.
427 Don't use this macro to turn on various extra optimizations for
428 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
430 #ifndef SUBTARGET_OVERRIDE_OPTIONS
431 #define SUBTARGET_OVERRIDE_OPTIONS
432 #endif
434 #define OVERRIDE_OPTIONS \
435 do \
436 { \
437 /* These need to be done at start up. \
439 m32r_init (); \
440 SUBTARGET_OVERRIDE_OPTIONS \
441 } \
442 while (0)
444 #ifndef SUBTARGET_OPTIMIZATION_OPTIONS
445 #define SUBTARGET_OPTIMIZATION_OPTIONS
446 #endif
448 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
449 do \
450 { \
451 if (LEVEL == 1) \
452 flag_regmove = TRUE; \
453 \
454 if (SIZE) \
455 { \
456 flag_omit_frame_pointer = TRUE; \
457 flag_strength_reduce = FALSE; \
458 } \
459 \
460 SUBTARGET_OPTIMIZATION_OPTIONS \
461 } \
462 while (0)
464 /* Define this macro if debugging can be performed even without a
465 frame pointer. If this macro is defined, GCC will turn on the
466 `-fomit-frame-pointer' option whenever `-O' is specified. */
467 #define CAN_DEBUG_WITHOUT_FP
468 \f
469 /* Target machine storage layout. */
471 /* Define this if most significant bit is lowest numbered
472 in instructions that operate on numbered bit-fields. */
473 #define BITS_BIG_ENDIAN 1
475 /* Define this if most significant byte of a word is the lowest numbered. */
476 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
478 /* Define this if most significant word of a multiword number is the lowest
479 numbered. */
480 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
482 /* Define this macro if WORDS_BIG_ENDIAN is not constant. This must
483 be a constant value with the same meaning as WORDS_BIG_ENDIAN,
484 which will be used only when compiling libgcc2.c. Typically the
485 value will be set based on preprocessor defines. */
486 /*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/
488 /* Width of a word, in units (bytes). */
489 #define UNITS_PER_WORD 4
491 /* Define this macro if it is advisable to hold scalars in registers
492 in a wider mode than that declared by the program. In such cases,
493 the value is constrained to be within the bounds of the declared
494 type, but kept valid in the wider mode. The signedness of the
495 extension may differ from that of the type. */
496 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
497 if (GET_MODE_CLASS (MODE) == MODE_INT \
498 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
499 { \
500 (MODE) = SImode; \
501 }
503 /* Define this macro if the promotion described by `PROMOTE_MODE'
504 should also be done for outgoing function arguments. */
505 /*#define PROMOTE_FUNCTION_ARGS*/
507 /* Likewise, if the function return value is promoted.
508 If defined, FUNCTION_VALUE must perform the same promotions done by
509 PROMOTE_MODE. */
510 /*#define PROMOTE_FUNCTION_RETURN*/
512 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
513 #define PARM_BOUNDARY 32
515 /* Boundary (in *bits*) on which stack pointer should be aligned. */
516 #define STACK_BOUNDARY 32
518 /* ALIGN FRAMES on word boundaries */
519 #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3)
521 /* Allocation boundary (in *bits*) for the code of a function. */
522 #define FUNCTION_BOUNDARY 32
524 /* Alignment of field after `int : 0' in a structure. */
525 #define EMPTY_FIELD_BOUNDARY 32
527 /* Every structure's size must be a multiple of this. */
528 #define STRUCTURE_SIZE_BOUNDARY 8
530 /* A bit-field declared as `int' forces `int' alignment for the struct. */
531 #define PCC_BITFIELD_TYPE_MATTERS 1
533 /* No data type wants to be aligned rounder than this. */
534 #define BIGGEST_ALIGNMENT 32
536 /* The best alignment to use in cases where we have a choice. */
537 #define FASTEST_ALIGNMENT 32
539 /* Make strings word-aligned so strcpy from constants will be faster. */
540 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
541 ((TREE_CODE (EXP) == STRING_CST \
542 && (ALIGN) < FASTEST_ALIGNMENT) \
543 ? FASTEST_ALIGNMENT : (ALIGN))
545 /* Make arrays of chars word-aligned for the same reasons. */
546 #define DATA_ALIGNMENT(TYPE, ALIGN) \
547 (TREE_CODE (TYPE) == ARRAY_TYPE \
548 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
549 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
551 /* Set this nonzero if move instructions will actually fail to work
552 when given unaligned data. */
553 #define STRICT_ALIGNMENT 1
555 /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */
556 #define LABEL_ALIGN(insn) 2
557 \f
558 /* Layout of source language data types. */
560 #define SHORT_TYPE_SIZE 16
561 #define INT_TYPE_SIZE 32
562 #define LONG_TYPE_SIZE 32
563 #define LONG_LONG_TYPE_SIZE 64
564 #define FLOAT_TYPE_SIZE 32
565 #define DOUBLE_TYPE_SIZE 64
566 #define LONG_DOUBLE_TYPE_SIZE 64
568 /* Define this as 1 if `char' should by default be signed; else as 0. */
569 #define DEFAULT_SIGNED_CHAR 1
574 #define WCHAR_TYPE_SIZE 16
575 \f
576 /* Standard register usage. */
578 /* Number of actual hardware registers.
579 The hardware registers are assigned numbers for the compiler
580 from 0 to just below FIRST_PSEUDO_REGISTER.
581 All registers that the compiler knows about must be given numbers,
582 even those that are not normally considered general registers. */
584 #define M32R_NUM_REGISTERS 19
586 #ifndef SUBTARGET_NUM_REGISTERS
587 #define SUBTARGET_NUM_REGISTERS 0
588 #endif
590 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
592 /* 1 for registers that have pervasive standard uses
593 and are not available for the register allocator.
595 0-3 - arguments/results
596 4-5 - call used [4 is used as a tmp during prologue/epilogue generation]
597 6 - call used, gptmp
598 7 - call used, static chain pointer
599 8-11 - call saved
600 12 - call saved [reserved for global pointer]
601 13 - frame pointer
602 14 - subroutine link register
603 15 - stack pointer
604 16 - arg pointer
605 17 - carry flag
606 18 - accumulator
607 19 - accumulator 1 in the m32r/x
608 By default, the extension registers are not available. */
610 #ifndef SUBTARGET_FIXED_REGISTERS
611 #define SUBTARGET_FIXED_REGISTERS
612 #endif
614 #define FIXED_REGISTERS \
615 { \
616 0, 0, 0, 0, 0, 0, 0, 0, \
617 0, 0, 0, 0, 0, 0, 0, 1, \
618 1, 1, 1 \
619 SUBTARGET_FIXED_REGISTERS \
620 }
622 /* 1 for registers not available across function calls.
623 These must include the FIXED_REGISTERS and also any
624 registers that can be used without being saved.
625 The latter must include the registers where values are returned
626 and the register where structure-value addresses are passed.
627 Aside from that, you can include as many other registers as you like. */
629 #ifndef SUBTARGET_CALL_USED_REGISTERS
630 #define SUBTARGET_CALL_USED_REGISTERS
631 #endif
633 #define CALL_USED_REGISTERS \
634 { \
635 1, 1, 1, 1, 1, 1, 1, 1, \
636 0, 0, 0, 0, 0, 0, 1, 1, \
637 1, 1, 1 \
638 SUBTARGET_CALL_USED_REGISTERS \
639 }
641 /* Zero or more C statements that may conditionally modify two variables
642 `fixed_regs' and `call_used_regs' (both of type `char []') after they
643 have been initialized from the two preceding macros.
645 This is necessary in case the fixed or call-clobbered registers depend
646 on target flags.
648 You need not define this macro if it has no work to do. */
650 #ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE
651 #define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE
652 #else
653 #define CONDITIONAL_REGISTER_USAGE \
654 do \
655 { \
656 if (flag_pic) \
657 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
658 } \
659 while (0)
660 #endif
662 /* If defined, an initializer for a vector of integers, containing the
663 numbers of hard registers in the order in which GCC should
664 prefer to use them (from most preferred to least). */
666 #ifndef SUBTARGET_REG_ALLOC_ORDER
667 #define SUBTARGET_REG_ALLOC_ORDER
668 #endif
671 #define REG_ALLOC_ORDER \
672 { \
673 4, 5, 6, 7, 2, 3, 8, 9, 10, \
674 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \
675 SUBTARGET_REG_ALLOC_ORDER \
676 }
679 #define REG_ALLOC_ORDER \
680 { \
681 0, 1, 2, 3, 4, 5, 6, 7, 8, \
682 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \
683 SUBTARGET_REG_ALLOC_ORDER \
684 }
685 #endif
687 /* Return number of consecutive hard regs needed starting at reg REGNO
688 to hold something of mode MODE.
689 This is ordinarily the length in words of a value of mode MODE
690 but can be less for certain modes in special long registers. */
691 #define HARD_REGNO_NREGS(REGNO, MODE) \
692 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
694 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
697 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
698 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
700 /* A C expression that is nonzero if it is desirable to choose
701 register allocation so as to avoid move instructions between a
702 value of mode MODE1 and a value of mode MODE2.
704 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
705 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
706 MODE2)' must be zero. */
708 /* Tie QI/HI/SI modes together. */
709 #define MODES_TIEABLE_P(MODE1, MODE2) \
710 ( GET_MODE_CLASS (MODE1) == MODE_INT \
711 && GET_MODE_CLASS (MODE2) == MODE_INT \
712 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
713 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
715 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
716 m32r_hard_regno_rename_ok (OLD_REG, NEW_REG)
717 \f
718 /* Register classes and constants. */
720 /* Define the classes of registers for register constraints in the
721 machine description. Also define ranges of constants.
723 One of the classes must always be named ALL_REGS and include all hard regs.
724 If there is more than one class, another class must be named NO_REGS
725 and contain no registers.
727 The name GENERAL_REGS must be the name of a class (or an alias for
728 another name such as ALL_REGS). This is the class of registers
729 that is allowed by "g" or "r" in a register constraint.
730 Also, registers outside this class are allocated only when
731 instructions express preferences for them.
733 The classes must be numbered in nondecreasing order; that is,
734 a larger-numbered class must never be contained completely
735 in a smaller-numbered class.
737 For any two classes, it is very desirable that there be another
738 class that represents their union.
740 It is important that any condition codes have class NO_REGS.
741 See `register_operand'. */
743 enum reg_class
744 {
746 };
748 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
750 /* Give names of register classes as strings for dump file. */
751 #define REG_CLASS_NAMES \
754 /* Define which registers fit in which classes.
755 This is an initializer for a vector of HARD_REG_SET
756 of length N_REG_CLASSES. */
758 #ifndef SUBTARGET_REG_CLASS_CARRY
759 #define SUBTARGET_REG_CLASS_CARRY 0
760 #endif
762 #ifndef SUBTARGET_REG_CLASS_ACCUM
763 #define SUBTARGET_REG_CLASS_ACCUM 0
764 #endif
766 #ifndef SUBTARGET_REG_CLASS_GENERAL
767 #define SUBTARGET_REG_CLASS_GENERAL 0
768 #endif
770 #ifndef SUBTARGET_REG_CLASS_ALL
771 #define SUBTARGET_REG_CLASS_ALL 0
772 #endif
774 #define REG_CLASS_CONTENTS \
775 { \
776 { 0x00000 }, \
777 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \
778 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \
779 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \
780 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \
781 }
783 /* The same information, inverted:
784 Return the class number of the smallest class containing
785 reg number REGNO. This could be a conditional expression
786 or could index an array. */
788 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
790 /* The class value for index registers, and the one for base regs. */
791 #define INDEX_REG_CLASS GENERAL_REGS
792 #define BASE_REG_CLASS GENERAL_REGS
794 #define REG_CLASS_FROM_LETTER(C) \
797 : NO_REGS)
799 /* These assume that REGNO is a hard or pseudo reg number.
800 They give nonzero only if REGNO is a hard reg of the suitable class
801 or a pseudo reg currently allocated to a suitable hard reg.
802 Since they use reg_renumber, they are safe only once reg_renumber
803 has been allocated, which happens in local-alloc.c. */
804 #define REGNO_OK_FOR_BASE_P(REGNO) \
805 ((REGNO) < FIRST_PSEUDO_REGISTER \
806 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \
807 : GPR_P (reg_renumber[REGNO]))
809 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
811 /* Given an rtx X being reloaded into a reg required to be
812 in class CLASS, return the class of reg to actually use.
813 In general this is just CLASS; but on some machines
814 in some cases it is preferable to use a more restrictive class. */
815 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
817 /* Return the maximum number of consecutive registers
818 needed to represent mode MODE in a register of class CLASS. */
819 #define CLASS_MAX_NREGS(CLASS, MODE) \
820 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
822 /* The letters I, J, K, L, M, N, O, P in a register constraint string
823 can be used to stand for particular ranges of immediate operands.
824 This macro defines what the ranges are.
825 C is the letter, and VALUE is a constant value.
826 Return 1 if VALUE is in the range specified by C. */
827 /* 'I' is used for 8 bit signed immediates.
828 'J' is used for 16 bit signed immediates.
829 'K' is used for 16 bit unsigned immediates.
830 'L' is used for 16 bit immediates left shifted by 16 (sign ???).
831 'M' is used for 24 bit unsigned immediates.
832 'N' is used for any 32 bit non-symbolic value.
833 'O' is used for 5 bit unsigned immediates (shift count).
834 'P' is used for 16 bit signed immediates for compares
835 (values in the range -32767 to +32768). */
837 /* Return true if a value is inside a range. */
838 #define IN_RANGE_P(VALUE, LOW, HIGH) \
839 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
840 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
842 /* Local to this file. */
843 #define INT8_P(X) ((X) >= - 0x80 && (X) <= 0x7f)
844 #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff)
845 #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000)
846 #define UPPER16_P(X) (((X) & 0xffff) == 0 \
847 && ((X) >> 16) >= - 0x8000 \
848 && ((X) >> 16) <= 0x7fff)
849 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
850 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
851 #define UINT32_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0xffffffff)
852 #define UINT5_P(X) ((X) >= 0 && (X) < 32)
853 #define INVERTED_SIGNED_8BIT(VAL) ((VAL) >= -127 && (VAL) <= 128)
855 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
864 : 0)
866 /* Similar, but for floating constants, and defining letters G and H.
867 Here VALUE is the CONST_DOUBLE rtx itself.
868 For the m32r, handle a few constants inline.
869 ??? We needn't treat DI and DF modes differently, but for now we do. */
870 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
873 : 0)
875 /* A C expression that defines the optional machine-dependent constraint
876 letters that can be used to segregate specific types of operands,
877 usually memory references, for the target machine. It should return 1 if
878 VALUE corresponds to the operand type represented by the constraint letter
879 C. If C is not defined as an extra constraint, the value returned should
880 be 0 regardless of VALUE. */
881 /* Q is for symbolic addresses loadable with ld24.
882 R is for symbolic addresses when ld24 can't be used.
883 S is for stores with pre {inc,dec}rement
884 T is for indirect of a pointer.
885 U is for loads with post increment. */
887 #define EXTRA_CONSTRAINT(VALUE, C) \
889 || addr24_operand (VALUE, VOIDmode)) \
891 || addr32_operand (VALUE, VOIDmode)) \
893 && STORE_PREINC_PREDEC_P (GET_MODE (VALUE), \
894 XEXP (VALUE, 0))) \
896 && memreg_operand (VALUE, GET_MODE (VALUE))) \
898 && LOAD_POSTINC_P (GET_MODE (VALUE), \
899 XEXP (VALUE, 0))) \
900 : 0)
901 \f
902 /* Stack layout and stack pointer usage. */
904 /* Define this macro if pushing a word onto the stack moves the stack
905 pointer to a smaller address. */
906 #define STACK_GROWS_DOWNWARD
908 /* Offset from frame pointer to start allocating local variables at.
909 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
910 first local allocated. Otherwise, it is the offset to the BEGINNING
911 of the first local allocated. */
912 /* The frame pointer points at the same place as the stack pointer, except if
913 alloca has been called. */
914 #define STARTING_FRAME_OFFSET \
915 M32R_STACK_ALIGN (current_function_outgoing_args_size)
917 /* Offset from the stack pointer register to the first location at which
918 outgoing arguments are placed. */
919 #define STACK_POINTER_OFFSET 0
921 /* Offset of first parameter from the argument pointer register value. */
922 #define FIRST_PARM_OFFSET(FNDECL) 0
924 /* Register to use for pushing function arguments. */
925 #define STACK_POINTER_REGNUM 15
927 /* Base register for access to local variables of the function. */
928 #define FRAME_POINTER_REGNUM 13
930 /* Base register for access to arguments of the function. */
931 #define ARG_POINTER_REGNUM 16
933 /* Register in which static-chain is passed to a function.
934 This must not be a register used by the prologue. */
935 #define STATIC_CHAIN_REGNUM 7
937 /* These aren't official macros. */
938 #define PROLOGUE_TMP_REGNUM 4
939 #define RETURN_ADDR_REGNUM 14
940 /* #define GP_REGNUM 12 */
941 #define CARRY_REGNUM 17
942 #define ACCUM_REGNUM 18
943 #define M32R_MAX_INT_REGS 16
945 #ifndef SUBTARGET_GPR_P
946 #define SUBTARGET_GPR_P(REGNO) 0
947 #endif
949 #ifndef SUBTARGET_ACCUM_P
950 #define SUBTARGET_ACCUM_P(REGNO) 0
951 #endif
953 #ifndef SUBTARGET_CARRY_P
954 #define SUBTARGET_CARRY_P(REGNO) 0
955 #endif
957 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
958 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
959 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
960 \f
961 /* Eliminating the frame and arg pointers. */
963 /* A C expression which is nonzero if a function must have and use a
964 frame pointer. This expression is evaluated in the reload pass.
965 If its value is nonzero the function will have a frame pointer. */
966 #define FRAME_POINTER_REQUIRED current_function_calls_alloca
968 #if 0
969 /* C statement to store the difference between the frame pointer
970 and the stack pointer values immediately after the function prologue.
971 If `ELIMINABLE_REGS' is defined, this macro will be not be used and
972 need not be defined. */
973 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
974 ((VAR) = m32r_compute_frame_size (get_frame_size ()))
975 #endif
977 /* If defined, this macro specifies a table of register pairs used to
978 eliminate unneeded registers that point into the stack frame. If
979 it is not defined, the only elimination attempted by the compiler
980 is to replace references to the frame pointer with references to
981 the stack pointer.
983 Note that the elimination of the argument pointer with the stack
984 pointer is specified first since that is the preferred elimination. */
986 #define ELIMINABLE_REGS \
987 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
988 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
989 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
991 /* A C expression that returns nonzero if the compiler is allowed to
992 try to replace register number FROM-REG with register number
993 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
994 defined, and will usually be the constant 1, since most of the
995 cases preventing register elimination are things that the compiler
996 already knows about. */
998 #define CAN_ELIMINATE(FROM, TO) \
999 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1000 ? ! frame_pointer_needed \
1001 : 1)
1003 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1004 specifies the initial difference between the specified pair of
1005 registers. This macro must be defined if `ELIMINABLE_REGS' is
1006 defined. */
1008 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1009 do \
1010 { \
1011 int size = m32r_compute_frame_size (get_frame_size ()); \
1012 \
1013 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1014 (OFFSET) = 0; \
1015 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1016 (OFFSET) = size - current_function_pretend_args_size; \
1017 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1018 (OFFSET) = size - current_function_pretend_args_size; \
1019 else \
1020 abort (); \
1021 } \
1022 while (0)
1023 \f
1024 /* Function argument passing. */
1026 /* When a prototype says `char' or `short', really pass an `int'. */
1027 #define PROMOTE_PROTOTYPES 1
1029 /* If defined, the maximum amount of space required for outgoing
1030 arguments will be computed and placed into the variable
1031 `current_function_outgoing_args_size'. No space will be pushed
1032 onto the stack for each call; instead, the function prologue should
1033 increase the stack frame size by this amount. */
1034 #define ACCUMULATE_OUTGOING_ARGS 1
1036 /* Value is the number of bytes of arguments automatically
1037 popped when returning from a subroutine call.
1038 FUNDECL is the declaration node of the function (as a tree),
1039 FUNTYPE is the data type of the function (as a tree),
1040 or for a library call it is an identifier node for the subroutine name.
1041 SIZE is the number of bytes of arguments passed on the stack. */
1042 #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
1044 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1045 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1046 ((TYPE) != 0 \
1047 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1048 || TREE_ADDRESSABLE (TYPE)))
1050 /* Define a data type for recording info about an argument list
1051 during the scan of that argument list. This data type should
1052 hold all necessary information about the function itself
1053 and about the args processed so far, enough to enable macros
1054 such as FUNCTION_ARG to determine where the next arg should go. */
1055 #define CUMULATIVE_ARGS int
1057 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1058 for a call to a function whose data type is FNTYPE.
1059 For a library call, FNTYPE is 0. */
1060 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1061 ((CUM) = 0)
1063 /* The number of registers used for parameter passing. Local to this file. */
1064 #define M32R_MAX_PARM_REGS 4
1066 /* 1 if N is a possible register number for function argument passing. */
1067 #define FUNCTION_ARG_REGNO_P(N) \
1068 ((unsigned) (N) < M32R_MAX_PARM_REGS)
1070 /* The ROUND_ADVANCE* macros are local to this file. */
1071 /* Round SIZE up to a word boundary. */
1072 #define ROUND_ADVANCE(SIZE) \
1073 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1075 /* Round arg MODE/TYPE up to the next word boundary. */
1076 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
1077 ((MODE) == BLKmode \
1078 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1079 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
1081 /* Round CUM up to the necessary point for argument MODE/TYPE. */
1082 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1084 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1085 a reg. This includes arguments that have to be passed by reference as the
1086 pointer to them is passed in a reg if one is available (and that is what
1087 we're given).
1088 This macro is only used in this file. */
1089 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1090 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1092 /* Determine where to put an argument to a function.
1093 Value is zero to push the argument on the stack,
1094 or a hard register in which to store the argument.
1096 MODE is the argument's machine mode.
1097 TYPE is the data type of the argument (as a tree).
1098 This is null for libcalls where that information may
1099 not be available.
1100 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1101 the preceding args and about the function being called.
1102 NAMED is nonzero if this argument is a named parameter
1103 (otherwise it is an extra parameter matching an ellipsis). */
1104 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1105 and the rest are pushed. */
1106 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1107 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1108 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \
1109 : 0)
1111 /* A C expression for the number of words, at the beginning of an
1112 argument, must be put in registers. The value must be zero for
1113 arguments that are passed entirely in registers or that are entirely
1114 pushed on the stack.
1116 On some machines, certain arguments must be passed partially in
1117 registers and partially in memory. On these machines, typically the
1118 first @var{n} words of arguments are passed in registers, and the rest
1119 on the stack. If a multi-word argument (a @code{double} or a
1120 structure) crosses that boundary, its first few words must be passed
1121 in registers and the rest must be pushed. This macro tells the
1122 compiler when this occurs, and how many of the words should go in
1123 registers. */
1124 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1125 function_arg_partial_nregs (&CUM, (int)MODE, TYPE, NAMED)
1127 /* A C expression that indicates when an argument must be passed by
1128 reference. If nonzero for an argument, a copy of that argument is
1129 made in memory and a pointer to the argument is passed instead of
1130 the argument itself. The pointer is passed in whatever way is
1131 appropriate for passing a pointer to that type. */
1132 /* All arguments greater than 8 bytes are passed this way. */
1133 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1134 ((TYPE) && m32r_pass_by_reference (TYPE))
1136 /* Update the data in CUM to advance over an argument
1137 of mode MODE and data type TYPE.
1138 (TYPE is null for libcalls where that information may not be available.) */
1139 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1140 ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
1141 + ROUND_ADVANCE_ARG ((MODE), (TYPE))))
1143 /* If defined, a C expression that gives the alignment boundary, in bits,
1144 of an argument with the specified mode and type. If it is not defined,
1145 PARM_BOUNDARY is used for all arguments. */
1146 #if 0
1147 /* We assume PARM_BOUNDARY == UNITS_PER_WORD here. */
1148 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1149 (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \
1150 ? PARM_BOUNDARY : 2 * PARM_BOUNDARY)
1151 #endif
1153 /* This macro offers an alternative
1154 to using `__builtin_saveregs' and defining the macro
1155 `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
1156 arguments into the stack so that all the arguments appear to have
1157 been passed consecutively on the stack. Once this is done, you
1158 can use the standard implementation of varargs that works for
1159 machines that pass all their arguments on the stack.
1161 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure,
1162 containing the values that obtain after processing of the named
1163 arguments. The arguments MODE and TYPE describe the last named
1164 argument--its machine mode and its data type as a tree node.
1166 The macro implementation should do two things: first, push onto the
1167 stack all the argument registers *not* used for the named
1168 arguments, and second, store the size of the data thus pushed into
1169 the `int'-valued variable whose name is supplied as the argument
1170 PRETEND_SIZE. The value that you store here will serve as
1171 additional offset for setting up the stack frame.
1173 If the argument NO_RTL is nonzero, it means that the
1174 arguments of the function are being analyzed for the second time.
1175 This happens for an inline function, which is not actually
1176 compiled until the end of the source file. The macro
1177 `SETUP_INCOMING_VARARGS' should not generate any instructions in
1178 this case. */
1180 #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1181 m32r_setup_incoming_varargs (& ARGS_SO_FAR, MODE, TYPE, & PRETEND_SIZE, NO_RTL)
1183 /* Implement `va_arg'. */
1184 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1185 m32r_va_arg (valist, type)
1186 \f
1187 /* Function results. */
1189 /* Define how to find the value returned by a function.
1190 VALTYPE is the data type of the value (as a tree).
1191 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1192 otherwise, FUNC is 0. */
1193 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
1195 /* Define how to find the value returned by a library function
1196 assuming the value has mode MODE. */
1197 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
1199 /* 1 if N is a possible register number for a function value
1200 as seen by the caller. */
1201 /* ??? What about r1 in DI/DF values. */
1202 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
1204 /* A C expression which can inhibit the returning of certain function
1205 values in registers, based on the type of value. A nonzero value says
1206 to return the function value in memory, just as large structures are
1207 always returned. Here TYPE will be a C expression of type `tree',
1208 representing the data type of the value. */
1209 #define RETURN_IN_MEMORY(TYPE) m32r_pass_by_reference (TYPE)
1211 /* Tell GCC to use RETURN_IN_MEMORY. */
1212 #define DEFAULT_PCC_STRUCT_RETURN 0
1214 /* Register in which address to store a structure value
1215 is passed to a function, or 0 to use `invisible' first argument. */
1216 #define STRUCT_VALUE 0
1217 \f
1218 /* Function entry and exit. */
1220 /* Initialize data used by insn expanders. This is called from
1221 init_emit, once for each function, before code is generated. */
1222 #define INIT_EXPANDERS m32r_init_expanders ()
1224 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1225 the stack pointer does not matter. The value is tested only in
1226 functions that have frame pointers.
1227 No definition is equivalent to always zero. */
1228 #define EXIT_IGNORE_STACK 1
1230 /* Output assembler code to FILE to increment profiler label # LABELNO
1231 for profiling a function entry. */
1232 #undef FUNCTION_PROFILER
1233 #define FUNCTION_PROFILER(FILE, LABELNO) \
1234 do \
1235 { \
1236 if (flag_pic) \
1237 { \
1242 } \
1243 else \
1244 { \
1245 if (TARGET_ADDR24) \
1247 else \
1248 { \
1252 } \
1253 } \
1255 } \
1256 while (0)
1257 \f
1258 /* Trampolines. */
1260 /* On the M32R, the trampoline is:
1262 mv r7, lr -> bl L1 ; 178e 7e01
1263 L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12)
1264 mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6
1265 ld r6, @r6 -> jmp r6 ; 26c6 1fc6
1266 L2: .word STATIC
1267 .word FUNCTION */
1269 #ifndef CACHE_FLUSH_FUNC
1271 #endif
1272 #ifndef CACHE_FLUSH_TRAP
1274 #endif
1276 /* Length in bytes of the trampoline for entering a nested function. */
1277 #define TRAMPOLINE_SIZE 24
1279 /* Emit RTL insns to initialize the variable parts of a trampoline.
1280 FNADDR is an RTX for the address of the function's pure code.
1281 CXT is an RTX for the static chain value for the function. */
1282 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1283 do \
1284 { \
1285 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 0)), \
1286 GEN_INT \
1287 (TARGET_LITTLE_ENDIAN ? 0x017e8e17 : 0x178e7e01)); \
1288 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), \
1289 GEN_INT \
1290 (TARGET_LITTLE_ENDIAN ? 0x0c00ae86 : 0x86ae000c)); \
1291 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), \
1292 GEN_INT \
1293 (TARGET_LITTLE_ENDIAN ? 0xe627871e : 0x1e8727e6)); \
1294 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), \
1295 GEN_INT \
1296 (TARGET_LITTLE_ENDIAN ? 0xc616c626 : 0x26c61fc6)); \
1297 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 16)), \
1298 (CXT)); \
1299 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 20)), \
1300 (FNADDR)); \
1301 if (m32r_cache_flush_trap_string && m32r_cache_flush_trap_string[0]) \
1302 emit_insn (gen_flush_icache (validize_mem (gen_rtx_MEM (SImode, TRAMP)),\
1303 GEN_INT (m32r_cache_flush_trap) )); \
1304 else if (m32r_cache_flush_func && m32r_cache_flush_func[0]) \
1305 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, m32r_cache_flush_func), \
1306 0, VOIDmode, 3, TRAMP, Pmode, \
1307 GEN_INT (TRAMPOLINE_SIZE), SImode, \
1308 GEN_INT (3), SImode); \
1309 } \
1310 while (0)
1311 \f
1312 /* Library calls. */
1314 /* Generate calls to memcpy, memcmp and memset. */
1315 #define TARGET_MEM_FUNCTIONS
1316 \f
1317 /* Addressing modes, and classification of registers for them. */
1319 /* Maximum number of registers that can appear in a valid memory address. */
1320 #define MAX_REGS_PER_ADDRESS 1
1322 /* We have post-inc load and pre-dec,pre-inc store,
1323 but only for 4 byte vals. */
1324 #define HAVE_PRE_DECREMENT 1
1325 #define HAVE_PRE_INCREMENT 1
1326 #define HAVE_POST_INCREMENT 1
1328 /* Recognize any constant value that is a valid address. */
1329 #define CONSTANT_ADDRESS_P(X) \
1330 ( GET_CODE (X) == LABEL_REF \
1331 || GET_CODE (X) == SYMBOL_REF \
1332 || GET_CODE (X) == CONST_INT \
1333 || (GET_CODE (X) == CONST \
1334 && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X))))
1336 /* Nonzero if the constant value X is a legitimate general operand.
1337 We don't allow (plus symbol large-constant) as the relocations can't
1338 describe it. INTVAL > 32767 handles both 16 bit and 24 bit relocations.
1339 We allow all CONST_DOUBLE's as the md file patterns will force the
1340 constant to memory if they can't handle them. */
1342 #define LEGITIMATE_CONSTANT_P(X) \
1343 (! (GET_CODE (X) == CONST \
1344 && GET_CODE (XEXP (X, 0)) == PLUS \
1345 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1346 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1347 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
1349 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1350 and check its validity for a certain class.
1351 We have two alternate definitions for each of them.
1352 The usual definition accepts all pseudo regs; the other rejects
1353 them unless they have been allocated suitable hard regs.
1354 The symbol REG_OK_STRICT causes the latter definition to be used.
1356 Most source files want to accept pseudo regs in the hope that
1357 they will get allocated to the class that the insn wants them to be in.
1358 Source files for reload pass need to be strict.
1359 After reload, it makes no difference, since pseudo regs have
1360 been eliminated by then. */
1362 #ifdef REG_OK_STRICT
1364 /* Nonzero if X is a hard reg that can be used as a base reg. */
1365 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
1366 /* Nonzero if X is a hard reg that can be used as an index. */
1367 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1369 #else
1371 /* Nonzero if X is a hard reg that can be used as a base reg
1372 or if it is a pseudo reg. */
1373 #define REG_OK_FOR_BASE_P(X) \
1374 (GPR_P (REGNO (X)) \
1375 || (REGNO (X)) == ARG_POINTER_REGNUM \
1376 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1377 /* Nonzero if X is a hard reg that can be used as an index
1378 or if it is a pseudo reg. */
1379 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1381 #endif
1383 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1384 that is a valid memory address for an instruction.
1385 The MODE argument is the machine mode for the MEM expression
1386 that wants to use this address. */
1388 /* Local to this file. */
1389 #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
1391 /* Local to this file. */
1392 #define RTX_OK_FOR_OFFSET_P(X) \
1393 (GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X)))
1395 /* Local to this file. */
1396 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
1397 (GET_CODE (X) == PLUS \
1398 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1399 && RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
1401 /* Local to this file. */
1402 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
1403 since more than one instruction will be required. */
1404 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
1405 (GET_CODE (X) == LO_SUM \
1406 && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)\
1407 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1408 && CONSTANT_P (XEXP (X, 1)))
1410 /* Local to this file. */
1411 /* Is this a load and increment operation. */
1412 #define LOAD_POSTINC_P(MODE, X) \
1413 (((MODE) == SImode || (MODE) == SFmode) \
1414 && GET_CODE (X) == POST_INC \
1415 && GET_CODE (XEXP (X, 0)) == REG \
1416 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1418 /* Local to this file. */
1419 /* Is this an increment/decrement and store operation. */
1420 #define STORE_PREINC_PREDEC_P(MODE, X) \
1421 (((MODE) == SImode || (MODE) == SFmode) \
1422 && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
1423 && GET_CODE (XEXP (X, 0)) == REG \
1424 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1426 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1427 do \
1428 { \
1429 if (RTX_OK_FOR_BASE_P (X)) \
1430 goto ADDR; \
1431 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \
1432 goto ADDR; \
1433 if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \
1434 goto ADDR; \
1435 if (LOAD_POSTINC_P ((MODE), (X))) \
1436 goto ADDR; \
1437 if (STORE_PREINC_PREDEC_P ((MODE), (X))) \
1438 goto ADDR; \
1439 } \
1440 while (0)
1442 /* Try machine-dependent ways of modifying an illegitimate address
1443 to be legitimate. If we find one, return the new, valid address.
1444 This macro is used in only one place: `memory_address' in explow.c.
1446 OLDX is the address as it was before break_out_memory_refs was called.
1447 In some cases it is useful to look at this to decide what needs to be done.
1449 MODE and WIN are passed so that this macro can use
1450 GO_IF_LEGITIMATE_ADDRESS.
1452 It is always safe for this macro to do nothing. It exists to recognize
1453 opportunities to optimize the output. */
1455 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1456 do \
1457 { \
1458 if (flag_pic) \
1459 (X) = m32r_legitimize_pic_address (X, NULL_RTX); \
1460 if (memory_address_p (MODE, X)) \
1461 goto WIN; \
1462 } \
1463 while (0)
1465 /* Go to LABEL if ADDR (a legitimate address expression)
1466 has an effect that depends on the machine mode it is used for. */
1467 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1468 do \
1469 { \
1470 if ( GET_CODE (ADDR) == PRE_DEC \
1471 || GET_CODE (ADDR) == PRE_INC \
1472 || GET_CODE (ADDR) == POST_INC \
1473 || GET_CODE (ADDR) == LO_SUM) \
1474 goto LABEL; \
1475 } \
1476 while (0)
1477 \f
1478 /* Condition code usage. */
1480 /* Return nonzero if SELECT_CC_MODE will never return MODE for a
1481 floating point inequality comparison. */
1483 \f
1484 /* Costs. */
1486 /* Compute extra cost of moving data between one register class
1487 and another. */
1488 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2
1490 /* Compute the cost of moving data between registers and memory. */
1491 /* Memory is 3 times as expensive as registers.
1492 ??? Is that the right way to look at it? */
1493 #define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \
1494 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
1496 /* The cost of a branch insn. */
1497 /* A value of 2 here causes GCC to avoid using branches in comparisons like
1498 while (a < N && a). Branches aren't that expensive on the M32R so
1499 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */
1500 #define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1)
1502 /* Nonzero if access to memory by bytes is slow and undesirable.
1503 For RISC chips, it means that access to memory by bytes is no
1504 better than access by words when possible, so grab a whole word
1505 and maybe make use of that. */
1506 #define SLOW_BYTE_ACCESS 1
1508 /* Define this macro if it is as good or better to call a constant
1509 function address than to call an address kept in a register. */
1510 #define NO_FUNCTION_CSE
1512 /* Define this macro if it is as good or better for a function to call
1513 itself with an explicit address than to call an address kept in a
1514 register. */
1515 #define NO_RECURSIVE_FUNCTION_CSE
1516 \f
1517 /* Section selection. */
1523 /* Define this macro if jump tables (for tablejump insns) should be
1524 output in the text section, along with the assembler instructions.
1525 Otherwise, the readonly data section is used.
1526 This macro is irrelevant if there is no separate readonly data section. */
1527 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1528 \f
1529 /* Position Independent Code. */
1531 /* The register number of the register used to address a table of static
1532 data addresses in memory. In some cases this register is defined by a
1533 processor's ``application binary interface'' (ABI). When this macro
1534 is defined, RTL is generated for this register once, as with the stack
1535 pointer and frame pointer registers. If this macro is not defined, it
1536 is up to the machine-dependent files to allocate such a register (if
1537 necessary). */
1538 #define PIC_OFFSET_TABLE_REGNUM 12
1540 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1541 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1542 is not defined. */
1543 /* This register is call-saved on the M32R. */
1544 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1546 /* By generating position-independent code, when two different programs (A
1547 and B) share a common library (libC.a), the text of the library can be
1548 shared whether or not the library is linked at the same address for both
1549 programs. In some of these environments, position-independent code
1550 requires not only the use of different addressing modes, but also
1551 special code to enable the use of these addressing modes.
1553 The FINALIZE_PIC macro serves as a hook to emit these special
1554 codes once the function is being compiled into assembly code, but not
1555 before. (It is not done before, because in the case of compiling an
1556 inline function, it would lead to multiple PIC prologues being
1557 included in functions which used inline functions and were compiled to
1558 assembly language.) */
1560 #define FINALIZE_PIC m32r_finalize_pic ()
1562 /* A C expression that is nonzero if X is a legitimate immediate
1563 operand on the target machine when generating position independent code.
1564 You can assume that X satisfies CONSTANT_P, so you need not
1565 check this. You can also assume `flag_pic' is true, so you need not
1566 check it either. You need not define this macro if all constants
1567 (including SYMBOL_REF) can be immediate operands when generating
1568 position independent code. */
1569 #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X)
1570 \f
1571 /* Control the assembler format that we output. */
1573 /* A C string constant describing how to begin a comment in the target
1574 assembler language. The compiler assumes that the comment will
1575 end at the end of the line. */
1578 /* Output to assembler file text saying following lines
1579 may contain character constants, extra white space, comments, etc. */
1582 /* Output to assembler file text saying following lines
1583 no longer contain unusual constructs. */
1586 /* Globalizing directive for a label. */
1589 /* If -Os, don't force line number labels to begin at the beginning of
1590 the word; we still want the assembler to try to put things in parallel,
1591 should that be possible.
1592 For m32r/d, instructions are never in parallel (other than with a nop)
1593 and the simulator and stub both handle a breakpoint in the middle of
1594 a word so don't ever force line number labels to begin at the beginning
1595 of a word. */
1597 #undef ASM_OUTPUT_SOURCE_LINE
1598 #define ASM_OUTPUT_SOURCE_LINE(file, line, counter) \
1599 do \
1600 { \
1602 line, counter); \
1603 assemble_name \
1604 (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
1605 fprintf (file, (optimize_size || TARGET_M32R) \
1608 counter); \
1609 } \
1610 while (0)
1612 /* How to refer to registers in assembler output.
1613 This sequence is indexed by compiler's hard-register-number (see above). */
1614 #ifndef SUBTARGET_REGISTER_NAMES
1615 #define SUBTARGET_REGISTER_NAMES
1616 #endif
1618 #define REGISTER_NAMES \
1619 { \
1623 SUBTARGET_REGISTER_NAMES \
1624 }
1626 /* If defined, a C initializer for an array of structures containing
1627 a name and a register number. This macro defines additional names
1628 for hard registers, thus allowing the `asm' option in declarations
1629 to refer to registers using alternate names. */
1630 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
1631 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES
1632 #endif
1634 #define ADDITIONAL_REGISTER_NAMES \
1635 { \
1640 SUBTARGET_ADDITIONAL_REGISTER_NAMES \
1641 }
1643 /* A C expression which evaluates to true if CODE is a valid
1644 punctuation character for use in the `PRINT_OPERAND' macro. */
1646 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1647 m32r_punct_chars[(unsigned char) (CHAR)]
1649 /* Print operand X (an rtx) in assembler syntax to file FILE.
1650 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1651 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1652 #define PRINT_OPERAND(FILE, X, CODE) \
1653 m32r_print_operand (FILE, X, CODE)
1655 /* A C compound statement to output to stdio stream STREAM the
1656 assembler syntax for an instruction operand that is a memory
1657 reference whose address is ADDR. ADDR is an RTL expression. */
1658 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1659 m32r_print_operand_address (FILE, ADDR)
1661 /* If defined, C string expressions to be used for the `%R', `%L',
1662 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These
1663 are useful when a single `md' file must support multiple assembler
1664 formats. In that case, the various `tm.h' files can define these
1665 macros differently. */
1671 /* This is how to output an element of a case-vector that is absolute. */
1672 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1673 do \
1674 { \
1675 char label[30]; \
1678 assemble_name (FILE, label); \
1680 } \
1681 while (0)
1683 /* This is how to output an element of a case-vector that is relative. */
1684 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
1685 do \
1686 { \
1687 char label[30]; \
1690 assemble_name (FILE, label); \
1693 assemble_name (FILE, label); \
1695 } \
1696 while (0)
1698 /* The desired alignment for the location counter at the beginning
1699 of a loop. */
1700 /* On the M32R, align loops to 32 byte boundaries (cache line size)
1701 if -malign-loops. */
1702 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
1704 /* Define this to be the maximum number of insns to move around when moving
1705 a loop test from the top of a loop to the bottom
1706 and seeing whether to duplicate it. The default is thirty.
1708 Loop unrolling currently doesn't like this optimization, so
1709 disable doing if we are unrolling loops and saving space. */
1710 #define LOOP_TEST_THRESHOLD (optimize_size \
1711 && !flag_unroll_loops \
1712 && !flag_unroll_all_loops ? 2 : 30)
1714 /* This is how to output an assembler line
1715 that says to advance the location counter
1716 to a multiple of 2**LOG bytes. */
1717 /* .balign is used to avoid confusion. */
1718 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1719 do \
1720 { \
1721 if ((LOG) != 0) \
1723 } \
1724 while (0)
1726 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
1727 separate, explicit argument. If you define this macro, it is used in
1728 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
1729 handling the required alignment of the variable. The alignment is
1730 specified as the number of bits. */
1734 #undef ASM_OUTPUT_ALIGNED_COMMON
1735 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1736 do \
1737 { \
1738 if (! TARGET_SDATA_NONE \
1739 && (SIZE) > 0 && (SIZE) <= g_switch_value) \
1741 else \
1743 assemble_name ((FILE), (NAME)); \
1745 } \
1746 while (0)
1748 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1749 do \
1750 { \
1751 if (! TARGET_SDATA_NONE \
1752 && (SIZE) > 0 && (SIZE) <= g_switch_value) \
1754 else \
1755 bss_section (); \
1756 ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \
1757 last_assemble_variable_decl = DECL; \
1758 ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \
1759 ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \
1760 } \
1761 while (0)
1762 \f
1763 /* Debugging information. */
1765 /* Generate DBX and DWARF debugging information. */
1766 #define DBX_DEBUGGING_INFO 1
1767 #define DWARF2_DEBUGGING_INFO 1
1769 /* Prefer STABS (for now). */
1770 #undef PREFERRED_DEBUGGING_TYPE
1771 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
1773 /* Turn off splitting of long stabs. */
1774 #define DBX_CONTIN_LENGTH 0
1775 \f
1776 /* Miscellaneous. */
1778 /* Specify the machine mode that this machine uses
1779 for the index in the tablejump instruction. */
1780 #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode)
1782 /* Define as C expression which evaluates to nonzero if the tablejump
1783 instruction expects the table to contain offsets from the address of the
1784 table.
1785 Do not define this if the table should contain absolute addresses. */
1786 /* It's not clear what PIC will look like or whether we want to use -fpic
1787 for the embedded form currently being talked about. For now require -fpic
1788 to get pc relative switch tables. */
1789 /*#define CASE_VECTOR_PC_RELATIVE 1 */
1791 /* Define if operations between registers always perform the operation
1792 on the full register even if a narrower mode is specified. */
1793 #define WORD_REGISTER_OPERATIONS
1795 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1796 will either zero-extend or sign-extend. The value of this macro should
1797 be the code that says which one of the two operations is implicitly
1798 done, NIL if none. */
1799 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1801 /* Max number of bytes we can move from memory
1802 to memory in one reasonably fast instruction. */
1803 #define MOVE_MAX 4
1805 /* Define this to be nonzero if shift instructions ignore all but the low-order
1806 few bits. */
1807 #define SHIFT_COUNT_TRUNCATED 1
1809 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1810 is done just by pretending it is already truncated. */
1811 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1813 /* Specify the machine mode that pointers have.
1814 After generation of rtl, the compiler makes no further distinction
1815 between pointers and any other objects of this machine mode. */
1816 /* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has
1817 it's own problems (you have to add extendpsisi2 and truncsipsi2).
1818 Try to avoid it. */
1819 #define Pmode SImode
1821 /* A function address in a call instruction. */
1822 #define FUNCTION_MODE SImode
1823 \f
1824 /* Define the information needed to generate branch and scc insns. This is
1825 stored from the compare operation. Note that we can't use "rtx" here
1826 since it hasn't been defined! */
1830 /* M32R function types. */
1831 enum m32r_function_type
1832 {
1834 };
1836 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
1838 /* Define this if you have defined special-purpose predicates in the
1839 file `MACHINE.c'. This macro is called within an initializer of an
1840 array of structures. The first field in the structure is the name
1841 of a predicate and the second field is an array of rtl codes. For
1842 each predicate, list all rtl codes that can be in expressions
1843 matched by the predicate. The list should have a trailing comma. */
1845 #define PREDICATE_CODES \
1853 CONST_DOUBLE, LABEL_REF, CONST, \
1854 SYMBOL_REF }}, \
1856 CONST_DOUBLE }}, \