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* config/rs6000/rs6000.c: Include optabs.h.
[official-gcc.git] / gcc / config / rs6000 / rs6000.c
blob0d74876bad70cf0756c708ac4a275cbdd1fd17e1
1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5
6 This file is part of GNU CC.
7
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23 #include "config.h"
24 #include "system.h"
25 #include "rtl.h"
26 #include "regs.h"
27 #include "hard-reg-set.h"
28 #include "real.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-attr.h"
32 #include "flags.h"
33 #include "recog.h"
34 #include "obstack.h"
35 #include "tree.h"
36 #include "expr.h"
37 #include "optabs.h"
38 #include "except.h"
39 #include "function.h"
40 #include "output.h"
41 #include "basic-block.h"
42 #include "integrate.h"
43 #include "toplev.h"
44 #include "ggc.h"
45 #include "hashtab.h"
46 #include "tm_p.h"
47 #include "target.h"
48 #include "target-def.h"
49
50 #ifndef TARGET_NO_PROTOTYPE
51 #define TARGET_NO_PROTOTYPE 0
52 #endif
53
54 extern int profile_block_flag;
55
56 #define min(A,B) ((A) < (B) ? (A) : (B))
57 #define max(A,B) ((A) > (B) ? (A) : (B))
58
59 /* Target cpu type */
60
61 enum processor_type rs6000_cpu;
62 struct rs6000_cpu_select rs6000_select[3] =
63 {
64 /* switch name, tune arch */
65 { (const char *)0, "--with-cpu=", 1, 1 },
66 { (const char *)0, "-mcpu=", 1, 1 },
67 { (const char *)0, "-mtune=", 1, 0 },
68 };
69
70 /* Set to non-zero once AIX common-mode calls have been defined. */
71 static int common_mode_defined;
72
73 /* Save information from a "cmpxx" operation until the branch or scc is
74 emitted. */
75 rtx rs6000_compare_op0, rs6000_compare_op1;
76 int rs6000_compare_fp_p;
77
78 /* Label number of label created for -mrelocatable, to call to so we can
79 get the address of the GOT section */
80 int rs6000_pic_labelno;
81
82 #ifdef USING_SVR4_H
83 /* Which abi to adhere to */
84 const char *rs6000_abi_name = RS6000_ABI_NAME;
85
86 /* Semantics of the small data area */
87 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
88
89 /* Which small data model to use */
90 const char *rs6000_sdata_name = (char *)0;
91
92 /* Counter for labels which are to be placed in .fixup. */
93 int fixuplabelno = 0;
94 #endif
95
96 /* ABI enumeration available for subtarget to use. */
97 enum rs6000_abi rs6000_current_abi;
98
99 /* Debug flags */
100 const char *rs6000_debug_name;
101 int rs6000_debug_stack; /* debug stack applications */
102 int rs6000_debug_arg; /* debug argument handling */
103
104 /* Flag to say the TOC is initialized */
105 int toc_initialized;
106 char toc_label_name[10];
107
108 /* Alias set for saves and restores from the rs6000 stack. */
109 static int rs6000_sr_alias_set;
110
111 static void rs6000_add_gc_roots PARAMS ((void));
112 static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT));
113 static rtx expand_block_move_mem PARAMS ((enum machine_mode, rtx, rtx));
114 static void validate_condition_mode
115 PARAMS ((enum rtx_code, enum machine_mode));
116 static rtx rs6000_generate_compare PARAMS ((enum rtx_code));
117 static void rs6000_maybe_dead PARAMS ((rtx));
118 static void rs6000_emit_stack_tie PARAMS ((void));
119 static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx));
120 static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int));
121 static unsigned rs6000_hash_constant PARAMS ((rtx));
122 static unsigned toc_hash_function PARAMS ((const void *));
123 static int toc_hash_eq PARAMS ((const void *, const void *));
124 static int toc_hash_mark_entry PARAMS ((void **, void *));
125 static void toc_hash_mark_table PARAMS ((void *));
126 static int constant_pool_expr_1 PARAMS ((rtx, int *, int *));
127 static void rs6000_free_machine_status PARAMS ((struct function *));
128 static void rs6000_init_machine_status PARAMS ((struct function *));
129 static int rs6000_ra_ever_killed PARAMS ((void));
130 static int rs6000_valid_type_attribute_p PARAMS ((tree, tree, tree, tree));
131 static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
132 static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
133 static rtx rs6000_emit_set_long_const PARAMS ((rtx,
134 HOST_WIDE_INT, HOST_WIDE_INT));
135 #if TARGET_ELF
136 static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *,
137 int));
138 static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int));
139 static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int));
140 #endif
141 #ifdef OBJECT_FORMAT_COFF
142 static void xcoff_asm_named_section PARAMS ((const char *, unsigned int,
143 unsigned int));
144 #endif
145 \f
146 /* Default register names. */
147 char rs6000_reg_names[][8] =
148 {
149 "0", "1", "2", "3", "4", "5", "6", "7",
150 "8", "9", "10", "11", "12", "13", "14", "15",
151 "16", "17", "18", "19", "20", "21", "22", "23",
152 "24", "25", "26", "27", "28", "29", "30", "31",
153 "0", "1", "2", "3", "4", "5", "6", "7",
154 "8", "9", "10", "11", "12", "13", "14", "15",
155 "16", "17", "18", "19", "20", "21", "22", "23",
156 "24", "25", "26", "27", "28", "29", "30", "31",
157 "mq", "lr", "ctr","ap",
158 "0", "1", "2", "3", "4", "5", "6", "7",
159 "xer"
160 };
161
162 #ifdef TARGET_REGNAMES
163 static char alt_reg_names[][8] =
164 {
165 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
166 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
167 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
168 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
169 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
170 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
171 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
172 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
173 "mq", "lr", "ctr", "ap",
174 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
175 "xer"
176 };
177 #endif
178 \f
179 #ifndef MASK_STRICT_ALIGN
180 #define MASK_STRICT_ALIGN 0
181 #endif
182 \f
183 /* Initialize the GCC target structure. */
184 #undef TARGET_VALID_TYPE_ATTRIBUTE
185 #define TARGET_VALID_TYPE_ATTRIBUTE rs6000_valid_type_attribute_p
186
187 #undef TARGET_ASM_FUNCTION_PROLOGUE
188 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
189 #undef TARGET_ASM_FUNCTION_EPILOGUE
190 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
191
192 #if TARGET_ELF
193 #undef TARGET_SECTION_TYPE_FLAGS
194 #define TARGET_SECTION_TYPE_FLAGS rs6000_elf_section_type_flags
195 #endif
196
197 struct gcc_target targetm = TARGET_INITIALIZER;
198 \f
199 /* Override command line options. Mostly we process the processor
200 type and sometimes adjust other TARGET_ options. */
201
202 void
203 rs6000_override_options (default_cpu)
204 const char *default_cpu;
205 {
206 size_t i, j;
207 struct rs6000_cpu_select *ptr;
208
209 /* Simplify the entries below by making a mask for any POWER
210 variant and any PowerPC variant. */
211
212 #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING)
213 #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
214 | MASK_PPC_GFXOPT | MASK_POWERPC64)
215 #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
216
217 static struct ptt
218 {
219 const char *name; /* Canonical processor name. */
220 enum processor_type processor; /* Processor type enum value. */
221 int target_enable; /* Target flags to enable. */
222 int target_disable; /* Target flags to disable. */
223 } processor_target_table[]
224 = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS,
225 POWER_MASKS | POWERPC_MASKS},
226 {"power", PROCESSOR_POWER,
227 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
228 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
229 {"power2", PROCESSOR_POWER,
230 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
231 POWERPC_MASKS | MASK_NEW_MNEMONICS},
232 {"power3", PROCESSOR_PPC630,
233 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
234 POWER_MASKS | MASK_PPC_GPOPT},
235 {"powerpc", PROCESSOR_POWERPC,
236 MASK_POWERPC | MASK_NEW_MNEMONICS,
237 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
238 {"powerpc64", PROCESSOR_POWERPC64,
239 MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS,
240 POWER_MASKS | POWERPC_OPT_MASKS},
241 {"rios", PROCESSOR_RIOS1,
242 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
243 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
244 {"rios1", PROCESSOR_RIOS1,
245 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
246 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
247 {"rsc", PROCESSOR_PPC601,
248 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
249 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
250 {"rsc1", PROCESSOR_PPC601,
251 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
252 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
253 {"rios2", PROCESSOR_RIOS2,
254 MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
255 POWERPC_MASKS | MASK_NEW_MNEMONICS},
256 {"rs64a", PROCESSOR_RS64A,
257 MASK_POWERPC | MASK_NEW_MNEMONICS,
258 POWER_MASKS | POWERPC_OPT_MASKS},
259 {"401", PROCESSOR_PPC403,
260 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
261 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
262 {"403", PROCESSOR_PPC403,
263 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN,
264 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
265 {"505", PROCESSOR_MPCCORE,
266 MASK_POWERPC | MASK_NEW_MNEMONICS,
267 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
268 {"601", PROCESSOR_PPC601,
269 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
270 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
271 {"602", PROCESSOR_PPC603,
272 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
273 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
274 {"603", PROCESSOR_PPC603,
275 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
276 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
277 {"603e", PROCESSOR_PPC603,
278 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
279 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
280 {"ec603e", PROCESSOR_PPC603,
281 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
282 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
283 {"604", PROCESSOR_PPC604,
284 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
285 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
286 {"604e", PROCESSOR_PPC604e,
287 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
288 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
289 {"620", PROCESSOR_PPC620,
290 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
291 POWER_MASKS | MASK_PPC_GPOPT},
292 {"630", PROCESSOR_PPC630,
293 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
294 POWER_MASKS | MASK_PPC_GPOPT},
295 {"740", PROCESSOR_PPC750,
296 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
297 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
298 {"750", PROCESSOR_PPC750,
299 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
300 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
301 {"801", PROCESSOR_MPCCORE,
302 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
303 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
304 {"821", PROCESSOR_MPCCORE,
305 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
306 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
307 {"823", PROCESSOR_MPCCORE,
308 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
309 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
310 {"860", PROCESSOR_MPCCORE,
311 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
312 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}};
313
314 size_t ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
315
316 int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */
317 int string = TARGET_STRING; /* save current -mstring/-mno-string status */
318
319 profile_block_flag = 0;
320
321 /* Identify the processor type */
322 rs6000_select[0].string = default_cpu;
323 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
324
325 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
326 {
327 ptr = &rs6000_select[i];
328 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
329 {
330 for (j = 0; j < ptt_size; j++)
331 if (! strcmp (ptr->string, processor_target_table[j].name))
332 {
333 if (ptr->set_tune_p)
334 rs6000_cpu = processor_target_table[j].processor;
335
336 if (ptr->set_arch_p)
337 {
338 target_flags |= processor_target_table[j].target_enable;
339 target_flags &= ~processor_target_table[j].target_disable;
340 }
341 break;
342 }
343
344 if (j == ptt_size)
345 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
346 }
347 }
348
349 /* If we are optimizing big endian systems for space, use the
350 store multiple instructions. */
351 if (BYTES_BIG_ENDIAN && optimize_size)
352 target_flags |= MASK_MULTIPLE;
353
354 /* If -mmultiple or -mno-multiple was explicitly used, don't
355 override with the processor default */
356 if (TARGET_MULTIPLE_SET)
357 target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
358
359 /* If -mstring or -mno-string was explicitly used, don't
360 override with the processor default */
361 if (TARGET_STRING_SET)
362 target_flags = (target_flags & ~MASK_STRING) | string;
363
364 /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu
365 is a 750, because the hardware doesn't support the instructions used in
366 little endian mode, and causes an alignment trap. The 750 does not cause
367 an alignment trap (except when the target is unaligned). */
368
369 if (! BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
370 {
371 if (TARGET_MULTIPLE)
372 {
373 target_flags &= ~MASK_MULTIPLE;
374 if (TARGET_MULTIPLE_SET)
375 warning ("-mmultiple is not supported on little endian systems");
376 }
377
378 if (TARGET_STRING)
379 {
380 target_flags &= ~MASK_STRING;
381 if (TARGET_STRING_SET)
382 warning ("-mstring is not supported on little endian systems");
383 }
384 }
385
386 if (flag_pic && DEFAULT_ABI == ABI_AIX)
387 {
388 warning ("-f%s ignored (all code is position independent)",
389 (flag_pic > 1) ? "PIC" : "pic");
390 flag_pic = 0;
391 }
392
393 #ifdef XCOFF_DEBUGGING_INFO
394 if (flag_function_sections && (write_symbols != NO_DEBUG)
395 && DEFAULT_ABI == ABI_AIX)
396 {
397 warning ("-ffunction-sections disabled on AIX when debugging");
398 flag_function_sections = 0;
399 }
400
401 if (flag_data_sections && (DEFAULT_ABI == ABI_AIX))
402 {
403 warning ("-fdata-sections not supported on AIX");
404 flag_data_sections = 0;
405 }
406 #endif
407
408 /* Set debug flags */
409 if (rs6000_debug_name)
410 {
411 if (! strcmp (rs6000_debug_name, "all"))
412 rs6000_debug_stack = rs6000_debug_arg = 1;
413 else if (! strcmp (rs6000_debug_name, "stack"))
414 rs6000_debug_stack = 1;
415 else if (! strcmp (rs6000_debug_name, "arg"))
416 rs6000_debug_arg = 1;
417 else
418 error ("Unknown -mdebug-%s switch", rs6000_debug_name);
419 }
420
421 #ifdef TARGET_REGNAMES
422 /* If the user desires alternate register names, copy in the alternate names
423 now. */
424 if (TARGET_REGNAMES)
425 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
426 #endif
427
428 #ifdef SUBTARGET_OVERRIDE_OPTIONS
429 SUBTARGET_OVERRIDE_OPTIONS;
430 #endif
431
432 /* Register global variables with the garbage collector. */
433 rs6000_add_gc_roots ();
434
435 /* Allocate an alias set for register saves & restores from stack. */
436 rs6000_sr_alias_set = new_alias_set ();
437
438 if (TARGET_TOC)
439 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
440
441 /* Arrange to save and restore machine status around nested functions. */
442 init_machine_status = rs6000_init_machine_status;
443 free_machine_status = rs6000_free_machine_status;
444 }
445
446 void
447 optimization_options (level, size)
448 int level ATTRIBUTE_UNUSED;
449 int size ATTRIBUTE_UNUSED;
450 {
451 }
452 \f
453 /* Do anything needed at the start of the asm file. */
454
455 void
456 rs6000_file_start (file, default_cpu)
457 FILE *file;
458 const char *default_cpu;
459 {
460 size_t i;
461 char buffer[80];
462 const char *start = buffer;
463 struct rs6000_cpu_select *ptr;
464
465 if (flag_verbose_asm)
466 {
467 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
468 rs6000_select[0].string = default_cpu;
469
470 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
471 {
472 ptr = &rs6000_select[i];
473 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
474 {
475 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
476 start = "";
477 }
478 }
479
480 #ifdef USING_SVR4_H
481 switch (rs6000_sdata)
482 {
483 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
484 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
485 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
486 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
487 }
488
489 if (rs6000_sdata && g_switch_value)
490 {
491 fprintf (file, "%s -G %d", start, g_switch_value);
492 start = "";
493 }
494 #endif
495
496 if (*start == '\0')
497 putc ('\n', file);
498 }
499 }
500
501 \f
502 /* Create a CONST_DOUBLE from a string. */
503
504 struct rtx_def *
505 rs6000_float_const (string, mode)
506 const char *string;
507 enum machine_mode mode;
508 {
509 REAL_VALUE_TYPE value;
510 value = REAL_VALUE_ATOF (string, mode);
511 return immed_real_const_1 (value, mode);
512 }
513 \f
514 /* Return non-zero if this function is known to have a null epilogue. */
515
516 int
517 direct_return ()
518 {
519 if (reload_completed)
520 {
521 rs6000_stack_t *info = rs6000_stack_info ();
522
523 if (info->first_gp_reg_save == 32
524 && info->first_fp_reg_save == 64
525 && ! info->lr_save_p
526 && ! info->cr_save_p
527 && ! info->push_p)
528 return 1;
529 }
530
531 return 0;
532 }
533
534 /* Returns 1 always. */
535
536 int
537 any_operand (op, mode)
538 register rtx op ATTRIBUTE_UNUSED;
539 enum machine_mode mode ATTRIBUTE_UNUSED;
540 {
541 return 1;
542 }
543
544 /* Returns 1 if op is the count register */
545 int
546 count_register_operand(op, mode)
547 register rtx op;
548 enum machine_mode mode ATTRIBUTE_UNUSED;
549 {
550 if (GET_CODE (op) != REG)
551 return 0;
552
553 if (REGNO (op) == COUNT_REGISTER_REGNUM)
554 return 1;
555
556 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
557 return 1;
558
559 return 0;
560 }
561
562 int
563 xer_operand(op, mode)
564 register rtx op;
565 enum machine_mode mode ATTRIBUTE_UNUSED;
566 {
567 if (GET_CODE (op) != REG)
568 return 0;
569
570 if (XER_REGNO_P (REGNO (op)))
571 return 1;
572
573 return 0;
574 }
575
576 /* Return 1 if OP is a constant that can fit in a D field. */
577
578 int
579 short_cint_operand (op, mode)
580 register rtx op;
581 enum machine_mode mode ATTRIBUTE_UNUSED;
582 {
583 return (GET_CODE (op) == CONST_INT
584 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
585 }
586
587 /* Similar for a unsigned D field. */
588
589 int
590 u_short_cint_operand (op, mode)
591 register rtx op;
592 enum machine_mode mode ATTRIBUTE_UNUSED;
593 {
594 return (GET_CODE (op) == CONST_INT
595 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K'));
596 }
597
598 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
599
600 int
601 non_short_cint_operand (op, mode)
602 register rtx op;
603 enum machine_mode mode ATTRIBUTE_UNUSED;
604 {
605 return (GET_CODE (op) == CONST_INT
606 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
607 }
608
609 /* Returns 1 if OP is a CONST_INT that is a positive value
610 and an exact power of 2. */
611
612 int
613 exact_log2_cint_operand (op, mode)
614 register rtx op;
615 enum machine_mode mode ATTRIBUTE_UNUSED;
616 {
617 return (GET_CODE (op) == CONST_INT
618 && INTVAL (op) > 0
619 && exact_log2 (INTVAL (op)) >= 0);
620 }
621
622 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
623 ctr, or lr). */
624
625 int
626 gpc_reg_operand (op, mode)
627 register rtx op;
628 enum machine_mode mode;
629 {
630 return (register_operand (op, mode)
631 && (GET_CODE (op) != REG
632 || (REGNO (op) >= ARG_POINTER_REGNUM
633 && !XER_REGNO_P (REGNO (op)))
634 || REGNO (op) < MQ_REGNO));
635 }
636
637 /* Returns 1 if OP is either a pseudo-register or a register denoting a
638 CR field. */
639
640 int
641 cc_reg_operand (op, mode)
642 register rtx op;
643 enum machine_mode mode;
644 {
645 return (register_operand (op, mode)
646 && (GET_CODE (op) != REG
647 || REGNO (op) >= FIRST_PSEUDO_REGISTER
648 || CR_REGNO_P (REGNO (op))));
649 }
650
651 /* Returns 1 if OP is either a pseudo-register or a register denoting a
652 CR field that isn't CR0. */
653
654 int
655 cc_reg_not_cr0_operand (op, mode)
656 register rtx op;
657 enum machine_mode mode;
658 {
659 return (register_operand (op, mode)
660 && (GET_CODE (op) != REG
661 || REGNO (op) >= FIRST_PSEUDO_REGISTER
662 || CR_REGNO_NOT_CR0_P (REGNO (op))));
663 }
664
665 /* Returns 1 if OP is either a constant integer valid for a D-field or a
666 non-special register. If a register, it must be in the proper mode unless
667 MODE is VOIDmode. */
668
669 int
670 reg_or_short_operand (op, mode)
671 register rtx op;
672 enum machine_mode mode;
673 {
674 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
675 }
676
677 /* Similar, except check if the negation of the constant would be valid for
678 a D-field. */
679
680 int
681 reg_or_neg_short_operand (op, mode)
682 register rtx op;
683 enum machine_mode mode;
684 {
685 if (GET_CODE (op) == CONST_INT)
686 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
687
688 return gpc_reg_operand (op, mode);
689 }
690
691 /* Return 1 if the operand is either a register or an integer whose high-order
692 16 bits are zero. */
693
694 int
695 reg_or_u_short_operand (op, mode)
696 register rtx op;
697 enum machine_mode mode;
698 {
699 return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
700 }
701
702 /* Return 1 is the operand is either a non-special register or ANY
703 constant integer. */
704
705 int
706 reg_or_cint_operand (op, mode)
707 register rtx op;
708 enum machine_mode mode;
709 {
710 return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
711 }
712
713 /* Return 1 is the operand is either a non-special register or ANY
714 32-bit signed constant integer. */
715
716 int
717 reg_or_arith_cint_operand (op, mode)
718 register rtx op;
719 enum machine_mode mode;
720 {
721 return (gpc_reg_operand (op, mode)
722 || (GET_CODE (op) == CONST_INT
723 #if HOST_BITS_PER_WIDE_INT != 32
724 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
725 < (unsigned HOST_WIDE_INT) 0x100000000ll)
726 #endif
727 ));
728 }
729
730 /* Return 1 is the operand is either a non-special register or a 32-bit
731 signed constant integer valid for 64-bit addition. */
732
733 int
734 reg_or_add_cint64_operand (op, mode)
735 register rtx op;
736 enum machine_mode mode;
737 {
738 return (gpc_reg_operand (op, mode)
739 || (GET_CODE (op) == CONST_INT
740 && INTVAL (op) < 0x7fff8000
741 #if HOST_BITS_PER_WIDE_INT != 32
742 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
743 < 0x100000000ll)
744 #endif
745 ));
746 }
747
748 /* Return 1 is the operand is either a non-special register or a 32-bit
749 signed constant integer valid for 64-bit subtraction. */
750
751 int
752 reg_or_sub_cint64_operand (op, mode)
753 register rtx op;
754 enum machine_mode mode;
755 {
756 return (gpc_reg_operand (op, mode)
757 || (GET_CODE (op) == CONST_INT
758 && (- INTVAL (op)) < 0x7fff8000
759 #if HOST_BITS_PER_WIDE_INT != 32
760 && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
761 < 0x100000000ll)
762 #endif
763 ));
764 }
765
766 /* Return 1 is the operand is either a non-special register or ANY
767 32-bit unsigned constant integer. */
768
769 int
770 reg_or_logical_cint_operand (op, mode)
771 register rtx op;
772 enum machine_mode mode;
773 {
774 if (GET_CODE (op) == CONST_INT)
775 {
776 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
777 {
778 if (GET_MODE_BITSIZE (mode) <= 32)
779 abort();
780
781 if (INTVAL (op) < 0)
782 return 0;
783 }
784
785 return ((INTVAL (op) & GET_MODE_MASK (mode)
786 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
787 }
788 else if (GET_CODE (op) == CONST_DOUBLE)
789 {
790 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
791 || mode != DImode)
792 abort();
793
794 return CONST_DOUBLE_HIGH (op) == 0;
795 }
796 else
797 return gpc_reg_operand (op, mode);
798 }
799
800 /* Return 1 if the operand is an operand that can be loaded via the GOT */
801
802 int
803 got_operand (op, mode)
804 register rtx op;
805 enum machine_mode mode ATTRIBUTE_UNUSED;
806 {
807 return (GET_CODE (op) == SYMBOL_REF
808 || GET_CODE (op) == CONST
809 || GET_CODE (op) == LABEL_REF);
810 }
811
812 /* Return 1 if the operand is a simple references that can be loaded via
813 the GOT (labels involving addition aren't allowed). */
814
815 int
816 got_no_const_operand (op, mode)
817 register rtx op;
818 enum machine_mode mode ATTRIBUTE_UNUSED;
819 {
820 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
821 }
822
823 /* Return the number of instructions it takes to form a constant in an
824 integer register. */
825
826 static int
827 num_insns_constant_wide (value)
828 HOST_WIDE_INT value;
829 {
830 /* signed constant loadable with {cal|addi} */
831 if (CONST_OK_FOR_LETTER_P (value, 'I'))
832 return 1;
833
834 /* constant loadable with {cau|addis} */
835 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
836 return 1;
837
838 #if HOST_BITS_PER_WIDE_INT == 64
839 else if (TARGET_POWERPC64)
840 {
841 HOST_WIDE_INT low = value & 0xffffffff;
842 HOST_WIDE_INT high = value >> 32;
843
844 low = (low ^ 0x80000000) - 0x80000000; /* sign extend */
845
846 if (high == 0 && (low & 0x80000000) == 0)
847 return 2;
848
849 else if (high == -1 && (low & 0x80000000) != 0)
850 return 2;
851
852 else if (! low)
853 return num_insns_constant_wide (high) + 1;
854
855 else
856 return (num_insns_constant_wide (high)
857 + num_insns_constant_wide (low) + 1);
858 }
859 #endif
860
861 else
862 return 2;
863 }
864
865 int
866 num_insns_constant (op, mode)
867 rtx op;
868 enum machine_mode mode;
869 {
870 if (GET_CODE (op) == CONST_INT)
871 {
872 #if HOST_BITS_PER_WIDE_INT == 64
873 if (mask64_operand (op, mode))
874 return 2;
875 else
876 #endif
877 return num_insns_constant_wide (INTVAL (op));
878 }
879
880 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
881 {
882 long l;
883 REAL_VALUE_TYPE rv;
884
885 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
886 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
887 return num_insns_constant_wide ((HOST_WIDE_INT)l);
888 }
889
890 else if (GET_CODE (op) == CONST_DOUBLE)
891 {
892 HOST_WIDE_INT low;
893 HOST_WIDE_INT high;
894 long l[2];
895 REAL_VALUE_TYPE rv;
896 int endian = (WORDS_BIG_ENDIAN == 0);
897
898 if (mode == VOIDmode || mode == DImode)
899 {
900 high = CONST_DOUBLE_HIGH (op);
901 low = CONST_DOUBLE_LOW (op);
902 }
903 else
904 {
905 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
906 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
907 high = l[endian];
908 low = l[1 - endian];
909 }
910
911 if (TARGET_32BIT)
912 return (num_insns_constant_wide (low)
913 + num_insns_constant_wide (high));
914
915 else
916 {
917 if (high == 0 && (low & 0x80000000) == 0)
918 return num_insns_constant_wide (low);
919
920 else if (high == -1 && (low & 0x80000000) != 0)
921 return num_insns_constant_wide (low);
922
923 else if (mask64_operand (op, mode))
924 return 2;
925
926 else if (low == 0)
927 return num_insns_constant_wide (high) + 1;
928
929 else
930 return (num_insns_constant_wide (high)
931 + num_insns_constant_wide (low) + 1);
932 }
933 }
934
935 else
936 abort ();
937 }
938
939 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register
940 with one instruction per word. We only do this if we can safely read
941 CONST_DOUBLE_{LOW,HIGH}. */
942
943 int
944 easy_fp_constant (op, mode)
945 register rtx op;
946 register enum machine_mode mode;
947 {
948 if (GET_CODE (op) != CONST_DOUBLE
949 || GET_MODE (op) != mode
950 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
951 return 0;
952
953 /* Consider all constants with -msoft-float to be easy */
954 if (TARGET_SOFT_FLOAT && mode != DImode)
955 return 1;
956
957 /* If we are using V.4 style PIC, consider all constants to be hard */
958 if (flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS))
959 return 0;
960
961 #ifdef TARGET_RELOCATABLE
962 /* Similarly if we are using -mrelocatable, consider all constants to be hard */
963 if (TARGET_RELOCATABLE)
964 return 0;
965 #endif
966
967 if (mode == DFmode)
968 {
969 long k[2];
970 REAL_VALUE_TYPE rv;
971
972 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
973 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
974
975 return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1
976 && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1);
977 }
978
979 else if (mode == SFmode)
980 {
981 long l;
982 REAL_VALUE_TYPE rv;
983
984 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
985 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
986
987 return num_insns_constant_wide (l) == 1;
988 }
989
990 else if (mode == DImode)
991 return ((TARGET_POWERPC64
992 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
993 || (num_insns_constant (op, DImode) <= 2));
994
995 else if (mode == SImode)
996 return 1;
997 else
998 abort ();
999 }
1000
1001 /* Return 1 if the operand is 0.0. */
1002 int
1003 zero_fp_constant (op, mode)
1004 register rtx op;
1005 register enum machine_mode mode;
1006 {
1007 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
1008 }
1009
1010 /* Return 1 if the operand is in volatile memory. Note that during the
1011 RTL generation phase, memory_operand does not return TRUE for
1012 volatile memory references. So this function allows us to
1013 recognize volatile references where its safe. */
1014
1015 int
1016 volatile_mem_operand (op, mode)
1017 register rtx op;
1018 enum machine_mode mode;
1019 {
1020 if (GET_CODE (op) != MEM)
1021 return 0;
1022
1023 if (!MEM_VOLATILE_P (op))
1024 return 0;
1025
1026 if (mode != GET_MODE (op))
1027 return 0;
1028
1029 if (reload_completed)
1030 return memory_operand (op, mode);
1031
1032 if (reload_in_progress)
1033 return strict_memory_address_p (mode, XEXP (op, 0));
1034
1035 return memory_address_p (mode, XEXP (op, 0));
1036 }
1037
1038 /* Return 1 if the operand is an offsettable memory operand. */
1039
1040 int
1041 offsettable_mem_operand (op, mode)
1042 register rtx op;
1043 enum machine_mode mode;
1044 {
1045 return ((GET_CODE (op) == MEM)
1046 && offsettable_address_p (reload_completed || reload_in_progress,
1047 mode, XEXP (op, 0)));
1048 }
1049
1050 /* Return 1 if the operand is either an easy FP constant (see above) or
1051 memory. */
1052
1053 int
1054 mem_or_easy_const_operand (op, mode)
1055 register rtx op;
1056 enum machine_mode mode;
1057 {
1058 return memory_operand (op, mode) || easy_fp_constant (op, mode);
1059 }
1060
1061 /* Return 1 if the operand is either a non-special register or an item
1062 that can be used as the operand of a `mode' add insn. */
1063
1064 int
1065 add_operand (op, mode)
1066 register rtx op;
1067 enum machine_mode mode;
1068 {
1069 if (GET_CODE (op) == CONST_INT)
1070 return (CONST_OK_FOR_LETTER_P (INTVAL(op), 'I')
1071 || CONST_OK_FOR_LETTER_P (INTVAL(op), 'L'));
1072
1073 return gpc_reg_operand (op, mode);
1074 }
1075
1076 /* Return 1 if OP is a constant but not a valid add_operand. */
1077
1078 int
1079 non_add_cint_operand (op, mode)
1080 register rtx op;
1081 enum machine_mode mode ATTRIBUTE_UNUSED;
1082 {
1083 return (GET_CODE (op) == CONST_INT
1084 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000
1085 && ! CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1086 }
1087
1088 /* Return 1 if the operand is a non-special register or a constant that
1089 can be used as the operand of an OR or XOR insn on the RS/6000. */
1090
1091 int
1092 logical_operand (op, mode)
1093 register rtx op;
1094 enum machine_mode mode;
1095 {
1096 /* an unsigned representation of 'op'. */
1097 unsigned HOST_WIDE_INT opl, oph;
1098
1099 if (gpc_reg_operand (op, mode))
1100 return 1;
1101
1102 if (GET_CODE (op) == CONST_INT)
1103 opl = INTVAL (op);
1104 else if (GET_CODE (op) == CONST_DOUBLE)
1105 {
1106 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1107 abort();
1108
1109 opl = CONST_DOUBLE_LOW (op);
1110 oph = CONST_DOUBLE_HIGH (op);
1111
1112 if (oph != ((unsigned HOST_WIDE_INT)0
1113 - ((opl & ((unsigned HOST_WIDE_INT)1
1114 << (HOST_BITS_PER_WIDE_INT - 1))) != 0)))
1115 return 0;
1116 }
1117 else
1118 return 0;
1119
1120 /* This must really be SImode, not MODE. */
1121 if (opl != (unsigned HOST_WIDE_INT) trunc_int_for_mode (opl, SImode))
1122 return 0;
1123
1124 return ((opl & 0xffff) == 0
1125 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0);
1126 }
1127
1128 /* Return 1 if C is a constant that is not a logical operand (as
1129 above), but could be split into one. */
1130
1131 int
1132 non_logical_cint_operand (op, mode)
1133 register rtx op;
1134 enum machine_mode mode;
1135 {
1136 return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
1137 && ! logical_operand (op, mode)
1138 && reg_or_logical_cint_operand (op, mode));
1139 }
1140
1141 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
1142 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
1143 Reject all ones and all zeros, since these should have been optimized
1144 away and confuse the making of MB and ME. */
1145
1146 int
1147 mask_operand (op, mode)
1148 register rtx op;
1149 enum machine_mode mode ATTRIBUTE_UNUSED;
1150 {
1151 HOST_WIDE_INT c;
1152 int i;
1153 int last_bit_value;
1154 int transitions = 0;
1155
1156 if (GET_CODE (op) != CONST_INT)
1157 return 0;
1158
1159 c = INTVAL (op);
1160
1161 if (c == 0 || c == ~0)
1162 return 0;
1163
1164 last_bit_value = c & 1;
1165
1166 for (i = 1; i < 32; i++)
1167 if (((c >>= 1) & 1) != last_bit_value)
1168 last_bit_value ^= 1, transitions++;
1169
1170 return transitions <= 2;
1171 }
1172
1173 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
1174 It is if there are no more than one 1->0 or 0->1 transitions.
1175 Reject all ones and all zeros, since these should have been optimized
1176 away and confuse the making of MB and ME. */
1177
1178 int
1179 mask64_operand (op, mode)
1180 register rtx op;
1181 enum machine_mode mode;
1182 {
1183 if (GET_CODE (op) == CONST_INT)
1184 {
1185 HOST_WIDE_INT c = INTVAL (op);
1186 int i;
1187 int last_bit_value;
1188 int transitions = 0;
1189
1190 if (c == 0 || c == ~0)
1191 return 0;
1192
1193 last_bit_value = c & 1;
1194
1195 for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
1196 if (((c >>= 1) & 1) != last_bit_value)
1197 last_bit_value ^= 1, transitions++;
1198
1199 return transitions <= 1;
1200 }
1201 else if (GET_CODE (op) == CONST_DOUBLE
1202 && (mode == VOIDmode || mode == DImode))
1203 {
1204 HOST_WIDE_INT low = CONST_DOUBLE_LOW (op);
1205 #if HOST_BITS_PER_WIDE_INT == 32
1206 HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op);
1207 #endif
1208 int i;
1209 int last_bit_value;
1210 int transitions = 0;
1211
1212 if ((low == 0
1213 #if HOST_BITS_PER_WIDE_INT == 32
1214 && high == 0
1215 #endif
1216 )
1217 || (low == ~0
1218 #if HOST_BITS_PER_WIDE_INT == 32
1219 && high == ~0
1220 #endif
1221 ))
1222 return 0;
1223
1224 last_bit_value = low & 1;
1225
1226 for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
1227 if (((low >>= 1) & 1) != last_bit_value)
1228 last_bit_value ^= 1, transitions++;
1229
1230 #if HOST_BITS_PER_WIDE_INT == 32
1231 if ((high & 1) != last_bit_value)
1232 last_bit_value ^= 1, transitions++;
1233
1234 for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
1235 if (((high >>= 1) & 1) != last_bit_value)
1236 last_bit_value ^= 1, transitions++;
1237 #endif
1238
1239 return transitions <= 1;
1240 }
1241 else
1242 return 0;
1243 }
1244
1245 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
1246 It is if there are no more than two 1->0 or 0->1 transitions.
1247 Reject all ones and all zeros, since these should have been optimized
1248 away and confuse the making of MB and ME. */
1249
1250 int
1251 rldic_operand (op, mode)
1252 register rtx op;
1253 enum machine_mode mode;
1254 {
1255 if (GET_CODE (op) == CONST_INT)
1256 {
1257 HOST_WIDE_INT c = INTVAL (op);
1258 int i;
1259 int last_bit_value;
1260 int transitions = 0;
1261
1262 if (c == 0 || c == ~0)
1263 return 0;
1264
1265 last_bit_value = c & 1;
1266
1267 for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
1268 if (((c >>= 1) & 1) != last_bit_value)
1269 last_bit_value ^= 1, transitions++;
1270
1271 return transitions <= 2;
1272 }
1273 else if (GET_CODE (op) == CONST_DOUBLE
1274 && (mode == VOIDmode || mode == DImode))
1275 {
1276 HOST_WIDE_INT low = CONST_DOUBLE_LOW (op);
1277 #if HOST_BITS_PER_WIDE_INT == 32
1278 HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op);
1279 #endif
1280 int i;
1281 int last_bit_value;
1282 int transitions = 0;
1283
1284 if ((low == 0
1285 #if HOST_BITS_PER_WIDE_INT == 32
1286 && high == 0
1287 #endif
1288 )
1289 || (low == ~0
1290 #if HOST_BITS_PER_WIDE_INT == 32
1291 && high == ~0
1292 #endif
1293 ))
1294 return 0;
1295
1296 last_bit_value = low & 1;
1297
1298 for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
1299 if (((low >>= 1) & 1) != last_bit_value)
1300 last_bit_value ^= 1, transitions++;
1301
1302 #if HOST_BITS_PER_WIDE_INT == 32
1303 if ((high & 1) != last_bit_value)
1304 last_bit_value ^= 1, transitions++;
1305
1306 for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
1307 if (((high >>= 1) & 1) != last_bit_value)
1308 last_bit_value ^= 1, transitions++;
1309 #endif
1310
1311 return transitions <= 2;
1312 }
1313 else
1314 return 0;
1315 }
1316
1317 /* Return 1 if the operand is either a non-special register or a constant
1318 that can be used as the operand of a PowerPC64 logical AND insn. */
1319
1320 int
1321 and64_operand (op, mode)
1322 register rtx op;
1323 enum machine_mode mode;
1324 {
1325 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
1326 return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
1327
1328 return (logical_operand (op, mode) || mask64_operand (op, mode));
1329 }
1330
1331 /* Return 1 if the operand is either a non-special register or a
1332 constant that can be used as the operand of an RS/6000 logical AND insn. */
1333
1334 int
1335 and_operand (op, mode)
1336 register rtx op;
1337 enum machine_mode mode;
1338 {
1339 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
1340 return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
1341
1342 return (logical_operand (op, mode) || mask_operand (op, mode));
1343 }
1344
1345 /* Return 1 if the operand is a general register or memory operand. */
1346
1347 int
1348 reg_or_mem_operand (op, mode)
1349 register rtx op;
1350 register enum machine_mode mode;
1351 {
1352 return (gpc_reg_operand (op, mode)
1353 || memory_operand (op, mode)
1354 || volatile_mem_operand (op, mode));
1355 }
1356
1357 /* Return 1 if the operand is a general register or memory operand without
1358 pre_inc or pre_dec which produces invalid form of PowerPC lwa
1359 instruction. */
1360
1361 int
1362 lwa_operand (op, mode)
1363 register rtx op;
1364 register enum machine_mode mode;
1365 {
1366 rtx inner = op;
1367
1368 if (reload_completed && GET_CODE (inner) == SUBREG)
1369 inner = SUBREG_REG (inner);
1370
1371 return gpc_reg_operand (inner, mode)
1372 || (memory_operand (inner, mode)
1373 && GET_CODE (XEXP (inner, 0)) != PRE_INC
1374 && GET_CODE (XEXP (inner, 0)) != PRE_DEC);
1375 }
1376
1377 /* Return 1 if the operand, used inside a MEM, is a valid first argument
1378 to CALL. This is a SYMBOL_REF or a pseudo-register, which will be
1379 forced to lr. */
1380
1381 int
1382 call_operand (op, mode)
1383 register rtx op;
1384 enum machine_mode mode;
1385 {
1386 if (mode != VOIDmode && GET_MODE (op) != mode)
1387 return 0;
1388
1389 return (GET_CODE (op) == SYMBOL_REF
1390 || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER));
1391 }
1392
1393
1394 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
1395 this file and the function is not weakly defined. */
1396
1397 int
1398 current_file_function_operand (op, mode)
1399 register rtx op;
1400 enum machine_mode mode ATTRIBUTE_UNUSED;
1401 {
1402 return (GET_CODE (op) == SYMBOL_REF
1403 && (SYMBOL_REF_FLAG (op)
1404 || (op == XEXP (DECL_RTL (current_function_decl), 0)
1405 && ! DECL_WEAK (current_function_decl))));
1406 }
1407
1408
1409 /* Return 1 if this operand is a valid input for a move insn. */
1410
1411 int
1412 input_operand (op, mode)
1413 register rtx op;
1414 enum machine_mode mode;
1415 {
1416 /* Memory is always valid. */
1417 if (memory_operand (op, mode))
1418 return 1;
1419
1420 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1421 if (GET_CODE (op) == CONSTANT_P_RTX)
1422 return 1;
1423
1424 /* For floating-point, easy constants are valid. */
1425 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1426 && CONSTANT_P (op)
1427 && easy_fp_constant (op, mode))
1428 return 1;
1429
1430 /* Allow any integer constant. */
1431 if (GET_MODE_CLASS (mode) == MODE_INT
1432 && (GET_CODE (op) == CONST_INT
1433 || GET_CODE (op) == CONST_DOUBLE))
1434 return 1;
1435
1436 /* For floating-point or multi-word mode, the only remaining valid type
1437 is a register. */
1438 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1439 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1440 return register_operand (op, mode);
1441
1442 /* The only cases left are integral modes one word or smaller (we
1443 do not get called for MODE_CC values). These can be in any
1444 register. */
1445 if (register_operand (op, mode))
1446 return 1;
1447
1448 /* A SYMBOL_REF referring to the TOC is valid. */
1449 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op))
1450 return 1;
1451
1452 /* A constant pool expression (relative to the TOC) is valid */
1453 if (TOC_RELATIVE_EXPR_P (op))
1454 return 1;
1455
1456 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1457 to be valid. */
1458 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
1459 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1460 && small_data_operand (op, Pmode))
1461 return 1;
1462
1463 return 0;
1464 }
1465
1466 /* Return 1 for an operand in small memory on V.4/eabi */
1467
1468 int
1469 small_data_operand (op, mode)
1470 rtx op ATTRIBUTE_UNUSED;
1471 enum machine_mode mode ATTRIBUTE_UNUSED;
1472 {
1473 #if TARGET_ELF
1474 rtx sym_ref;
1475
1476 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
1477 return 0;
1478
1479 if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
1480 return 0;
1481
1482 if (GET_CODE (op) == SYMBOL_REF)
1483 sym_ref = op;
1484
1485 else if (GET_CODE (op) != CONST
1486 || GET_CODE (XEXP (op, 0)) != PLUS
1487 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
1488 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
1489 return 0;
1490
1491 else
1492 {
1493 rtx sum = XEXP (op, 0);
1494 HOST_WIDE_INT summand;
1495
1496 /* We have to be careful here, because it is the referenced address
1497 that must be 32k from _SDA_BASE_, not just the symbol. */
1498 summand = INTVAL (XEXP (sum, 1));
1499 if (summand < 0 || summand > g_switch_value)
1500 return 0;
1501
1502 sym_ref = XEXP (sum, 0);
1503 }
1504
1505 if (*XSTR (sym_ref, 0) != '@')
1506 return 0;
1507
1508 return 1;
1509
1510 #else
1511 return 0;
1512 #endif
1513 }
1514 \f
1515 static int
1516 constant_pool_expr_1 (op, have_sym, have_toc)
1517 rtx op;
1518 int *have_sym;
1519 int *have_toc;
1520 {
1521 switch (GET_CODE(op))
1522 {
1523 case SYMBOL_REF:
1524 if (CONSTANT_POOL_ADDRESS_P (op))
1525 {
1526 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
1527 {
1528 *have_sym = 1;
1529 return 1;
1530 }
1531 else
1532 return 0;
1533 }
1534 else if (! strcmp (XSTR (op, 0), toc_label_name))
1535 {
1536 *have_toc = 1;
1537 return 1;
1538 }
1539 else
1540 return 0;
1541 case PLUS:
1542 case MINUS:
1543 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) &&
1544 constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc);
1545 case CONST:
1546 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
1547 case CONST_INT:
1548 return 1;
1549 default:
1550 return 0;
1551 }
1552 }
1553
1554 int
1555 constant_pool_expr_p (op)
1556 rtx op;
1557 {
1558 int have_sym = 0;
1559 int have_toc = 0;
1560 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
1561 }
1562
1563 int
1564 toc_relative_expr_p (op)
1565 rtx op;
1566 {
1567 int have_sym = 0;
1568 int have_toc = 0;
1569 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
1570 }
1571
1572 /* Try machine-dependent ways of modifying an illegitimate address
1573 to be legitimate. If we find one, return the new, valid address.
1574 This is used from only one place: `memory_address' in explow.c.
1575
1576 OLDX is the address as it was before break_out_memory_refs was called.
1577 In some cases it is useful to look at this to decide what needs to be done.
1578
1579 MODE is passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS.
1580
1581 It is always safe for this macro to do nothing. It exists to recognize
1582 opportunities to optimize the output.
1583
1584 On RS/6000, first check for the sum of a register with a constant
1585 integer that is out of range. If so, generate code to add the
1586 constant with the low-order 16 bits masked to the register and force
1587 this result into another register (this can be done with `cau').
1588 Then generate an address of REG+(CONST&0xffff), allowing for the
1589 possibility of bit 16 being a one.
1590
1591 Then check for the sum of a register and something not constant, try to
1592 load the other things into a register and return the sum. */
1593 rtx
1594 rs6000_legitimize_address (x, oldx, mode)
1595 rtx x;
1596 rtx oldx ATTRIBUTE_UNUSED;
1597 enum machine_mode mode;
1598 {
1599 if (GET_CODE (x) == PLUS
1600 && GET_CODE (XEXP (x, 0)) == REG
1601 && GET_CODE (XEXP (x, 1)) == CONST_INT
1602 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
1603 {
1604 HOST_WIDE_INT high_int, low_int;
1605 rtx sum;
1606 high_int = INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff);
1607 low_int = INTVAL (XEXP (x, 1)) & 0xffff;
1608 if (low_int & 0x8000)
1609 high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16;
1610 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
1611 GEN_INT (high_int)), 0);
1612 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
1613 }
1614 else if (GET_CODE (x) == PLUS
1615 && GET_CODE (XEXP (x, 0)) == REG
1616 && GET_CODE (XEXP (x, 1)) != CONST_INT
1617 && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode)
1618 && (TARGET_POWERPC64 || mode != DImode)
1619 && mode != TImode)
1620 {
1621 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
1622 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
1623 }
1624 else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic
1625 && GET_CODE (x) != CONST_INT
1626 && GET_CODE (x) != CONST_DOUBLE
1627 && CONSTANT_P (x)
1628 && (TARGET_HARD_FLOAT || mode != DFmode)
1629 && mode != DImode
1630 && mode != TImode)
1631 {
1632 rtx reg = gen_reg_rtx (Pmode);
1633 emit_insn (gen_elf_high (reg, (x)));
1634 return gen_rtx_LO_SUM (Pmode, reg, (x));
1635 }
1636 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
1637 && ! flag_pic
1638 && GET_CODE (x) != CONST_INT
1639 && GET_CODE (x) != CONST_DOUBLE
1640 && CONSTANT_P (x)
1641 && (TARGET_HARD_FLOAT || mode != DFmode)
1642 && mode != DImode
1643 && mode != TImode)
1644 {
1645 rtx reg = gen_reg_rtx (Pmode);
1646 emit_insn (gen_macho_high (reg, (x)));
1647 return gen_rtx_LO_SUM (Pmode, reg, (x));
1648 }
1649 else if (TARGET_TOC
1650 && CONSTANT_POOL_EXPR_P (x)
1651 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
1652 {
1653 return create_TOC_reference (x);
1654 }
1655 else
1656 return NULL_RTX;
1657 }
1658
1659 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1660 that is a valid memory address for an instruction.
1661 The MODE argument is the machine mode for the MEM expression
1662 that wants to use this address.
1663
1664 On the RS/6000, there are four valid address: a SYMBOL_REF that
1665 refers to a constant pool entry of an address (or the sum of it
1666 plus a constant), a short (16-bit signed) constant plus a register,
1667 the sum of two registers, or a register indirect, possibly with an
1668 auto-increment. For DFmode and DImode with an constant plus register,
1669 we must ensure that both words are addressable or PowerPC64 with offset
1670 word aligned.
1671
1672 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1673 32-bit DImode, TImode), indexed addressing cannot be used because
1674 adjacent memory cells are accessed by adding word-sized offsets
1675 during assembly output. */
1676 int
1677 rs6000_legitimate_address (mode, x, reg_ok_strict)
1678 enum machine_mode mode;
1679 rtx x;
1680 int reg_ok_strict;
1681 {
1682 if (LEGITIMATE_INDIRECT_ADDRESS_P (x, reg_ok_strict))
1683 return 1;
1684 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
1685 && TARGET_UPDATE
1686 && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (x, 0), reg_ok_strict))
1687 return 1;
1688 if (LEGITIMATE_SMALL_DATA_P (mode, x))
1689 return 1;
1690 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x))
1691 return 1;
1692 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
1693 if (! reg_ok_strict
1694 && GET_CODE (x) == PLUS
1695 && GET_CODE (XEXP (x, 0)) == REG
1696 && XEXP (x, 0) == virtual_stack_vars_rtx
1697 && GET_CODE (XEXP (x, 1)) == CONST_INT)
1698 return 1;
1699 if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, reg_ok_strict))
1700 return 1;
1701 if (mode != TImode
1702 && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode)
1703 && (TARGET_POWERPC64 || mode != DImode)
1704 && LEGITIMATE_INDEXED_ADDRESS_P (x, reg_ok_strict))
1705 return 1;
1706 if (LEGITIMATE_LO_SUM_ADDRESS_P (mode, x, reg_ok_strict))
1707 return 1;
1708 return 0;
1709 }
1710 \f
1711 /* Try to output insns to set TARGET equal to the constant C if it can be
1712 done in less than N insns. Do all computations in MODE. Returns the place
1713 where the output has been placed if it can be done and the insns have been
1714 emitted. If it would take more than N insns, zero is returned and no
1715 insns and emitted. */
1716
1717 rtx
1718 rs6000_emit_set_const (dest, mode, source, n)
1719 rtx dest, source;
1720 enum machine_mode mode;
1721 int n ATTRIBUTE_UNUSED;
1722 {
1723 HOST_WIDE_INT c0, c1;
1724
1725 if (mode == QImode || mode == HImode || mode == SImode)
1726 {
1727 if (dest == NULL)
1728 dest = gen_reg_rtx (mode);
1729 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
1730 return dest;
1731 }
1732
1733 if (GET_CODE (source) == CONST_INT)
1734 {
1735 c0 = INTVAL (source);
1736 c1 = -(c0 < 0);
1737 }
1738 else if (GET_CODE (source) == CONST_DOUBLE)
1739 {
1740 #if HOST_BITS_PER_WIDE_INT >= 64
1741 c0 = CONST_DOUBLE_LOW (source);
1742 c1 = -(c0 < 0);
1743 #else
1744 c0 = CONST_DOUBLE_LOW (source);
1745 c1 = CONST_DOUBLE_HIGH (source);
1746 #endif
1747 }
1748 else
1749 abort();
1750
1751 return rs6000_emit_set_long_const (dest, c0, c1);
1752 }
1753
1754 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
1755 fall back to a straight forward decomposition. We do this to avoid
1756 exponential run times encountered when looking for longer sequences
1757 with rs6000_emit_set_const. */
1758 static rtx
1759 rs6000_emit_set_long_const (dest, c1, c2)
1760 rtx dest;
1761 HOST_WIDE_INT c1, c2;
1762 {
1763 if (!TARGET_POWERPC64)
1764 {
1765 rtx operand1, operand2;
1766
1767 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
1768 DImode);
1769 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
1770 DImode);
1771 emit_move_insn (operand1, GEN_INT (c1));
1772 emit_move_insn (operand2, GEN_INT (c2));
1773 }
1774 else
1775 {
1776 HOST_WIDE_INT d1, d2, d3, d4;
1777
1778 /* Decompose the entire word */
1779 #if HOST_BITS_PER_WIDE_INT >= 64
1780 if (c2 != -(c1 < 0))
1781 abort ();
1782 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1783 c1 -= d1;
1784 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1785 c1 = (c1 - d2) >> 32;
1786 d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1787 c1 -= d3;
1788 d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1789 if (c1 != d4)
1790 abort ();
1791 #else
1792 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1793 c1 -= d1;
1794 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1795 if (c1 != d2)
1796 abort ();
1797 c2 += (d2 < 0);
1798 d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
1799 c2 -= d3;
1800 d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1801 if (c2 != d4)
1802 abort ();
1803 #endif
1804
1805 /* Construct the high word */
1806 if (d4)
1807 {
1808 emit_move_insn (dest, GEN_INT (d4));
1809 if (d3)
1810 emit_move_insn (dest,
1811 gen_rtx_PLUS (DImode, dest, GEN_INT (d3)));
1812 }
1813 else
1814 emit_move_insn (dest, GEN_INT (d3));
1815
1816 /* Shift it into place */
1817 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
1818
1819 /* Add in the low bits. */
1820 if (d2)
1821 emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d2)));
1822 if (d1)
1823 emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d1)));
1824 }
1825
1826 return dest;
1827 }
1828
1829 /* Emit a move from SOURCE to DEST in mode MODE. */
1830 void
1831 rs6000_emit_move (dest, source, mode)
1832 rtx dest;
1833 rtx source;
1834 enum machine_mode mode;
1835 {
1836 rtx operands[2];
1837 operands[0] = dest;
1838 operands[1] = source;
1839
1840 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
1841 if (GET_CODE (operands[1]) == CONST_DOUBLE
1842 && ! FLOAT_MODE_P (mode)
1843 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1844 {
1845 /* FIXME. This should never happen. */
1846 /* Since it seems that it does, do the safe thing and convert
1847 to a CONST_INT. */
1848 operands[1] =
1849 GEN_INT (trunc_int_for_mode (CONST_DOUBLE_LOW (operands[1]), mode));
1850 }
1851 if (GET_CODE (operands[1]) == CONST_DOUBLE
1852 && ! FLOAT_MODE_P (mode)
1853 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
1854 && CONST_DOUBLE_LOW (operands[1]) >= 0)
1855 || (CONST_DOUBLE_HIGH (operands[1]) == -1
1856 && CONST_DOUBLE_LOW (operands[1]) < 0)))
1857 abort ();
1858
1859 if (! no_new_pseudos && GET_CODE (operands[0]) != REG)
1860 operands[1] = force_reg (mode, operands[1]);
1861
1862 if (mode == SFmode && ! TARGET_POWERPC && TARGET_HARD_FLOAT
1863 && GET_CODE (operands[0]) == MEM)
1864 {
1865 int regnum;
1866
1867 if (reload_in_progress || reload_completed)
1868 regnum = true_regnum (operands[1]);
1869 else if (GET_CODE (operands[1]) == REG)
1870 regnum = REGNO (operands[1]);
1871 else
1872 regnum = -1;
1873
1874 /* If operands[1] is a register, on POWER it may have
1875 double-precision data in it, so truncate it to single
1876 precision. */
1877 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
1878 {
1879 rtx newreg;
1880 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
1881 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
1882 operands[1] = newreg;
1883 }
1884 }
1885
1886 /* Handle the case where reload calls us with an invalid address;
1887 and the case of CONSTANT_P_RTX. */
1888 if (! general_operand (operands[1], mode)
1889 || ! nonimmediate_operand (operands[0], mode)
1890 || GET_CODE (operands[1]) == CONSTANT_P_RTX)
1891 {
1892 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1893 return;
1894 }
1895
1896 /* FIXME: In the long term, this switch statement should go away
1897 and be replaced by a sequence of tests based on things like
1898 mode == Pmode. */
1899 switch (mode)
1900 {
1901 case HImode:
1902 case QImode:
1903 if (CONSTANT_P (operands[1])
1904 && GET_CODE (operands[1]) != CONST_INT)
1905 operands[1] = force_const_mem (mode, operands[1]);
1906 break;
1907
1908 case DFmode:
1909 case SFmode:
1910 if (CONSTANT_P (operands[1])
1911 && ! easy_fp_constant (operands[1], mode))
1912 operands[1] = force_const_mem (mode, operands[1]);
1913 break;
1914
1915 case SImode:
1916 case DImode:
1917 /* Use default pattern for address of ELF small data */
1918 if (TARGET_ELF
1919 && mode == Pmode
1920 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
1921 && (GET_CODE (operands[1]) == SYMBOL_REF
1922 || GET_CODE (operands[1]) == CONST)
1923 && small_data_operand (operands[1], mode))
1924 {
1925 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1926 return;
1927 }
1928
1929 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
1930 && mode == Pmode && mode == SImode
1931 && flag_pic == 1 && got_operand (operands[1], mode))
1932 {
1933 emit_insn (gen_movsi_got (operands[0], operands[1]));
1934 return;
1935 }
1936
1937 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
1938 && TARGET_NO_TOC && ! flag_pic
1939 && mode == Pmode
1940 && CONSTANT_P (operands[1])
1941 && GET_CODE (operands[1]) != HIGH
1942 && GET_CODE (operands[1]) != CONST_INT)
1943 {
1944 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
1945
1946 /* If this is a function address on -mcall-aixdesc,
1947 convert it to the address of the descriptor. */
1948 if (DEFAULT_ABI == ABI_AIX
1949 && GET_CODE (operands[1]) == SYMBOL_REF
1950 && XSTR (operands[1], 0)[0] == '.')
1951 {
1952 const char *name = XSTR (operands[1], 0);
1953 rtx new_ref;
1954 while (*name == '.')
1955 name++;
1956 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
1957 CONSTANT_POOL_ADDRESS_P (new_ref)
1958 = CONSTANT_POOL_ADDRESS_P (operands[1]);
1959 SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]);
1960 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
1961 operands[1] = new_ref;
1962 }
1963
1964 if (DEFAULT_ABI == ABI_DARWIN)
1965 {
1966 emit_insn (gen_macho_high (target, operands[1]));
1967 emit_insn (gen_macho_low (operands[0], target, operands[1]));
1968 return;
1969 }
1970
1971 emit_insn (gen_elf_high (target, operands[1]));
1972 emit_insn (gen_elf_low (operands[0], target, operands[1]));
1973 return;
1974 }
1975
1976 /* If this is a SYMBOL_REF that refers to a constant pool entry,
1977 and we have put it in the TOC, we just need to make a TOC-relative
1978 reference to it. */
1979 if (TARGET_TOC
1980 && GET_CODE (operands[1]) == SYMBOL_REF
1981 && CONSTANT_POOL_EXPR_P (operands[1])
1982 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
1983 get_pool_mode (operands[1])))
1984 {
1985 operands[1] = create_TOC_reference (operands[1]);
1986 }
1987 else if (mode == Pmode
1988 && CONSTANT_P (operands[1])
1989 && ((GET_CODE (operands[1]) != CONST_INT
1990 && ! easy_fp_constant (operands[1], mode))
1991 || (GET_CODE (operands[1]) == CONST_INT
1992 && num_insns_constant (operands[1], mode) > 2)
1993 || (GET_CODE (operands[0]) == REG
1994 && FP_REGNO_P (REGNO (operands[0]))))
1995 && GET_CODE (operands[1]) != HIGH
1996 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])
1997 && ! TOC_RELATIVE_EXPR_P (operands[1]))
1998 {
1999 /* Emit a USE operation so that the constant isn't deleted if
2000 expensive optimizations are turned on because nobody
2001 references it. This should only be done for operands that
2002 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
2003 This should not be done for operands that contain LABEL_REFs.
2004 For now, we just handle the obvious case. */
2005 if (GET_CODE (operands[1]) != LABEL_REF)
2006 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
2007
2008 /* Darwin uses a special PIC legitimizer. */
2009 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
2010 {
2011 #if TARGET_MACHO
2012 rtx temp_reg = ((reload_in_progress || reload_completed)
2013 ? operands[0] : NULL);
2014
2015 operands[1] =
2016 rs6000_machopic_legitimize_pic_address (operands[1], mode,
2017 temp_reg);
2018 #endif
2019 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2020 return;
2021 }
2022
2023 /* If we are to limit the number of things we put in the TOC and
2024 this is a symbol plus a constant we can add in one insn,
2025 just put the symbol in the TOC and add the constant. Don't do
2026 this if reload is in progress. */
2027 if (GET_CODE (operands[1]) == CONST
2028 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
2029 && GET_CODE (XEXP (operands[1], 0)) == PLUS
2030 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
2031 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
2032 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
2033 && ! side_effects_p (operands[0]))
2034 {
2035 rtx sym = force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
2036 rtx other = XEXP (XEXP (operands[1], 0), 1);
2037
2038 sym = force_reg (mode, sym);
2039 if (mode == SImode)
2040 emit_insn (gen_addsi3 (operands[0], sym, other));
2041 else
2042 emit_insn (gen_adddi3 (operands[0], sym, other));
2043 return;
2044 }
2045
2046 operands[1] = force_const_mem (mode, operands[1]);
2047
2048 if (TARGET_TOC
2049 && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0))
2050 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
2051 get_pool_constant (XEXP (operands[1], 0)),
2052 get_pool_mode (XEXP (operands[1], 0))))
2053 {
2054 operands[1]
2055 = gen_rtx_MEM (mode,
2056 create_TOC_reference (XEXP (operands[1], 0)));
2057 set_mem_alias_set (operands[1], get_TOC_alias_set ());
2058 RTX_UNCHANGING_P (operands[1]) = 1;
2059 }
2060 }
2061 break;
2062
2063 case TImode:
2064 if (GET_CODE (operands[0]) == MEM
2065 && GET_CODE (XEXP (operands[0], 0)) != REG
2066 && ! reload_in_progress)
2067 operands[0]
2068 = replace_equiv_address (operands[0],
2069 copy_addr_to_reg (XEXP (operands[0], 0)));
2070
2071 if (GET_CODE (operands[1]) == MEM
2072 && GET_CODE (XEXP (operands[1], 0)) != REG
2073 && ! reload_in_progress)
2074 operands[1]
2075 = replace_equiv_address (operands[1],
2076 copy_addr_to_reg (XEXP (operands[1], 0)));
2077 break;
2078
2079 default:
2080 abort ();
2081 }
2082
2083 /* Above, we may have called force_const_mem which may have returned
2084 an invalid address. If we can, fix this up; otherwise, reload will
2085 have to deal with it. */
2086 if (GET_CODE (operands[1]) == MEM
2087 && ! memory_address_p (mode, XEXP (operands[1], 0))
2088 && ! reload_in_progress)
2089 operands[1] = adjust_address (operands[1], mode, 0);
2090
2091 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2092 return;
2093 }
2094 \f
2095 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2096 for a call to a function whose data type is FNTYPE.
2097 For a library call, FNTYPE is 0.
2098
2099 For incoming args we set the number of arguments in the prototype large
2100 so we never return a PARALLEL. */
2101
2102 void
2103 init_cumulative_args (cum, fntype, libname, incoming)
2104 CUMULATIVE_ARGS *cum;
2105 tree fntype;
2106 rtx libname ATTRIBUTE_UNUSED;
2107 int incoming;
2108 {
2109 static CUMULATIVE_ARGS zero_cumulative;
2110
2111 *cum = zero_cumulative;
2112 cum->words = 0;
2113 cum->fregno = FP_ARG_MIN_REG;
2114 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
2115 cum->call_cookie = CALL_NORMAL;
2116 cum->sysv_gregno = GP_ARG_MIN_REG;
2117
2118 if (incoming)
2119 cum->nargs_prototype = 1000; /* don't return a PARALLEL */
2120
2121 else if (cum->prototype)
2122 cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1
2123 + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
2124 || RETURN_IN_MEMORY (TREE_TYPE (fntype))));
2125
2126 else
2127 cum->nargs_prototype = 0;
2128
2129 cum->orig_nargs = cum->nargs_prototype;
2130
2131 /* Check for longcall's */
2132 if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)))
2133 cum->call_cookie = CALL_LONG;
2134
2135 if (TARGET_DEBUG_ARG)
2136 {
2137 fprintf (stderr, "\ninit_cumulative_args:");
2138 if (fntype)
2139 {
2140 tree ret_type = TREE_TYPE (fntype);
2141 fprintf (stderr, " ret code = %s,",
2142 tree_code_name[ (int)TREE_CODE (ret_type) ]);
2143 }
2144
2145 if (cum->call_cookie & CALL_LONG)
2146 fprintf (stderr, " longcall,");
2147
2148 fprintf (stderr, " proto = %d, nargs = %d\n",
2149 cum->prototype, cum->nargs_prototype);
2150 }
2151 }
2152 \f
2153 /* If defined, a C expression which determines whether, and in which
2154 direction, to pad out an argument with extra space. The value
2155 should be of type `enum direction': either `upward' to pad above
2156 the argument, `downward' to pad below, or `none' to inhibit
2157 padding.
2158
2159 For the AIX ABI structs are always stored left shifted in their
2160 argument slot. */
2161
2162 enum direction
2163 function_arg_padding (mode, type)
2164 enum machine_mode mode;
2165 tree type;
2166 {
2167 if (type != 0 && AGGREGATE_TYPE_P (type))
2168 return upward;
2169
2170 /* This is the default definition. */
2171 return (! BYTES_BIG_ENDIAN
2172 ? upward
2173 : ((mode == BLKmode
2174 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
2175 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
2176 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
2177 ? downward : upward));
2178 }
2179
2180 /* If defined, a C expression that gives the alignment boundary, in bits,
2181 of an argument with the specified mode and type. If it is not defined,
2182 PARM_BOUNDARY is used for all arguments.
2183
2184 V.4 wants long longs to be double word aligned. */
2185
2186 int
2187 function_arg_boundary (mode, type)
2188 enum machine_mode mode;
2189 tree type ATTRIBUTE_UNUSED;
2190 {
2191 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
2192 && (mode == DImode || mode == DFmode))
2193 return 64;
2194 else
2195 return PARM_BOUNDARY;
2196 }
2197 \f
2198 /* Update the data in CUM to advance over an argument
2199 of mode MODE and data type TYPE.
2200 (TYPE is null for libcalls where that information may not be available.) */
2201
2202 void
2203 function_arg_advance (cum, mode, type, named)
2204 CUMULATIVE_ARGS *cum;
2205 enum machine_mode mode;
2206 tree type;
2207 int named;
2208 {
2209 cum->nargs_prototype--;
2210
2211 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
2212 {
2213 if (TARGET_HARD_FLOAT
2214 && (mode == SFmode || mode == DFmode))
2215 {
2216 if (cum->fregno <= FP_ARG_V4_MAX_REG)
2217 cum->fregno++;
2218 else
2219 {
2220 if (mode == DFmode)
2221 cum->words += cum->words & 1;
2222 cum->words += RS6000_ARG_SIZE (mode, type);
2223 }
2224 }
2225 else
2226 {
2227 int n_words;
2228 int gregno = cum->sysv_gregno;
2229
2230 /* Aggregates and IEEE quad get passed by reference. */
2231 if ((type && AGGREGATE_TYPE_P (type))
2232 || mode == TFmode)
2233 n_words = 1;
2234 else
2235 n_words = RS6000_ARG_SIZE (mode, type);
2236
2237 /* Long long is put in odd registers. */
2238 if (n_words == 2 && (gregno & 1) == 0)
2239 gregno += 1;
2240
2241 /* Long long is not split between registers and stack. */
2242 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
2243 {
2244 /* Long long is aligned on the stack. */
2245 if (n_words == 2)
2246 cum->words += cum->words & 1;
2247 cum->words += n_words;
2248 }
2249
2250 /* Note: continuing to accumulate gregno past when we've started
2251 spilling to the stack indicates the fact that we've started
2252 spilling to the stack to expand_builtin_saveregs. */
2253 cum->sysv_gregno = gregno + n_words;
2254 }
2255
2256 if (TARGET_DEBUG_ARG)
2257 {
2258 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
2259 cum->words, cum->fregno);
2260 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
2261 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
2262 fprintf (stderr, "mode = %4s, named = %d\n",
2263 GET_MODE_NAME (mode), named);
2264 }
2265 }
2266 else
2267 {
2268 int align = (TARGET_32BIT && (cum->words & 1) != 0
2269 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
2270 cum->words += align + RS6000_ARG_SIZE (mode, type);
2271
2272 if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT)
2273 cum->fregno++;
2274
2275 if (TARGET_DEBUG_ARG)
2276 {
2277 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
2278 cum->words, cum->fregno);
2279 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
2280 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
2281 fprintf (stderr, "named = %d, align = %d\n", named, align);
2282 }
2283 }
2284 }
2285 \f
2286 /* Determine where to put an argument to a function.
2287 Value is zero to push the argument on the stack,
2288 or a hard register in which to store the argument.
2289
2290 MODE is the argument's machine mode.
2291 TYPE is the data type of the argument (as a tree).
2292 This is null for libcalls where that information may
2293 not be available.
2294 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2295 the preceding args and about the function being called.
2296 NAMED is nonzero if this argument is a named parameter
2297 (otherwise it is an extra parameter matching an ellipsis).
2298
2299 On RS/6000 the first eight words of non-FP are normally in registers
2300 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
2301 Under V.4, the first 8 FP args are in registers.
2302
2303 If this is floating-point and no prototype is specified, we use
2304 both an FP and integer register (or possibly FP reg and stack). Library
2305 functions (when TYPE is zero) always have the proper types for args,
2306 so we can pass the FP value just in one register. emit_library_function
2307 doesn't support PARALLEL anyway. */
2308
2309 struct rtx_def *
2310 function_arg (cum, mode, type, named)
2311 CUMULATIVE_ARGS *cum;
2312 enum machine_mode mode;
2313 tree type;
2314 int named ATTRIBUTE_UNUSED;
2315 {
2316 enum rs6000_abi abi = DEFAULT_ABI;
2317
2318 /* Return a marker to indicate whether CR1 needs to set or clear the bit
2319 that V.4 uses to say fp args were passed in registers. Assume that we
2320 don't need the marker for software floating point, or compiler generated
2321 library calls. */
2322 if (mode == VOIDmode)
2323 {
2324 if ((abi == ABI_V4 || abi == ABI_SOLARIS)
2325 && TARGET_HARD_FLOAT
2326 && cum->nargs_prototype < 0
2327 && type && (cum->prototype || TARGET_NO_PROTOTYPE))
2328 {
2329 return GEN_INT (cum->call_cookie
2330 | ((cum->fregno == FP_ARG_MIN_REG)
2331 ? CALL_V4_SET_FP_ARGS
2332 : CALL_V4_CLEAR_FP_ARGS));
2333 }
2334
2335 return GEN_INT (cum->call_cookie);
2336 }
2337
2338 if (abi == ABI_V4 || abi == ABI_SOLARIS)
2339 {
2340 if (TARGET_HARD_FLOAT
2341 && (mode == SFmode || mode == DFmode))
2342 {
2343 if (cum->fregno <= FP_ARG_V4_MAX_REG)
2344 return gen_rtx_REG (mode, cum->fregno);
2345 else
2346 return NULL;
2347 }
2348 else
2349 {
2350 int n_words;
2351 int gregno = cum->sysv_gregno;
2352
2353 /* Aggregates and IEEE quad get passed by reference. */
2354 if ((type && AGGREGATE_TYPE_P (type))
2355 || mode == TFmode)
2356 n_words = 1;
2357 else
2358 n_words = RS6000_ARG_SIZE (mode, type);
2359
2360 /* Long long is put in odd registers. */
2361 if (n_words == 2 && (gregno & 1) == 0)
2362 gregno += 1;
2363
2364 /* Long long is not split between registers and stack. */
2365 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
2366 return gen_rtx_REG (mode, gregno);
2367 else
2368 return NULL;
2369 }
2370 }
2371 else
2372 {
2373 int align = (TARGET_32BIT && (cum->words & 1) != 0
2374 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
2375 int align_words = cum->words + align;
2376
2377 if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
2378 return NULL_RTX;
2379
2380 if (USE_FP_FOR_ARG_P (*cum, mode, type))
2381 {
2382 if (! type
2383 || ((cum->nargs_prototype > 0)
2384 /* IBM AIX extended its linkage convention definition always
2385 to require FP args after register save area hole on the
2386 stack. */
2387 && (DEFAULT_ABI != ABI_AIX
2388 || ! TARGET_XL_CALL
2389 || (align_words < GP_ARG_NUM_REG))))
2390 return gen_rtx_REG (mode, cum->fregno);
2391
2392 return gen_rtx_PARALLEL (mode,
2393 gen_rtvec (2,
2394 gen_rtx_EXPR_LIST (VOIDmode,
2395 ((align_words >= GP_ARG_NUM_REG)
2396 ? NULL_RTX
2397 : (align_words
2398 + RS6000_ARG_SIZE (mode, type)
2399 > GP_ARG_NUM_REG
2400 /* If this is partially on the stack, then
2401 we only include the portion actually
2402 in registers here. */
2403 ? gen_rtx_REG (SImode,
2404 GP_ARG_MIN_REG + align_words)
2405 : gen_rtx_REG (mode,
2406 GP_ARG_MIN_REG + align_words))),
2407 const0_rtx),
2408 gen_rtx_EXPR_LIST (VOIDmode,
2409 gen_rtx_REG (mode, cum->fregno),
2410 const0_rtx)));
2411 }
2412 else if (align_words < GP_ARG_NUM_REG)
2413 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
2414 else
2415 return NULL_RTX;
2416 }
2417 }
2418 \f
2419 /* For an arg passed partly in registers and partly in memory,
2420 this is the number of registers used.
2421 For args passed entirely in registers or entirely in memory, zero. */
2422
2423 int
2424 function_arg_partial_nregs (cum, mode, type, named)
2425 CUMULATIVE_ARGS *cum;
2426 enum machine_mode mode;
2427 tree type;
2428 int named ATTRIBUTE_UNUSED;
2429 {
2430 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
2431 return 0;
2432
2433 if (USE_FP_FOR_ARG_P (*cum, mode, type))
2434 {
2435 if (cum->nargs_prototype >= 0)
2436 return 0;
2437 }
2438
2439 if (cum->words < GP_ARG_NUM_REG
2440 && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type)))
2441 {
2442 int ret = GP_ARG_NUM_REG - cum->words;
2443 if (ret && TARGET_DEBUG_ARG)
2444 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
2445
2446 return ret;
2447 }
2448
2449 return 0;
2450 }
2451 \f
2452 /* A C expression that indicates when an argument must be passed by
2453 reference. If nonzero for an argument, a copy of that argument is
2454 made in memory and a pointer to the argument is passed instead of
2455 the argument itself. The pointer is passed in whatever way is
2456 appropriate for passing a pointer to that type.
2457
2458 Under V.4, structures and unions are passed by reference. */
2459
2460 int
2461 function_arg_pass_by_reference (cum, mode, type, named)
2462 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
2463 enum machine_mode mode ATTRIBUTE_UNUSED;
2464 tree type;
2465 int named ATTRIBUTE_UNUSED;
2466 {
2467 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
2468 && ((type && AGGREGATE_TYPE_P (type))
2469 || mode == TFmode))
2470 {
2471 if (TARGET_DEBUG_ARG)
2472 fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
2473
2474 return 1;
2475 }
2476
2477 return 0;
2478 }
2479 \f
2480 /* Perform any needed actions needed for a function that is receiving a
2481 variable number of arguments.
2482
2483 CUM is as above.
2484
2485 MODE and TYPE are the mode and type of the current parameter.
2486
2487 PRETEND_SIZE is a variable that should be set to the amount of stack
2488 that must be pushed by the prolog to pretend that our caller pushed
2489 it.
2490
2491 Normally, this macro will push all remaining incoming registers on the
2492 stack and set PRETEND_SIZE to the length of the registers pushed. */
2493
2494 void
2495 setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
2496 CUMULATIVE_ARGS *cum;
2497 enum machine_mode mode;
2498 tree type;
2499 int *pretend_size;
2500 int no_rtl;
2501
2502 {
2503 CUMULATIVE_ARGS next_cum;
2504 int reg_size = TARGET_32BIT ? 4 : 8;
2505 rtx save_area = NULL_RTX, mem;
2506 int first_reg_offset, set;
2507 tree fntype;
2508 int stdarg_p;
2509
2510 fntype = TREE_TYPE (current_function_decl);
2511 stdarg_p = (TYPE_ARG_TYPES (fntype) != 0
2512 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
2513 != void_type_node));
2514
2515 /* For varargs, we do not want to skip the dummy va_dcl argument.
2516 For stdargs, we do want to skip the last named argument. */
2517 next_cum = *cum;
2518 if (stdarg_p)
2519 function_arg_advance (&next_cum, mode, type, 1);
2520
2521 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
2522 {
2523 /* Indicate to allocate space on the stack for varargs save area. */
2524 /* ??? Does this really have to be located at a magic spot on the
2525 stack, or can we allocate this with assign_stack_local instead. */
2526 cfun->machine->sysv_varargs_p = 1;
2527 if (! no_rtl)
2528 save_area = plus_constant (virtual_stack_vars_rtx,
2529 - RS6000_VARARGS_SIZE);
2530
2531 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
2532 }
2533 else
2534 {
2535 first_reg_offset = next_cum.words;
2536 save_area = virtual_incoming_args_rtx;
2537 cfun->machine->sysv_varargs_p = 0;
2538
2539 if (MUST_PASS_IN_STACK (mode, type))
2540 first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type);
2541 }
2542
2543 set = get_varargs_alias_set ();
2544 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
2545 {
2546 mem = gen_rtx_MEM (BLKmode,
2547 plus_constant (save_area,
2548 first_reg_offset * reg_size)),
2549 set_mem_alias_set (mem, set);
2550
2551 move_block_from_reg
2552 (GP_ARG_MIN_REG + first_reg_offset, mem,
2553 GP_ARG_NUM_REG - first_reg_offset,
2554 (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD);
2555
2556 /* ??? Does ABI_V4 need this at all? */
2557 *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD;
2558 }
2559
2560 /* Save FP registers if needed. */
2561 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
2562 && TARGET_HARD_FLOAT && ! no_rtl
2563 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
2564 {
2565 int fregno = next_cum.fregno;
2566 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
2567 rtx lab = gen_label_rtx ();
2568 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
2569
2570 emit_jump_insn (gen_rtx_SET (VOIDmode,
2571 pc_rtx,
2572 gen_rtx_IF_THEN_ELSE (VOIDmode,
2573 gen_rtx_NE (VOIDmode, cr1,
2574 const0_rtx),
2575 gen_rtx_LABEL_REF (VOIDmode, lab),
2576 pc_rtx)));
2577
2578 while (fregno <= FP_ARG_V4_MAX_REG)
2579 {
2580 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
2581 set_mem_alias_set (mem, set);
2582 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
2583 fregno++;
2584 off += 8;
2585 }
2586
2587 emit_label (lab);
2588 }
2589 }
2590
2591 /* Create the va_list data type. */
2592
2593 tree
2594 rs6000_build_va_list ()
2595 {
2596 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
2597
2598 /* For AIX, prefer 'char *' because that's what the system
2599 header files like. */
2600 if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
2601 return build_pointer_type (char_type_node);
2602
2603 record = make_lang_type (RECORD_TYPE);
2604 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
2605
2606 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
2607 unsigned_char_type_node);
2608 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
2609 unsigned_char_type_node);
2610 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
2611 ptr_type_node);
2612 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
2613 ptr_type_node);
2614
2615 DECL_FIELD_CONTEXT (f_gpr) = record;
2616 DECL_FIELD_CONTEXT (f_fpr) = record;
2617 DECL_FIELD_CONTEXT (f_ovf) = record;
2618 DECL_FIELD_CONTEXT (f_sav) = record;
2619
2620 TREE_CHAIN (record) = type_decl;
2621 TYPE_NAME (record) = type_decl;
2622 TYPE_FIELDS (record) = f_gpr;
2623 TREE_CHAIN (f_gpr) = f_fpr;
2624 TREE_CHAIN (f_fpr) = f_ovf;
2625 TREE_CHAIN (f_ovf) = f_sav;
2626
2627 layout_type (record);
2628
2629 /* The correct type is an array type of one element. */
2630 return build_array_type (record, build_index_type (size_zero_node));
2631 }
2632
2633 /* Implement va_start. */
2634
2635 void
2636 rs6000_va_start (stdarg_p, valist, nextarg)
2637 int stdarg_p;
2638 tree valist;
2639 rtx nextarg;
2640 {
2641 HOST_WIDE_INT words, n_gpr, n_fpr;
2642 tree f_gpr, f_fpr, f_ovf, f_sav;
2643 tree gpr, fpr, ovf, sav, t;
2644
2645 /* Only SVR4 needs something special. */
2646 if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
2647 {
2648 std_expand_builtin_va_start (stdarg_p, valist, nextarg);
2649 return;
2650 }
2651
2652 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2653 f_fpr = TREE_CHAIN (f_gpr);
2654 f_ovf = TREE_CHAIN (f_fpr);
2655 f_sav = TREE_CHAIN (f_ovf);
2656
2657 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2658 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
2659 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
2660 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
2661 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
2662
2663 /* Count number of gp and fp argument registers used. */
2664 words = current_function_args_info.words;
2665 n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
2666 n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
2667
2668 if (TARGET_DEBUG_ARG)
2669 {
2670 fputs ("va_start: words = ", stderr);
2671 fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, words);
2672 fputs (", n_gpr = ", stderr);
2673 fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_gpr);
2674 fputs (", n_fpr = ", stderr);
2675 fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_fpr);
2676 putc ('\n', stderr);
2677 }
2678
2679 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0));
2680 TREE_SIDE_EFFECTS (t) = 1;
2681 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2682
2683 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0));
2684 TREE_SIDE_EFFECTS (t) = 1;
2685 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2686
2687 /* Find the overflow area. */
2688 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
2689 if (words != 0)
2690 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
2691 build_int_2 (words * UNITS_PER_WORD, 0));
2692 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
2693 TREE_SIDE_EFFECTS (t) = 1;
2694 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2695
2696 /* Find the register save area. */
2697 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
2698 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
2699 build_int_2 (-RS6000_VARARGS_SIZE, -1));
2700 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
2701 TREE_SIDE_EFFECTS (t) = 1;
2702 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2703 }
2704
2705 /* Implement va_arg. */
2706
2707 rtx
2708 rs6000_va_arg (valist, type)
2709 tree valist, type;
2710 {
2711 tree f_gpr, f_fpr, f_ovf, f_sav;
2712 tree gpr, fpr, ovf, sav, reg, t, u;
2713 int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale;
2714 rtx lab_false, lab_over, addr_rtx, r;
2715
2716 /* For AIX, the rule is that structures are passed left-aligned in
2717 their stack slot. However, GCC does not presently do this:
2718 structures which are the same size as integer types are passed
2719 right-aligned, as if they were in fact integers. This only
2720 matters for structures of size 1 or 2, or 4 when TARGET_64BIT. */
2721 if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
2722 {
2723 HOST_WIDE_INT align, rounded_size;
2724 enum machine_mode mode;
2725 tree addr_tree;
2726
2727 /* Compute the rounded size of the type. */
2728 align = PARM_BOUNDARY / BITS_PER_UNIT;
2729 rounded_size = (((int_size_in_bytes (type) + align - 1) / align)
2730 * align);
2731
2732 addr_tree = valist;
2733
2734 mode = TYPE_MODE (type);
2735 if (mode != BLKmode)
2736 {
2737 HOST_WIDE_INT adj;
2738 adj = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_UNIT;
2739 if (rounded_size > align)
2740 adj = rounded_size;
2741
2742 addr_tree = build (PLUS_EXPR, TREE_TYPE (addr_tree), addr_tree,
2743 build_int_2 (rounded_size - adj, 0));
2744 }
2745
2746 addr_rtx = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL);
2747 addr_rtx = copy_to_reg (addr_rtx);
2748
2749 /* Compute new value for AP. */
2750 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2751 build (PLUS_EXPR, TREE_TYPE (valist), valist,
2752 build_int_2 (rounded_size, 0)));
2753 TREE_SIDE_EFFECTS (t) = 1;
2754 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2755
2756 return addr_rtx;
2757 }
2758
2759 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2760 f_fpr = TREE_CHAIN (f_gpr);
2761 f_ovf = TREE_CHAIN (f_fpr);
2762 f_sav = TREE_CHAIN (f_ovf);
2763
2764 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2765 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
2766 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
2767 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
2768 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
2769
2770 size = int_size_in_bytes (type);
2771 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2772
2773 if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode)
2774 {
2775 /* Aggregates and long doubles are passed by reference. */
2776 indirect_p = 1;
2777 reg = gpr;
2778 n_reg = 1;
2779 sav_ofs = 0;
2780 sav_scale = 4;
2781 size = rsize = UNITS_PER_WORD;
2782 }
2783 else if (FLOAT_TYPE_P (type) && ! TARGET_SOFT_FLOAT)
2784 {
2785 /* FP args go in FP registers, if present. */
2786 indirect_p = 0;
2787 reg = fpr;
2788 n_reg = 1;
2789 sav_ofs = 8*4;
2790 sav_scale = 8;
2791 }
2792 else
2793 {
2794 /* Otherwise into GP registers. */
2795 indirect_p = 0;
2796 reg = gpr;
2797 n_reg = rsize;
2798 sav_ofs = 0;
2799 sav_scale = 4;
2800 }
2801
2802 /*
2803 * Pull the value out of the saved registers ...
2804 */
2805
2806 lab_false = gen_label_rtx ();
2807 lab_over = gen_label_rtx ();
2808 addr_rtx = gen_reg_rtx (Pmode);
2809
2810 emit_cmp_and_jump_insns (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL),
2811 GEN_INT (8 - n_reg + 1),
2812 GE, const1_rtx, QImode, 1, 1, lab_false);
2813
2814 /* Long long is aligned in the registers. */
2815 if (n_reg > 1)
2816 {
2817 u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg,
2818 build_int_2 (n_reg - 1, 0));
2819 u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u);
2820 u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u);
2821 TREE_SIDE_EFFECTS (u) = 1;
2822 expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
2823 }
2824
2825 if (sav_ofs)
2826 t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0));
2827 else
2828 t = sav;
2829
2830 u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, build_int_2 (n_reg, 0));
2831 TREE_SIDE_EFFECTS (u) = 1;
2832
2833 u = build1 (CONVERT_EXPR, integer_type_node, u);
2834 TREE_SIDE_EFFECTS (u) = 1;
2835
2836 u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0));
2837 TREE_SIDE_EFFECTS (u) = 1;
2838
2839 t = build (PLUS_EXPR, ptr_type_node, t, u);
2840 TREE_SIDE_EFFECTS (t) = 1;
2841
2842 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
2843 if (r != addr_rtx)
2844 emit_move_insn (addr_rtx, r);
2845
2846 emit_jump_insn (gen_jump (lab_over));
2847 emit_barrier ();
2848 emit_label (lab_false);
2849
2850 /*
2851 * ... otherwise out of the overflow area.
2852 */
2853
2854 /* Make sure we don't find reg 7 for the next int arg. */
2855 if (n_reg > 1)
2856 {
2857 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0));
2858 TREE_SIDE_EFFECTS (t) = 1;
2859 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2860 }
2861
2862 /* Care for on-stack alignment if needed. */
2863 if (rsize <= 1)
2864 t = ovf;
2865 else
2866 {
2867 t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (7, 0));
2868 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-8, -1));
2869 }
2870 t = save_expr (t);
2871
2872 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
2873 if (r != addr_rtx)
2874 emit_move_insn (addr_rtx, r);
2875
2876 t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0));
2877 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
2878 TREE_SIDE_EFFECTS (t) = 1;
2879 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2880
2881 emit_label (lab_over);
2882
2883 if (indirect_p)
2884 {
2885 r = gen_rtx_MEM (Pmode, addr_rtx);
2886 set_mem_alias_set (r, get_varargs_alias_set ());
2887 emit_move_insn (addr_rtx, r);
2888 }
2889
2890 return addr_rtx;
2891 }
2892 \f
2893 /* Generate a memory reference for expand_block_move, copying volatile,
2894 and other bits from an original memory reference. */
2895
2896 static rtx
2897 expand_block_move_mem (mode, addr, orig_mem)
2898 enum machine_mode mode;
2899 rtx addr;
2900 rtx orig_mem;
2901 {
2902 rtx mem = gen_rtx_MEM (mode, addr);
2903
2904 MEM_COPY_ATTRIBUTES (mem, orig_mem);
2905 #ifdef MEM_UNALIGNED_P
2906 MEM_UNALIGNED_P (mem) = MEM_UNALIGNED_P (orig_mem);
2907 #endif
2908 return mem;
2909 }
2910
2911 /* Expand a block move operation, and return 1 if successful. Return 0
2912 if we should let the compiler generate normal code.
2913
2914 operands[0] is the destination
2915 operands[1] is the source
2916 operands[2] is the length
2917 operands[3] is the alignment */
2918
2919 #define MAX_MOVE_REG 4
2920
2921 int
2922 expand_block_move (operands)
2923 rtx operands[];
2924 {
2925 rtx orig_dest = operands[0];
2926 rtx orig_src = operands[1];
2927 rtx bytes_rtx = operands[2];
2928 rtx align_rtx = operands[3];
2929 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2930 int align;
2931 int bytes;
2932 int offset;
2933 int num_reg;
2934 int i;
2935 rtx src_reg;
2936 rtx dest_reg;
2937 rtx src_addr;
2938 rtx dest_addr;
2939 rtx tmp_reg;
2940 rtx stores[MAX_MOVE_REG];
2941 int move_bytes;
2942
2943 /* If this is not a fixed size move, just call memcpy */
2944 if (! constp)
2945 return 0;
2946
2947 /* If this is not a fixed size alignment, abort */
2948 if (GET_CODE (align_rtx) != CONST_INT)
2949 abort ();
2950 align = INTVAL (align_rtx);
2951
2952 /* Anything to move? */
2953 bytes = INTVAL (bytes_rtx);
2954 if (bytes <= 0)
2955 return 1;
2956
2957 /* Don't support real large moves. If string instructions are not used,
2958 then don't generate more than 8 loads. */
2959 if (TARGET_STRING)
2960 {
2961 if (bytes > 8*4)
2962 return 0;
2963 }
2964 else if (! STRICT_ALIGNMENT)
2965 {
2966 if (TARGET_POWERPC64 && align >= 4)
2967 {
2968 if (bytes > 8*8)
2969 return 0;
2970 }
2971 else
2972 if (bytes > 8*4)
2973 return 0;
2974 }
2975 else if (bytes > 8*align)
2976 return 0;
2977
2978 /* Move the address into scratch registers. */
2979 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2980 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2981
2982 if (TARGET_STRING) /* string instructions are available */
2983 {
2984 for ( ; bytes > 0; bytes -= move_bytes)
2985 {
2986 if (bytes > 24 /* move up to 32 bytes at a time */
2987 && ! fixed_regs[5]
2988 && ! fixed_regs[6]
2989 && ! fixed_regs[7]
2990 && ! fixed_regs[8]
2991 && ! fixed_regs[9]
2992 && ! fixed_regs[10]
2993 && ! fixed_regs[11]
2994 && ! fixed_regs[12])
2995 {
2996 move_bytes = (bytes > 32) ? 32 : bytes;
2997 emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode,
2998 dest_reg,
2999 orig_dest),
3000 expand_block_move_mem (BLKmode,
3001 src_reg,
3002 orig_src),
3003 GEN_INT ((move_bytes == 32)
3004 ? 0 : move_bytes),
3005 align_rtx));
3006 }
3007 else if (bytes > 16 /* move up to 24 bytes at a time */
3008 && ! fixed_regs[5]
3009 && ! fixed_regs[6]
3010 && ! fixed_regs[7]
3011 && ! fixed_regs[8]
3012 && ! fixed_regs[9]
3013 && ! fixed_regs[10])
3014 {
3015 move_bytes = (bytes > 24) ? 24 : bytes;
3016 emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode,
3017 dest_reg,
3018 orig_dest),
3019 expand_block_move_mem (BLKmode,
3020 src_reg,
3021 orig_src),
3022 GEN_INT (move_bytes),
3023 align_rtx));
3024 }
3025 else if (bytes > 8 /* move up to 16 bytes at a time */
3026 && ! fixed_regs[5]
3027 && ! fixed_regs[6]
3028 && ! fixed_regs[7]
3029 && ! fixed_regs[8])
3030 {
3031 move_bytes = (bytes > 16) ? 16 : bytes;
3032 emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode,
3033 dest_reg,
3034 orig_dest),
3035 expand_block_move_mem (BLKmode,
3036 src_reg,
3037 orig_src),
3038 GEN_INT (move_bytes),
3039 align_rtx));
3040 }
3041 else if (bytes >= 8 && TARGET_POWERPC64
3042 /* 64-bit loads and stores require word-aligned displacements. */
3043 && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
3044 {
3045 move_bytes = 8;
3046 tmp_reg = gen_reg_rtx (DImode);
3047 emit_move_insn (tmp_reg,
3048 expand_block_move_mem (DImode,
3049 src_reg, orig_src));
3050 emit_move_insn (expand_block_move_mem (DImode,
3051 dest_reg, orig_dest),
3052 tmp_reg);
3053 }
3054 else if (bytes > 4)
3055 { /* move up to 8 bytes at a time */
3056 move_bytes = (bytes > 8) ? 8 : bytes;
3057 emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode,
3058 dest_reg,
3059 orig_dest),
3060 expand_block_move_mem (BLKmode,
3061 src_reg,
3062 orig_src),
3063 GEN_INT (move_bytes),
3064 align_rtx));
3065 }
3066 else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT))
3067 { /* move 4 bytes */
3068 move_bytes = 4;
3069 tmp_reg = gen_reg_rtx (SImode);
3070 emit_move_insn (tmp_reg,
3071 expand_block_move_mem (SImode,
3072 src_reg, orig_src));
3073 emit_move_insn (expand_block_move_mem (SImode,
3074 dest_reg, orig_dest),
3075 tmp_reg);
3076 }
3077 else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT))
3078 { /* move 2 bytes */
3079 move_bytes = 2;
3080 tmp_reg = gen_reg_rtx (HImode);
3081 emit_move_insn (tmp_reg,
3082 expand_block_move_mem (HImode,
3083 src_reg, orig_src));
3084 emit_move_insn (expand_block_move_mem (HImode,
3085 dest_reg, orig_dest),
3086 tmp_reg);
3087 }
3088 else if (bytes == 1) /* move 1 byte */
3089 {
3090 move_bytes = 1;
3091 tmp_reg = gen_reg_rtx (QImode);
3092 emit_move_insn (tmp_reg,
3093 expand_block_move_mem (QImode,
3094 src_reg, orig_src));
3095 emit_move_insn (expand_block_move_mem (QImode,
3096 dest_reg, orig_dest),
3097 tmp_reg);
3098 }
3099 else
3100 { /* move up to 4 bytes at a time */
3101 move_bytes = (bytes > 4) ? 4 : bytes;
3102 emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode,
3103 dest_reg,
3104 orig_dest),
3105 expand_block_move_mem (BLKmode,
3106 src_reg,
3107 orig_src),
3108 GEN_INT (move_bytes),
3109 align_rtx));
3110 }
3111
3112 if (bytes > move_bytes)
3113 {
3114 if (! TARGET_POWERPC64)
3115 {
3116 emit_insn (gen_addsi3 (src_reg, src_reg,
3117 GEN_INT (move_bytes)));
3118 emit_insn (gen_addsi3 (dest_reg, dest_reg,
3119 GEN_INT (move_bytes)));
3120 }
3121 else
3122 {
3123 emit_insn (gen_adddi3 (src_reg, src_reg,
3124 GEN_INT (move_bytes)));
3125 emit_insn (gen_adddi3 (dest_reg, dest_reg,
3126 GEN_INT (move_bytes)));
3127 }
3128 }
3129 }
3130 }
3131
3132 else /* string instructions not available */
3133 {
3134 num_reg = offset = 0;
3135 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
3136 {
3137 /* Calculate the correct offset for src/dest */
3138 if (offset == 0)
3139 {
3140 src_addr = src_reg;
3141 dest_addr = dest_reg;
3142 }
3143 else
3144 {
3145 src_addr = plus_constant (src_reg, offset);
3146 dest_addr = plus_constant (dest_reg, offset);
3147 }
3148
3149 /* Generate the appropriate load and store, saving the stores
3150 for later. */
3151 if (bytes >= 8 && TARGET_POWERPC64
3152 /* 64-bit loads and stores require word-aligned displacements. */
3153 && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
3154 {
3155 move_bytes = 8;
3156 tmp_reg = gen_reg_rtx (DImode);
3157 emit_insn (gen_movdi (tmp_reg,
3158 expand_block_move_mem (DImode,
3159 src_addr,
3160 orig_src)));
3161 stores[num_reg++] = gen_movdi (expand_block_move_mem (DImode,
3162 dest_addr,
3163 orig_dest),
3164 tmp_reg);
3165 }
3166 else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT))
3167 {
3168 move_bytes = 4;
3169 tmp_reg = gen_reg_rtx (SImode);
3170 emit_insn (gen_movsi (tmp_reg,
3171 expand_block_move_mem (SImode,
3172 src_addr,
3173 orig_src)));
3174 stores[num_reg++] = gen_movsi (expand_block_move_mem (SImode,
3175 dest_addr,
3176 orig_dest),
3177 tmp_reg);
3178 }
3179 else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT))
3180 {
3181 move_bytes = 2;
3182 tmp_reg = gen_reg_rtx (HImode);
3183 emit_insn (gen_movhi (tmp_reg,
3184 expand_block_move_mem (HImode,
3185 src_addr,
3186 orig_src)));
3187 stores[num_reg++] = gen_movhi (expand_block_move_mem (HImode,
3188 dest_addr,
3189 orig_dest),
3190 tmp_reg);
3191 }
3192 else
3193 {
3194 move_bytes = 1;
3195 tmp_reg = gen_reg_rtx (QImode);
3196 emit_insn (gen_movqi (tmp_reg,
3197 expand_block_move_mem (QImode,
3198 src_addr,
3199 orig_src)));
3200 stores[num_reg++] = gen_movqi (expand_block_move_mem (QImode,
3201 dest_addr,
3202 orig_dest),
3203 tmp_reg);
3204 }
3205
3206 if (num_reg >= MAX_MOVE_REG)
3207 {
3208 for (i = 0; i < num_reg; i++)
3209 emit_insn (stores[i]);
3210 num_reg = 0;
3211 }
3212 }
3213
3214 for (i = 0; i < num_reg; i++)
3215 emit_insn (stores[i]);
3216 }
3217
3218 return 1;
3219 }
3220
3221 \f
3222 /* Return 1 if OP is a load multiple operation. It is known to be a
3223 PARALLEL and the first section will be tested. */
3224
3225 int
3226 load_multiple_operation (op, mode)
3227 rtx op;
3228 enum machine_mode mode ATTRIBUTE_UNUSED;
3229 {
3230 int count = XVECLEN (op, 0);
3231 unsigned int dest_regno;
3232 rtx src_addr;
3233 int i;
3234
3235 /* Perform a quick check so we don't blow up below. */
3236 if (count <= 1
3237 || GET_CODE (XVECEXP (op, 0, 0)) != SET
3238 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
3239 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
3240 return 0;
3241
3242 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
3243 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
3244
3245 for (i = 1; i < count; i++)
3246 {
3247 rtx elt = XVECEXP (op, 0, i);
3248
3249 if (GET_CODE (elt) != SET
3250 || GET_CODE (SET_DEST (elt)) != REG
3251 || GET_MODE (SET_DEST (elt)) != SImode
3252 || REGNO (SET_DEST (elt)) != dest_regno + i
3253 || GET_CODE (SET_SRC (elt)) != MEM
3254 || GET_MODE (SET_SRC (elt)) != SImode
3255 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
3256 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
3257 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
3258 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
3259 return 0;
3260 }
3261
3262 return 1;
3263 }
3264
3265 /* Similar, but tests for store multiple. Here, the second vector element
3266 is a CLOBBER. It will be tested later. */
3267
3268 int
3269 store_multiple_operation (op, mode)
3270 rtx op;
3271 enum machine_mode mode ATTRIBUTE_UNUSED;
3272 {
3273 int count = XVECLEN (op, 0) - 1;
3274 unsigned int src_regno;
3275 rtx dest_addr;
3276 int i;
3277
3278 /* Perform a quick check so we don't blow up below. */
3279 if (count <= 1
3280 || GET_CODE (XVECEXP (op, 0, 0)) != SET
3281 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
3282 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
3283 return 0;
3284
3285 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
3286 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
3287
3288 for (i = 1; i < count; i++)
3289 {
3290 rtx elt = XVECEXP (op, 0, i + 1);
3291
3292 if (GET_CODE (elt) != SET
3293 || GET_CODE (SET_SRC (elt)) != REG
3294 || GET_MODE (SET_SRC (elt)) != SImode
3295 || REGNO (SET_SRC (elt)) != src_regno + i
3296 || GET_CODE (SET_DEST (elt)) != MEM
3297 || GET_MODE (SET_DEST (elt)) != SImode
3298 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
3299 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
3300 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
3301 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
3302 return 0;
3303 }
3304
3305 return 1;
3306 }
3307
3308 /* Return 1 for an PARALLEL suitable for mtcrf. */
3309
3310 int
3311 mtcrf_operation (op, mode)
3312 rtx op;
3313 enum machine_mode mode ATTRIBUTE_UNUSED;
3314 {
3315 int count = XVECLEN (op, 0);
3316 int i;
3317 rtx src_reg;
3318
3319 /* Perform a quick check so we don't blow up below. */
3320 if (count < 1
3321 || GET_CODE (XVECEXP (op, 0, 0)) != SET
3322 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
3323 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
3324 return 0;
3325 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
3326
3327 if (GET_CODE (src_reg) != REG
3328 || GET_MODE (src_reg) != SImode
3329 || ! INT_REGNO_P (REGNO (src_reg)))
3330 return 0;
3331
3332 for (i = 0; i < count; i++)
3333 {
3334 rtx exp = XVECEXP (op, 0, i);
3335 rtx unspec;
3336 int maskval;
3337
3338 if (GET_CODE (exp) != SET
3339 || GET_CODE (SET_DEST (exp)) != REG
3340 || GET_MODE (SET_DEST (exp)) != CCmode
3341 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
3342 return 0;
3343 unspec = SET_SRC (exp);
3344 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
3345
3346 if (GET_CODE (unspec) != UNSPEC
3347 || XINT (unspec, 1) != 20
3348 || XVECLEN (unspec, 0) != 2
3349 || XVECEXP (unspec, 0, 0) != src_reg
3350 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
3351 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
3352 return 0;
3353 }
3354 return 1;
3355 }
3356
3357 /* Return 1 for an PARALLEL suitable for lmw. */
3358
3359 int
3360 lmw_operation (op, mode)
3361 rtx op;
3362 enum machine_mode mode ATTRIBUTE_UNUSED;
3363 {
3364 int count = XVECLEN (op, 0);
3365 unsigned int dest_regno;
3366 rtx src_addr;
3367 unsigned int base_regno;
3368 HOST_WIDE_INT offset;
3369 int i;
3370
3371 /* Perform a quick check so we don't blow up below. */
3372 if (count <= 1
3373 || GET_CODE (XVECEXP (op, 0, 0)) != SET
3374 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
3375 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
3376 return 0;
3377
3378 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
3379 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
3380
3381 if (dest_regno > 31
3382 || count != 32 - (int) dest_regno)
3383 return 0;
3384
3385 if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr, 0))
3386 {
3387 offset = 0;
3388 base_regno = REGNO (src_addr);
3389 if (base_regno == 0)
3390 return 0;
3391 }
3392 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, src_addr, 0))
3393 {
3394 offset = INTVAL (XEXP (src_addr, 1));
3395 base_regno = REGNO (XEXP (src_addr, 0));
3396 }
3397 else
3398 return 0;
3399
3400 for (i = 0; i < count; i++)
3401 {
3402 rtx elt = XVECEXP (op, 0, i);
3403 rtx newaddr;
3404 rtx addr_reg;
3405 HOST_WIDE_INT newoffset;
3406
3407 if (GET_CODE (elt) != SET
3408 || GET_CODE (SET_DEST (elt)) != REG
3409 || GET_MODE (SET_DEST (elt)) != SImode
3410 || REGNO (SET_DEST (elt)) != dest_regno + i
3411 || GET_CODE (SET_SRC (elt)) != MEM
3412 || GET_MODE (SET_SRC (elt)) != SImode)
3413 return 0;
3414 newaddr = XEXP (SET_SRC (elt), 0);
3415 if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0))
3416 {
3417 newoffset = 0;
3418 addr_reg = newaddr;
3419 }
3420 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0))
3421 {
3422 addr_reg = XEXP (newaddr, 0);
3423 newoffset = INTVAL (XEXP (newaddr, 1));
3424 }
3425 else
3426 return 0;
3427 if (REGNO (addr_reg) != base_regno
3428 || newoffset != offset + 4 * i)
3429 return 0;
3430 }
3431
3432 return 1;
3433 }
3434
3435 /* Return 1 for an PARALLEL suitable for stmw. */
3436
3437 int
3438 stmw_operation (op, mode)
3439 rtx op;
3440 enum machine_mode mode ATTRIBUTE_UNUSED;
3441 {
3442 int count = XVECLEN (op, 0);
3443 unsigned int src_regno;
3444 rtx dest_addr;
3445 unsigned int base_regno;
3446 HOST_WIDE_INT offset;
3447 int i;
3448
3449 /* Perform a quick check so we don't blow up below. */
3450 if (count <= 1
3451 || GET_CODE (XVECEXP (op, 0, 0)) != SET
3452 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
3453 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
3454 return 0;
3455
3456 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
3457 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
3458
3459 if (src_regno > 31
3460 || count != 32 - (int) src_regno)
3461 return 0;
3462
3463 if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr, 0))
3464 {
3465 offset = 0;
3466 base_regno = REGNO (dest_addr);
3467 if (base_regno == 0)
3468 return 0;
3469 }
3470 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, dest_addr, 0))
3471 {
3472 offset = INTVAL (XEXP (dest_addr, 1));
3473 base_regno = REGNO (XEXP (dest_addr, 0));
3474 }
3475 else
3476 return 0;
3477
3478 for (i = 0; i < count; i++)
3479 {
3480 rtx elt = XVECEXP (op, 0, i);
3481 rtx newaddr;
3482 rtx addr_reg;
3483 HOST_WIDE_INT newoffset;
3484
3485 if (GET_CODE (elt) != SET
3486 || GET_CODE (SET_SRC (elt)) != REG
3487 || GET_MODE (SET_SRC (elt)) != SImode
3488 || REGNO (SET_SRC (elt)) != src_regno + i
3489 || GET_CODE (SET_DEST (elt)) != MEM
3490 || GET_MODE (SET_DEST (elt)) != SImode)
3491 return 0;
3492 newaddr = XEXP (SET_DEST (elt), 0);
3493 if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0))
3494 {
3495 newoffset = 0;
3496 addr_reg = newaddr;
3497 }
3498 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0))
3499 {
3500 addr_reg = XEXP (newaddr, 0);
3501 newoffset = INTVAL (XEXP (newaddr, 1));
3502 }
3503 else
3504 return 0;
3505 if (REGNO (addr_reg) != base_regno
3506 || newoffset != offset + 4 * i)
3507 return 0;
3508 }
3509
3510 return 1;
3511 }
3512 \f
3513
3514 /* A validation routine: say whether CODE, a condition code,
3515 and MODE match. The other alternatives either don't make
3516 sense or should never be generated. */
3517 static void
3518 validate_condition_mode (code, mode)
3519 enum rtx_code code;
3520 enum machine_mode mode;
3521 {
3522 if (GET_RTX_CLASS (code) != '<'
3523 || GET_MODE_CLASS (mode) != MODE_CC)
3524 abort ();
3525
3526 /* These don't make sense. */
3527 if ((code == GT || code == LT || code == GE || code == LE)
3528 && mode == CCUNSmode)
3529 abort ();
3530
3531 if ((code == GTU || code == LTU || code == GEU || code == LEU)
3532 && mode != CCUNSmode)
3533 abort ();
3534
3535 if (mode != CCFPmode
3536 && (code == ORDERED || code == UNORDERED
3537 || code == UNEQ || code == LTGT
3538 || code == UNGT || code == UNLT
3539 || code == UNGE || code == UNLE))
3540 abort();
3541
3542 /* These should never be generated except for
3543 flag_unsafe_math_optimizations. */
3544 if (mode == CCFPmode
3545 && ! flag_unsafe_math_optimizations
3546 && (code == LE || code == GE
3547 || code == UNEQ || code == LTGT
3548 || code == UNGT || code == UNLT))
3549 abort ();
3550
3551 /* These are invalid; the information is not there. */
3552 if (mode == CCEQmode
3553 && code != EQ && code != NE)
3554 abort ();
3555 }
3556
3557 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
3558 We only check the opcode against the mode of the CC value here. */
3559
3560 int
3561 branch_comparison_operator (op, mode)
3562 register rtx op;
3563 enum machine_mode mode ATTRIBUTE_UNUSED;
3564 {
3565 enum rtx_code code = GET_CODE (op);
3566 enum machine_mode cc_mode;
3567
3568 if (GET_RTX_CLASS (code) != '<')
3569 return 0;
3570
3571 cc_mode = GET_MODE (XEXP (op, 0));
3572 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
3573 return 0;
3574
3575 validate_condition_mode (code, cc_mode);
3576
3577 return 1;
3578 }
3579
3580 /* Return 1 if OP is a comparison operation that is valid for a branch
3581 insn and which is true if the corresponding bit in the CC register
3582 is set. */
3583
3584 int
3585 branch_positive_comparison_operator (op, mode)
3586 register rtx op;
3587 enum machine_mode mode;
3588 {
3589 enum rtx_code code;
3590
3591 if (! branch_comparison_operator (op, mode))
3592 return 0;
3593
3594 code = GET_CODE (op);
3595 return (code == EQ || code == LT || code == GT
3596 || code == LTU || code == GTU
3597 || code == UNORDERED);
3598 }
3599
3600
3601 /* Return 1 if OP is a comparison operation that is valid for an scc insn.
3602 We check the opcode against the mode of the CC value and disallow EQ or
3603 NE comparisons for integers. */
3604
3605 int
3606 scc_comparison_operator (op, mode)
3607 register rtx op;
3608 enum machine_mode mode;
3609 {
3610 enum rtx_code code = GET_CODE (op);
3611 enum machine_mode cc_mode;
3612
3613 if (GET_MODE (op) != mode && mode != VOIDmode)
3614 return 0;
3615
3616 if (GET_RTX_CLASS (code) != '<')
3617 return 0;
3618
3619 cc_mode = GET_MODE (XEXP (op, 0));
3620 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
3621 return 0;
3622
3623 validate_condition_mode (code, cc_mode);
3624
3625 if (code == NE && cc_mode != CCFPmode)
3626 return 0;
3627
3628 return 1;
3629 }
3630
3631 int
3632 trap_comparison_operator (op, mode)
3633 rtx op;
3634 enum machine_mode mode;
3635 {
3636 if (mode != VOIDmode && mode != GET_MODE (op))
3637 return 0;
3638 return GET_RTX_CLASS (GET_CODE (op)) == '<';
3639 }
3640
3641 int
3642 boolean_operator (op, mode)
3643 rtx op;
3644 enum machine_mode mode ATTRIBUTE_UNUSED;
3645 {
3646 enum rtx_code code = GET_CODE (op);
3647 return (code == AND || code == IOR || code == XOR);
3648 }
3649
3650 int
3651 boolean_or_operator (op, mode)
3652 rtx op;
3653 enum machine_mode mode ATTRIBUTE_UNUSED;
3654 {
3655 enum rtx_code code = GET_CODE (op);
3656 return (code == IOR || code == XOR);
3657 }
3658
3659 int
3660 min_max_operator (op, mode)
3661 rtx op;
3662 enum machine_mode mode ATTRIBUTE_UNUSED;
3663 {
3664 enum rtx_code code = GET_CODE (op);
3665 return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
3666 }
3667 \f
3668 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
3669 mask required to convert the result of a rotate insn into a shift
3670 left insn of SHIFTOP bits. Both are known to be CONST_INT. */
3671
3672 int
3673 includes_lshift_p (shiftop, andop)
3674 register rtx shiftop;
3675 register rtx andop;
3676 {
3677 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
3678
3679 shift_mask <<= INTVAL (shiftop);
3680
3681 return (INTVAL (andop) & ~shift_mask) == 0;
3682 }
3683
3684 /* Similar, but for right shift. */
3685
3686 int
3687 includes_rshift_p (shiftop, andop)
3688 register rtx shiftop;
3689 register rtx andop;
3690 {
3691 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
3692
3693 shift_mask >>= INTVAL (shiftop);
3694
3695 return (INTVAL (andop) & ~shift_mask) == 0;
3696 }
3697
3698 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
3699 mask required to convert the result of a rotate insn into a shift
3700 left insn of SHIFTOP bits. */
3701
3702 int
3703 includes_lshift64_p (shiftop, andop)
3704 register rtx shiftop;
3705 register rtx andop;
3706 {
3707 #if HOST_BITS_PER_WIDE_INT == 64
3708 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
3709
3710 shift_mask <<= INTVAL (shiftop);
3711
3712 return (INTVAL (andop) & ~shift_mask) == 0;
3713 #else
3714 unsigned HOST_WIDE_INT shift_mask_low = ~(unsigned HOST_WIDE_INT) 0;
3715 unsigned HOST_WIDE_INT shift_mask_high = ~(unsigned HOST_WIDE_INT) 0;
3716
3717 shift_mask_low <<= INTVAL (shiftop);
3718
3719 if (INTVAL (shiftop) > 32)
3720 shift_mask_high <<= (INTVAL (shiftop) - 32);
3721
3722 if (GET_CODE (andop) == CONST_INT)
3723 return (INTVAL (andop) & ~shift_mask_low) == 0;
3724 else
3725 return ((CONST_DOUBLE_HIGH (andop) & ~shift_mask_high) == 0
3726 && (CONST_DOUBLE_LOW (andop) & ~shift_mask_low) == 0);
3727 #endif
3728 }
3729
3730 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
3731 for lfq and stfq insns.
3732
3733 Note reg1 and reg2 *must* be hard registers. To be sure we will
3734 abort if we are passed pseudo registers. */
3735
3736 int
3737 registers_ok_for_quad_peep (reg1, reg2)
3738 rtx reg1, reg2;
3739 {
3740 /* We might have been passed a SUBREG. */
3741 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
3742 return 0;
3743
3744 return (REGNO (reg1) == REGNO (reg2) - 1);
3745 }
3746
3747 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and
3748 addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */
3749
3750 int
3751 addrs_ok_for_quad_peep (addr1, addr2)
3752 register rtx addr1;
3753 register rtx addr2;
3754 {
3755 unsigned int reg1;
3756 int offset1;
3757
3758 /* Extract an offset (if used) from the first addr. */
3759 if (GET_CODE (addr1) == PLUS)
3760 {
3761 /* If not a REG, return zero. */
3762 if (GET_CODE (XEXP (addr1, 0)) != REG)
3763 return 0;
3764 else
3765 {
3766 reg1 = REGNO (XEXP (addr1, 0));
3767 /* The offset must be constant! */
3768 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
3769 return 0;
3770 offset1 = INTVAL (XEXP (addr1, 1));
3771 }
3772 }
3773 else if (GET_CODE (addr1) != REG)
3774 return 0;
3775 else
3776 {
3777 reg1 = REGNO (addr1);
3778 /* This was a simple (mem (reg)) expression. Offset is 0. */
3779 offset1 = 0;
3780 }
3781
3782 /* Make sure the second address is a (mem (plus (reg) (const_int))). */
3783 if (GET_CODE (addr2) != PLUS)
3784 return 0;
3785
3786 if (GET_CODE (XEXP (addr2, 0)) != REG
3787 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
3788 return 0;
3789
3790 if (reg1 != REGNO (XEXP (addr2, 0)))
3791 return 0;
3792
3793 /* The offset for the second addr must be 8 more than the first addr. */
3794 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
3795 return 0;
3796
3797 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
3798 instructions. */
3799 return 1;
3800 }
3801 \f
3802 /* Return the register class of a scratch register needed to copy IN into
3803 or out of a register in CLASS in MODE. If it can be done directly,
3804 NO_REGS is returned. */
3805
3806 enum reg_class
3807 secondary_reload_class (class, mode, in)
3808 enum reg_class class;
3809 enum machine_mode mode ATTRIBUTE_UNUSED;
3810 rtx in;
3811 {
3812 int regno;
3813
3814 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN && flag_pic))
3815 {
3816 /* We cannot copy a symbolic operand directly into anything
3817 other than BASE_REGS for TARGET_ELF. So indicate that a
3818 register from BASE_REGS is needed as an intermediate
3819 register.
3820
3821 On Darwin, pic addresses require a load from memory, which
3822 needs a base register. */
3823 if (class != BASE_REGS
3824 && (GET_CODE (in) == SYMBOL_REF
3825 || GET_CODE (in) == HIGH
3826 || GET_CODE (in) == LABEL_REF
3827 || GET_CODE (in) == CONST))
3828 return BASE_REGS;
3829 }
3830
3831 if (GET_CODE (in) == REG)
3832 {
3833 regno = REGNO (in);
3834 if (regno >= FIRST_PSEUDO_REGISTER)
3835 {
3836 regno = true_regnum (in);
3837 if (regno >= FIRST_PSEUDO_REGISTER)
3838 regno = -1;
3839 }
3840 }
3841 else if (GET_CODE (in) == SUBREG)
3842 {
3843 regno = true_regnum (in);
3844 if (regno >= FIRST_PSEUDO_REGISTER)
3845 regno = -1;
3846 }
3847 else
3848 regno = -1;
3849
3850 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
3851 into anything. */
3852 if (class == GENERAL_REGS || class == BASE_REGS
3853 || (regno >= 0 && INT_REGNO_P (regno)))
3854 return NO_REGS;
3855
3856 /* Constants, memory, and FP registers can go into FP registers. */
3857 if ((regno == -1 || FP_REGNO_P (regno))
3858 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
3859 return NO_REGS;
3860
3861 /* We can copy among the CR registers. */
3862 if ((class == CR_REGS || class == CR0_REGS)
3863 && regno >= 0 && CR_REGNO_P (regno))
3864 return NO_REGS;
3865
3866 /* Otherwise, we need GENERAL_REGS. */
3867 return GENERAL_REGS;
3868 }
3869 \f
3870 /* Given a comparison operation, return the bit number in CCR to test. We
3871 know this is a valid comparison.
3872
3873 SCC_P is 1 if this is for an scc. That means that %D will have been
3874 used instead of %C, so the bits will be in different places.
3875
3876 Return -1 if OP isn't a valid comparison for some reason. */
3877
3878 int
3879 ccr_bit (op, scc_p)
3880 register rtx op;
3881 int scc_p;
3882 {
3883 enum rtx_code code = GET_CODE (op);
3884 enum machine_mode cc_mode;
3885 int cc_regnum;
3886 int base_bit;
3887 rtx reg;
3888
3889 if (GET_RTX_CLASS (code) != '<')
3890 return -1;
3891
3892 reg = XEXP (op, 0);
3893
3894 if (GET_CODE (reg) != REG
3895 || ! CR_REGNO_P (REGNO (reg)))
3896 abort ();
3897
3898 cc_mode = GET_MODE (reg);
3899 cc_regnum = REGNO (reg);
3900 base_bit = 4 * (cc_regnum - CR0_REGNO);
3901
3902 validate_condition_mode (code, cc_mode);
3903
3904 switch (code)
3905 {
3906 case NE:
3907 return scc_p ? base_bit + 3 : base_bit + 2;
3908 case EQ:
3909 return base_bit + 2;
3910 case GT: case GTU: case UNLE:
3911 return base_bit + 1;
3912 case LT: case LTU: case UNGE:
3913 return base_bit;
3914 case ORDERED: case UNORDERED:
3915 return base_bit + 3;
3916
3917 case GE: case GEU:
3918 /* If scc, we will have done a cror to put the bit in the
3919 unordered position. So test that bit. For integer, this is ! LT
3920 unless this is an scc insn. */
3921 return scc_p ? base_bit + 3 : base_bit;
3922
3923 case LE: case LEU:
3924 return scc_p ? base_bit + 3 : base_bit + 1;
3925
3926 default:
3927 abort ();
3928 }
3929 }
3930 \f
3931 /* Return the GOT register. */
3932
3933 struct rtx_def *
3934 rs6000_got_register (value)
3935 rtx value ATTRIBUTE_UNUSED;
3936 {
3937 /* The second flow pass currently (June 1999) can't update regs_ever_live
3938 without disturbing other parts of the compiler, so update it here to
3939 make the prolog/epilogue code happy. */
3940 if (no_new_pseudos && ! regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
3941 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3942
3943 current_function_uses_pic_offset_table = 1;
3944
3945 return pic_offset_table_rtx;
3946 }
3947 \f
3948 /* Functions to init, mark and free struct machine_function.
3949 These will be called, via pointer variables,
3950 from push_function_context and pop_function_context. */
3951
3952 static void
3953 rs6000_init_machine_status (p)
3954 struct function *p;
3955 {
3956 p->machine = (machine_function *) xcalloc (1, sizeof (machine_function));
3957 }
3958
3959 static void
3960 rs6000_free_machine_status (p)
3961 struct function *p;
3962 {
3963 if (p->machine == NULL)
3964 return;
3965
3966 free (p->machine);
3967 p->machine = NULL;
3968 }
3969
3970 \f
3971 /* Print an operand. Recognize special options, documented below. */
3972
3973 #if TARGET_ELF
3974 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
3975 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
3976 #else
3977 #define SMALL_DATA_RELOC "sda21"
3978 #define SMALL_DATA_REG 0
3979 #endif
3980
3981 void
3982 print_operand (file, x, code)
3983 FILE *file;
3984 rtx x;
3985 int code;
3986 {
3987 int i;
3988 HOST_WIDE_INT val;
3989
3990 /* These macros test for integers and extract the low-order bits. */
3991 #define INT_P(X) \
3992 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
3993 && GET_MODE (X) == VOIDmode)
3994
3995 #define INT_LOWPART(X) \
3996 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
3997
3998 switch (code)
3999 {
4000 case '.':
4001 /* Write out an instruction after the call which may be replaced
4002 with glue code by the loader. This depends on the AIX version. */
4003 asm_fprintf (file, RS6000_CALL_GLUE);
4004 return;
4005
4006 case '$':
4007 /* Write out either a '.' or '$' for the current location, depending
4008 on whether this is Solaris or not. */
4009 putc ((DEFAULT_ABI == ABI_SOLARIS) ? '.' : '$', file);
4010 return;
4011
4012 /* %a is output_address. */
4013
4014 case 'A':
4015 /* If X is a constant integer whose low-order 5 bits are zero,
4016 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
4017 in the AIX assembler where "sri" with a zero shift count
4018 write a trash instruction. */
4019 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
4020 putc ('l', file);
4021 else
4022 putc ('r', file);
4023 return;
4024
4025 case 'b':
4026 /* If constant, low-order 16 bits of constant, unsigned.
4027 Otherwise, write normally. */
4028 if (INT_P (x))
4029 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
4030 else
4031 print_operand (file, x, 0);
4032 return;
4033
4034 case 'B':
4035 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
4036 for 64-bit mask direction. */
4037 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
4038 return;
4039
4040 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
4041 output_operand. */
4042
4043 case 'D':
4044 /* There used to be a comment for 'C' reading "This is an
4045 optional cror needed for certain floating-point
4046 comparisons. Otherwise write nothing." */
4047
4048 /* Similar, except that this is for an scc, so we must be able to
4049 encode the test in a single bit that is one. We do the above
4050 for any LE, GE, GEU, or LEU and invert the bit for NE. */
4051 if (GET_CODE (x) == LE || GET_CODE (x) == GE
4052 || GET_CODE (x) == LEU || GET_CODE (x) == GEU)
4053 {
4054 int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO);
4055
4056 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
4057 base_bit + 2,
4058 base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU));
4059 }
4060
4061 else if (GET_CODE (x) == NE)
4062 {
4063 int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO);
4064
4065 fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
4066 base_bit + 2, base_bit + 2);
4067 }
4068 return;
4069
4070 case 'E':
4071 /* X is a CR register. Print the number of the EQ bit of the CR */
4072 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
4073 output_operand_lossage ("invalid %%E value");
4074 else
4075 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
4076 return;
4077
4078 case 'f':
4079 /* X is a CR register. Print the shift count needed to move it
4080 to the high-order four bits. */
4081 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
4082 output_operand_lossage ("invalid %%f value");
4083 else
4084 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
4085 return;
4086
4087 case 'F':
4088 /* Similar, but print the count for the rotate in the opposite
4089 direction. */
4090 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
4091 output_operand_lossage ("invalid %%F value");
4092 else
4093 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
4094 return;
4095
4096 case 'G':
4097 /* X is a constant integer. If it is negative, print "m",
4098 otherwise print "z". This is to make a aze or ame insn. */
4099 if (GET_CODE (x) != CONST_INT)
4100 output_operand_lossage ("invalid %%G value");
4101 else if (INTVAL (x) >= 0)
4102 putc ('z', file);
4103 else
4104 putc ('m', file);
4105 return;
4106
4107 case 'h':
4108 /* If constant, output low-order five bits. Otherwise,
4109 write normally. */
4110 if (INT_P (x))
4111 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
4112 else
4113 print_operand (file, x, 0);
4114 return;
4115
4116 case 'H':
4117 /* If constant, output low-order six bits. Otherwise,
4118 write normally. */
4119 if (INT_P (x))
4120 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
4121 else
4122 print_operand (file, x, 0);
4123 return;
4124
4125 case 'I':
4126 /* Print `i' if this is a constant, else nothing. */
4127 if (INT_P (x))
4128 putc ('i', file);
4129 return;
4130
4131 case 'j':
4132 /* Write the bit number in CCR for jump. */
4133 i = ccr_bit (x, 0);
4134 if (i == -1)
4135 output_operand_lossage ("invalid %%j code");
4136 else
4137 fprintf (file, "%d", i);
4138 return;
4139
4140 case 'J':
4141 /* Similar, but add one for shift count in rlinm for scc and pass
4142 scc flag to `ccr_bit'. */
4143 i = ccr_bit (x, 1);
4144 if (i == -1)
4145 output_operand_lossage ("invalid %%J code");
4146 else
4147 /* If we want bit 31, write a shift count of zero, not 32. */
4148 fprintf (file, "%d", i == 31 ? 0 : i + 1);
4149 return;
4150
4151 case 'k':
4152 /* X must be a constant. Write the 1's complement of the
4153 constant. */
4154 if (! INT_P (x))
4155 output_operand_lossage ("invalid %%k value");
4156 else
4157 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
4158 return;
4159
4160 case 'K':
4161 /* X must be a symbolic constant on ELF. Write an
4162 expression suitable for an 'addi' that adds in the low 16
4163 bits of the MEM. */
4164 if (GET_CODE (x) != CONST)
4165 {
4166 print_operand_address (file, x);
4167 fputs ("@l", file);
4168 }
4169 else
4170 {
4171 if (GET_CODE (XEXP (x, 0)) != PLUS
4172 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
4173 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
4174 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
4175 output_operand_lossage ("invalid %%K value");
4176 print_operand_address (file, XEXP (XEXP (x, 0), 0));
4177 fputs ("@l", file);
4178 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
4179 }
4180 return;
4181
4182 /* %l is output_asm_label. */
4183
4184 case 'L':
4185 /* Write second word of DImode or DFmode reference. Works on register
4186 or non-indexed memory only. */
4187 if (GET_CODE (x) == REG)
4188 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
4189 else if (GET_CODE (x) == MEM)
4190 {
4191 /* Handle possible auto-increment. Since it is pre-increment and
4192 we have already done it, we can just use an offset of word. */
4193 if (GET_CODE (XEXP (x, 0)) == PRE_INC
4194 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
4195 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
4196 UNITS_PER_WORD));
4197 else
4198 output_address (XEXP (adjust_address_nv (x, SImode,
4199 UNITS_PER_WORD),
4200 0));
4201
4202 if (small_data_operand (x, GET_MODE (x)))
4203 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
4204 reg_names[SMALL_DATA_REG]);
4205 }
4206 return;
4207
4208 case 'm':
4209 /* MB value for a mask operand. */
4210 if (! mask_operand (x, VOIDmode))
4211 output_operand_lossage ("invalid %%m value");
4212
4213 val = INT_LOWPART (x);
4214
4215 /* If the high bit is set and the low bit is not, the value is zero.
4216 If the high bit is zero, the value is the first 1 bit we find from
4217 the left. */
4218 if ((val & 0x80000000) && ((val & 1) == 0))
4219 {
4220 putc ('0', file);
4221 return;
4222 }
4223 else if ((val & 0x80000000) == 0)
4224 {
4225 for (i = 1; i < 32; i++)
4226 if ((val <<= 1) & 0x80000000)
4227 break;
4228 fprintf (file, "%d", i);
4229 return;
4230 }
4231
4232 /* Otherwise, look for the first 0 bit from the right. The result is its
4233 number plus 1. We know the low-order bit is one. */
4234 for (i = 0; i < 32; i++)
4235 if (((val >>= 1) & 1) == 0)
4236 break;
4237
4238 /* If we ended in ...01, i would be 0. The correct value is 31, so
4239 we want 31 - i. */
4240 fprintf (file, "%d", 31 - i);
4241 return;
4242
4243 case 'M':
4244 /* ME value for a mask operand. */
4245 if (! mask_operand (x, VOIDmode))
4246 output_operand_lossage ("invalid %%M value");
4247
4248 val = INT_LOWPART (x);
4249
4250 /* If the low bit is set and the high bit is not, the value is 31.
4251 If the low bit is zero, the value is the first 1 bit we find from
4252 the right. */
4253 if ((val & 1) && ((val & 0x80000000) == 0))
4254 {
4255 fputs ("31", file);
4256 return;
4257 }
4258 else if ((val & 1) == 0)
4259 {
4260 for (i = 0; i < 32; i++)
4261 if ((val >>= 1) & 1)
4262 break;
4263
4264 /* If we had ....10, i would be 0. The result should be
4265 30, so we need 30 - i. */
4266 fprintf (file, "%d", 30 - i);
4267 return;
4268 }
4269
4270 /* Otherwise, look for the first 0 bit from the left. The result is its
4271 number minus 1. We know the high-order bit is one. */
4272 for (i = 0; i < 32; i++)
4273 if (((val <<= 1) & 0x80000000) == 0)
4274 break;
4275
4276 fprintf (file, "%d", i);
4277 return;
4278
4279 /* %n outputs the negative of its operand. */
4280
4281 case 'N':
4282 /* Write the number of elements in the vector times 4. */
4283 if (GET_CODE (x) != PARALLEL)
4284 output_operand_lossage ("invalid %%N value");
4285 else
4286 fprintf (file, "%d", XVECLEN (x, 0) * 4);
4287 return;
4288
4289 case 'O':
4290 /* Similar, but subtract 1 first. */
4291 if (GET_CODE (x) != PARALLEL)
4292 output_operand_lossage ("invalid %%O value");
4293 else
4294 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
4295 return;
4296
4297 case 'p':
4298 /* X is a CONST_INT that is a power of two. Output the logarithm. */
4299 if (! INT_P (x)
4300 || INT_LOWPART (x) < 0
4301 || (i = exact_log2 (INT_LOWPART (x))) < 0)
4302 output_operand_lossage ("invalid %%p value");
4303 else
4304 fprintf (file, "%d", i);
4305 return;
4306
4307 case 'P':
4308 /* The operand must be an indirect memory reference. The result
4309 is the register number. */
4310 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
4311 || REGNO (XEXP (x, 0)) >= 32)
4312 output_operand_lossage ("invalid %%P value");
4313 else
4314 fprintf (file, "%d", REGNO (XEXP (x, 0)));
4315 return;
4316
4317 case 'q':
4318 /* This outputs the logical code corresponding to a boolean
4319 expression. The expression may have one or both operands
4320 negated (if one, only the first one). For condition register
4321 logical operations, it will also treat the negated
4322 CR codes as NOTs, but not handle NOTs of them. */
4323 {
4324 const char *const *t = 0;
4325 const char *s;
4326 enum rtx_code code = GET_CODE (x);
4327 static const char * const tbl[3][3] = {
4328 { "and", "andc", "nor" },
4329 { "or", "orc", "nand" },
4330 { "xor", "eqv", "xor" } };
4331
4332 if (code == AND)
4333 t = tbl[0];
4334 else if (code == IOR)
4335 t = tbl[1];
4336 else if (code == XOR)
4337 t = tbl[2];
4338 else
4339 output_operand_lossage ("invalid %%q value");
4340
4341 if (GET_CODE (XEXP (x, 0)) != NOT)
4342 s = t[0];
4343 else
4344 {
4345 if (GET_CODE (XEXP (x, 1)) == NOT)
4346 s = t[2];
4347 else
4348 s = t[1];
4349 }
4350
4351 fputs (s, file);
4352 }
4353 return;
4354
4355 case 'R':
4356 /* X is a CR register. Print the mask for `mtcrf'. */
4357 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
4358 output_operand_lossage ("invalid %%R value");
4359 else
4360 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
4361 return;
4362
4363 case 's':
4364 /* Low 5 bits of 32 - value */
4365 if (! INT_P (x))
4366 output_operand_lossage ("invalid %%s value");
4367 else
4368 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
4369 return;
4370
4371 case 'S':
4372 /* PowerPC64 mask position. All 0's and all 1's are excluded.
4373 CONST_INT 32-bit mask is considered sign-extended so any
4374 transition must occur within the CONST_INT, not on the boundary. */
4375 if (! mask64_operand (x, VOIDmode))
4376 output_operand_lossage ("invalid %%S value");
4377
4378 val = INT_LOWPART (x);
4379
4380 if (val & 1) /* Clear Left */
4381 {
4382 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
4383 if (!((val >>= 1) & 1))
4384 break;
4385
4386 #if HOST_BITS_PER_WIDE_INT == 32
4387 if (GET_CODE (x) == CONST_DOUBLE && i == 32)
4388 {
4389 val = CONST_DOUBLE_HIGH (x);
4390
4391 if (val == 0)
4392 --i;
4393 else
4394 for (i = 32; i < 64; i++)
4395 if (!((val >>= 1) & 1))
4396 break;
4397 }
4398 #endif
4399 /* i = index of last set bit from right
4400 mask begins at 63 - i from left */
4401 if (i > 63)
4402 output_operand_lossage ("%%S computed all 1's mask");
4403
4404 fprintf (file, "%d", 63 - i);
4405 return;
4406 }
4407 else /* Clear Right */
4408 {
4409 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
4410 if ((val >>= 1) & 1)
4411 break;
4412
4413 #if HOST_BITS_PER_WIDE_INT == 32
4414 if (GET_CODE (x) == CONST_DOUBLE && i == 32)
4415 {
4416 val = CONST_DOUBLE_HIGH (x);
4417
4418 if (val == (HOST_WIDE_INT) -1)
4419 --i;
4420 else
4421 for (i = 32; i < 64; i++)
4422 if ((val >>= 1) & 1)
4423 break;
4424 }
4425 #endif
4426 /* i = index of last clear bit from right
4427 mask ends at 62 - i from left */
4428 if (i > 62)
4429 output_operand_lossage ("%%S computed all 0's mask");
4430
4431 fprintf (file, "%d", 62 - i);
4432 return;
4433 }
4434
4435 case 'T':
4436 /* Print the symbolic name of a branch target register. */
4437 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
4438 && REGNO (x) != COUNT_REGISTER_REGNUM))
4439 output_operand_lossage ("invalid %%T value");
4440 else if (REGNO (x) == LINK_REGISTER_REGNUM)
4441 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
4442 else
4443 fputs ("ctr", file);
4444 return;
4445
4446 case 'u':
4447 /* High-order 16 bits of constant for use in unsigned operand. */
4448 if (! INT_P (x))
4449 output_operand_lossage ("invalid %%u value");
4450 else
4451 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
4452 (INT_LOWPART (x) >> 16) & 0xffff);
4453 return;
4454
4455 case 'v':
4456 /* High-order 16 bits of constant for use in signed operand. */
4457 if (! INT_P (x))
4458 output_operand_lossage ("invalid %%v value");
4459 else
4460 {
4461 int value = (INT_LOWPART (x) >> 16) & 0xffff;
4462
4463 /* Solaris assembler doesn't like lis 0,0x8000 */
4464 if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0)
4465 fprintf (file, "%d", value | (~0 << 16));
4466 else
4467 fprintf (file, "0x%x", value);
4468 return;
4469 }
4470
4471 case 'U':
4472 /* Print `u' if this has an auto-increment or auto-decrement. */
4473 if (GET_CODE (x) == MEM
4474 && (GET_CODE (XEXP (x, 0)) == PRE_INC
4475 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
4476 putc ('u', file);
4477 return;
4478
4479 case 'V':
4480 /* Print the trap code for this operand. */
4481 switch (GET_CODE (x))
4482 {
4483 case EQ:
4484 fputs ("eq", file); /* 4 */
4485 break;
4486 case NE:
4487 fputs ("ne", file); /* 24 */
4488 break;
4489 case LT:
4490 fputs ("lt", file); /* 16 */
4491 break;
4492 case LE:
4493 fputs ("le", file); /* 20 */
4494 break;
4495 case GT:
4496 fputs ("gt", file); /* 8 */
4497 break;
4498 case GE:
4499 fputs ("ge", file); /* 12 */
4500 break;
4501 case LTU:
4502 fputs ("llt", file); /* 2 */
4503 break;
4504 case LEU:
4505 fputs ("lle", file); /* 6 */
4506 break;
4507 case GTU:
4508 fputs ("lgt", file); /* 1 */
4509 break;
4510 case GEU:
4511 fputs ("lge", file); /* 5 */
4512 break;
4513 default:
4514 abort ();
4515 }
4516 break;
4517
4518 case 'w':
4519 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
4520 normally. */
4521 if (INT_P (x))
4522 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4523 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
4524 else
4525 print_operand (file, x, 0);
4526 return;
4527
4528 case 'W':
4529 /* MB value for a PowerPC64 rldic operand. */
4530 if (! rldic_operand (x, VOIDmode))
4531 output_operand_lossage ("invalid %%W value");
4532
4533 val = (GET_CODE (x) == CONST_INT
4534 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
4535
4536 if (val < 0)
4537 i = -1;
4538 else
4539 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
4540 if ((val <<= 1) < 0)
4541 break;
4542
4543 #if HOST_BITS_PER_WIDE_INT == 32
4544 if (GET_CODE (x) == CONST_INT && i >= 0)
4545 i += 32; /* zero-extend high-part was all 0's */
4546 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
4547 {
4548 val = CONST_DOUBLE_LOW (x);
4549
4550 if (val == 0)
4551 abort();
4552 else if (val < 0)
4553 --i;
4554 else
4555 for ( ; i < 64; i++)
4556 if ((val <<= 1) < 0)
4557 break;
4558 }
4559 #endif
4560
4561 fprintf (file, "%d", i + 1);
4562 return;
4563
4564 case 'X':
4565 if (GET_CODE (x) == MEM
4566 && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0), 0))
4567 putc ('x', file);
4568 return;
4569
4570 case 'Y':
4571 /* Like 'L', for third word of TImode */
4572 if (GET_CODE (x) == REG)
4573 fprintf (file, "%s", reg_names[REGNO (x) + 2]);
4574 else if (GET_CODE (x) == MEM)
4575 {
4576 if (GET_CODE (XEXP (x, 0)) == PRE_INC
4577 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
4578 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
4579 else
4580 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
4581 if (small_data_operand (x, GET_MODE (x)))
4582 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
4583 reg_names[SMALL_DATA_REG]);
4584 }
4585 return;
4586
4587 case 'z':
4588 /* X is a SYMBOL_REF. Write out the name preceded by a
4589 period and without any trailing data in brackets. Used for function
4590 names. If we are configured for System V (or the embedded ABI) on
4591 the PowerPC, do not emit the period, since those systems do not use
4592 TOCs and the like. */
4593 if (GET_CODE (x) != SYMBOL_REF)
4594 abort ();
4595
4596 if (XSTR (x, 0)[0] != '.')
4597 {
4598 switch (DEFAULT_ABI)
4599 {
4600 default:
4601 abort ();
4602
4603 case ABI_AIX:
4604 putc ('.', file);
4605 break;
4606
4607 case ABI_V4:
4608 case ABI_AIX_NODESC:
4609 case ABI_SOLARIS:
4610 case ABI_DARWIN:
4611 break;
4612 }
4613 }
4614 #if TARGET_AIX
4615 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
4616 #else
4617 assemble_name (file, XSTR (x, 0));
4618 #endif
4619 return;
4620
4621 case 'Z':
4622 /* Like 'L', for last word of TImode. */
4623 if (GET_CODE (x) == REG)
4624 fprintf (file, "%s", reg_names[REGNO (x) + 3]);
4625 else if (GET_CODE (x) == MEM)
4626 {
4627 if (GET_CODE (XEXP (x, 0)) == PRE_INC
4628 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
4629 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
4630 else
4631 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
4632 if (small_data_operand (x, GET_MODE (x)))
4633 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
4634 reg_names[SMALL_DATA_REG]);
4635 }
4636 return;
4637
4638 case 0:
4639 if (GET_CODE (x) == REG)
4640 fprintf (file, "%s", reg_names[REGNO (x)]);
4641 else if (GET_CODE (x) == MEM)
4642 {
4643 /* We need to handle PRE_INC and PRE_DEC here, since we need to
4644 know the width from the mode. */
4645 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
4646 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
4647 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
4648 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
4649 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
4650 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
4651 else
4652 output_address (XEXP (x, 0));
4653 }
4654 else
4655 output_addr_const (file, x);
4656 return;
4657
4658 default:
4659 output_operand_lossage ("invalid %%xn code");
4660 }
4661 }
4662 \f
4663 /* Print the address of an operand. */
4664
4665 void
4666 print_operand_address (file, x)
4667 FILE *file;
4668 register rtx x;
4669 {
4670 if (GET_CODE (x) == REG)
4671 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
4672 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
4673 || GET_CODE (x) == LABEL_REF)
4674 {
4675 output_addr_const (file, x);
4676 if (small_data_operand (x, GET_MODE (x)))
4677 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
4678 reg_names[SMALL_DATA_REG]);
4679 else if (TARGET_TOC)
4680 abort();
4681 }
4682 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
4683 {
4684 if (REGNO (XEXP (x, 0)) == 0)
4685 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
4686 reg_names[ REGNO (XEXP (x, 0)) ]);
4687 else
4688 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
4689 reg_names[ REGNO (XEXP (x, 1)) ]);
4690 }
4691 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
4692 {
4693 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1)));
4694 fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
4695 }
4696 #if TARGET_ELF
4697 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
4698 && CONSTANT_P (XEXP (x, 1)))
4699 {
4700 output_addr_const (file, XEXP (x, 1));
4701 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
4702 }
4703 #endif
4704 else if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x))
4705 {
4706 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
4707 {
4708 rtx contains_minus = XEXP (x, 1);
4709 rtx minus, symref;
4710 const char *name;
4711
4712 /* Find the (minus (sym) (toc)) buried in X, and temporarily
4713 turn it into (sym) for output_addr_const. */
4714 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
4715 contains_minus = XEXP (contains_minus, 0);
4716
4717 minus = XEXP (contains_minus, 0);
4718 symref = XEXP (minus, 0);
4719 XEXP (contains_minus, 0) = symref;
4720 if (TARGET_ELF)
4721 {
4722 char *newname;
4723
4724 name = XSTR (symref, 0);
4725 newname = alloca (strlen (name) + sizeof ("@toc"));
4726 strcpy (newname, name);
4727 strcat (newname, "@toc");
4728 XSTR (symref, 0) = newname;
4729 }
4730 output_addr_const (file, XEXP (x, 1));
4731 if (TARGET_ELF)
4732 XSTR (symref, 0) = name;
4733 XEXP (contains_minus, 0) = minus;
4734 }
4735 else
4736 output_addr_const (file, XEXP (x, 1));
4737
4738 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
4739 }
4740 else
4741 abort ();
4742 }
4743 \f
4744 enum rtx_code
4745 rs6000_reverse_condition (mode, code)
4746 enum machine_mode mode;
4747 enum rtx_code code;
4748 {
4749 /* Reversal of FP compares takes care -- an ordered compare
4750 becomes an unordered compare and vice versa. */
4751 if (mode == CCFPmode)
4752 return reverse_condition_maybe_unordered (code);
4753 else
4754 return reverse_condition (code);
4755 }
4756
4757
4758 /* Generate a compare for CODE. Return a brand-new rtx that
4759 represents the result of the compare. */
4760 static rtx
4761 rs6000_generate_compare (code)
4762 enum rtx_code code;
4763 {
4764 enum machine_mode comp_mode;
4765 rtx compare_result;
4766
4767 if (rs6000_compare_fp_p)
4768 comp_mode = CCFPmode;
4769 else if (code == GTU || code == LTU
4770 || code == GEU || code == LEU)
4771 comp_mode = CCUNSmode;
4772 else
4773 comp_mode = CCmode;
4774
4775 /* First, the compare. */
4776 compare_result = gen_reg_rtx (comp_mode);
4777 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
4778 gen_rtx_COMPARE (comp_mode,
4779 rs6000_compare_op0,
4780 rs6000_compare_op1)));
4781
4782 /* Some kinds of FP comparisons need an OR operation;
4783 except for flag_unsafe_math_optimizations we don't bother. */
4784 if (rs6000_compare_fp_p
4785 && ! flag_unsafe_math_optimizations
4786 && (code == LE || code == GE
4787 || code == UNEQ || code == LTGT
4788 || code == UNGT || code == UNLT))
4789 {
4790 enum rtx_code or1, or2;
4791 rtx or1_rtx, or2_rtx, compare2_rtx;
4792 rtx or_result = gen_reg_rtx (CCEQmode);
4793
4794 switch (code)
4795 {
4796 case LE: or1 = LT; or2 = EQ; break;
4797 case GE: or1 = GT; or2 = EQ; break;
4798 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
4799 case LTGT: or1 = LT; or2 = GT; break;
4800 case UNGT: or1 = UNORDERED; or2 = GT; break;
4801 case UNLT: or1 = UNORDERED; or2 = LT; break;
4802 default: abort ();
4803 }
4804 validate_condition_mode (or1, comp_mode);
4805 validate_condition_mode (or2, comp_mode);
4806 or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx);
4807 or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx);
4808 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
4809 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
4810 const_true_rtx);
4811 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
4812
4813 compare_result = or_result;
4814 code = EQ;
4815 }
4816
4817 validate_condition_mode (code, GET_MODE (compare_result));
4818
4819 return gen_rtx (code, VOIDmode, compare_result, const0_rtx);
4820 }
4821
4822
4823 /* Emit the RTL for an sCOND pattern. */
4824
4825 void
4826 rs6000_emit_sCOND (code, result)
4827 enum rtx_code code;
4828 rtx result;
4829 {
4830 rtx condition_rtx;
4831 enum machine_mode op_mode;
4832
4833 condition_rtx = rs6000_generate_compare (code);
4834
4835 op_mode = GET_MODE (rs6000_compare_op0);
4836 if (op_mode == VOIDmode)
4837 op_mode = GET_MODE (rs6000_compare_op1);
4838
4839 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
4840 {
4841 PUT_MODE (condition_rtx, DImode);
4842 convert_move (result, condition_rtx, 0);
4843 }
4844 else
4845 {
4846 PUT_MODE (condition_rtx, SImode);
4847 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
4848 }
4849 }
4850
4851
4852 /* Emit a branch of kind CODE to location LOC. */
4853
4854 void
4855 rs6000_emit_cbranch (code, loc)
4856 enum rtx_code code;
4857 rtx loc;
4858 {
4859 rtx condition_rtx, loc_ref;
4860
4861 condition_rtx = rs6000_generate_compare (code);
4862 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
4863 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4864 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
4865 loc_ref, pc_rtx)));
4866 }
4867
4868
4869 /* Return the string to output a conditional branch to LABEL, which is
4870 the operand number of the label, or -1 if the branch is really a
4871 conditional return.
4872
4873 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
4874 condition code register and its mode specifies what kind of
4875 comparison we made.
4876
4877 REVERSED is non-zero if we should reverse the sense of the comparison.
4878
4879 INSN is the insn. */
4880
4881 char *
4882 output_cbranch (op, label, reversed, insn)
4883 rtx op;
4884 const char * label;
4885 int reversed;
4886 rtx insn;
4887 {
4888 static char string[64];
4889 enum rtx_code code = GET_CODE (op);
4890 rtx cc_reg = XEXP (op, 0);
4891 enum machine_mode mode = GET_MODE (cc_reg);
4892 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
4893 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
4894 int really_reversed = reversed ^ need_longbranch;
4895 char *s = string;
4896 const char *ccode;
4897 const char *pred;
4898 rtx note;
4899
4900 validate_condition_mode (code, mode);
4901
4902 /* Work out which way this really branches. We could use
4903 reverse_condition_maybe_unordered here always but this
4904 makes the resulting assembler clearer. */
4905 if (really_reversed)
4906 code = rs6000_reverse_condition (mode, code);
4907
4908 switch (code)
4909 {
4910 /* Not all of these are actually distinct opcodes, but
4911 we distinguish them for clarity of the resulting assembler. */
4912 case NE: case LTGT:
4913 ccode = "ne"; break;
4914 case EQ: case UNEQ:
4915 ccode = "eq"; break;
4916 case GE: case GEU:
4917 ccode = "ge"; break;
4918 case GT: case GTU: case UNGT:
4919 ccode = "gt"; break;
4920 case LE: case LEU:
4921 ccode = "le"; break;
4922 case LT: case LTU: case UNLT:
4923 ccode = "lt"; break;
4924 case UNORDERED: ccode = "un"; break;
4925 case ORDERED: ccode = "nu"; break;
4926 case UNGE: ccode = "nl"; break;
4927 case UNLE: ccode = "ng"; break;
4928 default:
4929 abort();
4930 }
4931
4932 /* Maybe we have a guess as to how likely the branch is.
4933 The old mnemonics don't have a way to specify this information. */
4934 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
4935 if (note != NULL_RTX)
4936 {
4937 /* PROB is the difference from 50%. */
4938 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
4939
4940 /* For branches that are very close to 50%, assume not-taken. */
4941 if (abs (prob) > REG_BR_PROB_BASE / 20
4942 && ((prob > 0) ^ need_longbranch))
4943 pred = "+";
4944 else
4945 pred = "-";
4946 }
4947 else
4948 pred = "";
4949
4950 if (label == NULL)
4951 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
4952 else
4953 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
4954
4955 /* We need to escape any '%' characters in the reg_names string.
4956 Assume they'd only be the first character... */
4957 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
4958 *s++ = '%';
4959 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
4960
4961 if (label != NULL)
4962 {
4963 /* If the branch distance was too far, we may have to use an
4964 unconditional branch to go the distance. */
4965 if (need_longbranch)
4966 s += sprintf (s, ",%c$+8\n\tb %s", '%', label);
4967 else
4968 s += sprintf (s, ",%s", label);
4969 }
4970
4971 return string;
4972 }
4973
4974 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
4975 operands of the last comparison is nonzero/true, FALSE_COND if it
4976 is zero/false. Return 0 if the hardware has no such operation. */
4977 int
4978 rs6000_emit_cmove (dest, op, true_cond, false_cond)
4979 rtx dest;
4980 rtx op;
4981 rtx true_cond;
4982 rtx false_cond;
4983 {
4984 enum rtx_code code = GET_CODE (op);
4985 rtx op0 = rs6000_compare_op0;
4986 rtx op1 = rs6000_compare_op1;
4987 REAL_VALUE_TYPE c1;
4988 enum machine_mode mode = GET_MODE (op0);
4989 rtx temp;
4990
4991 /* First, work out if the hardware can do this at all, or
4992 if it's too slow... */
4993 /* If the comparison is an integer one, since we only have fsel
4994 it'll be cheaper to use a branch. */
4995 if (! rs6000_compare_fp_p)
4996 return 0;
4997
4998 /* Eliminate half of the comparisons by switching operands, this
4999 makes the remaining code simpler. */
5000 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
5001 || code == LTGT || code == LT)
5002 {
5003 code = reverse_condition_maybe_unordered (code);
5004 temp = true_cond;
5005 true_cond = false_cond;
5006 false_cond = temp;
5007 }
5008
5009 /* UNEQ and LTGT take four instructions for a comparison with zero,
5010 it'll probably be faster to use a branch here too. */
5011 if (code == UNEQ)
5012 return 0;
5013
5014 if (GET_CODE (op1) == CONST_DOUBLE)
5015 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
5016
5017 /* We're going to try to implement comparions by performing
5018 a subtract, then comparing against zero. Unfortunately,
5019 Inf - Inf is NaN which is not zero, and so if we don't
5020 know that the the operand is finite and the comparison
5021 would treat EQ different to UNORDERED, we can't do it. */
5022 if (! flag_unsafe_math_optimizations
5023 && code != GT && code != UNGE
5024 && (GET_CODE (op1) != CONST_DOUBLE || target_isinf (c1))
5025 /* Constructs of the form (a OP b ? a : b) are safe. */
5026 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
5027 || (! rtx_equal_p (op0, true_cond)
5028 && ! rtx_equal_p (op1, true_cond))))
5029 return 0;
5030 /* At this point we know we can use fsel. */
5031
5032 /* Reduce the comparison to a comparison against zero. */
5033 temp = gen_reg_rtx (mode);
5034 emit_insn (gen_rtx_SET (VOIDmode, temp,
5035 gen_rtx_MINUS (mode, op0, op1)));
5036 op0 = temp;
5037 op1 = CONST0_RTX (mode);
5038
5039 /* If we don't care about NaNs we can reduce some of the comparisons
5040 down to faster ones. */
5041 if (flag_unsafe_math_optimizations)
5042 switch (code)
5043 {
5044 case GT:
5045 code = LE;
5046 temp = true_cond;
5047 true_cond = false_cond;
5048 false_cond = temp;
5049 break;
5050 case UNGE:
5051 code = GE;
5052 break;
5053 case UNEQ:
5054 code = EQ;
5055 break;
5056 default:
5057 break;
5058 }
5059
5060 /* Now, reduce everything down to a GE. */
5061 switch (code)
5062 {
5063 case GE:
5064 break;
5065
5066 case LE:
5067 temp = gen_reg_rtx (mode);
5068 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0)));
5069 op0 = temp;
5070 break;
5071
5072 case ORDERED:
5073 temp = gen_reg_rtx (mode);
5074 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (mode, op0)));
5075 op0 = temp;
5076 break;
5077
5078 case EQ:
5079 temp = gen_reg_rtx (mode);
5080 emit_insn (gen_rtx_SET (VOIDmode, temp,
5081 gen_rtx_NEG (mode,
5082 gen_rtx_ABS (mode, op0))));
5083 op0 = temp;
5084 break;
5085
5086 case UNGE:
5087 temp = gen_reg_rtx (mode);
5088 emit_insn (gen_rtx_SET (VOIDmode, temp,
5089 gen_rtx_IF_THEN_ELSE (mode,
5090 gen_rtx_GE (VOIDmode,
5091 op0, op1),
5092 true_cond, false_cond)));
5093 false_cond = temp;
5094 true_cond = false_cond;
5095
5096 temp = gen_reg_rtx (mode);
5097 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0)));
5098 op0 = temp;
5099 break;
5100
5101 case GT:
5102 temp = gen_reg_rtx (mode);
5103 emit_insn (gen_rtx_SET (VOIDmode, temp,
5104 gen_rtx_IF_THEN_ELSE (mode,
5105 gen_rtx_GE (VOIDmode,
5106 op0, op1),
5107 true_cond, false_cond)));
5108 true_cond = temp;
5109 false_cond = true_cond;
5110
5111 temp = gen_reg_rtx (mode);
5112 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0)));
5113 op0 = temp;
5114 break;
5115
5116 default:
5117 abort ();
5118 }
5119
5120 emit_insn (gen_rtx_SET (VOIDmode, dest,
5121 gen_rtx_IF_THEN_ELSE (mode,
5122 gen_rtx_GE (VOIDmode,
5123 op0, op1),
5124 true_cond, false_cond)));
5125 return 1;
5126 }
5127
5128 void
5129 rs6000_emit_minmax (dest, code, op0, op1)
5130 rtx dest;
5131 enum rtx_code code;
5132 rtx op0;
5133 rtx op1;
5134 {
5135 enum machine_mode mode = GET_MODE (op0);
5136 rtx target;
5137 if (code == SMAX || code == UMAX)
5138 target = emit_conditional_move (dest, GE, op0, op1, mode,
5139 op0, op1, mode, 0);
5140 else
5141 target = emit_conditional_move (dest, GE, op0, op1, mode,
5142 op1, op0, mode, 0);
5143 if (target == NULL_RTX)
5144 abort ();
5145 if (target != dest)
5146 emit_move_insn (dest, target);
5147 }
5148 \f
5149 /* This page contains routines that are used to determine what the function
5150 prologue and epilogue code will do and write them out. */
5151
5152 /* Return the first fixed-point register that is required to be saved. 32 if
5153 none. */
5154
5155 int
5156 first_reg_to_save ()
5157 {
5158 int first_reg;
5159
5160 /* Find lowest numbered live register. */
5161 for (first_reg = 13; first_reg <= 31; first_reg++)
5162 if (regs_ever_live[first_reg]
5163 && (! call_used_regs[first_reg]
5164 || (first_reg == PIC_OFFSET_TABLE_REGNUM
5165 && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5166 && flag_pic == 1)
5167 || (DEFAULT_ABI == ABI_DARWIN
5168 && flag_pic)))))
5169 break;
5170
5171 if (profile_flag)
5172 {
5173 /* AIX must save/restore every register that contains a parameter
5174 before/after the .__mcount call plus an additional register
5175 for the static chain, if needed; use registers from 30 down to 22
5176 to do this. */
5177 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
5178 {
5179 int last_parm_reg, profile_first_reg;
5180
5181 /* Figure out last used parameter register. The proper thing
5182 to do is to walk incoming args of the function. A function
5183 might have live parameter registers even if it has no
5184 incoming args. */
5185 for (last_parm_reg = 10;
5186 last_parm_reg > 2 && ! regs_ever_live [last_parm_reg];
5187 last_parm_reg--)
5188 ;
5189
5190 /* Calculate first reg for saving parameter registers
5191 and static chain.
5192 Skip reg 31 which may contain the frame pointer. */
5193 profile_first_reg = (33 - last_parm_reg
5194 - (current_function_needs_context ? 1 : 0));
5195 #if TARGET_MACHO
5196 /* Need to skip another reg to account for R31 being PICBASE
5197 (when flag_pic is set) or R30 being used as the frame
5198 pointer (when flag_pic is not set). */
5199 --profile_first_reg;
5200 #endif
5201 /* Do not save frame pointer if no parameters needs to be saved. */
5202 if (profile_first_reg == 31)
5203 profile_first_reg = 32;
5204
5205 if (first_reg > profile_first_reg)
5206 first_reg = profile_first_reg;
5207 }
5208
5209 /* SVR4 may need one register to preserve the static chain. */
5210 else if (current_function_needs_context)
5211 {
5212 /* Skip reg 31 which may contain the frame pointer. */
5213 if (first_reg > 30)
5214 first_reg = 30;
5215 }
5216 }
5217
5218 #if TARGET_MACHO
5219 if (flag_pic && current_function_uses_pic_offset_table &&
5220 (first_reg > PIC_OFFSET_TABLE_REGNUM))
5221 return PIC_OFFSET_TABLE_REGNUM;
5222 #endif
5223
5224 return first_reg;
5225 }
5226
5227 /* Similar, for FP regs. */
5228
5229 int
5230 first_fp_reg_to_save ()
5231 {
5232 int first_reg;
5233
5234 /* Find lowest numbered live register. */
5235 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
5236 if (regs_ever_live[first_reg])
5237 break;
5238
5239 return first_reg;
5240 }
5241 \f
5242 /* Calculate the stack information for the current function. This is
5243 complicated by having two separate calling sequences, the AIX calling
5244 sequence and the V.4 calling sequence.
5245
5246 AIX (and Darwin/Mac OS) stack frames look like:
5247 32-bit 64-bit
5248 SP----> +---------------------------------------+
5249 | back chain to caller | 0 0
5250 +---------------------------------------+
5251 | saved CR | 4 8 (8-11)
5252 +---------------------------------------+
5253 | saved LR | 8 16
5254 +---------------------------------------+
5255 | reserved for compilers | 12 24
5256 +---------------------------------------+
5257 | reserved for binders | 16 32
5258 +---------------------------------------+
5259 | saved TOC pointer | 20 40
5260 +---------------------------------------+
5261 | Parameter save area (P) | 24 48
5262 +---------------------------------------+
5263 | Alloca space (A) | 24+P etc.
5264 +---------------------------------------+
5265 | Local variable space (L) | 24+P+A
5266 +---------------------------------------+
5267 | Float/int conversion temporary (X) | 24+P+A+L
5268 +---------------------------------------+
5269 | Save area for GP registers (G) | 24+P+A+X+L
5270 +---------------------------------------+
5271 | Save area for FP registers (F) | 24+P+A+X+L+G
5272 +---------------------------------------+
5273 old SP->| back chain to caller's caller |
5274 +---------------------------------------+
5275
5276 The required alignment for AIX configurations is two words (i.e., 8
5277 or 16 bytes).
5278
5279
5280 V.4 stack frames look like:
5281
5282 SP----> +---------------------------------------+
5283 | back chain to caller | 0
5284 +---------------------------------------+
5285 | caller's saved LR | 4
5286 +---------------------------------------+
5287 | Parameter save area (P) | 8
5288 +---------------------------------------+
5289 | Alloca space (A) | 8+P
5290 +---------------------------------------+
5291 | Varargs save area (V) | 8+P+A
5292 +---------------------------------------+
5293 | Local variable space (L) | 8+P+A+V
5294 +---------------------------------------+
5295 | Float/int conversion temporary (X) | 8+P+A+V+L
5296 +---------------------------------------+
5297 | saved CR (C) | 8+P+A+V+L+X
5298 +---------------------------------------+
5299 | Save area for GP registers (G) | 8+P+A+V+L+X+C
5300 +---------------------------------------+
5301 | Save area for FP registers (F) | 8+P+A+V+L+X+C+G
5302 +---------------------------------------+
5303 old SP->| back chain to caller's caller |
5304 +---------------------------------------+
5305
5306 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
5307 given. (But note below and in sysv4.h that we require only 8 and
5308 may round up the size of our stack frame anyways. The historical
5309 reason is early versions of powerpc-linux which didn't properly
5310 align the stack at program startup. A happy side-effect is that
5311 -mno-eabi libraries can be used with -meabi programs.)
5312
5313
5314 The EABI configuration defaults to the V.4 layout, unless
5315 -mcall-aix is used, in which case the AIX layout is used. However,
5316 the stack alignment requirements may differ. If -mno-eabi is not
5317 given, the required stack alignment is 8 bytes; if -mno-eabi is
5318 given, the required alignment is 16 bytes. (But see V.4 comment
5319 above.) */
5320
5321 #ifndef ABI_STACK_BOUNDARY
5322 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
5323 #endif
5324
5325 rs6000_stack_t *
5326 rs6000_stack_info ()
5327 {
5328 static rs6000_stack_t info, zero_info;
5329 rs6000_stack_t *info_ptr = &info;
5330 int reg_size = TARGET_POWERPC64 ? 8 : 4;
5331 enum rs6000_abi abi;
5332 int ehrd_size;
5333 int total_raw_size;
5334
5335 /* Zero all fields portably */
5336 info = zero_info;
5337
5338 /* Select which calling sequence */
5339 info_ptr->abi = abi = DEFAULT_ABI;
5340
5341 /* Calculate which registers need to be saved & save area size */
5342 info_ptr->first_gp_reg_save = first_reg_to_save ();
5343 /* Assume that we will have to save PIC_OFFSET_TABLE_REGNUM,
5344 even if it currently looks like we won't. */
5345 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
5346 || (flag_pic == 1
5347 && (abi == ABI_V4 || abi == ABI_SOLARIS))
5348 || (flag_pic &&
5349 abi == ABI_DARWIN))
5350 && info_ptr->first_gp_reg_save > PIC_OFFSET_TABLE_REGNUM)
5351 info_ptr->gp_size = reg_size * (32 - PIC_OFFSET_TABLE_REGNUM);
5352 else
5353 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
5354
5355 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
5356 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
5357
5358 /* Does this function call anything? */
5359 info_ptr->calls_p = (! current_function_is_leaf
5360 || cfun->machine->ra_needs_full_frame);
5361
5362 /* Determine if we need to save the link register */
5363 if (rs6000_ra_ever_killed ()
5364 || (DEFAULT_ABI == ABI_AIX && profile_flag)
5365 #ifdef TARGET_RELOCATABLE
5366 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
5367 #endif
5368 || (info_ptr->first_fp_reg_save != 64
5369 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
5370 || (abi == ABI_V4 && current_function_calls_alloca)
5371 || (abi == ABI_SOLARIS && current_function_calls_alloca)
5372 || (DEFAULT_ABI == ABI_DARWIN && flag_pic && current_function_uses_pic_offset_table)
5373 || info_ptr->calls_p)
5374 {
5375 info_ptr->lr_save_p = 1;
5376 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
5377 }
5378
5379 /* Determine if we need to save the condition code registers. */
5380 if (regs_ever_live[CR2_REGNO]
5381 || regs_ever_live[CR3_REGNO]
5382 || regs_ever_live[CR4_REGNO])
5383 {
5384 info_ptr->cr_save_p = 1;
5385 if (abi == ABI_V4 || abi == ABI_SOLARIS)
5386 info_ptr->cr_size = reg_size;
5387 }
5388
5389 /* If the current function calls __builtin_eh_return, then we need
5390 to allocate stack space for registers that will hold data for
5391 the exception handler. */
5392 if (current_function_calls_eh_return)
5393 {
5394 unsigned int i;
5395 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
5396 continue;
5397 ehrd_size = i * UNITS_PER_WORD;
5398 }
5399 else
5400 ehrd_size = 0;
5401
5402 /* Determine various sizes */
5403 info_ptr->reg_size = reg_size;
5404 info_ptr->fixed_size = RS6000_SAVE_AREA;
5405 info_ptr->varargs_size = RS6000_VARARGS_AREA;
5406 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
5407 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, 8);
5408 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
5409 + info_ptr->gp_size
5410 + ehrd_size
5411 + info_ptr->cr_size
5412 + info_ptr->lr_size
5413 + info_ptr->toc_size, 8);
5414 if (DEFAULT_ABI == ABI_DARWIN)
5415 info_ptr->save_size = RS6000_ALIGN (info_ptr->save_size, 16);
5416
5417 /* Calculate the offsets */
5418 switch (abi)
5419 {
5420 case ABI_NONE:
5421 default:
5422 abort ();
5423
5424 case ABI_AIX:
5425 case ABI_AIX_NODESC:
5426 case ABI_DARWIN:
5427 info_ptr->fp_save_offset = - info_ptr->fp_size;
5428 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
5429 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
5430 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
5431 info_ptr->lr_save_offset = 2*reg_size;
5432 break;
5433
5434 case ABI_V4:
5435 case ABI_SOLARIS:
5436 info_ptr->fp_save_offset = - info_ptr->fp_size;
5437 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
5438 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
5439 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
5440 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
5441 info_ptr->lr_save_offset = reg_size;
5442 break;
5443 }
5444
5445 total_raw_size = (info_ptr->vars_size
5446 + info_ptr->parm_size
5447 + info_ptr->save_size
5448 + info_ptr->varargs_size
5449 + info_ptr->fixed_size);
5450
5451 info_ptr->total_size = RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT);
5452
5453 /* Determine if we need to allocate any stack frame:
5454
5455 For AIX we need to push the stack if a frame pointer is needed (because
5456 the stack might be dynamically adjusted), if we are debugging, if we
5457 make calls, or if the sum of fp_save, gp_save, and local variables
5458 are more than the space needed to save all non-volatile registers:
5459 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 + 18*8 = 288 (GPR13 reserved).
5460
5461 For V.4 we don't have the stack cushion that AIX uses, but assume that
5462 the debugger can handle stackless frames. */
5463
5464 if (info_ptr->calls_p)
5465 info_ptr->push_p = 1;
5466
5467 else if (abi == ABI_V4 || abi == ABI_SOLARIS)
5468 info_ptr->push_p = (total_raw_size > info_ptr->fixed_size
5469 || info_ptr->calls_p);
5470
5471 else
5472 info_ptr->push_p = (frame_pointer_needed
5473 || (abi != ABI_DARWIN && write_symbols != NO_DEBUG)
5474 || ((total_raw_size - info_ptr->fixed_size)
5475 > (TARGET_32BIT ? 220 : 288)));
5476
5477 /* Zero offsets if we're not saving those registers */
5478 if (info_ptr->fp_size == 0)
5479 info_ptr->fp_save_offset = 0;
5480
5481 if (info_ptr->gp_size == 0)
5482 info_ptr->gp_save_offset = 0;
5483
5484 if (! info_ptr->lr_save_p)
5485 info_ptr->lr_save_offset = 0;
5486
5487 if (! info_ptr->cr_save_p)
5488 info_ptr->cr_save_offset = 0;
5489
5490 if (! info_ptr->toc_save_p)
5491 info_ptr->toc_save_offset = 0;
5492
5493 return info_ptr;
5494 }
5495
5496 void
5497 debug_stack_info (info)
5498 rs6000_stack_t *info;
5499 {
5500 const char *abi_string;
5501
5502 if (! info)
5503 info = rs6000_stack_info ();
5504
5505 fprintf (stderr, "\nStack information for function %s:\n",
5506 ((current_function_decl && DECL_NAME (current_function_decl))
5507 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
5508 : "<unknown>"));
5509
5510 switch (info->abi)
5511 {
5512 default: abi_string = "Unknown"; break;
5513 case ABI_NONE: abi_string = "NONE"; break;
5514 case ABI_AIX: abi_string = "AIX"; break;
5515 case ABI_AIX_NODESC: abi_string = "AIX"; break;
5516 case ABI_DARWIN: abi_string = "Darwin"; break;
5517 case ABI_V4: abi_string = "V.4"; break;
5518 case ABI_SOLARIS: abi_string = "Solaris"; break;
5519 }
5520
5521 fprintf (stderr, "\tABI = %5s\n", abi_string);
5522
5523 if (info->first_gp_reg_save != 32)
5524 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
5525
5526 if (info->first_fp_reg_save != 64)
5527 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
5528
5529 if (info->lr_save_p)
5530 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
5531
5532 if (info->cr_save_p)
5533 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
5534
5535 if (info->toc_save_p)
5536 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
5537
5538 if (info->push_p)
5539 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
5540
5541 if (info->calls_p)
5542 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
5543
5544 if (info->gp_save_offset)
5545 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
5546
5547 if (info->fp_save_offset)
5548 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
5549
5550 if (info->lr_save_offset)
5551 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
5552
5553 if (info->cr_save_offset)
5554 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
5555
5556 if (info->toc_save_offset)
5557 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
5558
5559 if (info->varargs_save_offset)
5560 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
5561
5562 if (info->total_size)
5563 fprintf (stderr, "\ttotal_size = %5d\n", info->total_size);
5564
5565 if (info->varargs_size)
5566 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
5567
5568 if (info->vars_size)
5569 fprintf (stderr, "\tvars_size = %5d\n", info->vars_size);
5570
5571 if (info->parm_size)
5572 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
5573
5574 if (info->fixed_size)
5575 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
5576
5577 if (info->gp_size)
5578 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
5579
5580 if (info->fp_size)
5581 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
5582
5583 if (info->lr_size)
5584 fprintf (stderr, "\tlr_size = %5d\n", info->cr_size);
5585
5586 if (info->cr_size)
5587 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
5588
5589 if (info->toc_size)
5590 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
5591
5592 if (info->save_size)
5593 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
5594
5595 if (info->reg_size != 4)
5596 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
5597
5598 fprintf (stderr, "\n");
5599 }
5600
5601 rtx
5602 rs6000_return_addr (count, frame)
5603 int count;
5604 rtx frame;
5605 {
5606 /* Currently we don't optimize very well between prolog and body code and
5607 for PIC code the code can be actually quite bad, so don't try to be
5608 too clever here. */
5609 if (count != 0
5610 || flag_pic != 0
5611 || DEFAULT_ABI == ABI_AIX
5612 || DEFAULT_ABI == ABI_AIX_NODESC)
5613 {
5614 cfun->machine->ra_needs_full_frame = 1;
5615 return
5616 gen_rtx_MEM (Pmode,
5617 memory_address (Pmode,
5618 plus_constant (copy_to_reg (gen_rtx_MEM (Pmode,
5619 memory_address (Pmode, frame))),
5620 RETURN_ADDRESS_OFFSET)));
5621 }
5622
5623 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
5624 }
5625
5626 static int
5627 rs6000_ra_ever_killed ()
5628 {
5629 rtx top;
5630
5631 #ifdef ASM_OUTPUT_MI_THUNK
5632 if (current_function_is_thunk)
5633 return 0;
5634 #endif
5635 if (!has_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM)
5636 || cfun->machine->ra_needs_full_frame)
5637 return regs_ever_live[LINK_REGISTER_REGNUM];
5638
5639 push_topmost_sequence ();
5640 top = get_insns ();
5641 pop_topmost_sequence ();
5642
5643 return reg_set_between_p (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
5644 top, NULL_RTX);
5645 }
5646 \f
5647 /* Add a REG_MAYBE_DEAD note to the insn. */
5648 static void
5649 rs6000_maybe_dead (insn)
5650 rtx insn;
5651 {
5652 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5653 const0_rtx,
5654 REG_NOTES (insn));
5655 }
5656
5657 /* Emit instructions needed to load the TOC register.
5658 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
5659 a constant pool; or for SVR4 -fpic. */
5660
5661 void
5662 rs6000_emit_load_toc_table (fromprolog)
5663 int fromprolog;
5664 {
5665 rtx dest;
5666 dest = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
5667
5668 if (TARGET_ELF && DEFAULT_ABI != ABI_AIX)
5669 {
5670 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5671 && flag_pic == 1)
5672 {
5673 rtx temp = (fromprolog
5674 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
5675 : gen_reg_rtx (Pmode));
5676 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp)));
5677 rs6000_maybe_dead (emit_move_insn (dest, temp));
5678 }
5679 else if (flag_pic == 2)
5680 {
5681 char buf[30];
5682 rtx tempLR = (fromprolog
5683 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
5684 : gen_reg_rtx (Pmode));
5685 rtx temp0 = (fromprolog
5686 ? gen_rtx_REG (Pmode, 0)
5687 : gen_reg_rtx (Pmode));
5688 rtx symF;
5689
5690 /* possibly create the toc section */
5691 if (! toc_initialized)
5692 {
5693 toc_section ();
5694 function_section (current_function_decl);
5695 }
5696
5697 if (fromprolog)
5698 {
5699 rtx symL;
5700
5701 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
5702 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
5703
5704 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
5705 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
5706
5707 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
5708 symF)));
5709 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
5710 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
5711 symL,
5712 symF)));
5713 }
5714 else
5715 {
5716 rtx tocsym;
5717 static int reload_toc_labelno = 0;
5718
5719 tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
5720
5721 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
5722 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
5723
5724 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR,
5725 symF,
5726 tocsym)));
5727 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
5728 rs6000_maybe_dead (emit_move_insn (temp0,
5729 gen_rtx_MEM (Pmode, dest)));
5730 }
5731 rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest)));
5732 }
5733 else if (flag_pic == 0 && TARGET_MINIMAL_TOC)
5734 {
5735 /* This is for AIX code running in non-PIC ELF. */
5736 char buf[30];
5737 rtx realsym;
5738 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
5739 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
5740
5741 rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym)));
5742 rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym)));
5743 }
5744 else
5745 abort();
5746 }
5747 else
5748 {
5749 if (TARGET_32BIT)
5750 rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest)));
5751 else
5752 rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest)));
5753 }
5754 }
5755
5756 int
5757 get_TOC_alias_set ()
5758 {
5759 static int set = -1;
5760 if (set == -1)
5761 set = new_alias_set ();
5762 return set;
5763 }
5764
5765 /* This retuns nonzero if the current function uses the TOC. This is
5766 determined by the presence of (unspec ... 7), which is generated by
5767 the various load_toc_* patterns. */
5768 int
5769 uses_TOC ()
5770 {
5771 rtx insn;
5772
5773 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5774 if (INSN_P (insn))
5775 {
5776 rtx pat = PATTERN (insn);
5777 int i;
5778
5779 if (GET_CODE (pat) == PARALLEL)
5780 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
5781 if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC
5782 && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == 7)
5783 return 1;
5784 }
5785 return 0;
5786 }
5787
5788 rtx
5789 create_TOC_reference(symbol)
5790 rtx symbol;
5791 {
5792 return gen_rtx_PLUS (Pmode,
5793 gen_rtx_REG (Pmode, TOC_REGISTER),
5794 gen_rtx_CONST (Pmode,
5795 gen_rtx_MINUS (Pmode, symbol,
5796 gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name)))));
5797 }
5798
5799 #if TARGET_AIX
5800 /* __throw will restore its own return address to be the same as the
5801 return address of the function that the throw is being made to.
5802 This is unfortunate, because we want to check the original
5803 return address to see if we need to restore the TOC.
5804 So we have to squirrel it away here.
5805 This is used only in compiling __throw and __rethrow.
5806
5807 Most of this code should be removed by CSE. */
5808 static rtx insn_after_throw;
5809
5810 /* This does the saving... */
5811 void
5812 rs6000_aix_emit_builtin_unwind_init ()
5813 {
5814 rtx mem;
5815 rtx stack_top = gen_reg_rtx (Pmode);
5816 rtx opcode_addr = gen_reg_rtx (Pmode);
5817
5818 insn_after_throw = gen_reg_rtx (SImode);
5819
5820 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
5821 emit_move_insn (stack_top, mem);
5822
5823 mem = gen_rtx_MEM (Pmode,
5824 gen_rtx_PLUS (Pmode, stack_top,
5825 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
5826 emit_move_insn (opcode_addr, mem);
5827 emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr));
5828 }
5829
5830 /* Emit insns to _restore_ the TOC register, at runtime (specifically in _eh.o).
5831 Only used on AIX.
5832
5833 The idea is that on AIX, function calls look like this:
5834 bl somefunction-trampoline
5835 lwz r2,20(sp)
5836
5837 and later,
5838 somefunction-trampoline:
5839 stw r2,20(sp)
5840 ... load function address in the count register ...
5841 bctr
5842 or like this, if the linker determines that this is not a cross-module call
5843 and so the TOC need not be restored:
5844 bl somefunction
5845 nop
5846 or like this, if the compiler could determine that this is not a
5847 cross-module call:
5848 bl somefunction
5849 now, the tricky bit here is that register 2 is saved and restored
5850 by the _linker_, so we can't readily generate debugging information
5851 for it. So we need to go back up the call chain looking at the
5852 insns at return addresses to see which calls saved the TOC register
5853 and so see where it gets restored from.
5854
5855 Oh, and all this gets done in RTL inside the eh_epilogue pattern,
5856 just before the actual epilogue.
5857
5858 On the bright side, this incurs no space or time overhead unless an
5859 exception is thrown, except for the extra code in libgcc.a.
5860
5861 The parameter STACKSIZE is a register containing (at runtime)
5862 the amount to be popped off the stack in addition to the stack frame
5863 of this routine (which will be __throw or __rethrow, and so is
5864 guaranteed to have a stack frame). */
5865 void
5866 rs6000_emit_eh_toc_restore (stacksize)
5867 rtx stacksize;
5868 {
5869 rtx top_of_stack;
5870 rtx bottom_of_stack = gen_reg_rtx (Pmode);
5871 rtx tocompare = gen_reg_rtx (SImode);
5872 rtx opcode = gen_reg_rtx (SImode);
5873 rtx opcode_addr = gen_reg_rtx (Pmode);
5874 rtx mem;
5875 rtx loop_start = gen_label_rtx ();
5876 rtx no_toc_restore_needed = gen_label_rtx ();
5877 rtx loop_exit = gen_label_rtx ();
5878
5879 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
5880 set_mem_alias_set (mem, rs6000_sr_alias_set);
5881 emit_move_insn (bottom_of_stack, mem);
5882
5883 top_of_stack = expand_binop (Pmode, add_optab,
5884 bottom_of_stack, stacksize,
5885 NULL_RTX, 1, OPTAB_WIDEN);
5886
5887 emit_move_insn (tocompare,
5888 GEN_INT (trunc_int_for_mode (TARGET_32BIT
5889 ? 0x80410014
5890 : 0xE8410028, SImode)));
5891
5892 if (insn_after_throw == NULL_RTX)
5893 abort();
5894 emit_move_insn (opcode, insn_after_throw);
5895
5896 emit_note (NULL, NOTE_INSN_LOOP_BEG);
5897 emit_label (loop_start);
5898
5899 do_compare_rtx_and_jump (opcode, tocompare, NE, 1,
5900 SImode, NULL_RTX, 0, NULL_RTX,
5901 no_toc_restore_needed);
5902
5903 mem = gen_rtx_MEM (Pmode,
5904 gen_rtx_PLUS (Pmode, bottom_of_stack,
5905 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
5906 emit_move_insn (gen_rtx_REG (Pmode, 2), mem);
5907
5908 emit_label (no_toc_restore_needed);
5909 do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1,
5910 Pmode, NULL_RTX, 0, NULL_RTX,
5911 loop_exit);
5912
5913 mem = gen_rtx_MEM (Pmode, bottom_of_stack);
5914 set_mem_alias_set (mem, rs6000_sr_alias_set);
5915 emit_move_insn (bottom_of_stack, mem);
5916
5917 mem = gen_rtx_MEM (Pmode,
5918 gen_rtx_PLUS (Pmode, bottom_of_stack,
5919 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
5920 emit_move_insn (opcode_addr, mem);
5921 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
5922
5923 emit_note (NULL, NOTE_INSN_LOOP_CONT);
5924 emit_jump (loop_start);
5925 emit_note (NULL, NOTE_INSN_LOOP_END);
5926 emit_label (loop_exit);
5927 }
5928 #endif /* TARGET_AIX */
5929 \f
5930 /* This ties together stack memory (MEM with an alias set of
5931 rs6000_sr_alias_set) and the change to the stack pointer. */
5932
5933 static void
5934 rs6000_emit_stack_tie ()
5935 {
5936 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
5937
5938 set_mem_alias_set (mem, rs6000_sr_alias_set);
5939 emit_insn (gen_stack_tie (mem));
5940 }
5941
5942 /* Emit the correct code for allocating stack space, as insns.
5943 If COPY_R12, make sure a copy of the old frame is left in r12.
5944 The generated code may use hard register 0 as a temporary. */
5945
5946 static void
5947 rs6000_emit_allocate_stack (size, copy_r12)
5948 HOST_WIDE_INT size;
5949 int copy_r12;
5950 {
5951 rtx insn;
5952 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
5953 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
5954 rtx todec = GEN_INT (-size);
5955
5956 if (current_function_limit_stack)
5957 {
5958 if (REG_P (stack_limit_rtx)
5959 && REGNO (stack_limit_rtx) > 1
5960 && REGNO (stack_limit_rtx) <= 31)
5961 {
5962 emit_insn (Pmode == SImode
5963 ? gen_addsi3 (tmp_reg,
5964 stack_limit_rtx,
5965 GEN_INT (size))
5966 : gen_adddi3 (tmp_reg,
5967 stack_limit_rtx,
5968 GEN_INT (size)));
5969
5970 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
5971 const0_rtx));
5972 }
5973 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
5974 && TARGET_32BIT
5975 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS))
5976 {
5977 rtx toload = gen_rtx_CONST (VOIDmode,
5978 gen_rtx_PLUS (Pmode,
5979 stack_limit_rtx,
5980 GEN_INT (size)));
5981
5982 emit_insn (gen_elf_high (tmp_reg, toload));
5983 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
5984 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
5985 const0_rtx));
5986 }
5987 else
5988 warning ("stack limit expression is not supported");
5989 }
5990
5991 if (copy_r12 || ! TARGET_UPDATE)
5992 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
5993
5994 if (TARGET_UPDATE)
5995 {
5996 if (size > 32767)
5997 {
5998 /* Need a note here so that try_split doesn't get confused. */
5999 if (get_last_insn() == NULL_RTX)
6000 emit_note (0, NOTE_INSN_DELETED);
6001 insn = emit_move_insn (tmp_reg, todec);
6002 try_split (PATTERN (insn), insn, 0);
6003 todec = tmp_reg;
6004 }
6005
6006 if (Pmode == SImode)
6007 insn = emit_insn (gen_movsi_update (stack_reg, stack_reg,
6008 todec, stack_reg));
6009 else
6010 insn = emit_insn (gen_movdi_update (stack_reg, stack_reg,
6011 todec, stack_reg));
6012 }
6013 else
6014 {
6015 if (Pmode == SImode)
6016 insn = emit_insn (gen_addsi3 (stack_reg, stack_reg, todec));
6017 else
6018 insn = emit_insn (gen_adddi3 (stack_reg, stack_reg, todec));
6019 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
6020 gen_rtx_REG (Pmode, 12));
6021 }
6022
6023 RTX_FRAME_RELATED_P (insn) = 1;
6024 REG_NOTES (insn) =
6025 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6026 gen_rtx_SET (VOIDmode, stack_reg,
6027 gen_rtx_PLUS (Pmode, stack_reg,
6028 GEN_INT (-size))),
6029 REG_NOTES (insn));
6030 }
6031
6032 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced with
6033 (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 is not
6034 NULL.
6035 It would be nice if dwarf2out_frame_debug_expr could deduce these
6036 equivalences by itself so it wasn't necessary to hold its hand so much. */
6037
6038 static void
6039 rs6000_frame_related (insn, reg, val, reg2, rreg)
6040 rtx insn;
6041 rtx reg;
6042 HOST_WIDE_INT val;
6043 rtx reg2;
6044 rtx rreg;
6045 {
6046 rtx real, temp;
6047
6048 real = copy_rtx (PATTERN (insn));
6049
6050 real = replace_rtx (real, reg,
6051 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
6052 STACK_POINTER_REGNUM),
6053 GEN_INT (val)));
6054
6055 /* We expect that 'real' is either a SET or a PARALLEL containing
6056 SETs (and possibly other stuff). In a PARALLEL, all the SETs
6057 are important so they all have to be marked RTX_FRAME_RELATED_P. */
6058
6059 if (GET_CODE (real) == SET)
6060 {
6061 rtx set = real;
6062
6063 temp = simplify_rtx (SET_SRC (set));
6064 if (temp)
6065 SET_SRC (set) = temp;
6066 temp = simplify_rtx (SET_DEST (set));
6067 if (temp)
6068 SET_DEST (set) = temp;
6069 if (GET_CODE (SET_DEST (set)) == MEM)
6070 {
6071 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
6072 if (temp)
6073 XEXP (SET_DEST (set), 0) = temp;
6074 }
6075 }
6076 else if (GET_CODE (real) == PARALLEL)
6077 {
6078 int i;
6079 for (i = 0; i < XVECLEN (real, 0); i++)
6080 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
6081 {
6082 rtx set = XVECEXP (real, 0, i);
6083
6084 temp = simplify_rtx (SET_SRC (set));
6085 if (temp)
6086 SET_SRC (set) = temp;
6087 temp = simplify_rtx (SET_DEST (set));
6088 if (temp)
6089 SET_DEST (set) = temp;
6090 if (GET_CODE (SET_DEST (set)) == MEM)
6091 {
6092 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
6093 if (temp)
6094 XEXP (SET_DEST (set), 0) = temp;
6095 }
6096 RTX_FRAME_RELATED_P (set) = 1;
6097 }
6098 }
6099 else
6100 abort();
6101
6102 if (reg2 != NULL_RTX)
6103 real = replace_rtx (real, reg2, rreg);
6104
6105 RTX_FRAME_RELATED_P (insn) = 1;
6106 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6107 real,
6108 REG_NOTES (insn));
6109 }
6110
6111 /* Emit function prologue as insns. */
6112
6113 void
6114 rs6000_emit_prologue ()
6115 {
6116 rs6000_stack_t *info = rs6000_stack_info ();
6117 enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode;
6118 int reg_size = TARGET_POWERPC64 ? 8 : 4;
6119 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
6120 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
6121 rtx frame_reg_rtx = sp_reg_rtx;
6122 rtx cr_save_rtx = NULL;
6123 rtx insn;
6124 int saving_FPRs_inline;
6125 int using_store_multiple;
6126 HOST_WIDE_INT sp_offset = 0;
6127
6128 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
6129 && info->first_gp_reg_save < 31);
6130 saving_FPRs_inline = (info->first_fp_reg_save == 64
6131 || FP_SAVE_INLINE (info->first_fp_reg_save));
6132
6133 /* For V.4, update stack before we do any saving and set back pointer. */
6134 if (info->push_p && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS))
6135 {
6136 if (info->total_size < 32767)
6137 sp_offset = info->total_size;
6138 else
6139 frame_reg_rtx = frame_ptr_rtx;
6140 rs6000_emit_allocate_stack (info->total_size,
6141 (frame_reg_rtx != sp_reg_rtx
6142 && (info->cr_save_p
6143 || info->lr_save_p
6144 || info->first_fp_reg_save < 64
6145 || info->first_gp_reg_save < 32
6146 )));
6147 if (frame_reg_rtx != sp_reg_rtx)
6148 rs6000_emit_stack_tie ();
6149 }
6150
6151 /* If we use the link register, get it into r0. */
6152 if (info->lr_save_p)
6153 emit_move_insn (gen_rtx_REG (Pmode, 0),
6154 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
6155
6156 /* If we need to save CR, put it into r12. */
6157 if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
6158 {
6159 cr_save_rtx = gen_rtx_REG (SImode, 12);
6160 emit_insn (gen_movesi_from_cr (cr_save_rtx));
6161 }
6162
6163 /* Do any required saving of fpr's. If only one or two to save, do it
6164 ourself. Otherwise, call function. */
6165 if (saving_FPRs_inline)
6166 {
6167 int i;
6168 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
6169 if ((regs_ever_live[info->first_fp_reg_save+i]
6170 && ! call_used_regs[info->first_fp_reg_save+i]))
6171 {
6172 rtx addr, reg, mem;
6173 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
6174 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6175 GEN_INT (info->fp_save_offset
6176 + sp_offset
6177 + 8*i));
6178 mem = gen_rtx_MEM (DFmode, addr);
6179 set_mem_alias_set (mem, rs6000_sr_alias_set);
6180
6181 insn = emit_move_insn (mem, reg);
6182 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
6183 NULL_RTX, NULL_RTX);
6184 }
6185 }
6186 else if (info->first_fp_reg_save != 64)
6187 {
6188 int i;
6189 char rname[30];
6190 const char *alloc_rname;
6191 rtvec p;
6192 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
6193
6194 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
6195 gen_rtx_REG (Pmode,
6196 LINK_REGISTER_REGNUM));
6197 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
6198 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
6199 alloc_rname = ggc_strdup (rname);
6200 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
6201 gen_rtx_SYMBOL_REF (Pmode,
6202 alloc_rname));
6203 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
6204 {
6205 rtx addr, reg, mem;
6206 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
6207 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6208 GEN_INT (info->fp_save_offset
6209 + sp_offset + 8*i));
6210 mem = gen_rtx_MEM (DFmode, addr);
6211 set_mem_alias_set (mem, rs6000_sr_alias_set);
6212
6213 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
6214 }
6215 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
6216 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
6217 NULL_RTX, NULL_RTX);
6218 }
6219
6220 /* Save GPRs. This is done as a PARALLEL if we are using
6221 the store-multiple instructions. */
6222 if (using_store_multiple)
6223 {
6224 rtvec p, dwarfp;
6225 int i;
6226 p = rtvec_alloc (32 - info->first_gp_reg_save);
6227 dwarfp = rtvec_alloc (32 - info->first_gp_reg_save);
6228 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
6229 {
6230 rtx addr, reg, mem;
6231 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
6232 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6233 GEN_INT (info->gp_save_offset
6234 + sp_offset
6235 + reg_size * i));
6236 mem = gen_rtx_MEM (reg_mode, addr);
6237 set_mem_alias_set (mem, rs6000_sr_alias_set);
6238
6239 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
6240 }
6241 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
6242 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
6243 NULL_RTX, NULL_RTX);
6244 }
6245 else
6246 {
6247 int i;
6248 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
6249 if ((regs_ever_live[info->first_gp_reg_save+i]
6250 && ! call_used_regs[info->first_gp_reg_save+i])
6251 || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM
6252 && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
6253 && flag_pic == 1)
6254 || (DEFAULT_ABI == ABI_DARWIN
6255 && flag_pic))))
6256 {
6257 rtx addr, reg, mem;
6258 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
6259 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6260 GEN_INT (info->gp_save_offset
6261 + sp_offset
6262 + reg_size * i));
6263 mem = gen_rtx_MEM (reg_mode, addr);
6264 set_mem_alias_set (mem, rs6000_sr_alias_set);
6265
6266 insn = emit_move_insn (mem, reg);
6267 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
6268 NULL_RTX, NULL_RTX);
6269 }
6270 }
6271
6272 /* ??? There's no need to emit actual instructions here, but it's the
6273 easiest way to get the frame unwind information emitted. */
6274 if (current_function_calls_eh_return)
6275 {
6276 unsigned int i, regno;
6277
6278 for (i = 0; ; ++i)
6279 {
6280 rtx addr, reg, mem;
6281
6282 regno = EH_RETURN_DATA_REGNO (i);
6283 if (regno == INVALID_REGNUM)
6284 break;
6285
6286 reg = gen_rtx_REG (reg_mode, regno);
6287 addr = plus_constant (frame_reg_rtx,
6288 info->ehrd_offset + sp_offset
6289 + reg_size * (int) i);
6290 mem = gen_rtx_MEM (reg_mode, addr);
6291 set_mem_alias_set (mem, rs6000_sr_alias_set);
6292
6293 insn = emit_move_insn (mem, reg);
6294 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
6295 NULL_RTX, NULL_RTX);
6296 }
6297 }
6298
6299 /* Save lr if we used it. */
6300 if (info->lr_save_p)
6301 {
6302 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6303 GEN_INT (info->lr_save_offset + sp_offset));
6304 rtx reg = gen_rtx_REG (Pmode, 0);
6305 rtx mem = gen_rtx_MEM (Pmode, addr);
6306 /* This should not be of rs6000_sr_alias_set, because of
6307 __builtin_return_address. */
6308
6309 insn = emit_move_insn (mem, reg);
6310 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
6311 reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
6312 }
6313
6314 /* Save CR if we use any that must be preserved. */
6315 if (info->cr_save_p)
6316 {
6317 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6318 GEN_INT (info->cr_save_offset + sp_offset));
6319 rtx mem = gen_rtx_MEM (SImode, addr);
6320
6321 set_mem_alias_set (mem, rs6000_sr_alias_set);
6322
6323 /* If r12 was used to hold the original sp, copy cr into r0 now
6324 that it's free. */
6325 if (REGNO (frame_reg_rtx) == 12)
6326 {
6327 cr_save_rtx = gen_rtx_REG (SImode, 0);
6328 emit_insn (gen_movesi_from_cr (cr_save_rtx));
6329 }
6330 insn = emit_move_insn (mem, cr_save_rtx);
6331
6332 /* Now, there's no way that dwarf2out_frame_debug_expr is going
6333 to understand '(unspec:SI [(reg:CC 68) ...] 19)'. But that's
6334 OK. All we have to do is specify that _one_ condition code
6335 register is saved in this stack slot. The thrower's epilogue
6336 will then restore all the call-saved registers. */
6337 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
6338 cr_save_rtx, gen_rtx_REG (SImode, CR0_REGNO));
6339 }
6340
6341 /* Update stack and set back pointer unless this is V.4,
6342 for which it was done previously. */
6343 if (info->push_p && DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
6344 rs6000_emit_allocate_stack (info->total_size, FALSE);
6345
6346 /* Set frame pointer, if needed. */
6347 if (frame_pointer_needed)
6348 {
6349 insn = emit_move_insn (gen_rtx_REG (reg_mode, FRAME_POINTER_REGNUM),
6350 sp_reg_rtx);
6351 RTX_FRAME_RELATED_P (insn) = 1;
6352 }
6353
6354 /* If we are using PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
6355 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
6356 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
6357 && flag_pic == 1 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]))
6358 {
6359 /* If emit_load_toc_table will use the link register, we need to save
6360 it. We use R11 for this purpose because emit_load_toc_table
6361 can use register 0. This allows us to use a plain 'blr' to return
6362 from the procedure more often. */
6363 int save_LR_around_toc_setup = (TARGET_ELF && flag_pic != 0
6364 && ! info->lr_save_p
6365 && EXIT_BLOCK_PTR->pred != NULL);
6366 if (save_LR_around_toc_setup)
6367 emit_move_insn (gen_rtx_REG (Pmode, 11),
6368 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
6369
6370 rs6000_emit_load_toc_table (TRUE);
6371
6372 if (save_LR_around_toc_setup)
6373 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
6374 gen_rtx_REG (Pmode, 11));
6375 }
6376
6377 if (DEFAULT_ABI == ABI_DARWIN
6378 && flag_pic && current_function_uses_pic_offset_table)
6379 {
6380 rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
6381
6382 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest)));
6383
6384 rs6000_maybe_dead (
6385 emit_move_insn (gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM),
6386 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)));
6387 }
6388 }
6389
6390
6391 /* Write function prologue. */
6392 static void
6393 rs6000_output_function_prologue (file, size)
6394 FILE *file;
6395 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
6396 {
6397 rs6000_stack_t *info = rs6000_stack_info ();
6398
6399 if (TARGET_DEBUG_STACK)
6400 debug_stack_info (info);
6401
6402 /* Write .extern for any function we will call to save and restore fp
6403 values. */
6404 if (info->first_fp_reg_save < 64 && !FP_SAVE_INLINE (info->first_fp_reg_save))
6405 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
6406 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
6407 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
6408
6409 /* Write .extern for AIX common mode routines, if needed. */
6410 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
6411 {
6412 fputs ("\t.extern __mulh\n", file);
6413 fputs ("\t.extern __mull\n", file);
6414 fputs ("\t.extern __divss\n", file);
6415 fputs ("\t.extern __divus\n", file);
6416 fputs ("\t.extern __quoss\n", file);
6417 fputs ("\t.extern __quous\n", file);
6418 common_mode_defined = 1;
6419 }
6420
6421 if (! HAVE_prologue)
6422 {
6423 start_sequence ();
6424
6425 /* A NOTE_INSN_DELETED is supposed to be at the start
6426 and end of the "toplevel" insn chain. */
6427 emit_note (0, NOTE_INSN_DELETED);
6428 rs6000_emit_prologue ();
6429 emit_note (0, NOTE_INSN_DELETED);
6430
6431 if (TARGET_DEBUG_STACK)
6432 debug_rtx_list (get_insns(), 100);
6433 final (get_insns(), file, FALSE, FALSE);
6434 end_sequence ();
6435 }
6436
6437 rs6000_pic_labelno++;
6438 }
6439
6440 /* Emit function epilogue as insns.
6441
6442 At present, dwarf2out_frame_debug_expr doesn't understand
6443 register restores, so we don't bother setting RTX_FRAME_RELATED_P
6444 anywhere in the epilogue. Most of the insns below would in any case
6445 need special notes to explain where r11 is in relation to the stack. */
6446
6447 void
6448 rs6000_emit_epilogue (sibcall)
6449 int sibcall;
6450 {
6451 rs6000_stack_t *info;
6452 int restoring_FPRs_inline;
6453 int using_load_multiple;
6454 int using_mfcr_multiple;
6455 int use_backchain_to_restore_sp;
6456 int sp_offset = 0;
6457 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
6458 rtx frame_reg_rtx = sp_reg_rtx;
6459 enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode;
6460 int reg_size = TARGET_POWERPC64 ? 8 : 4;
6461 int i;
6462
6463 info = rs6000_stack_info ();
6464 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
6465 && info->first_gp_reg_save < 31);
6466 restoring_FPRs_inline = (sibcall
6467 || current_function_calls_eh_return
6468 || info->first_fp_reg_save == 64
6469 || FP_SAVE_INLINE (info->first_fp_reg_save));
6470 use_backchain_to_restore_sp = (frame_pointer_needed
6471 || current_function_calls_alloca
6472 || info->total_size > 32767);
6473 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
6474 || rs6000_cpu == PROCESSOR_PPC603
6475 || rs6000_cpu == PROCESSOR_PPC750
6476 || optimize_size);
6477
6478 /* If we have a frame pointer, a call to alloca, or a large stack
6479 frame, restore the old stack pointer using the backchain. Otherwise,
6480 we know what size to update it with. */
6481 if (use_backchain_to_restore_sp)
6482 {
6483 /* Under V.4, don't reset the stack pointer until after we're done
6484 loading the saved registers. */
6485 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
6486 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
6487
6488 emit_move_insn (frame_reg_rtx,
6489 gen_rtx_MEM (Pmode, sp_reg_rtx));
6490
6491 }
6492 else if (info->push_p)
6493 {
6494 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
6495 sp_offset = info->total_size;
6496 else
6497 {
6498 emit_insn (TARGET_32BIT
6499 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
6500 GEN_INT (info->total_size))
6501 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
6502 GEN_INT (info->total_size)));
6503 }
6504 }
6505
6506 /* Get the old lr if we saved it. */
6507 if (info->lr_save_p)
6508 {
6509 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6510 GEN_INT (info->lr_save_offset + sp_offset));
6511 rtx mem = gen_rtx_MEM (Pmode, addr);
6512
6513 set_mem_alias_set (mem, rs6000_sr_alias_set);
6514
6515 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
6516 }
6517
6518 /* Get the old cr if we saved it. */
6519 if (info->cr_save_p)
6520 {
6521 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6522 GEN_INT (info->cr_save_offset + sp_offset));
6523 rtx mem = gen_rtx_MEM (SImode, addr);
6524
6525 set_mem_alias_set (mem, rs6000_sr_alias_set);
6526
6527 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
6528 }
6529
6530 /* Set LR here to try to overlap restores below. */
6531 if (info->lr_save_p)
6532 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
6533 gen_rtx_REG (Pmode, 0));
6534
6535 /* Load exception handler data registers, if needed. */
6536 if (current_function_calls_eh_return)
6537 {
6538 unsigned int i, regno;
6539
6540 for (i = 0; ; ++i)
6541 {
6542 rtx addr, mem;
6543
6544 regno = EH_RETURN_DATA_REGNO (i);
6545 if (regno == INVALID_REGNUM)
6546 break;
6547
6548 addr = plus_constant (frame_reg_rtx,
6549 info->ehrd_offset + sp_offset
6550 + reg_size * (int) i);
6551 mem = gen_rtx_MEM (reg_mode, addr);
6552 set_mem_alias_set (mem, rs6000_sr_alias_set);
6553
6554 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
6555 }
6556 }
6557
6558 /* Restore GPRs. This is done as a PARALLEL if we are using
6559 the load-multiple instructions. */
6560 if (using_load_multiple)
6561 {
6562 rtvec p;
6563 p = rtvec_alloc (32 - info->first_gp_reg_save);
6564 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
6565 {
6566 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6567 GEN_INT (info->gp_save_offset
6568 + sp_offset
6569 + reg_size * i));
6570 rtx mem = gen_rtx_MEM (reg_mode, addr);
6571
6572 set_mem_alias_set (mem, rs6000_sr_alias_set);
6573
6574 RTVEC_ELT (p, i) =
6575 gen_rtx_SET (VOIDmode,
6576 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
6577 mem);
6578 }
6579 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
6580 }
6581 else
6582 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
6583 if ((regs_ever_live[info->first_gp_reg_save+i]
6584 && ! call_used_regs[info->first_gp_reg_save+i])
6585 || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM
6586 && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
6587 && flag_pic == 1)
6588 || (DEFAULT_ABI == ABI_DARWIN
6589 && flag_pic))))
6590 {
6591 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6592 GEN_INT (info->gp_save_offset
6593 + sp_offset
6594 + reg_size * i));
6595 rtx mem = gen_rtx_MEM (reg_mode, addr);
6596
6597 set_mem_alias_set (mem, rs6000_sr_alias_set);
6598
6599 emit_move_insn (gen_rtx_REG (reg_mode,
6600 info->first_gp_reg_save + i),
6601 mem);
6602 }
6603
6604 /* Restore fpr's if we need to do it without calling a function. */
6605 if (restoring_FPRs_inline)
6606 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
6607 if ((regs_ever_live[info->first_fp_reg_save+i]
6608 && ! call_used_regs[info->first_fp_reg_save+i]))
6609 {
6610 rtx addr, mem;
6611 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6612 GEN_INT (info->fp_save_offset
6613 + sp_offset
6614 + 8*i));
6615 mem = gen_rtx_MEM (DFmode, addr);
6616 set_mem_alias_set (mem, rs6000_sr_alias_set);
6617
6618 emit_move_insn (gen_rtx_REG (DFmode,
6619 info->first_fp_reg_save + i),
6620 mem);
6621 }
6622
6623 /* If we saved cr, restore it here. Just those that were used. */
6624 if (info->cr_save_p)
6625 {
6626 rtx r12_rtx = gen_rtx_REG (SImode, 12);
6627 int count = 0;
6628
6629 if (using_mfcr_multiple)
6630 {
6631 for (i = 0; i < 8; i++)
6632 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
6633 count++;
6634 if (count == 0)
6635 abort ();
6636 }
6637
6638 if (using_mfcr_multiple && count > 1)
6639 {
6640 rtvec p;
6641 int ndx;
6642
6643 p = rtvec_alloc (count);
6644
6645 ndx = 0;
6646 for (i = 0; i < 8; i++)
6647 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
6648 {
6649 rtvec r = rtvec_alloc (2);
6650 RTVEC_ELT (r, 0) = r12_rtx;
6651 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
6652 RTVEC_ELT (p, ndx) =
6653 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
6654 gen_rtx_UNSPEC (CCmode, r, 20));
6655 ndx++;
6656 }
6657 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
6658 if (ndx != count)
6659 abort ();
6660 }
6661 else
6662 for (i = 0; i < 8; i++)
6663 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
6664 {
6665 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
6666 CR0_REGNO+i),
6667 r12_rtx));
6668 }
6669 }
6670
6671 /* If this is V.4, unwind the stack pointer after all of the loads
6672 have been done. We need to emit a block here so that sched
6673 doesn't decide to move the sp change before the register restores
6674 (which may not have any obvious dependency on the stack). This
6675 doesn't hurt performance, because there is no scheduling that can
6676 be done after this point. */
6677 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
6678 {
6679 if (frame_reg_rtx != sp_reg_rtx)
6680 rs6000_emit_stack_tie ();
6681
6682 if (use_backchain_to_restore_sp)
6683 {
6684 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
6685 }
6686 else if (sp_offset != 0)
6687 {
6688 emit_insn (Pmode == SImode
6689 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
6690 GEN_INT (sp_offset))
6691 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
6692 GEN_INT (sp_offset)));
6693 }
6694 }
6695
6696 if (current_function_calls_eh_return)
6697 {
6698 rtx sa = EH_RETURN_STACKADJ_RTX;
6699 emit_insn (Pmode == SImode
6700 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
6701 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
6702 }
6703
6704 if (!sibcall)
6705 {
6706 rtvec p;
6707 if (! restoring_FPRs_inline)
6708 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
6709 else
6710 p = rtvec_alloc (2);
6711
6712 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
6713 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
6714 gen_rtx_REG (Pmode,
6715 LINK_REGISTER_REGNUM));
6716
6717 /* If we have to restore more than two FP registers, branch to the
6718 restore function. It will return to our caller. */
6719 if (! restoring_FPRs_inline)
6720 {
6721 int i;
6722 char rname[30];
6723 const char *alloc_rname;
6724
6725 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
6726 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
6727 alloc_rname = ggc_strdup (rname);
6728 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
6729 gen_rtx_SYMBOL_REF (Pmode,
6730 alloc_rname));
6731
6732 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
6733 {
6734 rtx addr, mem;
6735 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
6736 GEN_INT (info->fp_save_offset + 8*i));
6737 mem = gen_rtx_MEM (DFmode, addr);
6738 set_mem_alias_set (mem, rs6000_sr_alias_set);
6739
6740 RTVEC_ELT (p, i+3) =
6741 gen_rtx_SET (VOIDmode,
6742 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
6743 mem);
6744 }
6745 }
6746
6747 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
6748 }
6749 }
6750
6751 /* Write function epilogue. */
6752
6753 static void
6754 rs6000_output_function_epilogue (file, size)
6755 FILE *file;
6756 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
6757 {
6758 rs6000_stack_t *info = rs6000_stack_info ();
6759
6760 if (! HAVE_epilogue)
6761 {
6762 rtx insn = get_last_insn ();
6763 /* If the last insn was a BARRIER, we don't have to write anything except
6764 the trace table. */
6765 if (GET_CODE (insn) == NOTE)
6766 insn = prev_nonnote_insn (insn);
6767 if (insn == 0 || GET_CODE (insn) != BARRIER)
6768 {
6769 /* This is slightly ugly, but at least we don't have two
6770 copies of the epilogue-emitting code. */
6771 start_sequence ();
6772
6773 /* A NOTE_INSN_DELETED is supposed to be at the start
6774 and end of the "toplevel" insn chain. */
6775 emit_note (0, NOTE_INSN_DELETED);
6776 rs6000_emit_epilogue (FALSE);
6777 emit_note (0, NOTE_INSN_DELETED);
6778
6779 if (TARGET_DEBUG_STACK)
6780 debug_rtx_list (get_insns(), 100);
6781 final (get_insns(), file, FALSE, FALSE);
6782 end_sequence ();
6783 }
6784 }
6785
6786 /* Output a traceback table here. See /usr/include/sys/debug.h for info
6787 on its format.
6788
6789 We don't output a traceback table if -finhibit-size-directive was
6790 used. The documentation for -finhibit-size-directive reads
6791 ``don't output a @code{.size} assembler directive, or anything
6792 else that would cause trouble if the function is split in the
6793 middle, and the two halves are placed at locations far apart in
6794 memory.'' The traceback table has this property, since it
6795 includes the offset from the start of the function to the
6796 traceback table itself.
6797
6798 System V.4 Powerpc's (and the embedded ABI derived from it) use a
6799 different traceback table. */
6800 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive)
6801 {
6802 const char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6803 int fixed_parms, float_parms, parm_info;
6804 int i;
6805
6806 while (*fname == '.') /* V.4 encodes . in the name */
6807 fname++;
6808
6809 /* Need label immediately before tbtab, so we can compute its offset
6810 from the function start. */
6811 if (*fname == '*')
6812 ++fname;
6813 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
6814 ASM_OUTPUT_LABEL (file, fname);
6815
6816 /* The .tbtab pseudo-op can only be used for the first eight
6817 expressions, since it can't handle the possibly variable
6818 length fields that follow. However, if you omit the optional
6819 fields, the assembler outputs zeros for all optional fields
6820 anyways, giving each variable length field is minimum length
6821 (as defined in sys/debug.h). Thus we can not use the .tbtab
6822 pseudo-op at all. */
6823
6824 /* An all-zero word flags the start of the tbtab, for debuggers
6825 that have to find it by searching forward from the entry
6826 point or from the current pc. */
6827 fputs ("\t.long 0\n", file);
6828
6829 /* Tbtab format type. Use format type 0. */
6830 fputs ("\t.byte 0,", file);
6831
6832 /* Language type. Unfortunately, there doesn't seem to be any
6833 official way to get this info, so we use language_string. C
6834 is 0. C++ is 9. No number defined for Obj-C, so use the
6835 value for C for now. There is no official value for Java,
6836 although IBM appears to be using 13. There is no official value
6837 for Chill, so we've choosen 44 pseudo-randomly. */
6838 if (! strcmp (language_string, "GNU C")
6839 || ! strcmp (language_string, "GNU Objective-C"))
6840 i = 0;
6841 else if (! strcmp (language_string, "GNU F77"))
6842 i = 1;
6843 else if (! strcmp (language_string, "GNU Ada"))
6844 i = 3;
6845 else if (! strcmp (language_string, "GNU Pascal"))
6846 i = 2;
6847 else if (! strcmp (language_string, "GNU C++"))
6848 i = 9;
6849 else if (! strcmp (language_string, "GNU Java"))
6850 i = 13;
6851 else if (! strcmp (language_string, "GNU CHILL"))
6852 i = 44;
6853 else
6854 abort ();
6855 fprintf (file, "%d,", i);
6856
6857 /* 8 single bit fields: global linkage (not set for C extern linkage,
6858 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
6859 from start of procedure stored in tbtab, internal function, function
6860 has controlled storage, function has no toc, function uses fp,
6861 function logs/aborts fp operations. */
6862 /* Assume that fp operations are used if any fp reg must be saved. */
6863 fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1));
6864
6865 /* 6 bitfields: function is interrupt handler, name present in
6866 proc table, function calls alloca, on condition directives
6867 (controls stack walks, 3 bits), saves condition reg, saves
6868 link reg. */
6869 /* The `function calls alloca' bit seems to be set whenever reg 31 is
6870 set up as a frame pointer, even when there is no alloca call. */
6871 fprintf (file, "%d,",
6872 ((1 << 6) | (frame_pointer_needed << 5)
6873 | (info->cr_save_p << 1) | (info->lr_save_p)));
6874
6875 /* 3 bitfields: saves backchain, spare bit, number of fpr saved
6876 (6 bits). */
6877 fprintf (file, "%d,",
6878 (info->push_p << 7) | (64 - info->first_fp_reg_save));
6879
6880 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
6881 fprintf (file, "%d,", (32 - first_reg_to_save ()));
6882
6883 {
6884 /* Compute the parameter info from the function decl argument
6885 list. */
6886 tree decl;
6887 int next_parm_info_bit;
6888
6889 next_parm_info_bit = 31;
6890 parm_info = 0;
6891 fixed_parms = 0;
6892 float_parms = 0;
6893
6894 for (decl = DECL_ARGUMENTS (current_function_decl);
6895 decl; decl = TREE_CHAIN (decl))
6896 {
6897 rtx parameter = DECL_INCOMING_RTL (decl);
6898 enum machine_mode mode = GET_MODE (parameter);
6899
6900 if (GET_CODE (parameter) == REG)
6901 {
6902 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
6903 {
6904 int bits;
6905
6906 float_parms++;
6907
6908 if (mode == SFmode)
6909 bits = 0x2;
6910 else if (mode == DFmode)
6911 bits = 0x3;
6912 else
6913 abort ();
6914
6915 /* If only one bit will fit, don't or in this entry. */
6916 if (next_parm_info_bit > 0)
6917 parm_info |= (bits << (next_parm_info_bit - 1));
6918 next_parm_info_bit -= 2;
6919 }
6920 else
6921 {
6922 fixed_parms += ((GET_MODE_SIZE (mode)
6923 + (UNITS_PER_WORD - 1))
6924 / UNITS_PER_WORD);
6925 next_parm_info_bit -= 1;
6926 }
6927 }
6928 }
6929 }
6930
6931 /* Number of fixed point parameters. */
6932 /* This is actually the number of words of fixed point parameters; thus
6933 an 8 byte struct counts as 2; and thus the maximum value is 8. */
6934 fprintf (file, "%d,", fixed_parms);
6935
6936 /* 2 bitfields: number of floating point parameters (7 bits), parameters
6937 all on stack. */
6938 /* This is actually the number of fp registers that hold parameters;
6939 and thus the maximum value is 13. */
6940 /* Set parameters on stack bit if parameters are not in their original
6941 registers, regardless of whether they are on the stack? Xlc
6942 seems to set the bit when not optimizing. */
6943 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
6944
6945 /* Optional fields follow. Some are variable length. */
6946
6947 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
6948 11 double float. */
6949 /* There is an entry for each parameter in a register, in the order that
6950 they occur in the parameter list. Any intervening arguments on the
6951 stack are ignored. If the list overflows a long (max possible length
6952 34 bits) then completely leave off all elements that don't fit. */
6953 /* Only emit this long if there was at least one parameter. */
6954 if (fixed_parms || float_parms)
6955 fprintf (file, "\t.long %d\n", parm_info);
6956
6957 /* Offset from start of code to tb table. */
6958 fputs ("\t.long ", file);
6959 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
6960 #if TARGET_AIX
6961 RS6000_OUTPUT_BASENAME (file, fname);
6962 #else
6963 assemble_name (file, fname);
6964 #endif
6965 fputs ("-.", file);
6966 #if TARGET_AIX
6967 RS6000_OUTPUT_BASENAME (file, fname);
6968 #else
6969 assemble_name (file, fname);
6970 #endif
6971 putc ('\n', file);
6972
6973 /* Interrupt handler mask. */
6974 /* Omit this long, since we never set the interrupt handler bit
6975 above. */
6976
6977 /* Number of CTL (controlled storage) anchors. */
6978 /* Omit this long, since the has_ctl bit is never set above. */
6979
6980 /* Displacement into stack of each CTL anchor. */
6981 /* Omit this list of longs, because there are no CTL anchors. */
6982
6983 /* Length of function name. */
6984 fprintf (file, "\t.short %d\n", (int) strlen (fname));
6985
6986 /* Function name. */
6987 assemble_string (fname, strlen (fname));
6988
6989 /* Register for alloca automatic storage; this is always reg 31.
6990 Only emit this if the alloca bit was set above. */
6991 if (frame_pointer_needed)
6992 fputs ("\t.byte 31\n", file);
6993 }
6994 }
6995 \f
6996 /* A C compound statement that outputs the assembler code for a thunk function,
6997 used to implement C++ virtual function calls with multiple inheritance. The
6998 thunk acts as a wrapper around a virtual function, adjusting the implicit
6999 object parameter before handing control off to the real function.
7000
7001 First, emit code to add the integer DELTA to the location that contains the
7002 incoming first argument. Assume that this argument contains a pointer, and
7003 is the one used to pass the `this' pointer in C++. This is the incoming
7004 argument *before* the function prologue, e.g. `%o0' on a sparc. The
7005 addition must preserve the values of all other incoming arguments.
7006
7007 After the addition, emit code to jump to FUNCTION, which is a
7008 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch
7009 the return address. Hence returning from FUNCTION will return to whoever
7010 called the current `thunk'.
7011
7012 The effect must be as if FUNCTION had been called directly with the adjusted
7013 first argument. This macro is responsible for emitting all of the code for
7014 a thunk function; output_function_prologue() and output_function_epilogue()
7015 are not invoked.
7016
7017 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been
7018 extracted from it.) It might possibly be useful on some targets, but
7019 probably not.
7020
7021 If you do not define this macro, the target-independent code in the C++
7022 frontend will generate a less efficient heavyweight thunk that calls
7023 FUNCTION instead of jumping to it. The generic approach does not support
7024 varargs. */
7025
7026 void
7027 output_mi_thunk (file, thunk_fndecl, delta, function)
7028 FILE *file;
7029 tree thunk_fndecl ATTRIBUTE_UNUSED;
7030 int delta;
7031 tree function;
7032 {
7033 const char *this_reg = reg_names[ aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) ? 4 : 3 ];
7034 const char *prefix;
7035 const char *fname;
7036 const char *r0 = reg_names[0];
7037 const char *toc = reg_names[2];
7038 const char *schain = reg_names[11];
7039 const char *r12 = reg_names[12];
7040 char buf[512];
7041 static int labelno = 0;
7042
7043 /* Small constants that can be done by one add instruction */
7044 if (delta >= -32768 && delta <= 32767)
7045 {
7046 if (! TARGET_NEW_MNEMONICS)
7047 fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta, this_reg);
7048 else
7049 fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta);
7050 }
7051
7052 /* Large constants that can be done by one addis instruction */
7053 else if ((delta & 0xffff) == 0 && num_insns_constant_wide (delta) == 1)
7054 asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg,
7055 delta >> 16);
7056
7057 /* 32-bit constants that can be done by an add and addis instruction. */
7058 else if (TARGET_32BIT || num_insns_constant_wide (delta) == 1)
7059 {
7060 /* Break into two pieces, propagating the sign bit from the low word to
7061 the upper word. */
7062 int delta_high = delta >> 16;
7063 int delta_low = delta & 0xffff;
7064 if ((delta_low & 0x8000) != 0)
7065 {
7066 delta_high++;
7067 delta_low = (delta_low ^ 0x8000) - 0x8000; /* sign extend */
7068 }
7069
7070 asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg,
7071 delta_high);
7072
7073 if (! TARGET_NEW_MNEMONICS)
7074 fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta_low, this_reg);
7075 else
7076 fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta_low);
7077 }
7078
7079 /* 64-bit constants, fixme */
7080 else
7081 abort ();
7082
7083 /* Get the prefix in front of the names. */
7084 switch (DEFAULT_ABI)
7085 {
7086 default:
7087 abort ();
7088
7089 case ABI_AIX:
7090 prefix = ".";
7091 break;
7092
7093 case ABI_V4:
7094 case ABI_AIX_NODESC:
7095 case ABI_SOLARIS:
7096 prefix = "";
7097 break;
7098 }
7099
7100 /* If the function is compiled in this module, jump to it directly.
7101 Otherwise, load up its address and jump to it. */
7102
7103 fname = XSTR (XEXP (DECL_RTL (function), 0), 0);
7104
7105 if (current_file_function_operand (XEXP (DECL_RTL (function), 0), VOIDmode)
7106 && ! lookup_attribute ("longcall",
7107 TYPE_ATTRIBUTES (TREE_TYPE (function))))
7108 {
7109 fprintf (file, "\tb %s", prefix);
7110 assemble_name (file, fname);
7111 if (DEFAULT_ABI == ABI_V4 && flag_pic) fputs ("@local", file);
7112 putc ('\n', file);
7113 }
7114
7115 else
7116 {
7117 switch (DEFAULT_ABI)
7118 {
7119 default:
7120 abort ();
7121
7122 case ABI_AIX:
7123 /* Set up a TOC entry for the function. */
7124 ASM_GENERATE_INTERNAL_LABEL (buf, "Lthunk", labelno);
7125 toc_section ();
7126 ASM_OUTPUT_INTERNAL_LABEL (file, "Lthunk", labelno);
7127 labelno++;
7128
7129 /* Note, MINIMAL_TOC doesn't make sense in the case of a thunk, since
7130 there will be only one TOC entry for this function. */
7131 fputs ("\t.tc\t", file);
7132 assemble_name (file, buf);
7133 fputs ("[TC],", file);
7134 assemble_name (file, buf);
7135 putc ('\n', file);
7136 text_section ();
7137 asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s," : "\tld %s", r12);
7138 assemble_name (file, buf);
7139 asm_fprintf (file, "(%s)\n", reg_names[2]);
7140 asm_fprintf (file,
7141 (TARGET_32BIT) ? "\t{l|lwz} %s,0(%s)\n" : "\tld %s,0(%s)\n",
7142 r0, r12);
7143
7144 asm_fprintf (file,
7145 (TARGET_32BIT) ? "\t{l|lwz} %s,4(%s)\n" : "\tld %s,8(%s)\n",
7146 toc, r12);
7147
7148 asm_fprintf (file, "\tmtctr %s\n", r0);
7149 asm_fprintf (file,
7150 (TARGET_32BIT) ? "\t{l|lwz} %s,8(%s)\n" : "\tld %s,16(%s)\n",
7151 schain, r12);
7152
7153 asm_fprintf (file, "\tbctr\n");
7154 break;
7155
7156 case ABI_AIX_NODESC:
7157 case ABI_SOLARIS:
7158 case ABI_V4:
7159 fprintf (file, "\tb %s", prefix);
7160 assemble_name (file, fname);
7161 if (flag_pic) fputs ("@plt", file);
7162 putc ('\n', file);
7163 break;
7164
7165 #if TARGET_MACHO
7166 case ABI_DARWIN:
7167 fprintf (file, "\tb %s", prefix);
7168 if (flag_pic && !machopic_name_defined_p (fname))
7169 assemble_name (file, machopic_stub_name (fname));
7170 else
7171 assemble_name (file, fname);
7172 putc ('\n', file);
7173 break;
7174 #endif
7175 }
7176 }
7177 }
7178
7179 \f
7180 /* A quick summary of the various types of 'constant-pool tables'
7181 under PowerPC:
7182
7183 Target Flags Name One table per
7184 AIX (none) AIX TOC object file
7185 AIX -mfull-toc AIX TOC object file
7186 AIX -mminimal-toc AIX minimal TOC translation unit
7187 SVR4/EABI (none) SVR4 SDATA object file
7188 SVR4/EABI -fpic SVR4 pic object file
7189 SVR4/EABI -fPIC SVR4 PIC translation unit
7190 SVR4/EABI -mrelocatable EABI TOC function
7191 SVR4/EABI -maix AIX TOC object file
7192 SVR4/EABI -maix -mminimal-toc
7193 AIX minimal TOC translation unit
7194
7195 Name Reg. Set by entries contains:
7196 made by addrs? fp? sum?
7197
7198 AIX TOC 2 crt0 as Y option option
7199 AIX minimal TOC 30 prolog gcc Y Y option
7200 SVR4 SDATA 13 crt0 gcc N Y N
7201 SVR4 pic 30 prolog ld Y not yet N
7202 SVR4 PIC 30 prolog gcc Y option option
7203 EABI TOC 30 prolog gcc Y option option
7204
7205 */
7206
7207 /* Hash table stuff for keeping track of TOC entries. */
7208
7209 struct toc_hash_struct
7210 {
7211 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
7212 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
7213 rtx key;
7214 enum machine_mode key_mode;
7215 int labelno;
7216 };
7217
7218 static htab_t toc_hash_table;
7219
7220 /* Hash functions for the hash table. */
7221
7222 static unsigned
7223 rs6000_hash_constant (k)
7224 rtx k;
7225 {
7226 unsigned result = (GET_CODE (k) << 3) ^ GET_MODE (k);
7227 const char *format = GET_RTX_FORMAT (GET_CODE (k));
7228 int flen = strlen (format);
7229 int fidx;
7230
7231 if (GET_CODE (k) == LABEL_REF)
7232 return result * 1231 + X0INT (XEXP (k, 0), 3);
7233
7234 if (GET_CODE (k) == CONST_DOUBLE)
7235 fidx = 2;
7236 else if (GET_CODE (k) == CODE_LABEL)
7237 fidx = 3;
7238 else
7239 fidx = 0;
7240
7241 for (; fidx < flen; fidx++)
7242 switch (format[fidx])
7243 {
7244 case 's':
7245 {
7246 unsigned i, len;
7247 const char *str = XSTR (k, fidx);
7248 len = strlen (str);
7249 result = result * 613 + len;
7250 for (i = 0; i < len; i++)
7251 result = result * 613 + (unsigned) str[i];
7252 break;
7253 }
7254 case 'u':
7255 case 'e':
7256 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
7257 break;
7258 case 'i':
7259 case 'n':
7260 result = result * 613 + (unsigned) XINT (k, fidx);
7261 break;
7262 case 'w':
7263 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
7264 result = result * 613 + (unsigned) XWINT (k, fidx);
7265 else
7266 {
7267 size_t i;
7268 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
7269 result = result * 613 + (unsigned) (XWINT (k, fidx)
7270 >> CHAR_BIT * i);
7271 }
7272 break;
7273 default:
7274 abort();
7275 }
7276 return result;
7277 }
7278
7279 static unsigned
7280 toc_hash_function (hash_entry)
7281 const void * hash_entry;
7282 {
7283 const struct toc_hash_struct *thc =
7284 (const struct toc_hash_struct *) hash_entry;
7285 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
7286 }
7287
7288 /* Compare H1 and H2 for equivalence. */
7289
7290 static int
7291 toc_hash_eq (h1, h2)
7292 const void * h1;
7293 const void * h2;
7294 {
7295 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
7296 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
7297
7298 if (((const struct toc_hash_struct *) h1)->key_mode
7299 != ((const struct toc_hash_struct *) h2)->key_mode)
7300 return 0;
7301
7302 /* Gotcha: One of these const_doubles will be in memory.
7303 The other may be on the constant-pool chain.
7304 So rtx_equal_p will think they are different... */
7305 if (r1 == r2)
7306 return 1;
7307 if (GET_CODE (r1) != GET_CODE (r2)
7308 || GET_MODE (r1) != GET_MODE (r2))
7309 return 0;
7310 if (GET_CODE (r1) == CONST_DOUBLE)
7311 {
7312 int format_len = strlen (GET_RTX_FORMAT (CONST_DOUBLE));
7313 int i;
7314 for (i = 2; i < format_len; i++)
7315 if (XWINT (r1, i) != XWINT (r2, i))
7316 return 0;
7317
7318 return 1;
7319 }
7320 else if (GET_CODE (r1) == LABEL_REF)
7321 return (CODE_LABEL_NUMBER (XEXP (r1, 0))
7322 == CODE_LABEL_NUMBER (XEXP (r2, 0)));
7323 else
7324 return rtx_equal_p (r1, r2);
7325 }
7326
7327 /* Mark the hash table-entry HASH_ENTRY. */
7328
7329 static int
7330 toc_hash_mark_entry (hash_slot, unused)
7331 void ** hash_slot;
7332 void * unused ATTRIBUTE_UNUSED;
7333 {
7334 const struct toc_hash_struct * hash_entry =
7335 *(const struct toc_hash_struct **) hash_slot;
7336 rtx r = hash_entry->key;
7337 ggc_set_mark (hash_entry);
7338 /* For CODE_LABELS, we don't want to drag in the whole insn chain... */
7339 if (GET_CODE (r) == LABEL_REF)
7340 {
7341 ggc_set_mark (r);
7342 ggc_set_mark (XEXP (r, 0));
7343 }
7344 else
7345 ggc_mark_rtx (r);
7346 return 1;
7347 }
7348
7349 /* Mark all the elements of the TOC hash-table *HT. */
7350
7351 static void
7352 toc_hash_mark_table (vht)
7353 void *vht;
7354 {
7355 htab_t *ht = vht;
7356
7357 htab_traverse (*ht, toc_hash_mark_entry, (void *)0);
7358 }
7359
7360 /* These are the names given by the C++ front-end to vtables, and
7361 vtable-like objects. Ideally, this logic should not be here;
7362 instead, there should be some programmatic way of inquiring as
7363 to whether or not an object is a vtable. */
7364
7365 #define VTABLE_NAME_P(NAME) \
7366 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
7367 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
7368 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
7369 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
7370
7371 void
7372 rs6000_output_symbol_ref (file, x)
7373 FILE *file;
7374 rtx x;
7375 {
7376 /* Currently C++ toc references to vtables can be emitted before it
7377 is decided whether the vtable is public or private. If this is
7378 the case, then the linker will eventually complain that there is
7379 a reference to an unknown section. Thus, for vtables only,
7380 we emit the TOC reference to reference the symbol and not the
7381 section. */
7382 const char *name = XSTR (x, 0);
7383
7384 if (VTABLE_NAME_P (name))
7385 {
7386 RS6000_OUTPUT_BASENAME (file, name);
7387 }
7388 else
7389 assemble_name (file, name);
7390 }
7391
7392 /* Output a TOC entry. We derive the entry name from what is
7393 being written. */
7394
7395 void
7396 output_toc (file, x, labelno, mode)
7397 FILE *file;
7398 rtx x;
7399 int labelno;
7400 enum machine_mode mode;
7401 {
7402 char buf[256];
7403 const char *name = buf;
7404 const char *real_name;
7405 rtx base = x;
7406 int offset = 0;
7407
7408 if (TARGET_NO_TOC)
7409 abort ();
7410
7411 /* When the linker won't eliminate them, don't output duplicate
7412 TOC entries (this happens on AIX if there is any kind of TOC,
7413 and on SVR4 under -fPIC or -mrelocatable). */
7414 if (TARGET_TOC)
7415 {
7416 struct toc_hash_struct *h;
7417 void * * found;
7418
7419 h = ggc_alloc (sizeof (*h));
7420 h->key = x;
7421 h->key_mode = mode;
7422 h->labelno = labelno;
7423
7424 found = htab_find_slot (toc_hash_table, h, 1);
7425 if (*found == NULL)
7426 *found = h;
7427 else /* This is indeed a duplicate.
7428 Set this label equal to that label. */
7429 {
7430 fputs ("\t.set ", file);
7431 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
7432 fprintf (file, "%d,", labelno);
7433 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
7434 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
7435 found)->labelno));
7436 return;
7437 }
7438 }
7439
7440 /* If we're going to put a double constant in the TOC, make sure it's
7441 aligned properly when strict alignment is on. */
7442 if (GET_CODE (x) == CONST_DOUBLE
7443 && STRICT_ALIGNMENT
7444 && GET_MODE_BITSIZE (mode) >= 64
7445 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
7446 ASM_OUTPUT_ALIGN (file, 3);
7447 }
7448
7449 ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno);
7450
7451 /* Handle FP constants specially. Note that if we have a minimal
7452 TOC, things we put here aren't actually in the TOC, so we can allow
7453 FP constants. */
7454 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
7455 {
7456 REAL_VALUE_TYPE rv;
7457 long k[2];
7458
7459 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
7460 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
7461
7462 if (TARGET_64BIT)
7463 {
7464 if (TARGET_MINIMAL_TOC)
7465 fputs (DOUBLE_INT_ASM_OP, file);
7466 else
7467 fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]);
7468 fprintf (file, "0x%lx%08lx\n", k[0], k[1]);
7469 return;
7470 }
7471 else
7472 {
7473 if (TARGET_MINIMAL_TOC)
7474 fputs ("\t.long ", file);
7475 else
7476 fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]);
7477 fprintf (file, "0x%lx,0x%lx\n", k[0], k[1]);
7478 return;
7479 }
7480 }
7481 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
7482 {
7483 REAL_VALUE_TYPE rv;
7484 long l;
7485
7486 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
7487 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7488
7489 if (TARGET_64BIT)
7490 {
7491 if (TARGET_MINIMAL_TOC)
7492 fputs (DOUBLE_INT_ASM_OP, file);
7493 else
7494 fprintf (file, "\t.tc FS_%lx[TC],", l);
7495 fprintf (file, "0x%lx00000000\n", l);
7496 return;
7497 }
7498 else
7499 {
7500 if (TARGET_MINIMAL_TOC)
7501 fputs ("\t.long ", file);
7502 else
7503 fprintf (file, "\t.tc FS_%lx[TC],", l);
7504 fprintf (file, "0x%lx\n", l);
7505 return;
7506 }
7507 }
7508 else if (GET_MODE (x) == VOIDmode
7509 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
7510 {
7511 unsigned HOST_WIDE_INT low;
7512 HOST_WIDE_INT high;
7513
7514 if (GET_CODE (x) == CONST_DOUBLE)
7515 {
7516 low = CONST_DOUBLE_LOW (x);
7517 high = CONST_DOUBLE_HIGH (x);
7518 }
7519 else
7520 #if HOST_BITS_PER_WIDE_INT == 32
7521 {
7522 low = INTVAL (x);
7523 high = (low & 0x80000000) ? ~0 : 0;
7524 }
7525 #else
7526 {
7527 low = INTVAL (x) & 0xffffffff;
7528 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
7529 }
7530 #endif
7531
7532 /* TOC entries are always Pmode-sized, but since this
7533 is a bigendian machine then if we're putting smaller
7534 integer constants in the TOC we have to pad them.
7535 (This is still a win over putting the constants in
7536 a separate constant pool, because then we'd have
7537 to have both a TOC entry _and_ the actual constant.)
7538
7539 For a 32-bit target, CONST_INT values are loaded and shifted
7540 entirely within `low' and can be stored in one TOC entry. */
7541
7542 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
7543 abort ();/* It would be easy to make this work, but it doesn't now. */
7544
7545 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
7546 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
7547 POINTER_SIZE, &low, &high, 0);
7548
7549 if (TARGET_64BIT)
7550 {
7551 if (TARGET_MINIMAL_TOC)
7552 fputs (DOUBLE_INT_ASM_OP, file);
7553 else
7554 fprintf (file, "\t.tc ID_%lx_%lx[TC],", (long)high, (long)low);
7555 fprintf (file, "0x%lx%08lx\n", (long) high, (long) low);
7556 return;
7557 }
7558 else
7559 {
7560 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
7561 {
7562 if (TARGET_MINIMAL_TOC)
7563 fputs ("\t.long ", file);
7564 else
7565 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
7566 (long)high, (long)low);
7567 fprintf (file, "0x%lx,0x%lx\n", (long) high, (long) low);
7568 }
7569 else
7570 {
7571 if (TARGET_MINIMAL_TOC)
7572 fputs ("\t.long ", file);
7573 else
7574 fprintf (file, "\t.tc IS_%lx[TC],", (long) low);
7575 fprintf (file, "0x%lx\n", (long) low);
7576 }
7577 return;
7578 }
7579 }
7580
7581 if (GET_CODE (x) == CONST)
7582 {
7583 if (GET_CODE (XEXP (x, 0)) != PLUS)
7584 abort ();
7585
7586 base = XEXP (XEXP (x, 0), 0);
7587 offset = INTVAL (XEXP (XEXP (x, 0), 1));
7588 }
7589
7590 if (GET_CODE (base) == SYMBOL_REF)
7591 name = XSTR (base, 0);
7592 else if (GET_CODE (base) == LABEL_REF)
7593 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
7594 else if (GET_CODE (base) == CODE_LABEL)
7595 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
7596 else
7597 abort ();
7598
7599 STRIP_NAME_ENCODING (real_name, name);
7600 if (TARGET_MINIMAL_TOC)
7601 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
7602 else
7603 {
7604 fprintf (file, "\t.tc %s", real_name);
7605
7606 if (offset < 0)
7607 fprintf (file, ".N%d", - offset);
7608 else if (offset)
7609 fprintf (file, ".P%d", offset);
7610
7611 fputs ("[TC],", file);
7612 }
7613
7614 /* Currently C++ toc references to vtables can be emitted before it
7615 is decided whether the vtable is public or private. If this is
7616 the case, then the linker will eventually complain that there is
7617 a TOC reference to an unknown section. Thus, for vtables only,
7618 we emit the TOC reference to reference the symbol and not the
7619 section. */
7620 if (VTABLE_NAME_P (name))
7621 {
7622 RS6000_OUTPUT_BASENAME (file, name);
7623 if (offset < 0)
7624 fprintf (file, "%d", offset);
7625 else if (offset > 0)
7626 fprintf (file, "+%d", offset);
7627 }
7628 else
7629 output_addr_const (file, x);
7630 putc ('\n', file);
7631 }
7632 \f
7633 /* Output an assembler pseudo-op to write an ASCII string of N characters
7634 starting at P to FILE.
7635
7636 On the RS/6000, we have to do this using the .byte operation and
7637 write out special characters outside the quoted string.
7638 Also, the assembler is broken; very long strings are truncated,
7639 so we must artificially break them up early. */
7640
7641 void
7642 output_ascii (file, p, n)
7643 FILE *file;
7644 const char *p;
7645 int n;
7646 {
7647 char c;
7648 int i, count_string;
7649 const char *for_string = "\t.byte \"";
7650 const char *for_decimal = "\t.byte ";
7651 const char *to_close = NULL;
7652
7653 count_string = 0;
7654 for (i = 0; i < n; i++)
7655 {
7656 c = *p++;
7657 if (c >= ' ' && c < 0177)
7658 {
7659 if (for_string)
7660 fputs (for_string, file);
7661 putc (c, file);
7662
7663 /* Write two quotes to get one. */
7664 if (c == '"')
7665 {
7666 putc (c, file);
7667 ++count_string;
7668 }
7669
7670 for_string = NULL;
7671 for_decimal = "\"\n\t.byte ";
7672 to_close = "\"\n";
7673 ++count_string;
7674
7675 if (count_string >= 512)
7676 {
7677 fputs (to_close, file);
7678
7679 for_string = "\t.byte \"";
7680 for_decimal = "\t.byte ";
7681 to_close = NULL;
7682 count_string = 0;
7683 }
7684 }
7685 else
7686 {
7687 if (for_decimal)
7688 fputs (for_decimal, file);
7689 fprintf (file, "%d", c);
7690
7691 for_string = "\n\t.byte \"";
7692 for_decimal = ", ";
7693 to_close = "\n";
7694 count_string = 0;
7695 }
7696 }
7697
7698 /* Now close the string if we have written one. Then end the line. */
7699 if (to_close)
7700 fputs (to_close, file);
7701 }
7702 \f
7703 /* Generate a unique section name for FILENAME for a section type
7704 represented by SECTION_DESC. Output goes into BUF.
7705
7706 SECTION_DESC can be any string, as long as it is different for each
7707 possible section type.
7708
7709 We name the section in the same manner as xlc. The name begins with an
7710 underscore followed by the filename (after stripping any leading directory
7711 names) with the last period replaced by the string SECTION_DESC. If
7712 FILENAME does not contain a period, SECTION_DESC is appended to the end of
7713 the name. */
7714
7715 void
7716 rs6000_gen_section_name (buf, filename, section_desc)
7717 char **buf;
7718 const char *filename;
7719 const char *section_desc;
7720 {
7721 const char *q, *after_last_slash, *last_period = 0;
7722 char *p;
7723 int len;
7724
7725 after_last_slash = filename;
7726 for (q = filename; *q; q++)
7727 {
7728 if (*q == '/')
7729 after_last_slash = q + 1;
7730 else if (*q == '.')
7731 last_period = q;
7732 }
7733
7734 len = strlen (after_last_slash) + strlen (section_desc) + 2;
7735 *buf = (char *) permalloc (len);
7736
7737 p = *buf;
7738 *p++ = '_';
7739
7740 for (q = after_last_slash; *q; q++)
7741 {
7742 if (q == last_period)
7743 {
7744 strcpy (p, section_desc);
7745 p += strlen (section_desc);
7746 }
7747
7748 else if (ISALNUM (*q))
7749 *p++ = *q;
7750 }
7751
7752 if (last_period == 0)
7753 strcpy (p, section_desc);
7754 else
7755 *p = '\0';
7756 }
7757 \f
7758
7759 /* Emit profile function. */
7760 void
7761 output_profile_hook (labelno)
7762 int labelno;
7763 {
7764 if (DEFAULT_ABI == ABI_AIX)
7765 {
7766 char buf[30];
7767 char *label_name;
7768 rtx fun;
7769
7770 labelno += 1;
7771
7772 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
7773 STRIP_NAME_ENCODING (label_name, ggc_strdup (buf));
7774 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
7775
7776 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
7777 fun, Pmode);
7778 }
7779 else if (DEFAULT_ABI == ABI_DARWIN)
7780 {
7781 const char *mcount_name = RS6000_MCOUNT;
7782 int caller_addr_regno = LINK_REGISTER_REGNUM;
7783
7784 /* Be conservative and always set this, at least for now. */
7785 current_function_uses_pic_offset_table = 1;
7786
7787 #if TARGET_MACHO
7788 /* For PIC code, set up a stub and collect the caller's address
7789 from r0, which is where the prologue puts it. */
7790 if (flag_pic)
7791 {
7792 mcount_name = machopic_stub_name (mcount_name);
7793 if (current_function_uses_pic_offset_table)
7794 caller_addr_regno = 0;
7795 }
7796 #endif
7797 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
7798 0, VOIDmode, 1,
7799 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
7800 }
7801 }
7802
7803 /* Write function profiler code. */
7804
7805 void
7806 output_function_profiler (file, labelno)
7807 FILE *file;
7808 int labelno;
7809 {
7810 char buf[100];
7811
7812 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
7813 switch (DEFAULT_ABI)
7814 {
7815 default:
7816 abort ();
7817
7818 case ABI_V4:
7819 case ABI_SOLARIS:
7820 case ABI_AIX_NODESC:
7821 fprintf (file, "\tmflr %s\n", reg_names[0]);
7822 if (flag_pic == 1)
7823 {
7824 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
7825 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
7826 reg_names[0], reg_names[1]);
7827 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
7828 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
7829 assemble_name (file, buf);
7830 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
7831 }
7832 else if (flag_pic > 1)
7833 {
7834 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
7835 reg_names[0], reg_names[1]);
7836 /* Now, we need to get the address of the label. */
7837 fputs ("\tbl 1f\n\t.long ", file);
7838 assemble_name (file, buf);
7839 fputs ("-.\n1:", file);
7840 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
7841 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
7842 reg_names[0], reg_names[11]);
7843 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
7844 reg_names[0], reg_names[0], reg_names[11]);
7845 }
7846 else
7847 {
7848 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
7849 assemble_name (file, buf);
7850 fputs ("@ha\n", file);
7851 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
7852 reg_names[0], reg_names[1]);
7853 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
7854 assemble_name (file, buf);
7855 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
7856 }
7857
7858 if (current_function_needs_context)
7859 asm_fprintf (file, "\tmr %s,%s\n",
7860 reg_names[30], reg_names[STATIC_CHAIN_REGNUM]);
7861 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
7862 if (current_function_needs_context)
7863 asm_fprintf (file, "\tmr %s,%s\n",
7864 reg_names[STATIC_CHAIN_REGNUM], reg_names[30]);
7865 break;
7866
7867 case ABI_AIX:
7868 case ABI_DARWIN:
7869 /* Don't do anything, done in output_profile_hook (). */
7870 break;
7871
7872 }
7873 }
7874
7875 /* Adjust the cost of a scheduling dependency. Return the new cost of
7876 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7877
7878 int
7879 rs6000_adjust_cost (insn, link, dep_insn, cost)
7880 rtx insn;
7881 rtx link;
7882 rtx dep_insn ATTRIBUTE_UNUSED;
7883 int cost;
7884 {
7885 if (! recog_memoized (insn))
7886 return 0;
7887
7888 if (REG_NOTE_KIND (link) != 0)
7889 return 0;
7890
7891 if (REG_NOTE_KIND (link) == 0)
7892 {
7893 /* Data dependency; DEP_INSN writes a register that INSN reads some
7894 cycles later. */
7895
7896 /* Tell the first scheduling pass about the latency between a mtctr
7897 and bctr (and mtlr and br/blr). The first scheduling pass will not
7898 know about this latency since the mtctr instruction, which has the
7899 latency associated to it, will be generated by reload. */
7900 if (get_attr_type (insn) == TYPE_JMPREG)
7901 return TARGET_POWER ? 5 : 4;
7902
7903 /* Fall out to return default cost. */
7904 }
7905
7906 return cost;
7907 }
7908
7909 /* A C statement (sans semicolon) to update the integer scheduling priority
7910 INSN_PRIORITY (INSN). Reduce the priority to execute the INSN earlier,
7911 increase the priority to execute INSN later. Do not define this macro if
7912 you do not need to adjust the scheduling priorities of insns. */
7913
7914 int
7915 rs6000_adjust_priority (insn, priority)
7916 rtx insn ATTRIBUTE_UNUSED;
7917 int priority;
7918 {
7919 /* On machines (like the 750) which have asymetric integer units, where one
7920 integer unit can do multiply and divides and the other can't, reduce the
7921 priority of multiply/divide so it is scheduled before other integer
7922 operationss. */
7923
7924 #if 0
7925 if (! INSN_P (insn))
7926 return priority;
7927
7928 if (GET_CODE (PATTERN (insn)) == USE)
7929 return priority;
7930
7931 switch (rs6000_cpu_attr) {
7932 case CPU_PPC750:
7933 switch (get_attr_type (insn))
7934 {
7935 default:
7936 break;
7937
7938 case TYPE_IMUL:
7939 case TYPE_IDIV:
7940 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
7941 priority, priority);
7942 if (priority >= 0 && priority < 0x01000000)
7943 priority >>= 3;
7944 break;
7945 }
7946 }
7947 #endif
7948
7949 return priority;
7950 }
7951
7952 /* Return how many instructions the machine can issue per cycle */
7953 int get_issue_rate()
7954 {
7955 switch (rs6000_cpu_attr) {
7956 case CPU_RIOS1: /* ? */
7957 case CPU_RS64A:
7958 case CPU_PPC601: /* ? */
7959 return 3;
7960 case CPU_PPC603:
7961 case CPU_PPC750:
7962 return 2;
7963 case CPU_RIOS2:
7964 case CPU_PPC604:
7965 case CPU_PPC604E:
7966 case CPU_PPC620:
7967 case CPU_PPC630:
7968 return 4;
7969 default:
7970 return 1;
7971 }
7972 }
7973
7974 \f
7975 /* Length in units of the trampoline for entering a nested function. */
7976
7977 int
7978 rs6000_trampoline_size ()
7979 {
7980 int ret = 0;
7981
7982 switch (DEFAULT_ABI)
7983 {
7984 default:
7985 abort ();
7986
7987 case ABI_AIX:
7988 ret = (TARGET_32BIT) ? 12 : 24;
7989 break;
7990
7991 case ABI_V4:
7992 case ABI_SOLARIS:
7993 case ABI_AIX_NODESC:
7994 ret = (TARGET_32BIT) ? 40 : 48;
7995 break;
7996 }
7997
7998 return ret;
7999 }
8000
8001 /* Emit RTL insns to initialize the variable parts of a trampoline.
8002 FNADDR is an RTX for the address of the function's pure code.
8003 CXT is an RTX for the static chain value for the function. */
8004
8005 void
8006 rs6000_initialize_trampoline (addr, fnaddr, cxt)
8007 rtx addr;
8008 rtx fnaddr;
8009 rtx cxt;
8010 {
8011 enum machine_mode pmode = Pmode;
8012 int regsize = (TARGET_32BIT) ? 4 : 8;
8013 rtx ctx_reg = force_reg (pmode, cxt);
8014
8015 switch (DEFAULT_ABI)
8016 {
8017 default:
8018 abort ();
8019
8020 /* Macros to shorten the code expansions below. */
8021 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
8022 #define MEM_PLUS(addr,offset) \
8023 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
8024
8025 /* Under AIX, just build the 3 word function descriptor */
8026 case ABI_AIX:
8027 {
8028 rtx fn_reg = gen_reg_rtx (pmode);
8029 rtx toc_reg = gen_reg_rtx (pmode);
8030 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
8031 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, 4));
8032 emit_move_insn (MEM_DEREF (addr), fn_reg);
8033 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
8034 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
8035 }
8036 break;
8037
8038 /* Under V.4/eabi, call __trampoline_setup to do the real work. */
8039 case ABI_V4:
8040 case ABI_SOLARIS:
8041 case ABI_AIX_NODESC:
8042 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
8043 FALSE, VOIDmode, 4,
8044 addr, pmode,
8045 GEN_INT (rs6000_trampoline_size ()), SImode,
8046 fnaddr, pmode,
8047 ctx_reg, pmode);
8048 break;
8049 }
8050
8051 return;
8052 }
8053
8054 \f
8055 /* If defined, a C expression whose value is nonzero if IDENTIFIER
8056 with arguments ARGS is a valid machine specific attribute for TYPE.
8057 The attributes in ATTRIBUTES have previously been assigned to TYPE. */
8058
8059 static int
8060 rs6000_valid_type_attribute_p (type, attributes, identifier, args)
8061 tree type;
8062 tree attributes ATTRIBUTE_UNUSED;
8063 tree identifier;
8064 tree args;
8065 {
8066 if (TREE_CODE (type) != FUNCTION_TYPE
8067 && TREE_CODE (type) != FIELD_DECL
8068 && TREE_CODE (type) != TYPE_DECL)
8069 return 0;
8070
8071 /* Longcall attribute says that the function is not within 2**26 bytes
8072 of the current function, and to do an indirect call. */
8073 if (is_attribute_p ("longcall", identifier))
8074 return (args == NULL_TREE);
8075
8076 return 0;
8077 }
8078
8079 /* Return a reference suitable for calling a function with the
8080 longcall attribute. */
8081 struct rtx_def *
8082 rs6000_longcall_ref (call_ref)
8083 rtx call_ref;
8084 {
8085 const char *call_name;
8086 tree node;
8087
8088 if (GET_CODE (call_ref) != SYMBOL_REF)
8089 return call_ref;
8090
8091 /* System V adds '.' to the internal name, so skip them. */
8092 call_name = XSTR (call_ref, 0);
8093 if (*call_name == '.')
8094 {
8095 while (*call_name == '.')
8096 call_name++;
8097
8098 node = get_identifier (call_name);
8099 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
8100 }
8101
8102 return force_reg (Pmode, call_ref);
8103 }
8104
8105 \f
8106 /* A C statement or statements to switch to the appropriate section
8107 for output of RTX in mode MODE. You can assume that RTX is some
8108 kind of constant in RTL. The argument MODE is redundant except in
8109 the case of a `const_int' rtx. Select the section by calling
8110 `text_section' or one of the alternatives for other sections.
8111
8112 Do not define this macro if you put all constants in the read-only
8113 data section. */
8114
8115 #ifdef USING_SVR4_H
8116
8117 void
8118 rs6000_select_rtx_section (mode, x)
8119 enum machine_mode mode;
8120 rtx x;
8121 {
8122 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
8123 toc_section ();
8124 else
8125 const_section ();
8126 }
8127
8128 /* A C statement or statements to switch to the appropriate
8129 section for output of DECL. DECL is either a `VAR_DECL' node
8130 or a constant of some sort. RELOC indicates whether forming
8131 the initial value of DECL requires link-time relocations. */
8132
8133 void
8134 rs6000_select_section (decl, reloc)
8135 tree decl;
8136 int reloc;
8137 {
8138 int size = int_size_in_bytes (TREE_TYPE (decl));
8139 int needs_sdata;
8140 int readonly;
8141 static void (* const sec_funcs[4]) PARAMS ((void)) = {
8142 &const_section,
8143 &sdata2_section,
8144 &data_section,
8145 &sdata_section
8146 };
8147
8148 needs_sdata = (size > 0
8149 && size <= g_switch_value
8150 && rs6000_sdata != SDATA_NONE
8151 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)));
8152
8153 if (TREE_CODE (decl) == STRING_CST)
8154 readonly = ! flag_writable_strings;
8155 else if (TREE_CODE (decl) == VAR_DECL)
8156 readonly = (! (flag_pic && reloc)
8157 && TREE_READONLY (decl)
8158 && ! TREE_SIDE_EFFECTS (decl)
8159 && DECL_INITIAL (decl)
8160 && DECL_INITIAL (decl) != error_mark_node
8161 && TREE_CONSTANT (DECL_INITIAL (decl)));
8162 else
8163 readonly = 1;
8164 if (needs_sdata && rs6000_sdata != SDATA_EABI)
8165 readonly = 0;
8166
8167 (*sec_funcs[(readonly ? 0 : 2) + (needs_sdata ? 1 : 0)])();
8168 }
8169
8170 /* A C statement to build up a unique section name, expressed as a
8171 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
8172 RELOC indicates whether the initial value of EXP requires
8173 link-time relocations. If you do not define this macro, GCC will use
8174 the symbol name prefixed by `.' as the section name. Note - this
8175 macro can now be called for unitialised data items as well as
8176 initialised data and functions. */
8177
8178 void
8179 rs6000_unique_section (decl, reloc)
8180 tree decl;
8181 int reloc;
8182 {
8183 int size = int_size_in_bytes (TREE_TYPE (decl));
8184 int needs_sdata;
8185 int readonly;
8186 int len;
8187 int sec;
8188 const char *name;
8189 char *string;
8190 const char *prefix;
8191
8192 static const char *const prefixes[7][2] =
8193 {
8194 { ".text.", ".gnu.linkonce.t." },
8195 { ".rodata.", ".gnu.linkonce.r." },
8196 { ".sdata2.", ".gnu.linkonce.s2." },
8197 { ".data.", ".gnu.linkonce.d." },
8198 { ".sdata.", ".gnu.linkonce.s." },
8199 { ".bss.", ".gnu.linkonce.b." },
8200 { ".sbss.", ".gnu.linkonce.sb." }
8201 };
8202
8203 needs_sdata = (TREE_CODE (decl) != FUNCTION_DECL
8204 && size > 0
8205 && size <= g_switch_value
8206 && rs6000_sdata != SDATA_NONE
8207 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)));
8208
8209 if (TREE_CODE (decl) == STRING_CST)
8210 readonly = ! flag_writable_strings;
8211 else if (TREE_CODE (decl) == VAR_DECL)
8212 readonly = (! (flag_pic && reloc)
8213 && TREE_READONLY (decl)
8214 && ! TREE_SIDE_EFFECTS (decl)
8215 && DECL_INITIAL (decl)
8216 && DECL_INITIAL (decl) != error_mark_node
8217 && TREE_CONSTANT (DECL_INITIAL (decl)));
8218 else
8219 readonly = 1;
8220 if (needs_sdata && rs6000_sdata != SDATA_EABI)
8221 readonly = 0;
8222
8223 sec = ((TREE_CODE (decl) == FUNCTION_DECL ? 0 : 1)
8224 + (readonly ? 0 : 2)
8225 + (needs_sdata ? 1 : 0)
8226 + (DECL_INITIAL (decl) == 0
8227 || DECL_INITIAL (decl) == error_mark_node) ? 4 : 0);
8228
8229 STRIP_NAME_ENCODING (name, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)));
8230 prefix = prefixes[sec][DECL_ONE_ONLY (decl)];
8231 len = strlen (name) + strlen (prefix);
8232 string = alloca (len + 1);
8233
8234 sprintf (string, "%s%s", prefix, name);
8235
8236 DECL_SECTION_NAME (decl) = build_string (len, string);
8237 }
8238
8239 \f
8240 /* If we are referencing a function that is static or is known to be
8241 in this file, make the SYMBOL_REF special. We can use this to indicate
8242 that we can branch to this function without emitting a no-op after the
8243 call. For real AIX calling sequences, we also replace the
8244 function name with the real name (1 or 2 leading .'s), rather than
8245 the function descriptor name. This saves a lot of overriding code
8246 to read the prefixes. */
8247
8248 void
8249 rs6000_encode_section_info (decl)
8250 tree decl;
8251 {
8252 if (TREE_CODE (decl) == FUNCTION_DECL)
8253 {
8254 rtx sym_ref = XEXP (DECL_RTL (decl), 0);
8255 if ((TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl))
8256 && ! DECL_WEAK (decl))
8257 SYMBOL_REF_FLAG (sym_ref) = 1;
8258
8259 if (DEFAULT_ABI == ABI_AIX)
8260 {
8261 size_t len1 = (DEFAULT_ABI == ABI_AIX) ? 1 : 2;
8262 size_t len2 = strlen (XSTR (sym_ref, 0));
8263 char *str = alloca (len1 + len2 + 1);
8264 str[0] = '.';
8265 str[1] = '.';
8266 memcpy (str + len1, XSTR (sym_ref, 0), len2 + 1);
8267
8268 XSTR (sym_ref, 0) = ggc_alloc_string (str, len1 + len2);
8269 }
8270 }
8271 else if (rs6000_sdata != SDATA_NONE
8272 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
8273 && TREE_CODE (decl) == VAR_DECL)
8274 {
8275 int size = int_size_in_bytes (TREE_TYPE (decl));
8276 tree section_name = DECL_SECTION_NAME (decl);
8277 const char *name = (char *)0;
8278 int len = 0;
8279
8280 if (section_name)
8281 {
8282 if (TREE_CODE (section_name) == STRING_CST)
8283 {
8284 name = TREE_STRING_POINTER (section_name);
8285 len = TREE_STRING_LENGTH (section_name);
8286 }
8287 else
8288 abort ();
8289 }
8290
8291 if ((size > 0 && size <= g_switch_value)
8292 || (name
8293 && ((len == sizeof (".sdata") - 1
8294 && strcmp (name, ".sdata") == 0)
8295 || (len == sizeof (".sdata2") - 1
8296 && strcmp (name, ".sdata2") == 0)
8297 || (len == sizeof (".sbss") - 1
8298 && strcmp (name, ".sbss") == 0)
8299 || (len == sizeof (".sbss2") - 1
8300 && strcmp (name, ".sbss2") == 0)
8301 || (len == sizeof (".PPC.EMB.sdata0") - 1
8302 && strcmp (name, ".PPC.EMB.sdata0") == 0)
8303 || (len == sizeof (".PPC.EMB.sbss0") - 1
8304 && strcmp (name, ".PPC.EMB.sbss0") == 0))))
8305 {
8306 rtx sym_ref = XEXP (DECL_RTL (decl), 0);
8307 size_t len = strlen (XSTR (sym_ref, 0));
8308 char *str = alloca (len + 2);
8309
8310 str[0] = '@';
8311 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
8312 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
8313 }
8314 }
8315 }
8316
8317 #endif /* USING_SVR4_H */
8318
8319 \f
8320 /* Return a REG that occurs in ADDR with coefficient 1.
8321 ADDR can be effectively incremented by incrementing REG.
8322
8323 r0 is special and we must not select it as an address
8324 register by this routine since our caller will try to
8325 increment the returned register via an "la" instruction. */
8326
8327 struct rtx_def *
8328 find_addr_reg (addr)
8329 rtx addr;
8330 {
8331 while (GET_CODE (addr) == PLUS)
8332 {
8333 if (GET_CODE (XEXP (addr, 0)) == REG
8334 && REGNO (XEXP (addr, 0)) != 0)
8335 addr = XEXP (addr, 0);
8336 else if (GET_CODE (XEXP (addr, 1)) == REG
8337 && REGNO (XEXP (addr, 1)) != 0)
8338 addr = XEXP (addr, 1);
8339 else if (CONSTANT_P (XEXP (addr, 0)))
8340 addr = XEXP (addr, 1);
8341 else if (CONSTANT_P (XEXP (addr, 1)))
8342 addr = XEXP (addr, 0);
8343 else
8344 abort ();
8345 }
8346 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
8347 return addr;
8348 abort ();
8349 }
8350
8351 void
8352 rs6000_fatal_bad_address (op)
8353 rtx op;
8354 {
8355 fatal_insn ("bad address", op);
8356 }
8357
8358 /* Called to register all of our global variables with the garbage
8359 collector. */
8360
8361 static void
8362 rs6000_add_gc_roots ()
8363 {
8364 ggc_add_rtx_root (&rs6000_compare_op0, 1);
8365 ggc_add_rtx_root (&rs6000_compare_op1, 1);
8366
8367 toc_hash_table = htab_create (1021, toc_hash_function, toc_hash_eq, NULL);
8368 ggc_add_root (&toc_hash_table, 1, sizeof (toc_hash_table),
8369 toc_hash_mark_table);
8370
8371 #if TARGET_MACHO
8372 machopic_add_gc_roots ();
8373 #endif
8374 }
8375
8376 #if TARGET_MACHO
8377
8378 #if 0
8379 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
8380 reference and a constant. */
8381
8382 int
8383 symbolic_operand (op)
8384 register rtx op;
8385 {
8386 switch (GET_CODE (op))
8387 {
8388 case SYMBOL_REF:
8389 case LABEL_REF:
8390 return 1;
8391 case CONST:
8392 op = XEXP (op, 0);
8393 return (GET_CODE (op) == SYMBOL_REF ||
8394 (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
8395 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
8396 && GET_CODE (XEXP (op, 1)) == CONST_INT);
8397 default:
8398 return 0;
8399 }
8400 }
8401 #endif
8402
8403 #ifdef RS6000_LONG_BRANCH
8404
8405 static tree stub_list = 0;
8406
8407 /* ADD_COMPILER_STUB adds the compiler generated stub for handling
8408 procedure calls to the linked list. */
8409
8410 void
8411 add_compiler_stub (label_name, function_name, line_number)
8412 tree label_name;
8413 tree function_name;
8414 int line_number;
8415 {
8416 tree stub = build_tree_list (function_name, label_name);
8417 TREE_TYPE (stub) = build_int_2 (line_number, 0);
8418 TREE_CHAIN (stub) = stub_list;
8419 stub_list = stub;
8420 }
8421
8422 #define STUB_LABEL_NAME(STUB) TREE_VALUE (STUB)
8423 #define STUB_FUNCTION_NAME(STUB) TREE_PURPOSE (STUB)
8424 #define STUB_LINE_NUMBER(STUB) TREE_INT_CST_LOW (TREE_TYPE (STUB))
8425
8426 /* OUTPUT_COMPILER_STUB outputs the compiler generated stub for handling
8427 procedure calls from the linked list and initializes the linked list. */
8428
8429 void output_compiler_stub ()
8430 {
8431 char tmp_buf[256];
8432 char label_buf[256];
8433 char *label;
8434 tree tmp_stub, stub;
8435
8436 if (!flag_pic)
8437 for (stub = stub_list; stub; stub = TREE_CHAIN (stub))
8438 {
8439 fprintf (asm_out_file,
8440 "%s:\n", IDENTIFIER_POINTER(STUB_LABEL_NAME(stub)));
8441
8442 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
8443 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
8444 fprintf (asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER(stub));
8445 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
8446
8447 if (IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))[0] == '*')
8448 strcpy (label_buf,
8449 IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))+1);
8450 else
8451 {
8452 label_buf[0] = '_';
8453 strcpy (label_buf+1,
8454 IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub)));
8455 }
8456
8457 strcpy (tmp_buf, "lis r12,hi16(");
8458 strcat (tmp_buf, label_buf);
8459 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
8460 strcat (tmp_buf, label_buf);
8461 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
8462 output_asm_insn (tmp_buf, 0);
8463
8464 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
8465 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
8466 fprintf(asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER (stub));
8467 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
8468 }
8469
8470 stub_list = 0;
8471 }
8472
8473 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
8474 already there or not. */
8475
8476 int no_previous_def (function_name)
8477 tree function_name;
8478 {
8479 tree stub;
8480 for (stub = stub_list; stub; stub = TREE_CHAIN (stub))
8481 if (function_name == STUB_FUNCTION_NAME (stub))
8482 return 0;
8483 return 1;
8484 }
8485
8486 /* GET_PREV_LABEL gets the label name from the previous definition of
8487 the function. */
8488
8489 tree get_prev_label (function_name)
8490 tree function_name;
8491 {
8492 tree stub;
8493 for (stub = stub_list; stub; stub = TREE_CHAIN (stub))
8494 if (function_name == STUB_FUNCTION_NAME (stub))
8495 return STUB_LABEL_NAME (stub);
8496 return 0;
8497 }
8498
8499 /* INSN is either a function call or a millicode call. It may have an
8500 unconditional jump in its delay slot.
8501
8502 CALL_DEST is the routine we are calling. */
8503
8504 char *
8505 output_call (insn, call_dest, operand_number)
8506 rtx insn;
8507 rtx call_dest;
8508 int operand_number;
8509 {
8510 static char buf[256];
8511 if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic)
8512 {
8513 tree labelname;
8514 tree funname = get_identifier (XSTR (call_dest, 0));
8515
8516 if (no_previous_def (funname))
8517 {
8518 int line_number;
8519 rtx label_rtx = gen_label_rtx ();
8520 char *label_buf, temp_buf[256];
8521 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
8522 CODE_LABEL_NUMBER (label_rtx));
8523 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
8524 labelname = get_identifier (label_buf);
8525 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
8526 if (insn)
8527 line_number = NOTE_LINE_NUMBER (insn);
8528 add_compiler_stub (labelname, funname, line_number);
8529 }
8530 else
8531 labelname = get_prev_label (funname);
8532
8533 sprintf (buf, "jbsr %%z%d,%.246s",
8534 operand_number, IDENTIFIER_POINTER (labelname));
8535 return buf;
8536 }
8537 else
8538 {
8539 sprintf (buf, "bl %%z%d", operand_number);
8540 return buf;
8541 }
8542 }
8543
8544 #endif /* RS6000_LONG_BRANCH */
8545
8546 #define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N) \
8547 do { \
8548 const char *symbol_ = (SYMBOL); \
8549 char *buffer_ = (BUF); \
8550 if (symbol_[0] == '"') \
8551 { \
8552 sprintf(buffer_, "\"L%d$%s", (N), symbol_+1); \
8553 } \
8554 else if (name_needs_quotes(symbol_)) \
8555 { \
8556 sprintf(buffer_, "\"L%d$%s\"", (N), symbol_); \
8557 } \
8558 else \
8559 { \
8560 sprintf(buffer_, "L%d$%s", (N), symbol_); \
8561 } \
8562 } while (0)
8563
8564
8565 /* Generate PIC and indirect symbol stubs. */
8566
8567 void
8568 machopic_output_stub (file, symb, stub)
8569 FILE *file;
8570 const char *symb, *stub;
8571 {
8572 unsigned int length;
8573 char *binder_name, *symbol_name, *lazy_ptr_name;
8574 char *local_label_0, *local_label_1, *local_label_2;
8575 static int label = 0;
8576
8577 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
8578 STRIP_NAME_ENCODING (symb, symb);
8579
8580 label += 1;
8581
8582 length = strlen (stub);
8583 binder_name = alloca (length + 32);
8584 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
8585
8586 length = strlen (symb);
8587 symbol_name = alloca (length + 32);
8588 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
8589
8590 lazy_ptr_name = alloca (length + 32);
8591 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
8592
8593 local_label_0 = alloca (length + 32);
8594 GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0);
8595
8596 local_label_1 = alloca (length + 32);
8597 GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_1, symb, length, 1);
8598
8599 local_label_2 = alloca (length + 32);
8600 GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_2, symb, length, 2);
8601
8602 if (flag_pic == 2)
8603 machopic_picsymbol_stub_section ();
8604 else
8605 machopic_symbol_stub_section ();
8606
8607 fprintf (file, "%s:\n", stub);
8608 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
8609
8610 if (flag_pic == 2)
8611 {
8612 fprintf (file, "\tmflr r0\n");
8613 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
8614 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
8615 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
8616 lazy_ptr_name, local_label_0);
8617 fprintf (file, "\tmtlr r0\n");
8618 fprintf (file, "\tlwz r12,lo16(%s-%s)(r11)\n",
8619 lazy_ptr_name, local_label_0);
8620 fprintf (file, "\tmtctr r12\n");
8621 fprintf (file, "\taddi r11,r11,lo16(%s-%s)\n",
8622 lazy_ptr_name, local_label_0);
8623 fprintf (file, "\tbctr\n");
8624 }
8625 else
8626 fprintf (file, "non-pure not supported\n");
8627
8628 machopic_lazy_symbol_ptr_section ();
8629 fprintf (file, "%s:\n", lazy_ptr_name);
8630 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
8631 fprintf (file, "\t.long dyld_stub_binding_helper\n");
8632 }
8633
8634 /* Legitimize PIC addresses. If the address is already
8635 position-independent, we return ORIG. Newly generated
8636 position-independent addresses go into a reg. This is REG if non
8637 zero, otherwise we allocate register(s) as necessary. */
8638
8639 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x4000) < 0x8000)
8640
8641 rtx
8642 rs6000_machopic_legitimize_pic_address (orig, mode, reg)
8643 rtx orig;
8644 enum machine_mode mode;
8645 rtx reg;
8646 {
8647 rtx base, offset;
8648
8649 if (reg == NULL && ! reload_in_progress && ! reload_completed)
8650 reg = gen_reg_rtx (Pmode);
8651
8652 if (GET_CODE (orig) == CONST)
8653 {
8654 if (GET_CODE (XEXP (orig, 0)) == PLUS
8655 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
8656 return orig;
8657
8658 if (GET_CODE (XEXP (orig, 0)) == PLUS)
8659 {
8660 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
8661 Pmode, reg);
8662 offset = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
8663 Pmode, reg);
8664 }
8665 else
8666 abort ();
8667
8668 if (GET_CODE (offset) == CONST_INT)
8669 {
8670 if (SMALL_INT (offset))
8671 return plus_constant (base, INTVAL (offset));
8672 else if (! reload_in_progress && ! reload_completed)
8673 offset = force_reg (Pmode, offset);
8674 else
8675 abort ();
8676 }
8677 return gen_rtx (PLUS, Pmode, base, offset);
8678 }
8679
8680 /* Fall back on generic machopic code. */
8681 return machopic_legitimize_pic_address (orig, mode, reg);
8682 }
8683
8684 /* This is just a placeholder to make linking work without having to
8685 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
8686 ever needed for Darwin (not too likely!) this would have to get a
8687 real definition. */
8688
8689 void
8690 toc_section ()
8691 {
8692 }
8693
8694 #endif /* TARGET_MACHO */
8695
8696 #if TARGET_ELF
8697 static unsigned int
8698 rs6000_elf_section_type_flags (decl, name, reloc)
8699 tree decl;
8700 const char *name;
8701 int reloc;
8702 {
8703 unsigned int flags = default_section_type_flags (decl, name, reloc);
8704
8705 if (TARGET_RELOCATABLE)
8706 flags |= SECTION_WRITE;
8707
8708 /* Solaris doesn't like @nobits, and gas can handle .sbss without it. */
8709 flags &= ~SECTION_BSS;
8710
8711 return flags;
8712 }
8713
8714 /* Record an element in the table of global constructors. SYMBOL is
8715 a SYMBOL_REF of the function to be called; PRIORITY is a number
8716 between 0 and MAX_INIT_PRIORITY.
8717
8718 This differs from default_named_section_asm_out_constructor in
8719 that we have special handling for -mrelocatable. */
8720
8721 static void
8722 rs6000_elf_asm_out_constructor (symbol, priority)
8723 rtx symbol;
8724 int priority;
8725 {
8726 const char *section = ".ctors";
8727 char buf[16];
8728
8729 if (priority != DEFAULT_INIT_PRIORITY)
8730 {
8731 sprintf (buf, ".ctors.%.5u",
8732 /* Invert the numbering so the linker puts us in the proper
8733 order; constructors are run from right to left, and the
8734 linker sorts in increasing order. */
8735 MAX_INIT_PRIORITY - priority);
8736 section = buf;
8737 }
8738
8739 named_section_flags (section, SECTION_WRITE, POINTER_SIZE / BITS_PER_UNIT);
8740
8741 if (TARGET_RELOCATABLE)
8742 {
8743 fputs ("\t.long (", asm_out_file);
8744 output_addr_const (asm_out_file, symbol);
8745 fputs (")@fixup\n", asm_out_file);
8746 }
8747 else
8748 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
8749 }
8750
8751 static void
8752 rs6000_elf_asm_out_destructor (symbol, priority)
8753 rtx symbol;
8754 int priority;
8755 {
8756 const char *section = ".dtors";
8757 char buf[16];
8758
8759 if (priority != DEFAULT_INIT_PRIORITY)
8760 {
8761 sprintf (buf, ".dtors.%.5u",
8762 /* Invert the numbering so the linker puts us in the proper
8763 order; constructors are run from right to left, and the
8764 linker sorts in increasing order. */
8765 MAX_INIT_PRIORITY - priority);
8766 section = buf;
8767 }
8768
8769 named_section_flags (section, SECTION_WRITE, POINTER_SIZE / BITS_PER_UNIT);
8770
8771 if (TARGET_RELOCATABLE)
8772 {
8773 fputs ("\t.long (", asm_out_file);
8774 output_addr_const (asm_out_file, symbol);
8775 fputs (")@fixup\n", asm_out_file);
8776 }
8777 else
8778 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
8779 }
8780 #endif
8781
8782 #ifdef OBJECT_FORMAT_COFF
8783 static void
8784 xcoff_asm_named_section (name, flags, align)
8785 const char *name;
8786 unsigned int flags ATTRIBUTE_UNUSED;
8787 unsigned int align ATTRIBUTE_UNUSED;
8788 {
8789 fprintf (asm_out_file, "\t.csect %s\n", name);
8790 }
8791 #endif
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