1 ;; Predicate definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2004-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return true if OP is either a i387 or SSE fp register.
21 (define_predicate "any_fp_register_operand"
22 (and (match_code "reg")
23 (match_test "ANY_FP_REGNO_P (REGNO (op))")))
25 ;; Return true if OP is an i387 fp register.
26 (define_predicate "fp_register_operand"
27 (and (match_code "reg")
28 (match_test "STACK_REGNO_P (REGNO (op))")))
30 ;; Return true if OP is a non-fp register_operand.
31 (define_predicate "register_and_not_any_fp_reg_operand"
32 (and (match_code "reg")
33 (not (match_test "ANY_FP_REGNO_P (REGNO (op))"))))
35 ;; True if the operand is a GENERAL class register.
36 (define_predicate "general_reg_operand"
37 (and (match_code "reg")
38 (match_test "GENERAL_REG_P (op)")))
40 ;; Return true if OP is a register operand other than an i387 fp register.
41 (define_predicate "register_and_not_fp_reg_operand"
42 (and (match_code "reg")
43 (not (match_test "STACK_REGNO_P (REGNO (op))"))))
45 ;; True if the operand is an MMX register.
46 (define_predicate "mmx_reg_operand"
47 (and (match_code "reg")
48 (match_test "MMX_REGNO_P (REGNO (op))")))
50 ;; True if the operand is an SSE register.
51 (define_predicate "sse_reg_operand"
52 (and (match_code "reg")
53 (match_test "SSE_REGNO_P (REGNO (op))")))
55 ;; True if the operand is an AVX-512 new register.
56 (define_predicate "ext_sse_reg_operand"
57 (and (match_code "reg")
58 (match_test "EXT_REX_SSE_REGNO_P (REGNO (op))")))
60 ;; True if the operand is an AVX-512 mask register.
61 (define_predicate "mask_reg_operand"
62 (and (match_code "reg")
63 (match_test "MASK_REGNO_P (REGNO (op))")))
65 ;; True if the operand is a Q_REGS class register.
66 (define_predicate "q_regs_operand"
67 (match_operand 0 "register_operand")
69 if (GET_CODE (op) == SUBREG)
71 return ANY_QI_REG_P (op);
74 ;; Match an SI or HImode register for a zero_extract.
75 (define_special_predicate "ext_register_operand"
76 (match_operand 0 "register_operand")
78 if ((!TARGET_64BIT || GET_MODE (op) != DImode)
79 && GET_MODE (op) != SImode && GET_MODE (op) != HImode)
81 if (GET_CODE (op) == SUBREG)
84 /* Be careful to accept only registers having upper parts. */
86 && (REGNO (op) > LAST_VIRTUAL_REGISTER || REGNO (op) <= BX_REG));
89 ;; Match nonimmediate operands, but exclude memory operands on 64bit targets.
90 (define_predicate "nonimmediate_x64nomem_operand"
91 (if_then_else (match_test "TARGET_64BIT")
92 (match_operand 0 "register_operand")
93 (match_operand 0 "nonimmediate_operand")))
95 ;; Match general operands, but exclude memory operands on 64bit targets.
96 (define_predicate "general_x64nomem_operand"
97 (if_then_else (match_test "TARGET_64BIT")
98 (match_operand 0 "nonmemory_operand")
99 (match_operand 0 "general_operand")))
101 ;; Return true if op is the AX register.
102 (define_predicate "ax_reg_operand"
103 (and (match_code "reg")
104 (match_test "REGNO (op) == AX_REG")))
106 ;; Return true if op is the flags register.
107 (define_predicate "flags_reg_operand"
108 (and (match_code "reg")
109 (match_test "REGNO (op) == FLAGS_REG")))
111 ;; Return true if op is one of QImode registers: %[abcd][hl].
112 (define_predicate "QIreg_operand"
113 (match_test "QI_REG_P (op)"))
115 ;; Return true if op is a QImode register operand other than
117 (define_predicate "ext_QIreg_operand"
118 (and (match_code "reg")
119 (match_test "TARGET_64BIT")
120 (match_test "REGNO (op) > BX_REG")))
122 ;; Return true if VALUE can be stored in a sign extended immediate field.
123 (define_predicate "x86_64_immediate_operand"
124 (match_code "const_int,symbol_ref,label_ref,const")
127 return immediate_operand (op, mode);
129 switch (GET_CODE (op))
132 /* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
133 to be at least 32 and this all acceptable constants are
134 represented as CONST_INT. */
135 if (HOST_BITS_PER_WIDE_INT == 32)
139 HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
140 return trunc_int_for_mode (val, SImode) == val;
145 /* For certain code models, the symbolic references are known to fit.
146 in CM_SMALL_PIC model we know it fits if it is local to the shared
147 library. Don't count TLS SYMBOL_REFs here, since they should fit
148 only if inside of UNSPEC handled below. */
149 /* TLS symbols are not constant. */
150 if (SYMBOL_REF_TLS_MODEL (op))
152 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
153 || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
156 /* For certain code models, the code is near as well. */
157 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
158 || ix86_cmodel == CM_KERNEL);
161 /* We also may accept the offsetted memory references in certain
163 if (GET_CODE (XEXP (op, 0)) == UNSPEC)
164 switch (XINT (XEXP (op, 0), 1))
166 case UNSPEC_GOTPCREL:
168 case UNSPEC_GOTNTPOFF:
175 if (GET_CODE (XEXP (op, 0)) == PLUS)
177 rtx op1 = XEXP (XEXP (op, 0), 0);
178 rtx op2 = XEXP (XEXP (op, 0), 1);
179 HOST_WIDE_INT offset;
181 if (ix86_cmodel == CM_LARGE)
183 if (!CONST_INT_P (op2))
185 offset = trunc_int_for_mode (INTVAL (op2), DImode);
186 switch (GET_CODE (op1))
189 /* TLS symbols are not constant. */
190 if (SYMBOL_REF_TLS_MODEL (op1))
192 /* For CM_SMALL assume that latest object is 16MB before
193 end of 31bits boundary. We may also accept pretty
194 large negative constants knowing that all objects are
195 in the positive half of address space. */
196 if ((ix86_cmodel == CM_SMALL
197 || (ix86_cmodel == CM_MEDIUM
198 && !SYMBOL_REF_FAR_ADDR_P (op1)))
199 && offset < 16*1024*1024
200 && trunc_int_for_mode (offset, SImode) == offset)
202 /* For CM_KERNEL we know that all object resist in the
203 negative half of 32bits address space. We may not
204 accept negative offsets, since they may be just off
205 and we may accept pretty large positive ones. */
206 if (ix86_cmodel == CM_KERNEL
208 && trunc_int_for_mode (offset, SImode) == offset)
213 /* These conditions are similar to SYMBOL_REF ones, just the
214 constraints for code models differ. */
215 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
216 && offset < 16*1024*1024
217 && trunc_int_for_mode (offset, SImode) == offset)
219 if (ix86_cmodel == CM_KERNEL
221 && trunc_int_for_mode (offset, SImode) == offset)
226 switch (XINT (op1, 1))
230 if (trunc_int_for_mode (offset, SImode) == offset)
248 ;; Return true if VALUE can be stored in the zero extended immediate field.
249 (define_predicate "x86_64_zext_immediate_operand"
250 (match_code "const_double,const_int,symbol_ref,label_ref,const")
252 switch (GET_CODE (op))
255 if (HOST_BITS_PER_WIDE_INT == 32)
256 return (GET_MODE (op) == VOIDmode && !CONST_DOUBLE_HIGH (op));
261 if (HOST_BITS_PER_WIDE_INT == 32)
262 return INTVAL (op) >= 0;
264 return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
267 /* For certain code models, the symbolic references are known to fit. */
268 /* TLS symbols are not constant. */
269 if (SYMBOL_REF_TLS_MODEL (op))
271 return (ix86_cmodel == CM_SMALL
272 || (ix86_cmodel == CM_MEDIUM
273 && !SYMBOL_REF_FAR_ADDR_P (op)));
276 /* For certain code models, the code is near as well. */
277 return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
280 /* We also may accept the offsetted memory references in certain
282 if (GET_CODE (XEXP (op, 0)) == PLUS)
284 rtx op1 = XEXP (XEXP (op, 0), 0);
285 rtx op2 = XEXP (XEXP (op, 0), 1);
287 if (ix86_cmodel == CM_LARGE)
289 switch (GET_CODE (op1))
292 /* TLS symbols are not constant. */
293 if (SYMBOL_REF_TLS_MODEL (op1))
295 /* For small code model we may accept pretty large positive
296 offsets, since one bit is available for free. Negative
297 offsets are limited by the size of NULL pointer area
298 specified by the ABI. */
299 if ((ix86_cmodel == CM_SMALL
300 || (ix86_cmodel == CM_MEDIUM
301 && !SYMBOL_REF_FAR_ADDR_P (op1)))
303 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
304 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
306 /* ??? For the kernel, we may accept adjustment of
307 -0x10000000, since we know that it will just convert
308 negative address space to positive, but perhaps this
309 is not worthwhile. */
313 /* These conditions are similar to SYMBOL_REF ones, just the
314 constraints for code models differ. */
315 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
317 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
318 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
334 ;; Return true if OP is general operand representable on x86_64.
335 (define_predicate "x86_64_general_operand"
336 (if_then_else (match_test "TARGET_64BIT")
337 (ior (match_operand 0 "nonimmediate_operand")
338 (match_operand 0 "x86_64_immediate_operand"))
339 (match_operand 0 "general_operand")))
341 ;; Return true if OP is representable on x86_64 as zero-extended operand.
342 ;; This predicate is used in zero-extending conversion operations that
343 ;; require non-VOIDmode immediate operands.
344 (define_predicate "x86_64_zext_operand"
345 (if_then_else (match_test "TARGET_64BIT")
346 (ior (match_operand 0 "nonimmediate_operand")
347 (and (match_operand 0 "x86_64_zext_immediate_operand")
348 (match_test "GET_MODE (op) != VOIDmode")))
349 (match_operand 0 "nonimmediate_operand")))
351 ;; Return true if OP is general operand representable on x86_64
352 ;; as either sign extended or zero extended constant.
353 (define_predicate "x86_64_szext_general_operand"
354 (if_then_else (match_test "TARGET_64BIT")
355 (ior (match_operand 0 "nonimmediate_operand")
356 (match_operand 0 "x86_64_immediate_operand")
357 (match_operand 0 "x86_64_zext_immediate_operand"))
358 (match_operand 0 "general_operand")))
360 ;; Return true if OP is nonmemory operand representable on x86_64.
361 (define_predicate "x86_64_nonmemory_operand"
362 (if_then_else (match_test "TARGET_64BIT")
363 (ior (match_operand 0 "register_operand")
364 (match_operand 0 "x86_64_immediate_operand"))
365 (match_operand 0 "nonmemory_operand")))
367 ;; Return true if OP is nonmemory operand representable on x86_64.
368 (define_predicate "x86_64_szext_nonmemory_operand"
369 (if_then_else (match_test "TARGET_64BIT")
370 (ior (match_operand 0 "register_operand")
371 (match_operand 0 "x86_64_immediate_operand")
372 (match_operand 0 "x86_64_zext_immediate_operand"))
373 (match_operand 0 "nonmemory_operand")))
375 ;; Return true when operand is PIC expression that can be computed by lea
377 (define_predicate "pic_32bit_operand"
378 (match_code "const,symbol_ref,label_ref")
383 /* Rule out relocations that translate into 64bit constants. */
384 if (TARGET_64BIT && GET_CODE (op) == CONST)
387 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
389 if (GET_CODE (op) == UNSPEC
390 && (XINT (op, 1) == UNSPEC_GOTOFF
391 || XINT (op, 1) == UNSPEC_GOT))
395 return symbolic_operand (op, mode);
398 ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
399 (define_predicate "x86_64_movabs_operand"
400 (and (match_operand 0 "nonmemory_operand")
401 (not (match_operand 0 "pic_32bit_operand"))))
403 ;; Return true if OP is either a symbol reference or a sum of a symbol
404 ;; reference and a constant.
405 (define_predicate "symbolic_operand"
406 (match_code "symbol_ref,label_ref,const")
408 switch (GET_CODE (op))
416 if (GET_CODE (op) == SYMBOL_REF
417 || GET_CODE (op) == LABEL_REF
418 || (GET_CODE (op) == UNSPEC
419 && (XINT (op, 1) == UNSPEC_GOT
420 || XINT (op, 1) == UNSPEC_GOTOFF
421 || XINT (op, 1) == UNSPEC_PCREL
422 || XINT (op, 1) == UNSPEC_GOTPCREL)))
424 if (GET_CODE (op) != PLUS
425 || !CONST_INT_P (XEXP (op, 1)))
429 if (GET_CODE (op) == SYMBOL_REF
430 || GET_CODE (op) == LABEL_REF)
432 /* Only @GOTOFF gets offsets. */
433 if (GET_CODE (op) != UNSPEC
434 || XINT (op, 1) != UNSPEC_GOTOFF)
437 op = XVECEXP (op, 0, 0);
438 if (GET_CODE (op) == SYMBOL_REF
439 || GET_CODE (op) == LABEL_REF)
448 ;; Return true if OP is a symbolic operand that resolves locally.
449 (define_predicate "local_symbolic_operand"
450 (match_code "const,label_ref,symbol_ref")
452 if (GET_CODE (op) == CONST
453 && GET_CODE (XEXP (op, 0)) == PLUS
454 && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
455 op = XEXP (XEXP (op, 0), 0);
457 if (GET_CODE (op) == LABEL_REF)
460 if (GET_CODE (op) != SYMBOL_REF)
463 if (SYMBOL_REF_TLS_MODEL (op))
466 /* Dll-imported symbols are always external. */
467 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
469 if (SYMBOL_REF_LOCAL_P (op))
472 /* There is, however, a not insubstantial body of code in the rest of
473 the compiler that assumes it can just stick the results of
474 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
475 /* ??? This is a hack. Should update the body of the compiler to
476 always create a DECL an invoke targetm.encode_section_info. */
477 if (strncmp (XSTR (op, 0), internal_label_prefix,
478 internal_label_prefix_len) == 0)
484 ;; Test for a legitimate @GOTOFF operand.
486 ;; VxWorks does not impose a fixed gap between segments; the run-time
487 ;; gap can be different from the object-file gap. We therefore can't
488 ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
489 ;; same segment as the GOT. Unfortunately, the flexibility of linker
490 ;; scripts means that we can't be sure of that in general, so assume
491 ;; that @GOTOFF is never valid on VxWorks.
492 (define_predicate "gotoff_operand"
493 (and (not (match_test "TARGET_VXWORKS_RTP"))
494 (match_operand 0 "local_symbolic_operand")))
496 ;; Test for various thread-local symbols.
497 (define_special_predicate "tls_symbolic_operand"
498 (and (match_code "symbol_ref")
499 (match_test "SYMBOL_REF_TLS_MODEL (op)")))
501 (define_special_predicate "tls_modbase_operand"
502 (and (match_code "symbol_ref")
503 (match_test "op == ix86_tls_module_base ()")))
505 ;; Test for a pc-relative call operand
506 (define_predicate "constant_call_address_operand"
507 (match_code "symbol_ref")
509 if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
511 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
516 ;; P6 processors will jump to the address after the decrement when %esp
517 ;; is used as a call operand, so they will execute return address as a code.
518 ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
520 (define_predicate "call_register_no_elim_operand"
521 (match_operand 0 "register_operand")
523 if (GET_CODE (op) == SUBREG)
524 op = SUBREG_REG (op);
526 if (!TARGET_64BIT && op == stack_pointer_rtx)
529 return register_no_elim_operand (op, mode);
532 ;; True for any non-virtual or eliminable register. Used in places where
533 ;; instantiation of such a register may cause the pattern to not be recognized.
534 (define_predicate "register_no_elim_operand"
535 (match_operand 0 "register_operand")
537 if (GET_CODE (op) == SUBREG)
538 op = SUBREG_REG (op);
539 return !(op == arg_pointer_rtx
540 || op == frame_pointer_rtx
541 || IN_RANGE (REGNO (op),
542 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER));
545 ;; Similarly, but include the stack pointer. This is used to prevent esp
546 ;; from being used as an index reg.
547 (define_predicate "index_register_operand"
548 (match_operand 0 "register_operand")
550 if (GET_CODE (op) == SUBREG)
551 op = SUBREG_REG (op);
552 if (reload_in_progress || reload_completed)
553 return REG_OK_FOR_INDEX_STRICT_P (op);
555 return REG_OK_FOR_INDEX_NONSTRICT_P (op);
558 ;; Return false if this is any eliminable register. Otherwise general_operand.
559 (define_predicate "general_no_elim_operand"
560 (if_then_else (match_code "reg,subreg")
561 (match_operand 0 "register_no_elim_operand")
562 (match_operand 0 "general_operand")))
564 ;; Return false if this is any eliminable register. Otherwise
565 ;; register_operand or a constant.
566 (define_predicate "nonmemory_no_elim_operand"
567 (ior (match_operand 0 "register_no_elim_operand")
568 (match_operand 0 "immediate_operand")))
570 ;; Test for a valid operand for indirect branch.
571 (define_predicate "indirect_branch_operand"
572 (ior (match_operand 0 "register_operand")
573 (and (not (match_test "TARGET_X32"))
574 (match_operand 0 "memory_operand"))))
576 ;; Test for a valid operand for a call instruction.
577 ;; Allow constant call address operands in Pmode only.
578 (define_special_predicate "call_insn_operand"
579 (ior (match_test "constant_call_address_operand
580 (op, mode == VOIDmode ? mode : Pmode)")
581 (match_operand 0 "call_register_no_elim_operand")
582 (and (not (match_test "TARGET_X32"))
583 (match_operand 0 "memory_operand"))))
585 ;; Similarly, but for tail calls, in which we cannot allow memory references.
586 (define_special_predicate "sibcall_insn_operand"
587 (ior (match_test "constant_call_address_operand
588 (op, mode == VOIDmode ? mode : Pmode)")
589 (match_operand 0 "register_no_elim_operand")))
591 ;; Return true if OP is a call from MS ABI to SYSV ABI function.
592 (define_predicate "call_rex64_ms_sysv_operation"
593 (match_code "parallel")
595 unsigned creg_size = ARRAY_SIZE (x86_64_ms_sysv_extra_clobbered_registers);
598 if ((unsigned) XVECLEN (op, 0) != creg_size + 2)
601 for (i = 0; i < creg_size; i++)
603 rtx elt = XVECEXP (op, 0, i+2);
604 enum machine_mode mode;
607 if (GET_CODE (elt) != CLOBBER
608 || GET_CODE (SET_DEST (elt)) != REG)
611 regno = x86_64_ms_sysv_extra_clobbered_registers[i];
612 mode = SSE_REGNO_P (regno) ? TImode : DImode;
614 if (GET_MODE (SET_DEST (elt)) != mode
615 || REGNO (SET_DEST (elt)) != regno)
621 ;; Match exactly zero.
622 (define_predicate "const0_operand"
623 (match_code "const_int,const_double,const_vector")
625 if (mode == VOIDmode)
626 mode = GET_MODE (op);
627 return op == CONST0_RTX (mode);
630 ;; Match one or vector filled with ones.
631 (define_predicate "const1_operand"
632 (match_code "const_int,const_double,const_vector")
634 if (mode == VOIDmode)
635 mode = GET_MODE (op);
636 return op == CONST1_RTX (mode);
639 ;; Match exactly eight.
640 (define_predicate "const8_operand"
641 (and (match_code "const_int")
642 (match_test "INTVAL (op) == 8")))
644 ;; Match exactly 128.
645 (define_predicate "const128_operand"
646 (and (match_code "const_int")
647 (match_test "INTVAL (op) == 128")))
649 ;; Match exactly 0x0FFFFFFFF in anddi as a zero-extension operation
650 (define_predicate "const_32bit_mask"
651 (and (match_code "const_int")
652 (match_test "trunc_int_for_mode (INTVAL (op), DImode)
653 == (HOST_WIDE_INT) 0xffffffff")))
655 ;; Match 2, 4, or 8. Used for leal multiplicands.
656 (define_predicate "const248_operand"
657 (match_code "const_int")
659 HOST_WIDE_INT i = INTVAL (op);
660 return i == 2 || i == 4 || i == 8;
663 ;; Match 2, 3, 5, or 6
664 (define_predicate "const2356_operand"
665 (match_code "const_int")
667 HOST_WIDE_INT i = INTVAL (op);
668 return i == 2 || i == 3 || i == 5 || i == 6;
671 ;; Match 1, 2, 4, or 8
672 (define_predicate "const1248_operand"
673 (match_code "const_int")
675 HOST_WIDE_INT i = INTVAL (op);
676 return i == 1 || i == 2 || i == 4 || i == 8;
679 ;; Match 3, 5, or 9. Used for leal multiplicands.
680 (define_predicate "const359_operand"
681 (match_code "const_int")
683 HOST_WIDE_INT i = INTVAL (op);
684 return i == 3 || i == 5 || i == 9;
687 ;; Match 4 or 8 to 11. Used for embeded rounding.
688 (define_predicate "const_4_or_8_to_11_operand"
689 (match_code "const_int")
691 HOST_WIDE_INT i = INTVAL (op);
692 return i == 4 || (i >= 8 && i <= 11);
695 ;; Match 4 or 8. Used for SAE.
696 (define_predicate "const48_operand"
697 (match_code "const_int")
699 HOST_WIDE_INT i = INTVAL (op);
700 return i == 4 || i == 8;
704 (define_predicate "const_0_to_1_operand"
705 (and (match_code "const_int")
706 (ior (match_test "op == const0_rtx")
707 (match_test "op == const1_rtx"))))
710 (define_predicate "const_0_to_3_operand"
711 (and (match_code "const_int")
712 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
715 (define_predicate "const_0_to_4_operand"
716 (and (match_code "const_int")
717 (match_test "IN_RANGE (INTVAL (op), 0, 4)")))
720 (define_predicate "const_0_to_5_operand"
721 (and (match_code "const_int")
722 (match_test "IN_RANGE (INTVAL (op), 0, 5)")))
725 (define_predicate "const_0_to_7_operand"
726 (and (match_code "const_int")
727 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
730 (define_predicate "const_0_to_15_operand"
731 (and (match_code "const_int")
732 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
735 (define_predicate "const_0_to_31_operand"
736 (and (match_code "const_int")
737 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
740 (define_predicate "const_0_to_63_operand"
741 (and (match_code "const_int")
742 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
745 (define_predicate "const_0_to_255_operand"
746 (and (match_code "const_int")
747 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
749 ;; Match (0 to 255) * 8
750 (define_predicate "const_0_to_255_mul_8_operand"
751 (match_code "const_int")
753 unsigned HOST_WIDE_INT val = INTVAL (op);
754 return val <= 255*8 && val % 8 == 0;
757 ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
758 ;; for shift & compare patterns, as shifting by 0 does not change flags).
759 (define_predicate "const_1_to_31_operand"
760 (and (match_code "const_int")
761 (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
763 ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
764 ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
765 (define_predicate "const_1_to_63_operand"
766 (and (match_code "const_int")
767 (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
770 (define_predicate "const_2_to_3_operand"
771 (and (match_code "const_int")
772 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
775 (define_predicate "const_4_to_5_operand"
776 (and (match_code "const_int")
777 (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
780 (define_predicate "const_4_to_7_operand"
781 (and (match_code "const_int")
782 (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
785 (define_predicate "const_6_to_7_operand"
786 (and (match_code "const_int")
787 (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
790 (define_predicate "const_8_to_9_operand"
791 (and (match_code "const_int")
792 (match_test "IN_RANGE (INTVAL (op), 8, 9)")))
795 (define_predicate "const_8_to_11_operand"
796 (and (match_code "const_int")
797 (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
800 (define_predicate "const_8_to_15_operand"
801 (and (match_code "const_int")
802 (match_test "IN_RANGE (INTVAL (op), 8, 15)")))
805 (define_predicate "const_10_to_11_operand"
806 (and (match_code "const_int")
807 (match_test "IN_RANGE (INTVAL (op), 10, 11)")))
810 (define_predicate "const_12_to_13_operand"
811 (and (match_code "const_int")
812 (match_test "IN_RANGE (INTVAL (op), 12, 13)")))
815 (define_predicate "const_12_to_15_operand"
816 (and (match_code "const_int")
817 (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
820 (define_predicate "const_14_to_15_operand"
821 (and (match_code "const_int")
822 (match_test "IN_RANGE (INTVAL (op), 14, 15)")))
825 (define_predicate "const_16_to_19_operand"
826 (and (match_code "const_int")
827 (match_test "IN_RANGE (INTVAL (op), 16, 19)")))
830 (define_predicate "const_16_to_31_operand"
831 (and (match_code "const_int")
832 (match_test "IN_RANGE (INTVAL (op), 16, 31)")))
835 (define_predicate "const_20_to_23_operand"
836 (and (match_code "const_int")
837 (match_test "IN_RANGE (INTVAL (op), 20, 23)")))
840 (define_predicate "const_24_to_27_operand"
841 (and (match_code "const_int")
842 (match_test "IN_RANGE (INTVAL (op), 24, 27)")))
845 (define_predicate "const_28_to_31_operand"
846 (and (match_code "const_int")
847 (match_test "IN_RANGE (INTVAL (op), 28, 31)")))
849 ;; True if this is a constant appropriate for an increment or decrement.
850 (define_predicate "incdec_operand"
851 (match_code "const_int")
853 /* On Pentium4, the inc and dec operations causes extra dependency on flag
854 registers, since carry flag is not set. */
855 if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
857 return op == const1_rtx || op == constm1_rtx;
860 ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
861 (define_predicate "reg_or_pm1_operand"
862 (ior (match_operand 0 "register_operand")
863 (and (match_code "const_int")
864 (ior (match_test "op == const1_rtx")
865 (match_test "op == constm1_rtx")))))
867 ;; True if OP is acceptable as operand of DImode shift expander.
868 (define_predicate "shiftdi_operand"
869 (if_then_else (match_test "TARGET_64BIT")
870 (match_operand 0 "nonimmediate_operand")
871 (match_operand 0 "register_operand")))
873 (define_predicate "ashldi_input_operand"
874 (if_then_else (match_test "TARGET_64BIT")
875 (match_operand 0 "nonimmediate_operand")
876 (match_operand 0 "reg_or_pm1_operand")))
878 ;; Return true if OP is a vector load from the constant pool with just
879 ;; the first element nonzero.
880 (define_predicate "zero_extended_scalar_load_operand"
884 op = maybe_get_pool_constant (op);
886 if (!(op && GET_CODE (op) == CONST_VECTOR))
889 n_elts = CONST_VECTOR_NUNITS (op);
891 for (n_elts--; n_elts > 0; n_elts--)
893 rtx elt = CONST_VECTOR_ELT (op, n_elts);
894 if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
900 /* Return true if operand is a vector constant that is all ones. */
901 (define_predicate "vector_all_ones_operand"
902 (match_code "const_vector")
904 int nunits = GET_MODE_NUNITS (mode);
906 if (GET_CODE (op) == CONST_VECTOR
907 && CONST_VECTOR_NUNITS (op) == nunits)
910 for (i = 0; i < nunits; ++i)
912 rtx x = CONST_VECTOR_ELT (op, i);
913 if (x != constm1_rtx)
922 ; Return true when OP is operand acceptable for standard SSE move.
923 (define_predicate "vector_move_operand"
924 (ior (match_operand 0 "nonimmediate_operand")
925 (match_operand 0 "const0_operand")))
927 ;; Return true when OP is either nonimmediate operand, or any
929 (define_predicate "nonimmediate_or_const_vector_operand"
930 (ior (match_operand 0 "nonimmediate_operand")
931 (match_code "const_vector")))
933 ;; Return true when OP is nonimmediate or standard SSE constant.
934 (define_predicate "nonimmediate_or_sse_const_operand"
935 (match_operand 0 "general_operand")
937 if (nonimmediate_operand (op, mode))
939 if (standard_sse_constant_p (op) > 0)
944 ;; Return true if OP is a register or a zero.
945 (define_predicate "reg_or_0_operand"
946 (ior (match_operand 0 "register_operand")
947 (match_operand 0 "const0_operand")))
949 ;; Return true for RTX codes that force SImode address.
950 (define_predicate "SImode_address_operand"
951 (match_code "subreg,zero_extend,and"))
953 ;; Return true if op if a valid address for LEA, and does not contain
954 ;; a segment override. Defined as a special predicate to allow
955 ;; mode-less const_int operands pass to address_operand.
956 (define_special_predicate "address_no_seg_operand"
957 (match_operand 0 "address_operand")
959 struct ix86_address parts;
962 ok = ix86_decompose_address (op, &parts);
964 return parts.seg == SEG_DEFAULT;
967 ;; Return true if op if a valid base register, displacement or
968 ;; sum of base register and displacement for VSIB addressing.
969 (define_predicate "vsib_address_operand"
970 (match_operand 0 "address_operand")
972 struct ix86_address parts;
976 ok = ix86_decompose_address (op, &parts);
978 if (parts.index || parts.seg != SEG_DEFAULT)
981 /* VSIB addressing doesn't support (%rip). */
985 if (GET_CODE (disp) == CONST)
987 disp = XEXP (disp, 0);
988 if (GET_CODE (disp) == PLUS)
989 disp = XEXP (disp, 0);
990 if (GET_CODE (disp) == UNSPEC)
991 switch (XINT (disp, 1))
993 case UNSPEC_GOTPCREL:
995 case UNSPEC_GOTNTPOFF:
1001 && (GET_CODE (disp) == SYMBOL_REF
1002 || GET_CODE (disp) == LABEL_REF))
1009 (define_predicate "vsib_mem_operator"
1012 ;; Return true if the rtx is known to be at least 32 bits aligned.
1013 (define_predicate "aligned_operand"
1014 (match_operand 0 "general_operand")
1016 struct ix86_address parts;
1019 /* Registers and immediate operands are always "aligned". */
1023 /* All patterns using aligned_operand on memory operands ends up
1024 in promoting memory operand to 64bit and thus causing memory mismatch. */
1025 if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
1028 /* Don't even try to do any aligned optimizations with volatiles. */
1029 if (MEM_VOLATILE_P (op))
1032 if (MEM_ALIGN (op) >= 32)
1037 /* Pushes and pops are only valid on the stack pointer. */
1038 if (GET_CODE (op) == PRE_DEC
1039 || GET_CODE (op) == POST_INC)
1042 /* Decode the address. */
1043 ok = ix86_decompose_address (op, &parts);
1046 if (parts.base && GET_CODE (parts.base) == SUBREG)
1047 parts.base = SUBREG_REG (parts.base);
1048 if (parts.index && GET_CODE (parts.index) == SUBREG)
1049 parts.index = SUBREG_REG (parts.index);
1051 /* Look for some component that isn't known to be aligned. */
1054 if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
1059 if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
1064 if (!CONST_INT_P (parts.disp)
1065 || (INTVAL (parts.disp) & 3))
1069 /* Didn't find one -- this must be an aligned address. */
1073 ;; Return true if OP is memory operand with a displacement.
1074 (define_predicate "memory_displacement_operand"
1075 (match_operand 0 "memory_operand")
1077 struct ix86_address parts;
1080 ok = ix86_decompose_address (XEXP (op, 0), &parts);
1082 return parts.disp != NULL_RTX;
1085 ;; Return true if OP is memory operand with a displacement only.
1086 (define_predicate "memory_displacement_only_operand"
1087 (match_operand 0 "memory_operand")
1089 struct ix86_address parts;
1095 ok = ix86_decompose_address (XEXP (op, 0), &parts);
1098 if (parts.base || parts.index)
1101 return parts.disp != NULL_RTX;
1104 ;; Return true if OP is memory operand which will need zero or
1105 ;; one register at most, not counting stack pointer or frame pointer.
1106 (define_predicate "cmpxchg8b_pic_memory_operand"
1107 (match_operand 0 "memory_operand")
1109 struct ix86_address parts;
1112 if (TARGET_64BIT || !flag_pic)
1115 ok = ix86_decompose_address (XEXP (op, 0), &parts);
1118 if (parts.base && GET_CODE (parts.base) == SUBREG)
1119 parts.base = SUBREG_REG (parts.base);
1120 if (parts.index && GET_CODE (parts.index) == SUBREG)
1121 parts.index = SUBREG_REG (parts.index);
1123 if (parts.base == NULL_RTX
1124 || parts.base == arg_pointer_rtx
1125 || parts.base == frame_pointer_rtx
1126 || parts.base == hard_frame_pointer_rtx
1127 || parts.base == stack_pointer_rtx)
1130 if (parts.index == NULL_RTX
1131 || parts.index == arg_pointer_rtx
1132 || parts.index == frame_pointer_rtx
1133 || parts.index == hard_frame_pointer_rtx
1134 || parts.index == stack_pointer_rtx)
1141 ;; Return true if OP is memory operand that cannot be represented
1142 ;; by the modRM array.
1143 (define_predicate "long_memory_operand"
1144 (and (match_operand 0 "memory_operand")
1145 (match_test "memory_address_length (op, false)")))
1147 ;; Return true if OP is a comparison operator that can be issued by fcmov.
1148 (define_predicate "fcmov_comparison_operator"
1149 (match_operand 0 "comparison_operator")
1151 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1152 enum rtx_code code = GET_CODE (op);
1154 if (inmode == CCFPmode || inmode == CCFPUmode)
1156 if (!ix86_trivial_fp_comparison_operator (op, mode))
1158 code = ix86_fp_compare_code_to_integer (code);
1160 /* i387 supports just limited amount of conditional codes. */
1163 case LTU: case GTU: case LEU: case GEU:
1164 if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode
1165 || inmode == CCCmode)
1168 case ORDERED: case UNORDERED:
1176 ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
1177 ;; The first set are supported directly; the second set can't be done with
1178 ;; full IEEE support, i.e. NaNs.
1180 (define_predicate "sse_comparison_operator"
1181 (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
1182 (and (match_test "TARGET_AVX")
1183 (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
1185 (define_predicate "ix86_comparison_int_operator"
1186 (match_code "ne,eq,ge,gt,le,lt"))
1188 (define_predicate "ix86_comparison_uns_operator"
1189 (match_code "ne,eq,geu,gtu,leu,ltu"))
1191 (define_predicate "bt_comparison_operator"
1192 (match_code "ne,eq"))
1194 ;; Return true if OP is a valid comparison operator in valid mode.
1195 (define_predicate "ix86_comparison_operator"
1196 (match_operand 0 "comparison_operator")
1198 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1199 enum rtx_code code = GET_CODE (op);
1201 if (inmode == CCFPmode || inmode == CCFPUmode)
1202 return ix86_trivial_fp_comparison_operator (op, mode);
1209 if (inmode == CCmode || inmode == CCGCmode
1210 || inmode == CCGOCmode || inmode == CCNOmode)
1213 case LTU: case GTU: case LEU: case GEU:
1214 if (inmode == CCmode || inmode == CCCmode)
1217 case ORDERED: case UNORDERED:
1218 if (inmode == CCmode)
1222 if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1230 ;; Return true if OP is a valid comparison operator
1231 ;; testing carry flag to be set.
1232 (define_predicate "ix86_carry_flag_operator"
1233 (match_code "ltu,lt,unlt,gtu,gt,ungt,le,unle,ge,unge,ltgt,uneq")
1235 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1236 enum rtx_code code = GET_CODE (op);
1238 if (inmode == CCFPmode || inmode == CCFPUmode)
1240 if (!ix86_trivial_fp_comparison_operator (op, mode))
1242 code = ix86_fp_compare_code_to_integer (code);
1244 else if (inmode == CCCmode)
1245 return code == LTU || code == GTU;
1246 else if (inmode != CCmode)
1252 ;; Return true if this comparison only requires testing one flag bit.
1253 (define_predicate "ix86_trivial_fp_comparison_operator"
1254 (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1256 ;; Return true if we know how to do this comparison. Others require
1257 ;; testing more than one flag bit, and we let the generic middle-end
1259 (define_predicate "ix86_fp_comparison_operator"
1260 (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1261 == IX86_FPCMP_ARITH")
1262 (match_operand 0 "comparison_operator")
1263 (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1265 ;; Same as above, but for swapped comparison used in *jcc<fp>_<int>_i387.
1266 (define_predicate "ix86_swapped_fp_comparison_operator"
1267 (match_operand 0 "comparison_operator")
1269 enum rtx_code code = GET_CODE (op);
1272 PUT_CODE (op, swap_condition (code));
1273 ret = ix86_fp_comparison_operator (op, mode);
1274 PUT_CODE (op, code);
1278 ;; Nearly general operand, but accept any const_double, since we wish
1279 ;; to be able to drop them into memory rather than have them get pulled
1281 (define_predicate "cmp_fp_expander_operand"
1282 (ior (match_code "const_double")
1283 (match_operand 0 "general_operand")))
1285 ;; Return true if this is a valid binary floating-point operation.
1286 (define_predicate "binary_fp_operator"
1287 (match_code "plus,minus,mult,div"))
1289 ;; Return true if this is a multiply operation.
1290 (define_predicate "mult_operator"
1291 (match_code "mult"))
1293 ;; Return true if this is a division operation.
1294 (define_predicate "div_operator"
1297 ;; Return true if this is a plus, minus, and, ior or xor operation.
1298 (define_predicate "plusminuslogic_operator"
1299 (match_code "plus,minus,and,ior,xor"))
1301 ;; Return true if this is a float extend operation.
1302 (define_predicate "float_operator"
1303 (match_code "float"))
1305 ;; Return true for ARITHMETIC_P.
1306 (define_predicate "arith_or_logical_operator"
1307 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1308 mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1310 ;; Return true for COMMUTATIVE_P.
1311 (define_predicate "commutative_operator"
1312 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1314 ;; Return true if OP is a binary operator that can be promoted to wider mode.
1315 (define_predicate "promotable_binary_operator"
1316 (ior (match_code "plus,minus,and,ior,xor,ashift")
1317 (and (match_code "mult")
1318 (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1320 (define_predicate "compare_operator"
1321 (match_code "compare"))
1323 (define_predicate "absneg_operator"
1324 (match_code "abs,neg"))
1326 ;; Return true if OP is misaligned memory operand
1327 (define_predicate "misaligned_operand"
1328 (and (match_code "mem")
1329 (match_test "MEM_ALIGN (op) < GET_MODE_ALIGNMENT (mode)")))
1331 ;; Return true if OP is a emms operation, known to be a PARALLEL.
1332 (define_predicate "emms_operation"
1333 (match_code "parallel")
1337 if (XVECLEN (op, 0) != 17)
1340 for (i = 0; i < 8; i++)
1342 rtx elt = XVECEXP (op, 0, i+1);
1344 if (GET_CODE (elt) != CLOBBER
1345 || GET_CODE (SET_DEST (elt)) != REG
1346 || GET_MODE (SET_DEST (elt)) != XFmode
1347 || REGNO (SET_DEST (elt)) != FIRST_STACK_REG + i)
1350 elt = XVECEXP (op, 0, i+9);
1352 if (GET_CODE (elt) != CLOBBER
1353 || GET_CODE (SET_DEST (elt)) != REG
1354 || GET_MODE (SET_DEST (elt)) != DImode
1355 || REGNO (SET_DEST (elt)) != FIRST_MMX_REG + i)
1361 ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1362 (define_predicate "vzeroall_operation"
1363 (match_code "parallel")
1365 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1367 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1370 for (i = 0; i < nregs; i++)
1372 rtx elt = XVECEXP (op, 0, i+1);
1374 if (GET_CODE (elt) != SET
1375 || GET_CODE (SET_DEST (elt)) != REG
1376 || GET_MODE (SET_DEST (elt)) != V8SImode
1377 || REGNO (SET_DEST (elt)) != SSE_REGNO (i)
1378 || SET_SRC (elt) != CONST0_RTX (V8SImode))
1384 ;; return true if OP is a vzeroupper operation.
1385 (define_predicate "vzeroupper_operation"
1386 (and (match_code "unspec_volatile")
1387 (match_test "XINT (op, 1) == UNSPECV_VZEROUPPER")))
1389 ;; Return true if OP is a parallel for a vbroadcast permute.
1391 (define_predicate "avx_vbroadcast_operand"
1392 (and (match_code "parallel")
1393 (match_code "const_int" "a"))
1395 rtx elt = XVECEXP (op, 0, 0);
1396 int i, nelt = XVECLEN (op, 0);
1398 /* Don't bother checking there are the right number of operands,
1399 merely that they're all identical. */
1400 for (i = 1; i < nelt; ++i)
1401 if (XVECEXP (op, 0, i) != elt)
1406 ;; Return true if OP is a proper third operand to vpblendw256.
1407 (define_predicate "avx2_pblendw_operand"
1408 (match_code "const_int")
1410 HOST_WIDE_INT val = INTVAL (op);
1411 HOST_WIDE_INT low = val & 0xff;
1412 return val == ((low << 8) | low);
1415 ;; Return true if OP is nonimmediate_operand or CONST_VECTOR.
1416 (define_predicate "general_vector_operand"
1417 (ior (match_operand 0 "nonimmediate_operand")
1418 (match_code "const_vector")))
1420 ;; Return true if OP is either -1 constant or stored in register.
1421 (define_predicate "register_or_constm1_operand"
1422 (ior (match_operand 0 "register_operand")
1423 (and (match_code "const_int")
1424 (match_test "op == constm1_rtx"))))