1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
64 #include "coretypes.h"
66 #include "hard-reg-set.h"
70 #include "basic-block.h"
73 #include "insn-config.h"
74 #include "insn-attr.h"
79 #include "integrate.h"
81 /* Next quantity number available for allocation. */
85 /* Information we maintain about each quantity. */
88 /* The number of refs to quantity Q. */
92 /* The frequency of uses of quantity Q. */
96 /* Insn number (counting from head of basic block)
97 where quantity Q was born. -1 if birth has not been recorded. */
101 /* Insn number (counting from head of basic block)
102 where given quantity died. Due to the way tying is done,
103 and the fact that we consider in this pass only regs that die but once,
104 a quantity can die only once. Each quantity's life span
105 is a set of consecutive insns. -1 if death has not been recorded. */
109 /* Number of words needed to hold the data in given quantity.
110 This depends on its machine mode. It is used for these purposes:
111 1. It is used in computing the relative importance of qtys,
112 which determines the order in which we look for regs for them.
113 2. It is used in rules that prevent tying several registers of
114 different sizes in a way that is geometrically impossible
115 (see combine_regs). */
119 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
123 /* The register number of one pseudo register whose reg_qty value is Q.
124 This register should be the head of the chain
125 maintained in reg_next_in_qty. */
129 /* Reg class contained in (smaller than) the preferred classes of all
130 the pseudo regs that are tied in given quantity.
131 This is the preferred class for allocating that quantity. */
133 enum reg_class min_class
;
135 /* Register class within which we allocate given qty if we can't get
136 its preferred class. */
138 enum reg_class alternate_class
;
140 /* This holds the mode of the registers that are tied to given qty,
141 or VOIDmode if registers with differing modes are tied together. */
143 enum machine_mode mode
;
145 /* the hard reg number chosen for given quantity,
146 or -1 if none was found. */
151 static struct qty
*qty
;
153 /* These fields are kept separately to speedup their clearing. */
155 /* We maintain two hard register sets that indicate suggested hard registers
156 for each quantity. The first, phys_copy_sugg, contains hard registers
157 that are tied to the quantity by a simple copy. The second contains all
158 hard registers that are tied to the quantity via an arithmetic operation.
160 The former register set is given priority for allocation. This tends to
161 eliminate copy insns. */
163 /* Element Q is a set of hard registers that are suggested for quantity Q by
166 static HARD_REG_SET
*qty_phys_copy_sugg
;
168 /* Element Q is a set of hard registers that are suggested for quantity Q by
171 static HARD_REG_SET
*qty_phys_sugg
;
173 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
175 static short *qty_phys_num_copy_sugg
;
177 /* Element Q is the number of suggested registers in qty_phys_sugg. */
179 static short *qty_phys_num_sugg
;
181 /* If (REG N) has been assigned a quantity number, is a register number
182 of another register assigned the same quantity number, or -1 for the
183 end of the chain. qty->first_reg point to the head of this chain. */
185 static int *reg_next_in_qty
;
187 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
189 of -1 if this register cannot be allocated by local-alloc,
190 or -2 if not known yet.
192 Note that if we see a use or death of pseudo register N with
193 reg_qty[N] == -2, register N must be local to the current block. If
194 it were used in more than one block, we would have reg_qty[N] == -1.
195 This relies on the fact that if reg_basic_block[N] is >= 0, register N
196 will not appear in any other block. We save a considerable number of
197 tests by exploiting this.
199 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
204 /* The offset (in words) of register N within its quantity.
205 This can be nonzero if register N is SImode, and has been tied
206 to a subreg of a DImode register. */
208 static char *reg_offset
;
210 /* Vector of substitutions of register numbers,
211 used to map pseudo regs into hardware regs.
212 This is set up as a result of register allocation.
213 Element N is the hard reg assigned to pseudo reg N,
214 or is -1 if no hard reg was assigned.
215 If N is a hard reg number, element N is N. */
219 /* Set of hard registers live at the current point in the scan
220 of the instructions in a basic block. */
222 static HARD_REG_SET regs_live
;
224 /* Each set of hard registers indicates registers live at a particular
225 point in the basic block. For N even, regs_live_at[N] says which
226 hard registers are needed *after* insn N/2 (i.e., they may not
227 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
229 If an object is to conflict with the inputs of insn J but not the
230 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
231 if it is to conflict with the outputs of insn J but not the inputs of
232 insn J + 1, it is said to die at index J*2 + 1. */
234 static HARD_REG_SET
*regs_live_at
;
236 /* Communicate local vars `insn_number' and `insn'
237 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
238 static int this_insn_number
;
239 static rtx this_insn
;
243 /* Set when an attempt should be made to replace a register
244 with the associated src_p entry. */
248 /* Set when a REG_EQUIV note is found or created. Use to
249 keep track of what memory accesses might be created later,
256 /* Loop depth is used to recognize equivalences which appear
257 to be present within the same loop (or in an inner loop). */
261 /* The list of each instruction which initializes this register. */
266 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
267 structure for that register. */
269 static struct equivalence
*reg_equiv
;
271 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
272 static int recorded_label_ref
;
274 static void alloc_qty (int, enum machine_mode
, int, int);
275 static void validate_equiv_mem_from_store (rtx
, rtx
, void *);
276 static int validate_equiv_mem (rtx
, rtx
, rtx
);
277 static int equiv_init_varies_p (rtx
);
278 static int equiv_init_movable_p (rtx
, int);
279 static int contains_replace_regs (rtx
);
280 static int memref_referenced_p (rtx
, rtx
);
281 static int memref_used_between_p (rtx
, rtx
, rtx
);
282 static void update_equiv_regs (void);
283 static void no_equiv (rtx
, rtx
, void *);
284 static void block_alloc (int);
285 static int qty_sugg_compare (int, int);
286 static int qty_sugg_compare_1 (const void *, const void *);
287 static int qty_compare (int, int);
288 static int qty_compare_1 (const void *, const void *);
289 static int combine_regs (rtx
, rtx
, int, int, rtx
, int);
290 static int reg_meets_class_p (int, enum reg_class
);
291 static void update_qty_class (int, int);
292 static void reg_is_set (rtx
, rtx
, void *);
293 static void reg_is_born (rtx
, int);
294 static void wipe_dead_reg (rtx
, int);
295 static int find_free_reg (enum reg_class
, enum machine_mode
, int, int, int,
297 static void mark_life (int, enum machine_mode
, int);
298 static void post_mark_life (int, enum machine_mode
, int, int, int);
299 static int no_conflict_p (rtx
, rtx
, rtx
);
300 static int requires_inout (const char *);
302 /* Allocate a new quantity (new within current basic block)
303 for register number REGNO which is born at index BIRTH
304 within the block. MODE and SIZE are info on reg REGNO. */
307 alloc_qty (int regno
, enum machine_mode mode
, int size
, int birth
)
309 int qtyno
= next_qty
++;
311 reg_qty
[regno
] = qtyno
;
312 reg_offset
[regno
] = 0;
313 reg_next_in_qty
[regno
] = -1;
315 qty
[qtyno
].first_reg
= regno
;
316 qty
[qtyno
].size
= size
;
317 qty
[qtyno
].mode
= mode
;
318 qty
[qtyno
].birth
= birth
;
319 qty
[qtyno
].n_calls_crossed
= REG_N_CALLS_CROSSED (regno
);
320 qty
[qtyno
].min_class
= reg_preferred_class (regno
);
321 qty
[qtyno
].alternate_class
= reg_alternate_class (regno
);
322 qty
[qtyno
].n_refs
= REG_N_REFS (regno
);
323 qty
[qtyno
].freq
= REG_FREQ (regno
);
326 /* Main entry point of this file. */
335 /* We need to keep track of whether or not we recorded a LABEL_REF so
336 that we know if the jump optimizer needs to be rerun. */
337 recorded_label_ref
= 0;
339 /* Leaf functions and non-leaf functions have different needs.
340 If defined, let the machine say what kind of ordering we
342 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
343 ORDER_REGS_FOR_LOCAL_ALLOC
;
346 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
349 update_equiv_regs ();
351 /* This sets the maximum number of quantities we can have. Quantity
352 numbers start at zero and we can have one for each pseudo. */
353 max_qty
= (max_regno
- FIRST_PSEUDO_REGISTER
);
355 /* Allocate vectors of temporary data.
356 See the declarations of these variables, above,
357 for what they mean. */
359 qty
= xmalloc (max_qty
* sizeof (struct qty
));
360 qty_phys_copy_sugg
= xmalloc (max_qty
* sizeof (HARD_REG_SET
));
361 qty_phys_num_copy_sugg
= xmalloc (max_qty
* sizeof (short));
362 qty_phys_sugg
= xmalloc (max_qty
* sizeof (HARD_REG_SET
));
363 qty_phys_num_sugg
= xmalloc (max_qty
* sizeof (short));
365 reg_qty
= xmalloc (max_regno
* sizeof (int));
366 reg_offset
= xmalloc (max_regno
* sizeof (char));
367 reg_next_in_qty
= xmalloc (max_regno
* sizeof (int));
369 /* Determine which pseudo-registers can be allocated by local-alloc.
370 In general, these are the registers used only in a single block and
373 We need not be concerned with which block actually uses the register
374 since we will never see it outside that block. */
376 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
378 if (REG_BASIC_BLOCK (i
) >= 0 && REG_N_DEATHS (i
) == 1)
384 /* Force loop below to initialize entire quantity array. */
387 /* Allocate each block's local registers, block by block. */
391 /* NEXT_QTY indicates which elements of the `qty_...'
392 vectors might need to be initialized because they were used
393 for the previous block; it is set to the entire array before
394 block 0. Initialize those, with explicit loop if there are few,
395 else with bzero and bcopy. Do not initialize vectors that are
396 explicit set by `alloc_qty'. */
400 for (i
= 0; i
< next_qty
; i
++)
402 CLEAR_HARD_REG_SET (qty_phys_copy_sugg
[i
]);
403 qty_phys_num_copy_sugg
[i
] = 0;
404 CLEAR_HARD_REG_SET (qty_phys_sugg
[i
]);
405 qty_phys_num_sugg
[i
] = 0;
410 #define CLEAR(vector) \
411 memset ((vector), 0, (sizeof (*(vector))) * next_qty);
413 CLEAR (qty_phys_copy_sugg
);
414 CLEAR (qty_phys_num_copy_sugg
);
415 CLEAR (qty_phys_sugg
);
416 CLEAR (qty_phys_num_sugg
);
421 block_alloc (b
->index
);
425 free (qty_phys_copy_sugg
);
426 free (qty_phys_num_copy_sugg
);
427 free (qty_phys_sugg
);
428 free (qty_phys_num_sugg
);
432 free (reg_next_in_qty
);
434 return recorded_label_ref
;
437 /* Used for communication between the following two functions: contains
438 a MEM that we wish to ensure remains unchanged. */
439 static rtx equiv_mem
;
441 /* Set nonzero if EQUIV_MEM is modified. */
442 static int equiv_mem_modified
;
444 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
445 Called via note_stores. */
448 validate_equiv_mem_from_store (rtx dest
, rtx set ATTRIBUTE_UNUSED
,
449 void *data ATTRIBUTE_UNUSED
)
452 && reg_overlap_mentioned_p (dest
, equiv_mem
))
454 && true_dependence (dest
, VOIDmode
, equiv_mem
, rtx_varies_p
)))
455 equiv_mem_modified
= 1;
458 /* Verify that no store between START and the death of REG invalidates
459 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
460 by storing into an overlapping memory location, or with a non-const
463 Return 1 if MEMREF remains valid. */
466 validate_equiv_mem (rtx start
, rtx reg
, rtx memref
)
472 equiv_mem_modified
= 0;
474 /* If the memory reference has side effects or is volatile, it isn't a
475 valid equivalence. */
476 if (side_effects_p (memref
))
479 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
484 if (find_reg_note (insn
, REG_DEAD
, reg
))
487 if (CALL_P (insn
) && ! MEM_READONLY_P (memref
)
488 && ! CONST_OR_PURE_CALL_P (insn
))
491 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
493 /* If a register mentioned in MEMREF is modified via an
494 auto-increment, we lose the equivalence. Do the same if one
495 dies; although we could extend the life, it doesn't seem worth
498 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
499 if ((REG_NOTE_KIND (note
) == REG_INC
500 || REG_NOTE_KIND (note
) == REG_DEAD
)
501 && REG_P (XEXP (note
, 0))
502 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
509 /* Returns zero if X is known to be invariant. */
512 equiv_init_varies_p (rtx x
)
514 RTX_CODE code
= GET_CODE (x
);
521 return !MEM_READONLY_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
532 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
, 0);
535 if (MEM_VOLATILE_P (x
))
544 fmt
= GET_RTX_FORMAT (code
);
545 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
548 if (equiv_init_varies_p (XEXP (x
, i
)))
551 else if (fmt
[i
] == 'E')
554 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
555 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
562 /* Returns nonzero if X (used to initialize register REGNO) is movable.
563 X is only movable if the registers it uses have equivalent initializations
564 which appear to be within the same loop (or in an inner loop) and movable
565 or if they are not candidates for local_alloc and don't vary. */
568 equiv_init_movable_p (rtx x
, int regno
)
572 enum rtx_code code
= GET_CODE (x
);
577 return equiv_init_movable_p (SET_SRC (x
), regno
);
592 return (reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
593 && reg_equiv
[REGNO (x
)].replace
)
594 || (REG_BASIC_BLOCK (REGNO (x
)) < 0 && ! rtx_varies_p (x
, 0));
596 case UNSPEC_VOLATILE
:
600 if (MEM_VOLATILE_P (x
))
609 fmt
= GET_RTX_FORMAT (code
);
610 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
614 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
618 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
619 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
627 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
630 contains_replace_regs (rtx x
)
634 enum rtx_code code
= GET_CODE (x
);
650 return reg_equiv
[REGNO (x
)].replace
;
656 fmt
= GET_RTX_FORMAT (code
);
657 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
661 if (contains_replace_regs (XEXP (x
, i
)))
665 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
666 if (contains_replace_regs (XVECEXP (x
, i
, j
)))
674 /* TRUE if X references a memory location that would be affected by a store
678 memref_referenced_p (rtx memref
, rtx x
)
682 enum rtx_code code
= GET_CODE (x
);
699 return (reg_equiv
[REGNO (x
)].replacement
700 && memref_referenced_p (memref
,
701 reg_equiv
[REGNO (x
)].replacement
));
704 if (true_dependence (memref
, VOIDmode
, x
, rtx_varies_p
))
709 /* If we are setting a MEM, it doesn't count (its address does), but any
710 other SET_DEST that has a MEM in it is referencing the MEM. */
711 if (MEM_P (SET_DEST (x
)))
713 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
716 else if (memref_referenced_p (memref
, SET_DEST (x
)))
719 return memref_referenced_p (memref
, SET_SRC (x
));
725 fmt
= GET_RTX_FORMAT (code
);
726 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
730 if (memref_referenced_p (memref
, XEXP (x
, i
)))
734 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
735 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
743 /* TRUE if some insn in the range (START, END] references a memory location
744 that would be affected by a store to MEMREF. */
747 memref_used_between_p (rtx memref
, rtx start
, rtx end
)
751 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
752 insn
= NEXT_INSN (insn
))
753 if (INSN_P (insn
) && memref_referenced_p (memref
, PATTERN (insn
)))
759 /* Find registers that are equivalent to a single value throughout the
760 compilation (either because they can be referenced in memory or are set once
761 from a single constant). Lower their priority for a register.
763 If such a register is only referenced once, try substituting its value
764 into the using insn. If it succeeds, we can eliminate the register
768 update_equiv_regs (void)
773 regset_head cleared_regs
;
774 int clear_regnos
= 0;
776 reg_equiv
= xcalloc (max_regno
, sizeof *reg_equiv
);
777 INIT_REG_SET (&cleared_regs
);
779 init_alias_analysis ();
781 /* Scan the insns and find which registers have equivalences. Do this
782 in a separate scan of the insns because (due to -fcse-follow-jumps)
783 a register can be set below its use. */
786 loop_depth
= bb
->loop_depth
;
788 for (insn
= BB_HEAD (bb
);
789 insn
!= NEXT_INSN (BB_END (bb
));
790 insn
= NEXT_INSN (insn
))
800 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
801 if (REG_NOTE_KIND (note
) == REG_INC
)
802 no_equiv (XEXP (note
, 0), note
, NULL
);
804 set
= single_set (insn
);
806 /* If this insn contains more (or less) than a single SET,
807 only mark all destinations as having no known equivalence. */
810 note_stores (PATTERN (insn
), no_equiv
, NULL
);
813 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
817 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
819 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
821 note_stores (part
, no_equiv
, NULL
);
825 dest
= SET_DEST (set
);
828 /* If this sets a MEM to the contents of a REG that is only used
829 in a single basic block, see if the register is always equivalent
830 to that memory location and if moving the store from INSN to the
831 insn that set REG is safe. If so, put a REG_EQUIV note on the
834 Don't add a REG_EQUIV note if the insn already has one. The existing
835 REG_EQUIV is likely more useful than the one we are adding.
837 If one of the regs in the address has reg_equiv[REGNO].replace set,
838 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
839 optimization may move the set of this register immediately before
840 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
841 the mention in the REG_EQUIV note would be to an uninitialized
843 /* ????? This test isn't good enough; we might see a MEM with a use of
844 a pseudo register before we see its setting insn that will cause
845 reg_equiv[].replace for that pseudo to be set.
846 Equivalences to MEMs should be made in another pass, after the
847 reg_equiv[].replace information has been gathered. */
849 if (MEM_P (dest
) && REG_P (src
)
850 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
851 && REG_BASIC_BLOCK (regno
) >= 0
852 && REG_N_SETS (regno
) == 1
853 && reg_equiv
[regno
].init_insns
!= 0
854 && reg_equiv
[regno
].init_insns
!= const0_rtx
855 && ! find_reg_note (XEXP (reg_equiv
[regno
].init_insns
, 0),
857 && ! contains_replace_regs (XEXP (dest
, 0)))
859 rtx init_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
860 if (validate_equiv_mem (init_insn
, src
, dest
)
861 && ! memref_used_between_p (dest
, init_insn
, insn
))
862 REG_NOTES (init_insn
)
863 = gen_rtx_EXPR_LIST (REG_EQUIV
, dest
, REG_NOTES (init_insn
));
866 /* We only handle the case of a pseudo register being set
867 once, or always to the same value. */
868 /* ??? The mn10200 port breaks if we add equivalences for
869 values that need an ADDRESS_REGS register and set them equivalent
870 to a MEM of a pseudo. The actual problem is in the over-conservative
871 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
872 calculate_needs, but we traditionally work around this problem
873 here by rejecting equivalences when the destination is in a register
874 that's likely spilled. This is fragile, of course, since the
875 preferred class of a pseudo depends on all instructions that set
879 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
880 || reg_equiv
[regno
].init_insns
== const0_rtx
881 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno
))
884 /* This might be setting a SUBREG of a pseudo, a pseudo that is
885 also set somewhere else to a constant. */
886 note_stores (set
, no_equiv
, NULL
);
890 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
892 /* cse sometimes generates function invariants, but doesn't put a
893 REG_EQUAL note on the insn. Since this note would be redundant,
894 there's no point creating it earlier than here. */
895 if (! note
&& ! rtx_varies_p (src
, 0))
896 note
= set_unique_reg_note (insn
, REG_EQUAL
, src
);
898 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
899 since it represents a function call */
900 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
903 if (REG_N_SETS (regno
) != 1
905 || rtx_varies_p (XEXP (note
, 0), 0)
906 || (reg_equiv
[regno
].replacement
907 && ! rtx_equal_p (XEXP (note
, 0),
908 reg_equiv
[regno
].replacement
))))
910 no_equiv (dest
, set
, NULL
);
913 /* Record this insn as initializing this register. */
914 reg_equiv
[regno
].init_insns
915 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
917 /* If this register is known to be equal to a constant, record that
918 it is always equivalent to the constant. */
919 if (note
&& ! rtx_varies_p (XEXP (note
, 0), 0))
920 PUT_MODE (note
, (enum machine_mode
) REG_EQUIV
);
922 /* If this insn introduces a "constant" register, decrease the priority
923 of that register. Record this insn if the register is only used once
924 more and the equivalence value is the same as our source.
926 The latter condition is checked for two reasons: First, it is an
927 indication that it may be more efficient to actually emit the insn
928 as written (if no registers are available, reload will substitute
929 the equivalence). Secondly, it avoids problems with any registers
930 dying in this insn whose death notes would be missed.
932 If we don't have a REG_EQUIV note, see if this insn is loading
933 a register used only in one basic block from a MEM. If so, and the
934 MEM remains unchanged for the life of the register, add a REG_EQUIV
937 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
939 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= 0
940 && MEM_P (SET_SRC (set
))
941 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
942 REG_NOTES (insn
) = note
= gen_rtx_EXPR_LIST (REG_EQUIV
, SET_SRC (set
),
947 int regno
= REGNO (dest
);
949 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
950 We might end up substituting the LABEL_REF for uses of the
951 pseudo here or later. That kind of transformation may turn an
952 indirect jump into a direct jump, in which case we must rerun the
953 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
954 if (GET_CODE (XEXP (note
, 0)) == LABEL_REF
955 || (GET_CODE (XEXP (note
, 0)) == CONST
956 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
957 && (GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0))
959 recorded_label_ref
= 1;
961 reg_equiv
[regno
].replacement
= XEXP (note
, 0);
962 reg_equiv
[regno
].src_p
= &SET_SRC (set
);
963 reg_equiv
[regno
].loop_depth
= loop_depth
;
965 /* Don't mess with things live during setjmp. */
966 if (REG_LIVE_LENGTH (regno
) >= 0 && optimize
)
968 /* Note that the statement below does not affect the priority
970 REG_LIVE_LENGTH (regno
) *= 2;
973 /* If the register is referenced exactly twice, meaning it is
974 set once and used once, indicate that the reference may be
975 replaced by the equivalence we computed above. Do this
976 even if the register is only used in one block so that
977 dependencies can be handled where the last register is
978 used in a different block (i.e. HIGH / LO_SUM sequences)
979 and to reduce the number of registers alive across
982 if (REG_N_REFS (regno
) == 2
983 && (rtx_equal_p (XEXP (note
, 0), src
)
984 || ! equiv_init_varies_p (src
))
985 && NONJUMP_INSN_P (insn
)
986 && equiv_init_movable_p (PATTERN (insn
), regno
))
987 reg_equiv
[regno
].replace
= 1;
993 /* Now scan all regs killed in an insn to see if any of them are
994 registers only used that once. If so, see if we can replace the
995 reference with the equivalent from. If we can, delete the
996 initializing reference and this register will go away. If we
997 can't replace the reference, and the initializing reference is
998 within the same loop (or in an inner loop), then move the register
999 initialization just before the use, so that they are in the same
1001 FOR_EACH_BB_REVERSE (bb
)
1003 loop_depth
= bb
->loop_depth
;
1004 for (insn
= BB_END (bb
);
1005 insn
!= PREV_INSN (BB_HEAD (bb
));
1006 insn
= PREV_INSN (insn
))
1010 if (! INSN_P (insn
))
1013 /* Don't substitute into a non-local goto, this confuses CFG. */
1015 && find_reg_note (insn
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1018 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1020 if (REG_NOTE_KIND (link
) == REG_DEAD
1021 /* Make sure this insn still refers to the register. */
1022 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
1024 int regno
= REGNO (XEXP (link
, 0));
1027 if (! reg_equiv
[regno
].replace
1028 || reg_equiv
[regno
].loop_depth
< loop_depth
)
1031 /* reg_equiv[REGNO].replace gets set only when
1032 REG_N_REFS[REGNO] is 2, i.e. the register is set
1033 once and used once. (If it were only set, but not used,
1034 flow would have deleted the setting insns.) Hence
1035 there can only be one insn in reg_equiv[REGNO].init_insns. */
1036 if (reg_equiv
[regno
].init_insns
== NULL_RTX
1037 || XEXP (reg_equiv
[regno
].init_insns
, 1) != NULL_RTX
)
1039 equiv_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
1041 /* We may not move instructions that can throw, since
1042 that changes basic block boundaries and we are not
1043 prepared to adjust the CFG to match. */
1044 if (can_throw_internal (equiv_insn
))
1047 if (asm_noperands (PATTERN (equiv_insn
)) < 0
1048 && validate_replace_rtx (regno_reg_rtx
[regno
],
1049 *(reg_equiv
[regno
].src_p
), insn
))
1055 /* Find the last note. */
1056 for (last_link
= link
; XEXP (last_link
, 1);
1057 last_link
= XEXP (last_link
, 1))
1060 /* Append the REG_DEAD notes from equiv_insn. */
1061 equiv_link
= REG_NOTES (equiv_insn
);
1065 equiv_link
= XEXP (equiv_link
, 1);
1066 if (REG_NOTE_KIND (note
) == REG_DEAD
)
1068 remove_note (equiv_insn
, note
);
1069 XEXP (last_link
, 1) = note
;
1070 XEXP (note
, 1) = NULL_RTX
;
1075 remove_death (regno
, insn
);
1076 REG_N_REFS (regno
) = 0;
1077 REG_FREQ (regno
) = 0;
1078 delete_insn (equiv_insn
);
1080 reg_equiv
[regno
].init_insns
1081 = XEXP (reg_equiv
[regno
].init_insns
, 1);
1083 /* Move the initialization of the register to just before
1084 INSN. Update the flow information. */
1085 else if (PREV_INSN (insn
) != equiv_insn
)
1089 new_insn
= emit_insn_before (PATTERN (equiv_insn
), insn
);
1090 REG_NOTES (new_insn
) = REG_NOTES (equiv_insn
);
1091 REG_NOTES (equiv_insn
) = 0;
1093 /* Make sure this insn is recognized before reload begins,
1094 otherwise eliminate_regs_in_insn will abort. */
1095 INSN_CODE (new_insn
) = INSN_CODE (equiv_insn
);
1097 delete_insn (equiv_insn
);
1099 XEXP (reg_equiv
[regno
].init_insns
, 0) = new_insn
;
1101 REG_BASIC_BLOCK (regno
) = bb
->index
;
1102 REG_N_CALLS_CROSSED (regno
) = 0;
1103 REG_LIVE_LENGTH (regno
) = 2;
1105 if (insn
== BB_HEAD (bb
))
1106 BB_HEAD (bb
) = PREV_INSN (insn
);
1108 /* Remember to clear REGNO from all basic block's live
1110 SET_REGNO_REG_SET (&cleared_regs
, regno
);
1118 /* Clear all dead REGNOs from all basic block's live info. */
1123 if (clear_regnos
> 8)
1127 AND_COMPL_REG_SET (bb
->global_live_at_start
, &cleared_regs
);
1128 AND_COMPL_REG_SET (bb
->global_live_at_end
, &cleared_regs
);
1133 reg_set_iterator rsi
;
1134 EXECUTE_IF_SET_IN_REG_SET (&cleared_regs
, 0, j
, rsi
)
1138 CLEAR_REGNO_REG_SET (bb
->global_live_at_start
, j
);
1139 CLEAR_REGNO_REG_SET (bb
->global_live_at_end
, j
);
1146 end_alias_analysis ();
1147 CLEAR_REG_SET (&cleared_regs
);
1151 /* Mark REG as having no known equivalence.
1152 Some instructions might have been processed before and furnished
1153 with REG_EQUIV notes for this register; these notes will have to be
1155 STORE is the piece of RTL that does the non-constant / conflicting
1156 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1157 but needs to be there because this function is called from note_stores. */
1159 no_equiv (rtx reg
, rtx store ATTRIBUTE_UNUSED
, void *data ATTRIBUTE_UNUSED
)
1166 regno
= REGNO (reg
);
1167 list
= reg_equiv
[regno
].init_insns
;
1168 if (list
== const0_rtx
)
1170 for (; list
; list
= XEXP (list
, 1))
1172 rtx insn
= XEXP (list
, 0);
1173 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
1175 reg_equiv
[regno
].init_insns
= const0_rtx
;
1176 reg_equiv
[regno
].replacement
= NULL_RTX
;
1179 /* Allocate hard regs to the pseudo regs used only within block number B.
1180 Only the pseudos that die but once can be handled. */
1188 int insn_number
= 0;
1190 int max_uid
= get_max_uid ();
1192 int no_conflict_combined_regno
= -1;
1194 /* Count the instructions in the basic block. */
1196 insn
= BB_END (BASIC_BLOCK (b
));
1200 if (++insn_count
> max_uid
)
1202 if (insn
== BB_HEAD (BASIC_BLOCK (b
)))
1204 insn
= PREV_INSN (insn
);
1207 /* +2 to leave room for a post_mark_life at the last insn and for
1208 the birth of a CLOBBER in the first insn. */
1209 regs_live_at
= xcalloc ((2 * insn_count
+ 2), sizeof (HARD_REG_SET
));
1211 /* Initialize table of hardware registers currently live. */
1213 REG_SET_TO_HARD_REG_SET (regs_live
, BASIC_BLOCK (b
)->global_live_at_start
);
1215 /* This loop scans the instructions of the basic block
1216 and assigns quantities to registers.
1217 It computes which registers to tie. */
1219 insn
= BB_HEAD (BASIC_BLOCK (b
));
1229 rtx r0
, r1
= NULL_RTX
;
1230 int combined_regno
= -1;
1233 this_insn_number
= insn_number
;
1236 extract_insn (insn
);
1237 which_alternative
= -1;
1239 /* Is this insn suitable for tying two registers?
1240 If so, try doing that.
1241 Suitable insns are those with at least two operands and where
1242 operand 0 is an output that is a register that is not
1245 We can tie operand 0 with some operand that dies in this insn.
1246 First look for operands that are required to be in the same
1247 register as operand 0. If we find such, only try tying that
1248 operand or one that can be put into that operand if the
1249 operation is commutative. If we don't find an operand
1250 that is required to be in the same register as operand 0,
1251 we can tie with any operand.
1253 Subregs in place of regs are also ok.
1255 If tying is done, WIN is set nonzero. */
1258 && recog_data
.n_operands
> 1
1259 && recog_data
.constraints
[0][0] == '='
1260 && recog_data
.constraints
[0][1] != '&')
1262 /* If non-negative, is an operand that must match operand 0. */
1263 int must_match_0
= -1;
1264 /* Counts number of alternatives that require a match with
1266 int n_matching_alts
= 0;
1268 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1270 const char *p
= recog_data
.constraints
[i
];
1271 int this_match
= requires_inout (p
);
1273 n_matching_alts
+= this_match
;
1274 if (this_match
== recog_data
.n_alternatives
)
1278 r0
= recog_data
.operand
[0];
1279 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1281 /* Skip this operand if we found an operand that
1282 must match operand 0 and this operand isn't it
1283 and can't be made to be it by commutativity. */
1285 if (must_match_0
>= 0 && i
!= must_match_0
1286 && ! (i
== must_match_0
+ 1
1287 && recog_data
.constraints
[i
-1][0] == '%')
1288 && ! (i
== must_match_0
- 1
1289 && recog_data
.constraints
[i
][0] == '%'))
1292 /* Likewise if each alternative has some operand that
1293 must match operand zero. In that case, skip any
1294 operand that doesn't list operand 0 since we know that
1295 the operand always conflicts with operand 0. We
1296 ignore commutativity in this case to keep things simple. */
1297 if (n_matching_alts
== recog_data
.n_alternatives
1298 && 0 == requires_inout (recog_data
.constraints
[i
]))
1301 r1
= recog_data
.operand
[i
];
1303 /* If the operand is an address, find a register in it.
1304 There may be more than one register, but we only try one
1306 if (recog_data
.constraints
[i
][0] == 'p'
1307 || EXTRA_ADDRESS_CONSTRAINT (recog_data
.constraints
[i
][0],
1308 recog_data
.constraints
[i
]))
1309 while (GET_CODE (r1
) == PLUS
|| GET_CODE (r1
) == MULT
)
1312 /* Avoid making a call-saved register unnecessarily
1314 hard_reg
= get_hard_reg_initial_reg (cfun
, r1
);
1315 if (hard_reg
!= NULL_RTX
)
1317 if (REG_P (hard_reg
)
1318 && IN_RANGE (REGNO (hard_reg
),
1319 0, FIRST_PSEUDO_REGISTER
- 1)
1320 && ! call_used_regs
[REGNO (hard_reg
)])
1324 if (REG_P (r0
) || GET_CODE (r0
) == SUBREG
)
1326 /* We have two priorities for hard register preferences.
1327 If we have a move insn or an insn whose first input
1328 can only be in the same register as the output, give
1329 priority to an equivalence found from that insn. */
1331 = (r1
== recog_data
.operand
[i
] && must_match_0
>= 0);
1333 if (REG_P (r1
) || GET_CODE (r1
) == SUBREG
)
1334 win
= combine_regs (r1
, r0
, may_save_copy
,
1335 insn_number
, insn
, 0);
1342 /* Recognize an insn sequence with an ultimate result
1343 which can safely overlap one of the inputs.
1344 The sequence begins with a CLOBBER of its result,
1345 and ends with an insn that copies the result to itself
1346 and has a REG_EQUAL note for an equivalent formula.
1347 That note indicates what the inputs are.
1348 The result and the input can overlap if each insn in
1349 the sequence either doesn't mention the input
1350 or has a REG_NO_CONFLICT note to inhibit the conflict.
1352 We do the combining test at the CLOBBER so that the
1353 destination register won't have had a quantity number
1354 assigned, since that would prevent combining. */
1357 && GET_CODE (PATTERN (insn
)) == CLOBBER
1358 && (r0
= XEXP (PATTERN (insn
), 0),
1360 && (link
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
)) != 0
1361 && XEXP (link
, 0) != 0
1362 && NONJUMP_INSN_P (XEXP (link
, 0))
1363 && (set
= single_set (XEXP (link
, 0))) != 0
1364 && SET_DEST (set
) == r0
&& SET_SRC (set
) == r0
1365 && (note
= find_reg_note (XEXP (link
, 0), REG_EQUAL
,
1368 if (r1
= XEXP (note
, 0), REG_P (r1
)
1369 /* Check that we have such a sequence. */
1370 && no_conflict_p (insn
, r0
, r1
))
1371 win
= combine_regs (r1
, r0
, 1, insn_number
, insn
, 1);
1372 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note
, 0)))[0] == 'e'
1373 && (r1
= XEXP (XEXP (note
, 0), 0),
1374 REG_P (r1
) || GET_CODE (r1
) == SUBREG
)
1375 && no_conflict_p (insn
, r0
, r1
))
1376 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1378 /* Here we care if the operation to be computed is
1380 else if (COMMUTATIVE_P (XEXP (note
, 0))
1381 && (r1
= XEXP (XEXP (note
, 0), 1),
1382 (REG_P (r1
) || GET_CODE (r1
) == SUBREG
))
1383 && no_conflict_p (insn
, r0
, r1
))
1384 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1386 /* If we did combine something, show the register number
1387 in question so that we know to ignore its death. */
1389 no_conflict_combined_regno
= REGNO (r1
);
1392 /* If registers were just tied, set COMBINED_REGNO
1393 to the number of the register used in this insn
1394 that was tied to the register set in this insn.
1395 This register's qty should not be "killed". */
1399 while (GET_CODE (r1
) == SUBREG
)
1400 r1
= SUBREG_REG (r1
);
1401 combined_regno
= REGNO (r1
);
1404 /* Mark the death of everything that dies in this instruction,
1405 except for anything that was just combined. */
1407 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1408 if (REG_NOTE_KIND (link
) == REG_DEAD
1409 && REG_P (XEXP (link
, 0))
1410 && combined_regno
!= (int) REGNO (XEXP (link
, 0))
1411 && (no_conflict_combined_regno
!= (int) REGNO (XEXP (link
, 0))
1412 || ! find_reg_note (insn
, REG_NO_CONFLICT
,
1414 wipe_dead_reg (XEXP (link
, 0), 0);
1416 /* Allocate qty numbers for all registers local to this block
1417 that are born (set) in this instruction.
1418 A pseudo that already has a qty is not changed. */
1420 note_stores (PATTERN (insn
), reg_is_set
, NULL
);
1422 /* If anything is set in this insn and then unused, mark it as dying
1423 after this insn, so it will conflict with our outputs. This
1424 can't match with something that combined, and it doesn't matter
1425 if it did. Do this after the calls to reg_is_set since these
1426 die after, not during, the current insn. */
1428 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1429 if (REG_NOTE_KIND (link
) == REG_UNUSED
1430 && REG_P (XEXP (link
, 0)))
1431 wipe_dead_reg (XEXP (link
, 0), 1);
1433 /* If this is an insn that has a REG_RETVAL note pointing at a
1434 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1435 block, so clear any register number that combined within it. */
1436 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)) != 0
1437 && NONJUMP_INSN_P (XEXP (note
, 0))
1438 && GET_CODE (PATTERN (XEXP (note
, 0))) == CLOBBER
)
1439 no_conflict_combined_regno
= -1;
1442 /* Set the registers live after INSN_NUMBER. Note that we never
1443 record the registers live before the block's first insn, since no
1444 pseudos we care about are live before that insn. */
1446 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
], regs_live
);
1447 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
+ 1], regs_live
);
1449 if (insn
== BB_END (BASIC_BLOCK (b
)))
1452 insn
= NEXT_INSN (insn
);
1455 /* Now every register that is local to this basic block
1456 should have been given a quantity, or else -1 meaning ignore it.
1457 Every quantity should have a known birth and death.
1459 Order the qtys so we assign them registers in order of the
1460 number of suggested registers they need so we allocate those with
1461 the most restrictive needs first. */
1463 qty_order
= xmalloc (next_qty
* sizeof (int));
1464 for (i
= 0; i
< next_qty
; i
++)
1467 #define EXCHANGE(I1, I2) \
1468 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1473 /* Make qty_order[2] be the one to allocate last. */
1474 if (qty_sugg_compare (0, 1) > 0)
1476 if (qty_sugg_compare (1, 2) > 0)
1479 /* ... Fall through ... */
1481 /* Put the best one to allocate in qty_order[0]. */
1482 if (qty_sugg_compare (0, 1) > 0)
1485 /* ... Fall through ... */
1489 /* Nothing to do here. */
1493 qsort (qty_order
, next_qty
, sizeof (int), qty_sugg_compare_1
);
1496 /* Try to put each quantity in a suggested physical register, if it has one.
1497 This may cause registers to be allocated that otherwise wouldn't be, but
1498 this seems acceptable in local allocation (unlike global allocation). */
1499 for (i
= 0; i
< next_qty
; i
++)
1502 if (qty_phys_num_sugg
[q
] != 0 || qty_phys_num_copy_sugg
[q
] != 0)
1503 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
, qty
[q
].mode
, q
,
1504 0, 1, qty
[q
].birth
, qty
[q
].death
);
1506 qty
[q
].phys_reg
= -1;
1509 /* Order the qtys so we assign them registers in order of
1510 decreasing length of life. Normally call qsort, but if we
1511 have only a very small number of quantities, sort them ourselves. */
1513 for (i
= 0; i
< next_qty
; i
++)
1516 #define EXCHANGE(I1, I2) \
1517 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1522 /* Make qty_order[2] be the one to allocate last. */
1523 if (qty_compare (0, 1) > 0)
1525 if (qty_compare (1, 2) > 0)
1528 /* ... Fall through ... */
1530 /* Put the best one to allocate in qty_order[0]. */
1531 if (qty_compare (0, 1) > 0)
1534 /* ... Fall through ... */
1538 /* Nothing to do here. */
1542 qsort (qty_order
, next_qty
, sizeof (int), qty_compare_1
);
1545 /* Now for each qty that is not a hardware register,
1546 look for a hardware register to put it in.
1547 First try the register class that is cheapest for this qty,
1548 if there is more than one class. */
1550 for (i
= 0; i
< next_qty
; i
++)
1553 if (qty
[q
].phys_reg
< 0)
1555 #ifdef INSN_SCHEDULING
1556 /* These values represent the adjusted lifetime of a qty so
1557 that it conflicts with qtys which appear near the start/end
1558 of this qty's lifetime.
1560 The purpose behind extending the lifetime of this qty is to
1561 discourage the register allocator from creating false
1564 The adjustment value is chosen to indicate that this qty
1565 conflicts with all the qtys in the instructions immediately
1566 before and after the lifetime of this qty.
1568 Experiments have shown that higher values tend to hurt
1569 overall code performance.
1571 If allocation using the extended lifetime fails we will try
1572 again with the qty's unadjusted lifetime. */
1573 int fake_birth
= MAX (0, qty
[q
].birth
- 2 + qty
[q
].birth
% 2);
1574 int fake_death
= MIN (insn_number
* 2 + 1,
1575 qty
[q
].death
+ 2 - qty
[q
].death
% 2);
1578 if (N_REG_CLASSES
> 1)
1580 #ifdef INSN_SCHEDULING
1581 /* We try to avoid using hard registers allocated to qtys which
1582 are born immediately after this qty or die immediately before
1585 This optimization is only appropriate when we will run
1586 a scheduling pass after reload and we are not optimizing
1588 if (flag_schedule_insns_after_reload
1590 && !SMALL_REGISTER_CLASSES
)
1592 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1593 qty
[q
].mode
, q
, 0, 0,
1594 fake_birth
, fake_death
);
1595 if (qty
[q
].phys_reg
>= 0)
1599 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1600 qty
[q
].mode
, q
, 0, 0,
1601 qty
[q
].birth
, qty
[q
].death
);
1602 if (qty
[q
].phys_reg
>= 0)
1606 #ifdef INSN_SCHEDULING
1607 /* Similarly, avoid false dependencies. */
1608 if (flag_schedule_insns_after_reload
1610 && !SMALL_REGISTER_CLASSES
1611 && qty
[q
].alternate_class
!= NO_REGS
)
1612 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1613 qty
[q
].mode
, q
, 0, 0,
1614 fake_birth
, fake_death
);
1616 if (qty
[q
].alternate_class
!= NO_REGS
)
1617 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1618 qty
[q
].mode
, q
, 0, 0,
1619 qty
[q
].birth
, qty
[q
].death
);
1623 /* Now propagate the register assignments
1624 to the pseudo regs belonging to the qtys. */
1626 for (q
= 0; q
< next_qty
; q
++)
1627 if (qty
[q
].phys_reg
>= 0)
1629 for (i
= qty
[q
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1630 reg_renumber
[i
] = qty
[q
].phys_reg
+ reg_offset
[i
];
1634 free (regs_live_at
);
1638 /* Compare two quantities' priority for getting real registers.
1639 We give shorter-lived quantities higher priority.
1640 Quantities with more references are also preferred, as are quantities that
1641 require multiple registers. This is the identical prioritization as
1642 done by global-alloc.
1644 We used to give preference to registers with *longer* lives, but using
1645 the same algorithm in both local- and global-alloc can speed up execution
1646 of some programs by as much as a factor of three! */
1648 /* Note that the quotient will never be bigger than
1649 the value of floor_log2 times the maximum number of
1650 times a register can occur in one insn (surely less than 100)
1651 weighted by frequency (max REG_FREQ_MAX).
1652 Multiplying this by 10000/REG_FREQ_MAX can't overflow.
1653 QTY_CMP_PRI is also used by qty_sugg_compare. */
1655 #define QTY_CMP_PRI(q) \
1656 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \
1657 / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX)))
1660 qty_compare (int q1
, int q2
)
1662 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1666 qty_compare_1 (const void *q1p
, const void *q2p
)
1668 int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1669 int tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1674 /* If qtys are equally good, sort by qty number,
1675 so that the results of qsort leave nothing to chance. */
1679 /* Compare two quantities' priority for getting real registers. This version
1680 is called for quantities that have suggested hard registers. First priority
1681 goes to quantities that have copy preferences, then to those that have
1682 normal preferences. Within those groups, quantities with the lower
1683 number of preferences have the highest priority. Of those, we use the same
1684 algorithm as above. */
1686 #define QTY_CMP_SUGG(q) \
1687 (qty_phys_num_copy_sugg[q] \
1688 ? qty_phys_num_copy_sugg[q] \
1689 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1692 qty_sugg_compare (int q1
, int q2
)
1694 int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1699 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1703 qty_sugg_compare_1 (const void *q1p
, const void *q2p
)
1705 int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1706 int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1711 tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1715 /* If qtys are equally good, sort by qty number,
1716 so that the results of qsort leave nothing to chance. */
1723 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1724 Returns 1 if have done so, or 0 if cannot.
1726 Combining registers means marking them as having the same quantity
1727 and adjusting the offsets within the quantity if either of
1730 We don't actually combine a hard reg with a pseudo; instead
1731 we just record the hard reg as the suggestion for the pseudo's quantity.
1732 If we really combined them, we could lose if the pseudo lives
1733 across an insn that clobbers the hard reg (eg, movmem).
1735 ALREADY_DEAD is nonzero if USEDREG is known to be dead even though
1736 there is no REG_DEAD note on INSN. This occurs during the processing
1737 of REG_NO_CONFLICT blocks.
1739 MAY_SAVE_COPY is nonzero if this insn is simply copying USEDREG to
1740 SETREG or if the input and output must share a register.
1741 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1743 There are elaborate checks for the validity of combining. */
1746 combine_regs (rtx usedreg
, rtx setreg
, int may_save_copy
, int insn_number
,
1747 rtx insn
, int already_dead
)
1754 /* Determine the numbers and sizes of registers being used. If a subreg
1755 is present that does not change the entire register, don't consider
1756 this a copy insn. */
1758 while (GET_CODE (usedreg
) == SUBREG
)
1760 rtx subreg
= SUBREG_REG (usedreg
);
1764 if (GET_MODE_SIZE (GET_MODE (subreg
)) > UNITS_PER_WORD
)
1767 if (REGNO (subreg
) < FIRST_PSEUDO_REGISTER
)
1768 offset
+= subreg_regno_offset (REGNO (subreg
),
1770 SUBREG_BYTE (usedreg
),
1771 GET_MODE (usedreg
));
1773 offset
+= (SUBREG_BYTE (usedreg
)
1774 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)));
1780 if (!REG_P (usedreg
))
1783 ureg
= REGNO (usedreg
);
1784 if (ureg
< FIRST_PSEUDO_REGISTER
)
1785 usize
= hard_regno_nregs
[ureg
][GET_MODE (usedreg
)];
1787 usize
= ((GET_MODE_SIZE (GET_MODE (usedreg
))
1788 + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)) - 1))
1789 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)));
1791 while (GET_CODE (setreg
) == SUBREG
)
1793 rtx subreg
= SUBREG_REG (setreg
);
1797 if (GET_MODE_SIZE (GET_MODE (subreg
)) > UNITS_PER_WORD
)
1800 if (REGNO (subreg
) < FIRST_PSEUDO_REGISTER
)
1801 offset
-= subreg_regno_offset (REGNO (subreg
),
1803 SUBREG_BYTE (setreg
),
1806 offset
-= (SUBREG_BYTE (setreg
)
1807 / REGMODE_NATURAL_SIZE (GET_MODE (setreg
)));
1813 if (!REG_P (setreg
))
1816 sreg
= REGNO (setreg
);
1817 if (sreg
< FIRST_PSEUDO_REGISTER
)
1818 ssize
= hard_regno_nregs
[sreg
][GET_MODE (setreg
)];
1820 ssize
= ((GET_MODE_SIZE (GET_MODE (setreg
))
1821 + (REGMODE_NATURAL_SIZE (GET_MODE (setreg
)) - 1))
1822 / REGMODE_NATURAL_SIZE (GET_MODE (setreg
)));
1824 /* If UREG is a pseudo-register that hasn't already been assigned a
1825 quantity number, it means that it is not local to this block or dies
1826 more than once. In either event, we can't do anything with it. */
1827 if ((ureg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[ureg
] < 0)
1828 /* Do not combine registers unless one fits within the other. */
1829 || (offset
> 0 && usize
+ offset
> ssize
)
1830 || (offset
< 0 && usize
+ offset
< ssize
)
1831 /* Do not combine with a smaller already-assigned object
1832 if that smaller object is already combined with something bigger. */
1833 || (ssize
> usize
&& ureg
>= FIRST_PSEUDO_REGISTER
1834 && usize
< qty
[reg_qty
[ureg
]].size
)
1835 /* Can't combine if SREG is not a register we can allocate. */
1836 || (sreg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[sreg
] == -1)
1837 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1838 These have already been taken care of. This probably wouldn't
1839 combine anyway, but don't take any chances. */
1840 || (ureg
>= FIRST_PSEUDO_REGISTER
1841 && find_reg_note (insn
, REG_NO_CONFLICT
, usedreg
))
1842 /* Don't tie something to itself. In most cases it would make no
1843 difference, but it would screw up if the reg being tied to itself
1844 also dies in this insn. */
1846 /* Don't try to connect two different hardware registers. */
1847 || (ureg
< FIRST_PSEUDO_REGISTER
&& sreg
< FIRST_PSEUDO_REGISTER
)
1848 /* Don't connect two different machine modes if they have different
1849 implications as to which registers may be used. */
1850 || !MODES_TIEABLE_P (GET_MODE (usedreg
), GET_MODE (setreg
)))
1853 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1854 qty_phys_sugg for the pseudo instead of tying them.
1856 Return "failure" so that the lifespan of UREG is terminated here;
1857 that way the two lifespans will be disjoint and nothing will prevent
1858 the pseudo reg from being given this hard reg. */
1860 if (ureg
< FIRST_PSEUDO_REGISTER
)
1862 /* Allocate a quantity number so we have a place to put our
1864 if (reg_qty
[sreg
] == -2)
1865 reg_is_born (setreg
, 2 * insn_number
);
1867 if (reg_qty
[sreg
] >= 0)
1870 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
))
1872 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
);
1873 qty_phys_num_copy_sugg
[reg_qty
[sreg
]]++;
1875 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
))
1877 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
);
1878 qty_phys_num_sugg
[reg_qty
[sreg
]]++;
1884 /* Similarly for SREG a hard register and UREG a pseudo register. */
1886 if (sreg
< FIRST_PSEUDO_REGISTER
)
1889 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
))
1891 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
);
1892 qty_phys_num_copy_sugg
[reg_qty
[ureg
]]++;
1894 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
))
1896 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
);
1897 qty_phys_num_sugg
[reg_qty
[ureg
]]++;
1902 /* At this point we know that SREG and UREG are both pseudos.
1903 Do nothing if SREG already has a quantity or is a register that we
1905 if (reg_qty
[sreg
] >= -1
1906 /* If we are not going to let any regs live across calls,
1907 don't tie a call-crossing reg to a non-call-crossing reg. */
1908 || (current_function_has_nonlocal_label
1909 && ((REG_N_CALLS_CROSSED (ureg
) > 0)
1910 != (REG_N_CALLS_CROSSED (sreg
) > 0))))
1913 /* We don't already know about SREG, so tie it to UREG
1914 if this is the last use of UREG, provided the classes they want
1917 if ((already_dead
|| find_regno_note (insn
, REG_DEAD
, ureg
))
1918 && reg_meets_class_p (sreg
, qty
[reg_qty
[ureg
]].min_class
))
1920 /* Add SREG to UREG's quantity. */
1921 sqty
= reg_qty
[ureg
];
1922 reg_qty
[sreg
] = sqty
;
1923 reg_offset
[sreg
] = reg_offset
[ureg
] + offset
;
1924 reg_next_in_qty
[sreg
] = qty
[sqty
].first_reg
;
1925 qty
[sqty
].first_reg
= sreg
;
1927 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1928 update_qty_class (sqty
, sreg
);
1930 /* Update info about quantity SQTY. */
1931 qty
[sqty
].n_calls_crossed
+= REG_N_CALLS_CROSSED (sreg
);
1932 qty
[sqty
].n_refs
+= REG_N_REFS (sreg
);
1933 qty
[sqty
].freq
+= REG_FREQ (sreg
);
1938 for (i
= qty
[sqty
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1939 reg_offset
[i
] -= offset
;
1941 qty
[sqty
].size
= ssize
;
1942 qty
[sqty
].mode
= GET_MODE (setreg
);
1951 /* Return 1 if the preferred class of REG allows it to be tied
1952 to a quantity or register whose class is CLASS.
1953 True if REG's reg class either contains or is contained in CLASS. */
1956 reg_meets_class_p (int reg
, enum reg_class
class)
1958 enum reg_class rclass
= reg_preferred_class (reg
);
1959 return (reg_class_subset_p (rclass
, class)
1960 || reg_class_subset_p (class, rclass
));
1963 /* Update the class of QTYNO assuming that REG is being tied to it. */
1966 update_qty_class (int qtyno
, int reg
)
1968 enum reg_class rclass
= reg_preferred_class (reg
);
1969 if (reg_class_subset_p (rclass
, qty
[qtyno
].min_class
))
1970 qty
[qtyno
].min_class
= rclass
;
1972 rclass
= reg_alternate_class (reg
);
1973 if (reg_class_subset_p (rclass
, qty
[qtyno
].alternate_class
))
1974 qty
[qtyno
].alternate_class
= rclass
;
1977 /* Handle something which alters the value of an rtx REG.
1979 REG is whatever is set or clobbered. SETTER is the rtx that
1980 is modifying the register.
1982 If it is not really a register, we do nothing.
1983 The file-global variables `this_insn' and `this_insn_number'
1984 carry info from `block_alloc'. */
1987 reg_is_set (rtx reg
, rtx setter
, void *data ATTRIBUTE_UNUSED
)
1989 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1990 a hard register. These may actually not exist any more. */
1992 if (GET_CODE (reg
) != SUBREG
1996 /* Mark this register as being born. If it is used in a CLOBBER, mark
1997 it as being born halfway between the previous insn and this insn so that
1998 it conflicts with our inputs but not the outputs of the previous insn. */
2000 reg_is_born (reg
, 2 * this_insn_number
- (GET_CODE (setter
) == CLOBBER
));
2003 /* Handle beginning of the life of register REG.
2004 BIRTH is the index at which this is happening. */
2007 reg_is_born (rtx reg
, int birth
)
2011 if (GET_CODE (reg
) == SUBREG
)
2013 regno
= REGNO (SUBREG_REG (reg
));
2014 if (regno
< FIRST_PSEUDO_REGISTER
)
2015 regno
= subreg_hard_regno (reg
, 1);
2018 regno
= REGNO (reg
);
2020 if (regno
< FIRST_PSEUDO_REGISTER
)
2022 mark_life (regno
, GET_MODE (reg
), 1);
2024 /* If the register was to have been born earlier that the present
2025 insn, mark it as live where it is actually born. */
2026 if (birth
< 2 * this_insn_number
)
2027 post_mark_life (regno
, GET_MODE (reg
), 1, birth
, 2 * this_insn_number
);
2031 if (reg_qty
[regno
] == -2)
2032 alloc_qty (regno
, GET_MODE (reg
), PSEUDO_REGNO_SIZE (regno
), birth
);
2034 /* If this register has a quantity number, show that it isn't dead. */
2035 if (reg_qty
[regno
] >= 0)
2036 qty
[reg_qty
[regno
]].death
= -1;
2040 /* Record the death of REG in the current insn. If OUTPUT_P is nonzero,
2041 REG is an output that is dying (i.e., it is never used), otherwise it
2042 is an input (the normal case).
2043 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2046 wipe_dead_reg (rtx reg
, int output_p
)
2048 int regno
= REGNO (reg
);
2050 /* If this insn has multiple results,
2051 and the dead reg is used in one of the results,
2052 extend its life to after this insn,
2053 so it won't get allocated together with any other result of this insn.
2055 It is unsafe to use !single_set here since it will ignore an unused
2056 output. Just because an output is unused does not mean the compiler
2057 can assume the side effect will not occur. Consider if REG appears
2058 in the address of an output and we reload the output. If we allocate
2059 REG to the same hard register as an unused output we could set the hard
2060 register before the output reload insn. */
2061 if (GET_CODE (PATTERN (this_insn
)) == PARALLEL
2062 && multiple_sets (this_insn
))
2065 for (i
= XVECLEN (PATTERN (this_insn
), 0) - 1; i
>= 0; i
--)
2067 rtx set
= XVECEXP (PATTERN (this_insn
), 0, i
);
2068 if (GET_CODE (set
) == SET
2069 && !REG_P (SET_DEST (set
))
2070 && !rtx_equal_p (reg
, SET_DEST (set
))
2071 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2076 /* If this register is used in an auto-increment address, then extend its
2077 life to after this insn, so that it won't get allocated together with
2078 the result of this insn. */
2079 if (! output_p
&& find_regno_note (this_insn
, REG_INC
, regno
))
2082 if (regno
< FIRST_PSEUDO_REGISTER
)
2084 mark_life (regno
, GET_MODE (reg
), 0);
2086 /* If a hard register is dying as an output, mark it as in use at
2087 the beginning of this insn (the above statement would cause this
2090 post_mark_life (regno
, GET_MODE (reg
), 1,
2091 2 * this_insn_number
, 2 * this_insn_number
+ 1);
2094 else if (reg_qty
[regno
] >= 0)
2095 qty
[reg_qty
[regno
]].death
= 2 * this_insn_number
+ output_p
;
2098 /* Find a block of SIZE words of hard regs in reg_class CLASS
2099 that can hold something of machine-mode MODE
2100 (but actually we test only the first of the block for holding MODE)
2101 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2102 and return the number of the first of them.
2103 Return -1 if such a block cannot be found.
2104 If QTYNO crosses calls, insist on a register preserved by calls,
2105 unless ACCEPT_CALL_CLOBBERED is nonzero.
2107 If JUST_TRY_SUGGESTED is nonzero, only try to see if the suggested
2108 register is available. If not, return -1. */
2111 find_free_reg (enum reg_class
class, enum machine_mode mode
, int qtyno
,
2112 int accept_call_clobbered
, int just_try_suggested
,
2113 int born_index
, int dead_index
)
2116 HARD_REG_SET first_used
, used
;
2117 #ifdef ELIMINABLE_REGS
2118 static const struct {const int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
2121 /* Validate our parameters. */
2122 if (born_index
< 0 || born_index
> dead_index
)
2125 /* Don't let a pseudo live in a reg across a function call
2126 if we might get a nonlocal goto. */
2127 if (current_function_has_nonlocal_label
2128 && qty
[qtyno
].n_calls_crossed
> 0)
2131 if (accept_call_clobbered
)
2132 COPY_HARD_REG_SET (used
, call_fixed_reg_set
);
2133 else if (qty
[qtyno
].n_calls_crossed
== 0)
2134 COPY_HARD_REG_SET (used
, fixed_reg_set
);
2136 COPY_HARD_REG_SET (used
, call_used_reg_set
);
2138 if (accept_call_clobbered
)
2139 IOR_HARD_REG_SET (used
, losing_caller_save_reg_set
);
2141 for (ins
= born_index
; ins
< dead_index
; ins
++)
2142 IOR_HARD_REG_SET (used
, regs_live_at
[ins
]);
2144 IOR_COMPL_HARD_REG_SET (used
, reg_class_contents
[(int) class]);
2146 /* Don't use the frame pointer reg in local-alloc even if
2147 we may omit the frame pointer, because if we do that and then we
2148 need a frame pointer, reload won't know how to move the pseudo
2149 to another hard reg. It can move only regs made by global-alloc.
2151 This is true of any register that can be eliminated. */
2152 #ifdef ELIMINABLE_REGS
2153 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
2154 SET_HARD_REG_BIT (used
, eliminables
[i
].from
);
2155 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2156 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2157 that it might be eliminated into. */
2158 SET_HARD_REG_BIT (used
, HARD_FRAME_POINTER_REGNUM
);
2161 SET_HARD_REG_BIT (used
, FRAME_POINTER_REGNUM
);
2164 #ifdef CANNOT_CHANGE_MODE_CLASS
2165 cannot_change_mode_set_regs (&used
, mode
, qty
[qtyno
].first_reg
);
2168 /* Normally, the registers that can be used for the first register in
2169 a multi-register quantity are the same as those that can be used for
2170 subsequent registers. However, if just trying suggested registers,
2171 restrict our consideration to them. If there are copy-suggested
2172 register, try them. Otherwise, try the arithmetic-suggested
2174 COPY_HARD_REG_SET (first_used
, used
);
2176 if (just_try_suggested
)
2178 if (qty_phys_num_copy_sugg
[qtyno
] != 0)
2179 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_copy_sugg
[qtyno
]);
2181 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_sugg
[qtyno
]);
2184 /* If all registers are excluded, we can't do anything. */
2185 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) ALL_REGS
], first_used
, fail
);
2187 /* If at least one would be suitable, test each hard reg. */
2189 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2191 #ifdef REG_ALLOC_ORDER
2192 int regno
= reg_alloc_order
[i
];
2196 if (! TEST_HARD_REG_BIT (first_used
, regno
)
2197 && HARD_REGNO_MODE_OK (regno
, mode
)
2198 && (qty
[qtyno
].n_calls_crossed
== 0
2199 || accept_call_clobbered
2200 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2203 int size1
= hard_regno_nregs
[regno
][mode
];
2204 for (j
= 1; j
< size1
&& ! TEST_HARD_REG_BIT (used
, regno
+ j
); j
++);
2207 /* Mark that this register is in use between its birth and death
2209 post_mark_life (regno
, mode
, 1, born_index
, dead_index
);
2212 #ifndef REG_ALLOC_ORDER
2213 /* Skip starting points we know will lose. */
2220 /* If we are just trying suggested register, we have just tried copy-
2221 suggested registers, and there are arithmetic-suggested registers,
2224 /* If it would be profitable to allocate a call-clobbered register
2225 and save and restore it around calls, do that. */
2226 if (just_try_suggested
&& qty_phys_num_copy_sugg
[qtyno
] != 0
2227 && qty_phys_num_sugg
[qtyno
] != 0)
2229 /* Don't try the copy-suggested regs again. */
2230 qty_phys_num_copy_sugg
[qtyno
] = 0;
2231 return find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, 1,
2232 born_index
, dead_index
);
2235 /* We need not check to see if the current function has nonlocal
2236 labels because we don't put any pseudos that are live over calls in
2237 registers in that case. */
2239 if (! accept_call_clobbered
2240 && flag_caller_saves
2241 && ! just_try_suggested
2242 && qty
[qtyno
].n_calls_crossed
!= 0
2243 && CALLER_SAVE_PROFITABLE (qty
[qtyno
].n_refs
,
2244 qty
[qtyno
].n_calls_crossed
))
2246 i
= find_free_reg (class, mode
, qtyno
, 1, 0, born_index
, dead_index
);
2248 caller_save_needed
= 1;
2254 /* Mark that REGNO with machine-mode MODE is live starting from the current
2255 insn (if LIFE is nonzero) or dead starting at the current insn (if LIFE
2259 mark_life (int regno
, enum machine_mode mode
, int life
)
2261 int j
= hard_regno_nregs
[regno
][mode
];
2264 SET_HARD_REG_BIT (regs_live
, regno
+ j
);
2267 CLEAR_HARD_REG_BIT (regs_live
, regno
+ j
);
2270 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2271 is nonzero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2272 to insn number DEATH (exclusive). */
2275 post_mark_life (int regno
, enum machine_mode mode
, int life
, int birth
,
2278 int j
= hard_regno_nregs
[regno
][mode
];
2279 HARD_REG_SET this_reg
;
2281 CLEAR_HARD_REG_SET (this_reg
);
2283 SET_HARD_REG_BIT (this_reg
, regno
+ j
);
2286 while (birth
< death
)
2288 IOR_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2292 while (birth
< death
)
2294 AND_COMPL_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2299 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2300 is the register being clobbered, and R1 is a register being used in
2301 the equivalent expression.
2303 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2304 in which it is used, return 1.
2306 Otherwise, return 0. */
2309 no_conflict_p (rtx insn
, rtx r0 ATTRIBUTE_UNUSED
, rtx r1
)
2312 rtx note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
2315 /* If R1 is a hard register, return 0 since we handle this case
2316 when we scan the insns that actually use it. */
2319 || (REG_P (r1
) && REGNO (r1
) < FIRST_PSEUDO_REGISTER
)
2320 || (GET_CODE (r1
) == SUBREG
&& REG_P (SUBREG_REG (r1
))
2321 && REGNO (SUBREG_REG (r1
)) < FIRST_PSEUDO_REGISTER
))
2324 last
= XEXP (note
, 0);
2326 for (p
= NEXT_INSN (insn
); p
&& p
!= last
; p
= NEXT_INSN (p
))
2329 if (find_reg_note (p
, REG_DEAD
, r1
))
2332 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2333 some earlier optimization pass has inserted instructions into
2334 the sequence, and it is not safe to perform this optimization.
2335 Note that emit_no_conflict_block always ensures that this is
2336 true when these sequences are created. */
2337 if (! find_reg_note (p
, REG_NO_CONFLICT
, r1
))
2344 /* Return the number of alternatives for which the constraint string P
2345 indicates that the operand must be equal to operand 0 and that no register
2349 requires_inout (const char *p
)
2353 int reg_allowed
= 0;
2354 int num_matching_alts
= 0;
2357 for ( ; (c
= *p
); p
+= len
)
2359 len
= CONSTRAINT_LEN (c
, p
);
2362 case '=': case '+': case '?':
2363 case '#': case '&': case '!':
2365 case 'm': case '<': case '>': case 'V': case 'o':
2366 case 'E': case 'F': case 'G': case 'H':
2367 case 's': case 'i': case 'n':
2368 case 'I': case 'J': case 'K': case 'L':
2369 case 'M': case 'N': case 'O': case 'P':
2371 /* These don't say anything we care about. */
2375 if (found_zero
&& ! reg_allowed
)
2376 num_matching_alts
++;
2378 found_zero
= reg_allowed
= 0;
2385 case '1': case '2': case '3': case '4': case '5':
2386 case '6': case '7': case '8': case '9':
2387 /* Skip the balance of the matching constraint. */
2390 while (ISDIGIT (*p
));
2395 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
2396 && !EXTRA_ADDRESS_CONSTRAINT (c
, p
))
2406 if (found_zero
&& ! reg_allowed
)
2407 num_matching_alts
++;
2409 return num_matching_alts
;
2413 dump_local_alloc (FILE *file
)
2416 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2417 if (reg_renumber
[i
] != -1)
2418 fprintf (file
, ";; Register %d in %d.\n", i
, reg_renumber
[i
]);