1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
4 ;; Free Software Foundation, Inc.
5 ;; Mostly by William Schelter.
6 ;; x86_64 support added by Jan Hubicka
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA. */
25 ;; The original PO technology requires these to be ordered by speed,
26 ;; so that assigner will pick the fastest.
28 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
31 ;; updates for most instructions.
33 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
34 ;; constraint letters.
36 ;; The special asm out single letter directives following a '%' are:
37 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
39 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
40 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
41 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
42 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
43 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
44 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
45 ;; 'J' Print the appropriate jump operand.
47 ;; 'b' Print the QImode name of the register for the indicated operand.
48 ;; %b0 would print %al if operands[0] is reg 0.
49 ;; 'w' Likewise, print the HImode name of the register.
50 ;; 'k' Likewise, print the SImode name of the register.
51 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
52 ;; 'y' Print "st(0)" instead of "st" as a register.
57 [; Relocation specifiers
69 (UNSPEC_STACK_PROBE 10)
70 (UNSPEC_STACK_ALLOC 11)
72 (UNSPEC_SSE_PROLOGUE_SAVE 13)
77 (UNSPEC_TLS_LD_BASE 17)
79 ; Other random patterns
89 ; For SSE/MMX support:
100 (UNSPEC_NOP 45) ; prevents combiner cleverness
115 [(UNSPECV_BLOCKAGE 0)
116 (UNSPECV_EH_RETURN 13)
124 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
127 ;; In C guard expressions, put expressions which may be compile-time
128 ;; constants first. This allows for better optimization. For
129 ;; example, write "TARGET_64BIT && reload_completed", not
130 ;; "reload_completed && TARGET_64BIT".
133 ;; Processor type. This attribute must exactly match the processor_type
134 ;; enumeration in i386.h.
135 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8"
136 (const (symbol_ref "ix86_cpu")))
138 ;; A basic instruction type. Refinements due to arguments to be
139 ;; provided in other attributes.
142 alu,alu1,negnot,imov,imovx,lea,
143 incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
144 icmp,test,ibr,setcc,icmov,
145 push,pop,call,callv,leave,
147 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,
148 sselog,sseiadd,sseishft,sseimul,
149 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
150 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
151 (const_string "other"))
153 ;; Main data type used by the insn
155 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF"
156 (const_string "unknown"))
158 ;; The CPU unit operations uses.
159 (define_attr "unit" "integer,i387,sse,mmx,unknown"
160 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
161 (const_string "i387")
162 (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
163 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
165 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
167 (eq_attr "type" "other")
168 (const_string "unknown")]
169 (const_string "integer")))
171 ;; The (bounding maximum) length of an instruction immediate.
172 (define_attr "length_immediate" ""
173 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
175 (eq_attr "unit" "i387,sse,mmx")
177 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
179 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
180 (eq_attr "type" "imov,test")
181 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
182 (eq_attr "type" "call")
183 (if_then_else (match_operand 0 "constant_call_address_operand" "")
186 (eq_attr "type" "callv")
187 (if_then_else (match_operand 1 "constant_call_address_operand" "")
190 ;; We don't know the size before shorten_branches. Expect
191 ;; the instruction to fit for better scheduling.
192 (eq_attr "type" "ibr")
195 (symbol_ref "/* Update immediate_length and other attributes! */
198 ;; The (bounding maximum) length of an instruction address.
199 (define_attr "length_address" ""
200 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
202 (and (eq_attr "type" "call")
203 (match_operand 0 "constant_call_address_operand" ""))
205 (and (eq_attr "type" "callv")
206 (match_operand 1 "constant_call_address_operand" ""))
209 (symbol_ref "ix86_attr_length_address_default (insn)")))
211 ;; Set when length prefix is used.
212 (define_attr "prefix_data16" ""
213 (if_then_else (ior (eq_attr "mode" "HI")
214 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
218 ;; Set when string REP prefix is used.
219 (define_attr "prefix_rep" ""
220 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
224 ;; Set when 0f opcode prefix is used.
225 (define_attr "prefix_0f" ""
227 (ior (eq_attr "type" "imovx,setcc,icmov")
228 (eq_attr "unit" "sse,mmx"))
232 ;; Set when 0f opcode prefix is used.
233 (define_attr "prefix_rex" ""
234 (cond [(and (eq_attr "mode" "DI")
235 (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
237 (and (eq_attr "mode" "QI")
238 (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
241 (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
247 ;; Set when modrm byte is used.
248 (define_attr "modrm" ""
249 (cond [(eq_attr "type" "str,cld,leave")
251 (eq_attr "unit" "i387")
253 (and (eq_attr "type" "incdec")
254 (ior (match_operand:SI 1 "register_operand" "")
255 (match_operand:HI 1 "register_operand" "")))
257 (and (eq_attr "type" "push")
258 (not (match_operand 1 "memory_operand" "")))
260 (and (eq_attr "type" "pop")
261 (not (match_operand 0 "memory_operand" "")))
263 (and (eq_attr "type" "imov")
264 (and (match_operand 0 "register_operand" "")
265 (match_operand 1 "immediate_operand" "")))
267 (and (eq_attr "type" "call")
268 (match_operand 0 "constant_call_address_operand" ""))
270 (and (eq_attr "type" "callv")
271 (match_operand 1 "constant_call_address_operand" ""))
276 ;; The (bounding maximum) length of an instruction in bytes.
277 ;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want
278 ;; to split it and compute proper length as for other insns.
279 (define_attr "length" ""
280 (cond [(eq_attr "type" "other,multi,fistp")
282 (eq_attr "unit" "i387")
284 (plus (attr "prefix_data16")
285 (attr "length_address")))]
286 (plus (plus (attr "modrm")
287 (plus (attr "prefix_0f")
288 (plus (attr "prefix_rex")
290 (plus (attr "prefix_rep")
291 (plus (attr "prefix_data16")
292 (plus (attr "length_immediate")
293 (attr "length_address")))))))
295 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
296 ;; `store' if there is a simple memory reference therein, or `unknown'
297 ;; if the instruction is complex.
299 (define_attr "memory" "none,load,store,both,unknown"
300 (cond [(eq_attr "type" "other,multi,str")
301 (const_string "unknown")
302 (eq_attr "type" "lea,fcmov,fpspc,cld")
303 (const_string "none")
304 (eq_attr "type" "fistp,leave")
305 (const_string "both")
306 (eq_attr "type" "push")
307 (if_then_else (match_operand 1 "memory_operand" "")
308 (const_string "both")
309 (const_string "store"))
310 (eq_attr "type" "pop")
311 (if_then_else (match_operand 0 "memory_operand" "")
312 (const_string "both")
313 (const_string "load"))
314 (eq_attr "type" "setcc")
315 (if_then_else (match_operand 0 "memory_operand" "")
316 (const_string "store")
317 (const_string "none"))
318 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
319 (if_then_else (ior (match_operand 0 "memory_operand" "")
320 (match_operand 1 "memory_operand" ""))
321 (const_string "load")
322 (const_string "none"))
323 (eq_attr "type" "ibr")
324 (if_then_else (match_operand 0 "memory_operand" "")
325 (const_string "load")
326 (const_string "none"))
327 (eq_attr "type" "call")
328 (if_then_else (match_operand 0 "constant_call_address_operand" "")
329 (const_string "none")
330 (const_string "load"))
331 (eq_attr "type" "callv")
332 (if_then_else (match_operand 1 "constant_call_address_operand" "")
333 (const_string "none")
334 (const_string "load"))
335 (and (eq_attr "type" "alu1,negnot")
336 (match_operand 1 "memory_operand" ""))
337 (const_string "both")
338 (and (match_operand 0 "memory_operand" "")
339 (match_operand 1 "memory_operand" ""))
340 (const_string "both")
341 (match_operand 0 "memory_operand" "")
342 (const_string "store")
343 (match_operand 1 "memory_operand" "")
344 (const_string "load")
347 imov,imovx,icmp,test,
349 sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,
350 mmx,mmxmov,mmxcmp,mmxcvt")
351 (match_operand 2 "memory_operand" ""))
352 (const_string "load")
353 (and (eq_attr "type" "icmov")
354 (match_operand 3 "memory_operand" ""))
355 (const_string "load")
357 (const_string "none")))
359 ;; Indicates if an instruction has both an immediate and a displacement.
361 (define_attr "imm_disp" "false,true,unknown"
362 (cond [(eq_attr "type" "other,multi")
363 (const_string "unknown")
364 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
365 (and (match_operand 0 "memory_displacement_operand" "")
366 (match_operand 1 "immediate_operand" "")))
367 (const_string "true")
368 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
369 (and (match_operand 0 "memory_displacement_operand" "")
370 (match_operand 2 "immediate_operand" "")))
371 (const_string "true")
373 (const_string "false")))
375 ;; Indicates if an FP operation has an integer source.
377 (define_attr "fp_int_src" "false,true"
378 (const_string "false"))
380 ;; Describe a user's asm statement.
381 (define_asm_attributes
382 [(set_attr "length" "128")
383 (set_attr "type" "multi")])
385 (include "pentium.md")
388 (include "athlon.md")
390 ;; Compare instructions.
392 ;; All compare insns have expanders that save the operands away without
393 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
394 ;; after the cmp) will actually emit the cmpM.
396 (define_expand "cmpdi"
398 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
399 (match_operand:DI 1 "x86_64_general_operand" "")))]
402 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
403 operands[0] = force_reg (DImode, operands[0]);
404 ix86_compare_op0 = operands[0];
405 ix86_compare_op1 = operands[1];
409 (define_expand "cmpsi"
411 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
412 (match_operand:SI 1 "general_operand" "")))]
415 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
416 operands[0] = force_reg (SImode, operands[0]);
417 ix86_compare_op0 = operands[0];
418 ix86_compare_op1 = operands[1];
422 (define_expand "cmphi"
424 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
425 (match_operand:HI 1 "general_operand" "")))]
428 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
429 operands[0] = force_reg (HImode, operands[0]);
430 ix86_compare_op0 = operands[0];
431 ix86_compare_op1 = operands[1];
435 (define_expand "cmpqi"
437 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
438 (match_operand:QI 1 "general_operand" "")))]
441 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
442 operands[0] = force_reg (QImode, operands[0]);
443 ix86_compare_op0 = operands[0];
444 ix86_compare_op1 = operands[1];
448 (define_insn "cmpdi_ccno_1_rex64"
450 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
451 (match_operand:DI 1 "const0_operand" "n,n")))]
452 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
454 test{q}\t{%0, %0|%0, %0}
455 cmp{q}\t{%1, %0|%0, %1}"
456 [(set_attr "type" "test,icmp")
457 (set_attr "length_immediate" "0,1")
458 (set_attr "mode" "DI")])
460 (define_insn "*cmpdi_minus_1_rex64"
462 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
463 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
465 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
466 "cmp{q}\t{%1, %0|%0, %1}"
467 [(set_attr "type" "icmp")
468 (set_attr "mode" "DI")])
470 (define_expand "cmpdi_1_rex64"
472 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
473 (match_operand:DI 1 "general_operand" "")))]
477 (define_insn "cmpdi_1_insn_rex64"
479 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
480 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
481 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
482 "cmp{q}\t{%1, %0|%0, %1}"
483 [(set_attr "type" "icmp")
484 (set_attr "mode" "DI")])
487 (define_insn "*cmpsi_ccno_1"
489 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
490 (match_operand:SI 1 "const0_operand" "n,n")))]
491 "ix86_match_ccmode (insn, CCNOmode)"
493 test{l}\t{%0, %0|%0, %0}
494 cmp{l}\t{%1, %0|%0, %1}"
495 [(set_attr "type" "test,icmp")
496 (set_attr "length_immediate" "0,1")
497 (set_attr "mode" "SI")])
499 (define_insn "*cmpsi_minus_1"
501 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
502 (match_operand:SI 1 "general_operand" "ri,mr"))
504 "ix86_match_ccmode (insn, CCGOCmode)"
505 "cmp{l}\t{%1, %0|%0, %1}"
506 [(set_attr "type" "icmp")
507 (set_attr "mode" "SI")])
509 (define_expand "cmpsi_1"
511 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
512 (match_operand:SI 1 "general_operand" "ri,mr")))]
516 (define_insn "*cmpsi_1_insn"
518 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
519 (match_operand:SI 1 "general_operand" "ri,mr")))]
520 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
521 && ix86_match_ccmode (insn, CCmode)"
522 "cmp{l}\t{%1, %0|%0, %1}"
523 [(set_attr "type" "icmp")
524 (set_attr "mode" "SI")])
526 (define_insn "*cmphi_ccno_1"
528 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
529 (match_operand:HI 1 "const0_operand" "n,n")))]
530 "ix86_match_ccmode (insn, CCNOmode)"
532 test{w}\t{%0, %0|%0, %0}
533 cmp{w}\t{%1, %0|%0, %1}"
534 [(set_attr "type" "test,icmp")
535 (set_attr "length_immediate" "0,1")
536 (set_attr "mode" "HI")])
538 (define_insn "*cmphi_minus_1"
540 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
541 (match_operand:HI 1 "general_operand" "ri,mr"))
543 "ix86_match_ccmode (insn, CCGOCmode)"
544 "cmp{w}\t{%1, %0|%0, %1}"
545 [(set_attr "type" "icmp")
546 (set_attr "mode" "HI")])
548 (define_insn "*cmphi_1"
550 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
551 (match_operand:HI 1 "general_operand" "ri,mr")))]
552 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
553 && ix86_match_ccmode (insn, CCmode)"
554 "cmp{w}\t{%1, %0|%0, %1}"
555 [(set_attr "type" "icmp")
556 (set_attr "mode" "HI")])
558 (define_insn "*cmpqi_ccno_1"
560 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
561 (match_operand:QI 1 "const0_operand" "n,n")))]
562 "ix86_match_ccmode (insn, CCNOmode)"
564 test{b}\t{%0, %0|%0, %0}
565 cmp{b}\t{$0, %0|%0, 0}"
566 [(set_attr "type" "test,icmp")
567 (set_attr "length_immediate" "0,1")
568 (set_attr "mode" "QI")])
570 (define_insn "*cmpqi_1"
572 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
573 (match_operand:QI 1 "general_operand" "qi,mq")))]
574 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
575 && ix86_match_ccmode (insn, CCmode)"
576 "cmp{b}\t{%1, %0|%0, %1}"
577 [(set_attr "type" "icmp")
578 (set_attr "mode" "QI")])
580 (define_insn "*cmpqi_minus_1"
582 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
583 (match_operand:QI 1 "general_operand" "qi,mq"))
585 "ix86_match_ccmode (insn, CCGOCmode)"
586 "cmp{b}\t{%1, %0|%0, %1}"
587 [(set_attr "type" "icmp")
588 (set_attr "mode" "QI")])
590 (define_insn "*cmpqi_ext_1"
593 (match_operand:QI 0 "general_operand" "Qm")
596 (match_operand 1 "ext_register_operand" "Q")
599 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
600 "cmp{b}\t{%h1, %0|%0, %h1}"
601 [(set_attr "type" "icmp")
602 (set_attr "mode" "QI")])
604 (define_insn "*cmpqi_ext_1_rex64"
607 (match_operand:QI 0 "register_operand" "Q")
610 (match_operand 1 "ext_register_operand" "Q")
613 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
614 "cmp{b}\t{%h1, %0|%0, %h1}"
615 [(set_attr "type" "icmp")
616 (set_attr "mode" "QI")])
618 (define_insn "*cmpqi_ext_2"
623 (match_operand 0 "ext_register_operand" "Q")
626 (match_operand:QI 1 "const0_operand" "n")))]
627 "ix86_match_ccmode (insn, CCNOmode)"
629 [(set_attr "type" "test")
630 (set_attr "length_immediate" "0")
631 (set_attr "mode" "QI")])
633 (define_expand "cmpqi_ext_3"
638 (match_operand 0 "ext_register_operand" "")
641 (match_operand:QI 1 "general_operand" "")))]
645 (define_insn "cmpqi_ext_3_insn"
650 (match_operand 0 "ext_register_operand" "Q")
653 (match_operand:QI 1 "general_operand" "Qmn")))]
654 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
655 "cmp{b}\t{%1, %h0|%h0, %1}"
656 [(set_attr "type" "icmp")
657 (set_attr "mode" "QI")])
659 (define_insn "cmpqi_ext_3_insn_rex64"
664 (match_operand 0 "ext_register_operand" "Q")
667 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
668 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
669 "cmp{b}\t{%1, %h0|%h0, %1}"
670 [(set_attr "type" "icmp")
671 (set_attr "mode" "QI")])
673 (define_insn "*cmpqi_ext_4"
678 (match_operand 0 "ext_register_operand" "Q")
683 (match_operand 1 "ext_register_operand" "Q")
686 "ix86_match_ccmode (insn, CCmode)"
687 "cmp{b}\t{%h1, %h0|%h0, %h1}"
688 [(set_attr "type" "icmp")
689 (set_attr "mode" "QI")])
691 ;; These implement float point compares.
692 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
693 ;; which would allow mix and match FP modes on the compares. Which is what
694 ;; the old patterns did, but with many more of them.
696 (define_expand "cmpxf"
698 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
699 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
700 "!TARGET_64BIT && TARGET_80387"
702 ix86_compare_op0 = operands[0];
703 ix86_compare_op1 = operands[1];
707 (define_expand "cmptf"
709 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
710 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
713 ix86_compare_op0 = operands[0];
714 ix86_compare_op1 = operands[1];
718 (define_expand "cmpdf"
720 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
721 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
722 "TARGET_80387 || TARGET_SSE2"
724 ix86_compare_op0 = operands[0];
725 ix86_compare_op1 = operands[1];
729 (define_expand "cmpsf"
731 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
732 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
733 "TARGET_80387 || TARGET_SSE"
735 ix86_compare_op0 = operands[0];
736 ix86_compare_op1 = operands[1];
740 ;; FP compares, step 1:
741 ;; Set the FP condition codes.
743 ;; CCFPmode compare with exceptions
744 ;; CCFPUmode compare with no exceptions
746 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
747 ;; and that fp moves clobber the condition codes, and that there is
748 ;; currently no way to describe this fact to reg-stack. So there are
749 ;; no splitters yet for this.
751 ;; %%% YIKES! This scheme does not retain a strong connection between
752 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
753 ;; work! Only allow tos/mem with tos in op 0.
755 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
756 ;; things aren't as bad as they sound...
758 (define_insn "*cmpfp_0"
759 [(set (match_operand:HI 0 "register_operand" "=a")
761 [(compare:CCFP (match_operand 1 "register_operand" "f")
762 (match_operand 2 "const0_operand" "X"))]
765 && FLOAT_MODE_P (GET_MODE (operands[1]))
766 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
768 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
769 return "ftst\;fnstsw\t%0\;fstp\t%y0";
771 return "ftst\;fnstsw\t%0";
773 [(set_attr "type" "multi")
775 (cond [(match_operand:SF 1 "" "")
777 (match_operand:DF 1 "" "")
780 (const_string "XF")))])
782 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
783 ;; used to manage the reg stack popping would not be preserved.
785 (define_insn "*cmpfp_2_sf"
788 (match_operand:SF 0 "register_operand" "f")
789 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
791 "* return output_fp_compare (insn, operands, 0, 0);"
792 [(set_attr "type" "fcmp")
793 (set_attr "mode" "SF")])
795 (define_insn "*cmpfp_2_sf_1"
796 [(set (match_operand:HI 0 "register_operand" "=a")
799 (match_operand:SF 1 "register_operand" "f")
800 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
803 "* return output_fp_compare (insn, operands, 2, 0);"
804 [(set_attr "type" "fcmp")
805 (set_attr "mode" "SF")])
807 (define_insn "*cmpfp_2_df"
810 (match_operand:DF 0 "register_operand" "f")
811 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
813 "* return output_fp_compare (insn, operands, 0, 0);"
814 [(set_attr "type" "fcmp")
815 (set_attr "mode" "DF")])
817 (define_insn "*cmpfp_2_df_1"
818 [(set (match_operand:HI 0 "register_operand" "=a")
821 (match_operand:DF 1 "register_operand" "f")
822 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
825 "* return output_fp_compare (insn, operands, 2, 0);"
826 [(set_attr "type" "multi")
827 (set_attr "mode" "DF")])
829 (define_insn "*cmpfp_2_xf"
832 (match_operand:XF 0 "register_operand" "f")
833 (match_operand:XF 1 "register_operand" "f")))]
834 "!TARGET_64BIT && TARGET_80387"
835 "* return output_fp_compare (insn, operands, 0, 0);"
836 [(set_attr "type" "fcmp")
837 (set_attr "mode" "XF")])
839 (define_insn "*cmpfp_2_tf"
842 (match_operand:TF 0 "register_operand" "f")
843 (match_operand:TF 1 "register_operand" "f")))]
845 "* return output_fp_compare (insn, operands, 0, 0);"
846 [(set_attr "type" "fcmp")
847 (set_attr "mode" "XF")])
849 (define_insn "*cmpfp_2_xf_1"
850 [(set (match_operand:HI 0 "register_operand" "=a")
853 (match_operand:XF 1 "register_operand" "f")
854 (match_operand:XF 2 "register_operand" "f"))]
856 "!TARGET_64BIT && TARGET_80387"
857 "* return output_fp_compare (insn, operands, 2, 0);"
858 [(set_attr "type" "multi")
859 (set_attr "mode" "XF")])
861 (define_insn "*cmpfp_2_tf_1"
862 [(set (match_operand:HI 0 "register_operand" "=a")
865 (match_operand:TF 1 "register_operand" "f")
866 (match_operand:TF 2 "register_operand" "f"))]
869 "* return output_fp_compare (insn, operands, 2, 0);"
870 [(set_attr "type" "multi")
871 (set_attr "mode" "XF")])
873 (define_insn "*cmpfp_2u"
876 (match_operand 0 "register_operand" "f")
877 (match_operand 1 "register_operand" "f")))]
879 && FLOAT_MODE_P (GET_MODE (operands[0]))
880 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
881 "* return output_fp_compare (insn, operands, 0, 1);"
882 [(set_attr "type" "fcmp")
884 (cond [(match_operand:SF 1 "" "")
886 (match_operand:DF 1 "" "")
889 (const_string "XF")))])
891 (define_insn "*cmpfp_2u_1"
892 [(set (match_operand:HI 0 "register_operand" "=a")
895 (match_operand 1 "register_operand" "f")
896 (match_operand 2 "register_operand" "f"))]
899 && FLOAT_MODE_P (GET_MODE (operands[1]))
900 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
901 "* return output_fp_compare (insn, operands, 2, 1);"
902 [(set_attr "type" "multi")
904 (cond [(match_operand:SF 1 "" "")
906 (match_operand:DF 1 "" "")
909 (const_string "XF")))])
911 ;; Patterns to match the SImode-in-memory ficom instructions.
913 ;; %%% Play games with accepting gp registers, as otherwise we have to
914 ;; force them to memory during rtl generation, which is no good. We
915 ;; can get rid of this once we teach reload to do memory input reloads
918 (define_insn "*ficom_1"
921 (match_operand 0 "register_operand" "f,f")
922 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
923 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
924 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
927 ;; Split the not-really-implemented gp register case into a
928 ;; push-op-pop sequence.
930 ;; %%% This is most efficient, but am I gonna get in trouble
931 ;; for separating cc0_setter and cc0_user?
936 (match_operand:SF 0 "register_operand" "")
937 (float (match_operand:SI 1 "register_operand" ""))))]
938 "0 && TARGET_80387 && reload_completed"
939 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
940 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
941 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
942 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
943 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
944 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
946 ;; FP compares, step 2
947 ;; Move the fpsw to ax.
949 (define_insn "*x86_fnstsw_1"
950 [(set (match_operand:HI 0 "register_operand" "=a")
951 (unspec:HI [(reg 18)] UNSPEC_FNSTSW))]
954 [(set_attr "length" "2")
955 (set_attr "mode" "SI")
956 (set_attr "unit" "i387")
957 (set_attr "ppro_uops" "few")])
959 ;; FP compares, step 3
960 ;; Get ax into flags, general case.
962 (define_insn "x86_sahf_1"
964 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
967 [(set_attr "length" "1")
968 (set_attr "athlon_decode" "vector")
969 (set_attr "mode" "SI")
970 (set_attr "ppro_uops" "one")])
972 ;; Pentium Pro can do steps 1 through 3 in one go.
974 (define_insn "*cmpfp_i"
976 (compare:CCFP (match_operand 0 "register_operand" "f")
977 (match_operand 1 "register_operand" "f")))]
978 "TARGET_80387 && TARGET_CMOVE
979 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
980 && FLOAT_MODE_P (GET_MODE (operands[0]))
981 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
982 "* return output_fp_compare (insn, operands, 1, 0);"
983 [(set_attr "type" "fcmp")
985 (cond [(match_operand:SF 1 "" "")
987 (match_operand:DF 1 "" "")
990 (const_string "XF")))
991 (set_attr "athlon_decode" "vector")])
993 (define_insn "*cmpfp_i_sse"
995 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
996 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
998 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
999 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1000 "* return output_fp_compare (insn, operands, 1, 0);"
1001 [(set_attr "type" "fcmp,ssecomi")
1003 (if_then_else (match_operand:SF 1 "" "")
1005 (const_string "DF")))
1006 (set_attr "athlon_decode" "vector")])
1008 (define_insn "*cmpfp_i_sse_only"
1010 (compare:CCFP (match_operand 0 "register_operand" "x")
1011 (match_operand 1 "nonimmediate_operand" "xm")))]
1012 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1013 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1014 "* return output_fp_compare (insn, operands, 1, 0);"
1015 [(set_attr "type" "ssecomi")
1017 (if_then_else (match_operand:SF 1 "" "")
1019 (const_string "DF")))
1020 (set_attr "athlon_decode" "vector")])
1022 (define_insn "*cmpfp_iu"
1023 [(set (reg:CCFPU 17)
1024 (compare:CCFPU (match_operand 0 "register_operand" "f")
1025 (match_operand 1 "register_operand" "f")))]
1026 "TARGET_80387 && TARGET_CMOVE
1027 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1028 && FLOAT_MODE_P (GET_MODE (operands[0]))
1029 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1030 "* return output_fp_compare (insn, operands, 1, 1);"
1031 [(set_attr "type" "fcmp")
1033 (cond [(match_operand:SF 1 "" "")
1035 (match_operand:DF 1 "" "")
1038 (const_string "XF")))
1039 (set_attr "athlon_decode" "vector")])
1041 (define_insn "*cmpfp_iu_sse"
1042 [(set (reg:CCFPU 17)
1043 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1044 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1046 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1047 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1048 "* return output_fp_compare (insn, operands, 1, 1);"
1049 [(set_attr "type" "fcmp,ssecomi")
1051 (if_then_else (match_operand:SF 1 "" "")
1053 (const_string "DF")))
1054 (set_attr "athlon_decode" "vector")])
1056 (define_insn "*cmpfp_iu_sse_only"
1057 [(set (reg:CCFPU 17)
1058 (compare:CCFPU (match_operand 0 "register_operand" "x")
1059 (match_operand 1 "nonimmediate_operand" "xm")))]
1060 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1061 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1062 "* return output_fp_compare (insn, operands, 1, 1);"
1063 [(set_attr "type" "ssecomi")
1065 (if_then_else (match_operand:SF 1 "" "")
1067 (const_string "DF")))
1068 (set_attr "athlon_decode" "vector")])
1070 ;; Move instructions.
1072 ;; General case of fullword move.
1074 (define_expand "movsi"
1075 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1076 (match_operand:SI 1 "general_operand" ""))]
1078 "ix86_expand_move (SImode, operands); DONE;")
1080 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1083 ;; %%% We don't use a post-inc memory reference because x86 is not a
1084 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1085 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1086 ;; targets without our curiosities, and it is just as easy to represent
1087 ;; this differently.
1089 (define_insn "*pushsi2"
1090 [(set (match_operand:SI 0 "push_operand" "=<")
1091 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1094 [(set_attr "type" "push")
1095 (set_attr "mode" "SI")])
1097 ;; For 64BIT abi we always round up to 8 bytes.
1098 (define_insn "*pushsi2_rex64"
1099 [(set (match_operand:SI 0 "push_operand" "=X")
1100 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1103 [(set_attr "type" "push")
1104 (set_attr "mode" "SI")])
1106 (define_insn "*pushsi2_prologue"
1107 [(set (match_operand:SI 0 "push_operand" "=<")
1108 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1109 (clobber (mem:BLK (scratch)))]
1112 [(set_attr "type" "push")
1113 (set_attr "mode" "SI")])
1115 (define_insn "*popsi1_epilogue"
1116 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1117 (mem:SI (reg:SI 7)))
1119 (plus:SI (reg:SI 7) (const_int 4)))
1120 (clobber (mem:BLK (scratch)))]
1123 [(set_attr "type" "pop")
1124 (set_attr "mode" "SI")])
1126 (define_insn "popsi1"
1127 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1128 (mem:SI (reg:SI 7)))
1130 (plus:SI (reg:SI 7) (const_int 4)))]
1133 [(set_attr "type" "pop")
1134 (set_attr "mode" "SI")])
1136 (define_insn "*movsi_xor"
1137 [(set (match_operand:SI 0 "register_operand" "=r")
1138 (match_operand:SI 1 "const0_operand" "i"))
1139 (clobber (reg:CC 17))]
1140 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1141 "xor{l}\t{%0, %0|%0, %0}"
1142 [(set_attr "type" "alu1")
1143 (set_attr "mode" "SI")
1144 (set_attr "length_immediate" "0")])
1146 (define_insn "*movsi_or"
1147 [(set (match_operand:SI 0 "register_operand" "=r")
1148 (match_operand:SI 1 "immediate_operand" "i"))
1149 (clobber (reg:CC 17))]
1150 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1151 && INTVAL (operands[1]) == -1
1152 && (TARGET_PENTIUM || optimize_size)"
1154 operands[1] = constm1_rtx;
1155 return "or{l}\t{%1, %0|%0, %1}";
1157 [(set_attr "type" "alu1")
1158 (set_attr "mode" "SI")
1159 (set_attr "length_immediate" "1")])
1161 ; The first alternative is used only to compute proper length of instruction.
1162 ; Reload's algorithm does not take into account the cost of spill instructions
1163 ; needed to free register in given class, so avoid it from choosing the first
1164 ; alternative when eax is not available.
1166 (define_insn "*movsi_1"
1167 [(set (match_operand:SI 0 "nonimmediate_operand" "=*?a,r,*?a,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
1168 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,*y,rm,*Y,*Y"))]
1169 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1171 switch (get_attr_type (insn))
1174 if (get_attr_mode (insn) == TImode || which_alternative == 9)
1175 return "movdqa\t{%1, %0|%0, %1}";
1176 return "movd\t{%1, %0|%0, %1}";
1179 if (get_attr_mode (insn) == DImode)
1180 return "movq\t{%1, %0|%0, %1}";
1181 return "movd\t{%1, %0|%0, %1}";
1184 return "lea{l}\t{%1, %0|%0, %1}";
1187 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1189 return "mov{l}\t{%1, %0|%0, %1}";
1193 (cond [(eq_attr "alternative" "4,5,6")
1194 (const_string "mmxmov")
1195 (eq_attr "alternative" "7,8,9")
1196 (const_string "ssemov")
1197 (and (ne (symbol_ref "flag_pic") (const_int 0))
1198 (match_operand:SI 1 "symbolic_operand" ""))
1199 (const_string "lea")
1201 (const_string "imov")))
1202 (set_attr "modrm" "0,*,0,*,*,*,*,*,*,*")
1203 (set_attr "mode" "SI,SI,SI,SI,SI,SI,DI,TI,SI,SI")])
1205 ;; Stores and loads of ax to arbitrary constant address.
1206 ;; We fake an second form of instruction to force reload to load address
1207 ;; into register when rax is not available
1208 (define_insn "*movabssi_1_rex64"
1209 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1210 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1213 movabs{l}\t{%1, %P0|%P0, %1}
1214 mov{l}\t{%1, %a0|%a0, %1}
1215 movabs{l}\t{%1, %a0|%a0, %1}"
1216 [(set_attr "type" "imov")
1217 (set_attr "modrm" "0,*,*")
1218 (set_attr "length_address" "8,0,0")
1219 (set_attr "length_immediate" "0,*,*")
1220 (set_attr "memory" "store")
1221 (set_attr "mode" "SI")])
1223 (define_insn "*movabssi_2_rex64"
1224 [(set (match_operand:SI 0 "register_operand" "=a,r")
1225 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1228 movabs{l}\t{%P1, %0|%0, %P1}
1229 mov{l}\t{%a1, %0|%0, %a1}"
1230 [(set_attr "type" "imov")
1231 (set_attr "modrm" "0,*")
1232 (set_attr "length_address" "8,0")
1233 (set_attr "length_immediate" "0")
1234 (set_attr "memory" "load")
1235 (set_attr "mode" "SI")])
1237 (define_insn "*swapsi"
1238 [(set (match_operand:SI 0 "register_operand" "+r")
1239 (match_operand:SI 1 "register_operand" "+r"))
1244 [(set_attr "type" "imov")
1245 (set_attr "pent_pair" "np")
1246 (set_attr "athlon_decode" "vector")
1247 (set_attr "mode" "SI")
1248 (set_attr "modrm" "0")
1249 (set_attr "ppro_uops" "few")])
1251 (define_expand "movhi"
1252 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1253 (match_operand:HI 1 "general_operand" ""))]
1255 "ix86_expand_move (HImode, operands); DONE;")
1257 (define_insn "*pushhi2"
1258 [(set (match_operand:HI 0 "push_operand" "=<,<")
1259 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1262 push{w}\t{|WORD PTR }%1
1264 [(set_attr "type" "push")
1265 (set_attr "mode" "HI")])
1267 ;; For 64BIT abi we always round up to 8 bytes.
1268 (define_insn "*pushhi2_rex64"
1269 [(set (match_operand:HI 0 "push_operand" "=X")
1270 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1273 [(set_attr "type" "push")
1274 (set_attr "mode" "QI")])
1276 ; The first alternative is used only to compute proper length of instruction.
1277 ; Reload's algorithm does not take into account the cost of spill instructions
1278 ; needed to free register in given class, so avoid it from choosing the first
1279 ; alternative when eax is not available.
1281 (define_insn "*movhi_1"
1282 [(set (match_operand:HI 0 "nonimmediate_operand" "=*?a,r,r,*?a,r,m")
1283 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1284 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1286 switch (get_attr_type (insn))
1289 /* movzwl is faster than movw on p2 due to partial word stalls,
1290 though not as fast as an aligned movl. */
1291 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1293 if (get_attr_mode (insn) == MODE_SI)
1294 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1296 return "mov{w}\t{%1, %0|%0, %1}";
1300 (cond [(and (eq_attr "alternative" "0,1")
1301 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1303 (eq (symbol_ref "TARGET_HIMODE_MATH")
1305 (const_string "imov")
1306 (and (eq_attr "alternative" "2,3,4")
1307 (match_operand:HI 1 "aligned_operand" ""))
1308 (const_string "imov")
1309 (and (ne (symbol_ref "TARGET_MOVX")
1311 (eq_attr "alternative" "0,1,3,4"))
1312 (const_string "imovx")
1314 (const_string "imov")))
1316 (cond [(eq_attr "type" "imovx")
1318 (and (eq_attr "alternative" "2,3,4")
1319 (match_operand:HI 1 "aligned_operand" ""))
1321 (and (eq_attr "alternative" "0,1")
1322 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1324 (eq (symbol_ref "TARGET_HIMODE_MATH")
1328 (const_string "HI")))
1329 (set_attr "modrm" "0,*,*,0,*,*")])
1331 ;; Stores and loads of ax to arbitrary constant address.
1332 ;; We fake an second form of instruction to force reload to load address
1333 ;; into register when rax is not available
1334 (define_insn "*movabshi_1_rex64"
1335 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1336 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1339 movabs{w}\t{%1, %P0|%P0, %1}
1340 mov{w}\t{%1, %a0|%a0, %1}
1341 movabs{w}\t{%1, %a0|%a0, %1}"
1342 [(set_attr "type" "imov")
1343 (set_attr "modrm" "0,*,*")
1344 (set_attr "length_address" "8,0,0")
1345 (set_attr "length_immediate" "0,*,*")
1346 (set_attr "memory" "store")
1347 (set_attr "mode" "HI")])
1349 (define_insn "*movabshi_2_rex64"
1350 [(set (match_operand:HI 0 "register_operand" "=a,r")
1351 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1354 movabs{w}\t{%P1, %0|%0, %P1}
1355 mov{w}\t{%a1, %0|%0, %a1}"
1356 [(set_attr "type" "imov")
1357 (set_attr "modrm" "0,*")
1358 (set_attr "length_address" "8,0")
1359 (set_attr "length_immediate" "0")
1360 (set_attr "memory" "load")
1361 (set_attr "mode" "HI")])
1363 (define_insn "*swaphi_1"
1364 [(set (match_operand:HI 0 "register_operand" "+r")
1365 (match_operand:HI 1 "register_operand" "+r"))
1368 "TARGET_PARTIAL_REG_STALL"
1370 [(set_attr "type" "imov")
1371 (set_attr "pent_pair" "np")
1372 (set_attr "mode" "HI")
1373 (set_attr "modrm" "0")
1374 (set_attr "ppro_uops" "few")])
1376 (define_insn "*swaphi_2"
1377 [(set (match_operand:HI 0 "register_operand" "+r")
1378 (match_operand:HI 1 "register_operand" "+r"))
1381 "! TARGET_PARTIAL_REG_STALL"
1383 [(set_attr "type" "imov")
1384 (set_attr "pent_pair" "np")
1385 (set_attr "mode" "SI")
1386 (set_attr "modrm" "0")
1387 (set_attr "ppro_uops" "few")])
1389 (define_expand "movstricthi"
1390 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1391 (match_operand:HI 1 "general_operand" ""))]
1392 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1394 /* Don't generate memory->memory moves, go through a register */
1395 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1396 operands[1] = force_reg (HImode, operands[1]);
1399 (define_insn "*movstricthi_1"
1400 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1401 (match_operand:HI 1 "general_operand" "rn,m"))]
1402 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1403 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1404 "mov{w}\t{%1, %0|%0, %1}"
1405 [(set_attr "type" "imov")
1406 (set_attr "mode" "HI")])
1408 (define_insn "*movstricthi_xor"
1409 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1410 (match_operand:HI 1 "const0_operand" "i"))
1411 (clobber (reg:CC 17))]
1413 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1414 "xor{w}\t{%0, %0|%0, %0}"
1415 [(set_attr "type" "alu1")
1416 (set_attr "mode" "HI")
1417 (set_attr "length_immediate" "0")])
1419 (define_expand "movqi"
1420 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1421 (match_operand:QI 1 "general_operand" ""))]
1423 "ix86_expand_move (QImode, operands); DONE;")
1425 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1426 ;; "push a byte". But actually we use pushw, which has the effect
1427 ;; of rounding the amount pushed up to a halfword.
1429 (define_insn "*pushqi2"
1430 [(set (match_operand:QI 0 "push_operand" "=X,X")
1431 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1434 push{w}\t{|word ptr }%1
1436 [(set_attr "type" "push")
1437 (set_attr "mode" "HI")])
1439 ;; For 64BIT abi we always round up to 8 bytes.
1440 (define_insn "*pushqi2_rex64"
1441 [(set (match_operand:QI 0 "push_operand" "=X")
1442 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1445 [(set_attr "type" "push")
1446 (set_attr "mode" "QI")])
1448 ;; Situation is quite tricky about when to choose full sized (SImode) move
1449 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1450 ;; partial register dependency machines (such as AMD Athlon), where QImode
1451 ;; moves issue extra dependency and for partial register stalls machines
1452 ;; that don't use QImode patterns (and QImode move cause stall on the next
1455 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1456 ;; register stall machines with, where we use QImode instructions, since
1457 ;; partial register stall can be caused there. Then we use movzx.
1458 (define_insn "*movqi_1"
1459 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1460 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1461 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1463 switch (get_attr_type (insn))
1466 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1468 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1470 if (get_attr_mode (insn) == MODE_SI)
1471 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1473 return "mov{b}\t{%1, %0|%0, %1}";
1477 (cond [(and (eq_attr "alternative" "3")
1478 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1480 (eq (symbol_ref "TARGET_QIMODE_MATH")
1482 (const_string "imov")
1483 (eq_attr "alternative" "3,5")
1484 (const_string "imovx")
1485 (and (ne (symbol_ref "TARGET_MOVX")
1487 (eq_attr "alternative" "2"))
1488 (const_string "imovx")
1490 (const_string "imov")))
1492 (cond [(eq_attr "alternative" "3,4,5")
1494 (eq_attr "alternative" "6")
1496 (eq_attr "type" "imovx")
1498 (and (eq_attr "type" "imov")
1499 (and (eq_attr "alternative" "0,1,2")
1500 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1503 ;; Avoid partial register stalls when not using QImode arithmetic
1504 (and (eq_attr "type" "imov")
1505 (and (eq_attr "alternative" "0,1,2")
1506 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1508 (eq (symbol_ref "TARGET_QIMODE_MATH")
1512 (const_string "QI")))])
1514 (define_expand "reload_outqi"
1515 [(parallel [(match_operand:QI 0 "" "=m")
1516 (match_operand:QI 1 "register_operand" "r")
1517 (match_operand:QI 2 "register_operand" "=&q")])]
1521 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1523 if (reg_overlap_mentioned_p (op2, op0))
1525 if (! q_regs_operand (op1, QImode))
1527 emit_insn (gen_movqi (op2, op1));
1530 emit_insn (gen_movqi (op0, op1));
1534 (define_insn "*swapqi"
1535 [(set (match_operand:QI 0 "register_operand" "+r")
1536 (match_operand:QI 1 "register_operand" "+r"))
1541 [(set_attr "type" "imov")
1542 (set_attr "pent_pair" "np")
1543 (set_attr "mode" "QI")
1544 (set_attr "modrm" "0")
1545 (set_attr "ppro_uops" "few")])
1547 (define_expand "movstrictqi"
1548 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1549 (match_operand:QI 1 "general_operand" ""))]
1550 "! TARGET_PARTIAL_REG_STALL"
1552 /* Don't generate memory->memory moves, go through a register. */
1553 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1554 operands[1] = force_reg (QImode, operands[1]);
1557 (define_insn "*movstrictqi_1"
1558 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1559 (match_operand:QI 1 "general_operand" "*qn,m"))]
1560 "! TARGET_PARTIAL_REG_STALL
1561 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1562 "mov{b}\t{%1, %0|%0, %1}"
1563 [(set_attr "type" "imov")
1564 (set_attr "mode" "QI")])
1566 (define_insn "*movstrictqi_xor"
1567 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1568 (match_operand:QI 1 "const0_operand" "i"))
1569 (clobber (reg:CC 17))]
1570 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1571 "xor{b}\t{%0, %0|%0, %0}"
1572 [(set_attr "type" "alu1")
1573 (set_attr "mode" "QI")
1574 (set_attr "length_immediate" "0")])
1576 (define_insn "*movsi_extv_1"
1577 [(set (match_operand:SI 0 "register_operand" "=R")
1578 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1582 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1583 [(set_attr "type" "imovx")
1584 (set_attr "mode" "SI")])
1586 (define_insn "*movhi_extv_1"
1587 [(set (match_operand:HI 0 "register_operand" "=R")
1588 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1592 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1593 [(set_attr "type" "imovx")
1594 (set_attr "mode" "SI")])
1596 (define_insn "*movqi_extv_1"
1597 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1598 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1603 switch (get_attr_type (insn))
1606 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1608 return "mov{b}\t{%h1, %0|%0, %h1}";
1612 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1613 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1614 (ne (symbol_ref "TARGET_MOVX")
1616 (const_string "imovx")
1617 (const_string "imov")))
1619 (if_then_else (eq_attr "type" "imovx")
1621 (const_string "QI")))])
1623 (define_insn "*movqi_extv_1_rex64"
1624 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1625 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1630 switch (get_attr_type (insn))
1633 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1635 return "mov{b}\t{%h1, %0|%0, %h1}";
1639 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1640 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1641 (ne (symbol_ref "TARGET_MOVX")
1643 (const_string "imovx")
1644 (const_string "imov")))
1646 (if_then_else (eq_attr "type" "imovx")
1648 (const_string "QI")))])
1650 ;; Stores and loads of ax to arbitrary constant address.
1651 ;; We fake an second form of instruction to force reload to load address
1652 ;; into register when rax is not available
1653 (define_insn "*movabsqi_1_rex64"
1654 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1655 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
1658 movabs{b}\t{%1, %P0|%P0, %1}
1659 mov{b}\t{%1, %a0|%a0, %1}
1660 movabs{b}\t{%1, %a0|%a0, %1}"
1661 [(set_attr "type" "imov")
1662 (set_attr "modrm" "0,*,*")
1663 (set_attr "length_address" "8,0,0")
1664 (set_attr "length_immediate" "0,*,*")
1665 (set_attr "memory" "store")
1666 (set_attr "mode" "QI")])
1668 (define_insn "*movabsqi_2_rex64"
1669 [(set (match_operand:QI 0 "register_operand" "=a,r")
1670 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1673 movabs{b}\t{%P1, %0|%0, %P1}
1674 mov{b}\t{%a1, %0|%0, %a1}"
1675 [(set_attr "type" "imov")
1676 (set_attr "modrm" "0,*")
1677 (set_attr "length_address" "8,0")
1678 (set_attr "length_immediate" "0")
1679 (set_attr "memory" "load")
1680 (set_attr "mode" "QI")])
1682 (define_insn "*movsi_extzv_1"
1683 [(set (match_operand:SI 0 "register_operand" "=R")
1684 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1688 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1689 [(set_attr "type" "imovx")
1690 (set_attr "mode" "SI")])
1692 (define_insn "*movqi_extzv_2"
1693 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1694 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1699 switch (get_attr_type (insn))
1702 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1704 return "mov{b}\t{%h1, %0|%0, %h1}";
1708 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1709 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1710 (ne (symbol_ref "TARGET_MOVX")
1712 (const_string "imovx")
1713 (const_string "imov")))
1715 (if_then_else (eq_attr "type" "imovx")
1717 (const_string "QI")))])
1719 (define_insn "*movqi_extzv_2_rex64"
1720 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1721 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1726 switch (get_attr_type (insn))
1729 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1731 return "mov{b}\t{%h1, %0|%0, %h1}";
1735 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1736 (ne (symbol_ref "TARGET_MOVX")
1738 (const_string "imovx")
1739 (const_string "imov")))
1741 (if_then_else (eq_attr "type" "imovx")
1743 (const_string "QI")))])
1745 (define_insn "movsi_insv_1"
1746 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1749 (match_operand:SI 1 "general_operand" "Qmn"))]
1751 "mov{b}\t{%b1, %h0|%h0, %b1}"
1752 [(set_attr "type" "imov")
1753 (set_attr "mode" "QI")])
1755 (define_insn "*movsi_insv_1_rex64"
1756 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1759 (match_operand:SI 1 "nonmemory_operand" "Qn"))]
1761 "mov{b}\t{%b1, %h0|%h0, %b1}"
1762 [(set_attr "type" "imov")
1763 (set_attr "mode" "QI")])
1765 (define_insn "*movqi_insv_2"
1766 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1769 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1773 "mov{b}\t{%h1, %h0|%h0, %h1}"
1774 [(set_attr "type" "imov")
1775 (set_attr "mode" "QI")])
1777 (define_expand "movdi"
1778 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1779 (match_operand:DI 1 "general_operand" ""))]
1781 "ix86_expand_move (DImode, operands); DONE;")
1783 (define_insn "*pushdi"
1784 [(set (match_operand:DI 0 "push_operand" "=<")
1785 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1789 (define_insn "pushdi2_rex64"
1790 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1791 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1796 [(set_attr "type" "push,multi")
1797 (set_attr "mode" "DI")])
1799 ;; Convert impossible pushes of immediate to existing instructions.
1800 ;; First try to get scratch register and go through it. In case this
1801 ;; fails, push sign extended lower part first and then overwrite
1802 ;; upper part by 32bit move.
1804 [(match_scratch:DI 2 "r")
1805 (set (match_operand:DI 0 "push_operand" "")
1806 (match_operand:DI 1 "immediate_operand" ""))]
1807 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1808 && !x86_64_immediate_operand (operands[1], DImode)"
1809 [(set (match_dup 2) (match_dup 1))
1810 (set (match_dup 0) (match_dup 2))]
1813 ;; We need to define this as both peepholer and splitter for case
1814 ;; peephole2 pass is not run.
1816 [(set (match_operand:DI 0 "push_operand" "")
1817 (match_operand:DI 1 "immediate_operand" ""))]
1818 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1819 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1820 [(set (match_dup 0) (match_dup 1))
1821 (set (match_dup 2) (match_dup 3))]
1822 "split_di (operands + 1, 1, operands + 2, operands + 3);
1823 operands[1] = gen_lowpart (DImode, operands[2]);
1824 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1829 [(set (match_operand:DI 0 "push_operand" "")
1830 (match_operand:DI 1 "immediate_operand" ""))]
1831 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
1832 && !symbolic_operand (operands[1], DImode)
1833 && !x86_64_immediate_operand (operands[1], DImode)"
1834 [(set (match_dup 0) (match_dup 1))
1835 (set (match_dup 2) (match_dup 3))]
1836 "split_di (operands + 1, 1, operands + 2, operands + 3);
1837 operands[1] = gen_lowpart (DImode, operands[2]);
1838 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1842 (define_insn "*pushdi2_prologue_rex64"
1843 [(set (match_operand:DI 0 "push_operand" "=<")
1844 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1845 (clobber (mem:BLK (scratch)))]
1848 [(set_attr "type" "push")
1849 (set_attr "mode" "DI")])
1851 (define_insn "*popdi1_epilogue_rex64"
1852 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1853 (mem:DI (reg:DI 7)))
1855 (plus:DI (reg:DI 7) (const_int 8)))
1856 (clobber (mem:BLK (scratch)))]
1859 [(set_attr "type" "pop")
1860 (set_attr "mode" "DI")])
1862 (define_insn "popdi1"
1863 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1864 (mem:DI (reg:DI 7)))
1866 (plus:DI (reg:DI 7) (const_int 8)))]
1869 [(set_attr "type" "pop")
1870 (set_attr "mode" "DI")])
1872 (define_insn "*movdi_xor_rex64"
1873 [(set (match_operand:DI 0 "register_operand" "=r")
1874 (match_operand:DI 1 "const0_operand" "i"))
1875 (clobber (reg:CC 17))]
1876 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1877 && reload_completed"
1878 "xor{l}\t{%k0, %k0|%k0, %k0}"
1879 [(set_attr "type" "alu1")
1880 (set_attr "mode" "SI")
1881 (set_attr "length_immediate" "0")])
1883 (define_insn "*movdi_or_rex64"
1884 [(set (match_operand:DI 0 "register_operand" "=r")
1885 (match_operand:DI 1 "const_int_operand" "i"))
1886 (clobber (reg:CC 17))]
1887 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1889 && GET_CODE (operands[1]) == CONST_INT
1890 && INTVAL (operands[1]) == -1"
1892 operands[1] = constm1_rtx;
1893 return "or{q}\t{%1, %0|%0, %1}";
1895 [(set_attr "type" "alu1")
1896 (set_attr "mode" "DI")
1897 (set_attr "length_immediate" "1")])
1899 (define_insn "*movdi_2"
1900 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
1901 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
1903 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1907 movq\t{%1, %0|%0, %1}
1908 movq\t{%1, %0|%0, %1}
1909 movq\t{%1, %0|%0, %1}
1910 movdqa\t{%1, %0|%0, %1}
1911 movq\t{%1, %0|%0, %1}"
1912 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
1913 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
1916 [(set (match_operand:DI 0 "push_operand" "")
1917 (match_operand:DI 1 "general_operand" ""))]
1918 "!TARGET_64BIT && reload_completed
1919 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1921 "ix86_split_long_move (operands); DONE;")
1923 ;; %%% This multiword shite has got to go.
1925 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1926 (match_operand:DI 1 "general_operand" ""))]
1927 "!TARGET_64BIT && reload_completed
1928 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1929 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1931 "ix86_split_long_move (operands); DONE;")
1933 (define_insn "*movdi_1_rex64"
1934 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,!*Y,!m,!*Y")
1935 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*Y,*m"))]
1937 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1939 switch (get_attr_type (insn))
1942 if (register_operand (operands[0], DImode)
1943 && register_operand (operands[1], DImode))
1944 return "movdqa\t{%1, %0|%0, %1}";
1947 return "movq\t{%1, %0|%0, %1}";
1951 return "lea{q}\t{%a1, %0|%0, %a1}";
1953 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1955 if (get_attr_mode (insn) == MODE_SI)
1956 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1957 else if (which_alternative == 2)
1958 return "movabs{q}\t{%1, %0|%0, %1}";
1960 return "mov{q}\t{%1, %0|%0, %1}";
1964 (cond [(eq_attr "alternative" "5,6")
1965 (const_string "mmxmov")
1966 (eq_attr "alternative" "7,8")
1967 (const_string "ssemov")
1968 (eq_attr "alternative" "4")
1969 (const_string "multi")
1970 (and (ne (symbol_ref "flag_pic") (const_int 0))
1971 (match_operand:DI 1 "symbolic_operand" ""))
1972 (const_string "lea")
1974 (const_string "imov")))
1975 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*")
1976 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*")
1977 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")])
1979 ;; Stores and loads of ax to arbitrary constant address.
1980 ;; We fake an second form of instruction to force reload to load address
1981 ;; into register when rax is not available
1982 (define_insn "*movabsdi_1_rex64"
1983 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1984 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
1987 movabs{q}\t{%1, %P0|%P0, %1}
1988 mov{q}\t{%1, %a0|%a0, %1}
1989 movabs{q}\t{%1, %a0|%a0, %1}"
1990 [(set_attr "type" "imov")
1991 (set_attr "modrm" "0,*,*")
1992 (set_attr "length_address" "8,0,0")
1993 (set_attr "length_immediate" "0,*,*")
1994 (set_attr "memory" "store")
1995 (set_attr "mode" "DI")])
1997 (define_insn "*movabsdi_2_rex64"
1998 [(set (match_operand:DI 0 "register_operand" "=a,r")
1999 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2002 movabs{q}\t{%P1, %0|%0, %P1}
2003 mov{q}\t{%a1, %0|%0, %a1}"
2004 [(set_attr "type" "imov")
2005 (set_attr "modrm" "0,*")
2006 (set_attr "length_address" "8,0")
2007 (set_attr "length_immediate" "0")
2008 (set_attr "memory" "load")
2009 (set_attr "mode" "DI")])
2011 ;; Convert impossible stores of immediate to existing instructions.
2012 ;; First try to get scratch register and go through it. In case this
2013 ;; fails, move by 32bit parts.
2015 [(match_scratch:DI 2 "r")
2016 (set (match_operand:DI 0 "memory_operand" "")
2017 (match_operand:DI 1 "immediate_operand" ""))]
2018 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2019 && !x86_64_immediate_operand (operands[1], DImode)"
2020 [(set (match_dup 2) (match_dup 1))
2021 (set (match_dup 0) (match_dup 2))]
2024 ;; We need to define this as both peepholer and splitter for case
2025 ;; peephole2 pass is not run.
2027 [(set (match_operand:DI 0 "memory_operand" "")
2028 (match_operand:DI 1 "immediate_operand" ""))]
2029 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2030 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2031 [(set (match_dup 2) (match_dup 3))
2032 (set (match_dup 4) (match_dup 5))]
2033 "split_di (operands, 2, operands + 2, operands + 4);")
2036 [(set (match_operand:DI 0 "memory_operand" "")
2037 (match_operand:DI 1 "immediate_operand" ""))]
2038 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2039 && !symbolic_operand (operands[1], DImode)
2040 && !x86_64_immediate_operand (operands[1], DImode)"
2041 [(set (match_dup 2) (match_dup 3))
2042 (set (match_dup 4) (match_dup 5))]
2043 "split_di (operands, 2, operands + 2, operands + 4);")
2045 (define_insn "*swapdi_rex64"
2046 [(set (match_operand:DI 0 "register_operand" "+r")
2047 (match_operand:DI 1 "register_operand" "+r"))
2052 [(set_attr "type" "imov")
2053 (set_attr "pent_pair" "np")
2054 (set_attr "athlon_decode" "vector")
2055 (set_attr "mode" "DI")
2056 (set_attr "modrm" "0")
2057 (set_attr "ppro_uops" "few")])
2060 (define_expand "movsf"
2061 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2062 (match_operand:SF 1 "general_operand" ""))]
2064 "ix86_expand_move (SFmode, operands); DONE;")
2066 (define_insn "*pushsf"
2067 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2068 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2071 switch (which_alternative)
2074 return "push{l}\t%1";
2077 /* This insn should be already splitted before reg-stack. */
2081 [(set_attr "type" "multi,push,multi")
2082 (set_attr "mode" "SF,SI,SF")])
2084 (define_insn "*pushsf_rex64"
2085 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2086 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2089 switch (which_alternative)
2092 return "push{q}\t%q1";
2095 /* This insn should be already splitted before reg-stack. */
2099 [(set_attr "type" "multi,push,multi")
2100 (set_attr "mode" "SF,DI,SF")])
2103 [(set (match_operand:SF 0 "push_operand" "")
2104 (match_operand:SF 1 "memory_operand" ""))]
2106 && GET_CODE (operands[1]) == MEM
2107 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2108 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2111 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2114 ;; %%% Kill this when call knows how to work this out.
2116 [(set (match_operand:SF 0 "push_operand" "")
2117 (match_operand:SF 1 "any_fp_register_operand" ""))]
2119 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2120 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2123 [(set (match_operand:SF 0 "push_operand" "")
2124 (match_operand:SF 1 "any_fp_register_operand" ""))]
2126 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2127 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2129 (define_insn "*movsf_1"
2130 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
2131 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,rm,*y,*y"))]
2132 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2133 && (reload_in_progress || reload_completed
2134 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2135 || GET_CODE (operands[1]) != CONST_DOUBLE
2136 || memory_operand (operands[0], SFmode))"
2138 switch (which_alternative)
2141 if (REG_P (operands[1])
2142 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2144 if (REGNO (operands[0]) == FIRST_STACK_REG
2145 && TARGET_USE_FFREEP)
2146 return "ffreep\t%y0";
2149 else if (STACK_TOP_P (operands[0]))
2150 return "fld%z1\t%y1";
2155 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2156 return "fstp%z0\t%y0";
2158 return "fst%z0\t%y0";
2161 switch (standard_80387_constant_p (operands[1]))
2172 return "mov{l}\t{%1, %0|%0, %1}";
2174 if (get_attr_mode (insn) == MODE_TI)
2175 return "pxor\t%0, %0";
2177 return "xorps\t%0, %0";
2179 if (get_attr_mode (insn) == MODE_V4SF)
2180 return "movaps\t{%1, %0|%0, %1}";
2182 return "movss\t{%1, %0|%0, %1}";
2185 return "movss\t{%1, %0|%0, %1}";
2189 return "movd\t{%1, %0|%0, %1}";
2192 return "movq\t{%1, %0|%0, %1}";
2198 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2200 (cond [(eq_attr "alternative" "3,4,9,10")
2202 (eq_attr "alternative" "5")
2204 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2206 (ne (symbol_ref "TARGET_SSE2")
2208 (eq (symbol_ref "optimize_size")
2211 (const_string "V4SF"))
2212 /* For architectures resolving dependencies on
2213 whole SSE registers use APS move to break dependency
2214 chains, otherwise use short move to avoid extra work.
2216 Do the same for architectures resolving dependencies on
2217 the parts. While in DF mode it is better to always handle
2218 just register parts, the SF mode is different due to lack
2219 of instructions to load just part of the register. It is
2220 better to maintain the whole registers in single format
2221 to avoid problems on using packed logical operations. */
2222 (eq_attr "alternative" "6")
2224 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2226 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2228 (const_string "V4SF")
2229 (const_string "SF"))
2230 (eq_attr "alternative" "11")
2231 (const_string "DI")]
2232 (const_string "SF")))])
2234 (define_insn "*swapsf"
2235 [(set (match_operand:SF 0 "register_operand" "+f")
2236 (match_operand:SF 1 "register_operand" "+f"))
2239 "reload_completed || !TARGET_SSE"
2241 if (STACK_TOP_P (operands[0]))
2246 [(set_attr "type" "fxch")
2247 (set_attr "mode" "SF")])
2249 (define_expand "movdf"
2250 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2251 (match_operand:DF 1 "general_operand" ""))]
2253 "ix86_expand_move (DFmode, operands); DONE;")
2255 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2256 ;; Size of pushdf using integer instructions is 2+2*memory operand size
2257 ;; On the average, pushdf using integers can be still shorter. Allow this
2258 ;; pattern for optimize_size too.
2260 (define_insn "*pushdf_nointeger"
2261 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2262 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2263 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2265 /* This insn should be already splitted before reg-stack. */
2268 [(set_attr "type" "multi")
2269 (set_attr "mode" "DF,SI,SI,DF")])
2271 (define_insn "*pushdf_integer"
2272 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2273 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2274 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2276 /* This insn should be already splitted before reg-stack. */
2279 [(set_attr "type" "multi")
2280 (set_attr "mode" "DF,SI,DF")])
2282 ;; %%% Kill this when call knows how to work this out.
2284 [(set (match_operand:DF 0 "push_operand" "")
2285 (match_operand:DF 1 "any_fp_register_operand" ""))]
2286 "!TARGET_64BIT && reload_completed"
2287 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2288 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2292 [(set (match_operand:DF 0 "push_operand" "")
2293 (match_operand:DF 1 "any_fp_register_operand" ""))]
2294 "TARGET_64BIT && reload_completed"
2295 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2296 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2300 [(set (match_operand:DF 0 "push_operand" "")
2301 (match_operand:DF 1 "general_operand" ""))]
2304 "ix86_split_long_move (operands); DONE;")
2306 ;; Moving is usually shorter when only FP registers are used. This separate
2307 ;; movdf pattern avoids the use of integer registers for FP operations
2308 ;; when optimizing for size.
2310 (define_insn "*movdf_nointeger"
2311 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2312 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,C,Y#f,YHm#f,Y#f"))]
2313 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2314 && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
2315 && (reload_in_progress || reload_completed
2316 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2317 || GET_CODE (operands[1]) != CONST_DOUBLE
2318 || memory_operand (operands[0], DFmode))"
2320 switch (which_alternative)
2323 if (REG_P (operands[1])
2324 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2326 if (REGNO (operands[0]) == FIRST_STACK_REG
2327 && TARGET_USE_FFREEP)
2328 return "ffreep\t%y0";
2331 else if (STACK_TOP_P (operands[0]))
2332 return "fld%z1\t%y1";
2337 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2338 return "fstp%z0\t%y0";
2340 return "fst%z0\t%y0";
2343 switch (standard_80387_constant_p (operands[1]))
2356 switch (get_attr_mode (insn))
2359 return "xorps\t%0, %0";
2361 return "xorpd\t%0, %0";
2363 return "pxor\t%0, %0";
2368 switch (get_attr_mode (insn))
2371 return "movaps\t{%1, %0|%0, %1}";
2373 return "movapd\t{%1, %0|%0, %1}";
2375 return "movsd\t{%1, %0|%0, %1}";
2380 if (get_attr_mode (insn) == MODE_V2DF)
2381 return "movlpd\t{%1, %0|%0, %1}";
2383 return "movsd\t{%1, %0|%0, %1}";
2385 return "movsd\t{%1, %0|%0, %1}";
2391 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2393 (cond [(eq_attr "alternative" "3,4")
2395 /* xorps is one byte shorter. */
2396 (eq_attr "alternative" "5")
2397 (cond [(ne (symbol_ref "optimize_size")
2399 (const_string "V4SF")
2400 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2402 (const_string "TI")]
2403 (const_string "V2DF"))
2404 /* For architectures resolving dependencies on
2405 whole SSE registers use APD move to break dependency
2406 chains, otherwise use short move to avoid extra work.
2408 movaps encodes one byte shorter. */
2409 (eq_attr "alternative" "6")
2411 [(ne (symbol_ref "optimize_size")
2413 (const_string "V4SF")
2414 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2416 (const_string "V2DF")]
2417 (const_string "DF"))
2418 /* For architectures resolving dependencies on register
2419 parts we may avoid extra work to zero out upper part
2421 (eq_attr "alternative" "7")
2423 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2425 (const_string "V2DF")
2426 (const_string "DF"))]
2427 (const_string "DF")))])
2429 (define_insn "*movdf_integer"
2430 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2431 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,C,Y#rf,Ym#rf,Y#rf"))]
2432 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2433 && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
2434 && (reload_in_progress || reload_completed
2435 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2436 || GET_CODE (operands[1]) != CONST_DOUBLE
2437 || memory_operand (operands[0], DFmode))"
2439 switch (which_alternative)
2442 if (REG_P (operands[1])
2443 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2445 if (REGNO (operands[0]) == FIRST_STACK_REG
2446 && TARGET_USE_FFREEP)
2447 return "ffreep\t%y0";
2450 else if (STACK_TOP_P (operands[0]))
2451 return "fld%z1\t%y1";
2456 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2457 return "fstp%z0\t%y0";
2459 return "fst%z0\t%y0";
2462 switch (standard_80387_constant_p (operands[1]))
2476 switch (get_attr_mode (insn))
2479 return "xorps\t%0, %0";
2481 return "xorpd\t%0, %0";
2483 return "pxor\t%0, %0";
2488 switch (get_attr_mode (insn))
2491 return "movaps\t{%1, %0|%0, %1}";
2493 return "movapd\t{%1, %0|%0, %1}";
2495 return "movsd\t{%1, %0|%0, %1}";
2500 if (get_attr_mode (insn) == MODE_V2DF)
2501 return "movlpd\t{%1, %0|%0, %1}";
2503 return "movsd\t{%1, %0|%0, %1}";
2505 return "movsd\t{%1, %0|%0, %1}";
2511 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2513 (cond [(eq_attr "alternative" "3,4")
2515 /* xorps is one byte shorter. */
2516 (eq_attr "alternative" "5")
2517 (cond [(ne (symbol_ref "optimize_size")
2519 (const_string "V4SF")
2520 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2522 (const_string "TI")]
2523 (const_string "V2DF"))
2524 /* For architectures resolving dependencies on
2525 whole SSE registers use APD move to break dependency
2526 chains, otherwise use short move to avoid extra work.
2528 movaps encodes one byte shorter. */
2529 (eq_attr "alternative" "6")
2531 [(ne (symbol_ref "optimize_size")
2533 (const_string "V4SF")
2534 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2536 (const_string "V2DF")]
2537 (const_string "DF"))
2538 /* For architectures resolving dependencies on register
2539 parts we may avoid extra work to zero out upper part
2541 (eq_attr "alternative" "7")
2543 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2545 (const_string "V2DF")
2546 (const_string "DF"))]
2547 (const_string "DF")))])
2550 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2551 (match_operand:DF 1 "general_operand" ""))]
2553 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2554 && ! (ANY_FP_REG_P (operands[0]) ||
2555 (GET_CODE (operands[0]) == SUBREG
2556 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2557 && ! (ANY_FP_REG_P (operands[1]) ||
2558 (GET_CODE (operands[1]) == SUBREG
2559 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2561 "ix86_split_long_move (operands); DONE;")
2563 (define_insn "*swapdf"
2564 [(set (match_operand:DF 0 "register_operand" "+f")
2565 (match_operand:DF 1 "register_operand" "+f"))
2568 "reload_completed || !TARGET_SSE2"
2570 if (STACK_TOP_P (operands[0]))
2575 [(set_attr "type" "fxch")
2576 (set_attr "mode" "DF")])
2578 (define_expand "movxf"
2579 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2580 (match_operand:XF 1 "general_operand" ""))]
2582 "ix86_expand_move (XFmode, operands); DONE;")
2584 (define_expand "movtf"
2585 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2586 (match_operand:TF 1 "general_operand" ""))]
2588 "ix86_expand_move (TFmode, operands); DONE;")
2590 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2591 ;; Size of pushdf using integer instructions is 3+3*memory operand size
2592 ;; Pushing using integer instructions is longer except for constants
2593 ;; and direct memory references.
2594 ;; (assuming that any given constant is pushed only once, but this ought to be
2595 ;; handled elsewhere).
2597 (define_insn "*pushxf_nointeger"
2598 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2599 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2600 "!TARGET_64BIT && optimize_size"
2602 /* This insn should be already splitted before reg-stack. */
2605 [(set_attr "type" "multi")
2606 (set_attr "mode" "XF,SI,SI")])
2608 (define_insn "*pushtf_nointeger"
2609 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
2610 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
2613 /* This insn should be already splitted before reg-stack. */
2616 [(set_attr "type" "multi")
2617 (set_attr "mode" "XF,SI,SI")])
2619 (define_insn "*pushxf_integer"
2620 [(set (match_operand:XF 0 "push_operand" "=<,<")
2621 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2622 "!TARGET_64BIT && !optimize_size"
2624 /* This insn should be already splitted before reg-stack. */
2627 [(set_attr "type" "multi")
2628 (set_attr "mode" "XF,SI")])
2630 (define_insn "*pushtf_integer"
2631 [(set (match_operand:TF 0 "push_operand" "=<,<")
2632 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
2635 /* This insn should be already splitted before reg-stack. */
2638 [(set_attr "type" "multi")
2639 (set_attr "mode" "XF,SI")])
2642 [(set (match_operand 0 "push_operand" "")
2643 (match_operand 1 "general_operand" ""))]
2645 && (GET_MODE (operands[0]) == XFmode
2646 || GET_MODE (operands[0]) == TFmode
2647 || GET_MODE (operands[0]) == DFmode)
2648 && !ANY_FP_REG_P (operands[1])"
2650 "ix86_split_long_move (operands); DONE;")
2653 [(set (match_operand:XF 0 "push_operand" "")
2654 (match_operand:XF 1 "any_fp_register_operand" ""))]
2656 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
2657 (set (mem:XF (reg:SI 7)) (match_dup 1))])
2660 [(set (match_operand:TF 0 "push_operand" "")
2661 (match_operand:TF 1 "any_fp_register_operand" ""))]
2663 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
2664 (set (mem:TF (reg:SI 7)) (match_dup 1))])
2667 [(set (match_operand:TF 0 "push_operand" "")
2668 (match_operand:TF 1 "any_fp_register_operand" ""))]
2670 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
2671 (set (mem:TF (reg:DI 7)) (match_dup 1))])
2673 ;; Do not use integer registers when optimizing for size
2674 (define_insn "*movxf_nointeger"
2675 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2676 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2679 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2680 && (reload_in_progress || reload_completed
2681 || GET_CODE (operands[1]) != CONST_DOUBLE
2682 || memory_operand (operands[0], XFmode))"
2684 switch (which_alternative)
2687 if (REG_P (operands[1])
2688 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2690 if (REGNO (operands[0]) == FIRST_STACK_REG
2691 && TARGET_USE_FFREEP)
2692 return "ffreep\t%y0";
2695 else if (STACK_TOP_P (operands[0]))
2696 return "fld%z1\t%y1";
2701 /* There is no non-popping store to memory for XFmode. So if
2702 we need one, follow the store with a load. */
2703 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2704 return "fstp%z0\t%y0\;fld%z0\t%y0";
2706 return "fstp%z0\t%y0";
2709 switch (standard_80387_constant_p (operands[1]))
2723 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2724 (set_attr "mode" "XF,XF,XF,SI,SI")])
2726 (define_insn "*movtf_nointeger"
2727 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2728 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2729 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2731 && (reload_in_progress || reload_completed
2732 || GET_CODE (operands[1]) != CONST_DOUBLE
2733 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2734 || memory_operand (operands[0], TFmode))"
2736 switch (which_alternative)
2739 if (REG_P (operands[1])
2740 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2742 if (REGNO (operands[0]) == FIRST_STACK_REG
2743 && TARGET_USE_FFREEP)
2744 return "ffreep\t%y0";
2747 else if (STACK_TOP_P (operands[0]))
2748 return "fld%z1\t%y1";
2753 /* There is no non-popping store to memory for XFmode. So if
2754 we need one, follow the store with a load. */
2755 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2756 return "fstp%z0\t%y0\;fld%z0\t%y0";
2758 return "fstp%z0\t%y0";
2761 switch (standard_80387_constant_p (operands[1]))
2775 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2776 (set_attr "mode" "XF,XF,XF,SI,SI")])
2778 (define_insn "*movxf_integer"
2779 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2780 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2783 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2784 && (reload_in_progress || reload_completed
2785 || GET_CODE (operands[1]) != CONST_DOUBLE
2786 || memory_operand (operands[0], XFmode))"
2788 switch (which_alternative)
2791 if (REG_P (operands[1])
2792 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2794 if (REGNO (operands[0]) == FIRST_STACK_REG
2795 && TARGET_USE_FFREEP)
2796 return "ffreep\t%y0";
2799 else if (STACK_TOP_P (operands[0]))
2800 return "fld%z1\t%y1";
2805 /* There is no non-popping store to memory for XFmode. So if
2806 we need one, follow the store with a load. */
2807 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2808 return "fstp%z0\t%y0\;fld%z0\t%y0";
2810 return "fstp%z0\t%y0";
2813 switch (standard_80387_constant_p (operands[1]))
2827 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2828 (set_attr "mode" "XF,XF,XF,SI,SI")])
2830 (define_insn "*movtf_integer"
2831 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2832 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2833 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2835 && (reload_in_progress || reload_completed
2836 || GET_CODE (operands[1]) != CONST_DOUBLE
2837 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2838 || memory_operand (operands[0], TFmode))"
2840 switch (which_alternative)
2843 if (REG_P (operands[1])
2844 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2846 if (REGNO (operands[0]) == FIRST_STACK_REG
2847 && TARGET_USE_FFREEP)
2848 return "ffreep\t%y0";
2851 else if (STACK_TOP_P (operands[0]))
2852 return "fld%z1\t%y1";
2857 /* There is no non-popping store to memory for XFmode. So if
2858 we need one, follow the store with a load. */
2859 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2860 return "fstp%z0\t%y0\;fld%z0\t%y0";
2862 return "fstp%z0\t%y0";
2865 switch (standard_80387_constant_p (operands[1]))
2879 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2880 (set_attr "mode" "XF,XF,XF,SI,SI")])
2883 [(set (match_operand 0 "nonimmediate_operand" "")
2884 (match_operand 1 "general_operand" ""))]
2886 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2887 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
2888 && ! (ANY_FP_REG_P (operands[0]) ||
2889 (GET_CODE (operands[0]) == SUBREG
2890 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2891 && ! (ANY_FP_REG_P (operands[1]) ||
2892 (GET_CODE (operands[1]) == SUBREG
2893 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2895 "ix86_split_long_move (operands); DONE;")
2898 [(set (match_operand 0 "register_operand" "")
2899 (match_operand 1 "memory_operand" ""))]
2901 && GET_CODE (operands[1]) == MEM
2902 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
2903 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
2904 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2905 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
2906 && (!(SSE_REG_P (operands[0]) ||
2907 (GET_CODE (operands[0]) == SUBREG
2908 && SSE_REG_P (SUBREG_REG (operands[0]))))
2909 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
2910 && (!(FP_REG_P (operands[0]) ||
2911 (GET_CODE (operands[0]) == SUBREG
2912 && FP_REG_P (SUBREG_REG (operands[0]))))
2913 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
2916 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2918 (define_insn "swapxf"
2919 [(set (match_operand:XF 0 "register_operand" "+f")
2920 (match_operand:XF 1 "register_operand" "+f"))
2925 if (STACK_TOP_P (operands[0]))
2930 [(set_attr "type" "fxch")
2931 (set_attr "mode" "XF")])
2933 (define_insn "swaptf"
2934 [(set (match_operand:TF 0 "register_operand" "+f")
2935 (match_operand:TF 1 "register_operand" "+f"))
2940 if (STACK_TOP_P (operands[0]))
2945 [(set_attr "type" "fxch")
2946 (set_attr "mode" "XF")])
2948 ;; Zero extension instructions
2950 (define_expand "zero_extendhisi2"
2951 [(set (match_operand:SI 0 "register_operand" "")
2952 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
2955 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2957 operands[1] = force_reg (HImode, operands[1]);
2958 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
2963 (define_insn "zero_extendhisi2_and"
2964 [(set (match_operand:SI 0 "register_operand" "=r")
2965 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
2966 (clobber (reg:CC 17))]
2967 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2969 [(set_attr "type" "alu1")
2970 (set_attr "mode" "SI")])
2973 [(set (match_operand:SI 0 "register_operand" "")
2974 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
2975 (clobber (reg:CC 17))]
2976 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2977 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
2978 (clobber (reg:CC 17))])]
2981 (define_insn "*zero_extendhisi2_movzwl"
2982 [(set (match_operand:SI 0 "register_operand" "=r")
2983 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
2984 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2985 "movz{wl|x}\t{%1, %0|%0, %1}"
2986 [(set_attr "type" "imovx")
2987 (set_attr "mode" "SI")])
2989 (define_expand "zero_extendqihi2"
2991 [(set (match_operand:HI 0 "register_operand" "")
2992 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2993 (clobber (reg:CC 17))])]
2997 (define_insn "*zero_extendqihi2_and"
2998 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
2999 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3000 (clobber (reg:CC 17))]
3001 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3003 [(set_attr "type" "alu1")
3004 (set_attr "mode" "HI")])
3006 (define_insn "*zero_extendqihi2_movzbw_and"
3007 [(set (match_operand:HI 0 "register_operand" "=r,r")
3008 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3009 (clobber (reg:CC 17))]
3010 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3012 [(set_attr "type" "imovx,alu1")
3013 (set_attr "mode" "HI")])
3015 (define_insn "*zero_extendqihi2_movzbw"
3016 [(set (match_operand:HI 0 "register_operand" "=r")
3017 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3018 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3019 "movz{bw|x}\t{%1, %0|%0, %1}"
3020 [(set_attr "type" "imovx")
3021 (set_attr "mode" "HI")])
3023 ;; For the movzbw case strip only the clobber
3025 [(set (match_operand:HI 0 "register_operand" "")
3026 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3027 (clobber (reg:CC 17))]
3029 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3030 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3031 [(set (match_operand:HI 0 "register_operand" "")
3032 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3034 ;; When source and destination does not overlap, clear destination
3035 ;; first and then do the movb
3037 [(set (match_operand:HI 0 "register_operand" "")
3038 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3039 (clobber (reg:CC 17))]
3041 && ANY_QI_REG_P (operands[0])
3042 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3043 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3044 [(set (match_dup 0) (const_int 0))
3045 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3046 "operands[2] = gen_lowpart (QImode, operands[0]);")
3048 ;; Rest is handled by single and.
3050 [(set (match_operand:HI 0 "register_operand" "")
3051 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3052 (clobber (reg:CC 17))]
3054 && true_regnum (operands[0]) == true_regnum (operands[1])"
3055 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3056 (clobber (reg:CC 17))])]
3059 (define_expand "zero_extendqisi2"
3061 [(set (match_operand:SI 0 "register_operand" "")
3062 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3063 (clobber (reg:CC 17))])]
3067 (define_insn "*zero_extendqisi2_and"
3068 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3069 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3070 (clobber (reg:CC 17))]
3071 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3073 [(set_attr "type" "alu1")
3074 (set_attr "mode" "SI")])
3076 (define_insn "*zero_extendqisi2_movzbw_and"
3077 [(set (match_operand:SI 0 "register_operand" "=r,r")
3078 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3079 (clobber (reg:CC 17))]
3080 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3082 [(set_attr "type" "imovx,alu1")
3083 (set_attr "mode" "SI")])
3085 (define_insn "*zero_extendqisi2_movzbw"
3086 [(set (match_operand:SI 0 "register_operand" "=r")
3087 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3088 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3089 "movz{bl|x}\t{%1, %0|%0, %1}"
3090 [(set_attr "type" "imovx")
3091 (set_attr "mode" "SI")])
3093 ;; For the movzbl case strip only the clobber
3095 [(set (match_operand:SI 0 "register_operand" "")
3096 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3097 (clobber (reg:CC 17))]
3099 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3100 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3102 (zero_extend:SI (match_dup 1)))])
3104 ;; When source and destination does not overlap, clear destination
3105 ;; first and then do the movb
3107 [(set (match_operand:SI 0 "register_operand" "")
3108 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3109 (clobber (reg:CC 17))]
3111 && ANY_QI_REG_P (operands[0])
3112 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3113 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3114 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3115 [(set (match_dup 0) (const_int 0))
3116 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3117 "operands[2] = gen_lowpart (QImode, operands[0]);")
3119 ;; Rest is handled by single and.
3121 [(set (match_operand:SI 0 "register_operand" "")
3122 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3123 (clobber (reg:CC 17))]
3125 && true_regnum (operands[0]) == true_regnum (operands[1])"
3126 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3127 (clobber (reg:CC 17))])]
3130 ;; %%% Kill me once multi-word ops are sane.
3131 (define_expand "zero_extendsidi2"
3132 [(set (match_operand:DI 0 "register_operand" "=r")
3133 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3137 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3142 (define_insn "zero_extendsidi2_32"
3143 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3144 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
3145 (clobber (reg:CC 17))]
3148 [(set_attr "mode" "SI")])
3150 (define_insn "zero_extendsidi2_rex64"
3151 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
3152 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
3155 mov\t{%k1, %k0|%k0, %k1}
3157 [(set_attr "type" "imovx,imov")
3158 (set_attr "mode" "SI,DI")])
3161 [(set (match_operand:DI 0 "memory_operand" "")
3162 (zero_extend:DI (match_dup 0)))]
3164 [(set (match_dup 4) (const_int 0))]
3165 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3168 [(set (match_operand:DI 0 "register_operand" "")
3169 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3170 (clobber (reg:CC 17))]
3171 "!TARGET_64BIT && reload_completed
3172 && true_regnum (operands[0]) == true_regnum (operands[1])"
3173 [(set (match_dup 4) (const_int 0))]
3174 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3177 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3178 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3179 (clobber (reg:CC 17))]
3180 "!TARGET_64BIT && reload_completed"
3181 [(set (match_dup 3) (match_dup 1))
3182 (set (match_dup 4) (const_int 0))]
3183 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3185 (define_insn "zero_extendhidi2"
3186 [(set (match_operand:DI 0 "register_operand" "=r,r")
3187 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3190 movz{wl|x}\t{%1, %k0|%k0, %1}
3191 movz{wq|x}\t{%1, %0|%0, %1}"
3192 [(set_attr "type" "imovx")
3193 (set_attr "mode" "SI,DI")])
3195 (define_insn "zero_extendqidi2"
3196 [(set (match_operand:DI 0 "register_operand" "=r,r")
3197 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3200 movz{bl|x}\t{%1, %k0|%k0, %1}
3201 movz{bq|x}\t{%1, %0|%0, %1}"
3202 [(set_attr "type" "imovx")
3203 (set_attr "mode" "SI,DI")])
3205 ;; Sign extension instructions
3207 (define_expand "extendsidi2"
3208 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3209 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3210 (clobber (reg:CC 17))
3211 (clobber (match_scratch:SI 2 ""))])]
3216 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3221 (define_insn "*extendsidi2_1"
3222 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3223 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3224 (clobber (reg:CC 17))
3225 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3229 (define_insn "extendsidi2_rex64"
3230 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3231 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3235 movs{lq|x}\t{%1,%0|%0, %1}"
3236 [(set_attr "type" "imovx")
3237 (set_attr "mode" "DI")
3238 (set_attr "prefix_0f" "0")
3239 (set_attr "modrm" "0,1")])
3241 (define_insn "extendhidi2"
3242 [(set (match_operand:DI 0 "register_operand" "=r")
3243 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3245 "movs{wq|x}\t{%1,%0|%0, %1}"
3246 [(set_attr "type" "imovx")
3247 (set_attr "mode" "DI")])
3249 (define_insn "extendqidi2"
3250 [(set (match_operand:DI 0 "register_operand" "=r")
3251 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3253 "movs{bq|x}\t{%1,%0|%0, %1}"
3254 [(set_attr "type" "imovx")
3255 (set_attr "mode" "DI")])
3257 ;; Extend to memory case when source register does die.
3259 [(set (match_operand:DI 0 "memory_operand" "")
3260 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3261 (clobber (reg:CC 17))
3262 (clobber (match_operand:SI 2 "register_operand" ""))]
3264 && dead_or_set_p (insn, operands[1])
3265 && !reg_mentioned_p (operands[1], operands[0]))"
3266 [(set (match_dup 3) (match_dup 1))
3267 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3268 (clobber (reg:CC 17))])
3269 (set (match_dup 4) (match_dup 1))]
3270 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3272 ;; Extend to memory case when source register does not die.
3274 [(set (match_operand:DI 0 "memory_operand" "")
3275 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3276 (clobber (reg:CC 17))
3277 (clobber (match_operand:SI 2 "register_operand" ""))]
3281 split_di (&operands[0], 1, &operands[3], &operands[4]);
3283 emit_move_insn (operands[3], operands[1]);
3285 /* Generate a cltd if possible and doing so it profitable. */
3286 if (true_regnum (operands[1]) == 0
3287 && true_regnum (operands[2]) == 1
3288 && (optimize_size || TARGET_USE_CLTD))
3290 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3294 emit_move_insn (operands[2], operands[1]);
3295 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3297 emit_move_insn (operands[4], operands[2]);
3301 ;; Extend to register case. Optimize case where source and destination
3302 ;; registers match and cases where we can use cltd.
3304 [(set (match_operand:DI 0 "register_operand" "")
3305 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3306 (clobber (reg:CC 17))
3307 (clobber (match_scratch:SI 2 ""))]
3311 split_di (&operands[0], 1, &operands[3], &operands[4]);
3313 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3314 emit_move_insn (operands[3], operands[1]);
3316 /* Generate a cltd if possible and doing so it profitable. */
3317 if (true_regnum (operands[3]) == 0
3318 && (optimize_size || TARGET_USE_CLTD))
3320 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3324 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3325 emit_move_insn (operands[4], operands[1]);
3327 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3331 (define_insn "extendhisi2"
3332 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3333 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3336 switch (get_attr_prefix_0f (insn))
3339 return "{cwtl|cwde}";
3341 return "movs{wl|x}\t{%1,%0|%0, %1}";
3344 [(set_attr "type" "imovx")
3345 (set_attr "mode" "SI")
3346 (set (attr "prefix_0f")
3347 ;; movsx is short decodable while cwtl is vector decoded.
3348 (if_then_else (and (eq_attr "cpu" "!k6")
3349 (eq_attr "alternative" "0"))
3351 (const_string "1")))
3353 (if_then_else (eq_attr "prefix_0f" "0")
3355 (const_string "1")))])
3357 (define_insn "*extendhisi2_zext"
3358 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3360 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3363 switch (get_attr_prefix_0f (insn))
3366 return "{cwtl|cwde}";
3368 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3371 [(set_attr "type" "imovx")
3372 (set_attr "mode" "SI")
3373 (set (attr "prefix_0f")
3374 ;; movsx is short decodable while cwtl is vector decoded.
3375 (if_then_else (and (eq_attr "cpu" "!k6")
3376 (eq_attr "alternative" "0"))
3378 (const_string "1")))
3380 (if_then_else (eq_attr "prefix_0f" "0")
3382 (const_string "1")))])
3384 (define_insn "extendqihi2"
3385 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3386 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3389 switch (get_attr_prefix_0f (insn))
3392 return "{cbtw|cbw}";
3394 return "movs{bw|x}\t{%1,%0|%0, %1}";
3397 [(set_attr "type" "imovx")
3398 (set_attr "mode" "HI")
3399 (set (attr "prefix_0f")
3400 ;; movsx is short decodable while cwtl is vector decoded.
3401 (if_then_else (and (eq_attr "cpu" "!k6")
3402 (eq_attr "alternative" "0"))
3404 (const_string "1")))
3406 (if_then_else (eq_attr "prefix_0f" "0")
3408 (const_string "1")))])
3410 (define_insn "extendqisi2"
3411 [(set (match_operand:SI 0 "register_operand" "=r")
3412 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3414 "movs{bl|x}\t{%1,%0|%0, %1}"
3415 [(set_attr "type" "imovx")
3416 (set_attr "mode" "SI")])
3418 (define_insn "*extendqisi2_zext"
3419 [(set (match_operand:DI 0 "register_operand" "=r")
3421 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3423 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3424 [(set_attr "type" "imovx")
3425 (set_attr "mode" "SI")])
3427 ;; Conversions between float and double.
3429 ;; These are all no-ops in the model used for the 80387. So just
3432 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3433 (define_insn "*dummy_extendsfdf2"
3434 [(set (match_operand:DF 0 "push_operand" "=<")
3435 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3440 [(set (match_operand:DF 0 "push_operand" "")
3441 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3443 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3444 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3447 [(set (match_operand:DF 0 "push_operand" "")
3448 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3450 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3451 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3453 (define_insn "*dummy_extendsfxf2"
3454 [(set (match_operand:XF 0 "push_operand" "=<")
3455 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3460 [(set (match_operand:XF 0 "push_operand" "")
3461 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3463 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3464 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3466 (define_insn "*dummy_extendsftf2"
3467 [(set (match_operand:TF 0 "push_operand" "=<")
3468 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3473 [(set (match_operand:TF 0 "push_operand" "")
3474 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
3476 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3477 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
3480 [(set (match_operand:TF 0 "push_operand" "")
3481 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
3483 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3484 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3486 (define_insn "*dummy_extenddfxf2"
3487 [(set (match_operand:XF 0 "push_operand" "=<")
3488 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3493 [(set (match_operand:XF 0 "push_operand" "")
3494 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3496 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3497 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3499 (define_insn "*dummy_extenddftf2"
3500 [(set (match_operand:TF 0 "push_operand" "=<")
3501 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3506 [(set (match_operand:TF 0 "push_operand" "")
3507 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
3509 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3510 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3513 [(set (match_operand:TF 0 "push_operand" "")
3514 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
3516 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3517 (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3519 (define_expand "extendsfdf2"
3520 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3521 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3522 "TARGET_80387 || TARGET_SSE2"
3524 /* ??? Needed for compress_float_constant since all fp constants
3525 are LEGITIMATE_CONSTANT_P. */
3526 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3527 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3528 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3529 operands[1] = force_reg (SFmode, operands[1]);
3532 (define_insn "*extendsfdf2_1"
3533 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
3534 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3535 "(TARGET_80387 || TARGET_SSE2)
3536 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3538 switch (which_alternative)
3541 if (REG_P (operands[1])
3542 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3544 else if (STACK_TOP_P (operands[0]))
3545 return "fld%z1\t%y1";
3550 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3551 return "fstp%z0\t%y0";
3554 return "fst%z0\t%y0";
3556 return "cvtss2sd\t{%1, %0|%0, %1}";
3562 [(set_attr "type" "fmov,fmov,ssecvt")
3563 (set_attr "mode" "SF,XF,DF")])
3565 (define_insn "*extendsfdf2_1_sse_only"
3566 [(set (match_operand:DF 0 "register_operand" "=Y")
3567 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3568 "!TARGET_80387 && TARGET_SSE2
3569 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3570 "cvtss2sd\t{%1, %0|%0, %1}"
3571 [(set_attr "type" "ssecvt")
3572 (set_attr "mode" "DF")])
3574 (define_expand "extendsfxf2"
3575 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3576 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3577 "!TARGET_64BIT && TARGET_80387"
3579 /* ??? Needed for compress_float_constant since all fp constants
3580 are LEGITIMATE_CONSTANT_P. */
3581 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3582 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3583 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3584 operands[1] = force_reg (SFmode, operands[1]);
3587 (define_insn "*extendsfxf2_1"
3588 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3589 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3590 "!TARGET_64BIT && TARGET_80387
3591 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3593 switch (which_alternative)
3596 if (REG_P (operands[1])
3597 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3599 else if (STACK_TOP_P (operands[0]))
3600 return "fld%z1\t%y1";
3605 /* There is no non-popping store to memory for XFmode. So if
3606 we need one, follow the store with a load. */
3607 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3608 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3610 return "fstp%z0\t%y0";
3616 [(set_attr "type" "fmov")
3617 (set_attr "mode" "SF,XF")])
3619 (define_expand "extendsftf2"
3620 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3621 (float_extend:TF (match_operand:SF 1 "general_operand" "")))]
3624 /* ??? Needed for compress_float_constant since all fp constants
3625 are LEGITIMATE_CONSTANT_P. */
3626 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3627 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3628 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3629 operands[1] = force_reg (SFmode, operands[1]);
3632 (define_insn "*extendsftf2_1"
3633 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3634 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3636 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3638 switch (which_alternative)
3641 if (REG_P (operands[1])
3642 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3644 else if (STACK_TOP_P (operands[0]))
3645 return "fld%z1\t%y1";
3650 /* There is no non-popping store to memory for XFmode. So if
3651 we need one, follow the store with a load. */
3652 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3653 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3655 return "fstp%z0\t%y0";
3661 [(set_attr "type" "fmov")
3662 (set_attr "mode" "SF,XF")])
3664 (define_expand "extenddfxf2"
3665 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3666 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3667 "!TARGET_64BIT && TARGET_80387"
3669 /* ??? Needed for compress_float_constant since all fp constants
3670 are LEGITIMATE_CONSTANT_P. */
3671 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3672 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3673 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3674 operands[1] = force_reg (DFmode, operands[1]);
3677 (define_insn "*extenddfxf2_1"
3678 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3679 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3680 "!TARGET_64BIT && TARGET_80387
3681 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3683 switch (which_alternative)
3686 if (REG_P (operands[1])
3687 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3689 else if (STACK_TOP_P (operands[0]))
3690 return "fld%z1\t%y1";
3695 /* There is no non-popping store to memory for XFmode. So if
3696 we need one, follow the store with a load. */
3697 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3698 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3700 return "fstp%z0\t%y0";
3706 [(set_attr "type" "fmov")
3707 (set_attr "mode" "DF,XF")])
3709 (define_expand "extenddftf2"
3710 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3711 (float_extend:TF (match_operand:DF 1 "general_operand" "")))]
3714 /* ??? Needed for compress_float_constant since all fp constants
3715 are LEGITIMATE_CONSTANT_P. */
3716 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3717 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3718 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3719 operands[1] = force_reg (DFmode, operands[1]);
3722 (define_insn "*extenddftf2_1"
3723 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3724 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3726 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3728 switch (which_alternative)
3731 if (REG_P (operands[1])
3732 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3734 else if (STACK_TOP_P (operands[0]))
3735 return "fld%z1\t%y1";
3740 /* There is no non-popping store to memory for XFmode. So if
3741 we need one, follow the store with a load. */
3742 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3743 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3745 return "fstp%z0\t%y0";
3751 [(set_attr "type" "fmov")
3752 (set_attr "mode" "DF,XF")])
3754 ;; %%% This seems bad bad news.
3755 ;; This cannot output into an f-reg because there is no way to be sure
3756 ;; of truncating in that case. Otherwise this is just like a simple move
3757 ;; insn. So we pretend we can output to a reg in order to get better
3758 ;; register preferencing, but we really use a stack slot.
3760 (define_expand "truncdfsf2"
3761 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3763 (match_operand:DF 1 "register_operand" "")))
3764 (clobber (match_dup 2))])]
3765 "TARGET_80387 || TARGET_SSE2"
3768 operands[2] = assign_386_stack_local (SFmode, 0);
3771 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3776 (define_insn "*truncdfsf2_1"
3777 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3779 (match_operand:DF 1 "register_operand" "f,f,f,f")))
3780 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3781 "TARGET_80387 && !TARGET_SSE2"
3783 switch (which_alternative)
3786 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3787 return "fstp%z0\t%y0";
3789 return "fst%z0\t%y0";
3794 [(set_attr "type" "fmov,multi,multi,multi")
3795 (set_attr "mode" "SF,SF,SF,SF")])
3797 (define_insn "*truncdfsf2_1_sse"
3798 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m#fxr,?f#xr,?r#fx,?x#fr,Y#fr")
3800 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3801 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3802 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3804 switch (which_alternative)
3807 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3808 return "fstp%z0\t%y0";
3810 return "fst%z0\t%y0";
3817 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3818 (set_attr "mode" "SF,SF,SF,SF,DF")])
3820 (define_insn "*truncdfsf2_1_sse_nooverlap"
3821 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,&Y")
3823 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3824 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3825 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3827 switch (which_alternative)
3830 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3831 return "fstp%z0\t%y0";
3833 return "fst%z0\t%y0";
3840 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3841 (set_attr "mode" "SF,SF,SF,SF,DF")])
3843 (define_insn "*truncdfsf2_2"
3844 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,Y,!m")
3846 (match_operand:DF 1 "nonimmediate_operand" "Y,mY,f#Y")))]
3847 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3848 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3850 switch (which_alternative)
3854 return "cvtsd2ss\t{%1, %0|%0, %1}";
3856 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3857 return "fstp%z0\t%y0";
3859 return "fst%z0\t%y0";
3864 [(set_attr "type" "ssecvt,ssecvt,fmov")
3865 (set_attr "athlon_decode" "vector,double,*")
3866 (set_attr "mode" "DF,DF,SF")])
3868 (define_insn "*truncdfsf2_2_nooverlap"
3869 [(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m")
3871 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
3872 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3873 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3875 switch (which_alternative)
3880 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3881 return "fstp%z0\t%y0";
3883 return "fst%z0\t%y0";
3888 [(set_attr "type" "ssecvt,fmov")
3889 (set_attr "mode" "DF,SF")])
3891 (define_insn "*truncdfsf2_3"
3892 [(set (match_operand:SF 0 "memory_operand" "=m")
3894 (match_operand:DF 1 "register_operand" "f")))]
3897 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3898 return "fstp%z0\t%y0";
3900 return "fst%z0\t%y0";
3902 [(set_attr "type" "fmov")
3903 (set_attr "mode" "SF")])
3905 (define_insn "truncdfsf2_sse_only"
3906 [(set (match_operand:SF 0 "register_operand" "=Y,Y")
3908 (match_operand:DF 1 "nonimmediate_operand" "Y,mY")))]
3909 "!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3910 "cvtsd2ss\t{%1, %0|%0, %1}"
3911 [(set_attr "type" "ssecvt")
3912 (set_attr "athlon_decode" "vector,double")
3913 (set_attr "mode" "DF")])
3915 (define_insn "*truncdfsf2_sse_only_nooverlap"
3916 [(set (match_operand:SF 0 "register_operand" "=&Y")
3918 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
3919 "!TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3921 [(set_attr "type" "ssecvt")
3922 (set_attr "mode" "DF")])
3925 [(set (match_operand:SF 0 "memory_operand" "")
3927 (match_operand:DF 1 "register_operand" "")))
3928 (clobber (match_operand:SF 2 "memory_operand" ""))]
3930 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3933 ; Avoid possible reformatting penalty on the destination by first
3936 [(set (match_operand:SF 0 "register_operand" "")
3938 (match_operand:DF 1 "nonimmediate_operand" "")))
3939 (clobber (match_operand 2 "" ""))]
3940 "TARGET_80387 && reload_completed
3941 && SSE_REG_P (operands[0])
3942 && !STACK_REG_P (operands[1])"
3946 if (!TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS)
3947 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3950 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
3951 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
3952 /* simplify_gen_subreg refuses to widen memory references. */
3953 if (GET_CODE (src) == SUBREG)
3954 alter_subreg (&src);
3955 if (reg_overlap_mentioned_p (operands[0], operands[1]))
3957 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
3958 emit_insn (gen_cvtsd2ss (dest, dest, src));
3964 [(set (match_operand:SF 0 "register_operand" "")
3966 (match_operand:DF 1 "nonimmediate_operand" "")))]
3967 "TARGET_80387 && reload_completed
3968 && SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3972 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
3973 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
3974 /* simplify_gen_subreg refuses to widen memory references. */
3975 if (GET_CODE (src) == SUBREG)
3976 alter_subreg (&src);
3977 if (reg_overlap_mentioned_p (operands[0], operands[1]))
3979 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
3980 emit_insn (gen_cvtsd2ss (dest, dest, src));
3985 [(set (match_operand:SF 0 "register_operand" "")
3987 (match_operand:DF 1 "fp_register_operand" "")))
3988 (clobber (match_operand:SF 2 "memory_operand" ""))]
3989 "TARGET_80387 && reload_completed"
3990 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3991 (set (match_dup 0) (match_dup 2))]
3994 (define_expand "truncxfsf2"
3995 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3997 (match_operand:XF 1 "register_operand" "")))
3998 (clobber (match_dup 2))])]
3999 "!TARGET_64BIT && TARGET_80387"
4000 "operands[2] = assign_386_stack_local (SFmode, 0);")
4002 (define_insn "*truncxfsf2_1"
4003 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4005 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4006 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4007 "!TARGET_64BIT && TARGET_80387"
4009 switch (which_alternative)
4012 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4013 return "fstp%z0\t%y0";
4015 return "fst%z0\t%y0";
4020 [(set_attr "type" "fmov,multi,multi,multi")
4021 (set_attr "mode" "SF")])
4023 (define_insn "*truncxfsf2_2"
4024 [(set (match_operand:SF 0 "memory_operand" "=m")
4026 (match_operand:XF 1 "register_operand" "f")))]
4027 "!TARGET_64BIT && TARGET_80387"
4029 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4030 return "fstp%z0\t%y0";
4032 return "fst%z0\t%y0";
4034 [(set_attr "type" "fmov")
4035 (set_attr "mode" "SF")])
4038 [(set (match_operand:SF 0 "memory_operand" "")
4040 (match_operand:XF 1 "register_operand" "")))
4041 (clobber (match_operand:SF 2 "memory_operand" ""))]
4043 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4047 [(set (match_operand:SF 0 "register_operand" "")
4049 (match_operand:XF 1 "register_operand" "")))
4050 (clobber (match_operand:SF 2 "memory_operand" ""))]
4051 "TARGET_80387 && reload_completed"
4052 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4053 (set (match_dup 0) (match_dup 2))]
4056 (define_expand "trunctfsf2"
4057 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4059 (match_operand:TF 1 "register_operand" "")))
4060 (clobber (match_dup 2))])]
4062 "operands[2] = assign_386_stack_local (SFmode, 0);")
4064 (define_insn "*trunctfsf2_1"
4065 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4067 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4068 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4071 switch (which_alternative)
4074 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4075 return "fstp%z0\t%y0";
4077 return "fst%z0\t%y0";
4082 [(set_attr "type" "fmov,multi,multi,multi")
4083 (set_attr "mode" "SF")])
4085 (define_insn "*trunctfsf2_2"
4086 [(set (match_operand:SF 0 "memory_operand" "=m")
4088 (match_operand:TF 1 "register_operand" "f")))]
4091 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4092 return "fstp%z0\t%y0";
4094 return "fst%z0\t%y0";
4096 [(set_attr "type" "fmov")
4097 (set_attr "mode" "SF")])
4100 [(set (match_operand:SF 0 "memory_operand" "")
4102 (match_operand:TF 1 "register_operand" "")))
4103 (clobber (match_operand:SF 2 "memory_operand" ""))]
4105 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4109 [(set (match_operand:SF 0 "register_operand" "")
4111 (match_operand:TF 1 "register_operand" "")))
4112 (clobber (match_operand:SF 2 "memory_operand" ""))]
4113 "TARGET_80387 && reload_completed"
4114 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4115 (set (match_dup 0) (match_dup 2))]
4119 (define_expand "truncxfdf2"
4120 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4122 (match_operand:XF 1 "register_operand" "")))
4123 (clobber (match_dup 2))])]
4124 "!TARGET_64BIT && TARGET_80387"
4125 "operands[2] = assign_386_stack_local (DFmode, 0);")
4127 (define_insn "*truncxfdf2_1"
4128 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4130 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4131 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4132 "!TARGET_64BIT && TARGET_80387"
4134 switch (which_alternative)
4137 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4138 return "fstp%z0\t%y0";
4140 return "fst%z0\t%y0";
4146 [(set_attr "type" "fmov,multi,multi,multi")
4147 (set_attr "mode" "DF")])
4149 (define_insn "*truncxfdf2_2"
4150 [(set (match_operand:DF 0 "memory_operand" "=m")
4152 (match_operand:XF 1 "register_operand" "f")))]
4153 "!TARGET_64BIT && TARGET_80387"
4155 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4156 return "fstp%z0\t%y0";
4158 return "fst%z0\t%y0";
4160 [(set_attr "type" "fmov")
4161 (set_attr "mode" "DF")])
4164 [(set (match_operand:DF 0 "memory_operand" "")
4166 (match_operand:XF 1 "register_operand" "")))
4167 (clobber (match_operand:DF 2 "memory_operand" ""))]
4169 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4173 [(set (match_operand:DF 0 "register_operand" "")
4175 (match_operand:XF 1 "register_operand" "")))
4176 (clobber (match_operand:DF 2 "memory_operand" ""))]
4177 "TARGET_80387 && reload_completed"
4178 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4179 (set (match_dup 0) (match_dup 2))]
4182 (define_expand "trunctfdf2"
4183 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4185 (match_operand:TF 1 "register_operand" "")))
4186 (clobber (match_dup 2))])]
4188 "operands[2] = assign_386_stack_local (DFmode, 0);")
4190 (define_insn "*trunctfdf2_1"
4191 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4193 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4194 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4197 switch (which_alternative)
4200 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4201 return "fstp%z0\t%y0";
4203 return "fst%z0\t%y0";
4209 [(set_attr "type" "fmov,multi,multi,multi")
4210 (set_attr "mode" "DF")])
4212 (define_insn "*trunctfdf2_2"
4213 [(set (match_operand:DF 0 "memory_operand" "=m")
4215 (match_operand:TF 1 "register_operand" "f")))]
4218 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4219 return "fstp%z0\t%y0";
4221 return "fst%z0\t%y0";
4223 [(set_attr "type" "fmov")
4224 (set_attr "mode" "DF")])
4227 [(set (match_operand:DF 0 "memory_operand" "")
4229 (match_operand:TF 1 "register_operand" "")))
4230 (clobber (match_operand:DF 2 "memory_operand" ""))]
4232 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4236 [(set (match_operand:DF 0 "register_operand" "")
4238 (match_operand:TF 1 "register_operand" "")))
4239 (clobber (match_operand:DF 2 "memory_operand" ""))]
4240 "TARGET_80387 && reload_completed"
4241 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4242 (set (match_dup 0) (match_dup 2))]
4246 ;; %%% Break up all these bad boys.
4248 ;; Signed conversion to DImode.
4250 (define_expand "fix_truncxfdi2"
4251 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4252 (fix:DI (match_operand:XF 1 "register_operand" "")))]
4253 "!TARGET_64BIT && TARGET_80387"
4256 (define_expand "fix_trunctfdi2"
4257 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4258 (fix:DI (match_operand:TF 1 "register_operand" "")))]
4262 (define_expand "fix_truncdfdi2"
4263 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4264 (fix:DI (match_operand:DF 1 "register_operand" "")))]
4265 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4267 if (TARGET_64BIT && TARGET_SSE2)
4269 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4270 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4271 if (out != operands[0])
4272 emit_move_insn (operands[0], out);
4277 (define_expand "fix_truncsfdi2"
4278 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4279 (fix:DI (match_operand:SF 1 "register_operand" "")))]
4280 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4282 if (TARGET_SSE && TARGET_64BIT)
4284 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4285 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4286 if (out != operands[0])
4287 emit_move_insn (operands[0], out);
4292 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4293 ;; of the machinery.
4294 (define_insn_and_split "*fix_truncdi_1"
4295 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4296 (fix:DI (match_operand 1 "register_operand" "f,f")))]
4297 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4298 && !reload_completed && !reload_in_progress
4299 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4304 operands[2] = assign_386_stack_local (HImode, 1);
4305 operands[3] = assign_386_stack_local (HImode, 2);
4306 if (memory_operand (operands[0], VOIDmode))
4307 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4308 operands[2], operands[3]));
4311 operands[4] = assign_386_stack_local (DImode, 0);
4312 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4313 operands[2], operands[3],
4318 [(set_attr "type" "fistp")])
4320 (define_insn "fix_truncdi_nomemory"
4321 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4322 (fix:DI (match_operand 1 "register_operand" "f,f")))
4323 (use (match_operand:HI 2 "memory_operand" "m,m"))
4324 (use (match_operand:HI 3 "memory_operand" "m,m"))
4325 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4326 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4327 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4328 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4330 [(set_attr "type" "fistp")])
4332 (define_insn "fix_truncdi_memory"
4333 [(set (match_operand:DI 0 "memory_operand" "=m")
4334 (fix:DI (match_operand 1 "register_operand" "f")))
4335 (use (match_operand:HI 2 "memory_operand" "m"))
4336 (use (match_operand:HI 3 "memory_operand" "m"))
4337 (clobber (match_scratch:DF 4 "=&1f"))]
4338 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4339 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4340 "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);"
4341 [(set_attr "type" "fistp")])
4344 [(set (match_operand:DI 0 "register_operand" "")
4345 (fix:DI (match_operand 1 "register_operand" "")))
4346 (use (match_operand:HI 2 "memory_operand" ""))
4347 (use (match_operand:HI 3 "memory_operand" ""))
4348 (clobber (match_operand:DI 4 "memory_operand" ""))
4349 (clobber (match_scratch 5 ""))]
4351 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4354 (clobber (match_dup 5))])
4355 (set (match_dup 0) (match_dup 4))]
4359 [(set (match_operand:DI 0 "memory_operand" "")
4360 (fix:DI (match_operand 1 "register_operand" "")))
4361 (use (match_operand:HI 2 "memory_operand" ""))
4362 (use (match_operand:HI 3 "memory_operand" ""))
4363 (clobber (match_operand:DI 4 "memory_operand" ""))
4364 (clobber (match_scratch 5 ""))]
4366 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4369 (clobber (match_dup 5))])]
4372 ;; When SSE available, it is always faster to use it!
4373 (define_insn "fix_truncsfdi_sse"
4374 [(set (match_operand:DI 0 "register_operand" "=r,r")
4375 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4376 "TARGET_64BIT && TARGET_SSE"
4377 "cvttss2si{q}\t{%1, %0|%0, %1}"
4378 [(set_attr "type" "sseicvt")
4379 (set_attr "athlon_decode" "double,vector")])
4381 (define_insn "fix_truncdfdi_sse"
4382 [(set (match_operand:DI 0 "register_operand" "=r,r")
4383 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4384 "TARGET_64BIT && TARGET_SSE2"
4385 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4386 [(set_attr "type" "sseicvt,sseicvt")
4387 (set_attr "athlon_decode" "double,vector")])
4389 ;; Signed conversion to SImode.
4391 (define_expand "fix_truncxfsi2"
4392 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4393 (fix:SI (match_operand:XF 1 "register_operand" "")))]
4394 "!TARGET_64BIT && TARGET_80387"
4397 (define_expand "fix_trunctfsi2"
4398 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4399 (fix:SI (match_operand:TF 1 "register_operand" "")))]
4403 (define_expand "fix_truncdfsi2"
4404 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4405 (fix:SI (match_operand:DF 1 "register_operand" "")))]
4406 "TARGET_80387 || TARGET_SSE2"
4410 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4411 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4412 if (out != operands[0])
4413 emit_move_insn (operands[0], out);
4418 (define_expand "fix_truncsfsi2"
4419 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4420 (fix:SI (match_operand:SF 1 "register_operand" "")))]
4421 "TARGET_80387 || TARGET_SSE"
4425 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4426 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4427 if (out != operands[0])
4428 emit_move_insn (operands[0], out);
4433 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4434 ;; of the machinery.
4435 (define_insn_and_split "*fix_truncsi_1"
4436 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4437 (fix:SI (match_operand 1 "register_operand" "f,f")))]
4438 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4439 && !reload_completed && !reload_in_progress
4440 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4445 operands[2] = assign_386_stack_local (HImode, 1);
4446 operands[3] = assign_386_stack_local (HImode, 2);
4447 if (memory_operand (operands[0], VOIDmode))
4448 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4449 operands[2], operands[3]));
4452 operands[4] = assign_386_stack_local (SImode, 0);
4453 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4454 operands[2], operands[3],
4459 [(set_attr "type" "fistp")])
4461 (define_insn "fix_truncsi_nomemory"
4462 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4463 (fix:SI (match_operand 1 "register_operand" "f,f")))
4464 (use (match_operand:HI 2 "memory_operand" "m,m"))
4465 (use (match_operand:HI 3 "memory_operand" "m,m"))
4466 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4467 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4468 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4470 [(set_attr "type" "fistp")])
4472 (define_insn "fix_truncsi_memory"
4473 [(set (match_operand:SI 0 "memory_operand" "=m")
4474 (fix:SI (match_operand 1 "register_operand" "f")))
4475 (use (match_operand:HI 2 "memory_operand" "m"))
4476 (use (match_operand:HI 3 "memory_operand" "m"))]
4477 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4478 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4479 "* return output_fix_trunc (insn, operands);"
4480 [(set_attr "type" "fistp")])
4482 ;; When SSE available, it is always faster to use it!
4483 (define_insn "fix_truncsfsi_sse"
4484 [(set (match_operand:SI 0 "register_operand" "=r,r")
4485 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4487 "cvttss2si\t{%1, %0|%0, %1}"
4488 [(set_attr "type" "sseicvt")
4489 (set_attr "athlon_decode" "double,vector")])
4491 (define_insn "fix_truncdfsi_sse"
4492 [(set (match_operand:SI 0 "register_operand" "=r,r")
4493 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4495 "cvttsd2si\t{%1, %0|%0, %1}"
4496 [(set_attr "type" "sseicvt")
4497 (set_attr "athlon_decode" "double,vector")])
4500 [(set (match_operand:SI 0 "register_operand" "")
4501 (fix:SI (match_operand 1 "register_operand" "")))
4502 (use (match_operand:HI 2 "memory_operand" ""))
4503 (use (match_operand:HI 3 "memory_operand" ""))
4504 (clobber (match_operand:SI 4 "memory_operand" ""))]
4506 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4508 (use (match_dup 3))])
4509 (set (match_dup 0) (match_dup 4))]
4513 [(set (match_operand:SI 0 "memory_operand" "")
4514 (fix:SI (match_operand 1 "register_operand" "")))
4515 (use (match_operand:HI 2 "memory_operand" ""))
4516 (use (match_operand:HI 3 "memory_operand" ""))
4517 (clobber (match_operand:SI 4 "memory_operand" ""))]
4519 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4521 (use (match_dup 3))])]
4524 ;; Signed conversion to HImode.
4526 (define_expand "fix_truncxfhi2"
4527 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4528 (fix:HI (match_operand:XF 1 "register_operand" "")))]
4529 "!TARGET_64BIT && TARGET_80387"
4532 (define_expand "fix_trunctfhi2"
4533 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4534 (fix:HI (match_operand:TF 1 "register_operand" "")))]
4538 (define_expand "fix_truncdfhi2"
4539 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4540 (fix:HI (match_operand:DF 1 "register_operand" "")))]
4541 "TARGET_80387 && !TARGET_SSE2"
4544 (define_expand "fix_truncsfhi2"
4545 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4546 (fix:HI (match_operand:SF 1 "register_operand" "")))]
4547 "TARGET_80387 && !TARGET_SSE"
4550 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4551 ;; of the machinery.
4552 (define_insn_and_split "*fix_trunchi_1"
4553 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4554 (fix:HI (match_operand 1 "register_operand" "f,f")))]
4555 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4556 && !reload_completed && !reload_in_progress
4557 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4562 operands[2] = assign_386_stack_local (HImode, 1);
4563 operands[3] = assign_386_stack_local (HImode, 2);
4564 if (memory_operand (operands[0], VOIDmode))
4565 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4566 operands[2], operands[3]));
4569 operands[4] = assign_386_stack_local (HImode, 0);
4570 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4571 operands[2], operands[3],
4576 [(set_attr "type" "fistp")])
4578 (define_insn "fix_trunchi_nomemory"
4579 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4580 (fix:HI (match_operand 1 "register_operand" "f,f")))
4581 (use (match_operand:HI 2 "memory_operand" "m,m"))
4582 (use (match_operand:HI 3 "memory_operand" "m,m"))
4583 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4584 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4585 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4587 [(set_attr "type" "fistp")])
4589 (define_insn "fix_trunchi_memory"
4590 [(set (match_operand:HI 0 "memory_operand" "=m")
4591 (fix:HI (match_operand 1 "register_operand" "f")))
4592 (use (match_operand:HI 2 "memory_operand" "m"))
4593 (use (match_operand:HI 3 "memory_operand" "m"))]
4594 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4595 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4596 "* return output_fix_trunc (insn, operands);"
4597 [(set_attr "type" "fistp")])
4600 [(set (match_operand:HI 0 "memory_operand" "")
4601 (fix:HI (match_operand 1 "register_operand" "")))
4602 (use (match_operand:HI 2 "memory_operand" ""))
4603 (use (match_operand:HI 3 "memory_operand" ""))
4604 (clobber (match_operand:HI 4 "memory_operand" ""))]
4606 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4608 (use (match_dup 3))])]
4612 [(set (match_operand:HI 0 "register_operand" "")
4613 (fix:HI (match_operand 1 "register_operand" "")))
4614 (use (match_operand:HI 2 "memory_operand" ""))
4615 (use (match_operand:HI 3 "memory_operand" ""))
4616 (clobber (match_operand:HI 4 "memory_operand" ""))]
4618 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4621 (clobber (match_dup 4))])
4622 (set (match_dup 0) (match_dup 4))]
4626 (define_insn "x86_fnstcw_1"
4627 [(set (match_operand:HI 0 "memory_operand" "=m")
4628 (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))]
4631 [(set_attr "length" "2")
4632 (set_attr "mode" "HI")
4633 (set_attr "unit" "i387")
4634 (set_attr "ppro_uops" "few")])
4636 (define_insn "x86_fldcw_1"
4638 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4641 [(set_attr "length" "2")
4642 (set_attr "mode" "HI")
4643 (set_attr "unit" "i387")
4644 (set_attr "athlon_decode" "vector")
4645 (set_attr "ppro_uops" "few")])
4647 ;; Conversion between fixed point and floating point.
4649 ;; Even though we only accept memory inputs, the backend _really_
4650 ;; wants to be able to do this between registers.
4652 (define_insn "floathisf2"
4653 [(set (match_operand:SF 0 "register_operand" "=f,f")
4654 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4655 "TARGET_80387 && !TARGET_SSE"
4659 [(set_attr "type" "fmov,multi")
4660 (set_attr "mode" "SF")
4661 (set_attr "fp_int_src" "true")])
4663 (define_expand "floatsisf2"
4664 [(set (match_operand:SF 0 "register_operand" "")
4665 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4666 "TARGET_SSE || TARGET_80387"
4669 (define_insn "*floatsisf2_i387"
4670 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4671 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4672 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4676 cvtsi2ss\t{%1, %0|%0, %1}
4677 cvtsi2ss\t{%1, %0|%0, %1}"
4678 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4679 (set_attr "mode" "SF")
4680 (set_attr "athlon_decode" "*,*,vector,double")
4681 (set_attr "fp_int_src" "true")])
4683 (define_insn "*floatsisf2_sse"
4684 [(set (match_operand:SF 0 "register_operand" "=x,x")
4685 (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4687 "cvtsi2ss\t{%1, %0|%0, %1}"
4688 [(set_attr "type" "sseicvt")
4689 (set_attr "mode" "SF")
4690 (set_attr "athlon_decode" "vector,double")
4691 (set_attr "fp_int_src" "true")])
4693 ; Avoid possible reformatting penalty on the destination by first
4696 [(set (match_operand:SF 0 "register_operand" "")
4697 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4698 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4699 && SSE_REG_P (operands[0])"
4703 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4704 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4705 emit_insn (gen_cvtsi2ss (dest, dest, operands[1]));
4709 (define_expand "floatdisf2"
4710 [(set (match_operand:SF 0 "register_operand" "")
4711 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4712 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
4715 (define_insn "*floatdisf2_i387_only"
4716 [(set (match_operand:SF 0 "register_operand" "=f,?f")
4717 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4718 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
4722 [(set_attr "type" "fmov,multi")
4723 (set_attr "mode" "SF")
4724 (set_attr "fp_int_src" "true")])
4726 (define_insn "*floatdisf2_i387"
4727 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4728 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4729 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4733 cvtsi2ss{q}\t{%1, %0|%0, %1}
4734 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4735 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4736 (set_attr "mode" "SF")
4737 (set_attr "athlon_decode" "*,*,vector,double")
4738 (set_attr "fp_int_src" "true")])
4740 (define_insn "*floatdisf2_sse"
4741 [(set (match_operand:SF 0 "register_operand" "=x,x")
4742 (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4743 "TARGET_64BIT && TARGET_SSE"
4744 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4745 [(set_attr "type" "sseicvt")
4746 (set_attr "mode" "SF")
4747 (set_attr "athlon_decode" "vector,double")
4748 (set_attr "fp_int_src" "true")])
4750 ; Avoid possible reformatting penalty on the destination by first
4753 [(set (match_operand:SF 0 "register_operand" "")
4754 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4755 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4756 && SSE_REG_P (operands[0])"
4760 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4761 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4762 emit_insn (gen_cvtsi2ssq (dest, dest, operands[1]));
4766 (define_insn "floathidf2"
4767 [(set (match_operand:DF 0 "register_operand" "=f,f")
4768 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4769 "TARGET_80387 && !TARGET_SSE2"
4773 [(set_attr "type" "fmov,multi")
4774 (set_attr "mode" "DF")
4775 (set_attr "fp_int_src" "true")])
4777 (define_expand "floatsidf2"
4778 [(set (match_operand:DF 0 "register_operand" "")
4779 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4780 "TARGET_80387 || TARGET_SSE2"
4783 (define_insn "*floatsidf2_i387"
4784 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4785 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4786 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4790 cvtsi2sd\t{%1, %0|%0, %1}
4791 cvtsi2sd\t{%1, %0|%0, %1}"
4792 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4793 (set_attr "mode" "DF")
4794 (set_attr "athlon_decode" "*,*,double,direct")
4795 (set_attr "fp_int_src" "true")])
4797 (define_insn "*floatsidf2_sse"
4798 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4799 (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4801 "cvtsi2sd\t{%1, %0|%0, %1}"
4802 [(set_attr "type" "sseicvt")
4803 (set_attr "mode" "DF")
4804 (set_attr "athlon_decode" "double,direct")
4805 (set_attr "fp_int_src" "true")])
4807 (define_expand "floatdidf2"
4808 [(set (match_operand:DF 0 "register_operand" "")
4809 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
4810 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
4813 (define_insn "*floatdidf2_i387_only"
4814 [(set (match_operand:DF 0 "register_operand" "=f,?f")
4815 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4816 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
4820 [(set_attr "type" "fmov,multi")
4821 (set_attr "mode" "DF")
4822 (set_attr "fp_int_src" "true")])
4824 (define_insn "*floatdidf2_i387"
4825 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4826 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4827 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4831 cvtsi2sd{q}\t{%1, %0|%0, %1}
4832 cvtsi2sd{q}\t{%1, %0|%0, %1}"
4833 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4834 (set_attr "mode" "DF")
4835 (set_attr "athlon_decode" "*,*,double,direct")
4836 (set_attr "fp_int_src" "true")])
4838 (define_insn "*floatdidf2_sse"
4839 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4840 (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4842 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
4843 [(set_attr "type" "sseicvt")
4844 (set_attr "mode" "DF")
4845 (set_attr "athlon_decode" "double,direct")
4846 (set_attr "fp_int_src" "true")])
4848 (define_insn "floathixf2"
4849 [(set (match_operand:XF 0 "register_operand" "=f,f")
4850 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4851 "!TARGET_64BIT && TARGET_80387"
4855 [(set_attr "type" "fmov,multi")
4856 (set_attr "mode" "XF")
4857 (set_attr "fp_int_src" "true")])
4859 (define_insn "floathitf2"
4860 [(set (match_operand:TF 0 "register_operand" "=f,f")
4861 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4866 [(set_attr "type" "fmov,multi")
4867 (set_attr "mode" "XF")
4868 (set_attr "fp_int_src" "true")])
4870 (define_insn "floatsixf2"
4871 [(set (match_operand:XF 0 "register_operand" "=f,f")
4872 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
4873 "!TARGET_64BIT && TARGET_80387"
4877 [(set_attr "type" "fmov,multi")
4878 (set_attr "mode" "XF")
4879 (set_attr "fp_int_src" "true")])
4881 (define_insn "floatsitf2"
4882 [(set (match_operand:TF 0 "register_operand" "=f,f")
4883 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
4888 [(set_attr "type" "fmov,multi")
4889 (set_attr "mode" "XF")
4890 (set_attr "fp_int_src" "true")])
4892 (define_insn "floatdixf2"
4893 [(set (match_operand:XF 0 "register_operand" "=f,f")
4894 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4895 "!TARGET_64BIT && TARGET_80387"
4899 [(set_attr "type" "fmov,multi")
4900 (set_attr "mode" "XF")
4901 (set_attr "fp_int_src" "true")])
4903 (define_insn "floatditf2"
4904 [(set (match_operand:TF 0 "register_operand" "=f,f")
4905 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4910 [(set_attr "type" "fmov,multi")
4911 (set_attr "mode" "XF")
4912 (set_attr "fp_int_src" "true")])
4914 ;; %%% Kill these when reload knows how to do it.
4916 [(set (match_operand 0 "fp_register_operand" "")
4917 (float (match_operand 1 "register_operand" "")))]
4918 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
4921 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
4922 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
4923 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
4924 ix86_free_from_memory (GET_MODE (operands[1]));
4928 (define_expand "floatunssisf2"
4929 [(use (match_operand:SF 0 "register_operand" ""))
4930 (use (match_operand:SI 1 "register_operand" ""))]
4931 "TARGET_SSE && TARGET_SSE_MATH && !TARGET_64BIT"
4932 "x86_emit_floatuns (operands); DONE;")
4934 (define_expand "floatunsdisf2"
4935 [(use (match_operand:SF 0 "register_operand" ""))
4936 (use (match_operand:DI 1 "register_operand" ""))]
4937 "TARGET_SSE && TARGET_SSE_MATH && TARGET_64BIT"
4938 "x86_emit_floatuns (operands); DONE;")
4940 (define_expand "floatunsdidf2"
4941 [(use (match_operand:DF 0 "register_operand" ""))
4942 (use (match_operand:DI 1 "register_operand" ""))]
4943 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_64BIT"
4944 "x86_emit_floatuns (operands); DONE;")
4948 ;; %%% splits for addsidi3
4949 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
4950 ; (plus:DI (match_operand:DI 1 "general_operand" "")
4951 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
4953 (define_expand "adddi3"
4954 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4955 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4956 (match_operand:DI 2 "x86_64_general_operand" "")))
4957 (clobber (reg:CC 17))]
4959 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
4961 (define_insn "*adddi3_1"
4962 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
4963 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4964 (match_operand:DI 2 "general_operand" "roiF,riF")))
4965 (clobber (reg:CC 17))]
4966 "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4970 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4971 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4972 (match_operand:DI 2 "general_operand" "")))
4973 (clobber (reg:CC 17))]
4974 "!TARGET_64BIT && reload_completed"
4975 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)]
4977 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
4978 (parallel [(set (match_dup 3)
4979 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
4982 (clobber (reg:CC 17))])]
4983 "split_di (operands+0, 1, operands+0, operands+3);
4984 split_di (operands+1, 1, operands+1, operands+4);
4985 split_di (operands+2, 1, operands+2, operands+5);")
4987 (define_insn "adddi3_carry_rex64"
4988 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4989 (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
4990 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
4991 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
4992 (clobber (reg:CC 17))]
4993 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4994 "adc{q}\t{%2, %0|%0, %2}"
4995 [(set_attr "type" "alu")
4996 (set_attr "pent_pair" "pu")
4997 (set_attr "mode" "DI")
4998 (set_attr "ppro_uops" "few")])
5000 (define_insn "*adddi3_cc_rex64"
5002 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
5003 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
5005 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5006 (plus:DI (match_dup 1) (match_dup 2)))]
5007 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5008 "add{q}\t{%2, %0|%0, %2}"
5009 [(set_attr "type" "alu")
5010 (set_attr "mode" "DI")])
5012 (define_insn "addqi3_carry"
5013 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm,r")
5014 (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
5015 (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
5016 (match_operand:QI 2 "general_operand" "ri,rm")))
5017 (clobber (reg:CC 17))]
5018 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5019 "adc{b}\t{%2, %0|%0, %2}"
5020 [(set_attr "type" "alu")
5021 (set_attr "pent_pair" "pu")
5022 (set_attr "mode" "QI")
5023 (set_attr "ppro_uops" "few")])
5025 (define_insn "addhi3_carry"
5026 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5027 (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
5028 (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
5029 (match_operand:HI 2 "general_operand" "ri,rm")))
5030 (clobber (reg:CC 17))]
5031 "ix86_binary_operator_ok (PLUS, HImode, operands)"
5032 "adc{w}\t{%2, %0|%0, %2}"
5033 [(set_attr "type" "alu")
5034 (set_attr "pent_pair" "pu")
5035 (set_attr "mode" "HI")
5036 (set_attr "ppro_uops" "few")])
5038 (define_insn "addsi3_carry"
5039 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5040 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5041 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5042 (match_operand:SI 2 "general_operand" "ri,rm")))
5043 (clobber (reg:CC 17))]
5044 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5045 "adc{l}\t{%2, %0|%0, %2}"
5046 [(set_attr "type" "alu")
5047 (set_attr "pent_pair" "pu")
5048 (set_attr "mode" "SI")
5049 (set_attr "ppro_uops" "few")])
5051 (define_insn "*addsi3_carry_zext"
5052 [(set (match_operand:DI 0 "register_operand" "=r")
5054 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5055 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5056 (match_operand:SI 2 "general_operand" "rim"))))
5057 (clobber (reg:CC 17))]
5058 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5059 "adc{l}\t{%2, %k0|%k0, %2}"
5060 [(set_attr "type" "alu")
5061 (set_attr "pent_pair" "pu")
5062 (set_attr "mode" "SI")
5063 (set_attr "ppro_uops" "few")])
5065 (define_insn "*addsi3_cc"
5067 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5068 (match_operand:SI 2 "general_operand" "ri,rm")]
5070 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5071 (plus:SI (match_dup 1) (match_dup 2)))]
5072 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5073 "add{l}\t{%2, %0|%0, %2}"
5074 [(set_attr "type" "alu")
5075 (set_attr "mode" "SI")])
5077 (define_insn "addqi3_cc"
5079 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5080 (match_operand:QI 2 "general_operand" "qi,qm")]
5082 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5083 (plus:QI (match_dup 1) (match_dup 2)))]
5084 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5085 "add{b}\t{%2, %0|%0, %2}"
5086 [(set_attr "type" "alu")
5087 (set_attr "mode" "QI")])
5089 (define_expand "addsi3"
5090 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5091 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5092 (match_operand:SI 2 "general_operand" "")))
5093 (clobber (reg:CC 17))])]
5095 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5097 (define_insn "*lea_1"
5098 [(set (match_operand:SI 0 "register_operand" "=r")
5099 (match_operand:SI 1 "address_operand" "p"))]
5101 "lea{l}\t{%a1, %0|%0, %a1}"
5102 [(set_attr "type" "lea")
5103 (set_attr "mode" "SI")])
5105 (define_insn "*lea_1_rex64"
5106 [(set (match_operand:SI 0 "register_operand" "=r")
5107 (subreg:SI (match_operand:DI 1 "address_operand" "p") 0))]
5109 "lea{l}\t{%a1, %0|%0, %a1}"
5110 [(set_attr "type" "lea")
5111 (set_attr "mode" "SI")])
5113 (define_insn "*lea_1_zext"
5114 [(set (match_operand:DI 0 "register_operand" "=r")
5115 (zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))]
5117 "lea{l}\t{%a1, %k0|%k0, %a1}"
5118 [(set_attr "type" "lea")
5119 (set_attr "mode" "SI")])
5121 (define_insn "*lea_2_rex64"
5122 [(set (match_operand:DI 0 "register_operand" "=r")
5123 (match_operand:DI 1 "address_operand" "p"))]
5125 "lea{q}\t{%a1, %0|%0, %a1}"
5126 [(set_attr "type" "lea")
5127 (set_attr "mode" "DI")])
5129 ;; The lea patterns for non-Pmodes needs to be matched by several
5130 ;; insns converted to real lea by splitters.
5132 (define_insn_and_split "*lea_general_1"
5133 [(set (match_operand 0 "register_operand" "=r")
5134 (plus (plus (match_operand 1 "index_register_operand" "r")
5135 (match_operand 2 "register_operand" "r"))
5136 (match_operand 3 "immediate_operand" "i")))]
5137 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5138 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5139 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5140 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5141 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5142 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5143 || GET_MODE (operands[3]) == VOIDmode)"
5145 "&& reload_completed"
5149 operands[0] = gen_lowpart (SImode, operands[0]);
5150 operands[1] = gen_lowpart (Pmode, operands[1]);
5151 operands[2] = gen_lowpart (Pmode, operands[2]);
5152 operands[3] = gen_lowpart (Pmode, operands[3]);
5153 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5155 if (Pmode != SImode)
5156 pat = gen_rtx_SUBREG (SImode, pat, 0);
5157 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5160 [(set_attr "type" "lea")
5161 (set_attr "mode" "SI")])
5163 (define_insn_and_split "*lea_general_1_zext"
5164 [(set (match_operand:DI 0 "register_operand" "=r")
5166 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r")
5167 (match_operand:SI 2 "register_operand" "r"))
5168 (match_operand:SI 3 "immediate_operand" "i"))))]
5171 "&& reload_completed"
5173 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5175 (match_dup 3)) 0)))]
5177 operands[1] = gen_lowpart (Pmode, operands[1]);
5178 operands[2] = gen_lowpart (Pmode, operands[2]);
5179 operands[3] = gen_lowpart (Pmode, operands[3]);
5181 [(set_attr "type" "lea")
5182 (set_attr "mode" "SI")])
5184 (define_insn_and_split "*lea_general_2"
5185 [(set (match_operand 0 "register_operand" "=r")
5186 (plus (mult (match_operand 1 "index_register_operand" "r")
5187 (match_operand 2 "const248_operand" "i"))
5188 (match_operand 3 "nonmemory_operand" "ri")))]
5189 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5190 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5191 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5192 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5193 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5194 || GET_MODE (operands[3]) == VOIDmode)"
5196 "&& reload_completed"
5200 operands[0] = gen_lowpart (SImode, operands[0]);
5201 operands[1] = gen_lowpart (Pmode, operands[1]);
5202 operands[3] = gen_lowpart (Pmode, operands[3]);
5203 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5205 if (Pmode != SImode)
5206 pat = gen_rtx_SUBREG (SImode, pat, 0);
5207 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5210 [(set_attr "type" "lea")
5211 (set_attr "mode" "SI")])
5213 (define_insn_and_split "*lea_general_2_zext"
5214 [(set (match_operand:DI 0 "register_operand" "=r")
5216 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5217 (match_operand:SI 2 "const248_operand" "n"))
5218 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5221 "&& reload_completed"
5223 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5225 (match_dup 3)) 0)))]
5227 operands[1] = gen_lowpart (Pmode, operands[1]);
5228 operands[3] = gen_lowpart (Pmode, operands[3]);
5230 [(set_attr "type" "lea")
5231 (set_attr "mode" "SI")])
5233 (define_insn_and_split "*lea_general_3"
5234 [(set (match_operand 0 "register_operand" "=r")
5235 (plus (plus (mult (match_operand 1 "index_register_operand" "r")
5236 (match_operand 2 "const248_operand" "i"))
5237 (match_operand 3 "register_operand" "r"))
5238 (match_operand 4 "immediate_operand" "i")))]
5239 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5240 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5241 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5242 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5243 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5245 "&& reload_completed"
5249 operands[0] = gen_lowpart (SImode, operands[0]);
5250 operands[1] = gen_lowpart (Pmode, operands[1]);
5251 operands[3] = gen_lowpart (Pmode, operands[3]);
5252 operands[4] = gen_lowpart (Pmode, operands[4]);
5253 pat = gen_rtx_PLUS (Pmode,
5254 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5258 if (Pmode != SImode)
5259 pat = gen_rtx_SUBREG (SImode, pat, 0);
5260 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5263 [(set_attr "type" "lea")
5264 (set_attr "mode" "SI")])
5266 (define_insn_and_split "*lea_general_3_zext"
5267 [(set (match_operand:DI 0 "register_operand" "=r")
5269 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5270 (match_operand:SI 2 "const248_operand" "n"))
5271 (match_operand:SI 3 "register_operand" "r"))
5272 (match_operand:SI 4 "immediate_operand" "i"))))]
5275 "&& reload_completed"
5277 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5280 (match_dup 4)) 0)))]
5282 operands[1] = gen_lowpart (Pmode, operands[1]);
5283 operands[3] = gen_lowpart (Pmode, operands[3]);
5284 operands[4] = gen_lowpart (Pmode, operands[4]);
5286 [(set_attr "type" "lea")
5287 (set_attr "mode" "SI")])
5289 (define_insn "*adddi_1_rex64"
5290 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5291 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5292 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5293 (clobber (reg:CC 17))]
5294 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5296 switch (get_attr_type (insn))
5299 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5300 return "lea{q}\t{%a2, %0|%0, %a2}";
5303 if (! rtx_equal_p (operands[0], operands[1]))
5305 if (operands[2] == const1_rtx)
5306 return "inc{q}\t%0";
5307 else if (operands[2] == constm1_rtx)
5308 return "dec{q}\t%0";
5313 if (! rtx_equal_p (operands[0], operands[1]))
5316 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5317 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5318 if (GET_CODE (operands[2]) == CONST_INT
5319 /* Avoid overflows. */
5320 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5321 && (INTVAL (operands[2]) == 128
5322 || (INTVAL (operands[2]) < 0
5323 && INTVAL (operands[2]) != -128)))
5325 operands[2] = GEN_INT (-INTVAL (operands[2]));
5326 return "sub{q}\t{%2, %0|%0, %2}";
5328 return "add{q}\t{%2, %0|%0, %2}";
5332 (cond [(eq_attr "alternative" "2")
5333 (const_string "lea")
5334 ; Current assemblers are broken and do not allow @GOTOFF in
5335 ; ought but a memory context.
5336 (match_operand:DI 2 "pic_symbolic_operand" "")
5337 (const_string "lea")
5338 (match_operand:DI 2 "incdec_operand" "")
5339 (const_string "incdec")
5341 (const_string "alu")))
5342 (set_attr "mode" "DI")])
5344 ;; Convert lea to the lea pattern to avoid flags dependency.
5346 [(set (match_operand:DI 0 "register_operand" "")
5347 (plus:DI (match_operand:DI 1 "register_operand" "")
5348 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5349 (clobber (reg:CC 17))]
5350 "TARGET_64BIT && reload_completed
5351 && true_regnum (operands[0]) != true_regnum (operands[1])"
5353 (plus:DI (match_dup 1)
5357 (define_insn "*adddi_2_rex64"
5360 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5361 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5363 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5364 (plus:DI (match_dup 1) (match_dup 2)))]
5365 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5366 && ix86_binary_operator_ok (PLUS, DImode, operands)
5367 /* Current assemblers are broken and do not allow @GOTOFF in
5368 ought but a memory context. */
5369 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5371 switch (get_attr_type (insn))
5374 if (! rtx_equal_p (operands[0], operands[1]))
5376 if (operands[2] == const1_rtx)
5377 return "inc{q}\t%0";
5378 else if (operands[2] == constm1_rtx)
5379 return "dec{q}\t%0";
5384 if (! rtx_equal_p (operands[0], operands[1]))
5386 /* ???? We ought to handle there the 32bit case too
5387 - do we need new constraint? */
5388 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5389 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5390 if (GET_CODE (operands[2]) == CONST_INT
5391 /* Avoid overflows. */
5392 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5393 && (INTVAL (operands[2]) == 128
5394 || (INTVAL (operands[2]) < 0
5395 && INTVAL (operands[2]) != -128)))
5397 operands[2] = GEN_INT (-INTVAL (operands[2]));
5398 return "sub{q}\t{%2, %0|%0, %2}";
5400 return "add{q}\t{%2, %0|%0, %2}";
5404 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5405 (const_string "incdec")
5406 (const_string "alu")))
5407 (set_attr "mode" "DI")])
5409 (define_insn "*adddi_3_rex64"
5411 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5412 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5413 (clobber (match_scratch:DI 0 "=r"))]
5415 && ix86_match_ccmode (insn, CCZmode)
5416 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5417 /* Current assemblers are broken and do not allow @GOTOFF in
5418 ought but a memory context. */
5419 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5421 switch (get_attr_type (insn))
5424 if (! rtx_equal_p (operands[0], operands[1]))
5426 if (operands[2] == const1_rtx)
5427 return "inc{q}\t%0";
5428 else if (operands[2] == constm1_rtx)
5429 return "dec{q}\t%0";
5434 if (! rtx_equal_p (operands[0], operands[1]))
5436 /* ???? We ought to handle there the 32bit case too
5437 - do we need new constraint? */
5438 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5439 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5440 if (GET_CODE (operands[2]) == CONST_INT
5441 /* Avoid overflows. */
5442 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5443 && (INTVAL (operands[2]) == 128
5444 || (INTVAL (operands[2]) < 0
5445 && INTVAL (operands[2]) != -128)))
5447 operands[2] = GEN_INT (-INTVAL (operands[2]));
5448 return "sub{q}\t{%2, %0|%0, %2}";
5450 return "add{q}\t{%2, %0|%0, %2}";
5454 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5455 (const_string "incdec")
5456 (const_string "alu")))
5457 (set_attr "mode" "DI")])
5459 ; For comparisons against 1, -1 and 128, we may generate better code
5460 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5461 ; is matched then. We can't accept general immediate, because for
5462 ; case of overflows, the result is messed up.
5463 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5465 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5466 ; only for comparisons not depending on it.
5467 (define_insn "*adddi_4_rex64"
5469 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5470 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5471 (clobber (match_scratch:DI 0 "=rm"))]
5473 && ix86_match_ccmode (insn, CCGCmode)"
5475 switch (get_attr_type (insn))
5478 if (operands[2] == constm1_rtx)
5479 return "inc{q}\t%0";
5480 else if (operands[2] == const1_rtx)
5481 return "dec{q}\t%0";
5486 if (! rtx_equal_p (operands[0], operands[1]))
5488 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5489 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5490 if ((INTVAL (operands[2]) == -128
5491 || (INTVAL (operands[2]) > 0
5492 && INTVAL (operands[2]) != 128))
5493 /* Avoid overflows. */
5494 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5495 return "sub{q}\t{%2, %0|%0, %2}";
5496 operands[2] = GEN_INT (-INTVAL (operands[2]));
5497 return "add{q}\t{%2, %0|%0, %2}";
5501 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5502 (const_string "incdec")
5503 (const_string "alu")))
5504 (set_attr "mode" "DI")])
5506 (define_insn "*adddi_5_rex64"
5509 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5510 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5512 (clobber (match_scratch:DI 0 "=r"))]
5514 && ix86_match_ccmode (insn, CCGOCmode)
5515 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5516 /* Current assemblers are broken and do not allow @GOTOFF in
5517 ought but a memory context. */
5518 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5520 switch (get_attr_type (insn))
5523 if (! rtx_equal_p (operands[0], operands[1]))
5525 if (operands[2] == const1_rtx)
5526 return "inc{q}\t%0";
5527 else if (operands[2] == constm1_rtx)
5528 return "dec{q}\t%0";
5533 if (! rtx_equal_p (operands[0], operands[1]))
5535 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5536 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5537 if (GET_CODE (operands[2]) == CONST_INT
5538 /* Avoid overflows. */
5539 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5540 && (INTVAL (operands[2]) == 128
5541 || (INTVAL (operands[2]) < 0
5542 && INTVAL (operands[2]) != -128)))
5544 operands[2] = GEN_INT (-INTVAL (operands[2]));
5545 return "sub{q}\t{%2, %0|%0, %2}";
5547 return "add{q}\t{%2, %0|%0, %2}";
5551 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5552 (const_string "incdec")
5553 (const_string "alu")))
5554 (set_attr "mode" "DI")])
5557 (define_insn "*addsi_1"
5558 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5559 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5560 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5561 (clobber (reg:CC 17))]
5562 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5564 switch (get_attr_type (insn))
5567 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5568 return "lea{l}\t{%a2, %0|%0, %a2}";
5571 if (! rtx_equal_p (operands[0], operands[1]))
5573 if (operands[2] == const1_rtx)
5574 return "inc{l}\t%0";
5575 else if (operands[2] == constm1_rtx)
5576 return "dec{l}\t%0";
5581 if (! rtx_equal_p (operands[0], operands[1]))
5584 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5585 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5586 if (GET_CODE (operands[2]) == CONST_INT
5587 && (INTVAL (operands[2]) == 128
5588 || (INTVAL (operands[2]) < 0
5589 && INTVAL (operands[2]) != -128)))
5591 operands[2] = GEN_INT (-INTVAL (operands[2]));
5592 return "sub{l}\t{%2, %0|%0, %2}";
5594 return "add{l}\t{%2, %0|%0, %2}";
5598 (cond [(eq_attr "alternative" "2")
5599 (const_string "lea")
5600 ; Current assemblers are broken and do not allow @GOTOFF in
5601 ; ought but a memory context.
5602 (match_operand:SI 2 "pic_symbolic_operand" "")
5603 (const_string "lea")
5604 (match_operand:SI 2 "incdec_operand" "")
5605 (const_string "incdec")
5607 (const_string "alu")))
5608 (set_attr "mode" "SI")])
5610 ;; Convert lea to the lea pattern to avoid flags dependency.
5612 [(set (match_operand 0 "register_operand" "")
5613 (plus (match_operand 1 "register_operand" "")
5614 (match_operand 2 "nonmemory_operand" "")))
5615 (clobber (reg:CC 17))]
5617 && true_regnum (operands[0]) != true_regnum (operands[1])"
5621 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5622 may confuse gen_lowpart. */
5623 if (GET_MODE (operands[0]) != Pmode)
5625 operands[1] = gen_lowpart (Pmode, operands[1]);
5626 operands[2] = gen_lowpart (Pmode, operands[2]);
5628 operands[0] = gen_lowpart (SImode, operands[0]);
5629 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5630 if (Pmode != SImode)
5631 pat = gen_rtx_SUBREG (SImode, pat, 0);
5632 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5636 ;; It may seem that nonimmediate operand is proper one for operand 1.
5637 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5638 ;; we take care in ix86_binary_operator_ok to not allow two memory
5639 ;; operands so proper swapping will be done in reload. This allow
5640 ;; patterns constructed from addsi_1 to match.
5641 (define_insn "addsi_1_zext"
5642 [(set (match_operand:DI 0 "register_operand" "=r,r")
5644 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5645 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5646 (clobber (reg:CC 17))]
5647 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5649 switch (get_attr_type (insn))
5652 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5653 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5656 if (operands[2] == const1_rtx)
5657 return "inc{l}\t%k0";
5658 else if (operands[2] == constm1_rtx)
5659 return "dec{l}\t%k0";
5664 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5665 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5666 if (GET_CODE (operands[2]) == CONST_INT
5667 && (INTVAL (operands[2]) == 128
5668 || (INTVAL (operands[2]) < 0
5669 && INTVAL (operands[2]) != -128)))
5671 operands[2] = GEN_INT (-INTVAL (operands[2]));
5672 return "sub{l}\t{%2, %k0|%k0, %2}";
5674 return "add{l}\t{%2, %k0|%k0, %2}";
5678 (cond [(eq_attr "alternative" "1")
5679 (const_string "lea")
5680 ; Current assemblers are broken and do not allow @GOTOFF in
5681 ; ought but a memory context.
5682 (match_operand:SI 2 "pic_symbolic_operand" "")
5683 (const_string "lea")
5684 (match_operand:SI 2 "incdec_operand" "")
5685 (const_string "incdec")
5687 (const_string "alu")))
5688 (set_attr "mode" "SI")])
5690 ;; Convert lea to the lea pattern to avoid flags dependency.
5692 [(set (match_operand:DI 0 "register_operand" "")
5694 (plus:SI (match_operand:SI 1 "register_operand" "")
5695 (match_operand:SI 2 "nonmemory_operand" ""))))
5696 (clobber (reg:CC 17))]
5697 "TARGET_64BIT && reload_completed
5698 && true_regnum (operands[0]) != true_regnum (operands[1])"
5700 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5702 operands[1] = gen_lowpart (Pmode, operands[1]);
5703 operands[2] = gen_lowpart (Pmode, operands[2]);
5706 (define_insn "*addsi_2"
5709 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5710 (match_operand:SI 2 "general_operand" "rmni,rni"))
5712 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5713 (plus:SI (match_dup 1) (match_dup 2)))]
5714 "ix86_match_ccmode (insn, CCGOCmode)
5715 && ix86_binary_operator_ok (PLUS, SImode, operands)
5716 /* Current assemblers are broken and do not allow @GOTOFF in
5717 ought but a memory context. */
5718 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5720 switch (get_attr_type (insn))
5723 if (! rtx_equal_p (operands[0], operands[1]))
5725 if (operands[2] == const1_rtx)
5726 return "inc{l}\t%0";
5727 else if (operands[2] == constm1_rtx)
5728 return "dec{l}\t%0";
5733 if (! rtx_equal_p (operands[0], operands[1]))
5735 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5736 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5737 if (GET_CODE (operands[2]) == CONST_INT
5738 && (INTVAL (operands[2]) == 128
5739 || (INTVAL (operands[2]) < 0
5740 && INTVAL (operands[2]) != -128)))
5742 operands[2] = GEN_INT (-INTVAL (operands[2]));
5743 return "sub{l}\t{%2, %0|%0, %2}";
5745 return "add{l}\t{%2, %0|%0, %2}";
5749 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5750 (const_string "incdec")
5751 (const_string "alu")))
5752 (set_attr "mode" "SI")])
5754 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5755 (define_insn "*addsi_2_zext"
5758 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5759 (match_operand:SI 2 "general_operand" "rmni"))
5761 (set (match_operand:DI 0 "register_operand" "=r")
5762 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5763 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5764 && ix86_binary_operator_ok (PLUS, SImode, operands)
5765 /* Current assemblers are broken and do not allow @GOTOFF in
5766 ought but a memory context. */
5767 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5769 switch (get_attr_type (insn))
5772 if (operands[2] == const1_rtx)
5773 return "inc{l}\t%k0";
5774 else if (operands[2] == constm1_rtx)
5775 return "dec{l}\t%k0";
5780 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5781 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5782 if (GET_CODE (operands[2]) == CONST_INT
5783 && (INTVAL (operands[2]) == 128
5784 || (INTVAL (operands[2]) < 0
5785 && INTVAL (operands[2]) != -128)))
5787 operands[2] = GEN_INT (-INTVAL (operands[2]));
5788 return "sub{l}\t{%2, %k0|%k0, %2}";
5790 return "add{l}\t{%2, %k0|%k0, %2}";
5794 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5795 (const_string "incdec")
5796 (const_string "alu")))
5797 (set_attr "mode" "SI")])
5799 (define_insn "*addsi_3"
5801 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5802 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5803 (clobber (match_scratch:SI 0 "=r"))]
5804 "ix86_match_ccmode (insn, CCZmode)
5805 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5806 /* Current assemblers are broken and do not allow @GOTOFF in
5807 ought but a memory context. */
5808 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5810 switch (get_attr_type (insn))
5813 if (! rtx_equal_p (operands[0], operands[1]))
5815 if (operands[2] == const1_rtx)
5816 return "inc{l}\t%0";
5817 else if (operands[2] == constm1_rtx)
5818 return "dec{l}\t%0";
5823 if (! rtx_equal_p (operands[0], operands[1]))
5825 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5826 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5827 if (GET_CODE (operands[2]) == CONST_INT
5828 && (INTVAL (operands[2]) == 128
5829 || (INTVAL (operands[2]) < 0
5830 && INTVAL (operands[2]) != -128)))
5832 operands[2] = GEN_INT (-INTVAL (operands[2]));
5833 return "sub{l}\t{%2, %0|%0, %2}";
5835 return "add{l}\t{%2, %0|%0, %2}";
5839 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5840 (const_string "incdec")
5841 (const_string "alu")))
5842 (set_attr "mode" "SI")])
5844 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5845 (define_insn "*addsi_3_zext"
5847 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5848 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5849 (set (match_operand:DI 0 "register_operand" "=r")
5850 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5851 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
5852 && ix86_binary_operator_ok (PLUS, SImode, operands)
5853 /* Current assemblers are broken and do not allow @GOTOFF in
5854 ought but a memory context. */
5855 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5857 switch (get_attr_type (insn))
5860 if (operands[2] == const1_rtx)
5861 return "inc{l}\t%k0";
5862 else if (operands[2] == constm1_rtx)
5863 return "dec{l}\t%k0";
5868 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5869 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5870 if (GET_CODE (operands[2]) == CONST_INT
5871 && (INTVAL (operands[2]) == 128
5872 || (INTVAL (operands[2]) < 0
5873 && INTVAL (operands[2]) != -128)))
5875 operands[2] = GEN_INT (-INTVAL (operands[2]));
5876 return "sub{l}\t{%2, %k0|%k0, %2}";
5878 return "add{l}\t{%2, %k0|%k0, %2}";
5882 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5883 (const_string "incdec")
5884 (const_string "alu")))
5885 (set_attr "mode" "SI")])
5887 ; For comparisons against 1, -1 and 128, we may generate better code
5888 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5889 ; is matched then. We can't accept general immediate, because for
5890 ; case of overflows, the result is messed up.
5891 ; This pattern also don't hold of 0x80000000, since the value overflows
5893 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5894 ; only for comparisons not depending on it.
5895 (define_insn "*addsi_4"
5897 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
5898 (match_operand:SI 2 "const_int_operand" "n")))
5899 (clobber (match_scratch:SI 0 "=rm"))]
5900 "ix86_match_ccmode (insn, CCGCmode)
5901 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
5903 switch (get_attr_type (insn))
5906 if (operands[2] == constm1_rtx)
5907 return "inc{l}\t%0";
5908 else if (operands[2] == const1_rtx)
5909 return "dec{l}\t%0";
5914 if (! rtx_equal_p (operands[0], operands[1]))
5916 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5917 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5918 if ((INTVAL (operands[2]) == -128
5919 || (INTVAL (operands[2]) > 0
5920 && INTVAL (operands[2]) != 128)))
5921 return "sub{l}\t{%2, %0|%0, %2}";
5922 operands[2] = GEN_INT (-INTVAL (operands[2]));
5923 return "add{l}\t{%2, %0|%0, %2}";
5927 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5928 (const_string "incdec")
5929 (const_string "alu")))
5930 (set_attr "mode" "SI")])
5932 (define_insn "*addsi_5"
5935 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5936 (match_operand:SI 2 "general_operand" "rmni"))
5938 (clobber (match_scratch:SI 0 "=r"))]
5939 "ix86_match_ccmode (insn, CCGOCmode)
5940 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5941 /* Current assemblers are broken and do not allow @GOTOFF in
5942 ought but a memory context. */
5943 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5945 switch (get_attr_type (insn))
5948 if (! rtx_equal_p (operands[0], operands[1]))
5950 if (operands[2] == const1_rtx)
5951 return "inc{l}\t%0";
5952 else if (operands[2] == constm1_rtx)
5953 return "dec{l}\t%0";
5958 if (! rtx_equal_p (operands[0], operands[1]))
5960 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5961 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5962 if (GET_CODE (operands[2]) == CONST_INT
5963 && (INTVAL (operands[2]) == 128
5964 || (INTVAL (operands[2]) < 0
5965 && INTVAL (operands[2]) != -128)))
5967 operands[2] = GEN_INT (-INTVAL (operands[2]));
5968 return "sub{l}\t{%2, %0|%0, %2}";
5970 return "add{l}\t{%2, %0|%0, %2}";
5974 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5975 (const_string "incdec")
5976 (const_string "alu")))
5977 (set_attr "mode" "SI")])
5979 (define_expand "addhi3"
5980 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
5981 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
5982 (match_operand:HI 2 "general_operand" "")))
5983 (clobber (reg:CC 17))])]
5984 "TARGET_HIMODE_MATH"
5985 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
5987 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
5988 ;; type optimizations enabled by define-splits. This is not important
5989 ;; for PII, and in fact harmful because of partial register stalls.
5991 (define_insn "*addhi_1_lea"
5992 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
5993 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
5994 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
5995 (clobber (reg:CC 17))]
5996 "!TARGET_PARTIAL_REG_STALL
5997 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5999 switch (get_attr_type (insn))
6004 if (operands[2] == const1_rtx)
6005 return "inc{w}\t%0";
6006 else if (operands[2] == constm1_rtx)
6007 return "dec{w}\t%0";
6011 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6012 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6013 if (GET_CODE (operands[2]) == CONST_INT
6014 && (INTVAL (operands[2]) == 128
6015 || (INTVAL (operands[2]) < 0
6016 && INTVAL (operands[2]) != -128)))
6018 operands[2] = GEN_INT (-INTVAL (operands[2]));
6019 return "sub{w}\t{%2, %0|%0, %2}";
6021 return "add{w}\t{%2, %0|%0, %2}";
6025 (if_then_else (eq_attr "alternative" "2")
6026 (const_string "lea")
6027 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6028 (const_string "incdec")
6029 (const_string "alu"))))
6030 (set_attr "mode" "HI,HI,SI")])
6032 (define_insn "*addhi_1"
6033 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6034 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6035 (match_operand:HI 2 "general_operand" "ri,rm")))
6036 (clobber (reg:CC 17))]
6037 "TARGET_PARTIAL_REG_STALL
6038 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6040 switch (get_attr_type (insn))
6043 if (operands[2] == const1_rtx)
6044 return "inc{w}\t%0";
6045 else if (operands[2] == constm1_rtx)
6046 return "dec{w}\t%0";
6050 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6051 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6052 if (GET_CODE (operands[2]) == CONST_INT
6053 && (INTVAL (operands[2]) == 128
6054 || (INTVAL (operands[2]) < 0
6055 && INTVAL (operands[2]) != -128)))
6057 operands[2] = GEN_INT (-INTVAL (operands[2]));
6058 return "sub{w}\t{%2, %0|%0, %2}";
6060 return "add{w}\t{%2, %0|%0, %2}";
6064 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6065 (const_string "incdec")
6066 (const_string "alu")))
6067 (set_attr "mode" "HI")])
6069 (define_insn "*addhi_2"
6072 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6073 (match_operand:HI 2 "general_operand" "rmni,rni"))
6075 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6076 (plus:HI (match_dup 1) (match_dup 2)))]
6077 "ix86_match_ccmode (insn, CCGOCmode)
6078 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6080 switch (get_attr_type (insn))
6083 if (operands[2] == const1_rtx)
6084 return "inc{w}\t%0";
6085 else if (operands[2] == constm1_rtx)
6086 return "dec{w}\t%0";
6090 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6091 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6092 if (GET_CODE (operands[2]) == CONST_INT
6093 && (INTVAL (operands[2]) == 128
6094 || (INTVAL (operands[2]) < 0
6095 && INTVAL (operands[2]) != -128)))
6097 operands[2] = GEN_INT (-INTVAL (operands[2]));
6098 return "sub{w}\t{%2, %0|%0, %2}";
6100 return "add{w}\t{%2, %0|%0, %2}";
6104 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6105 (const_string "incdec")
6106 (const_string "alu")))
6107 (set_attr "mode" "HI")])
6109 (define_insn "*addhi_3"
6111 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6112 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6113 (clobber (match_scratch:HI 0 "=r"))]
6114 "ix86_match_ccmode (insn, CCZmode)
6115 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6117 switch (get_attr_type (insn))
6120 if (operands[2] == const1_rtx)
6121 return "inc{w}\t%0";
6122 else if (operands[2] == constm1_rtx)
6123 return "dec{w}\t%0";
6127 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6128 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6129 if (GET_CODE (operands[2]) == CONST_INT
6130 && (INTVAL (operands[2]) == 128
6131 || (INTVAL (operands[2]) < 0
6132 && INTVAL (operands[2]) != -128)))
6134 operands[2] = GEN_INT (-INTVAL (operands[2]));
6135 return "sub{w}\t{%2, %0|%0, %2}";
6137 return "add{w}\t{%2, %0|%0, %2}";
6141 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6142 (const_string "incdec")
6143 (const_string "alu")))
6144 (set_attr "mode" "HI")])
6146 ; See comments above addsi_3_imm for details.
6147 (define_insn "*addhi_4"
6149 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6150 (match_operand:HI 2 "const_int_operand" "n")))
6151 (clobber (match_scratch:HI 0 "=rm"))]
6152 "ix86_match_ccmode (insn, CCGCmode)
6153 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6155 switch (get_attr_type (insn))
6158 if (operands[2] == constm1_rtx)
6159 return "inc{w}\t%0";
6160 else if (operands[2] == const1_rtx)
6161 return "dec{w}\t%0";
6166 if (! rtx_equal_p (operands[0], operands[1]))
6168 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6169 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6170 if ((INTVAL (operands[2]) == -128
6171 || (INTVAL (operands[2]) > 0
6172 && INTVAL (operands[2]) != 128)))
6173 return "sub{w}\t{%2, %0|%0, %2}";
6174 operands[2] = GEN_INT (-INTVAL (operands[2]));
6175 return "add{w}\t{%2, %0|%0, %2}";
6179 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6180 (const_string "incdec")
6181 (const_string "alu")))
6182 (set_attr "mode" "SI")])
6185 (define_insn "*addhi_5"
6188 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6189 (match_operand:HI 2 "general_operand" "rmni"))
6191 (clobber (match_scratch:HI 0 "=r"))]
6192 "ix86_match_ccmode (insn, CCGOCmode)
6193 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6195 switch (get_attr_type (insn))
6198 if (operands[2] == const1_rtx)
6199 return "inc{w}\t%0";
6200 else if (operands[2] == constm1_rtx)
6201 return "dec{w}\t%0";
6205 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6206 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6207 if (GET_CODE (operands[2]) == CONST_INT
6208 && (INTVAL (operands[2]) == 128
6209 || (INTVAL (operands[2]) < 0
6210 && INTVAL (operands[2]) != -128)))
6212 operands[2] = GEN_INT (-INTVAL (operands[2]));
6213 return "sub{w}\t{%2, %0|%0, %2}";
6215 return "add{w}\t{%2, %0|%0, %2}";
6219 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6220 (const_string "incdec")
6221 (const_string "alu")))
6222 (set_attr "mode" "HI")])
6224 (define_expand "addqi3"
6225 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6226 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6227 (match_operand:QI 2 "general_operand" "")))
6228 (clobber (reg:CC 17))])]
6229 "TARGET_QIMODE_MATH"
6230 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6232 ;; %%% Potential partial reg stall on alternative 2. What to do?
6233 (define_insn "*addqi_1_lea"
6234 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6235 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6236 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
6237 (clobber (reg:CC 17))]
6238 "!TARGET_PARTIAL_REG_STALL
6239 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6241 int widen = (which_alternative == 2);
6242 switch (get_attr_type (insn))
6247 if (operands[2] == const1_rtx)
6248 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6249 else if (operands[2] == constm1_rtx)
6250 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6254 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6255 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6256 if (GET_CODE (operands[2]) == CONST_INT
6257 && (INTVAL (operands[2]) == 128
6258 || (INTVAL (operands[2]) < 0
6259 && INTVAL (operands[2]) != -128)))
6261 operands[2] = GEN_INT (-INTVAL (operands[2]));
6263 return "sub{l}\t{%2, %k0|%k0, %2}";
6265 return "sub{b}\t{%2, %0|%0, %2}";
6268 return "add{l}\t{%k2, %k0|%k0, %k2}";
6270 return "add{b}\t{%2, %0|%0, %2}";
6274 (if_then_else (eq_attr "alternative" "3")
6275 (const_string "lea")
6276 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6277 (const_string "incdec")
6278 (const_string "alu"))))
6279 (set_attr "mode" "QI,QI,SI,SI")])
6281 (define_insn "*addqi_1"
6282 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6283 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6284 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6285 (clobber (reg:CC 17))]
6286 "TARGET_PARTIAL_REG_STALL
6287 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6289 int widen = (which_alternative == 2);
6290 switch (get_attr_type (insn))
6293 if (operands[2] == const1_rtx)
6294 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6295 else if (operands[2] == constm1_rtx)
6296 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6300 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6301 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6302 if (GET_CODE (operands[2]) == CONST_INT
6303 && (INTVAL (operands[2]) == 128
6304 || (INTVAL (operands[2]) < 0
6305 && INTVAL (operands[2]) != -128)))
6307 operands[2] = GEN_INT (-INTVAL (operands[2]));
6309 return "sub{l}\t{%2, %k0|%k0, %2}";
6311 return "sub{b}\t{%2, %0|%0, %2}";
6314 return "add{l}\t{%k2, %k0|%k0, %k2}";
6316 return "add{b}\t{%2, %0|%0, %2}";
6320 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6321 (const_string "incdec")
6322 (const_string "alu")))
6323 (set_attr "mode" "QI,QI,SI")])
6325 (define_insn "*addqi_1_slp"
6326 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6327 (plus:QI (match_dup 0)
6328 (match_operand:QI 1 "general_operand" "qn,qnm")))
6329 (clobber (reg:CC 17))]
6330 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6331 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6333 switch (get_attr_type (insn))
6336 if (operands[1] == const1_rtx)
6337 return "inc{b}\t%0";
6338 else if (operands[1] == constm1_rtx)
6339 return "dec{b}\t%0";
6343 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6344 if (GET_CODE (operands[1]) == CONST_INT
6345 && INTVAL (operands[1]) < 0)
6347 operands[2] = GEN_INT (-INTVAL (operands[2]));
6348 return "sub{b}\t{%1, %0|%0, %1}";
6350 return "add{b}\t{%1, %0|%0, %1}";
6354 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6355 (const_string "incdec")
6356 (const_string "alu1")))
6357 (set_attr "mode" "QI")])
6359 (define_insn "*addqi_2"
6362 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6363 (match_operand:QI 2 "general_operand" "qmni,qni"))
6365 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6366 (plus:QI (match_dup 1) (match_dup 2)))]
6367 "ix86_match_ccmode (insn, CCGOCmode)
6368 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6370 switch (get_attr_type (insn))
6373 if (operands[2] == const1_rtx)
6374 return "inc{b}\t%0";
6375 else if (operands[2] == constm1_rtx
6376 || (GET_CODE (operands[2]) == CONST_INT
6377 && INTVAL (operands[2]) == 255))
6378 return "dec{b}\t%0";
6382 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6383 if (GET_CODE (operands[2]) == CONST_INT
6384 && INTVAL (operands[2]) < 0)
6386 operands[2] = GEN_INT (-INTVAL (operands[2]));
6387 return "sub{b}\t{%2, %0|%0, %2}";
6389 return "add{b}\t{%2, %0|%0, %2}";
6393 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6394 (const_string "incdec")
6395 (const_string "alu")))
6396 (set_attr "mode" "QI")])
6398 (define_insn "*addqi_3"
6400 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6401 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6402 (clobber (match_scratch:QI 0 "=q"))]
6403 "ix86_match_ccmode (insn, CCZmode)
6404 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6406 switch (get_attr_type (insn))
6409 if (operands[2] == const1_rtx)
6410 return "inc{b}\t%0";
6411 else if (operands[2] == constm1_rtx
6412 || (GET_CODE (operands[2]) == CONST_INT
6413 && INTVAL (operands[2]) == 255))
6414 return "dec{b}\t%0";
6418 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6419 if (GET_CODE (operands[2]) == CONST_INT
6420 && INTVAL (operands[2]) < 0)
6422 operands[2] = GEN_INT (-INTVAL (operands[2]));
6423 return "sub{b}\t{%2, %0|%0, %2}";
6425 return "add{b}\t{%2, %0|%0, %2}";
6429 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6430 (const_string "incdec")
6431 (const_string "alu")))
6432 (set_attr "mode" "QI")])
6434 ; See comments above addsi_3_imm for details.
6435 (define_insn "*addqi_4"
6437 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6438 (match_operand:QI 2 "const_int_operand" "n")))
6439 (clobber (match_scratch:QI 0 "=qm"))]
6440 "ix86_match_ccmode (insn, CCGCmode)
6441 && (INTVAL (operands[2]) & 0xff) != 0x80"
6443 switch (get_attr_type (insn))
6446 if (operands[2] == constm1_rtx
6447 || (GET_CODE (operands[2]) == CONST_INT
6448 && INTVAL (operands[2]) == 255))
6449 return "inc{b}\t%0";
6450 else if (operands[2] == const1_rtx)
6451 return "dec{b}\t%0";
6456 if (! rtx_equal_p (operands[0], operands[1]))
6458 if (INTVAL (operands[2]) < 0)
6460 operands[2] = GEN_INT (-INTVAL (operands[2]));
6461 return "add{b}\t{%2, %0|%0, %2}";
6463 return "sub{b}\t{%2, %0|%0, %2}";
6467 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6468 (const_string "incdec")
6469 (const_string "alu")))
6470 (set_attr "mode" "QI")])
6473 (define_insn "*addqi_5"
6476 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6477 (match_operand:QI 2 "general_operand" "qmni"))
6479 (clobber (match_scratch:QI 0 "=q"))]
6480 "ix86_match_ccmode (insn, CCGOCmode)
6481 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6483 switch (get_attr_type (insn))
6486 if (operands[2] == const1_rtx)
6487 return "inc{b}\t%0";
6488 else if (operands[2] == constm1_rtx
6489 || (GET_CODE (operands[2]) == CONST_INT
6490 && INTVAL (operands[2]) == 255))
6491 return "dec{b}\t%0";
6495 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6496 if (GET_CODE (operands[2]) == CONST_INT
6497 && INTVAL (operands[2]) < 0)
6499 operands[2] = GEN_INT (-INTVAL (operands[2]));
6500 return "sub{b}\t{%2, %0|%0, %2}";
6502 return "add{b}\t{%2, %0|%0, %2}";
6506 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6507 (const_string "incdec")
6508 (const_string "alu")))
6509 (set_attr "mode" "QI")])
6512 (define_insn "addqi_ext_1"
6513 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6518 (match_operand 1 "ext_register_operand" "0")
6521 (match_operand:QI 2 "general_operand" "Qmn")))
6522 (clobber (reg:CC 17))]
6525 switch (get_attr_type (insn))
6528 if (operands[2] == const1_rtx)
6529 return "inc{b}\t%h0";
6530 else if (operands[2] == constm1_rtx
6531 || (GET_CODE (operands[2]) == CONST_INT
6532 && INTVAL (operands[2]) == 255))
6533 return "dec{b}\t%h0";
6537 return "add{b}\t{%2, %h0|%h0, %2}";
6541 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6542 (const_string "incdec")
6543 (const_string "alu")))
6544 (set_attr "mode" "QI")])
6546 (define_insn "*addqi_ext_1_rex64"
6547 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6552 (match_operand 1 "ext_register_operand" "0")
6555 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6556 (clobber (reg:CC 17))]
6559 switch (get_attr_type (insn))
6562 if (operands[2] == const1_rtx)
6563 return "inc{b}\t%h0";
6564 else if (operands[2] == constm1_rtx
6565 || (GET_CODE (operands[2]) == CONST_INT
6566 && INTVAL (operands[2]) == 255))
6567 return "dec{b}\t%h0";
6571 return "add{b}\t{%2, %h0|%h0, %2}";
6575 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6576 (const_string "incdec")
6577 (const_string "alu")))
6578 (set_attr "mode" "QI")])
6580 (define_insn "*addqi_ext_2"
6581 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6586 (match_operand 1 "ext_register_operand" "%0")
6590 (match_operand 2 "ext_register_operand" "Q")
6593 (clobber (reg:CC 17))]
6595 "add{b}\t{%h2, %h0|%h0, %h2}"
6596 [(set_attr "type" "alu")
6597 (set_attr "mode" "QI")])
6599 ;; The patterns that match these are at the end of this file.
6601 (define_expand "addxf3"
6602 [(set (match_operand:XF 0 "register_operand" "")
6603 (plus:XF (match_operand:XF 1 "register_operand" "")
6604 (match_operand:XF 2 "register_operand" "")))]
6605 "!TARGET_64BIT && TARGET_80387"
6608 (define_expand "addtf3"
6609 [(set (match_operand:TF 0 "register_operand" "")
6610 (plus:TF (match_operand:TF 1 "register_operand" "")
6611 (match_operand:TF 2 "register_operand" "")))]
6615 (define_expand "adddf3"
6616 [(set (match_operand:DF 0 "register_operand" "")
6617 (plus:DF (match_operand:DF 1 "register_operand" "")
6618 (match_operand:DF 2 "nonimmediate_operand" "")))]
6619 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6622 (define_expand "addsf3"
6623 [(set (match_operand:SF 0 "register_operand" "")
6624 (plus:SF (match_operand:SF 1 "register_operand" "")
6625 (match_operand:SF 2 "nonimmediate_operand" "")))]
6626 "TARGET_80387 || TARGET_SSE_MATH"
6629 ;; Subtract instructions
6631 ;; %%% splits for subsidi3
6633 (define_expand "subdi3"
6634 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6635 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6636 (match_operand:DI 2 "x86_64_general_operand" "")))
6637 (clobber (reg:CC 17))])]
6639 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6641 (define_insn "*subdi3_1"
6642 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6643 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6644 (match_operand:DI 2 "general_operand" "roiF,riF")))
6645 (clobber (reg:CC 17))]
6646 "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6650 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6651 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6652 (match_operand:DI 2 "general_operand" "")))
6653 (clobber (reg:CC 17))]
6654 "!TARGET_64BIT && reload_completed"
6655 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6656 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6657 (parallel [(set (match_dup 3)
6658 (minus:SI (match_dup 4)
6659 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6661 (clobber (reg:CC 17))])]
6662 "split_di (operands+0, 1, operands+0, operands+3);
6663 split_di (operands+1, 1, operands+1, operands+4);
6664 split_di (operands+2, 1, operands+2, operands+5);")
6666 (define_insn "subdi3_carry_rex64"
6667 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6668 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6669 (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
6670 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6671 (clobber (reg:CC 17))]
6672 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6673 "sbb{q}\t{%2, %0|%0, %2}"
6674 [(set_attr "type" "alu")
6675 (set_attr "pent_pair" "pu")
6676 (set_attr "ppro_uops" "few")
6677 (set_attr "mode" "DI")])
6679 (define_insn "*subdi_1_rex64"
6680 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6681 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6682 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6683 (clobber (reg:CC 17))]
6684 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6685 "sub{q}\t{%2, %0|%0, %2}"
6686 [(set_attr "type" "alu")
6687 (set_attr "mode" "DI")])
6689 (define_insn "*subdi_2_rex64"
6692 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6693 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6695 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6696 (minus:DI (match_dup 1) (match_dup 2)))]
6697 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6698 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6699 "sub{q}\t{%2, %0|%0, %2}"
6700 [(set_attr "type" "alu")
6701 (set_attr "mode" "DI")])
6703 (define_insn "*subdi_3_rex63"
6705 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6706 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6707 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6708 (minus:DI (match_dup 1) (match_dup 2)))]
6709 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6710 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6711 "sub{q}\t{%2, %0|%0, %2}"
6712 [(set_attr "type" "alu")
6713 (set_attr "mode" "DI")])
6715 (define_insn "subqi3_carry"
6716 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm,r")
6717 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6718 (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
6719 (match_operand:QI 2 "general_operand" "ri,rm"))))
6720 (clobber (reg:CC 17))]
6721 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6722 "sbb{b}\t{%2, %0|%0, %2}"
6723 [(set_attr "type" "alu")
6724 (set_attr "pent_pair" "pu")
6725 (set_attr "ppro_uops" "few")
6726 (set_attr "mode" "QI")])
6728 (define_insn "subhi3_carry"
6729 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6730 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6731 (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
6732 (match_operand:HI 2 "general_operand" "ri,rm"))))
6733 (clobber (reg:CC 17))]
6734 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6735 "sbb{w}\t{%2, %0|%0, %2}"
6736 [(set_attr "type" "alu")
6737 (set_attr "pent_pair" "pu")
6738 (set_attr "ppro_uops" "few")
6739 (set_attr "mode" "HI")])
6741 (define_insn "subsi3_carry"
6742 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6743 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6744 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6745 (match_operand:SI 2 "general_operand" "ri,rm"))))
6746 (clobber (reg:CC 17))]
6747 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6748 "sbb{l}\t{%2, %0|%0, %2}"
6749 [(set_attr "type" "alu")
6750 (set_attr "pent_pair" "pu")
6751 (set_attr "ppro_uops" "few")
6752 (set_attr "mode" "SI")])
6754 (define_insn "subsi3_carry_zext"
6755 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6757 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6758 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6759 (match_operand:SI 2 "general_operand" "ri,rm")))))
6760 (clobber (reg:CC 17))]
6761 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6762 "sbb{l}\t{%2, %k0|%k0, %2}"
6763 [(set_attr "type" "alu")
6764 (set_attr "pent_pair" "pu")
6765 (set_attr "ppro_uops" "few")
6766 (set_attr "mode" "SI")])
6768 (define_expand "subsi3"
6769 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6770 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6771 (match_operand:SI 2 "general_operand" "")))
6772 (clobber (reg:CC 17))])]
6774 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6776 (define_insn "*subsi_1"
6777 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6778 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6779 (match_operand:SI 2 "general_operand" "ri,rm")))
6780 (clobber (reg:CC 17))]
6781 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6782 "sub{l}\t{%2, %0|%0, %2}"
6783 [(set_attr "type" "alu")
6784 (set_attr "mode" "SI")])
6786 (define_insn "*subsi_1_zext"
6787 [(set (match_operand:DI 0 "register_operand" "=r")
6789 (minus:SI (match_operand:SI 1 "register_operand" "0")
6790 (match_operand:SI 2 "general_operand" "rim"))))
6791 (clobber (reg:CC 17))]
6792 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6793 "sub{l}\t{%2, %k0|%k0, %2}"
6794 [(set_attr "type" "alu")
6795 (set_attr "mode" "SI")])
6797 (define_insn "*subsi_2"
6800 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6801 (match_operand:SI 2 "general_operand" "ri,rm"))
6803 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6804 (minus:SI (match_dup 1) (match_dup 2)))]
6805 "ix86_match_ccmode (insn, CCGOCmode)
6806 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6807 "sub{l}\t{%2, %0|%0, %2}"
6808 [(set_attr "type" "alu")
6809 (set_attr "mode" "SI")])
6811 (define_insn "*subsi_2_zext"
6814 (minus:SI (match_operand:SI 1 "register_operand" "0")
6815 (match_operand:SI 2 "general_operand" "rim"))
6817 (set (match_operand:DI 0 "register_operand" "=r")
6819 (minus:SI (match_dup 1)
6821 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6822 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6823 "sub{l}\t{%2, %k0|%k0, %2}"
6824 [(set_attr "type" "alu")
6825 (set_attr "mode" "SI")])
6827 (define_insn "*subsi_3"
6829 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
6830 (match_operand:SI 2 "general_operand" "ri,rm")))
6831 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6832 (minus:SI (match_dup 1) (match_dup 2)))]
6833 "ix86_match_ccmode (insn, CCmode)
6834 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6835 "sub{l}\t{%2, %0|%0, %2}"
6836 [(set_attr "type" "alu")
6837 (set_attr "mode" "SI")])
6839 (define_insn "*subsi_3_zext"
6841 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
6842 (match_operand:SI 2 "general_operand" "rim")))
6843 (set (match_operand:DI 0 "register_operand" "=r")
6845 (minus:SI (match_dup 1)
6847 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6848 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6849 "sub{q}\t{%2, %0|%0, %2}"
6850 [(set_attr "type" "alu")
6851 (set_attr "mode" "DI")])
6853 (define_expand "subhi3"
6854 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6855 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6856 (match_operand:HI 2 "general_operand" "")))
6857 (clobber (reg:CC 17))])]
6858 "TARGET_HIMODE_MATH"
6859 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
6861 (define_insn "*subhi_1"
6862 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6863 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6864 (match_operand:HI 2 "general_operand" "ri,rm")))
6865 (clobber (reg:CC 17))]
6866 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6867 "sub{w}\t{%2, %0|%0, %2}"
6868 [(set_attr "type" "alu")
6869 (set_attr "mode" "HI")])
6871 (define_insn "*subhi_2"
6874 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6875 (match_operand:HI 2 "general_operand" "ri,rm"))
6877 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6878 (minus:HI (match_dup 1) (match_dup 2)))]
6879 "ix86_match_ccmode (insn, CCGOCmode)
6880 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6881 "sub{w}\t{%2, %0|%0, %2}"
6882 [(set_attr "type" "alu")
6883 (set_attr "mode" "HI")])
6885 (define_insn "*subhi_3"
6887 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
6888 (match_operand:HI 2 "general_operand" "ri,rm")))
6889 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6890 (minus:HI (match_dup 1) (match_dup 2)))]
6891 "ix86_match_ccmode (insn, CCmode)
6892 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6893 "sub{w}\t{%2, %0|%0, %2}"
6894 [(set_attr "type" "alu")
6895 (set_attr "mode" "HI")])
6897 (define_expand "subqi3"
6898 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6899 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6900 (match_operand:QI 2 "general_operand" "")))
6901 (clobber (reg:CC 17))])]
6902 "TARGET_QIMODE_MATH"
6903 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
6905 (define_insn "*subqi_1"
6906 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6907 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6908 (match_operand:QI 2 "general_operand" "qn,qmn")))
6909 (clobber (reg:CC 17))]
6910 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6911 "sub{b}\t{%2, %0|%0, %2}"
6912 [(set_attr "type" "alu")
6913 (set_attr "mode" "QI")])
6915 (define_insn "*subqi_1_slp"
6916 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6917 (minus:QI (match_dup 0)
6918 (match_operand:QI 1 "general_operand" "qn,qmn")))
6919 (clobber (reg:CC 17))]
6920 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6921 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6922 "sub{b}\t{%1, %0|%0, %1}"
6923 [(set_attr "type" "alu1")
6924 (set_attr "mode" "QI")])
6926 (define_insn "*subqi_2"
6929 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6930 (match_operand:QI 2 "general_operand" "qi,qm"))
6932 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6933 (minus:HI (match_dup 1) (match_dup 2)))]
6934 "ix86_match_ccmode (insn, CCGOCmode)
6935 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6936 "sub{b}\t{%2, %0|%0, %2}"
6937 [(set_attr "type" "alu")
6938 (set_attr "mode" "QI")])
6940 (define_insn "*subqi_3"
6942 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
6943 (match_operand:QI 2 "general_operand" "qi,qm")))
6944 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6945 (minus:HI (match_dup 1) (match_dup 2)))]
6946 "ix86_match_ccmode (insn, CCmode)
6947 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6948 "sub{b}\t{%2, %0|%0, %2}"
6949 [(set_attr "type" "alu")
6950 (set_attr "mode" "QI")])
6952 ;; The patterns that match these are at the end of this file.
6954 (define_expand "subxf3"
6955 [(set (match_operand:XF 0 "register_operand" "")
6956 (minus:XF (match_operand:XF 1 "register_operand" "")
6957 (match_operand:XF 2 "register_operand" "")))]
6958 "!TARGET_64BIT && TARGET_80387"
6961 (define_expand "subtf3"
6962 [(set (match_operand:TF 0 "register_operand" "")
6963 (minus:TF (match_operand:TF 1 "register_operand" "")
6964 (match_operand:TF 2 "register_operand" "")))]
6968 (define_expand "subdf3"
6969 [(set (match_operand:DF 0 "register_operand" "")
6970 (minus:DF (match_operand:DF 1 "register_operand" "")
6971 (match_operand:DF 2 "nonimmediate_operand" "")))]
6972 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6975 (define_expand "subsf3"
6976 [(set (match_operand:SF 0 "register_operand" "")
6977 (minus:SF (match_operand:SF 1 "register_operand" "")
6978 (match_operand:SF 2 "nonimmediate_operand" "")))]
6979 "TARGET_80387 || TARGET_SSE_MATH"
6982 ;; Multiply instructions
6984 (define_expand "muldi3"
6985 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6986 (mult:DI (match_operand:DI 1 "register_operand" "")
6987 (match_operand:DI 2 "x86_64_general_operand" "")))
6988 (clobber (reg:CC 17))])]
6992 (define_insn "*muldi3_1_rex64"
6993 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6994 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
6995 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
6996 (clobber (reg:CC 17))]
6998 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7000 imul{q}\t{%2, %1, %0|%0, %1, %2}
7001 imul{q}\t{%2, %1, %0|%0, %1, %2}
7002 imul{q}\t{%2, %0|%0, %2}"
7003 [(set_attr "type" "imul")
7004 (set_attr "prefix_0f" "0,0,1")
7005 (set (attr "athlon_decode")
7006 (cond [(eq_attr "cpu" "athlon")
7007 (const_string "vector")
7008 (eq_attr "alternative" "1")
7009 (const_string "vector")
7010 (and (eq_attr "alternative" "2")
7011 (match_operand 1 "memory_operand" ""))
7012 (const_string "vector")]
7013 (const_string "direct")))
7014 (set_attr "mode" "DI")])
7016 (define_expand "mulsi3"
7017 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7018 (mult:SI (match_operand:SI 1 "register_operand" "")
7019 (match_operand:SI 2 "general_operand" "")))
7020 (clobber (reg:CC 17))])]
7024 (define_insn "*mulsi3_1"
7025 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7026 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7027 (match_operand:SI 2 "general_operand" "K,i,mr")))
7028 (clobber (reg:CC 17))]
7029 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7031 imul{l}\t{%2, %1, %0|%0, %1, %2}
7032 imul{l}\t{%2, %1, %0|%0, %1, %2}
7033 imul{l}\t{%2, %0|%0, %2}"
7034 [(set_attr "type" "imul")
7035 (set_attr "prefix_0f" "0,0,1")
7036 (set (attr "athlon_decode")
7037 (cond [(eq_attr "cpu" "athlon")
7038 (const_string "vector")
7039 (eq_attr "alternative" "1")
7040 (const_string "vector")
7041 (and (eq_attr "alternative" "2")
7042 (match_operand 1 "memory_operand" ""))
7043 (const_string "vector")]
7044 (const_string "direct")))
7045 (set_attr "mode" "SI")])
7047 (define_insn "*mulsi3_1_zext"
7048 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7050 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7051 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7052 (clobber (reg:CC 17))]
7054 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7056 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7057 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7058 imul{l}\t{%2, %k0|%k0, %2}"
7059 [(set_attr "type" "imul")
7060 (set_attr "prefix_0f" "0,0,1")
7061 (set (attr "athlon_decode")
7062 (cond [(eq_attr "cpu" "athlon")
7063 (const_string "vector")
7064 (eq_attr "alternative" "1")
7065 (const_string "vector")
7066 (and (eq_attr "alternative" "2")
7067 (match_operand 1 "memory_operand" ""))
7068 (const_string "vector")]
7069 (const_string "direct")))
7070 (set_attr "mode" "SI")])
7072 (define_expand "mulhi3"
7073 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7074 (mult:HI (match_operand:HI 1 "register_operand" "")
7075 (match_operand:HI 2 "general_operand" "")))
7076 (clobber (reg:CC 17))])]
7077 "TARGET_HIMODE_MATH"
7080 (define_insn "*mulhi3_1"
7081 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7082 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
7083 (match_operand:HI 2 "general_operand" "K,i,mr")))
7084 (clobber (reg:CC 17))]
7085 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7087 imul{w}\t{%2, %1, %0|%0, %1, %2}
7088 imul{w}\t{%2, %1, %0|%0, %1, %2}
7089 imul{w}\t{%2, %0|%0, %2}"
7090 [(set_attr "type" "imul")
7091 (set_attr "prefix_0f" "0,0,1")
7092 (set (attr "athlon_decode")
7093 (cond [(eq_attr "cpu" "athlon")
7094 (const_string "vector")
7095 (eq_attr "alternative" "1,2")
7096 (const_string "vector")]
7097 (const_string "direct")))
7098 (set_attr "mode" "HI")])
7100 (define_expand "mulqi3"
7101 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7102 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
7103 (match_operand:QI 2 "register_operand" "")))
7104 (clobber (reg:CC 17))])]
7105 "TARGET_QIMODE_MATH"
7108 (define_insn "*mulqi3_1"
7109 [(set (match_operand:QI 0 "register_operand" "=a")
7110 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7111 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7112 (clobber (reg:CC 17))]
7114 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7116 [(set_attr "type" "imul")
7117 (set_attr "length_immediate" "0")
7118 (set (attr "athlon_decode")
7119 (if_then_else (eq_attr "cpu" "athlon")
7120 (const_string "vector")
7121 (const_string "direct")))
7122 (set_attr "mode" "QI")])
7124 (define_expand "umulqihi3"
7125 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7126 (mult:HI (zero_extend:HI
7127 (match_operand:QI 1 "nonimmediate_operand" ""))
7129 (match_operand:QI 2 "register_operand" ""))))
7130 (clobber (reg:CC 17))])]
7131 "TARGET_QIMODE_MATH"
7134 (define_insn "*umulqihi3_1"
7135 [(set (match_operand:HI 0 "register_operand" "=a")
7136 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7137 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7138 (clobber (reg:CC 17))]
7140 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7142 [(set_attr "type" "imul")
7143 (set_attr "length_immediate" "0")
7144 (set (attr "athlon_decode")
7145 (if_then_else (eq_attr "cpu" "athlon")
7146 (const_string "vector")
7147 (const_string "direct")))
7148 (set_attr "mode" "QI")])
7150 (define_expand "mulqihi3"
7151 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7152 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
7153 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
7154 (clobber (reg:CC 17))])]
7155 "TARGET_QIMODE_MATH"
7158 (define_insn "*mulqihi3_insn"
7159 [(set (match_operand:HI 0 "register_operand" "=a")
7160 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7161 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7162 (clobber (reg:CC 17))]
7164 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7166 [(set_attr "type" "imul")
7167 (set_attr "length_immediate" "0")
7168 (set (attr "athlon_decode")
7169 (if_then_else (eq_attr "cpu" "athlon")
7170 (const_string "vector")
7171 (const_string "direct")))
7172 (set_attr "mode" "QI")])
7174 (define_expand "umulditi3"
7175 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7176 (mult:TI (zero_extend:TI
7177 (match_operand:DI 1 "nonimmediate_operand" ""))
7179 (match_operand:DI 2 "register_operand" ""))))
7180 (clobber (reg:CC 17))])]
7184 (define_insn "*umulditi3_insn"
7185 [(set (match_operand:TI 0 "register_operand" "=A")
7186 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7187 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7188 (clobber (reg:CC 17))]
7190 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7192 [(set_attr "type" "imul")
7193 (set_attr "ppro_uops" "few")
7194 (set_attr "length_immediate" "0")
7195 (set (attr "athlon_decode")
7196 (if_then_else (eq_attr "cpu" "athlon")
7197 (const_string "vector")
7198 (const_string "double")))
7199 (set_attr "mode" "DI")])
7201 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7202 (define_expand "umulsidi3"
7203 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7204 (mult:DI (zero_extend:DI
7205 (match_operand:SI 1 "nonimmediate_operand" ""))
7207 (match_operand:SI 2 "register_operand" ""))))
7208 (clobber (reg:CC 17))])]
7212 (define_insn "*umulsidi3_insn"
7213 [(set (match_operand:DI 0 "register_operand" "=A")
7214 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7215 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7216 (clobber (reg:CC 17))]
7218 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7220 [(set_attr "type" "imul")
7221 (set_attr "ppro_uops" "few")
7222 (set_attr "length_immediate" "0")
7223 (set (attr "athlon_decode")
7224 (if_then_else (eq_attr "cpu" "athlon")
7225 (const_string "vector")
7226 (const_string "double")))
7227 (set_attr "mode" "SI")])
7229 (define_expand "mulditi3"
7230 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7231 (mult:TI (sign_extend:TI
7232 (match_operand:DI 1 "nonimmediate_operand" ""))
7234 (match_operand:DI 2 "register_operand" ""))))
7235 (clobber (reg:CC 17))])]
7239 (define_insn "*mulditi3_insn"
7240 [(set (match_operand:TI 0 "register_operand" "=A")
7241 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7242 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7243 (clobber (reg:CC 17))]
7245 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7247 [(set_attr "type" "imul")
7248 (set_attr "length_immediate" "0")
7249 (set (attr "athlon_decode")
7250 (if_then_else (eq_attr "cpu" "athlon")
7251 (const_string "vector")
7252 (const_string "double")))
7253 (set_attr "mode" "DI")])
7255 (define_expand "mulsidi3"
7256 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7257 (mult:DI (sign_extend:DI
7258 (match_operand:SI 1 "nonimmediate_operand" ""))
7260 (match_operand:SI 2 "register_operand" ""))))
7261 (clobber (reg:CC 17))])]
7265 (define_insn "*mulsidi3_insn"
7266 [(set (match_operand:DI 0 "register_operand" "=A")
7267 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7268 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7269 (clobber (reg:CC 17))]
7271 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7273 [(set_attr "type" "imul")
7274 (set_attr "length_immediate" "0")
7275 (set (attr "athlon_decode")
7276 (if_then_else (eq_attr "cpu" "athlon")
7277 (const_string "vector")
7278 (const_string "double")))
7279 (set_attr "mode" "SI")])
7281 (define_expand "umuldi3_highpart"
7282 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7285 (mult:TI (zero_extend:TI
7286 (match_operand:DI 1 "nonimmediate_operand" ""))
7288 (match_operand:DI 2 "register_operand" "")))
7290 (clobber (match_scratch:DI 3 ""))
7291 (clobber (reg:CC 17))])]
7295 (define_insn "*umuldi3_highpart_rex64"
7296 [(set (match_operand:DI 0 "register_operand" "=d")
7299 (mult:TI (zero_extend:TI
7300 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7302 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7304 (clobber (match_scratch:DI 3 "=1"))
7305 (clobber (reg:CC 17))]
7307 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7309 [(set_attr "type" "imul")
7310 (set_attr "ppro_uops" "few")
7311 (set_attr "length_immediate" "0")
7312 (set (attr "athlon_decode")
7313 (if_then_else (eq_attr "cpu" "athlon")
7314 (const_string "vector")
7315 (const_string "double")))
7316 (set_attr "mode" "DI")])
7318 (define_expand "umulsi3_highpart"
7319 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7322 (mult:DI (zero_extend:DI
7323 (match_operand:SI 1 "nonimmediate_operand" ""))
7325 (match_operand:SI 2 "register_operand" "")))
7327 (clobber (match_scratch:SI 3 ""))
7328 (clobber (reg:CC 17))])]
7332 (define_insn "*umulsi3_highpart_insn"
7333 [(set (match_operand:SI 0 "register_operand" "=d")
7336 (mult:DI (zero_extend:DI
7337 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7339 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7341 (clobber (match_scratch:SI 3 "=1"))
7342 (clobber (reg:CC 17))]
7343 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7345 [(set_attr "type" "imul")
7346 (set_attr "ppro_uops" "few")
7347 (set_attr "length_immediate" "0")
7348 (set (attr "athlon_decode")
7349 (if_then_else (eq_attr "cpu" "athlon")
7350 (const_string "vector")
7351 (const_string "double")))
7352 (set_attr "mode" "SI")])
7354 (define_insn "*umulsi3_highpart_zext"
7355 [(set (match_operand:DI 0 "register_operand" "=d")
7356 (zero_extend:DI (truncate:SI
7358 (mult:DI (zero_extend:DI
7359 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7361 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7363 (clobber (match_scratch:SI 3 "=1"))
7364 (clobber (reg:CC 17))]
7366 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7368 [(set_attr "type" "imul")
7369 (set_attr "ppro_uops" "few")
7370 (set_attr "length_immediate" "0")
7371 (set (attr "athlon_decode")
7372 (if_then_else (eq_attr "cpu" "athlon")
7373 (const_string "vector")
7374 (const_string "double")))
7375 (set_attr "mode" "SI")])
7377 (define_expand "smuldi3_highpart"
7378 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7381 (mult:TI (sign_extend:TI
7382 (match_operand:DI 1 "nonimmediate_operand" ""))
7384 (match_operand:DI 2 "register_operand" "")))
7386 (clobber (match_scratch:DI 3 ""))
7387 (clobber (reg:CC 17))])]
7391 (define_insn "*smuldi3_highpart_rex64"
7392 [(set (match_operand:DI 0 "register_operand" "=d")
7395 (mult:TI (sign_extend:TI
7396 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7398 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7400 (clobber (match_scratch:DI 3 "=1"))
7401 (clobber (reg:CC 17))]
7403 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7405 [(set_attr "type" "imul")
7406 (set_attr "ppro_uops" "few")
7407 (set (attr "athlon_decode")
7408 (if_then_else (eq_attr "cpu" "athlon")
7409 (const_string "vector")
7410 (const_string "double")))
7411 (set_attr "mode" "DI")])
7413 (define_expand "smulsi3_highpart"
7414 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7417 (mult:DI (sign_extend:DI
7418 (match_operand:SI 1 "nonimmediate_operand" ""))
7420 (match_operand:SI 2 "register_operand" "")))
7422 (clobber (match_scratch:SI 3 ""))
7423 (clobber (reg:CC 17))])]
7427 (define_insn "*smulsi3_highpart_insn"
7428 [(set (match_operand:SI 0 "register_operand" "=d")
7431 (mult:DI (sign_extend:DI
7432 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7434 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7436 (clobber (match_scratch:SI 3 "=1"))
7437 (clobber (reg:CC 17))]
7438 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7440 [(set_attr "type" "imul")
7441 (set_attr "ppro_uops" "few")
7442 (set (attr "athlon_decode")
7443 (if_then_else (eq_attr "cpu" "athlon")
7444 (const_string "vector")
7445 (const_string "double")))
7446 (set_attr "mode" "SI")])
7448 (define_insn "*smulsi3_highpart_zext"
7449 [(set (match_operand:DI 0 "register_operand" "=d")
7450 (zero_extend:DI (truncate:SI
7452 (mult:DI (sign_extend:DI
7453 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7455 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7457 (clobber (match_scratch:SI 3 "=1"))
7458 (clobber (reg:CC 17))]
7460 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7462 [(set_attr "type" "imul")
7463 (set_attr "ppro_uops" "few")
7464 (set (attr "athlon_decode")
7465 (if_then_else (eq_attr "cpu" "athlon")
7466 (const_string "vector")
7467 (const_string "double")))
7468 (set_attr "mode" "SI")])
7470 ;; The patterns that match these are at the end of this file.
7472 (define_expand "mulxf3"
7473 [(set (match_operand:XF 0 "register_operand" "")
7474 (mult:XF (match_operand:XF 1 "register_operand" "")
7475 (match_operand:XF 2 "register_operand" "")))]
7476 "!TARGET_64BIT && TARGET_80387"
7479 (define_expand "multf3"
7480 [(set (match_operand:TF 0 "register_operand" "")
7481 (mult:TF (match_operand:TF 1 "register_operand" "")
7482 (match_operand:TF 2 "register_operand" "")))]
7486 (define_expand "muldf3"
7487 [(set (match_operand:DF 0 "register_operand" "")
7488 (mult:DF (match_operand:DF 1 "register_operand" "")
7489 (match_operand:DF 2 "nonimmediate_operand" "")))]
7490 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7493 (define_expand "mulsf3"
7494 [(set (match_operand:SF 0 "register_operand" "")
7495 (mult:SF (match_operand:SF 1 "register_operand" "")
7496 (match_operand:SF 2 "nonimmediate_operand" "")))]
7497 "TARGET_80387 || TARGET_SSE_MATH"
7500 ;; Divide instructions
7502 (define_insn "divqi3"
7503 [(set (match_operand:QI 0 "register_operand" "=a")
7504 (div:QI (match_operand:HI 1 "register_operand" "0")
7505 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7506 (clobber (reg:CC 17))]
7507 "TARGET_QIMODE_MATH"
7509 [(set_attr "type" "idiv")
7510 (set_attr "mode" "QI")
7511 (set_attr "ppro_uops" "few")])
7513 (define_insn "udivqi3"
7514 [(set (match_operand:QI 0 "register_operand" "=a")
7515 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7516 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7517 (clobber (reg:CC 17))]
7518 "TARGET_QIMODE_MATH"
7520 [(set_attr "type" "idiv")
7521 (set_attr "mode" "QI")
7522 (set_attr "ppro_uops" "few")])
7524 ;; The patterns that match these are at the end of this file.
7526 (define_expand "divxf3"
7527 [(set (match_operand:XF 0 "register_operand" "")
7528 (div:XF (match_operand:XF 1 "register_operand" "")
7529 (match_operand:XF 2 "register_operand" "")))]
7530 "!TARGET_64BIT && TARGET_80387"
7533 (define_expand "divtf3"
7534 [(set (match_operand:TF 0 "register_operand" "")
7535 (div:TF (match_operand:TF 1 "register_operand" "")
7536 (match_operand:TF 2 "register_operand" "")))]
7540 (define_expand "divdf3"
7541 [(set (match_operand:DF 0 "register_operand" "")
7542 (div:DF (match_operand:DF 1 "register_operand" "")
7543 (match_operand:DF 2 "nonimmediate_operand" "")))]
7544 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7547 (define_expand "divsf3"
7548 [(set (match_operand:SF 0 "register_operand" "")
7549 (div:SF (match_operand:SF 1 "register_operand" "")
7550 (match_operand:SF 2 "nonimmediate_operand" "")))]
7551 "TARGET_80387 || TARGET_SSE_MATH"
7554 ;; Remainder instructions.
7556 (define_expand "divmoddi4"
7557 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7558 (div:DI (match_operand:DI 1 "register_operand" "")
7559 (match_operand:DI 2 "nonimmediate_operand" "")))
7560 (set (match_operand:DI 3 "register_operand" "")
7561 (mod:DI (match_dup 1) (match_dup 2)))
7562 (clobber (reg:CC 17))])]
7566 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7567 ;; Penalize eax case slightly because it results in worse scheduling
7569 (define_insn "*divmoddi4_nocltd_rex64"
7570 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7571 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7572 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7573 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7574 (mod:DI (match_dup 2) (match_dup 3)))
7575 (clobber (reg:CC 17))]
7576 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7578 [(set_attr "type" "multi")])
7580 (define_insn "*divmoddi4_cltd_rex64"
7581 [(set (match_operand:DI 0 "register_operand" "=a")
7582 (div:DI (match_operand:DI 2 "register_operand" "a")
7583 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7584 (set (match_operand:DI 1 "register_operand" "=&d")
7585 (mod:DI (match_dup 2) (match_dup 3)))
7586 (clobber (reg:CC 17))]
7587 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7589 [(set_attr "type" "multi")])
7591 (define_insn "*divmoddi_noext_rex64"
7592 [(set (match_operand:DI 0 "register_operand" "=a")
7593 (div:DI (match_operand:DI 1 "register_operand" "0")
7594 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7595 (set (match_operand:DI 3 "register_operand" "=d")
7596 (mod:DI (match_dup 1) (match_dup 2)))
7597 (use (match_operand:DI 4 "register_operand" "3"))
7598 (clobber (reg:CC 17))]
7601 [(set_attr "type" "idiv")
7602 (set_attr "mode" "DI")
7603 (set_attr "ppro_uops" "few")])
7606 [(set (match_operand:DI 0 "register_operand" "")
7607 (div:DI (match_operand:DI 1 "register_operand" "")
7608 (match_operand:DI 2 "nonimmediate_operand" "")))
7609 (set (match_operand:DI 3 "register_operand" "")
7610 (mod:DI (match_dup 1) (match_dup 2)))
7611 (clobber (reg:CC 17))]
7612 "TARGET_64BIT && reload_completed"
7613 [(parallel [(set (match_dup 3)
7614 (ashiftrt:DI (match_dup 4) (const_int 63)))
7615 (clobber (reg:CC 17))])
7616 (parallel [(set (match_dup 0)
7617 (div:DI (reg:DI 0) (match_dup 2)))
7619 (mod:DI (reg:DI 0) (match_dup 2)))
7621 (clobber (reg:CC 17))])]
7623 /* Avoid use of cltd in favor of a mov+shift. */
7624 if (!TARGET_USE_CLTD && !optimize_size)
7626 if (true_regnum (operands[1]))
7627 emit_move_insn (operands[0], operands[1]);
7629 emit_move_insn (operands[3], operands[1]);
7630 operands[4] = operands[3];
7634 if (true_regnum (operands[1]))
7636 operands[4] = operands[1];
7641 (define_expand "divmodsi4"
7642 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7643 (div:SI (match_operand:SI 1 "register_operand" "")
7644 (match_operand:SI 2 "nonimmediate_operand" "")))
7645 (set (match_operand:SI 3 "register_operand" "")
7646 (mod:SI (match_dup 1) (match_dup 2)))
7647 (clobber (reg:CC 17))])]
7651 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7652 ;; Penalize eax case slightly because it results in worse scheduling
7654 (define_insn "*divmodsi4_nocltd"
7655 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7656 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7657 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7658 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7659 (mod:SI (match_dup 2) (match_dup 3)))
7660 (clobber (reg:CC 17))]
7661 "!optimize_size && !TARGET_USE_CLTD"
7663 [(set_attr "type" "multi")])
7665 (define_insn "*divmodsi4_cltd"
7666 [(set (match_operand:SI 0 "register_operand" "=a")
7667 (div:SI (match_operand:SI 2 "register_operand" "a")
7668 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7669 (set (match_operand:SI 1 "register_operand" "=&d")
7670 (mod:SI (match_dup 2) (match_dup 3)))
7671 (clobber (reg:CC 17))]
7672 "optimize_size || TARGET_USE_CLTD"
7674 [(set_attr "type" "multi")])
7676 (define_insn "*divmodsi_noext"
7677 [(set (match_operand:SI 0 "register_operand" "=a")
7678 (div:SI (match_operand:SI 1 "register_operand" "0")
7679 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7680 (set (match_operand:SI 3 "register_operand" "=d")
7681 (mod:SI (match_dup 1) (match_dup 2)))
7682 (use (match_operand:SI 4 "register_operand" "3"))
7683 (clobber (reg:CC 17))]
7686 [(set_attr "type" "idiv")
7687 (set_attr "mode" "SI")
7688 (set_attr "ppro_uops" "few")])
7691 [(set (match_operand:SI 0 "register_operand" "")
7692 (div:SI (match_operand:SI 1 "register_operand" "")
7693 (match_operand:SI 2 "nonimmediate_operand" "")))
7694 (set (match_operand:SI 3 "register_operand" "")
7695 (mod:SI (match_dup 1) (match_dup 2)))
7696 (clobber (reg:CC 17))]
7698 [(parallel [(set (match_dup 3)
7699 (ashiftrt:SI (match_dup 4) (const_int 31)))
7700 (clobber (reg:CC 17))])
7701 (parallel [(set (match_dup 0)
7702 (div:SI (reg:SI 0) (match_dup 2)))
7704 (mod:SI (reg:SI 0) (match_dup 2)))
7706 (clobber (reg:CC 17))])]
7708 /* Avoid use of cltd in favor of a mov+shift. */
7709 if (!TARGET_USE_CLTD && !optimize_size)
7711 if (true_regnum (operands[1]))
7712 emit_move_insn (operands[0], operands[1]);
7714 emit_move_insn (operands[3], operands[1]);
7715 operands[4] = operands[3];
7719 if (true_regnum (operands[1]))
7721 operands[4] = operands[1];
7725 (define_insn "divmodhi4"
7726 [(set (match_operand:HI 0 "register_operand" "=a")
7727 (div:HI (match_operand:HI 1 "register_operand" "0")
7728 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7729 (set (match_operand:HI 3 "register_operand" "=&d")
7730 (mod:HI (match_dup 1) (match_dup 2)))
7731 (clobber (reg:CC 17))]
7732 "TARGET_HIMODE_MATH"
7734 [(set_attr "type" "multi")
7735 (set_attr "length_immediate" "0")
7736 (set_attr "mode" "SI")])
7738 (define_insn "udivmoddi4"
7739 [(set (match_operand:DI 0 "register_operand" "=a")
7740 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7741 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7742 (set (match_operand:DI 3 "register_operand" "=&d")
7743 (umod:DI (match_dup 1) (match_dup 2)))
7744 (clobber (reg:CC 17))]
7746 "xor{q}\t%3, %3\;div{q}\t%2"
7747 [(set_attr "type" "multi")
7748 (set_attr "length_immediate" "0")
7749 (set_attr "mode" "DI")])
7751 (define_insn "*udivmoddi4_noext"
7752 [(set (match_operand:DI 0 "register_operand" "=a")
7753 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7754 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7755 (set (match_operand:DI 3 "register_operand" "=d")
7756 (umod:DI (match_dup 1) (match_dup 2)))
7758 (clobber (reg:CC 17))]
7761 [(set_attr "type" "idiv")
7762 (set_attr "ppro_uops" "few")
7763 (set_attr "mode" "DI")])
7766 [(set (match_operand:DI 0 "register_operand" "")
7767 (udiv:DI (match_operand:DI 1 "register_operand" "")
7768 (match_operand:DI 2 "nonimmediate_operand" "")))
7769 (set (match_operand:DI 3 "register_operand" "")
7770 (umod:DI (match_dup 1) (match_dup 2)))
7771 (clobber (reg:CC 17))]
7772 "TARGET_64BIT && reload_completed"
7773 [(set (match_dup 3) (const_int 0))
7774 (parallel [(set (match_dup 0)
7775 (udiv:DI (match_dup 1) (match_dup 2)))
7777 (umod:DI (match_dup 1) (match_dup 2)))
7779 (clobber (reg:CC 17))])]
7782 (define_insn "udivmodsi4"
7783 [(set (match_operand:SI 0 "register_operand" "=a")
7784 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7785 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7786 (set (match_operand:SI 3 "register_operand" "=&d")
7787 (umod:SI (match_dup 1) (match_dup 2)))
7788 (clobber (reg:CC 17))]
7790 "xor{l}\t%3, %3\;div{l}\t%2"
7791 [(set_attr "type" "multi")
7792 (set_attr "length_immediate" "0")
7793 (set_attr "mode" "SI")])
7795 (define_insn "*udivmodsi4_noext"
7796 [(set (match_operand:SI 0 "register_operand" "=a")
7797 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7798 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7799 (set (match_operand:SI 3 "register_operand" "=d")
7800 (umod:SI (match_dup 1) (match_dup 2)))
7802 (clobber (reg:CC 17))]
7805 [(set_attr "type" "idiv")
7806 (set_attr "ppro_uops" "few")
7807 (set_attr "mode" "SI")])
7810 [(set (match_operand:SI 0 "register_operand" "")
7811 (udiv:SI (match_operand:SI 1 "register_operand" "")
7812 (match_operand:SI 2 "nonimmediate_operand" "")))
7813 (set (match_operand:SI 3 "register_operand" "")
7814 (umod:SI (match_dup 1) (match_dup 2)))
7815 (clobber (reg:CC 17))]
7817 [(set (match_dup 3) (const_int 0))
7818 (parallel [(set (match_dup 0)
7819 (udiv:SI (match_dup 1) (match_dup 2)))
7821 (umod:SI (match_dup 1) (match_dup 2)))
7823 (clobber (reg:CC 17))])]
7826 (define_expand "udivmodhi4"
7827 [(set (match_dup 4) (const_int 0))
7828 (parallel [(set (match_operand:HI 0 "register_operand" "")
7829 (udiv:HI (match_operand:HI 1 "register_operand" "")
7830 (match_operand:HI 2 "nonimmediate_operand" "")))
7831 (set (match_operand:HI 3 "register_operand" "")
7832 (umod:HI (match_dup 1) (match_dup 2)))
7834 (clobber (reg:CC 17))])]
7835 "TARGET_HIMODE_MATH"
7836 "operands[4] = gen_reg_rtx (HImode);")
7838 (define_insn "*udivmodhi_noext"
7839 [(set (match_operand:HI 0 "register_operand" "=a")
7840 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7841 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7842 (set (match_operand:HI 3 "register_operand" "=d")
7843 (umod:HI (match_dup 1) (match_dup 2)))
7844 (use (match_operand:HI 4 "register_operand" "3"))
7845 (clobber (reg:CC 17))]
7848 [(set_attr "type" "idiv")
7849 (set_attr "mode" "HI")
7850 (set_attr "ppro_uops" "few")])
7852 ;; We can not use div/idiv for double division, because it causes
7853 ;; "division by zero" on the overflow and that's not what we expect
7854 ;; from truncate. Because true (non truncating) double division is
7855 ;; never generated, we can't create this insn anyway.
7858 ; [(set (match_operand:SI 0 "register_operand" "=a")
7860 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7862 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7863 ; (set (match_operand:SI 3 "register_operand" "=d")
7865 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7866 ; (clobber (reg:CC 17))]
7868 ; "div{l}\t{%2, %0|%0, %2}"
7869 ; [(set_attr "type" "idiv")
7870 ; (set_attr "ppro_uops" "few")])
7872 ;;- Logical AND instructions
7874 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7875 ;; Note that this excludes ah.
7877 (define_insn "*testdi_1_rex64"
7880 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%*a,r,*a,r,rm")
7881 (match_operand:DI 1 "x86_64_szext_nonmemory_operand" "Z,Z,e,e,re"))
7883 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7885 test{l}\t{%k1, %k0|%k0, %k1}
7886 test{l}\t{%k1, %k0|%k0, %k1}
7887 test{q}\t{%1, %0|%0, %1}
7888 test{q}\t{%1, %0|%0, %1}
7889 test{q}\t{%1, %0|%0, %1}"
7890 [(set_attr "type" "test")
7891 (set_attr "modrm" "0,1,0,1,1")
7892 (set_attr "mode" "SI,SI,DI,DI,DI")
7893 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7895 (define_insn "testsi_1"
7898 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm")
7899 (match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
7901 "ix86_match_ccmode (insn, CCNOmode)"
7902 "test{l}\t{%1, %0|%0, %1}"
7903 [(set_attr "type" "test")
7904 (set_attr "modrm" "0,1,1")
7905 (set_attr "mode" "SI")
7906 (set_attr "pent_pair" "uv,np,uv")])
7908 (define_expand "testsi_ccno_1"
7911 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7912 (match_operand:SI 1 "nonmemory_operand" ""))
7917 (define_insn "*testhi_1"
7919 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm")
7920 (match_operand:HI 1 "nonmemory_operand" "n,n,rn"))
7922 "ix86_match_ccmode (insn, CCNOmode)"
7923 "test{w}\t{%1, %0|%0, %1}"
7924 [(set_attr "type" "test")
7925 (set_attr "modrm" "0,1,1")
7926 (set_attr "mode" "HI")
7927 (set_attr "pent_pair" "uv,np,uv")])
7929 (define_expand "testqi_ccz_1"
7931 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7932 (match_operand:QI 1 "nonmemory_operand" ""))
7937 (define_insn "*testqi_1"
7939 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r")
7940 (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n"))
7942 "ix86_match_ccmode (insn, CCNOmode)"
7944 if (which_alternative == 3)
7946 if (GET_CODE (operands[1]) == CONST_INT
7947 && (INTVAL (operands[1]) & 0xffffff00))
7948 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7949 return "test{l}\t{%1, %k0|%k0, %1}";
7951 return "test{b}\t{%1, %0|%0, %1}";
7953 [(set_attr "type" "test")
7954 (set_attr "modrm" "0,1,1,1")
7955 (set_attr "mode" "QI,QI,QI,SI")
7956 (set_attr "pent_pair" "uv,np,uv,np")])
7958 (define_expand "testqi_ext_ccno_0"
7963 (match_operand 0 "ext_register_operand" "")
7966 (match_operand 1 "const_int_operand" ""))
7971 (define_insn "*testqi_ext_0"
7976 (match_operand 0 "ext_register_operand" "Q")
7979 (match_operand 1 "const_int_operand" "n"))
7981 "ix86_match_ccmode (insn, CCNOmode)"
7982 "test{b}\t{%1, %h0|%h0, %1}"
7983 [(set_attr "type" "test")
7984 (set_attr "mode" "QI")
7985 (set_attr "length_immediate" "1")
7986 (set_attr "pent_pair" "np")])
7988 (define_insn "*testqi_ext_1"
7993 (match_operand 0 "ext_register_operand" "Q")
7997 (match_operand:QI 1 "nonimmediate_operand" "Qm")))
7999 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8000 "test{b}\t{%1, %h0|%h0, %1}"
8001 [(set_attr "type" "test")
8002 (set_attr "mode" "QI")])
8004 (define_insn "*testqi_ext_1_rex64"
8009 (match_operand 0 "ext_register_operand" "Q")
8013 (match_operand:QI 1 "register_operand" "Q")))
8015 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8016 "test{b}\t{%1, %h0|%h0, %1}"
8017 [(set_attr "type" "test")
8018 (set_attr "mode" "QI")])
8020 (define_insn "*testqi_ext_2"
8025 (match_operand 0 "ext_register_operand" "Q")
8029 (match_operand 1 "ext_register_operand" "Q")
8033 "ix86_match_ccmode (insn, CCNOmode)"
8034 "test{b}\t{%h1, %h0|%h0, %h1}"
8035 [(set_attr "type" "test")
8036 (set_attr "mode" "QI")])
8038 ;; Combine likes to form bit extractions for some tests. Humor it.
8039 (define_insn "*testqi_ext_3"
8041 (compare (zero_extract:SI
8042 (match_operand 0 "nonimmediate_operand" "rm")
8043 (match_operand:SI 1 "const_int_operand" "")
8044 (match_operand:SI 2 "const_int_operand" ""))
8046 "ix86_match_ccmode (insn, CCNOmode)
8047 && (GET_MODE (operands[0]) == SImode
8048 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
8049 || GET_MODE (operands[0]) == HImode
8050 || GET_MODE (operands[0]) == QImode)"
8053 (define_insn "*testqi_ext_3_rex64"
8055 (compare (zero_extract:DI
8056 (match_operand 0 "nonimmediate_operand" "rm")
8057 (match_operand:DI 1 "const_int_operand" "")
8058 (match_operand:DI 2 "const_int_operand" ""))
8061 && ix86_match_ccmode (insn, CCNOmode)
8062 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
8063 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
8064 /* Ensure that resulting mask is zero or sign extended operand. */
8065 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
8066 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
8067 && INTVAL (operands[1]) > 32))
8068 && (GET_MODE (operands[0]) == SImode
8069 || GET_MODE (operands[0]) == DImode
8070 || GET_MODE (operands[0]) == HImode
8071 || GET_MODE (operands[0]) == QImode)"
8076 (compare (zero_extract
8077 (match_operand 0 "nonimmediate_operand" "")
8078 (match_operand 1 "const_int_operand" "")
8079 (match_operand 2 "const_int_operand" ""))
8081 "ix86_match_ccmode (insn, CCNOmode)"
8082 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
8084 HOST_WIDE_INT len = INTVAL (operands[1]);
8085 HOST_WIDE_INT pos = INTVAL (operands[2]);
8087 enum machine_mode mode, submode;
8089 mode = GET_MODE (operands[0]);
8090 if (GET_CODE (operands[0]) == MEM)
8092 /* ??? Combine likes to put non-volatile mem extractions in QImode
8093 no matter the size of the test. So find a mode that works. */
8094 if (! MEM_VOLATILE_P (operands[0]))
8096 mode = smallest_mode_for_size (pos + len, MODE_INT);
8097 operands[0] = adjust_address (operands[0], mode, 0);
8100 else if (GET_CODE (operands[0]) == SUBREG
8101 && (submode = GET_MODE (SUBREG_REG (operands[0])),
8102 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8103 && pos + len <= GET_MODE_BITSIZE (submode))
8105 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8107 operands[0] = SUBREG_REG (operands[0]);
8109 else if (mode == HImode && pos + len <= 8)
8111 /* Small HImode tests can be converted to QImode. */
8113 operands[0] = gen_lowpart (QImode, operands[0]);
8116 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8117 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8119 operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
8122 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
8123 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
8124 ;; this is relatively important trick.
8125 ;; Do the conversion only post-reload to avoid limiting of the register class
8130 (and (match_operand 0 "register_operand" "")
8131 (match_operand 1 "const_int_operand" ""))
8134 && QI_REG_P (operands[0])
8135 && ((ix86_match_ccmode (insn, CCZmode)
8136 && !(INTVAL (operands[1]) & ~(255 << 8)))
8137 || (ix86_match_ccmode (insn, CCNOmode)
8138 && !(INTVAL (operands[1]) & ~(127 << 8))))
8139 && GET_MODE (operands[0]) != QImode"
8142 (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8145 "operands[0] = gen_lowpart (SImode, operands[0]);
8146 operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
8151 (and (match_operand 0 "nonimmediate_operand" "")
8152 (match_operand 1 "const_int_operand" ""))
8155 && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0]))
8156 && ((ix86_match_ccmode (insn, CCZmode)
8157 && !(INTVAL (operands[1]) & ~255))
8158 || (ix86_match_ccmode (insn, CCNOmode)
8159 && !(INTVAL (operands[1]) & ~127)))
8160 && GET_MODE (operands[0]) != QImode"
8163 (and:QI (match_dup 0)
8166 "operands[0] = gen_lowpart (QImode, operands[0]);
8167 operands[1] = gen_lowpart (QImode, operands[1]);")
8170 ;; %%% This used to optimize known byte-wide and operations to memory,
8171 ;; and sometimes to QImode registers. If this is considered useful,
8172 ;; it should be done with splitters.
8174 (define_expand "anddi3"
8175 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8176 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8177 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8178 (clobber (reg:CC 17))]
8180 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8182 (define_insn "*anddi_1_rex64"
8183 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8184 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8185 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8186 (clobber (reg:CC 17))]
8187 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8189 switch (get_attr_type (insn))
8193 enum machine_mode mode;
8195 if (GET_CODE (operands[2]) != CONST_INT)
8197 if (INTVAL (operands[2]) == 0xff)
8199 else if (INTVAL (operands[2]) == 0xffff)
8204 operands[1] = gen_lowpart (mode, operands[1]);
8206 return "movz{bq|x}\t{%1,%0|%0, %1}";
8208 return "movz{wq|x}\t{%1,%0|%0, %1}";
8212 if (! rtx_equal_p (operands[0], operands[1]))
8214 if (get_attr_mode (insn) == MODE_SI)
8215 return "and{l}\t{%k2, %k0|%k0, %k2}";
8217 return "and{q}\t{%2, %0|%0, %2}";
8220 [(set_attr "type" "alu,alu,alu,imovx")
8221 (set_attr "length_immediate" "*,*,*,0")
8222 (set_attr "mode" "SI,DI,DI,DI")])
8224 (define_insn "*anddi_2"
8226 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8227 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8229 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8230 (and:DI (match_dup 1) (match_dup 2)))]
8231 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8232 && ix86_binary_operator_ok (AND, DImode, operands)"
8234 and{l}\t{%k2, %k0|%k0, %k2}
8235 and{q}\t{%2, %0|%0, %2}
8236 and{q}\t{%2, %0|%0, %2}"
8237 [(set_attr "type" "alu")
8238 (set_attr "mode" "SI,DI,DI")])
8240 (define_expand "andsi3"
8241 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8242 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8243 (match_operand:SI 2 "general_operand" "")))
8244 (clobber (reg:CC 17))]
8246 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8248 (define_insn "*andsi_1"
8249 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8250 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8251 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8252 (clobber (reg:CC 17))]
8253 "ix86_binary_operator_ok (AND, SImode, operands)"
8255 switch (get_attr_type (insn))
8259 enum machine_mode mode;
8261 if (GET_CODE (operands[2]) != CONST_INT)
8263 if (INTVAL (operands[2]) == 0xff)
8265 else if (INTVAL (operands[2]) == 0xffff)
8270 operands[1] = gen_lowpart (mode, operands[1]);
8272 return "movz{bl|x}\t{%1,%0|%0, %1}";
8274 return "movz{wl|x}\t{%1,%0|%0, %1}";
8278 if (! rtx_equal_p (operands[0], operands[1]))
8280 return "and{l}\t{%2, %0|%0, %2}";
8283 [(set_attr "type" "alu,alu,imovx")
8284 (set_attr "length_immediate" "*,*,0")
8285 (set_attr "mode" "SI")])
8288 [(set (match_operand 0 "register_operand" "")
8290 (const_int -65536)))
8291 (clobber (reg:CC 17))]
8292 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
8293 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8294 "operands[1] = gen_lowpart (HImode, operands[0]);")
8297 [(set (match_operand 0 "ext_register_operand" "")
8300 (clobber (reg:CC 17))]
8301 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8302 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8303 "operands[1] = gen_lowpart (QImode, operands[0]);")
8306 [(set (match_operand 0 "ext_register_operand" "")
8308 (const_int -65281)))
8309 (clobber (reg:CC 17))]
8310 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8311 [(parallel [(set (zero_extract:SI (match_dup 0)
8315 (zero_extract:SI (match_dup 0)
8318 (zero_extract:SI (match_dup 0)
8321 (clobber (reg:CC 17))])]
8322 "operands[0] = gen_lowpart (SImode, operands[0]);")
8324 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8325 (define_insn "*andsi_1_zext"
8326 [(set (match_operand:DI 0 "register_operand" "=r")
8328 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8329 (match_operand:SI 2 "general_operand" "rim"))))
8330 (clobber (reg:CC 17))]
8331 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8332 "and{l}\t{%2, %k0|%k0, %2}"
8333 [(set_attr "type" "alu")
8334 (set_attr "mode" "SI")])
8336 (define_insn "*andsi_2"
8338 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8339 (match_operand:SI 2 "general_operand" "rim,ri"))
8341 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8342 (and:SI (match_dup 1) (match_dup 2)))]
8343 "ix86_match_ccmode (insn, CCNOmode)
8344 && ix86_binary_operator_ok (AND, SImode, operands)"
8345 "and{l}\t{%2, %0|%0, %2}"
8346 [(set_attr "type" "alu")
8347 (set_attr "mode" "SI")])
8349 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8350 (define_insn "*andsi_2_zext"
8352 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8353 (match_operand:SI 2 "general_operand" "rim"))
8355 (set (match_operand:DI 0 "register_operand" "=r")
8356 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8357 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8358 && ix86_binary_operator_ok (AND, SImode, operands)"
8359 "and{l}\t{%2, %k0|%k0, %2}"
8360 [(set_attr "type" "alu")
8361 (set_attr "mode" "SI")])
8363 (define_expand "andhi3"
8364 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8365 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8366 (match_operand:HI 2 "general_operand" "")))
8367 (clobber (reg:CC 17))]
8368 "TARGET_HIMODE_MATH"
8369 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8371 (define_insn "*andhi_1"
8372 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8373 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8374 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8375 (clobber (reg:CC 17))]
8376 "ix86_binary_operator_ok (AND, HImode, operands)"
8378 switch (get_attr_type (insn))
8381 if (GET_CODE (operands[2]) != CONST_INT)
8383 if (INTVAL (operands[2]) == 0xff)
8384 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8388 if (! rtx_equal_p (operands[0], operands[1]))
8391 return "and{w}\t{%2, %0|%0, %2}";
8394 [(set_attr "type" "alu,alu,imovx")
8395 (set_attr "length_immediate" "*,*,0")
8396 (set_attr "mode" "HI,HI,SI")])
8398 (define_insn "*andhi_2"
8400 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8401 (match_operand:HI 2 "general_operand" "rim,ri"))
8403 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8404 (and:HI (match_dup 1) (match_dup 2)))]
8405 "ix86_match_ccmode (insn, CCNOmode)
8406 && ix86_binary_operator_ok (AND, HImode, operands)"
8407 "and{w}\t{%2, %0|%0, %2}"
8408 [(set_attr "type" "alu")
8409 (set_attr "mode" "HI")])
8411 (define_expand "andqi3"
8412 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8413 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8414 (match_operand:QI 2 "general_operand" "")))
8415 (clobber (reg:CC 17))]
8416 "TARGET_QIMODE_MATH"
8417 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8419 ;; %%% Potential partial reg stall on alternative 2. What to do?
8420 (define_insn "*andqi_1"
8421 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8422 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8423 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8424 (clobber (reg:CC 17))]
8425 "ix86_binary_operator_ok (AND, QImode, operands)"
8427 and{b}\t{%2, %0|%0, %2}
8428 and{b}\t{%2, %0|%0, %2}
8429 and{l}\t{%k2, %k0|%k0, %k2}"
8430 [(set_attr "type" "alu")
8431 (set_attr "mode" "QI,QI,SI")])
8433 (define_insn "*andqi_1_slp"
8434 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8435 (and:QI (match_dup 0)
8436 (match_operand:QI 1 "general_operand" "qi,qmi")))
8437 (clobber (reg:CC 17))]
8438 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8439 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8440 "and{b}\t{%1, %0|%0, %1}"
8441 [(set_attr "type" "alu1")
8442 (set_attr "mode" "QI")])
8444 (define_insn "*andqi_2"
8447 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8448 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8450 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8451 (and:QI (match_dup 1) (match_dup 2)))]
8452 "ix86_match_ccmode (insn, CCNOmode)
8453 && ix86_binary_operator_ok (AND, QImode, operands)"
8455 if (which_alternative == 2)
8457 if (GET_CODE (operands[2]) == CONST_INT
8458 && (INTVAL (operands[2]) & 0xffffff00))
8459 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8460 return "and{l}\t{%2, %k0|%k0, %2}";
8462 return "and{b}\t{%2, %0|%0, %2}";
8464 [(set_attr "type" "alu")
8465 (set_attr "mode" "QI,QI,SI")])
8467 (define_insn "*andqi_2_slp"
8470 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8471 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8473 (set (strict_low_part (match_dup 0))
8474 (and:QI (match_dup 0) (match_dup 1)))]
8475 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8476 && ix86_match_ccmode (insn, CCNOmode)
8477 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8478 "and{b}\t{%1, %0|%0, %1}"
8479 [(set_attr "type" "alu1")
8480 (set_attr "mode" "QI")])
8482 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8483 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8484 ;; for a QImode operand, which of course failed.
8486 (define_insn "andqi_ext_0"
8487 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8492 (match_operand 1 "ext_register_operand" "0")
8495 (match_operand 2 "const_int_operand" "n")))
8496 (clobber (reg:CC 17))]
8498 "and{b}\t{%2, %h0|%h0, %2}"
8499 [(set_attr "type" "alu")
8500 (set_attr "length_immediate" "1")
8501 (set_attr "mode" "QI")])
8503 ;; Generated by peephole translating test to and. This shows up
8504 ;; often in fp comparisons.
8506 (define_insn "*andqi_ext_0_cc"
8511 (match_operand 1 "ext_register_operand" "0")
8514 (match_operand 2 "const_int_operand" "n"))
8516 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8525 "ix86_match_ccmode (insn, CCNOmode)"
8526 "and{b}\t{%2, %h0|%h0, %2}"
8527 [(set_attr "type" "alu")
8528 (set_attr "length_immediate" "1")
8529 (set_attr "mode" "QI")])
8531 (define_insn "*andqi_ext_1"
8532 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8537 (match_operand 1 "ext_register_operand" "0")
8541 (match_operand:QI 2 "general_operand" "Qm"))))
8542 (clobber (reg:CC 17))]
8544 "and{b}\t{%2, %h0|%h0, %2}"
8545 [(set_attr "type" "alu")
8546 (set_attr "length_immediate" "0")
8547 (set_attr "mode" "QI")])
8549 (define_insn "*andqi_ext_1_rex64"
8550 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8555 (match_operand 1 "ext_register_operand" "0")
8559 (match_operand 2 "ext_register_operand" "Q"))))
8560 (clobber (reg:CC 17))]
8562 "and{b}\t{%2, %h0|%h0, %2}"
8563 [(set_attr "type" "alu")
8564 (set_attr "length_immediate" "0")
8565 (set_attr "mode" "QI")])
8567 (define_insn "*andqi_ext_2"
8568 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8573 (match_operand 1 "ext_register_operand" "%0")
8577 (match_operand 2 "ext_register_operand" "Q")
8580 (clobber (reg:CC 17))]
8582 "and{b}\t{%h2, %h0|%h0, %h2}"
8583 [(set_attr "type" "alu")
8584 (set_attr "length_immediate" "0")
8585 (set_attr "mode" "QI")])
8587 ;; Convert wide AND instructions with immediate operand to shorter QImode
8588 ;; equivalents when possible.
8589 ;; Don't do the splitting with memory operands, since it introduces risk
8590 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8591 ;; for size, but that can (should?) be handled by generic code instead.
8593 [(set (match_operand 0 "register_operand" "")
8594 (and (match_operand 1 "register_operand" "")
8595 (match_operand 2 "const_int_operand" "")))
8596 (clobber (reg:CC 17))]
8598 && QI_REG_P (operands[0])
8599 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8600 && !(~INTVAL (operands[2]) & ~(255 << 8))
8601 && GET_MODE (operands[0]) != QImode"
8602 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8603 (and:SI (zero_extract:SI (match_dup 1)
8604 (const_int 8) (const_int 8))
8606 (clobber (reg:CC 17))])]
8607 "operands[0] = gen_lowpart (SImode, operands[0]);
8608 operands[1] = gen_lowpart (SImode, operands[1]);
8609 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8611 ;; Since AND can be encoded with sign extended immediate, this is only
8612 ;; profitable when 7th bit is not set.
8614 [(set (match_operand 0 "register_operand" "")
8615 (and (match_operand 1 "general_operand" "")
8616 (match_operand 2 "const_int_operand" "")))
8617 (clobber (reg:CC 17))]
8619 && ANY_QI_REG_P (operands[0])
8620 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8621 && !(~INTVAL (operands[2]) & ~255)
8622 && !(INTVAL (operands[2]) & 128)
8623 && GET_MODE (operands[0]) != QImode"
8624 [(parallel [(set (strict_low_part (match_dup 0))
8625 (and:QI (match_dup 1)
8627 (clobber (reg:CC 17))])]
8628 "operands[0] = gen_lowpart (QImode, operands[0]);
8629 operands[1] = gen_lowpart (QImode, operands[1]);
8630 operands[2] = gen_lowpart (QImode, operands[2]);")
8632 ;; Logical inclusive OR instructions
8634 ;; %%% This used to optimize known byte-wide and operations to memory.
8635 ;; If this is considered useful, it should be done with splitters.
8637 (define_expand "iordi3"
8638 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8639 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8640 (match_operand:DI 2 "x86_64_general_operand" "")))
8641 (clobber (reg:CC 17))]
8643 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8645 (define_insn "*iordi_1_rex64"
8646 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8647 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8648 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8649 (clobber (reg:CC 17))]
8651 && ix86_binary_operator_ok (IOR, DImode, operands)"
8652 "or{q}\t{%2, %0|%0, %2}"
8653 [(set_attr "type" "alu")
8654 (set_attr "mode" "DI")])
8656 (define_insn "*iordi_2_rex64"
8658 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8659 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8661 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8662 (ior:DI (match_dup 1) (match_dup 2)))]
8664 && ix86_match_ccmode (insn, CCNOmode)
8665 && ix86_binary_operator_ok (IOR, DImode, operands)"
8666 "or{q}\t{%2, %0|%0, %2}"
8667 [(set_attr "type" "alu")
8668 (set_attr "mode" "DI")])
8670 (define_insn "*iordi_3_rex64"
8672 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8673 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8675 (clobber (match_scratch:DI 0 "=r"))]
8677 && ix86_match_ccmode (insn, CCNOmode)
8678 && ix86_binary_operator_ok (IOR, DImode, operands)"
8679 "or{q}\t{%2, %0|%0, %2}"
8680 [(set_attr "type" "alu")
8681 (set_attr "mode" "DI")])
8684 (define_expand "iorsi3"
8685 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8686 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8687 (match_operand:SI 2 "general_operand" "")))
8688 (clobber (reg:CC 17))]
8690 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8692 (define_insn "*iorsi_1"
8693 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8694 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8695 (match_operand:SI 2 "general_operand" "ri,rmi")))
8696 (clobber (reg:CC 17))]
8697 "ix86_binary_operator_ok (IOR, SImode, operands)"
8698 "or{l}\t{%2, %0|%0, %2}"
8699 [(set_attr "type" "alu")
8700 (set_attr "mode" "SI")])
8702 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8703 (define_insn "*iorsi_1_zext"
8704 [(set (match_operand:DI 0 "register_operand" "=rm")
8706 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8707 (match_operand:SI 2 "general_operand" "rim"))))
8708 (clobber (reg:CC 17))]
8709 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8710 "or{l}\t{%2, %k0|%k0, %2}"
8711 [(set_attr "type" "alu")
8712 (set_attr "mode" "SI")])
8714 (define_insn "*iorsi_1_zext_imm"
8715 [(set (match_operand:DI 0 "register_operand" "=rm")
8716 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8717 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8718 (clobber (reg:CC 17))]
8720 "or{l}\t{%2, %k0|%k0, %2}"
8721 [(set_attr "type" "alu")
8722 (set_attr "mode" "SI")])
8724 (define_insn "*iorsi_2"
8726 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8727 (match_operand:SI 2 "general_operand" "rim,ri"))
8729 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8730 (ior:SI (match_dup 1) (match_dup 2)))]
8731 "ix86_match_ccmode (insn, CCNOmode)
8732 && ix86_binary_operator_ok (IOR, SImode, operands)"
8733 "or{l}\t{%2, %0|%0, %2}"
8734 [(set_attr "type" "alu")
8735 (set_attr "mode" "SI")])
8737 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8738 ;; ??? Special case for immediate operand is missing - it is tricky.
8739 (define_insn "*iorsi_2_zext"
8741 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8742 (match_operand:SI 2 "general_operand" "rim"))
8744 (set (match_operand:DI 0 "register_operand" "=r")
8745 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8746 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8747 && ix86_binary_operator_ok (IOR, SImode, operands)"
8748 "or{l}\t{%2, %k0|%k0, %2}"
8749 [(set_attr "type" "alu")
8750 (set_attr "mode" "SI")])
8752 (define_insn "*iorsi_2_zext_imm"
8754 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8755 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8757 (set (match_operand:DI 0 "register_operand" "=r")
8758 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8759 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8760 && ix86_binary_operator_ok (IOR, SImode, operands)"
8761 "or{l}\t{%2, %k0|%k0, %2}"
8762 [(set_attr "type" "alu")
8763 (set_attr "mode" "SI")])
8765 (define_insn "*iorsi_3"
8767 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8768 (match_operand:SI 2 "general_operand" "rim"))
8770 (clobber (match_scratch:SI 0 "=r"))]
8771 "ix86_match_ccmode (insn, CCNOmode)
8772 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8773 "or{l}\t{%2, %0|%0, %2}"
8774 [(set_attr "type" "alu")
8775 (set_attr "mode" "SI")])
8777 (define_expand "iorhi3"
8778 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8779 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8780 (match_operand:HI 2 "general_operand" "")))
8781 (clobber (reg:CC 17))]
8782 "TARGET_HIMODE_MATH"
8783 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8785 (define_insn "*iorhi_1"
8786 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8787 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8788 (match_operand:HI 2 "general_operand" "rmi,ri")))
8789 (clobber (reg:CC 17))]
8790 "ix86_binary_operator_ok (IOR, HImode, operands)"
8791 "or{w}\t{%2, %0|%0, %2}"
8792 [(set_attr "type" "alu")
8793 (set_attr "mode" "HI")])
8795 (define_insn "*iorhi_2"
8797 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8798 (match_operand:HI 2 "general_operand" "rim,ri"))
8800 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8801 (ior:HI (match_dup 1) (match_dup 2)))]
8802 "ix86_match_ccmode (insn, CCNOmode)
8803 && ix86_binary_operator_ok (IOR, HImode, operands)"
8804 "or{w}\t{%2, %0|%0, %2}"
8805 [(set_attr "type" "alu")
8806 (set_attr "mode" "HI")])
8808 (define_insn "*iorhi_3"
8810 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8811 (match_operand:HI 2 "general_operand" "rim"))
8813 (clobber (match_scratch:HI 0 "=r"))]
8814 "ix86_match_ccmode (insn, CCNOmode)
8815 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8816 "or{w}\t{%2, %0|%0, %2}"
8817 [(set_attr "type" "alu")
8818 (set_attr "mode" "HI")])
8820 (define_expand "iorqi3"
8821 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8822 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8823 (match_operand:QI 2 "general_operand" "")))
8824 (clobber (reg:CC 17))]
8825 "TARGET_QIMODE_MATH"
8826 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8828 ;; %%% Potential partial reg stall on alternative 2. What to do?
8829 (define_insn "*iorqi_1"
8830 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8831 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8832 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8833 (clobber (reg:CC 17))]
8834 "ix86_binary_operator_ok (IOR, QImode, operands)"
8836 or{b}\t{%2, %0|%0, %2}
8837 or{b}\t{%2, %0|%0, %2}
8838 or{l}\t{%k2, %k0|%k0, %k2}"
8839 [(set_attr "type" "alu")
8840 (set_attr "mode" "QI,QI,SI")])
8842 (define_insn "*iorqi_1_slp"
8843 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8844 (ior:QI (match_dup 0)
8845 (match_operand:QI 1 "general_operand" "qmi,qi")))
8846 (clobber (reg:CC 17))]
8847 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8848 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8849 "or{b}\t{%1, %0|%0, %1}"
8850 [(set_attr "type" "alu1")
8851 (set_attr "mode" "QI")])
8853 (define_insn "*iorqi_2"
8855 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8856 (match_operand:QI 2 "general_operand" "qim,qi"))
8858 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8859 (ior:QI (match_dup 1) (match_dup 2)))]
8860 "ix86_match_ccmode (insn, CCNOmode)
8861 && ix86_binary_operator_ok (IOR, QImode, operands)"
8862 "or{b}\t{%2, %0|%0, %2}"
8863 [(set_attr "type" "alu")
8864 (set_attr "mode" "QI")])
8866 (define_insn "*iorqi_2_slp"
8868 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8869 (match_operand:QI 1 "general_operand" "qim,qi"))
8871 (set (strict_low_part (match_dup 0))
8872 (ior:QI (match_dup 0) (match_dup 1)))]
8873 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8874 && ix86_match_ccmode (insn, CCNOmode)
8875 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8876 "or{b}\t{%1, %0|%0, %1}"
8877 [(set_attr "type" "alu1")
8878 (set_attr "mode" "QI")])
8880 (define_insn "*iorqi_3"
8882 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8883 (match_operand:QI 2 "general_operand" "qim"))
8885 (clobber (match_scratch:QI 0 "=q"))]
8886 "ix86_match_ccmode (insn, CCNOmode)
8887 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8888 "or{b}\t{%2, %0|%0, %2}"
8889 [(set_attr "type" "alu")
8890 (set_attr "mode" "QI")])
8892 (define_insn "iorqi_ext_0"
8893 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8898 (match_operand 1 "ext_register_operand" "0")
8901 (match_operand 2 "const_int_operand" "n")))
8902 (clobber (reg:CC 17))]
8903 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8904 "or{b}\t{%2, %h0|%h0, %2}"
8905 [(set_attr "type" "alu")
8906 (set_attr "length_immediate" "1")
8907 (set_attr "mode" "QI")])
8909 (define_insn "*iorqi_ext_1"
8910 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8915 (match_operand 1 "ext_register_operand" "0")
8919 (match_operand:QI 2 "general_operand" "Qm"))))
8920 (clobber (reg:CC 17))]
8922 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8923 "or{b}\t{%2, %h0|%h0, %2}"
8924 [(set_attr "type" "alu")
8925 (set_attr "length_immediate" "0")
8926 (set_attr "mode" "QI")])
8928 (define_insn "*iorqi_ext_1_rex64"
8929 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8934 (match_operand 1 "ext_register_operand" "0")
8938 (match_operand 2 "ext_register_operand" "Q"))))
8939 (clobber (reg:CC 17))]
8941 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8942 "or{b}\t{%2, %h0|%h0, %2}"
8943 [(set_attr "type" "alu")
8944 (set_attr "length_immediate" "0")
8945 (set_attr "mode" "QI")])
8947 (define_insn "*iorqi_ext_2"
8948 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8952 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8955 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8958 (clobber (reg:CC 17))]
8959 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8960 "ior{b}\t{%h2, %h0|%h0, %h2}"
8961 [(set_attr "type" "alu")
8962 (set_attr "length_immediate" "0")
8963 (set_attr "mode" "QI")])
8966 [(set (match_operand 0 "register_operand" "")
8967 (ior (match_operand 1 "register_operand" "")
8968 (match_operand 2 "const_int_operand" "")))
8969 (clobber (reg:CC 17))]
8971 && QI_REG_P (operands[0])
8972 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8973 && !(INTVAL (operands[2]) & ~(255 << 8))
8974 && GET_MODE (operands[0]) != QImode"
8975 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8976 (ior:SI (zero_extract:SI (match_dup 1)
8977 (const_int 8) (const_int 8))
8979 (clobber (reg:CC 17))])]
8980 "operands[0] = gen_lowpart (SImode, operands[0]);
8981 operands[1] = gen_lowpart (SImode, operands[1]);
8982 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8984 ;; Since OR can be encoded with sign extended immediate, this is only
8985 ;; profitable when 7th bit is set.
8987 [(set (match_operand 0 "register_operand" "")
8988 (ior (match_operand 1 "general_operand" "")
8989 (match_operand 2 "const_int_operand" "")))
8990 (clobber (reg:CC 17))]
8992 && ANY_QI_REG_P (operands[0])
8993 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8994 && !(INTVAL (operands[2]) & ~255)
8995 && (INTVAL (operands[2]) & 128)
8996 && GET_MODE (operands[0]) != QImode"
8997 [(parallel [(set (strict_low_part (match_dup 0))
8998 (ior:QI (match_dup 1)
9000 (clobber (reg:CC 17))])]
9001 "operands[0] = gen_lowpart (QImode, operands[0]);
9002 operands[1] = gen_lowpart (QImode, operands[1]);
9003 operands[2] = gen_lowpart (QImode, operands[2]);")
9005 ;; Logical XOR instructions
9007 ;; %%% This used to optimize known byte-wide and operations to memory.
9008 ;; If this is considered useful, it should be done with splitters.
9010 (define_expand "xordi3"
9011 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9012 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
9013 (match_operand:DI 2 "x86_64_general_operand" "")))
9014 (clobber (reg:CC 17))]
9016 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
9018 (define_insn "*xordi_1_rex64"
9019 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
9020 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9021 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
9022 (clobber (reg:CC 17))]
9024 && ix86_binary_operator_ok (XOR, DImode, operands)"
9026 xor{q}\t{%2, %0|%0, %2}
9027 xor{q}\t{%2, %0|%0, %2}"
9028 [(set_attr "type" "alu")
9029 (set_attr "mode" "DI,DI")])
9031 (define_insn "*xordi_2_rex64"
9033 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9034 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
9036 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
9037 (xor:DI (match_dup 1) (match_dup 2)))]
9039 && ix86_match_ccmode (insn, CCNOmode)
9040 && ix86_binary_operator_ok (XOR, DImode, operands)"
9042 xor{q}\t{%2, %0|%0, %2}
9043 xor{q}\t{%2, %0|%0, %2}"
9044 [(set_attr "type" "alu")
9045 (set_attr "mode" "DI,DI")])
9047 (define_insn "*xordi_3_rex64"
9049 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
9050 (match_operand:DI 2 "x86_64_general_operand" "rem"))
9052 (clobber (match_scratch:DI 0 "=r"))]
9054 && ix86_match_ccmode (insn, CCNOmode)
9055 && ix86_binary_operator_ok (XOR, DImode, operands)"
9056 "xor{q}\t{%2, %0|%0, %2}"
9057 [(set_attr "type" "alu")
9058 (set_attr "mode" "DI")])
9060 (define_expand "xorsi3"
9061 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9062 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
9063 (match_operand:SI 2 "general_operand" "")))
9064 (clobber (reg:CC 17))]
9066 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
9068 (define_insn "*xorsi_1"
9069 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
9070 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9071 (match_operand:SI 2 "general_operand" "ri,rm")))
9072 (clobber (reg:CC 17))]
9073 "ix86_binary_operator_ok (XOR, SImode, operands)"
9074 "xor{l}\t{%2, %0|%0, %2}"
9075 [(set_attr "type" "alu")
9076 (set_attr "mode" "SI")])
9078 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9079 ;; Add speccase for immediates
9080 (define_insn "*xorsi_1_zext"
9081 [(set (match_operand:DI 0 "register_operand" "=r")
9083 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9084 (match_operand:SI 2 "general_operand" "rim"))))
9085 (clobber (reg:CC 17))]
9086 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9087 "xor{l}\t{%2, %k0|%k0, %2}"
9088 [(set_attr "type" "alu")
9089 (set_attr "mode" "SI")])
9091 (define_insn "*xorsi_1_zext_imm"
9092 [(set (match_operand:DI 0 "register_operand" "=r")
9093 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
9094 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
9095 (clobber (reg:CC 17))]
9096 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9097 "xor{l}\t{%2, %k0|%k0, %2}"
9098 [(set_attr "type" "alu")
9099 (set_attr "mode" "SI")])
9101 (define_insn "*xorsi_2"
9103 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9104 (match_operand:SI 2 "general_operand" "rim,ri"))
9106 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
9107 (xor:SI (match_dup 1) (match_dup 2)))]
9108 "ix86_match_ccmode (insn, CCNOmode)
9109 && ix86_binary_operator_ok (XOR, SImode, operands)"
9110 "xor{l}\t{%2, %0|%0, %2}"
9111 [(set_attr "type" "alu")
9112 (set_attr "mode" "SI")])
9114 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9115 ;; ??? Special case for immediate operand is missing - it is tricky.
9116 (define_insn "*xorsi_2_zext"
9118 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9119 (match_operand:SI 2 "general_operand" "rim"))
9121 (set (match_operand:DI 0 "register_operand" "=r")
9122 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
9123 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9124 && ix86_binary_operator_ok (XOR, SImode, operands)"
9125 "xor{l}\t{%2, %k0|%k0, %2}"
9126 [(set_attr "type" "alu")
9127 (set_attr "mode" "SI")])
9129 (define_insn "*xorsi_2_zext_imm"
9131 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9132 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
9134 (set (match_operand:DI 0 "register_operand" "=r")
9135 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
9136 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9137 && ix86_binary_operator_ok (XOR, SImode, operands)"
9138 "xor{l}\t{%2, %k0|%k0, %2}"
9139 [(set_attr "type" "alu")
9140 (set_attr "mode" "SI")])
9142 (define_insn "*xorsi_3"
9144 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9145 (match_operand:SI 2 "general_operand" "rim"))
9147 (clobber (match_scratch:SI 0 "=r"))]
9148 "ix86_match_ccmode (insn, CCNOmode)
9149 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9150 "xor{l}\t{%2, %0|%0, %2}"
9151 [(set_attr "type" "alu")
9152 (set_attr "mode" "SI")])
9154 (define_expand "xorhi3"
9155 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9156 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
9157 (match_operand:HI 2 "general_operand" "")))
9158 (clobber (reg:CC 17))]
9159 "TARGET_HIMODE_MATH"
9160 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9162 (define_insn "*xorhi_1"
9163 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9164 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9165 (match_operand:HI 2 "general_operand" "rmi,ri")))
9166 (clobber (reg:CC 17))]
9167 "ix86_binary_operator_ok (XOR, HImode, operands)"
9168 "xor{w}\t{%2, %0|%0, %2}"
9169 [(set_attr "type" "alu")
9170 (set_attr "mode" "HI")])
9172 (define_insn "*xorhi_2"
9174 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9175 (match_operand:HI 2 "general_operand" "rim,ri"))
9177 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9178 (xor:HI (match_dup 1) (match_dup 2)))]
9179 "ix86_match_ccmode (insn, CCNOmode)
9180 && ix86_binary_operator_ok (XOR, HImode, operands)"
9181 "xor{w}\t{%2, %0|%0, %2}"
9182 [(set_attr "type" "alu")
9183 (set_attr "mode" "HI")])
9185 (define_insn "*xorhi_3"
9187 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9188 (match_operand:HI 2 "general_operand" "rim"))
9190 (clobber (match_scratch:HI 0 "=r"))]
9191 "ix86_match_ccmode (insn, CCNOmode)
9192 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9193 "xor{w}\t{%2, %0|%0, %2}"
9194 [(set_attr "type" "alu")
9195 (set_attr "mode" "HI")])
9197 (define_expand "xorqi3"
9198 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9199 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9200 (match_operand:QI 2 "general_operand" "")))
9201 (clobber (reg:CC 17))]
9202 "TARGET_QIMODE_MATH"
9203 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9205 ;; %%% Potential partial reg stall on alternative 2. What to do?
9206 (define_insn "*xorqi_1"
9207 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9208 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9209 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9210 (clobber (reg:CC 17))]
9211 "ix86_binary_operator_ok (XOR, QImode, operands)"
9213 xor{b}\t{%2, %0|%0, %2}
9214 xor{b}\t{%2, %0|%0, %2}
9215 xor{l}\t{%k2, %k0|%k0, %k2}"
9216 [(set_attr "type" "alu")
9217 (set_attr "mode" "QI,QI,SI")])
9219 (define_insn "*xorqi_1_slp"
9220 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
9221 (xor:QI (match_dup 0)
9222 (match_operand:QI 1 "general_operand" "qi,qmi")))
9223 (clobber (reg:CC 17))]
9224 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9225 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9226 "xor{b}\t{%1, %0|%0, %1}"
9227 [(set_attr "type" "alu1")
9228 (set_attr "mode" "QI")])
9230 (define_insn "xorqi_ext_0"
9231 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9236 (match_operand 1 "ext_register_operand" "0")
9239 (match_operand 2 "const_int_operand" "n")))
9240 (clobber (reg:CC 17))]
9241 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9242 "xor{b}\t{%2, %h0|%h0, %2}"
9243 [(set_attr "type" "alu")
9244 (set_attr "length_immediate" "1")
9245 (set_attr "mode" "QI")])
9247 (define_insn "*xorqi_ext_1"
9248 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9253 (match_operand 1 "ext_register_operand" "0")
9257 (match_operand:QI 2 "general_operand" "Qm"))))
9258 (clobber (reg:CC 17))]
9260 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9261 "xor{b}\t{%2, %h0|%h0, %2}"
9262 [(set_attr "type" "alu")
9263 (set_attr "length_immediate" "0")
9264 (set_attr "mode" "QI")])
9266 (define_insn "*xorqi_ext_1_rex64"
9267 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9272 (match_operand 1 "ext_register_operand" "0")
9276 (match_operand 2 "ext_register_operand" "Q"))))
9277 (clobber (reg:CC 17))]
9279 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9280 "xor{b}\t{%2, %h0|%h0, %2}"
9281 [(set_attr "type" "alu")
9282 (set_attr "length_immediate" "0")
9283 (set_attr "mode" "QI")])
9285 (define_insn "*xorqi_ext_2"
9286 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9290 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9293 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9296 (clobber (reg:CC 17))]
9297 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9298 "xor{b}\t{%h2, %h0|%h0, %h2}"
9299 [(set_attr "type" "alu")
9300 (set_attr "length_immediate" "0")
9301 (set_attr "mode" "QI")])
9303 (define_insn "*xorqi_cc_1"
9306 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9307 (match_operand:QI 2 "general_operand" "qim,qi"))
9309 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9310 (xor:QI (match_dup 1) (match_dup 2)))]
9311 "ix86_match_ccmode (insn, CCNOmode)
9312 && ix86_binary_operator_ok (XOR, QImode, operands)"
9313 "xor{b}\t{%2, %0|%0, %2}"
9314 [(set_attr "type" "alu")
9315 (set_attr "mode" "QI")])
9317 (define_insn "*xorqi_2_slp"
9319 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9320 (match_operand:QI 1 "general_operand" "qim,qi"))
9322 (set (strict_low_part (match_dup 0))
9323 (xor:QI (match_dup 0) (match_dup 1)))]
9324 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9325 && ix86_match_ccmode (insn, CCNOmode)
9326 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9327 "xor{b}\t{%1, %0|%0, %1}"
9328 [(set_attr "type" "alu1")
9329 (set_attr "mode" "QI")])
9331 (define_insn "*xorqi_cc_2"
9334 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9335 (match_operand:QI 2 "general_operand" "qim"))
9337 (clobber (match_scratch:QI 0 "=q"))]
9338 "ix86_match_ccmode (insn, CCNOmode)
9339 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9340 "xor{b}\t{%2, %0|%0, %2}"
9341 [(set_attr "type" "alu")
9342 (set_attr "mode" "QI")])
9344 (define_insn "*xorqi_cc_ext_1"
9349 (match_operand 1 "ext_register_operand" "0")
9352 (match_operand:QI 2 "general_operand" "qmn"))
9354 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9358 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9360 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9361 "xor{b}\t{%2, %h0|%h0, %2}"
9362 [(set_attr "type" "alu")
9363 (set_attr "mode" "QI")])
9365 (define_insn "*xorqi_cc_ext_1_rex64"
9370 (match_operand 1 "ext_register_operand" "0")
9373 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9375 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9379 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9381 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9382 "xor{b}\t{%2, %h0|%h0, %2}"
9383 [(set_attr "type" "alu")
9384 (set_attr "mode" "QI")])
9386 (define_expand "xorqi_cc_ext_1"
9392 (match_operand 1 "ext_register_operand" "")
9395 (match_operand:QI 2 "general_operand" ""))
9397 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9401 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9407 [(set (match_operand 0 "register_operand" "")
9408 (xor (match_operand 1 "register_operand" "")
9409 (match_operand 2 "const_int_operand" "")))
9410 (clobber (reg:CC 17))]
9412 && QI_REG_P (operands[0])
9413 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9414 && !(INTVAL (operands[2]) & ~(255 << 8))
9415 && GET_MODE (operands[0]) != QImode"
9416 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9417 (xor:SI (zero_extract:SI (match_dup 1)
9418 (const_int 8) (const_int 8))
9420 (clobber (reg:CC 17))])]
9421 "operands[0] = gen_lowpart (SImode, operands[0]);
9422 operands[1] = gen_lowpart (SImode, operands[1]);
9423 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9425 ;; Since XOR can be encoded with sign extended immediate, this is only
9426 ;; profitable when 7th bit is set.
9428 [(set (match_operand 0 "register_operand" "")
9429 (xor (match_operand 1 "general_operand" "")
9430 (match_operand 2 "const_int_operand" "")))
9431 (clobber (reg:CC 17))]
9433 && ANY_QI_REG_P (operands[0])
9434 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9435 && !(INTVAL (operands[2]) & ~255)
9436 && (INTVAL (operands[2]) & 128)
9437 && GET_MODE (operands[0]) != QImode"
9438 [(parallel [(set (strict_low_part (match_dup 0))
9439 (xor:QI (match_dup 1)
9441 (clobber (reg:CC 17))])]
9442 "operands[0] = gen_lowpart (QImode, operands[0]);
9443 operands[1] = gen_lowpart (QImode, operands[1]);
9444 operands[2] = gen_lowpart (QImode, operands[2]);")
9446 ;; Negation instructions
9448 (define_expand "negdi2"
9449 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9450 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9451 (clobber (reg:CC 17))])]
9453 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9455 (define_insn "*negdi2_1"
9456 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9457 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9458 (clobber (reg:CC 17))]
9460 && ix86_unary_operator_ok (NEG, DImode, operands)"
9464 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9465 (neg:DI (match_operand:DI 1 "general_operand" "")))
9466 (clobber (reg:CC 17))]
9467 "!TARGET_64BIT && reload_completed"
9470 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9471 (set (match_dup 0) (neg:SI (match_dup 2)))])
9474 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
9477 (clobber (reg:CC 17))])
9480 (neg:SI (match_dup 1)))
9481 (clobber (reg:CC 17))])]
9482 "split_di (operands+1, 1, operands+2, operands+3);
9483 split_di (operands+0, 1, operands+0, operands+1);")
9485 (define_insn "*negdi2_1_rex64"
9486 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9487 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9488 (clobber (reg:CC 17))]
9489 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9491 [(set_attr "type" "negnot")
9492 (set_attr "mode" "DI")])
9494 ;; The problem with neg is that it does not perform (compare x 0),
9495 ;; it really performs (compare 0 x), which leaves us with the zero
9496 ;; flag being the only useful item.
9498 (define_insn "*negdi2_cmpz_rex64"
9500 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9502 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9503 (neg:DI (match_dup 1)))]
9504 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9506 [(set_attr "type" "negnot")
9507 (set_attr "mode" "DI")])
9510 (define_expand "negsi2"
9511 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9512 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9513 (clobber (reg:CC 17))])]
9515 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9517 (define_insn "*negsi2_1"
9518 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9519 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9520 (clobber (reg:CC 17))]
9521 "ix86_unary_operator_ok (NEG, SImode, operands)"
9523 [(set_attr "type" "negnot")
9524 (set_attr "mode" "SI")])
9526 ;; Combine is quite creative about this pattern.
9527 (define_insn "*negsi2_1_zext"
9528 [(set (match_operand:DI 0 "register_operand" "=r")
9529 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9532 (clobber (reg:CC 17))]
9533 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9535 [(set_attr "type" "negnot")
9536 (set_attr "mode" "SI")])
9538 ;; The problem with neg is that it does not perform (compare x 0),
9539 ;; it really performs (compare 0 x), which leaves us with the zero
9540 ;; flag being the only useful item.
9542 (define_insn "*negsi2_cmpz"
9544 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9546 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9547 (neg:SI (match_dup 1)))]
9548 "ix86_unary_operator_ok (NEG, SImode, operands)"
9550 [(set_attr "type" "negnot")
9551 (set_attr "mode" "SI")])
9553 (define_insn "*negsi2_cmpz_zext"
9555 (compare:CCZ (lshiftrt:DI
9557 (match_operand:DI 1 "register_operand" "0")
9561 (set (match_operand:DI 0 "register_operand" "=r")
9562 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9565 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9567 [(set_attr "type" "negnot")
9568 (set_attr "mode" "SI")])
9570 (define_expand "neghi2"
9571 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9572 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9573 (clobber (reg:CC 17))])]
9574 "TARGET_HIMODE_MATH"
9575 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9577 (define_insn "*neghi2_1"
9578 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9579 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9580 (clobber (reg:CC 17))]
9581 "ix86_unary_operator_ok (NEG, HImode, operands)"
9583 [(set_attr "type" "negnot")
9584 (set_attr "mode" "HI")])
9586 (define_insn "*neghi2_cmpz"
9588 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9590 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9591 (neg:HI (match_dup 1)))]
9592 "ix86_unary_operator_ok (NEG, HImode, operands)"
9594 [(set_attr "type" "negnot")
9595 (set_attr "mode" "HI")])
9597 (define_expand "negqi2"
9598 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9599 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9600 (clobber (reg:CC 17))])]
9601 "TARGET_QIMODE_MATH"
9602 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9604 (define_insn "*negqi2_1"
9605 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9606 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9607 (clobber (reg:CC 17))]
9608 "ix86_unary_operator_ok (NEG, QImode, operands)"
9610 [(set_attr "type" "negnot")
9611 (set_attr "mode" "QI")])
9613 (define_insn "*negqi2_cmpz"
9615 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9617 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9618 (neg:QI (match_dup 1)))]
9619 "ix86_unary_operator_ok (NEG, QImode, operands)"
9621 [(set_attr "type" "negnot")
9622 (set_attr "mode" "QI")])
9624 ;; Changing of sign for FP values is doable using integer unit too.
9626 (define_expand "negsf2"
9627 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9628 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9629 (clobber (reg:CC 17))])]
9633 /* In case operand is in memory, we will not use SSE. */
9634 if (memory_operand (operands[0], VOIDmode)
9635 && rtx_equal_p (operands[0], operands[1]))
9636 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9639 /* Using SSE is tricky, since we need bitwise negation of -0
9641 rtx reg = gen_reg_rtx (SFmode);
9642 rtx dest = operands[0];
9643 rtx imm = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
9645 operands[1] = force_reg (SFmode, operands[1]);
9646 operands[0] = force_reg (SFmode, operands[0]);
9647 reg = force_reg (V4SFmode,
9648 gen_rtx_CONST_VECTOR (V4SFmode,
9649 gen_rtvec (4, imm, CONST0_RTX (SFmode),
9650 CONST0_RTX (SFmode),
9651 CONST0_RTX (SFmode))));
9652 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9653 if (dest != operands[0])
9654 emit_move_insn (dest, operands[0]);
9658 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9660 (define_insn "negsf2_memory"
9661 [(set (match_operand:SF 0 "memory_operand" "=m")
9662 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9663 (clobber (reg:CC 17))]
9664 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9667 (define_insn "negsf2_ifs"
9668 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9669 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9670 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
9671 (clobber (reg:CC 17))]
9673 && (reload_in_progress || reload_completed
9674 || (register_operand (operands[0], VOIDmode)
9675 && register_operand (operands[1], VOIDmode)))"
9679 [(set (match_operand:SF 0 "memory_operand" "")
9680 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9681 (use (match_operand:SF 2 "" ""))
9682 (clobber (reg:CC 17))]
9684 [(parallel [(set (match_dup 0)
9685 (neg:SF (match_dup 1)))
9686 (clobber (reg:CC 17))])])
9689 [(set (match_operand:SF 0 "register_operand" "")
9690 (neg:SF (match_operand:SF 1 "register_operand" "")))
9691 (use (match_operand:V4SF 2 "" ""))
9692 (clobber (reg:CC 17))]
9693 "reload_completed && !SSE_REG_P (operands[0])"
9694 [(parallel [(set (match_dup 0)
9695 (neg:SF (match_dup 1)))
9696 (clobber (reg:CC 17))])])
9699 [(set (match_operand:SF 0 "register_operand" "")
9700 (neg:SF (match_operand:SF 1 "register_operand" "")))
9701 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
9702 (clobber (reg:CC 17))]
9703 "reload_completed && SSE_REG_P (operands[0])"
9704 [(set (subreg:TI (match_dup 0) 0)
9705 (xor:TI (match_dup 1)
9708 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
9709 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
9710 if (operands_match_p (operands[0], operands[2]))
9714 operands[1] = operands[2];
9720 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9721 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9723 (define_insn "*negsf2_if"
9724 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9725 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9726 (clobber (reg:CC 17))]
9727 "TARGET_80387 && !TARGET_SSE
9728 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9732 [(set (match_operand:SF 0 "fp_register_operand" "")
9733 (neg:SF (match_operand:SF 1 "register_operand" "")))
9734 (clobber (reg:CC 17))]
9735 "TARGET_80387 && reload_completed"
9737 (neg:SF (match_dup 1)))]
9741 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
9742 (neg:SF (match_operand:SF 1 "register_operand" "")))
9743 (clobber (reg:CC 17))]
9744 "TARGET_80387 && reload_completed"
9745 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9746 (clobber (reg:CC 17))])]
9747 "operands[1] = gen_int_mode (0x80000000, SImode);
9748 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9751 [(set (match_operand 0 "memory_operand" "")
9752 (neg (match_operand 1 "memory_operand" "")))
9753 (clobber (reg:CC 17))]
9754 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9755 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9756 (clobber (reg:CC 17))])]
9758 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9760 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9763 operands[0] = adjust_address (operands[0], QImode, size - 1);
9764 operands[1] = gen_int_mode (0x80, QImode);
9767 (define_expand "negdf2"
9768 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9769 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9770 (clobber (reg:CC 17))])]
9774 /* In case operand is in memory, we will not use SSE. */
9775 if (memory_operand (operands[0], VOIDmode)
9776 && rtx_equal_p (operands[0], operands[1]))
9777 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9780 /* Using SSE is tricky, since we need bitwise negation of -0
9783 #if HOST_BITS_PER_WIDE_INT >= 64
9784 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
9786 rtx imm = immed_double_const (0, 0x80000000, DImode);
9788 rtx dest = operands[0];
9790 operands[1] = force_reg (DFmode, operands[1]);
9791 operands[0] = force_reg (DFmode, operands[0]);
9792 imm = gen_lowpart (DFmode, imm);
9793 reg = force_reg (V2DFmode,
9794 gen_rtx_CONST_VECTOR (V2DFmode,
9795 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
9796 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
9797 if (dest != operands[0])
9798 emit_move_insn (dest, operands[0]);
9802 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
9804 (define_insn "negdf2_memory"
9805 [(set (match_operand:DF 0 "memory_operand" "=m")
9806 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
9807 (clobber (reg:CC 17))]
9808 "ix86_unary_operator_ok (NEG, DFmode, operands)"
9811 (define_insn "negdf2_ifs"
9812 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9813 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9814 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
9815 (clobber (reg:CC 17))]
9816 "!TARGET_64BIT && TARGET_SSE2
9817 && (reload_in_progress || reload_completed
9818 || (register_operand (operands[0], VOIDmode)
9819 && register_operand (operands[1], VOIDmode)))"
9822 (define_insn "*negdf2_ifs_rex64"
9823 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,fm#Y")
9824 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
9825 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
9826 (clobber (reg:CC 17))]
9827 "TARGET_64BIT && TARGET_SSE2
9828 && (reload_in_progress || reload_completed
9829 || (register_operand (operands[0], VOIDmode)
9830 && register_operand (operands[1], VOIDmode)))"
9834 [(set (match_operand:DF 0 "memory_operand" "")
9835 (neg:DF (match_operand:DF 1 "memory_operand" "")))
9836 (use (match_operand:V2DF 2 "" ""))
9837 (clobber (reg:CC 17))]
9839 [(parallel [(set (match_dup 0)
9840 (neg:DF (match_dup 1)))
9841 (clobber (reg:CC 17))])])
9844 [(set (match_operand:DF 0 "register_operand" "")
9845 (neg:DF (match_operand:DF 1 "register_operand" "")))
9846 (use (match_operand:V2DF 2 "" ""))
9847 (clobber (reg:CC 17))]
9848 "reload_completed && !SSE_REG_P (operands[0])
9849 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
9850 [(parallel [(set (match_dup 0)
9851 (neg:DF (match_dup 1)))
9852 (clobber (reg:CC 17))])])
9855 [(set (match_operand:DF 0 "register_operand" "")
9856 (neg:DF (match_operand:DF 1 "register_operand" "")))
9857 (use (match_operand:V2DF 2 "" ""))
9858 (clobber (reg:CC 17))]
9859 "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
9860 [(parallel [(set (match_dup 0)
9861 (xor:DI (match_dup 1) (match_dup 2)))
9862 (clobber (reg:CC 17))])]
9863 "operands[0] = gen_lowpart (DImode, operands[0]);
9864 operands[1] = gen_lowpart (DImode, operands[1]);
9865 operands[2] = gen_lowpart (DImode, operands[2]);")
9868 [(set (match_operand:DF 0 "register_operand" "")
9869 (neg:DF (match_operand:DF 1 "register_operand" "")))
9870 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
9871 (clobber (reg:CC 17))]
9872 "reload_completed && SSE_REG_P (operands[0])"
9873 [(set (subreg:TI (match_dup 0) 0)
9874 (xor:TI (match_dup 1)
9877 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
9878 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
9879 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
9880 /* Avoid possible reformatting on the operands. */
9881 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
9882 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
9883 if (operands_match_p (operands[0], operands[2]))
9887 operands[1] = operands[2];
9892 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9893 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9895 (define_insn "*negdf2_if"
9896 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9897 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9898 (clobber (reg:CC 17))]
9899 "!TARGET_64BIT && TARGET_80387
9900 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9903 ;; FIXME: We should to allow integer registers here. Problem is that
9904 ;; we need another scratch register to get constant from.
9905 ;; Forcing constant to mem if no register available in peep2 should be
9906 ;; safe even for PIC mode, because of RIP relative addressing.
9907 (define_insn "*negdf2_if_rex64"
9908 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9909 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9910 (clobber (reg:CC 17))]
9911 "TARGET_64BIT && TARGET_80387
9912 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9916 [(set (match_operand:DF 0 "fp_register_operand" "")
9917 (neg:DF (match_operand:DF 1 "register_operand" "")))
9918 (clobber (reg:CC 17))]
9919 "TARGET_80387 && reload_completed"
9921 (neg:DF (match_dup 1)))]
9925 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
9926 (neg:DF (match_operand:DF 1 "register_operand" "")))
9927 (clobber (reg:CC 17))]
9928 "!TARGET_64BIT && TARGET_80387 && reload_completed"
9929 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
9930 (clobber (reg:CC 17))])]
9931 "operands[4] = gen_int_mode (0x80000000, SImode);
9932 split_di (operands+0, 1, operands+2, operands+3);")
9934 (define_expand "negxf2"
9935 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9936 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9937 (clobber (reg:CC 17))])]
9938 "!TARGET_64BIT && TARGET_80387"
9939 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
9941 (define_expand "negtf2"
9942 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9943 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
9944 (clobber (reg:CC 17))])]
9946 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
9948 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9949 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9951 (define_insn "*negxf2_if"
9952 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9953 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9954 (clobber (reg:CC 17))]
9955 "!TARGET_64BIT && TARGET_80387
9956 && ix86_unary_operator_ok (NEG, XFmode, operands)"
9960 [(set (match_operand:XF 0 "fp_register_operand" "")
9961 (neg:XF (match_operand:XF 1 "register_operand" "")))
9962 (clobber (reg:CC 17))]
9963 "TARGET_80387 && reload_completed"
9965 (neg:XF (match_dup 1)))]
9969 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
9970 (neg:XF (match_operand:XF 1 "register_operand" "")))
9971 (clobber (reg:CC 17))]
9972 "TARGET_80387 && reload_completed"
9973 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9974 (clobber (reg:CC 17))])]
9975 "operands[1] = GEN_INT (0x8000);
9976 operands[0] = gen_rtx_REG (SImode,
9977 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9979 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9980 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9982 (define_insn "*negtf2_if"
9983 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
9984 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
9985 (clobber (reg:CC 17))]
9986 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
9990 [(set (match_operand:TF 0 "fp_register_operand" "")
9991 (neg:TF (match_operand:TF 1 "register_operand" "")))
9992 (clobber (reg:CC 17))]
9993 "TARGET_80387 && reload_completed"
9995 (neg:TF (match_dup 1)))]
9999 [(set (match_operand:TF 0 "register_and_not_fp_reg_operand" "")
10000 (neg:TF (match_operand:TF 1 "register_operand" "")))
10001 (clobber (reg:CC 17))]
10002 "TARGET_80387 && reload_completed"
10003 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
10004 (clobber (reg:CC 17))])]
10005 "operands[1] = GEN_INT (0x8000);
10006 operands[0] = gen_rtx_REG (SImode,
10007 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10009 ;; Conditionalize these after reload. If they matches before reload, we
10010 ;; lose the clobber and ability to use integer instructions.
10012 (define_insn "*negsf2_1"
10013 [(set (match_operand:SF 0 "register_operand" "=f")
10014 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
10015 "TARGET_80387 && reload_completed"
10017 [(set_attr "type" "fsgn")
10018 (set_attr "mode" "SF")
10019 (set_attr "ppro_uops" "few")])
10021 (define_insn "*negdf2_1"
10022 [(set (match_operand:DF 0 "register_operand" "=f")
10023 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
10024 "TARGET_80387 && reload_completed"
10026 [(set_attr "type" "fsgn")
10027 (set_attr "mode" "DF")
10028 (set_attr "ppro_uops" "few")])
10030 (define_insn "*negextendsfdf2"
10031 [(set (match_operand:DF 0 "register_operand" "=f")
10032 (neg:DF (float_extend:DF
10033 (match_operand:SF 1 "register_operand" "0"))))]
10036 [(set_attr "type" "fsgn")
10037 (set_attr "mode" "DF")
10038 (set_attr "ppro_uops" "few")])
10040 (define_insn "*negxf2_1"
10041 [(set (match_operand:XF 0 "register_operand" "=f")
10042 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
10043 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10045 [(set_attr "type" "fsgn")
10046 (set_attr "mode" "XF")
10047 (set_attr "ppro_uops" "few")])
10049 (define_insn "*negextenddfxf2"
10050 [(set (match_operand:XF 0 "register_operand" "=f")
10051 (neg:XF (float_extend:XF
10052 (match_operand:DF 1 "register_operand" "0"))))]
10053 "!TARGET_64BIT && TARGET_80387"
10055 [(set_attr "type" "fsgn")
10056 (set_attr "mode" "XF")
10057 (set_attr "ppro_uops" "few")])
10059 (define_insn "*negextendsfxf2"
10060 [(set (match_operand:XF 0 "register_operand" "=f")
10061 (neg:XF (float_extend:XF
10062 (match_operand:SF 1 "register_operand" "0"))))]
10063 "!TARGET_64BIT && TARGET_80387"
10065 [(set_attr "type" "fsgn")
10066 (set_attr "mode" "XF")
10067 (set_attr "ppro_uops" "few")])
10069 (define_insn "*negtf2_1"
10070 [(set (match_operand:TF 0 "register_operand" "=f")
10071 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
10072 "TARGET_80387 && reload_completed"
10074 [(set_attr "type" "fsgn")
10075 (set_attr "mode" "XF")
10076 (set_attr "ppro_uops" "few")])
10078 (define_insn "*negextenddftf2"
10079 [(set (match_operand:TF 0 "register_operand" "=f")
10080 (neg:TF (float_extend:TF
10081 (match_operand:DF 1 "register_operand" "0"))))]
10084 [(set_attr "type" "fsgn")
10085 (set_attr "mode" "XF")
10086 (set_attr "ppro_uops" "few")])
10088 (define_insn "*negextendsftf2"
10089 [(set (match_operand:TF 0 "register_operand" "=f")
10090 (neg:TF (float_extend:TF
10091 (match_operand:SF 1 "register_operand" "0"))))]
10094 [(set_attr "type" "fsgn")
10095 (set_attr "mode" "XF")
10096 (set_attr "ppro_uops" "few")])
10098 ;; Absolute value instructions
10100 (define_expand "abssf2"
10101 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
10102 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
10103 (clobber (reg:CC 17))])]
10107 /* In case operand is in memory, we will not use SSE. */
10108 if (memory_operand (operands[0], VOIDmode)
10109 && rtx_equal_p (operands[0], operands[1]))
10110 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
10113 /* Using SSE is tricky, since we need bitwise negation of -0
10115 rtx reg = gen_reg_rtx (V4SFmode);
10116 rtx dest = operands[0];
10119 operands[1] = force_reg (SFmode, operands[1]);
10120 operands[0] = force_reg (SFmode, operands[0]);
10121 imm = gen_lowpart (SFmode, gen_int_mode(~0x80000000, SImode));
10122 reg = force_reg (V4SFmode,
10123 gen_rtx_CONST_VECTOR (V4SFmode,
10124 gen_rtvec (4, imm, CONST0_RTX (SFmode),
10125 CONST0_RTX (SFmode),
10126 CONST0_RTX (SFmode))));
10127 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
10128 if (dest != operands[0])
10129 emit_move_insn (dest, operands[0]);
10133 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
10135 (define_insn "abssf2_memory"
10136 [(set (match_operand:SF 0 "memory_operand" "=m")
10137 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
10138 (clobber (reg:CC 17))]
10139 "ix86_unary_operator_ok (ABS, SFmode, operands)"
10142 (define_insn "abssf2_ifs"
10143 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
10144 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
10145 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
10146 (clobber (reg:CC 17))]
10148 && (reload_in_progress || reload_completed
10149 || (register_operand (operands[0], VOIDmode)
10150 && register_operand (operands[1], VOIDmode)))"
10154 [(set (match_operand:SF 0 "memory_operand" "")
10155 (abs:SF (match_operand:SF 1 "memory_operand" "")))
10156 (use (match_operand:V4SF 2 "" ""))
10157 (clobber (reg:CC 17))]
10159 [(parallel [(set (match_dup 0)
10160 (abs:SF (match_dup 1)))
10161 (clobber (reg:CC 17))])])
10164 [(set (match_operand:SF 0 "register_operand" "")
10165 (abs:SF (match_operand:SF 1 "register_operand" "")))
10166 (use (match_operand:V4SF 2 "" ""))
10167 (clobber (reg:CC 17))]
10168 "reload_completed && !SSE_REG_P (operands[0])"
10169 [(parallel [(set (match_dup 0)
10170 (abs:SF (match_dup 1)))
10171 (clobber (reg:CC 17))])])
10174 [(set (match_operand:SF 0 "register_operand" "")
10175 (abs:SF (match_operand:SF 1 "register_operand" "")))
10176 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
10177 (clobber (reg:CC 17))]
10178 "reload_completed && SSE_REG_P (operands[0])"
10179 [(set (subreg:TI (match_dup 0) 0)
10180 (and:TI (match_dup 1)
10183 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
10184 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
10185 if (operands_match_p (operands[0], operands[2]))
10189 operands[1] = operands[2];
10194 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10195 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10197 (define_insn "*abssf2_if"
10198 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
10199 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
10200 (clobber (reg:CC 17))]
10201 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
10205 [(set (match_operand:SF 0 "fp_register_operand" "")
10206 (abs:SF (match_operand:SF 1 "register_operand" "")))
10207 (clobber (reg:CC 17))]
10209 [(set (match_dup 0)
10210 (abs:SF (match_dup 1)))]
10214 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
10215 (abs:SF (match_operand:SF 1 "register_operand" "")))
10216 (clobber (reg:CC 17))]
10217 "TARGET_80387 && reload_completed"
10218 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10219 (clobber (reg:CC 17))])]
10220 "operands[1] = gen_int_mode (~0x80000000, SImode);
10221 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
10224 [(set (match_operand 0 "memory_operand" "")
10225 (abs (match_operand 1 "memory_operand" "")))
10226 (clobber (reg:CC 17))]
10227 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
10228 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
10229 (clobber (reg:CC 17))])]
10231 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
10233 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
10236 operands[0] = adjust_address (operands[0], QImode, size - 1);
10237 operands[1] = gen_int_mode (~0x80, QImode);
10240 (define_expand "absdf2"
10241 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
10242 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
10243 (clobber (reg:CC 17))])]
10247 /* In case operand is in memory, we will not use SSE. */
10248 if (memory_operand (operands[0], VOIDmode)
10249 && rtx_equal_p (operands[0], operands[1]))
10250 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
10253 /* Using SSE is tricky, since we need bitwise negation of -0
10255 rtx reg = gen_reg_rtx (V2DFmode);
10256 #if HOST_BITS_PER_WIDE_INT >= 64
10257 rtx imm = gen_int_mode (~(((HOST_WIDE_INT)1) << 63), DImode);
10259 rtx imm = immed_double_const (~0, ~0x80000000, DImode);
10261 rtx dest = operands[0];
10263 operands[1] = force_reg (DFmode, operands[1]);
10264 operands[0] = force_reg (DFmode, operands[0]);
10266 /* Produce LONG_DOUBLE with the proper immediate argument. */
10267 imm = gen_lowpart (DFmode, imm);
10268 reg = force_reg (V2DFmode,
10269 gen_rtx_CONST_VECTOR (V2DFmode,
10270 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
10271 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
10272 if (dest != operands[0])
10273 emit_move_insn (dest, operands[0]);
10277 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
10279 (define_insn "absdf2_memory"
10280 [(set (match_operand:DF 0 "memory_operand" "=m")
10281 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
10282 (clobber (reg:CC 17))]
10283 "ix86_unary_operator_ok (ABS, DFmode, operands)"
10286 (define_insn "absdf2_ifs"
10287 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr,mr#Yf")
10288 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
10289 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
10290 (clobber (reg:CC 17))]
10291 "!TARGET_64BIT && TARGET_SSE2
10292 && (reload_in_progress || reload_completed
10293 || (register_operand (operands[0], VOIDmode)
10294 && register_operand (operands[1], VOIDmode)))"
10297 (define_insn "*absdf2_ifs_rex64"
10298 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr")
10299 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
10300 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
10301 (clobber (reg:CC 17))]
10302 "TARGET_64BIT && TARGET_SSE2
10303 && (reload_in_progress || reload_completed
10304 || (register_operand (operands[0], VOIDmode)
10305 && register_operand (operands[1], VOIDmode)))"
10309 [(set (match_operand:DF 0 "memory_operand" "")
10310 (abs:DF (match_operand:DF 1 "memory_operand" "")))
10311 (use (match_operand:V2DF 2 "" ""))
10312 (clobber (reg:CC 17))]
10314 [(parallel [(set (match_dup 0)
10315 (abs:DF (match_dup 1)))
10316 (clobber (reg:CC 17))])])
10319 [(set (match_operand:DF 0 "register_operand" "")
10320 (abs:DF (match_operand:DF 1 "register_operand" "")))
10321 (use (match_operand:V2DF 2 "" ""))
10322 (clobber (reg:CC 17))]
10323 "reload_completed && !SSE_REG_P (operands[0])"
10324 [(parallel [(set (match_dup 0)
10325 (abs:DF (match_dup 1)))
10326 (clobber (reg:CC 17))])])
10329 [(set (match_operand:DF 0 "register_operand" "")
10330 (abs:DF (match_operand:DF 1 "register_operand" "")))
10331 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
10332 (clobber (reg:CC 17))]
10333 "reload_completed && SSE_REG_P (operands[0])"
10334 [(set (subreg:TI (match_dup 0) 0)
10335 (and:TI (match_dup 1)
10338 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
10339 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
10340 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
10341 /* Avoid possible reformatting on the operands. */
10342 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
10343 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
10344 if (operands_match_p (operands[0], operands[2]))
10348 operands[1] = operands[2];
10354 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10355 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10357 (define_insn "*absdf2_if"
10358 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10359 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10360 (clobber (reg:CC 17))]
10361 "!TARGET_64BIT && TARGET_80387
10362 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10365 ;; FIXME: We should to allow integer registers here. Problem is that
10366 ;; we need another scratch register to get constant from.
10367 ;; Forcing constant to mem if no register available in peep2 should be
10368 ;; safe even for PIC mode, because of RIP relative addressing.
10369 (define_insn "*absdf2_if_rex64"
10370 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10371 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10372 (clobber (reg:CC 17))]
10373 "TARGET_64BIT && TARGET_80387
10374 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10378 [(set (match_operand:DF 0 "fp_register_operand" "")
10379 (abs:DF (match_operand:DF 1 "register_operand" "")))
10380 (clobber (reg:CC 17))]
10381 "TARGET_80387 && reload_completed"
10382 [(set (match_dup 0)
10383 (abs:DF (match_dup 1)))]
10387 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
10388 (abs:DF (match_operand:DF 1 "register_operand" "")))
10389 (clobber (reg:CC 17))]
10390 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10391 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
10392 (clobber (reg:CC 17))])]
10393 "operands[4] = gen_int_mode (~0x80000000, SImode);
10394 split_di (operands+0, 1, operands+2, operands+3);")
10396 (define_expand "absxf2"
10397 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10398 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10399 (clobber (reg:CC 17))])]
10400 "!TARGET_64BIT && TARGET_80387"
10401 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
10403 (define_expand "abstf2"
10404 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
10405 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
10406 (clobber (reg:CC 17))])]
10408 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
10410 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10411 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10413 (define_insn "*absxf2_if"
10414 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10415 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10416 (clobber (reg:CC 17))]
10417 "!TARGET_64BIT && TARGET_80387
10418 && ix86_unary_operator_ok (ABS, XFmode, operands)"
10422 [(set (match_operand:XF 0 "fp_register_operand" "")
10423 (abs:XF (match_operand:XF 1 "register_operand" "")))
10424 (clobber (reg:CC 17))]
10425 "TARGET_80387 && reload_completed"
10426 [(set (match_dup 0)
10427 (abs:XF (match_dup 1)))]
10431 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
10432 (abs:XF (match_operand:XF 1 "register_operand" "")))
10433 (clobber (reg:CC 17))]
10434 "TARGET_80387 && reload_completed"
10435 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10436 (clobber (reg:CC 17))])]
10437 "operands[1] = GEN_INT (~0x8000);
10438 operands[0] = gen_rtx_REG (SImode,
10439 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10441 (define_insn "*abstf2_if"
10442 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10443 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10444 (clobber (reg:CC 17))]
10445 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
10449 [(set (match_operand:TF 0 "fp_register_operand" "")
10450 (abs:TF (match_operand:TF 1 "register_operand" "")))
10451 (clobber (reg:CC 17))]
10452 "TARGET_80387 && reload_completed"
10453 [(set (match_dup 0)
10454 (abs:TF (match_dup 1)))]
10458 [(set (match_operand:TF 0 "register_and_not_any_fp_reg_operand" "")
10459 (abs:TF (match_operand:TF 1 "register_operand" "")))
10460 (clobber (reg:CC 17))]
10461 "TARGET_80387 && reload_completed"
10462 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10463 (clobber (reg:CC 17))])]
10464 "operands[1] = GEN_INT (~0x8000);
10465 operands[0] = gen_rtx_REG (SImode,
10466 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10468 (define_insn "*abssf2_1"
10469 [(set (match_operand:SF 0 "register_operand" "=f")
10470 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10471 "TARGET_80387 && reload_completed"
10473 [(set_attr "type" "fsgn")
10474 (set_attr "mode" "SF")])
10476 (define_insn "*absdf2_1"
10477 [(set (match_operand:DF 0 "register_operand" "=f")
10478 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10479 "TARGET_80387 && reload_completed"
10481 [(set_attr "type" "fsgn")
10482 (set_attr "mode" "DF")])
10484 (define_insn "*absextendsfdf2"
10485 [(set (match_operand:DF 0 "register_operand" "=f")
10486 (abs:DF (float_extend:DF
10487 (match_operand:SF 1 "register_operand" "0"))))]
10490 [(set_attr "type" "fsgn")
10491 (set_attr "mode" "DF")])
10493 (define_insn "*absxf2_1"
10494 [(set (match_operand:XF 0 "register_operand" "=f")
10495 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10496 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10498 [(set_attr "type" "fsgn")
10499 (set_attr "mode" "DF")])
10501 (define_insn "*absextenddfxf2"
10502 [(set (match_operand:XF 0 "register_operand" "=f")
10503 (abs:XF (float_extend:XF
10504 (match_operand:DF 1 "register_operand" "0"))))]
10505 "!TARGET_64BIT && TARGET_80387"
10507 [(set_attr "type" "fsgn")
10508 (set_attr "mode" "XF")])
10510 (define_insn "*absextendsfxf2"
10511 [(set (match_operand:XF 0 "register_operand" "=f")
10512 (abs:XF (float_extend:XF
10513 (match_operand:SF 1 "register_operand" "0"))))]
10514 "!TARGET_64BIT && TARGET_80387"
10516 [(set_attr "type" "fsgn")
10517 (set_attr "mode" "XF")])
10519 (define_insn "*abstf2_1"
10520 [(set (match_operand:TF 0 "register_operand" "=f")
10521 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
10522 "TARGET_80387 && reload_completed"
10524 [(set_attr "type" "fsgn")
10525 (set_attr "mode" "DF")])
10527 (define_insn "*absextenddftf2"
10528 [(set (match_operand:TF 0 "register_operand" "=f")
10529 (abs:TF (float_extend:TF
10530 (match_operand:DF 1 "register_operand" "0"))))]
10533 [(set_attr "type" "fsgn")
10534 (set_attr "mode" "XF")])
10536 (define_insn "*absextendsftf2"
10537 [(set (match_operand:TF 0 "register_operand" "=f")
10538 (abs:TF (float_extend:TF
10539 (match_operand:SF 1 "register_operand" "0"))))]
10542 [(set_attr "type" "fsgn")
10543 (set_attr "mode" "XF")])
10545 ;; One complement instructions
10547 (define_expand "one_cmpldi2"
10548 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10549 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10551 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10553 (define_insn "*one_cmpldi2_1_rex64"
10554 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10555 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10556 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10558 [(set_attr "type" "negnot")
10559 (set_attr "mode" "DI")])
10561 (define_insn "*one_cmpldi2_2_rex64"
10563 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10565 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10566 (not:DI (match_dup 1)))]
10567 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10568 && ix86_unary_operator_ok (NOT, DImode, operands)"
10570 [(set_attr "type" "alu1")
10571 (set_attr "mode" "DI")])
10575 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10577 (set (match_operand:DI 0 "nonimmediate_operand" "")
10578 (not:DI (match_dup 1)))]
10579 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10580 [(parallel [(set (reg:CCNO 17)
10581 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10584 (xor:DI (match_dup 1) (const_int -1)))])]
10587 (define_expand "one_cmplsi2"
10588 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10589 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10591 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10593 (define_insn "*one_cmplsi2_1"
10594 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10595 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10596 "ix86_unary_operator_ok (NOT, SImode, operands)"
10598 [(set_attr "type" "negnot")
10599 (set_attr "mode" "SI")])
10601 ;; ??? Currently never generated - xor is used instead.
10602 (define_insn "*one_cmplsi2_1_zext"
10603 [(set (match_operand:DI 0 "register_operand" "=r")
10604 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10605 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10607 [(set_attr "type" "negnot")
10608 (set_attr "mode" "SI")])
10610 (define_insn "*one_cmplsi2_2"
10612 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10614 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10615 (not:SI (match_dup 1)))]
10616 "ix86_match_ccmode (insn, CCNOmode)
10617 && ix86_unary_operator_ok (NOT, SImode, operands)"
10619 [(set_attr "type" "alu1")
10620 (set_attr "mode" "SI")])
10624 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10626 (set (match_operand:SI 0 "nonimmediate_operand" "")
10627 (not:SI (match_dup 1)))]
10628 "ix86_match_ccmode (insn, CCNOmode)"
10629 [(parallel [(set (reg:CCNO 17)
10630 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10633 (xor:SI (match_dup 1) (const_int -1)))])]
10636 ;; ??? Currently never generated - xor is used instead.
10637 (define_insn "*one_cmplsi2_2_zext"
10639 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10641 (set (match_operand:DI 0 "register_operand" "=r")
10642 (zero_extend:DI (not:SI (match_dup 1))))]
10643 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10644 && ix86_unary_operator_ok (NOT, SImode, operands)"
10646 [(set_attr "type" "alu1")
10647 (set_attr "mode" "SI")])
10651 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10653 (set (match_operand:DI 0 "register_operand" "")
10654 (zero_extend:DI (not:SI (match_dup 1))))]
10655 "ix86_match_ccmode (insn, CCNOmode)"
10656 [(parallel [(set (reg:CCNO 17)
10657 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10660 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10663 (define_expand "one_cmplhi2"
10664 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10665 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10666 "TARGET_HIMODE_MATH"
10667 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10669 (define_insn "*one_cmplhi2_1"
10670 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10671 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10672 "ix86_unary_operator_ok (NOT, HImode, operands)"
10674 [(set_attr "type" "negnot")
10675 (set_attr "mode" "HI")])
10677 (define_insn "*one_cmplhi2_2"
10679 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10681 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10682 (not:HI (match_dup 1)))]
10683 "ix86_match_ccmode (insn, CCNOmode)
10684 && ix86_unary_operator_ok (NEG, HImode, operands)"
10686 [(set_attr "type" "alu1")
10687 (set_attr "mode" "HI")])
10691 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10693 (set (match_operand:HI 0 "nonimmediate_operand" "")
10694 (not:HI (match_dup 1)))]
10695 "ix86_match_ccmode (insn, CCNOmode)"
10696 [(parallel [(set (reg:CCNO 17)
10697 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10700 (xor:HI (match_dup 1) (const_int -1)))])]
10703 ;; %%% Potential partial reg stall on alternative 1. What to do?
10704 (define_expand "one_cmplqi2"
10705 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10706 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10707 "TARGET_QIMODE_MATH"
10708 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10710 (define_insn "*one_cmplqi2_1"
10711 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10712 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10713 "ix86_unary_operator_ok (NOT, QImode, operands)"
10717 [(set_attr "type" "negnot")
10718 (set_attr "mode" "QI,SI")])
10720 (define_insn "*one_cmplqi2_2"
10722 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10724 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10725 (not:QI (match_dup 1)))]
10726 "ix86_match_ccmode (insn, CCNOmode)
10727 && ix86_unary_operator_ok (NOT, QImode, operands)"
10729 [(set_attr "type" "alu1")
10730 (set_attr "mode" "QI")])
10734 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10736 (set (match_operand:QI 0 "nonimmediate_operand" "")
10737 (not:QI (match_dup 1)))]
10738 "ix86_match_ccmode (insn, CCNOmode)"
10739 [(parallel [(set (reg:CCNO 17)
10740 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10743 (xor:QI (match_dup 1) (const_int -1)))])]
10746 ;; Arithmetic shift instructions
10748 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10749 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10750 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10751 ;; from the assembler input.
10753 ;; This instruction shifts the target reg/mem as usual, but instead of
10754 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10755 ;; is a left shift double, bits are taken from the high order bits of
10756 ;; reg, else if the insn is a shift right double, bits are taken from the
10757 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10758 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10760 ;; Since sh[lr]d does not change the `reg' operand, that is done
10761 ;; separately, making all shifts emit pairs of shift double and normal
10762 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10763 ;; support a 63 bit shift, each shift where the count is in a reg expands
10764 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10766 ;; If the shift count is a constant, we need never emit more than one
10767 ;; shift pair, instead using moves and sign extension for counts greater
10770 (define_expand "ashldi3"
10771 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10772 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10773 (match_operand:QI 2 "nonmemory_operand" "")))
10774 (clobber (reg:CC 17))])]
10777 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10779 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
10782 ix86_expand_binary_operator (ASHIFT, DImode, operands);
10786 (define_insn "*ashldi3_1_rex64"
10787 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10788 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
10789 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10790 (clobber (reg:CC 17))]
10791 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10793 switch (get_attr_type (insn))
10796 if (operands[2] != const1_rtx)
10798 if (!rtx_equal_p (operands[0], operands[1]))
10800 return "add{q}\t{%0, %0|%0, %0}";
10803 if (GET_CODE (operands[2]) != CONST_INT
10804 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10806 operands[1] = gen_rtx_MULT (DImode, operands[1],
10807 GEN_INT (1 << INTVAL (operands[2])));
10808 return "lea{q}\t{%a1, %0|%0, %a1}";
10811 if (REG_P (operands[2]))
10812 return "sal{q}\t{%b2, %0|%0, %b2}";
10813 else if (GET_CODE (operands[2]) == CONST_INT
10814 && INTVAL (operands[2]) == 1
10815 && (TARGET_SHIFT1 || optimize_size))
10816 return "sal{q}\t%0";
10818 return "sal{q}\t{%2, %0|%0, %2}";
10821 [(set (attr "type")
10822 (cond [(eq_attr "alternative" "1")
10823 (const_string "lea")
10824 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10826 (match_operand 0 "register_operand" ""))
10827 (match_operand 2 "const1_operand" ""))
10828 (const_string "alu")
10830 (const_string "ishift")))
10831 (set_attr "mode" "DI")])
10833 ;; Convert lea to the lea pattern to avoid flags dependency.
10835 [(set (match_operand:DI 0 "register_operand" "")
10836 (ashift:DI (match_operand:DI 1 "register_operand" "")
10837 (match_operand:QI 2 "immediate_operand" "")))
10838 (clobber (reg:CC 17))]
10839 "TARGET_64BIT && reload_completed
10840 && true_regnum (operands[0]) != true_regnum (operands[1])"
10841 [(set (match_dup 0)
10842 (mult:DI (match_dup 1)
10844 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
10846 ;; This pattern can't accept a variable shift count, since shifts by
10847 ;; zero don't affect the flags. We assume that shifts by constant
10848 ;; zero are optimized away.
10849 (define_insn "*ashldi3_cmp_rex64"
10852 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10853 (match_operand:QI 2 "immediate_operand" "e"))
10855 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10856 (ashift:DI (match_dup 1) (match_dup 2)))]
10857 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10858 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10860 switch (get_attr_type (insn))
10863 if (operands[2] != const1_rtx)
10865 return "add{q}\t{%0, %0|%0, %0}";
10868 if (REG_P (operands[2]))
10869 return "sal{q}\t{%b2, %0|%0, %b2}";
10870 else if (GET_CODE (operands[2]) == CONST_INT
10871 && INTVAL (operands[2]) == 1
10872 && (TARGET_SHIFT1 || optimize_size))
10873 return "sal{q}\t%0";
10875 return "sal{q}\t{%2, %0|%0, %2}";
10878 [(set (attr "type")
10879 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10881 (match_operand 0 "register_operand" ""))
10882 (match_operand 2 "const1_operand" ""))
10883 (const_string "alu")
10885 (const_string "ishift")))
10886 (set_attr "mode" "DI")])
10888 (define_insn "ashldi3_1"
10889 [(set (match_operand:DI 0 "register_operand" "=r")
10890 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10891 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10892 (clobber (match_scratch:SI 3 "=&r"))
10893 (clobber (reg:CC 17))]
10894 "!TARGET_64BIT && TARGET_CMOVE"
10896 [(set_attr "type" "multi")])
10898 (define_insn "*ashldi3_2"
10899 [(set (match_operand:DI 0 "register_operand" "=r")
10900 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10901 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10902 (clobber (reg:CC 17))]
10905 [(set_attr "type" "multi")])
10908 [(set (match_operand:DI 0 "register_operand" "")
10909 (ashift:DI (match_operand:DI 1 "register_operand" "")
10910 (match_operand:QI 2 "nonmemory_operand" "")))
10911 (clobber (match_scratch:SI 3 ""))
10912 (clobber (reg:CC 17))]
10913 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
10915 "ix86_split_ashldi (operands, operands[3]); DONE;")
10918 [(set (match_operand:DI 0 "register_operand" "")
10919 (ashift:DI (match_operand:DI 1 "register_operand" "")
10920 (match_operand:QI 2 "nonmemory_operand" "")))
10921 (clobber (reg:CC 17))]
10922 "!TARGET_64BIT && reload_completed"
10924 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10926 (define_insn "x86_shld_1"
10927 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10928 (ior:SI (ashift:SI (match_dup 0)
10929 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10930 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10931 (minus:QI (const_int 32) (match_dup 2)))))
10932 (clobber (reg:CC 17))]
10935 shld{l}\t{%2, %1, %0|%0, %1, %2}
10936 shld{l}\t{%s2%1, %0|%0, %1, %2}"
10937 [(set_attr "type" "ishift")
10938 (set_attr "prefix_0f" "1")
10939 (set_attr "mode" "SI")
10940 (set_attr "pent_pair" "np")
10941 (set_attr "athlon_decode" "vector")
10942 (set_attr "ppro_uops" "few")])
10944 (define_expand "x86_shift_adj_1"
10946 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10949 (set (match_operand:SI 0 "register_operand" "")
10950 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10951 (match_operand:SI 1 "register_operand" "")
10954 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10955 (match_operand:SI 3 "register_operand" "r")
10960 (define_expand "x86_shift_adj_2"
10961 [(use (match_operand:SI 0 "register_operand" ""))
10962 (use (match_operand:SI 1 "register_operand" ""))
10963 (use (match_operand:QI 2 "register_operand" ""))]
10966 rtx label = gen_label_rtx ();
10969 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10971 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10972 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10973 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10974 gen_rtx_LABEL_REF (VOIDmode, label),
10976 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10977 JUMP_LABEL (tmp) = label;
10979 emit_move_insn (operands[0], operands[1]);
10980 emit_move_insn (operands[1], const0_rtx);
10982 emit_label (label);
10983 LABEL_NUSES (label) = 1;
10988 (define_expand "ashlsi3"
10989 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10990 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10991 (match_operand:QI 2 "nonmemory_operand" "")))
10992 (clobber (reg:CC 17))]
10994 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10996 (define_insn "*ashlsi3_1"
10997 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10998 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
10999 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11000 (clobber (reg:CC 17))]
11001 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11003 switch (get_attr_type (insn))
11006 if (operands[2] != const1_rtx)
11008 if (!rtx_equal_p (operands[0], operands[1]))
11010 return "add{l}\t{%0, %0|%0, %0}";
11016 if (REG_P (operands[2]))
11017 return "sal{l}\t{%b2, %0|%0, %b2}";
11018 else if (GET_CODE (operands[2]) == CONST_INT
11019 && INTVAL (operands[2]) == 1
11020 && (TARGET_SHIFT1 || optimize_size))
11021 return "sal{l}\t%0";
11023 return "sal{l}\t{%2, %0|%0, %2}";
11026 [(set (attr "type")
11027 (cond [(eq_attr "alternative" "1")
11028 (const_string "lea")
11029 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11031 (match_operand 0 "register_operand" ""))
11032 (match_operand 2 "const1_operand" ""))
11033 (const_string "alu")
11035 (const_string "ishift")))
11036 (set_attr "mode" "SI")])
11038 ;; Convert lea to the lea pattern to avoid flags dependency.
11040 [(set (match_operand 0 "register_operand" "")
11041 (ashift (match_operand 1 "index_register_operand" "")
11042 (match_operand:QI 2 "const_int_operand" "")))
11043 (clobber (reg:CC 17))]
11045 && true_regnum (operands[0]) != true_regnum (operands[1])"
11049 operands[0] = gen_lowpart (SImode, operands[0]);
11050 operands[1] = gen_lowpart (Pmode, operands[1]);
11051 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
11052 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
11053 if (Pmode != SImode)
11054 pat = gen_rtx_SUBREG (SImode, pat, 0);
11055 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
11059 ;; Rare case of shifting RSP is handled by generating move and shift
11061 [(set (match_operand 0 "register_operand" "")
11062 (ashift (match_operand 1 "register_operand" "")
11063 (match_operand:QI 2 "const_int_operand" "")))
11064 (clobber (reg:CC 17))]
11066 && true_regnum (operands[0]) != true_regnum (operands[1])"
11070 emit_move_insn (operands[1], operands[0]);
11071 pat = gen_rtx_SET (VOIDmode, operands[0],
11072 gen_rtx_ASHIFT (GET_MODE (operands[0]),
11073 operands[0], operands[2]));
11074 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11075 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
11079 (define_insn "*ashlsi3_1_zext"
11080 [(set (match_operand:DI 0 "register_operand" "=r,r")
11081 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
11082 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
11083 (clobber (reg:CC 17))]
11084 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11086 switch (get_attr_type (insn))
11089 if (operands[2] != const1_rtx)
11091 return "add{l}\t{%k0, %k0|%k0, %k0}";
11097 if (REG_P (operands[2]))
11098 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11099 else if (GET_CODE (operands[2]) == CONST_INT
11100 && INTVAL (operands[2]) == 1
11101 && (TARGET_SHIFT1 || optimize_size))
11102 return "sal{l}\t%k0";
11104 return "sal{l}\t{%2, %k0|%k0, %2}";
11107 [(set (attr "type")
11108 (cond [(eq_attr "alternative" "1")
11109 (const_string "lea")
11110 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11112 (match_operand 2 "const1_operand" ""))
11113 (const_string "alu")
11115 (const_string "ishift")))
11116 (set_attr "mode" "SI")])
11118 ;; Convert lea to the lea pattern to avoid flags dependency.
11120 [(set (match_operand:DI 0 "register_operand" "")
11121 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
11122 (match_operand:QI 2 "const_int_operand" ""))))
11123 (clobber (reg:CC 17))]
11124 "TARGET_64BIT && reload_completed
11125 && true_regnum (operands[0]) != true_regnum (operands[1])"
11126 [(set (match_dup 0) (zero_extend:DI
11127 (subreg:SI (mult:SI (match_dup 1)
11128 (match_dup 2)) 0)))]
11130 operands[1] = gen_lowpart (Pmode, operands[1]);
11131 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
11134 ;; This pattern can't accept a variable shift count, since shifts by
11135 ;; zero don't affect the flags. We assume that shifts by constant
11136 ;; zero are optimized away.
11137 (define_insn "*ashlsi3_cmp"
11140 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11141 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11143 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11144 (ashift:SI (match_dup 1) (match_dup 2)))]
11145 "ix86_match_ccmode (insn, CCGOCmode)
11146 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11148 switch (get_attr_type (insn))
11151 if (operands[2] != const1_rtx)
11153 return "add{l}\t{%0, %0|%0, %0}";
11156 if (REG_P (operands[2]))
11157 return "sal{l}\t{%b2, %0|%0, %b2}";
11158 else if (GET_CODE (operands[2]) == CONST_INT
11159 && INTVAL (operands[2]) == 1
11160 && (TARGET_SHIFT1 || optimize_size))
11161 return "sal{l}\t%0";
11163 return "sal{l}\t{%2, %0|%0, %2}";
11166 [(set (attr "type")
11167 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11169 (match_operand 0 "register_operand" ""))
11170 (match_operand 2 "const1_operand" ""))
11171 (const_string "alu")
11173 (const_string "ishift")))
11174 (set_attr "mode" "SI")])
11176 (define_insn "*ashlsi3_cmp_zext"
11179 (ashift:SI (match_operand:SI 1 "register_operand" "0")
11180 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11182 (set (match_operand:DI 0 "register_operand" "=r")
11183 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
11184 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11185 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11187 switch (get_attr_type (insn))
11190 if (operands[2] != const1_rtx)
11192 return "add{l}\t{%k0, %k0|%k0, %k0}";
11195 if (REG_P (operands[2]))
11196 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11197 else if (GET_CODE (operands[2]) == CONST_INT
11198 && INTVAL (operands[2]) == 1
11199 && (TARGET_SHIFT1 || optimize_size))
11200 return "sal{l}\t%k0";
11202 return "sal{l}\t{%2, %k0|%k0, %2}";
11205 [(set (attr "type")
11206 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11208 (match_operand 2 "const1_operand" ""))
11209 (const_string "alu")
11211 (const_string "ishift")))
11212 (set_attr "mode" "SI")])
11214 (define_expand "ashlhi3"
11215 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11216 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
11217 (match_operand:QI 2 "nonmemory_operand" "")))
11218 (clobber (reg:CC 17))]
11219 "TARGET_HIMODE_MATH"
11220 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
11222 (define_insn "*ashlhi3_1_lea"
11223 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
11224 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
11225 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11226 (clobber (reg:CC 17))]
11227 "!TARGET_PARTIAL_REG_STALL
11228 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11230 switch (get_attr_type (insn))
11235 if (operands[2] != const1_rtx)
11237 return "add{w}\t{%0, %0|%0, %0}";
11240 if (REG_P (operands[2]))
11241 return "sal{w}\t{%b2, %0|%0, %b2}";
11242 else if (GET_CODE (operands[2]) == CONST_INT
11243 && INTVAL (operands[2]) == 1
11244 && (TARGET_SHIFT1 || optimize_size))
11245 return "sal{w}\t%0";
11247 return "sal{w}\t{%2, %0|%0, %2}";
11250 [(set (attr "type")
11251 (cond [(eq_attr "alternative" "1")
11252 (const_string "lea")
11253 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11255 (match_operand 0 "register_operand" ""))
11256 (match_operand 2 "const1_operand" ""))
11257 (const_string "alu")
11259 (const_string "ishift")))
11260 (set_attr "mode" "HI,SI")])
11262 (define_insn "*ashlhi3_1"
11263 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11264 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11265 (match_operand:QI 2 "nonmemory_operand" "cI")))
11266 (clobber (reg:CC 17))]
11267 "TARGET_PARTIAL_REG_STALL
11268 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11270 switch (get_attr_type (insn))
11273 if (operands[2] != const1_rtx)
11275 return "add{w}\t{%0, %0|%0, %0}";
11278 if (REG_P (operands[2]))
11279 return "sal{w}\t{%b2, %0|%0, %b2}";
11280 else if (GET_CODE (operands[2]) == CONST_INT
11281 && INTVAL (operands[2]) == 1
11282 && (TARGET_SHIFT1 || optimize_size))
11283 return "sal{w}\t%0";
11285 return "sal{w}\t{%2, %0|%0, %2}";
11288 [(set (attr "type")
11289 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11291 (match_operand 0 "register_operand" ""))
11292 (match_operand 2 "const1_operand" ""))
11293 (const_string "alu")
11295 (const_string "ishift")))
11296 (set_attr "mode" "HI")])
11298 ;; This pattern can't accept a variable shift count, since shifts by
11299 ;; zero don't affect the flags. We assume that shifts by constant
11300 ;; zero are optimized away.
11301 (define_insn "*ashlhi3_cmp"
11304 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11305 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11307 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11308 (ashift:HI (match_dup 1) (match_dup 2)))]
11309 "ix86_match_ccmode (insn, CCGOCmode)
11310 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11312 switch (get_attr_type (insn))
11315 if (operands[2] != const1_rtx)
11317 return "add{w}\t{%0, %0|%0, %0}";
11320 if (REG_P (operands[2]))
11321 return "sal{w}\t{%b2, %0|%0, %b2}";
11322 else if (GET_CODE (operands[2]) == CONST_INT
11323 && INTVAL (operands[2]) == 1
11324 && (TARGET_SHIFT1 || optimize_size))
11325 return "sal{w}\t%0";
11327 return "sal{w}\t{%2, %0|%0, %2}";
11330 [(set (attr "type")
11331 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11333 (match_operand 0 "register_operand" ""))
11334 (match_operand 2 "const1_operand" ""))
11335 (const_string "alu")
11337 (const_string "ishift")))
11338 (set_attr "mode" "HI")])
11340 (define_expand "ashlqi3"
11341 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11342 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
11343 (match_operand:QI 2 "nonmemory_operand" "")))
11344 (clobber (reg:CC 17))]
11345 "TARGET_QIMODE_MATH"
11346 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
11348 ;; %%% Potential partial reg stall on alternative 2. What to do?
11350 (define_insn "*ashlqi3_1_lea"
11351 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
11352 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
11353 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
11354 (clobber (reg:CC 17))]
11355 "!TARGET_PARTIAL_REG_STALL
11356 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11358 switch (get_attr_type (insn))
11363 if (operands[2] != const1_rtx)
11365 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11366 return "add{l}\t{%k0, %k0|%k0, %k0}";
11368 return "add{b}\t{%0, %0|%0, %0}";
11371 if (REG_P (operands[2]))
11373 if (get_attr_mode (insn) == MODE_SI)
11374 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11376 return "sal{b}\t{%b2, %0|%0, %b2}";
11378 else if (GET_CODE (operands[2]) == CONST_INT
11379 && INTVAL (operands[2]) == 1
11380 && (TARGET_SHIFT1 || optimize_size))
11382 if (get_attr_mode (insn) == MODE_SI)
11383 return "sal{l}\t%0";
11385 return "sal{b}\t%0";
11389 if (get_attr_mode (insn) == MODE_SI)
11390 return "sal{l}\t{%2, %k0|%k0, %2}";
11392 return "sal{b}\t{%2, %0|%0, %2}";
11396 [(set (attr "type")
11397 (cond [(eq_attr "alternative" "2")
11398 (const_string "lea")
11399 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11401 (match_operand 0 "register_operand" ""))
11402 (match_operand 2 "const1_operand" ""))
11403 (const_string "alu")
11405 (const_string "ishift")))
11406 (set_attr "mode" "QI,SI,SI")])
11408 (define_insn "*ashlqi3_1"
11409 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
11410 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11411 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
11412 (clobber (reg:CC 17))]
11413 "TARGET_PARTIAL_REG_STALL
11414 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11416 switch (get_attr_type (insn))
11419 if (operands[2] != const1_rtx)
11421 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11422 return "add{l}\t{%k0, %k0|%k0, %k0}";
11424 return "add{b}\t{%0, %0|%0, %0}";
11427 if (REG_P (operands[2]))
11429 if (get_attr_mode (insn) == MODE_SI)
11430 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11432 return "sal{b}\t{%b2, %0|%0, %b2}";
11434 else if (GET_CODE (operands[2]) == CONST_INT
11435 && INTVAL (operands[2]) == 1
11436 && (TARGET_SHIFT1 || optimize_size))
11438 if (get_attr_mode (insn) == MODE_SI)
11439 return "sal{l}\t%0";
11441 return "sal{b}\t%0";
11445 if (get_attr_mode (insn) == MODE_SI)
11446 return "sal{l}\t{%2, %k0|%k0, %2}";
11448 return "sal{b}\t{%2, %0|%0, %2}";
11452 [(set (attr "type")
11453 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11455 (match_operand 0 "register_operand" ""))
11456 (match_operand 2 "const1_operand" ""))
11457 (const_string "alu")
11459 (const_string "ishift")))
11460 (set_attr "mode" "QI,SI")])
11462 ;; This pattern can't accept a variable shift count, since shifts by
11463 ;; zero don't affect the flags. We assume that shifts by constant
11464 ;; zero are optimized away.
11465 (define_insn "*ashlqi3_cmp"
11468 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11469 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11471 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11472 (ashift:QI (match_dup 1) (match_dup 2)))]
11473 "ix86_match_ccmode (insn, CCGOCmode)
11474 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11476 switch (get_attr_type (insn))
11479 if (operands[2] != const1_rtx)
11481 return "add{b}\t{%0, %0|%0, %0}";
11484 if (REG_P (operands[2]))
11485 return "sal{b}\t{%b2, %0|%0, %b2}";
11486 else if (GET_CODE (operands[2]) == CONST_INT
11487 && INTVAL (operands[2]) == 1
11488 && (TARGET_SHIFT1 || optimize_size))
11489 return "sal{b}\t%0";
11491 return "sal{b}\t{%2, %0|%0, %2}";
11494 [(set (attr "type")
11495 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11497 (match_operand 0 "register_operand" ""))
11498 (match_operand 2 "const1_operand" ""))
11499 (const_string "alu")
11501 (const_string "ishift")))
11502 (set_attr "mode" "QI")])
11504 ;; See comment above `ashldi3' about how this works.
11506 (define_expand "ashrdi3"
11507 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11508 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11509 (match_operand:QI 2 "nonmemory_operand" "")))
11510 (clobber (reg:CC 17))])]
11513 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11515 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
11518 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
11522 (define_insn "ashrdi3_63_rex64"
11523 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11524 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11525 (match_operand:DI 2 "const_int_operand" "i,i")))
11526 (clobber (reg:CC 17))]
11527 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
11528 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11531 sar{q}\t{%2, %0|%0, %2}"
11532 [(set_attr "type" "imovx,ishift")
11533 (set_attr "prefix_0f" "0,*")
11534 (set_attr "length_immediate" "0,*")
11535 (set_attr "modrm" "0,1")
11536 (set_attr "mode" "DI")])
11538 (define_insn "*ashrdi3_1_one_bit_rex64"
11539 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11540 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11541 (match_operand:QI 2 "const_int_1_operand" "")))
11542 (clobber (reg:CC 17))]
11543 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11544 && (TARGET_SHIFT1 || optimize_size)"
11546 [(set_attr "type" "ishift")
11547 (set (attr "length")
11548 (if_then_else (match_operand:DI 0 "register_operand" "")
11550 (const_string "*")))])
11552 (define_insn "*ashrdi3_1_rex64"
11553 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11554 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11555 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11556 (clobber (reg:CC 17))]
11557 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11559 sar{q}\t{%2, %0|%0, %2}
11560 sar{q}\t{%b2, %0|%0, %b2}"
11561 [(set_attr "type" "ishift")
11562 (set_attr "mode" "DI")])
11564 ;; This pattern can't accept a variable shift count, since shifts by
11565 ;; zero don't affect the flags. We assume that shifts by constant
11566 ;; zero are optimized away.
11567 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11570 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11571 (match_operand:QI 2 "const_int_1_operand" ""))
11573 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11574 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11575 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11576 && (TARGET_SHIFT1 || optimize_size)
11577 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11579 [(set_attr "type" "ishift")
11580 (set (attr "length")
11581 (if_then_else (match_operand:DI 0 "register_operand" "")
11583 (const_string "*")))])
11585 ;; This pattern can't accept a variable shift count, since shifts by
11586 ;; zero don't affect the flags. We assume that shifts by constant
11587 ;; zero are optimized away.
11588 (define_insn "*ashrdi3_cmp_rex64"
11591 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11592 (match_operand:QI 2 "const_int_operand" "n"))
11594 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11595 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11596 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11597 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11598 "sar{q}\t{%2, %0|%0, %2}"
11599 [(set_attr "type" "ishift")
11600 (set_attr "mode" "DI")])
11603 (define_insn "ashrdi3_1"
11604 [(set (match_operand:DI 0 "register_operand" "=r")
11605 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11606 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11607 (clobber (match_scratch:SI 3 "=&r"))
11608 (clobber (reg:CC 17))]
11609 "!TARGET_64BIT && TARGET_CMOVE"
11611 [(set_attr "type" "multi")])
11613 (define_insn "*ashrdi3_2"
11614 [(set (match_operand:DI 0 "register_operand" "=r")
11615 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11616 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11617 (clobber (reg:CC 17))]
11620 [(set_attr "type" "multi")])
11623 [(set (match_operand:DI 0 "register_operand" "")
11624 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11625 (match_operand:QI 2 "nonmemory_operand" "")))
11626 (clobber (match_scratch:SI 3 ""))
11627 (clobber (reg:CC 17))]
11628 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11630 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11633 [(set (match_operand:DI 0 "register_operand" "")
11634 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11635 (match_operand:QI 2 "nonmemory_operand" "")))
11636 (clobber (reg:CC 17))]
11637 "!TARGET_64BIT && reload_completed"
11639 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11641 (define_insn "x86_shrd_1"
11642 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11643 (ior:SI (ashiftrt:SI (match_dup 0)
11644 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11645 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11646 (minus:QI (const_int 32) (match_dup 2)))))
11647 (clobber (reg:CC 17))]
11650 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11651 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11652 [(set_attr "type" "ishift")
11653 (set_attr "prefix_0f" "1")
11654 (set_attr "pent_pair" "np")
11655 (set_attr "ppro_uops" "few")
11656 (set_attr "mode" "SI")])
11658 (define_expand "x86_shift_adj_3"
11659 [(use (match_operand:SI 0 "register_operand" ""))
11660 (use (match_operand:SI 1 "register_operand" ""))
11661 (use (match_operand:QI 2 "register_operand" ""))]
11664 rtx label = gen_label_rtx ();
11667 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11669 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11670 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11671 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11672 gen_rtx_LABEL_REF (VOIDmode, label),
11674 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11675 JUMP_LABEL (tmp) = label;
11677 emit_move_insn (operands[0], operands[1]);
11678 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11680 emit_label (label);
11681 LABEL_NUSES (label) = 1;
11686 (define_insn "ashrsi3_31"
11687 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11688 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11689 (match_operand:SI 2 "const_int_operand" "i,i")))
11690 (clobber (reg:CC 17))]
11691 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11692 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11695 sar{l}\t{%2, %0|%0, %2}"
11696 [(set_attr "type" "imovx,ishift")
11697 (set_attr "prefix_0f" "0,*")
11698 (set_attr "length_immediate" "0,*")
11699 (set_attr "modrm" "0,1")
11700 (set_attr "mode" "SI")])
11702 (define_insn "*ashrsi3_31_zext"
11703 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11704 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11705 (match_operand:SI 2 "const_int_operand" "i,i"))))
11706 (clobber (reg:CC 17))]
11707 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11708 && INTVAL (operands[2]) == 31
11709 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11712 sar{l}\t{%2, %k0|%k0, %2}"
11713 [(set_attr "type" "imovx,ishift")
11714 (set_attr "prefix_0f" "0,*")
11715 (set_attr "length_immediate" "0,*")
11716 (set_attr "modrm" "0,1")
11717 (set_attr "mode" "SI")])
11719 (define_expand "ashrsi3"
11720 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11721 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11722 (match_operand:QI 2 "nonmemory_operand" "")))
11723 (clobber (reg:CC 17))]
11725 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11727 (define_insn "*ashrsi3_1_one_bit"
11728 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11729 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11730 (match_operand:QI 2 "const_int_1_operand" "")))
11731 (clobber (reg:CC 17))]
11732 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11733 && (TARGET_SHIFT1 || optimize_size)"
11735 [(set_attr "type" "ishift")
11736 (set (attr "length")
11737 (if_then_else (match_operand:SI 0 "register_operand" "")
11739 (const_string "*")))])
11741 (define_insn "*ashrsi3_1_one_bit_zext"
11742 [(set (match_operand:DI 0 "register_operand" "=r")
11743 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11744 (match_operand:QI 2 "const_int_1_operand" ""))))
11745 (clobber (reg:CC 17))]
11746 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11747 && (TARGET_SHIFT1 || optimize_size)"
11749 [(set_attr "type" "ishift")
11750 (set_attr "length" "2")])
11752 (define_insn "*ashrsi3_1"
11753 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11754 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11755 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11756 (clobber (reg:CC 17))]
11757 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11759 sar{l}\t{%2, %0|%0, %2}
11760 sar{l}\t{%b2, %0|%0, %b2}"
11761 [(set_attr "type" "ishift")
11762 (set_attr "mode" "SI")])
11764 (define_insn "*ashrsi3_1_zext"
11765 [(set (match_operand:DI 0 "register_operand" "=r,r")
11766 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11767 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11768 (clobber (reg:CC 17))]
11769 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11771 sar{l}\t{%2, %k0|%k0, %2}
11772 sar{l}\t{%b2, %k0|%k0, %b2}"
11773 [(set_attr "type" "ishift")
11774 (set_attr "mode" "SI")])
11776 ;; This pattern can't accept a variable shift count, since shifts by
11777 ;; zero don't affect the flags. We assume that shifts by constant
11778 ;; zero are optimized away.
11779 (define_insn "*ashrsi3_one_bit_cmp"
11782 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11783 (match_operand:QI 2 "const_int_1_operand" ""))
11785 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11786 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11787 "ix86_match_ccmode (insn, CCGOCmode)
11788 && (TARGET_SHIFT1 || optimize_size)
11789 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11791 [(set_attr "type" "ishift")
11792 (set (attr "length")
11793 (if_then_else (match_operand:SI 0 "register_operand" "")
11795 (const_string "*")))])
11797 (define_insn "*ashrsi3_one_bit_cmp_zext"
11800 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11801 (match_operand:QI 2 "const_int_1_operand" ""))
11803 (set (match_operand:DI 0 "register_operand" "=r")
11804 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11805 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11806 && (TARGET_SHIFT1 || optimize_size)
11807 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11809 [(set_attr "type" "ishift")
11810 (set_attr "length" "2")])
11812 ;; This pattern can't accept a variable shift count, since shifts by
11813 ;; zero don't affect the flags. We assume that shifts by constant
11814 ;; zero are optimized away.
11815 (define_insn "*ashrsi3_cmp"
11818 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11819 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11821 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11822 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11823 "ix86_match_ccmode (insn, CCGOCmode)
11824 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11825 "sar{l}\t{%2, %0|%0, %2}"
11826 [(set_attr "type" "ishift")
11827 (set_attr "mode" "SI")])
11829 (define_insn "*ashrsi3_cmp_zext"
11832 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11833 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11835 (set (match_operand:DI 0 "register_operand" "=r")
11836 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11837 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11838 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11839 "sar{l}\t{%2, %k0|%k0, %2}"
11840 [(set_attr "type" "ishift")
11841 (set_attr "mode" "SI")])
11843 (define_expand "ashrhi3"
11844 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11845 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11846 (match_operand:QI 2 "nonmemory_operand" "")))
11847 (clobber (reg:CC 17))]
11848 "TARGET_HIMODE_MATH"
11849 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11851 (define_insn "*ashrhi3_1_one_bit"
11852 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11853 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11854 (match_operand:QI 2 "const_int_1_operand" "")))
11855 (clobber (reg:CC 17))]
11856 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11857 && (TARGET_SHIFT1 || optimize_size)"
11859 [(set_attr "type" "ishift")
11860 (set (attr "length")
11861 (if_then_else (match_operand 0 "register_operand" "")
11863 (const_string "*")))])
11865 (define_insn "*ashrhi3_1"
11866 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11867 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11868 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11869 (clobber (reg:CC 17))]
11870 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11872 sar{w}\t{%2, %0|%0, %2}
11873 sar{w}\t{%b2, %0|%0, %b2}"
11874 [(set_attr "type" "ishift")
11875 (set_attr "mode" "HI")])
11877 ;; This pattern can't accept a variable shift count, since shifts by
11878 ;; zero don't affect the flags. We assume that shifts by constant
11879 ;; zero are optimized away.
11880 (define_insn "*ashrhi3_one_bit_cmp"
11883 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11884 (match_operand:QI 2 "const_int_1_operand" ""))
11886 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11887 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11888 "ix86_match_ccmode (insn, CCGOCmode)
11889 && (TARGET_SHIFT1 || optimize_size)
11890 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11892 [(set_attr "type" "ishift")
11893 (set (attr "length")
11894 (if_then_else (match_operand 0 "register_operand" "")
11896 (const_string "*")))])
11898 ;; This pattern can't accept a variable shift count, since shifts by
11899 ;; zero don't affect the flags. We assume that shifts by constant
11900 ;; zero are optimized away.
11901 (define_insn "*ashrhi3_cmp"
11904 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11905 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11907 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11908 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11909 "ix86_match_ccmode (insn, CCGOCmode)
11910 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11911 "sar{w}\t{%2, %0|%0, %2}"
11912 [(set_attr "type" "ishift")
11913 (set_attr "mode" "HI")])
11915 (define_expand "ashrqi3"
11916 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11917 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11918 (match_operand:QI 2 "nonmemory_operand" "")))
11919 (clobber (reg:CC 17))]
11920 "TARGET_QIMODE_MATH"
11921 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11923 (define_insn "*ashrqi3_1_one_bit"
11924 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11925 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11926 (match_operand:QI 2 "const_int_1_operand" "")))
11927 (clobber (reg:CC 17))]
11928 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11929 && (TARGET_SHIFT1 || optimize_size)"
11931 [(set_attr "type" "ishift")
11932 (set (attr "length")
11933 (if_then_else (match_operand 0 "register_operand" "")
11935 (const_string "*")))])
11937 (define_insn "*ashrqi3_1_one_bit_slp"
11938 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11939 (ashiftrt:QI (match_dup 0)
11940 (match_operand:QI 1 "const_int_1_operand" "")))
11941 (clobber (reg:CC 17))]
11942 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11943 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
11944 && (TARGET_SHIFT1 || optimize_size)"
11946 [(set_attr "type" "ishift1")
11947 (set (attr "length")
11948 (if_then_else (match_operand 0 "register_operand" "")
11950 (const_string "*")))])
11952 (define_insn "*ashrqi3_1"
11953 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11954 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11955 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11956 (clobber (reg:CC 17))]
11957 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11959 sar{b}\t{%2, %0|%0, %2}
11960 sar{b}\t{%b2, %0|%0, %b2}"
11961 [(set_attr "type" "ishift")
11962 (set_attr "mode" "QI")])
11964 (define_insn "*ashrqi3_1_slp"
11965 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11966 (ashiftrt:QI (match_dup 0)
11967 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11968 (clobber (reg:CC 17))]
11969 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11970 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11972 sar{b}\t{%1, %0|%0, %1}
11973 sar{b}\t{%b1, %0|%0, %b1}"
11974 [(set_attr "type" "ishift1")
11975 (set_attr "mode" "QI")])
11977 ;; This pattern can't accept a variable shift count, since shifts by
11978 ;; zero don't affect the flags. We assume that shifts by constant
11979 ;; zero are optimized away.
11980 (define_insn "*ashrqi3_one_bit_cmp"
11983 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11984 (match_operand:QI 2 "const_int_1_operand" "I"))
11986 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11987 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11988 "ix86_match_ccmode (insn, CCGOCmode)
11989 && (TARGET_SHIFT1 || optimize_size)
11990 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11992 [(set_attr "type" "ishift")
11993 (set (attr "length")
11994 (if_then_else (match_operand 0 "register_operand" "")
11996 (const_string "*")))])
11998 ;; This pattern can't accept a variable shift count, since shifts by
11999 ;; zero don't affect the flags. We assume that shifts by constant
12000 ;; zero are optimized away.
12001 (define_insn "*ashrqi3_cmp"
12004 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12005 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12007 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12008 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
12009 "ix86_match_ccmode (insn, CCGOCmode)
12010 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12011 "sar{b}\t{%2, %0|%0, %2}"
12012 [(set_attr "type" "ishift")
12013 (set_attr "mode" "QI")])
12015 ;; Logical shift instructions
12017 ;; See comment above `ashldi3' about how this works.
12019 (define_expand "lshrdi3"
12020 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
12021 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
12022 (match_operand:QI 2 "nonmemory_operand" "")))
12023 (clobber (reg:CC 17))])]
12026 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
12028 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
12031 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
12035 (define_insn "*lshrdi3_1_one_bit_rex64"
12036 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12037 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12038 (match_operand:QI 2 "const_int_1_operand" "")))
12039 (clobber (reg:CC 17))]
12040 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12041 && (TARGET_SHIFT1 || optimize_size)"
12043 [(set_attr "type" "ishift")
12044 (set (attr "length")
12045 (if_then_else (match_operand:DI 0 "register_operand" "")
12047 (const_string "*")))])
12049 (define_insn "*lshrdi3_1_rex64"
12050 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12051 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12052 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12053 (clobber (reg:CC 17))]
12054 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12056 shr{q}\t{%2, %0|%0, %2}
12057 shr{q}\t{%b2, %0|%0, %b2}"
12058 [(set_attr "type" "ishift")
12059 (set_attr "mode" "DI")])
12061 ;; This pattern can't accept a variable shift count, since shifts by
12062 ;; zero don't affect the flags. We assume that shifts by constant
12063 ;; zero are optimized away.
12064 (define_insn "*lshrdi3_cmp_one_bit_rex64"
12067 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12068 (match_operand:QI 2 "const_int_1_operand" ""))
12070 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12071 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
12072 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12073 && (TARGET_SHIFT1 || optimize_size)
12074 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12076 [(set_attr "type" "ishift")
12077 (set (attr "length")
12078 (if_then_else (match_operand:DI 0 "register_operand" "")
12080 (const_string "*")))])
12082 ;; This pattern can't accept a variable shift count, since shifts by
12083 ;; zero don't affect the flags. We assume that shifts by constant
12084 ;; zero are optimized away.
12085 (define_insn "*lshrdi3_cmp_rex64"
12088 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12089 (match_operand:QI 2 "const_int_operand" "e"))
12091 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12092 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
12093 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12094 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12095 "shr{q}\t{%2, %0|%0, %2}"
12096 [(set_attr "type" "ishift")
12097 (set_attr "mode" "DI")])
12099 (define_insn "lshrdi3_1"
12100 [(set (match_operand:DI 0 "register_operand" "=r")
12101 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
12102 (match_operand:QI 2 "nonmemory_operand" "Jc")))
12103 (clobber (match_scratch:SI 3 "=&r"))
12104 (clobber (reg:CC 17))]
12105 "!TARGET_64BIT && TARGET_CMOVE"
12107 [(set_attr "type" "multi")])
12109 (define_insn "*lshrdi3_2"
12110 [(set (match_operand:DI 0 "register_operand" "=r")
12111 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
12112 (match_operand:QI 2 "nonmemory_operand" "Jc")))
12113 (clobber (reg:CC 17))]
12116 [(set_attr "type" "multi")])
12119 [(set (match_operand:DI 0 "register_operand" "")
12120 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
12121 (match_operand:QI 2 "nonmemory_operand" "")))
12122 (clobber (match_scratch:SI 3 ""))
12123 (clobber (reg:CC 17))]
12124 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
12126 "ix86_split_lshrdi (operands, operands[3]); DONE;")
12129 [(set (match_operand:DI 0 "register_operand" "")
12130 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
12131 (match_operand:QI 2 "nonmemory_operand" "")))
12132 (clobber (reg:CC 17))]
12133 "!TARGET_64BIT && reload_completed"
12135 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
12137 (define_expand "lshrsi3"
12138 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12139 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
12140 (match_operand:QI 2 "nonmemory_operand" "")))
12141 (clobber (reg:CC 17))]
12143 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
12145 (define_insn "*lshrsi3_1_one_bit"
12146 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12147 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12148 (match_operand:QI 2 "const_int_1_operand" "")))
12149 (clobber (reg:CC 17))]
12150 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12151 && (TARGET_SHIFT1 || optimize_size)"
12153 [(set_attr "type" "ishift")
12154 (set (attr "length")
12155 (if_then_else (match_operand:SI 0 "register_operand" "")
12157 (const_string "*")))])
12159 (define_insn "*lshrsi3_1_one_bit_zext"
12160 [(set (match_operand:DI 0 "register_operand" "=r")
12161 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
12162 (match_operand:QI 2 "const_int_1_operand" "")))
12163 (clobber (reg:CC 17))]
12164 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12165 && (TARGET_SHIFT1 || optimize_size)"
12167 [(set_attr "type" "ishift")
12168 (set_attr "length" "2")])
12170 (define_insn "*lshrsi3_1"
12171 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12172 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12173 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12174 (clobber (reg:CC 17))]
12175 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12177 shr{l}\t{%2, %0|%0, %2}
12178 shr{l}\t{%b2, %0|%0, %b2}"
12179 [(set_attr "type" "ishift")
12180 (set_attr "mode" "SI")])
12182 (define_insn "*lshrsi3_1_zext"
12183 [(set (match_operand:DI 0 "register_operand" "=r,r")
12185 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12186 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12187 (clobber (reg:CC 17))]
12188 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12190 shr{l}\t{%2, %k0|%k0, %2}
12191 shr{l}\t{%b2, %k0|%k0, %b2}"
12192 [(set_attr "type" "ishift")
12193 (set_attr "mode" "SI")])
12195 ;; This pattern can't accept a variable shift count, since shifts by
12196 ;; zero don't affect the flags. We assume that shifts by constant
12197 ;; zero are optimized away.
12198 (define_insn "*lshrsi3_one_bit_cmp"
12201 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12202 (match_operand:QI 2 "const_int_1_operand" ""))
12204 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12205 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12206 "ix86_match_ccmode (insn, CCGOCmode)
12207 && (TARGET_SHIFT1 || optimize_size)
12208 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12210 [(set_attr "type" "ishift")
12211 (set (attr "length")
12212 (if_then_else (match_operand:SI 0 "register_operand" "")
12214 (const_string "*")))])
12216 (define_insn "*lshrsi3_cmp_one_bit_zext"
12219 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12220 (match_operand:QI 2 "const_int_1_operand" ""))
12222 (set (match_operand:DI 0 "register_operand" "=r")
12223 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12224 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12225 && (TARGET_SHIFT1 || optimize_size)
12226 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12228 [(set_attr "type" "ishift")
12229 (set_attr "length" "2")])
12231 ;; This pattern can't accept a variable shift count, since shifts by
12232 ;; zero don't affect the flags. We assume that shifts by constant
12233 ;; zero are optimized away.
12234 (define_insn "*lshrsi3_cmp"
12237 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12238 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12240 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12241 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12242 "ix86_match_ccmode (insn, CCGOCmode)
12243 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12244 "shr{l}\t{%2, %0|%0, %2}"
12245 [(set_attr "type" "ishift")
12246 (set_attr "mode" "SI")])
12248 (define_insn "*lshrsi3_cmp_zext"
12251 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12252 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12254 (set (match_operand:DI 0 "register_operand" "=r")
12255 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12256 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12257 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12258 "shr{l}\t{%2, %k0|%k0, %2}"
12259 [(set_attr "type" "ishift")
12260 (set_attr "mode" "SI")])
12262 (define_expand "lshrhi3"
12263 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12264 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
12265 (match_operand:QI 2 "nonmemory_operand" "")))
12266 (clobber (reg:CC 17))]
12267 "TARGET_HIMODE_MATH"
12268 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
12270 (define_insn "*lshrhi3_1_one_bit"
12271 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12272 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12273 (match_operand:QI 2 "const_int_1_operand" "")))
12274 (clobber (reg:CC 17))]
12275 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12276 && (TARGET_SHIFT1 || optimize_size)"
12278 [(set_attr "type" "ishift")
12279 (set (attr "length")
12280 (if_then_else (match_operand 0 "register_operand" "")
12282 (const_string "*")))])
12284 (define_insn "*lshrhi3_1"
12285 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12286 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12287 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12288 (clobber (reg:CC 17))]
12289 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12291 shr{w}\t{%2, %0|%0, %2}
12292 shr{w}\t{%b2, %0|%0, %b2}"
12293 [(set_attr "type" "ishift")
12294 (set_attr "mode" "HI")])
12296 ;; This pattern can't accept a variable shift count, since shifts by
12297 ;; zero don't affect the flags. We assume that shifts by constant
12298 ;; zero are optimized away.
12299 (define_insn "*lshrhi3_one_bit_cmp"
12302 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12303 (match_operand:QI 2 "const_int_1_operand" ""))
12305 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12306 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12307 "ix86_match_ccmode (insn, CCGOCmode)
12308 && (TARGET_SHIFT1 || optimize_size)
12309 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12311 [(set_attr "type" "ishift")
12312 (set (attr "length")
12313 (if_then_else (match_operand:SI 0 "register_operand" "")
12315 (const_string "*")))])
12317 ;; This pattern can't accept a variable shift count, since shifts by
12318 ;; zero don't affect the flags. We assume that shifts by constant
12319 ;; zero are optimized away.
12320 (define_insn "*lshrhi3_cmp"
12323 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12324 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12326 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12327 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12328 "ix86_match_ccmode (insn, CCGOCmode)
12329 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12330 "shr{w}\t{%2, %0|%0, %2}"
12331 [(set_attr "type" "ishift")
12332 (set_attr "mode" "HI")])
12334 (define_expand "lshrqi3"
12335 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12336 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
12337 (match_operand:QI 2 "nonmemory_operand" "")))
12338 (clobber (reg:CC 17))]
12339 "TARGET_QIMODE_MATH"
12340 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
12342 (define_insn "*lshrqi3_1_one_bit"
12343 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12344 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12345 (match_operand:QI 2 "const_int_1_operand" "")))
12346 (clobber (reg:CC 17))]
12347 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
12348 && (TARGET_SHIFT1 || optimize_size)"
12350 [(set_attr "type" "ishift")
12351 (set (attr "length")
12352 (if_then_else (match_operand 0 "register_operand" "")
12354 (const_string "*")))])
12356 (define_insn "*lshrqi3_1_one_bit_slp"
12357 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12358 (lshiftrt:QI (match_dup 0)
12359 (match_operand:QI 1 "const_int_1_operand" "")))
12360 (clobber (reg:CC 17))]
12361 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12362 && (TARGET_SHIFT1 || optimize_size)"
12364 [(set_attr "type" "ishift1")
12365 (set (attr "length")
12366 (if_then_else (match_operand 0 "register_operand" "")
12368 (const_string "*")))])
12370 (define_insn "*lshrqi3_1"
12371 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12372 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12373 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12374 (clobber (reg:CC 17))]
12375 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12377 shr{b}\t{%2, %0|%0, %2}
12378 shr{b}\t{%b2, %0|%0, %b2}"
12379 [(set_attr "type" "ishift")
12380 (set_attr "mode" "QI")])
12382 (define_insn "*lshrqi3_1_slp"
12383 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12384 (lshiftrt:QI (match_dup 0)
12385 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12386 (clobber (reg:CC 17))]
12387 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12388 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12390 shr{b}\t{%1, %0|%0, %1}
12391 shr{b}\t{%b1, %0|%0, %b1}"
12392 [(set_attr "type" "ishift1")
12393 (set_attr "mode" "QI")])
12395 ;; This pattern can't accept a variable shift count, since shifts by
12396 ;; zero don't affect the flags. We assume that shifts by constant
12397 ;; zero are optimized away.
12398 (define_insn "*lshrqi2_one_bit_cmp"
12401 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12402 (match_operand:QI 2 "const_int_1_operand" ""))
12404 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12405 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12406 "ix86_match_ccmode (insn, CCGOCmode)
12407 && (TARGET_SHIFT1 || optimize_size)
12408 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12410 [(set_attr "type" "ishift")
12411 (set (attr "length")
12412 (if_then_else (match_operand:SI 0 "register_operand" "")
12414 (const_string "*")))])
12416 ;; This pattern can't accept a variable shift count, since shifts by
12417 ;; zero don't affect the flags. We assume that shifts by constant
12418 ;; zero are optimized away.
12419 (define_insn "*lshrqi2_cmp"
12422 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12423 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12425 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12426 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12427 "ix86_match_ccmode (insn, CCGOCmode)
12428 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12429 "shr{b}\t{%2, %0|%0, %2}"
12430 [(set_attr "type" "ishift")
12431 (set_attr "mode" "QI")])
12433 ;; Rotate instructions
12435 (define_expand "rotldi3"
12436 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12437 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
12438 (match_operand:QI 2 "nonmemory_operand" "")))
12439 (clobber (reg:CC 17))]
12441 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12443 (define_insn "*rotlsi3_1_one_bit_rex64"
12444 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12445 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12446 (match_operand:QI 2 "const_int_1_operand" "")))
12447 (clobber (reg:CC 17))]
12448 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12449 && (TARGET_SHIFT1 || optimize_size)"
12451 [(set_attr "type" "rotate")
12452 (set (attr "length")
12453 (if_then_else (match_operand:DI 0 "register_operand" "")
12455 (const_string "*")))])
12457 (define_insn "*rotldi3_1_rex64"
12458 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12459 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12460 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12461 (clobber (reg:CC 17))]
12462 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12464 rol{q}\t{%2, %0|%0, %2}
12465 rol{q}\t{%b2, %0|%0, %b2}"
12466 [(set_attr "type" "rotate")
12467 (set_attr "mode" "DI")])
12469 (define_expand "rotlsi3"
12470 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12471 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12472 (match_operand:QI 2 "nonmemory_operand" "")))
12473 (clobber (reg:CC 17))]
12475 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12477 (define_insn "*rotlsi3_1_one_bit"
12478 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12479 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12480 (match_operand:QI 2 "const_int_1_operand" "")))
12481 (clobber (reg:CC 17))]
12482 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12483 && (TARGET_SHIFT1 || optimize_size)"
12485 [(set_attr "type" "rotate")
12486 (set (attr "length")
12487 (if_then_else (match_operand:SI 0 "register_operand" "")
12489 (const_string "*")))])
12491 (define_insn "*rotlsi3_1_one_bit_zext"
12492 [(set (match_operand:DI 0 "register_operand" "=r")
12494 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12495 (match_operand:QI 2 "const_int_1_operand" ""))))
12496 (clobber (reg:CC 17))]
12497 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12498 && (TARGET_SHIFT1 || optimize_size)"
12500 [(set_attr "type" "rotate")
12501 (set_attr "length" "2")])
12503 (define_insn "*rotlsi3_1"
12504 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12505 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12506 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12507 (clobber (reg:CC 17))]
12508 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12510 rol{l}\t{%2, %0|%0, %2}
12511 rol{l}\t{%b2, %0|%0, %b2}"
12512 [(set_attr "type" "rotate")
12513 (set_attr "mode" "SI")])
12515 (define_insn "*rotlsi3_1_zext"
12516 [(set (match_operand:DI 0 "register_operand" "=r,r")
12518 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12519 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12520 (clobber (reg:CC 17))]
12521 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12523 rol{l}\t{%2, %k0|%k0, %2}
12524 rol{l}\t{%b2, %k0|%k0, %b2}"
12525 [(set_attr "type" "rotate")
12526 (set_attr "mode" "SI")])
12528 (define_expand "rotlhi3"
12529 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12530 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12531 (match_operand:QI 2 "nonmemory_operand" "")))
12532 (clobber (reg:CC 17))]
12533 "TARGET_HIMODE_MATH"
12534 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12536 (define_insn "*rotlhi3_1_one_bit"
12537 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12538 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12539 (match_operand:QI 2 "const_int_1_operand" "")))
12540 (clobber (reg:CC 17))]
12541 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12542 && (TARGET_SHIFT1 || optimize_size)"
12544 [(set_attr "type" "rotate")
12545 (set (attr "length")
12546 (if_then_else (match_operand 0 "register_operand" "")
12548 (const_string "*")))])
12550 (define_insn "*rotlhi3_1"
12551 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12552 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12553 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12554 (clobber (reg:CC 17))]
12555 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12557 rol{w}\t{%2, %0|%0, %2}
12558 rol{w}\t{%b2, %0|%0, %b2}"
12559 [(set_attr "type" "rotate")
12560 (set_attr "mode" "HI")])
12562 (define_expand "rotlqi3"
12563 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12564 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12565 (match_operand:QI 2 "nonmemory_operand" "")))
12566 (clobber (reg:CC 17))]
12567 "TARGET_QIMODE_MATH"
12568 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12570 (define_insn "*rotlqi3_1_one_bit_slp"
12571 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12572 (rotate:QI (match_dup 0)
12573 (match_operand:QI 1 "const_int_1_operand" "")))
12574 (clobber (reg:CC 17))]
12575 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12576 && (TARGET_SHIFT1 || optimize_size)"
12578 [(set_attr "type" "rotate1")
12579 (set (attr "length")
12580 (if_then_else (match_operand 0 "register_operand" "")
12582 (const_string "*")))])
12584 (define_insn "*rotlqi3_1_one_bit"
12585 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12586 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12587 (match_operand:QI 2 "const_int_1_operand" "")))
12588 (clobber (reg:CC 17))]
12589 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12590 && (TARGET_SHIFT1 || optimize_size)"
12592 [(set_attr "type" "rotate")
12593 (set (attr "length")
12594 (if_then_else (match_operand 0 "register_operand" "")
12596 (const_string "*")))])
12598 (define_insn "*rotlqi3_1_slp"
12599 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12600 (rotate:QI (match_dup 0)
12601 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12602 (clobber (reg:CC 17))]
12603 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12604 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12606 rol{b}\t{%1, %0|%0, %1}
12607 rol{b}\t{%b1, %0|%0, %b1}"
12608 [(set_attr "type" "rotate1")
12609 (set_attr "mode" "QI")])
12611 (define_insn "*rotlqi3_1"
12612 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12613 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12614 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12615 (clobber (reg:CC 17))]
12616 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12618 rol{b}\t{%2, %0|%0, %2}
12619 rol{b}\t{%b2, %0|%0, %b2}"
12620 [(set_attr "type" "rotate")
12621 (set_attr "mode" "QI")])
12623 (define_expand "rotrdi3"
12624 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12625 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12626 (match_operand:QI 2 "nonmemory_operand" "")))
12627 (clobber (reg:CC 17))]
12629 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12631 (define_insn "*rotrdi3_1_one_bit_rex64"
12632 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12633 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12634 (match_operand:QI 2 "const_int_1_operand" "")))
12635 (clobber (reg:CC 17))]
12636 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12637 && (TARGET_SHIFT1 || optimize_size)"
12639 [(set_attr "type" "rotate")
12640 (set (attr "length")
12641 (if_then_else (match_operand:DI 0 "register_operand" "")
12643 (const_string "*")))])
12645 (define_insn "*rotrdi3_1_rex64"
12646 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12647 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12648 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12649 (clobber (reg:CC 17))]
12650 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12652 ror{q}\t{%2, %0|%0, %2}
12653 ror{q}\t{%b2, %0|%0, %b2}"
12654 [(set_attr "type" "rotate")
12655 (set_attr "mode" "DI")])
12657 (define_expand "rotrsi3"
12658 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12659 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12660 (match_operand:QI 2 "nonmemory_operand" "")))
12661 (clobber (reg:CC 17))]
12663 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12665 (define_insn "*rotrsi3_1_one_bit"
12666 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12667 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12668 (match_operand:QI 2 "const_int_1_operand" "")))
12669 (clobber (reg:CC 17))]
12670 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12671 && (TARGET_SHIFT1 || optimize_size)"
12673 [(set_attr "type" "rotate")
12674 (set (attr "length")
12675 (if_then_else (match_operand:SI 0 "register_operand" "")
12677 (const_string "*")))])
12679 (define_insn "*rotrsi3_1_one_bit_zext"
12680 [(set (match_operand:DI 0 "register_operand" "=r")
12682 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12683 (match_operand:QI 2 "const_int_1_operand" ""))))
12684 (clobber (reg:CC 17))]
12685 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12686 && (TARGET_SHIFT1 || optimize_size)"
12688 [(set_attr "type" "rotate")
12689 (set (attr "length")
12690 (if_then_else (match_operand:SI 0 "register_operand" "")
12692 (const_string "*")))])
12694 (define_insn "*rotrsi3_1"
12695 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12696 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12697 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12698 (clobber (reg:CC 17))]
12699 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12701 ror{l}\t{%2, %0|%0, %2}
12702 ror{l}\t{%b2, %0|%0, %b2}"
12703 [(set_attr "type" "rotate")
12704 (set_attr "mode" "SI")])
12706 (define_insn "*rotrsi3_1_zext"
12707 [(set (match_operand:DI 0 "register_operand" "=r,r")
12709 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12710 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12711 (clobber (reg:CC 17))]
12712 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12714 ror{l}\t{%2, %k0|%k0, %2}
12715 ror{l}\t{%b2, %k0|%k0, %b2}"
12716 [(set_attr "type" "rotate")
12717 (set_attr "mode" "SI")])
12719 (define_expand "rotrhi3"
12720 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12721 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12722 (match_operand:QI 2 "nonmemory_operand" "")))
12723 (clobber (reg:CC 17))]
12724 "TARGET_HIMODE_MATH"
12725 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12727 (define_insn "*rotrhi3_one_bit"
12728 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12729 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12730 (match_operand:QI 2 "const_int_1_operand" "")))
12731 (clobber (reg:CC 17))]
12732 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12733 && (TARGET_SHIFT1 || optimize_size)"
12735 [(set_attr "type" "rotate")
12736 (set (attr "length")
12737 (if_then_else (match_operand 0 "register_operand" "")
12739 (const_string "*")))])
12741 (define_insn "*rotrhi3"
12742 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12743 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12744 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12745 (clobber (reg:CC 17))]
12746 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12748 ror{w}\t{%2, %0|%0, %2}
12749 ror{w}\t{%b2, %0|%0, %b2}"
12750 [(set_attr "type" "rotate")
12751 (set_attr "mode" "HI")])
12753 (define_expand "rotrqi3"
12754 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12755 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12756 (match_operand:QI 2 "nonmemory_operand" "")))
12757 (clobber (reg:CC 17))]
12758 "TARGET_QIMODE_MATH"
12759 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12761 (define_insn "*rotrqi3_1_one_bit"
12762 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12763 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12764 (match_operand:QI 2 "const_int_1_operand" "")))
12765 (clobber (reg:CC 17))]
12766 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12767 && (TARGET_SHIFT1 || optimize_size)"
12769 [(set_attr "type" "rotate")
12770 (set (attr "length")
12771 (if_then_else (match_operand 0 "register_operand" "")
12773 (const_string "*")))])
12775 (define_insn "*rotrqi3_1_one_bit_slp"
12776 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12777 (rotatert:QI (match_dup 0)
12778 (match_operand:QI 1 "const_int_1_operand" "")))
12779 (clobber (reg:CC 17))]
12780 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12781 && (TARGET_SHIFT1 || optimize_size)"
12783 [(set_attr "type" "rotate1")
12784 (set (attr "length")
12785 (if_then_else (match_operand 0 "register_operand" "")
12787 (const_string "*")))])
12789 (define_insn "*rotrqi3_1"
12790 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12791 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12792 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12793 (clobber (reg:CC 17))]
12794 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12796 ror{b}\t{%2, %0|%0, %2}
12797 ror{b}\t{%b2, %0|%0, %b2}"
12798 [(set_attr "type" "rotate")
12799 (set_attr "mode" "QI")])
12801 (define_insn "*rotrqi3_1_slp"
12802 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12803 (rotatert:QI (match_dup 0)
12804 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12805 (clobber (reg:CC 17))]
12806 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12807 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12809 ror{b}\t{%1, %0|%0, %1}
12810 ror{b}\t{%b1, %0|%0, %b1}"
12811 [(set_attr "type" "rotate1")
12812 (set_attr "mode" "QI")])
12814 ;; Bit set / bit test instructions
12816 (define_expand "extv"
12817 [(set (match_operand:SI 0 "register_operand" "")
12818 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12819 (match_operand:SI 2 "immediate_operand" "")
12820 (match_operand:SI 3 "immediate_operand" "")))]
12823 /* Handle extractions from %ah et al. */
12824 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12827 /* From mips.md: extract_bit_field doesn't verify that our source
12828 matches the predicate, so check it again here. */
12829 if (! register_operand (operands[1], VOIDmode))
12833 (define_expand "extzv"
12834 [(set (match_operand:SI 0 "register_operand" "")
12835 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12836 (match_operand:SI 2 "immediate_operand" "")
12837 (match_operand:SI 3 "immediate_operand" "")))]
12840 /* Handle extractions from %ah et al. */
12841 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12844 /* From mips.md: extract_bit_field doesn't verify that our source
12845 matches the predicate, so check it again here. */
12846 if (! register_operand (operands[1], VOIDmode))
12850 (define_expand "insv"
12851 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
12852 (match_operand:SI 1 "immediate_operand" "")
12853 (match_operand:SI 2 "immediate_operand" ""))
12854 (match_operand:SI 3 "register_operand" ""))]
12857 /* Handle extractions from %ah et al. */
12858 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12861 /* From mips.md: insert_bit_field doesn't verify that our source
12862 matches the predicate, so check it again here. */
12863 if (! register_operand (operands[0], VOIDmode))
12867 ;; %%% bts, btr, btc, bt.
12869 ;; Store-flag instructions.
12871 ;; For all sCOND expanders, also expand the compare or test insn that
12872 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12874 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12875 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12876 ;; way, which can later delete the movzx if only QImode is needed.
12878 (define_expand "seq"
12879 [(set (match_operand:QI 0 "register_operand" "")
12880 (eq:QI (reg:CC 17) (const_int 0)))]
12882 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12884 (define_expand "sne"
12885 [(set (match_operand:QI 0 "register_operand" "")
12886 (ne:QI (reg:CC 17) (const_int 0)))]
12888 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12890 (define_expand "sgt"
12891 [(set (match_operand:QI 0 "register_operand" "")
12892 (gt:QI (reg:CC 17) (const_int 0)))]
12894 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12896 (define_expand "sgtu"
12897 [(set (match_operand:QI 0 "register_operand" "")
12898 (gtu:QI (reg:CC 17) (const_int 0)))]
12900 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12902 (define_expand "slt"
12903 [(set (match_operand:QI 0 "register_operand" "")
12904 (lt:QI (reg:CC 17) (const_int 0)))]
12906 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12908 (define_expand "sltu"
12909 [(set (match_operand:QI 0 "register_operand" "")
12910 (ltu:QI (reg:CC 17) (const_int 0)))]
12912 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12914 (define_expand "sge"
12915 [(set (match_operand:QI 0 "register_operand" "")
12916 (ge:QI (reg:CC 17) (const_int 0)))]
12918 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12920 (define_expand "sgeu"
12921 [(set (match_operand:QI 0 "register_operand" "")
12922 (geu:QI (reg:CC 17) (const_int 0)))]
12924 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12926 (define_expand "sle"
12927 [(set (match_operand:QI 0 "register_operand" "")
12928 (le:QI (reg:CC 17) (const_int 0)))]
12930 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12932 (define_expand "sleu"
12933 [(set (match_operand:QI 0 "register_operand" "")
12934 (leu:QI (reg:CC 17) (const_int 0)))]
12936 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12938 (define_expand "sunordered"
12939 [(set (match_operand:QI 0 "register_operand" "")
12940 (unordered:QI (reg:CC 17) (const_int 0)))]
12941 "TARGET_80387 || TARGET_SSE"
12942 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12944 (define_expand "sordered"
12945 [(set (match_operand:QI 0 "register_operand" "")
12946 (ordered:QI (reg:CC 17) (const_int 0)))]
12948 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12950 (define_expand "suneq"
12951 [(set (match_operand:QI 0 "register_operand" "")
12952 (uneq:QI (reg:CC 17) (const_int 0)))]
12953 "TARGET_80387 || TARGET_SSE"
12954 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12956 (define_expand "sunge"
12957 [(set (match_operand:QI 0 "register_operand" "")
12958 (unge:QI (reg:CC 17) (const_int 0)))]
12959 "TARGET_80387 || TARGET_SSE"
12960 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12962 (define_expand "sungt"
12963 [(set (match_operand:QI 0 "register_operand" "")
12964 (ungt:QI (reg:CC 17) (const_int 0)))]
12965 "TARGET_80387 || TARGET_SSE"
12966 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12968 (define_expand "sunle"
12969 [(set (match_operand:QI 0 "register_operand" "")
12970 (unle:QI (reg:CC 17) (const_int 0)))]
12971 "TARGET_80387 || TARGET_SSE"
12972 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12974 (define_expand "sunlt"
12975 [(set (match_operand:QI 0 "register_operand" "")
12976 (unlt:QI (reg:CC 17) (const_int 0)))]
12977 "TARGET_80387 || TARGET_SSE"
12978 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12980 (define_expand "sltgt"
12981 [(set (match_operand:QI 0 "register_operand" "")
12982 (ltgt:QI (reg:CC 17) (const_int 0)))]
12983 "TARGET_80387 || TARGET_SSE"
12984 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12986 (define_insn "*setcc_1"
12987 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12988 (match_operator:QI 1 "ix86_comparison_operator"
12989 [(reg 17) (const_int 0)]))]
12992 [(set_attr "type" "setcc")
12993 (set_attr "mode" "QI")])
12995 (define_insn "setcc_2"
12996 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12997 (match_operator:QI 1 "ix86_comparison_operator"
12998 [(reg 17) (const_int 0)]))]
13001 [(set_attr "type" "setcc")
13002 (set_attr "mode" "QI")])
13004 ;; In general it is not safe to assume too much about CCmode registers,
13005 ;; so simplify-rtx stops when it sees a second one. Under certain
13006 ;; conditions this is safe on x86, so help combine not create
13013 [(set (match_operand:QI 0 "nonimmediate_operand" "")
13014 (ne:QI (match_operator 1 "ix86_comparison_operator"
13015 [(reg 17) (const_int 0)])
13018 [(set (match_dup 0) (match_dup 1))]
13020 PUT_MODE (operands[1], QImode);
13024 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
13025 (ne:QI (match_operator 1 "ix86_comparison_operator"
13026 [(reg 17) (const_int 0)])
13029 [(set (match_dup 0) (match_dup 1))]
13031 PUT_MODE (operands[1], QImode);
13035 [(set (match_operand:QI 0 "nonimmediate_operand" "")
13036 (eq:QI (match_operator 1 "ix86_comparison_operator"
13037 [(reg 17) (const_int 0)])
13040 [(set (match_dup 0) (match_dup 1))]
13042 rtx new_op1 = copy_rtx (operands[1]);
13043 operands[1] = new_op1;
13044 PUT_MODE (new_op1, QImode);
13045 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
13046 GET_MODE (XEXP (new_op1, 0))));
13048 /* Make sure that (a) the CCmode we have for the flags is strong
13049 enough for the reversed compare or (b) we have a valid FP compare. */
13050 if (! ix86_comparison_operator (new_op1, VOIDmode))
13055 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
13056 (eq:QI (match_operator 1 "ix86_comparison_operator"
13057 [(reg 17) (const_int 0)])
13060 [(set (match_dup 0) (match_dup 1))]
13062 rtx new_op1 = copy_rtx (operands[1]);
13063 operands[1] = new_op1;
13064 PUT_MODE (new_op1, QImode);
13065 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
13066 GET_MODE (XEXP (new_op1, 0))));
13068 /* Make sure that (a) the CCmode we have for the flags is strong
13069 enough for the reversed compare or (b) we have a valid FP compare. */
13070 if (! ix86_comparison_operator (new_op1, VOIDmode))
13074 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
13075 ;; subsequent logical operations are used to imitate conditional moves.
13076 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
13077 ;; it directly. Further holding this value in pseudo register might bring
13078 ;; problem in implicit normalization in spill code.
13079 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
13080 ;; instructions after reload by splitting the conditional move patterns.
13082 (define_insn "*sse_setccsf"
13083 [(set (match_operand:SF 0 "register_operand" "=x")
13084 (match_operator:SF 1 "sse_comparison_operator"
13085 [(match_operand:SF 2 "register_operand" "0")
13086 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
13087 "TARGET_SSE && reload_completed"
13088 "cmp%D1ss\t{%3, %0|%0, %3}"
13089 [(set_attr "type" "ssecmp")
13090 (set_attr "mode" "SF")])
13092 (define_insn "*sse_setccdf"
13093 [(set (match_operand:DF 0 "register_operand" "=Y")
13094 (match_operator:DF 1 "sse_comparison_operator"
13095 [(match_operand:DF 2 "register_operand" "0")
13096 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
13097 "TARGET_SSE2 && reload_completed"
13098 "cmp%D1sd\t{%3, %0|%0, %3}"
13099 [(set_attr "type" "ssecmp")
13100 (set_attr "mode" "DF")])
13102 ;; Basic conditional jump instructions.
13103 ;; We ignore the overflow flag for signed branch instructions.
13105 ;; For all bCOND expanders, also expand the compare or test insn that
13106 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
13108 (define_expand "beq"
13110 (if_then_else (match_dup 1)
13111 (label_ref (match_operand 0 "" ""))
13114 "ix86_expand_branch (EQ, operands[0]); DONE;")
13116 (define_expand "bne"
13118 (if_then_else (match_dup 1)
13119 (label_ref (match_operand 0 "" ""))
13122 "ix86_expand_branch (NE, operands[0]); DONE;")
13124 (define_expand "bgt"
13126 (if_then_else (match_dup 1)
13127 (label_ref (match_operand 0 "" ""))
13130 "ix86_expand_branch (GT, operands[0]); DONE;")
13132 (define_expand "bgtu"
13134 (if_then_else (match_dup 1)
13135 (label_ref (match_operand 0 "" ""))
13138 "ix86_expand_branch (GTU, operands[0]); DONE;")
13140 (define_expand "blt"
13142 (if_then_else (match_dup 1)
13143 (label_ref (match_operand 0 "" ""))
13146 "ix86_expand_branch (LT, operands[0]); DONE;")
13148 (define_expand "bltu"
13150 (if_then_else (match_dup 1)
13151 (label_ref (match_operand 0 "" ""))
13154 "ix86_expand_branch (LTU, operands[0]); DONE;")
13156 (define_expand "bge"
13158 (if_then_else (match_dup 1)
13159 (label_ref (match_operand 0 "" ""))
13162 "ix86_expand_branch (GE, operands[0]); DONE;")
13164 (define_expand "bgeu"
13166 (if_then_else (match_dup 1)
13167 (label_ref (match_operand 0 "" ""))
13170 "ix86_expand_branch (GEU, operands[0]); DONE;")
13172 (define_expand "ble"
13174 (if_then_else (match_dup 1)
13175 (label_ref (match_operand 0 "" ""))
13178 "ix86_expand_branch (LE, operands[0]); DONE;")
13180 (define_expand "bleu"
13182 (if_then_else (match_dup 1)
13183 (label_ref (match_operand 0 "" ""))
13186 "ix86_expand_branch (LEU, operands[0]); DONE;")
13188 (define_expand "bunordered"
13190 (if_then_else (match_dup 1)
13191 (label_ref (match_operand 0 "" ""))
13193 "TARGET_80387 || TARGET_SSE"
13194 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
13196 (define_expand "bordered"
13198 (if_then_else (match_dup 1)
13199 (label_ref (match_operand 0 "" ""))
13201 "TARGET_80387 || TARGET_SSE"
13202 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
13204 (define_expand "buneq"
13206 (if_then_else (match_dup 1)
13207 (label_ref (match_operand 0 "" ""))
13209 "TARGET_80387 || TARGET_SSE"
13210 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
13212 (define_expand "bunge"
13214 (if_then_else (match_dup 1)
13215 (label_ref (match_operand 0 "" ""))
13217 "TARGET_80387 || TARGET_SSE"
13218 "ix86_expand_branch (UNGE, operands[0]); DONE;")
13220 (define_expand "bungt"
13222 (if_then_else (match_dup 1)
13223 (label_ref (match_operand 0 "" ""))
13225 "TARGET_80387 || TARGET_SSE"
13226 "ix86_expand_branch (UNGT, operands[0]); DONE;")
13228 (define_expand "bunle"
13230 (if_then_else (match_dup 1)
13231 (label_ref (match_operand 0 "" ""))
13233 "TARGET_80387 || TARGET_SSE"
13234 "ix86_expand_branch (UNLE, operands[0]); DONE;")
13236 (define_expand "bunlt"
13238 (if_then_else (match_dup 1)
13239 (label_ref (match_operand 0 "" ""))
13241 "TARGET_80387 || TARGET_SSE"
13242 "ix86_expand_branch (UNLT, operands[0]); DONE;")
13244 (define_expand "bltgt"
13246 (if_then_else (match_dup 1)
13247 (label_ref (match_operand 0 "" ""))
13249 "TARGET_80387 || TARGET_SSE"
13250 "ix86_expand_branch (LTGT, operands[0]); DONE;")
13252 (define_insn "*jcc_1"
13254 (if_then_else (match_operator 1 "ix86_comparison_operator"
13255 [(reg 17) (const_int 0)])
13256 (label_ref (match_operand 0 "" ""))
13260 [(set_attr "type" "ibr")
13261 (set_attr "modrm" "0")
13262 (set (attr "length")
13263 (if_then_else (and (ge (minus (match_dup 0) (pc))
13265 (lt (minus (match_dup 0) (pc))
13270 (define_insn "*jcc_2"
13272 (if_then_else (match_operator 1 "ix86_comparison_operator"
13273 [(reg 17) (const_int 0)])
13275 (label_ref (match_operand 0 "" ""))))]
13278 [(set_attr "type" "ibr")
13279 (set_attr "modrm" "0")
13280 (set (attr "length")
13281 (if_then_else (and (ge (minus (match_dup 0) (pc))
13283 (lt (minus (match_dup 0) (pc))
13288 ;; In general it is not safe to assume too much about CCmode registers,
13289 ;; so simplify-rtx stops when it sees a second one. Under certain
13290 ;; conditions this is safe on x86, so help combine not create
13298 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
13299 [(reg 17) (const_int 0)])
13301 (label_ref (match_operand 1 "" ""))
13305 (if_then_else (match_dup 0)
13306 (label_ref (match_dup 1))
13309 PUT_MODE (operands[0], VOIDmode);
13314 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
13315 [(reg 17) (const_int 0)])
13317 (label_ref (match_operand 1 "" ""))
13321 (if_then_else (match_dup 0)
13322 (label_ref (match_dup 1))
13325 rtx new_op0 = copy_rtx (operands[0]);
13326 operands[0] = new_op0;
13327 PUT_MODE (new_op0, VOIDmode);
13328 PUT_CODE (new_op0, REVERSE_CONDITION (GET_CODE (new_op0),
13329 GET_MODE (XEXP (new_op0, 0))));
13331 /* Make sure that (a) the CCmode we have for the flags is strong
13332 enough for the reversed compare or (b) we have a valid FP compare. */
13333 if (! ix86_comparison_operator (new_op0, VOIDmode))
13337 ;; Define combination compare-and-branch fp compare instructions to use
13338 ;; during early optimization. Splitting the operation apart early makes
13339 ;; for bad code when we want to reverse the operation.
13341 (define_insn "*fp_jcc_1"
13343 (if_then_else (match_operator 0 "comparison_operator"
13344 [(match_operand 1 "register_operand" "f")
13345 (match_operand 2 "register_operand" "f")])
13346 (label_ref (match_operand 3 "" ""))
13348 (clobber (reg:CCFP 18))
13349 (clobber (reg:CCFP 17))]
13350 "TARGET_CMOVE && TARGET_80387
13351 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13352 && FLOAT_MODE_P (GET_MODE (operands[1]))
13353 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13354 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13357 (define_insn "*fp_jcc_1_sse"
13359 (if_then_else (match_operator 0 "comparison_operator"
13360 [(match_operand 1 "register_operand" "f#x,x#f")
13361 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13362 (label_ref (match_operand 3 "" ""))
13364 (clobber (reg:CCFP 18))
13365 (clobber (reg:CCFP 17))]
13367 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13368 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13369 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13372 (define_insn "*fp_jcc_1_sse_only"
13374 (if_then_else (match_operator 0 "comparison_operator"
13375 [(match_operand 1 "register_operand" "x")
13376 (match_operand 2 "nonimmediate_operand" "xm")])
13377 (label_ref (match_operand 3 "" ""))
13379 (clobber (reg:CCFP 18))
13380 (clobber (reg:CCFP 17))]
13381 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13382 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13383 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13386 (define_insn "*fp_jcc_2"
13388 (if_then_else (match_operator 0 "comparison_operator"
13389 [(match_operand 1 "register_operand" "f")
13390 (match_operand 2 "register_operand" "f")])
13392 (label_ref (match_operand 3 "" ""))))
13393 (clobber (reg:CCFP 18))
13394 (clobber (reg:CCFP 17))]
13395 "TARGET_CMOVE && TARGET_80387
13396 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13397 && FLOAT_MODE_P (GET_MODE (operands[1]))
13398 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13399 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13402 (define_insn "*fp_jcc_2_sse"
13404 (if_then_else (match_operator 0 "comparison_operator"
13405 [(match_operand 1 "register_operand" "f#x,x#f")
13406 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13408 (label_ref (match_operand 3 "" ""))))
13409 (clobber (reg:CCFP 18))
13410 (clobber (reg:CCFP 17))]
13412 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13413 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13414 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13417 (define_insn "*fp_jcc_2_sse_only"
13419 (if_then_else (match_operator 0 "comparison_operator"
13420 [(match_operand 1 "register_operand" "x")
13421 (match_operand 2 "nonimmediate_operand" "xm")])
13423 (label_ref (match_operand 3 "" ""))))
13424 (clobber (reg:CCFP 18))
13425 (clobber (reg:CCFP 17))]
13426 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13427 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13428 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13431 (define_insn "*fp_jcc_3"
13433 (if_then_else (match_operator 0 "comparison_operator"
13434 [(match_operand 1 "register_operand" "f")
13435 (match_operand 2 "nonimmediate_operand" "fm")])
13436 (label_ref (match_operand 3 "" ""))
13438 (clobber (reg:CCFP 18))
13439 (clobber (reg:CCFP 17))
13440 (clobber (match_scratch:HI 4 "=a"))]
13442 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13443 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13444 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13445 && SELECT_CC_MODE (GET_CODE (operands[0]),
13446 operands[1], operands[2]) == CCFPmode
13447 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13450 (define_insn "*fp_jcc_4"
13452 (if_then_else (match_operator 0 "comparison_operator"
13453 [(match_operand 1 "register_operand" "f")
13454 (match_operand 2 "nonimmediate_operand" "fm")])
13456 (label_ref (match_operand 3 "" ""))))
13457 (clobber (reg:CCFP 18))
13458 (clobber (reg:CCFP 17))
13459 (clobber (match_scratch:HI 4 "=a"))]
13461 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13462 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13463 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13464 && SELECT_CC_MODE (GET_CODE (operands[0]),
13465 operands[1], operands[2]) == CCFPmode
13466 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13469 (define_insn "*fp_jcc_5"
13471 (if_then_else (match_operator 0 "comparison_operator"
13472 [(match_operand 1 "register_operand" "f")
13473 (match_operand 2 "register_operand" "f")])
13474 (label_ref (match_operand 3 "" ""))
13476 (clobber (reg:CCFP 18))
13477 (clobber (reg:CCFP 17))
13478 (clobber (match_scratch:HI 4 "=a"))]
13480 && FLOAT_MODE_P (GET_MODE (operands[1]))
13481 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13482 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13485 (define_insn "*fp_jcc_6"
13487 (if_then_else (match_operator 0 "comparison_operator"
13488 [(match_operand 1 "register_operand" "f")
13489 (match_operand 2 "register_operand" "f")])
13491 (label_ref (match_operand 3 "" ""))))
13492 (clobber (reg:CCFP 18))
13493 (clobber (reg:CCFP 17))
13494 (clobber (match_scratch:HI 4 "=a"))]
13496 && FLOAT_MODE_P (GET_MODE (operands[1]))
13497 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13498 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13503 (if_then_else (match_operator 0 "comparison_operator"
13504 [(match_operand 1 "register_operand" "")
13505 (match_operand 2 "nonimmediate_operand" "")])
13506 (match_operand 3 "" "")
13507 (match_operand 4 "" "")))
13508 (clobber (reg:CCFP 18))
13509 (clobber (reg:CCFP 17))]
13513 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13514 operands[3], operands[4], NULL_RTX);
13520 (if_then_else (match_operator 0 "comparison_operator"
13521 [(match_operand 1 "register_operand" "")
13522 (match_operand 2 "nonimmediate_operand" "")])
13523 (match_operand 3 "" "")
13524 (match_operand 4 "" "")))
13525 (clobber (reg:CCFP 18))
13526 (clobber (reg:CCFP 17))
13527 (clobber (match_scratch:HI 5 "=a"))]
13530 (if_then_else (match_dup 6)
13534 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13535 operands[3], operands[4], operands[5]);
13539 ;; Unconditional and other jump instructions
13541 (define_insn "jump"
13543 (label_ref (match_operand 0 "" "")))]
13546 [(set_attr "type" "ibr")
13547 (set (attr "length")
13548 (if_then_else (and (ge (minus (match_dup 0) (pc))
13550 (lt (minus (match_dup 0) (pc))
13554 (set_attr "modrm" "0")])
13556 (define_expand "indirect_jump"
13557 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13561 (define_insn "*indirect_jump"
13562 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13565 [(set_attr "type" "ibr")
13566 (set_attr "length_immediate" "0")])
13568 (define_insn "*indirect_jump_rtx64"
13569 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13572 [(set_attr "type" "ibr")
13573 (set_attr "length_immediate" "0")])
13575 (define_expand "tablejump"
13576 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13577 (use (label_ref (match_operand 1 "" "")))])]
13580 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13581 relative. Convert the relative address to an absolute address. */
13585 enum rtx_code code;
13591 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13593 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13597 op1 = pic_offset_table_rtx;
13602 op0 = pic_offset_table_rtx;
13606 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13611 (define_insn "*tablejump_1"
13612 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13613 (use (label_ref (match_operand 1 "" "")))]
13616 [(set_attr "type" "ibr")
13617 (set_attr "length_immediate" "0")])
13619 (define_insn "*tablejump_1_rtx64"
13620 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13621 (use (label_ref (match_operand 1 "" "")))]
13624 [(set_attr "type" "ibr")
13625 (set_attr "length_immediate" "0")])
13627 ;; Loop instruction
13629 ;; This is all complicated by the fact that since this is a jump insn
13630 ;; we must handle our own reloads.
13632 (define_expand "doloop_end"
13633 [(use (match_operand 0 "" "")) ; loop pseudo
13634 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13635 (use (match_operand 2 "" "")) ; max iterations
13636 (use (match_operand 3 "" "")) ; loop level
13637 (use (match_operand 4 "" ""))] ; label
13638 "!TARGET_64BIT && TARGET_USE_LOOP"
13641 /* Only use cloop on innermost loops. */
13642 if (INTVAL (operands[3]) > 1)
13644 if (GET_MODE (operands[0]) != SImode)
13646 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13651 (define_insn "doloop_end_internal"
13653 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13655 (label_ref (match_operand 0 "" ""))
13657 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
13658 (plus:SI (match_dup 1)
13660 (clobber (match_scratch:SI 3 "=X,X,r"))
13661 (clobber (reg:CC 17))]
13662 "!TARGET_64BIT && TARGET_USE_LOOP"
13664 if (which_alternative != 0)
13666 if (get_attr_length (insn) == 2)
13667 return "%+loop\t%l0";
13669 return "dec{l}\t%1\;%+jne\t%l0";
13671 [(set_attr "ppro_uops" "many")
13672 (set (attr "length")
13673 (if_then_else (and (eq_attr "alternative" "0")
13674 (and (ge (minus (match_dup 0) (pc))
13676 (lt (minus (match_dup 0) (pc))
13680 ;; We don't know the type before shorten branches. Optimistically expect
13681 ;; the loop instruction to match.
13682 (set (attr "type") (const_string "ibr"))])
13686 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13688 (match_operand 0 "" "")
13691 (plus:SI (match_dup 1)
13693 (clobber (match_scratch:SI 2 ""))
13694 (clobber (reg:CC 17))]
13695 "!TARGET_64BIT && TARGET_USE_LOOP
13696 && reload_completed
13697 && REGNO (operands[1]) != 2"
13698 [(parallel [(set (reg:CCZ 17)
13699 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13701 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13702 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13709 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13711 (match_operand 0 "" "")
13713 (set (match_operand:SI 2 "nonimmediate_operand" "")
13714 (plus:SI (match_dup 1)
13716 (clobber (match_scratch:SI 3 ""))
13717 (clobber (reg:CC 17))]
13718 "!TARGET_64BIT && TARGET_USE_LOOP
13719 && reload_completed
13720 && (! REG_P (operands[2])
13721 || ! rtx_equal_p (operands[1], operands[2]))"
13722 [(set (match_dup 3) (match_dup 1))
13723 (parallel [(set (reg:CCZ 17)
13724 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13726 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13727 (set (match_dup 2) (match_dup 3))
13728 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13733 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13736 [(set (reg 17) (match_operand 0 "" ""))
13737 (set (match_operand:QI 1 "register_operand" "")
13738 (match_operator:QI 2 "ix86_comparison_operator"
13739 [(reg 17) (const_int 0)]))
13740 (set (match_operand 3 "q_regs_operand" "")
13741 (zero_extend (match_dup 1)))]
13742 "(peep2_reg_dead_p (3, operands[1])
13743 || operands_match_p (operands[1], operands[3]))
13744 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13745 [(set (match_dup 4) (match_dup 0))
13746 (set (strict_low_part (match_dup 5))
13749 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13750 operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));
13751 ix86_expand_clear (operands[3]);
13754 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13757 [(set (reg 17) (match_operand 0 "" ""))
13758 (set (match_operand:QI 1 "register_operand" "")
13759 (match_operator:QI 2 "ix86_comparison_operator"
13760 [(reg 17) (const_int 0)]))
13761 (parallel [(set (match_operand 3 "q_regs_operand" "")
13762 (zero_extend (match_dup 1)))
13763 (clobber (reg:CC 17))])]
13764 "(peep2_reg_dead_p (3, operands[1])
13765 || operands_match_p (operands[1], operands[3]))
13766 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13767 [(set (match_dup 4) (match_dup 0))
13768 (set (strict_low_part (match_dup 5))
13771 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13772 operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));
13773 ix86_expand_clear (operands[3]);
13776 ;; Call instructions.
13778 ;; The predicates normally associated with named expanders are not properly
13779 ;; checked for calls. This is a bug in the generic code, but it isn't that
13780 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13782 ;; Call subroutine returning no value.
13784 (define_expand "call_pop"
13785 [(parallel [(call (match_operand:QI 0 "" "")
13786 (match_operand:SI 1 "" ""))
13788 (plus:SI (reg:SI 7)
13789 (match_operand:SI 3 "" "")))])]
13792 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3], 0);
13796 (define_insn "*call_pop_0"
13797 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13798 (match_operand:SI 1 "" ""))
13799 (set (reg:SI 7) (plus:SI (reg:SI 7)
13800 (match_operand:SI 2 "immediate_operand" "")))]
13803 if (SIBLING_CALL_P (insn))
13806 return "call\t%P0";
13808 [(set_attr "type" "call")])
13810 (define_insn "*call_pop_1"
13811 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13812 (match_operand:SI 1 "" ""))
13813 (set (reg:SI 7) (plus:SI (reg:SI 7)
13814 (match_operand:SI 2 "immediate_operand" "i")))]
13817 if (constant_call_address_operand (operands[0], Pmode))
13819 if (SIBLING_CALL_P (insn))
13822 return "call\t%P0";
13824 if (SIBLING_CALL_P (insn))
13827 return "call\t%A0";
13829 [(set_attr "type" "call")])
13831 (define_expand "call"
13832 [(call (match_operand:QI 0 "" "")
13833 (match_operand 1 "" ""))
13834 (use (match_operand 2 "" ""))]
13837 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 0);
13841 (define_expand "sibcall"
13842 [(call (match_operand:QI 0 "" "")
13843 (match_operand 1 "" ""))
13844 (use (match_operand 2 "" ""))]
13847 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 1);
13851 (define_insn "*call_0"
13852 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13853 (match_operand 1 "" ""))]
13856 if (SIBLING_CALL_P (insn))
13859 return "call\t%P0";
13861 [(set_attr "type" "call")])
13863 (define_insn "*call_1"
13864 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13865 (match_operand 1 "" ""))]
13866 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
13868 if (constant_call_address_operand (operands[0], QImode))
13869 return "call\t%P0";
13870 return "call\t%A0";
13872 [(set_attr "type" "call")])
13874 (define_insn "*sibcall_1"
13875 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
13876 (match_operand 1 "" ""))]
13877 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
13879 if (constant_call_address_operand (operands[0], QImode))
13883 [(set_attr "type" "call")])
13885 (define_insn "*call_1_rex64"
13886 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13887 (match_operand 1 "" ""))]
13888 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
13890 if (constant_call_address_operand (operands[0], QImode))
13891 return "call\t%P0";
13892 return "call\t%A0";
13894 [(set_attr "type" "call")])
13896 (define_insn "*sibcall_1_rex64"
13897 [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
13898 (match_operand 1 "" ""))]
13899 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13901 [(set_attr "type" "call")])
13903 (define_insn "*sibcall_1_rex64_v"
13904 [(call (mem:QI (reg:DI 40))
13905 (match_operand 0 "" ""))]
13906 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13908 [(set_attr "type" "call")])
13911 ;; Call subroutine, returning value in operand 0
13913 (define_expand "call_value_pop"
13914 [(parallel [(set (match_operand 0 "" "")
13915 (call (match_operand:QI 1 "" "")
13916 (match_operand:SI 2 "" "")))
13918 (plus:SI (reg:SI 7)
13919 (match_operand:SI 4 "" "")))])]
13922 ix86_expand_call (operands[0], operands[1], operands[2],
13923 operands[3], operands[4], 0);
13927 (define_expand "call_value"
13928 [(set (match_operand 0 "" "")
13929 (call (match_operand:QI 1 "" "")
13930 (match_operand:SI 2 "" "")))
13931 (use (match_operand:SI 3 "" ""))]
13932 ;; Operand 2 not used on the i386.
13935 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 0);
13939 (define_expand "sibcall_value"
13940 [(set (match_operand 0 "" "")
13941 (call (match_operand:QI 1 "" "")
13942 (match_operand:SI 2 "" "")))
13943 (use (match_operand:SI 3 "" ""))]
13944 ;; Operand 2 not used on the i386.
13947 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 1);
13951 ;; Call subroutine returning any type.
13953 (define_expand "untyped_call"
13954 [(parallel [(call (match_operand 0 "" "")
13956 (match_operand 1 "" "")
13957 (match_operand 2 "" "")])]
13962 /* In order to give reg-stack an easier job in validating two
13963 coprocessor registers as containing a possible return value,
13964 simply pretend the untyped call returns a complex long double
13967 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
13968 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
13969 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
13972 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13974 rtx set = XVECEXP (operands[2], 0, i);
13975 emit_move_insn (SET_DEST (set), SET_SRC (set));
13978 /* The optimizer does not know that the call sets the function value
13979 registers we stored in the result block. We avoid problems by
13980 claiming that all hard registers are used and clobbered at this
13982 emit_insn (gen_blockage (const0_rtx));
13987 ;; Prologue and epilogue instructions
13989 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13990 ;; all of memory. This blocks insns from being moved across this point.
13992 (define_insn "blockage"
13993 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
13996 [(set_attr "length" "0")])
13998 ;; Insn emitted into the body of a function to return from a function.
13999 ;; This is only done if the function's epilogue is known to be simple.
14000 ;; See comments for ix86_can_use_return_insn_p in i386.c.
14002 (define_expand "return"
14004 "ix86_can_use_return_insn_p ()"
14006 if (current_function_pops_args)
14008 rtx popc = GEN_INT (current_function_pops_args);
14009 emit_jump_insn (gen_return_pop_internal (popc));
14014 (define_insn "return_internal"
14018 [(set_attr "length" "1")
14019 (set_attr "length_immediate" "0")
14020 (set_attr "modrm" "0")])
14022 (define_insn "return_pop_internal"
14024 (use (match_operand:SI 0 "const_int_operand" ""))]
14027 [(set_attr "length" "3")
14028 (set_attr "length_immediate" "2")
14029 (set_attr "modrm" "0")])
14031 (define_insn "return_indirect_internal"
14033 (use (match_operand:SI 0 "register_operand" "r"))]
14036 [(set_attr "type" "ibr")
14037 (set_attr "length_immediate" "0")])
14043 [(set_attr "length" "1")
14044 (set_attr "length_immediate" "0")
14045 (set_attr "modrm" "0")
14046 (set_attr "ppro_uops" "one")])
14048 (define_expand "prologue"
14051 "ix86_expand_prologue (); DONE;")
14053 (define_insn "set_got"
14054 [(set (match_operand:SI 0 "register_operand" "=r")
14055 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
14056 (clobber (reg:CC 17))]
14058 { return output_set_got (operands[0]); }
14059 [(set_attr "type" "multi")
14060 (set_attr "length" "12")])
14062 (define_expand "epilogue"
14065 "ix86_expand_epilogue (1); DONE;")
14067 (define_expand "sibcall_epilogue"
14070 "ix86_expand_epilogue (0); DONE;")
14072 (define_expand "eh_return"
14073 [(use (match_operand 0 "register_operand" ""))
14074 (use (match_operand 1 "register_operand" ""))]
14077 rtx tmp, sa = operands[0], ra = operands[1];
14079 /* Tricky bit: we write the address of the handler to which we will
14080 be returning into someone else's stack frame, one word below the
14081 stack address we wish to restore. */
14082 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
14083 tmp = plus_constant (tmp, -UNITS_PER_WORD);
14084 tmp = gen_rtx_MEM (Pmode, tmp);
14085 emit_move_insn (tmp, ra);
14087 if (Pmode == SImode)
14088 emit_insn (gen_eh_return_si (sa));
14090 emit_insn (gen_eh_return_di (sa));
14095 (define_insn_and_split "eh_return_si"
14096 [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")]
14097 UNSPECV_EH_RETURN)]
14102 "ix86_expand_epilogue (2); DONE;")
14104 (define_insn_and_split "eh_return_di"
14105 [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
14106 UNSPECV_EH_RETURN)]
14111 "ix86_expand_epilogue (2); DONE;")
14113 (define_insn "leave"
14114 [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4)))
14115 (set (reg:SI 6) (mem:SI (reg:SI 6)))
14116 (clobber (mem:BLK (scratch)))]
14119 [(set_attr "type" "leave")])
14121 (define_insn "leave_rex64"
14122 [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8)))
14123 (set (reg:DI 6) (mem:DI (reg:DI 6)))
14124 (clobber (mem:BLK (scratch)))]
14127 [(set_attr "type" "leave")])
14129 (define_expand "ffssi2"
14131 [(set (match_operand:SI 0 "register_operand" "")
14132 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
14133 (clobber (match_scratch:SI 2 ""))
14134 (clobber (reg:CC 17))])]
14138 (define_insn_and_split "*ffs_cmove"
14139 [(set (match_operand:SI 0 "register_operand" "=r")
14140 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14141 (clobber (match_scratch:SI 2 "=&r"))
14142 (clobber (reg:CC 17))]
14145 "&& reload_completed"
14146 [(set (match_dup 2) (const_int -1))
14147 (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
14148 (set (match_dup 0) (ctz:SI (match_dup 1)))])
14149 (set (match_dup 0) (if_then_else:SI
14150 (eq (reg:CCZ 17) (const_int 0))
14153 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14154 (clobber (reg:CC 17))])]
14157 (define_insn_and_split "*ffs_no_cmove"
14158 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
14159 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14160 (clobber (match_scratch:SI 2 "=&r"))
14161 (clobber (reg:CC 17))]
14165 [(parallel [(set (match_dup 2) (const_int 0))
14166 (clobber (reg:CC 17))])
14167 (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
14168 (set (match_dup 0) (ctz:SI (match_dup 1)))])
14169 (set (strict_low_part (match_dup 3))
14170 (eq:QI (reg:CCZ 17) (const_int 0)))
14171 (parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
14172 (clobber (reg:CC 17))])
14173 (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
14174 (clobber (reg:CC 17))])
14175 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14176 (clobber (reg:CC 17))])]
14178 operands[3] = gen_lowpart (QImode, operands[2]);
14181 (define_insn "*ffssi_1"
14183 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
14185 (set (match_operand:SI 0 "register_operand" "=r")
14186 (ctz:SI (match_dup 1)))]
14188 "bsf{l}\t{%1, %0|%0, %1}"
14189 [(set_attr "prefix_0f" "1")
14190 (set_attr "ppro_uops" "few")])
14192 (define_insn "ctzsi2"
14193 [(set (match_operand:SI 0 "register_operand" "=r")
14194 (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14195 (clobber (reg:CC 17))]
14197 "bsf{l}\t{%1, %0|%0, %1}"
14198 [(set_attr "prefix_0f" "1")
14199 (set_attr "ppro_uops" "few")])
14201 (define_expand "clzsi2"
14203 [(set (match_operand:SI 0 "register_operand" "")
14204 (minus:SI (const_int 31)
14205 (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
14206 (clobber (reg:CC 17))])
14208 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
14209 (clobber (reg:CC 17))])]
14213 (define_insn "*bsr"
14214 [(set (match_operand:SI 0 "register_operand" "=r")
14215 (minus:SI (const_int 31)
14216 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
14217 (clobber (reg:CC 17))]
14219 "bsr{l}\t{%1, %0|%0, %1}"
14220 [(set_attr "prefix_0f" "1")
14221 (set_attr "ppro_uops" "few")])
14223 ;; Thread-local storage patterns for ELF.
14225 ;; Note that these code sequences must appear exactly as shown
14226 ;; in order to allow linker relaxation.
14228 (define_insn "*tls_global_dynamic_32_gnu"
14229 [(set (match_operand:SI 0 "register_operand" "=a")
14230 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14231 (match_operand:SI 2 "tls_symbolic_operand" "")
14232 (match_operand:SI 3 "call_insn_operand" "")]
14234 (clobber (match_scratch:SI 4 "=d"))
14235 (clobber (match_scratch:SI 5 "=c"))
14236 (clobber (reg:CC 17))]
14237 "!TARGET_64BIT && TARGET_GNU_TLS"
14238 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
14239 [(set_attr "type" "multi")
14240 (set_attr "length" "12")])
14242 (define_insn "*tls_global_dynamic_32_sun"
14243 [(set (match_operand:SI 0 "register_operand" "=a")
14244 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14245 (match_operand:SI 2 "tls_symbolic_operand" "")
14246 (match_operand:SI 3 "call_insn_operand" "")]
14248 (clobber (match_scratch:SI 4 "=d"))
14249 (clobber (match_scratch:SI 5 "=c"))
14250 (clobber (reg:CC 17))]
14251 "!TARGET_64BIT && TARGET_SUN_TLS"
14252 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
14253 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
14254 [(set_attr "type" "multi")
14255 (set_attr "length" "14")])
14257 (define_expand "tls_global_dynamic_32"
14258 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14261 (match_operand:SI 1 "tls_symbolic_operand" "")
14264 (clobber (match_scratch:SI 4 ""))
14265 (clobber (match_scratch:SI 5 ""))
14266 (clobber (reg:CC 17))])]
14270 operands[2] = pic_offset_table_rtx;
14273 operands[2] = gen_reg_rtx (Pmode);
14274 emit_insn (gen_set_got (operands[2]));
14276 operands[3] = ix86_tls_get_addr ();
14279 (define_insn "*tls_global_dynamic_64"
14280 [(set (match_operand:DI 0 "register_operand" "=a")
14281 (call (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
14282 (match_operand:DI 3 "" "")))
14283 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14286 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
14287 [(set_attr "type" "multi")
14288 (set_attr "length" "16")])
14290 (define_expand "tls_global_dynamic_64"
14291 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14292 (call (mem:QI (match_dup 2)) (const_int 0)))
14293 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14297 operands[2] = ix86_tls_get_addr ();
14300 (define_insn "*tls_local_dynamic_base_32_gnu"
14301 [(set (match_operand:SI 0 "register_operand" "=a")
14302 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14303 (match_operand:SI 2 "call_insn_operand" "")]
14304 UNSPEC_TLS_LD_BASE))
14305 (clobber (match_scratch:SI 3 "=d"))
14306 (clobber (match_scratch:SI 4 "=c"))
14307 (clobber (reg:CC 17))]
14308 "!TARGET_64BIT && TARGET_GNU_TLS"
14309 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
14310 [(set_attr "type" "multi")
14311 (set_attr "length" "11")])
14313 (define_insn "*tls_local_dynamic_base_32_sun"
14314 [(set (match_operand:SI 0 "register_operand" "=a")
14315 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14316 (match_operand:SI 2 "call_insn_operand" "")]
14317 UNSPEC_TLS_LD_BASE))
14318 (clobber (match_scratch:SI 3 "=d"))
14319 (clobber (match_scratch:SI 4 "=c"))
14320 (clobber (reg:CC 17))]
14321 "!TARGET_64BIT && TARGET_SUN_TLS"
14322 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
14323 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
14324 [(set_attr "type" "multi")
14325 (set_attr "length" "13")])
14327 (define_expand "tls_local_dynamic_base_32"
14328 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14329 (unspec:SI [(match_dup 1) (match_dup 2)]
14330 UNSPEC_TLS_LD_BASE))
14331 (clobber (match_scratch:SI 3 ""))
14332 (clobber (match_scratch:SI 4 ""))
14333 (clobber (reg:CC 17))])]
14337 operands[1] = pic_offset_table_rtx;
14340 operands[1] = gen_reg_rtx (Pmode);
14341 emit_insn (gen_set_got (operands[1]));
14343 operands[2] = ix86_tls_get_addr ();
14346 (define_insn "*tls_local_dynamic_base_64"
14347 [(set (match_operand:DI 0 "register_operand" "=a")
14348 (call (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
14349 (match_operand:DI 2 "" "")))
14350 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
14352 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
14353 [(set_attr "type" "multi")
14354 (set_attr "length" "12")])
14356 (define_expand "tls_local_dynamic_base_64"
14357 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14358 (call (mem:QI (match_dup 1)) (const_int 0)))
14359 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
14362 operands[1] = ix86_tls_get_addr ();
14365 ;; Local dynamic of a single variable is a lose. Show combine how
14366 ;; to convert that back to global dynamic.
14368 (define_insn_and_split "*tls_local_dynamic_32_once"
14369 [(set (match_operand:SI 0 "register_operand" "=a")
14370 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14371 (match_operand:SI 2 "call_insn_operand" "")]
14372 UNSPEC_TLS_LD_BASE)
14373 (const:SI (unspec:SI
14374 [(match_operand:SI 3 "tls_symbolic_operand" "")]
14376 (clobber (match_scratch:SI 4 "=d"))
14377 (clobber (match_scratch:SI 5 "=c"))
14378 (clobber (reg:CC 17))]
14382 [(parallel [(set (match_dup 0)
14383 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
14385 (clobber (match_dup 4))
14386 (clobber (match_dup 5))
14387 (clobber (reg:CC 17))])]
14390 ;; These patterns match the binary 387 instructions for addM3, subM3,
14391 ;; mulM3 and divM3. There are three patterns for each of DFmode and
14392 ;; SFmode. The first is the normal insn, the second the same insn but
14393 ;; with one operand a conversion, and the third the same insn but with
14394 ;; the other operand a conversion. The conversion may be SFmode or
14395 ;; SImode if the target mode DFmode, but only SImode if the target mode
14398 ;; Gcc is slightly more smart about handling normal two address instructions
14399 ;; so use special patterns for add and mull.
14400 (define_insn "*fop_sf_comm_nosse"
14401 [(set (match_operand:SF 0 "register_operand" "=f")
14402 (match_operator:SF 3 "binary_fp_operator"
14403 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14404 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
14405 "TARGET_80387 && !TARGET_SSE_MATH
14406 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14407 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14408 "* return output_387_binary_op (insn, operands);"
14409 [(set (attr "type")
14410 (if_then_else (match_operand:SF 3 "mult_operator" "")
14411 (const_string "fmul")
14412 (const_string "fop")))
14413 (set_attr "mode" "SF")])
14415 (define_insn "*fop_sf_comm"
14416 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14417 (match_operator:SF 3 "binary_fp_operator"
14418 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
14419 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
14420 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14421 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14422 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14423 "* return output_387_binary_op (insn, operands);"
14424 [(set (attr "type")
14425 (if_then_else (eq_attr "alternative" "1")
14426 (if_then_else (match_operand:SF 3 "mult_operator" "")
14427 (const_string "ssemul")
14428 (const_string "sseadd"))
14429 (if_then_else (match_operand:SF 3 "mult_operator" "")
14430 (const_string "fmul")
14431 (const_string "fop"))))
14432 (set_attr "mode" "SF")])
14434 (define_insn "*fop_sf_comm_sse"
14435 [(set (match_operand:SF 0 "register_operand" "=x")
14436 (match_operator:SF 3 "binary_fp_operator"
14437 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14438 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14439 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14440 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14441 "* return output_387_binary_op (insn, operands);"
14442 [(set (attr "type")
14443 (if_then_else (match_operand:SF 3 "mult_operator" "")
14444 (const_string "ssemul")
14445 (const_string "sseadd")))
14446 (set_attr "mode" "SF")])
14448 (define_insn "*fop_df_comm_nosse"
14449 [(set (match_operand:DF 0 "register_operand" "=f")
14450 (match_operator:DF 3 "binary_fp_operator"
14451 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14452 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
14453 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14454 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14455 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14456 "* return output_387_binary_op (insn, operands);"
14457 [(set (attr "type")
14458 (if_then_else (match_operand:SF 3 "mult_operator" "")
14459 (const_string "fmul")
14460 (const_string "fop")))
14461 (set_attr "mode" "DF")])
14463 (define_insn "*fop_df_comm"
14464 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14465 (match_operator:DF 3 "binary_fp_operator"
14466 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
14467 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
14468 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
14469 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14470 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14471 "* return output_387_binary_op (insn, operands);"
14472 [(set (attr "type")
14473 (if_then_else (eq_attr "alternative" "1")
14474 (if_then_else (match_operand:SF 3 "mult_operator" "")
14475 (const_string "ssemul")
14476 (const_string "sseadd"))
14477 (if_then_else (match_operand:SF 3 "mult_operator" "")
14478 (const_string "fmul")
14479 (const_string "fop"))))
14480 (set_attr "mode" "DF")])
14482 (define_insn "*fop_df_comm_sse"
14483 [(set (match_operand:DF 0 "register_operand" "=Y")
14484 (match_operator:DF 3 "binary_fp_operator"
14485 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14486 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14487 "TARGET_SSE2 && TARGET_SSE_MATH
14488 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14489 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14490 "* return output_387_binary_op (insn, operands);"
14491 [(set (attr "type")
14492 (if_then_else (match_operand:SF 3 "mult_operator" "")
14493 (const_string "ssemul")
14494 (const_string "sseadd")))
14495 (set_attr "mode" "DF")])
14497 (define_insn "*fop_xf_comm"
14498 [(set (match_operand:XF 0 "register_operand" "=f")
14499 (match_operator:XF 3 "binary_fp_operator"
14500 [(match_operand:XF 1 "register_operand" "%0")
14501 (match_operand:XF 2 "register_operand" "f")]))]
14502 "!TARGET_64BIT && TARGET_80387
14503 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14504 "* return output_387_binary_op (insn, operands);"
14505 [(set (attr "type")
14506 (if_then_else (match_operand:XF 3 "mult_operator" "")
14507 (const_string "fmul")
14508 (const_string "fop")))
14509 (set_attr "mode" "XF")])
14511 (define_insn "*fop_tf_comm"
14512 [(set (match_operand:TF 0 "register_operand" "=f")
14513 (match_operator:TF 3 "binary_fp_operator"
14514 [(match_operand:TF 1 "register_operand" "%0")
14515 (match_operand:TF 2 "register_operand" "f")]))]
14516 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14517 "* return output_387_binary_op (insn, operands);"
14518 [(set (attr "type")
14519 (if_then_else (match_operand:TF 3 "mult_operator" "")
14520 (const_string "fmul")
14521 (const_string "fop")))
14522 (set_attr "mode" "XF")])
14524 (define_insn "*fop_sf_1_nosse"
14525 [(set (match_operand:SF 0 "register_operand" "=f,f")
14526 (match_operator:SF 3 "binary_fp_operator"
14527 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
14528 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
14529 "TARGET_80387 && !TARGET_SSE_MATH
14530 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14531 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14532 "* return output_387_binary_op (insn, operands);"
14533 [(set (attr "type")
14534 (cond [(match_operand:SF 3 "mult_operator" "")
14535 (const_string "fmul")
14536 (match_operand:SF 3 "div_operator" "")
14537 (const_string "fdiv")
14539 (const_string "fop")))
14540 (set_attr "mode" "SF")])
14542 (define_insn "*fop_sf_1"
14543 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
14544 (match_operator:SF 3 "binary_fp_operator"
14545 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14546 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14547 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14548 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14549 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14550 "* return output_387_binary_op (insn, operands);"
14551 [(set (attr "type")
14552 (cond [(and (eq_attr "alternative" "2")
14553 (match_operand:SF 3 "mult_operator" ""))
14554 (const_string "ssemul")
14555 (and (eq_attr "alternative" "2")
14556 (match_operand:SF 3 "div_operator" ""))
14557 (const_string "ssediv")
14558 (eq_attr "alternative" "2")
14559 (const_string "sseadd")
14560 (match_operand:SF 3 "mult_operator" "")
14561 (const_string "fmul")
14562 (match_operand:SF 3 "div_operator" "")
14563 (const_string "fdiv")
14565 (const_string "fop")))
14566 (set_attr "mode" "SF")])
14568 (define_insn "*fop_sf_1_sse"
14569 [(set (match_operand:SF 0 "register_operand" "=x")
14570 (match_operator:SF 3 "binary_fp_operator"
14571 [(match_operand:SF 1 "register_operand" "0")
14572 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14574 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14575 "* return output_387_binary_op (insn, operands);"
14576 [(set (attr "type")
14577 (cond [(match_operand:SF 3 "mult_operator" "")
14578 (const_string "ssemul")
14579 (match_operand:SF 3 "div_operator" "")
14580 (const_string "ssediv")
14582 (const_string "sseadd")))
14583 (set_attr "mode" "SF")])
14585 ;; ??? Add SSE splitters for these!
14586 (define_insn "*fop_sf_2"
14587 [(set (match_operand:SF 0 "register_operand" "=f,f")
14588 (match_operator:SF 3 "binary_fp_operator"
14589 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14590 (match_operand:SF 2 "register_operand" "0,0")]))]
14591 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14592 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14593 [(set (attr "type")
14594 (cond [(match_operand:SF 3 "mult_operator" "")
14595 (const_string "fmul")
14596 (match_operand:SF 3 "div_operator" "")
14597 (const_string "fdiv")
14599 (const_string "fop")))
14600 (set_attr "fp_int_src" "true")
14601 (set_attr "ppro_uops" "many")
14602 (set_attr "mode" "SI")])
14604 (define_insn "*fop_sf_3"
14605 [(set (match_operand:SF 0 "register_operand" "=f,f")
14606 (match_operator:SF 3 "binary_fp_operator"
14607 [(match_operand:SF 1 "register_operand" "0,0")
14608 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14609 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14610 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14611 [(set (attr "type")
14612 (cond [(match_operand:SF 3 "mult_operator" "")
14613 (const_string "fmul")
14614 (match_operand:SF 3 "div_operator" "")
14615 (const_string "fdiv")
14617 (const_string "fop")))
14618 (set_attr "fp_int_src" "true")
14619 (set_attr "ppro_uops" "many")
14620 (set_attr "mode" "SI")])
14622 (define_insn "*fop_df_1_nosse"
14623 [(set (match_operand:DF 0 "register_operand" "=f,f")
14624 (match_operator:DF 3 "binary_fp_operator"
14625 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
14626 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14627 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14628 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14629 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14630 "* return output_387_binary_op (insn, operands);"
14631 [(set (attr "type")
14632 (cond [(match_operand:DF 3 "mult_operator" "")
14633 (const_string "fmul")
14634 (match_operand:DF 3 "div_operator" "")
14635 (const_string "fdiv")
14637 (const_string "fop")))
14638 (set_attr "mode" "DF")])
14641 (define_insn "*fop_df_1"
14642 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14643 (match_operator:DF 3 "binary_fp_operator"
14644 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14645 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14646 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14647 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14648 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14649 "* return output_387_binary_op (insn, operands);"
14650 [(set (attr "type")
14651 (cond [(and (eq_attr "alternative" "2")
14652 (match_operand:SF 3 "mult_operator" ""))
14653 (const_string "ssemul")
14654 (and (eq_attr "alternative" "2")
14655 (match_operand:SF 3 "div_operator" ""))
14656 (const_string "ssediv")
14657 (eq_attr "alternative" "2")
14658 (const_string "sseadd")
14659 (match_operand:DF 3 "mult_operator" "")
14660 (const_string "fmul")
14661 (match_operand:DF 3 "div_operator" "")
14662 (const_string "fdiv")
14664 (const_string "fop")))
14665 (set_attr "mode" "DF")])
14667 (define_insn "*fop_df_1_sse"
14668 [(set (match_operand:DF 0 "register_operand" "=Y")
14669 (match_operator:DF 3 "binary_fp_operator"
14670 [(match_operand:DF 1 "register_operand" "0")
14671 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14672 "TARGET_SSE2 && TARGET_SSE_MATH
14673 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14674 "* return output_387_binary_op (insn, operands);"
14675 [(set_attr "mode" "DF")
14677 (cond [(match_operand:SF 3 "mult_operator" "")
14678 (const_string "ssemul")
14679 (match_operand:SF 3 "div_operator" "")
14680 (const_string "ssediv")
14682 (const_string "sseadd")))])
14684 ;; ??? Add SSE splitters for these!
14685 (define_insn "*fop_df_2"
14686 [(set (match_operand:DF 0 "register_operand" "=f,f")
14687 (match_operator:DF 3 "binary_fp_operator"
14688 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14689 (match_operand:DF 2 "register_operand" "0,0")]))]
14690 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14691 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14692 [(set (attr "type")
14693 (cond [(match_operand:DF 3 "mult_operator" "")
14694 (const_string "fmul")
14695 (match_operand:DF 3 "div_operator" "")
14696 (const_string "fdiv")
14698 (const_string "fop")))
14699 (set_attr "fp_int_src" "true")
14700 (set_attr "ppro_uops" "many")
14701 (set_attr "mode" "SI")])
14703 (define_insn "*fop_df_3"
14704 [(set (match_operand:DF 0 "register_operand" "=f,f")
14705 (match_operator:DF 3 "binary_fp_operator"
14706 [(match_operand:DF 1 "register_operand" "0,0")
14707 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14708 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14709 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14710 [(set (attr "type")
14711 (cond [(match_operand:DF 3 "mult_operator" "")
14712 (const_string "fmul")
14713 (match_operand:DF 3 "div_operator" "")
14714 (const_string "fdiv")
14716 (const_string "fop")))
14717 (set_attr "fp_int_src" "true")
14718 (set_attr "ppro_uops" "many")
14719 (set_attr "mode" "SI")])
14721 (define_insn "*fop_df_4"
14722 [(set (match_operand:DF 0 "register_operand" "=f,f")
14723 (match_operator:DF 3 "binary_fp_operator"
14724 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14725 (match_operand:DF 2 "register_operand" "0,f")]))]
14726 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14727 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14728 "* return output_387_binary_op (insn, operands);"
14729 [(set (attr "type")
14730 (cond [(match_operand:DF 3 "mult_operator" "")
14731 (const_string "fmul")
14732 (match_operand:DF 3 "div_operator" "")
14733 (const_string "fdiv")
14735 (const_string "fop")))
14736 (set_attr "mode" "SF")])
14738 (define_insn "*fop_df_5"
14739 [(set (match_operand:DF 0 "register_operand" "=f,f")
14740 (match_operator:DF 3 "binary_fp_operator"
14741 [(match_operand:DF 1 "register_operand" "0,f")
14743 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14744 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14745 "* return output_387_binary_op (insn, operands);"
14746 [(set (attr "type")
14747 (cond [(match_operand:DF 3 "mult_operator" "")
14748 (const_string "fmul")
14749 (match_operand:DF 3 "div_operator" "")
14750 (const_string "fdiv")
14752 (const_string "fop")))
14753 (set_attr "mode" "SF")])
14755 (define_insn "*fop_df_6"
14756 [(set (match_operand:DF 0 "register_operand" "=f,f")
14757 (match_operator:DF 3 "binary_fp_operator"
14759 (match_operand:SF 1 "register_operand" "0,f"))
14761 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14762 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14763 "* return output_387_binary_op (insn, operands);"
14764 [(set (attr "type")
14765 (cond [(match_operand:DF 3 "mult_operator" "")
14766 (const_string "fmul")
14767 (match_operand:DF 3 "div_operator" "")
14768 (const_string "fdiv")
14770 (const_string "fop")))
14771 (set_attr "mode" "SF")])
14773 (define_insn "*fop_xf_1"
14774 [(set (match_operand:XF 0 "register_operand" "=f,f")
14775 (match_operator:XF 3 "binary_fp_operator"
14776 [(match_operand:XF 1 "register_operand" "0,f")
14777 (match_operand:XF 2 "register_operand" "f,0")]))]
14778 "!TARGET_64BIT && TARGET_80387
14779 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14780 "* return output_387_binary_op (insn, operands);"
14781 [(set (attr "type")
14782 (cond [(match_operand:XF 3 "mult_operator" "")
14783 (const_string "fmul")
14784 (match_operand:XF 3 "div_operator" "")
14785 (const_string "fdiv")
14787 (const_string "fop")))
14788 (set_attr "mode" "XF")])
14790 (define_insn "*fop_tf_1"
14791 [(set (match_operand:TF 0 "register_operand" "=f,f")
14792 (match_operator:TF 3 "binary_fp_operator"
14793 [(match_operand:TF 1 "register_operand" "0,f")
14794 (match_operand:TF 2 "register_operand" "f,0")]))]
14796 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14797 "* return output_387_binary_op (insn, operands);"
14798 [(set (attr "type")
14799 (cond [(match_operand:TF 3 "mult_operator" "")
14800 (const_string "fmul")
14801 (match_operand:TF 3 "div_operator" "")
14802 (const_string "fdiv")
14804 (const_string "fop")))
14805 (set_attr "mode" "XF")])
14807 (define_insn "*fop_xf_2"
14808 [(set (match_operand:XF 0 "register_operand" "=f,f")
14809 (match_operator:XF 3 "binary_fp_operator"
14810 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14811 (match_operand:XF 2 "register_operand" "0,0")]))]
14812 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
14813 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14814 [(set (attr "type")
14815 (cond [(match_operand:XF 3 "mult_operator" "")
14816 (const_string "fmul")
14817 (match_operand:XF 3 "div_operator" "")
14818 (const_string "fdiv")
14820 (const_string "fop")))
14821 (set_attr "fp_int_src" "true")
14822 (set_attr "mode" "SI")
14823 (set_attr "ppro_uops" "many")])
14825 (define_insn "*fop_tf_2"
14826 [(set (match_operand:TF 0 "register_operand" "=f,f")
14827 (match_operator:TF 3 "binary_fp_operator"
14828 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14829 (match_operand:TF 2 "register_operand" "0,0")]))]
14830 "TARGET_80387 && TARGET_USE_FIOP"
14831 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14832 [(set (attr "type")
14833 (cond [(match_operand:TF 3 "mult_operator" "")
14834 (const_string "fmul")
14835 (match_operand:TF 3 "div_operator" "")
14836 (const_string "fdiv")
14838 (const_string "fop")))
14839 (set_attr "fp_int_src" "true")
14840 (set_attr "mode" "SI")
14841 (set_attr "ppro_uops" "many")])
14843 (define_insn "*fop_xf_3"
14844 [(set (match_operand:XF 0 "register_operand" "=f,f")
14845 (match_operator:XF 3 "binary_fp_operator"
14846 [(match_operand:XF 1 "register_operand" "0,0")
14847 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14848 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
14849 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14850 [(set (attr "type")
14851 (cond [(match_operand:XF 3 "mult_operator" "")
14852 (const_string "fmul")
14853 (match_operand:XF 3 "div_operator" "")
14854 (const_string "fdiv")
14856 (const_string "fop")))
14857 (set_attr "fp_int_src" "true")
14858 (set_attr "mode" "SI")
14859 (set_attr "ppro_uops" "many")])
14861 (define_insn "*fop_tf_3"
14862 [(set (match_operand:TF 0 "register_operand" "=f,f")
14863 (match_operator:TF 3 "binary_fp_operator"
14864 [(match_operand:TF 1 "register_operand" "0,0")
14865 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14866 "TARGET_80387 && TARGET_USE_FIOP"
14867 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14868 [(set (attr "type")
14869 (cond [(match_operand:TF 3 "mult_operator" "")
14870 (const_string "fmul")
14871 (match_operand:TF 3 "div_operator" "")
14872 (const_string "fdiv")
14874 (const_string "fop")))
14875 (set_attr "fp_int_src" "true")
14876 (set_attr "mode" "SI")
14877 (set_attr "ppro_uops" "many")])
14879 (define_insn "*fop_xf_4"
14880 [(set (match_operand:XF 0 "register_operand" "=f,f")
14881 (match_operator:XF 3 "binary_fp_operator"
14882 [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
14883 (match_operand:XF 2 "register_operand" "0,f")]))]
14884 "!TARGET_64BIT && TARGET_80387"
14885 "* return output_387_binary_op (insn, operands);"
14886 [(set (attr "type")
14887 (cond [(match_operand:XF 3 "mult_operator" "")
14888 (const_string "fmul")
14889 (match_operand:XF 3 "div_operator" "")
14890 (const_string "fdiv")
14892 (const_string "fop")))
14893 (set_attr "mode" "SF")])
14895 (define_insn "*fop_tf_4"
14896 [(set (match_operand:TF 0 "register_operand" "=f,f")
14897 (match_operator:TF 3 "binary_fp_operator"
14898 [(float_extend:TF (match_operand 1 "nonimmediate_operand" "fm,0"))
14899 (match_operand:TF 2 "register_operand" "0,f")]))]
14901 "* return output_387_binary_op (insn, operands);"
14902 [(set (attr "type")
14903 (cond [(match_operand:TF 3 "mult_operator" "")
14904 (const_string "fmul")
14905 (match_operand:TF 3 "div_operator" "")
14906 (const_string "fdiv")
14908 (const_string "fop")))
14909 (set_attr "mode" "SF")])
14911 (define_insn "*fop_xf_5"
14912 [(set (match_operand:XF 0 "register_operand" "=f,f")
14913 (match_operator:XF 3 "binary_fp_operator"
14914 [(match_operand:XF 1 "register_operand" "0,f")
14916 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14917 "!TARGET_64BIT && TARGET_80387"
14918 "* return output_387_binary_op (insn, operands);"
14919 [(set (attr "type")
14920 (cond [(match_operand:XF 3 "mult_operator" "")
14921 (const_string "fmul")
14922 (match_operand:XF 3 "div_operator" "")
14923 (const_string "fdiv")
14925 (const_string "fop")))
14926 (set_attr "mode" "SF")])
14928 (define_insn "*fop_tf_5"
14929 [(set (match_operand:TF 0 "register_operand" "=f,f")
14930 (match_operator:TF 3 "binary_fp_operator"
14931 [(match_operand:TF 1 "register_operand" "0,f")
14933 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14935 "* return output_387_binary_op (insn, operands);"
14936 [(set (attr "type")
14937 (cond [(match_operand:TF 3 "mult_operator" "")
14938 (const_string "fmul")
14939 (match_operand:TF 3 "div_operator" "")
14940 (const_string "fdiv")
14942 (const_string "fop")))
14943 (set_attr "mode" "SF")])
14945 (define_insn "*fop_xf_6"
14946 [(set (match_operand:XF 0 "register_operand" "=f,f")
14947 (match_operator:XF 3 "binary_fp_operator"
14949 (match_operand 1 "register_operand" "0,f"))
14951 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14952 "!TARGET_64BIT && TARGET_80387"
14953 "* return output_387_binary_op (insn, operands);"
14954 [(set (attr "type")
14955 (cond [(match_operand:XF 3 "mult_operator" "")
14956 (const_string "fmul")
14957 (match_operand:XF 3 "div_operator" "")
14958 (const_string "fdiv")
14960 (const_string "fop")))
14961 (set_attr "mode" "SF")])
14963 (define_insn "*fop_tf_6"
14964 [(set (match_operand:TF 0 "register_operand" "=f,f")
14965 (match_operator:TF 3 "binary_fp_operator"
14967 (match_operand 1 "register_operand" "0,f"))
14969 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14971 "* return output_387_binary_op (insn, operands);"
14972 [(set (attr "type")
14973 (cond [(match_operand:TF 3 "mult_operator" "")
14974 (const_string "fmul")
14975 (match_operand:TF 3 "div_operator" "")
14976 (const_string "fdiv")
14978 (const_string "fop")))
14979 (set_attr "mode" "SF")])
14982 [(set (match_operand 0 "register_operand" "")
14983 (match_operator 3 "binary_fp_operator"
14984 [(float (match_operand:SI 1 "register_operand" ""))
14985 (match_operand 2 "register_operand" "")]))]
14986 "TARGET_80387 && reload_completed
14987 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14990 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14991 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14992 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14993 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14994 GET_MODE (operands[3]),
14997 ix86_free_from_memory (GET_MODE (operands[1]));
15002 [(set (match_operand 0 "register_operand" "")
15003 (match_operator 3 "binary_fp_operator"
15004 [(match_operand 1 "register_operand" "")
15005 (float (match_operand:SI 2 "register_operand" ""))]))]
15006 "TARGET_80387 && reload_completed
15007 && FLOAT_MODE_P (GET_MODE (operands[0]))"
15010 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
15011 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
15012 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15013 gen_rtx_fmt_ee (GET_CODE (operands[3]),
15014 GET_MODE (operands[3]),
15017 ix86_free_from_memory (GET_MODE (operands[2]));
15021 ;; FPU special functions.
15023 (define_expand "sqrtsf2"
15024 [(set (match_operand:SF 0 "register_operand" "")
15025 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
15026 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH"
15028 if (!TARGET_SSE_MATH)
15029 operands[1] = force_reg (SFmode, operands[1]);
15032 (define_insn "sqrtsf2_1"
15033 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
15034 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
15035 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15036 && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
15039 sqrtss\t{%1, %0|%0, %1}"
15040 [(set_attr "type" "fpspc,sse")
15041 (set_attr "mode" "SF,SF")
15042 (set_attr "athlon_decode" "direct,*")])
15044 (define_insn "sqrtsf2_1_sse_only"
15045 [(set (match_operand:SF 0 "register_operand" "=x")
15046 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
15047 "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
15048 "sqrtss\t{%1, %0|%0, %1}"
15049 [(set_attr "type" "sse")
15050 (set_attr "mode" "SF")
15051 (set_attr "athlon_decode" "*")])
15053 (define_insn "sqrtsf2_i387"
15054 [(set (match_operand:SF 0 "register_operand" "=f")
15055 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
15056 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15057 && !TARGET_SSE_MATH"
15059 [(set_attr "type" "fpspc")
15060 (set_attr "mode" "SF")
15061 (set_attr "athlon_decode" "direct")])
15063 (define_expand "sqrtdf2"
15064 [(set (match_operand:DF 0 "register_operand" "")
15065 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
15066 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
15067 || (TARGET_SSE2 && TARGET_SSE_MATH)"
15069 if (!TARGET_SSE2 || !TARGET_SSE_MATH)
15070 operands[1] = force_reg (DFmode, operands[1]);
15073 (define_insn "sqrtdf2_1"
15074 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
15075 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
15076 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15077 && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
15080 sqrtsd\t{%1, %0|%0, %1}"
15081 [(set_attr "type" "fpspc,sse")
15082 (set_attr "mode" "DF,DF")
15083 (set_attr "athlon_decode" "direct,*")])
15085 (define_insn "sqrtdf2_1_sse_only"
15086 [(set (match_operand:DF 0 "register_operand" "=Y")
15087 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
15088 "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
15089 "sqrtsd\t{%1, %0|%0, %1}"
15090 [(set_attr "type" "sse")
15091 (set_attr "mode" "DF")
15092 (set_attr "athlon_decode" "*")])
15094 (define_insn "sqrtdf2_i387"
15095 [(set (match_operand:DF 0 "register_operand" "=f")
15096 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
15097 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15098 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
15100 [(set_attr "type" "fpspc")
15101 (set_attr "mode" "DF")
15102 (set_attr "athlon_decode" "direct")])
15104 (define_insn "*sqrtextendsfdf2"
15105 [(set (match_operand:DF 0 "register_operand" "=f")
15106 (sqrt:DF (float_extend:DF
15107 (match_operand:SF 1 "register_operand" "0"))))]
15108 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15109 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
15111 [(set_attr "type" "fpspc")
15112 (set_attr "mode" "DF")
15113 (set_attr "athlon_decode" "direct")])
15115 (define_insn "sqrtxf2"
15116 [(set (match_operand:XF 0 "register_operand" "=f")
15117 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
15118 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
15119 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
15121 [(set_attr "type" "fpspc")
15122 (set_attr "mode" "XF")
15123 (set_attr "athlon_decode" "direct")])
15125 (define_insn "sqrttf2"
15126 [(set (match_operand:TF 0 "register_operand" "=f")
15127 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
15128 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15129 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
15131 [(set_attr "type" "fpspc")
15132 (set_attr "mode" "XF")
15133 (set_attr "athlon_decode" "direct")])
15135 (define_insn "*sqrtextenddfxf2"
15136 [(set (match_operand:XF 0 "register_operand" "=f")
15137 (sqrt:XF (float_extend:XF
15138 (match_operand:DF 1 "register_operand" "0"))))]
15139 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
15141 [(set_attr "type" "fpspc")
15142 (set_attr "mode" "XF")
15143 (set_attr "athlon_decode" "direct")])
15145 (define_insn "*sqrtextenddftf2"
15146 [(set (match_operand:TF 0 "register_operand" "=f")
15147 (sqrt:TF (float_extend:TF
15148 (match_operand:DF 1 "register_operand" "0"))))]
15149 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
15151 [(set_attr "type" "fpspc")
15152 (set_attr "mode" "XF")
15153 (set_attr "athlon_decode" "direct")])
15155 (define_insn "*sqrtextendsfxf2"
15156 [(set (match_operand:XF 0 "register_operand" "=f")
15157 (sqrt:XF (float_extend:XF
15158 (match_operand:SF 1 "register_operand" "0"))))]
15159 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
15161 [(set_attr "type" "fpspc")
15162 (set_attr "mode" "XF")
15163 (set_attr "athlon_decode" "direct")])
15165 (define_insn "*sqrtextendsftf2"
15166 [(set (match_operand:TF 0 "register_operand" "=f")
15167 (sqrt:TF (float_extend:TF
15168 (match_operand:SF 1 "register_operand" "0"))))]
15169 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
15171 [(set_attr "type" "fpspc")
15172 (set_attr "mode" "XF")
15173 (set_attr "athlon_decode" "direct")])
15175 (define_insn "sindf2"
15176 [(set (match_operand:DF 0 "register_operand" "=f")
15177 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
15178 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15179 && flag_unsafe_math_optimizations"
15181 [(set_attr "type" "fpspc")
15182 (set_attr "mode" "DF")])
15184 (define_insn "sinsf2"
15185 [(set (match_operand:SF 0 "register_operand" "=f")
15186 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
15187 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15188 && flag_unsafe_math_optimizations"
15190 [(set_attr "type" "fpspc")
15191 (set_attr "mode" "SF")])
15193 (define_insn "*sinextendsfdf2"
15194 [(set (match_operand:DF 0 "register_operand" "=f")
15195 (unspec:DF [(float_extend:DF
15196 (match_operand:SF 1 "register_operand" "0"))]
15198 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15199 && flag_unsafe_math_optimizations"
15201 [(set_attr "type" "fpspc")
15202 (set_attr "mode" "DF")])
15204 (define_insn "sinxf2"
15205 [(set (match_operand:XF 0 "register_operand" "=f")
15206 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
15207 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
15208 && flag_unsafe_math_optimizations"
15210 [(set_attr "type" "fpspc")
15211 (set_attr "mode" "XF")])
15213 (define_insn "sintf2"
15214 [(set (match_operand:TF 0 "register_operand" "=f")
15215 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))]
15216 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15217 && flag_unsafe_math_optimizations"
15219 [(set_attr "type" "fpspc")
15220 (set_attr "mode" "XF")])
15222 (define_insn "cosdf2"
15223 [(set (match_operand:DF 0 "register_operand" "=f")
15224 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
15225 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15226 && flag_unsafe_math_optimizations"
15228 [(set_attr "type" "fpspc")
15229 (set_attr "mode" "DF")])
15231 (define_insn "cossf2"
15232 [(set (match_operand:SF 0 "register_operand" "=f")
15233 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
15234 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15235 && flag_unsafe_math_optimizations"
15237 [(set_attr "type" "fpspc")
15238 (set_attr "mode" "SF")])
15240 (define_insn "*cosextendsfdf2"
15241 [(set (match_operand:DF 0 "register_operand" "=f")
15242 (unspec:DF [(float_extend:DF
15243 (match_operand:SF 1 "register_operand" "0"))]
15245 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15246 && flag_unsafe_math_optimizations"
15248 [(set_attr "type" "fpspc")
15249 (set_attr "mode" "DF")])
15251 (define_insn "cosxf2"
15252 [(set (match_operand:XF 0 "register_operand" "=f")
15253 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
15254 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15255 && flag_unsafe_math_optimizations"
15257 [(set_attr "type" "fpspc")
15258 (set_attr "mode" "XF")])
15260 (define_insn "costf2"
15261 [(set (match_operand:TF 0 "register_operand" "=f")
15262 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))]
15263 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15264 && flag_unsafe_math_optimizations"
15266 [(set_attr "type" "fpspc")
15267 (set_attr "mode" "XF")])
15269 ;; Block operation instructions
15272 [(set (reg:SI 19) (const_int 0))]
15275 [(set_attr "type" "cld")])
15277 (define_expand "movstrsi"
15278 [(use (match_operand:BLK 0 "memory_operand" ""))
15279 (use (match_operand:BLK 1 "memory_operand" ""))
15280 (use (match_operand:SI 2 "nonmemory_operand" ""))
15281 (use (match_operand:SI 3 "const_int_operand" ""))]
15284 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
15290 (define_expand "movstrdi"
15291 [(use (match_operand:BLK 0 "memory_operand" ""))
15292 (use (match_operand:BLK 1 "memory_operand" ""))
15293 (use (match_operand:DI 2 "nonmemory_operand" ""))
15294 (use (match_operand:DI 3 "const_int_operand" ""))]
15297 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
15303 ;; Most CPUs don't like single string operations
15304 ;; Handle this case here to simplify previous expander.
15306 (define_expand "strmovdi_rex64"
15307 [(set (match_dup 2)
15308 (mem:DI (match_operand:DI 1 "register_operand" "")))
15309 (set (mem:DI (match_operand:DI 0 "register_operand" ""))
15311 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
15312 (clobber (reg:CC 17))])
15313 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8)))
15314 (clobber (reg:CC 17))])]
15317 if (TARGET_SINGLE_STRINGOP || optimize_size)
15319 emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0],
15324 operands[2] = gen_reg_rtx (DImode);
15328 (define_expand "strmovsi"
15329 [(set (match_dup 2)
15330 (mem:SI (match_operand:SI 1 "register_operand" "")))
15331 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
15333 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
15334 (clobber (reg:CC 17))])
15335 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
15336 (clobber (reg:CC 17))])]
15341 emit_insn (gen_strmovsi_rex64 (operands[0], operands[1]));
15344 if (TARGET_SINGLE_STRINGOP || optimize_size)
15346 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
15351 operands[2] = gen_reg_rtx (SImode);
15354 (define_expand "strmovsi_rex64"
15355 [(set (match_dup 2)
15356 (mem:SI (match_operand:DI 1 "register_operand" "")))
15357 (set (mem:SI (match_operand:DI 0 "register_operand" ""))
15359 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
15360 (clobber (reg:CC 17))])
15361 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4)))
15362 (clobber (reg:CC 17))])]
15365 if (TARGET_SINGLE_STRINGOP || optimize_size)
15367 emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0],
15372 operands[2] = gen_reg_rtx (SImode);
15375 (define_expand "strmovhi"
15376 [(set (match_dup 2)
15377 (mem:HI (match_operand:SI 1 "register_operand" "")))
15378 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
15380 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
15381 (clobber (reg:CC 17))])
15382 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
15383 (clobber (reg:CC 17))])]
15388 emit_insn (gen_strmovhi_rex64 (operands[0], operands[1]));
15391 if (TARGET_SINGLE_STRINGOP || optimize_size)
15393 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
15398 operands[2] = gen_reg_rtx (HImode);
15401 (define_expand "strmovhi_rex64"
15402 [(set (match_dup 2)
15403 (mem:HI (match_operand:DI 1 "register_operand" "")))
15404 (set (mem:HI (match_operand:DI 0 "register_operand" ""))
15406 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
15407 (clobber (reg:CC 17))])
15408 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2)))
15409 (clobber (reg:CC 17))])]
15412 if (TARGET_SINGLE_STRINGOP || optimize_size)
15414 emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0],
15419 operands[2] = gen_reg_rtx (HImode);
15422 (define_expand "strmovqi"
15423 [(set (match_dup 2)
15424 (mem:QI (match_operand:SI 1 "register_operand" "")))
15425 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
15427 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
15428 (clobber (reg:CC 17))])
15429 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
15430 (clobber (reg:CC 17))])]
15435 emit_insn (gen_strmovqi_rex64 (operands[0], operands[1]));
15438 if (TARGET_SINGLE_STRINGOP || optimize_size)
15440 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
15445 operands[2] = gen_reg_rtx (QImode);
15448 (define_expand "strmovqi_rex64"
15449 [(set (match_dup 2)
15450 (mem:QI (match_operand:DI 1 "register_operand" "")))
15451 (set (mem:QI (match_operand:DI 0 "register_operand" ""))
15453 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
15454 (clobber (reg:CC 17))])
15455 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
15456 (clobber (reg:CC 17))])]
15459 if (TARGET_SINGLE_STRINGOP || optimize_size)
15461 emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0],
15466 operands[2] = gen_reg_rtx (QImode);
15469 (define_insn "strmovdi_rex_1"
15470 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
15471 (mem:DI (match_operand:DI 3 "register_operand" "1")))
15472 (set (match_operand:DI 0 "register_operand" "=D")
15473 (plus:DI (match_dup 2)
15475 (set (match_operand:DI 1 "register_operand" "=S")
15476 (plus:DI (match_dup 3)
15479 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15481 [(set_attr "type" "str")
15482 (set_attr "mode" "DI")
15483 (set_attr "memory" "both")])
15485 (define_insn "strmovsi_1"
15486 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
15487 (mem:SI (match_operand:SI 3 "register_operand" "1")))
15488 (set (match_operand:SI 0 "register_operand" "=D")
15489 (plus:SI (match_dup 2)
15491 (set (match_operand:SI 1 "register_operand" "=S")
15492 (plus:SI (match_dup 3)
15495 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15497 [(set_attr "type" "str")
15498 (set_attr "mode" "SI")
15499 (set_attr "memory" "both")])
15501 (define_insn "strmovsi_rex_1"
15502 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
15503 (mem:SI (match_operand:DI 3 "register_operand" "1")))
15504 (set (match_operand:DI 0 "register_operand" "=D")
15505 (plus:DI (match_dup 2)
15507 (set (match_operand:DI 1 "register_operand" "=S")
15508 (plus:DI (match_dup 3)
15511 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15513 [(set_attr "type" "str")
15514 (set_attr "mode" "SI")
15515 (set_attr "memory" "both")])
15517 (define_insn "strmovhi_1"
15518 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
15519 (mem:HI (match_operand:SI 3 "register_operand" "1")))
15520 (set (match_operand:SI 0 "register_operand" "=D")
15521 (plus:SI (match_dup 2)
15523 (set (match_operand:SI 1 "register_operand" "=S")
15524 (plus:SI (match_dup 3)
15527 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15529 [(set_attr "type" "str")
15530 (set_attr "memory" "both")
15531 (set_attr "mode" "HI")])
15533 (define_insn "strmovhi_rex_1"
15534 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
15535 (mem:HI (match_operand:DI 3 "register_operand" "1")))
15536 (set (match_operand:DI 0 "register_operand" "=D")
15537 (plus:DI (match_dup 2)
15539 (set (match_operand:DI 1 "register_operand" "=S")
15540 (plus:DI (match_dup 3)
15543 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15545 [(set_attr "type" "str")
15546 (set_attr "memory" "both")
15547 (set_attr "mode" "HI")])
15549 (define_insn "strmovqi_1"
15550 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
15551 (mem:QI (match_operand:SI 3 "register_operand" "1")))
15552 (set (match_operand:SI 0 "register_operand" "=D")
15553 (plus:SI (match_dup 2)
15555 (set (match_operand:SI 1 "register_operand" "=S")
15556 (plus:SI (match_dup 3)
15559 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15561 [(set_attr "type" "str")
15562 (set_attr "memory" "both")
15563 (set_attr "mode" "QI")])
15565 (define_insn "strmovqi_rex_1"
15566 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
15567 (mem:QI (match_operand:DI 3 "register_operand" "1")))
15568 (set (match_operand:DI 0 "register_operand" "=D")
15569 (plus:DI (match_dup 2)
15571 (set (match_operand:DI 1 "register_operand" "=S")
15572 (plus:DI (match_dup 3)
15575 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15577 [(set_attr "type" "str")
15578 (set_attr "memory" "both")
15579 (set_attr "mode" "QI")])
15581 (define_insn "rep_movdi_rex64"
15582 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15583 (set (match_operand:DI 0 "register_operand" "=D")
15584 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15586 (match_operand:DI 3 "register_operand" "0")))
15587 (set (match_operand:DI 1 "register_operand" "=S")
15588 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
15589 (match_operand:DI 4 "register_operand" "1")))
15590 (set (mem:BLK (match_dup 3))
15591 (mem:BLK (match_dup 4)))
15592 (use (match_dup 5))
15595 "{rep\;movsq|rep movsq}"
15596 [(set_attr "type" "str")
15597 (set_attr "prefix_rep" "1")
15598 (set_attr "memory" "both")
15599 (set_attr "mode" "DI")])
15601 (define_insn "rep_movsi"
15602 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
15603 (set (match_operand:SI 0 "register_operand" "=D")
15604 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
15606 (match_operand:SI 3 "register_operand" "0")))
15607 (set (match_operand:SI 1 "register_operand" "=S")
15608 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
15609 (match_operand:SI 4 "register_operand" "1")))
15610 (set (mem:BLK (match_dup 3))
15611 (mem:BLK (match_dup 4)))
15612 (use (match_dup 5))
15615 "{rep\;movsl|rep movsd}"
15616 [(set_attr "type" "str")
15617 (set_attr "prefix_rep" "1")
15618 (set_attr "memory" "both")
15619 (set_attr "mode" "SI")])
15621 (define_insn "rep_movsi_rex64"
15622 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15623 (set (match_operand:DI 0 "register_operand" "=D")
15624 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15626 (match_operand:DI 3 "register_operand" "0")))
15627 (set (match_operand:DI 1 "register_operand" "=S")
15628 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
15629 (match_operand:DI 4 "register_operand" "1")))
15630 (set (mem:BLK (match_dup 3))
15631 (mem:BLK (match_dup 4)))
15632 (use (match_dup 5))
15635 "{rep\;movsl|rep movsd}"
15636 [(set_attr "type" "str")
15637 (set_attr "prefix_rep" "1")
15638 (set_attr "memory" "both")
15639 (set_attr "mode" "SI")])
15641 (define_insn "rep_movqi"
15642 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
15643 (set (match_operand:SI 0 "register_operand" "=D")
15644 (plus:SI (match_operand:SI 3 "register_operand" "0")
15645 (match_operand:SI 5 "register_operand" "2")))
15646 (set (match_operand:SI 1 "register_operand" "=S")
15647 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
15648 (set (mem:BLK (match_dup 3))
15649 (mem:BLK (match_dup 4)))
15650 (use (match_dup 5))
15653 "{rep\;movsb|rep movsb}"
15654 [(set_attr "type" "str")
15655 (set_attr "prefix_rep" "1")
15656 (set_attr "memory" "both")
15657 (set_attr "mode" "SI")])
15659 (define_insn "rep_movqi_rex64"
15660 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15661 (set (match_operand:DI 0 "register_operand" "=D")
15662 (plus:DI (match_operand:DI 3 "register_operand" "0")
15663 (match_operand:DI 5 "register_operand" "2")))
15664 (set (match_operand:DI 1 "register_operand" "=S")
15665 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
15666 (set (mem:BLK (match_dup 3))
15667 (mem:BLK (match_dup 4)))
15668 (use (match_dup 5))
15671 "{rep\;movsb|rep movsb}"
15672 [(set_attr "type" "str")
15673 (set_attr "prefix_rep" "1")
15674 (set_attr "memory" "both")
15675 (set_attr "mode" "SI")])
15677 (define_expand "clrstrsi"
15678 [(use (match_operand:BLK 0 "memory_operand" ""))
15679 (use (match_operand:SI 1 "nonmemory_operand" ""))
15680 (use (match_operand 2 "const_int_operand" ""))]
15683 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
15689 (define_expand "clrstrdi"
15690 [(use (match_operand:BLK 0 "memory_operand" ""))
15691 (use (match_operand:DI 1 "nonmemory_operand" ""))
15692 (use (match_operand 2 "const_int_operand" ""))]
15695 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
15701 ;; Most CPUs don't like single string operations
15702 ;; Handle this case here to simplify previous expander.
15704 (define_expand "strsetdi_rex64"
15705 [(set (mem:DI (match_operand:DI 0 "register_operand" ""))
15706 (match_operand:DI 1 "register_operand" ""))
15707 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
15708 (clobber (reg:CC 17))])]
15711 if (TARGET_SINGLE_STRINGOP || optimize_size)
15713 emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
15718 (define_expand "strsetsi"
15719 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
15720 (match_operand:SI 1 "register_operand" ""))
15721 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
15722 (clobber (reg:CC 17))])]
15727 emit_insn (gen_strsetsi_rex64 (operands[0], operands[1]));
15730 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15732 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
15737 (define_expand "strsetsi_rex64"
15738 [(set (mem:SI (match_operand:DI 0 "register_operand" ""))
15739 (match_operand:SI 1 "register_operand" ""))
15740 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
15741 (clobber (reg:CC 17))])]
15744 if (TARGET_SINGLE_STRINGOP || optimize_size)
15746 emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
15751 (define_expand "strsethi"
15752 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
15753 (match_operand:HI 1 "register_operand" ""))
15754 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
15755 (clobber (reg:CC 17))])]
15760 emit_insn (gen_strsethi_rex64 (operands[0], operands[1]));
15763 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15765 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
15770 (define_expand "strsethi_rex64"
15771 [(set (mem:HI (match_operand:DI 0 "register_operand" ""))
15772 (match_operand:HI 1 "register_operand" ""))
15773 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
15774 (clobber (reg:CC 17))])]
15777 if (TARGET_SINGLE_STRINGOP || optimize_size)
15779 emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
15784 (define_expand "strsetqi"
15785 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
15786 (match_operand:QI 1 "register_operand" ""))
15787 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
15788 (clobber (reg:CC 17))])]
15793 emit_insn (gen_strsetqi_rex64 (operands[0], operands[1]));
15796 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15798 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
15803 (define_expand "strsetqi_rex64"
15804 [(set (mem:QI (match_operand:DI 0 "register_operand" ""))
15805 (match_operand:QI 1 "register_operand" ""))
15806 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
15807 (clobber (reg:CC 17))])]
15810 if (TARGET_SINGLE_STRINGOP || optimize_size)
15812 emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
15817 (define_insn "strsetdi_rex_1"
15818 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15819 (match_operand:SI 2 "register_operand" "a"))
15820 (set (match_operand:DI 0 "register_operand" "=D")
15821 (plus:DI (match_dup 1)
15824 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15826 [(set_attr "type" "str")
15827 (set_attr "memory" "store")
15828 (set_attr "mode" "DI")])
15830 (define_insn "strsetsi_1"
15831 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
15832 (match_operand:SI 2 "register_operand" "a"))
15833 (set (match_operand:SI 0 "register_operand" "=D")
15834 (plus:SI (match_dup 1)
15837 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15839 [(set_attr "type" "str")
15840 (set_attr "memory" "store")
15841 (set_attr "mode" "SI")])
15843 (define_insn "strsetsi_rex_1"
15844 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15845 (match_operand:SI 2 "register_operand" "a"))
15846 (set (match_operand:DI 0 "register_operand" "=D")
15847 (plus:DI (match_dup 1)
15850 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15852 [(set_attr "type" "str")
15853 (set_attr "memory" "store")
15854 (set_attr "mode" "SI")])
15856 (define_insn "strsethi_1"
15857 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
15858 (match_operand:HI 2 "register_operand" "a"))
15859 (set (match_operand:SI 0 "register_operand" "=D")
15860 (plus:SI (match_dup 1)
15863 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15865 [(set_attr "type" "str")
15866 (set_attr "memory" "store")
15867 (set_attr "mode" "HI")])
15869 (define_insn "strsethi_rex_1"
15870 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
15871 (match_operand:HI 2 "register_operand" "a"))
15872 (set (match_operand:DI 0 "register_operand" "=D")
15873 (plus:DI (match_dup 1)
15876 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15878 [(set_attr "type" "str")
15879 (set_attr "memory" "store")
15880 (set_attr "mode" "HI")])
15882 (define_insn "strsetqi_1"
15883 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
15884 (match_operand:QI 2 "register_operand" "a"))
15885 (set (match_operand:SI 0 "register_operand" "=D")
15886 (plus:SI (match_dup 1)
15889 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15891 [(set_attr "type" "str")
15892 (set_attr "memory" "store")
15893 (set_attr "mode" "QI")])
15895 (define_insn "strsetqi_rex_1"
15896 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
15897 (match_operand:QI 2 "register_operand" "a"))
15898 (set (match_operand:DI 0 "register_operand" "=D")
15899 (plus:DI (match_dup 1)
15902 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15904 [(set_attr "type" "str")
15905 (set_attr "memory" "store")
15906 (set_attr "mode" "QI")])
15908 (define_insn "rep_stosdi_rex64"
15909 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15910 (set (match_operand:DI 0 "register_operand" "=D")
15911 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15913 (match_operand:DI 3 "register_operand" "0")))
15914 (set (mem:BLK (match_dup 3))
15916 (use (match_operand:DI 2 "register_operand" "a"))
15917 (use (match_dup 4))
15920 "{rep\;stosq|rep stosq}"
15921 [(set_attr "type" "str")
15922 (set_attr "prefix_rep" "1")
15923 (set_attr "memory" "store")
15924 (set_attr "mode" "DI")])
15926 (define_insn "rep_stossi"
15927 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15928 (set (match_operand:SI 0 "register_operand" "=D")
15929 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
15931 (match_operand:SI 3 "register_operand" "0")))
15932 (set (mem:BLK (match_dup 3))
15934 (use (match_operand:SI 2 "register_operand" "a"))
15935 (use (match_dup 4))
15938 "{rep\;stosl|rep stosd}"
15939 [(set_attr "type" "str")
15940 (set_attr "prefix_rep" "1")
15941 (set_attr "memory" "store")
15942 (set_attr "mode" "SI")])
15944 (define_insn "rep_stossi_rex64"
15945 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15946 (set (match_operand:DI 0 "register_operand" "=D")
15947 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15949 (match_operand:DI 3 "register_operand" "0")))
15950 (set (mem:BLK (match_dup 3))
15952 (use (match_operand:SI 2 "register_operand" "a"))
15953 (use (match_dup 4))
15956 "{rep\;stosl|rep stosd}"
15957 [(set_attr "type" "str")
15958 (set_attr "prefix_rep" "1")
15959 (set_attr "memory" "store")
15960 (set_attr "mode" "SI")])
15962 (define_insn "rep_stosqi"
15963 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15964 (set (match_operand:SI 0 "register_operand" "=D")
15965 (plus:SI (match_operand:SI 3 "register_operand" "0")
15966 (match_operand:SI 4 "register_operand" "1")))
15967 (set (mem:BLK (match_dup 3))
15969 (use (match_operand:QI 2 "register_operand" "a"))
15970 (use (match_dup 4))
15973 "{rep\;stosb|rep stosb}"
15974 [(set_attr "type" "str")
15975 (set_attr "prefix_rep" "1")
15976 (set_attr "memory" "store")
15977 (set_attr "mode" "QI")])
15979 (define_insn "rep_stosqi_rex64"
15980 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15981 (set (match_operand:DI 0 "register_operand" "=D")
15982 (plus:DI (match_operand:DI 3 "register_operand" "0")
15983 (match_operand:DI 4 "register_operand" "1")))
15984 (set (mem:BLK (match_dup 3))
15986 (use (match_operand:QI 2 "register_operand" "a"))
15987 (use (match_dup 4))
15990 "{rep\;stosb|rep stosb}"
15991 [(set_attr "type" "str")
15992 (set_attr "prefix_rep" "1")
15993 (set_attr "memory" "store")
15994 (set_attr "mode" "QI")])
15996 (define_expand "cmpstrsi"
15997 [(set (match_operand:SI 0 "register_operand" "")
15998 (compare:SI (match_operand:BLK 1 "general_operand" "")
15999 (match_operand:BLK 2 "general_operand" "")))
16000 (use (match_operand 3 "general_operand" ""))
16001 (use (match_operand 4 "immediate_operand" ""))]
16004 rtx addr1, addr2, out, outlow, count, countreg, align;
16007 if (GET_CODE (out) != REG)
16008 out = gen_reg_rtx (SImode);
16010 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
16011 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
16013 count = operands[3];
16014 countreg = ix86_zero_extend_to_Pmode (count);
16016 /* %%% Iff we are testing strict equality, we can use known alignment
16017 to good advantage. This may be possible with combine, particularly
16018 once cc0 is dead. */
16019 align = operands[4];
16021 emit_insn (gen_cld ());
16022 if (GET_CODE (count) == CONST_INT)
16024 if (INTVAL (count) == 0)
16026 emit_move_insn (operands[0], const0_rtx);
16030 emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align,
16031 addr1, addr2, countreg));
16033 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
16034 addr1, addr2, countreg));
16040 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
16041 emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align,
16042 addr1, addr2, countreg));
16046 emit_insn (gen_cmpsi_1 (countreg, countreg));
16047 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
16048 addr1, addr2, countreg));
16052 outlow = gen_lowpart (QImode, out);
16053 emit_insn (gen_cmpintqi (outlow));
16054 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
16056 if (operands[0] != out)
16057 emit_move_insn (operands[0], out);
16062 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
16064 (define_expand "cmpintqi"
16065 [(set (match_dup 1)
16066 (gtu:QI (reg:CC 17) (const_int 0)))
16068 (ltu:QI (reg:CC 17) (const_int 0)))
16069 (parallel [(set (match_operand:QI 0 "register_operand" "")
16070 (minus:QI (match_dup 1)
16072 (clobber (reg:CC 17))])]
16074 "operands[1] = gen_reg_rtx (QImode);
16075 operands[2] = gen_reg_rtx (QImode);")
16077 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
16078 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
16080 (define_insn "cmpstrqi_nz_1"
16082 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
16083 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
16084 (use (match_operand:SI 6 "register_operand" "2"))
16085 (use (match_operand:SI 3 "immediate_operand" "i"))
16087 (clobber (match_operand:SI 0 "register_operand" "=S"))
16088 (clobber (match_operand:SI 1 "register_operand" "=D"))
16089 (clobber (match_operand:SI 2 "register_operand" "=c"))]
16092 [(set_attr "type" "str")
16093 (set_attr "mode" "QI")
16094 (set_attr "prefix_rep" "1")])
16096 (define_insn "cmpstrqi_nz_rex_1"
16098 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
16099 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
16100 (use (match_operand:DI 6 "register_operand" "2"))
16101 (use (match_operand:SI 3 "immediate_operand" "i"))
16103 (clobber (match_operand:DI 0 "register_operand" "=S"))
16104 (clobber (match_operand:DI 1 "register_operand" "=D"))
16105 (clobber (match_operand:DI 2 "register_operand" "=c"))]
16108 [(set_attr "type" "str")
16109 (set_attr "mode" "QI")
16110 (set_attr "prefix_rep" "1")])
16112 ;; The same, but the count is not known to not be zero.
16114 (define_insn "cmpstrqi_1"
16116 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
16118 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
16119 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
16121 (use (match_operand:SI 3 "immediate_operand" "i"))
16124 (clobber (match_operand:SI 0 "register_operand" "=S"))
16125 (clobber (match_operand:SI 1 "register_operand" "=D"))
16126 (clobber (match_operand:SI 2 "register_operand" "=c"))]
16129 [(set_attr "type" "str")
16130 (set_attr "mode" "QI")
16131 (set_attr "prefix_rep" "1")])
16133 (define_insn "cmpstrqi_rex_1"
16135 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
16137 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
16138 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
16140 (use (match_operand:SI 3 "immediate_operand" "i"))
16143 (clobber (match_operand:DI 0 "register_operand" "=S"))
16144 (clobber (match_operand:DI 1 "register_operand" "=D"))
16145 (clobber (match_operand:DI 2 "register_operand" "=c"))]
16148 [(set_attr "type" "str")
16149 (set_attr "mode" "QI")
16150 (set_attr "prefix_rep" "1")])
16152 (define_expand "strlensi"
16153 [(set (match_operand:SI 0 "register_operand" "")
16154 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
16155 (match_operand:QI 2 "immediate_operand" "")
16156 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
16159 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
16165 (define_expand "strlendi"
16166 [(set (match_operand:DI 0 "register_operand" "")
16167 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
16168 (match_operand:QI 2 "immediate_operand" "")
16169 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
16172 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
16178 (define_insn "strlenqi_1"
16179 [(set (match_operand:SI 0 "register_operand" "=&c")
16180 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
16181 (match_operand:QI 2 "register_operand" "a")
16182 (match_operand:SI 3 "immediate_operand" "i")
16183 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
16185 (clobber (match_operand:SI 1 "register_operand" "=D"))
16186 (clobber (reg:CC 17))]
16189 [(set_attr "type" "str")
16190 (set_attr "mode" "QI")
16191 (set_attr "prefix_rep" "1")])
16193 (define_insn "strlenqi_rex_1"
16194 [(set (match_operand:DI 0 "register_operand" "=&c")
16195 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
16196 (match_operand:QI 2 "register_operand" "a")
16197 (match_operand:DI 3 "immediate_operand" "i")
16198 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
16200 (clobber (match_operand:DI 1 "register_operand" "=D"))
16201 (clobber (reg:CC 17))]
16204 [(set_attr "type" "str")
16205 (set_attr "mode" "QI")
16206 (set_attr "prefix_rep" "1")])
16208 ;; Peephole optimizations to clean up after cmpstr*. This should be
16209 ;; handled in combine, but it is not currently up to the task.
16210 ;; When used for their truth value, the cmpstr* expanders generate
16219 ;; The intermediate three instructions are unnecessary.
16221 ;; This one handles cmpstr*_nz_1...
16225 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16226 (mem:BLK (match_operand 5 "register_operand" ""))))
16227 (use (match_operand 6 "register_operand" ""))
16228 (use (match_operand:SI 3 "immediate_operand" ""))
16230 (clobber (match_operand 0 "register_operand" ""))
16231 (clobber (match_operand 1 "register_operand" ""))
16232 (clobber (match_operand 2 "register_operand" ""))])
16233 (set (match_operand:QI 7 "register_operand" "")
16234 (gtu:QI (reg:CC 17) (const_int 0)))
16235 (set (match_operand:QI 8 "register_operand" "")
16236 (ltu:QI (reg:CC 17) (const_int 0)))
16238 (compare (match_dup 7) (match_dup 8)))
16240 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16243 (compare:CC (mem:BLK (match_dup 4))
16244 (mem:BLK (match_dup 5))))
16245 (use (match_dup 6))
16246 (use (match_dup 3))
16248 (clobber (match_dup 0))
16249 (clobber (match_dup 1))
16250 (clobber (match_dup 2))])]
16253 ;; ...and this one handles cmpstr*_1.
16257 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
16259 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16260 (mem:BLK (match_operand 5 "register_operand" "")))
16262 (use (match_operand:SI 3 "immediate_operand" ""))
16265 (clobber (match_operand 0 "register_operand" ""))
16266 (clobber (match_operand 1 "register_operand" ""))
16267 (clobber (match_operand 2 "register_operand" ""))])
16268 (set (match_operand:QI 7 "register_operand" "")
16269 (gtu:QI (reg:CC 17) (const_int 0)))
16270 (set (match_operand:QI 8 "register_operand" "")
16271 (ltu:QI (reg:CC 17) (const_int 0)))
16273 (compare (match_dup 7) (match_dup 8)))
16275 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16278 (if_then_else:CC (ne (match_dup 6)
16280 (compare:CC (mem:BLK (match_dup 4))
16281 (mem:BLK (match_dup 5)))
16283 (use (match_dup 3))
16286 (clobber (match_dup 0))
16287 (clobber (match_dup 1))
16288 (clobber (match_dup 2))])]
16293 ;; Conditional move instructions.
16295 (define_expand "movdicc"
16296 [(set (match_operand:DI 0 "register_operand" "")
16297 (if_then_else:DI (match_operand 1 "comparison_operator" "")
16298 (match_operand:DI 2 "general_operand" "")
16299 (match_operand:DI 3 "general_operand" "")))]
16301 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16303 (define_insn "x86_movdicc_0_m1_rex64"
16304 [(set (match_operand:DI 0 "register_operand" "=r")
16305 (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
16308 (clobber (reg:CC 17))]
16311 ; Since we don't have the proper number of operands for an alu insn,
16312 ; fill in all the blanks.
16313 [(set_attr "type" "alu")
16314 (set_attr "pent_pair" "pu")
16315 (set_attr "memory" "none")
16316 (set_attr "imm_disp" "false")
16317 (set_attr "mode" "DI")
16318 (set_attr "length_immediate" "0")])
16320 (define_insn "movdicc_c_rex64"
16321 [(set (match_operand:DI 0 "register_operand" "=r,r")
16322 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
16323 [(reg 17) (const_int 0)])
16324 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
16325 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
16326 "TARGET_64BIT && TARGET_CMOVE
16327 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16329 cmov%O2%C1\t{%2, %0|%0, %2}
16330 cmov%O2%c1\t{%3, %0|%0, %3}"
16331 [(set_attr "type" "icmov")
16332 (set_attr "mode" "DI")])
16334 (define_expand "movsicc"
16335 [(set (match_operand:SI 0 "register_operand" "")
16336 (if_then_else:SI (match_operand 1 "comparison_operator" "")
16337 (match_operand:SI 2 "general_operand" "")
16338 (match_operand:SI 3 "general_operand" "")))]
16340 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16342 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
16343 ;; the register first winds up with `sbbl $0,reg', which is also weird.
16344 ;; So just document what we're doing explicitly.
16346 (define_insn "x86_movsicc_0_m1"
16347 [(set (match_operand:SI 0 "register_operand" "=r")
16348 (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
16351 (clobber (reg:CC 17))]
16354 ; Since we don't have the proper number of operands for an alu insn,
16355 ; fill in all the blanks.
16356 [(set_attr "type" "alu")
16357 (set_attr "pent_pair" "pu")
16358 (set_attr "memory" "none")
16359 (set_attr "imm_disp" "false")
16360 (set_attr "mode" "SI")
16361 (set_attr "length_immediate" "0")])
16363 (define_insn "*movsicc_noc"
16364 [(set (match_operand:SI 0 "register_operand" "=r,r")
16365 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
16366 [(reg 17) (const_int 0)])
16367 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
16368 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
16370 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16372 cmov%O2%C1\t{%2, %0|%0, %2}
16373 cmov%O2%c1\t{%3, %0|%0, %3}"
16374 [(set_attr "type" "icmov")
16375 (set_attr "mode" "SI")])
16377 (define_expand "movhicc"
16378 [(set (match_operand:HI 0 "register_operand" "")
16379 (if_then_else:HI (match_operand 1 "comparison_operator" "")
16380 (match_operand:HI 2 "general_operand" "")
16381 (match_operand:HI 3 "general_operand" "")))]
16382 "TARGET_HIMODE_MATH"
16383 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16385 (define_insn "*movhicc_noc"
16386 [(set (match_operand:HI 0 "register_operand" "=r,r")
16387 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
16388 [(reg 17) (const_int 0)])
16389 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
16390 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
16392 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16394 cmov%O2%C1\t{%2, %0|%0, %2}
16395 cmov%O2%c1\t{%3, %0|%0, %3}"
16396 [(set_attr "type" "icmov")
16397 (set_attr "mode" "HI")])
16399 (define_expand "movqicc"
16400 [(set (match_operand:QI 0 "register_operand" "")
16401 (if_then_else:QI (match_operand 1 "comparison_operator" "")
16402 (match_operand:QI 2 "general_operand" "")
16403 (match_operand:QI 3 "general_operand" "")))]
16404 "TARGET_QIMODE_MATH"
16405 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16407 (define_insn_and_split "*movqicc_noc"
16408 [(set (match_operand:QI 0 "register_operand" "=r,r")
16409 (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
16410 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
16411 (match_operand:QI 2 "register_operand" "r,0")
16412 (match_operand:QI 3 "register_operand" "0,r")))]
16413 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
16415 "&& reload_completed"
16416 [(set (match_dup 0)
16417 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16420 "operands[0] = gen_lowpart (SImode, operands[0]);
16421 operands[2] = gen_lowpart (SImode, operands[2]);
16422 operands[3] = gen_lowpart (SImode, operands[3]);"
16423 [(set_attr "type" "icmov")
16424 (set_attr "mode" "SI")])
16426 (define_expand "movsfcc"
16427 [(set (match_operand:SF 0 "register_operand" "")
16428 (if_then_else:SF (match_operand 1 "comparison_operator" "")
16429 (match_operand:SF 2 "register_operand" "")
16430 (match_operand:SF 3 "register_operand" "")))]
16432 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16434 (define_insn "*movsfcc_1"
16435 [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
16436 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16437 [(reg 17) (const_int 0)])
16438 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
16439 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
16441 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16443 fcmov%F1\t{%2, %0|%0, %2}
16444 fcmov%f1\t{%3, %0|%0, %3}
16445 cmov%O2%C1\t{%2, %0|%0, %2}
16446 cmov%O2%c1\t{%3, %0|%0, %3}"
16447 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16448 (set_attr "mode" "SF,SF,SI,SI")])
16450 (define_expand "movdfcc"
16451 [(set (match_operand:DF 0 "register_operand" "")
16452 (if_then_else:DF (match_operand 1 "comparison_operator" "")
16453 (match_operand:DF 2 "register_operand" "")
16454 (match_operand:DF 3 "register_operand" "")))]
16456 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16458 (define_insn "*movdfcc_1"
16459 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
16460 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16461 [(reg 17) (const_int 0)])
16462 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
16463 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
16464 "!TARGET_64BIT && TARGET_CMOVE
16465 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16467 fcmov%F1\t{%2, %0|%0, %2}
16468 fcmov%f1\t{%3, %0|%0, %3}
16471 [(set_attr "type" "fcmov,fcmov,multi,multi")
16472 (set_attr "mode" "DF")])
16474 (define_insn "*movdfcc_1_rex64"
16475 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
16476 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16477 [(reg 17) (const_int 0)])
16478 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
16479 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
16480 "TARGET_64BIT && TARGET_CMOVE
16481 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16483 fcmov%F1\t{%2, %0|%0, %2}
16484 fcmov%f1\t{%3, %0|%0, %3}
16485 cmov%O2%C1\t{%2, %0|%0, %2}
16486 cmov%O2%c1\t{%3, %0|%0, %3}"
16487 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16488 (set_attr "mode" "DF")])
16491 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
16492 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16493 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
16494 (match_operand:DF 2 "nonimmediate_operand" "")
16495 (match_operand:DF 3 "nonimmediate_operand" "")))]
16496 "!TARGET_64BIT && reload_completed"
16497 [(set (match_dup 2)
16498 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16502 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16505 "split_di (operands+2, 1, operands+5, operands+6);
16506 split_di (operands+3, 1, operands+7, operands+8);
16507 split_di (operands, 1, operands+2, operands+3);")
16509 (define_expand "movxfcc"
16510 [(set (match_operand:XF 0 "register_operand" "")
16511 (if_then_else:XF (match_operand 1 "comparison_operator" "")
16512 (match_operand:XF 2 "register_operand" "")
16513 (match_operand:XF 3 "register_operand" "")))]
16514 "!TARGET_64BIT && TARGET_CMOVE"
16515 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16517 (define_expand "movtfcc"
16518 [(set (match_operand:TF 0 "register_operand" "")
16519 (if_then_else:TF (match_operand 1 "comparison_operator" "")
16520 (match_operand:TF 2 "register_operand" "")
16521 (match_operand:TF 3 "register_operand" "")))]
16523 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16525 (define_insn "*movxfcc_1"
16526 [(set (match_operand:XF 0 "register_operand" "=f,f")
16527 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
16528 [(reg 17) (const_int 0)])
16529 (match_operand:XF 2 "register_operand" "f,0")
16530 (match_operand:XF 3 "register_operand" "0,f")))]
16531 "!TARGET_64BIT && TARGET_CMOVE"
16533 fcmov%F1\t{%2, %0|%0, %2}
16534 fcmov%f1\t{%3, %0|%0, %3}"
16535 [(set_attr "type" "fcmov")
16536 (set_attr "mode" "XF")])
16538 (define_insn "*movtfcc_1"
16539 [(set (match_operand:TF 0 "register_operand" "=f,f")
16540 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
16541 [(reg 17) (const_int 0)])
16542 (match_operand:TF 2 "register_operand" "f,0")
16543 (match_operand:TF 3 "register_operand" "0,f")))]
16546 fcmov%F1\t{%2, %0|%0, %2}
16547 fcmov%f1\t{%3, %0|%0, %3}"
16548 [(set_attr "type" "fcmov")
16549 (set_attr "mode" "XF")])
16551 (define_expand "minsf3"
16553 (set (match_operand:SF 0 "register_operand" "")
16554 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16555 (match_operand:SF 2 "nonimmediate_operand" ""))
16558 (clobber (reg:CC 17))])]
16562 (define_insn "*minsf"
16563 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
16564 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
16565 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
16568 (clobber (reg:CC 17))]
16569 "TARGET_SSE && TARGET_IEEE_FP"
16572 (define_insn "*minsf_nonieee"
16573 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16574 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16575 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16578 (clobber (reg:CC 17))]
16579 "TARGET_SSE && !TARGET_IEEE_FP
16580 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16584 [(set (match_operand:SF 0 "register_operand" "")
16585 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16586 (match_operand:SF 2 "nonimmediate_operand" ""))
16587 (match_operand:SF 3 "register_operand" "")
16588 (match_operand:SF 4 "nonimmediate_operand" "")))
16589 (clobber (reg:CC 17))]
16590 "SSE_REG_P (operands[0]) && reload_completed
16591 && ((operands_match_p (operands[1], operands[3])
16592 && operands_match_p (operands[2], operands[4]))
16593 || (operands_match_p (operands[1], operands[4])
16594 && operands_match_p (operands[2], operands[3])))"
16595 [(set (match_dup 0)
16596 (if_then_else:SF (lt (match_dup 1)
16601 ;; Conditional addition patterns
16602 (define_expand "addqicc"
16603 [(match_operand:QI 0 "register_operand" "")
16604 (match_operand 1 "comparison_operator" "")
16605 (match_operand:QI 2 "register_operand" "")
16606 (match_operand:QI 3 "const_int_operand" "")]
16608 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16610 (define_expand "addhicc"
16611 [(match_operand:HI 0 "register_operand" "")
16612 (match_operand 1 "comparison_operator" "")
16613 (match_operand:HI 2 "register_operand" "")
16614 (match_operand:HI 3 "const_int_operand" "")]
16616 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16618 (define_expand "addsicc"
16619 [(match_operand:SI 0 "register_operand" "")
16620 (match_operand 1 "comparison_operator" "")
16621 (match_operand:SI 2 "register_operand" "")
16622 (match_operand:SI 3 "const_int_operand" "")]
16624 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16626 (define_expand "adddicc"
16627 [(match_operand:DI 0 "register_operand" "")
16628 (match_operand 1 "comparison_operator" "")
16629 (match_operand:DI 2 "register_operand" "")
16630 (match_operand:DI 3 "const_int_operand" "")]
16632 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16634 ;; We can't represent the LT test directly. Do this by swapping the operands.
16637 [(set (match_operand:SF 0 "fp_register_operand" "")
16638 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16639 (match_operand:SF 2 "register_operand" ""))
16640 (match_operand:SF 3 "register_operand" "")
16641 (match_operand:SF 4 "register_operand" "")))
16642 (clobber (reg:CC 17))]
16644 && ((operands_match_p (operands[1], operands[3])
16645 && operands_match_p (operands[2], operands[4]))
16646 || (operands_match_p (operands[1], operands[4])
16647 && operands_match_p (operands[2], operands[3])))"
16648 [(set (reg:CCFP 17)
16649 (compare:CCFP (match_dup 2)
16652 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
16656 (define_insn "*minsf_sse"
16657 [(set (match_operand:SF 0 "register_operand" "=x")
16658 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
16659 (match_operand:SF 2 "nonimmediate_operand" "xm"))
16662 "TARGET_SSE && reload_completed"
16663 "minss\t{%2, %0|%0, %2}"
16664 [(set_attr "type" "sse")
16665 (set_attr "mode" "SF")])
16667 (define_expand "mindf3"
16669 (set (match_operand:DF 0 "register_operand" "")
16670 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16671 (match_operand:DF 2 "nonimmediate_operand" ""))
16674 (clobber (reg:CC 17))])]
16675 "TARGET_SSE2 && TARGET_SSE_MATH"
16678 (define_insn "*mindf"
16679 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
16680 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
16681 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
16684 (clobber (reg:CC 17))]
16685 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
16688 (define_insn "*mindf_nonieee"
16689 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16690 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16691 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16694 (clobber (reg:CC 17))]
16695 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
16696 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16700 [(set (match_operand:DF 0 "register_operand" "")
16701 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16702 (match_operand:DF 2 "nonimmediate_operand" ""))
16703 (match_operand:DF 3 "register_operand" "")
16704 (match_operand:DF 4 "nonimmediate_operand" "")))
16705 (clobber (reg:CC 17))]
16706 "SSE_REG_P (operands[0]) && reload_completed
16707 && ((operands_match_p (operands[1], operands[3])
16708 && operands_match_p (operands[2], operands[4]))
16709 || (operands_match_p (operands[1], operands[4])
16710 && operands_match_p (operands[2], operands[3])))"
16711 [(set (match_dup 0)
16712 (if_then_else:DF (lt (match_dup 1)
16717 ;; We can't represent the LT test directly. Do this by swapping the operands.
16719 [(set (match_operand:DF 0 "fp_register_operand" "")
16720 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16721 (match_operand:DF 2 "register_operand" ""))
16722 (match_operand:DF 3 "register_operand" "")
16723 (match_operand:DF 4 "register_operand" "")))
16724 (clobber (reg:CC 17))]
16726 && ((operands_match_p (operands[1], operands[3])
16727 && operands_match_p (operands[2], operands[4]))
16728 || (operands_match_p (operands[1], operands[4])
16729 && operands_match_p (operands[2], operands[3])))"
16730 [(set (reg:CCFP 17)
16731 (compare:CCFP (match_dup 2)
16734 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
16738 (define_insn "*mindf_sse"
16739 [(set (match_operand:DF 0 "register_operand" "=Y")
16740 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
16741 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
16744 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
16745 "minsd\t{%2, %0|%0, %2}"
16746 [(set_attr "type" "sse")
16747 (set_attr "mode" "DF")])
16749 (define_expand "maxsf3"
16751 (set (match_operand:SF 0 "register_operand" "")
16752 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16753 (match_operand:SF 2 "nonimmediate_operand" ""))
16756 (clobber (reg:CC 17))])]
16760 (define_insn "*maxsf"
16761 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
16762 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
16763 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
16766 (clobber (reg:CC 17))]
16767 "TARGET_SSE && TARGET_IEEE_FP"
16770 (define_insn "*maxsf_nonieee"
16771 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16772 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16773 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16776 (clobber (reg:CC 17))]
16777 "TARGET_SSE && !TARGET_IEEE_FP
16778 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16782 [(set (match_operand:SF 0 "register_operand" "")
16783 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16784 (match_operand:SF 2 "nonimmediate_operand" ""))
16785 (match_operand:SF 3 "register_operand" "")
16786 (match_operand:SF 4 "nonimmediate_operand" "")))
16787 (clobber (reg:CC 17))]
16788 "SSE_REG_P (operands[0]) && reload_completed
16789 && ((operands_match_p (operands[1], operands[3])
16790 && operands_match_p (operands[2], operands[4]))
16791 || (operands_match_p (operands[1], operands[4])
16792 && operands_match_p (operands[2], operands[3])))"
16793 [(set (match_dup 0)
16794 (if_then_else:SF (gt (match_dup 1)
16800 [(set (match_operand:SF 0 "fp_register_operand" "")
16801 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16802 (match_operand:SF 2 "register_operand" ""))
16803 (match_operand:SF 3 "register_operand" "")
16804 (match_operand:SF 4 "register_operand" "")))
16805 (clobber (reg:CC 17))]
16807 && ((operands_match_p (operands[1], operands[3])
16808 && operands_match_p (operands[2], operands[4]))
16809 || (operands_match_p (operands[1], operands[4])
16810 && operands_match_p (operands[2], operands[3])))"
16811 [(set (reg:CCFP 17)
16812 (compare:CCFP (match_dup 1)
16815 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
16819 (define_insn "*maxsf_sse"
16820 [(set (match_operand:SF 0 "register_operand" "=x")
16821 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
16822 (match_operand:SF 2 "nonimmediate_operand" "xm"))
16825 "TARGET_SSE && reload_completed"
16826 "maxss\t{%2, %0|%0, %2}"
16827 [(set_attr "type" "sse")
16828 (set_attr "mode" "SF")])
16830 (define_expand "maxdf3"
16832 (set (match_operand:DF 0 "register_operand" "")
16833 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16834 (match_operand:DF 2 "nonimmediate_operand" ""))
16837 (clobber (reg:CC 17))])]
16838 "TARGET_SSE2 && TARGET_SSE_MATH"
16841 (define_insn "*maxdf"
16842 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
16843 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
16844 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
16847 (clobber (reg:CC 17))]
16848 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
16851 (define_insn "*maxdf_nonieee"
16852 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16853 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16854 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16857 (clobber (reg:CC 17))]
16858 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
16859 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16863 [(set (match_operand:DF 0 "register_operand" "")
16864 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16865 (match_operand:DF 2 "nonimmediate_operand" ""))
16866 (match_operand:DF 3 "register_operand" "")
16867 (match_operand:DF 4 "nonimmediate_operand" "")))
16868 (clobber (reg:CC 17))]
16869 "SSE_REG_P (operands[0]) && reload_completed
16870 && ((operands_match_p (operands[1], operands[3])
16871 && operands_match_p (operands[2], operands[4]))
16872 || (operands_match_p (operands[1], operands[4])
16873 && operands_match_p (operands[2], operands[3])))"
16874 [(set (match_dup 0)
16875 (if_then_else:DF (gt (match_dup 1)
16881 [(set (match_operand:DF 0 "fp_register_operand" "")
16882 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16883 (match_operand:DF 2 "register_operand" ""))
16884 (match_operand:DF 3 "register_operand" "")
16885 (match_operand:DF 4 "register_operand" "")))
16886 (clobber (reg:CC 17))]
16888 && ((operands_match_p (operands[1], operands[3])
16889 && operands_match_p (operands[2], operands[4]))
16890 || (operands_match_p (operands[1], operands[4])
16891 && operands_match_p (operands[2], operands[3])))"
16892 [(set (reg:CCFP 17)
16893 (compare:CCFP (match_dup 1)
16896 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
16900 (define_insn "*maxdf_sse"
16901 [(set (match_operand:DF 0 "register_operand" "=Y")
16902 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
16903 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
16906 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
16907 "maxsd\t{%2, %0|%0, %2}"
16908 [(set_attr "type" "sse")
16909 (set_attr "mode" "DF")])
16911 ;; Misc patterns (?)
16913 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
16914 ;; Otherwise there will be nothing to keep
16916 ;; [(set (reg ebp) (reg esp))]
16917 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
16918 ;; (clobber (eflags)]
16919 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
16921 ;; in proper program order.
16922 (define_expand "pro_epilogue_adjust_stack"
16923 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
16924 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16925 (match_operand:SI 2 "immediate_operand" "i,i")))
16926 (clobber (reg:CC 17))
16927 (clobber (mem:BLK (scratch)))])]
16932 emit_insn (gen_pro_epilogue_adjust_stack_rex64
16933 (operands[0], operands[1], operands[2]));
16938 (define_insn "*pro_epilogue_adjust_stack_1"
16939 [(set (match_operand:SI 0 "register_operand" "=r,r")
16940 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16941 (match_operand:SI 2 "immediate_operand" "i,i")))
16942 (clobber (reg:CC 17))
16943 (clobber (mem:BLK (scratch)))]
16946 switch (get_attr_type (insn))
16949 return "mov{l}\t{%1, %0|%0, %1}";
16952 if (GET_CODE (operands[2]) == CONST_INT
16953 && (INTVAL (operands[2]) == 128
16954 || (INTVAL (operands[2]) < 0
16955 && INTVAL (operands[2]) != -128)))
16957 operands[2] = GEN_INT (-INTVAL (operands[2]));
16958 return "sub{l}\t{%2, %0|%0, %2}";
16960 return "add{l}\t{%2, %0|%0, %2}";
16963 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16964 return "lea{l}\t{%a2, %0|%0, %a2}";
16970 [(set (attr "type")
16971 (cond [(eq_attr "alternative" "0")
16972 (const_string "alu")
16973 (match_operand:SI 2 "const0_operand" "")
16974 (const_string "imov")
16976 (const_string "lea")))
16977 (set_attr "mode" "SI")])
16979 (define_insn "pro_epilogue_adjust_stack_rex64"
16980 [(set (match_operand:DI 0 "register_operand" "=r,r")
16981 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
16982 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
16983 (clobber (reg:CC 17))
16984 (clobber (mem:BLK (scratch)))]
16987 switch (get_attr_type (insn))
16990 return "mov{q}\t{%1, %0|%0, %1}";
16993 if (GET_CODE (operands[2]) == CONST_INT
16994 && (INTVAL (operands[2]) == 128
16995 || (INTVAL (operands[2]) < 0
16996 && INTVAL (operands[2]) != -128)))
16998 operands[2] = GEN_INT (-INTVAL (operands[2]));
16999 return "sub{q}\t{%2, %0|%0, %2}";
17001 return "add{q}\t{%2, %0|%0, %2}";
17004 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
17005 return "lea{q}\t{%a2, %0|%0, %a2}";
17011 [(set (attr "type")
17012 (cond [(eq_attr "alternative" "0")
17013 (const_string "alu")
17014 (match_operand:DI 2 "const0_operand" "")
17015 (const_string "imov")
17017 (const_string "lea")))
17018 (set_attr "mode" "DI")])
17021 ;; Placeholder for the conditional moves. This one is split either to SSE
17022 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
17023 ;; fact is that compares supported by the cmp??ss instructions are exactly
17024 ;; swapped of those supported by cmove sequence.
17025 ;; The EQ/NE comparisons also needs bit care, since they are not directly
17026 ;; supported by i387 comparisons and we do need to emit two conditional moves
17029 (define_insn "sse_movsfcc"
17030 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
17031 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17032 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
17033 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
17034 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
17035 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
17036 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
17037 (clobber (reg:CC 17))]
17039 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
17040 /* Avoid combine from being smart and converting min/max
17041 instruction patterns into conditional moves. */
17042 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
17043 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
17044 || !rtx_equal_p (operands[4], operands[2])
17045 || !rtx_equal_p (operands[5], operands[3]))
17046 && (!TARGET_IEEE_FP
17047 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
17050 (define_insn "sse_movsfcc_eq"
17051 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
17052 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
17053 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
17054 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
17055 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
17056 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
17057 (clobber (reg:CC 17))]
17059 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17062 (define_insn "sse_movdfcc"
17063 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
17064 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17065 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
17066 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
17067 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
17068 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
17069 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
17070 (clobber (reg:CC 17))]
17072 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
17073 /* Avoid combine from being smart and converting min/max
17074 instruction patterns into conditional moves. */
17075 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
17076 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
17077 || !rtx_equal_p (operands[4], operands[2])
17078 || !rtx_equal_p (operands[5], operands[3]))
17079 && (!TARGET_IEEE_FP
17080 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
17083 (define_insn "sse_movdfcc_eq"
17084 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
17085 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
17086 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
17087 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
17088 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
17089 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
17090 (clobber (reg:CC 17))]
17092 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17095 ;; For non-sse moves just expand the usual cmove sequence.
17097 [(set (match_operand 0 "register_operand" "")
17098 (if_then_else (match_operator 1 "comparison_operator"
17099 [(match_operand 4 "nonimmediate_operand" "")
17100 (match_operand 5 "register_operand" "")])
17101 (match_operand 2 "nonimmediate_operand" "")
17102 (match_operand 3 "nonimmediate_operand" "")))
17103 (clobber (match_operand 6 "" ""))
17104 (clobber (reg:CC 17))]
17105 "!SSE_REG_P (operands[0]) && reload_completed
17106 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
17109 ix86_compare_op0 = operands[5];
17110 ix86_compare_op1 = operands[4];
17111 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
17112 VOIDmode, operands[5], operands[4]);
17113 ix86_expand_fp_movcc (operands);
17117 ;; Split SSE based conditional move into sequence:
17118 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
17119 ;; and op2, op0 - zero op2 if comparison was false
17120 ;; nand op0, op3 - load op3 to op0 if comparison was false
17121 ;; or op2, op0 - get the nonzero one into the result.
17123 [(set (match_operand 0 "register_operand" "")
17124 (if_then_else (match_operator 1 "sse_comparison_operator"
17125 [(match_operand 4 "register_operand" "")
17126 (match_operand 5 "nonimmediate_operand" "")])
17127 (match_operand 2 "register_operand" "")
17128 (match_operand 3 "register_operand" "")))
17129 (clobber (match_operand 6 "" ""))
17130 (clobber (reg:CC 17))]
17131 "SSE_REG_P (operands[0]) && reload_completed"
17132 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
17133 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
17134 (subreg:TI (match_dup 4) 0)))
17135 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
17136 (subreg:TI (match_dup 3) 0)))
17137 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
17138 (subreg:TI (match_dup 7) 0)))]
17140 if (GET_MODE (operands[2]) == DFmode
17141 && TARGET_SSE_PARTIAL_REGS && !optimize_size)
17143 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17144 emit_insn (gen_sse2_unpcklpd (op, op, op));
17145 op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17146 emit_insn (gen_sse2_unpcklpd (op, op, op));
17149 /* If op2 == op3, op3 would be clobbered before it is used. */
17150 if (operands_match_p (operands[2], operands[3]))
17152 emit_move_insn (operands[0], operands[2]);
17156 PUT_MODE (operands[1], GET_MODE (operands[0]));
17157 if (operands_match_p (operands[0], operands[4]))
17158 operands[6] = operands[4], operands[7] = operands[2];
17160 operands[6] = operands[2], operands[7] = operands[4];
17163 ;; Special case of conditional move we can handle effectively.
17164 ;; Do not brother with the integer/floating point case, since these are
17165 ;; bot considerably slower, unlike in the generic case.
17166 (define_insn "*sse_movsfcc_const0_1"
17167 [(set (match_operand:SF 0 "register_operand" "=&x")
17168 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17169 [(match_operand:SF 4 "register_operand" "0")
17170 (match_operand:SF 5 "nonimmediate_operand" "xm")])
17171 (match_operand:SF 2 "register_operand" "x")
17172 (match_operand:SF 3 "const0_operand" "X")))]
17176 (define_insn "*sse_movsfcc_const0_2"
17177 [(set (match_operand:SF 0 "register_operand" "=&x")
17178 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17179 [(match_operand:SF 4 "register_operand" "0")
17180 (match_operand:SF 5 "nonimmediate_operand" "xm")])
17181 (match_operand:SF 2 "const0_operand" "X")
17182 (match_operand:SF 3 "register_operand" "x")))]
17186 (define_insn "*sse_movsfcc_const0_3"
17187 [(set (match_operand:SF 0 "register_operand" "=&x")
17188 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17189 [(match_operand:SF 4 "nonimmediate_operand" "xm")
17190 (match_operand:SF 5 "register_operand" "0")])
17191 (match_operand:SF 2 "register_operand" "x")
17192 (match_operand:SF 3 "const0_operand" "X")))]
17196 (define_insn "*sse_movsfcc_const0_4"
17197 [(set (match_operand:SF 0 "register_operand" "=&x")
17198 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17199 [(match_operand:SF 4 "nonimmediate_operand" "xm")
17200 (match_operand:SF 5 "register_operand" "0")])
17201 (match_operand:SF 2 "const0_operand" "X")
17202 (match_operand:SF 3 "register_operand" "x")))]
17206 (define_insn "*sse_movdfcc_const0_1"
17207 [(set (match_operand:DF 0 "register_operand" "=&Y")
17208 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17209 [(match_operand:DF 4 "register_operand" "0")
17210 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
17211 (match_operand:DF 2 "register_operand" "Y")
17212 (match_operand:DF 3 "const0_operand" "X")))]
17216 (define_insn "*sse_movdfcc_const0_2"
17217 [(set (match_operand:DF 0 "register_operand" "=&Y")
17218 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17219 [(match_operand:DF 4 "register_operand" "0")
17220 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
17221 (match_operand:DF 2 "const0_operand" "X")
17222 (match_operand:DF 3 "register_operand" "Y")))]
17226 (define_insn "*sse_movdfcc_const0_3"
17227 [(set (match_operand:DF 0 "register_operand" "=&Y")
17228 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17229 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17230 (match_operand:DF 5 "register_operand" "0")])
17231 (match_operand:DF 2 "register_operand" "Y")
17232 (match_operand:DF 3 "const0_operand" "X")))]
17236 (define_insn "*sse_movdfcc_const0_4"
17237 [(set (match_operand:DF 0 "register_operand" "=&Y")
17238 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17239 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17240 (match_operand:DF 5 "register_operand" "0")])
17241 (match_operand:DF 2 "const0_operand" "X")
17242 (match_operand:DF 3 "register_operand" "Y")))]
17247 [(set (match_operand 0 "register_operand" "")
17248 (if_then_else (match_operator 1 "comparison_operator"
17249 [(match_operand 4 "nonimmediate_operand" "")
17250 (match_operand 5 "nonimmediate_operand" "")])
17251 (match_operand 2 "nonmemory_operand" "")
17252 (match_operand 3 "nonmemory_operand" "")))]
17253 "SSE_REG_P (operands[0]) && reload_completed
17254 && (const0_operand (operands[2], GET_MODE (operands[0]))
17255 || const0_operand (operands[3], GET_MODE (operands[0])))"
17256 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
17257 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
17260 if (TARGET_SSE_PARTIAL_REGS && !optimize_size
17261 && GET_MODE (operands[2]) == DFmode)
17263 if (REG_P (operands[2]))
17265 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17266 emit_insn (gen_sse2_unpcklpd (op, op, op));
17268 if (REG_P (operands[3]))
17270 rtx op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17271 emit_insn (gen_sse2_unpcklpd (op, op, op));
17274 PUT_MODE (operands[1], GET_MODE (operands[0]));
17275 if (!sse_comparison_operator (operands[1], VOIDmode)
17276 || !rtx_equal_p (operands[0], operands[4]))
17278 rtx tmp = operands[5];
17279 operands[5] = operands[4];
17281 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
17283 if (!rtx_equal_p (operands[0], operands[4]))
17285 if (const0_operand (operands[2], GET_MODE (operands[0])))
17287 operands[7] = operands[3];
17288 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
17293 operands[7] = operands[2];
17294 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
17296 operands[7] = simplify_gen_subreg (TImode, operands[7],
17297 GET_MODE (operands[7]), 0);
17300 (define_expand "allocate_stack_worker"
17301 [(match_operand:SI 0 "register_operand" "")]
17302 "TARGET_STACK_PROBE"
17305 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
17307 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
17311 (define_insn "allocate_stack_worker_1"
17312 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
17313 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
17314 (clobber (match_dup 0))
17315 (clobber (reg:CC 17))]
17316 "!TARGET_64BIT && TARGET_STACK_PROBE"
17318 [(set_attr "type" "multi")
17319 (set_attr "length" "5")])
17321 (define_insn "allocate_stack_worker_rex64"
17322 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
17323 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
17324 (clobber (match_dup 0))
17325 (clobber (reg:CC 17))]
17326 "TARGET_64BIT && TARGET_STACK_PROBE"
17328 [(set_attr "type" "multi")
17329 (set_attr "length" "5")])
17331 (define_expand "allocate_stack"
17332 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
17333 (minus:SI (reg:SI 7)
17334 (match_operand:SI 1 "general_operand" "")))
17335 (clobber (reg:CC 17))])
17336 (parallel [(set (reg:SI 7)
17337 (minus:SI (reg:SI 7) (match_dup 1)))
17338 (clobber (reg:CC 17))])]
17339 "TARGET_STACK_PROBE"
17341 #ifdef CHECK_STACK_LIMIT
17342 if (GET_CODE (operands[1]) == CONST_INT
17343 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
17344 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
17348 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
17351 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
17355 (define_expand "builtin_setjmp_receiver"
17356 [(label_ref (match_operand 0 "" ""))]
17357 "!TARGET_64BIT && flag_pic"
17359 emit_insn (gen_set_got (pic_offset_table_rtx));
17363 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
17366 [(set (match_operand 0 "register_operand" "")
17367 (match_operator 3 "promotable_binary_operator"
17368 [(match_operand 1 "register_operand" "")
17369 (match_operand 2 "aligned_operand" "")]))
17370 (clobber (reg:CC 17))]
17371 "! TARGET_PARTIAL_REG_STALL && reload_completed
17372 && ((GET_MODE (operands[0]) == HImode
17373 && ((!optimize_size && !TARGET_FAST_PREFIX)
17374 || GET_CODE (operands[2]) != CONST_INT
17375 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
17376 || (GET_MODE (operands[0]) == QImode
17377 && (TARGET_PROMOTE_QImode || optimize_size)))"
17378 [(parallel [(set (match_dup 0)
17379 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
17380 (clobber (reg:CC 17))])]
17381 "operands[0] = gen_lowpart (SImode, operands[0]);
17382 operands[1] = gen_lowpart (SImode, operands[1]);
17383 if (GET_CODE (operands[3]) != ASHIFT)
17384 operands[2] = gen_lowpart (SImode, operands[2]);
17385 PUT_MODE (operands[3], SImode);")
17389 (compare (and (match_operand 1 "aligned_operand" "")
17390 (match_operand 2 "const_int_operand" ""))
17392 (set (match_operand 0 "register_operand" "")
17393 (and (match_dup 1) (match_dup 2)))]
17394 "! TARGET_PARTIAL_REG_STALL && reload_completed
17395 && ix86_match_ccmode (insn, CCNOmode)
17396 && (GET_MODE (operands[0]) == HImode
17397 || (GET_MODE (operands[0]) == QImode
17398 /* Ensure that the operand will remain sign extended immediate. */
17399 && INTVAL (operands[2]) >= 0
17400 && (TARGET_PROMOTE_QImode || optimize_size)))"
17401 [(parallel [(set (reg:CCNO 17)
17402 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
17405 (and:SI (match_dup 1) (match_dup 2)))])]
17407 = gen_int_mode (INTVAL (operands[2])
17408 & GET_MODE_MASK (GET_MODE (operands[0])),
17410 operands[0] = gen_lowpart (SImode, operands[0]);
17411 operands[1] = gen_lowpart (SImode, operands[1]);")
17413 ; Don't promote the QImode tests, as i386 don't have encoding of
17414 ; the test instruction with 32bit sign extended immediate and thus
17418 (compare (and (match_operand:HI 0 "aligned_operand" "")
17419 (match_operand:HI 1 "const_int_operand" ""))
17421 "! TARGET_PARTIAL_REG_STALL && reload_completed
17422 && ix86_match_ccmode (insn, CCNOmode)
17423 && GET_MODE (operands[0]) == HImode"
17424 [(set (reg:CCNO 17)
17425 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
17428 = gen_int_mode (INTVAL (operands[1])
17429 & GET_MODE_MASK (GET_MODE (operands[0])),
17431 operands[0] = gen_lowpart (SImode, operands[0]);")
17434 [(set (match_operand 0 "register_operand" "")
17435 (neg (match_operand 1 "register_operand" "")))
17436 (clobber (reg:CC 17))]
17437 "! TARGET_PARTIAL_REG_STALL && reload_completed
17438 && (GET_MODE (operands[0]) == HImode
17439 || (GET_MODE (operands[0]) == QImode
17440 && (TARGET_PROMOTE_QImode || optimize_size)))"
17441 [(parallel [(set (match_dup 0)
17442 (neg:SI (match_dup 1)))
17443 (clobber (reg:CC 17))])]
17444 "operands[0] = gen_lowpart (SImode, operands[0]);
17445 operands[1] = gen_lowpart (SImode, operands[1]);")
17448 [(set (match_operand 0 "register_operand" "")
17449 (not (match_operand 1 "register_operand" "")))]
17450 "! TARGET_PARTIAL_REG_STALL && reload_completed
17451 && (GET_MODE (operands[0]) == HImode
17452 || (GET_MODE (operands[0]) == QImode
17453 && (TARGET_PROMOTE_QImode || optimize_size)))"
17454 [(set (match_dup 0)
17455 (not:SI (match_dup 1)))]
17456 "operands[0] = gen_lowpart (SImode, operands[0]);
17457 operands[1] = gen_lowpart (SImode, operands[1]);")
17460 [(set (match_operand 0 "register_operand" "")
17461 (if_then_else (match_operator 1 "comparison_operator"
17462 [(reg 17) (const_int 0)])
17463 (match_operand 2 "register_operand" "")
17464 (match_operand 3 "register_operand" "")))]
17465 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
17466 && (GET_MODE (operands[0]) == HImode
17467 || (GET_MODE (operands[0]) == QImode
17468 && (TARGET_PROMOTE_QImode || optimize_size)))"
17469 [(set (match_dup 0)
17470 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
17471 "operands[0] = gen_lowpart (SImode, operands[0]);
17472 operands[2] = gen_lowpart (SImode, operands[2]);
17473 operands[3] = gen_lowpart (SImode, operands[3]);")
17476 ;; RTL Peephole optimizations, run before sched2. These primarily look to
17477 ;; transform a complex memory operation into two memory to register operations.
17479 ;; Don't push memory operands
17481 [(set (match_operand:SI 0 "push_operand" "")
17482 (match_operand:SI 1 "memory_operand" ""))
17483 (match_scratch:SI 2 "r")]
17484 "! optimize_size && ! TARGET_PUSH_MEMORY"
17485 [(set (match_dup 2) (match_dup 1))
17486 (set (match_dup 0) (match_dup 2))]
17490 [(set (match_operand:DI 0 "push_operand" "")
17491 (match_operand:DI 1 "memory_operand" ""))
17492 (match_scratch:DI 2 "r")]
17493 "! optimize_size && ! TARGET_PUSH_MEMORY"
17494 [(set (match_dup 2) (match_dup 1))
17495 (set (match_dup 0) (match_dup 2))]
17498 ;; We need to handle SFmode only, because DFmode and XFmode is split to
17501 [(set (match_operand:SF 0 "push_operand" "")
17502 (match_operand:SF 1 "memory_operand" ""))
17503 (match_scratch:SF 2 "r")]
17504 "! optimize_size && ! TARGET_PUSH_MEMORY"
17505 [(set (match_dup 2) (match_dup 1))
17506 (set (match_dup 0) (match_dup 2))]
17510 [(set (match_operand:HI 0 "push_operand" "")
17511 (match_operand:HI 1 "memory_operand" ""))
17512 (match_scratch:HI 2 "r")]
17513 "! optimize_size && ! TARGET_PUSH_MEMORY"
17514 [(set (match_dup 2) (match_dup 1))
17515 (set (match_dup 0) (match_dup 2))]
17519 [(set (match_operand:QI 0 "push_operand" "")
17520 (match_operand:QI 1 "memory_operand" ""))
17521 (match_scratch:QI 2 "q")]
17522 "! optimize_size && ! TARGET_PUSH_MEMORY"
17523 [(set (match_dup 2) (match_dup 1))
17524 (set (match_dup 0) (match_dup 2))]
17527 ;; Don't move an immediate directly to memory when the instruction
17530 [(match_scratch:SI 1 "r")
17531 (set (match_operand:SI 0 "memory_operand" "")
17534 && ! TARGET_USE_MOV0
17535 && TARGET_SPLIT_LONG_MOVES
17536 && get_attr_length (insn) >= ix86_cost->large_insn
17537 && peep2_regno_dead_p (0, FLAGS_REG)"
17538 [(parallel [(set (match_dup 1) (const_int 0))
17539 (clobber (reg:CC 17))])
17540 (set (match_dup 0) (match_dup 1))]
17544 [(match_scratch:HI 1 "r")
17545 (set (match_operand:HI 0 "memory_operand" "")
17548 && ! TARGET_USE_MOV0
17549 && TARGET_SPLIT_LONG_MOVES
17550 && get_attr_length (insn) >= ix86_cost->large_insn
17551 && peep2_regno_dead_p (0, FLAGS_REG)"
17552 [(parallel [(set (match_dup 2) (const_int 0))
17553 (clobber (reg:CC 17))])
17554 (set (match_dup 0) (match_dup 1))]
17555 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
17558 [(match_scratch:QI 1 "q")
17559 (set (match_operand:QI 0 "memory_operand" "")
17562 && ! TARGET_USE_MOV0
17563 && TARGET_SPLIT_LONG_MOVES
17564 && get_attr_length (insn) >= ix86_cost->large_insn
17565 && peep2_regno_dead_p (0, FLAGS_REG)"
17566 [(parallel [(set (match_dup 2) (const_int 0))
17567 (clobber (reg:CC 17))])
17568 (set (match_dup 0) (match_dup 1))]
17569 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
17572 [(match_scratch:SI 2 "r")
17573 (set (match_operand:SI 0 "memory_operand" "")
17574 (match_operand:SI 1 "immediate_operand" ""))]
17576 && get_attr_length (insn) >= ix86_cost->large_insn
17577 && TARGET_SPLIT_LONG_MOVES"
17578 [(set (match_dup 2) (match_dup 1))
17579 (set (match_dup 0) (match_dup 2))]
17583 [(match_scratch:HI 2 "r")
17584 (set (match_operand:HI 0 "memory_operand" "")
17585 (match_operand:HI 1 "immediate_operand" ""))]
17586 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
17587 && TARGET_SPLIT_LONG_MOVES"
17588 [(set (match_dup 2) (match_dup 1))
17589 (set (match_dup 0) (match_dup 2))]
17593 [(match_scratch:QI 2 "q")
17594 (set (match_operand:QI 0 "memory_operand" "")
17595 (match_operand:QI 1 "immediate_operand" ""))]
17596 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
17597 && TARGET_SPLIT_LONG_MOVES"
17598 [(set (match_dup 2) (match_dup 1))
17599 (set (match_dup 0) (match_dup 2))]
17602 ;; Don't compare memory with zero, load and use a test instead.
17605 (compare (match_operand:SI 0 "memory_operand" "")
17607 (match_scratch:SI 3 "r")]
17608 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
17609 [(set (match_dup 3) (match_dup 0))
17610 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
17613 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
17614 ;; Don't split NOTs with a displacement operand, because resulting XOR
17615 ;; will not be pairable anyway.
17617 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
17618 ;; represented using a modRM byte. The XOR replacement is long decoded,
17619 ;; so this split helps here as well.
17621 ;; Note: Can't do this as a regular split because we can't get proper
17622 ;; lifetime information then.
17625 [(set (match_operand:SI 0 "nonimmediate_operand" "")
17626 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
17628 && peep2_regno_dead_p (0, FLAGS_REG)
17629 && ((TARGET_PENTIUM
17630 && (GET_CODE (operands[0]) != MEM
17631 || !memory_displacement_operand (operands[0], SImode)))
17632 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
17633 [(parallel [(set (match_dup 0)
17634 (xor:SI (match_dup 1) (const_int -1)))
17635 (clobber (reg:CC 17))])]
17639 [(set (match_operand:HI 0 "nonimmediate_operand" "")
17640 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
17642 && peep2_regno_dead_p (0, FLAGS_REG)
17643 && ((TARGET_PENTIUM
17644 && (GET_CODE (operands[0]) != MEM
17645 || !memory_displacement_operand (operands[0], HImode)))
17646 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
17647 [(parallel [(set (match_dup 0)
17648 (xor:HI (match_dup 1) (const_int -1)))
17649 (clobber (reg:CC 17))])]
17653 [(set (match_operand:QI 0 "nonimmediate_operand" "")
17654 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
17656 && peep2_regno_dead_p (0, FLAGS_REG)
17657 && ((TARGET_PENTIUM
17658 && (GET_CODE (operands[0]) != MEM
17659 || !memory_displacement_operand (operands[0], QImode)))
17660 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
17661 [(parallel [(set (match_dup 0)
17662 (xor:QI (match_dup 1) (const_int -1)))
17663 (clobber (reg:CC 17))])]
17666 ;; Non pairable "test imm, reg" instructions can be translated to
17667 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
17668 ;; byte opcode instead of two, have a short form for byte operands),
17669 ;; so do it for other CPUs as well. Given that the value was dead,
17670 ;; this should not create any new dependencies. Pass on the sub-word
17671 ;; versions if we're concerned about partial register stalls.
17675 (compare (and:SI (match_operand:SI 0 "register_operand" "")
17676 (match_operand:SI 1 "immediate_operand" ""))
17678 "ix86_match_ccmode (insn, CCNOmode)
17679 && (true_regnum (operands[0]) != 0
17680 || (GET_CODE (operands[1]) == CONST_INT
17681 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
17682 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17684 [(set (reg:CCNO 17)
17685 (compare:CCNO (and:SI (match_dup 0)
17689 (and:SI (match_dup 0) (match_dup 1)))])]
17692 ;; We don't need to handle HImode case, because it will be promoted to SImode
17693 ;; on ! TARGET_PARTIAL_REG_STALL
17697 (compare (and:QI (match_operand:QI 0 "register_operand" "")
17698 (match_operand:QI 1 "immediate_operand" ""))
17700 "! TARGET_PARTIAL_REG_STALL
17701 && ix86_match_ccmode (insn, CCNOmode)
17702 && true_regnum (operands[0]) != 0
17703 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17705 [(set (reg:CCNO 17)
17706 (compare:CCNO (and:QI (match_dup 0)
17710 (and:QI (match_dup 0) (match_dup 1)))])]
17718 (match_operand 0 "ext_register_operand" "")
17721 (match_operand 1 "const_int_operand" ""))
17723 "! TARGET_PARTIAL_REG_STALL
17724 && ix86_match_ccmode (insn, CCNOmode)
17725 && true_regnum (operands[0]) != 0
17726 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17727 [(parallel [(set (reg:CCNO 17)
17736 (set (zero_extract:SI (match_dup 0)
17747 ;; Don't do logical operations with memory inputs.
17749 [(match_scratch:SI 2 "r")
17750 (parallel [(set (match_operand:SI 0 "register_operand" "")
17751 (match_operator:SI 3 "arith_or_logical_operator"
17753 (match_operand:SI 1 "memory_operand" "")]))
17754 (clobber (reg:CC 17))])]
17755 "! optimize_size && ! TARGET_READ_MODIFY"
17756 [(set (match_dup 2) (match_dup 1))
17757 (parallel [(set (match_dup 0)
17758 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
17759 (clobber (reg:CC 17))])]
17763 [(match_scratch:SI 2 "r")
17764 (parallel [(set (match_operand:SI 0 "register_operand" "")
17765 (match_operator:SI 3 "arith_or_logical_operator"
17766 [(match_operand:SI 1 "memory_operand" "")
17768 (clobber (reg:CC 17))])]
17769 "! optimize_size && ! TARGET_READ_MODIFY"
17770 [(set (match_dup 2) (match_dup 1))
17771 (parallel [(set (match_dup 0)
17772 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
17773 (clobber (reg:CC 17))])]
17776 ; Don't do logical operations with memory outputs
17778 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
17779 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
17780 ; the same decoder scheduling characteristics as the original.
17783 [(match_scratch:SI 2 "r")
17784 (parallel [(set (match_operand:SI 0 "memory_operand" "")
17785 (match_operator:SI 3 "arith_or_logical_operator"
17787 (match_operand:SI 1 "nonmemory_operand" "")]))
17788 (clobber (reg:CC 17))])]
17789 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
17790 [(set (match_dup 2) (match_dup 0))
17791 (parallel [(set (match_dup 2)
17792 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
17793 (clobber (reg:CC 17))])
17794 (set (match_dup 0) (match_dup 2))]
17798 [(match_scratch:SI 2 "r")
17799 (parallel [(set (match_operand:SI 0 "memory_operand" "")
17800 (match_operator:SI 3 "arith_or_logical_operator"
17801 [(match_operand:SI 1 "nonmemory_operand" "")
17803 (clobber (reg:CC 17))])]
17804 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
17805 [(set (match_dup 2) (match_dup 0))
17806 (parallel [(set (match_dup 2)
17807 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
17808 (clobber (reg:CC 17))])
17809 (set (match_dup 0) (match_dup 2))]
17812 ;; Attempt to always use XOR for zeroing registers.
17814 [(set (match_operand 0 "register_operand" "")
17816 "(GET_MODE (operands[0]) == QImode
17817 || GET_MODE (operands[0]) == HImode
17818 || GET_MODE (operands[0]) == SImode
17819 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
17820 && (! TARGET_USE_MOV0 || optimize_size)
17821 && peep2_regno_dead_p (0, FLAGS_REG)"
17822 [(parallel [(set (match_dup 0) (const_int 0))
17823 (clobber (reg:CC 17))])]
17824 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
17825 true_regnum (operands[0]));")
17828 [(set (strict_low_part (match_operand 0 "register_operand" ""))
17830 "(GET_MODE (operands[0]) == QImode
17831 || GET_MODE (operands[0]) == HImode)
17832 && (! TARGET_USE_MOV0 || optimize_size)
17833 && peep2_regno_dead_p (0, FLAGS_REG)"
17834 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
17835 (clobber (reg:CC 17))])])
17837 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
17839 [(set (match_operand 0 "register_operand" "")
17841 "(GET_MODE (operands[0]) == HImode
17842 || GET_MODE (operands[0]) == SImode
17843 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
17844 && (optimize_size || TARGET_PENTIUM)
17845 && peep2_regno_dead_p (0, FLAGS_REG)"
17846 [(parallel [(set (match_dup 0) (const_int -1))
17847 (clobber (reg:CC 17))])]
17848 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
17849 true_regnum (operands[0]));")
17851 ;; Attempt to convert simple leas to adds. These can be created by
17854 [(set (match_operand:SI 0 "register_operand" "")
17855 (plus:SI (match_dup 0)
17856 (match_operand:SI 1 "nonmemory_operand" "")))]
17857 "peep2_regno_dead_p (0, FLAGS_REG)"
17858 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
17859 (clobber (reg:CC 17))])]
17863 [(set (match_operand:SI 0 "register_operand" "")
17864 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
17865 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
17866 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
17867 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
17868 (clobber (reg:CC 17))])]
17869 "operands[2] = gen_lowpart (SImode, operands[2]);")
17872 [(set (match_operand:DI 0 "register_operand" "")
17873 (plus:DI (match_dup 0)
17874 (match_operand:DI 1 "x86_64_general_operand" "")))]
17875 "peep2_regno_dead_p (0, FLAGS_REG)"
17876 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
17877 (clobber (reg:CC 17))])]
17881 [(set (match_operand:SI 0 "register_operand" "")
17882 (mult:SI (match_dup 0)
17883 (match_operand:SI 1 "const_int_operand" "")))]
17884 "exact_log2 (INTVAL (operands[1])) >= 0
17885 && peep2_regno_dead_p (0, FLAGS_REG)"
17886 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17887 (clobber (reg:CC 17))])]
17888 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17891 [(set (match_operand:DI 0 "register_operand" "")
17892 (mult:DI (match_dup 0)
17893 (match_operand:DI 1 "const_int_operand" "")))]
17894 "exact_log2 (INTVAL (operands[1])) >= 0
17895 && peep2_regno_dead_p (0, FLAGS_REG)"
17896 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
17897 (clobber (reg:CC 17))])]
17898 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17901 [(set (match_operand:SI 0 "register_operand" "")
17902 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
17903 (match_operand:DI 2 "const_int_operand" "")) 0))]
17904 "exact_log2 (INTVAL (operands[2])) >= 0
17905 && REGNO (operands[0]) == REGNO (operands[1])
17906 && peep2_regno_dead_p (0, FLAGS_REG)"
17907 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17908 (clobber (reg:CC 17))])]
17909 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
17911 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
17912 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
17913 ;; many CPUs it is also faster, since special hardware to avoid esp
17914 ;; dependencies is present.
17916 ;; While some of these conversions may be done using splitters, we use peepholes
17917 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
17919 ;; Convert prologue esp subtractions to push.
17920 ;; We need register to push. In order to keep verify_flow_info happy we have
17922 ;; - use scratch and clobber it in order to avoid dependencies
17923 ;; - use already live register
17924 ;; We can't use the second way right now, since there is no reliable way how to
17925 ;; verify that given register is live. First choice will also most likely in
17926 ;; fewer dependencies. On the place of esp adjustments it is very likely that
17927 ;; call clobbered registers are dead. We may want to use base pointer as an
17928 ;; alternative when no register is available later.
17931 [(match_scratch:SI 0 "r")
17932 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17933 (clobber (reg:CC 17))
17934 (clobber (mem:BLK (scratch)))])]
17935 "optimize_size || !TARGET_SUB_ESP_4"
17936 [(clobber (match_dup 0))
17937 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17938 (clobber (mem:BLK (scratch)))])])
17941 [(match_scratch:SI 0 "r")
17942 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17943 (clobber (reg:CC 17))
17944 (clobber (mem:BLK (scratch)))])]
17945 "optimize_size || !TARGET_SUB_ESP_8"
17946 [(clobber (match_dup 0))
17947 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17948 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17949 (clobber (mem:BLK (scratch)))])])
17951 ;; Convert esp subtractions to push.
17953 [(match_scratch:SI 0 "r")
17954 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17955 (clobber (reg:CC 17))])]
17956 "optimize_size || !TARGET_SUB_ESP_4"
17957 [(clobber (match_dup 0))
17958 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17961 [(match_scratch:SI 0 "r")
17962 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17963 (clobber (reg:CC 17))])]
17964 "optimize_size || !TARGET_SUB_ESP_8"
17965 [(clobber (match_dup 0))
17966 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17967 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17969 ;; Convert epilogue deallocator to pop.
17971 [(match_scratch:SI 0 "r")
17972 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17973 (clobber (reg:CC 17))
17974 (clobber (mem:BLK (scratch)))])]
17975 "optimize_size || !TARGET_ADD_ESP_4"
17976 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17977 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17978 (clobber (mem:BLK (scratch)))])]
17981 ;; Two pops case is tricky, since pop causes dependency on destination register.
17982 ;; We use two registers if available.
17984 [(match_scratch:SI 0 "r")
17985 (match_scratch:SI 1 "r")
17986 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17987 (clobber (reg:CC 17))
17988 (clobber (mem:BLK (scratch)))])]
17989 "optimize_size || !TARGET_ADD_ESP_8"
17990 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17991 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17992 (clobber (mem:BLK (scratch)))])
17993 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17994 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17998 [(match_scratch:SI 0 "r")
17999 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18000 (clobber (reg:CC 17))
18001 (clobber (mem:BLK (scratch)))])]
18003 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18004 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18005 (clobber (mem:BLK (scratch)))])
18006 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18007 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18010 ;; Convert esp additions to pop.
18012 [(match_scratch:SI 0 "r")
18013 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18014 (clobber (reg:CC 17))])]
18016 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18017 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18020 ;; Two pops case is tricky, since pop causes dependency on destination register.
18021 ;; We use two registers if available.
18023 [(match_scratch:SI 0 "r")
18024 (match_scratch:SI 1 "r")
18025 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18026 (clobber (reg:CC 17))])]
18028 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18029 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
18030 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
18031 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18035 [(match_scratch:SI 0 "r")
18036 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18037 (clobber (reg:CC 17))])]
18039 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18040 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
18041 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18042 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18045 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
18046 ;; required and register dies.
18049 (compare (match_operand:SI 0 "register_operand" "")
18050 (match_operand:SI 1 "incdec_operand" "")))]
18051 "ix86_match_ccmode (insn, CCGCmode)
18052 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18053 [(parallel [(set (reg:CCGC 17)
18054 (compare:CCGC (match_dup 0)
18056 (clobber (match_dup 0))])]
18061 (compare (match_operand:HI 0 "register_operand" "")
18062 (match_operand:HI 1 "incdec_operand" "")))]
18063 "ix86_match_ccmode (insn, CCGCmode)
18064 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18065 [(parallel [(set (reg:CCGC 17)
18066 (compare:CCGC (match_dup 0)
18068 (clobber (match_dup 0))])]
18073 (compare (match_operand:QI 0 "register_operand" "")
18074 (match_operand:QI 1 "incdec_operand" "")))]
18075 "ix86_match_ccmode (insn, CCGCmode)
18076 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18077 [(parallel [(set (reg:CCGC 17)
18078 (compare:CCGC (match_dup 0)
18080 (clobber (match_dup 0))])]
18083 ;; Convert compares with 128 to shorter add -128
18086 (compare (match_operand:SI 0 "register_operand" "")
18088 "ix86_match_ccmode (insn, CCGCmode)
18089 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18090 [(parallel [(set (reg:CCGC 17)
18091 (compare:CCGC (match_dup 0)
18093 (clobber (match_dup 0))])]
18098 (compare (match_operand:HI 0 "register_operand" "")
18100 "ix86_match_ccmode (insn, CCGCmode)
18101 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18102 [(parallel [(set (reg:CCGC 17)
18103 (compare:CCGC (match_dup 0)
18105 (clobber (match_dup 0))])]
18109 [(match_scratch:DI 0 "r")
18110 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18111 (clobber (reg:CC 17))
18112 (clobber (mem:BLK (scratch)))])]
18113 "optimize_size || !TARGET_SUB_ESP_4"
18114 [(clobber (match_dup 0))
18115 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18116 (clobber (mem:BLK (scratch)))])])
18119 [(match_scratch:DI 0 "r")
18120 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
18121 (clobber (reg:CC 17))
18122 (clobber (mem:BLK (scratch)))])]
18123 "optimize_size || !TARGET_SUB_ESP_8"
18124 [(clobber (match_dup 0))
18125 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18126 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18127 (clobber (mem:BLK (scratch)))])])
18129 ;; Convert esp subtractions to push.
18131 [(match_scratch:DI 0 "r")
18132 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18133 (clobber (reg:CC 17))])]
18134 "optimize_size || !TARGET_SUB_ESP_4"
18135 [(clobber (match_dup 0))
18136 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
18139 [(match_scratch:DI 0 "r")
18140 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
18141 (clobber (reg:CC 17))])]
18142 "optimize_size || !TARGET_SUB_ESP_8"
18143 [(clobber (match_dup 0))
18144 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18145 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
18147 ;; Convert epilogue deallocator to pop.
18149 [(match_scratch:DI 0 "r")
18150 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18151 (clobber (reg:CC 17))
18152 (clobber (mem:BLK (scratch)))])]
18153 "optimize_size || !TARGET_ADD_ESP_4"
18154 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18155 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18156 (clobber (mem:BLK (scratch)))])]
18159 ;; Two pops case is tricky, since pop causes dependency on destination register.
18160 ;; We use two registers if available.
18162 [(match_scratch:DI 0 "r")
18163 (match_scratch:DI 1 "r")
18164 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18165 (clobber (reg:CC 17))
18166 (clobber (mem:BLK (scratch)))])]
18167 "optimize_size || !TARGET_ADD_ESP_8"
18168 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18169 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18170 (clobber (mem:BLK (scratch)))])
18171 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
18172 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18176 [(match_scratch:DI 0 "r")
18177 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18178 (clobber (reg:CC 17))
18179 (clobber (mem:BLK (scratch)))])]
18181 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18182 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18183 (clobber (mem:BLK (scratch)))])
18184 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18185 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18188 ;; Convert esp additions to pop.
18190 [(match_scratch:DI 0 "r")
18191 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18192 (clobber (reg:CC 17))])]
18194 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18195 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18198 ;; Two pops case is tricky, since pop causes dependency on destination register.
18199 ;; We use two registers if available.
18201 [(match_scratch:DI 0 "r")
18202 (match_scratch:DI 1 "r")
18203 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18204 (clobber (reg:CC 17))])]
18206 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18207 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
18208 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
18209 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18213 [(match_scratch:DI 0 "r")
18214 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18215 (clobber (reg:CC 17))])]
18217 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18218 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
18219 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18220 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18223 ;; Imul $32bit_imm, mem, reg is vector decoded, while
18224 ;; imul $32bit_imm, reg, reg is direct decoded.
18226 [(match_scratch:DI 3 "r")
18227 (parallel [(set (match_operand:DI 0 "register_operand" "")
18228 (mult:DI (match_operand:DI 1 "memory_operand" "")
18229 (match_operand:DI 2 "immediate_operand" "")))
18230 (clobber (reg:CC 17))])]
18231 "TARGET_K8 && !optimize_size
18232 && (GET_CODE (operands[2]) != CONST_INT
18233 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18234 [(set (match_dup 3) (match_dup 1))
18235 (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
18236 (clobber (reg:CC 17))])]
18240 [(match_scratch:SI 3 "r")
18241 (parallel [(set (match_operand:SI 0 "register_operand" "")
18242 (mult:SI (match_operand:SI 1 "memory_operand" "")
18243 (match_operand:SI 2 "immediate_operand" "")))
18244 (clobber (reg:CC 17))])]
18245 "TARGET_K8 && !optimize_size
18246 && (GET_CODE (operands[2]) != CONST_INT
18247 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18248 [(set (match_dup 3) (match_dup 1))
18249 (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
18250 (clobber (reg:CC 17))])]
18254 [(match_scratch:SI 3 "r")
18255 (parallel [(set (match_operand:DI 0 "register_operand" "")
18257 (mult:SI (match_operand:SI 1 "memory_operand" "")
18258 (match_operand:SI 2 "immediate_operand" ""))))
18259 (clobber (reg:CC 17))])]
18260 "TARGET_K8 && !optimize_size
18261 && (GET_CODE (operands[2]) != CONST_INT
18262 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18263 [(set (match_dup 3) (match_dup 1))
18264 (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
18265 (clobber (reg:CC 17))])]
18268 ;; imul $8/16bit_imm, regmem, reg is vector decoded.
18269 ;; Convert it into imul reg, reg
18270 ;; It would be better to force assembler to encode instruction using long
18271 ;; immediate, but there is apparently no way to do so.
18273 [(parallel [(set (match_operand:DI 0 "register_operand" "")
18274 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
18275 (match_operand:DI 2 "const_int_operand" "")))
18276 (clobber (reg:CC 17))])
18277 (match_scratch:DI 3 "r")]
18278 "TARGET_K8 && !optimize_size
18279 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
18280 [(set (match_dup 3) (match_dup 2))
18281 (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
18282 (clobber (reg:CC 17))])]
18284 if (!rtx_equal_p (operands[0], operands[1]))
18285 emit_move_insn (operands[0], operands[1]);
18289 [(parallel [(set (match_operand:SI 0 "register_operand" "")
18290 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
18291 (match_operand:SI 2 "const_int_operand" "")))
18292 (clobber (reg:CC 17))])
18293 (match_scratch:SI 3 "r")]
18294 "TARGET_K8 && !optimize_size
18295 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
18296 [(set (match_dup 3) (match_dup 2))
18297 (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
18298 (clobber (reg:CC 17))])]
18300 if (!rtx_equal_p (operands[0], operands[1]))
18301 emit_move_insn (operands[0], operands[1]);
18305 [(parallel [(set (match_operand:HI 0 "register_operand" "")
18306 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
18307 (match_operand:HI 2 "immediate_operand" "")))
18308 (clobber (reg:CC 17))])
18309 (match_scratch:HI 3 "r")]
18310 "TARGET_K8 && !optimize_size"
18311 [(set (match_dup 3) (match_dup 2))
18312 (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
18313 (clobber (reg:CC 17))])]
18315 if (!rtx_equal_p (operands[0], operands[1]))
18316 emit_move_insn (operands[0], operands[1]);
18319 ;; Call-value patterns last so that the wildcard operand does not
18320 ;; disrupt insn-recog's switch tables.
18322 (define_insn "*call_value_pop_0"
18323 [(set (match_operand 0 "" "")
18324 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
18325 (match_operand:SI 2 "" "")))
18326 (set (reg:SI 7) (plus:SI (reg:SI 7)
18327 (match_operand:SI 3 "immediate_operand" "")))]
18330 if (SIBLING_CALL_P (insn))
18333 return "call\t%P1";
18335 [(set_attr "type" "callv")])
18337 (define_insn "*call_value_pop_1"
18338 [(set (match_operand 0 "" "")
18339 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
18340 (match_operand:SI 2 "" "")))
18341 (set (reg:SI 7) (plus:SI (reg:SI 7)
18342 (match_operand:SI 3 "immediate_operand" "i")))]
18345 if (constant_call_address_operand (operands[1], QImode))
18347 if (SIBLING_CALL_P (insn))
18350 return "call\t%P1";
18352 if (SIBLING_CALL_P (insn))
18355 return "call\t%A1";
18357 [(set_attr "type" "callv")])
18359 (define_insn "*call_value_0"
18360 [(set (match_operand 0 "" "")
18361 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
18362 (match_operand:SI 2 "" "")))]
18365 if (SIBLING_CALL_P (insn))
18368 return "call\t%P1";
18370 [(set_attr "type" "callv")])
18372 (define_insn "*call_value_0_rex64"
18373 [(set (match_operand 0 "" "")
18374 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
18375 (match_operand:DI 2 "const_int_operand" "")))]
18378 if (SIBLING_CALL_P (insn))
18381 return "call\t%P1";
18383 [(set_attr "type" "callv")])
18385 (define_insn "*call_value_1"
18386 [(set (match_operand 0 "" "")
18387 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
18388 (match_operand:SI 2 "" "")))]
18389 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
18391 if (constant_call_address_operand (operands[1], QImode))
18392 return "call\t%P1";
18393 return "call\t%*%1";
18395 [(set_attr "type" "callv")])
18397 (define_insn "*sibcall_value_1"
18398 [(set (match_operand 0 "" "")
18399 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
18400 (match_operand:SI 2 "" "")))]
18401 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
18403 if (constant_call_address_operand (operands[1], QImode))
18405 return "jmp\t%*%1";
18407 [(set_attr "type" "callv")])
18409 (define_insn "*call_value_1_rex64"
18410 [(set (match_operand 0 "" "")
18411 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
18412 (match_operand:DI 2 "" "")))]
18413 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
18415 if (constant_call_address_operand (operands[1], QImode))
18416 return "call\t%P1";
18417 return "call\t%A1";
18419 [(set_attr "type" "callv")])
18421 (define_insn "*sibcall_value_1_rex64"
18422 [(set (match_operand 0 "" "")
18423 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
18424 (match_operand:DI 2 "" "")))]
18425 "SIBLING_CALL_P (insn) && TARGET_64BIT"
18427 [(set_attr "type" "callv")])
18429 (define_insn "*sibcall_value_1_rex64_v"
18430 [(set (match_operand 0 "" "")
18431 (call (mem:QI (reg:DI 40))
18432 (match_operand:DI 1 "" "")))]
18433 "SIBLING_CALL_P (insn) && TARGET_64BIT"
18435 [(set_attr "type" "callv")])
18437 (define_insn "trap"
18438 [(trap_if (const_int 1) (const_int 5))]
18442 ;;; ix86 doesn't have conditional trap instructions, but we fake them
18443 ;;; for the sake of bounds checking. By emitting bounds checks as
18444 ;;; conditional traps rather than as conditional jumps around
18445 ;;; unconditional traps we avoid introducing spurious basic-block
18446 ;;; boundaries and facilitate elimination of redundant checks. In
18447 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
18450 ;;; FIXME: Static branch prediction rules for ix86 are such that
18451 ;;; forward conditional branches predict as untaken. As implemented
18452 ;;; below, pseudo conditional traps violate that rule. We should use
18453 ;;; .pushsection/.popsection to place all of the `int 5's in a special
18454 ;;; section loaded at the end of the text segment and branch forward
18455 ;;; there on bounds-failure, and then jump back immediately (in case
18456 ;;; the system chooses to ignore bounds violations, or to report
18457 ;;; violations and continue execution).
18459 (define_expand "conditional_trap"
18460 [(trap_if (match_operator 0 "comparison_operator"
18461 [(match_dup 2) (const_int 0)])
18462 (match_operand 1 "const_int_operand" ""))]
18465 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
18466 ix86_expand_compare (GET_CODE (operands[0]),
18472 (define_insn "*conditional_trap_1"
18473 [(trap_if (match_operator 0 "comparison_operator"
18474 [(reg 17) (const_int 0)])
18475 (match_operand 1 "const_int_operand" ""))]
18478 operands[2] = gen_label_rtx ();
18479 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
18480 (*targetm.asm_out.internal_label) (asm_out_file, "L",
18481 CODE_LABEL_NUMBER (operands[2]));
18485 ;; Pentium III SIMD instructions.
18487 ;; Moves for SSE/MMX regs.
18489 (define_insn "movv4sf_internal"
18490 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18491 (match_operand:V4SF 1 "nonimmediate_operand" "xm,x"))]
18493 "movaps\t{%1, %0|%0, %1}"
18494 [(set_attr "type" "ssemov")
18495 (set_attr "mode" "V4SF")])
18498 [(set (match_operand:V4SF 0 "register_operand" "")
18499 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
18501 [(set (match_dup 0)
18503 (vec_duplicate:V4SF (match_dup 1))
18507 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
18508 operands[2] = CONST0_RTX (V4SFmode);
18511 (define_insn "movv4si_internal"
18512 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
18513 (match_operand:V4SI 1 "nonimmediate_operand" "xm,x"))]
18516 if (get_attr_mode (insn) == MODE_V4SF)
18517 return "movaps\t{%1, %0|%0, %1}";
18519 return "movdqa\t{%1, %0|%0, %1}";
18521 [(set_attr "type" "ssemov")
18523 (cond [(eq_attr "alternative" "0")
18525 (ne (symbol_ref "optimize_size")
18527 (const_string "V4SF")
18528 (const_string "TI"))
18529 (eq_attr "alternative" "1")
18531 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18533 (ne (symbol_ref "optimize_size")
18535 (const_string "V4SF")
18536 (const_string "TI"))]
18537 (const_string "TI")))])
18539 (define_insn "movv2di_internal"
18540 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,m")
18541 (match_operand:V2DI 1 "nonimmediate_operand" "xm,x"))]
18544 if (get_attr_mode (insn) == MODE_V4SF)
18545 return "movaps\t{%1, %0|%0, %1}";
18547 return "movdqa\t{%1, %0|%0, %1}";
18549 [(set_attr "type" "ssemov")
18551 (cond [(eq_attr "alternative" "0")
18553 (ne (symbol_ref "optimize_size")
18555 (const_string "V4SF")
18556 (const_string "TI"))
18557 (eq_attr "alternative" "1")
18559 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18561 (ne (symbol_ref "optimize_size")
18563 (const_string "V4SF")
18564 (const_string "TI"))]
18565 (const_string "TI")))])
18568 [(set (match_operand:V2DF 0 "register_operand" "")
18569 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
18571 [(set (match_dup 0)
18573 (vec_duplicate:V2DF (match_dup 1))
18577 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
18578 operands[2] = CONST0_RTX (V2DFmode);
18581 (define_insn "movv8qi_internal"
18582 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
18583 (match_operand:V8QI 1 "nonimmediate_operand" "ym,y"))]
18585 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18586 "movq\t{%1, %0|%0, %1}"
18587 [(set_attr "type" "mmxmov")
18588 (set_attr "mode" "DI")])
18590 (define_insn "movv4hi_internal"
18591 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
18592 (match_operand:V4HI 1 "nonimmediate_operand" "ym,y"))]
18594 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18595 "movq\t{%1, %0|%0, %1}"
18596 [(set_attr "type" "mmxmov")
18597 (set_attr "mode" "DI")])
18599 (define_insn "movv2si_internal"
18600 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
18601 (match_operand:V2SI 1 "nonimmediate_operand" "ym,y"))]
18603 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18604 "movq\t{%1, %0|%0, %1}"
18605 [(set_attr "type" "mmxcvt")
18606 (set_attr "mode" "DI")])
18608 (define_insn "movv2sf_internal"
18609 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,m")
18610 (match_operand:V2SF 1 "nonimmediate_operand" "ym,y"))]
18612 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18613 "movq\\t{%1, %0|%0, %1}"
18614 [(set_attr "type" "mmxcvt")
18615 (set_attr "mode" "DI")])
18617 (define_expand "movti"
18618 [(set (match_operand:TI 0 "nonimmediate_operand" "")
18619 (match_operand:TI 1 "nonimmediate_operand" ""))]
18620 "TARGET_SSE || TARGET_64BIT"
18623 ix86_expand_move (TImode, operands);
18625 ix86_expand_vector_move (TImode, operands);
18629 (define_insn "movv2df_internal"
18630 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
18631 (match_operand:V2DF 1 "nonimmediate_operand" "xm,x"))]
18633 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18635 if (get_attr_mode (insn) == MODE_V4SF)
18636 return "movaps\t{%1, %0|%0, %1}";
18638 return "movapd\t{%1, %0|%0, %1}";
18640 [(set_attr "type" "ssemov")
18642 (cond [(eq_attr "alternative" "0")
18644 (ne (symbol_ref "optimize_size")
18646 (const_string "V4SF")
18647 (const_string "V2DF"))
18648 (eq_attr "alternative" "1")
18650 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18652 (ne (symbol_ref "optimize_size")
18654 (const_string "V4SF")
18655 (const_string "V2DF"))]
18656 (const_string "V2DF")))])
18658 (define_insn "movv8hi_internal"
18659 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m")
18660 (match_operand:V8HI 1 "nonimmediate_operand" "xm,x"))]
18662 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18664 if (get_attr_mode (insn) == MODE_V4SF)
18665 return "movaps\t{%1, %0|%0, %1}";
18667 return "movdqa\t{%1, %0|%0, %1}";
18669 [(set_attr "type" "ssemov")
18671 (cond [(eq_attr "alternative" "0")
18673 (ne (symbol_ref "optimize_size")
18675 (const_string "V4SF")
18676 (const_string "TI"))
18677 (eq_attr "alternative" "1")
18679 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18681 (ne (symbol_ref "optimize_size")
18683 (const_string "V4SF")
18684 (const_string "TI"))]
18685 (const_string "TI")))])
18687 (define_insn "movv16qi_internal"
18688 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
18689 (match_operand:V16QI 1 "nonimmediate_operand" "xm,x"))]
18691 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18693 if (get_attr_mode (insn) == MODE_V4SF)
18694 return "movaps\t{%1, %0|%0, %1}";
18696 return "movdqa\t{%1, %0|%0, %1}";
18698 [(set_attr "type" "ssemov")
18700 (cond [(eq_attr "alternative" "0")
18702 (ne (symbol_ref "optimize_size")
18704 (const_string "V4SF")
18705 (const_string "TI"))
18706 (eq_attr "alternative" "1")
18708 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18710 (ne (symbol_ref "optimize_size")
18712 (const_string "V4SF")
18713 (const_string "TI"))]
18714 (const_string "TI")))])
18716 (define_expand "movv2df"
18717 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
18718 (match_operand:V2DF 1 "nonimmediate_operand" ""))]
18721 ix86_expand_vector_move (V2DFmode, operands);
18725 (define_expand "movv8hi"
18726 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
18727 (match_operand:V8HI 1 "nonimmediate_operand" ""))]
18730 ix86_expand_vector_move (V8HImode, operands);
18734 (define_expand "movv16qi"
18735 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
18736 (match_operand:V16QI 1 "nonimmediate_operand" ""))]
18739 ix86_expand_vector_move (V16QImode, operands);
18743 (define_expand "movv4sf"
18744 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
18745 (match_operand:V4SF 1 "nonimmediate_operand" ""))]
18748 ix86_expand_vector_move (V4SFmode, operands);
18752 (define_expand "movv4si"
18753 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
18754 (match_operand:V4SI 1 "nonimmediate_operand" ""))]
18757 ix86_expand_vector_move (V4SImode, operands);
18761 (define_expand "movv2di"
18762 [(set (match_operand:V2DI 0 "nonimmediate_operand" "")
18763 (match_operand:V2DI 1 "nonimmediate_operand" ""))]
18766 ix86_expand_vector_move (V2DImode, operands);
18770 (define_expand "movv2si"
18771 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
18772 (match_operand:V2SI 1 "nonimmediate_operand" ""))]
18775 ix86_expand_vector_move (V2SImode, operands);
18779 (define_expand "movv4hi"
18780 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
18781 (match_operand:V4HI 1 "nonimmediate_operand" ""))]
18784 ix86_expand_vector_move (V4HImode, operands);
18788 (define_expand "movv8qi"
18789 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
18790 (match_operand:V8QI 1 "nonimmediate_operand" ""))]
18793 ix86_expand_vector_move (V8QImode, operands);
18797 (define_expand "movv2sf"
18798 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
18799 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
18802 ix86_expand_vector_move (V2SFmode, operands);
18806 (define_insn "*pushti"
18807 [(set (match_operand:TI 0 "push_operand" "=<")
18808 (match_operand:TI 1 "register_operand" "x"))]
18812 (define_insn "*pushv2df"
18813 [(set (match_operand:V2DF 0 "push_operand" "=<")
18814 (match_operand:V2DF 1 "register_operand" "x"))]
18818 (define_insn "*pushv2di"
18819 [(set (match_operand:V2DI 0 "push_operand" "=<")
18820 (match_operand:V2DI 1 "register_operand" "x"))]
18824 (define_insn "*pushv8hi"
18825 [(set (match_operand:V8HI 0 "push_operand" "=<")
18826 (match_operand:V8HI 1 "register_operand" "x"))]
18830 (define_insn "*pushv16qi"
18831 [(set (match_operand:V16QI 0 "push_operand" "=<")
18832 (match_operand:V16QI 1 "register_operand" "x"))]
18836 (define_insn "*pushv4sf"
18837 [(set (match_operand:V4SF 0 "push_operand" "=<")
18838 (match_operand:V4SF 1 "register_operand" "x"))]
18842 (define_insn "*pushv4si"
18843 [(set (match_operand:V4SI 0 "push_operand" "=<")
18844 (match_operand:V4SI 1 "register_operand" "x"))]
18848 (define_insn "*pushv2si"
18849 [(set (match_operand:V2SI 0 "push_operand" "=<")
18850 (match_operand:V2SI 1 "register_operand" "y"))]
18854 (define_insn "*pushv4hi"
18855 [(set (match_operand:V4HI 0 "push_operand" "=<")
18856 (match_operand:V4HI 1 "register_operand" "y"))]
18860 (define_insn "*pushv8qi"
18861 [(set (match_operand:V8QI 0 "push_operand" "=<")
18862 (match_operand:V8QI 1 "register_operand" "y"))]
18866 (define_insn "*pushv2sf"
18867 [(set (match_operand:V2SF 0 "push_operand" "=<")
18868 (match_operand:V2SF 1 "register_operand" "y"))]
18873 [(set (match_operand 0 "push_operand" "")
18874 (match_operand 1 "register_operand" ""))]
18875 "!TARGET_64BIT && reload_completed
18876 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
18877 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 3)))
18878 (set (match_dup 2) (match_dup 1))]
18879 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
18880 stack_pointer_rtx);
18881 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
18884 [(set (match_operand 0 "push_operand" "")
18885 (match_operand 1 "register_operand" ""))]
18886 "TARGET_64BIT && reload_completed
18887 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
18888 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 3)))
18889 (set (match_dup 2) (match_dup 1))]
18890 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
18891 stack_pointer_rtx);
18892 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
18895 (define_insn "movti_internal"
18896 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
18897 (match_operand:TI 1 "general_operand" "C,xm,x"))]
18898 "TARGET_SSE && !TARGET_64BIT
18899 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18901 switch (which_alternative)
18904 if (get_attr_mode (insn) == MODE_V4SF)
18905 return "xorps\t%0, %0";
18907 return "pxor\t%0, %0";
18910 if (get_attr_mode (insn) == MODE_V4SF)
18911 return "movaps\t{%1, %0|%0, %1}";
18913 return "movdqa\t{%1, %0|%0, %1}";
18918 [(set_attr "type" "ssemov,ssemov,ssemov")
18920 (cond [(eq_attr "alternative" "0,1")
18922 (ne (symbol_ref "optimize_size")
18924 (const_string "V4SF")
18925 (const_string "TI"))
18926 (eq_attr "alternative" "2")
18928 (ne (symbol_ref "optimize_size")
18930 (const_string "V4SF")
18931 (const_string "TI"))]
18932 (const_string "TI")))])
18934 (define_insn "*movti_rex64"
18935 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
18936 (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
18938 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18940 switch (which_alternative)
18946 if (get_attr_mode (insn) == MODE_V4SF)
18947 return "xorps\t%0, %0";
18949 return "pxor\t%0, %0";
18952 if (get_attr_mode (insn) == MODE_V4SF)
18953 return "movaps\t{%1, %0|%0, %1}";
18955 return "movdqa\t{%1, %0|%0, %1}";
18960 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
18962 (cond [(eq_attr "alternative" "2,3")
18964 (ne (symbol_ref "optimize_size")
18966 (const_string "V4SF")
18967 (const_string "TI"))
18968 (eq_attr "alternative" "4")
18970 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18972 (ne (symbol_ref "optimize_size")
18974 (const_string "V4SF")
18975 (const_string "TI"))]
18976 (const_string "DI")))])
18979 [(set (match_operand:TI 0 "nonimmediate_operand" "")
18980 (match_operand:TI 1 "general_operand" ""))]
18981 "reload_completed && !SSE_REG_P (operands[0])
18982 && !SSE_REG_P (operands[1])"
18984 "ix86_split_long_move (operands); DONE;")
18986 ;; These two patterns are useful for specifying exactly whether to use
18987 ;; movaps or movups
18988 (define_insn "sse_movaps"
18989 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18990 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
18993 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18994 "movaps\t{%1, %0|%0, %1}"
18995 [(set_attr "type" "ssemov,ssemov")
18996 (set_attr "mode" "V4SF")])
18998 (define_insn "sse_movups"
18999 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19000 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
19003 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19004 "movups\t{%1, %0|%0, %1}"
19005 [(set_attr "type" "ssecvt,ssecvt")
19006 (set_attr "mode" "V4SF")])
19009 ;; SSE Strange Moves.
19011 (define_insn "sse_movmskps"
19012 [(set (match_operand:SI 0 "register_operand" "=r")
19013 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
19016 "movmskps\t{%1, %0|%0, %1}"
19017 [(set_attr "type" "ssecvt")
19018 (set_attr "mode" "V4SF")])
19020 (define_insn "mmx_pmovmskb"
19021 [(set (match_operand:SI 0 "register_operand" "=r")
19022 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
19024 "TARGET_SSE || TARGET_3DNOW_A"
19025 "pmovmskb\t{%1, %0|%0, %1}"
19026 [(set_attr "type" "ssecvt")
19027 (set_attr "mode" "V4SF")])
19030 (define_insn "mmx_maskmovq"
19031 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
19032 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19033 (match_operand:V8QI 2 "register_operand" "y")]
19035 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
19036 ;; @@@ check ordering of operands in intel/nonintel syntax
19037 "maskmovq\t{%2, %1|%1, %2}"
19038 [(set_attr "type" "mmxcvt")
19039 (set_attr "mode" "DI")])
19041 (define_insn "mmx_maskmovq_rex"
19042 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
19043 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19044 (match_operand:V8QI 2 "register_operand" "y")]
19046 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
19047 ;; @@@ check ordering of operands in intel/nonintel syntax
19048 "maskmovq\t{%2, %1|%1, %2}"
19049 [(set_attr "type" "mmxcvt")
19050 (set_attr "mode" "DI")])
19052 (define_insn "sse_movntv4sf"
19053 [(set (match_operand:V4SF 0 "memory_operand" "=m")
19054 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
19057 "movntps\t{%1, %0|%0, %1}"
19058 [(set_attr "type" "ssemov")
19059 (set_attr "mode" "V4SF")])
19061 (define_insn "sse_movntdi"
19062 [(set (match_operand:DI 0 "memory_operand" "=m")
19063 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
19065 "TARGET_SSE || TARGET_3DNOW_A"
19066 "movntq\t{%1, %0|%0, %1}"
19067 [(set_attr "type" "mmxmov")
19068 (set_attr "mode" "DI")])
19070 (define_insn "sse_movhlps"
19071 [(set (match_operand:V4SF 0 "register_operand" "=x")
19073 (match_operand:V4SF 1 "register_operand" "0")
19074 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19075 (parallel [(const_int 2)
19081 "movhlps\t{%2, %0|%0, %2}"
19082 [(set_attr "type" "ssecvt")
19083 (set_attr "mode" "V4SF")])
19085 (define_insn "sse_movlhps"
19086 [(set (match_operand:V4SF 0 "register_operand" "=x")
19088 (match_operand:V4SF 1 "register_operand" "0")
19089 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19090 (parallel [(const_int 2)
19096 "movlhps\t{%2, %0|%0, %2}"
19097 [(set_attr "type" "ssecvt")
19098 (set_attr "mode" "V4SF")])
19100 (define_insn "sse_movhps"
19101 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19103 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
19104 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
19107 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
19108 "movhps\t{%2, %0|%0, %2}"
19109 [(set_attr "type" "ssecvt")
19110 (set_attr "mode" "V4SF")])
19112 (define_insn "sse_movlps"
19113 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19115 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
19116 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
19119 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
19120 "movlps\t{%2, %0|%0, %2}"
19121 [(set_attr "type" "ssecvt")
19122 (set_attr "mode" "V4SF")])
19124 (define_expand "sse_loadss"
19125 [(match_operand:V4SF 0 "register_operand" "")
19126 (match_operand:SF 1 "memory_operand" "")]
19129 emit_insn (gen_sse_loadss_1 (operands[0], operands[1],
19130 CONST0_RTX (V4SFmode)));
19134 (define_insn "sse_loadss_1"
19135 [(set (match_operand:V4SF 0 "register_operand" "=x")
19137 (vec_duplicate:V4SF (match_operand:SF 1 "memory_operand" "m"))
19138 (match_operand:V4SF 2 "const0_operand" "X")
19141 "movss\t{%1, %0|%0, %1}"
19142 [(set_attr "type" "ssemov")
19143 (set_attr "mode" "SF")])
19145 (define_insn "sse_movss"
19146 [(set (match_operand:V4SF 0 "register_operand" "=x")
19148 (match_operand:V4SF 1 "register_operand" "0")
19149 (match_operand:V4SF 2 "register_operand" "x")
19152 "movss\t{%2, %0|%0, %2}"
19153 [(set_attr "type" "ssemov")
19154 (set_attr "mode" "SF")])
19156 (define_insn "sse_storess"
19157 [(set (match_operand:SF 0 "memory_operand" "=m")
19159 (match_operand:V4SF 1 "register_operand" "x")
19160 (parallel [(const_int 0)])))]
19162 "movss\t{%1, %0|%0, %1}"
19163 [(set_attr "type" "ssemov")
19164 (set_attr "mode" "SF")])
19166 (define_insn "sse_shufps"
19167 [(set (match_operand:V4SF 0 "register_operand" "=x")
19168 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
19169 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
19170 (match_operand:SI 3 "immediate_operand" "i")]
19173 ;; @@@ check operand order for intel/nonintel syntax
19174 "shufps\t{%3, %2, %0|%0, %2, %3}"
19175 [(set_attr "type" "ssecvt")
19176 (set_attr "mode" "V4SF")])
19181 (define_insn "addv4sf3"
19182 [(set (match_operand:V4SF 0 "register_operand" "=x")
19183 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19184 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19186 "addps\t{%2, %0|%0, %2}"
19187 [(set_attr "type" "sseadd")
19188 (set_attr "mode" "V4SF")])
19190 (define_insn "vmaddv4sf3"
19191 [(set (match_operand:V4SF 0 "register_operand" "=x")
19193 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19194 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19198 "addss\t{%2, %0|%0, %2}"
19199 [(set_attr "type" "sseadd")
19200 (set_attr "mode" "SF")])
19202 (define_insn "subv4sf3"
19203 [(set (match_operand:V4SF 0 "register_operand" "=x")
19204 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19205 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19207 "subps\t{%2, %0|%0, %2}"
19208 [(set_attr "type" "sseadd")
19209 (set_attr "mode" "V4SF")])
19211 (define_insn "vmsubv4sf3"
19212 [(set (match_operand:V4SF 0 "register_operand" "=x")
19214 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19215 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19219 "subss\t{%2, %0|%0, %2}"
19220 [(set_attr "type" "sseadd")
19221 (set_attr "mode" "SF")])
19223 (define_insn "mulv4sf3"
19224 [(set (match_operand:V4SF 0 "register_operand" "=x")
19225 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
19226 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19228 "mulps\t{%2, %0|%0, %2}"
19229 [(set_attr "type" "ssemul")
19230 (set_attr "mode" "V4SF")])
19232 (define_insn "vmmulv4sf3"
19233 [(set (match_operand:V4SF 0 "register_operand" "=x")
19235 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
19236 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19240 "mulss\t{%2, %0|%0, %2}"
19241 [(set_attr "type" "ssemul")
19242 (set_attr "mode" "SF")])
19244 (define_insn "divv4sf3"
19245 [(set (match_operand:V4SF 0 "register_operand" "=x")
19246 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
19247 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19249 "divps\t{%2, %0|%0, %2}"
19250 [(set_attr "type" "ssediv")
19251 (set_attr "mode" "V4SF")])
19253 (define_insn "vmdivv4sf3"
19254 [(set (match_operand:V4SF 0 "register_operand" "=x")
19256 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
19257 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19261 "divss\t{%2, %0|%0, %2}"
19262 [(set_attr "type" "ssediv")
19263 (set_attr "mode" "SF")])
19266 ;; SSE square root/reciprocal
19268 (define_insn "rcpv4sf2"
19269 [(set (match_operand:V4SF 0 "register_operand" "=x")
19271 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
19273 "rcpps\t{%1, %0|%0, %1}"
19274 [(set_attr "type" "sse")
19275 (set_attr "mode" "V4SF")])
19277 (define_insn "vmrcpv4sf2"
19278 [(set (match_operand:V4SF 0 "register_operand" "=x")
19280 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19282 (match_operand:V4SF 2 "register_operand" "0")
19285 "rcpss\t{%1, %0|%0, %1}"
19286 [(set_attr "type" "sse")
19287 (set_attr "mode" "SF")])
19289 (define_insn "rsqrtv4sf2"
19290 [(set (match_operand:V4SF 0 "register_operand" "=x")
19292 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
19294 "rsqrtps\t{%1, %0|%0, %1}"
19295 [(set_attr "type" "sse")
19296 (set_attr "mode" "V4SF")])
19298 (define_insn "vmrsqrtv4sf2"
19299 [(set (match_operand:V4SF 0 "register_operand" "=x")
19301 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19303 (match_operand:V4SF 2 "register_operand" "0")
19306 "rsqrtss\t{%1, %0|%0, %1}"
19307 [(set_attr "type" "sse")
19308 (set_attr "mode" "SF")])
19310 (define_insn "sqrtv4sf2"
19311 [(set (match_operand:V4SF 0 "register_operand" "=x")
19312 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
19314 "sqrtps\t{%1, %0|%0, %1}"
19315 [(set_attr "type" "sse")
19316 (set_attr "mode" "V4SF")])
19318 (define_insn "vmsqrtv4sf2"
19319 [(set (match_operand:V4SF 0 "register_operand" "=x")
19321 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
19322 (match_operand:V4SF 2 "register_operand" "0")
19325 "sqrtss\t{%1, %0|%0, %1}"
19326 [(set_attr "type" "sse")
19327 (set_attr "mode" "SF")])
19329 ;; SSE logical operations.
19331 ;; SSE defines logical operations on floating point values. This brings
19332 ;; interesting challenge to RTL representation where logicals are only valid
19333 ;; on integral types. We deal with this by representing the floating point
19334 ;; logical as logical on arguments casted to TImode as this is what hardware
19335 ;; really does. Unfortunately hardware requires the type information to be
19336 ;; present and thus we must avoid subregs from being simplified and eliminated
19337 ;; in later compilation phases.
19339 ;; We have following variants from each instruction:
19340 ;; sse_andsf3 - the operation taking V4SF vector operands
19341 ;; and doing TImode cast on them
19342 ;; *sse_andsf3_memory - the operation taking one memory operand casted to
19343 ;; TImode, since backend insist on eliminating casts
19344 ;; on memory operands
19345 ;; sse_andti3_sf_1 - the operation taking SF scalar operands.
19346 ;; We can not accept memory operand here as instruction reads
19347 ;; whole scalar. This is generated only post reload by GCC
19348 ;; scalar float operations that expands to logicals (fabs)
19349 ;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode
19350 ;; memory operand. Eventually combine can be able
19351 ;; to synthesize these using splitter.
19352 ;; sse2_anddf3, *sse2_anddf3_memory
19355 ;; These are not called andti3 etc. because we really really don't want
19356 ;; the compiler to widen DImode ands to TImode ands and then try to move
19357 ;; into DImode subregs of SSE registers, and them together, and move out
19358 ;; of DImode subregs again!
19359 ;; SSE1 single precision floating point logical operation
19360 (define_expand "sse_andv4sf3"
19361 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19362 (and:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19363 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19367 (define_insn "*sse_andv4sf3"
19368 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19369 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19370 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19372 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19373 "andps\t{%2, %0|%0, %2}"
19374 [(set_attr "type" "sselog")
19375 (set_attr "mode" "V4SF")])
19377 (define_insn "*sse_andsf3"
19378 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19379 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19380 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19382 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19383 "andps\t{%2, %0|%0, %2}"
19384 [(set_attr "type" "sselog")
19385 (set_attr "mode" "V4SF")])
19387 (define_expand "sse_nandv4sf3"
19388 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19389 (and:TI (not:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0))
19390 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19394 (define_insn "*sse_nandv4sf3"
19395 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19396 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19397 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19399 "andnps\t{%2, %0|%0, %2}"
19400 [(set_attr "type" "sselog")
19401 (set_attr "mode" "V4SF")])
19403 (define_insn "*sse_nandsf3"
19404 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19405 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19406 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19408 "andnps\t{%2, %0|%0, %2}"
19409 [(set_attr "type" "sselog")
19410 (set_attr "mode" "V4SF")])
19412 (define_expand "sse_iorv4sf3"
19413 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19414 (ior:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19415 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19419 (define_insn "*sse_iorv4sf3"
19420 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19421 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19422 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19424 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19425 "orps\t{%2, %0|%0, %2}"
19426 [(set_attr "type" "sselog")
19427 (set_attr "mode" "V4SF")])
19429 (define_insn "*sse_iorsf3"
19430 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19431 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19432 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19434 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19435 "orps\t{%2, %0|%0, %2}"
19436 [(set_attr "type" "sselog")
19437 (set_attr "mode" "V4SF")])
19439 (define_expand "sse_xorv4sf3"
19440 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19441 (xor:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19442 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19444 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19447 (define_insn "*sse_xorv4sf3"
19448 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19449 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19450 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19452 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19453 "xorps\t{%2, %0|%0, %2}"
19454 [(set_attr "type" "sselog")
19455 (set_attr "mode" "V4SF")])
19457 (define_insn "*sse_xorsf3"
19458 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19459 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19460 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19462 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19463 "xorps\t{%2, %0|%0, %2}"
19464 [(set_attr "type" "sselog")
19465 (set_attr "mode" "V4SF")])
19467 ;; SSE2 double precision floating point logical operation
19469 (define_expand "sse2_andv2df3"
19470 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19471 (and:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
19472 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19476 (define_insn "*sse2_andv2df3"
19477 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19478 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19479 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19481 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19482 "andpd\t{%2, %0|%0, %2}"
19483 [(set_attr "type" "sselog")
19484 (set_attr "mode" "V2DF")])
19486 (define_insn "*sse2_andv2df3"
19487 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19488 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19489 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19491 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19492 "andpd\t{%2, %0|%0, %2}"
19493 [(set_attr "type" "sselog")
19494 (set_attr "mode" "V2DF")])
19496 (define_expand "sse2_nandv2df3"
19497 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19498 (and:TI (not:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0))
19499 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19503 (define_insn "*sse2_nandv2df3"
19504 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19505 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19506 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19508 "andnpd\t{%2, %0|%0, %2}"
19509 [(set_attr "type" "sselog")
19510 (set_attr "mode" "V2DF")])
19512 (define_insn "*sse_nandti3_df"
19513 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
19514 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19515 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
19517 "andnpd\t{%2, %0|%0, %2}"
19518 [(set_attr "type" "sselog")
19519 (set_attr "mode" "V2DF")])
19521 (define_expand "sse2_iorv2df3"
19522 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19523 (ior:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
19524 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19528 (define_insn "*sse2_iorv2df3"
19529 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19530 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19531 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19533 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19534 "orpd\t{%2, %0|%0, %2}"
19535 [(set_attr "type" "sselog")
19536 (set_attr "mode" "V2DF")])
19538 (define_insn "*sse2_iordf3"
19539 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19540 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19541 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19543 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19544 "orpd\t{%2, %0|%0, %2}"
19545 [(set_attr "type" "sselog")
19546 (set_attr "mode" "V2DF")])
19548 (define_expand "sse2_xorv2df3"
19549 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19550 (xor:TI (subreg:TI (match_operand:V2DF 1 "nonimmediate_operand" "") 0)
19551 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19555 (define_insn "*sse2_xorv2df3"
19556 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19557 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19558 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19560 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19561 "xorpd\t{%2, %0|%0, %2}"
19562 [(set_attr "type" "sselog")
19563 (set_attr "mode" "V2DF")])
19565 (define_insn "*sse2_xordf3"
19566 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19567 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19568 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19570 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19571 "xorpd\t{%2, %0|%0, %2}"
19572 [(set_attr "type" "sselog")
19573 (set_attr "mode" "V2DF")])
19575 ;; SSE2 integral logicals. These patterns must always come after floating
19576 ;; point ones since we don't want compiler to use integer opcodes on floating
19577 ;; point SSE values to avoid matching of subregs in the match_operand.
19578 (define_insn "*sse2_andti3"
19579 [(set (match_operand:TI 0 "register_operand" "=x")
19580 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19581 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19583 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19584 "pand\t{%2, %0|%0, %2}"
19585 [(set_attr "type" "sselog")
19586 (set_attr "mode" "TI")])
19588 (define_insn "sse2_andv2di3"
19589 [(set (match_operand:V2DI 0 "register_operand" "=x")
19590 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
19591 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19593 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19594 "pand\t{%2, %0|%0, %2}"
19595 [(set_attr "type" "sselog")
19596 (set_attr "mode" "TI")])
19598 (define_insn "*sse2_nandti3"
19599 [(set (match_operand:TI 0 "register_operand" "=x")
19600 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19601 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19603 "pandn\t{%2, %0|%0, %2}"
19604 [(set_attr "type" "sselog")
19605 (set_attr "mode" "TI")])
19607 (define_insn "sse2_nandv2di3"
19608 [(set (match_operand:V2DI 0 "register_operand" "=x")
19609 (and:V2DI (not:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0"))
19610 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19612 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19613 "pandn\t{%2, %0|%0, %2}"
19614 [(set_attr "type" "sselog")
19615 (set_attr "mode" "TI")])
19617 (define_insn "*sse2_iorti3"
19618 [(set (match_operand:TI 0 "register_operand" "=x")
19619 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19620 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19622 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19623 "por\t{%2, %0|%0, %2}"
19624 [(set_attr "type" "sselog")
19625 (set_attr "mode" "TI")])
19627 (define_insn "sse2_iorv2di3"
19628 [(set (match_operand:V2DI 0 "register_operand" "=x")
19629 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
19630 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19632 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19633 "por\t{%2, %0|%0, %2}"
19634 [(set_attr "type" "sselog")
19635 (set_attr "mode" "TI")])
19637 (define_insn "*sse2_xorti3"
19638 [(set (match_operand:TI 0 "register_operand" "=x")
19639 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19640 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19642 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19643 "pxor\t{%2, %0|%0, %2}"
19644 [(set_attr "type" "sselog")
19645 (set_attr "mode" "TI")])
19647 (define_insn "sse2_xorv2di3"
19648 [(set (match_operand:V2DI 0 "register_operand" "=x")
19649 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
19650 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19652 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19653 "pxor\t{%2, %0|%0, %2}"
19654 [(set_attr "type" "sselog")
19655 (set_attr "mode" "TI")])
19657 ;; Use xor, but don't show input operands so they aren't live before
19659 (define_insn "sse_clrv4sf"
19660 [(set (match_operand:V4SF 0 "register_operand" "=x")
19661 (match_operand:V4SF 1 "const0_operand" "X"))]
19664 if (get_attr_mode (insn) == MODE_TI)
19665 return "pxor\t{%0, %0|%0, %0}";
19667 return "xorps\t{%0, %0|%0, %0}";
19669 [(set_attr "type" "sselog")
19670 (set_attr "memory" "none")
19673 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
19675 (ne (symbol_ref "TARGET_SSE2")
19677 (eq (symbol_ref "optimize_size")
19679 (const_string "TI")
19680 (const_string "V4SF")))])
19682 ;; Use xor, but don't show input operands so they aren't live before
19684 (define_insn "sse_clrv2df"
19685 [(set (match_operand:V2DF 0 "register_operand" "=x")
19686 (unspec:V2DF [(const_int 0)] UNSPEC_NOP))]
19688 "xorpd\t{%0, %0|%0, %0}"
19689 [(set_attr "type" "sselog")
19690 (set_attr "memory" "none")
19691 (set_attr "mode" "V4SF")])
19693 ;; SSE mask-generating compares
19695 (define_insn "maskcmpv4sf3"
19696 [(set (match_operand:V4SI 0 "register_operand" "=x")
19697 (match_operator:V4SI 3 "sse_comparison_operator"
19698 [(match_operand:V4SF 1 "register_operand" "0")
19699 (match_operand:V4SF 2 "register_operand" "x")]))]
19701 "cmp%D3ps\t{%2, %0|%0, %2}"
19702 [(set_attr "type" "ssecmp")
19703 (set_attr "mode" "V4SF")])
19705 (define_insn "maskncmpv4sf3"
19706 [(set (match_operand:V4SI 0 "register_operand" "=x")
19708 (match_operator:V4SI 3 "sse_comparison_operator"
19709 [(match_operand:V4SF 1 "register_operand" "0")
19710 (match_operand:V4SF 2 "register_operand" "x")])))]
19713 if (GET_CODE (operands[3]) == UNORDERED)
19714 return "cmpordps\t{%2, %0|%0, %2}";
19716 return "cmpn%D3ps\t{%2, %0|%0, %2}";
19718 [(set_attr "type" "ssecmp")
19719 (set_attr "mode" "V4SF")])
19721 (define_insn "vmmaskcmpv4sf3"
19722 [(set (match_operand:V4SI 0 "register_operand" "=x")
19724 (match_operator:V4SI 3 "sse_comparison_operator"
19725 [(match_operand:V4SF 1 "register_operand" "0")
19726 (match_operand:V4SF 2 "register_operand" "x")])
19730 "cmp%D3ss\t{%2, %0|%0, %2}"
19731 [(set_attr "type" "ssecmp")
19732 (set_attr "mode" "SF")])
19734 (define_insn "vmmaskncmpv4sf3"
19735 [(set (match_operand:V4SI 0 "register_operand" "=x")
19738 (match_operator:V4SI 3 "sse_comparison_operator"
19739 [(match_operand:V4SF 1 "register_operand" "0")
19740 (match_operand:V4SF 2 "register_operand" "x")]))
19741 (subreg:V4SI (match_dup 1) 0)
19745 if (GET_CODE (operands[3]) == UNORDERED)
19746 return "cmpordss\t{%2, %0|%0, %2}";
19748 return "cmpn%D3ss\t{%2, %0|%0, %2}";
19750 [(set_attr "type" "ssecmp")
19751 (set_attr "mode" "SF")])
19753 (define_insn "sse_comi"
19754 [(set (reg:CCFP 17)
19755 (compare:CCFP (vec_select:SF
19756 (match_operand:V4SF 0 "register_operand" "x")
19757 (parallel [(const_int 0)]))
19759 (match_operand:V4SF 1 "register_operand" "x")
19760 (parallel [(const_int 0)]))))]
19762 "comiss\t{%1, %0|%0, %1}"
19763 [(set_attr "type" "ssecomi")
19764 (set_attr "mode" "SF")])
19766 (define_insn "sse_ucomi"
19767 [(set (reg:CCFPU 17)
19768 (compare:CCFPU (vec_select:SF
19769 (match_operand:V4SF 0 "register_operand" "x")
19770 (parallel [(const_int 0)]))
19772 (match_operand:V4SF 1 "register_operand" "x")
19773 (parallel [(const_int 0)]))))]
19775 "ucomiss\t{%1, %0|%0, %1}"
19776 [(set_attr "type" "ssecomi")
19777 (set_attr "mode" "SF")])
19782 (define_insn "sse_unpckhps"
19783 [(set (match_operand:V4SF 0 "register_operand" "=x")
19785 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
19786 (parallel [(const_int 2)
19790 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19791 (parallel [(const_int 0)
19797 "unpckhps\t{%2, %0|%0, %2}"
19798 [(set_attr "type" "ssecvt")
19799 (set_attr "mode" "V4SF")])
19801 (define_insn "sse_unpcklps"
19802 [(set (match_operand:V4SF 0 "register_operand" "=x")
19804 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
19805 (parallel [(const_int 0)
19809 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19810 (parallel [(const_int 2)
19816 "unpcklps\t{%2, %0|%0, %2}"
19817 [(set_attr "type" "ssecvt")
19818 (set_attr "mode" "V4SF")])
19823 (define_insn "smaxv4sf3"
19824 [(set (match_operand:V4SF 0 "register_operand" "=x")
19825 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
19826 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19828 "maxps\t{%2, %0|%0, %2}"
19829 [(set_attr "type" "sse")
19830 (set_attr "mode" "V4SF")])
19832 (define_insn "vmsmaxv4sf3"
19833 [(set (match_operand:V4SF 0 "register_operand" "=x")
19835 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
19836 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19840 "maxss\t{%2, %0|%0, %2}"
19841 [(set_attr "type" "sse")
19842 (set_attr "mode" "SF")])
19844 (define_insn "sminv4sf3"
19845 [(set (match_operand:V4SF 0 "register_operand" "=x")
19846 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
19847 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19849 "minps\t{%2, %0|%0, %2}"
19850 [(set_attr "type" "sse")
19851 (set_attr "mode" "V4SF")])
19853 (define_insn "vmsminv4sf3"
19854 [(set (match_operand:V4SF 0 "register_operand" "=x")
19856 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
19857 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19861 "minss\t{%2, %0|%0, %2}"
19862 [(set_attr "type" "sse")
19863 (set_attr "mode" "SF")])
19865 ;; SSE <-> integer/MMX conversions
19867 (define_insn "cvtpi2ps"
19868 [(set (match_operand:V4SF 0 "register_operand" "=x")
19870 (match_operand:V4SF 1 "register_operand" "0")
19871 (vec_duplicate:V4SF
19872 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
19875 "cvtpi2ps\t{%2, %0|%0, %2}"
19876 [(set_attr "type" "ssecvt")
19877 (set_attr "mode" "V4SF")])
19879 (define_insn "cvtps2pi"
19880 [(set (match_operand:V2SI 0 "register_operand" "=y")
19882 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
19883 (parallel [(const_int 0) (const_int 1)])))]
19885 "cvtps2pi\t{%1, %0|%0, %1}"
19886 [(set_attr "type" "ssecvt")
19887 (set_attr "mode" "V4SF")])
19889 (define_insn "cvttps2pi"
19890 [(set (match_operand:V2SI 0 "register_operand" "=y")
19892 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19894 (parallel [(const_int 0) (const_int 1)])))]
19896 "cvttps2pi\t{%1, %0|%0, %1}"
19897 [(set_attr "type" "ssecvt")
19898 (set_attr "mode" "SF")])
19900 (define_insn "cvtsi2ss"
19901 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
19903 (match_operand:V4SF 1 "register_operand" "0,0")
19904 (vec_duplicate:V4SF
19905 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
19908 "cvtsi2ss\t{%2, %0|%0, %2}"
19909 [(set_attr "type" "sseicvt")
19910 (set_attr "athlon_decode" "vector,double")
19911 (set_attr "mode" "SF")])
19913 (define_insn "cvtsi2ssq"
19914 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
19916 (match_operand:V4SF 1 "register_operand" "0,0")
19917 (vec_duplicate:V4SF
19918 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
19920 "TARGET_SSE && TARGET_64BIT"
19921 "cvtsi2ssq\t{%2, %0|%0, %2}"
19922 [(set_attr "type" "sseicvt")
19923 (set_attr "athlon_decode" "vector,double")
19924 (set_attr "mode" "SF")])
19926 (define_insn "cvtss2si"
19927 [(set (match_operand:SI 0 "register_operand" "=r,r")
19929 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
19930 (parallel [(const_int 0)])))]
19932 "cvtss2si\t{%1, %0|%0, %1}"
19933 [(set_attr "type" "sseicvt")
19934 (set_attr "athlon_decode" "double,vector")
19935 (set_attr "mode" "SF")])
19937 (define_insn "cvttss2si"
19938 [(set (match_operand:SI 0 "register_operand" "=r,r")
19940 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
19942 (parallel [(const_int 0)])))]
19944 "cvttss2si\t{%1, %0|%0, %1}"
19945 [(set_attr "type" "sseicvt")
19946 (set_attr "mode" "SF")
19947 (set_attr "athlon_decode" "double,vector")])
19954 (define_insn "addv8qi3"
19955 [(set (match_operand:V8QI 0 "register_operand" "=y")
19956 (plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19957 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19959 "paddb\t{%2, %0|%0, %2}"
19960 [(set_attr "type" "mmxadd")
19961 (set_attr "mode" "DI")])
19963 (define_insn "addv4hi3"
19964 [(set (match_operand:V4HI 0 "register_operand" "=y")
19965 (plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19966 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19968 "paddw\t{%2, %0|%0, %2}"
19969 [(set_attr "type" "mmxadd")
19970 (set_attr "mode" "DI")])
19972 (define_insn "addv2si3"
19973 [(set (match_operand:V2SI 0 "register_operand" "=y")
19974 (plus:V2SI (match_operand:V2SI 1 "register_operand" "0")
19975 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
19977 "paddd\t{%2, %0|%0, %2}"
19978 [(set_attr "type" "mmxadd")
19979 (set_attr "mode" "DI")])
19981 (define_insn "ssaddv8qi3"
19982 [(set (match_operand:V8QI 0 "register_operand" "=y")
19983 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19984 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19986 "paddsb\t{%2, %0|%0, %2}"
19987 [(set_attr "type" "mmxadd")
19988 (set_attr "mode" "DI")])
19990 (define_insn "ssaddv4hi3"
19991 [(set (match_operand:V4HI 0 "register_operand" "=y")
19992 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19993 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19995 "paddsw\t{%2, %0|%0, %2}"
19996 [(set_attr "type" "mmxadd")
19997 (set_attr "mode" "DI")])
19999 (define_insn "usaddv8qi3"
20000 [(set (match_operand:V8QI 0 "register_operand" "=y")
20001 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20002 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20004 "paddusb\t{%2, %0|%0, %2}"
20005 [(set_attr "type" "mmxadd")
20006 (set_attr "mode" "DI")])
20008 (define_insn "usaddv4hi3"
20009 [(set (match_operand:V4HI 0 "register_operand" "=y")
20010 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20011 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20013 "paddusw\t{%2, %0|%0, %2}"
20014 [(set_attr "type" "mmxadd")
20015 (set_attr "mode" "DI")])
20017 (define_insn "subv8qi3"
20018 [(set (match_operand:V8QI 0 "register_operand" "=y")
20019 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20020 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20022 "psubb\t{%2, %0|%0, %2}"
20023 [(set_attr "type" "mmxadd")
20024 (set_attr "mode" "DI")])
20026 (define_insn "subv4hi3"
20027 [(set (match_operand:V4HI 0 "register_operand" "=y")
20028 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20029 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20031 "psubw\t{%2, %0|%0, %2}"
20032 [(set_attr "type" "mmxadd")
20033 (set_attr "mode" "DI")])
20035 (define_insn "subv2si3"
20036 [(set (match_operand:V2SI 0 "register_operand" "=y")
20037 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
20038 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20040 "psubd\t{%2, %0|%0, %2}"
20041 [(set_attr "type" "mmxadd")
20042 (set_attr "mode" "DI")])
20044 (define_insn "sssubv8qi3"
20045 [(set (match_operand:V8QI 0 "register_operand" "=y")
20046 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20047 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20049 "psubsb\t{%2, %0|%0, %2}"
20050 [(set_attr "type" "mmxadd")
20051 (set_attr "mode" "DI")])
20053 (define_insn "sssubv4hi3"
20054 [(set (match_operand:V4HI 0 "register_operand" "=y")
20055 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20056 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20058 "psubsw\t{%2, %0|%0, %2}"
20059 [(set_attr "type" "mmxadd")
20060 (set_attr "mode" "DI")])
20062 (define_insn "ussubv8qi3"
20063 [(set (match_operand:V8QI 0 "register_operand" "=y")
20064 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20065 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20067 "psubusb\t{%2, %0|%0, %2}"
20068 [(set_attr "type" "mmxadd")
20069 (set_attr "mode" "DI")])
20071 (define_insn "ussubv4hi3"
20072 [(set (match_operand:V4HI 0 "register_operand" "=y")
20073 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20074 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20076 "psubusw\t{%2, %0|%0, %2}"
20077 [(set_attr "type" "mmxadd")
20078 (set_attr "mode" "DI")])
20080 (define_insn "mulv4hi3"
20081 [(set (match_operand:V4HI 0 "register_operand" "=y")
20082 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
20083 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20085 "pmullw\t{%2, %0|%0, %2}"
20086 [(set_attr "type" "mmxmul")
20087 (set_attr "mode" "DI")])
20089 (define_insn "smulv4hi3_highpart"
20090 [(set (match_operand:V4HI 0 "register_operand" "=y")
20093 (mult:V4SI (sign_extend:V4SI
20094 (match_operand:V4HI 1 "register_operand" "0"))
20096 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20099 "pmulhw\t{%2, %0|%0, %2}"
20100 [(set_attr "type" "mmxmul")
20101 (set_attr "mode" "DI")])
20103 (define_insn "umulv4hi3_highpart"
20104 [(set (match_operand:V4HI 0 "register_operand" "=y")
20107 (mult:V4SI (zero_extend:V4SI
20108 (match_operand:V4HI 1 "register_operand" "0"))
20110 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20112 "TARGET_SSE || TARGET_3DNOW_A"
20113 "pmulhuw\t{%2, %0|%0, %2}"
20114 [(set_attr "type" "mmxmul")
20115 (set_attr "mode" "DI")])
20117 (define_insn "mmx_pmaddwd"
20118 [(set (match_operand:V2SI 0 "register_operand" "=y")
20122 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
20123 (parallel [(const_int 0) (const_int 2)])))
20125 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
20126 (parallel [(const_int 0) (const_int 2)]))))
20128 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
20129 (parallel [(const_int 1)
20131 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
20132 (parallel [(const_int 1)
20133 (const_int 3)]))))))]
20135 "pmaddwd\t{%2, %0|%0, %2}"
20136 [(set_attr "type" "mmxmul")
20137 (set_attr "mode" "DI")])
20140 ;; MMX logical operations
20141 ;; Note we don't want to declare these as regular iordi3 insns to prevent
20142 ;; normal code that also wants to use the FPU from getting broken.
20143 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
20144 (define_insn "mmx_iordi3"
20145 [(set (match_operand:DI 0 "register_operand" "=y")
20147 [(ior:DI (match_operand:DI 1 "register_operand" "0")
20148 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20151 "por\t{%2, %0|%0, %2}"
20152 [(set_attr "type" "mmxadd")
20153 (set_attr "mode" "DI")])
20155 (define_insn "mmx_xordi3"
20156 [(set (match_operand:DI 0 "register_operand" "=y")
20158 [(xor:DI (match_operand:DI 1 "register_operand" "0")
20159 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20162 "pxor\t{%2, %0|%0, %2}"
20163 [(set_attr "type" "mmxadd")
20164 (set_attr "mode" "DI")
20165 (set_attr "memory" "none")])
20167 ;; Same as pxor, but don't show input operands so that we don't think
20169 (define_insn "mmx_clrdi"
20170 [(set (match_operand:DI 0 "register_operand" "=y")
20171 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
20173 "pxor\t{%0, %0|%0, %0}"
20174 [(set_attr "type" "mmxadd")
20175 (set_attr "mode" "DI")
20176 (set_attr "memory" "none")])
20178 (define_insn "mmx_anddi3"
20179 [(set (match_operand:DI 0 "register_operand" "=y")
20181 [(and:DI (match_operand:DI 1 "register_operand" "0")
20182 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20185 "pand\t{%2, %0|%0, %2}"
20186 [(set_attr "type" "mmxadd")
20187 (set_attr "mode" "DI")])
20189 (define_insn "mmx_nanddi3"
20190 [(set (match_operand:DI 0 "register_operand" "=y")
20192 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
20193 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20196 "pandn\t{%2, %0|%0, %2}"
20197 [(set_attr "type" "mmxadd")
20198 (set_attr "mode" "DI")])
20201 ;; MMX unsigned averages/sum of absolute differences
20203 (define_insn "mmx_uavgv8qi3"
20204 [(set (match_operand:V8QI 0 "register_operand" "=y")
20206 (plus:V8QI (plus:V8QI
20207 (match_operand:V8QI 1 "register_operand" "0")
20208 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
20209 (const_vector:V8QI [(const_int 1)
20218 "TARGET_SSE || TARGET_3DNOW_A"
20219 "pavgb\t{%2, %0|%0, %2}"
20220 [(set_attr "type" "mmxshft")
20221 (set_attr "mode" "DI")])
20223 (define_insn "mmx_uavgv4hi3"
20224 [(set (match_operand:V4HI 0 "register_operand" "=y")
20226 (plus:V4HI (plus:V4HI
20227 (match_operand:V4HI 1 "register_operand" "0")
20228 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
20229 (const_vector:V4HI [(const_int 1)
20234 "TARGET_SSE || TARGET_3DNOW_A"
20235 "pavgw\t{%2, %0|%0, %2}"
20236 [(set_attr "type" "mmxshft")
20237 (set_attr "mode" "DI")])
20239 (define_insn "mmx_psadbw"
20240 [(set (match_operand:DI 0 "register_operand" "=y")
20241 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
20242 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
20244 "TARGET_SSE || TARGET_3DNOW_A"
20245 "psadbw\t{%2, %0|%0, %2}"
20246 [(set_attr "type" "mmxshft")
20247 (set_attr "mode" "DI")])
20250 ;; MMX insert/extract/shuffle
20252 (define_insn "mmx_pinsrw"
20253 [(set (match_operand:V4HI 0 "register_operand" "=y")
20254 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
20255 (vec_duplicate:V4HI
20256 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
20257 (match_operand:SI 3 "immediate_operand" "i")))]
20258 "TARGET_SSE || TARGET_3DNOW_A"
20259 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
20260 [(set_attr "type" "mmxcvt")
20261 (set_attr "mode" "DI")])
20263 (define_insn "mmx_pextrw"
20264 [(set (match_operand:SI 0 "register_operand" "=r")
20265 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
20267 [(match_operand:SI 2 "immediate_operand" "i")]))))]
20268 "TARGET_SSE || TARGET_3DNOW_A"
20269 "pextrw\t{%2, %1, %0|%0, %1, %2}"
20270 [(set_attr "type" "mmxcvt")
20271 (set_attr "mode" "DI")])
20273 (define_insn "mmx_pshufw"
20274 [(set (match_operand:V4HI 0 "register_operand" "=y")
20275 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
20276 (match_operand:SI 2 "immediate_operand" "i")]
20278 "TARGET_SSE || TARGET_3DNOW_A"
20279 "pshufw\t{%2, %1, %0|%0, %1, %2}"
20280 [(set_attr "type" "mmxcvt")
20281 (set_attr "mode" "DI")])
20284 ;; MMX mask-generating comparisons
20286 (define_insn "eqv8qi3"
20287 [(set (match_operand:V8QI 0 "register_operand" "=y")
20288 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
20289 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20291 "pcmpeqb\t{%2, %0|%0, %2}"
20292 [(set_attr "type" "mmxcmp")
20293 (set_attr "mode" "DI")])
20295 (define_insn "eqv4hi3"
20296 [(set (match_operand:V4HI 0 "register_operand" "=y")
20297 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
20298 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20300 "pcmpeqw\t{%2, %0|%0, %2}"
20301 [(set_attr "type" "mmxcmp")
20302 (set_attr "mode" "DI")])
20304 (define_insn "eqv2si3"
20305 [(set (match_operand:V2SI 0 "register_operand" "=y")
20306 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
20307 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20309 "pcmpeqd\t{%2, %0|%0, %2}"
20310 [(set_attr "type" "mmxcmp")
20311 (set_attr "mode" "DI")])
20313 (define_insn "gtv8qi3"
20314 [(set (match_operand:V8QI 0 "register_operand" "=y")
20315 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
20316 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20318 "pcmpgtb\t{%2, %0|%0, %2}"
20319 [(set_attr "type" "mmxcmp")
20320 (set_attr "mode" "DI")])
20322 (define_insn "gtv4hi3"
20323 [(set (match_operand:V4HI 0 "register_operand" "=y")
20324 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20325 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20327 "pcmpgtw\t{%2, %0|%0, %2}"
20328 [(set_attr "type" "mmxcmp")
20329 (set_attr "mode" "DI")])
20331 (define_insn "gtv2si3"
20332 [(set (match_operand:V2SI 0 "register_operand" "=y")
20333 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20334 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20336 "pcmpgtd\t{%2, %0|%0, %2}"
20337 [(set_attr "type" "mmxcmp")
20338 (set_attr "mode" "DI")])
20341 ;; MMX max/min insns
20343 (define_insn "umaxv8qi3"
20344 [(set (match_operand:V8QI 0 "register_operand" "=y")
20345 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
20346 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20347 "TARGET_SSE || TARGET_3DNOW_A"
20348 "pmaxub\t{%2, %0|%0, %2}"
20349 [(set_attr "type" "mmxadd")
20350 (set_attr "mode" "DI")])
20352 (define_insn "smaxv4hi3"
20353 [(set (match_operand:V4HI 0 "register_operand" "=y")
20354 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
20355 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20356 "TARGET_SSE || TARGET_3DNOW_A"
20357 "pmaxsw\t{%2, %0|%0, %2}"
20358 [(set_attr "type" "mmxadd")
20359 (set_attr "mode" "DI")])
20361 (define_insn "uminv8qi3"
20362 [(set (match_operand:V8QI 0 "register_operand" "=y")
20363 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
20364 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20365 "TARGET_SSE || TARGET_3DNOW_A"
20366 "pminub\t{%2, %0|%0, %2}"
20367 [(set_attr "type" "mmxadd")
20368 (set_attr "mode" "DI")])
20370 (define_insn "sminv4hi3"
20371 [(set (match_operand:V4HI 0 "register_operand" "=y")
20372 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
20373 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20374 "TARGET_SSE || TARGET_3DNOW_A"
20375 "pminsw\t{%2, %0|%0, %2}"
20376 [(set_attr "type" "mmxadd")
20377 (set_attr "mode" "DI")])
20382 (define_insn "ashrv4hi3"
20383 [(set (match_operand:V4HI 0 "register_operand" "=y")
20384 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20385 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20387 "psraw\t{%2, %0|%0, %2}"
20388 [(set_attr "type" "mmxshft")
20389 (set_attr "mode" "DI")])
20391 (define_insn "ashrv2si3"
20392 [(set (match_operand:V2SI 0 "register_operand" "=y")
20393 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20394 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20396 "psrad\t{%2, %0|%0, %2}"
20397 [(set_attr "type" "mmxshft")
20398 (set_attr "mode" "DI")])
20400 (define_insn "lshrv4hi3"
20401 [(set (match_operand:V4HI 0 "register_operand" "=y")
20402 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20403 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20405 "psrlw\t{%2, %0|%0, %2}"
20406 [(set_attr "type" "mmxshft")
20407 (set_attr "mode" "DI")])
20409 (define_insn "lshrv2si3"
20410 [(set (match_operand:V2SI 0 "register_operand" "=y")
20411 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20412 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20414 "psrld\t{%2, %0|%0, %2}"
20415 [(set_attr "type" "mmxshft")
20416 (set_attr "mode" "DI")])
20418 ;; See logical MMX insns.
20419 (define_insn "mmx_lshrdi3"
20420 [(set (match_operand:DI 0 "register_operand" "=y")
20422 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
20423 (match_operand:DI 2 "nonmemory_operand" "yi"))]
20426 "psrlq\t{%2, %0|%0, %2}"
20427 [(set_attr "type" "mmxshft")
20428 (set_attr "mode" "DI")])
20430 (define_insn "ashlv4hi3"
20431 [(set (match_operand:V4HI 0 "register_operand" "=y")
20432 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
20433 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20435 "psllw\t{%2, %0|%0, %2}"
20436 [(set_attr "type" "mmxshft")
20437 (set_attr "mode" "DI")])
20439 (define_insn "ashlv2si3"
20440 [(set (match_operand:V2SI 0 "register_operand" "=y")
20441 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
20442 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20444 "pslld\t{%2, %0|%0, %2}"
20445 [(set_attr "type" "mmxshft")
20446 (set_attr "mode" "DI")])
20448 ;; See logical MMX insns.
20449 (define_insn "mmx_ashldi3"
20450 [(set (match_operand:DI 0 "register_operand" "=y")
20452 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
20453 (match_operand:DI 2 "nonmemory_operand" "yi"))]
20456 "psllq\t{%2, %0|%0, %2}"
20457 [(set_attr "type" "mmxshft")
20458 (set_attr "mode" "DI")])
20461 ;; MMX pack/unpack insns.
20463 (define_insn "mmx_packsswb"
20464 [(set (match_operand:V8QI 0 "register_operand" "=y")
20466 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
20467 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
20469 "packsswb\t{%2, %0|%0, %2}"
20470 [(set_attr "type" "mmxshft")
20471 (set_attr "mode" "DI")])
20473 (define_insn "mmx_packssdw"
20474 [(set (match_operand:V4HI 0 "register_operand" "=y")
20476 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
20477 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
20479 "packssdw\t{%2, %0|%0, %2}"
20480 [(set_attr "type" "mmxshft")
20481 (set_attr "mode" "DI")])
20483 (define_insn "mmx_packuswb"
20484 [(set (match_operand:V8QI 0 "register_operand" "=y")
20486 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
20487 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
20489 "packuswb\t{%2, %0|%0, %2}"
20490 [(set_attr "type" "mmxshft")
20491 (set_attr "mode" "DI")])
20493 (define_insn "mmx_punpckhbw"
20494 [(set (match_operand:V8QI 0 "register_operand" "=y")
20496 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
20497 (parallel [(const_int 4)
20505 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
20506 (parallel [(const_int 0)
20516 "punpckhbw\t{%2, %0|%0, %2}"
20517 [(set_attr "type" "mmxcvt")
20518 (set_attr "mode" "DI")])
20520 (define_insn "mmx_punpckhwd"
20521 [(set (match_operand:V4HI 0 "register_operand" "=y")
20523 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
20524 (parallel [(const_int 0)
20528 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
20529 (parallel [(const_int 2)
20535 "punpckhwd\t{%2, %0|%0, %2}"
20536 [(set_attr "type" "mmxcvt")
20537 (set_attr "mode" "DI")])
20539 (define_insn "mmx_punpckhdq"
20540 [(set (match_operand:V2SI 0 "register_operand" "=y")
20542 (match_operand:V2SI 1 "register_operand" "0")
20543 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
20544 (parallel [(const_int 1)
20548 "punpckhdq\t{%2, %0|%0, %2}"
20549 [(set_attr "type" "mmxcvt")
20550 (set_attr "mode" "DI")])
20552 (define_insn "mmx_punpcklbw"
20553 [(set (match_operand:V8QI 0 "register_operand" "=y")
20555 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
20556 (parallel [(const_int 0)
20564 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
20565 (parallel [(const_int 4)
20575 "punpcklbw\t{%2, %0|%0, %2}"
20576 [(set_attr "type" "mmxcvt")
20577 (set_attr "mode" "DI")])
20579 (define_insn "mmx_punpcklwd"
20580 [(set (match_operand:V4HI 0 "register_operand" "=y")
20582 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
20583 (parallel [(const_int 2)
20587 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
20588 (parallel [(const_int 0)
20594 "punpcklwd\t{%2, %0|%0, %2}"
20595 [(set_attr "type" "mmxcvt")
20596 (set_attr "mode" "DI")])
20598 (define_insn "mmx_punpckldq"
20599 [(set (match_operand:V2SI 0 "register_operand" "=y")
20601 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
20602 (parallel [(const_int 1)
20604 (match_operand:V2SI 2 "register_operand" "y")
20607 "punpckldq\t{%2, %0|%0, %2}"
20608 [(set_attr "type" "mmxcvt")
20609 (set_attr "mode" "DI")])
20612 ;; Miscellaneous stuff
20614 (define_insn "emms"
20615 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
20616 (clobber (reg:XF 8))
20617 (clobber (reg:XF 9))
20618 (clobber (reg:XF 10))
20619 (clobber (reg:XF 11))
20620 (clobber (reg:XF 12))
20621 (clobber (reg:XF 13))
20622 (clobber (reg:XF 14))
20623 (clobber (reg:XF 15))
20624 (clobber (reg:DI 29))
20625 (clobber (reg:DI 30))
20626 (clobber (reg:DI 31))
20627 (clobber (reg:DI 32))
20628 (clobber (reg:DI 33))
20629 (clobber (reg:DI 34))
20630 (clobber (reg:DI 35))
20631 (clobber (reg:DI 36))]
20634 [(set_attr "type" "mmx")
20635 (set_attr "memory" "unknown")])
20637 (define_insn "ldmxcsr"
20638 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
20642 [(set_attr "type" "sse")
20643 (set_attr "memory" "load")])
20645 (define_insn "stmxcsr"
20646 [(set (match_operand:SI 0 "memory_operand" "=m")
20647 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
20650 [(set_attr "type" "sse")
20651 (set_attr "memory" "store")])
20653 (define_expand "sfence"
20654 [(set (match_dup 0)
20655 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
20656 "TARGET_SSE || TARGET_3DNOW_A"
20658 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
20659 MEM_VOLATILE_P (operands[0]) = 1;
20662 (define_insn "*sfence_insn"
20663 [(set (match_operand:BLK 0 "" "")
20664 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
20665 "TARGET_SSE || TARGET_3DNOW_A"
20667 [(set_attr "type" "sse")
20668 (set_attr "memory" "unknown")])
20670 (define_expand "sse_prologue_save"
20671 [(parallel [(set (match_operand:BLK 0 "" "")
20672 (unspec:BLK [(reg:DI 21)
20679 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
20680 (use (match_operand:DI 1 "register_operand" ""))
20681 (use (match_operand:DI 2 "immediate_operand" ""))
20682 (use (label_ref:DI (match_operand 3 "" "")))])]
20686 (define_insn "*sse_prologue_save_insn"
20687 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
20688 (match_operand:DI 4 "const_int_operand" "n")))
20689 (unspec:BLK [(reg:DI 21)
20696 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
20697 (use (match_operand:DI 1 "register_operand" "r"))
20698 (use (match_operand:DI 2 "const_int_operand" "i"))
20699 (use (label_ref:DI (match_operand 3 "" "X")))]
20701 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
20702 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
20706 operands[0] = gen_rtx_MEM (Pmode,
20707 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
20708 output_asm_insn (\"jmp\\t%A1\", operands);
20709 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
20711 operands[4] = adjust_address (operands[0], DImode, i*16);
20712 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
20713 PUT_MODE (operands[4], TImode);
20714 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
20715 output_asm_insn (\"rex\", operands);
20716 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
20718 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
20719 CODE_LABEL_NUMBER (operands[3]));
20723 [(set_attr "type" "other")
20724 (set_attr "length_immediate" "0")
20725 (set_attr "length_address" "0")
20726 (set_attr "length" "135")
20727 (set_attr "memory" "store")
20728 (set_attr "modrm" "0")
20729 (set_attr "mode" "DI")])
20731 ;; 3Dnow! instructions
20733 (define_insn "addv2sf3"
20734 [(set (match_operand:V2SF 0 "register_operand" "=y")
20735 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
20736 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20738 "pfadd\\t{%2, %0|%0, %2}"
20739 [(set_attr "type" "mmxadd")
20740 (set_attr "mode" "V2SF")])
20742 (define_insn "subv2sf3"
20743 [(set (match_operand:V2SF 0 "register_operand" "=y")
20744 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
20745 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20747 "pfsub\\t{%2, %0|%0, %2}"
20748 [(set_attr "type" "mmxadd")
20749 (set_attr "mode" "V2SF")])
20751 (define_insn "subrv2sf3"
20752 [(set (match_operand:V2SF 0 "register_operand" "=y")
20753 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
20754 (match_operand:V2SF 1 "register_operand" "0")))]
20756 "pfsubr\\t{%2, %0|%0, %2}"
20757 [(set_attr "type" "mmxadd")
20758 (set_attr "mode" "V2SF")])
20760 (define_insn "gtv2sf3"
20761 [(set (match_operand:V2SI 0 "register_operand" "=y")
20762 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
20763 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20765 "pfcmpgt\\t{%2, %0|%0, %2}"
20766 [(set_attr "type" "mmxcmp")
20767 (set_attr "mode" "V2SF")])
20769 (define_insn "gev2sf3"
20770 [(set (match_operand:V2SI 0 "register_operand" "=y")
20771 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
20772 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20774 "pfcmpge\\t{%2, %0|%0, %2}"
20775 [(set_attr "type" "mmxcmp")
20776 (set_attr "mode" "V2SF")])
20778 (define_insn "eqv2sf3"
20779 [(set (match_operand:V2SI 0 "register_operand" "=y")
20780 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
20781 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20783 "pfcmpeq\\t{%2, %0|%0, %2}"
20784 [(set_attr "type" "mmxcmp")
20785 (set_attr "mode" "V2SF")])
20787 (define_insn "pfmaxv2sf3"
20788 [(set (match_operand:V2SF 0 "register_operand" "=y")
20789 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
20790 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20792 "pfmax\\t{%2, %0|%0, %2}"
20793 [(set_attr "type" "mmxadd")
20794 (set_attr "mode" "V2SF")])
20796 (define_insn "pfminv2sf3"
20797 [(set (match_operand:V2SF 0 "register_operand" "=y")
20798 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
20799 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20801 "pfmin\\t{%2, %0|%0, %2}"
20802 [(set_attr "type" "mmxadd")
20803 (set_attr "mode" "V2SF")])
20805 (define_insn "mulv2sf3"
20806 [(set (match_operand:V2SF 0 "register_operand" "=y")
20807 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
20808 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20810 "pfmul\\t{%2, %0|%0, %2}"
20811 [(set_attr "type" "mmxmul")
20812 (set_attr "mode" "V2SF")])
20814 (define_insn "femms"
20815 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
20816 (clobber (reg:XF 8))
20817 (clobber (reg:XF 9))
20818 (clobber (reg:XF 10))
20819 (clobber (reg:XF 11))
20820 (clobber (reg:XF 12))
20821 (clobber (reg:XF 13))
20822 (clobber (reg:XF 14))
20823 (clobber (reg:XF 15))
20824 (clobber (reg:DI 29))
20825 (clobber (reg:DI 30))
20826 (clobber (reg:DI 31))
20827 (clobber (reg:DI 32))
20828 (clobber (reg:DI 33))
20829 (clobber (reg:DI 34))
20830 (clobber (reg:DI 35))
20831 (clobber (reg:DI 36))]
20834 [(set_attr "type" "mmx")
20835 (set_attr "memory" "none")])
20837 (define_insn "pf2id"
20838 [(set (match_operand:V2SI 0 "register_operand" "=y")
20839 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
20841 "pf2id\\t{%1, %0|%0, %1}"
20842 [(set_attr "type" "mmxcvt")
20843 (set_attr "mode" "V2SF")])
20845 (define_insn "pf2iw"
20846 [(set (match_operand:V2SI 0 "register_operand" "=y")
20849 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
20851 "pf2iw\\t{%1, %0|%0, %1}"
20852 [(set_attr "type" "mmxcvt")
20853 (set_attr "mode" "V2SF")])
20855 (define_insn "pfacc"
20856 [(set (match_operand:V2SF 0 "register_operand" "=y")
20859 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
20860 (parallel [(const_int 0)]))
20861 (vec_select:SF (match_dup 1)
20862 (parallel [(const_int 1)])))
20864 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
20865 (parallel [(const_int 0)]))
20866 (vec_select:SF (match_dup 2)
20867 (parallel [(const_int 1)])))))]
20869 "pfacc\\t{%2, %0|%0, %2}"
20870 [(set_attr "type" "mmxadd")
20871 (set_attr "mode" "V2SF")])
20873 (define_insn "pfnacc"
20874 [(set (match_operand:V2SF 0 "register_operand" "=y")
20877 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
20878 (parallel [(const_int 0)]))
20879 (vec_select:SF (match_dup 1)
20880 (parallel [(const_int 1)])))
20882 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
20883 (parallel [(const_int 0)]))
20884 (vec_select:SF (match_dup 2)
20885 (parallel [(const_int 1)])))))]
20887 "pfnacc\\t{%2, %0|%0, %2}"
20888 [(set_attr "type" "mmxadd")
20889 (set_attr "mode" "V2SF")])
20891 (define_insn "pfpnacc"
20892 [(set (match_operand:V2SF 0 "register_operand" "=y")
20895 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
20896 (parallel [(const_int 0)]))
20897 (vec_select:SF (match_dup 1)
20898 (parallel [(const_int 1)])))
20900 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
20901 (parallel [(const_int 0)]))
20902 (vec_select:SF (match_dup 2)
20903 (parallel [(const_int 1)])))))]
20905 "pfpnacc\\t{%2, %0|%0, %2}"
20906 [(set_attr "type" "mmxadd")
20907 (set_attr "mode" "V2SF")])
20909 (define_insn "pi2fw"
20910 [(set (match_operand:V2SF 0 "register_operand" "=y")
20915 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
20916 (parallel [(const_int 0)]))))
20919 (vec_select:SI (match_dup 1)
20920 (parallel [(const_int 1)])))))))]
20922 "pi2fw\\t{%1, %0|%0, %1}"
20923 [(set_attr "type" "mmxcvt")
20924 (set_attr "mode" "V2SF")])
20926 (define_insn "floatv2si2"
20927 [(set (match_operand:V2SF 0 "register_operand" "=y")
20928 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
20930 "pi2fd\\t{%1, %0|%0, %1}"
20931 [(set_attr "type" "mmxcvt")
20932 (set_attr "mode" "V2SF")])
20934 ;; This insn is identical to pavgb in operation, but the opcode is
20935 ;; different. To avoid accidentally matching pavgb, use an unspec.
20937 (define_insn "pavgusb"
20938 [(set (match_operand:V8QI 0 "register_operand" "=y")
20940 [(match_operand:V8QI 1 "register_operand" "0")
20941 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
20944 "pavgusb\\t{%2, %0|%0, %2}"
20945 [(set_attr "type" "mmxshft")
20946 (set_attr "mode" "TI")])
20948 ;; 3DNow reciprocal and sqrt
20950 (define_insn "pfrcpv2sf2"
20951 [(set (match_operand:V2SF 0 "register_operand" "=y")
20952 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
20955 "pfrcp\\t{%1, %0|%0, %1}"
20956 [(set_attr "type" "mmx")
20957 (set_attr "mode" "TI")])
20959 (define_insn "pfrcpit1v2sf3"
20960 [(set (match_operand:V2SF 0 "register_operand" "=y")
20961 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
20962 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
20965 "pfrcpit1\\t{%2, %0|%0, %2}"
20966 [(set_attr "type" "mmx")
20967 (set_attr "mode" "TI")])
20969 (define_insn "pfrcpit2v2sf3"
20970 [(set (match_operand:V2SF 0 "register_operand" "=y")
20971 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
20972 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
20975 "pfrcpit2\\t{%2, %0|%0, %2}"
20976 [(set_attr "type" "mmx")
20977 (set_attr "mode" "TI")])
20979 (define_insn "pfrsqrtv2sf2"
20980 [(set (match_operand:V2SF 0 "register_operand" "=y")
20981 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
20984 "pfrsqrt\\t{%1, %0|%0, %1}"
20985 [(set_attr "type" "mmx")
20986 (set_attr "mode" "TI")])
20988 (define_insn "pfrsqit1v2sf3"
20989 [(set (match_operand:V2SF 0 "register_operand" "=y")
20990 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
20991 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
20994 "pfrsqit1\\t{%2, %0|%0, %2}"
20995 [(set_attr "type" "mmx")
20996 (set_attr "mode" "TI")])
20998 (define_insn "pmulhrwv4hi3"
20999 [(set (match_operand:V4HI 0 "register_operand" "=y")
21005 (match_operand:V4HI 1 "register_operand" "0"))
21007 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
21008 (const_vector:V4SI [(const_int 32768)
21011 (const_int 32768)]))
21014 "pmulhrw\\t{%2, %0|%0, %2}"
21015 [(set_attr "type" "mmxmul")
21016 (set_attr "mode" "TI")])
21018 (define_insn "pswapdv2si2"
21019 [(set (match_operand:V2SI 0 "register_operand" "=y")
21020 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
21021 (parallel [(const_int 1) (const_int 0)])))]
21023 "pswapd\\t{%1, %0|%0, %1}"
21024 [(set_attr "type" "mmxcvt")
21025 (set_attr "mode" "TI")])
21027 (define_insn "pswapdv2sf2"
21028 [(set (match_operand:V2SF 0 "register_operand" "=y")
21029 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
21030 (parallel [(const_int 1) (const_int 0)])))]
21032 "pswapd\\t{%1, %0|%0, %1}"
21033 [(set_attr "type" "mmxcvt")
21034 (set_attr "mode" "TI")])
21036 (define_expand "prefetch"
21037 [(prefetch (match_operand 0 "address_operand" "")
21038 (match_operand:SI 1 "const_int_operand" "")
21039 (match_operand:SI 2 "const_int_operand" ""))]
21040 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
21042 int rw = INTVAL (operands[1]);
21043 int locality = INTVAL (operands[2]);
21045 if (rw != 0 && rw != 1)
21047 if (locality < 0 || locality > 3)
21049 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
21052 /* Use 3dNOW prefetch in case we are asking for write prefetch not
21053 suported by SSE counterpart or the SSE prefetch is not available
21054 (K6 machines). Otherwise use SSE prefetch as it allows specifying
21056 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
21057 operands[2] = GEN_INT (3);
21059 operands[1] = const0_rtx;
21062 (define_insn "*prefetch_sse"
21063 [(prefetch (match_operand:SI 0 "address_operand" "p")
21065 (match_operand:SI 1 "const_int_operand" ""))]
21066 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
21068 static const char * const patterns[4] = {
21069 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21072 int locality = INTVAL (operands[1]);
21073 if (locality < 0 || locality > 3)
21076 return patterns[locality];
21078 [(set_attr "type" "sse")
21079 (set_attr "memory" "none")])
21081 (define_insn "*prefetch_sse_rex"
21082 [(prefetch (match_operand:DI 0 "address_operand" "p")
21084 (match_operand:SI 1 "const_int_operand" ""))]
21085 "TARGET_PREFETCH_SSE && TARGET_64BIT"
21087 static const char * const patterns[4] = {
21088 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21091 int locality = INTVAL (operands[1]);
21092 if (locality < 0 || locality > 3)
21095 return patterns[locality];
21097 [(set_attr "type" "sse")
21098 (set_attr "memory" "none")])
21100 (define_insn "*prefetch_3dnow"
21101 [(prefetch (match_operand:SI 0 "address_operand" "p")
21102 (match_operand:SI 1 "const_int_operand" "n")
21104 "TARGET_3DNOW && !TARGET_64BIT"
21106 if (INTVAL (operands[1]) == 0)
21107 return "prefetch\t%a0";
21109 return "prefetchw\t%a0";
21111 [(set_attr "type" "mmx")
21112 (set_attr "memory" "none")])
21114 (define_insn "*prefetch_3dnow_rex"
21115 [(prefetch (match_operand:DI 0 "address_operand" "p")
21116 (match_operand:SI 1 "const_int_operand" "n")
21118 "TARGET_3DNOW && TARGET_64BIT"
21120 if (INTVAL (operands[1]) == 0)
21121 return "prefetch\t%a0";
21123 return "prefetchw\t%a0";
21125 [(set_attr "type" "mmx")
21126 (set_attr "memory" "none")])
21130 (define_insn "addv2df3"
21131 [(set (match_operand:V2DF 0 "register_operand" "=x")
21132 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21133 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21135 "addpd\t{%2, %0|%0, %2}"
21136 [(set_attr "type" "sseadd")
21137 (set_attr "mode" "V2DF")])
21139 (define_insn "vmaddv2df3"
21140 [(set (match_operand:V2DF 0 "register_operand" "=x")
21141 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21142 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21146 "addsd\t{%2, %0|%0, %2}"
21147 [(set_attr "type" "sseadd")
21148 (set_attr "mode" "DF")])
21150 (define_insn "subv2df3"
21151 [(set (match_operand:V2DF 0 "register_operand" "=x")
21152 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21153 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21155 "subpd\t{%2, %0|%0, %2}"
21156 [(set_attr "type" "sseadd")
21157 (set_attr "mode" "V2DF")])
21159 (define_insn "vmsubv2df3"
21160 [(set (match_operand:V2DF 0 "register_operand" "=x")
21161 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21162 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21166 "subsd\t{%2, %0|%0, %2}"
21167 [(set_attr "type" "sseadd")
21168 (set_attr "mode" "DF")])
21170 (define_insn "mulv2df3"
21171 [(set (match_operand:V2DF 0 "register_operand" "=x")
21172 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
21173 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21175 "mulpd\t{%2, %0|%0, %2}"
21176 [(set_attr "type" "ssemul")
21177 (set_attr "mode" "V2DF")])
21179 (define_insn "vmmulv2df3"
21180 [(set (match_operand:V2DF 0 "register_operand" "=x")
21181 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
21182 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21186 "mulsd\t{%2, %0|%0, %2}"
21187 [(set_attr "type" "ssemul")
21188 (set_attr "mode" "DF")])
21190 (define_insn "divv2df3"
21191 [(set (match_operand:V2DF 0 "register_operand" "=x")
21192 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
21193 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21195 "divpd\t{%2, %0|%0, %2}"
21196 [(set_attr "type" "ssediv")
21197 (set_attr "mode" "V2DF")])
21199 (define_insn "vmdivv2df3"
21200 [(set (match_operand:V2DF 0 "register_operand" "=x")
21201 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
21202 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21206 "divsd\t{%2, %0|%0, %2}"
21207 [(set_attr "type" "ssediv")
21208 (set_attr "mode" "DF")])
21212 (define_insn "smaxv2df3"
21213 [(set (match_operand:V2DF 0 "register_operand" "=x")
21214 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
21215 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21217 "maxpd\t{%2, %0|%0, %2}"
21218 [(set_attr "type" "sseadd")
21219 (set_attr "mode" "V2DF")])
21221 (define_insn "vmsmaxv2df3"
21222 [(set (match_operand:V2DF 0 "register_operand" "=x")
21223 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
21224 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21228 "maxsd\t{%2, %0|%0, %2}"
21229 [(set_attr "type" "sseadd")
21230 (set_attr "mode" "DF")])
21232 (define_insn "sminv2df3"
21233 [(set (match_operand:V2DF 0 "register_operand" "=x")
21234 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
21235 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21237 "minpd\t{%2, %0|%0, %2}"
21238 [(set_attr "type" "sseadd")
21239 (set_attr "mode" "V2DF")])
21241 (define_insn "vmsminv2df3"
21242 [(set (match_operand:V2DF 0 "register_operand" "=x")
21243 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
21244 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21248 "minsd\t{%2, %0|%0, %2}"
21249 [(set_attr "type" "sseadd")
21250 (set_attr "mode" "DF")])
21251 ;; SSE2 square root. There doesn't appear to be an extension for the
21252 ;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
21254 (define_insn "sqrtv2df2"
21255 [(set (match_operand:V2DF 0 "register_operand" "=x")
21256 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
21258 "sqrtpd\t{%1, %0|%0, %1}"
21259 [(set_attr "type" "sse")
21260 (set_attr "mode" "V2DF")])
21262 (define_insn "vmsqrtv2df2"
21263 [(set (match_operand:V2DF 0 "register_operand" "=x")
21264 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
21265 (match_operand:V2DF 2 "register_operand" "0")
21268 "sqrtsd\t{%1, %0|%0, %1}"
21269 [(set_attr "type" "sse")
21270 (set_attr "mode" "SF")])
21272 ;; SSE mask-generating compares
21274 (define_insn "maskcmpv2df3"
21275 [(set (match_operand:V2DI 0 "register_operand" "=x")
21276 (match_operator:V2DI 3 "sse_comparison_operator"
21277 [(match_operand:V2DF 1 "register_operand" "0")
21278 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
21280 "cmp%D3pd\t{%2, %0|%0, %2}"
21281 [(set_attr "type" "ssecmp")
21282 (set_attr "mode" "V2DF")])
21284 (define_insn "maskncmpv2df3"
21285 [(set (match_operand:V2DI 0 "register_operand" "=x")
21287 (match_operator:V2DI 3 "sse_comparison_operator"
21288 [(match_operand:V2DF 1 "register_operand" "0")
21289 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
21292 if (GET_CODE (operands[3]) == UNORDERED)
21293 return "cmpordps\t{%2, %0|%0, %2}";
21295 return "cmpn%D3pd\t{%2, %0|%0, %2}";
21297 [(set_attr "type" "ssecmp")
21298 (set_attr "mode" "V2DF")])
21300 (define_insn "vmmaskcmpv2df3"
21301 [(set (match_operand:V2DI 0 "register_operand" "=x")
21303 (match_operator:V2DI 3 "sse_comparison_operator"
21304 [(match_operand:V2DF 1 "register_operand" "0")
21305 (match_operand:V2DF 2 "nonimmediate_operand" "x")])
21309 "cmp%D3sd\t{%2, %0|%0, %2}"
21310 [(set_attr "type" "ssecmp")
21311 (set_attr "mode" "DF")])
21313 (define_insn "vmmaskncmpv2df3"
21314 [(set (match_operand:V2DI 0 "register_operand" "=x")
21317 (match_operator:V2DI 3 "sse_comparison_operator"
21318 [(match_operand:V2DF 1 "register_operand" "0")
21319 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
21320 (subreg:V2DI (match_dup 1) 0)
21324 if (GET_CODE (operands[3]) == UNORDERED)
21325 return "cmpordsd\t{%2, %0|%0, %2}";
21327 return "cmpn%D3sd\t{%2, %0|%0, %2}";
21329 [(set_attr "type" "ssecmp")
21330 (set_attr "mode" "DF")])
21332 (define_insn "sse2_comi"
21333 [(set (reg:CCFP 17)
21334 (compare:CCFP (vec_select:DF
21335 (match_operand:V2DF 0 "register_operand" "x")
21336 (parallel [(const_int 0)]))
21338 (match_operand:V2DF 1 "register_operand" "x")
21339 (parallel [(const_int 0)]))))]
21341 "comisd\t{%1, %0|%0, %1}"
21342 [(set_attr "type" "ssecomi")
21343 (set_attr "mode" "DF")])
21345 (define_insn "sse2_ucomi"
21346 [(set (reg:CCFPU 17)
21347 (compare:CCFPU (vec_select:DF
21348 (match_operand:V2DF 0 "register_operand" "x")
21349 (parallel [(const_int 0)]))
21351 (match_operand:V2DF 1 "register_operand" "x")
21352 (parallel [(const_int 0)]))))]
21354 "ucomisd\t{%1, %0|%0, %1}"
21355 [(set_attr "type" "ssecomi")
21356 (set_attr "mode" "DF")])
21358 ;; SSE Strange Moves.
21360 (define_insn "sse2_movmskpd"
21361 [(set (match_operand:SI 0 "register_operand" "=r")
21362 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
21365 "movmskpd\t{%1, %0|%0, %1}"
21366 [(set_attr "type" "ssecvt")
21367 (set_attr "mode" "V2DF")])
21369 (define_insn "sse2_pmovmskb"
21370 [(set (match_operand:SI 0 "register_operand" "=r")
21371 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
21374 "pmovmskb\t{%1, %0|%0, %1}"
21375 [(set_attr "type" "ssecvt")
21376 (set_attr "mode" "V2DF")])
21378 (define_insn "sse2_maskmovdqu"
21379 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
21380 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
21381 (match_operand:V16QI 2 "register_operand" "x")]
21384 ;; @@@ check ordering of operands in intel/nonintel syntax
21385 "maskmovdqu\t{%2, %1|%1, %2}"
21386 [(set_attr "type" "ssecvt")
21387 (set_attr "mode" "TI")])
21389 (define_insn "sse2_maskmovdqu_rex64"
21390 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
21391 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
21392 (match_operand:V16QI 2 "register_operand" "x")]
21395 ;; @@@ check ordering of operands in intel/nonintel syntax
21396 "maskmovdqu\t{%2, %1|%1, %2}"
21397 [(set_attr "type" "ssecvt")
21398 (set_attr "mode" "TI")])
21400 (define_insn "sse2_movntv2df"
21401 [(set (match_operand:V2DF 0 "memory_operand" "=m")
21402 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
21405 "movntpd\t{%1, %0|%0, %1}"
21406 [(set_attr "type" "ssecvt")
21407 (set_attr "mode" "V2DF")])
21409 (define_insn "sse2_movntv2di"
21410 [(set (match_operand:V2DI 0 "memory_operand" "=m")
21411 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
21414 "movntdq\t{%1, %0|%0, %1}"
21415 [(set_attr "type" "ssecvt")
21416 (set_attr "mode" "TI")])
21418 (define_insn "sse2_movntsi"
21419 [(set (match_operand:SI 0 "memory_operand" "=m")
21420 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
21423 "movnti\t{%1, %0|%0, %1}"
21424 [(set_attr "type" "ssecvt")
21425 (set_attr "mode" "V2DF")])
21427 ;; SSE <-> integer/MMX conversions
21429 ;; Conversions between SI and SF
21431 (define_insn "cvtdq2ps"
21432 [(set (match_operand:V4SF 0 "register_operand" "=x")
21433 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
21435 "cvtdq2ps\t{%1, %0|%0, %1}"
21436 [(set_attr "type" "ssecvt")
21437 (set_attr "mode" "V2DF")])
21439 (define_insn "cvtps2dq"
21440 [(set (match_operand:V4SI 0 "register_operand" "=x")
21441 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
21443 "cvtps2dq\t{%1, %0|%0, %1}"
21444 [(set_attr "type" "ssecvt")
21445 (set_attr "mode" "TI")])
21447 (define_insn "cvttps2dq"
21448 [(set (match_operand:V4SI 0 "register_operand" "=x")
21449 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
21452 "cvttps2dq\t{%1, %0|%0, %1}"
21453 [(set_attr "type" "ssecvt")
21454 (set_attr "mode" "TI")])
21456 ;; Conversions between SI and DF
21458 (define_insn "cvtdq2pd"
21459 [(set (match_operand:V2DF 0 "register_operand" "=x")
21460 (float:V2DF (vec_select:V2SI
21461 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
21464 (const_int 1)]))))]
21466 "cvtdq2pd\t{%1, %0|%0, %1}"
21467 [(set_attr "type" "ssecvt")
21468 (set_attr "mode" "V2DF")])
21470 (define_insn "cvtpd2dq"
21471 [(set (match_operand:V4SI 0 "register_operand" "=x")
21473 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
21474 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
21476 "cvtpd2dq\t{%1, %0|%0, %1}"
21477 [(set_attr "type" "ssecvt")
21478 (set_attr "mode" "TI")])
21480 (define_insn "cvttpd2dq"
21481 [(set (match_operand:V4SI 0 "register_operand" "=x")
21483 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
21485 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
21487 "cvttpd2dq\t{%1, %0|%0, %1}"
21488 [(set_attr "type" "ssecvt")
21489 (set_attr "mode" "TI")])
21491 (define_insn "cvtpd2pi"
21492 [(set (match_operand:V2SI 0 "register_operand" "=y")
21493 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
21495 "cvtpd2pi\t{%1, %0|%0, %1}"
21496 [(set_attr "type" "ssecvt")
21497 (set_attr "mode" "TI")])
21499 (define_insn "cvttpd2pi"
21500 [(set (match_operand:V2SI 0 "register_operand" "=y")
21501 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
21504 "cvttpd2pi\t{%1, %0|%0, %1}"
21505 [(set_attr "type" "ssecvt")
21506 (set_attr "mode" "TI")])
21508 (define_insn "cvtpi2pd"
21509 [(set (match_operand:V2DF 0 "register_operand" "=x")
21510 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
21512 "cvtpi2pd\t{%1, %0|%0, %1}"
21513 [(set_attr "type" "ssecvt")
21514 (set_attr "mode" "TI")])
21516 ;; Conversions between SI and DF
21518 (define_insn "cvtsd2si"
21519 [(set (match_operand:SI 0 "register_operand" "=r")
21520 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "xm")
21521 (parallel [(const_int 0)]))))]
21523 "cvtsd2si\t{%1, %0|%0, %1}"
21524 [(set_attr "type" "sseicvt")
21525 (set_attr "mode" "SI")])
21527 (define_insn "cvttsd2si"
21528 [(set (match_operand:SI 0 "register_operand" "=r,r")
21529 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
21530 (parallel [(const_int 0)]))] UNSPEC_FIX))]
21532 "cvttsd2si\t{%1, %0|%0, %1}"
21533 [(set_attr "type" "sseicvt")
21534 (set_attr "mode" "SI")
21535 (set_attr "athlon_decode" "double,vector")])
21537 (define_insn "cvtsi2sd"
21538 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
21539 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
21540 (vec_duplicate:V2DF
21542 (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
21545 "cvtsi2sd\t{%2, %0|%0, %2}"
21546 [(set_attr "type" "sseicvt")
21547 (set_attr "mode" "DF")
21548 (set_attr "athlon_decode" "double,direct")])
21550 ;; Conversions between SF and DF
21552 (define_insn "cvtsd2ss"
21553 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
21554 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0,0")
21555 (vec_duplicate:V4SF
21556 (float_truncate:V2SF
21557 (match_operand:V2DF 2 "nonimmediate_operand" "x,xm")))
21560 "cvtsd2ss\t{%2, %0|%0, %2}"
21561 [(set_attr "type" "ssecvt")
21562 (set_attr "athlon_decode" "vector,double")
21563 (set_attr "mode" "SF")])
21565 (define_insn "cvtss2sd"
21566 [(set (match_operand:V2DF 0 "register_operand" "=x")
21567 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
21570 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
21571 (parallel [(const_int 0)
21575 "cvtss2sd\t{%2, %0|%0, %2}"
21576 [(set_attr "type" "ssecvt")
21577 (set_attr "mode" "DF")])
21579 (define_insn "cvtpd2ps"
21580 [(set (match_operand:V4SF 0 "register_operand" "=x")
21583 (subreg:V2SI (float_truncate:V2SF
21584 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
21585 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
21587 "cvtpd2ps\t{%1, %0|%0, %1}"
21588 [(set_attr "type" "ssecvt")
21589 (set_attr "mode" "V4SF")])
21591 (define_insn "cvtps2pd"
21592 [(set (match_operand:V2DF 0 "register_operand" "=x")
21594 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
21595 (parallel [(const_int 0)
21596 (const_int 1)]))))]
21598 "cvtps2pd\t{%1, %0|%0, %1}"
21599 [(set_attr "type" "ssecvt")
21600 (set_attr "mode" "V2DF")])
21602 ;; SSE2 variants of MMX insns
21606 (define_insn "addv16qi3"
21607 [(set (match_operand:V16QI 0 "register_operand" "=x")
21608 (plus:V16QI (match_operand:V16QI 1 "register_operand" "0")
21609 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21611 "paddb\t{%2, %0|%0, %2}"
21612 [(set_attr "type" "sseiadd")
21613 (set_attr "mode" "TI")])
21615 (define_insn "addv8hi3"
21616 [(set (match_operand:V8HI 0 "register_operand" "=x")
21617 (plus:V8HI (match_operand:V8HI 1 "register_operand" "0")
21618 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21620 "paddw\t{%2, %0|%0, %2}"
21621 [(set_attr "type" "sseiadd")
21622 (set_attr "mode" "TI")])
21624 (define_insn "addv4si3"
21625 [(set (match_operand:V4SI 0 "register_operand" "=x")
21626 (plus:V4SI (match_operand:V4SI 1 "register_operand" "0")
21627 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
21629 "paddd\t{%2, %0|%0, %2}"
21630 [(set_attr "type" "sseiadd")
21631 (set_attr "mode" "TI")])
21633 (define_insn "addv2di3"
21634 [(set (match_operand:V2DI 0 "register_operand" "=x")
21635 (plus:V2DI (match_operand:V2DI 1 "register_operand" "0")
21636 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21638 "paddq\t{%2, %0|%0, %2}"
21639 [(set_attr "type" "sseiadd")
21640 (set_attr "mode" "TI")])
21642 (define_insn "ssaddv16qi3"
21643 [(set (match_operand:V16QI 0 "register_operand" "=x")
21644 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "0")
21645 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21647 "paddsb\t{%2, %0|%0, %2}"
21648 [(set_attr "type" "sseiadd")
21649 (set_attr "mode" "TI")])
21651 (define_insn "ssaddv8hi3"
21652 [(set (match_operand:V8HI 0 "register_operand" "=x")
21653 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "0")
21654 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21656 "paddsw\t{%2, %0|%0, %2}"
21657 [(set_attr "type" "sseiadd")
21658 (set_attr "mode" "TI")])
21660 (define_insn "usaddv16qi3"
21661 [(set (match_operand:V16QI 0 "register_operand" "=x")
21662 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "0")
21663 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21665 "paddusb\t{%2, %0|%0, %2}"
21666 [(set_attr "type" "sseiadd")
21667 (set_attr "mode" "TI")])
21669 (define_insn "usaddv8hi3"
21670 [(set (match_operand:V8HI 0 "register_operand" "=x")
21671 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "0")
21672 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21674 "paddusw\t{%2, %0|%0, %2}"
21675 [(set_attr "type" "sseiadd")
21676 (set_attr "mode" "TI")])
21678 (define_insn "subv16qi3"
21679 [(set (match_operand:V16QI 0 "register_operand" "=x")
21680 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
21681 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21683 "psubb\t{%2, %0|%0, %2}"
21684 [(set_attr "type" "sseiadd")
21685 (set_attr "mode" "TI")])
21687 (define_insn "subv8hi3"
21688 [(set (match_operand:V8HI 0 "register_operand" "=x")
21689 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
21690 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21692 "psubw\t{%2, %0|%0, %2}"
21693 [(set_attr "type" "sseiadd")
21694 (set_attr "mode" "TI")])
21696 (define_insn "subv4si3"
21697 [(set (match_operand:V4SI 0 "register_operand" "=x")
21698 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
21699 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
21701 "psubd\t{%2, %0|%0, %2}"
21702 [(set_attr "type" "sseiadd")
21703 (set_attr "mode" "TI")])
21705 (define_insn "subv2di3"
21706 [(set (match_operand:V2DI 0 "register_operand" "=x")
21707 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
21708 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21710 "psubq\t{%2, %0|%0, %2}"
21711 [(set_attr "type" "sseiadd")
21712 (set_attr "mode" "TI")])
21714 (define_insn "sssubv16qi3"
21715 [(set (match_operand:V16QI 0 "register_operand" "=x")
21716 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
21717 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21719 "psubsb\t{%2, %0|%0, %2}"
21720 [(set_attr "type" "sseiadd")
21721 (set_attr "mode" "TI")])
21723 (define_insn "sssubv8hi3"
21724 [(set (match_operand:V8HI 0 "register_operand" "=x")
21725 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
21726 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21728 "psubsw\t{%2, %0|%0, %2}"
21729 [(set_attr "type" "sseiadd")
21730 (set_attr "mode" "TI")])
21732 (define_insn "ussubv16qi3"
21733 [(set (match_operand:V16QI 0 "register_operand" "=x")
21734 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
21735 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21737 "psubusb\t{%2, %0|%0, %2}"
21738 [(set_attr "type" "sseiadd")
21739 (set_attr "mode" "TI")])
21741 (define_insn "ussubv8hi3"
21742 [(set (match_operand:V8HI 0 "register_operand" "=x")
21743 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
21744 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21746 "psubusw\t{%2, %0|%0, %2}"
21747 [(set_attr "type" "sseiadd")
21748 (set_attr "mode" "TI")])
21750 (define_insn "mulv8hi3"
21751 [(set (match_operand:V8HI 0 "register_operand" "=x")
21752 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
21753 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21755 "pmullw\t{%2, %0|%0, %2}"
21756 [(set_attr "type" "sseimul")
21757 (set_attr "mode" "TI")])
21759 (define_insn "smulv8hi3_highpart"
21760 [(set (match_operand:V8HI 0 "register_operand" "=x")
21763 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
21764 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
21767 "pmulhw\t{%2, %0|%0, %2}"
21768 [(set_attr "type" "sseimul")
21769 (set_attr "mode" "TI")])
21771 (define_insn "umulv8hi3_highpart"
21772 [(set (match_operand:V8HI 0 "register_operand" "=x")
21775 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
21776 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
21779 "pmulhuw\t{%2, %0|%0, %2}"
21780 [(set_attr "type" "sseimul")
21781 (set_attr "mode" "TI")])
21783 (define_insn "sse2_umulsidi3"
21784 [(set (match_operand:DI 0 "register_operand" "=y")
21785 (mult:DI (zero_extend:DI (vec_select:SI
21786 (match_operand:V2SI 1 "register_operand" "0")
21787 (parallel [(const_int 0)])))
21788 (zero_extend:DI (vec_select:SI
21789 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
21790 (parallel [(const_int 0)])))))]
21792 "pmuludq\t{%2, %0|%0, %2}"
21793 [(set_attr "type" "sseimul")
21794 (set_attr "mode" "TI")])
21796 (define_insn "sse2_umulv2siv2di3"
21797 [(set (match_operand:V2DI 0 "register_operand" "=x")
21798 (mult:V2DI (zero_extend:V2DI
21800 (match_operand:V4SI 1 "register_operand" "0")
21801 (parallel [(const_int 0) (const_int 2)])))
21804 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
21805 (parallel [(const_int 0) (const_int 2)])))))]
21807 "pmuludq\t{%2, %0|%0, %2}"
21808 [(set_attr "type" "sseimul")
21809 (set_attr "mode" "TI")])
21811 (define_insn "sse2_pmaddwd"
21812 [(set (match_operand:V4SI 0 "register_operand" "=x")
21815 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
21816 (parallel [(const_int 0)
21820 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
21821 (parallel [(const_int 0)
21826 (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
21827 (parallel [(const_int 1)
21831 (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
21832 (parallel [(const_int 1)
21835 (const_int 7)]))))))]
21837 "pmaddwd\t{%2, %0|%0, %2}"
21838 [(set_attr "type" "sseiadd")
21839 (set_attr "mode" "TI")])
21841 ;; Same as pxor, but don't show input operands so that we don't think
21843 (define_insn "sse2_clrti"
21844 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
21847 if (get_attr_mode (insn) == MODE_TI)
21848 return "pxor\t%0, %0";
21850 return "xorps\t%0, %0";
21852 [(set_attr "type" "ssemov")
21853 (set_attr "memory" "none")
21856 (ne (symbol_ref "optimize_size")
21858 (const_string "V4SF")
21859 (const_string "TI")))])
21861 ;; MMX unsigned averages/sum of absolute differences
21863 (define_insn "sse2_uavgv16qi3"
21864 [(set (match_operand:V16QI 0 "register_operand" "=x")
21866 (plus:V16QI (plus:V16QI
21867 (match_operand:V16QI 1 "register_operand" "0")
21868 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
21869 (const_vector:V16QI [(const_int 1) (const_int 1)
21870 (const_int 1) (const_int 1)
21871 (const_int 1) (const_int 1)
21872 (const_int 1) (const_int 1)
21873 (const_int 1) (const_int 1)
21874 (const_int 1) (const_int 1)
21875 (const_int 1) (const_int 1)
21876 (const_int 1) (const_int 1)]))
21879 "pavgb\t{%2, %0|%0, %2}"
21880 [(set_attr "type" "sseiadd")
21881 (set_attr "mode" "TI")])
21883 (define_insn "sse2_uavgv8hi3"
21884 [(set (match_operand:V8HI 0 "register_operand" "=x")
21886 (plus:V8HI (plus:V8HI
21887 (match_operand:V8HI 1 "register_operand" "0")
21888 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
21889 (const_vector:V8HI [(const_int 1) (const_int 1)
21890 (const_int 1) (const_int 1)
21891 (const_int 1) (const_int 1)
21892 (const_int 1) (const_int 1)]))
21895 "pavgw\t{%2, %0|%0, %2}"
21896 [(set_attr "type" "sseiadd")
21897 (set_attr "mode" "TI")])
21899 ;; @@@ this isn't the right representation.
21900 (define_insn "sse2_psadbw"
21901 [(set (match_operand:V2DI 0 "register_operand" "=x")
21902 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
21903 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
21906 "psadbw\t{%2, %0|%0, %2}"
21907 [(set_attr "type" "sseiadd")
21908 (set_attr "mode" "TI")])
21911 ;; MMX insert/extract/shuffle
21913 (define_insn "sse2_pinsrw"
21914 [(set (match_operand:V8HI 0 "register_operand" "=x")
21915 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
21916 (vec_duplicate:V8HI
21917 (match_operand:SI 2 "nonimmediate_operand" "rm"))
21918 (match_operand:SI 3 "immediate_operand" "i")))]
21920 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
21921 [(set_attr "type" "ssecvt")
21922 (set_attr "mode" "TI")])
21924 (define_insn "sse2_pextrw"
21925 [(set (match_operand:SI 0 "register_operand" "=r")
21927 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
21929 [(match_operand:SI 2 "immediate_operand" "i")]))))]
21931 "pextrw\t{%2, %1, %0|%0, %1, %2}"
21932 [(set_attr "type" "ssecvt")
21933 (set_attr "mode" "TI")])
21935 (define_insn "sse2_pshufd"
21936 [(set (match_operand:V4SI 0 "register_operand" "=x")
21937 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
21938 (match_operand:SI 2 "immediate_operand" "i")]
21941 "pshufd\t{%2, %1, %0|%0, %1, %2}"
21942 [(set_attr "type" "ssecvt")
21943 (set_attr "mode" "TI")])
21945 (define_insn "sse2_pshuflw"
21946 [(set (match_operand:V8HI 0 "register_operand" "=x")
21947 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
21948 (match_operand:SI 2 "immediate_operand" "i")]
21951 "pshuflw\t{%2, %1, %0|%0, %1, %2}"
21952 [(set_attr "type" "ssecvt")
21953 (set_attr "mode" "TI")])
21955 (define_insn "sse2_pshufhw"
21956 [(set (match_operand:V8HI 0 "register_operand" "=x")
21957 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
21958 (match_operand:SI 2 "immediate_operand" "i")]
21961 "pshufhw\t{%2, %1, %0|%0, %1, %2}"
21962 [(set_attr "type" "ssecvt")
21963 (set_attr "mode" "TI")])
21965 ;; MMX mask-generating comparisons
21967 (define_insn "eqv16qi3"
21968 [(set (match_operand:V16QI 0 "register_operand" "=x")
21969 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
21970 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21972 "pcmpeqb\t{%2, %0|%0, %2}"
21973 [(set_attr "type" "ssecmp")
21974 (set_attr "mode" "TI")])
21976 (define_insn "eqv8hi3"
21977 [(set (match_operand:V8HI 0 "register_operand" "=x")
21978 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
21979 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21981 "pcmpeqw\t{%2, %0|%0, %2}"
21982 [(set_attr "type" "ssecmp")
21983 (set_attr "mode" "TI")])
21985 (define_insn "eqv4si3"
21986 [(set (match_operand:V4SI 0 "register_operand" "=x")
21987 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
21988 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
21990 "pcmpeqd\t{%2, %0|%0, %2}"
21991 [(set_attr "type" "ssecmp")
21992 (set_attr "mode" "TI")])
21994 (define_insn "gtv16qi3"
21995 [(set (match_operand:V16QI 0 "register_operand" "=x")
21996 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
21997 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21999 "pcmpgtb\t{%2, %0|%0, %2}"
22000 [(set_attr "type" "ssecmp")
22001 (set_attr "mode" "TI")])
22003 (define_insn "gtv8hi3"
22004 [(set (match_operand:V8HI 0 "register_operand" "=x")
22005 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22006 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22008 "pcmpgtw\t{%2, %0|%0, %2}"
22009 [(set_attr "type" "ssecmp")
22010 (set_attr "mode" "TI")])
22012 (define_insn "gtv4si3"
22013 [(set (match_operand:V4SI 0 "register_operand" "=x")
22014 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22015 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22017 "pcmpgtd\t{%2, %0|%0, %2}"
22018 [(set_attr "type" "ssecmp")
22019 (set_attr "mode" "TI")])
22022 ;; MMX max/min insns
22024 (define_insn "umaxv16qi3"
22025 [(set (match_operand:V16QI 0 "register_operand" "=x")
22026 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
22027 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22029 "pmaxub\t{%2, %0|%0, %2}"
22030 [(set_attr "type" "sseiadd")
22031 (set_attr "mode" "TI")])
22033 (define_insn "smaxv8hi3"
22034 [(set (match_operand:V8HI 0 "register_operand" "=x")
22035 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
22036 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22038 "pmaxsw\t{%2, %0|%0, %2}"
22039 [(set_attr "type" "sseiadd")
22040 (set_attr "mode" "TI")])
22042 (define_insn "uminv16qi3"
22043 [(set (match_operand:V16QI 0 "register_operand" "=x")
22044 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
22045 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22047 "pminub\t{%2, %0|%0, %2}"
22048 [(set_attr "type" "sseiadd")
22049 (set_attr "mode" "TI")])
22051 (define_insn "sminv8hi3"
22052 [(set (match_operand:V8HI 0 "register_operand" "=x")
22053 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
22054 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22056 "pminsw\t{%2, %0|%0, %2}"
22057 [(set_attr "type" "sseiadd")
22058 (set_attr "mode" "TI")])
22063 (define_insn "ashrv8hi3"
22064 [(set (match_operand:V8HI 0 "register_operand" "=x")
22065 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22066 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22068 "psraw\t{%2, %0|%0, %2}"
22069 [(set_attr "type" "sseishft")
22070 (set_attr "mode" "TI")])
22072 (define_insn "ashrv4si3"
22073 [(set (match_operand:V4SI 0 "register_operand" "=x")
22074 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22075 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22077 "psrad\t{%2, %0|%0, %2}"
22078 [(set_attr "type" "sseishft")
22079 (set_attr "mode" "TI")])
22081 (define_insn "lshrv8hi3"
22082 [(set (match_operand:V8HI 0 "register_operand" "=x")
22083 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22084 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22086 "psrlw\t{%2, %0|%0, %2}"
22087 [(set_attr "type" "sseishft")
22088 (set_attr "mode" "TI")])
22090 (define_insn "lshrv4si3"
22091 [(set (match_operand:V4SI 0 "register_operand" "=x")
22092 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22093 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22095 "psrld\t{%2, %0|%0, %2}"
22096 [(set_attr "type" "sseishft")
22097 (set_attr "mode" "TI")])
22099 (define_insn "lshrv2di3"
22100 [(set (match_operand:V2DI 0 "register_operand" "=x")
22101 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
22102 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22104 "psrlq\t{%2, %0|%0, %2}"
22105 [(set_attr "type" "sseishft")
22106 (set_attr "mode" "TI")])
22108 (define_insn "ashlv8hi3"
22109 [(set (match_operand:V8HI 0 "register_operand" "=x")
22110 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
22111 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22113 "psllw\t{%2, %0|%0, %2}"
22114 [(set_attr "type" "sseishft")
22115 (set_attr "mode" "TI")])
22117 (define_insn "ashlv4si3"
22118 [(set (match_operand:V4SI 0 "register_operand" "=x")
22119 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
22120 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22122 "pslld\t{%2, %0|%0, %2}"
22123 [(set_attr "type" "sseishft")
22124 (set_attr "mode" "TI")])
22126 (define_insn "ashlv2di3"
22127 [(set (match_operand:V2DI 0 "register_operand" "=x")
22128 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
22129 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22131 "psllq\t{%2, %0|%0, %2}"
22132 [(set_attr "type" "sseishft")
22133 (set_attr "mode" "TI")])
22135 (define_insn "ashrv8hi3_ti"
22136 [(set (match_operand:V8HI 0 "register_operand" "=x")
22137 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22138 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22140 "psraw\t{%2, %0|%0, %2}"
22141 [(set_attr "type" "sseishft")
22142 (set_attr "mode" "TI")])
22144 (define_insn "ashrv4si3_ti"
22145 [(set (match_operand:V4SI 0 "register_operand" "=x")
22146 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22147 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22149 "psrad\t{%2, %0|%0, %2}"
22150 [(set_attr "type" "sseishft")
22151 (set_attr "mode" "TI")])
22153 (define_insn "lshrv8hi3_ti"
22154 [(set (match_operand:V8HI 0 "register_operand" "=x")
22155 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22156 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22158 "psrlw\t{%2, %0|%0, %2}"
22159 [(set_attr "type" "sseishft")
22160 (set_attr "mode" "TI")])
22162 (define_insn "lshrv4si3_ti"
22163 [(set (match_operand:V4SI 0 "register_operand" "=x")
22164 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22165 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22167 "psrld\t{%2, %0|%0, %2}"
22168 [(set_attr "type" "sseishft")
22169 (set_attr "mode" "TI")])
22171 (define_insn "lshrv2di3_ti"
22172 [(set (match_operand:V2DI 0 "register_operand" "=x")
22173 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
22174 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22176 "psrlq\t{%2, %0|%0, %2}"
22177 [(set_attr "type" "sseishft")
22178 (set_attr "mode" "TI")])
22180 (define_insn "ashlv8hi3_ti"
22181 [(set (match_operand:V8HI 0 "register_operand" "=x")
22182 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
22183 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22185 "psllw\t{%2, %0|%0, %2}"
22186 [(set_attr "type" "sseishft")
22187 (set_attr "mode" "TI")])
22189 (define_insn "ashlv4si3_ti"
22190 [(set (match_operand:V4SI 0 "register_operand" "=x")
22191 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
22192 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22194 "pslld\t{%2, %0|%0, %2}"
22195 [(set_attr "type" "sseishft")
22196 (set_attr "mode" "TI")])
22198 (define_insn "ashlv2di3_ti"
22199 [(set (match_operand:V2DI 0 "register_operand" "=x")
22200 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
22201 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22203 "psllq\t{%2, %0|%0, %2}"
22204 [(set_attr "type" "sseishft")
22205 (set_attr "mode" "TI")])
22207 ;; See logical MMX insns for the reason for the unspec. Strictly speaking
22208 ;; we wouldn't need here it since we never generate TImode arithmetic.
22210 ;; There has to be some kind of prize for the weirdest new instruction...
22211 (define_insn "sse2_ashlti3"
22212 [(set (match_operand:TI 0 "register_operand" "=x")
22214 [(ashift:TI (match_operand:TI 1 "register_operand" "0")
22215 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
22216 (const_int 8)))] UNSPEC_NOP))]
22218 "pslldq\t{%2, %0|%0, %2}"
22219 [(set_attr "type" "sseishft")
22220 (set_attr "mode" "TI")])
22222 (define_insn "sse2_lshrti3"
22223 [(set (match_operand:TI 0 "register_operand" "=x")
22225 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
22226 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
22227 (const_int 8)))] UNSPEC_NOP))]
22229 "psrldq\t{%2, %0|%0, %2}"
22230 [(set_attr "type" "sseishft")
22231 (set_attr "mode" "TI")])
22235 (define_insn "sse2_unpckhpd"
22236 [(set (match_operand:V2DF 0 "register_operand" "=x")
22238 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
22239 (parallel [(const_int 1)]))
22240 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
22241 (parallel [(const_int 0)]))))]
22243 "unpckhpd\t{%2, %0|%0, %2}"
22244 [(set_attr "type" "ssecvt")
22245 (set_attr "mode" "TI")])
22247 (define_insn "sse2_unpcklpd"
22248 [(set (match_operand:V2DF 0 "register_operand" "=x")
22250 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
22251 (parallel [(const_int 0)]))
22252 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
22253 (parallel [(const_int 1)]))))]
22255 "unpcklpd\t{%2, %0|%0, %2}"
22256 [(set_attr "type" "ssecvt")
22257 (set_attr "mode" "TI")])
22259 ;; MMX pack/unpack insns.
22261 (define_insn "sse2_packsswb"
22262 [(set (match_operand:V16QI 0 "register_operand" "=x")
22264 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
22265 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
22267 "packsswb\t{%2, %0|%0, %2}"
22268 [(set_attr "type" "ssecvt")
22269 (set_attr "mode" "TI")])
22271 (define_insn "sse2_packssdw"
22272 [(set (match_operand:V8HI 0 "register_operand" "=x")
22274 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
22275 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
22277 "packssdw\t{%2, %0|%0, %2}"
22278 [(set_attr "type" "ssecvt")
22279 (set_attr "mode" "TI")])
22281 (define_insn "sse2_packuswb"
22282 [(set (match_operand:V16QI 0 "register_operand" "=x")
22284 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
22285 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
22287 "packuswb\t{%2, %0|%0, %2}"
22288 [(set_attr "type" "ssecvt")
22289 (set_attr "mode" "TI")])
22291 (define_insn "sse2_punpckhbw"
22292 [(set (match_operand:V16QI 0 "register_operand" "=x")
22294 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
22295 (parallel [(const_int 8) (const_int 0)
22296 (const_int 9) (const_int 1)
22297 (const_int 10) (const_int 2)
22298 (const_int 11) (const_int 3)
22299 (const_int 12) (const_int 4)
22300 (const_int 13) (const_int 5)
22301 (const_int 14) (const_int 6)
22302 (const_int 15) (const_int 7)]))
22303 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
22304 (parallel [(const_int 0) (const_int 8)
22305 (const_int 1) (const_int 9)
22306 (const_int 2) (const_int 10)
22307 (const_int 3) (const_int 11)
22308 (const_int 4) (const_int 12)
22309 (const_int 5) (const_int 13)
22310 (const_int 6) (const_int 14)
22311 (const_int 7) (const_int 15)]))
22312 (const_int 21845)))]
22314 "punpckhbw\t{%2, %0|%0, %2}"
22315 [(set_attr "type" "ssecvt")
22316 (set_attr "mode" "TI")])
22318 (define_insn "sse2_punpckhwd"
22319 [(set (match_operand:V8HI 0 "register_operand" "=x")
22321 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
22322 (parallel [(const_int 4) (const_int 0)
22323 (const_int 5) (const_int 1)
22324 (const_int 6) (const_int 2)
22325 (const_int 7) (const_int 3)]))
22326 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
22327 (parallel [(const_int 0) (const_int 4)
22328 (const_int 1) (const_int 5)
22329 (const_int 2) (const_int 6)
22330 (const_int 3) (const_int 7)]))
22333 "punpckhwd\t{%2, %0|%0, %2}"
22334 [(set_attr "type" "ssecvt")
22335 (set_attr "mode" "TI")])
22337 (define_insn "sse2_punpckhdq"
22338 [(set (match_operand:V4SI 0 "register_operand" "=x")
22340 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
22341 (parallel [(const_int 2) (const_int 0)
22342 (const_int 3) (const_int 1)]))
22343 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
22344 (parallel [(const_int 0) (const_int 2)
22345 (const_int 1) (const_int 3)]))
22348 "punpckhdq\t{%2, %0|%0, %2}"
22349 [(set_attr "type" "ssecvt")
22350 (set_attr "mode" "TI")])
22352 (define_insn "sse2_punpcklbw"
22353 [(set (match_operand:V16QI 0 "register_operand" "=x")
22355 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
22356 (parallel [(const_int 0) (const_int 8)
22357 (const_int 1) (const_int 9)
22358 (const_int 2) (const_int 10)
22359 (const_int 3) (const_int 11)
22360 (const_int 4) (const_int 12)
22361 (const_int 5) (const_int 13)
22362 (const_int 6) (const_int 14)
22363 (const_int 7) (const_int 15)]))
22364 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
22365 (parallel [(const_int 8) (const_int 0)
22366 (const_int 9) (const_int 1)
22367 (const_int 10) (const_int 2)
22368 (const_int 11) (const_int 3)
22369 (const_int 12) (const_int 4)
22370 (const_int 13) (const_int 5)
22371 (const_int 14) (const_int 6)
22372 (const_int 15) (const_int 7)]))
22373 (const_int 21845)))]
22375 "punpcklbw\t{%2, %0|%0, %2}"
22376 [(set_attr "type" "ssecvt")
22377 (set_attr "mode" "TI")])
22379 (define_insn "sse2_punpcklwd"
22380 [(set (match_operand:V8HI 0 "register_operand" "=x")
22382 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
22383 (parallel [(const_int 0) (const_int 4)
22384 (const_int 1) (const_int 5)
22385 (const_int 2) (const_int 6)
22386 (const_int 3) (const_int 7)]))
22387 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
22388 (parallel [(const_int 4) (const_int 0)
22389 (const_int 5) (const_int 1)
22390 (const_int 6) (const_int 2)
22391 (const_int 7) (const_int 3)]))
22394 "punpcklwd\t{%2, %0|%0, %2}"
22395 [(set_attr "type" "ssecvt")
22396 (set_attr "mode" "TI")])
22398 (define_insn "sse2_punpckldq"
22399 [(set (match_operand:V4SI 0 "register_operand" "=x")
22401 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
22402 (parallel [(const_int 0) (const_int 2)
22403 (const_int 1) (const_int 3)]))
22404 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
22405 (parallel [(const_int 2) (const_int 0)
22406 (const_int 3) (const_int 1)]))
22409 "punpckldq\t{%2, %0|%0, %2}"
22410 [(set_attr "type" "ssecvt")
22411 (set_attr "mode" "TI")])
22413 (define_insn "sse2_punpcklqdq"
22414 [(set (match_operand:V2DI 0 "register_operand" "=x")
22416 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
22417 (parallel [(const_int 1)
22419 (match_operand:V2DI 1 "register_operand" "0")
22422 "punpcklqdq\t{%2, %0|%0, %2}"
22423 [(set_attr "type" "ssecvt")
22424 (set_attr "mode" "TI")])
22426 (define_insn "sse2_punpckhqdq"
22427 [(set (match_operand:V2DI 0 "register_operand" "=x")
22429 (match_operand:V2DI 1 "register_operand" "0")
22430 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
22431 (parallel [(const_int 1)
22435 "punpckhqdq\t{%2, %0|%0, %2}"
22436 [(set_attr "type" "ssecvt")
22437 (set_attr "mode" "TI")])
22441 (define_insn "sse2_movapd"
22442 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22443 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
22446 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22447 "movapd\t{%1, %0|%0, %1}"
22448 [(set_attr "type" "ssemov")
22449 (set_attr "mode" "V2DF")])
22451 (define_insn "sse2_movupd"
22452 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22453 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
22456 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22457 "movupd\t{%1, %0|%0, %1}"
22458 [(set_attr "type" "ssecvt")
22459 (set_attr "mode" "V2DF")])
22461 (define_insn "sse2_movdqa"
22462 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
22463 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
22466 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22467 "movdqa\t{%1, %0|%0, %1}"
22468 [(set_attr "type" "ssemov")
22469 (set_attr "mode" "TI")])
22471 (define_insn "sse2_movdqu"
22472 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
22473 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
22476 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22477 "movdqu\t{%1, %0|%0, %1}"
22478 [(set_attr "type" "ssecvt")
22479 (set_attr "mode" "TI")])
22481 (define_insn "sse2_movdq2q"
22482 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y")
22483 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x")
22484 (parallel [(const_int 0)])))]
22487 movq\t{%1, %0|%0, %1}
22488 movdq2q\t{%1, %0|%0, %1}"
22489 [(set_attr "type" "ssecvt")
22490 (set_attr "mode" "TI")])
22492 (define_insn "sse2_movq2dq"
22493 [(set (match_operand:V2DI 0 "register_operand" "=x,?x")
22494 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y")
22498 movq\t{%1, %0|%0, %1}
22499 movq2dq\t{%1, %0|%0, %1}"
22500 [(set_attr "type" "ssecvt,ssemov")
22501 (set_attr "mode" "TI")])
22503 (define_insn "sse2_movq"
22504 [(set (match_operand:V2DI 0 "register_operand" "=x")
22505 (vec_concat:V2DI (vec_select:DI
22506 (match_operand:V2DI 1 "nonimmediate_operand" "xm")
22507 (parallel [(const_int 0)]))
22510 "movq\t{%1, %0|%0, %1}"
22511 [(set_attr "type" "ssemov")
22512 (set_attr "mode" "TI")])
22514 (define_insn "sse2_loadd"
22515 [(set (match_operand:V4SI 0 "register_operand" "=x")
22517 (vec_duplicate:V4HI (match_operand:SI 1 "nonimmediate_operand" "mr"))
22518 (const_vector:V4SI [(const_int 0)
22524 "movd\t{%1, %0|%0, %1}"
22525 [(set_attr "type" "ssemov")
22526 (set_attr "mode" "TI")])
22528 (define_insn "sse2_stored"
22529 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
22531 (match_operand:V4SI 1 "register_operand" "x")
22532 (parallel [(const_int 0)])))]
22534 "movd\t{%1, %0|%0, %1}"
22535 [(set_attr "type" "ssemov")
22536 (set_attr "mode" "TI")])
22538 (define_insn "sse2_movhpd"
22539 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22541 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
22542 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
22544 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
22545 "movhpd\t{%2, %0|%0, %2}"
22546 [(set_attr "type" "ssecvt")
22547 (set_attr "mode" "V2DF")])
22549 (define_insn "sse2_movlpd"
22550 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22552 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
22553 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
22555 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
22556 "movlpd\t{%2, %0|%0, %2}"
22557 [(set_attr "type" "ssecvt")
22558 (set_attr "mode" "V2DF")])
22560 (define_expand "sse2_loadsd"
22561 [(match_operand:V2DF 0 "register_operand" "")
22562 (match_operand:DF 1 "memory_operand" "")]
22565 emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1],
22566 CONST0_RTX (V2DFmode)));
22570 (define_insn "sse2_loadsd_1"
22571 [(set (match_operand:V2DF 0 "register_operand" "=x")
22573 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m"))
22574 (match_operand:V2DF 2 "const0_operand" "X")
22577 "movsd\t{%1, %0|%0, %1}"
22578 [(set_attr "type" "ssecvt")
22579 (set_attr "mode" "DF")])
22581 (define_insn "sse2_movsd"
22582 [(set (match_operand:V2DF 0 "register_operand" "=x")
22584 (match_operand:V2DF 1 "register_operand" "0")
22585 (match_operand:V2DF 2 "register_operand" "x")
22588 "movsd\t{%2, %0|%0, %2}"
22589 [(set_attr "type" "ssecvt")
22590 (set_attr "mode" "DF")])
22592 (define_insn "sse2_storesd"
22593 [(set (match_operand:DF 0 "memory_operand" "=m")
22595 (match_operand:V2DF 1 "register_operand" "x")
22596 (parallel [(const_int 0)])))]
22598 "movsd\t{%1, %0|%0, %1}"
22599 [(set_attr "type" "ssecvt")
22600 (set_attr "mode" "DF")])
22602 (define_insn "sse2_shufpd"
22603 [(set (match_operand:V2DF 0 "register_operand" "=x")
22604 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
22605 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
22606 (match_operand:SI 3 "immediate_operand" "i")]
22609 ;; @@@ check operand order for intel/nonintel syntax
22610 "shufpd\t{%3, %2, %0|%0, %2, %3}"
22611 [(set_attr "type" "ssecvt")
22612 (set_attr "mode" "V2DF")])
22614 (define_insn "sse2_clflush"
22615 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
22619 [(set_attr "type" "sse")
22620 (set_attr "memory" "unknown")])
22622 (define_expand "sse2_mfence"
22623 [(set (match_dup 0)
22624 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
22627 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
22628 MEM_VOLATILE_P (operands[0]) = 1;
22631 (define_insn "*mfence_insn"
22632 [(set (match_operand:BLK 0 "" "")
22633 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
22636 [(set_attr "type" "sse")
22637 (set_attr "memory" "unknown")])
22639 (define_expand "sse2_lfence"
22640 [(set (match_dup 0)
22641 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
22644 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
22645 MEM_VOLATILE_P (operands[0]) = 1;
22648 (define_insn "*lfence_insn"
22649 [(set (match_operand:BLK 0 "" "")
22650 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
22653 [(set_attr "type" "sse")
22654 (set_attr "memory" "unknown")])