1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
23 /* This module is essentially the "combiner" phase of the U. of Arizona
24 Portable Optimizer, but redone to work on our list-structured
25 representation for RTL instead of their string representation.
27 The LOG_LINKS of each insn identify the most recent assignment
28 to each REG used in the insn. It is a list of previous insns,
29 each of which contains a SET for a REG that is used in this insn
30 and not used or set in between. LOG_LINKs never cross basic blocks.
31 They were set up by the preceding pass (lifetime analysis).
33 We try to combine each pair of insns joined by a logical link.
34 We also try to combine triples of insns A, B and C when
35 C has a link back to B and B has a link back to A.
37 LOG_LINKS does not have links for use of the CC0. They don't
38 need to, because the insn that sets the CC0 is always immediately
39 before the insn that tests it. So we always regard a branch
40 insn as having a logical link to the preceding insn. The same is true
41 for an insn explicitly using CC0.
43 We check (with use_crosses_set_p) to avoid combining in such a way
44 as to move a computation to a place where its value would be different.
46 Combination is done by mathematically substituting the previous
47 insn(s) values for the regs they set into the expressions in
48 the later insns that refer to these regs. If the result is a valid insn
49 for our target machine, according to the machine description,
50 we install it, delete the earlier insns, and update the data flow
51 information (LOG_LINKS and REG_NOTES) for what we did.
53 There are a few exceptions where the dataflow information isn't
54 completely updated (however this is only a local issue since it is
55 regenerated before the next pass that uses it):
57 - reg_live_length is not updated
58 - reg_n_refs is not adjusted in the rare case when a register is
59 no longer required in a computation
60 - there are extremely rare cases (see distribute_notes) when a
62 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
63 removed because there is no way to know which register it was
66 To simplify substitution, we combine only when the earlier insn(s)
67 consist of only a single assignment. To simplify updating afterward,
68 we never combine when a subroutine call appears in the middle.
70 Since we do not represent assignments to CC0 explicitly except when that
71 is all an insn does, there is no LOG_LINKS entry in an insn that uses
72 the condition code for the insn that set the condition code.
73 Fortunately, these two insns must be consecutive.
74 Therefore, every JUMP_INSN is taken to have an implicit logical link
75 to the preceding insn. This is not quite right, since non-jumps can
76 also use the condition code; but in practice such insns would not
81 #include "coretypes.h"
88 #include "hard-reg-set.h"
89 #include "basic-block.h"
90 #include "insn-config.h"
92 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
94 #include "insn-attr.h"
100 #include "insn-codes.h"
101 #include "rtlhooks-def.h"
102 /* Include output.h for dump_file. */
106 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts
;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges
;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras
;
121 /* Number of instructions combined in this function. */
123 static int combine_successes
;
125 /* Totals over entire compilation. */
127 static int total_attempts
, total_merges
, total_extras
, total_successes
;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs
;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs
;
146 /* Maximum register number, which is the size of the tables below. */
148 static unsigned int combine_max_regno
;
151 /* Record last point of death of (hard or pseudo) register n. */
154 /* Record last point of modification of (hard or pseudo) register n. */
157 /* The next group of fields allows the recording of the last value assigned
158 to (hard or pseudo) register n. We use this information to see if an
159 operation being processed is redundant given a prior operation performed
160 on the register. For example, an `and' with a constant is redundant if
161 all the zero bits are already known to be turned off.
163 We use an approach similar to that used by cse, but change it in the
166 (1) We do not want to reinitialize at each label.
167 (2) It is useful, but not critical, to know the actual value assigned
168 to a register. Often just its form is helpful.
170 Therefore, we maintain the following fields:
172 last_set_value the last value assigned
173 last_set_label records the value of label_tick when the
174 register was assigned
175 last_set_table_tick records the value of label_tick when a
176 value using the register is assigned
177 last_set_invalid set to nonzero when it is not valid
178 to use the value of this register in some
181 To understand the usage of these tables, it is important to understand
182 the distinction between the value in last_set_value being valid and
183 the register being validly contained in some other expression in the
186 (The next two parameters are out of date).
188 reg_stat[i].last_set_value is valid if it is nonzero, and either
189 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
191 Register I may validly appear in any expression returned for the value
192 of another register if reg_n_sets[i] is 1. It may also appear in the
193 value for register J if reg_stat[j].last_set_invalid is zero, or
194 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
196 If an expression is found in the table containing a register which may
197 not validly appear in an expression, the register is replaced by
198 something that won't match, (clobber (const_int 0)). */
200 /* Record last value assigned to (hard or pseudo) register n. */
204 /* Record the value of label_tick when an expression involving register n
205 is placed in last_set_value. */
207 int last_set_table_tick
;
209 /* Record the value of label_tick when the value for register n is placed in
214 /* These fields are maintained in parallel with last_set_value and are
215 used to store the mode in which the register was last set, the bits
216 that were known to be zero when it was last set, and the number of
217 sign bits copies it was known to have when it was last set. */
219 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
220 char last_set_sign_bit_copies
;
221 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
223 /* Set nonzero if references to register n in expressions should not be
224 used. last_set_invalid is set nonzero when this register is being
225 assigned to and last_set_table_tick == label_tick. */
227 char last_set_invalid
;
229 /* Some registers that are set more than once and used in more than one
230 basic block are nevertheless always set in similar ways. For example,
231 a QImode register may be loaded from memory in two places on a machine
232 where byte loads zero extend.
234 We record in the following fields if a register has some leading bits
235 that are always equal to the sign bit, and what we know about the
236 nonzero bits of a register, specifically which bits are known to be
239 If an entry is zero, it means that we don't know anything special. */
241 unsigned char sign_bit_copies
;
243 unsigned HOST_WIDE_INT nonzero_bits
;
245 /* Record the value of the label_tick when the last truncation
246 happened. The field truncated_to_mode is only valid if
247 truncation_label == label_tick. */
249 int truncation_label
;
251 /* Record the last truncation seen for this register. If truncation
252 is not a nop to this mode we might be able to save an explicit
253 truncation if we know that value already contains a truncated
256 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
259 static struct reg_stat
*reg_stat
;
261 /* Record the luid of the last insn that invalidated memory
262 (anything that writes memory, and subroutine calls, but not pushes). */
264 static int mem_last_set
;
266 /* Record the luid of the last CALL_INSN
267 so we can tell whether a potential combination crosses any calls. */
269 static int last_call_luid
;
271 /* When `subst' is called, this is the insn that is being modified
272 (by combining in a previous insn). The PATTERN of this insn
273 is still the old pattern partially modified and it should not be
274 looked at, but this may be used to examine the successors of the insn
275 to judge whether a simplification is valid. */
277 static rtx subst_insn
;
279 /* This is the lowest LUID that `subst' is currently dealing with.
280 get_last_value will not return a value if the register was set at or
281 after this LUID. If not for this mechanism, we could get confused if
282 I2 or I1 in try_combine were an insn that used the old value of a register
283 to obtain a new value. In that case, we might erroneously get the
284 new value of the register when we wanted the old one. */
286 static int subst_low_luid
;
288 /* This contains any hard registers that are used in newpat; reg_dead_at_p
289 must consider all these registers to be always live. */
291 static HARD_REG_SET newpat_used_regs
;
293 /* This is an insn to which a LOG_LINKS entry has been added. If this
294 insn is the earlier than I2 or I3, combine should rescan starting at
297 static rtx added_links_insn
;
299 /* Basic block in which we are performing combines. */
300 static basic_block this_basic_block
;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known
;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost
;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx
*uid_log_links
;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick
;
324 /* Reset to label_tick for each label. */
326 static int label_tick_ebb_start
;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode
;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid
;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
348 enum { UNDO_RTX
, UNDO_INT
, UNDO_MODE
} kind
;
349 union { rtx r
; int i
; enum machine_mode m
; } old_contents
;
350 union { rtx
*r
; int *i
; } where
;
353 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
354 num_undo says how many are currently recorded.
356 other_insn is nonzero if we have modified some other insn in the process
357 of working on subst_insn. It must be verified too. */
366 static struct undobuf undobuf
;
368 /* Number of times the pseudo being substituted for
369 was found and replaced. */
371 static int n_occurrences
;
373 static rtx
reg_nonzero_bits_for_combine (rtx
, enum machine_mode
, rtx
,
375 unsigned HOST_WIDE_INT
,
376 unsigned HOST_WIDE_INT
*);
377 static rtx
reg_num_sign_bit_copies_for_combine (rtx
, enum machine_mode
, rtx
,
379 unsigned int, unsigned int *);
380 static void do_SUBST (rtx
*, rtx
);
381 static void do_SUBST_INT (int *, int);
382 static void init_reg_last (void);
383 static void setup_incoming_promotions (rtx
);
384 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
385 static int cant_combine_insn_p (rtx
);
386 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
387 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
388 static int contains_muldiv (rtx
);
389 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
390 static void undo_all (void);
391 static void undo_commit (void);
392 static rtx
*find_split_point (rtx
*, rtx
);
393 static rtx
subst (rtx
, rtx
, rtx
, int, int);
394 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
395 static rtx
simplify_if_then_else (rtx
);
396 static rtx
simplify_set (rtx
);
397 static rtx
simplify_logical (rtx
);
398 static rtx
expand_compound_operation (rtx
);
399 static rtx
expand_field_assignment (rtx
);
400 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
401 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
402 static rtx
extract_left_shift (rtx
, int);
403 static rtx
make_compound_operation (rtx
, enum rtx_code
);
404 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
405 unsigned HOST_WIDE_INT
*);
406 static rtx
canon_reg_for_combine (rtx
, rtx
);
407 static rtx
force_to_mode (rtx
, enum machine_mode
,
408 unsigned HOST_WIDE_INT
, int);
409 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
410 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
411 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
412 static rtx
make_field_assignment (rtx
);
413 static rtx
apply_distributive_law (rtx
);
414 static rtx
distribute_and_simplify_rtx (rtx
, int);
415 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
416 unsigned HOST_WIDE_INT
);
417 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
418 unsigned HOST_WIDE_INT
);
419 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
420 HOST_WIDE_INT
, enum machine_mode
, int *);
421 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
422 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
424 static int recog_for_combine (rtx
*, rtx
, rtx
*);
425 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
426 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
427 static void update_table_tick (rtx
);
428 static void record_value_for_reg (rtx
, rtx
, rtx
);
429 static void check_conversions (rtx
, rtx
);
430 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
431 static void record_dead_and_set_regs (rtx
);
432 static int get_last_value_validate (rtx
*, rtx
, int, int);
433 static rtx
get_last_value (rtx
);
434 static int use_crosses_set_p (rtx
, int);
435 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
436 static int reg_dead_at_p (rtx
, rtx
);
437 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
438 static int reg_bitfield_target_p (rtx
, rtx
);
439 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
440 static void distribute_links (rtx
);
441 static void mark_used_regs_combine (rtx
);
442 static void record_promoted_value (rtx
, rtx
);
443 static int unmentioned_reg_p_1 (rtx
*, void *);
444 static bool unmentioned_reg_p (rtx
, rtx
);
445 static void record_truncated_value (rtx
);
446 static bool reg_truncated_to_mode (enum machine_mode
, rtx
);
447 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
450 /* It is not safe to use ordinary gen_lowpart in combine.
451 See comments in gen_lowpart_for_combine. */
452 #undef RTL_HOOKS_GEN_LOWPART
453 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
455 /* Our implementation of gen_lowpart never emits a new pseudo. */
456 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
457 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
459 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
460 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
462 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
463 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
465 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
466 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
468 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
471 /* This is used by find_single_use to locate an rtx in LOC that
472 contains exactly one use of DEST, which is typically either a REG
473 or CC0. It returns a pointer to the innermost rtx expression
474 containing DEST. Appearances of DEST that are being used to
475 totally replace it are not counted. */
478 find_single_use_1 (rtx dest
, rtx
*loc
)
481 enum rtx_code code
= GET_CODE (x
);
499 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
500 of a REG that occupies all of the REG, the insn uses DEST if
501 it is mentioned in the destination or the source. Otherwise, we
502 need just check the source. */
503 if (GET_CODE (SET_DEST (x
)) != CC0
504 && GET_CODE (SET_DEST (x
)) != PC
505 && !REG_P (SET_DEST (x
))
506 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
507 && REG_P (SUBREG_REG (SET_DEST (x
)))
508 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
509 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
510 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
511 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
514 return find_single_use_1 (dest
, &SET_SRC (x
));
518 return find_single_use_1 (dest
, &XEXP (x
, 0));
524 /* If it wasn't one of the common cases above, check each expression and
525 vector of this code. Look for a unique usage of DEST. */
527 fmt
= GET_RTX_FORMAT (code
);
528 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
532 if (dest
== XEXP (x
, i
)
533 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
534 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
537 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
540 result
= this_result
;
541 else if (this_result
)
542 /* Duplicate usage. */
545 else if (fmt
[i
] == 'E')
549 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
551 if (XVECEXP (x
, i
, j
) == dest
553 && REG_P (XVECEXP (x
, i
, j
))
554 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
557 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
560 result
= this_result
;
561 else if (this_result
)
571 /* See if DEST, produced in INSN, is used only a single time in the
572 sequel. If so, return a pointer to the innermost rtx expression in which
575 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
577 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
578 care about REG_DEAD notes or LOG_LINKS.
580 Otherwise, we find the single use by finding an insn that has a
581 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
582 only referenced once in that insn, we know that it must be the first
583 and last insn referencing DEST. */
586 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
595 next
= NEXT_INSN (insn
);
597 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
600 result
= find_single_use_1 (dest
, &PATTERN (next
));
610 for (next
= next_nonnote_insn (insn
);
611 next
!= 0 && !LABEL_P (next
);
612 next
= next_nonnote_insn (next
))
613 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
615 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
616 if (XEXP (link
, 0) == insn
)
621 result
= find_single_use_1 (dest
, &PATTERN (next
));
631 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
632 insn. The substitution can be undone by undo_all. If INTO is already
633 set to NEWVAL, do not record this change. Because computing NEWVAL might
634 also call SUBST, we have to compute it before we put anything into
638 do_SUBST (rtx
*into
, rtx newval
)
643 if (oldval
== newval
)
646 /* We'd like to catch as many invalid transformations here as
647 possible. Unfortunately, there are way too many mode changes
648 that are perfectly valid, so we'd waste too much effort for
649 little gain doing the checks here. Focus on catching invalid
650 transformations involving integer constants. */
651 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
652 && GET_CODE (newval
) == CONST_INT
)
654 /* Sanity check that we're replacing oldval with a CONST_INT
655 that is a valid sign-extension for the original mode. */
656 gcc_assert (INTVAL (newval
)
657 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
659 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
660 CONST_INT is not valid, because after the replacement, the
661 original mode would be gone. Unfortunately, we can't tell
662 when do_SUBST is called to replace the operand thereof, so we
663 perform this test on oldval instead, checking whether an
664 invalid replacement took place before we got here. */
665 gcc_assert (!(GET_CODE (oldval
) == SUBREG
666 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
));
667 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
668 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
));
672 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
674 buf
= XNEW (struct undo
);
676 buf
->kind
= UNDO_RTX
;
678 buf
->old_contents
.r
= oldval
;
681 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
684 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
686 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
687 for the value of a HOST_WIDE_INT value (including CONST_INT) is
691 do_SUBST_INT (int *into
, int newval
)
696 if (oldval
== newval
)
700 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
702 buf
= XNEW (struct undo
);
704 buf
->kind
= UNDO_INT
;
706 buf
->old_contents
.i
= oldval
;
709 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
712 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
714 /* Similar to SUBST, but just substitute the mode. This is used when
715 changing the mode of a pseudo-register, so that any other
716 references to the entry in the regno_reg_rtx array will change as
720 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
723 enum machine_mode oldval
= GET_MODE (*into
);
725 if (oldval
== newval
)
729 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
731 buf
= XNEW (struct undo
);
733 buf
->kind
= UNDO_MODE
;
735 buf
->old_contents
.m
= oldval
;
736 PUT_MODE (*into
, newval
);
738 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
741 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
743 /* Subroutine of try_combine. Determine whether the combine replacement
744 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
745 that the original instruction sequence I1, I2 and I3. Note that I1
746 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
747 costs of all instructions can be estimated, and the replacements are
748 more expensive than the original sequence. */
751 combine_validate_cost (rtx i1
, rtx i2
, rtx i3
, rtx newpat
, rtx newi2pat
)
753 int i1_cost
, i2_cost
, i3_cost
;
754 int new_i2_cost
, new_i3_cost
;
755 int old_cost
, new_cost
;
757 /* Lookup the original insn_rtx_costs. */
758 i2_cost
= INSN_COST (i2
);
759 i3_cost
= INSN_COST (i3
);
763 i1_cost
= INSN_COST (i1
);
764 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0)
765 ? i1_cost
+ i2_cost
+ i3_cost
: 0;
769 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
773 /* Calculate the replacement insn_rtx_costs. */
774 new_i3_cost
= insn_rtx_cost (newpat
);
777 new_i2_cost
= insn_rtx_cost (newi2pat
);
778 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
779 ? new_i2_cost
+ new_i3_cost
: 0;
783 new_cost
= new_i3_cost
;
787 if (undobuf
.other_insn
)
789 int old_other_cost
, new_other_cost
;
791 old_other_cost
= INSN_COST (undobuf
.other_insn
);
792 new_other_cost
= insn_rtx_cost (PATTERN (undobuf
.other_insn
));
793 if (old_other_cost
> 0 && new_other_cost
> 0)
795 old_cost
+= old_other_cost
;
796 new_cost
+= new_other_cost
;
802 /* Disallow this recombination if both new_cost and old_cost are
803 greater than zero, and new_cost is greater than old cost. */
805 && new_cost
> old_cost
)
812 "rejecting combination of insns %d, %d and %d\n",
813 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
814 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
815 i1_cost
, i2_cost
, i3_cost
, old_cost
);
820 "rejecting combination of insns %d and %d\n",
821 INSN_UID (i2
), INSN_UID (i3
));
822 fprintf (dump_file
, "original costs %d + %d = %d\n",
823 i2_cost
, i3_cost
, old_cost
);
828 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
829 new_i2_cost
, new_i3_cost
, new_cost
);
832 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
838 /* Update the uid_insn_cost array with the replacement costs. */
839 INSN_COST (i2
) = new_i2_cost
;
840 INSN_COST (i3
) = new_i3_cost
;
848 /* Delete any insns that copy a register to itself. */
851 delete_noop_moves (void)
858 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
860 next
= NEXT_INSN (insn
);
861 if (INSN_P (insn
) && noop_move_p (insn
))
865 /* If we're about to remove the first insn of a libcall
866 then move the libcall note to the next real insn and
867 update the retval note. */
868 if ((note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
))
869 && XEXP (note
, 0) != insn
)
871 rtx new_libcall_insn
= next_real_insn (insn
);
872 rtx retval_note
= find_reg_note (XEXP (note
, 0),
873 REG_RETVAL
, NULL_RTX
);
874 REG_NOTES (new_libcall_insn
)
875 = gen_rtx_INSN_LIST (REG_LIBCALL
, XEXP (note
, 0),
876 REG_NOTES (new_libcall_insn
));
877 XEXP (retval_note
, 0) = new_libcall_insn
;
881 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
883 delete_insn_and_edges (insn
);
890 /* Fill in log links field for all insns. */
893 create_log_links (void)
897 struct df_ref
**def_vec
, **use_vec
;
899 next_use
= XCNEWVEC (rtx
, max_reg_num ());
901 /* Pass through each block from the end, recording the uses of each
902 register and establishing log links when def is encountered.
903 Note that we do not clear next_use array in order to save time,
904 so we have to test whether the use is in the same basic block as def.
906 There are a few cases below when we do not consider the definition or
907 usage -- these are taken from original flow.c did. Don't ask me why it is
908 done this way; I don't know and if it works, I don't want to know. */
912 FOR_BB_INSNS_REVERSE (bb
, insn
)
917 /* Log links are created only once. */
918 gcc_assert (!LOG_LINKS (insn
));
920 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
922 struct df_ref
*def
= *def_vec
;
923 int regno
= DF_REF_REGNO (def
);
926 if (!next_use
[regno
])
929 /* Do not consider if it is pre/post modification in MEM. */
930 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
933 /* Do not make the log link for frame pointer. */
934 if ((regno
== FRAME_POINTER_REGNUM
935 && (! reload_completed
|| frame_pointer_needed
))
936 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
937 || (regno
== HARD_FRAME_POINTER_REGNUM
938 && (! reload_completed
|| frame_pointer_needed
))
940 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
941 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
946 use_insn
= next_use
[regno
];
947 if (BLOCK_FOR_INSN (use_insn
) == bb
)
951 We don't build a LOG_LINK for hard registers contained
952 in ASM_OPERANDs. If these registers get replaced,
953 we might wind up changing the semantics of the insn,
954 even if reload can make what appear to be valid
955 assignments later. */
956 if (regno
>= FIRST_PSEUDO_REGISTER
957 || asm_noperands (PATTERN (use_insn
)) < 0)
958 LOG_LINKS (use_insn
) =
959 alloc_INSN_LIST (insn
, LOG_LINKS (use_insn
));
961 next_use
[regno
] = NULL_RTX
;
964 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
966 struct df_ref
*use
= *use_vec
;
967 int regno
= DF_REF_REGNO (use
);
969 /* Do not consider the usage of the stack pointer
971 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
974 next_use
[regno
] = insn
;
982 /* Clear LOG_LINKS fields of insns. */
985 clear_log_links (void)
989 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
991 free_INSN_LIST_list (&LOG_LINKS (insn
));
997 /* Main entry point for combiner. F is the first insn of the function.
998 NREGS is the first unused pseudo-reg number.
1000 Return nonzero if the combiner has turned an indirect jump
1001 instruction into a direct jump. */
1003 combine_instructions (rtx f
, unsigned int nregs
)
1009 rtx links
, nextlinks
;
1012 int new_direct_jump_p
= 0;
1014 for (first
= f
; first
&& !INSN_P (first
); )
1015 first
= NEXT_INSN (first
);
1019 combine_attempts
= 0;
1022 combine_successes
= 0;
1024 combine_max_regno
= nregs
;
1026 rtl_hooks
= combine_rtl_hooks
;
1028 reg_stat
= XCNEWVEC (struct reg_stat
, nregs
);
1030 init_recog_no_volatile ();
1032 /* Allocate array for insn info. */
1033 max_uid_known
= get_max_uid ();
1034 uid_log_links
= XCNEWVEC (rtx
, max_uid_known
+ 1);
1035 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1037 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1039 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1040 problems when, for example, we have j <<= 1 in a loop. */
1042 nonzero_sign_valid
= 0;
1044 /* Scan all SETs and see if we can deduce anything about what
1045 bits are known to be zero for some registers and how many copies
1046 of the sign bit are known to exist for those registers.
1048 Also set any known values so that we can use it while searching
1049 for what bits are known to be set. */
1051 label_tick
= label_tick_ebb_start
= 1;
1053 setup_incoming_promotions (first
);
1055 create_log_links ();
1056 FOR_EACH_BB (this_basic_block
)
1061 FOR_BB_INSNS (this_basic_block
, insn
)
1062 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1064 subst_low_luid
= DF_INSN_LUID (insn
);
1067 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1069 record_dead_and_set_regs (insn
);
1072 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1073 if (REG_NOTE_KIND (links
) == REG_INC
)
1074 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1078 /* Record the current insn_rtx_cost of this instruction. */
1079 if (NONJUMP_INSN_P (insn
))
1080 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
));
1082 fprintf(dump_file
, "insn_cost %d: %d\n",
1083 INSN_UID (insn
), INSN_COST (insn
));
1085 else if (LABEL_P (insn
))
1086 label_tick_ebb_start
= label_tick
;
1089 nonzero_sign_valid
= 1;
1091 /* Now scan all the insns in forward order. */
1093 label_tick
= label_tick_ebb_start
= 1;
1095 setup_incoming_promotions (first
);
1097 FOR_EACH_BB (this_basic_block
)
1102 for (insn
= BB_HEAD (this_basic_block
);
1103 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1104 insn
= next
? next
: NEXT_INSN (insn
))
1109 /* See if we know about function return values before this
1110 insn based upon SUBREG flags. */
1111 check_conversions (insn
, PATTERN (insn
));
1113 /* Try this insn with each insn it links back to. */
1115 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1116 if ((next
= try_combine (insn
, XEXP (links
, 0),
1117 NULL_RTX
, &new_direct_jump_p
)) != 0)
1120 /* Try each sequence of three linked insns ending with this one. */
1122 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1124 rtx link
= XEXP (links
, 0);
1126 /* If the linked insn has been replaced by a note, then there
1127 is no point in pursuing this chain any further. */
1131 for (nextlinks
= LOG_LINKS (link
);
1133 nextlinks
= XEXP (nextlinks
, 1))
1134 if ((next
= try_combine (insn
, link
,
1135 XEXP (nextlinks
, 0),
1136 &new_direct_jump_p
)) != 0)
1141 /* Try to combine a jump insn that uses CC0
1142 with a preceding insn that sets CC0, and maybe with its
1143 logical predecessor as well.
1144 This is how we make decrement-and-branch insns.
1145 We need this special code because data flow connections
1146 via CC0 do not get entered in LOG_LINKS. */
1149 && (prev
= prev_nonnote_insn (insn
)) != 0
1150 && NONJUMP_INSN_P (prev
)
1151 && sets_cc0_p (PATTERN (prev
)))
1153 if ((next
= try_combine (insn
, prev
,
1154 NULL_RTX
, &new_direct_jump_p
)) != 0)
1157 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1158 nextlinks
= XEXP (nextlinks
, 1))
1159 if ((next
= try_combine (insn
, prev
,
1160 XEXP (nextlinks
, 0),
1161 &new_direct_jump_p
)) != 0)
1165 /* Do the same for an insn that explicitly references CC0. */
1166 if (NONJUMP_INSN_P (insn
)
1167 && (prev
= prev_nonnote_insn (insn
)) != 0
1168 && NONJUMP_INSN_P (prev
)
1169 && sets_cc0_p (PATTERN (prev
))
1170 && GET_CODE (PATTERN (insn
)) == SET
1171 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1173 if ((next
= try_combine (insn
, prev
,
1174 NULL_RTX
, &new_direct_jump_p
)) != 0)
1177 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1178 nextlinks
= XEXP (nextlinks
, 1))
1179 if ((next
= try_combine (insn
, prev
,
1180 XEXP (nextlinks
, 0),
1181 &new_direct_jump_p
)) != 0)
1185 /* Finally, see if any of the insns that this insn links to
1186 explicitly references CC0. If so, try this insn, that insn,
1187 and its predecessor if it sets CC0. */
1188 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1189 if (NONJUMP_INSN_P (XEXP (links
, 0))
1190 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
1191 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
1192 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
1193 && NONJUMP_INSN_P (prev
)
1194 && sets_cc0_p (PATTERN (prev
))
1195 && (next
= try_combine (insn
, XEXP (links
, 0),
1196 prev
, &new_direct_jump_p
)) != 0)
1200 /* Try combining an insn with two different insns whose results it
1202 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1203 for (nextlinks
= XEXP (links
, 1); nextlinks
;
1204 nextlinks
= XEXP (nextlinks
, 1))
1205 if ((next
= try_combine (insn
, XEXP (links
, 0),
1206 XEXP (nextlinks
, 0),
1207 &new_direct_jump_p
)) != 0)
1210 /* Try this insn with each REG_EQUAL note it links back to. */
1211 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1214 rtx temp
= XEXP (links
, 0);
1215 if ((set
= single_set (temp
)) != 0
1216 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1217 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1218 /* Avoid using a register that may already been marked
1219 dead by an earlier instruction. */
1220 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1221 && (GET_MODE (note
) == VOIDmode
1222 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1223 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1225 /* Temporarily replace the set's source with the
1226 contents of the REG_EQUAL note. The insn will
1227 be deleted or recognized by try_combine. */
1228 rtx orig
= SET_SRC (set
);
1229 SET_SRC (set
) = note
;
1231 i2mod_old_rhs
= copy_rtx (orig
);
1232 i2mod_new_rhs
= copy_rtx (note
);
1233 next
= try_combine (insn
, i2mod
, NULL_RTX
,
1234 &new_direct_jump_p
);
1238 SET_SRC (set
) = orig
;
1243 record_dead_and_set_regs (insn
);
1248 else if (LABEL_P (insn
))
1249 label_tick_ebb_start
= label_tick
;
1255 new_direct_jump_p
|= purge_all_dead_edges ();
1256 delete_noop_moves ();
1259 free (uid_log_links
);
1260 free (uid_insn_cost
);
1264 struct undo
*undo
, *next
;
1265 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1273 total_attempts
+= combine_attempts
;
1274 total_merges
+= combine_merges
;
1275 total_extras
+= combine_extras
;
1276 total_successes
+= combine_successes
;
1278 nonzero_sign_valid
= 0;
1279 rtl_hooks
= general_rtl_hooks
;
1281 /* Make recognizer allow volatile MEMs again. */
1284 return new_direct_jump_p
;
1287 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1290 init_reg_last (void)
1293 for (i
= 0; i
< combine_max_regno
; i
++)
1294 memset (reg_stat
+ i
, 0, offsetof (struct reg_stat
, sign_bit_copies
));
1297 /* Set up any promoted values for incoming argument registers. */
1300 setup_incoming_promotions (rtx first
)
1304 if (!targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
1307 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1308 arg
= TREE_CHAIN (arg
))
1310 rtx reg
= DECL_INCOMING_RTL (arg
);
1315 if (TYPE_MODE (DECL_ARG_TYPE (arg
)) == TYPE_MODE (TREE_TYPE (arg
)))
1317 enum machine_mode mode
= TYPE_MODE (TREE_TYPE (arg
));
1318 int uns
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1320 mode
= promote_mode (TREE_TYPE (arg
), mode
, &uns
, 1);
1321 if (mode
== GET_MODE (reg
) && mode
!= DECL_MODE (arg
))
1324 x
= gen_rtx_CLOBBER (DECL_MODE (arg
), const0_rtx
);
1325 x
= gen_rtx_fmt_e ((uns
? ZERO_EXTEND
: SIGN_EXTEND
), mode
, x
);
1326 record_value_for_reg (reg
, first
, x
);
1332 /* Called via note_stores. If X is a pseudo that is narrower than
1333 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1335 If we are setting only a portion of X and we can't figure out what
1336 portion, assume all bits will be used since we don't know what will
1339 Similarly, set how many bits of X are known to be copies of the sign bit
1340 at all locations in the function. This is the smallest number implied
1344 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
, void *data
)
1346 rtx insn
= (rtx
) data
;
1350 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1351 /* If this register is undefined at the start of the file, we can't
1352 say what its contents were. */
1353 && ! REGNO_REG_SET_P
1354 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
))
1355 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
1357 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1359 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1360 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
1364 /* If this register is being initialized using itself, and the
1365 register is uninitialized in this basic block, and there are
1366 no LOG_LINKS which set the register, then part of the
1367 register is uninitialized. In that case we can't assume
1368 anything about the number of nonzero bits.
1370 ??? We could do better if we checked this in
1371 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1372 could avoid making assumptions about the insn which initially
1373 sets the register, while still using the information in other
1374 insns. We would have to be careful to check every insn
1375 involved in the combination. */
1378 && reg_referenced_p (x
, PATTERN (insn
))
1379 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1384 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
1386 if (dead_or_set_p (XEXP (link
, 0), x
))
1391 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1392 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
1397 /* If this is a complex assignment, see if we can convert it into a
1398 simple assignment. */
1399 set
= expand_field_assignment (set
);
1401 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1402 set what we know about X. */
1404 if (SET_DEST (set
) == x
1405 || (GET_CODE (SET_DEST (set
)) == SUBREG
1406 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1407 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1408 && SUBREG_REG (SET_DEST (set
)) == x
))
1410 rtx src
= SET_SRC (set
);
1412 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1413 /* If X is narrower than a word and SRC is a non-negative
1414 constant that would appear negative in the mode of X,
1415 sign-extend it for use in reg_stat[].nonzero_bits because some
1416 machines (maybe most) will actually do the sign-extension
1417 and this is the conservative approach.
1419 ??? For 2.5, try to tighten up the MD files in this regard
1420 instead of this kludge. */
1422 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1423 && GET_CODE (src
) == CONST_INT
1425 && 0 != (INTVAL (src
)
1426 & ((HOST_WIDE_INT
) 1
1427 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1428 src
= GEN_INT (INTVAL (src
)
1429 | ((HOST_WIDE_INT
) (-1)
1430 << GET_MODE_BITSIZE (GET_MODE (x
))));
1433 /* Don't call nonzero_bits if it cannot change anything. */
1434 if (reg_stat
[REGNO (x
)].nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1435 reg_stat
[REGNO (x
)].nonzero_bits
1436 |= nonzero_bits (src
, nonzero_bits_mode
);
1437 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1438 if (reg_stat
[REGNO (x
)].sign_bit_copies
== 0
1439 || reg_stat
[REGNO (x
)].sign_bit_copies
> num
)
1440 reg_stat
[REGNO (x
)].sign_bit_copies
= num
;
1444 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1445 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
1450 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1451 insns that were previously combined into I3 or that will be combined
1452 into the merger of INSN and I3.
1454 Return 0 if the combination is not allowed for any reason.
1456 If the combination is allowed, *PDEST will be set to the single
1457 destination of INSN and *PSRC to the single source, and this function
1461 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
1462 rtx
*pdest
, rtx
*psrc
)
1465 rtx set
= 0, src
, dest
;
1470 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
1471 && next_active_insn (succ
) == i3
)
1472 : next_active_insn (insn
) == i3
);
1474 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1475 or a PARALLEL consisting of such a SET and CLOBBERs.
1477 If INSN has CLOBBER parallel parts, ignore them for our processing.
1478 By definition, these happen during the execution of the insn. When it
1479 is merged with another insn, all bets are off. If they are, in fact,
1480 needed and aren't also supplied in I3, they may be added by
1481 recog_for_combine. Otherwise, it won't match.
1483 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1486 Get the source and destination of INSN. If more than one, can't
1489 if (GET_CODE (PATTERN (insn
)) == SET
)
1490 set
= PATTERN (insn
);
1491 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1492 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1494 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1496 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1499 switch (GET_CODE (elt
))
1501 /* This is important to combine floating point insns
1502 for the SH4 port. */
1504 /* Combining an isolated USE doesn't make sense.
1505 We depend here on combinable_i3pat to reject them. */
1506 /* The code below this loop only verifies that the inputs of
1507 the SET in INSN do not change. We call reg_set_between_p
1508 to verify that the REG in the USE does not change between
1510 If the USE in INSN was for a pseudo register, the matching
1511 insn pattern will likely match any register; combining this
1512 with any other USE would only be safe if we knew that the
1513 used registers have identical values, or if there was
1514 something to tell them apart, e.g. different modes. For
1515 now, we forgo such complicated tests and simply disallow
1516 combining of USES of pseudo registers with any other USE. */
1517 if (REG_P (XEXP (elt
, 0))
1518 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1520 rtx i3pat
= PATTERN (i3
);
1521 int i
= XVECLEN (i3pat
, 0) - 1;
1522 unsigned int regno
= REGNO (XEXP (elt
, 0));
1526 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1528 if (GET_CODE (i3elt
) == USE
1529 && REG_P (XEXP (i3elt
, 0))
1530 && (REGNO (XEXP (i3elt
, 0)) == regno
1531 ? reg_set_between_p (XEXP (elt
, 0),
1532 PREV_INSN (insn
), i3
)
1533 : regno
>= FIRST_PSEUDO_REGISTER
))
1540 /* We can ignore CLOBBERs. */
1545 /* Ignore SETs whose result isn't used but not those that
1546 have side-effects. */
1547 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1548 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1549 || INTVAL (XEXP (note
, 0)) <= 0)
1550 && ! side_effects_p (elt
))
1553 /* If we have already found a SET, this is a second one and
1554 so we cannot combine with this insn. */
1562 /* Anything else means we can't combine. */
1568 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1569 so don't do anything with it. */
1570 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1579 set
= expand_field_assignment (set
);
1580 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1582 /* Don't eliminate a store in the stack pointer. */
1583 if (dest
== stack_pointer_rtx
1584 /* Don't combine with an insn that sets a register to itself if it has
1585 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1586 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1587 /* Can't merge an ASM_OPERANDS. */
1588 || GET_CODE (src
) == ASM_OPERANDS
1589 /* Can't merge a function call. */
1590 || GET_CODE (src
) == CALL
1591 /* Don't eliminate a function call argument. */
1593 && (find_reg_fusage (i3
, USE
, dest
)
1595 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1596 && global_regs
[REGNO (dest
)])))
1597 /* Don't substitute into an incremented register. */
1598 || FIND_REG_INC_NOTE (i3
, dest
)
1599 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1600 /* Don't substitute into a non-local goto, this confuses CFG. */
1601 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1603 /* Don't combine the end of a libcall into anything. */
1604 /* ??? This gives worse code, and appears to be unnecessary, since no
1605 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1606 use REG_RETVAL notes for noconflict blocks, but other code here
1607 makes sure that those insns don't disappear. */
1608 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1610 /* Make sure that DEST is not used after SUCC but before I3. */
1611 || (succ
&& ! all_adjacent
1612 && reg_used_between_p (dest
, succ
, i3
))
1613 /* Make sure that the value that is to be substituted for the register
1614 does not use any registers whose values alter in between. However,
1615 If the insns are adjacent, a use can't cross a set even though we
1616 think it might (this can happen for a sequence of insns each setting
1617 the same destination; last_set of that register might point to
1618 a NOTE). If INSN has a REG_EQUIV note, the register is always
1619 equivalent to the memory so the substitution is valid even if there
1620 are intervening stores. Also, don't move a volatile asm or
1621 UNSPEC_VOLATILE across any other insns. */
1624 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1625 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1626 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1627 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1628 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1629 better register allocation by not doing the combine. */
1630 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1631 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1632 /* Don't combine across a CALL_INSN, because that would possibly
1633 change whether the life span of some REGs crosses calls or not,
1634 and it is a pain to update that information.
1635 Exception: if source is a constant, moving it later can't hurt.
1636 Accept that special case, because it helps -fforce-addr a lot. */
1637 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1640 /* DEST must either be a REG or CC0. */
1643 /* If register alignment is being enforced for multi-word items in all
1644 cases except for parameters, it is possible to have a register copy
1645 insn referencing a hard register that is not allowed to contain the
1646 mode being copied and which would not be valid as an operand of most
1647 insns. Eliminate this problem by not combining with such an insn.
1649 Also, on some machines we don't want to extend the life of a hard
1653 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1654 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1655 /* Don't extend the life of a hard register unless it is
1656 user variable (if we have few registers) or it can't
1657 fit into the desired register (meaning something special
1659 Also avoid substituting a return register into I3, because
1660 reload can't handle a conflict with constraints of other
1662 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1663 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1666 else if (GET_CODE (dest
) != CC0
)
1670 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1671 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1672 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1674 /* Don't substitute for a register intended as a clobberable
1676 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1677 if (rtx_equal_p (reg
, dest
))
1680 /* If the clobber represents an earlyclobber operand, we must not
1681 substitute an expression containing the clobbered register.
1682 As we do not analyze the constraint strings here, we have to
1683 make the conservative assumption. However, if the register is
1684 a fixed hard reg, the clobber cannot represent any operand;
1685 we leave it up to the machine description to either accept or
1686 reject use-and-clobber patterns. */
1688 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1689 || !fixed_regs
[REGNO (reg
)])
1690 if (reg_overlap_mentioned_p (reg
, src
))
1694 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1695 or not), reject, unless nothing volatile comes between it and I3 */
1697 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1699 /* Make sure succ doesn't contain a volatile reference. */
1700 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1703 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1704 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1708 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1709 to be an explicit register variable, and was chosen for a reason. */
1711 if (GET_CODE (src
) == ASM_OPERANDS
1712 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1715 /* If there are any volatile insns between INSN and I3, reject, because
1716 they might affect machine state. */
1718 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1719 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1722 /* If INSN contains an autoincrement or autodecrement, make sure that
1723 register is not used between there and I3, and not already used in
1724 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1725 Also insist that I3 not be a jump; if it were one
1726 and the incremented register were spilled, we would lose. */
1729 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1730 if (REG_NOTE_KIND (link
) == REG_INC
1732 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1733 || (pred
!= NULL_RTX
1734 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1735 || (succ
!= NULL_RTX
1736 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1737 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1742 /* Don't combine an insn that follows a CC0-setting insn.
1743 An insn that uses CC0 must not be separated from the one that sets it.
1744 We do, however, allow I2 to follow a CC0-setting insn if that insn
1745 is passed as I1; in that case it will be deleted also.
1746 We also allow combining in this case if all the insns are adjacent
1747 because that would leave the two CC0 insns adjacent as well.
1748 It would be more logical to test whether CC0 occurs inside I1 or I2,
1749 but that would be much slower, and this ought to be equivalent. */
1751 p
= prev_nonnote_insn (insn
);
1752 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1757 /* If we get here, we have passed all the tests and the combination is
1766 /* LOC is the location within I3 that contains its pattern or the component
1767 of a PARALLEL of the pattern. We validate that it is valid for combining.
1769 One problem is if I3 modifies its output, as opposed to replacing it
1770 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1771 so would produce an insn that is not equivalent to the original insns.
1775 (set (reg:DI 101) (reg:DI 100))
1776 (set (subreg:SI (reg:DI 101) 0) <foo>)
1778 This is NOT equivalent to:
1780 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1781 (set (reg:DI 101) (reg:DI 100))])
1783 Not only does this modify 100 (in which case it might still be valid
1784 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1786 We can also run into a problem if I2 sets a register that I1
1787 uses and I1 gets directly substituted into I3 (not via I2). In that
1788 case, we would be getting the wrong value of I2DEST into I3, so we
1789 must reject the combination. This case occurs when I2 and I1 both
1790 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1791 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1792 of a SET must prevent combination from occurring.
1794 Before doing the above check, we first try to expand a field assignment
1795 into a set of logical operations.
1797 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1798 we place a register that is both set and used within I3. If more than one
1799 such register is detected, we fail.
1801 Return 1 if the combination is valid, zero otherwise. */
1804 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1805 int i1_not_in_src
, rtx
*pi3dest_killed
)
1809 if (GET_CODE (x
) == SET
)
1812 rtx dest
= SET_DEST (set
);
1813 rtx src
= SET_SRC (set
);
1814 rtx inner_dest
= dest
;
1817 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1818 || GET_CODE (inner_dest
) == SUBREG
1819 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1820 inner_dest
= XEXP (inner_dest
, 0);
1822 /* Check for the case where I3 modifies its output, as discussed
1823 above. We don't want to prevent pseudos from being combined
1824 into the address of a MEM, so only prevent the combination if
1825 i1 or i2 set the same MEM. */
1826 if ((inner_dest
!= dest
&&
1827 (!MEM_P (inner_dest
)
1828 || rtx_equal_p (i2dest
, inner_dest
)
1829 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1830 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1831 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1833 /* This is the same test done in can_combine_p except we can't test
1834 all_adjacent; we don't have to, since this instruction will stay
1835 in place, thus we are not considering increasing the lifetime of
1838 Also, if this insn sets a function argument, combining it with
1839 something that might need a spill could clobber a previous
1840 function argument; the all_adjacent test in can_combine_p also
1841 checks this; here, we do a more specific test for this case. */
1843 || (REG_P (inner_dest
)
1844 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1845 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1846 GET_MODE (inner_dest
))))
1847 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1850 /* If DEST is used in I3, it is being killed in this insn, so
1851 record that for later. We have to consider paradoxical
1852 subregs here, since they kill the whole register, but we
1853 ignore partial subregs, STRICT_LOW_PART, etc.
1854 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1855 STACK_POINTER_REGNUM, since these are always considered to be
1856 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1858 if (GET_CODE (subdest
) == SUBREG
1859 && (GET_MODE_SIZE (GET_MODE (subdest
))
1860 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
1861 subdest
= SUBREG_REG (subdest
);
1864 && reg_referenced_p (subdest
, PATTERN (i3
))
1865 && REGNO (subdest
) != FRAME_POINTER_REGNUM
1866 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1867 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
1869 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1870 && (REGNO (subdest
) != ARG_POINTER_REGNUM
1871 || ! fixed_regs
[REGNO (subdest
)])
1873 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
1875 if (*pi3dest_killed
)
1878 *pi3dest_killed
= subdest
;
1882 else if (GET_CODE (x
) == PARALLEL
)
1886 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1887 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1888 i1_not_in_src
, pi3dest_killed
))
1895 /* Return 1 if X is an arithmetic expression that contains a multiplication
1896 and division. We don't count multiplications by powers of two here. */
1899 contains_muldiv (rtx x
)
1901 switch (GET_CODE (x
))
1903 case MOD
: case DIV
: case UMOD
: case UDIV
:
1907 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1908 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1911 return contains_muldiv (XEXP (x
, 0))
1912 || contains_muldiv (XEXP (x
, 1));
1915 return contains_muldiv (XEXP (x
, 0));
1921 /* Determine whether INSN can be used in a combination. Return nonzero if
1922 not. This is used in try_combine to detect early some cases where we
1923 can't perform combinations. */
1926 cant_combine_insn_p (rtx insn
)
1931 /* If this isn't really an insn, we can't do anything.
1932 This can occur when flow deletes an insn that it has merged into an
1933 auto-increment address. */
1934 if (! INSN_P (insn
))
1937 /* Never combine loads and stores involving hard regs that are likely
1938 to be spilled. The register allocator can usually handle such
1939 reg-reg moves by tying. If we allow the combiner to make
1940 substitutions of likely-spilled regs, reload might die.
1941 As an exception, we allow combinations involving fixed regs; these are
1942 not available to the register allocator so there's no risk involved. */
1944 set
= single_set (insn
);
1947 src
= SET_SRC (set
);
1948 dest
= SET_DEST (set
);
1949 if (GET_CODE (src
) == SUBREG
)
1950 src
= SUBREG_REG (src
);
1951 if (GET_CODE (dest
) == SUBREG
)
1952 dest
= SUBREG_REG (dest
);
1953 if (REG_P (src
) && REG_P (dest
)
1954 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1955 && ! fixed_regs
[REGNO (src
)]
1956 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1957 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1958 && ! fixed_regs
[REGNO (dest
)]
1959 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1965 struct likely_spilled_retval_info
1967 unsigned regno
, nregs
;
1971 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
1972 hard registers that are known to be written to / clobbered in full. */
1974 likely_spilled_retval_1 (rtx x
, rtx set
, void *data
)
1976 struct likely_spilled_retval_info
*info
= data
;
1977 unsigned regno
, nregs
;
1980 if (!REG_P (XEXP (set
, 0)))
1983 if (regno
>= info
->regno
+ info
->nregs
)
1985 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
1986 if (regno
+ nregs
<= info
->regno
)
1988 new_mask
= (2U << (nregs
- 1)) - 1;
1989 if (regno
< info
->regno
)
1990 new_mask
>>= info
->regno
- regno
;
1992 new_mask
<<= regno
- info
->regno
;
1993 info
->mask
&= ~new_mask
;
1996 /* Return nonzero iff part of the return value is live during INSN, and
1997 it is likely spilled. This can happen when more than one insn is needed
1998 to copy the return value, e.g. when we consider to combine into the
1999 second copy insn for a complex value. */
2002 likely_spilled_retval_p (rtx insn
)
2004 rtx use
= BB_END (this_basic_block
);
2006 unsigned regno
, nregs
;
2007 /* We assume here that no machine mode needs more than
2008 32 hard registers when the value overlaps with a register
2009 for which FUNCTION_VALUE_REGNO_P is true. */
2011 struct likely_spilled_retval_info info
;
2013 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2015 reg
= XEXP (PATTERN (use
), 0);
2016 if (!REG_P (reg
) || !FUNCTION_VALUE_REGNO_P (REGNO (reg
)))
2018 regno
= REGNO (reg
);
2019 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2022 mask
= (2U << (nregs
- 1)) - 1;
2024 /* Disregard parts of the return value that are set later. */
2028 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2030 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2033 /* Check if any of the (probably) live return value registers is
2038 if ((mask
& 1 << nregs
)
2039 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno
+ nregs
)))
2045 /* Adjust INSN after we made a change to its destination.
2047 Changing the destination can invalidate notes that say something about
2048 the results of the insn and a LOG_LINK pointing to the insn. */
2051 adjust_for_new_dest (rtx insn
)
2053 /* For notes, be conservative and simply remove them. */
2054 remove_reg_equal_equiv_notes (insn
);
2056 /* The new insn will have a destination that was previously the destination
2057 of an insn just above it. Call distribute_links to make a LOG_LINK from
2058 the next use of that destination. */
2059 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
2062 /* Return TRUE if combine can reuse reg X in mode MODE.
2063 ADDED_SETS is nonzero if the original set is still required. */
2065 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2073 /* Allow hard registers if the new mode is legal, and occupies no more
2074 registers than the old mode. */
2075 if (regno
< FIRST_PSEUDO_REGISTER
)
2076 return (HARD_REGNO_MODE_OK (regno
, mode
)
2077 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2078 >= hard_regno_nregs
[regno
][mode
]));
2080 /* Or a pseudo that is only used once. */
2081 return (REG_N_SETS (regno
) == 1 && !added_sets
2082 && !REG_USERVAR_P (x
));
2086 /* Check whether X, the destination of a set, refers to part of
2087 the register specified by REG. */
2090 reg_subword_p (rtx x
, rtx reg
)
2092 /* Check that reg is an integer mode register. */
2093 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2096 if (GET_CODE (x
) == STRICT_LOW_PART
2097 || GET_CODE (x
) == ZERO_EXTRACT
)
2100 return GET_CODE (x
) == SUBREG
2101 && SUBREG_REG (x
) == reg
2102 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2106 /* Try to combine the insns I1 and I2 into I3.
2107 Here I1 and I2 appear earlier than I3.
2108 I1 can be zero; then we combine just I2 into I3.
2110 If we are combining three insns and the resulting insn is not recognized,
2111 try splitting it into two insns. If that happens, I2 and I3 are retained
2112 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2115 Return 0 if the combination does not work. Then nothing is changed.
2116 If we did the combination, return the insn at which combine should
2119 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2120 new direct jump instruction. */
2123 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
2125 /* New patterns for I3 and I2, respectively. */
2126 rtx newpat
, newi2pat
= 0;
2127 rtvec newpat_vec_with_clobbers
= 0;
2128 int substed_i2
= 0, substed_i1
= 0;
2129 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2130 int added_sets_1
, added_sets_2
;
2131 /* Total number of SETs to put into I3. */
2133 /* Nonzero if I2's body now appears in I3. */
2135 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2136 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2137 /* Contains I3 if the destination of I3 is used in its source, which means
2138 that the old life of I3 is being killed. If that usage is placed into
2139 I2 and not in I3, a REG_DEAD note must be made. */
2140 rtx i3dest_killed
= 0;
2141 /* SET_DEST and SET_SRC of I2 and I1. */
2142 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
2143 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2144 rtx i1pat
= 0, i2pat
= 0;
2145 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2146 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2147 int i2dest_killed
= 0, i1dest_killed
= 0;
2148 int i1_feeds_i3
= 0;
2149 /* Notes that must be added to REG_NOTES in I3 and I2. */
2150 rtx new_i3_notes
, new_i2_notes
;
2151 /* Notes that we substituted I3 into I2 instead of the normal case. */
2152 int i3_subst_into_i2
= 0;
2153 /* Notes that I1, I2 or I3 is a MULT operation. */
2162 /* Exit early if one of the insns involved can't be used for
2164 if (cant_combine_insn_p (i3
)
2165 || cant_combine_insn_p (i2
)
2166 || (i1
&& cant_combine_insn_p (i1
))
2167 || likely_spilled_retval_p (i3
)
2168 /* We also can't do anything if I3 has a
2169 REG_LIBCALL note since we don't want to disrupt the contiguity of a
2172 /* ??? This gives worse code, and appears to be unnecessary, since no
2173 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
2174 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
2180 undobuf
.other_insn
= 0;
2182 /* Reset the hard register usage information. */
2183 CLEAR_HARD_REG_SET (newpat_used_regs
);
2185 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2186 code below, set I1 to be the earlier of the two insns. */
2187 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2188 temp
= i1
, i1
= i2
, i2
= temp
;
2190 added_links_insn
= 0;
2192 /* First check for one important special-case that the code below will
2193 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2194 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2195 we may be able to replace that destination with the destination of I3.
2196 This occurs in the common code where we compute both a quotient and
2197 remainder into a structure, in which case we want to do the computation
2198 directly into the structure to avoid register-register copies.
2200 Note that this case handles both multiple sets in I2 and also
2201 cases where I2 has a number of CLOBBER or PARALLELs.
2203 We make very conservative checks below and only try to handle the
2204 most common cases of this. For example, we only handle the case
2205 where I2 and I3 are adjacent to avoid making difficult register
2208 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2209 && REG_P (SET_SRC (PATTERN (i3
)))
2210 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2211 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2212 && GET_CODE (PATTERN (i2
)) == PARALLEL
2213 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2214 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2215 below would need to check what is inside (and reg_overlap_mentioned_p
2216 doesn't support those codes anyway). Don't allow those destinations;
2217 the resulting insn isn't likely to be recognized anyway. */
2218 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2219 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2220 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2221 SET_DEST (PATTERN (i3
)))
2222 && next_real_insn (i2
) == i3
)
2224 rtx p2
= PATTERN (i2
);
2226 /* Make sure that the destination of I3,
2227 which we are going to substitute into one output of I2,
2228 is not used within another output of I2. We must avoid making this:
2229 (parallel [(set (mem (reg 69)) ...)
2230 (set (reg 69) ...)])
2231 which is not well-defined as to order of actions.
2232 (Besides, reload can't handle output reloads for this.)
2234 The problem can also happen if the dest of I3 is a memory ref,
2235 if another dest in I2 is an indirect memory ref. */
2236 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2237 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2238 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2239 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2240 SET_DEST (XVECEXP (p2
, 0, i
))))
2243 if (i
== XVECLEN (p2
, 0))
2244 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2245 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2246 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2247 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2252 subst_low_luid
= DF_INSN_LUID (i2
);
2254 added_sets_2
= added_sets_1
= 0;
2255 i2dest
= SET_SRC (PATTERN (i3
));
2256 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2258 /* Replace the dest in I2 with our dest and make the resulting
2259 insn the new pattern for I3. Then skip to where we
2260 validate the pattern. Everything was set up above. */
2261 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
2262 SET_DEST (PATTERN (i3
)));
2265 i3_subst_into_i2
= 1;
2266 goto validate_replacement
;
2270 /* If I2 is setting a pseudo to a constant and I3 is setting some
2271 sub-part of it to another constant, merge them by making a new
2274 && (temp
= single_set (i2
)) != 0
2275 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
2276 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
2277 && GET_CODE (PATTERN (i3
)) == SET
2278 && (GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
2279 || GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_DOUBLE
)
2280 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2282 rtx dest
= SET_DEST (PATTERN (i3
));
2286 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2288 if (GET_CODE (XEXP (dest
, 1)) == CONST_INT
2289 && GET_CODE (XEXP (dest
, 2)) == CONST_INT
)
2291 width
= INTVAL (XEXP (dest
, 1));
2292 offset
= INTVAL (XEXP (dest
, 2));
2293 dest
= XEXP (dest
, 0);
2294 if (BITS_BIG_ENDIAN
)
2295 offset
= GET_MODE_BITSIZE (GET_MODE (dest
)) - width
- offset
;
2300 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2301 dest
= XEXP (dest
, 0);
2302 width
= GET_MODE_BITSIZE (GET_MODE (dest
));
2308 /* If this is the low part, we're done. */
2309 if (subreg_lowpart_p (dest
))
2311 /* Handle the case where inner is twice the size of outer. */
2312 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2313 == 2 * GET_MODE_BITSIZE (GET_MODE (dest
)))
2314 offset
+= GET_MODE_BITSIZE (GET_MODE (dest
));
2315 /* Otherwise give up for now. */
2321 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2322 <= HOST_BITS_PER_WIDE_INT
* 2))
2324 HOST_WIDE_INT mhi
, ohi
, ihi
;
2325 HOST_WIDE_INT mlo
, olo
, ilo
;
2326 rtx inner
= SET_SRC (PATTERN (i3
));
2327 rtx outer
= SET_SRC (temp
);
2329 if (GET_CODE (outer
) == CONST_INT
)
2331 olo
= INTVAL (outer
);
2332 ohi
= olo
< 0 ? -1 : 0;
2336 olo
= CONST_DOUBLE_LOW (outer
);
2337 ohi
= CONST_DOUBLE_HIGH (outer
);
2340 if (GET_CODE (inner
) == CONST_INT
)
2342 ilo
= INTVAL (inner
);
2343 ihi
= ilo
< 0 ? -1 : 0;
2347 ilo
= CONST_DOUBLE_LOW (inner
);
2348 ihi
= CONST_DOUBLE_HIGH (inner
);
2351 if (width
< HOST_BITS_PER_WIDE_INT
)
2353 mlo
= ((unsigned HOST_WIDE_INT
) 1 << width
) - 1;
2356 else if (width
< HOST_BITS_PER_WIDE_INT
* 2)
2358 mhi
= ((unsigned HOST_WIDE_INT
) 1
2359 << (width
- HOST_BITS_PER_WIDE_INT
)) - 1;
2371 if (offset
>= HOST_BITS_PER_WIDE_INT
)
2373 mhi
= mlo
<< (offset
- HOST_BITS_PER_WIDE_INT
);
2375 ihi
= ilo
<< (offset
- HOST_BITS_PER_WIDE_INT
);
2378 else if (offset
> 0)
2380 mhi
= (mhi
<< offset
) | ((unsigned HOST_WIDE_INT
) mlo
2381 >> (HOST_BITS_PER_WIDE_INT
- offset
));
2382 mlo
= mlo
<< offset
;
2383 ihi
= (ihi
<< offset
) | ((unsigned HOST_WIDE_INT
) ilo
2384 >> (HOST_BITS_PER_WIDE_INT
- offset
));
2385 ilo
= ilo
<< offset
;
2388 olo
= (olo
& ~mlo
) | ilo
;
2389 ohi
= (ohi
& ~mhi
) | ihi
;
2393 subst_low_luid
= DF_INSN_LUID (i2
);
2394 added_sets_2
= added_sets_1
= 0;
2395 i2dest
= SET_DEST (temp
);
2396 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2398 SUBST (SET_SRC (temp
),
2399 immed_double_const (olo
, ohi
, GET_MODE (SET_DEST (temp
))));
2401 newpat
= PATTERN (i2
);
2402 goto validate_replacement
;
2407 /* If we have no I1 and I2 looks like:
2408 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2410 make up a dummy I1 that is
2413 (set (reg:CC X) (compare:CC Y (const_int 0)))
2415 (We can ignore any trailing CLOBBERs.)
2417 This undoes a previous combination and allows us to match a branch-and-
2420 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2421 && XVECLEN (PATTERN (i2
), 0) >= 2
2422 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2423 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2425 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2426 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2427 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2428 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2429 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2430 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2432 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2433 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2438 /* We make I1 with the same INSN_UID as I2. This gives it
2439 the same DF_INSN_LUID for value tracking. Our fake I1 will
2440 never appear in the insn stream so giving it the same INSN_UID
2441 as I2 will not cause a problem. */
2443 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2444 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
2445 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
);
2447 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2448 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2449 SET_DEST (PATTERN (i1
)));
2454 /* Verify that I2 and I1 are valid for combining. */
2455 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
2456 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
2462 /* Record whether I2DEST is used in I2SRC and similarly for the other
2463 cases. Knowing this will help in register status updating below. */
2464 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2465 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2466 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2467 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2468 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2470 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2472 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
2474 /* Ensure that I3's pattern can be the destination of combines. */
2475 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
2476 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
2483 /* See if any of the insns is a MULT operation. Unless one is, we will
2484 reject a combination that is, since it must be slower. Be conservative
2486 if (GET_CODE (i2src
) == MULT
2487 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2488 || (GET_CODE (PATTERN (i3
)) == SET
2489 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2492 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2493 We used to do this EXCEPT in one case: I3 has a post-inc in an
2494 output operand. However, that exception can give rise to insns like
2496 which is a famous insn on the PDP-11 where the value of r3 used as the
2497 source was model-dependent. Avoid this sort of thing. */
2500 if (!(GET_CODE (PATTERN (i3
)) == SET
2501 && REG_P (SET_SRC (PATTERN (i3
)))
2502 && MEM_P (SET_DEST (PATTERN (i3
)))
2503 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2504 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2505 /* It's not the exception. */
2508 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2509 if (REG_NOTE_KIND (link
) == REG_INC
2510 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2512 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2519 /* See if the SETs in I1 or I2 need to be kept around in the merged
2520 instruction: whenever the value set there is still needed past I3.
2521 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2523 For the SET in I1, we have two cases: If I1 and I2 independently
2524 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2525 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2526 in I1 needs to be kept around unless I1DEST dies or is set in either
2527 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2528 I1DEST. If so, we know I1 feeds into I2. */
2530 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
2533 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
2534 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
2536 /* If the set in I2 needs to be kept around, we must make a copy of
2537 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2538 PATTERN (I2), we are only substituting for the original I1DEST, not into
2539 an already-substituted copy. This also prevents making self-referential
2540 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2545 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2546 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2548 i2pat
= copy_rtx (PATTERN (i2
));
2553 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2554 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2556 i1pat
= copy_rtx (PATTERN (i1
));
2561 /* Substitute in the latest insn for the regs set by the earlier ones. */
2563 maxreg
= max_reg_num ();
2568 /* Many machines that don't use CC0 have insns that can both perform an
2569 arithmetic operation and set the condition code. These operations will
2570 be represented as a PARALLEL with the first element of the vector
2571 being a COMPARE of an arithmetic operation with the constant zero.
2572 The second element of the vector will set some pseudo to the result
2573 of the same arithmetic operation. If we simplify the COMPARE, we won't
2574 match such a pattern and so will generate an extra insn. Here we test
2575 for this case, where both the comparison and the operation result are
2576 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2577 I2SRC. Later we will make the PARALLEL that contains I2. */
2579 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2580 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2581 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
2582 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2584 #ifdef SELECT_CC_MODE
2586 enum machine_mode compare_mode
;
2589 newpat
= PATTERN (i3
);
2590 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
2594 #ifdef SELECT_CC_MODE
2595 /* See if a COMPARE with the operand we substituted in should be done
2596 with the mode that is currently being used. If not, do the same
2597 processing we do in `subst' for a SET; namely, if the destination
2598 is used only once, try to replace it with a register of the proper
2599 mode and also replace the COMPARE. */
2600 if (undobuf
.other_insn
== 0
2601 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
2602 &undobuf
.other_insn
))
2603 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
2605 != GET_MODE (SET_DEST (newpat
))))
2607 if (can_change_dest_mode(SET_DEST (newpat
), added_sets_2
,
2610 unsigned int regno
= REGNO (SET_DEST (newpat
));
2613 if (regno
< FIRST_PSEUDO_REGISTER
)
2614 new_dest
= gen_rtx_REG (compare_mode
, regno
);
2617 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
2618 new_dest
= regno_reg_rtx
[regno
];
2621 SUBST (SET_DEST (newpat
), new_dest
);
2622 SUBST (XEXP (*cc_use
, 0), new_dest
);
2623 SUBST (SET_SRC (newpat
),
2624 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
2627 undobuf
.other_insn
= 0;
2634 /* It is possible that the source of I2 or I1 may be performing
2635 an unneeded operation, such as a ZERO_EXTEND of something
2636 that is known to have the high part zero. Handle that case
2637 by letting subst look at the innermost one of them.
2639 Another way to do this would be to have a function that tries
2640 to simplify a single insn instead of merging two or more
2641 insns. We don't do this because of the potential of infinite
2642 loops and because of the potential extra memory required.
2643 However, doing it the way we are is a bit of a kludge and
2644 doesn't catch all cases.
2646 But only do this if -fexpensive-optimizations since it slows
2647 things down and doesn't usually win.
2649 This is not done in the COMPARE case above because the
2650 unmodified I2PAT is used in the PARALLEL and so a pattern
2651 with a modified I2SRC would not match. */
2653 if (flag_expensive_optimizations
)
2655 /* Pass pc_rtx so no substitutions are done, just
2659 subst_low_luid
= DF_INSN_LUID (i1
);
2660 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
2664 subst_low_luid
= DF_INSN_LUID (i2
);
2665 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
2669 n_occurrences
= 0; /* `subst' counts here */
2671 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2672 need to make a unique copy of I2SRC each time we substitute it
2673 to avoid self-referential rtl. */
2675 subst_low_luid
= DF_INSN_LUID (i2
);
2676 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
2677 ! i1_feeds_i3
&& i1dest_in_i1src
);
2680 /* Record whether i2's body now appears within i3's body. */
2681 i2_is_used
= n_occurrences
;
2684 /* If we already got a failure, don't try to do more. Otherwise,
2685 try to substitute in I1 if we have it. */
2687 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
2689 /* Before we can do this substitution, we must redo the test done
2690 above (see detailed comments there) that ensures that I1DEST
2691 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2693 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
2701 subst_low_luid
= DF_INSN_LUID (i1
);
2702 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2706 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2707 to count all the ways that I2SRC and I1SRC can be used. */
2708 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2709 && i2_is_used
+ added_sets_2
> 1)
2710 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2711 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2713 /* Fail if we tried to make a new register. */
2714 || max_reg_num () != maxreg
2715 /* Fail if we couldn't do something and have a CLOBBER. */
2716 || GET_CODE (newpat
) == CLOBBER
2717 /* Fail if this new pattern is a MULT and we didn't have one before
2718 at the outer level. */
2719 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2726 /* If the actions of the earlier insns must be kept
2727 in addition to substituting them into the latest one,
2728 we must make a new PARALLEL for the latest insn
2729 to hold additional the SETs. */
2731 if (added_sets_1
|| added_sets_2
)
2735 if (GET_CODE (newpat
) == PARALLEL
)
2737 rtvec old
= XVEC (newpat
, 0);
2738 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2739 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2740 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2741 sizeof (old
->elem
[0]) * old
->num_elem
);
2746 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2747 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2748 XVECEXP (newpat
, 0, 0) = old
;
2752 XVECEXP (newpat
, 0, --total_sets
) = i1pat
;
2756 /* If there is no I1, use I2's body as is. We used to also not do
2757 the subst call below if I2 was substituted into I3,
2758 but that could lose a simplification. */
2760 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2762 /* See comment where i2pat is assigned. */
2763 XVECEXP (newpat
, 0, --total_sets
)
2764 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2768 /* We come here when we are replacing a destination in I2 with the
2769 destination of I3. */
2770 validate_replacement
:
2772 /* Note which hard regs this insn has as inputs. */
2773 mark_used_regs_combine (newpat
);
2775 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2776 consider splitting this pattern, we might need these clobbers. */
2777 if (i1
&& GET_CODE (newpat
) == PARALLEL
2778 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
2780 int len
= XVECLEN (newpat
, 0);
2782 newpat_vec_with_clobbers
= rtvec_alloc (len
);
2783 for (i
= 0; i
< len
; i
++)
2784 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
2787 /* Is the result of combination a valid instruction? */
2788 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2790 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2791 the second SET's destination is a register that is unused and isn't
2792 marked as an instruction that might trap in an EH region. In that case,
2793 we just need the first SET. This can occur when simplifying a divmod
2794 insn. We *must* test for this case here because the code below that
2795 splits two independent SETs doesn't handle this case correctly when it
2796 updates the register status.
2798 It's pointless doing this if we originally had two sets, one from
2799 i3, and one from i2. Combining then splitting the parallel results
2800 in the original i2 again plus an invalid insn (which we delete).
2801 The net effect is only to move instructions around, which makes
2802 debug info less accurate.
2804 Also check the case where the first SET's destination is unused.
2805 That would not cause incorrect code, but does cause an unneeded
2808 if (insn_code_number
< 0
2809 && !(added_sets_2
&& i1
== 0)
2810 && GET_CODE (newpat
) == PARALLEL
2811 && XVECLEN (newpat
, 0) == 2
2812 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2813 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2814 && asm_noperands (newpat
) < 0)
2816 rtx set0
= XVECEXP (newpat
, 0, 0);
2817 rtx set1
= XVECEXP (newpat
, 0, 1);
2820 if (((REG_P (SET_DEST (set1
))
2821 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2822 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2823 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2824 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2825 || INTVAL (XEXP (note
, 0)) <= 0)
2826 && ! side_effects_p (SET_SRC (set1
)))
2829 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2832 else if (((REG_P (SET_DEST (set0
))
2833 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2834 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2835 && find_reg_note (i3
, REG_UNUSED
,
2836 SUBREG_REG (SET_DEST (set0
)))))
2837 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2838 || INTVAL (XEXP (note
, 0)) <= 0)
2839 && ! side_effects_p (SET_SRC (set0
)))
2842 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2844 if (insn_code_number
>= 0)
2846 /* If we will be able to accept this, we have made a
2847 change to the destination of I3. This requires us to
2848 do a few adjustments. */
2850 PATTERN (i3
) = newpat
;
2851 adjust_for_new_dest (i3
);
2856 /* If we were combining three insns and the result is a simple SET
2857 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2858 insns. There are two ways to do this. It can be split using a
2859 machine-specific method (like when you have an addition of a large
2860 constant) or by combine in the function find_split_point. */
2862 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2863 && asm_noperands (newpat
) < 0)
2865 rtx m_split
, *split
;
2867 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2868 use I2DEST as a scratch register will help. In the latter case,
2869 convert I2DEST to the mode of the source of NEWPAT if we can. */
2871 m_split
= split_insns (newpat
, i3
);
2873 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2874 inputs of NEWPAT. */
2876 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2877 possible to try that as a scratch reg. This would require adding
2878 more code to make it work though. */
2880 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
2882 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
2884 /* First try to split using the original register as a
2885 scratch register. */
2886 m_split
= split_insns (gen_rtx_PARALLEL
2888 gen_rtvec (2, newpat
,
2889 gen_rtx_CLOBBER (VOIDmode
,
2893 /* If that didn't work, try changing the mode of I2DEST if
2896 && new_mode
!= GET_MODE (i2dest
)
2897 && new_mode
!= VOIDmode
2898 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
2900 enum machine_mode old_mode
= GET_MODE (i2dest
);
2903 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
2904 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
2907 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
2908 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
2911 m_split
= split_insns (gen_rtx_PARALLEL
2913 gen_rtvec (2, newpat
,
2914 gen_rtx_CLOBBER (VOIDmode
,
2919 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2923 PUT_MODE (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
2924 buf
= undobuf
.undos
;
2925 undobuf
.undos
= buf
->next
;
2926 buf
->next
= undobuf
.frees
;
2927 undobuf
.frees
= buf
;
2932 /* If recog_for_combine has discarded clobbers, try to use them
2933 again for the split. */
2934 if (m_split
== 0 && newpat_vec_with_clobbers
)
2936 = split_insns (gen_rtx_PARALLEL (VOIDmode
,
2937 newpat_vec_with_clobbers
), i3
);
2939 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2941 m_split
= PATTERN (m_split
);
2942 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2943 if (insn_code_number
>= 0)
2946 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2947 && (next_real_insn (i2
) == i3
2948 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
2951 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2952 newi2pat
= PATTERN (m_split
);
2954 i3set
= single_set (NEXT_INSN (m_split
));
2955 i2set
= single_set (m_split
);
2957 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2959 /* If I2 or I3 has multiple SETs, we won't know how to track
2960 register status, so don't use these insns. If I2's destination
2961 is used between I2 and I3, we also can't use these insns. */
2963 if (i2_code_number
>= 0 && i2set
&& i3set
2964 && (next_real_insn (i2
) == i3
2965 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2966 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2968 if (insn_code_number
>= 0)
2971 /* It is possible that both insns now set the destination of I3.
2972 If so, we must show an extra use of it. */
2974 if (insn_code_number
>= 0)
2976 rtx new_i3_dest
= SET_DEST (i3set
);
2977 rtx new_i2_dest
= SET_DEST (i2set
);
2979 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2980 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2981 || GET_CODE (new_i3_dest
) == SUBREG
)
2982 new_i3_dest
= XEXP (new_i3_dest
, 0);
2984 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2985 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2986 || GET_CODE (new_i2_dest
) == SUBREG
)
2987 new_i2_dest
= XEXP (new_i2_dest
, 0);
2989 if (REG_P (new_i3_dest
)
2990 && REG_P (new_i2_dest
)
2991 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2992 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
2996 /* If we can split it and use I2DEST, go ahead and see if that
2997 helps things be recognized. Verify that none of the registers
2998 are set between I2 and I3. */
2999 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
3003 /* We need I2DEST in the proper mode. If it is a hard register
3004 or the only use of a pseudo, we can change its mode.
3005 Make sure we don't change a hard register to have a mode that
3006 isn't valid for it, or change the number of registers. */
3007 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3008 || GET_MODE (*split
) == VOIDmode
3009 || can_change_dest_mode (i2dest
, added_sets_2
,
3011 && (next_real_insn (i2
) == i3
3012 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3013 /* We can't overwrite I2DEST if its value is still used by
3015 && ! reg_referenced_p (i2dest
, newpat
))
3017 rtx newdest
= i2dest
;
3018 enum rtx_code split_code
= GET_CODE (*split
);
3019 enum machine_mode split_mode
= GET_MODE (*split
);
3020 bool subst_done
= false;
3021 newi2pat
= NULL_RTX
;
3023 /* Get NEWDEST as a register in the proper mode. We have already
3024 validated that we can do this. */
3025 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3027 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3028 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3031 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3032 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3036 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3037 an ASHIFT. This can occur if it was inside a PLUS and hence
3038 appeared to be a memory address. This is a kludge. */
3039 if (split_code
== MULT
3040 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
3041 && INTVAL (XEXP (*split
, 1)) > 0
3042 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
3044 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3045 XEXP (*split
, 0), GEN_INT (i
)));
3046 /* Update split_code because we may not have a multiply
3048 split_code
= GET_CODE (*split
);
3051 #ifdef INSN_SCHEDULING
3052 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3053 be written as a ZERO_EXTEND. */
3054 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3056 #ifdef LOAD_EXTEND_OP
3057 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3058 what it really is. */
3059 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3061 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3062 SUBREG_REG (*split
)));
3065 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3066 SUBREG_REG (*split
)));
3070 /* Attempt to split binary operators using arithmetic identities. */
3071 if (BINARY_P (SET_SRC (newpat
))
3072 && split_mode
== GET_MODE (SET_SRC (newpat
))
3073 && ! side_effects_p (SET_SRC (newpat
)))
3075 rtx setsrc
= SET_SRC (newpat
);
3076 enum machine_mode mode
= GET_MODE (setsrc
);
3077 enum rtx_code code
= GET_CODE (setsrc
);
3078 rtx src_op0
= XEXP (setsrc
, 0);
3079 rtx src_op1
= XEXP (setsrc
, 1);
3081 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3082 if (rtx_equal_p (src_op0
, src_op1
))
3084 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3085 SUBST (XEXP (setsrc
, 0), newdest
);
3086 SUBST (XEXP (setsrc
, 1), newdest
);
3089 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3090 else if ((code
== PLUS
|| code
== MULT
)
3091 && GET_CODE (src_op0
) == code
3092 && GET_CODE (XEXP (src_op0
, 0)) == code
3093 && (INTEGRAL_MODE_P (mode
)
3094 || (FLOAT_MODE_P (mode
)
3095 && flag_unsafe_math_optimizations
)))
3097 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3098 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3099 rtx r
= XEXP (src_op0
, 1);
3102 /* Split both "((X op Y) op X) op Y" and
3103 "((X op Y) op Y) op X" as "T op T" where T is
3105 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3106 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3108 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3110 SUBST (XEXP (setsrc
, 0), newdest
);
3111 SUBST (XEXP (setsrc
, 1), newdest
);
3114 /* Split "((X op X) op Y) op Y)" as "T op T" where
3116 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3118 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3119 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3120 SUBST (XEXP (setsrc
, 0), newdest
);
3121 SUBST (XEXP (setsrc
, 1), newdest
);
3129 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3130 SUBST (*split
, newdest
);
3133 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3135 /* recog_for_combine might have added CLOBBERs to newi2pat.
3136 Make sure NEWPAT does not depend on the clobbered regs. */
3137 if (GET_CODE (newi2pat
) == PARALLEL
)
3138 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3139 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3141 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3142 if (reg_overlap_mentioned_p (reg
, newpat
))
3149 /* If the split point was a MULT and we didn't have one before,
3150 don't use one now. */
3151 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3152 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3156 /* Check for a case where we loaded from memory in a narrow mode and
3157 then sign extended it, but we need both registers. In that case,
3158 we have a PARALLEL with both loads from the same memory location.
3159 We can split this into a load from memory followed by a register-register
3160 copy. This saves at least one insn, more if register allocation can
3163 We cannot do this if the destination of the first assignment is a
3164 condition code register or cc0. We eliminate this case by making sure
3165 the SET_DEST and SET_SRC have the same mode.
3167 We cannot do this if the destination of the second assignment is
3168 a register that we have already assumed is zero-extended. Similarly
3169 for a SUBREG of such a register. */
3171 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3172 && GET_CODE (newpat
) == PARALLEL
3173 && XVECLEN (newpat
, 0) == 2
3174 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3175 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3176 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3177 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3178 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3179 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3180 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3181 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3183 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3184 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3185 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3187 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
3188 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3189 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3190 && (reg_stat
[REGNO (temp
)].nonzero_bits
3191 != GET_MODE_MASK (word_mode
))))
3192 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3193 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3195 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
3196 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3197 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3198 && (reg_stat
[REGNO (temp
)].nonzero_bits
3199 != GET_MODE_MASK (word_mode
)))))
3200 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3201 SET_SRC (XVECEXP (newpat
, 0, 1)))
3202 && ! find_reg_note (i3
, REG_UNUSED
,
3203 SET_DEST (XVECEXP (newpat
, 0, 0))))
3207 newi2pat
= XVECEXP (newpat
, 0, 0);
3208 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3209 newpat
= XVECEXP (newpat
, 0, 1);
3210 SUBST (SET_SRC (newpat
),
3211 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3212 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3214 if (i2_code_number
>= 0)
3215 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3217 if (insn_code_number
>= 0)
3221 /* Similarly, check for a case where we have a PARALLEL of two independent
3222 SETs but we started with three insns. In this case, we can do the sets
3223 as two separate insns. This case occurs when some SET allows two
3224 other insns to combine, but the destination of that SET is still live. */
3226 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3227 && GET_CODE (newpat
) == PARALLEL
3228 && XVECLEN (newpat
, 0) == 2
3229 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3230 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3231 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3232 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3233 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3234 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3235 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3237 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3238 XVECEXP (newpat
, 0, 0))
3239 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3240 XVECEXP (newpat
, 0, 1))
3241 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3242 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1))))
3244 /* We cannot split the parallel into two sets if both sets
3246 && ! (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0))
3247 && reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 1)))
3251 /* Normally, it doesn't matter which of the two is done first,
3252 but it does if one references cc0. In that case, it has to
3255 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
3257 newi2pat
= XVECEXP (newpat
, 0, 0);
3258 newpat
= XVECEXP (newpat
, 0, 1);
3263 newi2pat
= XVECEXP (newpat
, 0, 1);
3264 newpat
= XVECEXP (newpat
, 0, 0);
3267 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3269 if (i2_code_number
>= 0)
3270 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3273 /* If it still isn't recognized, fail and change things back the way they
3275 if ((insn_code_number
< 0
3276 /* Is the result a reasonable ASM_OPERANDS? */
3277 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3283 /* If we had to change another insn, make sure it is valid also. */
3284 if (undobuf
.other_insn
)
3286 rtx other_pat
= PATTERN (undobuf
.other_insn
);
3287 rtx new_other_notes
;
3290 CLEAR_HARD_REG_SET (newpat_used_regs
);
3292 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3295 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3301 PATTERN (undobuf
.other_insn
) = other_pat
;
3303 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3304 are still valid. Then add any non-duplicate notes added by
3305 recog_for_combine. */
3306 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3308 next
= XEXP (note
, 1);
3310 if (REG_NOTE_KIND (note
) == REG_UNUSED
3311 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
3312 remove_note (undobuf
.other_insn
, note
);
3315 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3316 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3319 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3320 they are adjacent to each other or not. */
3322 rtx p
= prev_nonnote_insn (i3
);
3323 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3324 && sets_cc0_p (newi2pat
))
3332 /* Only allow this combination if insn_rtx_costs reports that the
3333 replacement instructions are cheaper than the originals. */
3334 if (!combine_validate_cost (i1
, i2
, i3
, newpat
, newi2pat
))
3340 /* We now know that we can do this combination. Merge the insns and
3341 update the status of registers and LOG_LINKS. */
3349 /* I3 now uses what used to be its destination and which is now
3350 I2's destination. This requires us to do a few adjustments. */
3351 PATTERN (i3
) = newpat
;
3352 adjust_for_new_dest (i3
);
3354 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3357 However, some later insn might be using I2's dest and have
3358 a LOG_LINK pointing at I3. We must remove this link.
3359 The simplest way to remove the link is to point it at I1,
3360 which we know will be a NOTE. */
3362 /* newi2pat is usually a SET here; however, recog_for_combine might
3363 have added some clobbers. */
3364 if (GET_CODE (newi2pat
) == PARALLEL
)
3365 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3367 ni2dest
= SET_DEST (newi2pat
);
3369 for (insn
= NEXT_INSN (i3
);
3370 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3371 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3372 insn
= NEXT_INSN (insn
))
3374 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3376 for (link
= LOG_LINKS (insn
); link
;
3377 link
= XEXP (link
, 1))
3378 if (XEXP (link
, 0) == i3
)
3379 XEXP (link
, 0) = i1
;
3387 rtx i3notes
, i2notes
, i1notes
= 0;
3388 rtx i3links
, i2links
, i1links
= 0;
3391 /* Compute which registers we expect to eliminate. newi2pat may be setting
3392 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3393 same as i3dest, in which case newi2pat may be setting i1dest. */
3394 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3395 || i2dest_in_i2src
|| i2dest_in_i1src
3398 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
3399 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3403 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3405 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3406 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
3408 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
3410 /* Ensure that we do not have something that should not be shared but
3411 occurs multiple times in the new insns. Check this by first
3412 resetting all the `used' flags and then copying anything is shared. */
3414 reset_used_flags (i3notes
);
3415 reset_used_flags (i2notes
);
3416 reset_used_flags (i1notes
);
3417 reset_used_flags (newpat
);
3418 reset_used_flags (newi2pat
);
3419 if (undobuf
.other_insn
)
3420 reset_used_flags (PATTERN (undobuf
.other_insn
));
3422 i3notes
= copy_rtx_if_shared (i3notes
);
3423 i2notes
= copy_rtx_if_shared (i2notes
);
3424 i1notes
= copy_rtx_if_shared (i1notes
);
3425 newpat
= copy_rtx_if_shared (newpat
);
3426 newi2pat
= copy_rtx_if_shared (newi2pat
);
3427 if (undobuf
.other_insn
)
3428 reset_used_flags (PATTERN (undobuf
.other_insn
));
3430 INSN_CODE (i3
) = insn_code_number
;
3431 PATTERN (i3
) = newpat
;
3433 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
3435 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
3437 reset_used_flags (call_usage
);
3438 call_usage
= copy_rtx (call_usage
);
3441 replace_rtx (call_usage
, i2dest
, i2src
);
3444 replace_rtx (call_usage
, i1dest
, i1src
);
3446 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
3449 if (undobuf
.other_insn
)
3450 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
3452 /* We had one special case above where I2 had more than one set and
3453 we replaced a destination of one of those sets with the destination
3454 of I3. In that case, we have to update LOG_LINKS of insns later
3455 in this basic block. Note that this (expensive) case is rare.
3457 Also, in this case, we must pretend that all REG_NOTEs for I2
3458 actually came from I3, so that REG_UNUSED notes from I2 will be
3459 properly handled. */
3461 if (i3_subst_into_i2
)
3463 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
3464 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
3465 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
3466 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
3467 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
3468 && ! find_reg_note (i2
, REG_UNUSED
,
3469 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
3470 for (temp
= NEXT_INSN (i2
);
3471 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3472 || BB_HEAD (this_basic_block
) != temp
);
3473 temp
= NEXT_INSN (temp
))
3474 if (temp
!= i3
&& INSN_P (temp
))
3475 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
3476 if (XEXP (link
, 0) == i2
)
3477 XEXP (link
, 0) = i3
;
3482 while (XEXP (link
, 1))
3483 link
= XEXP (link
, 1);
3484 XEXP (link
, 1) = i2notes
;
3498 INSN_CODE (i2
) = i2_code_number
;
3499 PATTERN (i2
) = newi2pat
;
3502 SET_INSN_DELETED (i2
);
3508 SET_INSN_DELETED (i1
);
3511 /* Get death notes for everything that is now used in either I3 or
3512 I2 and used to die in a previous insn. If we built two new
3513 patterns, move from I1 to I2 then I2 to I3 so that we get the
3514 proper movement on registers that I2 modifies. */
3518 move_deaths (newi2pat
, NULL_RTX
, DF_INSN_LUID (i1
), i2
, &midnotes
);
3519 move_deaths (newpat
, newi2pat
, DF_INSN_LUID (i1
), i3
, &midnotes
);
3522 move_deaths (newpat
, NULL_RTX
, i1
? DF_INSN_LUID (i1
) : DF_INSN_LUID (i2
),
3525 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3527 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
3530 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
3533 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
3536 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3539 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3540 know these are REG_UNUSED and want them to go to the desired insn,
3541 so we always pass it as i3. */
3543 if (newi2pat
&& new_i2_notes
)
3544 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3547 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3549 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3550 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3551 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3552 in that case, it might delete I2. Similarly for I2 and I1.
3553 Show an additional death due to the REG_DEAD note we make here. If
3554 we discard it in distribute_notes, we will decrement it again. */
3558 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
3559 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
3561 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
3563 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
3565 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3569 if (i2dest_in_i2src
)
3571 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3572 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
3573 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3575 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
3576 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3577 NULL_RTX
, NULL_RTX
);
3580 if (i1dest_in_i1src
)
3582 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3583 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
3584 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3586 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
3587 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3588 NULL_RTX
, NULL_RTX
);
3591 distribute_links (i3links
);
3592 distribute_links (i2links
);
3593 distribute_links (i1links
);
3598 rtx i2_insn
= 0, i2_val
= 0, set
;
3600 /* The insn that used to set this register doesn't exist, and
3601 this life of the register may not exist either. See if one of
3602 I3's links points to an insn that sets I2DEST. If it does,
3603 that is now the last known value for I2DEST. If we don't update
3604 this and I2 set the register to a value that depended on its old
3605 contents, we will get confused. If this insn is used, thing
3606 will be set correctly in combine_instructions. */
3608 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
3609 if ((set
= single_set (XEXP (link
, 0))) != 0
3610 && rtx_equal_p (i2dest
, SET_DEST (set
)))
3611 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
3613 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
3615 /* If the reg formerly set in I2 died only once and that was in I3,
3616 zero its use count so it won't make `reload' do any work. */
3618 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
3619 && ! i2dest_in_i2src
)
3621 regno
= REGNO (i2dest
);
3622 INC_REG_N_SETS (regno
, -1);
3626 if (i1
&& REG_P (i1dest
))
3629 rtx i1_insn
= 0, i1_val
= 0, set
;
3631 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
3632 if ((set
= single_set (XEXP (link
, 0))) != 0
3633 && rtx_equal_p (i1dest
, SET_DEST (set
)))
3634 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
3636 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
3638 regno
= REGNO (i1dest
);
3639 if (! added_sets_1
&& ! i1dest_in_i1src
)
3640 INC_REG_N_SETS (regno
, -1);
3643 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3644 been made to this insn. The order of
3645 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3646 can affect nonzero_bits of newpat */
3648 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
3649 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
3651 /* Set new_direct_jump_p if a new return or simple jump instruction
3654 If I3 is now an unconditional jump, ensure that it has a
3655 BARRIER following it since it may have initially been a
3656 conditional jump. It may also be the last nonnote insn. */
3658 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
3660 *new_direct_jump_p
= 1;
3661 mark_jump_label (PATTERN (i3
), i3
, 0);
3663 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
3664 || !BARRIER_P (temp
))
3665 emit_barrier_after (i3
);
3668 if (undobuf
.other_insn
!= NULL_RTX
3669 && (returnjump_p (undobuf
.other_insn
)
3670 || any_uncondjump_p (undobuf
.other_insn
)))
3672 *new_direct_jump_p
= 1;
3674 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
3675 || !BARRIER_P (temp
))
3676 emit_barrier_after (undobuf
.other_insn
);
3679 /* An NOOP jump does not need barrier, but it does need cleaning up
3681 if (GET_CODE (newpat
) == SET
3682 && SET_SRC (newpat
) == pc_rtx
3683 && SET_DEST (newpat
) == pc_rtx
)
3684 *new_direct_jump_p
= 1;
3687 if (undobuf
.other_insn
!= NULL_RTX
)
3691 fprintf (dump_file
, "modifying other_insn ");
3692 dump_insn_slim (dump_file
, undobuf
.other_insn
);
3694 df_insn_rescan (undobuf
.other_insn
);
3697 if (i1
&& !(NOTE_P(i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
3701 fprintf (dump_file
, "modifying insn i1 ");
3702 dump_insn_slim (dump_file
, i1
);
3704 df_insn_rescan (i1
);
3707 if (i2
&& !(NOTE_P(i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
3711 fprintf (dump_file
, "modifying insn i2 ");
3712 dump_insn_slim (dump_file
, i2
);
3714 df_insn_rescan (i2
);
3717 if (i3
&& !(NOTE_P(i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
3721 fprintf (dump_file
, "modifying insn i3 ");
3722 dump_insn_slim (dump_file
, i3
);
3724 df_insn_rescan (i3
);
3727 combine_successes
++;
3730 if (added_links_insn
3731 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
3732 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
3733 return added_links_insn
;
3735 return newi2pat
? i2
: i3
;
3738 /* Undo all the modifications recorded in undobuf. */
3743 struct undo
*undo
, *next
;
3745 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3751 *undo
->where
.r
= undo
->old_contents
.r
;
3754 *undo
->where
.i
= undo
->old_contents
.i
;
3757 PUT_MODE (*undo
->where
.r
, undo
->old_contents
.m
);
3763 undo
->next
= undobuf
.frees
;
3764 undobuf
.frees
= undo
;
3770 /* We've committed to accepting the changes we made. Move all
3771 of the undos to the free list. */
3776 struct undo
*undo
, *next
;
3778 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3781 undo
->next
= undobuf
.frees
;
3782 undobuf
.frees
= undo
;
3787 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3788 where we have an arithmetic expression and return that point. LOC will
3791 try_combine will call this function to see if an insn can be split into
3795 find_split_point (rtx
*loc
, rtx insn
)
3798 enum rtx_code code
= GET_CODE (x
);
3800 unsigned HOST_WIDE_INT len
= 0;
3801 HOST_WIDE_INT pos
= 0;
3803 rtx inner
= NULL_RTX
;
3805 /* First special-case some codes. */
3809 #ifdef INSN_SCHEDULING
3810 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3812 if (MEM_P (SUBREG_REG (x
)))
3815 return find_split_point (&SUBREG_REG (x
), insn
);
3819 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3820 using LO_SUM and HIGH. */
3821 if (GET_CODE (XEXP (x
, 0)) == CONST
3822 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
3825 gen_rtx_LO_SUM (Pmode
,
3826 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
3828 return &XEXP (XEXP (x
, 0), 0);
3832 /* If we have a PLUS whose second operand is a constant and the
3833 address is not valid, perhaps will can split it up using
3834 the machine-specific way to split large constants. We use
3835 the first pseudo-reg (one of the virtual regs) as a placeholder;
3836 it will not remain in the result. */
3837 if (GET_CODE (XEXP (x
, 0)) == PLUS
3838 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3839 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
3841 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
3842 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
3845 /* This should have produced two insns, each of which sets our
3846 placeholder. If the source of the second is a valid address,
3847 we can make put both sources together and make a split point
3851 && NEXT_INSN (seq
) != NULL_RTX
3852 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
3853 && NONJUMP_INSN_P (seq
)
3854 && GET_CODE (PATTERN (seq
)) == SET
3855 && SET_DEST (PATTERN (seq
)) == reg
3856 && ! reg_mentioned_p (reg
,
3857 SET_SRC (PATTERN (seq
)))
3858 && NONJUMP_INSN_P (NEXT_INSN (seq
))
3859 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
3860 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
3861 && memory_address_p (GET_MODE (x
),
3862 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
3864 rtx src1
= SET_SRC (PATTERN (seq
));
3865 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
3867 /* Replace the placeholder in SRC2 with SRC1. If we can
3868 find where in SRC2 it was placed, that can become our
3869 split point and we can replace this address with SRC2.
3870 Just try two obvious places. */
3872 src2
= replace_rtx (src2
, reg
, src1
);
3874 if (XEXP (src2
, 0) == src1
)
3875 split
= &XEXP (src2
, 0);
3876 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
3877 && XEXP (XEXP (src2
, 0), 0) == src1
)
3878 split
= &XEXP (XEXP (src2
, 0), 0);
3882 SUBST (XEXP (x
, 0), src2
);
3887 /* If that didn't work, perhaps the first operand is complex and
3888 needs to be computed separately, so make a split point there.
3889 This will occur on machines that just support REG + CONST
3890 and have a constant moved through some previous computation. */
3892 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
3893 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3894 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
3895 return &XEXP (XEXP (x
, 0), 0);
3901 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3902 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3903 we need to put the operand into a register. So split at that
3906 if (SET_DEST (x
) == cc0_rtx
3907 && GET_CODE (SET_SRC (x
)) != COMPARE
3908 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
3909 && !OBJECT_P (SET_SRC (x
))
3910 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
3911 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
3912 return &SET_SRC (x
);
3915 /* See if we can split SET_SRC as it stands. */
3916 split
= find_split_point (&SET_SRC (x
), insn
);
3917 if (split
&& split
!= &SET_SRC (x
))
3920 /* See if we can split SET_DEST as it stands. */
3921 split
= find_split_point (&SET_DEST (x
), insn
);
3922 if (split
&& split
!= &SET_DEST (x
))
3925 /* See if this is a bitfield assignment with everything constant. If
3926 so, this is an IOR of an AND, so split it into that. */
3927 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3928 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3929 <= HOST_BITS_PER_WIDE_INT
)
3930 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3931 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3932 && GET_CODE (SET_SRC (x
)) == CONST_INT
3933 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3934 + INTVAL (XEXP (SET_DEST (x
), 2)))
3935 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3936 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3938 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3939 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3940 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3941 rtx dest
= XEXP (SET_DEST (x
), 0);
3942 enum machine_mode mode
= GET_MODE (dest
);
3943 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3946 if (BITS_BIG_ENDIAN
)
3947 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3949 or_mask
= gen_int_mode (src
<< pos
, mode
);
3952 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
3955 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
3957 simplify_gen_binary (IOR
, mode
,
3958 simplify_gen_binary (AND
, mode
,
3963 SUBST (SET_DEST (x
), dest
);
3965 split
= find_split_point (&SET_SRC (x
), insn
);
3966 if (split
&& split
!= &SET_SRC (x
))
3970 /* Otherwise, see if this is an operation that we can split into two.
3971 If so, try to split that. */
3972 code
= GET_CODE (SET_SRC (x
));
3977 /* If we are AND'ing with a large constant that is only a single
3978 bit and the result is only being used in a context where we
3979 need to know if it is zero or nonzero, replace it with a bit
3980 extraction. This will avoid the large constant, which might
3981 have taken more than one insn to make. If the constant were
3982 not a valid argument to the AND but took only one insn to make,
3983 this is no worse, but if it took more than one insn, it will
3986 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3987 && REG_P (XEXP (SET_SRC (x
), 0))
3988 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3989 && REG_P (SET_DEST (x
))
3990 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3991 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3992 && XEXP (*split
, 0) == SET_DEST (x
)
3993 && XEXP (*split
, 1) == const0_rtx
)
3995 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3996 XEXP (SET_SRC (x
), 0),
3997 pos
, NULL_RTX
, 1, 1, 0, 0);
3998 if (extraction
!= 0)
4000 SUBST (SET_SRC (x
), extraction
);
4001 return find_split_point (loc
, insn
);
4007 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4008 is known to be on, this can be converted into a NEG of a shift. */
4009 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4010 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4011 && 1 <= (pos
= exact_log2
4012 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4013 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4015 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4019 gen_rtx_LSHIFTRT (mode
,
4020 XEXP (SET_SRC (x
), 0),
4023 split
= find_split_point (&SET_SRC (x
), insn
);
4024 if (split
&& split
!= &SET_SRC (x
))
4030 inner
= XEXP (SET_SRC (x
), 0);
4032 /* We can't optimize if either mode is a partial integer
4033 mode as we don't know how many bits are significant
4035 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4036 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4040 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
4046 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
4047 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
4049 inner
= XEXP (SET_SRC (x
), 0);
4050 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4051 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4053 if (BITS_BIG_ENDIAN
)
4054 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
4055 unsignedp
= (code
== ZERO_EXTRACT
);
4063 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
4065 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4067 /* For unsigned, we have a choice of a shift followed by an
4068 AND or two shifts. Use two shifts for field sizes where the
4069 constant might be too large. We assume here that we can
4070 always at least get 8-bit constants in an AND insn, which is
4071 true for every current RISC. */
4073 if (unsignedp
&& len
<= 8)
4078 (mode
, gen_lowpart (mode
, inner
),
4080 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
4082 split
= find_split_point (&SET_SRC (x
), insn
);
4083 if (split
&& split
!= &SET_SRC (x
))
4090 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4091 gen_rtx_ASHIFT (mode
,
4092 gen_lowpart (mode
, inner
),
4093 GEN_INT (GET_MODE_BITSIZE (mode
)
4095 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
4097 split
= find_split_point (&SET_SRC (x
), insn
);
4098 if (split
&& split
!= &SET_SRC (x
))
4103 /* See if this is a simple operation with a constant as the second
4104 operand. It might be that this constant is out of range and hence
4105 could be used as a split point. */
4106 if (BINARY_P (SET_SRC (x
))
4107 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4108 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4109 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4110 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4111 return &XEXP (SET_SRC (x
), 1);
4113 /* Finally, see if this is a simple operation with its first operand
4114 not in a register. The operation might require this operand in a
4115 register, so return it as a split point. We can always do this
4116 because if the first operand were another operation, we would have
4117 already found it as a split point. */
4118 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4119 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4120 return &XEXP (SET_SRC (x
), 0);
4126 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4127 it is better to write this as (not (ior A B)) so we can split it.
4128 Similarly for IOR. */
4129 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4132 gen_rtx_NOT (GET_MODE (x
),
4133 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4135 XEXP (XEXP (x
, 0), 0),
4136 XEXP (XEXP (x
, 1), 0))));
4137 return find_split_point (loc
, insn
);
4140 /* Many RISC machines have a large set of logical insns. If the
4141 second operand is a NOT, put it first so we will try to split the
4142 other operand first. */
4143 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4145 rtx tem
= XEXP (x
, 0);
4146 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4147 SUBST (XEXP (x
, 1), tem
);
4155 /* Otherwise, select our actions depending on our rtx class. */
4156 switch (GET_RTX_CLASS (code
))
4158 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4160 split
= find_split_point (&XEXP (x
, 2), insn
);
4163 /* ... fall through ... */
4165 case RTX_COMM_ARITH
:
4167 case RTX_COMM_COMPARE
:
4168 split
= find_split_point (&XEXP (x
, 1), insn
);
4171 /* ... fall through ... */
4173 /* Some machines have (and (shift ...) ...) insns. If X is not
4174 an AND, but XEXP (X, 0) is, use it as our split point. */
4175 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4176 return &XEXP (x
, 0);
4178 split
= find_split_point (&XEXP (x
, 0), insn
);
4184 /* Otherwise, we don't have a split point. */
4189 /* Throughout X, replace FROM with TO, and return the result.
4190 The result is TO if X is FROM;
4191 otherwise the result is X, but its contents may have been modified.
4192 If they were modified, a record was made in undobuf so that
4193 undo_all will (among other things) return X to its original state.
4195 If the number of changes necessary is too much to record to undo,
4196 the excess changes are not made, so the result is invalid.
4197 The changes already made can still be undone.
4198 undobuf.num_undo is incremented for such changes, so by testing that
4199 the caller can tell whether the result is valid.
4201 `n_occurrences' is incremented each time FROM is replaced.
4203 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4205 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4206 by copying if `n_occurrences' is nonzero. */
4209 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
4211 enum rtx_code code
= GET_CODE (x
);
4212 enum machine_mode op0_mode
= VOIDmode
;
4217 /* Two expressions are equal if they are identical copies of a shared
4218 RTX or if they are both registers with the same register number
4221 #define COMBINE_RTX_EQUAL_P(X,Y) \
4223 || (REG_P (X) && REG_P (Y) \
4224 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4226 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4229 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4232 /* If X and FROM are the same register but different modes, they
4233 will not have been seen as equal above. However, the log links code
4234 will make a LOG_LINKS entry for that case. If we do nothing, we
4235 will try to rerecognize our original insn and, when it succeeds,
4236 we will delete the feeding insn, which is incorrect.
4238 So force this insn not to match in this (rare) case. */
4239 if (! in_dest
&& code
== REG
&& REG_P (from
)
4240 && reg_overlap_mentioned_p (x
, from
))
4241 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4243 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4244 of which may contain things that can be combined. */
4245 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4248 /* It is possible to have a subexpression appear twice in the insn.
4249 Suppose that FROM is a register that appears within TO.
4250 Then, after that subexpression has been scanned once by `subst',
4251 the second time it is scanned, TO may be found. If we were
4252 to scan TO here, we would find FROM within it and create a
4253 self-referent rtl structure which is completely wrong. */
4254 if (COMBINE_RTX_EQUAL_P (x
, to
))
4257 /* Parallel asm_operands need special attention because all of the
4258 inputs are shared across the arms. Furthermore, unsharing the
4259 rtl results in recognition failures. Failure to handle this case
4260 specially can result in circular rtl.
4262 Solve this by doing a normal pass across the first entry of the
4263 parallel, and only processing the SET_DESTs of the subsequent
4266 if (code
== PARALLEL
4267 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
4268 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
4270 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
4272 /* If this substitution failed, this whole thing fails. */
4273 if (GET_CODE (new) == CLOBBER
4274 && XEXP (new, 0) == const0_rtx
)
4277 SUBST (XVECEXP (x
, 0, 0), new);
4279 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
4281 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
4284 && GET_CODE (dest
) != CC0
4285 && GET_CODE (dest
) != PC
)
4287 new = subst (dest
, from
, to
, 0, unique_copy
);
4289 /* If this substitution failed, this whole thing fails. */
4290 if (GET_CODE (new) == CLOBBER
4291 && XEXP (new, 0) == const0_rtx
)
4294 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
4300 len
= GET_RTX_LENGTH (code
);
4301 fmt
= GET_RTX_FORMAT (code
);
4303 /* We don't need to process a SET_DEST that is a register, CC0,
4304 or PC, so set up to skip this common case. All other cases
4305 where we want to suppress replacing something inside a
4306 SET_SRC are handled via the IN_DEST operand. */
4308 && (REG_P (SET_DEST (x
))
4309 || GET_CODE (SET_DEST (x
)) == CC0
4310 || GET_CODE (SET_DEST (x
)) == PC
))
4313 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4316 op0_mode
= GET_MODE (XEXP (x
, 0));
4318 for (i
= 0; i
< len
; i
++)
4323 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4325 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
4327 new = (unique_copy
&& n_occurrences
4328 ? copy_rtx (to
) : to
);
4333 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
4336 /* If this substitution failed, this whole thing
4338 if (GET_CODE (new) == CLOBBER
4339 && XEXP (new, 0) == const0_rtx
)
4343 SUBST (XVECEXP (x
, i
, j
), new);
4346 else if (fmt
[i
] == 'e')
4348 /* If this is a register being set, ignore it. */
4352 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
4354 || code
== STRICT_LOW_PART
))
4357 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
4359 /* In general, don't install a subreg involving two
4360 modes not tieable. It can worsen register
4361 allocation, and can even make invalid reload
4362 insns, since the reg inside may need to be copied
4363 from in the outside mode, and that may be invalid
4364 if it is an fp reg copied in integer mode.
4366 We allow two exceptions to this: It is valid if
4367 it is inside another SUBREG and the mode of that
4368 SUBREG and the mode of the inside of TO is
4369 tieable and it is valid if X is a SET that copies
4372 if (GET_CODE (to
) == SUBREG
4373 && ! MODES_TIEABLE_P (GET_MODE (to
),
4374 GET_MODE (SUBREG_REG (to
)))
4375 && ! (code
== SUBREG
4376 && MODES_TIEABLE_P (GET_MODE (x
),
4377 GET_MODE (SUBREG_REG (to
))))
4379 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
4382 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
4384 #ifdef CANNOT_CHANGE_MODE_CLASS
4387 && REGNO (to
) < FIRST_PSEUDO_REGISTER
4388 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
4391 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
4394 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
4398 /* If we are in a SET_DEST, suppress most cases unless we
4399 have gone inside a MEM, in which case we want to
4400 simplify the address. We assume here that things that
4401 are actually part of the destination have their inner
4402 parts in the first expression. This is true for SUBREG,
4403 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4404 things aside from REG and MEM that should appear in a
4406 new = subst (XEXP (x
, i
), from
, to
,
4408 && (code
== SUBREG
|| code
== STRICT_LOW_PART
4409 || code
== ZERO_EXTRACT
))
4411 && i
== 0), unique_copy
);
4413 /* If we found that we will have to reject this combination,
4414 indicate that by returning the CLOBBER ourselves, rather than
4415 an expression containing it. This will speed things up as
4416 well as prevent accidents where two CLOBBERs are considered
4417 to be equal, thus producing an incorrect simplification. */
4419 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
4422 if (GET_CODE (x
) == SUBREG
4423 && (GET_CODE (new) == CONST_INT
4424 || GET_CODE (new) == CONST_DOUBLE
))
4426 enum machine_mode mode
= GET_MODE (x
);
4428 x
= simplify_subreg (GET_MODE (x
), new,
4429 GET_MODE (SUBREG_REG (x
)),
4432 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
4434 else if (GET_CODE (new) == CONST_INT
4435 && GET_CODE (x
) == ZERO_EXTEND
)
4437 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
4438 new, GET_MODE (XEXP (x
, 0)));
4442 SUBST (XEXP (x
, i
), new);
4447 /* Try to simplify X. If the simplification changed the code, it is likely
4448 that further simplification will help, so loop, but limit the number
4449 of repetitions that will be performed. */
4451 for (i
= 0; i
< 4; i
++)
4453 /* If X is sufficiently simple, don't bother trying to do anything
4455 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
4456 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
4458 if (GET_CODE (x
) == code
)
4461 code
= GET_CODE (x
);
4463 /* We no longer know the original mode of operand 0 since we
4464 have changed the form of X) */
4465 op0_mode
= VOIDmode
;
4471 /* Simplify X, a piece of RTL. We just operate on the expression at the
4472 outer level; call `subst' to simplify recursively. Return the new
4475 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4476 if we are inside a SET_DEST. */
4479 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
4481 enum rtx_code code
= GET_CODE (x
);
4482 enum machine_mode mode
= GET_MODE (x
);
4486 /* If this is a commutative operation, put a constant last and a complex
4487 expression first. We don't need to do this for comparisons here. */
4488 if (COMMUTATIVE_ARITH_P (x
)
4489 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
4492 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4493 SUBST (XEXP (x
, 1), temp
);
4496 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4497 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4498 things. Check for cases where both arms are testing the same
4501 Don't do anything if all operands are very simple. */
4504 && ((!OBJECT_P (XEXP (x
, 0))
4505 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4506 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
4507 || (!OBJECT_P (XEXP (x
, 1))
4508 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
4509 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
4511 && (!OBJECT_P (XEXP (x
, 0))
4512 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4513 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
4515 rtx cond
, true_rtx
, false_rtx
;
4517 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
4519 /* If everything is a comparison, what we have is highly unlikely
4520 to be simpler, so don't use it. */
4521 && ! (COMPARISON_P (x
)
4522 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
4524 rtx cop1
= const0_rtx
;
4525 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
4527 if (cond_code
== NE
&& COMPARISON_P (cond
))
4530 /* Simplify the alternative arms; this may collapse the true and
4531 false arms to store-flag values. Be careful to use copy_rtx
4532 here since true_rtx or false_rtx might share RTL with x as a
4533 result of the if_then_else_cond call above. */
4534 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
4535 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
4537 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4538 is unlikely to be simpler. */
4539 if (general_operand (true_rtx
, VOIDmode
)
4540 && general_operand (false_rtx
, VOIDmode
))
4542 enum rtx_code reversed
;
4544 /* Restarting if we generate a store-flag expression will cause
4545 us to loop. Just drop through in this case. */
4547 /* If the result values are STORE_FLAG_VALUE and zero, we can
4548 just make the comparison operation. */
4549 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4550 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
4552 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4553 && ((reversed
= reversed_comparison_code_parts
4554 (cond_code
, cond
, cop1
, NULL
))
4556 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
4559 /* Likewise, we can make the negate of a comparison operation
4560 if the result values are - STORE_FLAG_VALUE and zero. */
4561 else if (GET_CODE (true_rtx
) == CONST_INT
4562 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
4563 && false_rtx
== const0_rtx
)
4564 x
= simplify_gen_unary (NEG
, mode
,
4565 simplify_gen_relational (cond_code
,
4569 else if (GET_CODE (false_rtx
) == CONST_INT
4570 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
4571 && true_rtx
== const0_rtx
4572 && ((reversed
= reversed_comparison_code_parts
4573 (cond_code
, cond
, cop1
, NULL
))
4575 x
= simplify_gen_unary (NEG
, mode
,
4576 simplify_gen_relational (reversed
,
4581 return gen_rtx_IF_THEN_ELSE (mode
,
4582 simplify_gen_relational (cond_code
,
4587 true_rtx
, false_rtx
);
4589 code
= GET_CODE (x
);
4590 op0_mode
= VOIDmode
;
4595 /* Try to fold this expression in case we have constants that weren't
4598 switch (GET_RTX_CLASS (code
))
4601 if (op0_mode
== VOIDmode
)
4602 op0_mode
= GET_MODE (XEXP (x
, 0));
4603 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
4606 case RTX_COMM_COMPARE
:
4608 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
4609 if (cmp_mode
== VOIDmode
)
4611 cmp_mode
= GET_MODE (XEXP (x
, 1));
4612 if (cmp_mode
== VOIDmode
)
4613 cmp_mode
= op0_mode
;
4615 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
4616 XEXP (x
, 0), XEXP (x
, 1));
4619 case RTX_COMM_ARITH
:
4621 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4623 case RTX_BITFIELD_OPS
:
4625 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
4626 XEXP (x
, 1), XEXP (x
, 2));
4635 code
= GET_CODE (temp
);
4636 op0_mode
= VOIDmode
;
4637 mode
= GET_MODE (temp
);
4640 /* First see if we can apply the inverse distributive law. */
4641 if (code
== PLUS
|| code
== MINUS
4642 || code
== AND
|| code
== IOR
|| code
== XOR
)
4644 x
= apply_distributive_law (x
);
4645 code
= GET_CODE (x
);
4646 op0_mode
= VOIDmode
;
4649 /* If CODE is an associative operation not otherwise handled, see if we
4650 can associate some operands. This can win if they are constants or
4651 if they are logically related (i.e. (a & b) & a). */
4652 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
4653 || code
== AND
|| code
== IOR
|| code
== XOR
4654 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
4655 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
4656 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
4658 if (GET_CODE (XEXP (x
, 0)) == code
)
4660 rtx other
= XEXP (XEXP (x
, 0), 0);
4661 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
4662 rtx inner_op1
= XEXP (x
, 1);
4665 /* Make sure we pass the constant operand if any as the second
4666 one if this is a commutative operation. */
4667 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
4669 rtx tem
= inner_op0
;
4670 inner_op0
= inner_op1
;
4673 inner
= simplify_binary_operation (code
== MINUS
? PLUS
4674 : code
== DIV
? MULT
4676 mode
, inner_op0
, inner_op1
);
4678 /* For commutative operations, try the other pair if that one
4680 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
4682 other
= XEXP (XEXP (x
, 0), 1);
4683 inner
= simplify_binary_operation (code
, mode
,
4684 XEXP (XEXP (x
, 0), 0),
4689 return simplify_gen_binary (code
, mode
, other
, inner
);
4693 /* A little bit of algebraic simplification here. */
4697 /* Ensure that our address has any ASHIFTs converted to MULT in case
4698 address-recognizing predicates are called later. */
4699 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
4700 SUBST (XEXP (x
, 0), temp
);
4704 if (op0_mode
== VOIDmode
)
4705 op0_mode
= GET_MODE (SUBREG_REG (x
));
4707 /* See if this can be moved to simplify_subreg. */
4708 if (CONSTANT_P (SUBREG_REG (x
))
4709 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
4710 /* Don't call gen_lowpart if the inner mode
4711 is VOIDmode and we cannot simplify it, as SUBREG without
4712 inner mode is invalid. */
4713 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
4714 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
4715 return gen_lowpart (mode
, SUBREG_REG (x
));
4717 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
4721 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
4727 /* Don't change the mode of the MEM if that would change the meaning
4729 if (MEM_P (SUBREG_REG (x
))
4730 && (MEM_VOLATILE_P (SUBREG_REG (x
))
4731 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
4732 return gen_rtx_CLOBBER (mode
, const0_rtx
);
4734 /* Note that we cannot do any narrowing for non-constants since
4735 we might have been counting on using the fact that some bits were
4736 zero. We now do this in the SET. */
4741 temp
= expand_compound_operation (XEXP (x
, 0));
4743 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4744 replaced by (lshiftrt X C). This will convert
4745 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4747 if (GET_CODE (temp
) == ASHIFTRT
4748 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4749 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4750 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4751 INTVAL (XEXP (temp
, 1)));
4753 /* If X has only a single bit that might be nonzero, say, bit I, convert
4754 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4755 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4756 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4757 or a SUBREG of one since we'd be making the expression more
4758 complex if it was just a register. */
4761 && ! (GET_CODE (temp
) == SUBREG
4762 && REG_P (SUBREG_REG (temp
)))
4763 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4765 rtx temp1
= simplify_shift_const
4766 (NULL_RTX
, ASHIFTRT
, mode
,
4767 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4768 GET_MODE_BITSIZE (mode
) - 1 - i
),
4769 GET_MODE_BITSIZE (mode
) - 1 - i
);
4771 /* If all we did was surround TEMP with the two shifts, we
4772 haven't improved anything, so don't use it. Otherwise,
4773 we are better off with TEMP1. */
4774 if (GET_CODE (temp1
) != ASHIFTRT
4775 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4776 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4782 /* We can't handle truncation to a partial integer mode here
4783 because we don't know the real bitsize of the partial
4785 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4788 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4789 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4790 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4792 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4793 GET_MODE_MASK (mode
), 0));
4795 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4796 whose value is a comparison can be replaced with a subreg if
4797 STORE_FLAG_VALUE permits. */
4798 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4799 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4800 && (temp
= get_last_value (XEXP (x
, 0)))
4801 && COMPARISON_P (temp
))
4802 return gen_lowpart (mode
, XEXP (x
, 0));
4807 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4808 using cc0, in which case we want to leave it as a COMPARE
4809 so we can distinguish it from a register-register-copy. */
4810 if (XEXP (x
, 1) == const0_rtx
)
4813 /* x - 0 is the same as x unless x's mode has signed zeros and
4814 allows rounding towards -infinity. Under those conditions,
4816 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4817 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4818 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4824 /* (const (const X)) can become (const X). Do it this way rather than
4825 returning the inner CONST since CONST can be shared with a
4827 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4828 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4833 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4834 can add in an offset. find_split_point will split this address up
4835 again if it doesn't match. */
4836 if (GET_CODE (XEXP (x
, 0)) == HIGH
4837 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4843 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4844 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4845 bit-field and can be replaced by either a sign_extend or a
4846 sign_extract. The `and' may be a zero_extend and the two
4847 <c>, -<c> constants may be reversed. */
4848 if (GET_CODE (XEXP (x
, 0)) == XOR
4849 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4850 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4851 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4852 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4853 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4854 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4855 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4856 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4857 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4858 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4859 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4860 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4861 == (unsigned int) i
+ 1))))
4862 return simplify_shift_const
4863 (NULL_RTX
, ASHIFTRT
, mode
,
4864 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4865 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4866 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4867 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4869 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4870 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4871 the bitsize of the mode - 1. This allows simplification of
4872 "a = (b & 8) == 0;" */
4873 if (XEXP (x
, 1) == constm1_rtx
4874 && !REG_P (XEXP (x
, 0))
4875 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4876 && REG_P (SUBREG_REG (XEXP (x
, 0))))
4877 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4878 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4879 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4880 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4881 GET_MODE_BITSIZE (mode
) - 1),
4882 GET_MODE_BITSIZE (mode
) - 1);
4884 /* If we are adding two things that have no bits in common, convert
4885 the addition into an IOR. This will often be further simplified,
4886 for example in cases like ((a & 1) + (a & 2)), which can
4889 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4890 && (nonzero_bits (XEXP (x
, 0), mode
)
4891 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4893 /* Try to simplify the expression further. */
4894 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4895 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
4897 /* If we could, great. If not, do not go ahead with the IOR
4898 replacement, since PLUS appears in many special purpose
4899 address arithmetic instructions. */
4900 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4906 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4907 (and <foo> (const_int pow2-1)) */
4908 if (GET_CODE (XEXP (x
, 1)) == AND
4909 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4910 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4911 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4912 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4913 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4917 /* If we have (mult (plus A B) C), apply the distributive law and then
4918 the inverse distributive law to see if things simplify. This
4919 occurs mostly in addresses, often when unrolling loops. */
4921 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4923 rtx result
= distribute_and_simplify_rtx (x
, 0);
4928 /* Try simplify a*(b/c) as (a*b)/c. */
4929 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4930 && GET_CODE (XEXP (x
, 0)) == DIV
)
4932 rtx tem
= simplify_binary_operation (MULT
, mode
,
4933 XEXP (XEXP (x
, 0), 0),
4936 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4941 /* If this is a divide by a power of two, treat it as a shift if
4942 its first operand is a shift. */
4943 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4944 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4945 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4946 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4947 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4948 || GET_CODE (XEXP (x
, 0)) == ROTATE
4949 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4950 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4954 case GT
: case GTU
: case GE
: case GEU
:
4955 case LT
: case LTU
: case LE
: case LEU
:
4956 case UNEQ
: case LTGT
:
4957 case UNGT
: case UNGE
:
4958 case UNLT
: case UNLE
:
4959 case UNORDERED
: case ORDERED
:
4960 /* If the first operand is a condition code, we can't do anything
4962 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4963 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4964 && ! CC0_P (XEXP (x
, 0))))
4966 rtx op0
= XEXP (x
, 0);
4967 rtx op1
= XEXP (x
, 1);
4968 enum rtx_code new_code
;
4970 if (GET_CODE (op0
) == COMPARE
)
4971 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4973 /* Simplify our comparison, if possible. */
4974 new_code
= simplify_comparison (code
, &op0
, &op1
);
4976 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4977 if only the low-order bit is possibly nonzero in X (such as when
4978 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4979 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4980 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4983 Remove any ZERO_EXTRACT we made when thinking this was a
4984 comparison. It may now be simpler to use, e.g., an AND. If a
4985 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4986 the call to make_compound_operation in the SET case. */
4988 if (STORE_FLAG_VALUE
== 1
4989 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4990 && op1
== const0_rtx
4991 && mode
== GET_MODE (op0
)
4992 && nonzero_bits (op0
, mode
) == 1)
4993 return gen_lowpart (mode
,
4994 expand_compound_operation (op0
));
4996 else if (STORE_FLAG_VALUE
== 1
4997 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4998 && op1
== const0_rtx
4999 && mode
== GET_MODE (op0
)
5000 && (num_sign_bit_copies (op0
, mode
)
5001 == GET_MODE_BITSIZE (mode
)))
5003 op0
= expand_compound_operation (op0
);
5004 return simplify_gen_unary (NEG
, mode
,
5005 gen_lowpart (mode
, op0
),
5009 else if (STORE_FLAG_VALUE
== 1
5010 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5011 && op1
== const0_rtx
5012 && mode
== GET_MODE (op0
)
5013 && nonzero_bits (op0
, mode
) == 1)
5015 op0
= expand_compound_operation (op0
);
5016 return simplify_gen_binary (XOR
, mode
,
5017 gen_lowpart (mode
, op0
),
5021 else if (STORE_FLAG_VALUE
== 1
5022 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5023 && op1
== const0_rtx
5024 && mode
== GET_MODE (op0
)
5025 && (num_sign_bit_copies (op0
, mode
)
5026 == GET_MODE_BITSIZE (mode
)))
5028 op0
= expand_compound_operation (op0
);
5029 return plus_constant (gen_lowpart (mode
, op0
), 1);
5032 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5034 if (STORE_FLAG_VALUE
== -1
5035 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5036 && op1
== const0_rtx
5037 && (num_sign_bit_copies (op0
, mode
)
5038 == GET_MODE_BITSIZE (mode
)))
5039 return gen_lowpart (mode
,
5040 expand_compound_operation (op0
));
5042 else if (STORE_FLAG_VALUE
== -1
5043 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5044 && op1
== const0_rtx
5045 && mode
== GET_MODE (op0
)
5046 && nonzero_bits (op0
, mode
) == 1)
5048 op0
= expand_compound_operation (op0
);
5049 return simplify_gen_unary (NEG
, mode
,
5050 gen_lowpart (mode
, op0
),
5054 else if (STORE_FLAG_VALUE
== -1
5055 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5056 && op1
== const0_rtx
5057 && mode
== GET_MODE (op0
)
5058 && (num_sign_bit_copies (op0
, mode
)
5059 == GET_MODE_BITSIZE (mode
)))
5061 op0
= expand_compound_operation (op0
);
5062 return simplify_gen_unary (NOT
, mode
,
5063 gen_lowpart (mode
, op0
),
5067 /* If X is 0/1, (eq X 0) is X-1. */
5068 else if (STORE_FLAG_VALUE
== -1
5069 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5070 && op1
== const0_rtx
5071 && mode
== GET_MODE (op0
)
5072 && nonzero_bits (op0
, mode
) == 1)
5074 op0
= expand_compound_operation (op0
);
5075 return plus_constant (gen_lowpart (mode
, op0
), -1);
5078 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5079 one bit that might be nonzero, we can convert (ne x 0) to
5080 (ashift x c) where C puts the bit in the sign bit. Remove any
5081 AND with STORE_FLAG_VALUE when we are done, since we are only
5082 going to test the sign bit. */
5083 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5084 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5085 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5086 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5087 && op1
== const0_rtx
5088 && mode
== GET_MODE (op0
)
5089 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5091 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5092 expand_compound_operation (op0
),
5093 GET_MODE_BITSIZE (mode
) - 1 - i
);
5094 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5100 /* If the code changed, return a whole new comparison. */
5101 if (new_code
!= code
)
5102 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5104 /* Otherwise, keep this operation, but maybe change its operands.
5105 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5106 SUBST (XEXP (x
, 0), op0
);
5107 SUBST (XEXP (x
, 1), op1
);
5112 return simplify_if_then_else (x
);
5118 /* If we are processing SET_DEST, we are done. */
5122 return expand_compound_operation (x
);
5125 return simplify_set (x
);
5129 return simplify_logical (x
);
5136 /* If this is a shift by a constant amount, simplify it. */
5137 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5138 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5139 INTVAL (XEXP (x
, 1)));
5141 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5143 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5145 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5157 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5160 simplify_if_then_else (rtx x
)
5162 enum machine_mode mode
= GET_MODE (x
);
5163 rtx cond
= XEXP (x
, 0);
5164 rtx true_rtx
= XEXP (x
, 1);
5165 rtx false_rtx
= XEXP (x
, 2);
5166 enum rtx_code true_code
= GET_CODE (cond
);
5167 int comparison_p
= COMPARISON_P (cond
);
5170 enum rtx_code false_code
;
5173 /* Simplify storing of the truth value. */
5174 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5175 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5176 XEXP (cond
, 0), XEXP (cond
, 1));
5178 /* Also when the truth value has to be reversed. */
5180 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5181 && (reversed
= reversed_comparison (cond
, mode
)))
5184 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5185 in it is being compared against certain values. Get the true and false
5186 comparisons and see if that says anything about the value of each arm. */
5189 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5191 && REG_P (XEXP (cond
, 0)))
5194 rtx from
= XEXP (cond
, 0);
5195 rtx true_val
= XEXP (cond
, 1);
5196 rtx false_val
= true_val
;
5199 /* If FALSE_CODE is EQ, swap the codes and arms. */
5201 if (false_code
== EQ
)
5203 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5204 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5207 /* If we are comparing against zero and the expression being tested has
5208 only a single bit that might be nonzero, that is its value when it is
5209 not equal to zero. Similarly if it is known to be -1 or 0. */
5211 if (true_code
== EQ
&& true_val
== const0_rtx
5212 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5215 false_val
= GEN_INT (trunc_int_for_mode (nzb
, GET_MODE (from
)));
5217 else if (true_code
== EQ
&& true_val
== const0_rtx
5218 && (num_sign_bit_copies (from
, GET_MODE (from
))
5219 == GET_MODE_BITSIZE (GET_MODE (from
))))
5222 false_val
= constm1_rtx
;
5225 /* Now simplify an arm if we know the value of the register in the
5226 branch and it is used in the arm. Be careful due to the potential
5227 of locally-shared RTL. */
5229 if (reg_mentioned_p (from
, true_rtx
))
5230 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
5232 pc_rtx
, pc_rtx
, 0, 0);
5233 if (reg_mentioned_p (from
, false_rtx
))
5234 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
5236 pc_rtx
, pc_rtx
, 0, 0);
5238 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
5239 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
5241 true_rtx
= XEXP (x
, 1);
5242 false_rtx
= XEXP (x
, 2);
5243 true_code
= GET_CODE (cond
);
5246 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5247 reversed, do so to avoid needing two sets of patterns for
5248 subtract-and-branch insns. Similarly if we have a constant in the true
5249 arm, the false arm is the same as the first operand of the comparison, or
5250 the false arm is more complicated than the true arm. */
5253 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
5254 && (true_rtx
== pc_rtx
5255 || (CONSTANT_P (true_rtx
)
5256 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
5257 || true_rtx
== const0_rtx
5258 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
5259 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
5260 && !OBJECT_P (false_rtx
))
5261 || reg_mentioned_p (true_rtx
, false_rtx
)
5262 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
5264 true_code
= reversed_comparison_code (cond
, NULL
);
5265 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
5266 SUBST (XEXP (x
, 1), false_rtx
);
5267 SUBST (XEXP (x
, 2), true_rtx
);
5269 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5272 /* It is possible that the conditional has been simplified out. */
5273 true_code
= GET_CODE (cond
);
5274 comparison_p
= COMPARISON_P (cond
);
5277 /* If the two arms are identical, we don't need the comparison. */
5279 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
5282 /* Convert a == b ? b : a to "a". */
5283 if (true_code
== EQ
&& ! side_effects_p (cond
)
5284 && !HONOR_NANS (mode
)
5285 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
5286 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
5288 else if (true_code
== NE
&& ! side_effects_p (cond
)
5289 && !HONOR_NANS (mode
)
5290 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5291 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
5294 /* Look for cases where we have (abs x) or (neg (abs X)). */
5296 if (GET_MODE_CLASS (mode
) == MODE_INT
5297 && GET_CODE (false_rtx
) == NEG
5298 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
5300 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
5301 && ! side_effects_p (true_rtx
))
5306 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
5310 simplify_gen_unary (NEG
, mode
,
5311 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
5317 /* Look for MIN or MAX. */
5319 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
5321 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5322 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
5323 && ! side_effects_p (cond
))
5328 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
5331 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
5334 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
5337 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
5342 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5343 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5344 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5345 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5346 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5347 neither 1 or -1, but it isn't worth checking for. */
5349 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5351 && GET_MODE_CLASS (mode
) == MODE_INT
5352 && ! side_effects_p (x
))
5354 rtx t
= make_compound_operation (true_rtx
, SET
);
5355 rtx f
= make_compound_operation (false_rtx
, SET
);
5356 rtx cond_op0
= XEXP (cond
, 0);
5357 rtx cond_op1
= XEXP (cond
, 1);
5358 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
5359 enum machine_mode m
= mode
;
5360 rtx z
= 0, c1
= NULL_RTX
;
5362 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
5363 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
5364 || GET_CODE (t
) == ASHIFT
5365 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
5366 && rtx_equal_p (XEXP (t
, 0), f
))
5367 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
5369 /* If an identity-zero op is commutative, check whether there
5370 would be a match if we swapped the operands. */
5371 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
5372 || GET_CODE (t
) == XOR
)
5373 && rtx_equal_p (XEXP (t
, 1), f
))
5374 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
5375 else if (GET_CODE (t
) == SIGN_EXTEND
5376 && (GET_CODE (XEXP (t
, 0)) == PLUS
5377 || GET_CODE (XEXP (t
, 0)) == MINUS
5378 || GET_CODE (XEXP (t
, 0)) == IOR
5379 || GET_CODE (XEXP (t
, 0)) == XOR
5380 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5381 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5382 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5383 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5384 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5385 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5386 && (num_sign_bit_copies (f
, GET_MODE (f
))
5388 (GET_MODE_BITSIZE (mode
)
5389 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
5391 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5392 extend_op
= SIGN_EXTEND
;
5393 m
= GET_MODE (XEXP (t
, 0));
5395 else if (GET_CODE (t
) == SIGN_EXTEND
5396 && (GET_CODE (XEXP (t
, 0)) == PLUS
5397 || GET_CODE (XEXP (t
, 0)) == IOR
5398 || GET_CODE (XEXP (t
, 0)) == XOR
)
5399 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5400 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5401 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5402 && (num_sign_bit_copies (f
, GET_MODE (f
))
5404 (GET_MODE_BITSIZE (mode
)
5405 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
5407 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5408 extend_op
= SIGN_EXTEND
;
5409 m
= GET_MODE (XEXP (t
, 0));
5411 else if (GET_CODE (t
) == ZERO_EXTEND
5412 && (GET_CODE (XEXP (t
, 0)) == PLUS
5413 || GET_CODE (XEXP (t
, 0)) == MINUS
5414 || GET_CODE (XEXP (t
, 0)) == IOR
5415 || GET_CODE (XEXP (t
, 0)) == XOR
5416 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5417 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5418 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5419 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5420 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5421 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5422 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5423 && ((nonzero_bits (f
, GET_MODE (f
))
5424 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
5427 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5428 extend_op
= ZERO_EXTEND
;
5429 m
= GET_MODE (XEXP (t
, 0));
5431 else if (GET_CODE (t
) == ZERO_EXTEND
5432 && (GET_CODE (XEXP (t
, 0)) == PLUS
5433 || GET_CODE (XEXP (t
, 0)) == IOR
5434 || GET_CODE (XEXP (t
, 0)) == XOR
)
5435 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5436 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5437 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5438 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5439 && ((nonzero_bits (f
, GET_MODE (f
))
5440 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
5443 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5444 extend_op
= ZERO_EXTEND
;
5445 m
= GET_MODE (XEXP (t
, 0));
5450 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
5451 cond_op0
, cond_op1
),
5452 pc_rtx
, pc_rtx
, 0, 0);
5453 temp
= simplify_gen_binary (MULT
, m
, temp
,
5454 simplify_gen_binary (MULT
, m
, c1
,
5456 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
5457 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
5459 if (extend_op
!= UNKNOWN
)
5460 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
5466 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5467 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5468 negation of a single bit, we can convert this operation to a shift. We
5469 can actually do this more generally, but it doesn't seem worth it. */
5471 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5472 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5473 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
5474 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
5475 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
5476 == GET_MODE_BITSIZE (mode
))
5477 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
5479 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5480 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
5482 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5483 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5484 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5485 && GET_MODE (XEXP (cond
, 0)) == mode
5486 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
5487 == nonzero_bits (XEXP (cond
, 0), mode
)
5488 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
5489 return XEXP (cond
, 0);
5494 /* Simplify X, a SET expression. Return the new expression. */
5497 simplify_set (rtx x
)
5499 rtx src
= SET_SRC (x
);
5500 rtx dest
= SET_DEST (x
);
5501 enum machine_mode mode
5502 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5506 /* (set (pc) (return)) gets written as (return). */
5507 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5510 /* Now that we know for sure which bits of SRC we are using, see if we can
5511 simplify the expression for the object knowing that we only need the
5514 if (GET_MODE_CLASS (mode
) == MODE_INT
5515 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5517 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, 0);
5518 SUBST (SET_SRC (x
), src
);
5521 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5522 the comparison result and try to simplify it unless we already have used
5523 undobuf.other_insn. */
5524 if ((GET_MODE_CLASS (mode
) == MODE_CC
5525 || GET_CODE (src
) == COMPARE
5527 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5528 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5529 && COMPARISON_P (*cc_use
)
5530 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5532 enum rtx_code old_code
= GET_CODE (*cc_use
);
5533 enum rtx_code new_code
;
5535 int other_changed
= 0;
5536 enum machine_mode compare_mode
= GET_MODE (dest
);
5538 if (GET_CODE (src
) == COMPARE
)
5539 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5541 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
5543 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
5546 new_code
= old_code
;
5547 else if (!CONSTANT_P (tmp
))
5549 new_code
= GET_CODE (tmp
);
5550 op0
= XEXP (tmp
, 0);
5551 op1
= XEXP (tmp
, 1);
5555 rtx pat
= PATTERN (other_insn
);
5556 undobuf
.other_insn
= other_insn
;
5557 SUBST (*cc_use
, tmp
);
5559 /* Attempt to simplify CC user. */
5560 if (GET_CODE (pat
) == SET
)
5562 rtx
new = simplify_rtx (SET_SRC (pat
));
5563 if (new != NULL_RTX
)
5564 SUBST (SET_SRC (pat
), new);
5567 /* Convert X into a no-op move. */
5568 SUBST (SET_DEST (x
), pc_rtx
);
5569 SUBST (SET_SRC (x
), pc_rtx
);
5573 /* Simplify our comparison, if possible. */
5574 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
5576 #ifdef SELECT_CC_MODE
5577 /* If this machine has CC modes other than CCmode, check to see if we
5578 need to use a different CC mode here. */
5579 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5580 compare_mode
= GET_MODE (op0
);
5582 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5585 /* If the mode changed, we have to change SET_DEST, the mode in the
5586 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5587 a hard register, just build new versions with the proper mode. If it
5588 is a pseudo, we lose unless it is only time we set the pseudo, in
5589 which case we can safely change its mode. */
5590 if (compare_mode
!= GET_MODE (dest
))
5592 if (can_change_dest_mode (dest
, 0, compare_mode
))
5594 unsigned int regno
= REGNO (dest
);
5597 if (regno
< FIRST_PSEUDO_REGISTER
)
5598 new_dest
= gen_rtx_REG (compare_mode
, regno
);
5601 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
5602 new_dest
= regno_reg_rtx
[regno
];
5605 SUBST (SET_DEST (x
), new_dest
);
5606 SUBST (XEXP (*cc_use
, 0), new_dest
);
5613 #endif /* SELECT_CC_MODE */
5615 /* If the code changed, we have to build a new comparison in
5616 undobuf.other_insn. */
5617 if (new_code
!= old_code
)
5619 int other_changed_previously
= other_changed
;
5620 unsigned HOST_WIDE_INT mask
;
5622 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5626 /* If the only change we made was to change an EQ into an NE or
5627 vice versa, OP0 has only one bit that might be nonzero, and OP1
5628 is zero, check if changing the user of the condition code will
5629 produce a valid insn. If it won't, we can keep the original code
5630 in that insn by surrounding our operation with an XOR. */
5632 if (((old_code
== NE
&& new_code
== EQ
)
5633 || (old_code
== EQ
&& new_code
== NE
))
5634 && ! other_changed_previously
&& op1
== const0_rtx
5635 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5636 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5638 rtx pat
= PATTERN (other_insn
), note
= 0;
5640 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5641 && ! check_asm_operands (pat
)))
5643 PUT_CODE (*cc_use
, old_code
);
5646 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
5647 op0
, GEN_INT (mask
));
5653 undobuf
.other_insn
= other_insn
;
5656 /* If we are now comparing against zero, change our source if
5657 needed. If we do not use cc0, we always have a COMPARE. */
5658 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5660 SUBST (SET_SRC (x
), op0
);
5666 /* Otherwise, if we didn't previously have a COMPARE in the
5667 correct mode, we need one. */
5668 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5670 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5673 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
5675 SUBST (SET_SRC (x
), op0
);
5678 /* Otherwise, update the COMPARE if needed. */
5679 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
5681 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5687 /* Get SET_SRC in a form where we have placed back any
5688 compound expressions. Then do the checks below. */
5689 src
= make_compound_operation (src
, SET
);
5690 SUBST (SET_SRC (x
), src
);
5693 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5694 and X being a REG or (subreg (reg)), we may be able to convert this to
5695 (set (subreg:m2 x) (op)).
5697 We can always do this if M1 is narrower than M2 because that means that
5698 we only care about the low bits of the result.
5700 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5701 perform a narrower operation than requested since the high-order bits will
5702 be undefined. On machine where it is defined, this transformation is safe
5703 as long as M1 and M2 have the same number of words. */
5705 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5706 && !OBJECT_P (SUBREG_REG (src
))
5707 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5709 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5710 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5711 #ifndef WORD_REGISTER_OPERATIONS
5712 && (GET_MODE_SIZE (GET_MODE (src
))
5713 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5715 #ifdef CANNOT_CHANGE_MODE_CLASS
5716 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
5717 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5718 GET_MODE (SUBREG_REG (src
)),
5722 || (GET_CODE (dest
) == SUBREG
5723 && REG_P (SUBREG_REG (dest
)))))
5725 SUBST (SET_DEST (x
),
5726 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5728 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5730 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5734 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5737 && GET_CODE (src
) == SUBREG
5738 && subreg_lowpart_p (src
)
5739 && (GET_MODE_BITSIZE (GET_MODE (src
))
5740 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5742 rtx inner
= SUBREG_REG (src
);
5743 enum machine_mode inner_mode
= GET_MODE (inner
);
5745 /* Here we make sure that we don't have a sign bit on. */
5746 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5747 && (nonzero_bits (inner
, inner_mode
)
5748 < ((unsigned HOST_WIDE_INT
) 1
5749 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5751 SUBST (SET_SRC (x
), inner
);
5757 #ifdef LOAD_EXTEND_OP
5758 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5759 would require a paradoxical subreg. Replace the subreg with a
5760 zero_extend to avoid the reload that would otherwise be required. */
5762 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5763 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
5764 && SUBREG_BYTE (src
) == 0
5765 && (GET_MODE_SIZE (GET_MODE (src
))
5766 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5767 && MEM_P (SUBREG_REG (src
)))
5770 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5771 GET_MODE (src
), SUBREG_REG (src
)));
5777 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5778 are comparing an item known to be 0 or -1 against 0, use a logical
5779 operation instead. Check for one of the arms being an IOR of the other
5780 arm with some value. We compute three terms to be IOR'ed together. In
5781 practice, at most two will be nonzero. Then we do the IOR's. */
5783 if (GET_CODE (dest
) != PC
5784 && GET_CODE (src
) == IF_THEN_ELSE
5785 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5786 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5787 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5788 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5789 #ifdef HAVE_conditional_move
5790 && ! can_conditionally_move_p (GET_MODE (src
))
5792 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5793 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5794 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5795 && ! side_effects_p (src
))
5797 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5798 ? XEXP (src
, 1) : XEXP (src
, 2));
5799 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5800 ? XEXP (src
, 2) : XEXP (src
, 1));
5801 rtx term1
= const0_rtx
, term2
, term3
;
5803 if (GET_CODE (true_rtx
) == IOR
5804 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5805 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5806 else if (GET_CODE (true_rtx
) == IOR
5807 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5808 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5809 else if (GET_CODE (false_rtx
) == IOR
5810 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5811 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5812 else if (GET_CODE (false_rtx
) == IOR
5813 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5814 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5816 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
5817 XEXP (XEXP (src
, 0), 0), true_rtx
);
5818 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
5819 simplify_gen_unary (NOT
, GET_MODE (src
),
5820 XEXP (XEXP (src
, 0), 0),
5825 simplify_gen_binary (IOR
, GET_MODE (src
),
5826 simplify_gen_binary (IOR
, GET_MODE (src
),
5833 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5834 whole thing fail. */
5835 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5837 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5840 /* Convert this into a field assignment operation, if possible. */
5841 return make_field_assignment (x
);
5844 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5848 simplify_logical (rtx x
)
5850 enum machine_mode mode
= GET_MODE (x
);
5851 rtx op0
= XEXP (x
, 0);
5852 rtx op1
= XEXP (x
, 1);
5854 switch (GET_CODE (x
))
5857 /* We can call simplify_and_const_int only if we don't lose
5858 any (sign) bits when converting INTVAL (op1) to
5859 "unsigned HOST_WIDE_INT". */
5860 if (GET_CODE (op1
) == CONST_INT
5861 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5862 || INTVAL (op1
) > 0))
5864 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5865 if (GET_CODE (x
) != AND
)
5872 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5873 apply the distributive law and then the inverse distributive
5874 law to see if things simplify. */
5875 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5877 rtx result
= distribute_and_simplify_rtx (x
, 0);
5881 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5883 rtx result
= distribute_and_simplify_rtx (x
, 1);
5890 /* If we have (ior (and A B) C), apply the distributive law and then
5891 the inverse distributive law to see if things simplify. */
5893 if (GET_CODE (op0
) == AND
)
5895 rtx result
= distribute_and_simplify_rtx (x
, 0);
5900 if (GET_CODE (op1
) == AND
)
5902 rtx result
= distribute_and_simplify_rtx (x
, 1);
5915 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5916 operations" because they can be replaced with two more basic operations.
5917 ZERO_EXTEND is also considered "compound" because it can be replaced with
5918 an AND operation, which is simpler, though only one operation.
5920 The function expand_compound_operation is called with an rtx expression
5921 and will convert it to the appropriate shifts and AND operations,
5922 simplifying at each stage.
5924 The function make_compound_operation is called to convert an expression
5925 consisting of shifts and ANDs into the equivalent compound expression.
5926 It is the inverse of this function, loosely speaking. */
5929 expand_compound_operation (rtx x
)
5931 unsigned HOST_WIDE_INT pos
= 0, len
;
5933 unsigned int modewidth
;
5936 switch (GET_CODE (x
))
5941 /* We can't necessarily use a const_int for a multiword mode;
5942 it depends on implicitly extending the value.
5943 Since we don't know the right way to extend it,
5944 we can't tell whether the implicit way is right.
5946 Even for a mode that is no wider than a const_int,
5947 we can't win, because we need to sign extend one of its bits through
5948 the rest of it, and we don't know which bit. */
5949 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5952 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5953 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5954 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5955 reloaded. If not for that, MEM's would very rarely be safe.
5957 Reject MODEs bigger than a word, because we might not be able
5958 to reference a two-register group starting with an arbitrary register
5959 (and currently gen_lowpart might crash for a SUBREG). */
5961 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5964 /* Reject MODEs that aren't scalar integers because turning vector
5965 or complex modes into shifts causes problems. */
5967 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5970 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5971 /* If the inner object has VOIDmode (the only way this can happen
5972 is if it is an ASM_OPERANDS), we can't do anything since we don't
5973 know how much masking to do. */
5982 /* ... fall through ... */
5985 /* If the operand is a CLOBBER, just return it. */
5986 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5989 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5990 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5991 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5994 /* Reject MODEs that aren't scalar integers because turning vector
5995 or complex modes into shifts causes problems. */
5997 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6000 len
= INTVAL (XEXP (x
, 1));
6001 pos
= INTVAL (XEXP (x
, 2));
6003 /* This should stay within the object being extracted, fail otherwise. */
6004 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
6007 if (BITS_BIG_ENDIAN
)
6008 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6015 /* Convert sign extension to zero extension, if we know that the high
6016 bit is not set, as this is easier to optimize. It will be converted
6017 back to cheaper alternative in make_extraction. */
6018 if (GET_CODE (x
) == SIGN_EXTEND
6019 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6020 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6021 & ~(((unsigned HOST_WIDE_INT
)
6022 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6026 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6027 rtx temp2
= expand_compound_operation (temp
);
6029 /* Make sure this is a profitable operation. */
6030 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
6032 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
6038 /* We can optimize some special cases of ZERO_EXTEND. */
6039 if (GET_CODE (x
) == ZERO_EXTEND
)
6041 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6042 know that the last value didn't have any inappropriate bits
6044 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6045 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6046 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6047 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6048 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6049 return XEXP (XEXP (x
, 0), 0);
6051 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6052 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6053 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6054 && subreg_lowpart_p (XEXP (x
, 0))
6055 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6056 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6057 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6058 return SUBREG_REG (XEXP (x
, 0));
6060 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6061 is a comparison and STORE_FLAG_VALUE permits. This is like
6062 the first case, but it works even when GET_MODE (x) is larger
6063 than HOST_WIDE_INT. */
6064 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6065 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6066 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6067 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6068 <= HOST_BITS_PER_WIDE_INT
)
6069 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
6070 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6071 return XEXP (XEXP (x
, 0), 0);
6073 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6074 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6075 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6076 && subreg_lowpart_p (XEXP (x
, 0))
6077 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6078 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6079 <= HOST_BITS_PER_WIDE_INT
)
6080 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
6081 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6082 return SUBREG_REG (XEXP (x
, 0));
6086 /* If we reach here, we want to return a pair of shifts. The inner
6087 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6088 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6089 logical depending on the value of UNSIGNEDP.
6091 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6092 converted into an AND of a shift.
6094 We must check for the case where the left shift would have a negative
6095 count. This can happen in a case like (x >> 31) & 255 on machines
6096 that can't shift by a constant. On those machines, we would first
6097 combine the shift with the AND to produce a variable-position
6098 extraction. Then the constant of 31 would be substituted in to produce
6099 a such a position. */
6101 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
6102 if (modewidth
+ len
>= pos
)
6104 enum machine_mode mode
= GET_MODE (x
);
6105 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6106 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6108 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6109 tem
, modewidth
- pos
- len
);
6110 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6111 mode
, tem
, modewidth
- len
);
6113 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6114 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6115 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6118 ((HOST_WIDE_INT
) 1 << len
) - 1);
6120 /* Any other cases we can't handle. */
6123 /* If we couldn't do this for some reason, return the original
6125 if (GET_CODE (tem
) == CLOBBER
)
6131 /* X is a SET which contains an assignment of one object into
6132 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6133 or certain SUBREGS). If possible, convert it into a series of
6136 We half-heartedly support variable positions, but do not at all
6137 support variable lengths. */
6140 expand_field_assignment (rtx x
)
6143 rtx pos
; /* Always counts from low bit. */
6145 rtx mask
, cleared
, masked
;
6146 enum machine_mode compute_mode
;
6148 /* Loop until we find something we can't simplify. */
6151 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6152 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6154 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6155 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
6156 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6158 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6159 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
6161 inner
= XEXP (SET_DEST (x
), 0);
6162 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6163 pos
= XEXP (SET_DEST (x
), 2);
6165 /* A constant position should stay within the width of INNER. */
6166 if (GET_CODE (pos
) == CONST_INT
6167 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
6170 if (BITS_BIG_ENDIAN
)
6172 if (GET_CODE (pos
) == CONST_INT
)
6173 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
6175 else if (GET_CODE (pos
) == MINUS
6176 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
6177 && (INTVAL (XEXP (pos
, 1))
6178 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
6179 /* If position is ADJUST - X, new position is X. */
6180 pos
= XEXP (pos
, 0);
6182 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6183 GEN_INT (GET_MODE_BITSIZE (
6190 /* A SUBREG between two modes that occupy the same numbers of words
6191 can be done by moving the SUBREG to the source. */
6192 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6193 /* We need SUBREGs to compute nonzero_bits properly. */
6194 && nonzero_sign_valid
6195 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6196 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6197 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6198 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6200 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6202 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6209 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6210 inner
= SUBREG_REG (inner
);
6212 compute_mode
= GET_MODE (inner
);
6214 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6215 if (! SCALAR_INT_MODE_P (compute_mode
))
6217 enum machine_mode imode
;
6219 /* Don't do anything for vector or complex integral types. */
6220 if (! FLOAT_MODE_P (compute_mode
))
6223 /* Try to find an integral mode to pun with. */
6224 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6225 if (imode
== BLKmode
)
6228 compute_mode
= imode
;
6229 inner
= gen_lowpart (imode
, inner
);
6232 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6233 if (len
>= HOST_BITS_PER_WIDE_INT
)
6236 /* Now compute the equivalent expression. Make a copy of INNER
6237 for the SET_DEST in case it is a MEM into which we will substitute;
6238 we don't want shared RTL in that case. */
6239 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
6240 cleared
= simplify_gen_binary (AND
, compute_mode
,
6241 simplify_gen_unary (NOT
, compute_mode
,
6242 simplify_gen_binary (ASHIFT
,
6247 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6248 simplify_gen_binary (
6250 gen_lowpart (compute_mode
, SET_SRC (x
)),
6254 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6255 simplify_gen_binary (IOR
, compute_mode
,
6262 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6263 it is an RTX that represents a variable starting position; otherwise,
6264 POS is the (constant) starting bit position (counted from the LSB).
6266 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6269 IN_DEST is nonzero if this is a reference in the destination of a
6270 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6271 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6274 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6275 ZERO_EXTRACT should be built even for bits starting at bit 0.
6277 MODE is the desired mode of the result (if IN_DEST == 0).
6279 The result is an RTX for the extraction or NULL_RTX if the target
6283 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6284 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6285 int in_dest
, int in_compare
)
6287 /* This mode describes the size of the storage area
6288 to fetch the overall value from. Within that, we
6289 ignore the POS lowest bits, etc. */
6290 enum machine_mode is_mode
= GET_MODE (inner
);
6291 enum machine_mode inner_mode
;
6292 enum machine_mode wanted_inner_mode
;
6293 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6294 enum machine_mode pos_mode
= word_mode
;
6295 enum machine_mode extraction_mode
= word_mode
;
6296 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6298 rtx orig_pos_rtx
= pos_rtx
;
6299 HOST_WIDE_INT orig_pos
;
6301 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6303 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6304 consider just the QI as the memory to extract from.
6305 The subreg adds or removes high bits; its mode is
6306 irrelevant to the meaning of this extraction,
6307 since POS and LEN count from the lsb. */
6308 if (MEM_P (SUBREG_REG (inner
)))
6309 is_mode
= GET_MODE (SUBREG_REG (inner
));
6310 inner
= SUBREG_REG (inner
);
6312 else if (GET_CODE (inner
) == ASHIFT
6313 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6314 && pos_rtx
== 0 && pos
== 0
6315 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6317 /* We're extracting the least significant bits of an rtx
6318 (ashift X (const_int C)), where LEN > C. Extract the
6319 least significant (LEN - C) bits of X, giving an rtx
6320 whose mode is MODE, then shift it left C times. */
6321 new = make_extraction (mode
, XEXP (inner
, 0),
6322 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6323 unsignedp
, in_dest
, in_compare
);
6325 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6328 inner_mode
= GET_MODE (inner
);
6330 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6331 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6333 /* See if this can be done without an extraction. We never can if the
6334 width of the field is not the same as that of some integer mode. For
6335 registers, we can only avoid the extraction if the position is at the
6336 low-order bit and this is either not in the destination or we have the
6337 appropriate STRICT_LOW_PART operation available.
6339 For MEM, we can avoid an extract if the field starts on an appropriate
6340 boundary and we can change the mode of the memory reference. */
6342 if (tmode
!= BLKmode
6343 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6345 && (inner_mode
== tmode
6347 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
6348 GET_MODE_BITSIZE (inner_mode
))
6349 || reg_truncated_to_mode (tmode
, inner
))
6352 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6353 || (MEM_P (inner
) && pos_rtx
== 0
6355 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6356 : BITS_PER_UNIT
)) == 0
6357 /* We can't do this if we are widening INNER_MODE (it
6358 may not be aligned, for one thing). */
6359 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6360 && (inner_mode
== tmode
6361 || (! mode_dependent_address_p (XEXP (inner
, 0))
6362 && ! MEM_VOLATILE_P (inner
))))))
6364 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6365 field. If the original and current mode are the same, we need not
6366 adjust the offset. Otherwise, we do if bytes big endian.
6368 If INNER is not a MEM, get a piece consisting of just the field
6369 of interest (in this case POS % BITS_PER_WORD must be 0). */
6373 HOST_WIDE_INT offset
;
6375 /* POS counts from lsb, but make OFFSET count in memory order. */
6376 if (BYTES_BIG_ENDIAN
)
6377 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6379 offset
= pos
/ BITS_PER_UNIT
;
6381 new = adjust_address_nv (inner
, tmode
, offset
);
6383 else if (REG_P (inner
))
6385 if (tmode
!= inner_mode
)
6387 /* We can't call gen_lowpart in a DEST since we
6388 always want a SUBREG (see below) and it would sometimes
6389 return a new hard register. */
6392 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6394 if (WORDS_BIG_ENDIAN
6395 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6396 final_word
= ((GET_MODE_SIZE (inner_mode
)
6397 - GET_MODE_SIZE (tmode
))
6398 / UNITS_PER_WORD
) - final_word
;
6400 final_word
*= UNITS_PER_WORD
;
6401 if (BYTES_BIG_ENDIAN
&&
6402 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6403 final_word
+= (GET_MODE_SIZE (inner_mode
)
6404 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6406 /* Avoid creating invalid subregs, for example when
6407 simplifying (x>>32)&255. */
6408 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
6411 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6414 new = gen_lowpart (tmode
, inner
);
6420 new = force_to_mode (inner
, tmode
,
6421 len
>= HOST_BITS_PER_WIDE_INT
6422 ? ~(unsigned HOST_WIDE_INT
) 0
6423 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6426 /* If this extraction is going into the destination of a SET,
6427 make a STRICT_LOW_PART unless we made a MEM. */
6430 return (MEM_P (new) ? new
6431 : (GET_CODE (new) != SUBREG
6432 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6433 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6438 if (GET_CODE (new) == CONST_INT
)
6439 return gen_int_mode (INTVAL (new), mode
);
6441 /* If we know that no extraneous bits are set, and that the high
6442 bit is not set, convert the extraction to the cheaper of
6443 sign and zero extension, that are equivalent in these cases. */
6444 if (flag_expensive_optimizations
6445 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6446 && ((nonzero_bits (new, tmode
)
6447 & ~(((unsigned HOST_WIDE_INT
)
6448 GET_MODE_MASK (tmode
))
6452 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6453 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6455 /* Prefer ZERO_EXTENSION, since it gives more information to
6457 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6462 /* Otherwise, sign- or zero-extend unless we already are in the
6465 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6469 /* Unless this is a COMPARE or we have a funny memory reference,
6470 don't do anything with zero-extending field extracts starting at
6471 the low-order bit since they are simple AND operations. */
6472 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6473 && ! in_compare
&& unsignedp
)
6476 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6477 if the position is not a constant and the length is not 1. In all
6478 other cases, we would only be going outside our object in cases when
6479 an original shift would have been undefined. */
6481 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6482 || (pos_rtx
!= 0 && len
!= 1)))
6485 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6486 and the mode for the result. */
6487 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6489 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6490 pos_mode
= mode_for_extraction (EP_insv
, 2);
6491 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6494 if (! in_dest
&& unsignedp
6495 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6497 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6498 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6499 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6502 if (! in_dest
&& ! unsignedp
6503 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6505 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6506 pos_mode
= mode_for_extraction (EP_extv
, 3);
6507 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6510 /* Never narrow an object, since that might not be safe. */
6512 if (mode
!= VOIDmode
6513 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6514 extraction_mode
= mode
;
6516 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6517 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6518 pos_mode
= GET_MODE (pos_rtx
);
6520 /* If this is not from memory, the desired mode is the preferred mode
6521 for an extraction pattern's first input operand, or word_mode if there
6524 wanted_inner_mode
= wanted_inner_reg_mode
;
6527 /* Be careful not to go beyond the extracted object and maintain the
6528 natural alignment of the memory. */
6529 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
6530 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
6531 > GET_MODE_BITSIZE (wanted_inner_mode
))
6533 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
6534 gcc_assert (wanted_inner_mode
!= VOIDmode
);
6537 /* If we have to change the mode of memory and cannot, the desired mode
6538 is EXTRACTION_MODE. */
6539 if (inner_mode
!= wanted_inner_mode
6540 && (mode_dependent_address_p (XEXP (inner
, 0))
6541 || MEM_VOLATILE_P (inner
)
6543 wanted_inner_mode
= extraction_mode
;
6548 if (BITS_BIG_ENDIAN
)
6550 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6551 BITS_BIG_ENDIAN style. If position is constant, compute new
6552 position. Otherwise, build subtraction.
6553 Note that POS is relative to the mode of the original argument.
6554 If it's a MEM we need to recompute POS relative to that.
6555 However, if we're extracting from (or inserting into) a register,
6556 we want to recompute POS relative to wanted_inner_mode. */
6557 int width
= (MEM_P (inner
)
6558 ? GET_MODE_BITSIZE (is_mode
)
6559 : GET_MODE_BITSIZE (wanted_inner_mode
));
6562 pos
= width
- len
- pos
;
6565 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6566 /* POS may be less than 0 now, but we check for that below.
6567 Note that it can only be less than 0 if !MEM_P (inner). */
6570 /* If INNER has a wider mode, and this is a constant extraction, try to
6571 make it smaller and adjust the byte to point to the byte containing
6573 if (wanted_inner_mode
!= VOIDmode
6574 && inner_mode
!= wanted_inner_mode
6576 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6578 && ! mode_dependent_address_p (XEXP (inner
, 0))
6579 && ! MEM_VOLATILE_P (inner
))
6583 /* The computations below will be correct if the machine is big
6584 endian in both bits and bytes or little endian in bits and bytes.
6585 If it is mixed, we must adjust. */
6587 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6588 adjust OFFSET to compensate. */
6589 if (BYTES_BIG_ENDIAN
6590 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6591 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6593 /* We can now move to the desired byte. */
6594 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
6595 * GET_MODE_SIZE (wanted_inner_mode
);
6596 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6598 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6599 && is_mode
!= wanted_inner_mode
)
6600 offset
= (GET_MODE_SIZE (is_mode
)
6601 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6603 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6606 /* If INNER is not memory, we can always get it into the proper mode. If we
6607 are changing its mode, POS must be a constant and smaller than the size
6609 else if (!MEM_P (inner
))
6611 if (GET_MODE (inner
) != wanted_inner_mode
6613 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6619 inner
= force_to_mode (inner
, wanted_inner_mode
,
6621 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6622 ? ~(unsigned HOST_WIDE_INT
) 0
6623 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6628 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6629 have to zero extend. Otherwise, we can just use a SUBREG. */
6631 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6633 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6635 /* If we know that no extraneous bits are set, and that the high
6636 bit is not set, convert extraction to cheaper one - either
6637 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6639 if (flag_expensive_optimizations
6640 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6641 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6642 & ~(((unsigned HOST_WIDE_INT
)
6643 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6647 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6649 /* Prefer ZERO_EXTENSION, since it gives more information to
6651 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6656 else if (pos_rtx
!= 0
6657 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6658 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6660 /* Make POS_RTX unless we already have it and it is correct. If we don't
6661 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6663 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6664 pos_rtx
= orig_pos_rtx
;
6666 else if (pos_rtx
== 0)
6667 pos_rtx
= GEN_INT (pos
);
6669 /* Make the required operation. See if we can use existing rtx. */
6670 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6671 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6673 new = gen_lowpart (mode
, new);
6678 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6679 with any other operations in X. Return X without that shift if so. */
6682 extract_left_shift (rtx x
, int count
)
6684 enum rtx_code code
= GET_CODE (x
);
6685 enum machine_mode mode
= GET_MODE (x
);
6691 /* This is the shift itself. If it is wide enough, we will return
6692 either the value being shifted if the shift count is equal to
6693 COUNT or a shift for the difference. */
6694 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6695 && INTVAL (XEXP (x
, 1)) >= count
)
6696 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6697 INTVAL (XEXP (x
, 1)) - count
);
6701 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6702 return simplify_gen_unary (code
, mode
, tem
, mode
);
6706 case PLUS
: case IOR
: case XOR
: case AND
:
6707 /* If we can safely shift this constant and we find the inner shift,
6708 make a new operation. */
6709 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6710 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6711 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6712 return simplify_gen_binary (code
, mode
, tem
,
6713 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6724 /* Look at the expression rooted at X. Look for expressions
6725 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6726 Form these expressions.
6728 Return the new rtx, usually just X.
6730 Also, for machines like the VAX that don't have logical shift insns,
6731 try to convert logical to arithmetic shift operations in cases where
6732 they are equivalent. This undoes the canonicalizations to logical
6733 shifts done elsewhere.
6735 We try, as much as possible, to re-use rtl expressions to save memory.
6737 IN_CODE says what kind of expression we are processing. Normally, it is
6738 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6739 being kludges), it is MEM. When processing the arguments of a comparison
6740 or a COMPARE against zero, it is COMPARE. */
6743 make_compound_operation (rtx x
, enum rtx_code in_code
)
6745 enum rtx_code code
= GET_CODE (x
);
6746 enum machine_mode mode
= GET_MODE (x
);
6747 int mode_width
= GET_MODE_BITSIZE (mode
);
6749 enum rtx_code next_code
;
6755 /* Select the code to be used in recursive calls. Once we are inside an
6756 address, we stay there. If we have a comparison, set to COMPARE,
6757 but once inside, go back to our default of SET. */
6759 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6760 : ((code
== COMPARE
|| COMPARISON_P (x
))
6761 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6762 : in_code
== COMPARE
? SET
: in_code
);
6764 /* Process depending on the code of this operation. If NEW is set
6765 nonzero, it will be returned. */
6770 /* Convert shifts by constants into multiplications if inside
6772 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6773 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6774 && INTVAL (XEXP (x
, 1)) >= 0)
6776 new = make_compound_operation (XEXP (x
, 0), next_code
);
6777 new = gen_rtx_MULT (mode
, new,
6778 GEN_INT ((HOST_WIDE_INT
) 1
6779 << INTVAL (XEXP (x
, 1))));
6784 /* If the second operand is not a constant, we can't do anything
6786 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6789 /* If the constant is a power of two minus one and the first operand
6790 is a logical right shift, make an extraction. */
6791 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6792 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6794 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6795 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6796 0, in_code
== COMPARE
);
6799 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6800 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6801 && subreg_lowpart_p (XEXP (x
, 0))
6802 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6803 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6805 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6807 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6808 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6809 0, in_code
== COMPARE
);
6811 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6812 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6813 || GET_CODE (XEXP (x
, 0)) == IOR
)
6814 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6815 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6816 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6818 /* Apply the distributive law, and then try to make extractions. */
6819 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6820 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6822 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6824 new = make_compound_operation (new, in_code
);
6827 /* If we are have (and (rotate X C) M) and C is larger than the number
6828 of bits in M, this is an extraction. */
6830 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6831 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6832 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6833 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6835 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6836 new = make_extraction (mode
, new,
6837 (GET_MODE_BITSIZE (mode
)
6838 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6839 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6842 /* On machines without logical shifts, if the operand of the AND is
6843 a logical shift and our mask turns off all the propagated sign
6844 bits, we can replace the logical shift with an arithmetic shift. */
6845 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6846 && !have_insn_for (LSHIFTRT
, mode
)
6847 && have_insn_for (ASHIFTRT
, mode
)
6848 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6849 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6850 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6851 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6853 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6855 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6856 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6858 gen_rtx_ASHIFTRT (mode
,
6859 make_compound_operation
6860 (XEXP (XEXP (x
, 0), 0), next_code
),
6861 XEXP (XEXP (x
, 0), 1)));
6864 /* If the constant is one less than a power of two, this might be
6865 representable by an extraction even if no shift is present.
6866 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6867 we are in a COMPARE. */
6868 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6869 new = make_extraction (mode
,
6870 make_compound_operation (XEXP (x
, 0),
6872 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6874 /* If we are in a comparison and this is an AND with a power of two,
6875 convert this into the appropriate bit extract. */
6876 else if (in_code
== COMPARE
6877 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6878 new = make_extraction (mode
,
6879 make_compound_operation (XEXP (x
, 0),
6881 i
, NULL_RTX
, 1, 1, 0, 1);
6886 /* If the sign bit is known to be zero, replace this with an
6887 arithmetic shift. */
6888 if (have_insn_for (ASHIFTRT
, mode
)
6889 && ! have_insn_for (LSHIFTRT
, mode
)
6890 && mode_width
<= HOST_BITS_PER_WIDE_INT
6891 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6893 new = gen_rtx_ASHIFTRT (mode
,
6894 make_compound_operation (XEXP (x
, 0),
6900 /* ... fall through ... */
6906 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6907 this is a SIGN_EXTRACT. */
6908 if (GET_CODE (rhs
) == CONST_INT
6909 && GET_CODE (lhs
) == ASHIFT
6910 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6911 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6913 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6914 new = make_extraction (mode
, new,
6915 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6916 NULL_RTX
, mode_width
- INTVAL (rhs
),
6917 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6921 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6922 If so, try to merge the shifts into a SIGN_EXTEND. We could
6923 also do this for some cases of SIGN_EXTRACT, but it doesn't
6924 seem worth the effort; the case checked for occurs on Alpha. */
6927 && ! (GET_CODE (lhs
) == SUBREG
6928 && (OBJECT_P (SUBREG_REG (lhs
))))
6929 && GET_CODE (rhs
) == CONST_INT
6930 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6931 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6932 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6933 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6934 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6939 /* Call ourselves recursively on the inner expression. If we are
6940 narrowing the object and it has a different RTL code from
6941 what it originally did, do this SUBREG as a force_to_mode. */
6943 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6947 simplified
= simplify_subreg (GET_MODE (x
), tem
, GET_MODE (tem
),
6953 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6954 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6955 && subreg_lowpart_p (x
))
6957 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6960 /* If we have something other than a SUBREG, we might have
6961 done an expansion, so rerun ourselves. */
6962 if (GET_CODE (newer
) != SUBREG
)
6963 newer
= make_compound_operation (newer
, in_code
);
6979 x
= gen_lowpart (mode
, new);
6980 code
= GET_CODE (x
);
6983 /* Now recursively process each operand of this operation. */
6984 fmt
= GET_RTX_FORMAT (code
);
6985 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6988 new = make_compound_operation (XEXP (x
, i
), next_code
);
6989 SUBST (XEXP (x
, i
), new);
6992 /* If this is a commutative operation, the changes to the operands
6993 may have made it noncanonical. */
6994 if (COMMUTATIVE_ARITH_P (x
)
6995 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
6998 SUBST (XEXP (x
, 0), XEXP (x
, 1));
6999 SUBST (XEXP (x
, 1), tem
);
7005 /* Given M see if it is a value that would select a field of bits
7006 within an item, but not the entire word. Return -1 if not.
7007 Otherwise, return the starting position of the field, where 0 is the
7010 *PLEN is set to the length of the field. */
7013 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7015 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7016 int pos
= exact_log2 (m
& -m
);
7020 /* Now shift off the low-order zero bits and see if we have a
7021 power of two minus 1. */
7022 len
= exact_log2 ((m
>> pos
) + 1);
7031 /* If X refers to a register that equals REG in value, replace these
7032 references with REG. */
7034 canon_reg_for_combine (rtx x
, rtx reg
)
7041 enum rtx_code code
= GET_CODE (x
);
7042 switch (GET_RTX_CLASS (code
))
7045 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7046 if (op0
!= XEXP (x
, 0))
7047 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7052 case RTX_COMM_ARITH
:
7053 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7054 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7055 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7056 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7060 case RTX_COMM_COMPARE
:
7061 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7062 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7063 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7064 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7065 GET_MODE (op0
), op0
, op1
);
7069 case RTX_BITFIELD_OPS
:
7070 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7071 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7072 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7073 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7074 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7075 GET_MODE (op0
), op0
, op1
, op2
);
7080 if (rtx_equal_p (get_last_value (reg
), x
)
7081 || rtx_equal_p (reg
, get_last_value (x
)))
7090 fmt
= GET_RTX_FORMAT (code
);
7092 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7095 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7096 if (op
!= XEXP (x
, i
))
7106 else if (fmt
[i
] == 'E')
7109 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7111 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
7112 if (op
!= XVECEXP (x
, i
, j
))
7119 XVECEXP (x
, i
, j
) = op
;
7130 /* Return X converted to MODE. If the value is already truncated to
7131 MODE we can just return a subreg even though in the general case we
7132 would need an explicit truncation. */
7135 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
7137 if (GET_MODE_SIZE (GET_MODE (x
)) <= GET_MODE_SIZE (mode
)
7138 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
7139 GET_MODE_BITSIZE (GET_MODE (x
)))
7140 || (REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
7141 return gen_lowpart (mode
, x
);
7143 return simplify_gen_unary (TRUNCATE
, mode
, x
, GET_MODE (x
));
7146 /* See if X can be simplified knowing that we will only refer to it in
7147 MODE and will only refer to those bits that are nonzero in MASK.
7148 If other bits are being computed or if masking operations are done
7149 that select a superset of the bits in MASK, they can sometimes be
7152 Return a possibly simplified expression, but always convert X to
7153 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7155 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7156 are all off in X. This is used when X will be complemented, by either
7157 NOT, NEG, or XOR. */
7160 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
7163 enum rtx_code code
= GET_CODE (x
);
7164 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
7165 enum machine_mode op_mode
;
7166 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
7169 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7170 code below will do the wrong thing since the mode of such an
7171 expression is VOIDmode.
7173 Also do nothing if X is a CLOBBER; this can happen if X was
7174 the return value from a call to gen_lowpart. */
7175 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
7178 /* We want to perform the operation is its present mode unless we know
7179 that the operation is valid in MODE, in which case we do the operation
7181 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
7182 && have_insn_for (code
, mode
))
7183 ? mode
: GET_MODE (x
));
7185 /* It is not valid to do a right-shift in a narrower mode
7186 than the one it came in with. */
7187 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
7188 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
7189 op_mode
= GET_MODE (x
);
7191 /* Truncate MASK to fit OP_MODE. */
7193 mask
&= GET_MODE_MASK (op_mode
);
7195 /* When we have an arithmetic operation, or a shift whose count we
7196 do not know, we need to assume that all bits up to the highest-order
7197 bit in MASK will be needed. This is how we form such a mask. */
7198 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
7199 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
7201 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
7204 /* Determine what bits of X are guaranteed to be (non)zero. */
7205 nonzero
= nonzero_bits (x
, mode
);
7207 /* If none of the bits in X are needed, return a zero. */
7208 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
7211 /* If X is a CONST_INT, return a new one. Do this here since the
7212 test below will fail. */
7213 if (GET_CODE (x
) == CONST_INT
)
7215 if (SCALAR_INT_MODE_P (mode
))
7216 return gen_int_mode (INTVAL (x
) & mask
, mode
);
7219 x
= GEN_INT (INTVAL (x
) & mask
);
7220 return gen_lowpart_common (mode
, x
);
7224 /* If X is narrower than MODE and we want all the bits in X's mode, just
7225 get X in the proper mode. */
7226 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
7227 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
7228 return gen_lowpart (mode
, x
);
7233 /* If X is a (clobber (const_int)), return it since we know we are
7234 generating something that won't match. */
7241 x
= expand_compound_operation (x
);
7242 if (GET_CODE (x
) != code
)
7243 return force_to_mode (x
, mode
, mask
, next_select
);
7247 if (subreg_lowpart_p (x
)
7248 /* We can ignore the effect of this SUBREG if it narrows the mode or
7249 if the constant masks to zero all the bits the mode doesn't
7251 && ((GET_MODE_SIZE (GET_MODE (x
))
7252 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7254 & GET_MODE_MASK (GET_MODE (x
))
7255 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
7256 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
7260 /* If this is an AND with a constant, convert it into an AND
7261 whose constant is the AND of that constant with MASK. If it
7262 remains an AND of MASK, delete it since it is redundant. */
7264 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7266 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
7267 mask
& INTVAL (XEXP (x
, 1)));
7269 /* If X is still an AND, see if it is an AND with a mask that
7270 is just some low-order bits. If so, and it is MASK, we don't
7273 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
7274 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
7278 /* If it remains an AND, try making another AND with the bits
7279 in the mode mask that aren't in MASK turned on. If the
7280 constant in the AND is wide enough, this might make a
7281 cheaper constant. */
7283 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
7284 && GET_MODE_MASK (GET_MODE (x
)) != mask
7285 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
7287 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
7288 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
7289 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
7292 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7293 number, sign extend it. */
7294 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
7295 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7296 cval
|= (HOST_WIDE_INT
) -1 << width
;
7298 y
= simplify_gen_binary (AND
, GET_MODE (x
),
7299 XEXP (x
, 0), GEN_INT (cval
));
7300 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
7310 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7311 low-order bits (as in an alignment operation) and FOO is already
7312 aligned to that boundary, mask C1 to that boundary as well.
7313 This may eliminate that PLUS and, later, the AND. */
7316 unsigned int width
= GET_MODE_BITSIZE (mode
);
7317 unsigned HOST_WIDE_INT smask
= mask
;
7319 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7320 number, sign extend it. */
7322 if (width
< HOST_BITS_PER_WIDE_INT
7323 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7324 smask
|= (HOST_WIDE_INT
) -1 << width
;
7326 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7327 && exact_log2 (- smask
) >= 0
7328 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
7329 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
7330 return force_to_mode (plus_constant (XEXP (x
, 0),
7331 (INTVAL (XEXP (x
, 1)) & smask
)),
7332 mode
, smask
, next_select
);
7335 /* ... fall through ... */
7338 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7339 most significant bit in MASK since carries from those bits will
7340 affect the bits we are interested in. */
7345 /* If X is (minus C Y) where C's least set bit is larger than any bit
7346 in the mask, then we may replace with (neg Y). */
7347 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7348 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
7349 & -INTVAL (XEXP (x
, 0))))
7352 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
7354 return force_to_mode (x
, mode
, mask
, next_select
);
7357 /* Similarly, if C contains every bit in the fuller_mask, then we may
7358 replace with (not Y). */
7359 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7360 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
7361 == INTVAL (XEXP (x
, 0))))
7363 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
7364 XEXP (x
, 1), GET_MODE (x
));
7365 return force_to_mode (x
, mode
, mask
, next_select
);
7373 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7374 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7375 operation which may be a bitfield extraction. Ensure that the
7376 constant we form is not wider than the mode of X. */
7378 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7379 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7380 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7381 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7382 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7383 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7384 + floor_log2 (INTVAL (XEXP (x
, 1))))
7385 < GET_MODE_BITSIZE (GET_MODE (x
)))
7386 && (INTVAL (XEXP (x
, 1))
7387 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7389 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7390 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7391 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
7392 XEXP (XEXP (x
, 0), 0), temp
);
7393 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7394 XEXP (XEXP (x
, 0), 1));
7395 return force_to_mode (x
, mode
, mask
, next_select
);
7399 /* For most binary operations, just propagate into the operation and
7400 change the mode if we have an operation of that mode. */
7402 op0
= gen_lowpart_or_truncate (op_mode
,
7403 force_to_mode (XEXP (x
, 0), mode
, mask
,
7405 op1
= gen_lowpart_or_truncate (op_mode
,
7406 force_to_mode (XEXP (x
, 1), mode
, mask
,
7409 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7410 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
7414 /* For left shifts, do the same, but just for the first operand.
7415 However, we cannot do anything with shifts where we cannot
7416 guarantee that the counts are smaller than the size of the mode
7417 because such a count will have a different meaning in a
7420 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7421 && INTVAL (XEXP (x
, 1)) >= 0
7422 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7423 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7424 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7425 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7428 /* If the shift count is a constant and we can do arithmetic in
7429 the mode of the shift, refine which bits we need. Otherwise, use the
7430 conservative form of the mask. */
7431 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7432 && INTVAL (XEXP (x
, 1)) >= 0
7433 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7434 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7435 mask
>>= INTVAL (XEXP (x
, 1));
7439 op0
= gen_lowpart_or_truncate (op_mode
,
7440 force_to_mode (XEXP (x
, 0), op_mode
,
7441 mask
, next_select
));
7443 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7444 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7448 /* Here we can only do something if the shift count is a constant,
7449 this shift constant is valid for the host, and we can do arithmetic
7452 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7453 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7454 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7456 rtx inner
= XEXP (x
, 0);
7457 unsigned HOST_WIDE_INT inner_mask
;
7459 /* Select the mask of the bits we need for the shift operand. */
7460 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7462 /* We can only change the mode of the shift if we can do arithmetic
7463 in the mode of the shift and INNER_MASK is no wider than the
7464 width of X's mode. */
7465 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
7466 op_mode
= GET_MODE (x
);
7468 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
7470 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7471 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7474 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7475 shift and AND produces only copies of the sign bit (C2 is one less
7476 than a power of two), we can do this with just a shift. */
7478 if (GET_CODE (x
) == LSHIFTRT
7479 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7480 /* The shift puts one of the sign bit copies in the least significant
7482 && ((INTVAL (XEXP (x
, 1))
7483 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7484 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7485 && exact_log2 (mask
+ 1) >= 0
7486 /* Number of bits left after the shift must be more than the mask
7488 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7489 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7490 /* Must be more sign bit copies than the mask needs. */
7491 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7492 >= exact_log2 (mask
+ 1)))
7493 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7494 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7495 - exact_log2 (mask
+ 1)));
7500 /* If we are just looking for the sign bit, we don't need this shift at
7501 all, even if it has a variable count. */
7502 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7503 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7504 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7505 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
7507 /* If this is a shift by a constant, get a mask that contains those bits
7508 that are not copies of the sign bit. We then have two cases: If
7509 MASK only includes those bits, this can be a logical shift, which may
7510 allow simplifications. If MASK is a single-bit field not within
7511 those bits, we are requesting a copy of the sign bit and hence can
7512 shift the sign bit to the appropriate location. */
7514 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7515 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7519 /* If the considered data is wider than HOST_WIDE_INT, we can't
7520 represent a mask for all its bits in a single scalar.
7521 But we only care about the lower bits, so calculate these. */
7523 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7525 nonzero
= ~(HOST_WIDE_INT
) 0;
7527 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7528 is the number of bits a full-width mask would have set.
7529 We need only shift if these are fewer than nonzero can
7530 hold. If not, we must keep all bits set in nonzero. */
7532 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7533 < HOST_BITS_PER_WIDE_INT
)
7534 nonzero
>>= INTVAL (XEXP (x
, 1))
7535 + HOST_BITS_PER_WIDE_INT
7536 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7540 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7541 nonzero
>>= INTVAL (XEXP (x
, 1));
7544 if ((mask
& ~nonzero
) == 0)
7546 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
7547 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
7548 if (GET_CODE (x
) != ASHIFTRT
)
7549 return force_to_mode (x
, mode
, mask
, next_select
);
7552 else if ((i
= exact_log2 (mask
)) >= 0)
7554 x
= simplify_shift_const
7555 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7556 GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7558 if (GET_CODE (x
) != ASHIFTRT
)
7559 return force_to_mode (x
, mode
, mask
, next_select
);
7563 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7564 even if the shift count isn't a constant. */
7566 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7567 XEXP (x
, 0), XEXP (x
, 1));
7571 /* If this is a zero- or sign-extension operation that just affects bits
7572 we don't care about, remove it. Be sure the call above returned
7573 something that is still a shift. */
7575 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7576 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7577 && INTVAL (XEXP (x
, 1)) >= 0
7578 && (INTVAL (XEXP (x
, 1))
7579 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7580 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7581 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7582 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7589 /* If the shift count is constant and we can do computations
7590 in the mode of X, compute where the bits we care about are.
7591 Otherwise, we can't do anything. Don't change the mode of
7592 the shift or propagate MODE into the shift, though. */
7593 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7594 && INTVAL (XEXP (x
, 1)) >= 0)
7596 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7597 GET_MODE (x
), GEN_INT (mask
),
7599 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7601 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7602 INTVAL (temp
), next_select
));
7607 /* If we just want the low-order bit, the NEG isn't needed since it
7608 won't change the low-order bit. */
7610 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
7612 /* We need any bits less significant than the most significant bit in
7613 MASK since carries from those bits will affect the bits we are
7619 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7620 same as the XOR case above. Ensure that the constant we form is not
7621 wider than the mode of X. */
7623 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7624 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7625 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7626 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7627 < GET_MODE_BITSIZE (GET_MODE (x
)))
7628 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7630 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7632 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
7633 XEXP (XEXP (x
, 0), 0), temp
);
7634 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7635 temp
, XEXP (XEXP (x
, 0), 1));
7637 return force_to_mode (x
, mode
, mask
, next_select
);
7640 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7641 use the full mask inside the NOT. */
7645 op0
= gen_lowpart_or_truncate (op_mode
,
7646 force_to_mode (XEXP (x
, 0), mode
, mask
,
7648 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7649 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7653 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7654 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7655 which is equal to STORE_FLAG_VALUE. */
7656 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7657 && GET_MODE (XEXP (x
, 0)) == mode
7658 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7659 && (nonzero_bits (XEXP (x
, 0), mode
)
7660 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7661 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
7666 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7667 written in a narrower mode. We play it safe and do not do so. */
7670 gen_lowpart_or_truncate (GET_MODE (x
),
7671 force_to_mode (XEXP (x
, 1), mode
,
7672 mask
, next_select
)));
7674 gen_lowpart_or_truncate (GET_MODE (x
),
7675 force_to_mode (XEXP (x
, 2), mode
,
7676 mask
, next_select
)));
7683 /* Ensure we return a value of the proper mode. */
7684 return gen_lowpart_or_truncate (mode
, x
);
7687 /* Return nonzero if X is an expression that has one of two values depending on
7688 whether some other value is zero or nonzero. In that case, we return the
7689 value that is being tested, *PTRUE is set to the value if the rtx being
7690 returned has a nonzero value, and *PFALSE is set to the other alternative.
7692 If we return zero, we set *PTRUE and *PFALSE to X. */
7695 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7697 enum machine_mode mode
= GET_MODE (x
);
7698 enum rtx_code code
= GET_CODE (x
);
7699 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7700 unsigned HOST_WIDE_INT nz
;
7702 /* If we are comparing a value against zero, we are done. */
7703 if ((code
== NE
|| code
== EQ
)
7704 && XEXP (x
, 1) == const0_rtx
)
7706 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7707 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7711 /* If this is a unary operation whose operand has one of two values, apply
7712 our opcode to compute those values. */
7713 else if (UNARY_P (x
)
7714 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7716 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7717 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7718 GET_MODE (XEXP (x
, 0)));
7722 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7723 make can't possibly match and would suppress other optimizations. */
7724 else if (code
== COMPARE
)
7727 /* If this is a binary operation, see if either side has only one of two
7728 values. If either one does or if both do and they are conditional on
7729 the same value, compute the new true and false values. */
7730 else if (BINARY_P (x
))
7732 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7733 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7735 if ((cond0
!= 0 || cond1
!= 0)
7736 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7738 /* If if_then_else_cond returned zero, then true/false are the
7739 same rtl. We must copy one of them to prevent invalid rtl
7742 true0
= copy_rtx (true0
);
7743 else if (cond1
== 0)
7744 true1
= copy_rtx (true1
);
7746 if (COMPARISON_P (x
))
7748 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
7750 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
7755 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
7756 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
7759 return cond0
? cond0
: cond1
;
7762 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7763 operands is zero when the other is nonzero, and vice-versa,
7764 and STORE_FLAG_VALUE is 1 or -1. */
7766 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7767 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7769 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7771 rtx op0
= XEXP (XEXP (x
, 0), 1);
7772 rtx op1
= XEXP (XEXP (x
, 1), 1);
7774 cond0
= XEXP (XEXP (x
, 0), 0);
7775 cond1
= XEXP (XEXP (x
, 1), 0);
7777 if (COMPARISON_P (cond0
)
7778 && COMPARISON_P (cond1
)
7779 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
7780 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7781 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7782 || ((swap_condition (GET_CODE (cond0
))
7783 == reversed_comparison_code (cond1
, NULL
))
7784 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7785 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7786 && ! side_effects_p (x
))
7788 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7789 *pfalse
= simplify_gen_binary (MULT
, mode
,
7791 ? simplify_gen_unary (NEG
, mode
,
7799 /* Similarly for MULT, AND and UMIN, except that for these the result
7801 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7802 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7803 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7805 cond0
= XEXP (XEXP (x
, 0), 0);
7806 cond1
= XEXP (XEXP (x
, 1), 0);
7808 if (COMPARISON_P (cond0
)
7809 && COMPARISON_P (cond1
)
7810 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
7811 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7812 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7813 || ((swap_condition (GET_CODE (cond0
))
7814 == reversed_comparison_code (cond1
, NULL
))
7815 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7816 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7817 && ! side_effects_p (x
))
7819 *ptrue
= *pfalse
= const0_rtx
;
7825 else if (code
== IF_THEN_ELSE
)
7827 /* If we have IF_THEN_ELSE already, extract the condition and
7828 canonicalize it if it is NE or EQ. */
7829 cond0
= XEXP (x
, 0);
7830 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7831 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7832 return XEXP (cond0
, 0);
7833 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7835 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7836 return XEXP (cond0
, 0);
7842 /* If X is a SUBREG, we can narrow both the true and false values
7843 if the inner expression, if there is a condition. */
7844 else if (code
== SUBREG
7845 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7848 true0
= simplify_gen_subreg (mode
, true0
,
7849 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7850 false0
= simplify_gen_subreg (mode
, false0
,
7851 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7852 if (true0
&& false0
)
7860 /* If X is a constant, this isn't special and will cause confusions
7861 if we treat it as such. Likewise if it is equivalent to a constant. */
7862 else if (CONSTANT_P (x
)
7863 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7866 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7867 will be least confusing to the rest of the compiler. */
7868 else if (mode
== BImode
)
7870 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7874 /* If X is known to be either 0 or -1, those are the true and
7875 false values when testing X. */
7876 else if (x
== constm1_rtx
|| x
== const0_rtx
7877 || (mode
!= VOIDmode
7878 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7880 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7884 /* Likewise for 0 or a single bit. */
7885 else if (SCALAR_INT_MODE_P (mode
)
7886 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7887 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7889 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7893 /* Otherwise fail; show no condition with true and false values the same. */
7894 *ptrue
= *pfalse
= x
;
7898 /* Return the value of expression X given the fact that condition COND
7899 is known to be true when applied to REG as its first operand and VAL
7900 as its second. X is known to not be shared and so can be modified in
7903 We only handle the simplest cases, and specifically those cases that
7904 arise with IF_THEN_ELSE expressions. */
7907 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7909 enum rtx_code code
= GET_CODE (x
);
7914 if (side_effects_p (x
))
7917 /* If either operand of the condition is a floating point value,
7918 then we have to avoid collapsing an EQ comparison. */
7920 && rtx_equal_p (x
, reg
)
7921 && ! FLOAT_MODE_P (GET_MODE (x
))
7922 && ! FLOAT_MODE_P (GET_MODE (val
)))
7925 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7928 /* If X is (abs REG) and we know something about REG's relationship
7929 with zero, we may be able to simplify this. */
7931 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7934 case GE
: case GT
: case EQ
:
7937 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7939 GET_MODE (XEXP (x
, 0)));
7944 /* The only other cases we handle are MIN, MAX, and comparisons if the
7945 operands are the same as REG and VAL. */
7947 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
7949 if (rtx_equal_p (XEXP (x
, 0), val
))
7950 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7952 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7954 if (COMPARISON_P (x
))
7956 if (comparison_dominates_p (cond
, code
))
7957 return const_true_rtx
;
7959 code
= reversed_comparison_code (x
, NULL
);
7961 && comparison_dominates_p (cond
, code
))
7966 else if (code
== SMAX
|| code
== SMIN
7967 || code
== UMIN
|| code
== UMAX
)
7969 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7971 /* Do not reverse the condition when it is NE or EQ.
7972 This is because we cannot conclude anything about
7973 the value of 'SMAX (x, y)' when x is not equal to y,
7974 but we can when x equals y. */
7975 if ((code
== SMAX
|| code
== UMAX
)
7976 && ! (cond
== EQ
|| cond
== NE
))
7977 cond
= reverse_condition (cond
);
7982 return unsignedp
? x
: XEXP (x
, 1);
7984 return unsignedp
? x
: XEXP (x
, 0);
7986 return unsignedp
? XEXP (x
, 1) : x
;
7988 return unsignedp
? XEXP (x
, 0) : x
;
7995 else if (code
== SUBREG
)
7997 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7998 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8000 if (SUBREG_REG (x
) != r
)
8002 /* We must simplify subreg here, before we lose track of the
8003 original inner_mode. */
8004 new = simplify_subreg (GET_MODE (x
), r
,
8005 inner_mode
, SUBREG_BYTE (x
));
8009 SUBST (SUBREG_REG (x
), r
);
8014 /* We don't have to handle SIGN_EXTEND here, because even in the
8015 case of replacing something with a modeless CONST_INT, a
8016 CONST_INT is already (supposed to be) a valid sign extension for
8017 its narrower mode, which implies it's already properly
8018 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8019 story is different. */
8020 else if (code
== ZERO_EXTEND
)
8022 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8023 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8025 if (XEXP (x
, 0) != r
)
8027 /* We must simplify the zero_extend here, before we lose
8028 track of the original inner_mode. */
8029 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8034 SUBST (XEXP (x
, 0), r
);
8040 fmt
= GET_RTX_FORMAT (code
);
8041 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8044 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8045 else if (fmt
[i
] == 'E')
8046 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8047 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8054 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8055 assignment as a field assignment. */
8058 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8060 if (x
== y
|| rtx_equal_p (x
, y
))
8063 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8066 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8067 Note that all SUBREGs of MEM are paradoxical; otherwise they
8068 would have been rewritten. */
8069 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8070 && MEM_P (SUBREG_REG (y
))
8071 && rtx_equal_p (SUBREG_REG (y
),
8072 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8075 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8076 && MEM_P (SUBREG_REG (x
))
8077 && rtx_equal_p (SUBREG_REG (x
),
8078 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8081 /* We used to see if get_last_value of X and Y were the same but that's
8082 not correct. In one direction, we'll cause the assignment to have
8083 the wrong destination and in the case, we'll import a register into this
8084 insn that might have already have been dead. So fail if none of the
8085 above cases are true. */
8089 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8090 Return that assignment if so.
8092 We only handle the most common cases. */
8095 make_field_assignment (rtx x
)
8097 rtx dest
= SET_DEST (x
);
8098 rtx src
= SET_SRC (x
);
8103 unsigned HOST_WIDE_INT len
;
8105 enum machine_mode mode
;
8107 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8108 a clear of a one-bit field. We will have changed it to
8109 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8112 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
8113 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
8114 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
8115 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8117 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8120 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8124 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
8125 && subreg_lowpart_p (XEXP (src
, 0))
8126 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
8127 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
8128 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
8129 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
8130 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
8131 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8133 assign
= make_extraction (VOIDmode
, dest
, 0,
8134 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
8137 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8141 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8143 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
8144 && XEXP (XEXP (src
, 0), 0) == const1_rtx
8145 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8147 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8150 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
8154 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8155 SRC is an AND with all bits of that field set, then we can discard
8157 if (GET_CODE (dest
) == ZERO_EXTRACT
8158 && GET_CODE (XEXP (dest
, 1)) == CONST_INT
8159 && GET_CODE (src
) == AND
8160 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
8162 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
8163 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
8164 unsigned HOST_WIDE_INT ze_mask
;
8166 if (width
>= HOST_BITS_PER_WIDE_INT
)
8169 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
8171 /* Complete overlap. We can remove the source AND. */
8172 if ((and_mask
& ze_mask
) == ze_mask
)
8173 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
8175 /* Partial overlap. We can reduce the source AND. */
8176 if ((and_mask
& ze_mask
) != and_mask
)
8178 mode
= GET_MODE (src
);
8179 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
8180 gen_int_mode (and_mask
& ze_mask
, mode
));
8181 return gen_rtx_SET (VOIDmode
, dest
, src
);
8185 /* The other case we handle is assignments into a constant-position
8186 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8187 a mask that has all one bits except for a group of zero bits and
8188 OTHER is known to have zeros where C1 has ones, this is such an
8189 assignment. Compute the position and length from C1. Shift OTHER
8190 to the appropriate position, force it to the required mode, and
8191 make the extraction. Check for the AND in both operands. */
8193 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
8196 rhs
= expand_compound_operation (XEXP (src
, 0));
8197 lhs
= expand_compound_operation (XEXP (src
, 1));
8199 if (GET_CODE (rhs
) == AND
8200 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
8201 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
8202 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
8203 else if (GET_CODE (lhs
) == AND
8204 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
8205 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
8206 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
8210 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
8211 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
8212 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
8213 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
8216 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
8220 /* The mode to use for the source is the mode of the assignment, or of
8221 what is inside a possible STRICT_LOW_PART. */
8222 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
8223 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
8225 /* Shift OTHER right POS places and make it the source, restricting it
8226 to the proper length and mode. */
8228 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
8232 src
= force_to_mode (src
, mode
,
8233 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
8234 ? ~(unsigned HOST_WIDE_INT
) 0
8235 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
8238 /* If SRC is masked by an AND that does not make a difference in
8239 the value being stored, strip it. */
8240 if (GET_CODE (assign
) == ZERO_EXTRACT
8241 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
8242 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
8243 && GET_CODE (src
) == AND
8244 && GET_CODE (XEXP (src
, 1)) == CONST_INT
8245 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
8246 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
8247 src
= XEXP (src
, 0);
8249 return gen_rtx_SET (VOIDmode
, assign
, src
);
8252 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8256 apply_distributive_law (rtx x
)
8258 enum rtx_code code
= GET_CODE (x
);
8259 enum rtx_code inner_code
;
8260 rtx lhs
, rhs
, other
;
8263 /* Distributivity is not true for floating point as it can change the
8264 value. So we don't do it unless -funsafe-math-optimizations. */
8265 if (FLOAT_MODE_P (GET_MODE (x
))
8266 && ! flag_unsafe_math_optimizations
)
8269 /* The outer operation can only be one of the following: */
8270 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
8271 && code
!= PLUS
&& code
!= MINUS
)
8277 /* If either operand is a primitive we can't do anything, so get out
8279 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
8282 lhs
= expand_compound_operation (lhs
);
8283 rhs
= expand_compound_operation (rhs
);
8284 inner_code
= GET_CODE (lhs
);
8285 if (inner_code
!= GET_CODE (rhs
))
8288 /* See if the inner and outer operations distribute. */
8295 /* These all distribute except over PLUS. */
8296 if (code
== PLUS
|| code
== MINUS
)
8301 if (code
!= PLUS
&& code
!= MINUS
)
8306 /* This is also a multiply, so it distributes over everything. */
8310 /* Non-paradoxical SUBREGs distributes over all operations,
8311 provided the inner modes and byte offsets are the same, this
8312 is an extraction of a low-order part, we don't convert an fp
8313 operation to int or vice versa, this is not a vector mode,
8314 and we would not be converting a single-word operation into a
8315 multi-word operation. The latter test is not required, but
8316 it prevents generating unneeded multi-word operations. Some
8317 of the previous tests are redundant given the latter test,
8318 but are retained because they are required for correctness.
8320 We produce the result slightly differently in this case. */
8322 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
8323 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
8324 || ! subreg_lowpart_p (lhs
)
8325 || (GET_MODE_CLASS (GET_MODE (lhs
))
8326 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
8327 || (GET_MODE_SIZE (GET_MODE (lhs
))
8328 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
8329 || VECTOR_MODE_P (GET_MODE (lhs
))
8330 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
8331 /* Result might need to be truncated. Don't change mode if
8332 explicit truncation is needed. */
8333 || !TRULY_NOOP_TRUNCATION
8334 (GET_MODE_BITSIZE (GET_MODE (x
)),
8335 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs
)))))
8338 tem
= simplify_gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
8339 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
8340 return gen_lowpart (GET_MODE (x
), tem
);
8346 /* Set LHS and RHS to the inner operands (A and B in the example
8347 above) and set OTHER to the common operand (C in the example).
8348 There is only one way to do this unless the inner operation is
8350 if (COMMUTATIVE_ARITH_P (lhs
)
8351 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
8352 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
8353 else if (COMMUTATIVE_ARITH_P (lhs
)
8354 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
8355 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
8356 else if (COMMUTATIVE_ARITH_P (lhs
)
8357 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
8358 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
8359 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
8360 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
8364 /* Form the new inner operation, seeing if it simplifies first. */
8365 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
8367 /* There is one exception to the general way of distributing:
8368 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8369 if (code
== XOR
&& inner_code
== IOR
)
8372 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
8375 /* We may be able to continuing distributing the result, so call
8376 ourselves recursively on the inner operation before forming the
8377 outer operation, which we return. */
8378 return simplify_gen_binary (inner_code
, GET_MODE (x
),
8379 apply_distributive_law (tem
), other
);
8382 /* See if X is of the form (* (+ A B) C), and if so convert to
8383 (+ (* A C) (* B C)) and try to simplify.
8385 Most of the time, this results in no change. However, if some of
8386 the operands are the same or inverses of each other, simplifications
8389 For example, (and (ior A B) (not B)) can occur as the result of
8390 expanding a bit field assignment. When we apply the distributive
8391 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8392 which then simplifies to (and (A (not B))).
8394 Note that no checks happen on the validity of applying the inverse
8395 distributive law. This is pointless since we can do it in the
8396 few places where this routine is called.
8398 N is the index of the term that is decomposed (the arithmetic operation,
8399 i.e. (+ A B) in the first example above). !N is the index of the term that
8400 is distributed, i.e. of C in the first example above. */
8402 distribute_and_simplify_rtx (rtx x
, int n
)
8404 enum machine_mode mode
;
8405 enum rtx_code outer_code
, inner_code
;
8406 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
8408 decomposed
= XEXP (x
, n
);
8409 if (!ARITHMETIC_P (decomposed
))
8412 mode
= GET_MODE (x
);
8413 outer_code
= GET_CODE (x
);
8414 distributed
= XEXP (x
, !n
);
8416 inner_code
= GET_CODE (decomposed
);
8417 inner_op0
= XEXP (decomposed
, 0);
8418 inner_op1
= XEXP (decomposed
, 1);
8420 /* Special case (and (xor B C) (not A)), which is equivalent to
8421 (xor (ior A B) (ior A C)) */
8422 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
8424 distributed
= XEXP (distributed
, 0);
8430 /* Distribute the second term. */
8431 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
8432 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
8436 /* Distribute the first term. */
8437 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
8438 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
8441 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
8443 if (GET_CODE (tmp
) != outer_code
8444 && rtx_cost (tmp
, SET
) < rtx_cost (x
, SET
))
8450 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8451 in MODE. Return an equivalent form, if different from (and VAROP
8452 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8455 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
8456 unsigned HOST_WIDE_INT constop
)
8458 unsigned HOST_WIDE_INT nonzero
;
8459 unsigned HOST_WIDE_INT orig_constop
;
8464 orig_constop
= constop
;
8465 if (GET_CODE (varop
) == CLOBBER
)
8468 /* Simplify VAROP knowing that we will be only looking at some of the
8471 Note by passing in CONSTOP, we guarantee that the bits not set in
8472 CONSTOP are not significant and will never be examined. We must
8473 ensure that is the case by explicitly masking out those bits
8474 before returning. */
8475 varop
= force_to_mode (varop
, mode
, constop
, 0);
8477 /* If VAROP is a CLOBBER, we will fail so return it. */
8478 if (GET_CODE (varop
) == CLOBBER
)
8481 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8482 to VAROP and return the new constant. */
8483 if (GET_CODE (varop
) == CONST_INT
)
8484 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
8486 /* See what bits may be nonzero in VAROP. Unlike the general case of
8487 a call to nonzero_bits, here we don't care about bits outside
8490 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
8492 /* Turn off all bits in the constant that are known to already be zero.
8493 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8494 which is tested below. */
8498 /* If we don't have any bits left, return zero. */
8502 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8503 a power of two, we can replace this with an ASHIFT. */
8504 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
8505 && (i
= exact_log2 (constop
)) >= 0)
8506 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
8508 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8509 or XOR, then try to apply the distributive law. This may eliminate
8510 operations if either branch can be simplified because of the AND.
8511 It may also make some cases more complex, but those cases probably
8512 won't match a pattern either with or without this. */
8514 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8518 apply_distributive_law
8519 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8520 simplify_and_const_int (NULL_RTX
,
8524 simplify_and_const_int (NULL_RTX
,
8529 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8530 the AND and see if one of the operands simplifies to zero. If so, we
8531 may eliminate it. */
8533 if (GET_CODE (varop
) == PLUS
8534 && exact_log2 (constop
+ 1) >= 0)
8538 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8539 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8540 if (o0
== const0_rtx
)
8542 if (o1
== const0_rtx
)
8546 /* Make a SUBREG if necessary. If we can't make it, fail. */
8547 varop
= gen_lowpart (mode
, varop
);
8548 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
8551 /* If we are only masking insignificant bits, return VAROP. */
8552 if (constop
== nonzero
)
8555 if (varop
== orig_varop
&& constop
== orig_constop
)
8558 /* Otherwise, return an AND. */
8559 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
8563 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8566 Return an equivalent form, if different from X. Otherwise, return X. If
8567 X is zero, we are to always construct the equivalent form. */
8570 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
8571 unsigned HOST_WIDE_INT constop
)
8573 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
8578 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
8579 gen_int_mode (constop
, mode
));
8580 if (GET_MODE (x
) != mode
)
8581 x
= gen_lowpart (mode
, x
);
8585 /* Given a REG, X, compute which bits in X can be nonzero.
8586 We don't care about bits outside of those defined in MODE.
8588 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8589 a shift, AND, or zero_extract, we can do better. */
8592 reg_nonzero_bits_for_combine (rtx x
, enum machine_mode mode
,
8593 rtx known_x ATTRIBUTE_UNUSED
,
8594 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
8595 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
8596 unsigned HOST_WIDE_INT
*nonzero
)
8600 /* If X is a register whose nonzero bits value is current, use it.
8601 Otherwise, if X is a register whose value we can find, use that
8602 value. Otherwise, use the previously-computed global nonzero bits
8603 for this register. */
8605 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8606 && (reg_stat
[REGNO (x
)].last_set_mode
== mode
8607 || (GET_MODE_CLASS (reg_stat
[REGNO (x
)].last_set_mode
) == MODE_INT
8608 && GET_MODE_CLASS (mode
) == MODE_INT
))
8609 && ((reg_stat
[REGNO (x
)].last_set_label
>= label_tick_ebb_start
8610 && reg_stat
[REGNO (x
)].last_set_label
< label_tick
)
8611 || (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8612 && DF_INSN_LUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_luid
)
8613 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8614 && REG_N_SETS (REGNO (x
)) == 1
8616 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
8618 *nonzero
&= reg_stat
[REGNO (x
)].last_set_nonzero_bits
;
8622 tem
= get_last_value (x
);
8626 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8627 /* If X is narrower than MODE and TEM is a non-negative
8628 constant that would appear negative in the mode of X,
8629 sign-extend it for use in reg_nonzero_bits because some
8630 machines (maybe most) will actually do the sign-extension
8631 and this is the conservative approach.
8633 ??? For 2.5, try to tighten up the MD files in this regard
8634 instead of this kludge. */
8636 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
8637 && GET_CODE (tem
) == CONST_INT
8639 && 0 != (INTVAL (tem
)
8640 & ((HOST_WIDE_INT
) 1
8641 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8642 tem
= GEN_INT (INTVAL (tem
)
8643 | ((HOST_WIDE_INT
) (-1)
8644 << GET_MODE_BITSIZE (GET_MODE (x
))));
8648 else if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].nonzero_bits
)
8650 unsigned HOST_WIDE_INT mask
= reg_stat
[REGNO (x
)].nonzero_bits
;
8652 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
8653 /* We don't know anything about the upper bits. */
8654 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8661 /* Return the number of bits at the high-order end of X that are known to
8662 be equal to the sign bit. X will be used in mode MODE; if MODE is
8663 VOIDmode, X will be used in its own mode. The returned value will always
8664 be between 1 and the number of bits in MODE. */
8667 reg_num_sign_bit_copies_for_combine (rtx x
, enum machine_mode mode
,
8668 rtx known_x ATTRIBUTE_UNUSED
,
8669 enum machine_mode known_mode
8671 unsigned int known_ret ATTRIBUTE_UNUSED
,
8672 unsigned int *result
)
8676 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8677 && reg_stat
[REGNO (x
)].last_set_mode
== mode
8678 && ((reg_stat
[REGNO (x
)].last_set_label
>= label_tick_ebb_start
8679 && reg_stat
[REGNO (x
)].last_set_label
< label_tick
)
8680 || (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8681 && DF_INSN_LUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_luid
)
8682 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8683 && REG_N_SETS (REGNO (x
)) == 1
8685 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
8687 *result
= reg_stat
[REGNO (x
)].last_set_sign_bit_copies
;
8691 tem
= get_last_value (x
);
8695 if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].sign_bit_copies
!= 0
8696 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
8697 *result
= reg_stat
[REGNO (x
)].sign_bit_copies
;
8702 /* Return the number of "extended" bits there are in X, when interpreted
8703 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8704 unsigned quantities, this is the number of high-order zero bits.
8705 For signed quantities, this is the number of copies of the sign bit
8706 minus 1. In both case, this function returns the number of "spare"
8707 bits. For example, if two quantities for which this function returns
8708 at least 1 are added, the addition is known not to overflow.
8710 This function will always return 0 unless called during combine, which
8711 implies that it must be called from a define_split. */
8714 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8716 if (nonzero_sign_valid
== 0)
8720 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8721 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8722 - floor_log2 (nonzero_bits (x
, mode
)))
8724 : num_sign_bit_copies (x
, mode
) - 1);
8727 /* This function is called from `simplify_shift_const' to merge two
8728 outer operations. Specifically, we have already found that we need
8729 to perform operation *POP0 with constant *PCONST0 at the outermost
8730 position. We would now like to also perform OP1 with constant CONST1
8731 (with *POP0 being done last).
8733 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8734 the resulting operation. *PCOMP_P is set to 1 if we would need to
8735 complement the innermost operand, otherwise it is unchanged.
8737 MODE is the mode in which the operation will be done. No bits outside
8738 the width of this mode matter. It is assumed that the width of this mode
8739 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8741 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8742 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8743 result is simply *PCONST0.
8745 If the resulting operation cannot be expressed as one operation, we
8746 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8749 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8751 enum rtx_code op0
= *pop0
;
8752 HOST_WIDE_INT const0
= *pconst0
;
8754 const0
&= GET_MODE_MASK (mode
);
8755 const1
&= GET_MODE_MASK (mode
);
8757 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8761 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8764 if (op1
== UNKNOWN
|| op0
== SET
)
8767 else if (op0
== UNKNOWN
)
8768 op0
= op1
, const0
= const1
;
8770 else if (op0
== op1
)
8794 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8795 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8798 /* If the two constants aren't the same, we can't do anything. The
8799 remaining six cases can all be done. */
8800 else if (const0
!= const1
)
8808 /* (a & b) | b == b */
8810 else /* op1 == XOR */
8811 /* (a ^ b) | b == a | b */
8817 /* (a & b) ^ b == (~a) & b */
8818 op0
= AND
, *pcomp_p
= 1;
8819 else /* op1 == IOR */
8820 /* (a | b) ^ b == a & ~b */
8821 op0
= AND
, const0
= ~const0
;
8826 /* (a | b) & b == b */
8828 else /* op1 == XOR */
8829 /* (a ^ b) & b) == (~a) & b */
8836 /* Check for NO-OP cases. */
8837 const0
&= GET_MODE_MASK (mode
);
8839 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8841 else if (const0
== 0 && op0
== AND
)
8843 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8847 /* ??? Slightly redundant with the above mask, but not entirely.
8848 Moving this above means we'd have to sign-extend the mode mask
8849 for the final test. */
8850 const0
= trunc_int_for_mode (const0
, mode
);
8858 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8859 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8860 simplify it. Otherwise, return a simplified value.
8862 The shift is normally computed in the widest mode we find in VAROP, as
8863 long as it isn't a different number of words than RESULT_MODE. Exceptions
8864 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8867 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
8868 rtx varop
, int orig_count
)
8870 enum rtx_code orig_code
= code
;
8871 rtx orig_varop
= varop
;
8873 enum machine_mode mode
= result_mode
;
8874 enum machine_mode shift_mode
, tmode
;
8875 unsigned int mode_words
8876 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8877 /* We form (outer_op (code varop count) (outer_const)). */
8878 enum rtx_code outer_op
= UNKNOWN
;
8879 HOST_WIDE_INT outer_const
= 0;
8880 int complement_p
= 0;
8883 /* Make sure and truncate the "natural" shift on the way in. We don't
8884 want to do this inside the loop as it makes it more difficult to
8886 if (SHIFT_COUNT_TRUNCATED
)
8887 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
8889 /* If we were given an invalid count, don't do anything except exactly
8890 what was requested. */
8892 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
8897 /* Unless one of the branches of the `if' in this loop does a `continue',
8898 we will `break' the loop after the `if'. */
8902 /* If we have an operand of (clobber (const_int 0)), fail. */
8903 if (GET_CODE (varop
) == CLOBBER
)
8906 /* If we discovered we had to complement VAROP, leave. Making a NOT
8907 here would cause an infinite loop. */
8911 /* Convert ROTATERT to ROTATE. */
8912 if (code
== ROTATERT
)
8914 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
8916 if (VECTOR_MODE_P (result_mode
))
8917 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
8919 count
= bitsize
- count
;
8922 /* We need to determine what mode we will do the shift in. If the
8923 shift is a right shift or a ROTATE, we must always do it in the mode
8924 it was originally done in. Otherwise, we can do it in MODE, the
8925 widest mode encountered. */
8927 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8928 ? result_mode
: mode
);
8930 /* Handle cases where the count is greater than the size of the mode
8931 minus 1. For ASHIFT, use the size minus one as the count (this can
8932 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8933 take the count modulo the size. For other shifts, the result is
8936 Since these shifts are being produced by the compiler by combining
8937 multiple operations, each of which are defined, we know what the
8938 result is supposed to be. */
8940 if (count
> (GET_MODE_BITSIZE (shift_mode
) - 1))
8942 if (code
== ASHIFTRT
)
8943 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8944 else if (code
== ROTATE
|| code
== ROTATERT
)
8945 count
%= GET_MODE_BITSIZE (shift_mode
);
8948 /* We can't simply return zero because there may be an
8956 /* An arithmetic right shift of a quantity known to be -1 or 0
8958 if (code
== ASHIFTRT
8959 && (num_sign_bit_copies (varop
, shift_mode
)
8960 == GET_MODE_BITSIZE (shift_mode
)))
8966 /* If we are doing an arithmetic right shift and discarding all but
8967 the sign bit copies, this is equivalent to doing a shift by the
8968 bitsize minus one. Convert it into that shift because it will often
8969 allow other simplifications. */
8971 if (code
== ASHIFTRT
8972 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8973 >= GET_MODE_BITSIZE (shift_mode
)))
8974 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8976 /* We simplify the tests below and elsewhere by converting
8977 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8978 `make_compound_operation' will convert it to an ASHIFTRT for
8979 those machines (such as VAX) that don't have an LSHIFTRT. */
8980 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8982 && ((nonzero_bits (varop
, shift_mode
)
8983 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8987 if (((code
== LSHIFTRT
8988 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8989 && !(nonzero_bits (varop
, shift_mode
) >> count
))
8991 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8992 && !((nonzero_bits (varop
, shift_mode
) << count
)
8993 & GET_MODE_MASK (shift_mode
))))
8994 && !side_effects_p (varop
))
8997 switch (GET_CODE (varop
))
9003 new = expand_compound_operation (varop
);
9012 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9013 minus the width of a smaller mode, we can do this with a
9014 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9015 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9016 && ! mode_dependent_address_p (XEXP (varop
, 0))
9017 && ! MEM_VOLATILE_P (varop
)
9018 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9019 MODE_INT
, 1)) != BLKmode
)
9021 new = adjust_address_nv (varop
, tmode
,
9022 BYTES_BIG_ENDIAN
? 0
9023 : count
/ BITS_PER_UNIT
);
9025 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9026 : ZERO_EXTEND
, mode
, new);
9033 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9034 the same number of words as what we've seen so far. Then store
9035 the widest mode in MODE. */
9036 if (subreg_lowpart_p (varop
)
9037 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9038 > GET_MODE_SIZE (GET_MODE (varop
)))
9039 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9040 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9043 varop
= SUBREG_REG (varop
);
9044 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9045 mode
= GET_MODE (varop
);
9051 /* Some machines use MULT instead of ASHIFT because MULT
9052 is cheaper. But it is still better on those machines to
9053 merge two shifts into one. */
9054 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9055 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9058 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
9060 GEN_INT (exact_log2 (
9061 INTVAL (XEXP (varop
, 1)))));
9067 /* Similar, for when divides are cheaper. */
9068 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9069 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9072 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
9074 GEN_INT (exact_log2 (
9075 INTVAL (XEXP (varop
, 1)))));
9081 /* If we are extracting just the sign bit of an arithmetic
9082 right shift, that shift is not needed. However, the sign
9083 bit of a wider mode may be different from what would be
9084 interpreted as the sign bit in a narrower mode, so, if
9085 the result is narrower, don't discard the shift. */
9086 if (code
== LSHIFTRT
9087 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9088 && (GET_MODE_BITSIZE (result_mode
)
9089 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9091 varop
= XEXP (varop
, 0);
9095 /* ... fall through ... */
9100 /* Here we have two nested shifts. The result is usually the
9101 AND of a new shift with a mask. We compute the result below. */
9102 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9103 && INTVAL (XEXP (varop
, 1)) >= 0
9104 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9105 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9106 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9107 && !VECTOR_MODE_P (result_mode
))
9109 enum rtx_code first_code
= GET_CODE (varop
);
9110 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9111 unsigned HOST_WIDE_INT mask
;
9114 /* We have one common special case. We can't do any merging if
9115 the inner code is an ASHIFTRT of a smaller mode. However, if
9116 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9117 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9118 we can convert it to
9119 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9120 This simplifies certain SIGN_EXTEND operations. */
9121 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9122 && count
== (GET_MODE_BITSIZE (result_mode
)
9123 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9125 /* C3 has the low-order C1 bits zero. */
9127 mask
= (GET_MODE_MASK (mode
)
9128 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9130 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9131 XEXP (varop
, 0), mask
);
9132 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9134 count
= first_count
;
9139 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9140 than C1 high-order bits equal to the sign bit, we can convert
9141 this to either an ASHIFT or an ASHIFTRT depending on the
9144 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9146 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9147 && GET_MODE (varop
) == shift_mode
9148 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9151 varop
= XEXP (varop
, 0);
9152 count
-= first_count
;
9162 /* There are some cases we can't do. If CODE is ASHIFTRT,
9163 we can only do this if FIRST_CODE is also ASHIFTRT.
9165 We can't do the case when CODE is ROTATE and FIRST_CODE is
9168 If the mode of this shift is not the mode of the outer shift,
9169 we can't do this if either shift is a right shift or ROTATE.
9171 Finally, we can't do any of these if the mode is too wide
9172 unless the codes are the same.
9174 Handle the case where the shift codes are the same
9177 if (code
== first_code
)
9179 if (GET_MODE (varop
) != result_mode
9180 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9184 count
+= first_count
;
9185 varop
= XEXP (varop
, 0);
9189 if (code
== ASHIFTRT
9190 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9191 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9192 || (GET_MODE (varop
) != result_mode
9193 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9194 || first_code
== ROTATE
9195 || code
== ROTATE
)))
9198 /* To compute the mask to apply after the shift, shift the
9199 nonzero bits of the inner shift the same way the
9200 outer shift will. */
9202 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9205 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
9208 /* Give up if we can't compute an outer operation to use. */
9210 || GET_CODE (mask_rtx
) != CONST_INT
9211 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9213 result_mode
, &complement_p
))
9216 /* If the shifts are in the same direction, we add the
9217 counts. Otherwise, we subtract them. */
9218 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9219 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9220 count
+= first_count
;
9222 count
-= first_count
;
9224 /* If COUNT is positive, the new shift is usually CODE,
9225 except for the two exceptions below, in which case it is
9226 FIRST_CODE. If the count is negative, FIRST_CODE should
9229 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9230 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9233 code
= first_code
, count
= -count
;
9235 varop
= XEXP (varop
, 0);
9239 /* If we have (A << B << C) for any shift, we can convert this to
9240 (A << C << B). This wins if A is a constant. Only try this if
9241 B is not a constant. */
9243 else if (GET_CODE (varop
) == code
9244 && GET_CODE (XEXP (varop
, 0)) == CONST_INT
9245 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
)
9247 rtx
new = simplify_const_binary_operation (code
, mode
,
9250 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9257 /* Make this fit the case below. */
9258 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9259 GEN_INT (GET_MODE_MASK (mode
)));
9265 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9266 with C the size of VAROP - 1 and the shift is logical if
9267 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9268 we have an (le X 0) operation. If we have an arithmetic shift
9269 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9270 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9272 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9273 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9274 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9275 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9276 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9277 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9280 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9283 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9284 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9289 /* If we have (shift (logical)), move the logical to the outside
9290 to allow it to possibly combine with another logical and the
9291 shift to combine with another shift. This also canonicalizes to
9292 what a ZERO_EXTRACT looks like. Also, some machines have
9293 (and (shift)) insns. */
9295 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9296 /* We can't do this if we have (ashiftrt (xor)) and the
9297 constant has its sign bit set in shift_mode. */
9298 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9299 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9301 && (new = simplify_const_binary_operation (code
, result_mode
,
9303 GEN_INT (count
))) != 0
9304 && GET_CODE (new) == CONST_INT
9305 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9306 INTVAL (new), result_mode
, &complement_p
))
9308 varop
= XEXP (varop
, 0);
9312 /* If we can't do that, try to simplify the shift in each arm of the
9313 logical expression, make a new logical expression, and apply
9314 the inverse distributive law. This also can't be done
9315 for some (ashiftrt (xor)). */
9316 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9317 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9318 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9321 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9322 XEXP (varop
, 0), count
);
9323 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9324 XEXP (varop
, 1), count
);
9326 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
9328 varop
= apply_distributive_law (varop
);
9336 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9337 says that the sign bit can be tested, FOO has mode MODE, C is
9338 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9339 that may be nonzero. */
9340 if (code
== LSHIFTRT
9341 && XEXP (varop
, 1) == const0_rtx
9342 && GET_MODE (XEXP (varop
, 0)) == result_mode
9343 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9344 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9345 && STORE_FLAG_VALUE
== -1
9346 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9347 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9348 (HOST_WIDE_INT
) 1, result_mode
,
9351 varop
= XEXP (varop
, 0);
9358 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9359 than the number of bits in the mode is equivalent to A. */
9360 if (code
== LSHIFTRT
9361 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9362 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9364 varop
= XEXP (varop
, 0);
9369 /* NEG commutes with ASHIFT since it is multiplication. Move the
9370 NEG outside to allow shifts to combine. */
9372 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9373 (HOST_WIDE_INT
) 0, result_mode
,
9376 varop
= XEXP (varop
, 0);
9382 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9383 is one less than the number of bits in the mode is
9384 equivalent to (xor A 1). */
9385 if (code
== LSHIFTRT
9386 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9387 && XEXP (varop
, 1) == constm1_rtx
9388 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9389 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9390 (HOST_WIDE_INT
) 1, result_mode
,
9394 varop
= XEXP (varop
, 0);
9398 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9399 that might be nonzero in BAR are those being shifted out and those
9400 bits are known zero in FOO, we can replace the PLUS with FOO.
9401 Similarly in the other operand order. This code occurs when
9402 we are computing the size of a variable-size array. */
9404 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9405 && count
< HOST_BITS_PER_WIDE_INT
9406 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9407 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9408 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9410 varop
= XEXP (varop
, 0);
9413 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9414 && count
< HOST_BITS_PER_WIDE_INT
9415 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9416 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9418 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9419 & nonzero_bits (XEXP (varop
, 1),
9422 varop
= XEXP (varop
, 1);
9426 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9428 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9429 && (new = simplify_const_binary_operation (ASHIFT
, result_mode
,
9431 GEN_INT (count
))) != 0
9432 && GET_CODE (new) == CONST_INT
9433 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9434 INTVAL (new), result_mode
, &complement_p
))
9436 varop
= XEXP (varop
, 0);
9440 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9441 signbit', and attempt to change the PLUS to an XOR and move it to
9442 the outer operation as is done above in the AND/IOR/XOR case
9443 leg for shift(logical). See details in logical handling above
9444 for reasoning in doing so. */
9445 if (code
== LSHIFTRT
9446 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9447 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
9448 && (new = simplify_const_binary_operation (code
, result_mode
,
9450 GEN_INT (count
))) != 0
9451 && GET_CODE (new) == CONST_INT
9452 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9453 INTVAL (new), result_mode
, &complement_p
))
9455 varop
= XEXP (varop
, 0);
9462 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9463 with C the size of VAROP - 1 and the shift is logical if
9464 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9465 we have a (gt X 0) operation. If the shift is arithmetic with
9466 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9467 we have a (neg (gt X 0)) operation. */
9469 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9470 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9471 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9472 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9473 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9474 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9475 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9478 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9481 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9482 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9489 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9490 if the truncate does not affect the value. */
9491 if (code
== LSHIFTRT
9492 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9493 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9494 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9495 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9496 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9498 rtx varop_inner
= XEXP (varop
, 0);
9501 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9502 XEXP (varop_inner
, 0),
9504 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9505 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9518 /* We need to determine what mode to do the shift in. If the shift is
9519 a right shift or ROTATE, we must always do it in the mode it was
9520 originally done in. Otherwise, we can do it in MODE, the widest mode
9521 encountered. The code we care about is that of the shift that will
9522 actually be done, not the shift that was originally requested. */
9524 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9525 ? result_mode
: mode
);
9527 /* We have now finished analyzing the shift. The result should be
9528 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9529 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9530 to the result of the shift. OUTER_CONST is the relevant constant,
9531 but we must turn off all bits turned off in the shift. */
9533 if (outer_op
== UNKNOWN
9534 && orig_code
== code
&& orig_count
== count
9535 && varop
== orig_varop
9536 && shift_mode
== GET_MODE (varop
))
9539 /* Make a SUBREG if necessary. If we can't make it, fail. */
9540 varop
= gen_lowpart (shift_mode
, varop
);
9541 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9544 /* If we have an outer operation and we just made a shift, it is
9545 possible that we could have simplified the shift were it not
9546 for the outer operation. So try to do the simplification
9549 if (outer_op
!= UNKNOWN
)
9550 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
9555 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
9557 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9558 turn off all the bits that the shift would have turned off. */
9559 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9560 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9561 GET_MODE_MASK (result_mode
) >> orig_count
);
9563 /* Do the remainder of the processing in RESULT_MODE. */
9564 x
= gen_lowpart_or_truncate (result_mode
, x
);
9566 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9569 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9571 if (outer_op
!= UNKNOWN
)
9573 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9574 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9576 if (outer_op
== AND
)
9577 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9578 else if (outer_op
== SET
)
9580 /* This means that we have determined that the result is
9581 equivalent to a constant. This should be rare. */
9582 if (!side_effects_p (x
))
9583 x
= GEN_INT (outer_const
);
9585 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
9586 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9588 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
9589 GEN_INT (outer_const
));
9595 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9596 The result of the shift is RESULT_MODE. If we cannot simplify it,
9597 return X or, if it is NULL, synthesize the expression with
9598 simplify_gen_binary. Otherwise, return a simplified value.
9600 The shift is normally computed in the widest mode we find in VAROP, as
9601 long as it isn't a different number of words than RESULT_MODE. Exceptions
9602 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9605 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
9606 rtx varop
, int count
)
9608 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
9613 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
9614 if (GET_MODE (x
) != result_mode
)
9615 x
= gen_lowpart (result_mode
, x
);
9620 /* Like recog, but we receive the address of a pointer to a new pattern.
9621 We try to match the rtx that the pointer points to.
9622 If that fails, we may try to modify or replace the pattern,
9623 storing the replacement into the same pointer object.
9625 Modifications include deletion or addition of CLOBBERs.
9627 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9628 the CLOBBERs are placed.
9630 The value is the final insn code from the pattern ultimately matched,
9634 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9637 int insn_code_number
;
9638 int num_clobbers_to_add
= 0;
9641 rtx old_notes
, old_pat
;
9643 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9644 we use to indicate that something didn't match. If we find such a
9645 thing, force rejection. */
9646 if (GET_CODE (pat
) == PARALLEL
)
9647 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9648 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9649 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9652 old_pat
= PATTERN (insn
);
9653 old_notes
= REG_NOTES (insn
);
9654 PATTERN (insn
) = pat
;
9655 REG_NOTES (insn
) = 0;
9657 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9659 /* If it isn't, there is the possibility that we previously had an insn
9660 that clobbered some register as a side effect, but the combined
9661 insn doesn't need to do that. So try once more without the clobbers
9662 unless this represents an ASM insn. */
9664 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9665 && GET_CODE (pat
) == PARALLEL
)
9669 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9670 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9673 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9677 SUBST_INT (XVECLEN (pat
, 0), pos
);
9680 pat
= XVECEXP (pat
, 0, 0);
9682 PATTERN (insn
) = pat
;
9683 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9685 PATTERN (insn
) = old_pat
;
9686 REG_NOTES (insn
) = old_notes
;
9688 /* Recognize all noop sets, these will be killed by followup pass. */
9689 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9690 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9692 /* If we had any clobbers to add, make a new pattern than contains
9693 them. Then check to make sure that all of them are dead. */
9694 if (num_clobbers_to_add
)
9696 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9697 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9699 + num_clobbers_to_add
)
9700 : num_clobbers_to_add
+ 1));
9702 if (GET_CODE (pat
) == PARALLEL
)
9703 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9704 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9706 XVECEXP (newpat
, 0, 0) = pat
;
9708 add_clobbers (newpat
, insn_code_number
);
9710 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9711 i
< XVECLEN (newpat
, 0); i
++)
9713 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
9714 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9716 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
9718 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
9719 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9720 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9729 return insn_code_number
;
9732 /* Like gen_lowpart_general but for use by combine. In combine it
9733 is not possible to create any new pseudoregs. However, it is
9734 safe to create invalid memory addresses, because combine will
9735 try to recognize them and all they will do is make the combine
9738 If for some reason this cannot do its job, an rtx
9739 (clobber (const_int 0)) is returned.
9740 An insn containing that will not be recognized. */
9743 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
9745 enum machine_mode imode
= GET_MODE (x
);
9746 unsigned int osize
= GET_MODE_SIZE (omode
);
9747 unsigned int isize
= GET_MODE_SIZE (imode
);
9753 /* Return identity if this is a CONST or symbolic reference. */
9755 && (GET_CODE (x
) == CONST
9756 || GET_CODE (x
) == SYMBOL_REF
9757 || GET_CODE (x
) == LABEL_REF
))
9760 /* We can only support MODE being wider than a word if X is a
9761 constant integer or has a mode the same size. */
9762 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
9763 && ! ((imode
== VOIDmode
9764 && (GET_CODE (x
) == CONST_INT
9765 || GET_CODE (x
) == CONST_DOUBLE
))
9769 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9770 won't know what to do. So we will strip off the SUBREG here and
9771 process normally. */
9772 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
9776 /* For use in case we fall down into the address adjustments
9777 further below, we need to adjust the known mode and size of
9778 x; imode and isize, since we just adjusted x. */
9779 imode
= GET_MODE (x
);
9784 isize
= GET_MODE_SIZE (imode
);
9787 result
= gen_lowpart_common (omode
, x
);
9796 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9798 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9801 /* If we want to refer to something bigger than the original memref,
9802 generate a paradoxical subreg instead. That will force a reload
9803 of the original memref X. */
9805 return gen_rtx_SUBREG (omode
, x
, 0);
9807 if (WORDS_BIG_ENDIAN
)
9808 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
9810 /* Adjust the address so that the address-after-the-data is
9812 if (BYTES_BIG_ENDIAN
)
9813 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
9815 return adjust_address_nv (x
, omode
, offset
);
9818 /* If X is a comparison operator, rewrite it in a new mode. This
9819 probably won't match, but may allow further simplifications. */
9820 else if (COMPARISON_P (x
))
9821 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
9823 /* If we couldn't simplify X any other way, just enclose it in a
9824 SUBREG. Normally, this SUBREG won't match, but some patterns may
9825 include an explicit SUBREG or we may simplify it further in combine. */
9831 offset
= subreg_lowpart_offset (omode
, imode
);
9832 if (imode
== VOIDmode
)
9834 imode
= int_mode_for_mode (omode
);
9835 x
= gen_lowpart_common (imode
, x
);
9839 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
9845 return gen_rtx_CLOBBER (imode
, const0_rtx
);
9848 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9849 comparison code that will be tested.
9851 The result is a possibly different comparison code to use. *POP0 and
9852 *POP1 may be updated.
9854 It is possible that we might detect that a comparison is either always
9855 true or always false. However, we do not perform general constant
9856 folding in combine, so this knowledge isn't useful. Such tautologies
9857 should have been detected earlier. Hence we ignore all such cases. */
9859 static enum rtx_code
9860 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
9866 enum machine_mode mode
, tmode
;
9868 /* Try a few ways of applying the same transformation to both operands. */
9871 #ifndef WORD_REGISTER_OPERATIONS
9872 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9873 so check specially. */
9874 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9875 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9876 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9877 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9878 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9879 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9880 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9881 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9882 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9883 && XEXP (op0
, 1) == XEXP (op1
, 1)
9884 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
9885 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
9886 && (INTVAL (XEXP (op0
, 1))
9887 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9889 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9891 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9892 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9896 /* If both operands are the same constant shift, see if we can ignore the
9897 shift. We can if the shift is a rotate or if the bits shifted out of
9898 this shift are known to be zero for both inputs and if the type of
9899 comparison is compatible with the shift. */
9900 if (GET_CODE (op0
) == GET_CODE (op1
)
9901 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9902 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9903 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9904 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9905 || (GET_CODE (op0
) == ASHIFTRT
9906 && (code
!= GTU
&& code
!= LTU
9907 && code
!= GEU
&& code
!= LEU
)))
9908 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9909 && INTVAL (XEXP (op0
, 1)) >= 0
9910 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9911 && XEXP (op0
, 1) == XEXP (op1
, 1))
9913 enum machine_mode mode
= GET_MODE (op0
);
9914 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9915 int shift_count
= INTVAL (XEXP (op0
, 1));
9917 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9918 mask
&= (mask
>> shift_count
) << shift_count
;
9919 else if (GET_CODE (op0
) == ASHIFT
)
9920 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9922 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
9923 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
9924 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9929 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9930 SUBREGs are of the same mode, and, in both cases, the AND would
9931 be redundant if the comparison was done in the narrower mode,
9932 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9933 and the operand's possibly nonzero bits are 0xffffff01; in that case
9934 if we only care about QImode, we don't need the AND). This case
9935 occurs if the output mode of an scc insn is not SImode and
9936 STORE_FLAG_VALUE == 1 (e.g., the 386).
9938 Similarly, check for a case where the AND's are ZERO_EXTEND
9939 operations from some narrower mode even though a SUBREG is not
9942 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9943 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9944 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9946 rtx inner_op0
= XEXP (op0
, 0);
9947 rtx inner_op1
= XEXP (op1
, 0);
9948 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9949 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9952 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9953 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9954 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9955 && (GET_MODE (SUBREG_REG (inner_op0
))
9956 == GET_MODE (SUBREG_REG (inner_op1
)))
9957 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9958 <= HOST_BITS_PER_WIDE_INT
)
9959 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9960 GET_MODE (SUBREG_REG (inner_op0
)))))
9961 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9962 GET_MODE (SUBREG_REG (inner_op1
))))))
9964 op0
= SUBREG_REG (inner_op0
);
9965 op1
= SUBREG_REG (inner_op1
);
9967 /* The resulting comparison is always unsigned since we masked
9968 off the original sign bit. */
9969 code
= unsigned_condition (code
);
9975 for (tmode
= GET_CLASS_NARROWEST_MODE
9976 (GET_MODE_CLASS (GET_MODE (op0
)));
9977 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9978 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9980 op0
= gen_lowpart (tmode
, inner_op0
);
9981 op1
= gen_lowpart (tmode
, inner_op1
);
9982 code
= unsigned_condition (code
);
9991 /* If both operands are NOT, we can strip off the outer operation
9992 and adjust the comparison code for swapped operands; similarly for
9993 NEG, except that this must be an equality comparison. */
9994 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9995 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9996 && (code
== EQ
|| code
== NE
)))
9997 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10003 /* If the first operand is a constant, swap the operands and adjust the
10004 comparison code appropriately, but don't do this if the second operand
10005 is already a constant integer. */
10006 if (swap_commutative_operands_p (op0
, op1
))
10008 tem
= op0
, op0
= op1
, op1
= tem
;
10009 code
= swap_condition (code
);
10012 /* We now enter a loop during which we will try to simplify the comparison.
10013 For the most part, we only are concerned with comparisons with zero,
10014 but some things may really be comparisons with zero but not start
10015 out looking that way. */
10017 while (GET_CODE (op1
) == CONST_INT
)
10019 enum machine_mode mode
= GET_MODE (op0
);
10020 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10021 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10022 int equality_comparison_p
;
10023 int sign_bit_comparison_p
;
10024 int unsigned_comparison_p
;
10025 HOST_WIDE_INT const_op
;
10027 /* We only want to handle integral modes. This catches VOIDmode,
10028 CCmode, and the floating-point modes. An exception is that we
10029 can handle VOIDmode if OP0 is a COMPARE or a comparison
10032 if (GET_MODE_CLASS (mode
) != MODE_INT
10033 && ! (mode
== VOIDmode
10034 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
10037 /* Get the constant we are comparing against and turn off all bits
10038 not on in our mode. */
10039 const_op
= INTVAL (op1
);
10040 if (mode
!= VOIDmode
)
10041 const_op
= trunc_int_for_mode (const_op
, mode
);
10042 op1
= GEN_INT (const_op
);
10044 /* If we are comparing against a constant power of two and the value
10045 being compared can only have that single bit nonzero (e.g., it was
10046 `and'ed with that bit), we can replace this with a comparison
10049 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10050 || code
== LT
|| code
== LTU
)
10051 && mode_width
<= HOST_BITS_PER_WIDE_INT
10052 && exact_log2 (const_op
) >= 0
10053 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10055 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10056 op1
= const0_rtx
, const_op
= 0;
10059 /* Similarly, if we are comparing a value known to be either -1 or
10060 0 with -1, change it to the opposite comparison against zero. */
10063 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10064 || code
== GEU
|| code
== LTU
)
10065 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10067 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10068 op1
= const0_rtx
, const_op
= 0;
10071 /* Do some canonicalizations based on the comparison code. We prefer
10072 comparisons against zero and then prefer equality comparisons.
10073 If we can reduce the size of a constant, we will do that too. */
10078 /* < C is equivalent to <= (C - 1) */
10082 op1
= GEN_INT (const_op
);
10084 /* ... fall through to LE case below. */
10090 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10094 op1
= GEN_INT (const_op
);
10098 /* If we are doing a <= 0 comparison on a value known to have
10099 a zero sign bit, we can replace this with == 0. */
10100 else if (const_op
== 0
10101 && mode_width
<= HOST_BITS_PER_WIDE_INT
10102 && (nonzero_bits (op0
, mode
)
10103 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10108 /* >= C is equivalent to > (C - 1). */
10112 op1
= GEN_INT (const_op
);
10114 /* ... fall through to GT below. */
10120 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10124 op1
= GEN_INT (const_op
);
10128 /* If we are doing a > 0 comparison on a value known to have
10129 a zero sign bit, we can replace this with != 0. */
10130 else if (const_op
== 0
10131 && mode_width
<= HOST_BITS_PER_WIDE_INT
10132 && (nonzero_bits (op0
, mode
)
10133 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10138 /* < C is equivalent to <= (C - 1). */
10142 op1
= GEN_INT (const_op
);
10144 /* ... fall through ... */
10147 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10148 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10149 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10151 const_op
= 0, op1
= const0_rtx
;
10159 /* unsigned <= 0 is equivalent to == 0 */
10163 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10164 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10165 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10167 const_op
= 0, op1
= const0_rtx
;
10173 /* >= C is equivalent to > (C - 1). */
10177 op1
= GEN_INT (const_op
);
10179 /* ... fall through ... */
10182 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10183 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10184 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10186 const_op
= 0, op1
= const0_rtx
;
10194 /* unsigned > 0 is equivalent to != 0 */
10198 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10199 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10200 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10202 const_op
= 0, op1
= const0_rtx
;
10211 /* Compute some predicates to simplify code below. */
10213 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10214 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10215 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10218 /* If this is a sign bit comparison and we can do arithmetic in
10219 MODE, say that we will only be needing the sign bit of OP0. */
10220 if (sign_bit_comparison_p
10221 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10222 op0
= force_to_mode (op0
, mode
,
10224 << (GET_MODE_BITSIZE (mode
) - 1)),
10227 /* Now try cases based on the opcode of OP0. If none of the cases
10228 does a "continue", we exit this loop immediately after the
10231 switch (GET_CODE (op0
))
10234 /* If we are extracting a single bit from a variable position in
10235 a constant that has only a single bit set and are comparing it
10236 with zero, we can convert this into an equality comparison
10237 between the position and the location of the single bit. */
10238 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10239 have already reduced the shift count modulo the word size. */
10240 if (!SHIFT_COUNT_TRUNCATED
10241 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
10242 && XEXP (op0
, 1) == const1_rtx
10243 && equality_comparison_p
&& const_op
== 0
10244 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10246 if (BITS_BIG_ENDIAN
)
10248 enum machine_mode new_mode
10249 = mode_for_extraction (EP_extzv
, 1);
10250 if (new_mode
== MAX_MACHINE_MODE
)
10251 i
= BITS_PER_WORD
- 1 - i
;
10255 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10259 op0
= XEXP (op0
, 2);
10263 /* Result is nonzero iff shift count is equal to I. */
10264 code
= reverse_condition (code
);
10268 /* ... fall through ... */
10271 tem
= expand_compound_operation (op0
);
10280 /* If testing for equality, we can take the NOT of the constant. */
10281 if (equality_comparison_p
10282 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10284 op0
= XEXP (op0
, 0);
10289 /* If just looking at the sign bit, reverse the sense of the
10291 if (sign_bit_comparison_p
)
10293 op0
= XEXP (op0
, 0);
10294 code
= (code
== GE
? LT
: GE
);
10300 /* If testing for equality, we can take the NEG of the constant. */
10301 if (equality_comparison_p
10302 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10304 op0
= XEXP (op0
, 0);
10309 /* The remaining cases only apply to comparisons with zero. */
10313 /* When X is ABS or is known positive,
10314 (neg X) is < 0 if and only if X != 0. */
10316 if (sign_bit_comparison_p
10317 && (GET_CODE (XEXP (op0
, 0)) == ABS
10318 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10319 && (nonzero_bits (XEXP (op0
, 0), mode
)
10320 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10322 op0
= XEXP (op0
, 0);
10323 code
= (code
== LT
? NE
: EQ
);
10327 /* If we have NEG of something whose two high-order bits are the
10328 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10329 if (num_sign_bit_copies (op0
, mode
) >= 2)
10331 op0
= XEXP (op0
, 0);
10332 code
= swap_condition (code
);
10338 /* If we are testing equality and our count is a constant, we
10339 can perform the inverse operation on our RHS. */
10340 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10341 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10342 op1
, XEXP (op0
, 1))) != 0)
10344 op0
= XEXP (op0
, 0);
10349 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10350 a particular bit. Convert it to an AND of a constant of that
10351 bit. This will be converted into a ZERO_EXTRACT. */
10352 if (const_op
== 0 && sign_bit_comparison_p
10353 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10354 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10356 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10359 - INTVAL (XEXP (op0
, 1)))));
10360 code
= (code
== LT
? NE
: EQ
);
10364 /* Fall through. */
10367 /* ABS is ignorable inside an equality comparison with zero. */
10368 if (const_op
== 0 && equality_comparison_p
)
10370 op0
= XEXP (op0
, 0);
10376 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10377 (compare FOO CONST) if CONST fits in FOO's mode and we
10378 are either testing inequality or have an unsigned
10379 comparison with ZERO_EXTEND or a signed comparison with
10380 SIGN_EXTEND. But don't do it if we don't have a compare
10381 insn of the given mode, since we'd have to revert it
10382 later on, and then we wouldn't know whether to sign- or
10384 mode
= GET_MODE (XEXP (op0
, 0));
10385 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10386 && ! unsigned_comparison_p
10387 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10388 && ((unsigned HOST_WIDE_INT
) const_op
10389 < (((unsigned HOST_WIDE_INT
) 1
10390 << (GET_MODE_BITSIZE (mode
) - 1))))
10391 && cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
10393 op0
= XEXP (op0
, 0);
10399 /* Check for the case where we are comparing A - C1 with C2, that is
10401 (subreg:MODE (plus (A) (-C1))) op (C2)
10403 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10404 comparison in the wider mode. One of the following two conditions
10405 must be true in order for this to be valid:
10407 1. The mode extension results in the same bit pattern being added
10408 on both sides and the comparison is equality or unsigned. As
10409 C2 has been truncated to fit in MODE, the pattern can only be
10412 2. The mode extension results in the sign bit being copied on
10415 The difficulty here is that we have predicates for A but not for
10416 (A - C1) so we need to check that C1 is within proper bounds so
10417 as to perturbate A as little as possible. */
10419 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10420 && subreg_lowpart_p (op0
)
10421 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
10422 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10423 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
)
10425 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
10426 rtx a
= XEXP (SUBREG_REG (op0
), 0);
10427 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
10430 && (unsigned HOST_WIDE_INT
) c1
10431 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
10432 && (equality_comparison_p
|| unsigned_comparison_p
)
10433 /* (A - C1) zero-extends if it is positive and sign-extends
10434 if it is negative, C2 both zero- and sign-extends. */
10435 && ((0 == (nonzero_bits (a
, inner_mode
)
10436 & ~GET_MODE_MASK (mode
))
10438 /* (A - C1) sign-extends if it is positive and 1-extends
10439 if it is negative, C2 both sign- and 1-extends. */
10440 || (num_sign_bit_copies (a
, inner_mode
)
10441 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10444 || ((unsigned HOST_WIDE_INT
) c1
10445 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
10446 /* (A - C1) always sign-extends, like C2. */
10447 && num_sign_bit_copies (a
, inner_mode
)
10448 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10449 - (mode_width
- 1))))
10451 op0
= SUBREG_REG (op0
);
10456 /* If the inner mode is narrower and we are extracting the low part,
10457 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10458 if (subreg_lowpart_p (op0
)
10459 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10460 /* Fall through */ ;
10464 /* ... fall through ... */
10467 mode
= GET_MODE (XEXP (op0
, 0));
10468 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10469 && (unsigned_comparison_p
|| equality_comparison_p
)
10470 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10471 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
10472 && cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
10474 op0
= XEXP (op0
, 0);
10480 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10481 this for equality comparisons due to pathological cases involving
10483 if (equality_comparison_p
10484 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10485 op1
, XEXP (op0
, 1))))
10487 op0
= XEXP (op0
, 0);
10492 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10493 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10494 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10496 op0
= XEXP (XEXP (op0
, 0), 0);
10497 code
= (code
== LT
? EQ
: NE
);
10503 /* We used to optimize signed comparisons against zero, but that
10504 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10505 arrive here as equality comparisons, or (GEU, LTU) are
10506 optimized away. No need to special-case them. */
10508 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10509 (eq B (minus A C)), whichever simplifies. We can only do
10510 this for equality comparisons due to pathological cases involving
10512 if (equality_comparison_p
10513 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10514 XEXP (op0
, 1), op1
)))
10516 op0
= XEXP (op0
, 0);
10521 if (equality_comparison_p
10522 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10523 XEXP (op0
, 0), op1
)))
10525 op0
= XEXP (op0
, 1);
10530 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10531 of bits in X minus 1, is one iff X > 0. */
10532 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10533 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10534 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10536 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10538 op0
= XEXP (op0
, 1);
10539 code
= (code
== GE
? LE
: GT
);
10545 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10546 if C is zero or B is a constant. */
10547 if (equality_comparison_p
10548 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10549 XEXP (op0
, 1), op1
)))
10551 op0
= XEXP (op0
, 0);
10558 case UNEQ
: case LTGT
:
10559 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10560 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10561 case UNORDERED
: case ORDERED
:
10562 /* We can't do anything if OP0 is a condition code value, rather
10563 than an actual data value. */
10565 || CC0_P (XEXP (op0
, 0))
10566 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10569 /* Get the two operands being compared. */
10570 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10571 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10573 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10575 /* Check for the cases where we simply want the result of the
10576 earlier test or the opposite of that result. */
10577 if (code
== NE
|| code
== EQ
10578 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10579 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10580 && (STORE_FLAG_VALUE
10581 & (((HOST_WIDE_INT
) 1
10582 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10583 && (code
== LT
|| code
== GE
)))
10585 enum rtx_code new_code
;
10586 if (code
== LT
|| code
== NE
)
10587 new_code
= GET_CODE (op0
);
10589 new_code
= reversed_comparison_code (op0
, NULL
);
10591 if (new_code
!= UNKNOWN
)
10602 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10604 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10605 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10606 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10608 op0
= XEXP (op0
, 1);
10609 code
= (code
== GE
? GT
: LE
);
10615 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10616 will be converted to a ZERO_EXTRACT later. */
10617 if (const_op
== 0 && equality_comparison_p
10618 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10619 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10621 op0
= simplify_and_const_int
10622 (NULL_RTX
, mode
, gen_rtx_LSHIFTRT (mode
,
10624 XEXP (XEXP (op0
, 0), 1)),
10625 (HOST_WIDE_INT
) 1);
10629 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10630 zero and X is a comparison and C1 and C2 describe only bits set
10631 in STORE_FLAG_VALUE, we can compare with X. */
10632 if (const_op
== 0 && equality_comparison_p
10633 && mode_width
<= HOST_BITS_PER_WIDE_INT
10634 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10635 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10636 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10637 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10638 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10640 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10641 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10642 if ((~STORE_FLAG_VALUE
& mask
) == 0
10643 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
10644 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10645 && COMPARISON_P (tem
))))
10647 op0
= XEXP (XEXP (op0
, 0), 0);
10652 /* If we are doing an equality comparison of an AND of a bit equal
10653 to the sign bit, replace this with a LT or GE comparison of
10654 the underlying value. */
10655 if (equality_comparison_p
10657 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10658 && mode_width
<= HOST_BITS_PER_WIDE_INT
10659 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10660 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10662 op0
= XEXP (op0
, 0);
10663 code
= (code
== EQ
? GE
: LT
);
10667 /* If this AND operation is really a ZERO_EXTEND from a narrower
10668 mode, the constant fits within that mode, and this is either an
10669 equality or unsigned comparison, try to do this comparison in
10674 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10675 -> (ne:DI (reg:SI 4) (const_int 0))
10677 unless TRULY_NOOP_TRUNCATION allows it or the register is
10678 known to hold a value of the required mode the
10679 transformation is invalid. */
10680 if ((equality_comparison_p
|| unsigned_comparison_p
)
10681 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10682 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10683 & GET_MODE_MASK (mode
))
10685 && const_op
>> i
== 0
10686 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
10687 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
10688 GET_MODE_BITSIZE (GET_MODE (op0
)))
10689 || (REG_P (XEXP (op0
, 0))
10690 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
10692 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10696 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10697 fits in both M1 and M2 and the SUBREG is either paradoxical
10698 or represents the low part, permute the SUBREG and the AND
10700 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10702 unsigned HOST_WIDE_INT c1
;
10703 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10704 /* Require an integral mode, to avoid creating something like
10706 if (SCALAR_INT_MODE_P (tmode
)
10707 /* It is unsafe to commute the AND into the SUBREG if the
10708 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10709 not defined. As originally written the upper bits
10710 have a defined value due to the AND operation.
10711 However, if we commute the AND inside the SUBREG then
10712 they no longer have defined values and the meaning of
10713 the code has been changed. */
10715 #ifdef WORD_REGISTER_OPERATIONS
10716 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10717 && mode_width
<= BITS_PER_WORD
)
10719 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10720 && subreg_lowpart_p (XEXP (op0
, 0))))
10721 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10722 && mode_width
<= HOST_BITS_PER_WIDE_INT
10723 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10724 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10725 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10727 && c1
!= GET_MODE_MASK (tmode
))
10729 op0
= simplify_gen_binary (AND
, tmode
,
10730 SUBREG_REG (XEXP (op0
, 0)),
10731 gen_int_mode (c1
, tmode
));
10732 op0
= gen_lowpart (mode
, op0
);
10737 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10738 if (const_op
== 0 && equality_comparison_p
10739 && XEXP (op0
, 1) == const1_rtx
10740 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10742 op0
= simplify_and_const_int
10743 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10744 code
= (code
== NE
? EQ
: NE
);
10748 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10749 (eq (and (lshiftrt X) 1) 0).
10750 Also handle the case where (not X) is expressed using xor. */
10751 if (const_op
== 0 && equality_comparison_p
10752 && XEXP (op0
, 1) == const1_rtx
10753 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10755 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10756 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10758 if (GET_CODE (shift_op
) == NOT
10759 || (GET_CODE (shift_op
) == XOR
10760 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
10761 && GET_CODE (shift_count
) == CONST_INT
10762 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10763 && (INTVAL (XEXP (shift_op
, 1))
10764 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
10766 op0
= simplify_and_const_int
10768 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
10769 (HOST_WIDE_INT
) 1);
10770 code
= (code
== NE
? EQ
: NE
);
10777 /* If we have (compare (ashift FOO N) (const_int C)) and
10778 the high order N bits of FOO (N+1 if an inequality comparison)
10779 are known to be zero, we can do this by comparing FOO with C
10780 shifted right N bits so long as the low-order N bits of C are
10782 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10783 && INTVAL (XEXP (op0
, 1)) >= 0
10784 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10785 < HOST_BITS_PER_WIDE_INT
)
10787 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10788 && mode_width
<= HOST_BITS_PER_WIDE_INT
10789 && (nonzero_bits (XEXP (op0
, 0), mode
)
10790 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10791 + ! equality_comparison_p
))) == 0)
10793 /* We must perform a logical shift, not an arithmetic one,
10794 as we want the top N bits of C to be zero. */
10795 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10797 temp
>>= INTVAL (XEXP (op0
, 1));
10798 op1
= gen_int_mode (temp
, mode
);
10799 op0
= XEXP (op0
, 0);
10803 /* If we are doing a sign bit comparison, it means we are testing
10804 a particular bit. Convert it to the appropriate AND. */
10805 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10806 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10808 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10811 - INTVAL (XEXP (op0
, 1)))));
10812 code
= (code
== LT
? NE
: EQ
);
10816 /* If this an equality comparison with zero and we are shifting
10817 the low bit to the sign bit, we can convert this to an AND of the
10819 if (const_op
== 0 && equality_comparison_p
10820 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10821 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10824 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10825 (HOST_WIDE_INT
) 1);
10831 /* If this is an equality comparison with zero, we can do this
10832 as a logical shift, which might be much simpler. */
10833 if (equality_comparison_p
&& const_op
== 0
10834 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10836 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10838 INTVAL (XEXP (op0
, 1)));
10842 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10843 do the comparison in a narrower mode. */
10844 if (! unsigned_comparison_p
10845 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10846 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10847 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10848 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10849 MODE_INT
, 1)) != BLKmode
10850 && (((unsigned HOST_WIDE_INT
) const_op
10851 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10852 <= GET_MODE_MASK (tmode
)))
10854 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
10858 /* Likewise if OP0 is a PLUS of a sign extension with a
10859 constant, which is usually represented with the PLUS
10860 between the shifts. */
10861 if (! unsigned_comparison_p
10862 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10863 && GET_CODE (XEXP (op0
, 0)) == PLUS
10864 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10865 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10866 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10867 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10868 MODE_INT
, 1)) != BLKmode
10869 && (((unsigned HOST_WIDE_INT
) const_op
10870 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10871 <= GET_MODE_MASK (tmode
)))
10873 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10874 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10875 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
10876 add_const
, XEXP (op0
, 1));
10878 op0
= simplify_gen_binary (PLUS
, tmode
,
10879 gen_lowpart (tmode
, inner
),
10884 /* ... fall through ... */
10886 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10887 the low order N bits of FOO are known to be zero, we can do this
10888 by comparing FOO with C shifted left N bits so long as no
10889 overflow occurs. */
10890 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10891 && INTVAL (XEXP (op0
, 1)) >= 0
10892 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10893 && mode_width
<= HOST_BITS_PER_WIDE_INT
10894 && (nonzero_bits (XEXP (op0
, 0), mode
)
10895 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10896 && (((unsigned HOST_WIDE_INT
) const_op
10897 + (GET_CODE (op0
) != LSHIFTRT
10898 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
10901 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
10903 /* If the shift was logical, then we must make the condition
10905 if (GET_CODE (op0
) == LSHIFTRT
)
10906 code
= unsigned_condition (code
);
10908 const_op
<<= INTVAL (XEXP (op0
, 1));
10909 op1
= GEN_INT (const_op
);
10910 op0
= XEXP (op0
, 0);
10914 /* If we are using this shift to extract just the sign bit, we
10915 can replace this with an LT or GE comparison. */
10917 && (equality_comparison_p
|| sign_bit_comparison_p
)
10918 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10919 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10922 op0
= XEXP (op0
, 0);
10923 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10935 /* Now make any compound operations involved in this comparison. Then,
10936 check for an outmost SUBREG on OP0 that is not doing anything or is
10937 paradoxical. The latter transformation must only be performed when
10938 it is known that the "extra" bits will be the same in op0 and op1 or
10939 that they don't matter. There are three cases to consider:
10941 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10942 care bits and we can assume they have any convenient value. So
10943 making the transformation is safe.
10945 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10946 In this case the upper bits of op0 are undefined. We should not make
10947 the simplification in that case as we do not know the contents of
10950 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10951 UNKNOWN. In that case we know those bits are zeros or ones. We must
10952 also be sure that they are the same as the upper bits of op1.
10954 We can never remove a SUBREG for a non-equality comparison because
10955 the sign bit is in a different place in the underlying object. */
10957 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10958 op1
= make_compound_operation (op1
, SET
);
10960 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10961 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10962 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
10963 && (code
== NE
|| code
== EQ
))
10965 if (GET_MODE_SIZE (GET_MODE (op0
))
10966 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
10968 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10970 if (REG_P (SUBREG_REG (op0
)))
10972 op0
= SUBREG_REG (op0
);
10973 op1
= gen_lowpart (GET_MODE (op0
), op1
);
10976 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10977 <= HOST_BITS_PER_WIDE_INT
)
10978 && (nonzero_bits (SUBREG_REG (op0
),
10979 GET_MODE (SUBREG_REG (op0
)))
10980 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10982 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
10984 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10985 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10986 op0
= SUBREG_REG (op0
), op1
= tem
;
10990 /* We now do the opposite procedure: Some machines don't have compare
10991 insns in all modes. If OP0's mode is an integer mode smaller than a
10992 word and we can't do a compare in that mode, see if there is a larger
10993 mode for which we can do the compare. There are a number of cases in
10994 which we can use the wider mode. */
10996 mode
= GET_MODE (op0
);
10997 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10998 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10999 && ! have_insn_for (COMPARE
, mode
))
11000 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11002 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11003 tmode
= GET_MODE_WIDER_MODE (tmode
))
11004 if (have_insn_for (COMPARE
, tmode
))
11008 /* If the only nonzero bits in OP0 and OP1 are those in the
11009 narrower mode and this is an equality or unsigned comparison,
11010 we can use the wider mode. Similarly for sign-extended
11011 values, in which case it is true for all comparisons. */
11012 zero_extended
= ((code
== EQ
|| code
== NE
11013 || code
== GEU
|| code
== GTU
11014 || code
== LEU
|| code
== LTU
)
11015 && (nonzero_bits (op0
, tmode
)
11016 & ~GET_MODE_MASK (mode
)) == 0
11017 && ((GET_CODE (op1
) == CONST_INT
11018 || (nonzero_bits (op1
, tmode
)
11019 & ~GET_MODE_MASK (mode
)) == 0)));
11022 || ((num_sign_bit_copies (op0
, tmode
)
11023 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11024 - GET_MODE_BITSIZE (mode
)))
11025 && (num_sign_bit_copies (op1
, tmode
)
11026 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11027 - GET_MODE_BITSIZE (mode
)))))
11029 /* If OP0 is an AND and we don't have an AND in MODE either,
11030 make a new AND in the proper mode. */
11031 if (GET_CODE (op0
) == AND
11032 && !have_insn_for (AND
, mode
))
11033 op0
= simplify_gen_binary (AND
, tmode
,
11034 gen_lowpart (tmode
,
11036 gen_lowpart (tmode
,
11039 op0
= gen_lowpart (tmode
, op0
);
11040 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11041 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11042 op1
= gen_lowpart (tmode
, op1
);
11046 /* If this is a test for negative, we can make an explicit
11047 test of the sign bit. */
11049 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11050 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11052 op0
= simplify_gen_binary (AND
, tmode
,
11053 gen_lowpart (tmode
, op0
),
11054 GEN_INT ((HOST_WIDE_INT
) 1
11055 << (GET_MODE_BITSIZE (mode
)
11057 code
= (code
== LT
) ? NE
: EQ
;
11062 #ifdef CANONICALIZE_COMPARISON
11063 /* If this machine only supports a subset of valid comparisons, see if we
11064 can convert an unsupported one into a supported one. */
11065 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11074 /* Utility function for record_value_for_reg. Count number of
11079 enum rtx_code code
= GET_CODE (x
);
11083 if (GET_RTX_CLASS (code
) == '2'
11084 || GET_RTX_CLASS (code
) == 'c')
11086 rtx x0
= XEXP (x
, 0);
11087 rtx x1
= XEXP (x
, 1);
11090 return 1 + 2 * count_rtxs (x0
);
11092 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11093 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11094 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11095 return 2 + 2 * count_rtxs (x0
)
11096 + count_rtxs (x
== XEXP (x1
, 0)
11097 ? XEXP (x1
, 1) : XEXP (x1
, 0));
11099 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11100 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11101 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11102 return 2 + 2 * count_rtxs (x1
)
11103 + count_rtxs (x
== XEXP (x0
, 0)
11104 ? XEXP (x0
, 1) : XEXP (x0
, 0));
11107 fmt
= GET_RTX_FORMAT (code
);
11108 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11110 ret
+= count_rtxs (XEXP (x
, i
));
11115 /* Utility function for following routine. Called when X is part of a value
11116 being stored into last_set_value. Sets last_set_table_tick
11117 for each register mentioned. Similar to mention_regs in cse.c */
11120 update_table_tick (rtx x
)
11122 enum rtx_code code
= GET_CODE (x
);
11123 const char *fmt
= GET_RTX_FORMAT (code
);
11128 unsigned int regno
= REGNO (x
);
11129 unsigned int endregno
= END_REGNO (x
);
11132 for (r
= regno
; r
< endregno
; r
++)
11133 reg_stat
[r
].last_set_table_tick
= label_tick
;
11138 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11139 /* Note that we can't have an "E" in values stored; see
11140 get_last_value_validate. */
11143 /* Check for identical subexpressions. If x contains
11144 identical subexpression we only have to traverse one of
11146 if (i
== 0 && ARITHMETIC_P (x
))
11148 /* Note that at this point x1 has already been
11150 rtx x0
= XEXP (x
, 0);
11151 rtx x1
= XEXP (x
, 1);
11153 /* If x0 and x1 are identical then there is no need to
11158 /* If x0 is identical to a subexpression of x1 then while
11159 processing x1, x0 has already been processed. Thus we
11160 are done with x. */
11161 if (ARITHMETIC_P (x1
)
11162 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11165 /* If x1 is identical to a subexpression of x0 then we
11166 still have to process the rest of x0. */
11167 if (ARITHMETIC_P (x0
)
11168 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11170 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11175 update_table_tick (XEXP (x
, i
));
11179 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11180 are saying that the register is clobbered and we no longer know its
11181 value. If INSN is zero, don't update reg_stat[].last_set; this is
11182 only permitted with VALUE also zero and is used to invalidate the
11186 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11188 unsigned int regno
= REGNO (reg
);
11189 unsigned int endregno
= END_REGNO (reg
);
11192 /* If VALUE contains REG and we have a previous value for REG, substitute
11193 the previous value. */
11194 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11198 /* Set things up so get_last_value is allowed to see anything set up to
11200 subst_low_luid
= DF_INSN_LUID (insn
);
11201 tem
= get_last_value (reg
);
11203 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11204 it isn't going to be useful and will take a lot of time to process,
11205 so just use the CLOBBER. */
11209 if (ARITHMETIC_P (tem
)
11210 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11211 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11212 tem
= XEXP (tem
, 0);
11213 else if (count_occurrences (value
, reg
, 1) >= 2)
11215 /* If there are two or more occurrences of REG in VALUE,
11216 prevent the value from growing too much. */
11217 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
11218 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
11221 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11225 /* For each register modified, show we don't know its value, that
11226 we don't know about its bitwise content, that its value has been
11227 updated, and that we don't know the location of the death of the
11229 for (i
= regno
; i
< endregno
; i
++)
11232 reg_stat
[i
].last_set
= insn
;
11234 reg_stat
[i
].last_set_value
= 0;
11235 reg_stat
[i
].last_set_mode
= 0;
11236 reg_stat
[i
].last_set_nonzero_bits
= 0;
11237 reg_stat
[i
].last_set_sign_bit_copies
= 0;
11238 reg_stat
[i
].last_death
= 0;
11239 reg_stat
[i
].truncated_to_mode
= 0;
11242 /* Mark registers that are being referenced in this value. */
11244 update_table_tick (value
);
11246 /* Now update the status of each register being set.
11247 If someone is using this register in this block, set this register
11248 to invalid since we will get confused between the two lives in this
11249 basic block. This makes using this register always invalid. In cse, we
11250 scan the table to invalidate all entries using this register, but this
11251 is too much work for us. */
11253 for (i
= regno
; i
< endregno
; i
++)
11255 reg_stat
[i
].last_set_label
= label_tick
;
11257 || (value
&& reg_stat
[i
].last_set_table_tick
>= label_tick_ebb_start
))
11258 reg_stat
[i
].last_set_invalid
= 1;
11260 reg_stat
[i
].last_set_invalid
= 0;
11263 /* The value being assigned might refer to X (like in "x++;"). In that
11264 case, we must replace it with (clobber (const_int 0)) to prevent
11266 if (value
&& ! get_last_value_validate (&value
, insn
,
11267 reg_stat
[regno
].last_set_label
, 0))
11269 value
= copy_rtx (value
);
11270 if (! get_last_value_validate (&value
, insn
,
11271 reg_stat
[regno
].last_set_label
, 1))
11275 /* For the main register being modified, update the value, the mode, the
11276 nonzero bits, and the number of sign bit copies. */
11278 reg_stat
[regno
].last_set_value
= value
;
11282 enum machine_mode mode
= GET_MODE (reg
);
11283 subst_low_luid
= DF_INSN_LUID (insn
);
11284 reg_stat
[regno
].last_set_mode
= mode
;
11285 if (GET_MODE_CLASS (mode
) == MODE_INT
11286 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11287 mode
= nonzero_bits_mode
;
11288 reg_stat
[regno
].last_set_nonzero_bits
= nonzero_bits (value
, mode
);
11289 reg_stat
[regno
].last_set_sign_bit_copies
11290 = num_sign_bit_copies (value
, GET_MODE (reg
));
11294 /* Called via note_stores from record_dead_and_set_regs to handle one
11295 SET or CLOBBER in an insn. DATA is the instruction in which the
11296 set is occurring. */
11299 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11301 rtx record_dead_insn
= (rtx
) data
;
11303 if (GET_CODE (dest
) == SUBREG
)
11304 dest
= SUBREG_REG (dest
);
11306 if (!record_dead_insn
)
11309 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
11315 /* If we are setting the whole register, we know its value. Otherwise
11316 show that we don't know the value. We can handle SUBREG in
11318 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11319 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11320 else if (GET_CODE (setter
) == SET
11321 && GET_CODE (SET_DEST (setter
)) == SUBREG
11322 && SUBREG_REG (SET_DEST (setter
)) == dest
11323 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11324 && subreg_lowpart_p (SET_DEST (setter
)))
11325 record_value_for_reg (dest
, record_dead_insn
,
11326 gen_lowpart (GET_MODE (dest
),
11327 SET_SRC (setter
)));
11329 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11331 else if (MEM_P (dest
)
11332 /* Ignore pushes, they clobber nothing. */
11333 && ! push_operand (dest
, GET_MODE (dest
)))
11334 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
11337 /* Update the records of when each REG was most recently set or killed
11338 for the things done by INSN. This is the last thing done in processing
11339 INSN in the combiner loop.
11341 We update reg_stat[], in particular fields last_set, last_set_value,
11342 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11343 last_death, and also the similar information mem_last_set (which insn
11344 most recently modified memory) and last_call_luid (which insn was the
11345 most recent subroutine call). */
11348 record_dead_and_set_regs (rtx insn
)
11353 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11355 if (REG_NOTE_KIND (link
) == REG_DEAD
11356 && REG_P (XEXP (link
, 0)))
11358 unsigned int regno
= REGNO (XEXP (link
, 0));
11359 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
11361 for (i
= regno
; i
< endregno
; i
++)
11362 reg_stat
[i
].last_death
= insn
;
11364 else if (REG_NOTE_KIND (link
) == REG_INC
)
11365 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11370 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11371 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11373 reg_stat
[i
].last_set_invalid
= 1;
11374 reg_stat
[i
].last_set
= insn
;
11375 reg_stat
[i
].last_set_value
= 0;
11376 reg_stat
[i
].last_set_mode
= 0;
11377 reg_stat
[i
].last_set_nonzero_bits
= 0;
11378 reg_stat
[i
].last_set_sign_bit_copies
= 0;
11379 reg_stat
[i
].last_death
= 0;
11380 reg_stat
[i
].truncated_to_mode
= 0;
11383 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
11385 /* We can't combine into a call pattern. Remember, though, that
11386 the return value register is set at this LUID. We could
11387 still replace a register with the return value from the
11388 wrong subroutine call! */
11389 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
11392 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11395 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11396 register present in the SUBREG, so for each such SUBREG go back and
11397 adjust nonzero and sign bit information of the registers that are
11398 known to have some zero/sign bits set.
11400 This is needed because when combine blows the SUBREGs away, the
11401 information on zero/sign bits is lost and further combines can be
11402 missed because of that. */
11405 record_promoted_value (rtx insn
, rtx subreg
)
11408 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11409 enum machine_mode mode
= GET_MODE (subreg
);
11411 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11414 for (links
= LOG_LINKS (insn
); links
;)
11416 insn
= XEXP (links
, 0);
11417 set
= single_set (insn
);
11419 if (! set
|| !REG_P (SET_DEST (set
))
11420 || REGNO (SET_DEST (set
)) != regno
11421 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11423 links
= XEXP (links
, 1);
11427 if (reg_stat
[regno
].last_set
== insn
)
11429 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11430 reg_stat
[regno
].last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
11433 if (REG_P (SET_SRC (set
)))
11435 regno
= REGNO (SET_SRC (set
));
11436 links
= LOG_LINKS (insn
);
11443 /* Check if X, a register, is known to contain a value already
11444 truncated to MODE. In this case we can use a subreg to refer to
11445 the truncated value even though in the generic case we would need
11446 an explicit truncation. */
11449 reg_truncated_to_mode (enum machine_mode mode
, rtx x
)
11451 enum machine_mode truncated
= reg_stat
[REGNO (x
)].truncated_to_mode
;
11454 || reg_stat
[REGNO (x
)].truncation_label
< label_tick_ebb_start
)
11456 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
11458 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
11459 GET_MODE_BITSIZE (truncated
)))
11464 /* X is a REG or a SUBREG. If X is some sort of a truncation record
11465 it. For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11466 a truncate into a subreg using this information. */
11469 record_truncated_value (rtx x
)
11471 enum machine_mode truncated_mode
;
11473 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
11475 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
11476 truncated_mode
= GET_MODE (x
);
11478 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
11481 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode
),
11482 GET_MODE_BITSIZE (original_mode
)))
11485 x
= SUBREG_REG (x
);
11487 /* ??? For hard-regs we now record everything. We might be able to
11488 optimize this using last_set_mode. */
11489 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
11490 truncated_mode
= GET_MODE (x
);
11494 if (reg_stat
[REGNO (x
)].truncated_to_mode
== 0
11495 || reg_stat
[REGNO (x
)].truncation_label
< label_tick_ebb_start
11496 || (GET_MODE_SIZE (truncated_mode
)
11497 < GET_MODE_SIZE (reg_stat
[REGNO (x
)].truncated_to_mode
)))
11499 reg_stat
[REGNO (x
)].truncated_to_mode
= truncated_mode
;
11500 reg_stat
[REGNO (x
)].truncation_label
= label_tick
;
11504 /* Scan X for promoted SUBREGs and truncated REGs. For each one
11505 found, note what it implies to the registers used in it. */
11508 check_conversions (rtx insn
, rtx x
)
11510 if (GET_CODE (x
) == SUBREG
|| REG_P (x
))
11512 if (GET_CODE (x
) == SUBREG
11513 && SUBREG_PROMOTED_VAR_P (x
)
11514 && REG_P (SUBREG_REG (x
)))
11515 record_promoted_value (insn
, x
);
11517 record_truncated_value (x
);
11521 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11524 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11528 check_conversions (insn
, XEXP (x
, i
));
11532 if (XVEC (x
, i
) != 0)
11533 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11534 check_conversions (insn
, XVECEXP (x
, i
, j
));
11540 /* Utility routine for the following function. Verify that all the registers
11541 mentioned in *LOC are valid when *LOC was part of a value set when
11542 label_tick == TICK. Return 0 if some are not.
11544 If REPLACE is nonzero, replace the invalid reference with
11545 (clobber (const_int 0)) and return 1. This replacement is useful because
11546 we often can get useful information about the form of a value (e.g., if
11547 it was produced by a shift that always produces -1 or 0) even though
11548 we don't know exactly what registers it was produced from. */
11551 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11554 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11555 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11560 unsigned int regno
= REGNO (x
);
11561 unsigned int endregno
= END_REGNO (x
);
11564 for (j
= regno
; j
< endregno
; j
++)
11565 if (reg_stat
[j
].last_set_invalid
11566 /* If this is a pseudo-register that was only set once and not
11567 live at the beginning of the function, it is always valid. */
11568 || (! (regno
>= FIRST_PSEUDO_REGISTER
11569 && REG_N_SETS (regno
) == 1
11570 && !REGNO_REG_SET_P
11571 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))
11572 && reg_stat
[j
].last_set_label
> tick
))
11575 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11581 /* If this is a memory reference, make sure that there were
11582 no stores after it that might have clobbered the value. We don't
11583 have alias info, so we assume any store invalidates it. */
11584 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
11585 && DF_INSN_LUID (insn
) <= mem_last_set
)
11588 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11592 for (i
= 0; i
< len
; i
++)
11596 /* Check for identical subexpressions. If x contains
11597 identical subexpression we only have to traverse one of
11599 if (i
== 1 && ARITHMETIC_P (x
))
11601 /* Note that at this point x0 has already been checked
11602 and found valid. */
11603 rtx x0
= XEXP (x
, 0);
11604 rtx x1
= XEXP (x
, 1);
11606 /* If x0 and x1 are identical then x is also valid. */
11610 /* If x1 is identical to a subexpression of x0 then
11611 while checking x0, x1 has already been checked. Thus
11612 it is valid and so as x. */
11613 if (ARITHMETIC_P (x0
)
11614 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11617 /* If x0 is identical to a subexpression of x1 then x is
11618 valid iff the rest of x1 is valid. */
11619 if (ARITHMETIC_P (x1
)
11620 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11622 get_last_value_validate (&XEXP (x1
,
11623 x0
== XEXP (x1
, 0) ? 1 : 0),
11624 insn
, tick
, replace
);
11627 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11631 /* Don't bother with these. They shouldn't occur anyway. */
11632 else if (fmt
[i
] == 'E')
11636 /* If we haven't found a reason for it to be invalid, it is valid. */
11640 /* Get the last value assigned to X, if known. Some registers
11641 in the value may be replaced with (clobber (const_int 0)) if their value
11642 is known longer known reliably. */
11645 get_last_value (rtx x
)
11647 unsigned int regno
;
11650 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11651 then convert it to the desired mode. If this is a paradoxical SUBREG,
11652 we cannot predict what values the "extra" bits might have. */
11653 if (GET_CODE (x
) == SUBREG
11654 && subreg_lowpart_p (x
)
11655 && (GET_MODE_SIZE (GET_MODE (x
))
11656 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11657 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11658 return gen_lowpart (GET_MODE (x
), value
);
11664 value
= reg_stat
[regno
].last_set_value
;
11666 /* If we don't have a value, or if it isn't for this basic block and
11667 it's either a hard register, set more than once, or it's a live
11668 at the beginning of the function, return 0.
11670 Because if it's not live at the beginning of the function then the reg
11671 is always set before being used (is never used without being set).
11672 And, if it's set only once, and it's always set before use, then all
11673 uses must have the same last value, even if it's not from this basic
11677 || (reg_stat
[regno
].last_set_label
< label_tick_ebb_start
11678 && (regno
< FIRST_PSEUDO_REGISTER
11679 || REG_N_SETS (regno
) != 1
11681 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))))
11684 /* If the value was set in a later insn than the ones we are processing,
11685 we can't use it even if the register was only set once. */
11686 if (reg_stat
[regno
].last_set_label
== label_tick
11687 && DF_INSN_LUID (reg_stat
[regno
].last_set
) >= subst_low_luid
)
11690 /* If the value has all its registers valid, return it. */
11691 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11692 reg_stat
[regno
].last_set_label
, 0))
11695 /* Otherwise, make a copy and replace any invalid register with
11696 (clobber (const_int 0)). If that fails for some reason, return 0. */
11698 value
= copy_rtx (value
);
11699 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11700 reg_stat
[regno
].last_set_label
, 1))
11706 /* Return nonzero if expression X refers to a REG or to memory
11707 that is set in an instruction more recent than FROM_LUID. */
11710 use_crosses_set_p (rtx x
, int from_luid
)
11714 enum rtx_code code
= GET_CODE (x
);
11718 unsigned int regno
= REGNO (x
);
11719 unsigned endreg
= END_REGNO (x
);
11721 #ifdef PUSH_ROUNDING
11722 /* Don't allow uses of the stack pointer to be moved,
11723 because we don't know whether the move crosses a push insn. */
11724 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11727 for (; regno
< endreg
; regno
++)
11728 if (reg_stat
[regno
].last_set
11729 && reg_stat
[regno
].last_set_label
== label_tick
11730 && DF_INSN_LUID (reg_stat
[regno
].last_set
) > from_luid
)
11735 if (code
== MEM
&& mem_last_set
> from_luid
)
11738 fmt
= GET_RTX_FORMAT (code
);
11740 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11745 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11746 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
11749 else if (fmt
[i
] == 'e'
11750 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
11756 /* Define three variables used for communication between the following
11759 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11760 static int reg_dead_flag
;
11762 /* Function called via note_stores from reg_dead_at_p.
11764 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11765 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11768 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11770 unsigned int regno
, endregno
;
11775 regno
= REGNO (dest
);
11776 endregno
= END_REGNO (dest
);
11777 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11778 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11781 /* Return nonzero if REG is known to be dead at INSN.
11783 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11784 referencing REG, it is dead. If we hit a SET referencing REG, it is
11785 live. Otherwise, see if it is live or dead at the start of the basic
11786 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11787 must be assumed to be always live. */
11790 reg_dead_at_p (rtx reg
, rtx insn
)
11795 /* Set variables for reg_dead_at_p_1. */
11796 reg_dead_regno
= REGNO (reg
);
11797 reg_dead_endregno
= END_REGNO (reg
);
11801 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11802 we allow the machine description to decide whether use-and-clobber
11803 patterns are OK. */
11804 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11806 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11807 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11811 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11812 beginning of function. */
11813 for (; insn
&& !LABEL_P (insn
) && !BARRIER_P (insn
);
11814 insn
= prev_nonnote_insn (insn
))
11816 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11818 return reg_dead_flag
== 1 ? 1 : 0;
11820 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11824 /* Get the basic block that we were in. */
11826 block
= ENTRY_BLOCK_PTR
->next_bb
;
11829 FOR_EACH_BB (block
)
11830 if (insn
== BB_HEAD (block
))
11833 if (block
== EXIT_BLOCK_PTR
)
11837 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11838 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
11844 /* Note hard registers in X that are used. */
11847 mark_used_regs_combine (rtx x
)
11849 RTX_CODE code
= GET_CODE (x
);
11850 unsigned int regno
;
11863 case ADDR_DIFF_VEC
:
11866 /* CC0 must die in the insn after it is set, so we don't need to take
11867 special note of it here. */
11873 /* If we are clobbering a MEM, mark any hard registers inside the
11874 address as used. */
11875 if (MEM_P (XEXP (x
, 0)))
11876 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11881 /* A hard reg in a wide mode may really be multiple registers.
11882 If so, mark all of them just like the first. */
11883 if (regno
< FIRST_PSEUDO_REGISTER
)
11885 /* None of this applies to the stack, frame or arg pointers. */
11886 if (regno
== STACK_POINTER_REGNUM
11887 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11888 || regno
== HARD_FRAME_POINTER_REGNUM
11890 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11891 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11893 || regno
== FRAME_POINTER_REGNUM
)
11896 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
11902 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11904 rtx testreg
= SET_DEST (x
);
11906 while (GET_CODE (testreg
) == SUBREG
11907 || GET_CODE (testreg
) == ZERO_EXTRACT
11908 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11909 testreg
= XEXP (testreg
, 0);
11911 if (MEM_P (testreg
))
11912 mark_used_regs_combine (XEXP (testreg
, 0));
11914 mark_used_regs_combine (SET_SRC (x
));
11922 /* Recursively scan the operands of this expression. */
11925 const char *fmt
= GET_RTX_FORMAT (code
);
11927 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11930 mark_used_regs_combine (XEXP (x
, i
));
11931 else if (fmt
[i
] == 'E')
11935 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11936 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11942 /* Remove register number REGNO from the dead registers list of INSN.
11944 Return the note used to record the death, if there was one. */
11947 remove_death (unsigned int regno
, rtx insn
)
11949 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11952 remove_note (insn
, note
);
11957 /* For each register (hardware or pseudo) used within expression X, if its
11958 death is in an instruction with luid between FROM_LUID (inclusive) and
11959 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11960 list headed by PNOTES.
11962 That said, don't move registers killed by maybe_kill_insn.
11964 This is done when X is being merged by combination into TO_INSN. These
11965 notes will then be distributed as needed. */
11968 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
11973 enum rtx_code code
= GET_CODE (x
);
11977 unsigned int regno
= REGNO (x
);
11978 rtx where_dead
= reg_stat
[regno
].last_death
;
11980 /* Don't move the register if it gets killed in between from and to. */
11981 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11982 && ! reg_referenced_p (x
, maybe_kill_insn
))
11986 && DF_INSN_LUID (where_dead
) >= from_luid
11987 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
11989 rtx note
= remove_death (regno
, where_dead
);
11991 /* It is possible for the call above to return 0. This can occur
11992 when last_death points to I2 or I1 that we combined with.
11993 In that case make a new note.
11995 We must also check for the case where X is a hard register
11996 and NOTE is a death note for a range of hard registers
11997 including X. In that case, we must put REG_DEAD notes for
11998 the remaining registers in place of NOTE. */
12000 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12001 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12002 > GET_MODE_SIZE (GET_MODE (x
))))
12004 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12005 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
12006 unsigned int ourend
= END_HARD_REGNO (x
);
12009 for (i
= deadregno
; i
< deadend
; i
++)
12010 if (i
< regno
|| i
>= ourend
)
12011 REG_NOTES (where_dead
)
12012 = gen_rtx_EXPR_LIST (REG_DEAD
,
12014 REG_NOTES (where_dead
));
12017 /* If we didn't find any note, or if we found a REG_DEAD note that
12018 covers only part of the given reg, and we have a multi-reg hard
12019 register, then to be safe we must check for REG_DEAD notes
12020 for each register other than the first. They could have
12021 their own REG_DEAD notes lying around. */
12022 else if ((note
== 0
12024 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12025 < GET_MODE_SIZE (GET_MODE (x
)))))
12026 && regno
< FIRST_PSEUDO_REGISTER
12027 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12029 unsigned int ourend
= END_HARD_REGNO (x
);
12030 unsigned int i
, offset
;
12034 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12038 for (i
= regno
+ offset
; i
< ourend
; i
++)
12039 move_deaths (regno_reg_rtx
[i
],
12040 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
12043 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12045 XEXP (note
, 1) = *pnotes
;
12049 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12055 else if (GET_CODE (x
) == SET
)
12057 rtx dest
= SET_DEST (x
);
12059 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12061 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12062 that accesses one word of a multi-word item, some
12063 piece of everything register in the expression is used by
12064 this insn, so remove any old death. */
12065 /* ??? So why do we test for equality of the sizes? */
12067 if (GET_CODE (dest
) == ZERO_EXTRACT
12068 || GET_CODE (dest
) == STRICT_LOW_PART
12069 || (GET_CODE (dest
) == SUBREG
12070 && (((GET_MODE_SIZE (GET_MODE (dest
))
12071 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12072 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12073 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12075 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12079 /* If this is some other SUBREG, we know it replaces the entire
12080 value, so use that as the destination. */
12081 if (GET_CODE (dest
) == SUBREG
)
12082 dest
= SUBREG_REG (dest
);
12084 /* If this is a MEM, adjust deaths of anything used in the address.
12085 For a REG (the only other possibility), the entire value is
12086 being replaced so the old value is not used in this insn. */
12089 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
12094 else if (GET_CODE (x
) == CLOBBER
)
12097 len
= GET_RTX_LENGTH (code
);
12098 fmt
= GET_RTX_FORMAT (code
);
12100 for (i
= 0; i
< len
; i
++)
12105 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12106 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
12109 else if (fmt
[i
] == 'e')
12110 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12114 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12115 pattern of an insn. X must be a REG. */
12118 reg_bitfield_target_p (rtx x
, rtx body
)
12122 if (GET_CODE (body
) == SET
)
12124 rtx dest
= SET_DEST (body
);
12126 unsigned int regno
, tregno
, endregno
, endtregno
;
12128 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12129 target
= XEXP (dest
, 0);
12130 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12131 target
= SUBREG_REG (XEXP (dest
, 0));
12135 if (GET_CODE (target
) == SUBREG
)
12136 target
= SUBREG_REG (target
);
12138 if (!REG_P (target
))
12141 tregno
= REGNO (target
), regno
= REGNO (x
);
12142 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12143 return target
== x
;
12145 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
12146 endregno
= end_hard_regno (GET_MODE (x
), regno
);
12148 return endregno
> tregno
&& regno
< endtregno
;
12151 else if (GET_CODE (body
) == PARALLEL
)
12152 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12153 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12159 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12160 as appropriate. I3 and I2 are the insns resulting from the combination
12161 insns including FROM (I2 may be zero).
12163 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12164 not need REG_DEAD notes because they are being substituted for. This
12165 saves searching in the most common cases.
12167 Each note in the list is either ignored or placed on some insns, depending
12168 on the type of note. */
12171 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
12174 rtx note
, next_note
;
12177 for (note
= notes
; note
; note
= next_note
)
12179 rtx place
= 0, place2
= 0;
12181 next_note
= XEXP (note
, 1);
12182 switch (REG_NOTE_KIND (note
))
12186 /* Doesn't matter much where we put this, as long as it's somewhere.
12187 It is preferable to keep these notes on branches, which is most
12188 likely to be i3. */
12192 case REG_VALUE_PROFILE
:
12193 /* Just get rid of this note, as it is unused later anyway. */
12196 case REG_NON_LOCAL_GOTO
:
12201 gcc_assert (i2
&& JUMP_P (i2
));
12206 case REG_EH_REGION
:
12207 /* These notes must remain with the call or trapping instruction. */
12210 else if (i2
&& CALL_P (i2
))
12214 gcc_assert (flag_non_call_exceptions
);
12215 if (may_trap_p (i3
))
12217 else if (i2
&& may_trap_p (i2
))
12219 /* ??? Otherwise assume we've combined things such that we
12220 can now prove that the instructions can't trap. Drop the
12221 note in this case. */
12227 /* These notes must remain with the call. It should not be
12228 possible for both I2 and I3 to be a call. */
12233 gcc_assert (i2
&& CALL_P (i2
));
12239 /* Any clobbers for i3 may still exist, and so we must process
12240 REG_UNUSED notes from that insn.
12242 Any clobbers from i2 or i1 can only exist if they were added by
12243 recog_for_combine. In that case, recog_for_combine created the
12244 necessary REG_UNUSED notes. Trying to keep any original
12245 REG_UNUSED notes from these insns can cause incorrect output
12246 if it is for the same register as the original i3 dest.
12247 In that case, we will notice that the register is set in i3,
12248 and then add a REG_UNUSED note for the destination of i3, which
12249 is wrong. However, it is possible to have REG_UNUSED notes from
12250 i2 or i1 for register which were both used and clobbered, so
12251 we keep notes from i2 or i1 if they will turn into REG_DEAD
12254 /* If this register is set or clobbered in I3, put the note there
12255 unless there is one already. */
12256 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12258 if (from_insn
!= i3
)
12261 if (! (REG_P (XEXP (note
, 0))
12262 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12263 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12266 /* Otherwise, if this register is used by I3, then this register
12267 now dies here, so we must put a REG_DEAD note here unless there
12269 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12270 && ! (REG_P (XEXP (note
, 0))
12271 ? find_regno_note (i3
, REG_DEAD
,
12272 REGNO (XEXP (note
, 0)))
12273 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12275 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12283 /* These notes say something about results of an insn. We can
12284 only support them if they used to be on I3 in which case they
12285 remain on I3. Otherwise they are ignored.
12287 If the note refers to an expression that is not a constant, we
12288 must also ignore the note since we cannot tell whether the
12289 equivalence is still true. It might be possible to do
12290 slightly better than this (we only have a problem if I2DEST
12291 or I1DEST is present in the expression), but it doesn't
12292 seem worth the trouble. */
12294 if (from_insn
== i3
12295 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12300 case REG_NO_CONFLICT
:
12301 /* These notes say something about how a register is used. They must
12302 be present on any use of the register in I2 or I3. */
12303 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12306 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12316 /* This can show up in several ways -- either directly in the
12317 pattern, or hidden off in the constant pool with (or without?)
12318 a REG_EQUAL note. */
12319 /* ??? Ignore the without-reg_equal-note problem for now. */
12320 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12321 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12322 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12323 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12327 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12328 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12329 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12330 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12338 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
12339 a JUMP_LABEL instead or decrement LABEL_NUSES. */
12340 if (place
&& JUMP_P (place
))
12342 rtx label
= JUMP_LABEL (place
);
12345 JUMP_LABEL (place
) = XEXP (note
, 0);
12348 gcc_assert (label
== XEXP (note
, 0));
12349 if (LABEL_P (label
))
12350 LABEL_NUSES (label
)--;
12354 if (place2
&& JUMP_P (place2
))
12356 rtx label
= JUMP_LABEL (place2
);
12359 JUMP_LABEL (place2
) = XEXP (note
, 0);
12362 gcc_assert (label
== XEXP (note
, 0));
12363 if (LABEL_P (label
))
12364 LABEL_NUSES (label
)--;
12371 /* This note says something about the value of a register prior
12372 to the execution of an insn. It is too much trouble to see
12373 if the note is still correct in all situations. It is better
12374 to simply delete it. */
12377 case REG_LIBCALL_ID
:
12378 /* If the insn previously containing this note still exists,
12379 put it back where it was. Otherwise move it to the previous
12381 if (!NOTE_P (from_insn
))
12384 place
= prev_real_insn (from_insn
);
12387 /* If the insn previously containing this note still exists,
12388 put it back where it was. Otherwise move it to the previous
12389 insn. Adjust the corresponding REG_LIBCALL note. */
12390 if (!NOTE_P (from_insn
))
12394 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12395 place
= prev_real_insn (from_insn
);
12397 XEXP (tem
, 0) = place
;
12398 /* If we're deleting the last remaining instruction of a
12399 libcall sequence, don't add the notes. */
12400 else if (XEXP (note
, 0) == from_insn
)
12402 /* Don't add the dangling REG_RETVAL note. */
12409 /* This is handled similarly to REG_RETVAL. */
12410 if (!NOTE_P (from_insn
))
12414 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12415 place
= next_real_insn (from_insn
);
12417 XEXP (tem
, 0) = place
;
12418 /* If we're deleting the last remaining instruction of a
12419 libcall sequence, don't add the notes. */
12420 else if (XEXP (note
, 0) == from_insn
)
12422 /* Don't add the dangling REG_LIBCALL note. */
12429 /* If we replaced the right hand side of FROM_INSN with a
12430 REG_EQUAL note, the original use of the dying register
12431 will not have been combined into I3 and I2. In such cases,
12432 FROM_INSN is guaranteed to be the first of the combined
12433 instructions, so we simply need to search back before
12434 FROM_INSN for the previous use or set of this register,
12435 then alter the notes there appropriately.
12437 If the register is used as an input in I3, it dies there.
12438 Similarly for I2, if it is nonzero and adjacent to I3.
12440 If the register is not used as an input in either I3 or I2
12441 and it is not one of the registers we were supposed to eliminate,
12442 there are two possibilities. We might have a non-adjacent I2
12443 or we might have somehow eliminated an additional register
12444 from a computation. For example, we might have had A & B where
12445 we discover that B will always be zero. In this case we will
12446 eliminate the reference to A.
12448 In both cases, we must search to see if we can find a previous
12449 use of A and put the death note there. */
12452 && from_insn
== i2mod
12453 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
12458 && CALL_P (from_insn
)
12459 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12461 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12463 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12464 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12466 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
12468 && reg_overlap_mentioned_p (XEXP (note
, 0),
12470 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12477 basic_block bb
= this_basic_block
;
12479 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
12481 if (! INSN_P (tem
))
12483 if (tem
== BB_HEAD (bb
))
12488 /* If the register is being set at TEM, see if that is all
12489 TEM is doing. If so, delete TEM. Otherwise, make this
12490 into a REG_UNUSED note instead. Don't delete sets to
12491 global register vars. */
12492 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
12493 || !global_regs
[REGNO (XEXP (note
, 0))])
12494 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12496 rtx set
= single_set (tem
);
12497 rtx inner_dest
= 0;
12499 rtx cc0_setter
= NULL_RTX
;
12503 for (inner_dest
= SET_DEST (set
);
12504 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12505 || GET_CODE (inner_dest
) == SUBREG
12506 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12507 inner_dest
= XEXP (inner_dest
, 0))
12510 /* Verify that it was the set, and not a clobber that
12511 modified the register.
12513 CC0 targets must be careful to maintain setter/user
12514 pairs. If we cannot delete the setter due to side
12515 effects, mark the user with an UNUSED note instead
12518 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12519 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12521 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12522 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12523 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12527 /* Move the notes and links of TEM elsewhere.
12528 This might delete other dead insns recursively.
12529 First set the pattern to something that won't use
12531 rtx old_notes
= REG_NOTES (tem
);
12533 PATTERN (tem
) = pc_rtx
;
12534 REG_NOTES (tem
) = NULL
;
12536 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
12537 NULL_RTX
, NULL_RTX
);
12538 distribute_links (LOG_LINKS (tem
));
12540 SET_INSN_DELETED (tem
);
12543 /* Delete the setter too. */
12546 PATTERN (cc0_setter
) = pc_rtx
;
12547 old_notes
= REG_NOTES (cc0_setter
);
12548 REG_NOTES (cc0_setter
) = NULL
;
12550 distribute_notes (old_notes
, cc0_setter
,
12551 cc0_setter
, NULL_RTX
,
12552 NULL_RTX
, NULL_RTX
);
12553 distribute_links (LOG_LINKS (cc0_setter
));
12555 SET_INSN_DELETED (cc0_setter
);
12561 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12563 /* If there isn't already a REG_UNUSED note, put one
12564 here. Do not place a REG_DEAD note, even if
12565 the register is also used here; that would not
12566 match the algorithm used in lifetime analysis
12567 and can cause the consistency check in the
12568 scheduler to fail. */
12569 if (! find_regno_note (tem
, REG_UNUSED
,
12570 REGNO (XEXP (note
, 0))))
12575 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12577 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12581 /* If we are doing a 3->2 combination, and we have a
12582 register which formerly died in i3 and was not used
12583 by i2, which now no longer dies in i3 and is used in
12584 i2 but does not die in i2, and place is between i2
12585 and i3, then we may need to move a link from place to
12587 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
12589 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
12590 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12592 rtx links
= LOG_LINKS (place
);
12593 LOG_LINKS (place
) = 0;
12594 distribute_links (links
);
12599 if (tem
== BB_HEAD (bb
))
12605 /* If the register is set or already dead at PLACE, we needn't do
12606 anything with this note if it is still a REG_DEAD note.
12607 We check here if it is set at all, not if is it totally replaced,
12608 which is what `dead_or_set_p' checks, so also check for it being
12611 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12613 unsigned int regno
= REGNO (XEXP (note
, 0));
12616 if (dead_or_set_p (place
, XEXP (note
, 0))
12617 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12619 /* Unless the register previously died in PLACE, clear
12620 last_death. [I no longer understand why this is
12622 if (reg_stat
[regno
].last_death
!= place
)
12623 reg_stat
[regno
].last_death
= 0;
12627 reg_stat
[regno
].last_death
= place
;
12629 /* If this is a death note for a hard reg that is occupying
12630 multiple registers, ensure that we are still using all
12631 parts of the object. If we find a piece of the object
12632 that is unused, we must arrange for an appropriate REG_DEAD
12633 note to be added for it. However, we can't just emit a USE
12634 and tag the note to it, since the register might actually
12635 be dead; so we recourse, and the recursive call then finds
12636 the previous insn that used this register. */
12638 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12639 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12641 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
12645 for (i
= regno
; i
< endregno
; i
++)
12646 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12647 && ! find_regno_fusage (place
, USE
, i
))
12648 || dead_or_set_regno_p (place
, i
))
12653 /* Put only REG_DEAD notes for pieces that are
12654 not already dead or set. */
12656 for (i
= regno
; i
< endregno
;
12657 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12659 rtx piece
= regno_reg_rtx
[i
];
12660 basic_block bb
= this_basic_block
;
12662 if (! dead_or_set_p (place
, piece
)
12663 && ! reg_bitfield_target_p (piece
,
12667 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12669 distribute_notes (new_note
, place
, place
,
12670 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12672 else if (! refers_to_regno_p (i
, i
+ 1,
12673 PATTERN (place
), 0)
12674 && ! find_regno_fusage (place
, USE
, i
))
12675 for (tem
= PREV_INSN (place
); ;
12676 tem
= PREV_INSN (tem
))
12678 if (! INSN_P (tem
))
12680 if (tem
== BB_HEAD (bb
))
12684 if (dead_or_set_p (tem
, piece
)
12685 || reg_bitfield_target_p (piece
,
12689 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12704 /* Any other notes should not be present at this point in the
12706 gcc_unreachable ();
12711 XEXP (note
, 1) = REG_NOTES (place
);
12712 REG_NOTES (place
) = note
;
12717 = gen_rtx_fmt_ee (GET_CODE (note
), REG_NOTE_KIND (note
),
12718 XEXP (note
, 0), REG_NOTES (place2
));
12722 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12723 I3, I2, and I1 to new locations. This is also called to add a link
12724 pointing at I3 when I3's destination is changed. */
12727 distribute_links (rtx links
)
12729 rtx link
, next_link
;
12731 for (link
= links
; link
; link
= next_link
)
12737 next_link
= XEXP (link
, 1);
12739 /* If the insn that this link points to is a NOTE or isn't a single
12740 set, ignore it. In the latter case, it isn't clear what we
12741 can do other than ignore the link, since we can't tell which
12742 register it was for. Such links wouldn't be used by combine
12745 It is not possible for the destination of the target of the link to
12746 have been changed by combine. The only potential of this is if we
12747 replace I3, I2, and I1 by I3 and I2. But in that case the
12748 destination of I2 also remains unchanged. */
12750 if (NOTE_P (XEXP (link
, 0))
12751 || (set
= single_set (XEXP (link
, 0))) == 0)
12754 reg
= SET_DEST (set
);
12755 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12756 || GET_CODE (reg
) == STRICT_LOW_PART
)
12757 reg
= XEXP (reg
, 0);
12759 /* A LOG_LINK is defined as being placed on the first insn that uses
12760 a register and points to the insn that sets the register. Start
12761 searching at the next insn after the target of the link and stop
12762 when we reach a set of the register or the end of the basic block.
12764 Note that this correctly handles the link that used to point from
12765 I3 to I2. Also note that not much searching is typically done here
12766 since most links don't point very far away. */
12768 for (insn
= NEXT_INSN (XEXP (link
, 0));
12769 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12770 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12771 insn
= NEXT_INSN (insn
))
12772 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12774 if (reg_referenced_p (reg
, PATTERN (insn
)))
12778 else if (CALL_P (insn
)
12779 && find_reg_fusage (insn
, USE
, reg
))
12784 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12787 /* If we found a place to put the link, place it there unless there
12788 is already a link to the same insn as LINK at that point. */
12794 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12795 if (XEXP (link2
, 0) == XEXP (link
, 0))
12800 XEXP (link
, 1) = LOG_LINKS (place
);
12801 LOG_LINKS (place
) = link
;
12803 /* Set added_links_insn to the earliest insn we added a
12805 if (added_links_insn
== 0
12806 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
12807 added_links_insn
= place
;
12813 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12814 Check whether the expression pointer to by LOC is a register or
12815 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12816 Otherwise return zero. */
12819 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
12824 && (REG_P (x
) || MEM_P (x
))
12825 && ! reg_mentioned_p (x
, (rtx
) expr
))
12830 /* Check for any register or memory mentioned in EQUIV that is not
12831 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12832 of EXPR where some registers may have been replaced by constants. */
12835 unmentioned_reg_p (rtx equiv
, rtx expr
)
12837 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
12841 dump_combine_stats (FILE *file
)
12845 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12846 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12850 dump_combine_total_stats (FILE *file
)
12854 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12855 total_attempts
, total_merges
, total_extras
, total_successes
);
12859 gate_handle_combine (void)
12861 return (optimize
> 0);
12864 /* Try combining insns through substitution. */
12865 static unsigned int
12866 rest_of_handle_combine (void)
12868 int rebuild_jump_labels_after_combine
;
12870 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
12871 df_note_add_problem ();
12874 regstat_init_n_sets_and_refs ();
12876 rebuild_jump_labels_after_combine
12877 = combine_instructions (get_insns (), max_reg_num ());
12879 /* Combining insns may have turned an indirect jump into a
12880 direct jump. Rebuild the JUMP_LABEL fields of jumping
12882 if (rebuild_jump_labels_after_combine
)
12884 timevar_push (TV_JUMP
);
12885 rebuild_jump_labels (get_insns ());
12887 timevar_pop (TV_JUMP
);
12890 regstat_free_n_sets_and_refs ();
12894 struct tree_opt_pass pass_combine
=
12896 "combine", /* name */
12897 gate_handle_combine
, /* gate */
12898 rest_of_handle_combine
, /* execute */
12901 0, /* static_pass_number */
12902 TV_COMBINE
, /* tv_id */
12903 0, /* properties_required */
12904 0, /* properties_provided */
12905 0, /* properties_destroyed */
12906 0, /* todo_flags_start */
12909 TODO_ggc_collect
, /* todo_flags_finish */