2 /* { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } */
3 /* { dg-options "-Os -fno-asynchronous-unwind-tables -g -fsel-sched-pipelining -fselective-scheduling2" } */
6 extern void bar (int, int, int, int, int, int, int);
9 synth (int *values
, int n_values
, int ci
, int s1
, int v
, int s2
)
14 int co
= ci
? r1
: baz () < r1
;
15 bar (0, n_values
, s1
, s2
, v
, co
, 0);