1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This module is essentially the "combiner" phase of the U. of Arizona
22 Portable Optimizer, but redone to work on our list-structured
23 representation for RTL instead of their string representation.
25 The LOG_LINKS of each insn identify the most recent assignment
26 to each REG used in the insn. It is a list of previous insns,
27 each of which contains a SET for a REG that is used in this insn
28 and not used or set in between. LOG_LINKs never cross basic blocks.
29 They were set up by the preceding pass (lifetime analysis).
31 We try to combine each pair of insns joined by a logical link.
32 We also try to combine triples of insns A, B and C when
33 C has a link back to B and B has a link back to A.
35 LOG_LINKS does not have links for use of the CC0. They don't
36 need to, because the insn that sets the CC0 is always immediately
37 before the insn that tests it. So we always regard a branch
38 insn as having a logical link to the preceding insn. The same is true
39 for an insn explicitly using CC0.
41 We check (with use_crosses_set_p) to avoid combining in such a way
42 as to move a computation to a place where its value would be different.
44 Combination is done by mathematically substituting the previous
45 insn(s) values for the regs they set into the expressions in
46 the later insns that refer to these regs. If the result is a valid insn
47 for our target machine, according to the machine description,
48 we install it, delete the earlier insns, and update the data flow
49 information (LOG_LINKS and REG_NOTES) for what we did.
51 There are a few exceptions where the dataflow information created by
52 flow.c aren't completely updated:
54 - reg_live_length is not updated
55 - reg_n_refs is not adjusted in the rare case when a register is
56 no longer required in a computation
57 - there are extremely rare cases (see distribute_regnotes) when a
59 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60 removed because there is no way to know which register it was
63 To simplify substitution, we combine only when the earlier insn(s)
64 consist of only a single assignment. To simplify updating afterward,
65 we never combine when a subroutine call appears in the middle.
67 Since we do not represent assignments to CC0 explicitly except when that
68 is all an insn does, there is no LOG_LINKS entry in an insn that uses
69 the condition code for the insn that set the condition code.
70 Fortunately, these two insns must be consecutive.
71 Therefore, every JUMP_INSN is taken to have an implicit logical link
72 to the preceding insn. This is not quite right, since non-jumps can
73 also use the condition code; but in practice such insns would not
83 /* Must precede rtl.h for FFS. */
89 #include "hard-reg-set.h"
91 #include "basic-block.h"
92 #include "insn-config.h"
93 #include "insn-flags.h"
94 #include "insn-codes.h"
95 #include "insn-attr.h"
99 /* It is not safe to use ordinary gen_lowpart in combine.
100 Use gen_lowpart_for_combine instead. See comments there. */
101 #define gen_lowpart dont_use_gen_lowpart_you_dummy
103 /* Number of attempts to combine instructions in this function. */
105 static int combine_attempts
;
107 /* Number of attempts that got as far as substitution in this function. */
109 static int combine_merges
;
111 /* Number of instructions combined with added SETs in this function. */
113 static int combine_extras
;
115 /* Number of instructions combined in this function. */
117 static int combine_successes
;
119 /* Totals over entire compilation. */
121 static int total_attempts
, total_merges
, total_extras
, total_successes
;
123 /* Define a defulat value for REVERSIBLE_CC_MODE.
124 We can never assume that a condition code mode is safe to reverse unless
125 the md tells us so. */
126 #ifndef REVERSIBLE_CC_MODE
127 #define REVERSIBLE_CC_MODE(MODE) 0
130 /* Vector mapping INSN_UIDs to cuids.
131 The cuids are like uids but increase monotonically always.
132 Combine always uses cuids so that it can compare them.
133 But actually renumbering the uids, which we used to do,
134 proves to be a bad idea because it makes it hard to compare
135 the dumps produced by earlier passes with those from later passes. */
137 static int *uid_cuid
;
139 /* Get the cuid of an insn. */
141 #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
143 /* Maximum register number, which is the size of the tables below. */
145 static int combine_max_regno
;
147 /* Record last point of death of (hard or pseudo) register n. */
149 static rtx
*reg_last_death
;
151 /* Record last point of modification of (hard or pseudo) register n. */
153 static rtx
*reg_last_set
;
155 /* Record the cuid of the last insn that invalidated memory
156 (anything that writes memory, and subroutine calls, but not pushes). */
158 static int mem_last_set
;
160 /* Record the cuid of the last CALL_INSN
161 so we can tell whether a potential combination crosses any calls. */
163 static int last_call_cuid
;
165 /* When `subst' is called, this is the insn that is being modified
166 (by combining in a previous insn). The PATTERN of this insn
167 is still the old pattern partially modified and it should not be
168 looked at, but this may be used to examine the successors of the insn
169 to judge whether a simplification is valid. */
171 static rtx subst_insn
;
173 /* This is the lowest CUID that `subst' is currently dealing with.
174 get_last_value will not return a value if the register was set at or
175 after this CUID. If not for this mechanism, we could get confused if
176 I2 or I1 in try_combine were an insn that used the old value of a register
177 to obtain a new value. In that case, we might erroneously get the
178 new value of the register when we wanted the old one. */
180 static int subst_low_cuid
;
182 /* This contains any hard registers that are used in newpat; reg_dead_at_p
183 must consider all these registers to be always live. */
185 static HARD_REG_SET newpat_used_regs
;
187 /* This is an insn to which a LOG_LINKS entry has been added. If this
188 insn is the earlier than I2 or I3, combine should rescan starting at
191 static rtx added_links_insn
;
193 /* This is the value of undobuf.num_undo when we started processing this
194 substitution. This will prevent gen_rtx_combine from re-used a piece
195 from the previous expression. Doing so can produce circular rtl
198 static int previous_num_undos
;
200 /* Basic block number of the block in which we are performing combines. */
201 static int this_basic_block
;
203 /* The next group of arrays allows the recording of the last value assigned
204 to (hard or pseudo) register n. We use this information to see if a
205 operation being processed is redundant given a prior operation performed
206 on the register. For example, an `and' with a constant is redundant if
207 all the zero bits are already known to be turned off.
209 We use an approach similar to that used by cse, but change it in the
212 (1) We do not want to reinitialize at each label.
213 (2) It is useful, but not critical, to know the actual value assigned
214 to a register. Often just its form is helpful.
216 Therefore, we maintain the following arrays:
218 reg_last_set_value the last value assigned
219 reg_last_set_label records the value of label_tick when the
220 register was assigned
221 reg_last_set_table_tick records the value of label_tick when a
222 value using the register is assigned
223 reg_last_set_invalid set to non-zero when it is not valid
224 to use the value of this register in some
227 To understand the usage of these tables, it is important to understand
228 the distinction between the value in reg_last_set_value being valid
229 and the register being validly contained in some other expression in the
232 Entry I in reg_last_set_value is valid if it is non-zero, and either
233 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
235 Register I may validly appear in any expression returned for the value
236 of another register if reg_n_sets[i] is 1. It may also appear in the
237 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
238 reg_last_set_invalid[j] is zero.
240 If an expression is found in the table containing a register which may
241 not validly appear in an expression, the register is replaced by
242 something that won't match, (clobber (const_int 0)).
244 reg_last_set_invalid[i] is set non-zero when register I is being assigned
245 to and reg_last_set_table_tick[i] == label_tick. */
247 /* Record last value assigned to (hard or pseudo) register n. */
249 static rtx
*reg_last_set_value
;
251 /* Record the value of label_tick when the value for register n is placed in
252 reg_last_set_value[n]. */
254 static int *reg_last_set_label
;
256 /* Record the value of label_tick when an expression involving register n
257 is placed in reg_last_set_value. */
259 static int *reg_last_set_table_tick
;
261 /* Set non-zero if references to register n in expressions should not be
264 static char *reg_last_set_invalid
;
266 /* Incremented for each label. */
268 static int label_tick
;
270 /* Some registers that are set more than once and used in more than one
271 basic block are nevertheless always set in similar ways. For example,
272 a QImode register may be loaded from memory in two places on a machine
273 where byte loads zero extend.
275 We record in the following array what we know about the nonzero
276 bits of a register, specifically which bits are known to be zero.
278 If an entry is zero, it means that we don't know anything special. */
280 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
282 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
283 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
285 static enum machine_mode nonzero_bits_mode
;
287 /* Nonzero if we know that a register has some leading bits that are always
288 equal to the sign bit. */
290 static char *reg_sign_bit_copies
;
292 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
293 It is zero while computing them and after combine has completed. This
294 former test prevents propagating values based on previously set values,
295 which can be incorrect if a variable is modified in a loop. */
297 static int nonzero_sign_valid
;
299 /* These arrays are maintained in parallel with reg_last_set_value
300 and are used to store the mode in which the register was last set,
301 the bits that were known to be zero when it was last set, and the
302 number of sign bits copies it was known to have when it was last set. */
304 static enum machine_mode
*reg_last_set_mode
;
305 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
306 static char *reg_last_set_sign_bit_copies
;
308 /* Record one modification to rtl structure
309 to be undone by storing old_contents into *where.
310 is_int is 1 if the contents are an int. */
315 union {rtx r
; int i
;} old_contents
;
316 union {rtx
*r
; int *i
;} where
;
319 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
320 num_undo says how many are currently recorded.
322 storage is nonzero if we must undo the allocation of new storage.
323 The value of storage is what to pass to obfree.
325 other_insn is nonzero if we have modified some other insn in the process
326 of working on subst_insn. It must be verified too. */
334 struct undo undo
[MAX_UNDO
];
338 static struct undobuf undobuf
;
340 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
341 insn. The substitution can be undone by undo_all. If INTO is already
342 set to NEWVAL, do not record this change. Because computing NEWVAL might
343 also call SUBST, we have to compute it before we put anything into
346 #define SUBST(INTO, NEWVAL) \
347 do { rtx _new = (NEWVAL); \
348 if (undobuf.num_undo < MAX_UNDO) \
350 undobuf.undo[undobuf.num_undo].is_int = 0; \
351 undobuf.undo[undobuf.num_undo].where.r = &INTO; \
352 undobuf.undo[undobuf.num_undo].old_contents.r = INTO; \
354 if (undobuf.undo[undobuf.num_undo].old_contents.r != INTO) \
355 undobuf.num_undo++; \
359 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
361 Note that substitution for the value of a CONST_INT is not safe. */
363 #define SUBST_INT(INTO, NEWVAL) \
364 do { if (undobuf.num_undo < MAX_UNDO) \
366 undobuf.undo[undobuf.num_undo].is_int = 1; \
367 undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \
368 undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \
370 if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \
371 undobuf.num_undo++; \
375 /* Number of times the pseudo being substituted for
376 was found and replaced. */
378 static int n_occurrences
;
380 static void init_reg_last_arrays
PROTO(());
381 static void setup_incoming_promotions
PROTO(());
382 static void set_nonzero_bits_and_sign_copies
PROTO((rtx
, rtx
));
383 static int can_combine_p
PROTO((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
384 static int combinable_i3pat
PROTO((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
385 static rtx try_combine
PROTO((rtx
, rtx
, rtx
));
386 static void undo_all
PROTO((void));
387 static rtx
*find_split_point
PROTO((rtx
*, rtx
));
388 static rtx subst
PROTO((rtx
, rtx
, rtx
, int, int));
389 static rtx simplify_rtx
PROTO((rtx
, enum machine_mode
, int, int));
390 static rtx simplify_if_then_else
PROTO((rtx
));
391 static rtx simplify_set
PROTO((rtx
));
392 static rtx simplify_logical
PROTO((rtx
, int));
393 static rtx expand_compound_operation
PROTO((rtx
));
394 static rtx expand_field_assignment
PROTO((rtx
));
395 static rtx make_extraction
PROTO((enum machine_mode
, rtx
, int, rtx
, int,
397 static rtx extract_left_shift
PROTO((rtx
, int));
398 static rtx make_compound_operation
PROTO((rtx
, enum rtx_code
));
399 static int get_pos_from_mask
PROTO((unsigned HOST_WIDE_INT
, int *));
400 static rtx force_to_mode
PROTO((rtx
, enum machine_mode
,
401 unsigned HOST_WIDE_INT
, rtx
, int));
402 static rtx if_then_else_cond
PROTO((rtx
, rtx
*, rtx
*));
403 static rtx known_cond
PROTO((rtx
, enum rtx_code
, rtx
, rtx
));
404 static rtx make_field_assignment
PROTO((rtx
));
405 static rtx apply_distributive_law
PROTO((rtx
));
406 static rtx simplify_and_const_int
PROTO((rtx
, enum machine_mode
, rtx
,
407 unsigned HOST_WIDE_INT
));
408 static unsigned HOST_WIDE_INT nonzero_bits
PROTO((rtx
, enum machine_mode
));
409 static int num_sign_bit_copies
PROTO((rtx
, enum machine_mode
));
410 static int merge_outer_ops
PROTO((enum rtx_code
*, HOST_WIDE_INT
*,
411 enum rtx_code
, HOST_WIDE_INT
,
412 enum machine_mode
, int *));
413 static rtx simplify_shift_const
PROTO((rtx
, enum rtx_code
, enum machine_mode
,
415 static int recog_for_combine
PROTO((rtx
*, rtx
, rtx
*));
416 static rtx gen_lowpart_for_combine
PROTO((enum machine_mode
, rtx
));
417 static rtx gen_rtx_combine
PVPROTO((enum rtx_code code
, enum machine_mode mode
,
419 static rtx gen_binary
PROTO((enum rtx_code
, enum machine_mode
,
421 static rtx gen_unary
PROTO((enum rtx_code
, enum machine_mode
,
422 enum machine_mode
, rtx
));
423 static enum rtx_code simplify_comparison
PROTO((enum rtx_code
, rtx
*, rtx
*));
424 static int reversible_comparison_p
PROTO((rtx
));
425 static void update_table_tick
PROTO((rtx
));
426 static void record_value_for_reg
PROTO((rtx
, rtx
, rtx
));
427 static void record_dead_and_set_regs_1
PROTO((rtx
, rtx
));
428 static void record_dead_and_set_regs
PROTO((rtx
));
429 static int get_last_value_validate
PROTO((rtx
*, int, int));
430 static rtx get_last_value
PROTO((rtx
));
431 static int use_crosses_set_p
PROTO((rtx
, int));
432 static void reg_dead_at_p_1
PROTO((rtx
, rtx
));
433 static int reg_dead_at_p
PROTO((rtx
, rtx
));
434 static void move_deaths
PROTO((rtx
, int, rtx
, rtx
*));
435 static int reg_bitfield_target_p
PROTO((rtx
, rtx
));
436 static void distribute_notes
PROTO((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
437 static void distribute_links
PROTO((rtx
));
438 static void mark_used_regs_combine
PROTO((rtx
));
440 /* Main entry point for combiner. F is the first insn of the function.
441 NREGS is the first unused pseudo-reg number. */
444 combine_instructions (f
, nregs
)
448 register rtx insn
, next
, prev
;
450 register rtx links
, nextlinks
;
452 combine_attempts
= 0;
455 combine_successes
= 0;
456 undobuf
.num_undo
= previous_num_undos
= 0;
458 combine_max_regno
= nregs
;
461 = (unsigned HOST_WIDE_INT
*) alloca (nregs
* sizeof (HOST_WIDE_INT
));
462 reg_sign_bit_copies
= (char *) alloca (nregs
* sizeof (char));
464 bzero ((char *) reg_nonzero_bits
, nregs
* sizeof (HOST_WIDE_INT
));
465 bzero (reg_sign_bit_copies
, nregs
* sizeof (char));
467 reg_last_death
= (rtx
*) alloca (nregs
* sizeof (rtx
));
468 reg_last_set
= (rtx
*) alloca (nregs
* sizeof (rtx
));
469 reg_last_set_value
= (rtx
*) alloca (nregs
* sizeof (rtx
));
470 reg_last_set_table_tick
= (int *) alloca (nregs
* sizeof (int));
471 reg_last_set_label
= (int *) alloca (nregs
* sizeof (int));
472 reg_last_set_invalid
= (char *) alloca (nregs
* sizeof (char));
474 = (enum machine_mode
*) alloca (nregs
* sizeof (enum machine_mode
));
475 reg_last_set_nonzero_bits
476 = (unsigned HOST_WIDE_INT
*) alloca (nregs
* sizeof (HOST_WIDE_INT
));
477 reg_last_set_sign_bit_copies
478 = (char *) alloca (nregs
* sizeof (char));
480 init_reg_last_arrays ();
482 init_recog_no_volatile ();
484 /* Compute maximum uid value so uid_cuid can be allocated. */
486 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
487 if (INSN_UID (insn
) > i
)
490 uid_cuid
= (int *) alloca ((i
+ 1) * sizeof (int));
492 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
494 /* Don't use reg_nonzero_bits when computing it. This can cause problems
495 when, for example, we have j <<= 1 in a loop. */
497 nonzero_sign_valid
= 0;
499 /* Compute the mapping from uids to cuids.
500 Cuids are numbers assigned to insns, like uids,
501 except that cuids increase monotonically through the code.
503 Scan all SETs and see if we can deduce anything about what
504 bits are known to be zero for some registers and how many copies
505 of the sign bit are known to exist for those registers.
507 Also set any known values so that we can use it while searching
508 for what bits are known to be set. */
512 setup_incoming_promotions ();
514 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
516 INSN_CUID (insn
) = ++i
;
520 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
522 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
);
523 record_dead_and_set_regs (insn
);
526 if (GET_CODE (insn
) == CODE_LABEL
)
530 nonzero_sign_valid
= 1;
532 /* Now scan all the insns in forward order. */
534 this_basic_block
= -1;
538 init_reg_last_arrays ();
539 setup_incoming_promotions ();
541 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
545 /* If INSN starts a new basic block, update our basic block number. */
546 if (this_basic_block
+ 1 < n_basic_blocks
547 && basic_block_head
[this_basic_block
+ 1] == insn
)
550 if (GET_CODE (insn
) == CODE_LABEL
)
553 else if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
555 /* Try this insn with each insn it links back to. */
557 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
558 if ((next
= try_combine (insn
, XEXP (links
, 0), NULL_RTX
)) != 0)
561 /* Try each sequence of three linked insns ending with this one. */
563 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
564 for (nextlinks
= LOG_LINKS (XEXP (links
, 0)); nextlinks
;
565 nextlinks
= XEXP (nextlinks
, 1))
566 if ((next
= try_combine (insn
, XEXP (links
, 0),
567 XEXP (nextlinks
, 0))) != 0)
571 /* Try to combine a jump insn that uses CC0
572 with a preceding insn that sets CC0, and maybe with its
573 logical predecessor as well.
574 This is how we make decrement-and-branch insns.
575 We need this special code because data flow connections
576 via CC0 do not get entered in LOG_LINKS. */
578 if (GET_CODE (insn
) == JUMP_INSN
579 && (prev
= prev_nonnote_insn (insn
)) != 0
580 && GET_CODE (prev
) == INSN
581 && sets_cc0_p (PATTERN (prev
)))
583 if ((next
= try_combine (insn
, prev
, NULL_RTX
)) != 0)
586 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
587 nextlinks
= XEXP (nextlinks
, 1))
588 if ((next
= try_combine (insn
, prev
,
589 XEXP (nextlinks
, 0))) != 0)
593 /* Do the same for an insn that explicitly references CC0. */
594 if (GET_CODE (insn
) == INSN
595 && (prev
= prev_nonnote_insn (insn
)) != 0
596 && GET_CODE (prev
) == INSN
597 && sets_cc0_p (PATTERN (prev
))
598 && GET_CODE (PATTERN (insn
)) == SET
599 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
601 if ((next
= try_combine (insn
, prev
, NULL_RTX
)) != 0)
604 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
605 nextlinks
= XEXP (nextlinks
, 1))
606 if ((next
= try_combine (insn
, prev
,
607 XEXP (nextlinks
, 0))) != 0)
611 /* Finally, see if any of the insns that this insn links to
612 explicitly references CC0. If so, try this insn, that insn,
613 and its predecessor if it sets CC0. */
614 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
615 if (GET_CODE (XEXP (links
, 0)) == INSN
616 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
617 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
618 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
619 && GET_CODE (prev
) == INSN
620 && sets_cc0_p (PATTERN (prev
))
621 && (next
= try_combine (insn
, XEXP (links
, 0), prev
)) != 0)
625 /* Try combining an insn with two different insns whose results it
627 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
628 for (nextlinks
= XEXP (links
, 1); nextlinks
;
629 nextlinks
= XEXP (nextlinks
, 1))
630 if ((next
= try_combine (insn
, XEXP (links
, 0),
631 XEXP (nextlinks
, 0))) != 0)
634 if (GET_CODE (insn
) != NOTE
)
635 record_dead_and_set_regs (insn
);
642 total_attempts
+= combine_attempts
;
643 total_merges
+= combine_merges
;
644 total_extras
+= combine_extras
;
645 total_successes
+= combine_successes
;
647 nonzero_sign_valid
= 0;
650 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
653 init_reg_last_arrays ()
655 int nregs
= combine_max_regno
;
657 bzero ((char *) reg_last_death
, nregs
* sizeof (rtx
));
658 bzero ((char *) reg_last_set
, nregs
* sizeof (rtx
));
659 bzero ((char *) reg_last_set_value
, nregs
* sizeof (rtx
));
660 bzero ((char *) reg_last_set_table_tick
, nregs
* sizeof (int));
661 bzero ((char *) reg_last_set_label
, nregs
* sizeof (int));
662 bzero (reg_last_set_invalid
, nregs
* sizeof (char));
663 bzero ((char *) reg_last_set_mode
, nregs
* sizeof (enum machine_mode
));
664 bzero ((char *) reg_last_set_nonzero_bits
, nregs
* sizeof (HOST_WIDE_INT
));
665 bzero (reg_last_set_sign_bit_copies
, nregs
* sizeof (char));
668 /* Set up any promoted values for incoming argument registers. */
671 setup_incoming_promotions ()
673 #ifdef PROMOTE_FUNCTION_ARGS
676 enum machine_mode mode
;
678 rtx first
= get_insns ();
680 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
681 if (FUNCTION_ARG_REGNO_P (regno
)
682 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
683 record_value_for_reg (reg
, first
,
684 gen_rtx (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
686 gen_rtx (CLOBBER
, mode
, const0_rtx
)));
690 /* Called via note_stores. If X is a pseudo that is used in more than
691 one basic block, is narrower that HOST_BITS_PER_WIDE_INT, and is being
692 set, record what bits are known zero. If we are clobbering X,
693 ignore this "set" because the clobbered value won't be used.
695 If we are setting only a portion of X and we can't figure out what
696 portion, assume all bits will be used since we don't know what will
699 Similarly, set how many bits of X are known to be copies of the sign bit
700 at all locations in the function. This is the smallest number implied
704 set_nonzero_bits_and_sign_copies (x
, set
)
710 if (GET_CODE (x
) == REG
711 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
712 && reg_n_sets
[REGNO (x
)] > 1
713 && reg_basic_block
[REGNO (x
)] < 0
714 /* If this register is undefined at the start of the file, we can't
715 say what its contents were. */
716 && ! (basic_block_live_at_start
[0][REGNO (x
) / REGSET_ELT_BITS
]
717 & ((REGSET_ELT_TYPE
) 1 << (REGNO (x
) % REGSET_ELT_BITS
)))
718 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
720 if (GET_CODE (set
) == CLOBBER
)
722 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
723 reg_sign_bit_copies
[REGNO (x
)] = 0;
727 /* If this is a complex assignment, see if we can convert it into a
728 simple assignment. */
729 set
= expand_field_assignment (set
);
731 /* If this is a simple assignment, or we have a paradoxical SUBREG,
732 set what we know about X. */
734 if (SET_DEST (set
) == x
735 || (GET_CODE (SET_DEST (set
)) == SUBREG
736 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
737 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
738 && SUBREG_REG (SET_DEST (set
)) == x
))
740 rtx src
= SET_SRC (set
);
742 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
743 /* If X is narrower than a word and SRC is a non-negative
744 constant that would appear negative in the mode of X,
745 sign-extend it for use in reg_nonzero_bits because some
746 machines (maybe most) will actually do the sign-extension
747 and this is the conservative approach.
749 ??? For 2.5, try to tighten up the MD files in this regard
750 instead of this kludge. */
752 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
753 && GET_CODE (src
) == CONST_INT
755 && 0 != (INTVAL (src
)
757 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
758 src
= GEN_INT (INTVAL (src
)
759 | ((HOST_WIDE_INT
) (-1)
760 << GET_MODE_BITSIZE (GET_MODE (x
))));
763 reg_nonzero_bits
[REGNO (x
)]
764 |= nonzero_bits (src
, nonzero_bits_mode
);
765 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
766 if (reg_sign_bit_copies
[REGNO (x
)] == 0
767 || reg_sign_bit_copies
[REGNO (x
)] > num
)
768 reg_sign_bit_copies
[REGNO (x
)] = num
;
772 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
773 reg_sign_bit_copies
[REGNO (x
)] = 0;
778 /* See if INSN can be combined into I3. PRED and SUCC are optionally
779 insns that were previously combined into I3 or that will be combined
780 into the merger of INSN and I3.
782 Return 0 if the combination is not allowed for any reason.
784 If the combination is allowed, *PDEST will be set to the single
785 destination of INSN and *PSRC to the single source, and this function
789 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
796 rtx set
= 0, src
, dest
;
798 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
799 && next_active_insn (succ
) == i3
)
800 : next_active_insn (insn
) == i3
);
802 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
803 or a PARALLEL consisting of such a SET and CLOBBERs.
805 If INSN has CLOBBER parallel parts, ignore them for our processing.
806 By definition, these happen during the execution of the insn. When it
807 is merged with another insn, all bets are off. If they are, in fact,
808 needed and aren't also supplied in I3, they may be added by
809 recog_for_combine. Otherwise, it won't match.
811 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
814 Get the source and destination of INSN. If more than one, can't
817 if (GET_CODE (PATTERN (insn
)) == SET
)
818 set
= PATTERN (insn
);
819 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
820 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
822 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
824 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
826 switch (GET_CODE (elt
))
828 /* We can ignore CLOBBERs. */
833 /* Ignore SETs whose result isn't used but not those that
834 have side-effects. */
835 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
836 && ! side_effects_p (elt
))
839 /* If we have already found a SET, this is a second one and
840 so we cannot combine with this insn. */
848 /* Anything else means we can't combine. */
854 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
855 so don't do anything with it. */
856 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
865 set
= expand_field_assignment (set
);
866 src
= SET_SRC (set
), dest
= SET_DEST (set
);
868 /* Don't eliminate a store in the stack pointer. */
869 if (dest
== stack_pointer_rtx
870 /* If we couldn't eliminate a field assignment, we can't combine. */
871 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
872 /* Don't combine with an insn that sets a register to itself if it has
873 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
874 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
875 /* Can't merge a function call. */
876 || GET_CODE (src
) == CALL
877 /* Don't eliminate a function call argument. */
878 || (GET_CODE (i3
) == CALL_INSN
879 && (find_reg_fusage (i3
, USE
, dest
)
880 || (GET_CODE (dest
) == REG
881 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
882 && global_regs
[REGNO (dest
)])))
883 /* Don't substitute into an incremented register. */
884 || FIND_REG_INC_NOTE (i3
, dest
)
885 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
886 /* Don't combine the end of a libcall into anything. */
887 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
888 /* Make sure that DEST is not used after SUCC but before I3. */
889 || (succ
&& ! all_adjacent
890 && reg_used_between_p (dest
, succ
, i3
))
891 /* Make sure that the value that is to be substituted for the register
892 does not use any registers whose values alter in between. However,
893 If the insns are adjacent, a use can't cross a set even though we
894 think it might (this can happen for a sequence of insns each setting
895 the same destination; reg_last_set of that register might point to
896 a NOTE). If INSN has a REG_EQUIV note, the register is always
897 equivalent to the memory so the substitution is valid even if there
898 are intervening stores. Also, don't move a volatile asm or
899 UNSPEC_VOLATILE across any other insns. */
901 && (((GET_CODE (src
) != MEM
902 || ! find_reg_note (insn
, REG_EQUIV
, src
))
903 && use_crosses_set_p (src
, INSN_CUID (insn
)))
904 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
905 || GET_CODE (src
) == UNSPEC_VOLATILE
))
906 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
907 better register allocation by not doing the combine. */
908 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
909 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
910 /* Don't combine across a CALL_INSN, because that would possibly
911 change whether the life span of some REGs crosses calls or not,
912 and it is a pain to update that information.
913 Exception: if source is a constant, moving it later can't hurt.
914 Accept that special case, because it helps -fforce-addr a lot. */
915 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
918 /* DEST must either be a REG or CC0. */
919 if (GET_CODE (dest
) == REG
)
921 /* If register alignment is being enforced for multi-word items in all
922 cases except for parameters, it is possible to have a register copy
923 insn referencing a hard register that is not allowed to contain the
924 mode being copied and which would not be valid as an operand of most
925 insns. Eliminate this problem by not combining with such an insn.
927 Also, on some machines we don't want to extend the life of a hard
930 if (GET_CODE (src
) == REG
931 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
932 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
933 /* Don't extend the life of a hard register unless it is
934 user variable (if we have few registers) or it can't
935 fit into the desired register (meaning something special
937 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
938 && (! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
))
939 #ifdef SMALL_REGISTER_CLASSES
940 || ! REG_USERVAR_P (src
)
945 else if (GET_CODE (dest
) != CC0
)
948 /* Don't substitute for a register intended as a clobberable operand.
949 Similarly, don't substitute an expression containing a register that
950 will be clobbered in I3. */
951 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
952 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
953 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
954 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
956 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
959 /* If INSN contains anything volatile, or is an `asm' (whether volatile
960 or not), reject, unless nothing volatile comes between it and I3,
961 with the exception of SUCC. */
963 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
964 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
965 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
966 && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
969 /* If there are any volatile insns between INSN and I3, reject, because
970 they might affect machine state. */
972 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
973 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
974 && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
977 /* If INSN or I2 contains an autoincrement or autodecrement,
978 make sure that register is not used between there and I3,
979 and not already used in I3 either.
980 Also insist that I3 not be a jump; if it were one
981 and the incremented register were spilled, we would lose. */
984 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
985 if (REG_NOTE_KIND (link
) == REG_INC
986 && (GET_CODE (i3
) == JUMP_INSN
987 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
988 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
993 /* Don't combine an insn that follows a CC0-setting insn.
994 An insn that uses CC0 must not be separated from the one that sets it.
995 We do, however, allow I2 to follow a CC0-setting insn if that insn
996 is passed as I1; in that case it will be deleted also.
997 We also allow combining in this case if all the insns are adjacent
998 because that would leave the two CC0 insns adjacent as well.
999 It would be more logical to test whether CC0 occurs inside I1 or I2,
1000 but that would be much slower, and this ought to be equivalent. */
1002 p
= prev_nonnote_insn (insn
);
1003 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1008 /* If we get here, we have passed all the tests and the combination is
1017 /* LOC is the location within I3 that contains its pattern or the component
1018 of a PARALLEL of the pattern. We validate that it is valid for combining.
1020 One problem is if I3 modifies its output, as opposed to replacing it
1021 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1022 so would produce an insn that is not equivalent to the original insns.
1026 (set (reg:DI 101) (reg:DI 100))
1027 (set (subreg:SI (reg:DI 101) 0) <foo>)
1029 This is NOT equivalent to:
1031 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1032 (set (reg:DI 101) (reg:DI 100))])
1034 Not only does this modify 100 (in which case it might still be valid
1035 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1037 We can also run into a problem if I2 sets a register that I1
1038 uses and I1 gets directly substituted into I3 (not via I2). In that
1039 case, we would be getting the wrong value of I2DEST into I3, so we
1040 must reject the combination. This case occurs when I2 and I1 both
1041 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1042 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1043 of a SET must prevent combination from occurring.
1045 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
1046 if the destination of a SET is a hard register that isn't a user
1049 Before doing the above check, we first try to expand a field assignment
1050 into a set of logical operations.
1052 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1053 we place a register that is both set and used within I3. If more than one
1054 such register is detected, we fail.
1056 Return 1 if the combination is valid, zero otherwise. */
1059 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1065 rtx
*pi3dest_killed
;
1069 if (GET_CODE (x
) == SET
)
1071 rtx set
= expand_field_assignment (x
);
1072 rtx dest
= SET_DEST (set
);
1073 rtx src
= SET_SRC (set
);
1074 rtx inner_dest
= dest
, inner_src
= src
;
1078 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1079 || GET_CODE (inner_dest
) == SUBREG
1080 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1081 inner_dest
= XEXP (inner_dest
, 0);
1083 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1086 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1087 || GET_CODE (inner_src
) == SUBREG
1088 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1089 inner_src
= XEXP (inner_src
, 0);
1091 /* If it is better that two different modes keep two different pseudos,
1092 avoid combining them. This avoids producing the following pattern
1094 (set (subreg:SI (reg/v:QI 21) 0)
1095 (lshiftrt:SI (reg/v:SI 20)
1097 If that were made, reload could not handle the pair of
1098 reg 20/21, since it would try to get any GENERAL_REGS
1099 but some of them don't handle QImode. */
1101 if (rtx_equal_p (inner_src
, i2dest
)
1102 && GET_CODE (inner_dest
) == REG
1103 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1107 /* Check for the case where I3 modifies its output, as
1109 if ((inner_dest
!= dest
1110 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1111 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1112 /* This is the same test done in can_combine_p except that we
1113 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1115 || (GET_CODE (inner_dest
) == REG
1116 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1117 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1118 GET_MODE (inner_dest
))
1119 #ifdef SMALL_REGISTER_CLASSES
1120 || (GET_CODE (src
) != CALL
&& ! REG_USERVAR_P (inner_dest
))
1123 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1126 /* If DEST is used in I3, it is being killed in this insn,
1127 so record that for later.
1128 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1129 STACK_POINTER_REGNUM, since these are always considered to be
1130 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1131 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1132 && reg_referenced_p (dest
, PATTERN (i3
))
1133 && REGNO (dest
) != FRAME_POINTER_REGNUM
1134 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1135 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1137 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1138 && (REGNO (dest
) != ARG_POINTER_REGNUM
1139 || ! fixed_regs
[REGNO (dest
)])
1141 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1143 if (*pi3dest_killed
)
1146 *pi3dest_killed
= dest
;
1150 else if (GET_CODE (x
) == PARALLEL
)
1154 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1155 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1156 i1_not_in_src
, pi3dest_killed
))
1163 /* Try to combine the insns I1 and I2 into I3.
1164 Here I1 and I2 appear earlier than I3.
1165 I1 can be zero; then we combine just I2 into I3.
1167 It we are combining three insns and the resulting insn is not recognized,
1168 try splitting it into two insns. If that happens, I2 and I3 are retained
1169 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1172 Return 0 if the combination does not work. Then nothing is changed.
1173 If we did the combination, return the insn at which combine should
1177 try_combine (i3
, i2
, i1
)
1178 register rtx i3
, i2
, i1
;
1180 /* New patterns for I3 and I3, respectively. */
1181 rtx newpat
, newi2pat
= 0;
1182 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1183 int added_sets_1
, added_sets_2
;
1184 /* Total number of SETs to put into I3. */
1186 /* Nonzero is I2's body now appears in I3. */
1188 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1189 int insn_code_number
, i2_code_number
, other_code_number
;
1190 /* Contains I3 if the destination of I3 is used in its source, which means
1191 that the old life of I3 is being killed. If that usage is placed into
1192 I2 and not in I3, a REG_DEAD note must be made. */
1193 rtx i3dest_killed
= 0;
1194 /* SET_DEST and SET_SRC of I2 and I1. */
1195 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1196 /* PATTERN (I2), or a copy of it in certain cases. */
1198 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1199 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1200 int i1_feeds_i3
= 0;
1201 /* Notes that must be added to REG_NOTES in I3 and I2. */
1202 rtx new_i3_notes
, new_i2_notes
;
1203 /* Notes that we substituted I3 into I2 instead of the normal case. */
1204 int i3_subst_into_i2
= 0;
1205 /* Notes that I1, I2 or I3 is a MULT operation. */
1213 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1214 This can occur when flow deletes an insn that it has merged into an
1215 auto-increment address. We also can't do anything if I3 has a
1216 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1219 if (GET_RTX_CLASS (GET_CODE (i3
)) != 'i'
1220 || GET_RTX_CLASS (GET_CODE (i2
)) != 'i'
1221 || (i1
&& GET_RTX_CLASS (GET_CODE (i1
)) != 'i')
1222 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
))
1227 undobuf
.num_undo
= previous_num_undos
= 0;
1228 undobuf
.other_insn
= 0;
1230 /* Save the current high-water-mark so we can free storage if we didn't
1231 accept this combination. */
1232 undobuf
.storage
= (char *) oballoc (0);
1234 /* Reset the hard register usage information. */
1235 CLEAR_HARD_REG_SET (newpat_used_regs
);
1237 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1238 code below, set I1 to be the earlier of the two insns. */
1239 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1240 temp
= i1
, i1
= i2
, i2
= temp
;
1242 added_links_insn
= 0;
1244 /* First check for one important special-case that the code below will
1245 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1246 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1247 we may be able to replace that destination with the destination of I3.
1248 This occurs in the common code where we compute both a quotient and
1249 remainder into a structure, in which case we want to do the computation
1250 directly into the structure to avoid register-register copies.
1252 We make very conservative checks below and only try to handle the
1253 most common cases of this. For example, we only handle the case
1254 where I2 and I3 are adjacent to avoid making difficult register
1257 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1258 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1259 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1260 #ifdef SMALL_REGISTER_CLASSES
1261 && (GET_CODE (SET_DEST (PATTERN (i3
))) != REG
1262 || REGNO (SET_DEST (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1263 || REG_USERVAR_P (SET_DEST (PATTERN (i3
))))
1265 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1266 && GET_CODE (PATTERN (i2
)) == PARALLEL
1267 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1268 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1269 below would need to check what is inside (and reg_overlap_mentioned_p
1270 doesn't support those codes anyway). Don't allow those destinations;
1271 the resulting insn isn't likely to be recognized anyway. */
1272 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1273 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1274 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1275 SET_DEST (PATTERN (i3
)))
1276 && next_real_insn (i2
) == i3
)
1278 rtx p2
= PATTERN (i2
);
1280 /* Make sure that the destination of I3,
1281 which we are going to substitute into one output of I2,
1282 is not used within another output of I2. We must avoid making this:
1283 (parallel [(set (mem (reg 69)) ...)
1284 (set (reg 69) ...)])
1285 which is not well-defined as to order of actions.
1286 (Besides, reload can't handle output reloads for this.)
1288 The problem can also happen if the dest of I3 is a memory ref,
1289 if another dest in I2 is an indirect memory ref. */
1290 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1291 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1292 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1293 SET_DEST (XVECEXP (p2
, 0, i
))))
1296 if (i
== XVECLEN (p2
, 0))
1297 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1298 if (SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1303 subst_low_cuid
= INSN_CUID (i2
);
1305 added_sets_2
= added_sets_1
= 0;
1306 i2dest
= SET_SRC (PATTERN (i3
));
1308 /* Replace the dest in I2 with our dest and make the resulting
1309 insn the new pattern for I3. Then skip to where we
1310 validate the pattern. Everything was set up above. */
1311 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1312 SET_DEST (PATTERN (i3
)));
1315 i3_subst_into_i2
= 1;
1316 goto validate_replacement
;
1321 /* If we have no I1 and I2 looks like:
1322 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1324 make up a dummy I1 that is
1327 (set (reg:CC X) (compare:CC Y (const_int 0)))
1329 (We can ignore any trailing CLOBBERs.)
1331 This undoes a previous combination and allows us to match a branch-and-
1334 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1335 && XVECLEN (PATTERN (i2
), 0) >= 2
1336 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1337 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1339 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1340 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1341 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1342 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1343 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1344 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1346 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1347 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1352 /* We make I1 with the same INSN_UID as I2. This gives it
1353 the same INSN_CUID for value tracking. Our fake I1 will
1354 never appear in the insn stream so giving it the same INSN_UID
1355 as I2 will not cause a problem. */
1357 i1
= gen_rtx (INSN
, VOIDmode
, INSN_UID (i2
), 0, i2
,
1358 XVECEXP (PATTERN (i2
), 0, 1), -1, 0, 0);
1360 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1361 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1362 SET_DEST (PATTERN (i1
)));
1367 /* Verify that I2 and I1 are valid for combining. */
1368 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1369 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1375 /* Record whether I2DEST is used in I2SRC and similarly for the other
1376 cases. Knowing this will help in register status updating below. */
1377 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1378 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1379 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1381 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1383 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1385 /* Ensure that I3's pattern can be the destination of combines. */
1386 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1387 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1394 /* See if any of the insns is a MULT operation. Unless one is, we will
1395 reject a combination that is, since it must be slower. Be conservative
1397 if (GET_CODE (i2src
) == MULT
1398 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1399 || (GET_CODE (PATTERN (i3
)) == SET
1400 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1403 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1404 We used to do this EXCEPT in one case: I3 has a post-inc in an
1405 output operand. However, that exception can give rise to insns like
1407 which is a famous insn on the PDP-11 where the value of r3 used as the
1408 source was model-dependent. Avoid this sort of thing. */
1411 if (!(GET_CODE (PATTERN (i3
)) == SET
1412 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1413 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1414 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1415 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1416 /* It's not the exception. */
1419 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1420 if (REG_NOTE_KIND (link
) == REG_INC
1421 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1423 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1430 /* See if the SETs in I1 or I2 need to be kept around in the merged
1431 instruction: whenever the value set there is still needed past I3.
1432 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1434 For the SET in I1, we have two cases: If I1 and I2 independently
1435 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1436 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1437 in I1 needs to be kept around unless I1DEST dies or is set in either
1438 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1439 I1DEST. If so, we know I1 feeds into I2. */
1441 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1444 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1445 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1447 /* If the set in I2 needs to be kept around, we must make a copy of
1448 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1449 PATTERN (I2), we are only substituting for the original I1DEST, not into
1450 an already-substituted copy. This also prevents making self-referential
1451 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1454 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1455 ? gen_rtx (SET
, VOIDmode
, i2dest
, i2src
)
1459 i2pat
= copy_rtx (i2pat
);
1463 /* Substitute in the latest insn for the regs set by the earlier ones. */
1465 maxreg
= max_reg_num ();
1469 /* It is possible that the source of I2 or I1 may be performing an
1470 unneeded operation, such as a ZERO_EXTEND of something that is known
1471 to have the high part zero. Handle that case by letting subst look at
1472 the innermost one of them.
1474 Another way to do this would be to have a function that tries to
1475 simplify a single insn instead of merging two or more insns. We don't
1476 do this because of the potential of infinite loops and because
1477 of the potential extra memory required. However, doing it the way
1478 we are is a bit of a kludge and doesn't catch all cases.
1480 But only do this if -fexpensive-optimizations since it slows things down
1481 and doesn't usually win. */
1483 if (flag_expensive_optimizations
)
1485 /* Pass pc_rtx so no substitutions are done, just simplifications.
1486 The cases that we are interested in here do not involve the few
1487 cases were is_replaced is checked. */
1490 subst_low_cuid
= INSN_CUID (i1
);
1491 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1495 subst_low_cuid
= INSN_CUID (i2
);
1496 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1499 previous_num_undos
= undobuf
.num_undo
;
1503 /* Many machines that don't use CC0 have insns that can both perform an
1504 arithmetic operation and set the condition code. These operations will
1505 be represented as a PARALLEL with the first element of the vector
1506 being a COMPARE of an arithmetic operation with the constant zero.
1507 The second element of the vector will set some pseudo to the result
1508 of the same arithmetic operation. If we simplify the COMPARE, we won't
1509 match such a pattern and so will generate an extra insn. Here we test
1510 for this case, where both the comparison and the operation result are
1511 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1512 I2SRC. Later we will make the PARALLEL that contains I2. */
1514 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1515 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1516 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1517 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1520 enum machine_mode compare_mode
;
1522 newpat
= PATTERN (i3
);
1523 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1527 #ifdef EXTRA_CC_MODES
1528 /* See if a COMPARE with the operand we substituted in should be done
1529 with the mode that is currently being used. If not, do the same
1530 processing we do in `subst' for a SET; namely, if the destination
1531 is used only once, try to replace it with a register of the proper
1532 mode and also replace the COMPARE. */
1533 if (undobuf
.other_insn
== 0
1534 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1535 &undobuf
.other_insn
))
1536 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1538 != GET_MODE (SET_DEST (newpat
))))
1540 int regno
= REGNO (SET_DEST (newpat
));
1541 rtx new_dest
= gen_rtx (REG
, compare_mode
, regno
);
1543 if (regno
< FIRST_PSEUDO_REGISTER
1544 || (reg_n_sets
[regno
] == 1 && ! added_sets_2
1545 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1547 if (regno
>= FIRST_PSEUDO_REGISTER
)
1548 SUBST (regno_reg_rtx
[regno
], new_dest
);
1550 SUBST (SET_DEST (newpat
), new_dest
);
1551 SUBST (XEXP (*cc_use
, 0), new_dest
);
1552 SUBST (SET_SRC (newpat
),
1553 gen_rtx_combine (COMPARE
, compare_mode
,
1554 i2src
, const0_rtx
));
1557 undobuf
.other_insn
= 0;
1564 n_occurrences
= 0; /* `subst' counts here */
1566 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1567 need to make a unique copy of I2SRC each time we substitute it
1568 to avoid self-referential rtl. */
1570 subst_low_cuid
= INSN_CUID (i2
);
1571 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1572 ! i1_feeds_i3
&& i1dest_in_i1src
);
1573 previous_num_undos
= undobuf
.num_undo
;
1575 /* Record whether i2's body now appears within i3's body. */
1576 i2_is_used
= n_occurrences
;
1579 /* If we already got a failure, don't try to do more. Otherwise,
1580 try to substitute in I1 if we have it. */
1582 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1584 /* Before we can do this substitution, we must redo the test done
1585 above (see detailed comments there) that ensures that I1DEST
1586 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1588 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1596 subst_low_cuid
= INSN_CUID (i1
);
1597 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1598 previous_num_undos
= undobuf
.num_undo
;
1601 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1602 to count all the ways that I2SRC and I1SRC can be used. */
1603 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1604 && i2_is_used
+ added_sets_2
> 1)
1605 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1606 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1608 /* Fail if we tried to make a new register (we used to abort, but there's
1609 really no reason to). */
1610 || max_reg_num () != maxreg
1611 /* Fail if we couldn't do something and have a CLOBBER. */
1612 || GET_CODE (newpat
) == CLOBBER
1613 /* Fail if this new pattern is a MULT and we didn't have one before
1614 at the outer level. */
1615 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1622 /* If the actions of the earlier insns must be kept
1623 in addition to substituting them into the latest one,
1624 we must make a new PARALLEL for the latest insn
1625 to hold additional the SETs. */
1627 if (added_sets_1
|| added_sets_2
)
1631 if (GET_CODE (newpat
) == PARALLEL
)
1633 rtvec old
= XVEC (newpat
, 0);
1634 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1635 newpat
= gen_rtx (PARALLEL
, VOIDmode
, rtvec_alloc (total_sets
));
1636 bcopy ((char *) &old
->elem
[0], (char *) &XVECEXP (newpat
, 0, 0),
1637 sizeof (old
->elem
[0]) * old
->num_elem
);
1642 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1643 newpat
= gen_rtx (PARALLEL
, VOIDmode
, rtvec_alloc (total_sets
));
1644 XVECEXP (newpat
, 0, 0) = old
;
1648 XVECEXP (newpat
, 0, --total_sets
)
1649 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1650 ? gen_rtx (SET
, VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1654 /* If there is no I1, use I2's body as is. We used to also not do
1655 the subst call below if I2 was substituted into I3,
1656 but that could lose a simplification. */
1658 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
1660 /* See comment where i2pat is assigned. */
1661 XVECEXP (newpat
, 0, --total_sets
)
1662 = subst (i2pat
, i1dest
, i1src
, 0, 0);
1666 /* We come here when we are replacing a destination in I2 with the
1667 destination of I3. */
1668 validate_replacement
:
1670 /* Note which hard regs this insn has as inputs. */
1671 mark_used_regs_combine (newpat
);
1673 /* Is the result of combination a valid instruction? */
1674 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1676 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1677 the second SET's destination is a register that is unused. In that case,
1678 we just need the first SET. This can occur when simplifying a divmod
1679 insn. We *must* test for this case here because the code below that
1680 splits two independent SETs doesn't handle this case correctly when it
1681 updates the register status. Also check the case where the first
1682 SET's destination is unused. That would not cause incorrect code, but
1683 does cause an unneeded insn to remain. */
1685 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
1686 && XVECLEN (newpat
, 0) == 2
1687 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1688 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1689 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
1690 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
1691 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
1692 && asm_noperands (newpat
) < 0)
1694 newpat
= XVECEXP (newpat
, 0, 0);
1695 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1698 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
1699 && XVECLEN (newpat
, 0) == 2
1700 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1701 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1702 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
1703 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
1704 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
1705 && asm_noperands (newpat
) < 0)
1707 newpat
= XVECEXP (newpat
, 0, 1);
1708 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1711 /* If we were combining three insns and the result is a simple SET
1712 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1713 insns. There are two ways to do this. It can be split using a
1714 machine-specific method (like when you have an addition of a large
1715 constant) or by combine in the function find_split_point. */
1717 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
1718 && asm_noperands (newpat
) < 0)
1720 rtx m_split
, *split
;
1721 rtx ni2dest
= i2dest
;
1723 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1724 use I2DEST as a scratch register will help. In the latter case,
1725 convert I2DEST to the mode of the source of NEWPAT if we can. */
1727 m_split
= split_insns (newpat
, i3
);
1729 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1730 inputs of NEWPAT. */
1732 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1733 possible to try that as a scratch reg. This would require adding
1734 more code to make it work though. */
1736 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
1738 /* If I2DEST is a hard register or the only use of a pseudo,
1739 we can change its mode. */
1740 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
1741 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
1742 && GET_CODE (i2dest
) == REG
1743 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
1744 || (reg_n_sets
[REGNO (i2dest
)] == 1 && ! added_sets_2
1745 && ! REG_USERVAR_P (i2dest
))))
1746 ni2dest
= gen_rtx (REG
, GET_MODE (SET_DEST (newpat
)),
1749 m_split
= split_insns (gen_rtx (PARALLEL
, VOIDmode
,
1750 gen_rtvec (2, newpat
,
1757 if (m_split
&& GET_CODE (m_split
) == SEQUENCE
1758 && XVECLEN (m_split
, 0) == 2
1759 && (next_real_insn (i2
) == i3
1760 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
1764 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
1765 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
1767 i3set
= single_set (XVECEXP (m_split
, 0, 1));
1768 i2set
= single_set (XVECEXP (m_split
, 0, 0));
1770 /* In case we changed the mode of I2DEST, replace it in the
1771 pseudo-register table here. We can't do it above in case this
1772 code doesn't get executed and we do a split the other way. */
1774 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
1775 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
1777 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
1779 /* If I2 or I3 has multiple SETs, we won't know how to track
1780 register status, so don't use these insns. */
1782 if (i2_code_number
>= 0 && i2set
&& i3set
)
1783 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
1786 if (insn_code_number
>= 0)
1789 /* It is possible that both insns now set the destination of I3.
1790 If so, we must show an extra use of it. */
1792 if (insn_code_number
>= 0 && GET_CODE (SET_DEST (i3set
)) == REG
1793 && GET_CODE (SET_DEST (i2set
)) == REG
1794 && REGNO (SET_DEST (i3set
)) == REGNO (SET_DEST (i2set
)))
1795 reg_n_sets
[REGNO (SET_DEST (i2set
))]++;
1798 /* If we can split it and use I2DEST, go ahead and see if that
1799 helps things be recognized. Verify that none of the registers
1800 are set between I2 and I3. */
1801 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
1803 && GET_CODE (i2dest
) == REG
1805 /* We need I2DEST in the proper mode. If it is a hard register
1806 or the only use of a pseudo, we can change its mode. */
1807 && (GET_MODE (*split
) == GET_MODE (i2dest
)
1808 || GET_MODE (*split
) == VOIDmode
1809 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
1810 || (reg_n_sets
[REGNO (i2dest
)] == 1 && ! added_sets_2
1811 && ! REG_USERVAR_P (i2dest
)))
1812 && (next_real_insn (i2
) == i3
1813 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
1814 /* We can't overwrite I2DEST if its value is still used by
1816 && ! reg_referenced_p (i2dest
, newpat
))
1818 rtx newdest
= i2dest
;
1819 enum rtx_code split_code
= GET_CODE (*split
);
1820 enum machine_mode split_mode
= GET_MODE (*split
);
1822 /* Get NEWDEST as a register in the proper mode. We have already
1823 validated that we can do this. */
1824 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
1826 newdest
= gen_rtx (REG
, split_mode
, REGNO (i2dest
));
1828 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
1829 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
1832 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1833 an ASHIFT. This can occur if it was inside a PLUS and hence
1834 appeared to be a memory address. This is a kludge. */
1835 if (split_code
== MULT
1836 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
1837 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
1839 SUBST (*split
, gen_rtx_combine (ASHIFT
, split_mode
,
1840 XEXP (*split
, 0), GEN_INT (i
)));
1841 /* Update split_code because we may not have a multiply
1843 split_code
= GET_CODE (*split
);
1846 #ifdef INSN_SCHEDULING
1847 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1848 be written as a ZERO_EXTEND. */
1849 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
1850 SUBST (*split
, gen_rtx_combine (ZERO_EXTEND
, split_mode
,
1854 newi2pat
= gen_rtx_combine (SET
, VOIDmode
, newdest
, *split
);
1855 SUBST (*split
, newdest
);
1856 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
1858 /* If the split point was a MULT and we didn't have one before,
1859 don't use one now. */
1860 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
1861 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1865 /* Check for a case where we loaded from memory in a narrow mode and
1866 then sign extended it, but we need both registers. In that case,
1867 we have a PARALLEL with both loads from the same memory location.
1868 We can split this into a load from memory followed by a register-register
1869 copy. This saves at least one insn, more if register allocation can
1872 We cannot do this if the destination of the second assignment is
1873 a register that we have already assumed is zero-extended. Similarly
1874 for a SUBREG of such a register. */
1876 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
1877 && GET_CODE (newpat
) == PARALLEL
1878 && XVECLEN (newpat
, 0) == 2
1879 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1880 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
1881 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1882 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
1883 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
1884 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
1886 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
1887 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
1888 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
1889 (GET_CODE (temp
) == REG
1890 && reg_nonzero_bits
[REGNO (temp
)] != 0
1891 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
1892 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
1893 && (reg_nonzero_bits
[REGNO (temp
)]
1894 != GET_MODE_MASK (word_mode
))))
1895 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
1896 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
1897 (GET_CODE (temp
) == REG
1898 && reg_nonzero_bits
[REGNO (temp
)] != 0
1899 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
1900 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
1901 && (reg_nonzero_bits
[REGNO (temp
)]
1902 != GET_MODE_MASK (word_mode
)))))
1903 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
1904 SET_SRC (XVECEXP (newpat
, 0, 1)))
1905 && ! find_reg_note (i3
, REG_UNUSED
,
1906 SET_DEST (XVECEXP (newpat
, 0, 0))))
1910 newi2pat
= XVECEXP (newpat
, 0, 0);
1911 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
1912 newpat
= XVECEXP (newpat
, 0, 1);
1913 SUBST (SET_SRC (newpat
),
1914 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
1915 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
1916 if (i2_code_number
>= 0)
1917 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1919 if (insn_code_number
>= 0)
1924 /* If we will be able to accept this, we have made a change to the
1925 destination of I3. This can invalidate a LOG_LINKS pointing
1926 to I3. No other part of combine.c makes such a transformation.
1928 The new I3 will have a destination that was previously the
1929 destination of I1 or I2 and which was used in i2 or I3. Call
1930 distribute_links to make a LOG_LINK from the next use of
1931 that destination. */
1933 PATTERN (i3
) = newpat
;
1934 distribute_links (gen_rtx (INSN_LIST
, VOIDmode
, i3
, NULL_RTX
));
1936 /* I3 now uses what used to be its destination and which is
1937 now I2's destination. That means we need a LOG_LINK from
1938 I3 to I2. But we used to have one, so we still will.
1940 However, some later insn might be using I2's dest and have
1941 a LOG_LINK pointing at I3. We must remove this link.
1942 The simplest way to remove the link is to point it at I1,
1943 which we know will be a NOTE. */
1945 for (insn
= NEXT_INSN (i3
);
1946 insn
&& (this_basic_block
== n_basic_blocks
- 1
1947 || insn
!= basic_block_head
[this_basic_block
+ 1]);
1948 insn
= NEXT_INSN (insn
))
1950 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
1951 && reg_referenced_p (ni2dest
, PATTERN (insn
)))
1953 for (link
= LOG_LINKS (insn
); link
;
1954 link
= XEXP (link
, 1))
1955 if (XEXP (link
, 0) == i3
)
1956 XEXP (link
, 0) = i1
;
1964 /* Similarly, check for a case where we have a PARALLEL of two independent
1965 SETs but we started with three insns. In this case, we can do the sets
1966 as two separate insns. This case occurs when some SET allows two
1967 other insns to combine, but the destination of that SET is still live. */
1969 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
1970 && GET_CODE (newpat
) == PARALLEL
1971 && XVECLEN (newpat
, 0) == 2
1972 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1973 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
1974 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
1975 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1976 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
1977 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
1978 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
1980 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1981 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
1982 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
1983 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
1984 XVECEXP (newpat
, 0, 0))
1985 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
1986 XVECEXP (newpat
, 0, 1)))
1988 newi2pat
= XVECEXP (newpat
, 0, 1);
1989 newpat
= XVECEXP (newpat
, 0, 0);
1991 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
1992 if (i2_code_number
>= 0)
1993 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1996 /* If it still isn't recognized, fail and change things back the way they
1998 if ((insn_code_number
< 0
1999 /* Is the result a reasonable ASM_OPERANDS? */
2000 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2006 /* If we had to change another insn, make sure it is valid also. */
2007 if (undobuf
.other_insn
)
2009 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2010 rtx new_other_notes
;
2013 CLEAR_HARD_REG_SET (newpat_used_regs
);
2015 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2018 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2024 PATTERN (undobuf
.other_insn
) = other_pat
;
2026 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2027 are still valid. Then add any non-duplicate notes added by
2028 recog_for_combine. */
2029 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2031 next
= XEXP (note
, 1);
2033 if (REG_NOTE_KIND (note
) == REG_UNUSED
2034 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2036 if (GET_CODE (XEXP (note
, 0)) == REG
)
2037 reg_n_deaths
[REGNO (XEXP (note
, 0))]--;
2039 remove_note (undobuf
.other_insn
, note
);
2043 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2044 if (GET_CODE (XEXP (note
, 0)) == REG
)
2045 reg_n_deaths
[REGNO (XEXP (note
, 0))]++;
2047 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2048 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2051 /* We now know that we can do this combination. Merge the insns and
2052 update the status of registers and LOG_LINKS. */
2055 rtx i3notes
, i2notes
, i1notes
= 0;
2056 rtx i3links
, i2links
, i1links
= 0;
2059 /* Compute which registers we expect to eliminate. */
2060 rtx elim_i2
= (newi2pat
|| i2dest_in_i2src
|| i2dest_in_i1src
2062 rtx elim_i1
= i1
== 0 || i1dest_in_i1src
? 0 : i1dest
;
2064 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2066 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2067 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2069 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2071 /* Ensure that we do not have something that should not be shared but
2072 occurs multiple times in the new insns. Check this by first
2073 resetting all the `used' flags and then copying anything is shared. */
2075 reset_used_flags (i3notes
);
2076 reset_used_flags (i2notes
);
2077 reset_used_flags (i1notes
);
2078 reset_used_flags (newpat
);
2079 reset_used_flags (newi2pat
);
2080 if (undobuf
.other_insn
)
2081 reset_used_flags (PATTERN (undobuf
.other_insn
));
2083 i3notes
= copy_rtx_if_shared (i3notes
);
2084 i2notes
= copy_rtx_if_shared (i2notes
);
2085 i1notes
= copy_rtx_if_shared (i1notes
);
2086 newpat
= copy_rtx_if_shared (newpat
);
2087 newi2pat
= copy_rtx_if_shared (newi2pat
);
2088 if (undobuf
.other_insn
)
2089 reset_used_flags (PATTERN (undobuf
.other_insn
));
2091 INSN_CODE (i3
) = insn_code_number
;
2092 PATTERN (i3
) = newpat
;
2093 if (undobuf
.other_insn
)
2094 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2096 /* We had one special case above where I2 had more than one set and
2097 we replaced a destination of one of those sets with the destination
2098 of I3. In that case, we have to update LOG_LINKS of insns later
2099 in this basic block. Note that this (expensive) case is rare.
2101 Also, in this case, we must pretend that all REG_NOTEs for I2
2102 actually came from I3, so that REG_UNUSED notes from I2 will be
2103 properly handled. */
2105 if (i3_subst_into_i2
)
2107 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2108 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2109 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2110 && ! find_reg_note (i2
, REG_UNUSED
,
2111 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2112 for (temp
= NEXT_INSN (i2
);
2113 temp
&& (this_basic_block
== n_basic_blocks
- 1
2114 || basic_block_head
[this_basic_block
] != temp
);
2115 temp
= NEXT_INSN (temp
))
2116 if (temp
!= i3
&& GET_RTX_CLASS (GET_CODE (temp
)) == 'i')
2117 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2118 if (XEXP (link
, 0) == i2
)
2119 XEXP (link
, 0) = i3
;
2124 while (XEXP (link
, 1))
2125 link
= XEXP (link
, 1);
2126 XEXP (link
, 1) = i2notes
;
2140 INSN_CODE (i2
) = i2_code_number
;
2141 PATTERN (i2
) = newi2pat
;
2145 PUT_CODE (i2
, NOTE
);
2146 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2147 NOTE_SOURCE_FILE (i2
) = 0;
2154 PUT_CODE (i1
, NOTE
);
2155 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2156 NOTE_SOURCE_FILE (i1
) = 0;
2159 /* Get death notes for everything that is now used in either I3 or
2160 I2 and used to die in a previous insn. */
2162 move_deaths (newpat
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
), i3
, &midnotes
);
2164 move_deaths (newi2pat
, INSN_CUID (i1
), i2
, &midnotes
);
2166 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2168 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2171 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2174 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2177 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2180 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2181 know these are REG_UNUSED and want them to go to the desired insn,
2182 so we always pass it as i3. We have not counted the notes in
2183 reg_n_deaths yet, so we need to do so now. */
2185 if (newi2pat
&& new_i2_notes
)
2187 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2188 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2189 reg_n_deaths
[REGNO (XEXP (temp
, 0))]++;
2191 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2196 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2197 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2198 reg_n_deaths
[REGNO (XEXP (temp
, 0))]++;
2200 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2203 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2204 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
2205 Show an additional death due to the REG_DEAD note we make here. If
2206 we discard it in distribute_notes, we will decrement it again. */
2210 if (GET_CODE (i3dest_killed
) == REG
)
2211 reg_n_deaths
[REGNO (i3dest_killed
)]++;
2213 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i3dest_killed
,
2215 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2216 NULL_RTX
, NULL_RTX
);
2219 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
2220 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
2221 we passed I3 in that case, it might delete I2. */
2223 if (i2dest_in_i2src
)
2225 if (GET_CODE (i2dest
) == REG
)
2226 reg_n_deaths
[REGNO (i2dest
)]++;
2228 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2229 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i2dest
, NULL_RTX
),
2230 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2232 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i2dest
, NULL_RTX
),
2233 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2234 NULL_RTX
, NULL_RTX
);
2237 if (i1dest_in_i1src
)
2239 if (GET_CODE (i1dest
) == REG
)
2240 reg_n_deaths
[REGNO (i1dest
)]++;
2242 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2243 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i1dest
, NULL_RTX
),
2244 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2246 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i1dest
, NULL_RTX
),
2247 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2248 NULL_RTX
, NULL_RTX
);
2251 distribute_links (i3links
);
2252 distribute_links (i2links
);
2253 distribute_links (i1links
);
2255 if (GET_CODE (i2dest
) == REG
)
2258 rtx i2_insn
= 0, i2_val
= 0, set
;
2260 /* The insn that used to set this register doesn't exist, and
2261 this life of the register may not exist either. See if one of
2262 I3's links points to an insn that sets I2DEST. If it does,
2263 that is now the last known value for I2DEST. If we don't update
2264 this and I2 set the register to a value that depended on its old
2265 contents, we will get confused. If this insn is used, thing
2266 will be set correctly in combine_instructions. */
2268 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2269 if ((set
= single_set (XEXP (link
, 0))) != 0
2270 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2271 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2273 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2275 /* If the reg formerly set in I2 died only once and that was in I3,
2276 zero its use count so it won't make `reload' do any work. */
2277 if (! added_sets_2
&& newi2pat
== 0 && ! i2dest_in_i2src
)
2279 regno
= REGNO (i2dest
);
2280 reg_n_sets
[regno
]--;
2281 if (reg_n_sets
[regno
] == 0
2282 && ! (basic_block_live_at_start
[0][regno
/ REGSET_ELT_BITS
]
2283 & ((REGSET_ELT_TYPE
) 1 << (regno
% REGSET_ELT_BITS
))))
2284 reg_n_refs
[regno
] = 0;
2288 if (i1
&& GET_CODE (i1dest
) == REG
)
2291 rtx i1_insn
= 0, i1_val
= 0, set
;
2293 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2294 if ((set
= single_set (XEXP (link
, 0))) != 0
2295 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2296 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2298 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2300 regno
= REGNO (i1dest
);
2301 if (! added_sets_1
&& ! i1dest_in_i1src
)
2303 reg_n_sets
[regno
]--;
2304 if (reg_n_sets
[regno
] == 0
2305 && ! (basic_block_live_at_start
[0][regno
/ REGSET_ELT_BITS
]
2306 & ((REGSET_ELT_TYPE
) 1 << (regno
% REGSET_ELT_BITS
))))
2307 reg_n_refs
[regno
] = 0;
2311 /* Update reg_nonzero_bits et al for any changes that may have been made
2314 note_stores (newpat
, set_nonzero_bits_and_sign_copies
);
2316 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
);
2318 /* If I3 is now an unconditional jump, ensure that it has a
2319 BARRIER following it since it may have initially been a
2320 conditional jump. It may also be the last nonnote insn. */
2322 if ((GET_CODE (newpat
) == RETURN
|| simplejump_p (i3
))
2323 && ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2324 || GET_CODE (temp
) != BARRIER
))
2325 emit_barrier_after (i3
);
2328 combine_successes
++;
2330 if (added_links_insn
2331 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2332 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2333 return added_links_insn
;
2335 return newi2pat
? i2
: i3
;
2338 /* Undo all the modifications recorded in undobuf. */
2344 if (undobuf
.num_undo
> MAX_UNDO
)
2345 undobuf
.num_undo
= MAX_UNDO
;
2346 for (i
= undobuf
.num_undo
- 1; i
>= 0; i
--)
2348 if (undobuf
.undo
[i
].is_int
)
2349 *undobuf
.undo
[i
].where
.i
= undobuf
.undo
[i
].old_contents
.i
;
2351 *undobuf
.undo
[i
].where
.r
= undobuf
.undo
[i
].old_contents
.r
;
2355 obfree (undobuf
.storage
);
2356 undobuf
.num_undo
= 0;
2359 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2360 where we have an arithmetic expression and return that point. LOC will
2363 try_combine will call this function to see if an insn can be split into
2367 find_split_point (loc
, insn
)
2372 enum rtx_code code
= GET_CODE (x
);
2374 int len
= 0, pos
, unsignedp
;
2377 /* First special-case some codes. */
2381 #ifdef INSN_SCHEDULING
2382 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2384 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2387 return find_split_point (&SUBREG_REG (x
), insn
);
2391 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2392 using LO_SUM and HIGH. */
2393 if (GET_CODE (XEXP (x
, 0)) == CONST
2394 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2397 gen_rtx_combine (LO_SUM
, Pmode
,
2398 gen_rtx_combine (HIGH
, Pmode
, XEXP (x
, 0)),
2400 return &XEXP (XEXP (x
, 0), 0);
2404 /* If we have a PLUS whose second operand is a constant and the
2405 address is not valid, perhaps will can split it up using
2406 the machine-specific way to split large constants. We use
2407 the first psuedo-reg (one of the virtual regs) as a placeholder;
2408 it will not remain in the result. */
2409 if (GET_CODE (XEXP (x
, 0)) == PLUS
2410 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2411 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2413 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2414 rtx seq
= split_insns (gen_rtx (SET
, VOIDmode
, reg
, XEXP (x
, 0)),
2417 /* This should have produced two insns, each of which sets our
2418 placeholder. If the source of the second is a valid address,
2419 we can make put both sources together and make a split point
2422 if (seq
&& XVECLEN (seq
, 0) == 2
2423 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2424 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2425 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2426 && ! reg_mentioned_p (reg
,
2427 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2428 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2429 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2430 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2431 && memory_address_p (GET_MODE (x
),
2432 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2434 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2435 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2437 /* Replace the placeholder in SRC2 with SRC1. If we can
2438 find where in SRC2 it was placed, that can become our
2439 split point and we can replace this address with SRC2.
2440 Just try two obvious places. */
2442 src2
= replace_rtx (src2
, reg
, src1
);
2444 if (XEXP (src2
, 0) == src1
)
2445 split
= &XEXP (src2
, 0);
2446 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2447 && XEXP (XEXP (src2
, 0), 0) == src1
)
2448 split
= &XEXP (XEXP (src2
, 0), 0);
2452 SUBST (XEXP (x
, 0), src2
);
2457 /* If that didn't work, perhaps the first operand is complex and
2458 needs to be computed separately, so make a split point there.
2459 This will occur on machines that just support REG + CONST
2460 and have a constant moved through some previous computation. */
2462 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2463 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2464 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2466 return &XEXP (XEXP (x
, 0), 0);
2472 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2473 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2474 we need to put the operand into a register. So split at that
2477 if (SET_DEST (x
) == cc0_rtx
2478 && GET_CODE (SET_SRC (x
)) != COMPARE
2479 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2480 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2481 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2482 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2483 return &SET_SRC (x
);
2486 /* See if we can split SET_SRC as it stands. */
2487 split
= find_split_point (&SET_SRC (x
), insn
);
2488 if (split
&& split
!= &SET_SRC (x
))
2491 /* See if this is a bitfield assignment with everything constant. If
2492 so, this is an IOR of an AND, so split it into that. */
2493 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2494 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2495 <= HOST_BITS_PER_WIDE_INT
)
2496 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2497 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2498 && GET_CODE (SET_SRC (x
)) == CONST_INT
2499 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2500 + INTVAL (XEXP (SET_DEST (x
), 2)))
2501 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2502 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2504 int pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2505 int len
= INTVAL (XEXP (SET_DEST (x
), 1));
2506 int src
= INTVAL (SET_SRC (x
));
2507 rtx dest
= XEXP (SET_DEST (x
), 0);
2508 enum machine_mode mode
= GET_MODE (dest
);
2509 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
2511 if (BITS_BIG_ENDIAN
)
2512 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
2516 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
2519 gen_binary (IOR
, mode
,
2520 gen_binary (AND
, mode
, dest
,
2521 GEN_INT (~ (mask
<< pos
)
2522 & GET_MODE_MASK (mode
))),
2523 GEN_INT (src
<< pos
)));
2525 SUBST (SET_DEST (x
), dest
);
2527 split
= find_split_point (&SET_SRC (x
), insn
);
2528 if (split
&& split
!= &SET_SRC (x
))
2532 /* Otherwise, see if this is an operation that we can split into two.
2533 If so, try to split that. */
2534 code
= GET_CODE (SET_SRC (x
));
2539 /* If we are AND'ing with a large constant that is only a single
2540 bit and the result is only being used in a context where we
2541 need to know if it is zero or non-zero, replace it with a bit
2542 extraction. This will avoid the large constant, which might
2543 have taken more than one insn to make. If the constant were
2544 not a valid argument to the AND but took only one insn to make,
2545 this is no worse, but if it took more than one insn, it will
2548 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2549 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
2550 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
2551 && GET_CODE (SET_DEST (x
)) == REG
2552 && (split
= find_single_use (SET_DEST (x
), insn
, NULL_PTR
)) != 0
2553 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
2554 && XEXP (*split
, 0) == SET_DEST (x
)
2555 && XEXP (*split
, 1) == const0_rtx
)
2558 make_extraction (GET_MODE (SET_DEST (x
)),
2559 XEXP (SET_SRC (x
), 0),
2560 pos
, NULL_RTX
, 1, 1, 0, 0));
2561 return find_split_point (loc
, insn
);
2566 inner
= XEXP (SET_SRC (x
), 0);
2568 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
2574 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2575 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
2577 inner
= XEXP (SET_SRC (x
), 0);
2578 len
= INTVAL (XEXP (SET_SRC (x
), 1));
2579 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
2581 if (BITS_BIG_ENDIAN
)
2582 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
2583 unsignedp
= (code
== ZERO_EXTRACT
);
2588 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
2590 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
2592 /* For unsigned, we have a choice of a shift followed by an
2593 AND or two shifts. Use two shifts for field sizes where the
2594 constant might be too large. We assume here that we can
2595 always at least get 8-bit constants in an AND insn, which is
2596 true for every current RISC. */
2598 if (unsignedp
&& len
<= 8)
2603 gen_rtx_combine (LSHIFTRT
, mode
,
2604 gen_lowpart_for_combine (mode
, inner
),
2606 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
2608 split
= find_split_point (&SET_SRC (x
), insn
);
2609 if (split
&& split
!= &SET_SRC (x
))
2616 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
2617 gen_rtx_combine (ASHIFT
, mode
,
2618 gen_lowpart_for_combine (mode
, inner
),
2619 GEN_INT (GET_MODE_BITSIZE (mode
)
2621 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
2623 split
= find_split_point (&SET_SRC (x
), insn
);
2624 if (split
&& split
!= &SET_SRC (x
))
2629 /* See if this is a simple operation with a constant as the second
2630 operand. It might be that this constant is out of range and hence
2631 could be used as a split point. */
2632 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
2633 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
2634 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
2635 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
2636 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
2637 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
2638 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
2640 return &XEXP (SET_SRC (x
), 1);
2642 /* Finally, see if this is a simple operation with its first operand
2643 not in a register. The operation might require this operand in a
2644 register, so return it as a split point. We can always do this
2645 because if the first operand were another operation, we would have
2646 already found it as a split point. */
2647 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
2648 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
2649 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
2650 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
2651 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
2652 return &XEXP (SET_SRC (x
), 0);
2658 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2659 it is better to write this as (not (ior A B)) so we can split it.
2660 Similarly for IOR. */
2661 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
2664 gen_rtx_combine (NOT
, GET_MODE (x
),
2665 gen_rtx_combine (code
== IOR
? AND
: IOR
,
2667 XEXP (XEXP (x
, 0), 0),
2668 XEXP (XEXP (x
, 1), 0))));
2669 return find_split_point (loc
, insn
);
2672 /* Many RISC machines have a large set of logical insns. If the
2673 second operand is a NOT, put it first so we will try to split the
2674 other operand first. */
2675 if (GET_CODE (XEXP (x
, 1)) == NOT
)
2677 rtx tem
= XEXP (x
, 0);
2678 SUBST (XEXP (x
, 0), XEXP (x
, 1));
2679 SUBST (XEXP (x
, 1), tem
);
2684 /* Otherwise, select our actions depending on our rtx class. */
2685 switch (GET_RTX_CLASS (code
))
2687 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2689 split
= find_split_point (&XEXP (x
, 2), insn
);
2692 /* ... fall through ... */
2696 split
= find_split_point (&XEXP (x
, 1), insn
);
2699 /* ... fall through ... */
2701 /* Some machines have (and (shift ...) ...) insns. If X is not
2702 an AND, but XEXP (X, 0) is, use it as our split point. */
2703 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
2704 return &XEXP (x
, 0);
2706 split
= find_split_point (&XEXP (x
, 0), insn
);
2712 /* Otherwise, we don't have a split point. */
2716 /* Throughout X, replace FROM with TO, and return the result.
2717 The result is TO if X is FROM;
2718 otherwise the result is X, but its contents may have been modified.
2719 If they were modified, a record was made in undobuf so that
2720 undo_all will (among other things) return X to its original state.
2722 If the number of changes necessary is too much to record to undo,
2723 the excess changes are not made, so the result is invalid.
2724 The changes already made can still be undone.
2725 undobuf.num_undo is incremented for such changes, so by testing that
2726 the caller can tell whether the result is valid.
2728 `n_occurrences' is incremented each time FROM is replaced.
2730 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2732 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2733 by copying if `n_occurrences' is non-zero. */
2736 subst (x
, from
, to
, in_dest
, unique_copy
)
2737 register rtx x
, from
, to
;
2741 register enum rtx_code code
= GET_CODE (x
);
2742 enum machine_mode op0_mode
= VOIDmode
;
2744 register int len
, i
;
2747 /* Two expressions are equal if they are identical copies of a shared
2748 RTX or if they are both registers with the same register number
2751 #define COMBINE_RTX_EQUAL_P(X,Y) \
2753 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2754 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2756 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
2759 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
2762 /* If X and FROM are the same register but different modes, they will
2763 not have been seen as equal above. However, flow.c will make a
2764 LOG_LINKS entry for that case. If we do nothing, we will try to
2765 rerecognize our original insn and, when it succeeds, we will
2766 delete the feeding insn, which is incorrect.
2768 So force this insn not to match in this (rare) case. */
2769 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
2770 && REGNO (x
) == REGNO (from
))
2771 return gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
2773 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2774 of which may contain things that can be combined. */
2775 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
2778 /* It is possible to have a subexpression appear twice in the insn.
2779 Suppose that FROM is a register that appears within TO.
2780 Then, after that subexpression has been scanned once by `subst',
2781 the second time it is scanned, TO may be found. If we were
2782 to scan TO here, we would find FROM within it and create a
2783 self-referent rtl structure which is completely wrong. */
2784 if (COMBINE_RTX_EQUAL_P (x
, to
))
2787 len
= GET_RTX_LENGTH (code
);
2788 fmt
= GET_RTX_FORMAT (code
);
2790 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2791 set up to skip this common case. All other cases where we want to
2792 suppress replacing something inside a SET_SRC are handled via the
2795 && (GET_CODE (SET_DEST (x
)) == REG
2796 || GET_CODE (SET_DEST (x
)) == CC0
2797 || GET_CODE (SET_DEST (x
)) == PC
))
2800 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2802 op0_mode
= GET_MODE (XEXP (x
, 0));
2804 for (i
= 0; i
< len
; i
++)
2809 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2811 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
2813 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
2818 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0, unique_copy
);
2820 /* If this substitution failed, this whole thing fails. */
2821 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
2825 SUBST (XVECEXP (x
, i
, j
), new);
2828 else if (fmt
[i
] == 'e')
2830 if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
2832 /* In general, don't install a subreg involving two modes not
2833 tieable. It can worsen register allocation, and can even
2834 make invalid reload insns, since the reg inside may need to
2835 be copied from in the outside mode, and that may be invalid
2836 if it is an fp reg copied in integer mode.
2838 We allow two exceptions to this: It is valid if it is inside
2839 another SUBREG and the mode of that SUBREG and the mode of
2840 the inside of TO is tieable and it is valid if X is a SET
2841 that copies FROM to CC0. */
2842 if (GET_CODE (to
) == SUBREG
2843 && ! MODES_TIEABLE_P (GET_MODE (to
),
2844 GET_MODE (SUBREG_REG (to
)))
2845 && ! (code
== SUBREG
2846 && MODES_TIEABLE_P (GET_MODE (x
),
2847 GET_MODE (SUBREG_REG (to
))))
2849 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
2852 return gen_rtx (CLOBBER
, VOIDmode
, const0_rtx
);
2854 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
2858 /* If we are in a SET_DEST, suppress most cases unless we
2859 have gone inside a MEM, in which case we want to
2860 simplify the address. We assume here that things that
2861 are actually part of the destination have their inner
2862 parts in the first expression. This is true for SUBREG,
2863 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2864 things aside from REG and MEM that should appear in a
2866 new = subst (XEXP (x
, i
), from
, to
,
2868 && (code
== SUBREG
|| code
== STRICT_LOW_PART
2869 || code
== ZERO_EXTRACT
))
2871 && i
== 0), unique_copy
);
2873 /* If we found that we will have to reject this combination,
2874 indicate that by returning the CLOBBER ourselves, rather than
2875 an expression containing it. This will speed things up as
2876 well as prevent accidents where two CLOBBERs are considered
2877 to be equal, thus producing an incorrect simplification. */
2879 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
2882 SUBST (XEXP (x
, i
), new);
2886 /* Try to simplify X. If the simplification changed the code, it is likely
2887 that further simplification will help, so loop, but limit the number
2888 of repetitions that will be performed. */
2890 for (i
= 0; i
< 4; i
++)
2892 /* If X is sufficiently simple, don't bother trying to do anything
2894 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
2895 x
= simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
2897 if (GET_CODE (x
) == code
)
2900 code
= GET_CODE (x
);
2902 /* We no longer know the original mode of operand 0 since we
2903 have changed the form of X) */
2904 op0_mode
= VOIDmode
;
2910 /* Simplify X, a piece of RTL. We just operate on the expression at the
2911 outer level; call `subst' to simplify recursively. Return the new
2914 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
2915 will be the iteration even if an expression with a code different from
2916 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
2919 simplify_rtx (x
, op0_mode
, last
, in_dest
)
2921 enum machine_mode op0_mode
;
2925 enum rtx_code code
= GET_CODE (x
);
2926 enum machine_mode mode
= GET_MODE (x
);
2930 /* If this is a commutative operation, put a constant last and a complex
2931 expression first. We don't need to do this for comparisons here. */
2932 if (GET_RTX_CLASS (code
) == 'c'
2933 && ((CONSTANT_P (XEXP (x
, 0)) && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
2934 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == 'o'
2935 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')
2936 || (GET_CODE (XEXP (x
, 0)) == SUBREG
2937 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == 'o'
2938 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')))
2941 SUBST (XEXP (x
, 0), XEXP (x
, 1));
2942 SUBST (XEXP (x
, 1), temp
);
2945 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
2946 sign extension of a PLUS with a constant, reverse the order of the sign
2947 extension and the addition. Note that this not the same as the original
2948 code, but overflow is undefined for signed values. Also note that the
2949 PLUS will have been partially moved "inside" the sign-extension, so that
2950 the first operand of X will really look like:
2951 (ashiftrt (plus (ashift A C4) C5) C4).
2953 (plus (ashiftrt (ashift A C4) C2) C4)
2954 and replace the first operand of X with that expression. Later parts
2955 of this function may simplify the expression further.
2957 For example, if we start with (mult (sign_extend (plus A C1)) C2),
2958 we swap the SIGN_EXTEND and PLUS. Later code will apply the
2959 distributive law to produce (plus (mult (sign_extend X) C1) C3).
2961 We do this to simplify address expressions. */
2963 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
2964 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
2965 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
2966 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
2967 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
2968 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2969 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
2970 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
2971 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
2972 XEXP (XEXP (XEXP (x
, 0), 0), 1),
2973 XEXP (XEXP (x
, 0), 1))) != 0)
2976 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
2977 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
2978 INTVAL (XEXP (XEXP (x
, 0), 1)));
2980 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
2981 INTVAL (XEXP (XEXP (x
, 0), 1)));
2983 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
2986 /* If this is a simple operation applied to an IF_THEN_ELSE, try
2987 applying it to the arms of the IF_THEN_ELSE. This often simplifies
2988 things. Check for cases where both arms are testing the same
2991 Don't do anything if all operands are very simple. */
2993 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
2994 || GET_RTX_CLASS (code
) == '<')
2995 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
2996 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
2997 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
2999 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3000 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3001 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3003 || (GET_RTX_CLASS (code
) == '1'
3004 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3005 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3006 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3009 rtx cond
, true, false;
3011 cond
= if_then_else_cond (x
, &true, &false);
3014 rtx cop1
= const0_rtx
;
3015 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3017 /* Simplify the alternative arms; this may collapse the true and
3018 false arms to store-flag values. */
3019 true = subst (true, pc_rtx
, pc_rtx
, 0, 0);
3020 false = subst (false, pc_rtx
, pc_rtx
, 0, 0);
3022 /* Restarting if we generate a store-flag expression will cause
3023 us to loop. Just drop through in this case. */
3025 /* If the result values are STORE_FLAG_VALUE and zero, we can
3026 just make the comparison operation. */
3027 if (true == const_true_rtx
&& false == const0_rtx
)
3028 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3029 else if (true == const0_rtx
&& false == const_true_rtx
)
3030 x
= gen_binary (reverse_condition (cond_code
), mode
, cond
, cop1
);
3032 /* Likewise, we can make the negate of a comparison operation
3033 if the result values are - STORE_FLAG_VALUE and zero. */
3034 else if (GET_CODE (true) == CONST_INT
3035 && INTVAL (true) == - STORE_FLAG_VALUE
3036 && false == const0_rtx
)
3037 x
= gen_unary (NEG
, mode
, mode
,
3038 gen_binary (cond_code
, mode
, cond
, cop1
));
3039 else if (GET_CODE (false) == CONST_INT
3040 && INTVAL (false) == - STORE_FLAG_VALUE
3041 && true == const0_rtx
)
3042 x
= gen_unary (NEG
, mode
, mode
,
3043 gen_binary (reverse_condition (cond_code
),
3046 return gen_rtx (IF_THEN_ELSE
, mode
,
3047 gen_binary (cond_code
, VOIDmode
, cond
, cop1
),
3050 code
= GET_CODE (x
);
3051 op0_mode
= VOIDmode
;
3055 /* Try to fold this expression in case we have constants that weren't
3058 switch (GET_RTX_CLASS (code
))
3061 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3064 temp
= simplify_relational_operation (code
, op0_mode
,
3065 XEXP (x
, 0), XEXP (x
, 1));
3066 #ifdef FLOAT_STORE_FLAG_VALUE
3067 if (temp
!= 0 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3068 temp
= ((temp
== const0_rtx
) ? CONST0_RTX (GET_MODE (x
))
3069 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE
, GET_MODE (x
)));
3074 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3078 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3079 XEXP (x
, 1), XEXP (x
, 2));
3084 x
= temp
, code
= GET_CODE (temp
);
3086 /* First see if we can apply the inverse distributive law. */
3087 if (code
== PLUS
|| code
== MINUS
3088 || code
== AND
|| code
== IOR
|| code
== XOR
)
3090 x
= apply_distributive_law (x
);
3091 code
= GET_CODE (x
);
3094 /* If CODE is an associative operation not otherwise handled, see if we
3095 can associate some operands. This can win if they are constants or
3096 if they are logically related (i.e. (a & b) & a. */
3097 if ((code
== PLUS
|| code
== MINUS
3098 || code
== MULT
|| code
== AND
|| code
== IOR
|| code
== XOR
3099 || code
== DIV
|| code
== UDIV
3100 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3101 && INTEGRAL_MODE_P (mode
))
3103 if (GET_CODE (XEXP (x
, 0)) == code
)
3105 rtx other
= XEXP (XEXP (x
, 0), 0);
3106 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3107 rtx inner_op1
= XEXP (x
, 1);
3110 /* Make sure we pass the constant operand if any as the second
3111 one if this is a commutative operation. */
3112 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3114 rtx tem
= inner_op0
;
3115 inner_op0
= inner_op1
;
3118 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3119 : code
== DIV
? MULT
3120 : code
== UDIV
? MULT
3122 mode
, inner_op0
, inner_op1
);
3124 /* For commutative operations, try the other pair if that one
3126 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3128 other
= XEXP (XEXP (x
, 0), 1);
3129 inner
= simplify_binary_operation (code
, mode
,
3130 XEXP (XEXP (x
, 0), 0),
3135 return gen_binary (code
, mode
, other
, inner
);
3139 /* A little bit of algebraic simplification here. */
3143 /* Ensure that our address has any ASHIFTs converted to MULT in case
3144 address-recognizing predicates are called later. */
3145 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3146 SUBST (XEXP (x
, 0), temp
);
3150 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3151 is paradoxical. If we can't do that safely, then it becomes
3152 something nonsensical so that this combination won't take place. */
3154 if (GET_CODE (SUBREG_REG (x
)) == MEM
3155 && (GET_MODE_SIZE (mode
)
3156 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
3158 rtx inner
= SUBREG_REG (x
);
3159 int endian_offset
= 0;
3160 /* Don't change the mode of the MEM
3161 if that would change the meaning of the address. */
3162 if (MEM_VOLATILE_P (SUBREG_REG (x
))
3163 || mode_dependent_address_p (XEXP (inner
, 0)))
3164 return gen_rtx (CLOBBER
, mode
, const0_rtx
);
3166 if (BYTES_BIG_ENDIAN
)
3168 if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
3169 endian_offset
+= UNITS_PER_WORD
- GET_MODE_SIZE (mode
);
3170 if (GET_MODE_SIZE (GET_MODE (inner
)) < UNITS_PER_WORD
)
3171 endian_offset
-= (UNITS_PER_WORD
3172 - GET_MODE_SIZE (GET_MODE (inner
)));
3174 /* Note if the plus_constant doesn't make a valid address
3175 then this combination won't be accepted. */
3176 x
= gen_rtx (MEM
, mode
,
3177 plus_constant (XEXP (inner
, 0),
3178 (SUBREG_WORD (x
) * UNITS_PER_WORD
3180 MEM_VOLATILE_P (x
) = MEM_VOLATILE_P (inner
);
3181 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (inner
);
3182 MEM_IN_STRUCT_P (x
) = MEM_IN_STRUCT_P (inner
);
3186 /* If we are in a SET_DEST, these other cases can't apply. */
3190 /* Changing mode twice with SUBREG => just change it once,
3191 or not at all if changing back to starting mode. */
3192 if (GET_CODE (SUBREG_REG (x
)) == SUBREG
)
3194 if (mode
== GET_MODE (SUBREG_REG (SUBREG_REG (x
)))
3195 && SUBREG_WORD (x
) == 0 && SUBREG_WORD (SUBREG_REG (x
)) == 0)
3196 return SUBREG_REG (SUBREG_REG (x
));
3198 SUBST_INT (SUBREG_WORD (x
),
3199 SUBREG_WORD (x
) + SUBREG_WORD (SUBREG_REG (x
)));
3200 SUBST (SUBREG_REG (x
), SUBREG_REG (SUBREG_REG (x
)));
3203 /* SUBREG of a hard register => just change the register number
3204 and/or mode. If the hard register is not valid in that mode,
3205 suppress this combination. If the hard register is the stack,
3206 frame, or argument pointer, leave this as a SUBREG. */
3208 if (GET_CODE (SUBREG_REG (x
)) == REG
3209 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
3210 && REGNO (SUBREG_REG (x
)) != FRAME_POINTER_REGNUM
3211 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3212 && REGNO (SUBREG_REG (x
)) != HARD_FRAME_POINTER_REGNUM
3214 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3215 && REGNO (SUBREG_REG (x
)) != ARG_POINTER_REGNUM
3217 && REGNO (SUBREG_REG (x
)) != STACK_POINTER_REGNUM
)
3219 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
),
3221 return gen_rtx (REG
, mode
,
3222 REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
));
3224 return gen_rtx (CLOBBER
, mode
, const0_rtx
);
3227 /* For a constant, try to pick up the part we want. Handle a full
3228 word and low-order part. Only do this if we are narrowing
3229 the constant; if it is being widened, we have no idea what
3230 the extra bits will have been set to. */
3232 if (CONSTANT_P (SUBREG_REG (x
)) && op0_mode
!= VOIDmode
3233 && GET_MODE_SIZE (mode
) == UNITS_PER_WORD
3234 && GET_MODE_SIZE (op0_mode
) < UNITS_PER_WORD
3235 && GET_MODE_CLASS (mode
) == MODE_INT
)
3237 temp
= operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
),
3243 /* If we want a subreg of a constant, at offset 0,
3244 take the low bits. On a little-endian machine, that's
3245 always valid. On a big-endian machine, it's valid
3246 only if the constant's mode fits in one word. */
3247 if (CONSTANT_P (SUBREG_REG (x
)) && subreg_lowpart_p (x
)
3248 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (op0_mode
)
3249 && (! WORDS_BIG_ENDIAN
3250 || GET_MODE_BITSIZE (op0_mode
) <= BITS_PER_WORD
))
3251 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3253 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3254 since we are saying that the high bits don't matter. */
3255 if (CONSTANT_P (SUBREG_REG (x
)) && GET_MODE (SUBREG_REG (x
)) == VOIDmode
3256 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (op0_mode
))
3257 return SUBREG_REG (x
);
3259 /* Note that we cannot do any narrowing for non-constants since
3260 we might have been counting on using the fact that some bits were
3261 zero. We now do this in the SET. */
3266 /* (not (plus X -1)) can become (neg X). */
3267 if (GET_CODE (XEXP (x
, 0)) == PLUS
3268 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3269 return gen_rtx_combine (NEG
, mode
, XEXP (XEXP (x
, 0), 0));
3271 /* Similarly, (not (neg X)) is (plus X -1). */
3272 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3273 return gen_rtx_combine (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
3276 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3277 if (GET_CODE (XEXP (x
, 0)) == XOR
3278 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3279 && (temp
= simplify_unary_operation (NOT
, mode
,
3280 XEXP (XEXP (x
, 0), 1),
3282 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3284 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3285 other than 1, but that is not valid. We could do a similar
3286 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3287 but this doesn't seem common enough to bother with. */
3288 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3289 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3290 return gen_rtx (ROTATE
, mode
, gen_unary (NOT
, mode
, mode
, const1_rtx
),
3291 XEXP (XEXP (x
, 0), 1));
3293 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3294 && subreg_lowpart_p (XEXP (x
, 0))
3295 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3296 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3297 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3298 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3300 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3302 x
= gen_rtx (ROTATE
, inner_mode
,
3303 gen_unary (NOT
, inner_mode
, inner_mode
, const1_rtx
),
3304 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3305 return gen_lowpart_for_combine (mode
, x
);
3308 #if STORE_FLAG_VALUE == -1
3309 /* (not (comparison foo bar)) can be done by reversing the comparison
3311 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3312 && reversible_comparison_p (XEXP (x
, 0)))
3313 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x
, 0))),
3314 mode
, XEXP (XEXP (x
, 0), 0),
3315 XEXP (XEXP (x
, 0), 1));
3317 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3318 is (lt foo (const_int 0)), so we can perform the above
3321 if (XEXP (x
, 1) == const1_rtx
3322 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3323 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3324 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3325 return gen_rtx_combine (GE
, mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3328 /* Apply De Morgan's laws to reduce number of patterns for machines
3329 with negating logical insns (and-not, nand, etc.). If result has
3330 only one NOT, put it first, since that is how the patterns are
3333 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3335 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3337 if (GET_CODE (in1
) == NOT
)
3338 in1
= XEXP (in1
, 0);
3340 in1
= gen_rtx_combine (NOT
, GET_MODE (in1
), in1
);
3342 if (GET_CODE (in2
) == NOT
)
3343 in2
= XEXP (in2
, 0);
3344 else if (GET_CODE (in2
) == CONST_INT
3345 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
3346 in2
= GEN_INT (GET_MODE_MASK (mode
) & ~ INTVAL (in2
));
3348 in2
= gen_rtx_combine (NOT
, GET_MODE (in2
), in2
);
3350 if (GET_CODE (in2
) == NOT
)
3353 in2
= in1
; in1
= tem
;
3356 return gen_rtx_combine (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3362 /* (neg (plus X 1)) can become (not X). */
3363 if (GET_CODE (XEXP (x
, 0)) == PLUS
3364 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3365 return gen_rtx_combine (NOT
, mode
, XEXP (XEXP (x
, 0), 0));
3367 /* Similarly, (neg (not X)) is (plus X 1). */
3368 if (GET_CODE (XEXP (x
, 0)) == NOT
)
3369 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
3371 /* (neg (minus X Y)) can become (minus Y X). */
3372 if (GET_CODE (XEXP (x
, 0)) == MINUS
3373 && (! FLOAT_MODE_P (mode
)
3374 /* x-y != -(y-x) with IEEE floating point. */
3375 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3377 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
3378 XEXP (XEXP (x
, 0), 0));
3380 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3381 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
3382 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3383 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3385 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3386 if we can then eliminate the NEG (e.g.,
3387 if the operand is a constant). */
3389 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
3391 temp
= simplify_unary_operation (NEG
, mode
,
3392 XEXP (XEXP (x
, 0), 0), mode
);
3395 SUBST (XEXP (XEXP (x
, 0), 0), temp
);
3400 temp
= expand_compound_operation (XEXP (x
, 0));
3402 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3403 replaced by (lshiftrt X C). This will convert
3404 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3406 if (GET_CODE (temp
) == ASHIFTRT
3407 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3408 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3409 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3410 INTVAL (XEXP (temp
, 1)));
3412 /* If X has only a single bit that might be nonzero, say, bit I, convert
3413 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3414 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3415 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3416 or a SUBREG of one since we'd be making the expression more
3417 complex if it was just a register. */
3419 if (GET_CODE (temp
) != REG
3420 && ! (GET_CODE (temp
) == SUBREG
3421 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3422 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3424 rtx temp1
= simplify_shift_const
3425 (NULL_RTX
, ASHIFTRT
, mode
,
3426 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3427 GET_MODE_BITSIZE (mode
) - 1 - i
),
3428 GET_MODE_BITSIZE (mode
) - 1 - i
);
3430 /* If all we did was surround TEMP with the two shifts, we
3431 haven't improved anything, so don't use it. Otherwise,
3432 we are better off with TEMP1. */
3433 if (GET_CODE (temp1
) != ASHIFTRT
3434 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3435 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3440 case FLOAT_TRUNCATE
:
3441 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3442 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
3443 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3444 return XEXP (XEXP (x
, 0), 0);
3446 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3447 (OP:SF foo:SF) if OP is NEG or ABS. */
3448 if ((GET_CODE (XEXP (x
, 0)) == ABS
3449 || GET_CODE (XEXP (x
, 0)) == NEG
)
3450 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
3451 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3452 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
3453 XEXP (XEXP (XEXP (x
, 0), 0), 0));
3455 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3456 is (float_truncate:SF x). */
3457 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3458 && subreg_lowpart_p (XEXP (x
, 0))
3459 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
3460 return SUBREG_REG (XEXP (x
, 0));
3465 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3466 using cc0, in which case we want to leave it as a COMPARE
3467 so we can distinguish it from a register-register-copy. */
3468 if (XEXP (x
, 1) == const0_rtx
)
3471 /* In IEEE floating point, x-0 is not the same as x. */
3472 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3473 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
3475 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
3481 /* (const (const X)) can become (const X). Do it this way rather than
3482 returning the inner CONST since CONST can be shared with a
3484 if (GET_CODE (XEXP (x
, 0)) == CONST
)
3485 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3490 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3491 can add in an offset. find_split_point will split this address up
3492 again if it doesn't match. */
3493 if (GET_CODE (XEXP (x
, 0)) == HIGH
3494 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
3500 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3501 outermost. That's because that's the way indexed addresses are
3502 supposed to appear. This code used to check many more cases, but
3503 they are now checked elsewhere. */
3504 if (GET_CODE (XEXP (x
, 0)) == PLUS
3505 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
3506 return gen_binary (PLUS
, mode
,
3507 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
3509 XEXP (XEXP (x
, 0), 1));
3511 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3512 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3513 bit-field and can be replaced by either a sign_extend or a
3514 sign_extract. The `and' may be a zero_extend. */
3515 if (GET_CODE (XEXP (x
, 0)) == XOR
3516 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3517 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3518 && INTVAL (XEXP (x
, 1)) == - INTVAL (XEXP (XEXP (x
, 0), 1))
3519 && (i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
3520 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3521 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
3522 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3523 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
3524 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
3525 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
3526 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
3528 return simplify_shift_const
3529 (NULL_RTX
, ASHIFTRT
, mode
,
3530 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3531 XEXP (XEXP (XEXP (x
, 0), 0), 0),
3532 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
3533 GET_MODE_BITSIZE (mode
) - (i
+ 1));
3535 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3536 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3537 is 1. This produces better code than the alternative immediately
3539 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3540 && reversible_comparison_p (XEXP (x
, 0))
3541 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
3542 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
)))
3544 gen_unary (NEG
, mode
, mode
,
3545 gen_binary (reverse_condition (GET_CODE (XEXP (x
, 0))),
3546 mode
, XEXP (XEXP (x
, 0), 0),
3547 XEXP (XEXP (x
, 0), 1)));
3549 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3550 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3551 the bitsize of the mode - 1. This allows simplification of
3552 "a = (b & 8) == 0;" */
3553 if (XEXP (x
, 1) == constm1_rtx
3554 && GET_CODE (XEXP (x
, 0)) != REG
3555 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
3556 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
3557 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
3558 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
3559 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3560 gen_rtx_combine (XOR
, mode
,
3561 XEXP (x
, 0), const1_rtx
),
3562 GET_MODE_BITSIZE (mode
) - 1),
3563 GET_MODE_BITSIZE (mode
) - 1);
3565 /* If we are adding two things that have no bits in common, convert
3566 the addition into an IOR. This will often be further simplified,
3567 for example in cases like ((a & 1) + (a & 2)), which can
3570 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3571 && (nonzero_bits (XEXP (x
, 0), mode
)
3572 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
3573 return gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3577 #if STORE_FLAG_VALUE == 1
3578 /* (minus 1 (comparison foo bar)) can be done by reversing the comparison
3580 if (XEXP (x
, 0) == const1_rtx
3581 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
3582 && reversible_comparison_p (XEXP (x
, 1)))
3583 return gen_binary (reverse_condition (GET_CODE (XEXP (x
, 1))),
3584 mode
, XEXP (XEXP (x
, 1), 0),
3585 XEXP (XEXP (x
, 1), 1));
3588 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3589 (and <foo> (const_int pow2-1)) */
3590 if (GET_CODE (XEXP (x
, 1)) == AND
3591 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
3592 && exact_log2 (- INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
3593 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3594 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
3595 - INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
3597 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3599 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
3600 return gen_binary (MINUS
, mode
,
3601 gen_binary (MINUS
, mode
, XEXP (x
, 0),
3602 XEXP (XEXP (x
, 1), 0)),
3603 XEXP (XEXP (x
, 1), 1));
3607 /* If we have (mult (plus A B) C), apply the distributive law and then
3608 the inverse distributive law to see if things simplify. This
3609 occurs mostly in addresses, often when unrolling loops. */
3611 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
3613 x
= apply_distributive_law
3614 (gen_binary (PLUS
, mode
,
3615 gen_binary (MULT
, mode
,
3616 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
3617 gen_binary (MULT
, mode
,
3618 XEXP (XEXP (x
, 0), 1), XEXP (x
, 1))));
3620 if (GET_CODE (x
) != MULT
)
3626 /* If this is a divide by a power of two, treat it as a shift if
3627 its first operand is a shift. */
3628 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
3629 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
3630 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
3631 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3632 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3633 || GET_CODE (XEXP (x
, 0)) == ROTATE
3634 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
3635 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
3639 case GT
: case GTU
: case GE
: case GEU
:
3640 case LT
: case LTU
: case LE
: case LEU
:
3641 /* If the first operand is a condition code, we can't do anything
3643 if (GET_CODE (XEXP (x
, 0)) == COMPARE
3644 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
3646 && XEXP (x
, 0) != cc0_rtx
3650 rtx op0
= XEXP (x
, 0);
3651 rtx op1
= XEXP (x
, 1);
3652 enum rtx_code new_code
;
3654 if (GET_CODE (op0
) == COMPARE
)
3655 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
3657 /* Simplify our comparison, if possible. */
3658 new_code
= simplify_comparison (code
, &op0
, &op1
);
3660 #if STORE_FLAG_VALUE == 1
3661 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3662 if only the low-order bit is possibly nonzero in X (such as when
3663 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
3664 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
3665 known to be either 0 or -1, NE becomes a NEG and EQ becomes
3668 Remove any ZERO_EXTRACT we made when thinking this was a
3669 comparison. It may now be simpler to use, e.g., an AND. If a
3670 ZERO_EXTRACT is indeed appropriate, it will be placed back by
3671 the call to make_compound_operation in the SET case. */
3673 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3674 && op1
== const0_rtx
3675 && nonzero_bits (op0
, mode
) == 1)
3676 return gen_lowpart_for_combine (mode
,
3677 expand_compound_operation (op0
));
3679 else if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3680 && op1
== const0_rtx
3681 && (num_sign_bit_copies (op0
, mode
)
3682 == GET_MODE_BITSIZE (mode
)))
3684 op0
= expand_compound_operation (op0
);
3685 return gen_unary (NEG
, mode
, mode
,
3686 gen_lowpart_for_combine (mode
, op0
));
3689 else if (new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
3690 && op1
== const0_rtx
3691 && nonzero_bits (op0
, mode
) == 1)
3693 op0
= expand_compound_operation (op0
);
3694 return gen_binary (XOR
, mode
,
3695 gen_lowpart_for_combine (mode
, op0
),
3699 else if (new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
3700 && op1
== const0_rtx
3701 && (num_sign_bit_copies (op0
, mode
)
3702 == GET_MODE_BITSIZE (mode
)))
3704 op0
= expand_compound_operation (op0
);
3705 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
3709 #if STORE_FLAG_VALUE == -1
3710 /* If STORE_FLAG_VALUE is -1, we have cases similar to
3712 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3713 && op1
== const0_rtx
3714 && (num_sign_bit_copies (op0
, mode
)
3715 == GET_MODE_BITSIZE (mode
)))
3716 return gen_lowpart_for_combine (mode
,
3717 expand_compound_operation (op0
));
3719 else if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3720 && op1
== const0_rtx
3721 && nonzero_bits (op0
, mode
) == 1)
3723 op0
= expand_compound_operation (op0
);
3724 return gen_unary (NEG
, mode
, mode
,
3725 gen_lowpart_for_combine (mode
, op0
));
3728 else if (new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
3729 && op1
== const0_rtx
3730 && (num_sign_bit_copies (op0
, mode
)
3731 == GET_MODE_BITSIZE (mode
)))
3733 op0
= expand_compound_operation (op0
);
3734 return gen_unary (NOT
, mode
, mode
,
3735 gen_lowpart_for_combine (mode
, op0
));
3738 /* If X is 0/1, (eq X 0) is X-1. */
3739 else if (new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
3740 && op1
== const0_rtx
3741 && nonzero_bits (op0
, mode
) == 1)
3743 op0
= expand_compound_operation (op0
);
3744 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
3748 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3749 one bit that might be nonzero, we can convert (ne x 0) to
3750 (ashift x c) where C puts the bit in the sign bit. Remove any
3751 AND with STORE_FLAG_VALUE when we are done, since we are only
3752 going to test the sign bit. */
3753 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3754 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3755 && (STORE_FLAG_VALUE
3756 == (HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
3757 && op1
== const0_rtx
3758 && mode
== GET_MODE (op0
)
3759 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
3761 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3762 expand_compound_operation (op0
),
3763 GET_MODE_BITSIZE (mode
) - 1 - i
);
3764 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
3770 /* If the code changed, return a whole new comparison. */
3771 if (new_code
!= code
)
3772 return gen_rtx_combine (new_code
, mode
, op0
, op1
);
3774 /* Otherwise, keep this operation, but maybe change its operands.
3775 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3776 SUBST (XEXP (x
, 0), op0
);
3777 SUBST (XEXP (x
, 1), op1
);
3782 return simplify_if_then_else (x
);
3788 /* If we are processing SET_DEST, we are done. */
3792 return expand_compound_operation (x
);
3795 return simplify_set (x
);
3800 return simplify_logical (x
, last
);
3803 /* (abs (neg <foo>)) -> (abs <foo>) */
3804 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3805 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3807 /* If operand is something known to be positive, ignore the ABS. */
3808 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
3809 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
3810 <= HOST_BITS_PER_WIDE_INT
)
3811 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
3812 & ((HOST_WIDE_INT
) 1
3813 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
3818 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
3819 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
3820 return gen_rtx_combine (NEG
, mode
, XEXP (x
, 0));
3825 /* (ffs (*_extend <X>)) = (ffs <X>) */
3826 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3827 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3828 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3832 /* (float (sign_extend <X>)) = (float <X>). */
3833 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
3834 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3842 /* If this is a shift by a constant amount, simplify it. */
3843 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3844 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
3845 INTVAL (XEXP (x
, 1)));
3847 #ifdef SHIFT_COUNT_TRUNCATED
3848 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
3850 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
3852 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
3863 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
3866 simplify_if_then_else (x
)
3869 enum machine_mode mode
= GET_MODE (x
);
3870 rtx cond
= XEXP (x
, 0);
3871 rtx
true = XEXP (x
, 1);
3872 rtx
false = XEXP (x
, 2);
3873 enum rtx_code true_code
= GET_CODE (cond
);
3874 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
3878 /* Simplify storing of the truth value. */
3879 if (comparison_p
&& true == const_true_rtx
&& false == const0_rtx
)
3880 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
3882 /* Also when the truth value has to be reversed. */
3883 if (comparison_p
&& reversible_comparison_p (cond
)
3884 && true == const0_rtx
&& false == const_true_rtx
)
3885 return gen_binary (reverse_condition (true_code
),
3886 mode
, XEXP (cond
, 0), XEXP (cond
, 1));
3888 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
3889 in it is being compared against certain values. Get the true and false
3890 comparisons and see if that says anything about the value of each arm. */
3892 if (comparison_p
&& reversible_comparison_p (cond
)
3893 && GET_CODE (XEXP (cond
, 0)) == REG
)
3896 rtx from
= XEXP (cond
, 0);
3897 enum rtx_code false_code
= reverse_condition (true_code
);
3898 rtx true_val
= XEXP (cond
, 1);
3899 rtx false_val
= true_val
;
3902 /* If FALSE_CODE is EQ, swap the codes and arms. */
3904 if (false_code
== EQ
)
3906 swapped
= 1, true_code
= EQ
, false_code
= NE
;
3907 temp
= true, true = false, false = temp
;
3910 /* If we are comparing against zero and the expression being tested has
3911 only a single bit that might be nonzero, that is its value when it is
3912 not equal to zero. Similarly if it is known to be -1 or 0. */
3914 if (true_code
== EQ
&& true_val
== const0_rtx
3915 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
3916 false_code
= EQ
, false_val
= GEN_INT (nzb
);
3917 else if (true_code
== EQ
&& true_val
== const0_rtx
3918 && (num_sign_bit_copies (from
, GET_MODE (from
))
3919 == GET_MODE_BITSIZE (GET_MODE (from
))))
3920 false_code
= EQ
, false_val
= constm1_rtx
;
3922 /* Now simplify an arm if we know the value of the register in the
3923 branch and it is used in the arm. Be careful due to the potential
3924 of locally-shared RTL. */
3926 if (reg_mentioned_p (from
, true))
3927 true = subst (known_cond (copy_rtx (true), true_code
, from
, true_val
),
3928 pc_rtx
, pc_rtx
, 0, 0);
3929 if (reg_mentioned_p (from
, false))
3930 false = subst (known_cond (copy_rtx (false), false_code
,
3932 pc_rtx
, pc_rtx
, 0, 0);
3934 SUBST (XEXP (x
, 1), swapped
? false : true);
3935 SUBST (XEXP (x
, 2), swapped
? true : false);
3937 true = XEXP (x
, 1), false = XEXP (x
, 2), true_code
= GET_CODE (cond
);
3940 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3941 reversed, do so to avoid needing two sets of patterns for
3942 subtract-and-branch insns. Similarly if we have a constant in the true
3943 arm, the false arm is the same as the first operand of the comparison, or
3944 the false arm is more complicated than the true arm. */
3946 if (comparison_p
&& reversible_comparison_p (cond
)
3948 || (CONSTANT_P (true)
3949 && GET_CODE (false) != CONST_INT
&& false != pc_rtx
)
3950 || true == const0_rtx
3951 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
3952 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
3953 || (GET_CODE (true) == SUBREG
3954 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
3955 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
3956 || reg_mentioned_p (true, false)
3957 || rtx_equal_p (false, XEXP (cond
, 0))))
3959 true_code
= reverse_condition (true_code
);
3961 gen_binary (true_code
, GET_MODE (cond
), XEXP (cond
, 0),
3964 SUBST (XEXP (x
, 1), false);
3965 SUBST (XEXP (x
, 2), true);
3967 temp
= true, true = false, false = temp
, cond
= XEXP (x
, 0);
3970 /* If the two arms are identical, we don't need the comparison. */
3972 if (rtx_equal_p (true, false) && ! side_effects_p (cond
))
3975 /* Look for cases where we have (abs x) or (neg (abs X)). */
3977 if (GET_MODE_CLASS (mode
) == MODE_INT
3978 && GET_CODE (false) == NEG
3979 && rtx_equal_p (true, XEXP (false, 0))
3981 && rtx_equal_p (true, XEXP (cond
, 0))
3982 && ! side_effects_p (true))
3987 return gen_unary (ABS
, mode
, mode
, true);
3990 return gen_unary (NEG
, mode
, mode
, gen_unary (ABS
, mode
, mode
, true));
3993 /* Look for MIN or MAX. */
3995 if ((! FLOAT_MODE_P (mode
) | flag_fast_math
)
3997 && rtx_equal_p (XEXP (cond
, 0), true)
3998 && rtx_equal_p (XEXP (cond
, 1), false)
3999 && ! side_effects_p (cond
))
4004 return gen_binary (SMAX
, mode
, true, false);
4007 return gen_binary (SMIN
, mode
, true, false);
4010 return gen_binary (UMAX
, mode
, true, false);
4013 return gen_binary (UMIN
, mode
, true, false);
4016 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
4018 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4019 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4020 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4021 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4022 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4023 neither of the above, but it isn't worth checking for. */
4025 if (comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4027 rtx t
= make_compound_operation (true, SET
);
4028 rtx f
= make_compound_operation (false, SET
);
4029 rtx cond_op0
= XEXP (cond
, 0);
4030 rtx cond_op1
= XEXP (cond
, 1);
4031 enum rtx_code op
, extend_op
= NIL
;
4032 enum machine_mode m
= mode
;
4035 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4036 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4037 || GET_CODE (t
) == ASHIFT
4038 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4039 && rtx_equal_p (XEXP (t
, 0), f
))
4040 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4042 /* If an identity-zero op is commutative, check whether there
4043 would be a match if we swapped the operands. */
4044 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4045 || GET_CODE (t
) == XOR
)
4046 && rtx_equal_p (XEXP (t
, 1), f
))
4047 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4048 else if (GET_CODE (t
) == SIGN_EXTEND
4049 && (GET_CODE (XEXP (t
, 0)) == PLUS
4050 || GET_CODE (XEXP (t
, 0)) == MINUS
4051 || GET_CODE (XEXP (t
, 0)) == IOR
4052 || GET_CODE (XEXP (t
, 0)) == XOR
4053 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4054 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4055 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4056 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4057 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4058 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4059 && (num_sign_bit_copies (f
, GET_MODE (f
))
4060 > (GET_MODE_BITSIZE (mode
)
4061 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4063 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4064 extend_op
= SIGN_EXTEND
;
4065 m
= GET_MODE (XEXP (t
, 0));
4067 else if (GET_CODE (t
) == SIGN_EXTEND
4068 && (GET_CODE (XEXP (t
, 0)) == PLUS
4069 || GET_CODE (XEXP (t
, 0)) == IOR
4070 || GET_CODE (XEXP (t
, 0)) == XOR
)
4071 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4072 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4073 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4074 && (num_sign_bit_copies (f
, GET_MODE (f
))
4075 > (GET_MODE_BITSIZE (mode
)
4076 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4078 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4079 extend_op
= SIGN_EXTEND
;
4080 m
= GET_MODE (XEXP (t
, 0));
4082 else if (GET_CODE (t
) == ZERO_EXTEND
4083 && (GET_CODE (XEXP (t
, 0)) == PLUS
4084 || GET_CODE (XEXP (t
, 0)) == MINUS
4085 || GET_CODE (XEXP (t
, 0)) == IOR
4086 || GET_CODE (XEXP (t
, 0)) == XOR
4087 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4088 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4089 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4090 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4091 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4092 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4093 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4094 && ((nonzero_bits (f
, GET_MODE (f
))
4095 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4098 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4099 extend_op
= ZERO_EXTEND
;
4100 m
= GET_MODE (XEXP (t
, 0));
4102 else if (GET_CODE (t
) == ZERO_EXTEND
4103 && (GET_CODE (XEXP (t
, 0)) == PLUS
4104 || GET_CODE (XEXP (t
, 0)) == IOR
4105 || GET_CODE (XEXP (t
, 0)) == XOR
)
4106 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4107 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4108 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4109 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4110 && ((nonzero_bits (f
, GET_MODE (f
))
4111 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4114 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4115 extend_op
= ZERO_EXTEND
;
4116 m
= GET_MODE (XEXP (t
, 0));
4121 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4122 pc_rtx
, pc_rtx
, 0, 0);
4123 temp
= gen_binary (MULT
, m
, temp
,
4124 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4125 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4126 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4128 if (extend_op
!= NIL
)
4129 temp
= gen_unary (extend_op
, mode
, m
, temp
);
4136 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4137 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4138 negation of a single bit, we can convert this operation to a shift. We
4139 can actually do this more generally, but it doesn't seem worth it. */
4141 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4142 && false == const0_rtx
&& GET_CODE (true) == CONST_INT
4143 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4144 && (i
= exact_log2 (INTVAL (true))) >= 0)
4145 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4146 == GET_MODE_BITSIZE (mode
))
4147 && (i
= exact_log2 (- INTVAL (true))) >= 0)))
4149 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4150 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4155 /* Simplify X, a SET expression. Return the new expression. */
4161 rtx src
= SET_SRC (x
);
4162 rtx dest
= SET_DEST (x
);
4163 enum machine_mode mode
4164 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4168 /* (set (pc) (return)) gets written as (return). */
4169 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4172 /* Now that we know for sure which bits of SRC we are using, see if we can
4173 simplify the expression for the object knowing that we only need the
4176 if (GET_MODE_CLASS (mode
) == MODE_INT
)
4177 src
= force_to_mode (src
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
4179 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4180 the comparison result and try to simplify it unless we already have used
4181 undobuf.other_insn. */
4182 if ((GET_CODE (src
) == COMPARE
4187 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4188 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4189 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4190 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4192 enum rtx_code old_code
= GET_CODE (*cc_use
);
4193 enum rtx_code new_code
;
4195 int other_changed
= 0;
4196 enum machine_mode compare_mode
= GET_MODE (dest
);
4198 if (GET_CODE (src
) == COMPARE
)
4199 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4201 op0
= src
, op1
= const0_rtx
;
4203 /* Simplify our comparison, if possible. */
4204 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
4206 #ifdef EXTRA_CC_MODES
4207 /* If this machine has CC modes other than CCmode, check to see if we
4208 need to use a different CC mode here. */
4209 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
4210 #endif /* EXTRA_CC_MODES */
4212 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4213 /* If the mode changed, we have to change SET_DEST, the mode in the
4214 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4215 a hard register, just build new versions with the proper mode. If it
4216 is a pseudo, we lose unless it is only time we set the pseudo, in
4217 which case we can safely change its mode. */
4218 if (compare_mode
!= GET_MODE (dest
))
4220 int regno
= REGNO (dest
);
4221 rtx new_dest
= gen_rtx (REG
, compare_mode
, regno
);
4223 if (regno
< FIRST_PSEUDO_REGISTER
4224 || (reg_n_sets
[regno
] == 1 && ! REG_USERVAR_P (dest
)))
4226 if (regno
>= FIRST_PSEUDO_REGISTER
)
4227 SUBST (regno_reg_rtx
[regno
], new_dest
);
4229 SUBST (SET_DEST (x
), new_dest
);
4230 SUBST (XEXP (*cc_use
, 0), new_dest
);
4238 /* If the code changed, we have to build a new comparison in
4239 undobuf.other_insn. */
4240 if (new_code
!= old_code
)
4242 unsigned HOST_WIDE_INT mask
;
4244 SUBST (*cc_use
, gen_rtx_combine (new_code
, GET_MODE (*cc_use
),
4247 /* If the only change we made was to change an EQ into an NE or
4248 vice versa, OP0 has only one bit that might be nonzero, and OP1
4249 is zero, check if changing the user of the condition code will
4250 produce a valid insn. If it won't, we can keep the original code
4251 in that insn by surrounding our operation with an XOR. */
4253 if (((old_code
== NE
&& new_code
== EQ
)
4254 || (old_code
== EQ
&& new_code
== NE
))
4255 && ! other_changed
&& op1
== const0_rtx
4256 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
4257 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
4259 rtx pat
= PATTERN (other_insn
), note
= 0;
4261 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
4262 && ! check_asm_operands (pat
)))
4264 PUT_CODE (*cc_use
, old_code
);
4267 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
4275 undobuf
.other_insn
= other_insn
;
4278 /* If we are now comparing against zero, change our source if
4279 needed. If we do not use cc0, we always have a COMPARE. */
4280 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
4282 SUBST (SET_SRC (x
), op0
);
4288 /* Otherwise, if we didn't previously have a COMPARE in the
4289 correct mode, we need one. */
4290 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
4293 gen_rtx_combine (COMPARE
, compare_mode
, op0
, op1
));
4298 /* Otherwise, update the COMPARE if needed. */
4299 SUBST (XEXP (src
, 0), op0
);
4300 SUBST (XEXP (src
, 1), op1
);
4305 /* Get SET_SRC in a form where we have placed back any
4306 compound expressions. Then do the checks below. */
4307 src
= make_compound_operation (src
, SET
);
4308 SUBST (SET_SRC (x
), src
);
4311 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4312 and X being a REG or (subreg (reg)), we may be able to convert this to
4313 (set (subreg:m2 x) (op)).
4315 We can always do this if M1 is narrower than M2 because that means that
4316 we only care about the low bits of the result.
4318 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4319 perform a narrower operation that requested since the high-order bits will
4320 be undefined. On machine where it is defined, this transformation is safe
4321 as long as M1 and M2 have the same number of words. */
4323 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
4324 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
4325 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
4327 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
4328 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
4329 #ifndef WORD_REGISTER_OPERATIONS
4330 && (GET_MODE_SIZE (GET_MODE (src
))
4331 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
4333 && (GET_CODE (dest
) == REG
4334 || (GET_CODE (dest
) == SUBREG
4335 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
4337 SUBST (SET_DEST (x
),
4338 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
4340 SUBST (SET_SRC (x
), SUBREG_REG (src
));
4342 src
= SET_SRC (x
), dest
= SET_DEST (x
);
4345 #ifdef LOAD_EXTEND_OP
4346 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4347 would require a paradoxical subreg. Replace the subreg with a
4348 zero_extend to avoid the reload that would otherwise be required. */
4350 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
4351 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
4352 && SUBREG_WORD (src
) == 0
4353 && (GET_MODE_SIZE (GET_MODE (src
))
4354 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
4355 && GET_CODE (SUBREG_REG (src
)) == MEM
)
4358 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
4359 GET_MODE (src
), XEXP (src
, 0)));
4365 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4366 are comparing an item known to be 0 or -1 against 0, use a logical
4367 operation instead. Check for one of the arms being an IOR of the other
4368 arm with some value. We compute three terms to be IOR'ed together. In
4369 practice, at most two will be nonzero. Then we do the IOR's. */
4371 if (GET_CODE (dest
) != PC
4372 && GET_CODE (src
) == IF_THEN_ELSE
4373 #ifdef HAVE_conditional_move
4374 && ! HAVE_conditional_move
4376 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
4377 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
4378 && XEXP (XEXP (src
, 0), 1) == const0_rtx
4379 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
4380 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
4381 GET_MODE (XEXP (XEXP (src
, 0), 0)))
4382 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
4383 && ! side_effects_p (src
))
4385 rtx
true = (GET_CODE (XEXP (src
, 0)) == NE
4386 ? XEXP (src
, 1) : XEXP (src
, 2));
4387 rtx
false = (GET_CODE (XEXP (src
, 0)) == NE
4388 ? XEXP (src
, 2) : XEXP (src
, 1));
4389 rtx term1
= const0_rtx
, term2
, term3
;
4391 if (GET_CODE (true) == IOR
&& rtx_equal_p (XEXP (true, 0), false))
4392 term1
= false, true = XEXP (true, 1), false = const0_rtx
;
4393 else if (GET_CODE (true) == IOR
4394 && rtx_equal_p (XEXP (true, 1), false))
4395 term1
= false, true = XEXP (true, 0), false = const0_rtx
;
4396 else if (GET_CODE (false) == IOR
4397 && rtx_equal_p (XEXP (false, 0), true))
4398 term1
= true, false = XEXP (false, 1), true = const0_rtx
;
4399 else if (GET_CODE (false) == IOR
4400 && rtx_equal_p (XEXP (false, 1), true))
4401 term1
= true, false = XEXP (false, 0), true = const0_rtx
;
4403 term2
= gen_binary (AND
, GET_MODE (src
), XEXP (XEXP (src
, 0), 0), true);
4404 term3
= gen_binary (AND
, GET_MODE (src
),
4405 gen_unary (NOT
, GET_MODE (src
), GET_MODE (src
),
4406 XEXP (XEXP (src
, 0), 0)),
4410 gen_binary (IOR
, GET_MODE (src
),
4411 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
4417 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4418 whole thing fail. */
4419 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
4421 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
4424 /* Convert this into a field assignment operation, if possible. */
4425 return make_field_assignment (x
);
4428 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4429 result. LAST is nonzero if this is the last retry. */
4432 simplify_logical (x
, last
)
4436 enum machine_mode mode
= GET_MODE (x
);
4437 rtx op0
= XEXP (x
, 0);
4438 rtx op1
= XEXP (x
, 1);
4440 switch (GET_CODE (x
))
4443 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4444 insn (and may simplify more). */
4445 if (GET_CODE (op0
) == XOR
4446 && rtx_equal_p (XEXP (op0
, 0), op1
)
4447 && ! side_effects_p (op1
))
4448 x
= gen_binary (AND
, mode
,
4449 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)), op1
);
4451 if (GET_CODE (op0
) == XOR
4452 && rtx_equal_p (XEXP (op0
, 1), op1
)
4453 && ! side_effects_p (op1
))
4454 x
= gen_binary (AND
, mode
,
4455 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)), op1
);
4457 /* Similarly for (~ (A ^ B)) & A. */
4458 if (GET_CODE (op0
) == NOT
4459 && GET_CODE (XEXP (op0
, 0)) == XOR
4460 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
4461 && ! side_effects_p (op1
))
4462 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
4464 if (GET_CODE (op0
) == NOT
4465 && GET_CODE (XEXP (op0
, 0)) == XOR
4466 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
4467 && ! side_effects_p (op1
))
4468 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
4470 if (GET_CODE (op1
) == CONST_INT
)
4472 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
4474 /* If we have (ior (and (X C1) C2)) and the next restart would be
4475 the last, simplify this by making C1 as small as possible
4478 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
4479 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
4480 && GET_CODE (op1
) == CONST_INT
)
4481 return gen_binary (IOR
, mode
,
4482 gen_binary (AND
, mode
, XEXP (op0
, 0),
4483 GEN_INT (INTVAL (XEXP (op0
, 1))
4484 & ~ INTVAL (op1
))), op1
);
4486 if (GET_CODE (x
) != AND
)
4490 /* Convert (A | B) & A to A. */
4491 if (GET_CODE (op0
) == IOR
4492 && (rtx_equal_p (XEXP (op0
, 0), op1
)
4493 || rtx_equal_p (XEXP (op0
, 1), op1
))
4494 && ! side_effects_p (XEXP (op0
, 0))
4495 && ! side_effects_p (XEXP (op0
, 1)))
4498 /* In the following group of tests (and those in case IOR below),
4499 we start with some combination of logical operations and apply
4500 the distributive law followed by the inverse distributive law.
4501 Most of the time, this results in no change. However, if some of
4502 the operands are the same or inverses of each other, simplifications
4505 For example, (and (ior A B) (not B)) can occur as the result of
4506 expanding a bit field assignment. When we apply the distributive
4507 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4508 which then simplifies to (and (A (not B))).
4510 If we have (and (ior A B) C), apply the distributive law and then
4511 the inverse distributive law to see if things simplify. */
4513 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
4515 x
= apply_distributive_law
4516 (gen_binary (GET_CODE (op0
), mode
,
4517 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
4518 gen_binary (AND
, mode
, XEXP (op0
, 1), op1
)));
4519 if (GET_CODE (x
) != AND
)
4523 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
4524 return apply_distributive_law
4525 (gen_binary (GET_CODE (op1
), mode
,
4526 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
4527 gen_binary (AND
, mode
, XEXP (op1
, 1), op0
)));
4529 /* Similarly, taking advantage of the fact that
4530 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4532 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
4533 return apply_distributive_law
4534 (gen_binary (XOR
, mode
,
4535 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
4536 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 1))));
4538 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
4539 return apply_distributive_law
4540 (gen_binary (XOR
, mode
,
4541 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
4542 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 1))));
4546 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4547 if (GET_CODE (op1
) == CONST_INT
4548 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4549 && (nonzero_bits (op0
, mode
) & ~ INTVAL (op1
)) == 0)
4552 /* Convert (A & B) | A to A. */
4553 if (GET_CODE (op0
) == AND
4554 && (rtx_equal_p (XEXP (op0
, 0), op1
)
4555 || rtx_equal_p (XEXP (op0
, 1), op1
))
4556 && ! side_effects_p (XEXP (op0
, 0))
4557 && ! side_effects_p (XEXP (op0
, 1)))
4560 /* If we have (ior (and A B) C), apply the distributive law and then
4561 the inverse distributive law to see if things simplify. */
4563 if (GET_CODE (op0
) == AND
)
4565 x
= apply_distributive_law
4566 (gen_binary (AND
, mode
,
4567 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
4568 gen_binary (IOR
, mode
, XEXP (op0
, 1), op1
)));
4570 if (GET_CODE (x
) != IOR
)
4574 if (GET_CODE (op1
) == AND
)
4576 x
= apply_distributive_law
4577 (gen_binary (AND
, mode
,
4578 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
4579 gen_binary (IOR
, mode
, XEXP (op1
, 1), op0
)));
4581 if (GET_CODE (x
) != IOR
)
4585 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4586 mode size to (rotate A CX). */
4588 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
4589 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
4590 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
4591 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
4592 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
4593 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
4594 == GET_MODE_BITSIZE (mode
)))
4595 return gen_rtx (ROTATE
, mode
, XEXP (op0
, 0),
4596 (GET_CODE (op0
) == ASHIFT
4597 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
4599 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4600 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
4601 does not affect any of the bits in OP1, it can really be done
4602 as a PLUS and we can associate. We do this by seeing if OP1
4603 can be safely shifted left C bits. */
4604 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
4605 && GET_CODE (XEXP (op0
, 0)) == PLUS
4606 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
4607 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
4608 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
4610 int count
= INTVAL (XEXP (op0
, 1));
4611 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
4613 if (mask
>> count
== INTVAL (op1
)
4614 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
4616 SUBST (XEXP (XEXP (op0
, 0), 1),
4617 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
4624 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4625 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4628 int num_negated
= 0;
4630 if (GET_CODE (op0
) == NOT
)
4631 num_negated
++, op0
= XEXP (op0
, 0);
4632 if (GET_CODE (op1
) == NOT
)
4633 num_negated
++, op1
= XEXP (op1
, 0);
4635 if (num_negated
== 2)
4637 SUBST (XEXP (x
, 0), op0
);
4638 SUBST (XEXP (x
, 1), op1
);
4640 else if (num_negated
== 1)
4641 return gen_unary (NOT
, mode
, mode
, gen_binary (XOR
, mode
, op0
, op1
));
4644 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4645 correspond to a machine insn or result in further simplifications
4646 if B is a constant. */
4648 if (GET_CODE (op0
) == AND
4649 && rtx_equal_p (XEXP (op0
, 1), op1
)
4650 && ! side_effects_p (op1
))
4651 return gen_binary (AND
, mode
,
4652 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)),
4655 else if (GET_CODE (op0
) == AND
4656 && rtx_equal_p (XEXP (op0
, 0), op1
)
4657 && ! side_effects_p (op1
))
4658 return gen_binary (AND
, mode
,
4659 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)),
4662 #if STORE_FLAG_VALUE == 1
4663 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4665 if (op1
== const1_rtx
4666 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
4667 && reversible_comparison_p (op0
))
4668 return gen_rtx_combine (reverse_condition (GET_CODE (op0
)),
4669 mode
, XEXP (op0
, 0), XEXP (op0
, 1));
4671 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4672 is (lt foo (const_int 0)), so we can perform the above
4675 if (op1
== const1_rtx
4676 && GET_CODE (op0
) == LSHIFTRT
4677 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
4678 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4679 return gen_rtx_combine (GE
, mode
, XEXP (op0
, 0), const0_rtx
);
4682 /* (xor (comparison foo bar) (const_int sign-bit))
4683 when STORE_FLAG_VALUE is the sign bit. */
4684 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4685 && (STORE_FLAG_VALUE
4686 == (HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4687 && op1
== const_true_rtx
4688 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
4689 && reversible_comparison_p (op0
))
4690 return gen_rtx_combine (reverse_condition (GET_CODE (op0
)),
4691 mode
, XEXP (op0
, 0), XEXP (op0
, 1));
4698 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4699 operations" because they can be replaced with two more basic operations.
4700 ZERO_EXTEND is also considered "compound" because it can be replaced with
4701 an AND operation, which is simpler, though only one operation.
4703 The function expand_compound_operation is called with an rtx expression
4704 and will convert it to the appropriate shifts and AND operations,
4705 simplifying at each stage.
4707 The function make_compound_operation is called to convert an expression
4708 consisting of shifts and ANDs into the equivalent compound expression.
4709 It is the inverse of this function, loosely speaking. */
4712 expand_compound_operation (x
)
4720 switch (GET_CODE (x
))
4725 /* We can't necessarily use a const_int for a multiword mode;
4726 it depends on implicitly extending the value.
4727 Since we don't know the right way to extend it,
4728 we can't tell whether the implicit way is right.
4730 Even for a mode that is no wider than a const_int,
4731 we can't win, because we need to sign extend one of its bits through
4732 the rest of it, and we don't know which bit. */
4733 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
4736 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
4737 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
4738 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
4739 reloaded. If not for that, MEM's would very rarely be safe.
4741 Reject MODEs bigger than a word, because we might not be able
4742 to reference a two-register group starting with an arbitrary register
4743 (and currently gen_lowpart might crash for a SUBREG). */
4745 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
4748 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
4749 /* If the inner object has VOIDmode (the only way this can happen
4750 is if it is a ASM_OPERANDS), we can't do anything since we don't
4751 know how much masking to do. */
4760 /* If the operand is a CLOBBER, just return it. */
4761 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
4764 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
4765 || GET_CODE (XEXP (x
, 2)) != CONST_INT
4766 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4769 len
= INTVAL (XEXP (x
, 1));
4770 pos
= INTVAL (XEXP (x
, 2));
4772 /* If this goes outside the object being extracted, replace the object
4773 with a (use (mem ...)) construct that only combine understands
4774 and is used only for this purpose. */
4775 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4776 SUBST (XEXP (x
, 0), gen_rtx (USE
, GET_MODE (x
), XEXP (x
, 0)));
4778 if (BITS_BIG_ENDIAN
)
4779 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
4787 /* If we reach here, we want to return a pair of shifts. The inner
4788 shift is a left shift of BITSIZE - POS - LEN bits. The outer
4789 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
4790 logical depending on the value of UNSIGNEDP.
4792 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
4793 converted into an AND of a shift.
4795 We must check for the case where the left shift would have a negative
4796 count. This can happen in a case like (x >> 31) & 255 on machines
4797 that can't shift by a constant. On those machines, we would first
4798 combine the shift with the AND to produce a variable-position
4799 extraction. Then the constant of 31 would be substituted in to produce
4800 a such a position. */
4802 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
4803 if (modewidth
>= pos
- len
)
4804 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
4806 simplify_shift_const (NULL_RTX
, ASHIFT
,
4809 modewidth
- pos
- len
),
4812 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
4813 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
4814 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
4817 ((HOST_WIDE_INT
) 1 << len
) - 1);
4819 /* Any other cases we can't handle. */
4823 /* If we couldn't do this for some reason, return the original
4825 if (GET_CODE (tem
) == CLOBBER
)
4831 /* X is a SET which contains an assignment of one object into
4832 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
4833 or certain SUBREGS). If possible, convert it into a series of
4836 We half-heartedly support variable positions, but do not at all
4837 support variable lengths. */
4840 expand_field_assignment (x
)
4844 rtx pos
; /* Always counts from low bit. */
4847 enum machine_mode compute_mode
;
4849 /* Loop until we find something we can't simplify. */
4852 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
4853 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
4855 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
4856 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
4859 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4860 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
4862 inner
= XEXP (SET_DEST (x
), 0);
4863 len
= INTVAL (XEXP (SET_DEST (x
), 1));
4864 pos
= XEXP (SET_DEST (x
), 2);
4866 /* If the position is constant and spans the width of INNER,
4867 surround INNER with a USE to indicate this. */
4868 if (GET_CODE (pos
) == CONST_INT
4869 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
4870 inner
= gen_rtx (USE
, GET_MODE (SET_DEST (x
)), inner
);
4872 if (BITS_BIG_ENDIAN
)
4874 if (GET_CODE (pos
) == CONST_INT
)
4875 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
4877 else if (GET_CODE (pos
) == MINUS
4878 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
4879 && (INTVAL (XEXP (pos
, 1))
4880 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
4881 /* If position is ADJUST - X, new position is X. */
4882 pos
= XEXP (pos
, 0);
4884 pos
= gen_binary (MINUS
, GET_MODE (pos
),
4885 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
4891 /* A SUBREG between two modes that occupy the same numbers of words
4892 can be done by moving the SUBREG to the source. */
4893 else if (GET_CODE (SET_DEST (x
)) == SUBREG
4894 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
4895 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
4896 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
4897 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
4899 x
= gen_rtx (SET
, VOIDmode
, SUBREG_REG (SET_DEST (x
)),
4900 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x
))),
4907 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
4908 inner
= SUBREG_REG (inner
);
4910 compute_mode
= GET_MODE (inner
);
4912 /* Compute a mask of LEN bits, if we can do this on the host machine. */
4913 if (len
< HOST_BITS_PER_WIDE_INT
)
4914 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
4918 /* Now compute the equivalent expression. Make a copy of INNER
4919 for the SET_DEST in case it is a MEM into which we will substitute;
4920 we don't want shared RTL in that case. */
4921 x
= gen_rtx (SET
, VOIDmode
, copy_rtx (inner
),
4922 gen_binary (IOR
, compute_mode
,
4923 gen_binary (AND
, compute_mode
,
4924 gen_unary (NOT
, compute_mode
,
4930 gen_binary (ASHIFT
, compute_mode
,
4931 gen_binary (AND
, compute_mode
,
4932 gen_lowpart_for_combine
4942 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
4943 it is an RTX that represents a variable starting position; otherwise,
4944 POS is the (constant) starting bit position (counted from the LSB).
4946 INNER may be a USE. This will occur when we started with a bitfield
4947 that went outside the boundary of the object in memory, which is
4948 allowed on most machines. To isolate this case, we produce a USE
4949 whose mode is wide enough and surround the MEM with it. The only
4950 code that understands the USE is this routine. If it is not removed,
4951 it will cause the resulting insn not to match.
4953 UNSIGNEDP is non-zero for an unsigned reference and zero for a
4956 IN_DEST is non-zero if this is a reference in the destination of a
4957 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
4958 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
4961 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
4962 ZERO_EXTRACT should be built even for bits starting at bit 0.
4964 MODE is the desired mode of the result (if IN_DEST == 0). */
4967 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
4968 unsignedp
, in_dest
, in_compare
)
4969 enum machine_mode mode
;
4975 int in_dest
, in_compare
;
4977 /* This mode describes the size of the storage area
4978 to fetch the overall value from. Within that, we
4979 ignore the POS lowest bits, etc. */
4980 enum machine_mode is_mode
= GET_MODE (inner
);
4981 enum machine_mode inner_mode
;
4982 enum machine_mode wanted_mem_mode
= byte_mode
;
4983 enum machine_mode pos_mode
= word_mode
;
4984 enum machine_mode extraction_mode
= word_mode
;
4985 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
4988 rtx orig_pos_rtx
= pos_rtx
;
4991 /* Get some information about INNER and get the innermost object. */
4992 if (GET_CODE (inner
) == USE
)
4993 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
4994 /* We don't need to adjust the position because we set up the USE
4995 to pretend that it was a full-word object. */
4996 spans_byte
= 1, inner
= XEXP (inner
, 0);
4997 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
4999 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5000 consider just the QI as the memory to extract from.
5001 The subreg adds or removes high bits; its mode is
5002 irrelevant to the meaning of this extraction,
5003 since POS and LEN count from the lsb. */
5004 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5005 is_mode
= GET_MODE (SUBREG_REG (inner
));
5006 inner
= SUBREG_REG (inner
);
5009 inner_mode
= GET_MODE (inner
);
5011 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5012 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5014 /* See if this can be done without an extraction. We never can if the
5015 width of the field is not the same as that of some integer mode. For
5016 registers, we can only avoid the extraction if the position is at the
5017 low-order bit and this is either not in the destination or we have the
5018 appropriate STRICT_LOW_PART operation available.
5020 For MEM, we can avoid an extract if the field starts on an appropriate
5021 boundary and we can change the mode of the memory reference. However,
5022 we cannot directly access the MEM if we have a USE and the underlying
5023 MEM is not TMODE. This combination means that MEM was being used in a
5024 context where bits outside its mode were being referenced; that is only
5025 valid in bit-field insns. */
5027 if (tmode
!= BLKmode
5028 && ! (spans_byte
&& inner_mode
!= tmode
)
5029 && ((pos_rtx
== 0 && pos
== 0 && GET_CODE (inner
) != MEM
5031 || (GET_CODE (inner
) == REG
5032 && (movstrict_optab
->handlers
[(int) tmode
].insn_code
5033 != CODE_FOR_nothing
))))
5034 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
5036 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
5037 : BITS_PER_UNIT
)) == 0
5038 /* We can't do this if we are widening INNER_MODE (it
5039 may not be aligned, for one thing). */
5040 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
5041 && (inner_mode
== tmode
5042 || (! mode_dependent_address_p (XEXP (inner
, 0))
5043 && ! MEM_VOLATILE_P (inner
))))))
5045 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5046 field. If the original and current mode are the same, we need not
5047 adjust the offset. Otherwise, we do if bytes big endian.
5049 If INNER is not a MEM, get a piece consisting of the just the field
5050 of interest (in this case POS must be 0). */
5052 if (GET_CODE (inner
) == MEM
)
5055 /* POS counts from lsb, but make OFFSET count in memory order. */
5056 if (BYTES_BIG_ENDIAN
)
5057 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
5059 offset
= pos
/ BITS_PER_UNIT
;
5061 new = gen_rtx (MEM
, tmode
, plus_constant (XEXP (inner
, 0), offset
));
5062 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner
);
5063 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner
);
5064 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner
);
5066 else if (GET_CODE (inner
) == REG
)
5068 /* We can't call gen_lowpart_for_combine here since we always want
5069 a SUBREG and it would sometimes return a new hard register. */
5070 if (tmode
!= inner_mode
)
5071 new = gen_rtx (SUBREG
, tmode
, inner
,
5073 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
5074 ? ((GET_MODE_SIZE (inner_mode
)
5075 - GET_MODE_SIZE (tmode
))
5082 new = force_to_mode (inner
, tmode
,
5083 len
>= HOST_BITS_PER_WIDE_INT
5084 ? GET_MODE_MASK (tmode
)
5085 : ((HOST_WIDE_INT
) 1 << len
) - 1,
5088 /* If this extraction is going into the destination of a SET,
5089 make a STRICT_LOW_PART unless we made a MEM. */
5092 return (GET_CODE (new) == MEM
? new
5093 : (GET_CODE (new) != SUBREG
5094 ? gen_rtx (CLOBBER
, tmode
, const0_rtx
)
5095 : gen_rtx_combine (STRICT_LOW_PART
, VOIDmode
, new)));
5097 /* Otherwise, sign- or zero-extend unless we already are in the
5100 return (mode
== tmode
? new
5101 : gen_rtx_combine (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
5105 /* Unless this is a COMPARE or we have a funny memory reference,
5106 don't do anything with zero-extending field extracts starting at
5107 the low-order bit since they are simple AND operations. */
5108 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
5109 && ! in_compare
&& ! spans_byte
&& unsignedp
)
5112 /* Unless we are allowed to span bytes, reject this if we would be
5113 spanning bytes or if the position is not a constant and the length
5114 is not 1. In all other cases, we would only be going outside
5115 out object in cases when an original shift would have been
5118 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
5119 || (pos_rtx
!= 0 && len
!= 1)))
5122 /* Get the mode to use should INNER be a MEM, the mode for the position,
5123 and the mode for the result. */
5127 wanted_mem_mode
= insn_operand_mode
[(int) CODE_FOR_insv
][0];
5128 pos_mode
= insn_operand_mode
[(int) CODE_FOR_insv
][2];
5129 extraction_mode
= insn_operand_mode
[(int) CODE_FOR_insv
][3];
5134 if (! in_dest
&& unsignedp
)
5136 wanted_mem_mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][1];
5137 pos_mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][3];
5138 extraction_mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][0];
5143 if (! in_dest
&& ! unsignedp
)
5145 wanted_mem_mode
= insn_operand_mode
[(int) CODE_FOR_extv
][1];
5146 pos_mode
= insn_operand_mode
[(int) CODE_FOR_extv
][3];
5147 extraction_mode
= insn_operand_mode
[(int) CODE_FOR_extv
][0];
5151 /* Never narrow an object, since that might not be safe. */
5153 if (mode
!= VOIDmode
5154 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
5155 extraction_mode
= mode
;
5157 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
5158 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
5159 pos_mode
= GET_MODE (pos_rtx
);
5161 /* If this is not from memory or we have to change the mode of memory and
5162 cannot, the desired mode is EXTRACTION_MODE. */
5163 if (GET_CODE (inner
) != MEM
5164 || (inner_mode
!= wanted_mem_mode
5165 && (mode_dependent_address_p (XEXP (inner
, 0))
5166 || MEM_VOLATILE_P (inner
))))
5167 wanted_mem_mode
= extraction_mode
;
5171 if (BITS_BIG_ENDIAN
)
5173 /* If position is constant, compute new position. Otherwise,
5174 build subtraction. */
5176 pos
= (MAX (GET_MODE_BITSIZE (is_mode
),
5177 GET_MODE_BITSIZE (wanted_mem_mode
))
5181 = gen_rtx_combine (MINUS
, GET_MODE (pos_rtx
),
5182 GEN_INT (MAX (GET_MODE_BITSIZE (is_mode
),
5183 GET_MODE_BITSIZE (wanted_mem_mode
))
5188 /* If INNER has a wider mode, make it smaller. If this is a constant
5189 extract, try to adjust the byte to point to the byte containing
5191 if (wanted_mem_mode
!= VOIDmode
5192 && GET_MODE_SIZE (wanted_mem_mode
) < GET_MODE_SIZE (is_mode
)
5193 && ((GET_CODE (inner
) == MEM
5194 && (inner_mode
== wanted_mem_mode
5195 || (! mode_dependent_address_p (XEXP (inner
, 0))
5196 && ! MEM_VOLATILE_P (inner
))))))
5200 /* The computations below will be correct if the machine is big
5201 endian in both bits and bytes or little endian in bits and bytes.
5202 If it is mixed, we must adjust. */
5204 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5205 adjust OFFSET to compensate. */
5206 if (BYTES_BIG_ENDIAN
5208 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
5209 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
5211 /* If this is a constant position, we can move to the desired byte. */
5214 offset
+= pos
/ BITS_PER_UNIT
;
5215 pos
%= GET_MODE_BITSIZE (wanted_mem_mode
);
5218 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
5220 && is_mode
!= wanted_mem_mode
)
5221 offset
= (GET_MODE_SIZE (is_mode
)
5222 - GET_MODE_SIZE (wanted_mem_mode
) - offset
);
5224 if (offset
!= 0 || inner_mode
!= wanted_mem_mode
)
5226 rtx newmem
= gen_rtx (MEM
, wanted_mem_mode
,
5227 plus_constant (XEXP (inner
, 0), offset
));
5228 RTX_UNCHANGING_P (newmem
) = RTX_UNCHANGING_P (inner
);
5229 MEM_VOLATILE_P (newmem
) = MEM_VOLATILE_P (inner
);
5230 MEM_IN_STRUCT_P (newmem
) = MEM_IN_STRUCT_P (inner
);
5235 /* If INNER is not memory, we can always get it into the proper mode. */
5236 else if (GET_CODE (inner
) != MEM
)
5237 inner
= force_to_mode (inner
, extraction_mode
,
5238 pos_rtx
|| len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
5239 ? GET_MODE_MASK (extraction_mode
)
5240 : (((HOST_WIDE_INT
) 1 << len
) - 1) << orig_pos
,
5243 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5244 have to zero extend. Otherwise, we can just use a SUBREG. */
5246 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
5247 pos_rtx
= gen_rtx_combine (ZERO_EXTEND
, pos_mode
, pos_rtx
);
5248 else if (pos_rtx
!= 0
5249 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
5250 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
5252 /* Make POS_RTX unless we already have it and it is correct. If we don't
5253 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5255 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
5256 pos_rtx
= orig_pos_rtx
;
5258 else if (pos_rtx
== 0)
5259 pos_rtx
= GEN_INT (pos
);
5261 /* Make the required operation. See if we can use existing rtx. */
5262 new = gen_rtx_combine (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
5263 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
5265 new = gen_lowpart_for_combine (mode
, new);
5270 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5271 with any other operations in X. Return X without that shift if so. */
5274 extract_left_shift (x
, count
)
5278 enum rtx_code code
= GET_CODE (x
);
5279 enum machine_mode mode
= GET_MODE (x
);
5285 /* This is the shift itself. If it is wide enough, we will return
5286 either the value being shifted if the shift count is equal to
5287 COUNT or a shift for the difference. */
5288 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
5289 && INTVAL (XEXP (x
, 1)) >= count
)
5290 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
5291 INTVAL (XEXP (x
, 1)) - count
);
5295 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
5296 return gen_unary (code
, mode
, mode
, tem
);
5300 case PLUS
: case IOR
: case XOR
: case AND
:
5301 /* If we can safely shift this constant and we find the inner shift,
5302 make a new operation. */
5303 if (GET_CODE (XEXP (x
,1)) == CONST_INT
5304 && (INTVAL (XEXP (x
, 1)) & (((HOST_WIDE_INT
) 1 << count
)) - 1) == 0
5305 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
5306 return gen_binary (code
, mode
, tem
,
5307 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
5315 /* Look at the expression rooted at X. Look for expressions
5316 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5317 Form these expressions.
5319 Return the new rtx, usually just X.
5321 Also, for machines like the Vax that don't have logical shift insns,
5322 try to convert logical to arithmetic shift operations in cases where
5323 they are equivalent. This undoes the canonicalizations to logical
5324 shifts done elsewhere.
5326 We try, as much as possible, to re-use rtl expressions to save memory.
5328 IN_CODE says what kind of expression we are processing. Normally, it is
5329 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5330 being kludges), it is MEM. When processing the arguments of a comparison
5331 or a COMPARE against zero, it is COMPARE. */
5334 make_compound_operation (x
, in_code
)
5336 enum rtx_code in_code
;
5338 enum rtx_code code
= GET_CODE (x
);
5339 enum machine_mode mode
= GET_MODE (x
);
5340 int mode_width
= GET_MODE_BITSIZE (mode
);
5342 enum rtx_code next_code
;
5348 /* Select the code to be used in recursive calls. Once we are inside an
5349 address, we stay there. If we have a comparison, set to COMPARE,
5350 but once inside, go back to our default of SET. */
5352 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
5353 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
5354 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
5355 : in_code
== COMPARE
? SET
: in_code
);
5357 /* Process depending on the code of this operation. If NEW is set
5358 non-zero, it will be returned. */
5363 /* Convert shifts by constants into multiplications if inside
5365 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
5366 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
5367 && INTVAL (XEXP (x
, 1)) >= 0)
5369 new = make_compound_operation (XEXP (x
, 0), next_code
);
5370 new = gen_rtx_combine (MULT
, mode
, new,
5371 GEN_INT ((HOST_WIDE_INT
) 1
5372 << INTVAL (XEXP (x
, 1))));
5377 /* If the second operand is not a constant, we can't do anything
5379 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
5382 /* If the constant is a power of two minus one and the first operand
5383 is a logical right shift, make an extraction. */
5384 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5385 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
5387 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
5388 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
5389 0, in_code
== COMPARE
);
5392 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5393 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
5394 && subreg_lowpart_p (XEXP (x
, 0))
5395 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
5396 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
5398 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
5400 new = make_extraction (mode
, new, 0,
5401 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
5402 0, in_code
== COMPARE
);
5404 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
5405 else if ((GET_CODE (XEXP (x
, 0)) == XOR
5406 || GET_CODE (XEXP (x
, 0)) == IOR
)
5407 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
5408 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
5409 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
5411 /* Apply the distributive law, and then try to make extractions. */
5412 new = gen_rtx_combine (GET_CODE (XEXP (x
, 0)), mode
,
5413 gen_rtx (AND
, mode
, XEXP (XEXP (x
, 0), 0),
5415 gen_rtx (AND
, mode
, XEXP (XEXP (x
, 0), 1),
5417 new = make_compound_operation (new, in_code
);
5420 /* If we are have (and (rotate X C) M) and C is larger than the number
5421 of bits in M, this is an extraction. */
5423 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
5424 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
5425 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
5426 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
5428 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
5429 new = make_extraction (mode
, new,
5430 (GET_MODE_BITSIZE (mode
)
5431 - INTVAL (XEXP (XEXP (x
, 0), 1))),
5432 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
5435 /* On machines without logical shifts, if the operand of the AND is
5436 a logical shift and our mask turns off all the propagated sign
5437 bits, we can replace the logical shift with an arithmetic shift. */
5438 else if (ashr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
5439 && (lshr_optab
->handlers
[(int) mode
].insn_code
5440 == CODE_FOR_nothing
)
5441 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5442 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
5443 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
5444 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
5445 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
5447 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
5449 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
5450 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
5452 gen_rtx_combine (ASHIFTRT
, mode
,
5453 make_compound_operation (XEXP (XEXP (x
, 0), 0),
5455 XEXP (XEXP (x
, 0), 1)));
5458 /* If the constant is one less than a power of two, this might be
5459 representable by an extraction even if no shift is present.
5460 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5461 we are in a COMPARE. */
5462 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
5463 new = make_extraction (mode
,
5464 make_compound_operation (XEXP (x
, 0),
5466 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
5468 /* If we are in a comparison and this is an AND with a power of two,
5469 convert this into the appropriate bit extract. */
5470 else if (in_code
== COMPARE
5471 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
5472 new = make_extraction (mode
,
5473 make_compound_operation (XEXP (x
, 0),
5475 i
, NULL_RTX
, 1, 1, 0, 1);
5480 /* If the sign bit is known to be zero, replace this with an
5481 arithmetic shift. */
5482 if (ashr_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
5483 && lshr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
5484 && mode_width
<= HOST_BITS_PER_WIDE_INT
5485 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
5487 new = gen_rtx_combine (ASHIFTRT
, mode
,
5488 make_compound_operation (XEXP (x
, 0),
5494 /* ... fall through ... */
5500 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5501 this is a SIGN_EXTRACT. */
5502 if (GET_CODE (rhs
) == CONST_INT
5503 && GET_CODE (lhs
) == ASHIFT
5504 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
5505 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
5507 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
5508 new = make_extraction (mode
, new,
5509 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
5510 NULL_RTX
, mode_width
- INTVAL (rhs
),
5511 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
5514 /* See if we have operations between an ASHIFTRT and an ASHIFT.
5515 If so, try to merge the shifts into a SIGN_EXTEND. We could
5516 also do this for some cases of SIGN_EXTRACT, but it doesn't
5517 seem worth the effort; the case checked for occurs on Alpha. */
5519 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
5520 && ! (GET_CODE (lhs
) == SUBREG
5521 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
5522 && GET_CODE (rhs
) == CONST_INT
5523 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
5524 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
5525 new = make_extraction (mode
, make_compound_operation (new, next_code
),
5526 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
5527 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
5532 /* Call ourselves recursively on the inner expression. If we are
5533 narrowing the object and it has a different RTL code from
5534 what it originally did, do this SUBREG as a force_to_mode. */
5536 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
5537 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
5538 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
5539 && subreg_lowpart_p (x
))
5541 rtx newer
= force_to_mode (tem
, mode
,
5542 GET_MODE_MASK (mode
), NULL_RTX
, 0);
5544 /* If we have something other than a SUBREG, we might have
5545 done an expansion, so rerun outselves. */
5546 if (GET_CODE (newer
) != SUBREG
)
5547 newer
= make_compound_operation (newer
, in_code
);
5555 x
= gen_lowpart_for_combine (mode
, new);
5556 code
= GET_CODE (x
);
5559 /* Now recursively process each operand of this operation. */
5560 fmt
= GET_RTX_FORMAT (code
);
5561 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
5564 new = make_compound_operation (XEXP (x
, i
), next_code
);
5565 SUBST (XEXP (x
, i
), new);
5571 /* Given M see if it is a value that would select a field of bits
5572 within an item, but not the entire word. Return -1 if not.
5573 Otherwise, return the starting position of the field, where 0 is the
5576 *PLEN is set to the length of the field. */
5579 get_pos_from_mask (m
, plen
)
5580 unsigned HOST_WIDE_INT m
;
5583 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5584 int pos
= exact_log2 (m
& - m
);
5589 /* Now shift off the low-order zero bits and see if we have a power of
5591 *plen
= exact_log2 ((m
>> pos
) + 1);
5599 /* See if X can be simplified knowing that we will only refer to it in
5600 MODE and will only refer to those bits that are nonzero in MASK.
5601 If other bits are being computed or if masking operations are done
5602 that select a superset of the bits in MASK, they can sometimes be
5605 Return a possibly simplified expression, but always convert X to
5606 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
5608 Also, if REG is non-zero and X is a register equal in value to REG,
5611 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
5612 are all off in X. This is used when X will be complemented, by either
5613 NOT, NEG, or XOR. */
5616 force_to_mode (x
, mode
, mask
, reg
, just_select
)
5618 enum machine_mode mode
;
5619 unsigned HOST_WIDE_INT mask
;
5623 enum rtx_code code
= GET_CODE (x
);
5624 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
5625 enum machine_mode op_mode
;
5626 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
5629 /* If this is a CALL, don't do anything. Some of the code below
5630 will do the wrong thing since the mode of a CALL is VOIDmode. */
5634 /* We want to perform the operation is its present mode unless we know
5635 that the operation is valid in MODE, in which case we do the operation
5637 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
5638 && code_to_optab
[(int) code
] != 0
5639 && (code_to_optab
[(int) code
]->handlers
[(int) mode
].insn_code
5640 != CODE_FOR_nothing
))
5641 ? mode
: GET_MODE (x
));
5643 /* It is not valid to do a right-shift in a narrower mode
5644 than the one it came in with. */
5645 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
5646 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
5647 op_mode
= GET_MODE (x
);
5649 /* Truncate MASK to fit OP_MODE. */
5651 mask
&= GET_MODE_MASK (op_mode
);
5653 /* When we have an arithmetic operation, or a shift whose count we
5654 do not know, we need to assume that all bit the up to the highest-order
5655 bit in MASK will be needed. This is how we form such a mask. */
5657 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
5658 ? GET_MODE_MASK (op_mode
)
5659 : ((HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1)) - 1);
5661 fuller_mask
= ~ (HOST_WIDE_INT
) 0;
5663 /* Determine what bits of X are guaranteed to be (non)zero. */
5664 nonzero
= nonzero_bits (x
, mode
);
5666 /* If none of the bits in X are needed, return a zero. */
5667 if (! just_select
&& (nonzero
& mask
) == 0)
5670 /* If X is a CONST_INT, return a new one. Do this here since the
5671 test below will fail. */
5672 if (GET_CODE (x
) == CONST_INT
)
5674 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
5675 int width
= GET_MODE_BITSIZE (mode
);
5677 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
5678 number, sign extend it. */
5679 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
5680 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
5681 cval
|= (HOST_WIDE_INT
) -1 << width
;
5683 return GEN_INT (cval
);
5686 /* If X is narrower than MODE and we want all the bits in X's mode, just
5687 get X in the proper mode. */
5688 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
5689 && (GET_MODE_MASK (GET_MODE (x
)) & ~ mask
) == 0)
5690 return gen_lowpart_for_combine (mode
, x
);
5692 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
5693 MASK are already known to be zero in X, we need not do anything. */
5694 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~ mask
& nonzero
) == 0)
5700 /* If X is a (clobber (const_int)), return it since we know we are
5701 generating something that won't match. */
5705 /* X is a (use (mem ..)) that was made from a bit-field extraction that
5706 spanned the boundary of the MEM. If we are now masking so it is
5707 within that boundary, we don't need the USE any more. */
5708 if (! BITS_BIG_ENDIAN
5709 && (mask
& ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5710 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
5717 x
= expand_compound_operation (x
);
5718 if (GET_CODE (x
) != code
)
5719 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
5723 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
5724 || rtx_equal_p (reg
, get_last_value (x
))))
5729 if (subreg_lowpart_p (x
)
5730 /* We can ignore the effect of this SUBREG if it narrows the mode or
5731 if the constant masks to zero all the bits the mode doesn't
5733 && ((GET_MODE_SIZE (GET_MODE (x
))
5734 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
5736 & GET_MODE_MASK (GET_MODE (x
))
5737 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
5738 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
5742 /* If this is an AND with a constant, convert it into an AND
5743 whose constant is the AND of that constant with MASK. If it
5744 remains an AND of MASK, delete it since it is redundant. */
5746 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
5747 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
5749 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
5750 mask
& INTVAL (XEXP (x
, 1)));
5752 /* If X is still an AND, see if it is an AND with a mask that
5753 is just some low-order bits. If so, and it is MASK, we don't
5756 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
5757 && INTVAL (XEXP (x
, 1)) == mask
)
5760 /* If it remains an AND, try making another AND with the bits
5761 in the mode mask that aren't in MASK turned on. If the
5762 constant in the AND is wide enough, this might make a
5763 cheaper constant. */
5765 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
5766 && GET_MODE_MASK (GET_MODE (x
)) != mask
)
5768 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
5769 | (GET_MODE_MASK (GET_MODE (x
)) & ~ mask
));
5770 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
5773 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
5774 number, sign extend it. */
5775 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
5776 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
5777 cval
|= (HOST_WIDE_INT
) -1 << width
;
5779 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
5780 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
5790 /* In (and (plus FOO C1) M), if M is a mask that just turns off
5791 low-order bits (as in an alignment operation) and FOO is already
5792 aligned to that boundary, mask C1 to that boundary as well.
5793 This may eliminate that PLUS and, later, the AND. */
5794 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
5795 && exact_log2 (- mask
) >= 0
5796 && (nonzero_bits (XEXP (x
, 0), mode
) & ~ mask
) == 0
5797 && (INTVAL (XEXP (x
, 1)) & ~ mask
) != 0)
5798 return force_to_mode (plus_constant (XEXP (x
, 0),
5799 INTVAL (XEXP (x
, 1)) & mask
),
5800 mode
, mask
, reg
, next_select
);
5802 /* ... fall through ... */
5806 /* For PLUS, MINUS and MULT, we need any bits less significant than the
5807 most significant bit in MASK since carries from those bits will
5808 affect the bits we are interested in. */
5814 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
5815 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
5816 operation which may be a bitfield extraction. Ensure that the
5817 constant we form is not wider than the mode of X. */
5819 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5820 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
5821 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
5822 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
5823 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5824 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
5825 + floor_log2 (INTVAL (XEXP (x
, 1))))
5826 < GET_MODE_BITSIZE (GET_MODE (x
)))
5827 && (INTVAL (XEXP (x
, 1))
5828 & ~ nonzero_bits (XEXP (x
, 0), GET_MODE (x
)) == 0))
5830 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
5831 << INTVAL (XEXP (XEXP (x
, 0), 1)));
5832 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
5833 XEXP (XEXP (x
, 0), 0), temp
);
5834 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (x
, 1));
5835 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
5839 /* For most binary operations, just propagate into the operation and
5840 change the mode if we have an operation of that mode. */
5842 op0
= gen_lowpart_for_combine (op_mode
,
5843 force_to_mode (XEXP (x
, 0), mode
, mask
,
5845 op1
= gen_lowpart_for_combine (op_mode
,
5846 force_to_mode (XEXP (x
, 1), mode
, mask
,
5849 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
5850 MASK since OP1 might have been sign-extended but we never want
5851 to turn on extra bits, since combine might have previously relied
5852 on them being off. */
5853 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
5854 && (INTVAL (op1
) & mask
) != 0)
5855 op1
= GEN_INT (INTVAL (op1
) & mask
);
5857 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
5858 x
= gen_binary (code
, op_mode
, op0
, op1
);
5862 /* For left shifts, do the same, but just for the first operand.
5863 However, we cannot do anything with shifts where we cannot
5864 guarantee that the counts are smaller than the size of the mode
5865 because such a count will have a different meaning in a
5868 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
5869 && INTVAL (XEXP (x
, 1)) >= 0
5870 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
5871 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
5872 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
5873 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
5876 /* If the shift count is a constant and we can do arithmetic in
5877 the mode of the shift, refine which bits we need. Otherwise, use the
5878 conservative form of the mask. */
5879 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
5880 && INTVAL (XEXP (x
, 1)) >= 0
5881 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
5882 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
5883 mask
>>= INTVAL (XEXP (x
, 1));
5887 op0
= gen_lowpart_for_combine (op_mode
,
5888 force_to_mode (XEXP (x
, 0), op_mode
,
5889 mask
, reg
, next_select
));
5891 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
5892 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
5896 /* Here we can only do something if the shift count is a constant,
5897 this shift constant is valid for the host, and we can do arithmetic
5900 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
5901 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
5902 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
5904 rtx inner
= XEXP (x
, 0);
5906 /* Select the mask of the bits we need for the shift operand. */
5907 mask
<<= INTVAL (XEXP (x
, 1));
5909 /* We can only change the mode of the shift if we can do arithmetic
5910 in the mode of the shift and MASK is no wider than the width of
5912 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
5913 || (mask
& ~ GET_MODE_MASK (op_mode
)) != 0)
5914 op_mode
= GET_MODE (x
);
5916 inner
= force_to_mode (inner
, op_mode
, mask
, reg
, next_select
);
5918 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
5919 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
5922 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
5923 shift and AND produces only copies of the sign bit (C2 is one less
5924 than a power of two), we can do this with just a shift. */
5926 if (GET_CODE (x
) == LSHIFTRT
5927 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5928 && ((INTVAL (XEXP (x
, 1))
5929 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
5930 >= GET_MODE_BITSIZE (GET_MODE (x
)))
5931 && exact_log2 (mask
+ 1) >= 0
5932 && (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5933 >= exact_log2 (mask
+ 1)))
5934 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
5935 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
5936 - exact_log2 (mask
+ 1)));
5940 /* If we are just looking for the sign bit, we don't need this shift at
5941 all, even if it has a variable count. */
5942 if (mask
== ((HOST_WIDE_INT
) 1
5943 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1)))
5944 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
5946 /* If this is a shift by a constant, get a mask that contains those bits
5947 that are not copies of the sign bit. We then have two cases: If
5948 MASK only includes those bits, this can be a logical shift, which may
5949 allow simplifications. If MASK is a single-bit field not within
5950 those bits, we are requesting a copy of the sign bit and hence can
5951 shift the sign bit to the appropriate location. */
5953 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
5954 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
5958 nonzero
= GET_MODE_MASK (GET_MODE (x
));
5959 nonzero
>>= INTVAL (XEXP (x
, 1));
5961 if ((mask
& ~ nonzero
) == 0
5962 || (i
= exact_log2 (mask
)) >= 0)
5964 x
= simplify_shift_const
5965 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
5966 i
< 0 ? INTVAL (XEXP (x
, 1))
5967 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
5969 if (GET_CODE (x
) != ASHIFTRT
)
5970 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
5974 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
5975 even if the shift count isn't a constant. */
5977 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
5979 /* If this is a sign-extension operation that just affects bits
5980 we don't care about, remove it. Be sure the call above returned
5981 something that is still a shift. */
5983 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
5984 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5985 && INTVAL (XEXP (x
, 1)) >= 0
5986 && (INTVAL (XEXP (x
, 1))
5987 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
5988 && GET_CODE (XEXP (x
, 0)) == ASHIFT
5989 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
5990 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
5991 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
5998 /* If the shift count is constant and we can do computations
5999 in the mode of X, compute where the bits we care about are.
6000 Otherwise, we can't do anything. Don't change the mode of
6001 the shift or propagate MODE into the shift, though. */
6002 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6003 && INTVAL (XEXP (x
, 1)) >= 0)
6005 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
6006 GET_MODE (x
), GEN_INT (mask
),
6008 if (temp
&& GET_CODE(temp
) == CONST_INT
)
6010 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
6011 INTVAL (temp
), reg
, next_select
));
6016 /* If we just want the low-order bit, the NEG isn't needed since it
6017 won't change the low-order bit. */
6019 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
6021 /* We need any bits less significant than the most significant bit in
6022 MASK since carries from those bits will affect the bits we are
6028 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6029 same as the XOR case above. Ensure that the constant we form is not
6030 wider than the mode of X. */
6032 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6033 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6034 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6035 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
6036 < GET_MODE_BITSIZE (GET_MODE (x
)))
6037 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
6039 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
6040 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
6041 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
6043 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6047 op0
= gen_lowpart_for_combine (op_mode
,
6048 force_to_mode (XEXP (x
, 0), mode
, mask
,
6050 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6051 x
= gen_unary (code
, op_mode
, op_mode
, op0
);
6055 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6056 in STORE_FLAG_VALUE and FOO has no bits that might be nonzero not
6058 if ((mask
& ~ STORE_FLAG_VALUE
) == 0 && XEXP (x
, 0) == const0_rtx
6059 && (nonzero_bits (XEXP (x
, 0), mode
) & ~ mask
) == 0)
6060 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6065 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6066 written in a narrower mode. We play it safe and do not do so. */
6069 gen_lowpart_for_combine (GET_MODE (x
),
6070 force_to_mode (XEXP (x
, 1), mode
,
6071 mask
, reg
, next_select
)));
6073 gen_lowpart_for_combine (GET_MODE (x
),
6074 force_to_mode (XEXP (x
, 2), mode
,
6075 mask
, reg
,next_select
)));
6079 /* Ensure we return a value of the proper mode. */
6080 return gen_lowpart_for_combine (mode
, x
);
6083 /* Return nonzero if X is an expression that has one of two values depending on
6084 whether some other value is zero or nonzero. In that case, we return the
6085 value that is being tested, *PTRUE is set to the value if the rtx being
6086 returned has a nonzero value, and *PFALSE is set to the other alternative.
6088 If we return zero, we set *PTRUE and *PFALSE to X. */
6091 if_then_else_cond (x
, ptrue
, pfalse
)
6093 rtx
*ptrue
, *pfalse
;
6095 enum machine_mode mode
= GET_MODE (x
);
6096 enum rtx_code code
= GET_CODE (x
);
6097 int size
= GET_MODE_BITSIZE (mode
);
6098 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
6099 unsigned HOST_WIDE_INT nz
;
6101 /* If this is a unary operation whose operand has one of two values, apply
6102 our opcode to compute those values. */
6103 if (GET_RTX_CLASS (code
) == '1'
6104 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
6106 *ptrue
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), true0
);
6107 *pfalse
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), false0
);
6111 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6112 make can't possibly match and would supress other optimizations. */
6113 else if (code
== COMPARE
)
6116 /* If this is a binary operation, see if either side has only one of two
6117 values. If either one does or if both do and they are conditional on
6118 the same value, compute the new true and false values. */
6119 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
6120 || GET_RTX_CLASS (code
) == '<')
6122 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
6123 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
6125 if ((cond0
!= 0 || cond1
!= 0)
6126 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
6128 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
6129 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
6130 return cond0
? cond0
: cond1
;
6133 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
6135 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6136 operands is zero when the other is non-zero, and vice-versa. */
6138 if ((code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
6140 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
6142 rtx op0
= XEXP (XEXP (x
, 0), 1);
6143 rtx op1
= XEXP (XEXP (x
, 1), 1);
6145 cond0
= XEXP (XEXP (x
, 0), 0);
6146 cond1
= XEXP (XEXP (x
, 1), 0);
6148 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
6149 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
6150 && reversible_comparison_p (cond1
)
6151 && ((GET_CODE (cond0
) == reverse_condition (GET_CODE (cond1
))
6152 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
6153 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
6154 || ((swap_condition (GET_CODE (cond0
))
6155 == reverse_condition (GET_CODE (cond1
)))
6156 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
6157 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
6158 && ! side_effects_p (x
))
6160 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
6161 *pfalse
= gen_binary (MULT
, mode
,
6163 ? gen_unary (NEG
, mode
, mode
, op1
) : op1
),
6169 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6171 if ((code
== MULT
|| code
== AND
|| code
== UMIN
)
6172 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
6174 cond0
= XEXP (XEXP (x
, 0), 0);
6175 cond1
= XEXP (XEXP (x
, 1), 0);
6177 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
6178 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
6179 && reversible_comparison_p (cond1
)
6180 && ((GET_CODE (cond0
) == reverse_condition (GET_CODE (cond1
))
6181 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
6182 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
6183 || ((swap_condition (GET_CODE (cond0
))
6184 == reverse_condition (GET_CODE (cond1
)))
6185 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
6186 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
6187 && ! side_effects_p (x
))
6189 *ptrue
= *pfalse
= const0_rtx
;
6196 else if (code
== IF_THEN_ELSE
)
6198 /* If we have IF_THEN_ELSE already, extract the condition and
6199 canonicalize it if it is NE or EQ. */
6200 cond0
= XEXP (x
, 0);
6201 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
6202 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
6203 return XEXP (cond0
, 0);
6204 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
6206 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
6207 return XEXP (cond0
, 0);
6213 /* If X is a normal SUBREG with both inner and outer modes integral,
6214 we can narrow both the true and false values of the inner expression,
6215 if there is a condition. */
6216 else if (code
== SUBREG
&& GET_MODE_CLASS (mode
) == MODE_INT
6217 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_INT
6218 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))
6219 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
6222 *ptrue
= force_to_mode (true0
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
6224 = force_to_mode (false0
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
6229 /* If X is a constant, this isn't special and will cause confusions
6230 if we treat it as such. Likewise if it is equivalent to a constant. */
6231 else if (CONSTANT_P (x
)
6232 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
6235 /* If X is known to be either 0 or -1, those are the true and
6236 false values when testing X. */
6237 else if (num_sign_bit_copies (x
, mode
) == size
)
6239 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
6243 /* Likewise for 0 or a single bit. */
6244 else if (exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
6246 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
6250 /* Otherwise fail; show no condition with true and false values the same. */
6251 *ptrue
= *pfalse
= x
;
6255 /* Return the value of expression X given the fact that condition COND
6256 is known to be true when applied to REG as its first operand and VAL
6257 as its second. X is known to not be shared and so can be modified in
6260 We only handle the simplest cases, and specifically those cases that
6261 arise with IF_THEN_ELSE expressions. */
6264 known_cond (x
, cond
, reg
, val
)
6269 enum rtx_code code
= GET_CODE (x
);
6274 if (side_effects_p (x
))
6277 if (cond
== EQ
&& rtx_equal_p (x
, reg
))
6280 /* If X is (abs REG) and we know something about REG's relationship
6281 with zero, we may be able to simplify this. */
6283 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
6286 case GE
: case GT
: case EQ
:
6289 return gen_unary (NEG
, GET_MODE (XEXP (x
, 0)), GET_MODE (XEXP (x
, 0)),
6293 /* The only other cases we handle are MIN, MAX, and comparisons if the
6294 operands are the same as REG and VAL. */
6296 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
6298 if (rtx_equal_p (XEXP (x
, 0), val
))
6299 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
6301 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
6303 if (GET_RTX_CLASS (code
) == '<')
6304 return (comparison_dominates_p (cond
, code
) ? const_true_rtx
6305 : (comparison_dominates_p (cond
,
6306 reverse_condition (code
))
6309 else if (code
== SMAX
|| code
== SMIN
6310 || code
== UMIN
|| code
== UMAX
)
6312 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
6314 if (code
== SMAX
|| code
== UMAX
)
6315 cond
= reverse_condition (cond
);
6320 return unsignedp
? x
: XEXP (x
, 1);
6322 return unsignedp
? x
: XEXP (x
, 0);
6324 return unsignedp
? XEXP (x
, 1) : x
;
6326 return unsignedp
? XEXP (x
, 0) : x
;
6332 fmt
= GET_RTX_FORMAT (code
);
6333 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6336 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
6337 else if (fmt
[i
] == 'E')
6338 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6339 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
6346 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6347 Return that assignment if so.
6349 We only handle the most common cases. */
6352 make_field_assignment (x
)
6355 rtx dest
= SET_DEST (x
);
6356 rtx src
= SET_SRC (x
);
6361 enum machine_mode mode
;
6363 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6364 a clear of a one-bit field. We will have changed it to
6365 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
6368 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
6369 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
6370 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
6371 && (rtx_equal_p (dest
, XEXP (src
, 1))
6372 || rtx_equal_p (dest
, get_last_value (XEXP (src
, 1)))
6373 || rtx_equal_p (get_last_value (dest
), XEXP (src
, 1))))
6375 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
6377 return gen_rtx (SET
, VOIDmode
, assign
, const0_rtx
);
6380 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
6381 && subreg_lowpart_p (XEXP (src
, 0))
6382 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
6383 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
6384 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
6385 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
6386 && (rtx_equal_p (dest
, XEXP (src
, 1))
6387 || rtx_equal_p (dest
, get_last_value (XEXP (src
, 1)))
6388 || rtx_equal_p (get_last_value (dest
), XEXP (src
, 1))))
6390 assign
= make_extraction (VOIDmode
, dest
, 0,
6391 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
6393 return gen_rtx (SET
, VOIDmode
, assign
, const0_rtx
);
6396 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
6398 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
6399 && XEXP (XEXP (src
, 0), 0) == const1_rtx
6400 && (rtx_equal_p (dest
, XEXP (src
, 1))
6401 || rtx_equal_p (dest
, get_last_value (XEXP (src
, 1)))
6402 || rtx_equal_p (get_last_value (dest
), XEXP (src
, 1))))
6404 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
6406 return gen_rtx (SET
, VOIDmode
, assign
, const1_rtx
);
6409 /* The other case we handle is assignments into a constant-position
6410 field. They look like (ior (and DEST C1) OTHER). If C1 represents
6411 a mask that has all one bits except for a group of zero bits and
6412 OTHER is known to have zeros where C1 has ones, this is such an
6413 assignment. Compute the position and length from C1. Shift OTHER
6414 to the appropriate position, force it to the required mode, and
6415 make the extraction. Check for the AND in both operands. */
6417 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == AND
6418 && GET_CODE (XEXP (XEXP (src
, 0), 1)) == CONST_INT
6419 && (rtx_equal_p (XEXP (XEXP (src
, 0), 0), dest
)
6420 || rtx_equal_p (XEXP (XEXP (src
, 0), 0), get_last_value (dest
))
6421 || rtx_equal_p (get_last_value (XEXP (XEXP (src
, 0), 1)), dest
)))
6422 c1
= INTVAL (XEXP (XEXP (src
, 0), 1)), other
= XEXP (src
, 1);
6423 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 1)) == AND
6424 && GET_CODE (XEXP (XEXP (src
, 1), 1)) == CONST_INT
6425 && (rtx_equal_p (XEXP (XEXP (src
, 1), 0), dest
)
6426 || rtx_equal_p (XEXP (XEXP (src
, 1), 0), get_last_value (dest
))
6427 || rtx_equal_p (get_last_value (XEXP (XEXP (src
, 1), 0)),
6429 c1
= INTVAL (XEXP (XEXP (src
, 1), 1)), other
= XEXP (src
, 0);
6433 pos
= get_pos_from_mask (c1
^ GET_MODE_MASK (GET_MODE (dest
)), &len
);
6434 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
6435 || (GET_MODE_BITSIZE (GET_MODE (other
)) <= HOST_BITS_PER_WIDE_INT
6436 && (c1
& nonzero_bits (other
, GET_MODE (other
))) != 0))
6439 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
6441 /* The mode to use for the source is the mode of the assignment, or of
6442 what is inside a possible STRICT_LOW_PART. */
6443 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
6444 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
6446 /* Shift OTHER right POS places and make it the source, restricting it
6447 to the proper length and mode. */
6449 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6450 GET_MODE (src
), other
, pos
),
6452 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
6453 ? GET_MODE_MASK (mode
)
6454 : ((HOST_WIDE_INT
) 1 << len
) - 1,
6457 return gen_rtx_combine (SET
, VOIDmode
, assign
, src
);
6460 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
6464 apply_distributive_law (x
)
6467 enum rtx_code code
= GET_CODE (x
);
6468 rtx lhs
, rhs
, other
;
6470 enum rtx_code inner_code
;
6472 /* Distributivity is not true for floating point.
6473 It can change the value. So don't do it.
6474 -- rms and moshier@world.std.com. */
6475 if (FLOAT_MODE_P (GET_MODE (x
)))
6478 /* The outer operation can only be one of the following: */
6479 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
6480 && code
!= PLUS
&& code
!= MINUS
)
6483 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
6485 /* If either operand is a primitive we can't do anything, so get out fast. */
6486 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
6487 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
6490 lhs
= expand_compound_operation (lhs
);
6491 rhs
= expand_compound_operation (rhs
);
6492 inner_code
= GET_CODE (lhs
);
6493 if (inner_code
!= GET_CODE (rhs
))
6496 /* See if the inner and outer operations distribute. */
6503 /* These all distribute except over PLUS. */
6504 if (code
== PLUS
|| code
== MINUS
)
6509 if (code
!= PLUS
&& code
!= MINUS
)
6514 /* This is also a multiply, so it distributes over everything. */
6518 /* Non-paradoxical SUBREGs distributes over all operations, provided
6519 the inner modes and word numbers are the same, this is an extraction
6520 of a low-order part, we don't convert an fp operation to int or
6521 vice versa, and we would not be converting a single-word
6522 operation into a multi-word operation. The latter test is not
6523 required, but it prevents generating unneeded multi-word operations.
6524 Some of the previous tests are redundant given the latter test, but
6525 are retained because they are required for correctness.
6527 We produce the result slightly differently in this case. */
6529 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
6530 || SUBREG_WORD (lhs
) != SUBREG_WORD (rhs
)
6531 || ! subreg_lowpart_p (lhs
)
6532 || (GET_MODE_CLASS (GET_MODE (lhs
))
6533 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
6534 || (GET_MODE_SIZE (GET_MODE (lhs
))
6535 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
6536 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
6539 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
6540 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
6541 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
6547 /* Set LHS and RHS to the inner operands (A and B in the example
6548 above) and set OTHER to the common operand (C in the example).
6549 These is only one way to do this unless the inner operation is
6551 if (GET_RTX_CLASS (inner_code
) == 'c'
6552 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
6553 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
6554 else if (GET_RTX_CLASS (inner_code
) == 'c'
6555 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
6556 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
6557 else if (GET_RTX_CLASS (inner_code
) == 'c'
6558 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
6559 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
6560 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
6561 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
6565 /* Form the new inner operation, seeing if it simplifies first. */
6566 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
6568 /* There is one exception to the general way of distributing:
6569 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
6570 if (code
== XOR
&& inner_code
== IOR
)
6573 other
= gen_unary (NOT
, GET_MODE (x
), GET_MODE (x
), other
);
6576 /* We may be able to continuing distributing the result, so call
6577 ourselves recursively on the inner operation before forming the
6578 outer operation, which we return. */
6579 return gen_binary (inner_code
, GET_MODE (x
),
6580 apply_distributive_law (tem
), other
);
6583 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
6586 Return an equivalent form, if different from X. Otherwise, return X. If
6587 X is zero, we are to always construct the equivalent form. */
6590 simplify_and_const_int (x
, mode
, varop
, constop
)
6592 enum machine_mode mode
;
6594 unsigned HOST_WIDE_INT constop
;
6596 unsigned HOST_WIDE_INT nonzero
;
6599 /* Simplify VAROP knowing that we will be only looking at some of the
6601 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
6603 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
6604 CONST_INT, we are done. */
6605 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
6608 /* See what bits may be nonzero in VAROP. Unlike the general case of
6609 a call to nonzero_bits, here we don't care about bits outside
6612 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
6614 /* Turn off all bits in the constant that are known to already be zero.
6615 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
6616 which is tested below. */
6620 /* If we don't have any bits left, return zero. */
6624 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
6625 a power of two, we can replace this with a ASHIFT. */
6626 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
6627 && (i
= exact_log2 (constop
)) >= 0)
6628 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
6630 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
6631 or XOR, then try to apply the distributive law. This may eliminate
6632 operations if either branch can be simplified because of the AND.
6633 It may also make some cases more complex, but those cases probably
6634 won't match a pattern either with or without this. */
6636 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
6638 gen_lowpart_for_combine
6640 apply_distributive_law
6641 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
6642 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
6643 XEXP (varop
, 0), constop
),
6644 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
6645 XEXP (varop
, 1), constop
))));
6647 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
6648 if we already had one (just check for the simplest cases). */
6649 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
6650 && GET_MODE (XEXP (x
, 0)) == mode
6651 && SUBREG_REG (XEXP (x
, 0)) == varop
)
6652 varop
= XEXP (x
, 0);
6654 varop
= gen_lowpart_for_combine (mode
, varop
);
6656 /* If we can't make the SUBREG, try to return what we were given. */
6657 if (GET_CODE (varop
) == CLOBBER
)
6658 return x
? x
: varop
;
6660 /* If we are only masking insignificant bits, return VAROP. */
6661 if (constop
== nonzero
)
6664 /* Otherwise, return an AND. See how much, if any, of X we can use. */
6665 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
6666 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
6670 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
6671 || INTVAL (XEXP (x
, 1)) != constop
)
6672 SUBST (XEXP (x
, 1), GEN_INT (constop
));
6674 SUBST (XEXP (x
, 0), varop
);
6680 /* Given an expression, X, compute which bits in X can be non-zero.
6681 We don't care about bits outside of those defined in MODE.
6683 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
6684 a shift, AND, or zero_extract, we can do better. */
6686 static unsigned HOST_WIDE_INT
6687 nonzero_bits (x
, mode
)
6689 enum machine_mode mode
;
6691 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
6692 unsigned HOST_WIDE_INT inner_nz
;
6694 int mode_width
= GET_MODE_BITSIZE (mode
);
6697 /* For floating-point values, assume all bits are needed. */
6698 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
6701 /* If X is wider than MODE, use its mode instead. */
6702 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
6704 mode
= GET_MODE (x
);
6705 nonzero
= GET_MODE_MASK (mode
);
6706 mode_width
= GET_MODE_BITSIZE (mode
);
6709 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
6710 /* Our only callers in this case look for single bit values. So
6711 just return the mode mask. Those tests will then be false. */
6714 #ifndef WORD_REGISTER_OPERATIONS
6715 /* If MODE is wider than X, but both are a single word for both the host
6716 and target machines, we can compute this from which bits of the
6717 object might be nonzero in its own mode, taking into account the fact
6718 that on many CISC machines, accessing an object in a wider mode
6719 causes the high-order bits to become undefined. So they are
6720 not known to be zero. */
6722 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
6723 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
6724 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6725 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
6727 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
6728 nonzero
|= GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
));
6733 code
= GET_CODE (x
);
6737 #ifdef STACK_BOUNDARY
6738 /* If this is the stack pointer, we may know something about its
6739 alignment. If PUSH_ROUNDING is defined, it is possible for the
6740 stack to be momentarily aligned only to that amount, so we pick
6741 the least alignment. */
6743 if (x
== stack_pointer_rtx
)
6745 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6747 #ifdef PUSH_ROUNDING
6748 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
6751 return nonzero
& ~ (sp_alignment
- 1);
6755 /* If X is a register whose nonzero bits value is current, use it.
6756 Otherwise, if X is a register whose value we can find, use that
6757 value. Otherwise, use the previously-computed global nonzero bits
6758 for this register. */
6760 if (reg_last_set_value
[REGNO (x
)] != 0
6761 && reg_last_set_mode
[REGNO (x
)] == mode
6762 && (reg_n_sets
[REGNO (x
)] == 1
6763 || reg_last_set_label
[REGNO (x
)] == label_tick
)
6764 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
6765 return reg_last_set_nonzero_bits
[REGNO (x
)];
6767 tem
= get_last_value (x
);
6771 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
6772 /* If X is narrower than MODE and TEM is a non-negative
6773 constant that would appear negative in the mode of X,
6774 sign-extend it for use in reg_nonzero_bits because some
6775 machines (maybe most) will actually do the sign-extension
6776 and this is the conservative approach.
6778 ??? For 2.5, try to tighten up the MD files in this regard
6779 instead of this kludge. */
6781 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
6782 && GET_CODE (tem
) == CONST_INT
6784 && 0 != (INTVAL (tem
)
6785 & ((HOST_WIDE_INT
) 1
6786 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
6787 tem
= GEN_INT (INTVAL (tem
)
6788 | ((HOST_WIDE_INT
) (-1)
6789 << GET_MODE_BITSIZE (GET_MODE (x
))));
6791 return nonzero_bits (tem
, mode
);
6793 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
6794 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
6799 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
6800 /* If X is negative in MODE, sign-extend the value. */
6801 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
6802 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
6803 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
6809 #ifdef LOAD_EXTEND_OP
6810 /* In many, if not most, RISC machines, reading a byte from memory
6811 zeros the rest of the register. Noticing that fact saves a lot
6812 of extra zero-extends. */
6813 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
6814 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
6824 /* If this produces an integer result, we know which bits are set.
6825 Code here used to clear bits outside the mode of X, but that is
6828 if (GET_MODE_CLASS (mode
) == MODE_INT
6829 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6830 nonzero
= STORE_FLAG_VALUE
;
6834 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
6835 == GET_MODE_BITSIZE (GET_MODE (x
)))
6838 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
6839 nonzero
|= (GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
)));
6843 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
6844 == GET_MODE_BITSIZE (GET_MODE (x
)))
6849 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
6853 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
6854 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
6855 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
6859 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
6860 Otherwise, show all the bits in the outer mode but not the inner
6862 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
6863 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
6865 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
6868 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
6869 inner_nz
|= (GET_MODE_MASK (mode
)
6870 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
6873 nonzero
&= inner_nz
;
6877 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
6878 & nonzero_bits (XEXP (x
, 1), mode
));
6882 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
6883 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
6884 | nonzero_bits (XEXP (x
, 1), mode
));
6887 case PLUS
: case MINUS
:
6889 case DIV
: case UDIV
:
6890 case MOD
: case UMOD
:
6891 /* We can apply the rules of arithmetic to compute the number of
6892 high- and low-order zero bits of these operations. We start by
6893 computing the width (position of the highest-order non-zero bit)
6894 and the number of low-order zero bits for each value. */
6896 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
6897 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
6898 int width0
= floor_log2 (nz0
) + 1;
6899 int width1
= floor_log2 (nz1
) + 1;
6900 int low0
= floor_log2 (nz0
& -nz0
);
6901 int low1
= floor_log2 (nz1
& -nz1
);
6902 HOST_WIDE_INT op0_maybe_minusp
6903 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
6904 HOST_WIDE_INT op1_maybe_minusp
6905 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
6906 int result_width
= mode_width
;
6912 result_width
= MAX (width0
, width1
) + 1;
6913 result_low
= MIN (low0
, low1
);
6916 result_low
= MIN (low0
, low1
);
6919 result_width
= width0
+ width1
;
6920 result_low
= low0
+ low1
;
6923 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
6924 result_width
= width0
;
6927 result_width
= width0
;
6930 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
6931 result_width
= MIN (width0
, width1
);
6932 result_low
= MIN (low0
, low1
);
6935 result_width
= MIN (width0
, width1
);
6936 result_low
= MIN (low0
, low1
);
6940 if (result_width
< mode_width
)
6941 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
6944 nonzero
&= ~ (((HOST_WIDE_INT
) 1 << result_low
) - 1);
6949 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6950 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
6951 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
6955 /* If this is a SUBREG formed for a promoted variable that has
6956 been zero-extended, we know that at least the high-order bits
6957 are zero, though others might be too. */
6959 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
6960 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
6961 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
6963 /* If the inner mode is a single word for both the host and target
6964 machines, we can compute this from which bits of the inner
6965 object might be nonzero. */
6966 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
6967 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
6968 <= HOST_BITS_PER_WIDE_INT
))
6970 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
6972 #ifndef WORD_REGISTER_OPERATIONS
6973 /* On many CISC machines, accessing an object in a wider mode
6974 causes the high-order bits to become undefined. So they are
6975 not known to be zero. */
6976 if (GET_MODE_SIZE (GET_MODE (x
))
6977 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6978 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
6979 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
6988 /* The nonzero bits are in two classes: any bits within MODE
6989 that aren't in GET_MODE (x) are always significant. The rest of the
6990 nonzero bits are those that are significant in the operand of
6991 the shift when shifted the appropriate number of bits. This
6992 shows that high-order bits are cleared by the right shift and
6993 low-order bits by left shifts. */
6994 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6995 && INTVAL (XEXP (x
, 1)) >= 0
6996 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
6998 enum machine_mode inner_mode
= GET_MODE (x
);
6999 int width
= GET_MODE_BITSIZE (inner_mode
);
7000 int count
= INTVAL (XEXP (x
, 1));
7001 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
7002 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
7003 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
7004 unsigned HOST_WIDE_INT outer
= 0;
7006 if (mode_width
> width
)
7007 outer
= (op_nonzero
& nonzero
& ~ mode_mask
);
7009 if (code
== LSHIFTRT
)
7011 else if (code
== ASHIFTRT
)
7015 /* If the sign bit may have been nonzero before the shift, we
7016 need to mark all the places it could have been copied to
7017 by the shift as possibly nonzero. */
7018 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
7019 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
7021 else if (code
== ASHIFT
)
7024 inner
= ((inner
<< (count
% width
)
7025 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
7027 nonzero
&= (outer
| inner
);
7032 /* This is at most the number of bits in the mode. */
7033 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
7037 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
7038 | nonzero_bits (XEXP (x
, 2), mode
));
7045 /* Return the number of bits at the high-order end of X that are known to
7046 be equal to the sign bit. X will be used in mode MODE; if MODE is
7047 VOIDmode, X will be used in its own mode. The returned value will always
7048 be between 1 and the number of bits in MODE. */
7051 num_sign_bit_copies (x
, mode
)
7053 enum machine_mode mode
;
7055 enum rtx_code code
= GET_CODE (x
);
7057 int num0
, num1
, result
;
7058 unsigned HOST_WIDE_INT nonzero
;
7061 /* If we weren't given a mode, use the mode of X. If the mode is still
7062 VOIDmode, we don't know anything. Likewise if one of the modes is
7065 if (mode
== VOIDmode
)
7066 mode
= GET_MODE (x
);
7068 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
7071 bitwidth
= GET_MODE_BITSIZE (mode
);
7073 /* For a smaller object, just ignore the high bits. */
7074 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
7075 return MAX (1, (num_sign_bit_copies (x
, GET_MODE (x
))
7076 - (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
)));
7078 #ifndef WORD_REGISTER_OPERATIONS
7079 /* If this machine does not do all register operations on the entire
7080 register and MODE is wider than the mode of X, we can say nothing
7081 at all about the high-order bits. */
7082 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
7090 if (reg_last_set_value
[REGNO (x
)] != 0
7091 && reg_last_set_mode
[REGNO (x
)] == mode
7092 && (reg_n_sets
[REGNO (x
)] == 1
7093 || reg_last_set_label
[REGNO (x
)] == label_tick
)
7094 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
7095 return reg_last_set_sign_bit_copies
[REGNO (x
)];
7097 tem
= get_last_value (x
);
7099 return num_sign_bit_copies (tem
, mode
);
7101 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
7102 return reg_sign_bit_copies
[REGNO (x
)];
7106 #ifdef LOAD_EXTEND_OP
7107 /* Some RISC machines sign-extend all loads of smaller than a word. */
7108 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
7109 return MAX (1, bitwidth
- GET_MODE_BITSIZE (GET_MODE (x
)) + 1);
7114 /* If the constant is negative, take its 1's complement and remask.
7115 Then see how many zero bits we have. */
7116 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
7117 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
7118 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
7119 nonzero
= (~ nonzero
) & GET_MODE_MASK (mode
);
7121 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
7124 /* If this is a SUBREG for a promoted object that is sign-extended
7125 and we are looking at it in a wider mode, we know that at least the
7126 high-order bits are known to be sign bit copies. */
7128 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
7129 return MAX (bitwidth
- GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
7130 num_sign_bit_copies (SUBREG_REG (x
), mode
));
7132 /* For a smaller object, just ignore the high bits. */
7133 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
7135 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
7136 return MAX (1, (num0
7137 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
7141 #ifdef WORD_REGISTER_OPERATIONS
7142 /* For paradoxical SUBREGs on machines where all register operations
7143 affect the entire register, just look inside. Note that we are
7144 passing MODE to the recursive call, so the number of sign bit copies
7145 will remain relative to that mode, not the inner mode. */
7147 if (GET_MODE_SIZE (GET_MODE (x
))
7148 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7149 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
7154 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7155 return MAX (1, bitwidth
- INTVAL (XEXP (x
, 1)));
7159 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
7160 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
7163 /* For a smaller object, just ignore the high bits. */
7164 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
7165 return MAX (1, (num0
- (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
7169 return num_sign_bit_copies (XEXP (x
, 0), mode
);
7171 case ROTATE
: case ROTATERT
:
7172 /* If we are rotating left by a number of bits less than the number
7173 of sign bit copies, we can just subtract that amount from the
7175 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7176 && INTVAL (XEXP (x
, 1)) >= 0 && INTVAL (XEXP (x
, 1)) < bitwidth
)
7178 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7179 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
7180 : bitwidth
- INTVAL (XEXP (x
, 1))));
7185 /* In general, this subtracts one sign bit copy. But if the value
7186 is known to be positive, the number of sign bit copies is the
7187 same as that of the input. Finally, if the input has just one bit
7188 that might be nonzero, all the bits are copies of the sign bit. */
7189 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
7193 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7195 && bitwidth
<= HOST_BITS_PER_WIDE_INT
7196 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
7201 case IOR
: case AND
: case XOR
:
7202 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
7203 /* Logical operations will preserve the number of sign-bit copies.
7204 MIN and MAX operations always return one of the operands. */
7205 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7206 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
7207 return MIN (num0
, num1
);
7209 case PLUS
: case MINUS
:
7210 /* For addition and subtraction, we can have a 1-bit carry. However,
7211 if we are subtracting 1 from a positive number, there will not
7212 be such a carry. Furthermore, if the positive number is known to
7213 be 0 or 1, we know the result is either -1 or 0. */
7215 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
7216 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
7218 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
7219 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
7220 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
7221 : bitwidth
- floor_log2 (nonzero
) - 1);
7224 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7225 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
7226 return MAX (1, MIN (num0
, num1
) - 1);
7229 /* The number of bits of the product is the sum of the number of
7230 bits of both terms. However, unless one of the terms if known
7231 to be positive, we must allow for an additional bit since negating
7232 a negative number can remove one sign bit copy. */
7234 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7235 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
7237 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
7239 && bitwidth
<= HOST_BITS_PER_WIDE_INT
7240 && ((nonzero_bits (XEXP (x
, 0), mode
)
7241 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
7242 && (nonzero_bits (XEXP (x
, 1), mode
)
7243 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) != 0))
7246 return MAX (1, result
);
7249 /* The result must be <= the first operand. */
7250 return num_sign_bit_copies (XEXP (x
, 0), mode
);
7253 /* The result must be <= the scond operand. */
7254 return num_sign_bit_copies (XEXP (x
, 1), mode
);
7257 /* Similar to unsigned division, except that we have to worry about
7258 the case where the divisor is negative, in which case we have
7260 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7262 && bitwidth
<= HOST_BITS_PER_WIDE_INT
7263 && (nonzero_bits (XEXP (x
, 1), mode
)
7264 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
7270 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
7272 && bitwidth
<= HOST_BITS_PER_WIDE_INT
7273 && (nonzero_bits (XEXP (x
, 1), mode
)
7274 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
7280 /* Shifts by a constant add to the number of bits equal to the
7282 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7283 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7284 && INTVAL (XEXP (x
, 1)) > 0)
7285 num0
= MIN (bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
7290 /* Left shifts destroy copies. */
7291 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7292 || INTVAL (XEXP (x
, 1)) < 0
7293 || INTVAL (XEXP (x
, 1)) >= bitwidth
)
7296 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
7297 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
7300 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
7301 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
7302 return MIN (num0
, num1
);
7304 #if STORE_FLAG_VALUE == -1
7305 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
7306 case GEU
: case GTU
: case LEU
: case LTU
:
7311 /* If we haven't been able to figure it out by one of the above rules,
7312 see if some of the high-order bits are known to be zero. If so,
7313 count those bits and return one less than that amount. If we can't
7314 safely compute the mask for this mode, always return BITWIDTH. */
7316 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
7319 nonzero
= nonzero_bits (x
, mode
);
7320 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
7321 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
7324 /* Return the number of "extended" bits there are in X, when interpreted
7325 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
7326 unsigned quantities, this is the number of high-order zero bits.
7327 For signed quantities, this is the number of copies of the sign bit
7328 minus 1. In both case, this function returns the number of "spare"
7329 bits. For example, if two quantities for which this function returns
7330 at least 1 are added, the addition is known not to overflow.
7332 This function will always return 0 unless called during combine, which
7333 implies that it must be called from a define_split. */
7336 extended_count (x
, mode
, unsignedp
)
7338 enum machine_mode mode
;
7341 if (nonzero_sign_valid
== 0)
7345 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7346 && (GET_MODE_BITSIZE (mode
) - 1
7347 - floor_log2 (nonzero_bits (x
, mode
))))
7348 : num_sign_bit_copies (x
, mode
) - 1);
7351 /* This function is called from `simplify_shift_const' to merge two
7352 outer operations. Specifically, we have already found that we need
7353 to perform operation *POP0 with constant *PCONST0 at the outermost
7354 position. We would now like to also perform OP1 with constant CONST1
7355 (with *POP0 being done last).
7357 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7358 the resulting operation. *PCOMP_P is set to 1 if we would need to
7359 complement the innermost operand, otherwise it is unchanged.
7361 MODE is the mode in which the operation will be done. No bits outside
7362 the width of this mode matter. It is assumed that the width of this mode
7363 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7365 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
7366 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
7367 result is simply *PCONST0.
7369 If the resulting operation cannot be expressed as one operation, we
7370 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
7373 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
7374 enum rtx_code
*pop0
;
7375 HOST_WIDE_INT
*pconst0
;
7377 HOST_WIDE_INT const1
;
7378 enum machine_mode mode
;
7381 enum rtx_code op0
= *pop0
;
7382 HOST_WIDE_INT const0
= *pconst0
;
7384 const0
&= GET_MODE_MASK (mode
);
7385 const1
&= GET_MODE_MASK (mode
);
7387 /* If OP0 is an AND, clear unimportant bits in CONST1. */
7391 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
7394 if (op1
== NIL
|| op0
== SET
)
7397 else if (op0
== NIL
)
7398 op0
= op1
, const0
= const1
;
7400 else if (op0
== op1
)
7422 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
7423 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
7426 /* If the two constants aren't the same, we can't do anything. The
7427 remaining six cases can all be done. */
7428 else if (const0
!= const1
)
7436 /* (a & b) | b == b */
7438 else /* op1 == XOR */
7439 /* (a ^ b) | b == a | b */
7445 /* (a & b) ^ b == (~a) & b */
7446 op0
= AND
, *pcomp_p
= 1;
7447 else /* op1 == IOR */
7448 /* (a | b) ^ b == a & ~b */
7449 op0
= AND
, *pconst0
= ~ const0
;
7454 /* (a | b) & b == b */
7456 else /* op1 == XOR */
7457 /* (a ^ b) & b) == (~a) & b */
7462 /* Check for NO-OP cases. */
7463 const0
&= GET_MODE_MASK (mode
);
7465 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
7467 else if (const0
== 0 && op0
== AND
)
7469 else if (const0
== GET_MODE_MASK (mode
) && op0
== AND
)
7478 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
7479 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
7480 that we started with.
7482 The shift is normally computed in the widest mode we find in VAROP, as
7483 long as it isn't a different number of words than RESULT_MODE. Exceptions
7484 are ASHIFTRT and ROTATE, which are always done in their original mode, */
7487 simplify_shift_const (x
, code
, result_mode
, varop
, count
)
7490 enum machine_mode result_mode
;
7494 enum rtx_code orig_code
= code
;
7495 int orig_count
= count
;
7496 enum machine_mode mode
= result_mode
;
7497 enum machine_mode shift_mode
, tmode
;
7499 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
7500 /* We form (outer_op (code varop count) (outer_const)). */
7501 enum rtx_code outer_op
= NIL
;
7502 HOST_WIDE_INT outer_const
= 0;
7504 int complement_p
= 0;
7507 /* If we were given an invalid count, don't do anything except exactly
7508 what was requested. */
7510 if (count
< 0 || count
> GET_MODE_BITSIZE (mode
))
7515 return gen_rtx (code
, mode
, varop
, GEN_INT (count
));
7518 /* Unless one of the branches of the `if' in this loop does a `continue',
7519 we will `break' the loop after the `if'. */
7523 /* If we have an operand of (clobber (const_int 0)), just return that
7525 if (GET_CODE (varop
) == CLOBBER
)
7528 /* If we discovered we had to complement VAROP, leave. Making a NOT
7529 here would cause an infinite loop. */
7533 /* Convert ROTATETRT to ROTATE. */
7534 if (code
== ROTATERT
)
7535 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
7537 /* We need to determine what mode we will do the shift in. If the
7538 shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
7539 was originally done in. Otherwise, we can do it in MODE, the widest
7540 mode encountered. */
7541 shift_mode
= (code
== ASHIFTRT
|| code
== ROTATE
? result_mode
: mode
);
7543 /* Handle cases where the count is greater than the size of the mode
7544 minus 1. For ASHIFT, use the size minus one as the count (this can
7545 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
7546 take the count modulo the size. For other shifts, the result is
7549 Since these shifts are being produced by the compiler by combining
7550 multiple operations, each of which are defined, we know what the
7551 result is supposed to be. */
7553 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
7555 if (code
== ASHIFTRT
)
7556 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
7557 else if (code
== ROTATE
|| code
== ROTATERT
)
7558 count
%= GET_MODE_BITSIZE (shift_mode
);
7561 /* We can't simply return zero because there may be an
7569 /* Negative counts are invalid and should not have been made (a
7570 programmer-specified negative count should have been handled
7575 /* An arithmetic right shift of a quantity known to be -1 or 0
7577 if (code
== ASHIFTRT
7578 && (num_sign_bit_copies (varop
, shift_mode
)
7579 == GET_MODE_BITSIZE (shift_mode
)))
7585 /* If we are doing an arithmetic right shift and discarding all but
7586 the sign bit copies, this is equivalent to doing a shift by the
7587 bitsize minus one. Convert it into that shift because it will often
7588 allow other simplifications. */
7590 if (code
== ASHIFTRT
7591 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
7592 >= GET_MODE_BITSIZE (shift_mode
)))
7593 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
7595 /* We simplify the tests below and elsewhere by converting
7596 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
7597 `make_compound_operation' will convert it to a ASHIFTRT for
7598 those machines (such as Vax) that don't have a LSHIFTRT. */
7599 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
7601 && ((nonzero_bits (varop
, shift_mode
)
7602 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
7606 switch (GET_CODE (varop
))
7612 new = expand_compound_operation (varop
);
7621 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
7622 minus the width of a smaller mode, we can do this with a
7623 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
7624 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
7625 && ! mode_dependent_address_p (XEXP (varop
, 0))
7626 && ! MEM_VOLATILE_P (varop
)
7627 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
7628 MODE_INT
, 1)) != BLKmode
)
7630 if (BYTES_BIG_ENDIAN
)
7631 new = gen_rtx (MEM
, tmode
, XEXP (varop
, 0));
7634 new = gen_rtx (MEM
, tmode
,
7635 plus_constant (XEXP (varop
, 0),
7636 count
/ BITS_PER_UNIT
));
7637 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop
);
7638 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop
);
7639 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop
);
7641 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
7642 : ZERO_EXTEND
, mode
, new);
7649 /* Similar to the case above, except that we can only do this if
7650 the resulting mode is the same as that of the underlying
7651 MEM and adjust the address depending on the *bits* endianness
7652 because of the way that bit-field extract insns are defined. */
7653 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
7654 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
7655 MODE_INT
, 1)) != BLKmode
7656 && tmode
== GET_MODE (XEXP (varop
, 0)))
7658 if (BITS_BIG_ENDIAN
)
7659 new = XEXP (varop
, 0);
7662 new = copy_rtx (XEXP (varop
, 0));
7663 SUBST (XEXP (new, 0),
7664 plus_constant (XEXP (new, 0),
7665 count
/ BITS_PER_UNIT
));
7668 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
7669 : ZERO_EXTEND
, mode
, new);
7676 /* If VAROP is a SUBREG, strip it as long as the inner operand has
7677 the same number of words as what we've seen so far. Then store
7678 the widest mode in MODE. */
7679 if (subreg_lowpart_p (varop
)
7680 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
7681 > GET_MODE_SIZE (GET_MODE (varop
)))
7682 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
7683 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7686 varop
= SUBREG_REG (varop
);
7687 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
7688 mode
= GET_MODE (varop
);
7694 /* Some machines use MULT instead of ASHIFT because MULT
7695 is cheaper. But it is still better on those machines to
7696 merge two shifts into one. */
7697 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
7698 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
7700 varop
= gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
7701 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));;
7707 /* Similar, for when divides are cheaper. */
7708 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
7709 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
7711 varop
= gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
7712 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
7718 /* If we are extracting just the sign bit of an arithmetic right
7719 shift, that shift is not needed. */
7720 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1)
7722 varop
= XEXP (varop
, 0);
7726 /* ... fall through ... */
7731 /* Here we have two nested shifts. The result is usually the
7732 AND of a new shift with a mask. We compute the result below. */
7733 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
7734 && INTVAL (XEXP (varop
, 1)) >= 0
7735 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
7736 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
7737 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
7739 enum rtx_code first_code
= GET_CODE (varop
);
7740 int first_count
= INTVAL (XEXP (varop
, 1));
7741 unsigned HOST_WIDE_INT mask
;
7744 /* We have one common special case. We can't do any merging if
7745 the inner code is an ASHIFTRT of a smaller mode. However, if
7746 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
7747 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
7748 we can convert it to
7749 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
7750 This simplifies certain SIGN_EXTEND operations. */
7751 if (code
== ASHIFT
&& first_code
== ASHIFTRT
7752 && (GET_MODE_BITSIZE (result_mode
)
7753 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
7755 /* C3 has the low-order C1 bits zero. */
7757 mask
= (GET_MODE_MASK (mode
)
7758 & ~ (((HOST_WIDE_INT
) 1 << first_count
) - 1));
7760 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
7761 XEXP (varop
, 0), mask
);
7762 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
7764 count
= first_count
;
7769 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
7770 than C1 high-order bits equal to the sign bit, we can convert
7771 this to either an ASHIFT or a ASHIFTRT depending on the
7774 We cannot do this if VAROP's mode is not SHIFT_MODE. */
7776 if (code
== ASHIFTRT
&& first_code
== ASHIFT
7777 && GET_MODE (varop
) == shift_mode
7778 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
7781 count
-= first_count
;
7783 count
= - count
, code
= ASHIFT
;
7784 varop
= XEXP (varop
, 0);
7788 /* There are some cases we can't do. If CODE is ASHIFTRT,
7789 we can only do this if FIRST_CODE is also ASHIFTRT.
7791 We can't do the case when CODE is ROTATE and FIRST_CODE is
7794 If the mode of this shift is not the mode of the outer shift,
7795 we can't do this if either shift is ASHIFTRT or ROTATE.
7797 Finally, we can't do any of these if the mode is too wide
7798 unless the codes are the same.
7800 Handle the case where the shift codes are the same
7803 if (code
== first_code
)
7805 if (GET_MODE (varop
) != result_mode
7806 && (code
== ASHIFTRT
|| code
== ROTATE
))
7809 count
+= first_count
;
7810 varop
= XEXP (varop
, 0);
7814 if (code
== ASHIFTRT
7815 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
7816 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
7817 || (GET_MODE (varop
) != result_mode
7818 && (first_code
== ASHIFTRT
|| first_code
== ROTATE
7819 || code
== ROTATE
)))
7822 /* To compute the mask to apply after the shift, shift the
7823 nonzero bits of the inner shift the same way the
7824 outer shift will. */
7826 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
7829 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
7832 /* Give up if we can't compute an outer operation to use. */
7834 || GET_CODE (mask_rtx
) != CONST_INT
7835 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
7837 result_mode
, &complement_p
))
7840 /* If the shifts are in the same direction, we add the
7841 counts. Otherwise, we subtract them. */
7842 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
7843 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
7844 count
+= first_count
;
7846 count
-= first_count
;
7848 /* If COUNT is positive, the new shift is usually CODE,
7849 except for the two exceptions below, in which case it is
7850 FIRST_CODE. If the count is negative, FIRST_CODE should
7853 && ((first_code
== ROTATE
&& code
== ASHIFT
)
7854 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
7857 code
= first_code
, count
= - count
;
7859 varop
= XEXP (varop
, 0);
7863 /* If we have (A << B << C) for any shift, we can convert this to
7864 (A << C << B). This wins if A is a constant. Only try this if
7865 B is not a constant. */
7867 else if (GET_CODE (varop
) == code
7868 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
7870 = simplify_binary_operation (code
, mode
,
7874 varop
= gen_rtx_combine (code
, mode
, new, XEXP (varop
, 1));
7881 /* Make this fit the case below. */
7882 varop
= gen_rtx_combine (XOR
, mode
, XEXP (varop
, 0),
7883 GEN_INT (GET_MODE_MASK (mode
)));
7889 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
7890 with C the size of VAROP - 1 and the shift is logical if
7891 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7892 we have an (le X 0) operation. If we have an arithmetic shift
7893 and STORE_FLAG_VALUE is 1 or we have a logical shift with
7894 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
7896 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
7897 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
7898 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7899 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
7900 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
7901 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
7904 varop
= gen_rtx_combine (LE
, GET_MODE (varop
), XEXP (varop
, 1),
7907 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
7908 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
7913 /* If we have (shift (logical)), move the logical to the outside
7914 to allow it to possibly combine with another logical and the
7915 shift to combine with another shift. This also canonicalizes to
7916 what a ZERO_EXTRACT looks like. Also, some machines have
7917 (and (shift)) insns. */
7919 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
7920 && (new = simplify_binary_operation (code
, result_mode
,
7922 GEN_INT (count
))) != 0
7923 && GET_CODE(new) == CONST_INT
7924 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
7925 INTVAL (new), result_mode
, &complement_p
))
7927 varop
= XEXP (varop
, 0);
7931 /* If we can't do that, try to simplify the shift in each arm of the
7932 logical expression, make a new logical expression, and apply
7933 the inverse distributive law. */
7935 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
7936 XEXP (varop
, 0), count
);
7937 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
7938 XEXP (varop
, 1), count
);
7940 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
7941 varop
= apply_distributive_law (varop
);
7948 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
7949 says that the sign bit can be tested, FOO has mode MODE, C is
7950 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
7951 that may be nonzero. */
7952 if (code
== LSHIFTRT
7953 && XEXP (varop
, 1) == const0_rtx
7954 && GET_MODE (XEXP (varop
, 0)) == result_mode
7955 && count
== GET_MODE_BITSIZE (result_mode
) - 1
7956 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
7957 && ((STORE_FLAG_VALUE
7958 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (result_mode
) - 1))))
7959 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
7960 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
7961 (HOST_WIDE_INT
) 1, result_mode
,
7964 varop
= XEXP (varop
, 0);
7971 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
7972 than the number of bits in the mode is equivalent to A. */
7973 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
7974 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
7976 varop
= XEXP (varop
, 0);
7981 /* NEG commutes with ASHIFT since it is multiplication. Move the
7982 NEG outside to allow shifts to combine. */
7984 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
7985 (HOST_WIDE_INT
) 0, result_mode
,
7988 varop
= XEXP (varop
, 0);
7994 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
7995 is one less than the number of bits in the mode is
7996 equivalent to (xor A 1). */
7997 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
7998 && XEXP (varop
, 1) == constm1_rtx
7999 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
8000 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
8001 (HOST_WIDE_INT
) 1, result_mode
,
8005 varop
= XEXP (varop
, 0);
8009 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8010 that might be nonzero in BAR are those being shifted out and those
8011 bits are known zero in FOO, we can replace the PLUS with FOO.
8012 Similarly in the other operand order. This code occurs when
8013 we are computing the size of a variable-size array. */
8015 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8016 && count
< HOST_BITS_PER_WIDE_INT
8017 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
8018 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
8019 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
8021 varop
= XEXP (varop
, 0);
8024 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8025 && count
< HOST_BITS_PER_WIDE_INT
8026 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8027 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
8029 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
8030 & nonzero_bits (XEXP (varop
, 1),
8033 varop
= XEXP (varop
, 1);
8037 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8039 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
8040 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
8042 GEN_INT (count
))) != 0
8043 && GET_CODE(new) == CONST_INT
8044 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
8045 INTVAL (new), result_mode
, &complement_p
))
8047 varop
= XEXP (varop
, 0);
8053 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8054 with C the size of VAROP - 1 and the shift is logical if
8055 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8056 we have a (gt X 0) operation. If the shift is arithmetic with
8057 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8058 we have a (neg (gt X 0)) operation. */
8060 if (GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
8061 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
8062 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8063 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
8064 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
8065 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
8066 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
8069 varop
= gen_rtx_combine (GT
, GET_MODE (varop
), XEXP (varop
, 1),
8072 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
8073 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
8083 /* We need to determine what mode to do the shift in. If the shift is
8084 a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
8085 done in. Otherwise, we can do it in MODE, the widest mode encountered.
8086 The code we care about is that of the shift that will actually be done,
8087 not the shift that was originally requested. */
8088 shift_mode
= (code
== ASHIFTRT
|| code
== ROTATE
? result_mode
: mode
);
8090 /* We have now finished analyzing the shift. The result should be
8091 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8092 OUTER_OP is non-NIL, it is an operation that needs to be applied
8093 to the result of the shift. OUTER_CONST is the relevant constant,
8094 but we must turn off all bits turned off in the shift.
8096 If we were passed a value for X, see if we can use any pieces of
8097 it. If not, make new rtx. */
8099 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
8100 && GET_CODE (XEXP (x
, 1)) == CONST_INT
8101 && INTVAL (XEXP (x
, 1)) == count
)
8102 const_rtx
= XEXP (x
, 1);
8104 const_rtx
= GEN_INT (count
);
8106 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8107 && GET_MODE (XEXP (x
, 0)) == shift_mode
8108 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8109 varop
= XEXP (x
, 0);
8110 else if (GET_MODE (varop
) != shift_mode
)
8111 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
8113 /* If we can't make the SUBREG, try to return what we were given. */
8114 if (GET_CODE (varop
) == CLOBBER
)
8115 return x
? x
: varop
;
8117 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
8122 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
8123 x
= gen_rtx_combine (code
, shift_mode
, varop
, const_rtx
);
8125 SUBST (XEXP (x
, 0), varop
);
8126 SUBST (XEXP (x
, 1), const_rtx
);
8129 /* If we have an outer operation and we just made a shift, it is
8130 possible that we could have simplified the shift were it not
8131 for the outer operation. So try to do the simplification
8134 if (outer_op
!= NIL
&& GET_CODE (x
) == code
8135 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8136 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
8137 INTVAL (XEXP (x
, 1)));
8139 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8140 turn off all the bits that the shift would have turned off. */
8141 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
8142 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
8143 GET_MODE_MASK (result_mode
) >> orig_count
);
8145 /* Do the remainder of the processing in RESULT_MODE. */
8146 x
= gen_lowpart_for_combine (result_mode
, x
);
8148 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8151 x
= gen_unary (NOT
, result_mode
, result_mode
, x
);
8153 if (outer_op
!= NIL
)
8155 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
8156 outer_const
&= GET_MODE_MASK (result_mode
);
8158 if (outer_op
== AND
)
8159 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
8160 else if (outer_op
== SET
)
8161 /* This means that we have determined that the result is
8162 equivalent to a constant. This should be rare. */
8163 x
= GEN_INT (outer_const
);
8164 else if (GET_RTX_CLASS (outer_op
) == '1')
8165 x
= gen_unary (outer_op
, result_mode
, result_mode
, x
);
8167 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
8173 /* Like recog, but we receive the address of a pointer to a new pattern.
8174 We try to match the rtx that the pointer points to.
8175 If that fails, we may try to modify or replace the pattern,
8176 storing the replacement into the same pointer object.
8178 Modifications include deletion or addition of CLOBBERs.
8180 PNOTES is a pointer to a location where any REG_UNUSED notes added for
8181 the CLOBBERs are placed.
8183 The value is the final insn code from the pattern ultimately matched,
8187 recog_for_combine (pnewpat
, insn
, pnotes
)
8192 register rtx pat
= *pnewpat
;
8193 int insn_code_number
;
8194 int num_clobbers_to_add
= 0;
8198 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
8199 we use to indicate that something didn't match. If we find such a
8200 thing, force rejection. */
8201 if (GET_CODE (pat
) == PARALLEL
)
8202 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
8203 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
8204 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
8207 /* Is the result of combination a valid instruction? */
8208 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
8210 /* If it isn't, there is the possibility that we previously had an insn
8211 that clobbered some register as a side effect, but the combined
8212 insn doesn't need to do that. So try once more without the clobbers
8213 unless this represents an ASM insn. */
8215 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
8216 && GET_CODE (pat
) == PARALLEL
)
8220 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
8221 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
8224 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
8228 SUBST_INT (XVECLEN (pat
, 0), pos
);
8231 pat
= XVECEXP (pat
, 0, 0);
8233 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
8236 /* If we had any clobbers to add, make a new pattern than contains
8237 them. Then check to make sure that all of them are dead. */
8238 if (num_clobbers_to_add
)
8240 rtx newpat
= gen_rtx (PARALLEL
, VOIDmode
,
8241 gen_rtvec (GET_CODE (pat
) == PARALLEL
8242 ? XVECLEN (pat
, 0) + num_clobbers_to_add
8243 : num_clobbers_to_add
+ 1));
8245 if (GET_CODE (pat
) == PARALLEL
)
8246 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
8247 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
8249 XVECEXP (newpat
, 0, 0) = pat
;
8251 add_clobbers (newpat
, insn_code_number
);
8253 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
8254 i
< XVECLEN (newpat
, 0); i
++)
8256 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
8257 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
8259 notes
= gen_rtx (EXPR_LIST
, REG_UNUSED
,
8260 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
8268 return insn_code_number
;
8271 /* Like gen_lowpart but for use by combine. In combine it is not possible
8272 to create any new pseudoregs. However, it is safe to create
8273 invalid memory addresses, because combine will try to recognize
8274 them and all they will do is make the combine attempt fail.
8276 If for some reason this cannot do its job, an rtx
8277 (clobber (const_int 0)) is returned.
8278 An insn containing that will not be recognized. */
8283 gen_lowpart_for_combine (mode
, x
)
8284 enum machine_mode mode
;
8289 if (GET_MODE (x
) == mode
)
8292 /* We can only support MODE being wider than a word if X is a
8293 constant integer or has a mode the same size. */
8295 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
8296 && ! ((GET_MODE (x
) == VOIDmode
8297 && (GET_CODE (x
) == CONST_INT
8298 || GET_CODE (x
) == CONST_DOUBLE
))
8299 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
8300 return gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
8302 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
8303 won't know what to do. So we will strip off the SUBREG here and
8304 process normally. */
8305 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
8308 if (GET_MODE (x
) == mode
)
8312 result
= gen_lowpart_common (mode
, x
);
8316 if (GET_CODE (x
) == MEM
)
8318 register int offset
= 0;
8321 /* Refuse to work on a volatile memory ref or one with a mode-dependent
8323 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
8324 return gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
8326 /* If we want to refer to something bigger than the original memref,
8327 generate a perverse subreg instead. That will force a reload
8328 of the original memref X. */
8329 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
8330 return gen_rtx (SUBREG
, mode
, x
, 0);
8332 if (WORDS_BIG_ENDIAN
)
8333 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
8334 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
8335 if (BYTES_BIG_ENDIAN
)
8337 /* Adjust the address so that the address-after-the-data is
8339 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
8340 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
8342 new = gen_rtx (MEM
, mode
, plus_constant (XEXP (x
, 0), offset
));
8343 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x
);
8344 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x
);
8345 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x
);
8349 /* If X is a comparison operator, rewrite it in a new mode. This
8350 probably won't match, but may allow further simplifications. */
8351 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
8352 return gen_rtx_combine (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
8354 /* If we couldn't simplify X any other way, just enclose it in a
8355 SUBREG. Normally, this SUBREG won't match, but some patterns may
8356 include an explicit SUBREG or we may simplify it further in combine. */
8361 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
8362 word
= ((GET_MODE_SIZE (GET_MODE (x
))
8363 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
8365 return gen_rtx (SUBREG
, mode
, x
, word
);
8369 /* Make an rtx expression. This is a subset of gen_rtx and only supports
8370 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
8372 If the identical expression was previously in the insn (in the undobuf),
8373 it will be returned. Only if it is not found will a new expression
8378 gen_rtx_combine
VPROTO((enum rtx_code code
, enum machine_mode mode
, ...))
8382 enum machine_mode mode
;
8394 code
= va_arg (p
, enum rtx_code
);
8395 mode
= va_arg (p
, enum machine_mode
);
8398 n_args
= GET_RTX_LENGTH (code
);
8399 fmt
= GET_RTX_FORMAT (code
);
8401 if (n_args
== 0 || n_args
> 3)
8404 /* Get each arg and verify that it is supposed to be an expression. */
8405 for (j
= 0; j
< n_args
; j
++)
8410 args
[j
] = va_arg (p
, rtx
);
8413 /* See if this is in undobuf. Be sure we don't use objects that came
8414 from another insn; this could produce circular rtl structures. */
8416 for (i
= previous_num_undos
; i
< undobuf
.num_undo
; i
++)
8417 if (!undobuf
.undo
[i
].is_int
8418 && GET_CODE (undobuf
.undo
[i
].old_contents
.r
) == code
8419 && GET_MODE (undobuf
.undo
[i
].old_contents
.r
) == mode
)
8421 for (j
= 0; j
< n_args
; j
++)
8422 if (XEXP (undobuf
.undo
[i
].old_contents
.r
, j
) != args
[j
])
8426 return undobuf
.undo
[i
].old_contents
.r
;
8429 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
8430 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
8431 rt
= rtx_alloc (code
);
8432 PUT_MODE (rt
, mode
);
8433 XEXP (rt
, 0) = args
[0];
8436 XEXP (rt
, 1) = args
[1];
8438 XEXP (rt
, 2) = args
[2];
8443 /* These routines make binary and unary operations by first seeing if they
8444 fold; if not, a new expression is allocated. */
8447 gen_binary (code
, mode
, op0
, op1
)
8449 enum machine_mode mode
;
8455 if (GET_RTX_CLASS (code
) == 'c'
8456 && (GET_CODE (op0
) == CONST_INT
8457 || (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)))
8458 tem
= op0
, op0
= op1
, op1
= tem
;
8460 if (GET_RTX_CLASS (code
) == '<')
8462 enum machine_mode op_mode
= GET_MODE (op0
);
8464 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
8465 just (REL_OP X Y). */
8466 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
8468 op1
= XEXP (op0
, 1);
8469 op0
= XEXP (op0
, 0);
8470 op_mode
= GET_MODE (op0
);
8473 if (op_mode
== VOIDmode
)
8474 op_mode
= GET_MODE (op1
);
8475 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
8478 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
8483 /* Put complex operands first and constants second. */
8484 if (GET_RTX_CLASS (code
) == 'c'
8485 && ((CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
8486 || (GET_RTX_CLASS (GET_CODE (op0
)) == 'o'
8487 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')
8488 || (GET_CODE (op0
) == SUBREG
8489 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0
))) == 'o'
8490 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')))
8491 return gen_rtx_combine (code
, mode
, op1
, op0
);
8493 return gen_rtx_combine (code
, mode
, op0
, op1
);
8497 gen_unary (code
, mode
, op0_mode
, op0
)
8499 enum machine_mode mode
, op0_mode
;
8502 rtx result
= simplify_unary_operation (code
, mode
, op0
, op0_mode
);
8507 return gen_rtx_combine (code
, mode
, op0
);
8510 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
8511 comparison code that will be tested.
8513 The result is a possibly different comparison code to use. *POP0 and
8514 *POP1 may be updated.
8516 It is possible that we might detect that a comparison is either always
8517 true or always false. However, we do not perform general constant
8518 folding in combine, so this knowledge isn't useful. Such tautologies
8519 should have been detected earlier. Hence we ignore all such cases. */
8521 static enum rtx_code
8522 simplify_comparison (code
, pop0
, pop1
)
8531 enum machine_mode mode
, tmode
;
8533 /* Try a few ways of applying the same transformation to both operands. */
8536 #ifndef WORD_REGISTER_OPERATIONS
8537 /* The test below this one won't handle SIGN_EXTENDs on these machines,
8538 so check specially. */
8539 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
8540 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
8541 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
8542 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
8543 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
8544 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
8545 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
8546 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
8547 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
8548 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
8549 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
8550 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
8551 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
8552 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
8553 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
8554 && (INTVAL (XEXP (op0
, 1))
8555 == (GET_MODE_BITSIZE (GET_MODE (op0
))
8557 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
8559 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
8560 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
8564 /* If both operands are the same constant shift, see if we can ignore the
8565 shift. We can if the shift is a rotate or if the bits shifted out of
8566 this shift are known to be zero for both inputs and if the type of
8567 comparison is compatible with the shift. */
8568 if (GET_CODE (op0
) == GET_CODE (op1
)
8569 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
8570 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
8571 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
8572 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
8573 || (GET_CODE (op0
) == ASHIFTRT
8574 && (code
!= GTU
&& code
!= LTU
8575 && code
!= GEU
&& code
!= GEU
)))
8576 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
8577 && INTVAL (XEXP (op0
, 1)) >= 0
8578 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
8579 && XEXP (op0
, 1) == XEXP (op1
, 1))
8581 enum machine_mode mode
= GET_MODE (op0
);
8582 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8583 int shift_count
= INTVAL (XEXP (op0
, 1));
8585 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
8586 mask
&= (mask
>> shift_count
) << shift_count
;
8587 else if (GET_CODE (op0
) == ASHIFT
)
8588 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
8590 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~ mask
) == 0
8591 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~ mask
) == 0)
8592 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
8597 /* If both operands are AND's of a paradoxical SUBREG by constant, the
8598 SUBREGs are of the same mode, and, in both cases, the AND would
8599 be redundant if the comparison was done in the narrower mode,
8600 do the comparison in the narrower mode (e.g., we are AND'ing with 1
8601 and the operand's possibly nonzero bits are 0xffffff01; in that case
8602 if we only care about QImode, we don't need the AND). This case
8603 occurs if the output mode of an scc insn is not SImode and
8604 STORE_FLAG_VALUE == 1 (e.g., the 386).
8606 Similarly, check for a case where the AND's are ZERO_EXTEND
8607 operations from some narrower mode even though a SUBREG is not
8610 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
8611 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
8612 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
8614 rtx inner_op0
= XEXP (op0
, 0);
8615 rtx inner_op1
= XEXP (op1
, 0);
8616 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
8617 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
8620 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
8621 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
8622 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
8623 && (GET_MODE (SUBREG_REG (inner_op0
))
8624 == GET_MODE (SUBREG_REG (inner_op1
)))
8625 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
8626 <= HOST_BITS_PER_WIDE_INT
)
8627 && (0 == (~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
8628 GET_MODE (SUBREG_REG (op0
))))
8629 && (0 == (~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
8630 GET_MODE (SUBREG_REG (inner_op1
)))))
8632 op0
= SUBREG_REG (inner_op0
);
8633 op1
= SUBREG_REG (inner_op1
);
8635 /* The resulting comparison is always unsigned since we masked
8636 off the original sign bit. */
8637 code
= unsigned_condition (code
);
8643 for (tmode
= GET_CLASS_NARROWEST_MODE
8644 (GET_MODE_CLASS (GET_MODE (op0
)));
8645 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
8646 if (c0
== GET_MODE_MASK (tmode
))
8648 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
8649 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
8650 code
= unsigned_condition (code
);
8659 /* If both operands are NOT, we can strip off the outer operation
8660 and adjust the comparison code for swapped operands; similarly for
8661 NEG, except that this must be an equality comparison. */
8662 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
8663 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
8664 && (code
== EQ
|| code
== NE
)))
8665 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
8671 /* If the first operand is a constant, swap the operands and adjust the
8672 comparison code appropriately. */
8673 if (CONSTANT_P (op0
))
8675 tem
= op0
, op0
= op1
, op1
= tem
;
8676 code
= swap_condition (code
);
8679 /* We now enter a loop during which we will try to simplify the comparison.
8680 For the most part, we only are concerned with comparisons with zero,
8681 but some things may really be comparisons with zero but not start
8682 out looking that way. */
8684 while (GET_CODE (op1
) == CONST_INT
)
8686 enum machine_mode mode
= GET_MODE (op0
);
8687 int mode_width
= GET_MODE_BITSIZE (mode
);
8688 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8689 int equality_comparison_p
;
8690 int sign_bit_comparison_p
;
8691 int unsigned_comparison_p
;
8692 HOST_WIDE_INT const_op
;
8694 /* We only want to handle integral modes. This catches VOIDmode,
8695 CCmode, and the floating-point modes. An exception is that we
8696 can handle VOIDmode if OP0 is a COMPARE or a comparison
8699 if (GET_MODE_CLASS (mode
) != MODE_INT
8700 && ! (mode
== VOIDmode
8701 && (GET_CODE (op0
) == COMPARE
8702 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
8705 /* Get the constant we are comparing against and turn off all bits
8706 not on in our mode. */
8707 const_op
= INTVAL (op1
);
8708 if (mode_width
<= HOST_BITS_PER_WIDE_INT
)
8711 /* If we are comparing against a constant power of two and the value
8712 being compared can only have that single bit nonzero (e.g., it was
8713 `and'ed with that bit), we can replace this with a comparison
8716 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
8717 || code
== LT
|| code
== LTU
)
8718 && mode_width
<= HOST_BITS_PER_WIDE_INT
8719 && exact_log2 (const_op
) >= 0
8720 && nonzero_bits (op0
, mode
) == const_op
)
8722 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
8723 op1
= const0_rtx
, const_op
= 0;
8726 /* Similarly, if we are comparing a value known to be either -1 or
8727 0 with -1, change it to the opposite comparison against zero. */
8730 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
8731 || code
== GEU
|| code
== LTU
)
8732 && num_sign_bit_copies (op0
, mode
) == mode_width
)
8734 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
8735 op1
= const0_rtx
, const_op
= 0;
8738 /* Do some canonicalizations based on the comparison code. We prefer
8739 comparisons against zero and then prefer equality comparisons.
8740 If we can reduce the size of a constant, we will do that too. */
8745 /* < C is equivalent to <= (C - 1) */
8749 op1
= GEN_INT (const_op
);
8751 /* ... fall through to LE case below. */
8757 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
8761 op1
= GEN_INT (const_op
);
8765 /* If we are doing a <= 0 comparison on a value known to have
8766 a zero sign bit, we can replace this with == 0. */
8767 else if (const_op
== 0
8768 && mode_width
<= HOST_BITS_PER_WIDE_INT
8769 && (nonzero_bits (op0
, mode
)
8770 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
8775 /* >= C is equivalent to > (C - 1). */
8779 op1
= GEN_INT (const_op
);
8781 /* ... fall through to GT below. */
8787 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
8791 op1
= GEN_INT (const_op
);
8795 /* If we are doing a > 0 comparison on a value known to have
8796 a zero sign bit, we can replace this with != 0. */
8797 else if (const_op
== 0
8798 && mode_width
<= HOST_BITS_PER_WIDE_INT
8799 && (nonzero_bits (op0
, mode
)
8800 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
8805 /* < C is equivalent to <= (C - 1). */
8809 op1
= GEN_INT (const_op
);
8811 /* ... fall through ... */
8814 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
8815 else if (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1))
8817 const_op
= 0, op1
= const0_rtx
;
8825 /* unsigned <= 0 is equivalent to == 0 */
8829 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
8830 else if (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
8832 const_op
= 0, op1
= const0_rtx
;
8838 /* >= C is equivalent to < (C - 1). */
8842 op1
= GEN_INT (const_op
);
8844 /* ... fall through ... */
8847 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
8848 else if (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1))
8850 const_op
= 0, op1
= const0_rtx
;
8858 /* unsigned > 0 is equivalent to != 0 */
8862 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
8863 else if (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
8865 const_op
= 0, op1
= const0_rtx
;
8871 /* Compute some predicates to simplify code below. */
8873 equality_comparison_p
= (code
== EQ
|| code
== NE
);
8874 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
8875 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
8878 /* If this is a sign bit comparison and we can do arithmetic in
8879 MODE, say that we will only be needing the sign bit of OP0. */
8880 if (sign_bit_comparison_p
8881 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8882 op0
= force_to_mode (op0
, mode
,
8884 << (GET_MODE_BITSIZE (mode
) - 1)),
8887 /* Now try cases based on the opcode of OP0. If none of the cases
8888 does a "continue", we exit this loop immediately after the
8891 switch (GET_CODE (op0
))
8894 /* If we are extracting a single bit from a variable position in
8895 a constant that has only a single bit set and are comparing it
8896 with zero, we can convert this into an equality comparison
8897 between the position and the location of the single bit. We can't
8898 do this if bit endian and we don't have an extzv since we then
8899 can't know what mode to use for the endianness adjustment. */
8901 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
8902 && XEXP (op0
, 1) == const1_rtx
8903 && equality_comparison_p
&& const_op
== 0
8904 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0
8905 && (! BITS_BIG_ENDIAN
8912 if (BITS_BIG_ENDIAN
)
8913 i
= (GET_MODE_BITSIZE
8914 (insn_operand_mode
[(int) CODE_FOR_extzv
][1]) - 1 - i
);
8917 op0
= XEXP (op0
, 2);
8921 /* Result is nonzero iff shift count is equal to I. */
8922 code
= reverse_condition (code
);
8926 /* ... fall through ... */
8929 tem
= expand_compound_operation (op0
);
8938 /* If testing for equality, we can take the NOT of the constant. */
8939 if (equality_comparison_p
8940 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
8942 op0
= XEXP (op0
, 0);
8947 /* If just looking at the sign bit, reverse the sense of the
8949 if (sign_bit_comparison_p
)
8951 op0
= XEXP (op0
, 0);
8952 code
= (code
== GE
? LT
: GE
);
8958 /* If testing for equality, we can take the NEG of the constant. */
8959 if (equality_comparison_p
8960 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
8962 op0
= XEXP (op0
, 0);
8967 /* The remaining cases only apply to comparisons with zero. */
8971 /* When X is ABS or is known positive,
8972 (neg X) is < 0 if and only if X != 0. */
8974 if (sign_bit_comparison_p
8975 && (GET_CODE (XEXP (op0
, 0)) == ABS
8976 || (mode_width
<= HOST_BITS_PER_WIDE_INT
8977 && (nonzero_bits (XEXP (op0
, 0), mode
)
8978 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
8980 op0
= XEXP (op0
, 0);
8981 code
= (code
== LT
? NE
: EQ
);
8985 /* If we have NEG of something whose two high-order bits are the
8986 same, we know that "(-a) < 0" is equivalent to "a > 0". */
8987 if (num_sign_bit_copies (op0
, mode
) >= 2)
8989 op0
= XEXP (op0
, 0);
8990 code
= swap_condition (code
);
8996 /* If we are testing equality and our count is a constant, we
8997 can perform the inverse operation on our RHS. */
8998 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
8999 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
9000 op1
, XEXP (op0
, 1))) != 0)
9002 op0
= XEXP (op0
, 0);
9007 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9008 a particular bit. Convert it to an AND of a constant of that
9009 bit. This will be converted into a ZERO_EXTRACT. */
9010 if (const_op
== 0 && sign_bit_comparison_p
9011 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9012 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
9014 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
9017 - INTVAL (XEXP (op0
, 1)))));
9018 code
= (code
== LT
? NE
: EQ
);
9022 /* ... fall through ... */
9025 /* ABS is ignorable inside an equality comparison with zero. */
9026 if (const_op
== 0 && equality_comparison_p
)
9028 op0
= XEXP (op0
, 0);
9035 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9036 to (compare FOO CONST) if CONST fits in FOO's mode and we
9037 are either testing inequality or have an unsigned comparison
9038 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9039 if (! unsigned_comparison_p
9040 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
9041 <= HOST_BITS_PER_WIDE_INT
)
9042 && ((unsigned HOST_WIDE_INT
) const_op
9043 < (((HOST_WIDE_INT
) 1
9044 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
9046 op0
= XEXP (op0
, 0);
9052 /* Check for the case where we are comparing A - C1 with C2,
9053 both constants are smaller than 1/2 the maxium positive
9054 value in MODE, and the comparison is equality or unsigned.
9055 In that case, if A is either zero-extended to MODE or has
9056 sufficient sign bits so that the high-order bit in MODE
9057 is a copy of the sign in the inner mode, we can prove that it is
9058 safe to do the operation in the wider mode. This simplifies
9059 many range checks. */
9061 if (mode_width
<= HOST_BITS_PER_WIDE_INT
9062 && subreg_lowpart_p (op0
)
9063 && GET_CODE (SUBREG_REG (op0
)) == PLUS
9064 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
9065 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
9066 && (- INTVAL (XEXP (SUBREG_REG (op0
), 1))
9067 < GET_MODE_MASK (mode
) / 2)
9068 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
9069 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
9070 GET_MODE (SUBREG_REG (op0
)))
9071 & ~ GET_MODE_MASK (mode
))
9072 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
9073 GET_MODE (SUBREG_REG (op0
)))
9074 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
9075 - GET_MODE_BITSIZE (mode
)))))
9077 op0
= SUBREG_REG (op0
);
9081 /* If the inner mode is narrower and we are extracting the low part,
9082 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9083 if (subreg_lowpart_p (op0
)
9084 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
9085 /* Fall through */ ;
9089 /* ... fall through ... */
9092 if ((unsigned_comparison_p
|| equality_comparison_p
)
9093 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
9094 <= HOST_BITS_PER_WIDE_INT
)
9095 && ((unsigned HOST_WIDE_INT
) const_op
9096 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
9098 op0
= XEXP (op0
, 0);
9104 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
9105 this for equality comparisons due to pathological cases involving
9107 if (equality_comparison_p
9108 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
9109 op1
, XEXP (op0
, 1))))
9111 op0
= XEXP (op0
, 0);
9116 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9117 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
9118 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
9120 op0
= XEXP (XEXP (op0
, 0), 0);
9121 code
= (code
== LT
? EQ
: NE
);
9127 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9128 (eq B (minus A C)), whichever simplifies. We can only do
9129 this for equality comparisons due to pathological cases involving
9131 if (equality_comparison_p
9132 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
9133 XEXP (op0
, 1), op1
)))
9135 op0
= XEXP (op0
, 0);
9140 if (equality_comparison_p
9141 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
9142 XEXP (op0
, 0), op1
)))
9144 op0
= XEXP (op0
, 1);
9149 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9150 of bits in X minus 1, is one iff X > 0. */
9151 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
9152 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
9153 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
9154 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
9156 op0
= XEXP (op0
, 1);
9157 code
= (code
== GE
? LE
: GT
);
9163 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
9164 if C is zero or B is a constant. */
9165 if (equality_comparison_p
9166 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
9167 XEXP (op0
, 1), op1
)))
9169 op0
= XEXP (op0
, 0);
9176 case LT
: case LTU
: case LE
: case LEU
:
9177 case GT
: case GTU
: case GE
: case GEU
:
9178 /* We can't do anything if OP0 is a condition code value, rather
9179 than an actual data value. */
9182 || XEXP (op0
, 0) == cc0_rtx
9184 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
9187 /* Get the two operands being compared. */
9188 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
9189 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
9191 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
9193 /* Check for the cases where we simply want the result of the
9194 earlier test or the opposite of that result. */
9196 || (code
== EQ
&& reversible_comparison_p (op0
))
9197 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9198 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
9199 && (STORE_FLAG_VALUE
9200 & (((HOST_WIDE_INT
) 1
9201 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
9203 || (code
== GE
&& reversible_comparison_p (op0
)))))
9205 code
= (code
== LT
|| code
== NE
9206 ? GET_CODE (op0
) : reverse_condition (GET_CODE (op0
)));
9207 op0
= tem
, op1
= tem1
;
9213 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
9215 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
9216 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
9217 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
9219 op0
= XEXP (op0
, 1);
9220 code
= (code
== GE
? GT
: LE
);
9226 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
9227 will be converted to a ZERO_EXTRACT later. */
9228 if (const_op
== 0 && equality_comparison_p
9229 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9230 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
9232 op0
= simplify_and_const_int
9233 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
9235 XEXP (XEXP (op0
, 0), 1)),
9240 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
9241 zero and X is a comparison and C1 and C2 describe only bits set
9242 in STORE_FLAG_VALUE, we can compare with X. */
9243 if (const_op
== 0 && equality_comparison_p
9244 && mode_width
<= HOST_BITS_PER_WIDE_INT
9245 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9246 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
9247 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
9248 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
9249 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
9251 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
9252 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
9253 if ((~ STORE_FLAG_VALUE
& mask
) == 0
9254 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
9255 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
9256 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
9258 op0
= XEXP (XEXP (op0
, 0), 0);
9263 /* If we are doing an equality comparison of an AND of a bit equal
9264 to the sign bit, replace this with a LT or GE comparison of
9265 the underlying value. */
9266 if (equality_comparison_p
9268 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9269 && mode_width
<= HOST_BITS_PER_WIDE_INT
9270 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
9271 == (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9273 op0
= XEXP (op0
, 0);
9274 code
= (code
== EQ
? GE
: LT
);
9278 /* If this AND operation is really a ZERO_EXTEND from a narrower
9279 mode, the constant fits within that mode, and this is either an
9280 equality or unsigned comparison, try to do this comparison in
9281 the narrower mode. */
9282 if ((equality_comparison_p
|| unsigned_comparison_p
)
9283 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9284 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
9285 & GET_MODE_MASK (mode
))
9287 && const_op
>> i
== 0
9288 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
9290 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
9296 /* If we have (compare (ashift FOO N) (const_int C)) and
9297 the high order N bits of FOO (N+1 if an inequality comparison)
9298 are known to be zero, we can do this by comparing FOO with C
9299 shifted right N bits so long as the low-order N bits of C are
9301 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
9302 && INTVAL (XEXP (op0
, 1)) >= 0
9303 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
9304 < HOST_BITS_PER_WIDE_INT
)
9306 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
9307 && mode_width
<= HOST_BITS_PER_WIDE_INT
9308 && (nonzero_bits (XEXP (op0
, 0), mode
)
9309 & ~ (mask
>> (INTVAL (XEXP (op0
, 1))
9310 + ! equality_comparison_p
))) == 0)
9312 const_op
>>= INTVAL (XEXP (op0
, 1));
9313 op1
= GEN_INT (const_op
);
9314 op0
= XEXP (op0
, 0);
9318 /* If we are doing a sign bit comparison, it means we are testing
9319 a particular bit. Convert it to the appropriate AND. */
9320 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
9321 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
9323 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
9326 - INTVAL (XEXP (op0
, 1)))));
9327 code
= (code
== LT
? NE
: EQ
);
9331 /* If this an equality comparison with zero and we are shifting
9332 the low bit to the sign bit, we can convert this to an AND of the
9334 if (const_op
== 0 && equality_comparison_p
9335 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9336 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
9338 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
9345 /* If this is an equality comparison with zero, we can do this
9346 as a logical shift, which might be much simpler. */
9347 if (equality_comparison_p
&& const_op
== 0
9348 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
9350 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
9352 INTVAL (XEXP (op0
, 1)));
9356 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
9357 do the comparison in a narrower mode. */
9358 if (! unsigned_comparison_p
9359 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9360 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9361 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
9362 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
9363 MODE_INT
, 1)) != BLKmode
9364 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
9365 || ((unsigned HOST_WIDE_INT
) - const_op
9366 <= GET_MODE_MASK (tmode
))))
9368 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
9372 /* ... fall through ... */
9374 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
9375 the low order N bits of FOO are known to be zero, we can do this
9376 by comparing FOO with C shifted left N bits so long as no
9378 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
9379 && INTVAL (XEXP (op0
, 1)) >= 0
9380 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9381 && mode_width
<= HOST_BITS_PER_WIDE_INT
9382 && (nonzero_bits (XEXP (op0
, 0), mode
)
9383 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
9385 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
9388 const_op
<<= INTVAL (XEXP (op0
, 1));
9389 op1
= GEN_INT (const_op
);
9390 op0
= XEXP (op0
, 0);
9394 /* If we are using this shift to extract just the sign bit, we
9395 can replace this with an LT or GE comparison. */
9397 && (equality_comparison_p
|| sign_bit_comparison_p
)
9398 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9399 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
9401 op0
= XEXP (op0
, 0);
9402 code
= (code
== NE
|| code
== GT
? LT
: GE
);
9411 /* Now make any compound operations involved in this comparison. Then,
9412 check for an outmost SUBREG on OP0 that isn't doing anything or is
9413 paradoxical. The latter case can only occur when it is known that the
9414 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
9415 We can never remove a SUBREG for a non-equality comparison because the
9416 sign bit is in a different place in the underlying object. */
9418 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
9419 op1
= make_compound_operation (op1
, SET
);
9421 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
9422 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
9423 && (code
== NE
|| code
== EQ
)
9424 && ((GET_MODE_SIZE (GET_MODE (op0
))
9425 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
9427 op0
= SUBREG_REG (op0
);
9428 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
9431 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
9432 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
9433 && (code
== NE
|| code
== EQ
)
9434 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
9435 <= HOST_BITS_PER_WIDE_INT
)
9436 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
9437 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0
9438 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
9440 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
9441 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0))
9442 op0
= SUBREG_REG (op0
), op1
= tem
;
9444 /* We now do the opposite procedure: Some machines don't have compare
9445 insns in all modes. If OP0's mode is an integer mode smaller than a
9446 word and we can't do a compare in that mode, see if there is a larger
9447 mode for which we can do the compare. There are a number of cases in
9448 which we can use the wider mode. */
9450 mode
= GET_MODE (op0
);
9451 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
9452 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
9453 && cmp_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
)
9454 for (tmode
= GET_MODE_WIDER_MODE (mode
);
9456 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
9457 tmode
= GET_MODE_WIDER_MODE (tmode
))
9458 if (cmp_optab
->handlers
[(int) tmode
].insn_code
!= CODE_FOR_nothing
)
9460 /* If the only nonzero bits in OP0 and OP1 are those in the
9461 narrower mode and this is an equality or unsigned comparison,
9462 we can use the wider mode. Similarly for sign-extended
9463 values, in which case it is true for all comparisons. */
9464 if (((code
== EQ
|| code
== NE
9465 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
9466 && (nonzero_bits (op0
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0
9467 && (nonzero_bits (op1
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0)
9468 || ((num_sign_bit_copies (op0
, tmode
)
9469 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
9470 && (num_sign_bit_copies (op1
, tmode
)
9471 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
9473 op0
= gen_lowpart_for_combine (tmode
, op0
);
9474 op1
= gen_lowpart_for_combine (tmode
, op1
);
9478 /* If this is a test for negative, we can make an explicit
9479 test of the sign bit. */
9481 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
9482 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9484 op0
= gen_binary (AND
, tmode
,
9485 gen_lowpart_for_combine (tmode
, op0
),
9486 GEN_INT ((HOST_WIDE_INT
) 1
9487 << (GET_MODE_BITSIZE (mode
) - 1)));
9488 code
= (code
== LT
) ? NE
: EQ
;
9493 #ifdef CANONICALIZE_COMPARISON
9494 /* If this machine only supports a subset of valid comparisons, see if we
9495 can convert an unsupported one into a supported one. */
9496 CANONICALIZE_COMPARISON (code
, op0
, op1
);
9505 /* Return 1 if we know that X, a comparison operation, is not operating
9506 on a floating-point value or is EQ or NE, meaning that we can safely
9510 reversible_comparison_p (x
)
9513 if (TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
9515 || GET_CODE (x
) == NE
|| GET_CODE (x
) == EQ
)
9518 switch (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))))
9521 case MODE_PARTIAL_INT
:
9522 case MODE_COMPLEX_INT
:
9526 /* If the mode of the condition codes tells us that this is safe,
9527 we need look no further. */
9528 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x
, 0))))
9531 /* Otherwise try and find where the condition codes were last set and
9533 x
= get_last_value (XEXP (x
, 0));
9534 return (x
&& GET_CODE (x
) == COMPARE
9535 && ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0))));
9541 /* Utility function for following routine. Called when X is part of a value
9542 being stored into reg_last_set_value. Sets reg_last_set_table_tick
9543 for each register mentioned. Similar to mention_regs in cse.c */
9546 update_table_tick (x
)
9549 register enum rtx_code code
= GET_CODE (x
);
9550 register char *fmt
= GET_RTX_FORMAT (code
);
9555 int regno
= REGNO (x
);
9556 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
9557 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
9559 for (i
= regno
; i
< endregno
; i
++)
9560 reg_last_set_table_tick
[i
] = label_tick
;
9565 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9566 /* Note that we can't have an "E" in values stored; see
9567 get_last_value_validate. */
9569 update_table_tick (XEXP (x
, i
));
9572 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
9573 are saying that the register is clobbered and we no longer know its
9574 value. If INSN is zero, don't update reg_last_set; this is only permitted
9575 with VALUE also zero and is used to invalidate the register. */
9578 record_value_for_reg (reg
, insn
, value
)
9583 int regno
= REGNO (reg
);
9584 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
9585 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
9588 /* If VALUE contains REG and we have a previous value for REG, substitute
9589 the previous value. */
9590 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
9594 /* Set things up so get_last_value is allowed to see anything set up to
9596 subst_low_cuid
= INSN_CUID (insn
);
9597 tem
= get_last_value (reg
);
9600 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
9603 /* For each register modified, show we don't know its value, that
9604 we don't know about its bitwise content, that its value has been
9605 updated, and that we don't know the location of the death of the
9607 for (i
= regno
; i
< endregno
; i
++)
9610 reg_last_set
[i
] = insn
;
9611 reg_last_set_value
[i
] = 0;
9612 reg_last_set_mode
[i
] = 0;
9613 reg_last_set_nonzero_bits
[i
] = 0;
9614 reg_last_set_sign_bit_copies
[i
] = 0;
9615 reg_last_death
[i
] = 0;
9618 /* Mark registers that are being referenced in this value. */
9620 update_table_tick (value
);
9622 /* Now update the status of each register being set.
9623 If someone is using this register in this block, set this register
9624 to invalid since we will get confused between the two lives in this
9625 basic block. This makes using this register always invalid. In cse, we
9626 scan the table to invalidate all entries using this register, but this
9627 is too much work for us. */
9629 for (i
= regno
; i
< endregno
; i
++)
9631 reg_last_set_label
[i
] = label_tick
;
9632 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
9633 reg_last_set_invalid
[i
] = 1;
9635 reg_last_set_invalid
[i
] = 0;
9638 /* The value being assigned might refer to X (like in "x++;"). In that
9639 case, we must replace it with (clobber (const_int 0)) to prevent
9641 if (value
&& ! get_last_value_validate (&value
,
9642 reg_last_set_label
[regno
], 0))
9644 value
= copy_rtx (value
);
9645 if (! get_last_value_validate (&value
, reg_last_set_label
[regno
], 1))
9649 /* For the main register being modified, update the value, the mode, the
9650 nonzero bits, and the number of sign bit copies. */
9652 reg_last_set_value
[regno
] = value
;
9656 subst_low_cuid
= INSN_CUID (insn
);
9657 reg_last_set_mode
[regno
] = GET_MODE (reg
);
9658 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
9659 reg_last_set_sign_bit_copies
[regno
]
9660 = num_sign_bit_copies (value
, GET_MODE (reg
));
9664 /* Used for communication between the following two routines. */
9665 static rtx record_dead_insn
;
9667 /* Called via note_stores from record_dead_and_set_regs to handle one
9668 SET or CLOBBER in an insn. */
9671 record_dead_and_set_regs_1 (dest
, setter
)
9674 if (GET_CODE (dest
) == SUBREG
)
9675 dest
= SUBREG_REG (dest
);
9677 if (GET_CODE (dest
) == REG
)
9679 /* If we are setting the whole register, we know its value. Otherwise
9680 show that we don't know the value. We can handle SUBREG in
9682 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
9683 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
9684 else if (GET_CODE (setter
) == SET
9685 && GET_CODE (SET_DEST (setter
)) == SUBREG
9686 && SUBREG_REG (SET_DEST (setter
)) == dest
9687 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
9688 && subreg_lowpart_p (SET_DEST (setter
)))
9689 record_value_for_reg (dest
, record_dead_insn
,
9690 gen_lowpart_for_combine (GET_MODE (dest
),
9693 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
9695 else if (GET_CODE (dest
) == MEM
9696 /* Ignore pushes, they clobber nothing. */
9697 && ! push_operand (dest
, GET_MODE (dest
)))
9698 mem_last_set
= INSN_CUID (record_dead_insn
);
9701 /* Update the records of when each REG was most recently set or killed
9702 for the things done by INSN. This is the last thing done in processing
9703 INSN in the combiner loop.
9705 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
9706 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
9707 and also the similar information mem_last_set (which insn most recently
9708 modified memory) and last_call_cuid (which insn was the most recent
9709 subroutine call). */
9712 record_dead_and_set_regs (insn
)
9718 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
9720 if (REG_NOTE_KIND (link
) == REG_DEAD
9721 && GET_CODE (XEXP (link
, 0)) == REG
)
9723 int regno
= REGNO (XEXP (link
, 0));
9725 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
9726 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
9729 for (i
= regno
; i
< endregno
; i
++)
9730 reg_last_death
[i
] = insn
;
9732 else if (REG_NOTE_KIND (link
) == REG_INC
)
9733 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
9736 if (GET_CODE (insn
) == CALL_INSN
)
9738 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
9739 if (call_used_regs
[i
])
9741 reg_last_set_value
[i
] = 0;
9742 reg_last_set_mode
[i
] = 0;
9743 reg_last_set_nonzero_bits
[i
] = 0;
9744 reg_last_set_sign_bit_copies
[i
] = 0;
9745 reg_last_death
[i
] = 0;
9748 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
9751 record_dead_insn
= insn
;
9752 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
);
9755 /* Utility routine for the following function. Verify that all the registers
9756 mentioned in *LOC are valid when *LOC was part of a value set when
9757 label_tick == TICK. Return 0 if some are not.
9759 If REPLACE is non-zero, replace the invalid reference with
9760 (clobber (const_int 0)) and return 1. This replacement is useful because
9761 we often can get useful information about the form of a value (e.g., if
9762 it was produced by a shift that always produces -1 or 0) even though
9763 we don't know exactly what registers it was produced from. */
9766 get_last_value_validate (loc
, tick
, replace
)
9772 char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
9773 int len
= GET_RTX_LENGTH (GET_CODE (x
));
9776 if (GET_CODE (x
) == REG
)
9778 int regno
= REGNO (x
);
9779 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
9780 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
9783 for (j
= regno
; j
< endregno
; j
++)
9784 if (reg_last_set_invalid
[j
]
9785 /* If this is a pseudo-register that was only set once, it is
9787 || (! (regno
>= FIRST_PSEUDO_REGISTER
&& reg_n_sets
[regno
] == 1)
9788 && reg_last_set_label
[j
] > tick
))
9791 *loc
= gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
9798 for (i
= 0; i
< len
; i
++)
9800 && get_last_value_validate (&XEXP (x
, i
), tick
, replace
) == 0)
9801 /* Don't bother with these. They shouldn't occur anyway. */
9805 /* If we haven't found a reason for it to be invalid, it is valid. */
9809 /* Get the last value assigned to X, if known. Some registers
9810 in the value may be replaced with (clobber (const_int 0)) if their value
9811 is known longer known reliably. */
9820 /* If this is a non-paradoxical SUBREG, get the value of its operand and
9821 then convert it to the desired mode. If this is a paradoxical SUBREG,
9822 we cannot predict what values the "extra" bits might have. */
9823 if (GET_CODE (x
) == SUBREG
9824 && subreg_lowpart_p (x
)
9825 && (GET_MODE_SIZE (GET_MODE (x
))
9826 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
9827 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
9828 return gen_lowpart_for_combine (GET_MODE (x
), value
);
9830 if (GET_CODE (x
) != REG
)
9834 value
= reg_last_set_value
[regno
];
9836 /* If we don't have a value or if it isn't for this basic block, return 0. */
9839 || (reg_n_sets
[regno
] != 1
9840 && reg_last_set_label
[regno
] != label_tick
))
9843 /* If the value was set in a later insn that the ones we are processing,
9844 we can't use it even if the register was only set once, but make a quick
9845 check to see if the previous insn set it to something. This is commonly
9846 the case when the same pseudo is used by repeated insns. */
9848 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
9852 for (insn
= prev_nonnote_insn (subst_insn
);
9853 insn
&& INSN_CUID (insn
) >= subst_low_cuid
;
9854 insn
= prev_nonnote_insn (insn
))
9858 && (set
= single_set (insn
)) != 0
9859 && rtx_equal_p (SET_DEST (set
), x
))
9861 value
= SET_SRC (set
);
9863 /* Make sure that VALUE doesn't reference X. Replace any
9864 expliit references with a CLOBBER. If there are any remaining
9865 references (rare), don't use the value. */
9867 if (reg_mentioned_p (x
, value
))
9868 value
= replace_rtx (copy_rtx (value
), x
,
9869 gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
));
9871 if (reg_overlap_mentioned_p (x
, value
))
9878 /* If the value has all its registers valid, return it. */
9879 if (get_last_value_validate (&value
, reg_last_set_label
[regno
], 0))
9882 /* Otherwise, make a copy and replace any invalid register with
9883 (clobber (const_int 0)). If that fails for some reason, return 0. */
9885 value
= copy_rtx (value
);
9886 if (get_last_value_validate (&value
, reg_last_set_label
[regno
], 1))
9892 /* Return nonzero if expression X refers to a REG or to memory
9893 that is set in an instruction more recent than FROM_CUID. */
9896 use_crosses_set_p (x
, from_cuid
)
9902 register enum rtx_code code
= GET_CODE (x
);
9906 register int regno
= REGNO (x
);
9907 int endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
9908 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
9910 #ifdef PUSH_ROUNDING
9911 /* Don't allow uses of the stack pointer to be moved,
9912 because we don't know whether the move crosses a push insn. */
9913 if (regno
== STACK_POINTER_REGNUM
)
9916 for (;regno
< endreg
; regno
++)
9917 if (reg_last_set
[regno
]
9918 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
9923 if (code
== MEM
&& mem_last_set
> from_cuid
)
9926 fmt
= GET_RTX_FORMAT (code
);
9928 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9933 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9934 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
9937 else if (fmt
[i
] == 'e'
9938 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
9944 /* Define three variables used for communication between the following
9947 static int reg_dead_regno
, reg_dead_endregno
;
9948 static int reg_dead_flag
;
9950 /* Function called via note_stores from reg_dead_at_p.
9952 If DEST is within [reg_dead_rengno, reg_dead_endregno), set
9953 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
9956 reg_dead_at_p_1 (dest
, x
)
9960 int regno
, endregno
;
9962 if (GET_CODE (dest
) != REG
)
9965 regno
= REGNO (dest
);
9966 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
9967 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
9969 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
9970 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
9973 /* Return non-zero if REG is known to be dead at INSN.
9975 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
9976 referencing REG, it is dead. If we hit a SET referencing REG, it is
9977 live. Otherwise, see if it is live or dead at the start of the basic
9978 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
9979 must be assumed to be always live. */
9982 reg_dead_at_p (reg
, insn
)
9988 /* Set variables for reg_dead_at_p_1. */
9989 reg_dead_regno
= REGNO (reg
);
9990 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
9991 ? HARD_REGNO_NREGS (reg_dead_regno
,
9997 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
9998 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
10000 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
10001 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
10005 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10006 beginning of function. */
10007 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
;
10008 insn
= prev_nonnote_insn (insn
))
10010 note_stores (PATTERN (insn
), reg_dead_at_p_1
);
10012 return reg_dead_flag
== 1 ? 1 : 0;
10014 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
10018 /* Get the basic block number that we were in. */
10023 for (block
= 0; block
< n_basic_blocks
; block
++)
10024 if (insn
== basic_block_head
[block
])
10027 if (block
== n_basic_blocks
)
10031 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
10032 if (basic_block_live_at_start
[block
][i
/ REGSET_ELT_BITS
]
10033 & ((REGSET_ELT_TYPE
) 1 << (i
% REGSET_ELT_BITS
)))
10039 /* Note hard registers in X that are used. This code is similar to
10040 that in flow.c, but much simpler since we don't care about pseudos. */
10043 mark_used_regs_combine (x
)
10046 register RTX_CODE code
= GET_CODE (x
);
10047 register int regno
;
10059 case ADDR_DIFF_VEC
:
10062 /* CC0 must die in the insn after it is set, so we don't need to take
10063 special note of it here. */
10069 /* If we are clobbering a MEM, mark any hard registers inside the
10070 address as used. */
10071 if (GET_CODE (XEXP (x
, 0)) == MEM
)
10072 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
10077 /* A hard reg in a wide mode may really be multiple registers.
10078 If so, mark all of them just like the first. */
10079 if (regno
< FIRST_PSEUDO_REGISTER
)
10081 /* None of this applies to the stack, frame or arg pointers */
10082 if (regno
== STACK_POINTER_REGNUM
10083 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
10084 || regno
== HARD_FRAME_POINTER_REGNUM
10086 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
10087 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
10089 || regno
== FRAME_POINTER_REGNUM
)
10092 i
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
10094 SET_HARD_REG_BIT (newpat_used_regs
, regno
+ i
);
10100 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
10102 register rtx testreg
= SET_DEST (x
);
10104 while (GET_CODE (testreg
) == SUBREG
10105 || GET_CODE (testreg
) == ZERO_EXTRACT
10106 || GET_CODE (testreg
) == SIGN_EXTRACT
10107 || GET_CODE (testreg
) == STRICT_LOW_PART
)
10108 testreg
= XEXP (testreg
, 0);
10110 if (GET_CODE (testreg
) == MEM
)
10111 mark_used_regs_combine (XEXP (testreg
, 0));
10113 mark_used_regs_combine (SET_SRC (x
));
10118 /* Recursively scan the operands of this expression. */
10121 register char *fmt
= GET_RTX_FORMAT (code
);
10123 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10126 mark_used_regs_combine (XEXP (x
, i
));
10127 else if (fmt
[i
] == 'E')
10131 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
10132 mark_used_regs_combine (XVECEXP (x
, i
, j
));
10139 /* Remove register number REGNO from the dead registers list of INSN.
10141 Return the note used to record the death, if there was one. */
10144 remove_death (regno
, insn
)
10148 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
10152 reg_n_deaths
[regno
]--;
10153 remove_note (insn
, note
);
10159 /* For each register (hardware or pseudo) used within expression X, if its
10160 death is in an instruction with cuid between FROM_CUID (inclusive) and
10161 TO_INSN (exclusive), put a REG_DEAD note for that register in the
10162 list headed by PNOTES.
10164 This is done when X is being merged by combination into TO_INSN. These
10165 notes will then be distributed as needed. */
10168 move_deaths (x
, from_cuid
, to_insn
, pnotes
)
10174 register char *fmt
;
10175 register int len
, i
;
10176 register enum rtx_code code
= GET_CODE (x
);
10180 register int regno
= REGNO (x
);
10181 register rtx where_dead
= reg_last_death
[regno
];
10183 if (where_dead
&& INSN_CUID (where_dead
) >= from_cuid
10184 && INSN_CUID (where_dead
) < INSN_CUID (to_insn
))
10186 rtx note
= remove_death (regno
, where_dead
);
10188 /* It is possible for the call above to return 0. This can occur
10189 when reg_last_death points to I2 or I1 that we combined with.
10190 In that case make a new note.
10192 We must also check for the case where X is a hard register
10193 and NOTE is a death note for a range of hard registers
10194 including X. In that case, we must put REG_DEAD notes for
10195 the remaining registers in place of NOTE. */
10197 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
10198 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
10199 != GET_MODE_SIZE (GET_MODE (x
))))
10201 int deadregno
= REGNO (XEXP (note
, 0));
10203 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
10204 GET_MODE (XEXP (note
, 0))));
10205 int ourend
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
10208 for (i
= deadregno
; i
< deadend
; i
++)
10209 if (i
< regno
|| i
>= ourend
)
10210 REG_NOTES (where_dead
)
10211 = gen_rtx (EXPR_LIST
, REG_DEAD
,
10212 gen_rtx (REG
, reg_raw_mode
[i
], i
),
10213 REG_NOTES (where_dead
));
10216 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
10218 XEXP (note
, 1) = *pnotes
;
10222 *pnotes
= gen_rtx (EXPR_LIST
, REG_DEAD
, x
, *pnotes
);
10224 reg_n_deaths
[regno
]++;
10230 else if (GET_CODE (x
) == SET
)
10232 rtx dest
= SET_DEST (x
);
10234 move_deaths (SET_SRC (x
), from_cuid
, to_insn
, pnotes
);
10236 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
10237 that accesses one word of a multi-word item, some
10238 piece of everything register in the expression is used by
10239 this insn, so remove any old death. */
10241 if (GET_CODE (dest
) == ZERO_EXTRACT
10242 || GET_CODE (dest
) == STRICT_LOW_PART
10243 || (GET_CODE (dest
) == SUBREG
10244 && (((GET_MODE_SIZE (GET_MODE (dest
))
10245 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
10246 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
10247 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
10249 move_deaths (dest
, from_cuid
, to_insn
, pnotes
);
10253 /* If this is some other SUBREG, we know it replaces the entire
10254 value, so use that as the destination. */
10255 if (GET_CODE (dest
) == SUBREG
)
10256 dest
= SUBREG_REG (dest
);
10258 /* If this is a MEM, adjust deaths of anything used in the address.
10259 For a REG (the only other possibility), the entire value is
10260 being replaced so the old value is not used in this insn. */
10262 if (GET_CODE (dest
) == MEM
)
10263 move_deaths (XEXP (dest
, 0), from_cuid
, to_insn
, pnotes
);
10267 else if (GET_CODE (x
) == CLOBBER
)
10270 len
= GET_RTX_LENGTH (code
);
10271 fmt
= GET_RTX_FORMAT (code
);
10273 for (i
= 0; i
< len
; i
++)
10278 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
10279 move_deaths (XVECEXP (x
, i
, j
), from_cuid
, to_insn
, pnotes
);
10281 else if (fmt
[i
] == 'e')
10282 move_deaths (XEXP (x
, i
), from_cuid
, to_insn
, pnotes
);
10286 /* Return 1 if X is the target of a bit-field assignment in BODY, the
10287 pattern of an insn. X must be a REG. */
10290 reg_bitfield_target_p (x
, body
)
10296 if (GET_CODE (body
) == SET
)
10298 rtx dest
= SET_DEST (body
);
10300 int regno
, tregno
, endregno
, endtregno
;
10302 if (GET_CODE (dest
) == ZERO_EXTRACT
)
10303 target
= XEXP (dest
, 0);
10304 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
10305 target
= SUBREG_REG (XEXP (dest
, 0));
10309 if (GET_CODE (target
) == SUBREG
)
10310 target
= SUBREG_REG (target
);
10312 if (GET_CODE (target
) != REG
)
10315 tregno
= REGNO (target
), regno
= REGNO (x
);
10316 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
10317 return target
== x
;
10319 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
10320 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
10322 return endregno
> tregno
&& regno
< endtregno
;
10325 else if (GET_CODE (body
) == PARALLEL
)
10326 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
10327 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
10333 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
10334 as appropriate. I3 and I2 are the insns resulting from the combination
10335 insns including FROM (I2 may be zero).
10337 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
10338 not need REG_DEAD notes because they are being substituted for. This
10339 saves searching in the most common cases.
10341 Each note in the list is either ignored or placed on some insns, depending
10342 on the type of note. */
10345 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
10349 rtx elim_i2
, elim_i1
;
10351 rtx note
, next_note
;
10354 for (note
= notes
; note
; note
= next_note
)
10356 rtx place
= 0, place2
= 0;
10358 /* If this NOTE references a pseudo register, ensure it references
10359 the latest copy of that register. */
10360 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
10361 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
10362 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
10364 next_note
= XEXP (note
, 1);
10365 switch (REG_NOTE_KIND (note
))
10368 /* Any clobbers for i3 may still exist, and so we must process
10369 REG_UNUSED notes from that insn.
10371 Any clobbers from i2 or i1 can only exist if they were added by
10372 recog_for_combine. In that case, recog_for_combine created the
10373 necessary REG_UNUSED notes. Trying to keep any original
10374 REG_UNUSED notes from these insns can cause incorrect output
10375 if it is for the same register as the original i3 dest.
10376 In that case, we will notice that the register is set in i3,
10377 and then add a REG_UNUSED note for the destination of i3, which
10378 is wrong. However, it is possible to have REG_UNUSED notes from
10379 i2 or i1 for register which were both used and clobbered, so
10380 we keep notes from i2 or i1 if they will turn into REG_DEAD
10383 /* If this register is set or clobbered in I3, put the note there
10384 unless there is one already. */
10385 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
10387 if (from_insn
!= i3
)
10390 if (! (GET_CODE (XEXP (note
, 0)) == REG
10391 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
10392 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
10395 /* Otherwise, if this register is used by I3, then this register
10396 now dies here, so we must put a REG_DEAD note here unless there
10398 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
10399 && ! (GET_CODE (XEXP (note
, 0)) == REG
10400 ? find_regno_note (i3
, REG_DEAD
, REGNO (XEXP (note
, 0)))
10401 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
10403 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
10411 /* These notes say something about results of an insn. We can
10412 only support them if they used to be on I3 in which case they
10413 remain on I3. Otherwise they are ignored.
10415 If the note refers to an expression that is not a constant, we
10416 must also ignore the note since we cannot tell whether the
10417 equivalence is still true. It might be possible to do
10418 slightly better than this (we only have a problem if I2DEST
10419 or I1DEST is present in the expression), but it doesn't
10420 seem worth the trouble. */
10422 if (from_insn
== i3
10423 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
10428 case REG_NO_CONFLICT
:
10430 /* These notes say something about how a register is used. They must
10431 be present on any use of the register in I2 or I3. */
10432 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
10435 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
10445 /* It is too much trouble to try to see if this note is still
10446 correct in all situations. It is better to simply delete it. */
10450 /* If the insn previously containing this note still exists,
10451 put it back where it was. Otherwise move it to the previous
10452 insn. Adjust the corresponding REG_LIBCALL note. */
10453 if (GET_CODE (from_insn
) != NOTE
)
10457 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
10458 place
= prev_real_insn (from_insn
);
10460 XEXP (tem
, 0) = place
;
10465 /* This is handled similarly to REG_RETVAL. */
10466 if (GET_CODE (from_insn
) != NOTE
)
10470 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
10471 place
= next_real_insn (from_insn
);
10473 XEXP (tem
, 0) = place
;
10478 /* If the register is used as an input in I3, it dies there.
10479 Similarly for I2, if it is non-zero and adjacent to I3.
10481 If the register is not used as an input in either I3 or I2
10482 and it is not one of the registers we were supposed to eliminate,
10483 there are two possibilities. We might have a non-adjacent I2
10484 or we might have somehow eliminated an additional register
10485 from a computation. For example, we might have had A & B where
10486 we discover that B will always be zero. In this case we will
10487 eliminate the reference to A.
10489 In both cases, we must search to see if we can find a previous
10490 use of A and put the death note there. */
10493 && GET_CODE (from_insn
) == CALL_INSN
10494 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
10496 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
10498 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
10499 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
10502 if (XEXP (note
, 0) == elim_i2
|| XEXP (note
, 0) == elim_i1
)
10505 /* If the register is used in both I2 and I3 and it dies in I3,
10506 we might have added another reference to it. If reg_n_refs
10507 was 2, bump it to 3. This has to be correct since the
10508 register must have been set somewhere. The reason this is
10509 done is because local-alloc.c treats 2 references as a
10512 if (place
== i3
&& i2
!= 0 && GET_CODE (XEXP (note
, 0)) == REG
10513 && reg_n_refs
[REGNO (XEXP (note
, 0))]== 2
10514 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
10515 reg_n_refs
[REGNO (XEXP (note
, 0))] = 3;
10518 for (tem
= prev_nonnote_insn (i3
);
10519 tem
&& (GET_CODE (tem
) == INSN
10520 || GET_CODE (tem
) == CALL_INSN
);
10521 tem
= prev_nonnote_insn (tem
))
10523 /* If the register is being set at TEM, see if that is all
10524 TEM is doing. If so, delete TEM. Otherwise, make this
10525 into a REG_UNUSED note instead. */
10526 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
10528 rtx set
= single_set (tem
);
10530 /* Verify that it was the set, and not a clobber that
10531 modified the register. */
10533 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
10534 && rtx_equal_p (XEXP (note
, 0), SET_DEST (set
)))
10536 /* Move the notes and links of TEM elsewhere.
10537 This might delete other dead insns recursively.
10538 First set the pattern to something that won't use
10541 PATTERN (tem
) = pc_rtx
;
10543 distribute_notes (REG_NOTES (tem
), tem
, tem
,
10544 NULL_RTX
, NULL_RTX
, NULL_RTX
);
10545 distribute_links (LOG_LINKS (tem
));
10547 PUT_CODE (tem
, NOTE
);
10548 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
10549 NOTE_SOURCE_FILE (tem
) = 0;
10553 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
10555 /* If there isn't already a REG_UNUSED note, put one
10557 if (! find_regno_note (tem
, REG_UNUSED
,
10558 REGNO (XEXP (note
, 0))))
10563 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
10564 || (GET_CODE (tem
) == CALL_INSN
10565 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
10572 /* If the register is set or already dead at PLACE, we needn't do
10573 anything with this note if it is still a REG_DEAD note.
10575 Note that we cannot use just `dead_or_set_p' here since we can
10576 convert an assignment to a register into a bit-field assignment.
10577 Therefore, we must also omit the note if the register is the
10578 target of a bitfield assignment. */
10580 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
10582 int regno
= REGNO (XEXP (note
, 0));
10584 if (dead_or_set_p (place
, XEXP (note
, 0))
10585 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
10587 /* Unless the register previously died in PLACE, clear
10588 reg_last_death. [I no longer understand why this is
10590 if (reg_last_death
[regno
] != place
)
10591 reg_last_death
[regno
] = 0;
10595 reg_last_death
[regno
] = place
;
10597 /* If this is a death note for a hard reg that is occupying
10598 multiple registers, ensure that we are still using all
10599 parts of the object. If we find a piece of the object
10600 that is unused, we must add a USE for that piece before
10601 PLACE and put the appropriate REG_DEAD note on it.
10603 An alternative would be to put a REG_UNUSED for the pieces
10604 on the insn that set the register, but that can't be done if
10605 it is not in the same block. It is simpler, though less
10606 efficient, to add the USE insns. */
10608 if (place
&& regno
< FIRST_PSEUDO_REGISTER
10609 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
10612 = regno
+ HARD_REGNO_NREGS (regno
,
10613 GET_MODE (XEXP (note
, 0)));
10617 for (i
= regno
; i
< endregno
; i
++)
10618 if (! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
10619 && ! find_regno_fusage (place
, USE
, i
))
10621 rtx piece
= gen_rtx (REG
, reg_raw_mode
[i
], i
);
10624 /* See if we already placed a USE note for this
10625 register in front of PLACE. */
10627 GET_CODE (PREV_INSN (p
)) == INSN
10628 && GET_CODE (PATTERN (PREV_INSN (p
))) == USE
;
10630 if (rtx_equal_p (piece
,
10631 XEXP (PATTERN (PREV_INSN (p
)), 0)))
10640 = emit_insn_before (gen_rtx (USE
, VOIDmode
,
10643 REG_NOTES (use_insn
)
10644 = gen_rtx (EXPR_LIST
, REG_DEAD
, piece
,
10645 REG_NOTES (use_insn
));
10651 /* Check for the case where the register dying partially
10652 overlaps the register set by this insn. */
10654 for (i
= regno
; i
< endregno
; i
++)
10655 if (dead_or_set_regno_p (place
, i
))
10663 /* Put only REG_DEAD notes for pieces that are
10664 still used and that are not already dead or set. */
10666 for (i
= regno
; i
< endregno
; i
++)
10668 rtx piece
= gen_rtx (REG
, reg_raw_mode
[i
], i
);
10670 if ((reg_referenced_p (piece
, PATTERN (place
))
10671 || (GET_CODE (place
) == CALL_INSN
10672 && find_reg_fusage (place
, USE
, piece
)))
10673 && ! dead_or_set_p (place
, piece
)
10674 && ! reg_bitfield_target_p (piece
,
10676 REG_NOTES (place
) = gen_rtx (EXPR_LIST
, REG_DEAD
,
10678 REG_NOTES (place
));
10688 /* Any other notes should not be present at this point in the
10695 XEXP (note
, 1) = REG_NOTES (place
);
10696 REG_NOTES (place
) = note
;
10698 else if ((REG_NOTE_KIND (note
) == REG_DEAD
10699 || REG_NOTE_KIND (note
) == REG_UNUSED
)
10700 && GET_CODE (XEXP (note
, 0)) == REG
)
10701 reg_n_deaths
[REGNO (XEXP (note
, 0))]--;
10705 if ((REG_NOTE_KIND (note
) == REG_DEAD
10706 || REG_NOTE_KIND (note
) == REG_UNUSED
)
10707 && GET_CODE (XEXP (note
, 0)) == REG
)
10708 reg_n_deaths
[REGNO (XEXP (note
, 0))]++;
10710 REG_NOTES (place2
) = gen_rtx (GET_CODE (note
), REG_NOTE_KIND (note
),
10711 XEXP (note
, 0), REG_NOTES (place2
));
10716 /* Similarly to above, distribute the LOG_LINKS that used to be present on
10717 I3, I2, and I1 to new locations. This is also called in one case to
10718 add a link pointing at I3 when I3's destination is changed. */
10721 distribute_links (links
)
10724 rtx link
, next_link
;
10726 for (link
= links
; link
; link
= next_link
)
10732 next_link
= XEXP (link
, 1);
10734 /* If the insn that this link points to is a NOTE or isn't a single
10735 set, ignore it. In the latter case, it isn't clear what we
10736 can do other than ignore the link, since we can't tell which
10737 register it was for. Such links wouldn't be used by combine
10740 It is not possible for the destination of the target of the link to
10741 have been changed by combine. The only potential of this is if we
10742 replace I3, I2, and I1 by I3 and I2. But in that case the
10743 destination of I2 also remains unchanged. */
10745 if (GET_CODE (XEXP (link
, 0)) == NOTE
10746 || (set
= single_set (XEXP (link
, 0))) == 0)
10749 reg
= SET_DEST (set
);
10750 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
10751 || GET_CODE (reg
) == SIGN_EXTRACT
10752 || GET_CODE (reg
) == STRICT_LOW_PART
)
10753 reg
= XEXP (reg
, 0);
10755 /* A LOG_LINK is defined as being placed on the first insn that uses
10756 a register and points to the insn that sets the register. Start
10757 searching at the next insn after the target of the link and stop
10758 when we reach a set of the register or the end of the basic block.
10760 Note that this correctly handles the link that used to point from
10761 I3 to I2. Also note that not much searching is typically done here
10762 since most links don't point very far away. */
10764 for (insn
= NEXT_INSN (XEXP (link
, 0));
10765 (insn
&& (this_basic_block
== n_basic_blocks
- 1
10766 || basic_block_head
[this_basic_block
+ 1] != insn
));
10767 insn
= NEXT_INSN (insn
))
10768 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
10769 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
10771 if (reg_referenced_p (reg
, PATTERN (insn
)))
10775 else if (GET_CODE (insn
) == CALL_INSN
10776 && find_reg_fusage (insn
, USE
, reg
))
10782 /* If we found a place to put the link, place it there unless there
10783 is already a link to the same insn as LINK at that point. */
10789 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
10790 if (XEXP (link2
, 0) == XEXP (link
, 0))
10795 XEXP (link
, 1) = LOG_LINKS (place
);
10796 LOG_LINKS (place
) = link
;
10798 /* Set added_links_insn to the earliest insn we added a
10800 if (added_links_insn
== 0
10801 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
10802 added_links_insn
= place
;
10809 dump_combine_stats (file
)
10814 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
10815 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
10819 dump_combine_total_stats (file
)
10824 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
10825 total_attempts
, total_merges
, total_extras
, total_successes
);