| blob | 3ec5c9fb635b70337fa49293b07ffc6ad9b6e9f4 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2016 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
68 /* This file should be included last. */
71 /* Defined for convenience. */
72 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
74 /* Classifies an address.
76 ADDRESS_REG_IMM
77 A simple base register plus immediate offset.
79 ADDRESS_REG_WB
80 A base register indexed by immediate offset with writeback.
82 ADDRESS_REG_REG
83 A base register indexed by (optionally scaled) register.
85 ADDRESS_REG_UXTW
86 A base register indexed by (optionally scaled) zero-extended register.
88 ADDRESS_REG_SXTW
89 A base register indexed by (optionally scaled) sign-extended register.
91 ADDRESS_LO_SUM
92 A LO_SUM rtx with a base register and "LO12" symbol relocation.
94 ADDRESS_SYMBOLIC:
95 A constant symbolic address, in pc-relative literal pool. */
98 ADDRESS_REG_IMM,
99 ADDRESS_REG_WB,
100 ADDRESS_REG_REG,
101 ADDRESS_REG_UXTW,
102 ADDRESS_REG_SXTW,
103 ADDRESS_LO_SUM,
104 ADDRESS_SYMBOLIC
105 };
109 rtx base;
110 rtx offset;
113 };
115 struct simd_immediate_info
116 {
117 rtx value;
122 };
124 /* The current code model. */
127 #ifdef HAVE_AS_TLS
128 #undef TARGET_HAVE_TLS
129 #define TARGET_HAVE_TLS 1
130 #endif
134 const_tree,
145 /* Major revision number of the ARM Architecture implemented by the target. */
148 /* The processor for which instructions should be scheduled. */
151 /* Mask to specify which instruction scheduling options should be used. */
154 /* Global flag for PC relative loads. */
157 /* Support for command line parsing of boolean flags in the tuning
158 structures. */
159 struct aarch64_flag_desc
160 {
163 };
165 #define AARCH64_FUSION_PAIR(name, internal_name) \
166 { name, AARCH64_FUSE_##internal_name },
168 {
173 };
174 #undef AARCH64_FUION_PAIR
176 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
177 { name, AARCH64_EXTRA_TUNE_##internal_name },
179 {
184 };
185 #undef AARCH64_EXTRA_TUNING_OPTION
187 /* Tuning parameters. */
190 {
191 {
196 },
203 };
206 {
207 {
212 },
219 };
222 {
223 {
228 },
235 };
238 {
239 {
244 },
251 };
254 {
256 /* Avoid the use of slow int<->fp moves for spilling by setting
257 their cost higher than memmov_cost. */
261 };
264 {
266 /* Avoid the use of slow int<->fp moves for spilling by setting
267 their cost higher than memmov_cost. */
271 };
274 {
276 /* Avoid the use of slow int<->fp moves for spilling by setting
277 their cost higher than memmov_cost. */
281 };
284 {
286 /* Avoid the use of slow int<->fp moves for spilling by setting
287 their cost higher than memmov_cost (actual, 4 and 9). */
291 };
294 {
299 };
302 {
304 /* Avoid the use of slow int<->fp moves for spilling by setting
305 their cost higher than memmov_cost. */
309 };
311 /* Generic costs for vector insn classes. */
313 {
327 };
329 /* Generic costs for vector insn classes. */
331 {
345 };
348 {
362 };
364 /* Generic costs for vector insn classes. */
366 {
380 };
382 /* Generic costs for branch instructions. */
384 {
387 };
389 /* Branch costs for Cortex-A57. */
391 {
394 };
397 {
418 };
421 {
443 };
446 {
468 };
471 {
493 };
496 {
518 };
521 {
542 };
545 {
566 };
569 {
590 };
592 /* Support for fine-grained override of the tuning structures. */
593 struct aarch64_tuning_override_function
594 {
597 };
602 static const struct aarch64_tuning_override_function
603 aarch64_tuning_override_functions[] =
604 {
608 };
610 /* A processor implementing AArch64. */
611 struct processor
612 {
620 };
622 /* Architectures implementing AArch64. */
624 {
625 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
626 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
628 #undef AARCH64_ARCH
630 };
632 /* Processor cores implementing AArch64. */
634 {
635 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART) \
636 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
637 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
638 FLAGS, &COSTS##_tunings},
640 #undef AARCH64_CORE
644 };
647 /* Target specification. These are populated by the -march, -mtune, -mcpu
648 handling code or by target attributes. */
653 /* The current tuning set. */
656 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
658 /* An ISA extension in the co-processor and main instruction set space. */
659 struct aarch64_option_extension
660 {
664 };
667 {
671 }
672 aarch64_cc;
674 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
676 /* The condition codes of the processor, and the inverse function. */
678 {
681 };
683 /* Generate code to enable conditional branches in functions over 1 MiB. */
687 {
704 }
706 void
708 {
712 else
714 }
716 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
717 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
718 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
719 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
720 cost (in this case the best class is the lowest cost one). Using ALL_REGS
721 irrespectively of its cost results in bad allocations with many redundant
722 int<->FP moves which are expensive on various cores.
723 To avoid this we don't allow ALL_REGS as the allocno class, but force a
724 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
725 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
726 Otherwise set the allocno class depending on the mode.
727 The result of this is that it is no longer inefficient to have a higher
728 memory move cost than the register move cost.
729 */
731 static reg_class_t
733 reg_class_t best_class)
734 {
745 }
747 static unsigned int
749 {
753 }
755 static int
758 {
766 }
768 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
769 unsigned
771 {
779 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
780 equivalent DWARF register. */
782 }
784 /* Return TRUE if MODE is any of the large INT modes. */
785 static bool
787 {
789 }
791 /* Return TRUE if MODE is any of the vector modes. */
792 static bool
794 {
797 }
799 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
800 static bool
803 {
811 }
813 /* Implement HARD_REGNO_NREGS. */
815 int
817 {
819 {
825 }
827 }
829 /* Implement HARD_REGNO_MODE_OK. */
831 int
833 {
838 /* The purpose of comparing with ptr_mode is to support the
839 global register variable associated with the stack pointer
840 register via the syntax of asm ("wsp") in ILP32. */
850 {
852 return
854 else
856 }
859 }
861 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
862 machine_mode
864 machine_mode mode)
865 {
866 /* Handle modes that fit within single registers. */
868 {
871 else
873 }
874 /* Fall back to generic for multi-reg and very large modes. */
875 else
877 }
879 /* Return true if calls to DECL should be treated as
880 long-calls (ie called via a register). */
881 static bool
883 {
885 }
887 /* Return true if calls to symbol-ref SYM should be treated as
888 long-calls (ie called via a register). */
889 bool
891 {
893 }
895 /* Return true if calls to symbol-ref SYM should not go through
896 plt stubs. */
898 bool
900 {
904 && decl
905 && (!flag_plt
911 }
913 /* Return true if the offsets to a zero/sign-extract operation
914 represent an expression that matches an extend operation. The
915 operands represent the paramters from
917 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
918 bool
920 rtx extract_imm)
921 {
938 }
940 /* Emit an insn that's a simple single-set. Both the operands must be
941 known to be valid. */
944 {
946 }
948 /* X and Y are two things to compare using CODE. Emit the compare insn and
949 return the rtx for register 0 in the proper mode. */
950 rtx
952 {
958 }
960 /* Build the SYMBOL_REF for __tls_get_addr. */
964 rtx
966 {
970 }
972 /* Return the TLS model to use for ADDR. */
974 static enum tls_model
976 {
981 {
985 }
990 }
992 /* We'll allow lo_sum's in addresses in our legitimate addresses
993 so that combine would take care of combining addresses where
994 necessary, but for generation purposes, we'll generate the address
995 as :
996 RTL Absolute
997 tmp = hi (symbol_ref); adrp x1, foo
998 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
999 nop
1001 PIC TLS
1002 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1003 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1004 bl __tls_get_addr
1005 nop
1007 Load TLS symbol, depending on TLS mechanism and TLS access model.
1009 Global Dynamic - Traditional TLS:
1010 adrp tmp, :tlsgd:imm
1011 add dest, tmp, #:tlsgd_lo12:imm
1012 bl __tls_get_addr
1014 Global Dynamic - TLS Descriptors:
1015 adrp dest, :tlsdesc:imm
1016 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1017 add dest, dest, #:tlsdesc_lo12:imm
1018 blr tmp
1019 mrs tp, tpidr_el0
1020 add dest, dest, tp
1022 Initial Exec:
1023 mrs tp, tpidr_el0
1024 adrp tmp, :gottprel:imm
1025 ldr dest, [tmp, #:gottprel_lo12:imm]
1026 add dest, dest, tp
1028 Local Exec:
1029 mrs tp, tpidr_el0
1030 add t0, tp, #:tprel_hi12:imm, lsl #12
1031 add t0, t0, #:tprel_lo12_nc:imm
1032 */
1034 static void
1037 {
1039 {
1041 {
1042 /* In ILP32, the mode of dest can be either SImode or DImode. */
1054 }
1061 {
1064 rtx insn;
1065 rtx mem;
1067 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1068 here before rtl expand. Tree IVOPT will generate rtl pattern to
1069 decide rtx costs, in which case pic_offset_table_rtx is not
1070 initialized. For that case no need to generate the first adrp
1071 instruction as the final cost for global variable access is
1072 one instruction. */
1074 {
1075 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1076 using the page base as GOT base, the first page may be wasted,
1077 in the worst scenario, there is only 28K space for GOT).
1079 The generate instruction sequence for accessing global variable
1080 is:
1082 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1084 Only one instruction needed. But we must initialize
1085 pic_offset_table_rtx properly. We generate initialize insn for
1086 every global access, and allow CSE to remove all redundant.
1088 The final instruction sequences will look like the following
1089 for multiply global variables access.
1091 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1093 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1094 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1095 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1096 ... */
1104 }
1107 {
1110 else
1114 }
1115 else
1116 {
1121 }
1123 /* The operand is expected to be MEM. Whenever the related insn
1124 pattern changed, above code which calculate mem should be
1125 updated. */
1131 }
1134 {
1135 /* In ILP32, the mode of dest can be either SImode or DImode,
1136 while the got entry is always of SImode size. The mode of
1137 dest depends on how dest is used: if dest is assigned to a
1138 pointer (e.g. in the memory), it has SImode; it may have
1139 DImode if dest is dereferenced to access the memeory.
1140 This is why we have to handle three different ldr_got_small
1141 patterns here (two patterns for ILP32). */
1143 rtx insn;
1144 rtx mem;
1153 {
1156 else
1160 }
1161 else
1162 {
1167 }
1174 }
1177 {
1189 }
1192 {
1195 rtx tp;
1199 /* In ILP32, the got entry is always of SImode size. Unlike
1200 small GOT, the dest is fixed at reg 0. */
1203 else
1213 }
1216 {
1217 /* In ILP32, the mode of dest can be either SImode or DImode,
1218 while the got entry is always of SImode size. The mode of
1219 dest depends on how dest is used: if dest is assigned to a
1220 pointer (e.g. in the memory), it has SImode; it may have
1221 DImode if dest is dereferenced to access the memeory.
1222 This is why we have to handle three different tlsie_small
1223 patterns here (two patterns for ILP32). */
1229 {
1232 else
1233 {
1236 }
1237 }
1238 else
1239 {
1242 }
1247 }
1253 {
1261 {
1284 }
1288 }
1295 {
1300 {
1303 else
1304 {
1307 }
1308 }
1309 else
1310 {
1313 }
1317 }
1321 }
1322 }
1324 /* Emit a move from SRC to DEST. Assume that the move expanders can
1325 handle all moves if !can_create_pseudo_p (). The distinction is
1326 important because, unlike emit_move_insn, the move expanders know
1327 how to force Pmode objects into the constant pool even when the
1328 constant pool address is not itself legitimate. */
1329 static rtx
1331 {
1335 }
1337 /* Split a 128-bit move operation into two 64-bit move operations,
1338 taking care to handle partial overlap of register to register
1339 copies. Special cases are needed when moving between GP regs and
1340 FP regs. SRC can be a register, constant or memory; DST a register
1341 or memory. If either operand is memory it must not have any side
1342 effects. */
1343 void
1345 {
1356 {
1360 /* Handle FP <-> GP regs. */
1362 {
1367 {
1370 }
1371 else
1372 {
1375 }
1377 }
1379 {
1384 {
1387 }
1388 else
1389 {
1392 }
1394 }
1395 }
1402 /* At most one pairing may overlap. */
1404 {
1407 }
1408 else
1409 {
1412 }
1413 }
1415 bool
1417 {
1420 }
1422 /* Split a complex SIMD combine. */
1424 void
1426 {
1433 {
1437 {
1461 }
1465 }
1466 }
1468 /* Split a complex SIMD move. */
1470 void
1472 {
1479 {
1485 {
1509 }
1513 }
1514 }
1516 bool
1519 {
1523 }
1526 static rtx
1528 {
1531 else
1532 {
1535 }
1536 }
1539 static rtx
1541 {
1543 {
1544 rtx high;
1545 /* Load the full offset into a register. This
1546 might be improvable in the future. */
1552 }
1554 }
1556 static int
1558 machine_mode mode)
1559 {
1568 {
1572 }
1575 {
1577 {
1582 else
1585 }
1587 }
1589 /* Remaining cases are all for DImode. */
1598 {
1599 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1600 For a 64-bit bitmask try whether changing 16 bits to all ones or
1601 zeroes creates a valid bitmask. To check any repeated bitmask,
1602 try using 16 bits from the other 32-bit half of val. */
1605 {
1616 }
1618 {
1620 {
1624 }
1626 }
1627 }
1629 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1630 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1631 otherwise skip zero bits. */
1643 {
1649 num_insns ++;
1650 }
1653 }
1656 void
1658 {
1663 /* Check on what type of symbol it is. */
1667 {
1671 /* If we have (const (plus symbol offset)), separate out the offset
1672 before we start classifying the symbol. */
1677 {
1681 {
1687 }
1692 /* If we aren't generating PC relative literals, then
1693 we need to expand the literal pool access carefully.
1694 This is something that needs to be done in a number
1695 of places, so could well live as a separate function. */
1697 {
1702 }
1719 {
1725 }
1726 /* FALLTHRU */
1739 }
1740 }
1743 {
1746 else
1747 {
1751 }
1754 }
1757 }
1759 static bool
1761 tree exp ATTRIBUTE_UNUSED)
1762 {
1763 /* Currently, always true. */
1765 }
1767 /* Implement TARGET_PASS_BY_REFERENCE. */
1769 static bool
1771 machine_mode mode,
1772 const_tree type,
1774 {
1775 HOST_WIDE_INT size;
1776 machine_mode dummymode;
1779 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
1783 /* Aggregates are passed by reference based on their size. */
1785 {
1787 }
1789 /* Variable sized arguments are always returned by reference. */
1793 /* Can this be a candidate to be passed in fp/simd register(s)? */
1796 NULL))
1799 /* Arguments which are variable sized or larger than 2 registers are
1800 passed by reference unless they are a homogenous floating point
1801 aggregate. */
1803 }
1805 /* Return TRUE if VALTYPE is padded to its least significant bits. */
1806 static bool
1808 {
1809 machine_mode dummy_mode;
1812 /* Never happens in little-endian mode. */
1816 /* Only composite types smaller than or equal to 16 bytes can
1817 be potentially returned in registers. */
1823 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
1824 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
1825 is always passed/returned in the least significant bits of fp/simd
1826 register(s). */
1832 }
1834 /* Implement TARGET_FUNCTION_VALUE.
1835 Define how to find the value returned by a function. */
1837 static rtx
1840 {
1841 machine_mode mode;
1844 machine_mode ag_mode;
1851 {
1855 {
1858 }
1859 }
1863 {
1865 {
1868 }
1869 else
1870 {
1872 rtx par;
1876 {
1881 }
1883 }
1884 }
1885 else
1887 }
1889 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
1890 Return true if REGNO is the number of a hard register in which the values
1891 of called function may come back. */
1893 static bool
1895 {
1896 /* Maximum of 16 bytes can be returned in the general registers. Examples
1897 of 16-byte return values are: 128-bit integers and 16-byte small
1898 structures (excluding homogeneous floating-point aggregates). */
1902 /* Up to four fp/simd registers can return a function value, e.g. a
1903 homogeneous floating-point aggregate having four members. */
1908 }
1910 /* Implement TARGET_RETURN_IN_MEMORY.
1912 If the type T of the result of a function is such that
1913 void func (T arg)
1914 would require that arg be passed as a value in a register (or set of
1915 registers) according to the parameter passing rules, then the result
1916 is returned in the same registers as would be used for such an
1917 argument. */
1919 static bool
1921 {
1922 HOST_WIDE_INT size;
1923 machine_mode ag_mode;
1929 /* Simple scalar types always returned in registers. */
1933 type,
1936 NULL))
1939 /* Types larger than 2 registers returned in memory. */
1942 }
1944 static bool
1947 {
1950 type,
1952 nregs,
1953 NULL);
1954 }
1956 /* Given MODE and TYPE of a function argument, return the alignment in
1957 bits. The idea is to suppress any stronger alignment requested by
1958 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
1959 This is a helper function for local use only. */
1961 static unsigned int
1963 {
1967 {
1969 {
1972 else
1974 }
1975 else
1977 }
1978 else
1982 }
1984 /* Layout a function argument according to the AAPCS64 rules. The rule
1985 numbers refer to the rule numbers in the AAPCS64. */
1987 static void
1989 const_tree type,
1991 {
1995 HOST_WIDE_INT size;
1997 /* We need to do this once per argument. */
2003 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2004 size
2006 UNITS_PER_WORD);
2010 mode,
2011 type,
2014 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2015 The following code thus handles passing by SIMD/FP registers first. */
2019 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2020 and homogenous short-vector aggregates (HVA). */
2022 {
2027 {
2030 {
2033 }
2034 else
2035 {
2036 rtx par;
2040 {
2043 tmp = gen_rtx_EXPR_LIST
2047 }
2049 }
2051 }
2052 else
2053 {
2054 /* C.3 NSRN is set to 8. */
2057 }
2058 }
2063 /* C6 - C9. though the sign and zero extension semantics are
2064 handled elsewhere. This is the case where the argument fits
2065 entirely general registers. */
2067 {
2072 /* C.8 if the argument has an alignment of 16 then the NGRN is
2073 rounded up to the next even number. */
2075 {
2078 }
2079 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2080 A reg is still generated for it, but the caller should be smart
2081 enough not to use it. */
2083 {
2085 }
2086 else
2087 {
2088 rtx par;
2093 {
2098 }
2100 }
2104 }
2106 /* C.11 */
2109 /* The argument is passed on stack; record the needed number of words for
2110 this argument and align the total size if necessary. */
2111 on_stack:
2117 }
2119 /* Implement TARGET_FUNCTION_ARG. */
2121 static rtx
2124 {
2133 }
2135 void
2137 const_tree fntype ATTRIBUTE_UNUSED,
2138 rtx libname ATTRIBUTE_UNUSED,
2139 const_tree fndecl ATTRIBUTE_UNUSED,
2141 {
2155 {
2162 }
2164 }
2166 static void
2168 machine_mode mode,
2169 const_tree type,
2171 {
2174 {
2184 }
2185 }
2187 bool
2189 {
2192 }
2194 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2195 PARM_BOUNDARY bits of alignment, but will be given anything up
2196 to STACK_BOUNDARY bits if the type requires it. This makes sure
2197 that both before and after the layout of each argument, the Next
2198 Stacked Argument Address (NSAA) will have a minimum alignment of
2199 8 bytes. */
2201 static unsigned int
2203 {
2211 }
2213 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2215 Return true if an argument passed on the stack should be padded upwards,
2216 i.e. if the least-significant byte of the stack slot has useful data.
2218 Small aggregate types are placed in the lowest memory address.
2220 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2222 bool
2224 {
2225 /* On little-endian targets, the least significant byte of every stack
2226 argument is passed at the lowest byte address of the stack slot. */
2230 /* Otherwise, integral, floating-point and pointer types are padded downward:
2231 the least significant byte of a stack argument is passed at the highest
2232 byte address of the stack slot. */
2239 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2241 }
2243 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2245 It specifies padding for the last (may also be the only)
2246 element of a block move between registers and memory. If
2247 assuming the block is in the memory, padding upward means that
2248 the last element is padded after its highest significant byte,
2249 while in downward padding, the last element is padded at the
2250 its least significant byte side.
2252 Small aggregates and small complex types are always padded
2253 upwards.
2255 We don't need to worry about homogeneous floating-point or
2256 short-vector aggregates; their move is not affected by the
2257 padding direction determined here. Regardless of endianness,
2258 each element of such an aggregate is put in the least
2259 significant bits of a fp/simd register.
2261 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2262 register has useful data, and return the opposite if the most
2263 significant byte does. */
2265 bool
2268 {
2270 /* Small composite types are always padded upward. */
2272 {
2277 }
2279 /* Otherwise, use the default padding. */
2281 }
2283 static machine_mode
2285 {
2287 }
2289 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2291 /* We use the 12-bit shifted immediate arithmetic instructions so values
2292 must be multiple of (1 << 12), i.e. 4096. */
2293 #define ARITH_FACTOR 4096
2295 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2296 #error Cannot use simple address calculation for stack probing
2297 #endif
2299 /* The pair of scratch registers used for stack probing. */
2300 #define PROBE_STACK_FIRST_REG 9
2301 #define PROBE_STACK_SECOND_REG 10
2303 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2304 inclusive. These are offsets from the current stack pointer. */
2306 static void
2308 {
2311 /* See the same assertion on PROBE_INTERVAL above. */
2314 /* See if we have a constant small number of probes to generate. If so,
2315 that's the easy case. */
2317 {
2324 }
2326 /* The run-time loop is made up of 8 insns in the generic case while the
2327 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2329 {
2334 stack_pointer_rtx,
2338 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2339 it exceeds SIZE. If only two probes are needed, this will not
2340 generate any code. Then probe at FIRST + SIZE. */
2342 {
2346 }
2350 {
2355 }
2356 else
2358 }
2360 /* Otherwise, do the same as above, but in a loop. Note that we must be
2361 extra careful with variables wrapping around because we might be at
2362 the very top (or the very bottom) of the address space and we have
2363 to be able to handle this case properly; in particular, we use an
2364 equality test for the loop condition. */
2365 else
2366 {
2369 /* Step 1: round SIZE to the previous multiple of the interval. */
2374 /* Step 2: compute initial and final value of the loop counter. */
2376 /* TEST_ADDR = SP + FIRST. */
2380 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2386 /* Step 3: the loop
2388 do
2389 {
2390 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2391 probe at TEST_ADDR
2392 }
2393 while (TEST_ADDR != LAST_ADDR)
2395 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2396 until it is equal to ROUNDED_SIZE. */
2400 else
2404 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2405 that SIZE is equal to ROUNDED_SIZE. */
2408 {
2412 {
2417 }
2418 else
2420 }
2421 }
2423 /* Make sure nothing is scheduled before we are done. */
2425 }
2427 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2428 absolute addresses. */
2432 {
2439 /* Loop. */
2442 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2447 /* Probe at TEST_ADDR. */
2450 /* Test if TEST_ADDR == LAST_ADDR. */
2454 /* Branch. */
2460 }
2462 static bool
2464 {
2465 /* In aarch64_override_options_after_change
2466 flag_omit_leaf_frame_pointer turns off the frame pointer by
2467 default. Turn it back on now if we've not got a leaf
2468 function. */
2474 }
2476 /* Mark the registers that need to be saved by the callee and calculate
2477 the size of the callee-saved registers area and frame record (both FP
2478 and LR may be omitted). */
2479 static void
2481 {
2488 #define SLOT_NOT_REQUIRED (-2)
2489 #define SLOT_REQUIRED (-1)
2494 /* First mark all the registers that really need to be saved... */
2501 /* ... that includes the eh data registers (if needed)... */
2507 /* ... and any callee saved register that dataflow says is live. */
2520 {
2521 /* FP and LR are placed in the linkage record. */
2528 }
2530 /* Now assign stack slots for them. */
2533 {
2540 }
2544 {
2552 }
2572 }
2574 static bool
2576 {
2578 }
2580 static unsigned
2582 {
2584 regno ++;
2586 }
2588 static void
2590 HOST_WIDE_INT adjustment)
2591 {
2602 }
2604 static rtx
2606 HOST_WIDE_INT adjustment)
2607 {
2609 {
2620 }
2621 }
2623 static void
2626 {
2636 }
2638 static rtx
2640 HOST_WIDE_INT adjustment)
2641 {
2643 {
2652 }
2653 }
2655 static rtx
2657 rtx reg2)
2658 {
2660 {
2669 }
2670 }
2672 static rtx
2674 rtx mem2)
2675 {
2677 {
2686 }
2687 }
2690 static void
2693 {
2703 {
2705 HOST_WIDE_INT offset;
2715 offset));
2723 {
2725 rtx mem2;
2729 offset));
2731 reg2));
2733 /* The first part of a frame-related parallel insn is
2734 always assumed to be relevant to the frame
2735 calculations; subsequent parts, are only
2736 frame-related if explicitly marked. */
2739 }
2740 else
2744 }
2745 }
2747 static void
2751 {
2757 HOST_WIDE_INT offset;
2762 {
2779 {
2781 rtx mem2;
2789 }
2790 else
2793 }
2794 }
2796 /* AArch64 stack frames generated by this compiler look like:
2798 +-------------------------------+
2799 | |
2800 | incoming stack arguments |
2801 | |
2802 +-------------------------------+
2803 | | <-- incoming stack pointer (aligned)
2804 | callee-allocated save area |
2805 | for register varargs |
2806 | |
2807 +-------------------------------+
2808 | local variables | <-- frame_pointer_rtx
2809 | |
2810 +-------------------------------+
2811 | padding0 | \
2812 +-------------------------------+ |
2813 | callee-saved registers | | frame.saved_regs_size
2814 +-------------------------------+ |
2815 | LR' | |
2816 +-------------------------------+ |
2817 | FP' | / <- hard_frame_pointer_rtx (aligned)
2818 +-------------------------------+
2819 | dynamic allocation |
2820 +-------------------------------+
2821 | padding |
2822 +-------------------------------+
2823 | outgoing stack arguments | <-- arg_pointer
2824 | |
2825 +-------------------------------+
2826 | | <-- stack_pointer_rtx (aligned)
2828 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
2829 but leave frame_pointer_rtx and hard_frame_pointer_rtx
2830 unchanged. */
2832 /* Generate the prologue instructions for entry into a function.
2833 Establish the stack frame by decreasing the stack pointer with a
2834 properly calculated size and, if necessary, create a frame record
2835 filled with the values of LR and previous frame pointer. The
2836 current FP is also set up if it is in use. */
2838 void
2840 {
2841 /* sub sp, sp, #<frame_size>
2842 stp {fp, lr}, [sp, #<frame_size> - 16]
2843 add fp, sp, #<frame_size> - hardfp_offset
2844 stp {cs_reg}, [fp, #-16] etc.
2846 sub sp, sp, <final_adjustment_if_any>
2847 */
2850 HOST_WIDE_INT hard_fp_offset;
2863 {
2865 {
2869 }
2872 }
2874 /* Store pairs and load pairs have a range only -512 to 504. */
2876 {
2877 /* When the frame has a large size, an initial decrease is done on
2878 the stack pointer to jump over the callee-allocated save area for
2879 register varargs, the local variable area and/or the callee-saved
2880 register area. This will allow the pre-index write-back
2881 store pair instructions to be used for setting up the stack frame
2882 efficiently. */
2891 {
2901 }
2903 {
2908 {
2912 }
2914 {
2918 }
2919 }
2920 }
2921 else
2925 {
2929 {
2933 {
2940 }
2941 else
2944 /* Set up frame pointer to point to the location of the
2945 previous frame pointer on the stack. */
2947 stack_pointer_rtx,
2951 }
2952 else
2953 {
2961 {
2965 }
2966 else
2967 {
2974 else
2976 }
2977 }
2980 skip_wb);
2982 skip_wb);
2983 }
2985 /* when offset >= 512,
2986 sub sp, sp, #<outgoing_args_size> */
2988 {
2990 {
2995 }
2996 }
2997 }
2999 /* Return TRUE if we can use a simple_return insn.
3001 This function checks whether the callee saved stack is empty, which
3002 means no restore actions are need. The pro_and_epilogue will use
3003 this to check whether shrink-wrapping opt is feasible. */
3005 bool
3007 {
3017 }
3019 /* Generate the epilogue instructions for returning from a function. */
3020 void
3022 {
3024 HOST_WIDE_INT fp_offset;
3025 HOST_WIDE_INT hard_fp_offset;
3027 /* We need to add memory barrier to prevent read from deallocated stack. */
3037 /* Store pairs and load pairs have a range only -512 to 504. */
3039 {
3047 {
3052 }
3053 }
3054 else
3057 /* If there were outgoing arguments or we've done dynamic stack
3058 allocation, then restore the stack pointer from the frame
3059 pointer. This is at most one insn and more efficient than using
3060 GCC's internal mechanism. */
3063 {
3068 hard_frame_pointer_rtx,
3071 }
3074 {
3097 {
3103 {
3108 }
3109 else
3110 {
3117 }
3118 }
3119 else
3120 {
3123 }
3125 /* Reset the CFA to be SP + FRAME_SIZE. */
3132 }
3135 {
3140 {
3144 }
3145 else
3146 {
3151 {
3156 }
3159 }
3161 /* Reset the CFA to be SP + 0. */
3164 }
3166 /* Stack adjustment for exception handler. */
3168 {
3169 /* We need to unwind the stack by the offset computed by
3170 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3171 to be SP; letting the CFA move during this adjustment
3172 is just as correct as retaining the CFA from the body
3173 of the function. Therefore, do nothing special. */
3175 }
3180 }
3182 /* Return the place to copy the exception unwinding return address to.
3183 This will probably be a stack slot, but could (in theory be the
3184 return register). */
3185 rtx
3187 {
3188 HOST_WIDE_INT fp_offset;
3198 /* DSE and CSELIB do not detect an alias between sp+k1 and fp+k2. This can
3199 result in a store to save LR introduced by builtin_eh_return () being
3200 incorrectly deleted because the alias is not detected.
3201 So in the calculation of the address to copy the exception unwinding
3202 return address to, we note 2 cases.
3203 If FP is needed and the fp_offset is 0, it means that SP = FP and hence
3204 we return a SP-relative location since all the addresses are SP-relative
3205 in this case. This prevents the store from being optimized away.
3206 If the fp_offset is not 0, then the addresses will be FP-relative and
3207 therefore we return a FP-relative location. */
3210 {
3214 else
3217 }
3219 /* If FP is not needed, we calculate the location of LR, which would be
3220 at the top of the saved registers block. */
3224 stack_pointer_rtx,
3225 fp_offset
3228 }
3230 /* Possibly output code to build up a constant in a register. For
3231 the benefit of the costs infrastructure, returns the number of
3232 instructions which would be emitted. GENERATE inhibits or
3233 enables code generation. */
3235 static int
3237 {
3241 {
3245 }
3246 else
3247 {
3252 HOST_WIDE_INT valm;
3253 HOST_WIDE_INT tval;
3256 {
3266 }
3268 /* zcount contains the number of additional MOVK instructions
3269 required if the constant is built up with an initial MOVZ instruction,
3270 while ncount is the number of MOVK instructions required if starting
3271 with a MOVN instruction. Choose the sequence that yields the fewest
3272 number of instructions, preferring MOVZ instructions when they are both
3273 the same. */
3275 {
3280 insns++;
3281 }
3282 else
3283 {
3288 insns++;
3289 }
3294 {
3296 {
3301 insns++;
3302 }
3304 }
3305 }
3307 }
3309 static void
3311 {
3320 {
3323 }
3325 {
3327 {
3333 else
3336 }
3338 {
3342 }
3343 }
3344 }
3346 /* Output code to add DELTA to the first argument, and then jump
3347 to FUNCTION. Used for C++ multiple inheritance. */
3348 static void
3350 HOST_WIDE_INT delta,
3351 HOST_WIDE_INT vcall_offset,
3352 tree function)
3353 {
3354 /* The this pointer is always in x0. Note that this differs from
3355 Arm where the this pointer maybe bumped to r1 if r0 is required
3356 to return a pointer to an aggregate. On AArch64 a result value
3357 pointer will be in x8. */
3367 else
3368 {
3377 {
3381 else
3383 }
3387 else
3394 else
3395 {
3398 }
3402 else
3408 }
3410 /* Generate a tail call to the target function. */
3412 {
3415 }
3427 /* Stop pretending to be a post-reload pass. */
3429 }
3431 static bool
3433 {
3438 {
3442 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3443 TLS offsets, not real symbol references. */
3446 }
3448 }
3451 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3452 a left shift of 0 or 12 bits. */
3453 bool
3455 {
3458 );
3459 }
3462 /* Return true if val is an immediate that can be loaded into a
3463 register by a MOVZ instruction. */
3464 static bool
3466 {
3468 {
3472 }
3473 else
3474 {
3475 /* Ignore sign extension. */
3477 }
3480 }
3482 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
3485 {
3491 };
3494 /* Return true if val is a valid bitmask immediate. */
3496 bool
3498 {
3502 /* Check for a single sequence of one bits and return quickly if so.
3503 The special cases of all ones and all zeroes returns false. */
3510 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
3514 /* Invert if the immediate doesn't start with a zero bit - this means we
3515 only need to search for sequences of one bits. */
3519 /* Find the first set bit and set tmp to val with the first sequence of one
3520 bits removed. Return success if there is a single sequence of ones. */
3527 /* Find the next set bit and compute the difference in bit position. */
3532 /* Check the bit position difference is a power of 2, and that the first
3533 sequence of one bits fits within 'bits' bits. */
3537 /* Check the sequence of one bits is repeated 64/bits times. */
3539 }
3542 /* Return true if val is an immediate that can be loaded into a
3543 register in a single instruction. */
3544 bool
3546 {
3550 }
3552 static bool
3554 {
3562 {
3566 else
3567 /* Avoid generating a 64-bit relocation in ILP32; leave
3568 to aarch64_expand_mov_immediate to handle it properly. */
3570 }
3573 }
3575 /* Implement TARGET_CASE_VALUES_THRESHOLD.
3576 The expansion for a table switch is quite expensive due to the number
3577 of instructions, the table lookup and hard to predict indirect jump.
3578 When optimizing for speed, and -O3 enabled, use the per-core tuning if
3579 set, otherwise use tables for > 16 cases as a tradeoff between size and
3580 performance. When optimizing for size, use the default setting. */
3582 static unsigned int
3584 {
3585 /* Use the specified limit for the number of cases before using jump
3586 tables at higher optimization levels. */
3590 else
3592 }
3594 /* Return true if register REGNO is a valid index register.
3595 STRICT_P is true if REG_OK_STRICT is in effect. */
3597 bool
3599 {
3601 {
3609 }
3611 }
3613 /* Return true if register REGNO is a valid base register for mode MODE.
3614 STRICT_P is true if REG_OK_STRICT is in effect. */
3616 bool
3618 {
3620 {
3628 }
3630 /* The fake registers will be eliminated to either the stack or
3631 hard frame pointer, both of which are usually valid base registers.
3632 Reload deals with the cases where the eliminated form isn't valid. */
3637 }
3639 /* Return true if X is a valid base register for mode MODE.
3640 STRICT_P is true if REG_OK_STRICT is in effect. */
3642 static bool
3644 {
3649 }
3651 /* Return true if address offset is a valid index. If it is, fill in INFO
3652 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
3654 static bool
3657 {
3659 rtx index;
3662 /* (reg:P) */
3665 {
3669 }
3670 /* (sign_extend:DI (reg:SI)) */
3675 {
3680 }
3681 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
3688 {
3693 }
3694 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
3701 {
3706 }
3707 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
3714 {
3722 }
3723 /* (and:DI (mult:DI (reg:DI) (const_int scale))
3724 (const_int 0xffffffff<<shift)) */
3731 {
3737 }
3738 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
3745 {
3753 }
3754 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
3755 (const_int 0xffffffff<<shift)) */
3762 {
3768 }
3769 /* (mult:P (reg:P) (const_int scale)) */
3774 {
3778 }
3779 /* (ashift:P (reg:P) (const_int shift)) */
3784 {
3788 }
3789 else
3800 {
3805 }
3808 }
3810 bool
3812 {
3816 }
3820 HOST_WIDE_INT offset)
3821 {
3823 }
3827 {
3831 }
3833 /* Return true if MODE is one of the modes for which we
3834 support LDP/STP operations. */
3836 static bool
3838 {
3843 }
3845 /* Return true if REGNO is a virtual pointer register, or an eliminable
3846 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
3847 include stack_pointer or hard_frame_pointer. */
3848 static bool
3850 {
3855 }
3857 /* Return true if X is a valid address for machine mode MODE. If it is,
3858 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
3859 effect. OUTER_CODE is PARALLEL for a load/store pair. */
3861 static bool
3865 {
3869 /* On BE, we use load/store pair for all large int mode load/stores. */
3871 || (BYTES_BIG_ENDIAN
3875 !load_store_pair_p
3879 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
3880 REG addressing. */
3886 {
3902 {
3908 }
3913 {
3920 /* TImode and TFmode values are allowed in both pairs of X
3921 registers and individual Q registers. The available
3922 address modes are:
3923 X,X: 7-bit signed scaled offset
3924 Q: 9-bit signed offset
3925 We conservatively require an offset representable in either mode.
3926 */
3931 /* A 7bit offset check because OImode will emit a ldp/stp
3932 instruction (only big endian will get here).
3933 For ldp/stp instructions, the offset is scaled for the size of a
3934 single element of the pair. */
3938 /* Three 9/12 bit offsets checks because CImode will emit three
3939 ldr/str instructions (only big endian will get here). */
3946 /* Two 7bit offsets checks because XImode will emit two ldp/stp
3947 instructions (only big endian will get here). */
3956 else
3959 }
3962 {
3963 /* Look for base + (scaled/extended) index register. */
3966 {
3969 }
3972 {
3975 }
3976 }
3997 {
3998 HOST_WIDE_INT offset;
4002 /* TImode and TFmode values are allowed in both pairs of X
4003 registers and individual Q registers. The available
4004 address modes are:
4005 X,X: 7-bit signed scaled offset
4006 Q: 9-bit signed offset
4007 We conservatively require an offset representable in either mode.
4008 */
4016 else
4018 }
4024 /* load literal: pc-relative constant pool entry. Only supported
4025 for SI mode or larger. */
4029 {
4037 }
4046 {
4051 {
4052 /* The symbol and offset must be aligned to the access size. */
4059 {
4063 }
4069 else
4078 }
4079 }
4084 }
4085 }
4087 bool
4089 {
4090 rtx offset;
4094 }
4096 /* Classify the base of symbolic expression X. */
4098 enum aarch64_symbol_type
4100 {
4101 rtx offset;
4105 }
4108 /* Return TRUE if X is a legitimate address for accessing memory in
4109 mode MODE. */
4110 static bool
4112 {
4116 }
4118 /* Return TRUE if X is a legitimate address for accessing memory in
4119 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4120 pair operation. */
4121 bool
4124 {
4128 }
4130 /* Return TRUE if rtx X is immediate constant 0.0 */
4131 bool
4133 {
4140 }
4142 /* Return the fixed registers used for condition codes. */
4144 static bool
4146 {
4150 }
4152 /* Emit call insn with PAT and do aarch64-specific handling. */
4154 void
4156 {
4162 }
4164 machine_mode
4166 {
4167 /* All floating point compares return CCFP if it is an equality
4168 comparison, and CCFPE otherwise. */
4170 {
4172 {
4193 }
4194 }
4196 /* Equality comparisons of short modes against zero can be performed
4197 using the TST instruction with the appropriate bitmask. */
4212 /* A compare with a shifted operand. Because of canonicalization,
4213 the comparison will have to be swapped when we emit the assembly
4214 code. */
4222 /* Similarly for a negated operand, but we can only do this for
4223 equalities. */
4230 /* A test for unsigned overflow. */
4237 /* For everything else, return CCmode. */
4239 }
4241 static int
4244 int
4246 {
4253 }
4255 static int
4257 {
4259 {
4263 {
4277 }
4282 {
4294 }
4299 {
4311 }
4316 {
4322 }
4327 {
4331 }
4336 {
4340 }
4346 }
4349 }
4351 bool
4353 HOST_WIDE_INT minval,
4354 HOST_WIDE_INT maxval)
4355 {
4356 HOST_WIDE_INT firstval;
4373 }
4375 bool
4377 {
4379 }
4382 /* N Z C V. */
4383 #define AARCH64_CC_V 1
4384 #define AARCH64_CC_C (1 << 1)
4385 #define AARCH64_CC_Z (1 << 2)
4386 #define AARCH64_CC_N (1 << 3)
4388 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
4390 {
4407 };
4409 static void
4411 {
4413 {
4414 /* An integer or symbol address without a preceding # sign. */
4417 {
4429 {
4432 }
4433 /* Fall through. */
4437 }
4441 /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
4442 {
4447 {
4450 }
4453 {
4466 }
4467 }
4471 {
4474 /* Print N such that 2^N == X. */
4476 {
4479 }
4482 }
4486 /* Print the number of non-zero bits in X (a const_int). */
4488 {
4491 }
4497 /* Print the higher numbered register of a pair (TImode) of regs. */
4499 {
4502 }
4509 {
4511 /* Print a condition (eq, ne, etc) or its inverse. */
4513 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
4515 {
4519 }
4522 {
4525 }
4532 }
4540 /* Print a scalar FP/SIMD register name. */
4542 {
4543 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4545 }
4553 /* Print the first FP/SIMD register name in a list. */
4555 {
4556 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4558 }
4563 /* Print a scalar FP/SIMD register name + 1. */
4565 {
4566 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4568 }
4573 /* Print bottom 16 bits of integer constant in hex. */
4575 {
4578 }
4584 /* Print a general register name or the zero register (32-bit or
4585 64-bit). */
4588 {
4591 }
4594 {
4597 }
4600 {
4603 }
4605 /* Fall through */
4608 /* Print a normal operand, if it's a general register, then we
4609 assume DImode. */
4611 {
4614 }
4617 {
4638 {
4641 HOST_WIDE_INT_MIN,
4642 HOST_WIDE_INT_MAX));
4644 }
4646 {
4648 }
4649 else
4654 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
4655 be getting CONST_DOUBLEs holding integers. */
4658 {
4661 }
4663 {
4664 #define buf_size 20
4672 #undef buf_size
4673 }
4679 }
4687 {
4714 }
4720 {
4755 }
4762 {
4768 }
4773 {
4774 HOST_WIDE_INT cond_code;
4775 /* Print nzcv. */
4778 {
4781 }
4786 }
4792 }
4793 }
4795 static void
4797 {
4802 {
4806 else
4815 else
4824 else
4833 else
4840 {
4867 }
4878 }
4881 }
4883 bool
4885 {
4892 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
4893 referencing instruction, but they are constant offsets, not
4894 symbols. */
4900 {
4902 {
4908 }
4911 }
4914 }
4916 /* Implement REGNO_REG_CLASS. */
4918 enum reg_class
4920 {
4935 }
4937 static rtx
4939 {
4940 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
4941 where mask is selected by alignment and size of the offset.
4942 We try to pick as large a range for the offset as possible to
4943 maximize the chance of a CSE. However, for aligned addresses
4944 we limit the range to 4k so that structures with different sized
4945 elements are likely to use the same base. We need to be careful
4946 not to split a CONST for some forms of address expression, otherwise
4947 it will generate sub-optimal code. */
4950 {
4956 {
4960 /* Force any scaling into a temp for CSE. */
4964 /* Let the pointer register be in op0. */
4968 /* If the pointer is virtual or frame related, then we know that
4969 virtual register instantiation or register elimination is going
4970 to apply a second constant. We want the two constants folded
4971 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
4973 {
4977 }
4979 /* Otherwise, in order to encourage CSE (and thence loop strength
4980 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
4984 }
4986 /* Does it look like we'll need a load/store-pair operation? */
4987 HOST_WIDE_INT base_offset;
4992 /* For offsets aren't a multiple of the access size, the limit is
4993 -256...255. */
4996 else
5000 {
5004 }
5005 }
5008 }
5010 /* Return the reload icode required for a constant pool in mode. */
5011 static enum insn_code
5013 {
5015 {
5051 }
5054 }
5055 static reg_class_t
5057 reg_class_t rclass,
5058 machine_mode mode,
5060 {
5062 /* If we have to disable direct literal pool loads and stores because the
5063 function is too big, then we need a scratch register. */
5068 {
5071 }
5073 /* Without the TARGET_SIMD instructions we cannot move a Q register
5074 to a Q register directly. We need a scratch. */
5078 {
5084 }
5086 /* A TFmode or TImode memory access should be handled via an FP_REGS
5087 because AArch64 has richer addressing modes for LDR/STR instructions
5088 than LDP/STP instructions. */
5097 }
5099 static bool
5101 {
5102 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5103 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5106 {
5118 }
5119 else
5120 {
5121 /* If we decided that we didn't need a leaf frame pointer but then used
5122 LR in the function, then we'll want a frame pointer after all, so
5123 prevent this elimination to ensure a frame pointer is used. */
5125 && flag_omit_leaf_frame_pointer
5128 }
5131 }
5133 HOST_WIDE_INT
5135 {
5139 {
5146 }
5149 {
5153 }
5156 }
5158 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5159 previous frame. */
5161 rtx
5163 {
5167 }
5170 static void
5172 {
5174 {
5177 }
5178 else
5179 {
5182 }
5187 }
5189 static void
5191 {
5195 /* Don't need to copy the trailing D-words, we fill those in below. */
5207 /* XXX We should really define a "clear_cache" pattern and use
5208 gen_clear_cache(). */
5213 ptr_mode);
5214 }
5216 static unsigned char
5218 {
5220 {
5227 return
5239 }
5241 }
5243 static reg_class_t
5245 {
5250 {
5256 }
5258 /* If it's an integer immediate that MOVI can't handle, then
5259 FP_REGS is not an option, so we return NO_REGS instead. */
5264 /* Register eliminiation can result in a request for
5265 SP+constant->FP_REGS. We cannot support such operations which
5266 use SP as source and an FP_REG as destination, so reject out
5267 right now. */
5269 {
5272 /* Look through a possible SUBREG introduced by ILP32. */
5278 POINTER_REGS));
5280 }
5283 }
5285 void
5287 {
5289 }
5291 static void
5293 {
5296 else
5297 {
5305 }
5306 }
5308 static void
5310 {
5313 else
5314 {
5322 }
5323 }
5327 {
5333 {
5334 {
5337 },
5338 {
5341 },
5342 {
5345 },
5346 /* We assume that DImode is only generated when not optimizing and
5347 that we don't really need 64-bit address offsets. That would
5348 imply an object file with 8GB of code in a single function! */
5349 {
5352 }
5353 };
5361 /* Need to implement table size reduction, by chaning the code below. */
5371 }
5374 /* Return size in bits of an arithmetic operand which is shifted/scaled and
5375 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
5376 operator. */
5378 int
5380 {
5382 {
5385 {
5389 }
5390 }
5392 }
5394 /* Constant pools are per function only when PC relative
5395 literal loads are true or we are in the large memory
5396 model. */
5400 {
5403 }
5405 static bool
5407 {
5408 /* Fixme:: In an ideal world this would work similar
5409 to the logic in aarch64_select_rtx_section but this
5410 breaks bootstrap in gcc go. For now we workaround
5411 this by returning false here. */
5413 }
5415 /* Select appropriate section for constants depending
5416 on where we place literal pools. */
5420 rtx x,
5422 {
5427 }
5429 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
5430 void
5432 HOST_WIDE_INT offset)
5433 {
5434 /* When using per-function literal pools, we must ensure that any code
5435 section is aligned to the minimal instruction length, lest we get
5436 errors from the assembler re "unaligned instructions". */
5439 }
5441 /* Costs. */
5443 /* Helper function for rtx cost calculation. Strip a shift expression
5444 from X. Returns the inner operand if successful, or the original
5445 expression on failure. */
5446 static rtx
5448 {
5451 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
5452 we can convert both to ROR during final output. */
5467 }
5469 /* Helper function for rtx cost calculation. Strip an extend
5470 expression from X. Returns the inner operand if successful, or the
5471 original expression on failure. We deal with a number of possible
5472 canonicalization variations here. */
5473 static rtx
5475 {
5478 /* Zero and sign extraction of a widened value. */
5486 /* It can also be represented (for zero-extend) as an AND with an
5487 immediate. */
5496 /* Now handle extended register, as this may also have an optional
5497 left shift by 1..4. */
5511 }
5513 /* Return true iff CODE is a shift supported in combination
5514 with arithmetic instructions. */
5516 static bool
5518 {
5520 }
5522 /* Helper function for rtx cost calculation. Calculate the cost of
5523 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
5524 Return the calculated cost of the expression, recursing manually in to
5525 operands where needed. */
5527 static int
5529 {
5545 /* Integer multiply/fma. */
5547 {
5548 /* The multiply will be canonicalized as a shift, cost it as such. */
5552 {
5556 {
5558 {
5560 /* ARITH + shift-by-register. */
5563 /* ARITH + extended register. We don't have a cost field
5564 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
5566 else
5567 /* ARITH + shift-by-immediate. */
5569 }
5570 else
5571 /* LSL (immediate). */
5574 }
5575 /* Strip extends as we will have costed them in the case above. */
5582 }
5584 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
5585 compound and let the below cases handle it. After all, MNEG is a
5586 special-case alias of MSUB. */
5588 {
5591 }
5593 /* Integer multiplies or FMAs have zero/sign extending variants. */
5598 {
5603 {
5605 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
5607 else
5608 /* MUL/SMULL/UMULL. */
5610 }
5613 }
5615 /* This is either an integer multiply or a MADD. In both cases
5616 we want to recurse and cost the operands. */
5621 {
5623 /* MADD/MSUB. */
5625 else
5626 /* MUL. */
5628 }
5631 }
5632 else
5633 {
5635 {
5636 /* Floating-point FMA/FMUL can also support negations of the
5637 operands, unless the rounding mode is upward or downward in
5638 which case FNMUL is different than FMUL with operand negation. */
5642 {
5647 }
5650 /* FMADD/FNMADD/FNMSUB/FMSUB. */
5652 else
5653 /* FMUL/FNMUL. */
5655 }
5660 }
5661 }
5663 static int
5665 machine_mode mode,
5666 addr_space_t as ATTRIBUTE_UNUSED,
5668 {
5676 {
5678 {
5679 /* This is a CONST or SYMBOL ref which will be split
5680 in a different way depending on the code model in use.
5681 Cost it through the generic infrastructure. */
5683 /* Divide through by the cost of one instruction to
5684 bring it to the same units as the address costs. */
5686 /* The cost is then the cost of preparing the address,
5687 followed by an immediate (possibly 0) offset. */
5689 }
5690 else
5691 {
5692 /* This is most likely a jump table from a case
5693 statement. */
5695 }
5696 }
5699 {
5711 else
5730 }
5734 {
5735 /* For the sake of calculating the cost of the shifted register
5736 component, we can treat same sized modes in the same way. */
5738 {
5751 /* We can't tell, or this is a 128-bit vector. */
5755 }
5756 }
5759 }
5761 /* Return the cost of a branch. If SPEED_P is true then the compiler is
5762 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
5763 to be taken. */
5765 int
5767 {
5768 /* When optimizing for speed, use the cost of unpredictable branches. */
5774 else
5776 }
5778 /* Return true if the RTX X in mode MODE is a zero or sign extract
5779 usable in an ADD or SUB (extended register) instruction. */
5780 static bool
5782 {
5783 /* Catch add with a sign extract.
5784 This is add_<optab><mode>_multp2. */
5787 {
5798 op1))
5799 {
5801 }
5802 }
5803 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
5804 No shift. */
5810 }
5812 static bool
5814 {
5816 {
5828 }
5829 }
5831 /* Return true iff X is an rtx that will match an extr instruction
5832 i.e. as described in the *extr<mode>5_insn family of patterns.
5833 OP0 and OP1 will be set to the operands of the shifts involved
5834 on success and will be NULL_RTX otherwise. */
5836 static bool
5838 {
5853 {
5854 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
5866 {
5870 }
5871 }
5874 }
5876 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
5877 storing it in *COST. Result is true if the total cost of the operation
5878 has now been calculated. */
5879 static bool
5881 {
5882 rtx inner;
5883 rtx comparator;
5887 {
5891 }
5892 else
5893 {
5897 }
5900 {
5901 /* Conditional branch. */
5904 else
5905 {
5907 {
5909 {
5910 /* TBZ/TBNZ/CBZ/CBNZ. */
5912 /* TBZ/TBNZ. */
5915 else
5916 /* CBZ/CBNZ. */
5920 }
5921 }
5923 {
5924 /* TBZ/TBNZ. */
5927 }
5928 }
5929 }
5931 {
5932 /* CCMP. */
5934 {
5935 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
5939 {
5946 else
5948 }
5950 }
5952 /* It's a conditional operation based on the status flags,
5953 so it must be some flavor of CSEL. */
5955 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
5961 {
5962 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
5965 }
5970 }
5972 /* We don't know what this is, cost all operands. */
5974 }
5976 /* Check whether X is a bitfield operation of the form shift + extend that
5977 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
5978 operand to which the bitfield operation is applied. Otherwise return
5979 NULL_RTX. */
5981 static rtx
5983 {
5997 {
6015 }
6018 }
6020 /* Calculate the cost of calculating X, storing it in *COST. Result
6021 is true if the total cost of the operation has now been calculated. */
6022 static bool
6025 {
6031 /* By default, assume that everything has equivalent cost to the
6032 cheapest instruction. Any additional costs are applied as a delta
6033 above this default. */
6037 {
6039 /* The cost depends entirely on the operands to SET. */
6045 {
6048 {
6062 }
6071 /* Fall through. */
6073 /* The cost is one per vector-register copied. */
6075 {
6079 }
6080 /* const0_rtx is in general free, but we will use an
6081 instruction to set a register to 0. */
6083 {
6084 /* The cost is 1 per register copied. */
6088 }
6089 else
6090 /* Cost is just the cost of the RHS of the set. */
6096 /* Bit-field insertion. Strip any redundant widening of
6097 the RHS to meet the width of the target. */
6108 {
6109 /* MOV immediate is assumed to always be cheap. */
6111 }
6112 else
6113 {
6114 /* BFM. */
6118 }
6123 /* We can't make sense of this, assume default cost. */
6126 }
6130 /* If an instruction can incorporate a constant within the
6131 instruction, the instruction's expression avoids calling
6132 rtx_cost() on the constant. If rtx_cost() is called on a
6133 constant, then it is usually because the constant must be
6134 moved into a register by one or more instructions.
6136 The exception is constant 0, which can be expressed
6137 as XZR/WZR and is therefore free. The exception to this is
6138 if we have (set (reg) (const0_rtx)) in which case we must cost
6139 the move. However, we can catch that when we cost the SET, so
6140 we don't need to consider that here. */
6143 else
6144 {
6145 /* To an approximation, building any other constant is
6146 proportionally expensive to the number of instructions
6147 required to build that constant. This is true whether we
6148 are compiling for SPEED or otherwise. */
6151 }
6156 {
6157 /* mov[df,sf]_aarch64. */
6159 /* FMOV (scalar immediate). */
6162 {
6163 /* This will be a load from memory. */
6166 else
6168 }
6169 else
6170 /* Otherwise this is +0.0. We get this using MOVI d0, #0
6171 or MOV v0.s[0], wzr - neither of which are modeled by the
6172 cost tables. Just use the default cost. */
6173 {
6174 }
6175 }
6181 {
6182 /* For loads we want the base cost of a load, plus an
6183 approximation for the additional cost of the addressing
6184 mode. */
6198 }
6206 {
6208 {
6209 /* FNEG. */
6211 }
6213 }
6216 {
6219 {
6220 /* CSETM. */
6223 }
6225 /* Cost this as SUB wzr, X. */
6229 }
6232 {
6233 /* Support (neg(fma...)) as a single instruction only if
6234 sign of zeros is unimportant. This matches the decision
6235 making in aarch64.md. */
6237 {
6238 /* FNMADD. */
6241 }
6243 {
6244 /* FNMUL. */
6247 }
6249 /* FNEG. */
6252 }
6259 {
6262 else
6264 }
6274 {
6278 }
6281 {
6282 /* TODO: A write to the CC flags possibly costs extra, this
6283 needs encoding in the cost tables. */
6286 /* ANDS. */
6288 {
6291 }
6294 {
6295 /* ADDS (and CMN alias). */
6298 }
6301 {
6302 /* SUBS. */
6305 }
6310 {
6311 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
6312 Handle it here directly rather than going to cost_logic
6313 since we know the immediate generated for the TST is valid
6314 so we can avoid creating an intermediate rtx for it only
6315 for costing purposes. */
6322 }
6325 {
6326 /* CMN. */
6333 }
6335 /* CMP.
6337 Compare can freely swap the order of operands, and
6338 canonicalization puts the more complex operation first.
6339 But the integer MINUS logic expects the shift/extend
6340 operation in op1. */
6343 {
6346 }
6348 }
6351 {
6352 /* FCMP. */
6357 {
6359 /* FCMP supports constant 0.0 for no extra cost. */
6361 }
6363 }
6366 {
6367 /* Vector compare. */
6372 {
6373 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
6374 cost. */
6376 }
6378 }
6382 {
6386 cost_minus:
6389 /* Detect valid immediates. */
6395 {
6397 /* SUB(S) (immediate). */
6400 }
6402 /* Look for SUB (extended register). */
6404 {
6412 }
6416 /* Cost this as an FMA-alike operation. */
6420 {
6423 speed);
6425 }
6430 {
6432 {
6433 /* Vector SUB. */
6435 }
6437 {
6438 /* SUB(S). */
6440 }
6442 {
6443 /* FSUB. */
6445 }
6446 }
6448 }
6451 {
6452 rtx new_op0;
6457 cost_plus:
6460 {
6461 /* CSINC. */
6465 }
6470 {
6474 /* ADD (immediate). */
6477 }
6481 /* Look for ADD (extended register). */
6483 {
6491 }
6493 /* Strip any extend, leave shifts behind as we will
6494 cost them through mult_cost. */
6499 {
6501 speed);
6503 }
6508 {
6510 {
6511 /* Vector ADD. */
6513 }
6515 {
6516 /* ADD. */
6518 }
6520 {
6521 /* FADD. */
6523 }
6524 }
6526 }
6532 {
6535 else
6537 }
6542 {
6546 {
6549 else
6551 }
6553 }
6556 {
6563 }
6564 /* Fall through. */
6567 cost_logic:
6572 {
6576 }
6584 {
6585 /* This is a UBFM/SBFM. */
6590 }
6593 {
6594 /* We possibly get the immediate for free, this is not
6595 modelled. */
6598 {
6605 }
6606 else
6607 {
6610 /* Handle ORN, EON, or BIC. */
6616 /* If we had a shift on op0 then this is a logical-shift-
6617 by-register/immediate operation. Otherwise, this is just
6618 a logical operation. */
6620 {
6622 {
6623 /* Shift by immediate. */
6626 else
6628 }
6629 else
6631 }
6633 /* In both cases we want to cost both operands. */
6638 }
6639 }
6647 {
6648 /* Vector NOT. */
6651 }
6653 /* MVN-shifted-reg. */
6655 {
6662 }
6663 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
6664 Handle the second form here taking care that 'a' in the above can
6665 be a shift. */
6667 {
6676 {
6679 else
6681 }
6684 }
6685 /* MVN. */
6694 /* If a value is written in SI mode, then zero extended to DI
6695 mode, the operation will in general be free as a write to
6696 a 'w' register implicitly zeroes the upper bits of an 'x'
6697 register. However, if this is
6699 (set (reg) (zero_extend (reg)))
6701 we must cost the explicit register move. */
6705 {
6709 /* MOV. */
6711 else
6712 /* Free, the cost is that of the SI mode operation. */
6716 }
6718 {
6719 /* All loads can zero extend to any size for free. */
6722 }
6726 {
6731 }
6734 {
6736 {
6737 /* UMOV. */
6739 }
6740 else
6741 {
6742 /* UXTB/UXTH. */
6744 }
6745 }
6750 {
6751 /* LDRSH. */
6753 {
6760 }
6762 }
6766 {
6771 }
6774 {
6777 else
6779 }
6787 {
6789 {
6791 {
6792 /* Vector shift (immediate). */
6794 }
6795 else
6796 {
6797 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
6798 aliases. */
6800 }
6801 }
6803 /* We can incorporate zero/sign extend for free. */
6810 }
6811 else
6812 {
6814 {
6816 {
6817 /* Vector shift (register). */
6819 }
6820 else
6821 {
6822 /* LSLV. */
6824 }
6825 }
6827 }
6837 {
6838 /* ASR (immediate) and friends. */
6840 {
6843 else
6845 }
6849 }
6850 else
6851 {
6853 /* ASR (register) and friends. */
6855 {
6858 else
6860 }
6862 }
6868 {
6869 /* LDR. */
6872 }
6875 {
6876 /* ADRP, followed by ADD. */
6880 }
6883 {
6884 /* ADR. */
6887 }
6890 {
6891 /* One extra load instruction, after accessing the GOT. */
6895 }
6900 /* ADRP/ADD (immediate). */
6907 /* UBFX/SBFX. */
6909 {
6912 else
6914 }
6916 /* We can trust that the immediates used will be correct (there
6917 are no by-register forms), so we need only cost op0. */
6923 /* aarch64_rtx_mult_cost always handles recursion to its
6924 operands. */
6928 /* We can expand signed mod by power of 2 using a NEGS, two parallel
6929 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
6930 an unconditional negate. This case should only ever be reached through
6931 the set_smod_pow2_cheap check in expmed.c. */
6935 {
6936 /* We expand to 4 instructions. Reset the baseline. */
6944 }
6946 /* Fall-through. */
6949 {
6961 }
6968 {
6972 /* There is no integer SQRT, so only DIV and UDIV can get
6973 here. */
6975 else
6977 }
7003 {
7006 else
7008 }
7010 /* FMSUB, FNMADD, and FNMSUB are free. */
7017 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7018 and the by-element operand as operand 0. */
7022 /* Catch vector-by-element operations. The by-element operand can
7023 either be (vec_duplicate (vec_select (x))) or just
7024 (vec_select (x)), depending on whether we are multiplying by
7025 a vector or a scalar.
7027 Canonicalization is not very good in these cases, FMA4 will put the
7028 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7039 /* If the remaining parameters are not registers,
7040 get the cost to put them into registers. */
7054 {
7056 {
7057 /*Vector truncate. */
7059 }
7060 else
7062 }
7067 {
7069 {
7070 /*Vector conversion. */
7072 }
7073 else
7075 }
7081 /* Strip the rounding part. They will all be implemented
7082 by the fcvt* family of instructions anyway. */
7084 {
7093 }
7096 {
7099 else
7101 }
7103 /* We can combine fmul by a power of 2 followed by a fcvt into a single
7104 fixed-point fcvt. */
7109 {
7113 }
7120 {
7121 /* ABS (vector). */
7124 }
7126 {
7129 /* FABD, which is analogous to FADD. */
7131 {
7138 }
7139 /* Simple FABS is analogous to FNEG. */
7142 }
7143 else
7144 {
7145 /* Integer ABS will either be split to
7146 two arithmetic instructions, or will be an ABS
7147 (scalar), which we don't model. */
7151 }
7157 {
7160 else
7161 {
7162 /* FMAXNM/FMINNM/FMAX/FMIN.
7163 TODO: This may not be accurate for all implementations, but
7164 we do not model this in the cost tables. */
7166 }
7167 }
7171 /* The floating point round to integer frint* instructions. */
7173 {
7178 }
7181 {
7186 }
7191 /* Decompose <su>muldi3_highpart. */
7193 mode == DImode
7194 /* (lshiftrt:TI */
7197 /* (mult:TI */
7199 /* (ANY_EXTEND:TI (reg:DI))
7200 (ANY_EXTEND:TI (reg:DI))) */
7207 /* (const_int 64) */
7210 {
7211 /* UMULH/SMULH. */
7219 }
7221 /* Fall through. */
7224 }
7231 }
7233 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
7234 calculated for X. This cost is stored in *COST. Returns true
7235 if the total cost of X was calculated. */
7236 static bool
7239 {
7243 {
7248 }
7251 }
7253 static int
7256 {
7262 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
7269 /* Moving between GPR and stack cost is the same as GP2GP. */
7274 /* To/From the stack register, we move via the gprs. */
7280 {
7281 /* 128-bit operations on general registers require 2 instructions. */
7289 /* When AdvSIMD instructions are disabled it is not possible to move
7290 a 128-bit value directly between Q registers. This is handled in
7291 secondary reload. A general register is used as a scratch to move
7292 the upper DI value and the lower DI value is moved directly,
7293 hence the cost is the sum of three moves. */
7298 }
7308 }
7310 static int
7312 reg_class_t rclass ATTRIBUTE_UNUSED,
7314 {
7316 }
7318 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
7319 to optimize 1.0/sqrt. */
7321 static bool
7323 {
7325 && flag_unsafe_math_optimizations
7329 }
7331 /* Function to decide when to use the approximate reciprocal square root
7332 builtin. */
7334 static tree
7336 {
7340 }
7344 /* Select reciprocal square root initial estimate
7345 insn depending on machine mode. */
7347 rsqrte_type
7349 {
7351 {
7358 }
7359 }
7363 /* Select reciprocal square root Newton-Raphson step
7364 insn depending on machine mode. */
7366 rsqrts_type
7368 {
7370 {
7377 }
7378 }
7380 /* Emit instruction sequence to compute the reciprocal square root using the
7381 Newton-Raphson series. Iterate over the series twice for SF
7382 and thrice for DF. */
7384 void
7386 {
7402 /* Optionally iterate over the series one less time than otherwise. */
7404 iterations--;
7407 {
7417 }
7420 }
7422 /* Return the number of instructions that can be issued per cycle. */
7423 static int
7425 {
7427 }
7429 static int
7431 {
7435 }
7438 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
7439 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
7440 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
7442 static int
7445 {
7447 }
7450 /* Vectorizer cost model target hooks. */
7452 /* Implement targetm.vectorize.builtin_vectorization_cost. */
7453 static int
7455 tree vectype,
7457 {
7461 {
7510 }
7511 }
7513 /* Implement targetm.vectorize.add_stmt_cost. */
7514 static unsigned
7518 {
7523 {
7528 /* Statements in an inner loop relative to the loop being
7529 vectorized are weighted more heavily. The value here is
7530 arbitrary and could potentially be improved with analysis. */
7536 }
7539 }
7543 /* Parse the TO_PARSE string and put the architecture struct that it
7544 selects into RES and the architectural features into ISA_FLAGS.
7545 Return an aarch64_parse_opt_result describing the parse result.
7546 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
7548 static enum aarch64_parse_opt_result
7551 {
7563 else
7570 /* Loop through the list of supported ARCHes to find a match. */
7572 {
7574 {
7578 {
7579 /* TO_PARSE string contains at least one extension. */
7580 enum aarch64_parse_opt_result ext_res
7585 }
7586 /* Extension parsing was successful. Confirm the result
7587 arch and ISA flags. */
7591 }
7592 }
7594 /* ARCH name not found in list. */
7596 }
7598 /* Parse the TO_PARSE string and put the result tuning in RES and the
7599 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
7600 describing the parse result. If there is an error parsing, RES and
7601 ISA_FLAGS are left unchanged. */
7603 static enum aarch64_parse_opt_result
7606 {
7618 else
7625 /* Loop through the list of supported CPUs to find a match. */
7627 {
7629 {
7634 {
7635 /* TO_PARSE string contains at least one extension. */
7636 enum aarch64_parse_opt_result ext_res
7641 }
7642 /* Extension parsing was successfull. Confirm the result
7643 cpu and ISA flags. */
7647 }
7648 }
7650 /* CPU name not found in list. */
7652 }
7654 /* Parse the TO_PARSE string and put the cpu it selects into RES.
7655 Return an aarch64_parse_opt_result describing the parse result.
7656 If the parsing fails the RES does not change. */
7658 static enum aarch64_parse_opt_result
7660 {
7666 /* Loop through the list of supported CPUs to find a match. */
7668 {
7670 {
7673 }
7674 }
7676 /* CPU name not found in list. */
7678 }
7680 /* Parse TOKEN, which has length LENGTH to see if it is an option
7681 described in FLAG. If it is, return the index bit for that fusion type.
7682 If not, error (printing OPTION_NAME) and return zero. */
7684 static unsigned int
7689 {
7691 {
7695 }
7699 }
7701 /* Parse OPTION which is a comma-separated list of flags to enable.
7702 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
7703 default state we inherit from the CPU tuning structures. OPTION_NAME
7704 gives the top-level option we are parsing in the -moverride string,
7705 for use in error messages. */
7707 static unsigned int
7712 {
7719 {
7722 token_length,
7723 flags,
7724 option_name);
7725 /* If we find "none" (or, for simplicity's sake, an error) anywhere
7726 in the token stream, reset the supported operations. So:
7728 adrp+add.cmp+branch.none.adrp+add
7730 would have the result of turning on only adrp+add fusion. */
7736 }
7738 /* We ended with a comma, print something. */
7740 {
7743 }
7745 /* We still have one more token to parse. */
7748 token_length,
7749 flags,
7750 option_name);
7756 }
7758 /* Support for overriding instruction fusion. */
7760 static void
7763 {
7765 aarch64_fusible_pairs,
7768 }
7770 /* Support for overriding other tuning flags. */
7772 static void
7775 {
7776 tune->extra_tuning_flags
7778 aarch64_tuning_flags,
7781 }
7783 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
7784 we understand. If it is, extract the option string and handoff to
7785 the appropriate function. */
7787 void
7791 {
7797 {
7800 }
7802 /* Get the length of the option name. */
7804 /* Skip the '=' to get to the option string. */
7805 option_part++;
7808 {
7810 {
7813 }
7814 }
7818 }
7820 /* A checking mechanism for the implementation of the tls size. */
7822 static void
7824 {
7829 {
7831 /* Both the default and maximum TLS size allowed under tiny is 1M which
7832 needs two instructions to address, so we clamp the size to 24. */
7837 /* The maximum TLS size allowed under small is 4G. */
7842 /* The maximum TLS size allowed under large is 16E.
7843 FIXME: 16E should be 64bit, we only support 48bit offset now. */
7849 }
7852 }
7854 /* Parse STRING looking for options in the format:
7855 string :: option:string
7856 option :: name=substring
7857 name :: {a-z}
7858 substring :: defined by option. */
7860 static void
7863 {
7874 {
7876 /* Make this substring look like a string. */
7880 }
7882 /* One last option to parse. */
7885 }
7888 static void
7890 {
7891 /* The logic here is that if we are disabling all frame pointer generation
7892 then we do not need to disable leaf frame pointer generation as a
7893 separate operation. But if we are *only* disabling leaf frame pointer
7894 generation then we set flag_omit_frame_pointer to true, but in
7895 aarch64_frame_pointer_required we return false only for leaf functions.
7897 PR 70044: We have to be careful about being called multiple times for the
7898 same function. Once we have decided to set flag_omit_frame_pointer just
7899 so that we can omit leaf frame pointers, we must then not interpret a
7900 second call as meaning that all frame pointer generation should be
7901 omitted. We do this by setting flag_omit_frame_pointer to a special,
7902 non-zero value. */
7911 /* If not optimizing for size, set the default
7912 alignment to what the target wants. */
7914 {
7921 }
7923 /* If nopcrelative_literal_loads is set on the command line, this
7924 implies that the user asked for PC relative literal loads. */
7928 /* If it is not set on the command line, we default to no pc
7929 relative literal loads, unless the workaround for Cortex-A53
7930 erratum 843419 is in effect. */
7931 /* This is PR70113. When building the Linux kernel with
7932 CONFIG_ARM64_ERRATUM_843419, support for relocations
7933 R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
7934 removed from the kernel to avoid loading objects with possibly
7935 offending sequences. With nopcrelative_literal_loads, we would
7936 generate such relocations, preventing the kernel build from
7937 succeeding. */
7942 /* In the tiny memory model it makes no sense
7943 to disallow non PC relative literal pool loads
7944 as many other things will break anyway. */
7949 }
7951 /* 'Unpack' up the internal tuning structs and update the options
7952 in OPTS. The caller must have set up selected_tune and selected_arch
7953 as all the other target-specific codegen decisions are
7954 derived from them. */
7956 void
7958 {
7961 /* Make a copy of the tuning parameters attached to the core, which
7962 we may later overwrite. */
7970 /* This target defaults to strict volatile bitfields. */
7979 {
7991 }
7993 /* We don't mind passing in global_options_set here as we don't use
7994 the *options_set structs anyway. */
7996 queue_depth,
8000 /* Set the L1 cache line size. */
8008 }
8010 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
8011 specified in STR and throw errors if appropriate. Put the results if
8012 they are valid in RES and ISA_FLAGS. Return whether the option is
8013 valid. */
8015 static bool
8018 {
8019 enum aarch64_parse_opt_result parse_res
8026 {
8038 }
8041 }
8043 /* Validate a command-line -march option. Parse the arch and extensions
8044 (if any) specified in STR and throw errors if appropriate. Put the
8045 results, if they are valid, in RES and ISA_FLAGS. Return whether the
8046 option is valid. */
8048 static bool
8051 {
8052 enum aarch64_parse_opt_result parse_res
8059 {
8071 }
8074 }
8076 /* Validate a command-line -mtune option. Parse the cpu
8077 specified in STR and throw errors if appropriate. Put the
8078 result, if it is valid, in RES. Return whether the option is
8079 valid. */
8081 static bool
8083 {
8084 enum aarch64_parse_opt_result parse_res
8091 {
8100 }
8102 }
8104 /* Return the CPU corresponding to the enum CPU.
8105 If it doesn't specify a cpu, return the default. */
8109 {
8113 /* The & 0x3f is to extract the bottom 6 bits that encode the
8114 default cpu as selected by the --with-cpu GCC configure option
8115 in config.gcc.
8116 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
8117 flags mechanism should be reworked to make it more sane. */
8119 }
8121 /* Return the architecture corresponding to the enum ARCH.
8122 If it doesn't specify a valid architecture, return the default. */
8126 {
8133 }
8135 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
8136 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
8137 tuning structs. In particular it must set selected_tune and
8138 aarch64_isa_flags that define the available ISA features and tuning
8139 decisions. It must also set selected_arch as this will be used to
8140 output the .arch asm tags for each function. */
8142 static void
8144 {
8157 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
8158 If either of -march or -mtune is given, they override their
8159 respective component of -mcpu. */
8171 /* If the user did not specify a processor, choose the default
8172 one for them. This will be the CPU set during configuration using
8173 --with-cpu, otherwise it is "generic". */
8175 {
8177 {
8181 }
8182 else
8183 {
8184 /* Get default configure-time CPU. */
8187 }
8191 }
8192 /* If both -mcpu and -march are specified check that they are architecturally
8193 compatible, warn if they're not and prefer the -march ISA flags. */
8195 {
8197 {
8201 }
8206 }
8207 else
8208 {
8209 /* -mcpu but no -march. */
8216 }
8218 /* Set the arch as well as we will need it when outputing
8219 the .arch directive in assembly. */
8221 {
8224 }
8229 #ifndef HAVE_AS_MABI_OPTION
8230 /* The compiler may have been configured with 2.23.* binutils, which does
8231 not have support for ILP32. */
8234 #endif
8236 /* Make sure we properly set up the explicit options. */
8247 /* Save these options as the default ones in case we push and pop them later
8248 while processing functions with potential target attributes. */
8249 target_option_default_node = target_option_current_node
8254 }
8256 /* Implement targetm.override_options_after_change. */
8258 static void
8260 {
8262 }
8266 {
8270 }
8272 void
8274 {
8276 }
8278 /* A checking mechanism for the implementation of the various code models. */
8279 static void
8281 {
8283 {
8285 {
8290 #ifdef HAVE_AS_SMALL_PIC_RELOCS
8292 ? AARCH64_CMODEL_SMALL_PIC
8294 #else
8296 #endif
8304 }
8305 }
8306 else
8308 }
8310 /* Implement TARGET_OPTION_SAVE. */
8312 static void
8314 {
8316 }
8318 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
8319 using the information saved in PTR. */
8321 static void
8323 {
8331 }
8333 /* Implement TARGET_OPTION_PRINT. */
8335 static void
8337 {
8348 }
8352 void
8354 {
8356 }
8358 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
8359 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
8360 make sure optab availability predicates are recomputed when necessary. */
8362 void
8364 {
8369 else
8371 }
8373 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
8374 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
8375 of the function, if such exists. This function may be called multiple
8376 times on a single function so use aarch64_previous_fndecl to avoid
8377 setting up identical state. */
8379 static void
8381 {
8385 tree old_tree = (aarch64_previous_fndecl
8391 /* If current function has no attributes but the previous one did,
8392 use the default node. */
8396 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
8397 the default have been handled by aarch64_save_restore_target_globals from
8398 aarch64_pragma_target_parse. */
8404 /* First set the target options. */
8408 }
8410 /* Enum describing the various ways we can handle attributes.
8411 In many cases we can reuse the generic option handling machinery. */
8413 enum aarch64_attr_opt_type
8414 {
8418 aarch64_attr_custom /* Attribute requires a custom handling function. */
8419 };
8421 /* All the information needed to handle a target attribute.
8422 NAME is the name of the attribute.
8423 ATTR_TYPE specifies the type of behavior of the attribute as described
8424 in the definition of enum aarch64_attr_opt_type.
8425 ALLOW_NEG is true if the attribute supports a "no-" form.
8426 HANDLER is the function that takes the attribute string and whether
8427 it is a pragma or attribute and handles the option. It is needed only
8428 when the ATTR_TYPE is aarch64_attr_custom.
8429 OPT_NUM is the enum specifying the option that the attribute modifies.
8430 This is needed for attributes that mirror the behavior of a command-line
8431 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
8432 aarch64_attr_enum. */
8434 struct aarch64_attribute_info
8435 {
8441 };
8443 /* Handle the ARCH_STR argument to the arch= target attribute.
8444 PRAGMA_OR_ATTR is used in potential error messages. */
8446 static bool
8448 {
8450 enum aarch64_parse_opt_result parse_res
8454 {
8459 }
8462 {
8475 }
8478 }
8480 /* Handle the argument CPU_STR to the cpu= target attribute.
8481 PRAGMA_OR_ATTR is used in potential error messages. */
8483 static bool
8485 {
8487 enum aarch64_parse_opt_result parse_res
8491 {
8499 }
8502 {
8515 }
8518 }
8520 /* Handle the argument STR to the tune= target attribute.
8521 PRAGMA_OR_ATTR is used in potential error messages. */
8523 static bool
8525 {
8527 enum aarch64_parse_opt_result parse_res
8531 {
8536 }
8539 {
8545 }
8548 }
8550 /* Parse an architecture extensions target attribute string specified in STR.
8551 For example "+fp+nosimd". Show any errors if needed. Return TRUE
8552 if successful. Update aarch64_isa_flags to reflect the ISA features
8553 modified.
8554 PRAGMA_OR_ATTR is used in potential error messages. */
8556 static bool
8558 {
8562 /* We allow "+nothing" in the beginning to clear out all architectural
8563 features if the user wants to handpick specific features. */
8565 {
8568 }
8573 {
8576 }
8579 {
8592 }
8595 }
8597 /* The target attributes that we support. On top of these we also support just
8598 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
8599 handled explicitly in aarch64_process_one_target_attr. */
8602 {
8604 OPT_mgeneral_regs_only },
8606 OPT_mfix_cortex_a53_835769 },
8608 OPT_mfix_cortex_a53_843419 },
8612 OPT_momit_leaf_frame_pointer },
8615 OPT_march_ },
8618 OPT_mtune_ },
8620 };
8622 /* Parse ARG_STR which contains the definition of one target attribute.
8623 Show appropriate errors if any or return true if the attribute is valid.
8624 PRAGMA_OR_ATTR holds the string to use in error messages about whether
8625 we're processing a target attribute or pragma. */
8627 static bool
8629 {
8635 {
8638 }
8643 /* Skip leading whitespace. */
8645 str_to_check++;
8647 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
8648 It is easier to detect and handle it explicitly here rather than going
8649 through the machinery for the rest of the target attributes in this
8650 function. */
8655 {
8658 }
8661 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
8662 and point ARG to "foo". */
8664 {
8666 arg++;
8667 }
8671 {
8672 /* If the names don't match up, or the user has given an argument
8673 to an attribute that doesn't accept one, or didn't give an argument
8674 to an attribute that expects one, fail to match. */
8683 {
8687 }
8689 /* If the name matches but the attribute does not allow "no-" versions
8690 then we can't match. */
8692 {
8696 }
8699 {
8700 /* Has a custom handler registered.
8701 For example, cpu=, arch=, tune=. */
8708 /* Either set or unset a boolean option. */
8710 {
8718 }
8719 /* Set or unset a bit in the target_flags. aarch64_handle_option
8720 should know what mask to apply given the option number. */
8722 {
8724 /* We only need to specify the option number.
8725 aarch64_handle_option will know which mask to apply. */
8731 }
8732 /* Use the option setting machinery to set an option to an enum. */
8734 {
8741 {
8744 global_dc);
8745 }
8746 else
8747 {
8750 }
8752 }
8755 }
8756 }
8758 /* If we reached here we either have found an attribute and validated
8759 it or didn't match any. If we matched an attribute but its arguments
8760 were malformed we will have returned false already. */
8762 }
8764 /* Count how many times the character C appears in
8765 NULL-terminated string STR. */
8767 static unsigned int
8769 {
8772 {
8774 res++;
8776 str++;
8777 }
8780 }
8782 /* Parse the tree in ARGS that contains the target attribute information
8783 and update the global target options space. PRAGMA_OR_ATTR is a string
8784 to be used in error messages, specifying whether this is processing
8785 a target attribute or a target pragma. */
8787 bool
8789 {
8791 {
8792 do
8793 {
8796 {
8799 }
8804 }
8805 /* We expect to find a string to parse. */
8813 {
8816 }
8818 /* Used to catch empty spaces between commas i.e.
8819 attribute ((target ("attr1,,attr2"))). */
8822 /* Handle multiple target attributes separated by ','. */
8827 {
8828 num_attrs++;
8830 {
8833 }
8836 }
8839 {
8843 }
8846 }
8848 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
8849 process attribute ((target ("..."))). */
8851 static bool
8853 {
8856 tree old_optimize;
8860 /* If what we're processing is the current pragma string then the
8861 target option node is already stored in target_option_current_node
8862 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
8863 having to re-parse the string. This is especially useful to keep
8864 arm_neon.h compile times down since that header contains a lot
8865 of intrinsics enclosed in pragmas. */
8867 {
8870 }
8876 /* If the function changed the optimization levels as well as setting
8877 target options, start with the optimizations specified. */
8882 /* Save the current target options to restore at the end. */
8885 /* If fndecl already has some target attributes applied to it, unpack
8886 them so that we add this attribute on top of them, rather than
8887 overwriting them. */
8889 {
8895 }
8896 else
8903 /* Set up any additional state. */
8905 {
8907 /* Initialize SIMD builtins if we haven't already.
8908 Set current_target_pragma to NULL for the duration so that
8909 the builtin initialization code doesn't try to tag the functions
8910 being built with the attributes specified by any current pragma, thus
8911 going into an infinite recursion. */
8913 {
8918 }
8920 }
8921 else
8927 {
8932 }
8940 }
8942 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
8943 tri-bool options (yes, no, don't care) and the default value is
8944 DEF, determine whether to reject inlining. */
8946 static bool
8949 {
8950 /* If the callee doesn't care, always allow inlining. */
8954 /* If the caller doesn't care, always allow inlining. */
8958 /* Otherwise, allow inlining if either the callee and caller values
8959 agree, or if the callee is using the default value. */
8961 }
8963 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
8964 to inline CALLEE into CALLER based on target-specific info.
8965 Make sure that the caller and callee have compatible architectural
8966 features. Then go through the other possible target attributes
8967 and see if they can block inlining. Try not to reject always_inline
8968 callees unless they are incompatible architecturally. */
8970 static bool
8972 {
8976 /* If callee has no option attributes, then it is ok to inline. */
8987 /* Callee's ISA flags should be a subset of the caller's. */
8992 /* Allow non-strict aligned functions inlining into strict
8993 aligned ones. */
9003 /* If the architectural features match up and the callee is always_inline
9004 then the other attributes don't matter. */
9016 /* Honour explicit requests to workaround errata. */
9029 /* If the user explicitly specified -momit-leaf-frame-pointer for the
9030 caller and calle and they don't match up, reject inlining. */
9037 /* If the callee has specific tuning overrides, respect them. */
9042 /* If the user specified tuning override strings for the
9043 caller and callee and they don't match up, reject inlining.
9044 We just do a string compare here, we don't analyze the meaning
9045 of the string, as it would be too costly for little gain. */
9053 }
9055 /* Return true if SYMBOL_REF X binds locally. */
9057 static bool
9059 {
9063 }
9065 /* Return true if SYMBOL_REF X is thread local */
9066 static bool
9068 {
9076 }
9078 /* Classify a TLS symbol into one of the TLS kinds. */
9079 enum aarch64_symbol_type
9081 {
9085 {
9092 {
9098 }
9109 else
9118 }
9119 }
9121 /* Return the method that should be used to access SYMBOL_REF or
9122 LABEL_REF X. */
9124 enum aarch64_symbol_type
9126 {
9128 {
9130 {
9145 }
9146 }
9149 {
9151 {
9152 /* This is alright even in PIC code as the constant
9153 pool reference is always PC relative and within
9154 the same translation unit. */
9158 else
9160 }
9166 {
9168 /* When we retreive symbol + offset address, we have to make sure
9169 the offset does not cause overflow of the final address. But
9170 we have no way of knowing the address of symbol at compile time
9171 so we can't accurately say if the distance between the PC and
9172 symbol + offset is outside the addressible range of +/-1M in the
9173 TINY code model. So we rely on images not being greater than
9174 1M and cap the offset at 1M and anything beyond 1M will have to
9175 be loaded using an alternative mechanism. */
9182 /* Same reasoning as the tiny code model, but the offset cap here is
9183 4G. */
9204 }
9205 }
9207 /* By default push everything into the constant pool. */
9209 }
9211 bool
9213 {
9215 }
9217 bool
9219 {
9227 }
9229 /* Return true if X holds either a quarter-precision or
9230 floating-point +0.0 constant. */
9231 static bool
9233 {
9240 /* We only handle moving 0.0 to a TFmode register. */
9245 }
9247 static bool
9249 {
9250 /* Do not allow vector struct mode constants. We could support
9251 0 and -1 easily, but they need support in aarch64-simd.md. */
9255 /* This could probably go away because
9256 we now decompose CONST_INTs according to expand_mov_immediate. */
9267 }
9269 rtx
9271 {
9277 /* Can return in any reg. */
9280 }
9282 /* On AAPCS systems, this is the "struct __va_list". */
9285 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
9286 Return the type to use as __builtin_va_list.
9288 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
9290 struct __va_list
9291 {
9292 void *__stack;
9293 void *__gr_top;
9294 void *__vr_top;
9295 int __gr_offs;
9296 int __vr_offs;
9297 }; */
9299 static tree
9301 {
9302 tree va_list_name;
9305 /* Create the type. */
9307 /* Give it the required name. */
9309 TYPE_DECL,
9311 va_list_type);
9316 /* Create the fields. */
9319 ptr_type_node);
9322 ptr_type_node);
9325 ptr_type_node);
9328 integer_type_node);
9331 integer_type_node);
9333 /* Tell tree-stdarg pass about our internal offset fields.
9334 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
9335 purpose to identify whether the code is updating va_list internal
9336 offset fields through irregular way. */
9358 /* Compute its layout. */
9362 }
9364 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
9365 static void
9367 {
9371 tree t;
9385 {
9388 }
9397 NULL_TREE);
9399 NULL_TREE);
9401 NULL_TREE);
9403 NULL_TREE);
9405 NULL_TREE);
9407 /* Emit code to initialize STACK, which points to the next varargs stack
9408 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
9409 by named arguments. STACK is 8-byte aligned. */
9416 /* Emit code to initialize GRTOP, the top of the GR save area.
9417 virtual_incoming_args_rtx should have been 16 byte aligned. */
9422 /* Emit code to initialize VRTOP, the top of the VR save area.
9423 This address is gr_save_area_bytes below GRTOP, rounded
9424 down to the next 16-byte boundary. */
9434 /* Emit code to initialize GROFF, the offset from GRTOP of the
9435 next GPR argument. */
9440 /* Likewise emit code to initialize VROFF, the offset from FTOP
9441 of the next VR argument. */
9445 }
9447 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
9449 static tree
9452 {
9453 tree addr;
9459 machine_mode mode;
9486 type,
9490 {
9491 /* TYPE passed in fp/simd registers. */
9503 {
9506 }
9509 {
9511 }
9512 }
9513 else
9514 {
9515 /* TYPE passed in general registers. */
9528 {
9530 }
9531 }
9533 /* Get a local temporary for the field value. */
9536 /* Emit code to branch if off >= 0. */
9542 {
9543 /* Emit: offs = (offs + 15) & -16. */
9549 }
9550 else
9553 /* Update ap.__[g|v]r_offs */
9558 /* String up. */
9562 /* [cond2] if (ap.__[g|v]r_offs > 0) */
9567 /* String up: make sure the assignment happens before the use. */
9571 /* Prepare the trees handling the argument that is passed on the stack;
9572 the top level node will store in ON_STACK. */
9575 {
9576 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
9584 }
9585 else
9587 /* Advance ap.__stack */
9595 /* String up roundup and advance. */
9598 /* String up with arg */
9600 /* Big-endianness related address adjustment. */
9603 {
9607 }
9612 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
9622 {
9623 /* type ha; // treat as "struct {ftype field[n];}"
9624 ... [computing offs]
9625 for (i = 0; i <nregs; ++i, offs += 16)
9626 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
9627 return ha; */
9631 /* Declare a local variable. */
9635 /* Establish the base type. */
9637 {
9650 /* The half precision and quad precision are not fully supported yet. Enable
9651 the following code after the support is complete. Need to find the correct
9652 type node for __fp16 *. */
9653 #if 0
9658 #endif
9661 {
9665 }
9669 }
9671 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
9679 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
9681 {
9691 }
9695 }
9705 }
9707 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
9709 static void
9713 {
9715 CUMULATIVE_ARGS local_cum;
9719 /* The caller has advanced CUM up to, but not beyond, the last named
9720 argument. Advance a local copy of CUM past the last "real" named
9721 argument, to find out how many registers are left over. */
9725 /* Found out how many registers we need to save.
9726 Honor tree-stdvar analysis results. */
9735 {
9738 }
9741 {
9743 {
9746 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
9754 }
9756 {
9757 /* We can't use move_block_from_reg, because it will use
9758 the wrong mode, storing D regs only. */
9762 /* Set OFF to the offset from virtual_incoming_args_rtx of
9763 the first vector register. The VR save area lies below
9764 the GR one, and is aligned to 16 bytes. */
9771 {
9779 }
9780 }
9781 }
9783 /* We don't save the size into *PRETEND_SIZE because we want to avoid
9784 any complication of having crtl->args.pretend_args_size changed. */
9789 }
9791 static void
9793 {
9796 {
9798 {
9801 }
9802 }
9803 }
9805 /* Walk down the type tree of TYPE counting consecutive base elements.
9806 If *MODEP is VOIDmode, then set it to the first valid floating point
9807 type. If a non-floating point type is found, or if a floating point
9808 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
9809 otherwise return the count in the sub-tree. */
9810 static int
9812 {
9813 machine_mode mode;
9814 HOST_WIDE_INT size;
9817 {
9845 /* Use V2SImode and V4SImode as representatives of all 64-bit
9846 and 128-bit vector types. */
9849 {
9858 }
9863 /* Vector modes are considered to be opaque: two vectors are
9864 equivalent for the purposes of being homogeneous aggregates
9865 if they are the same size. */
9872 {
9876 /* Can't handle incomplete types nor sizes that are not
9877 fixed. */
9884 || !index
9895 /* There must be no padding. */
9900 }
9903 {
9906 tree field;
9908 /* Can't handle incomplete types nor sizes that are not
9909 fixed. */
9915 {
9923 }
9925 /* There must be no padding. */
9930 }
9934 {
9935 /* These aren't very interesting except in a degenerate case. */
9938 tree field;
9940 /* Can't handle incomplete types nor sizes that are not
9941 fixed. */
9947 {
9955 }
9957 /* There must be no padding. */
9962 }
9966 }
9969 }
9971 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
9972 type as described in AAPCS64 \S 4.1.2.
9974 See the comment above aarch64_composite_type_p for the notes on MODE. */
9976 static bool
9978 machine_mode mode)
9979 {
9989 }
9991 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
9992 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
9993 array types. The C99 floating-point complex types are also considered
9994 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
9995 types, which are GCC extensions and out of the scope of AAPCS64, are
9996 treated as composite types here as well.
9998 Note that MODE itself is not sufficient in determining whether a type
9999 is such a composite type or not. This is because
10000 stor-layout.c:compute_record_mode may have already changed the MODE
10001 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
10002 structure with only one field may have its MODE set to the mode of the
10003 field. Also an integer mode whose size matches the size of the
10004 RECORD_TYPE type may be used to substitute the original mode
10005 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
10006 solely relied on. */
10008 static bool
10010 machine_mode mode)
10011 {
10024 }
10026 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
10027 shall be passed or returned in simd/fp register(s) (providing these
10028 parameter passing registers are available).
10030 Upon successful return, *COUNT returns the number of needed registers,
10031 *BASE_MODE returns the mode of the individual register and when IS_HAF
10032 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
10033 floating-point aggregate or a homogeneous short-vector aggregate. */
10035 static bool
10037 const_tree type,
10041 {
10049 {
10052 }
10054 {
10058 }
10060 {
10064 {
10067 }
10068 else
10070 }
10071 else
10076 }
10078 /* Implement TARGET_STRUCT_VALUE_RTX. */
10080 static rtx
10083 {
10085 }
10087 /* Implements target hook vector_mode_supported_p. */
10088 static bool
10090 {
10102 }
10104 /* Return appropriate SIMD container
10105 for MODE within a vector of WIDTH bits. */
10106 static machine_mode
10108 {
10111 {
10114 {
10129 }
10130 else
10132 {
10143 }
10144 }
10146 }
10148 /* Return 128-bit container as the preferred SIMD mode for MODE. */
10149 static machine_mode
10151 {
10153 }
10155 /* Return the bitmask of possible vector sizes for the vectorizer
10156 to iterate over. */
10157 static unsigned int
10159 {
10161 }
10163 /* Implement TARGET_MANGLE_TYPE. */
10167 {
10168 /* The AArch64 ABI documents say that "__va_list" has to be
10169 managled as if it is in the "std" namespace. */
10173 /* Half-precision float. */
10177 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
10178 builtin types. */
10182 /* Use the default mangling. */
10184 }
10187 /* Return true if the rtx_insn contains a MEM RTX somewhere
10188 in it. */
10190 static bool
10192 {
10199 }
10201 /* Find the first rtx_insn before insn that will generate an assembly
10202 instruction. */
10206 {
10210 do
10211 {
10213 }
10217 }
10219 static bool
10221 {
10223 /* A number of these may be AArch32 only. */
10228 };
10231 {
10234 }
10237 }
10239 /* Check if there is a register dependency between a load and the insn
10240 for which we hold recog_data. */
10242 static bool
10244 {
10245 rtx load_reg;
10255 {
10261 }
10263 }
10266 /* When working around the Cortex-A53 erratum 835769,
10267 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
10268 instruction and has a preceding memory instruction such that a NOP
10269 should be inserted between them. */
10271 bool
10273 {
10276 rtx body;
10289 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
10290 Restore recog state to INSN to avoid state corruption. */
10298 /* If the previous insn is a memory op and there is no dependency between
10299 it and the DImode madd, emit a NOP between them. If body is NULL then we
10300 have a complex memory operation, probably a load/store pair.
10301 Be conservative for now and emit a NOP. */
10308 }
10311 /* Implement FINAL_PRESCAN_INSN. */
10313 void
10315 {
10318 }
10321 /* Return the equivalent letter for size. */
10322 static char
10324 {
10326 {
10332 }
10333 }
10335 /* Return true iff x is a uniform vector of floating-point
10336 constants, and the constant can be represented in
10337 quarter-precision form. Note, as aarch64_float_const_representable
10338 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
10339 static bool
10341 {
10342 rtx elt;
10346 }
10348 /* Return true for valid and false for invalid. */
10349 bool
10352 {
10353 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
10354 matches = 1; \
10355 for (i = 0; i < idx; i += (STRIDE)) \
10356 if (!(TEST)) \
10357 matches = 0; \
10358 if (matches) \
10359 { \
10360 immtype = (CLASS); \
10361 elsize = (ELSIZE); \
10362 eshift = (SHIFT); \
10363 emvn = (NEG); \
10364 break; \
10365 }
10375 {
10381 {
10386 }
10389 }
10391 /* Splat vector constant out into a byte vector. */
10393 {
10394 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
10395 it must be laid out in the vector register in reverse order. */
10403 {
10406 }
10408 }
10410 /* Sanity check. */
10413 do
10414 {
10463 }
10470 {
10480 /* Un-invert bytes of recognized vector, if necessary. */
10486 {
10487 /* FIXME: Broken on 32-bit H_W_I hosts. */
10496 }
10497 else
10498 {
10502 /* Construct 'abcdefgh' because the assembler cannot handle
10503 generic constants. */
10508 }
10509 }
10512 #undef CHECK
10513 }
10515 /* Check of immediate shift constants are within range. */
10516 bool
10518 {
10522 else
10524 }
10526 /* Return true if X is a uniform vector where all elements
10527 are either the floating-point constant 0.0 or the
10528 integer constant 0. */
10529 bool
10531 {
10533 }
10536 /* Return the bitmask CONST_INT to select the bits required by a zero extract
10537 operation of width WIDTH at bit position POS. */
10539 rtx
10541 {
10545 unsigned HOST_WIDE_INT mask
10548 }
10550 bool
10552 {
10557 {
10562 }
10565 }
10567 bool
10569 {
10582 }
10584 /* Return a const_int vector of VAL. */
10585 rtx
10587 {
10596 }
10598 /* Check OP is a legal scalar immediate for the MOVI instruction. */
10600 bool
10602 {
10603 machine_mode vmode;
10609 }
10611 /* Construct and return a PARALLEL RTX vector with elements numbering the
10612 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
10613 the vector - from the perspective of the architecture. This does not
10614 line up with GCC's perspective on lane numbers, so we end up with
10615 different masks depending on our target endian-ness. The diagram
10616 below may help. We must draw the distinction when building masks
10617 which select one half of the vector. An instruction selecting
10618 architectural low-lanes for a big-endian target, must be described using
10619 a mask selecting GCC high-lanes.
10621 Big-Endian Little-Endian
10623 GCC 0 1 2 3 3 2 1 0
10624 | x | x | x | x | | x | x | x | x |
10625 Architecture 3 2 1 0 3 2 1 0
10627 Low Mask: { 2, 3 } { 0, 1 }
10628 High Mask: { 0, 1 } { 2, 3 }
10629 */
10631 rtx
10633 {
10639 rtx t1;
10644 else
10652 }
10654 /* Check OP for validity as a PARALLEL RTX vector with elements
10655 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
10656 from the perspective of the architecture. See the diagram above
10657 aarch64_simd_vect_par_cnst_half for more details. */
10659 bool
10662 {
10675 {
10682 }
10684 }
10686 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
10687 HIGH (exclusive). */
10688 void
10690 const_tree exp)
10691 {
10692 HOST_WIDE_INT lane;
10697 {
10700 else
10702 }
10703 }
10705 /* Return TRUE if OP is a valid vector addressing mode. */
10706 bool
10708 {
10711 }
10713 /* Emit a register copy from operand to operand, taking care not to
10714 early-clobber source registers in the process.
10716 COUNT is the number of components into which the copy needs to be
10717 decomposed. */
10718 void
10721 {
10731 else
10735 }
10737 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
10738 one of VSTRUCT modes: OI, CI, or XI. */
10739 int
10741 {
10743 }
10745 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
10746 alignment of a vector to 128 bits. */
10747 static HOST_WIDE_INT
10749 {
10752 }
10754 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
10755 static bool
10757 {
10761 /* We guarantee alignment for vectors up to 128-bits. */
10766 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
10768 }
10770 /* If VALS is a vector constant that can be loaded into a register
10771 using DUP, generate instructions to do so and return an RTX to
10772 assign to the register. Otherwise return NULL_RTX. */
10773 static rtx
10775 {
10778 rtx x;
10783 /* We can load this constant by using DUP and a constant in a
10784 single ARM register. This will be cheaper than a vector
10785 load. */
10788 }
10791 /* Generate code to load VALS, which is a PARALLEL containing only
10792 constants (for vec_init) or CONST_VECTOR, efficiently into a
10793 register. Returns an RTX to copy into the register, or NULL_RTX
10794 for a PARALLEL that can not be converted into a CONST_VECTOR. */
10795 static rtx
10797 {
10799 rtx const_dup;
10808 {
10809 /* A CONST_VECTOR must contain only CONST_INTs and
10810 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
10811 Only store valid constants in a CONST_VECTOR. */
10813 {
10816 n_const++;
10817 }
10820 }
10821 else
10826 /* Load using MOVI/MVNI. */
10829 /* Loaded using DUP. */
10832 /* Load from constant pool. We can not take advantage of single-cycle
10833 LD1 because we need a PC-relative addressing mode. */
10835 else
10836 /* A PARALLEL containing something not valid inside CONST_VECTOR.
10837 We can not construct an initializer. */
10839 }
10841 /* Expand a vector initialisation sequence, such that TARGET is
10842 initialised to contain VALS. */
10844 void
10846 {
10849 /* The number of vector elements. */
10851 /* The number of vector elements which are not constant. */
10854 /* The first element of vals. */
10858 /* Count the number of variable elements to initialise. */
10860 {
10864 else
10868 }
10870 /* No variable elements, hand off to aarch64_simd_make_constant which knows
10871 how best to handle this. */
10873 {
10876 {
10879 }
10880 }
10882 /* Splat a single non-constant element if we can. */
10884 {
10888 }
10890 /* Initialise a vector which is part-variable. We want to first try
10891 to build those lanes which are constant in the most efficient way we
10892 can. */
10894 {
10897 /* Load constant part of vector. We really don't care what goes into the
10898 parts we will overwrite, but we're more likely to be able to load the
10899 constant efficiently if it has fewer, larger, repeating parts
10900 (see aarch64_simd_valid_immediate). */
10902 {
10908 {
10909 /* Look in the copied vector, as more elements are const. */
10912 {
10915 }
10916 }
10918 }
10920 }
10922 /* Insert the variable lanes directly. */
10928 {
10934 }
10935 }
10937 static unsigned HOST_WIDE_INT
10939 {
10940 return
10941 (!SHIFT_COUNT_TRUNCATED
10944 }
10946 /* Select a format to encode pointers in exception handling data. */
10947 int
10949 {
10952 {
10958 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
10959 for everything. */
10963 /* No assumptions here. 8-byte relocs required. */
10966 }
10968 }
10970 /* The last .arch and .tune assembly strings that we printed. */
10974 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
10975 by the function fndecl. */
10977 void
10979 tree fndecl)
10980 {
10986 else
10997 /* Only update the assembler .arch string if it is distinct from the last
10998 such string we printed. */
11001 {
11004 }
11006 /* Print the cpu name we're tuning for in the comments, might be
11007 useful to readers of the generated asm. Do it only when it changes
11008 from function to function and verbose assembly is requested. */
11013 {
11017 }
11019 /* Don't forget the type directive for ELF. */
11022 }
11024 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
11026 static void
11028 {
11045 }
11047 /* Emit load exclusive. */
11049 static void
11052 {
11056 {
11063 }
11066 }
11068 /* Emit store exclusive. */
11070 static void
11073 {
11077 {
11084 }
11087 }
11089 /* Mark the previous jump instruction as unlikely. */
11091 static void
11093 {
11098 }
11100 /* Expand a compare and swap pattern. */
11102 void
11104 {
11109 gen_cas_fn gen;
11111 {
11112 gen_aarch64_compare_and_swapqi,
11113 gen_aarch64_compare_and_swaphi,
11114 gen_aarch64_compare_and_swapsi,
11115 gen_aarch64_compare_and_swapdi
11116 };
11118 {
11119 gen_aarch64_compare_and_swapqi_lse,
11120 gen_aarch64_compare_and_swaphi_lse,
11121 gen_aarch64_compare_and_swapsi_lse,
11122 gen_aarch64_compare_and_swapdi_lse
11123 };
11136 /* Normally the succ memory model must be stronger than fail, but in the
11137 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
11138 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
11145 {
11148 /* For short modes, we're going to perform the comparison in SImode,
11149 so do the zero-extension now. */
11153 /* Fall through. */
11157 /* Force the value into a register if needed. */
11164 }
11167 {
11174 }
11177 else
11188 }
11190 /* Test whether the target supports using a atomic load-operate instruction.
11191 CODE is the operation and AFTER is TRUE if the data in memory after the
11192 operation should be returned and FALSE if the data before the operation
11193 should be returned. Returns FALSE if the operation isn't supported by the
11194 architecture. */
11196 bool
11198 {
11203 {
11213 }
11214 }
11216 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
11217 sequence implementing an atomic operation. */
11219 static void
11221 {
11228 {
11230 }
11231 }
11233 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
11234 for the data in memory. EXPECTED is the value expected to be in memory.
11235 DESIRED is the value to store to memory. MEM is the memory location. MODEL
11236 is the memory ordering to use. */
11238 void
11241 rtx model)
11242 {
11244 machine_mode mode;
11249 {
11256 }
11258 /* Move the expected value into the CAS destination register. */
11261 /* Emit the CAS. */
11264 /* Compare the expected value with the value loaded by the CAS, to establish
11265 whether the swap was made. */
11267 }
11269 /* Split a compare and swap pattern. */
11271 void
11273 {
11275 machine_mode mode;
11280 rtx model_rtx;
11294 {
11297 }
11300 /* The initial load can be relaxed for a __sync operation since a final
11301 barrier will be emitted to stop code hoisting. */
11305 else
11317 {
11322 }
11323 else
11324 {
11328 }
11332 /* Emit any final barrier needed for a __sync operation. */
11335 }
11337 /* Emit a BIC instruction. */
11339 static void
11341 {
11346 {
11351 }
11354 }
11356 /* Emit an atomic swap. */
11358 static void
11361 {
11365 {
11372 }
11375 }
11377 /* Operations supported by aarch64_emit_atomic_load_op. */
11379 enum aarch64_atomic_load_op_code
11380 {
11384 AARCH64_LDOP_BIC /* A & ~B */
11385 };
11387 /* Emit an atomic load-operate. */
11389 static void
11393 {
11396 {
11397 gen_aarch64_atomic_loadaddqi,
11398 gen_aarch64_atomic_loadaddhi,
11399 gen_aarch64_atomic_loadaddsi,
11400 gen_aarch64_atomic_loadadddi
11401 };
11403 {
11404 gen_aarch64_atomic_loadeorqi,
11405 gen_aarch64_atomic_loadeorhi,
11406 gen_aarch64_atomic_loadeorsi,
11407 gen_aarch64_atomic_loadeordi
11408 };
11410 {
11411 gen_aarch64_atomic_loadsetqi,
11412 gen_aarch64_atomic_loadsethi,
11413 gen_aarch64_atomic_loadsetsi,
11414 gen_aarch64_atomic_loadsetdi
11415 };
11417 {
11418 gen_aarch64_atomic_loadclrqi,
11419 gen_aarch64_atomic_loadclrhi,
11420 gen_aarch64_atomic_loadclrsi,
11421 gen_aarch64_atomic_loadclrdi
11422 };
11423 aarch64_atomic_load_op_fn gen;
11427 {
11434 }
11437 {
11444 }
11447 }
11449 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
11450 location to store the data read from memory. OUT_RESULT is the location to
11451 store the result of the operation. MEM is the memory location to read and
11452 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
11453 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
11454 be NULL. */
11456 void
11459 {
11463 aarch64_atomic_load_op_code ldop_code;
11464 rtx src;
11465 rtx x;
11473 /* Make sure the value is in a register, putting it into a destination
11474 register if it needs to be manipulated. */
11477 {
11480 }
11481 else
11485 /* Preprocess the data for the operation as necessary. If the operation is
11486 a SET then emit a swap instruction and finish. */
11488 {
11494 /* Negate the value and treat it as a PLUS. */
11495 {
11496 rtx neg_src;
11498 /* Resize the value if necessary. */
11507 }
11508 /* Fall-through. */
11522 {
11523 rtx not_src;
11525 /* Resize the value if necessary. */
11534 }
11539 /* The operation can't be done with atomic instructions. */
11541 }
11545 /* If necessary, calculate the data in memory after the update by redoing the
11546 operation from values in registers. */
11551 {
11555 }
11560 {
11576 }
11581 }
11583 /* Split an atomic operation. */
11585 void
11588 {
11594 rtx x;
11596 /* Split the atomic operation into a sequence. */
11604 else
11608 /* The initial load can be relaxed for a __sync operation since a final
11609 barrier will be emitted to stop code hoisting. */
11613 else
11617 {
11631 {
11634 }
11635 /* Fall through. */
11641 }
11651 /* Emit any final barrier needed for a __sync operation. */
11654 }
11656 static void
11658 {
11659 /* Half-precision float operations. The compiler handles all operations
11660 with NULL libfuncs by converting to SFmode. */
11662 /* Conversions. */
11666 /* Arithmetic. */
11673 /* Comparisons. */
11681 }
11683 /* Target hook for c_mode_for_suffix. */
11684 static machine_mode
11686 {
11691 }
11693 /* We can only represent floating point constants which will fit in
11694 "quarter-precision" values. These values are characterised by
11695 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
11696 by:
11698 (-1)^s * (n/16) * 2^r
11700 Where:
11701 's' is the sign bit.
11702 'n' is an integer in the range 16 <= n <= 31.
11703 'r' is an integer in the range -3 <= r <= 4. */
11705 /* Return true iff X can be represented by a quarter-precision
11706 floating point immediate operand X. Note, we cannot represent 0.0. */
11707 bool
11709 {
11710 /* This represents our current view of how many bits
11711 make up the mantissa. */
11721 /* We don't support HFmode constants yet. */
11727 /* We cannot represent infinities, NaNs or +/-zero. We won't
11728 know if we have +zero until we analyse the mantissa, but we
11729 can reject the other invalid values. */
11734 /* Extract exponent. */
11738 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
11739 highest (sign) bit, with a fixed binary point at bit point_pos.
11740 m1 holds the low part of the mantissa, m2 the high part.
11741 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
11742 bits for the mantissa, this can fail (low bits will be lost). */
11746 /* If the low part of the mantissa has bits set we cannot represent
11747 the value. */
11750 /* We have rejected the lower HOST_WIDE_INT, so update our
11751 understanding of how many bits lie in the mantissa and
11752 look only at the high HOST_WIDE_INT. */
11756 /* We can only represent values with a mantissa of the form 1.xxxx. */
11761 /* Having filtered unrepresentable values, we may now remove all
11762 but the highest 5 bits. */
11765 /* We cannot represent the value 0.0, so reject it. This is handled
11766 elsewhere. */
11770 /* Then, as bit 4 is always set, we can mask it off, leaving
11771 the mantissa in the range [0, 15]. */
11775 /* GCC internally does not use IEEE754-like encoding (where normalized
11776 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
11777 Our mantissa values are shifted 4 places to the left relative to
11778 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
11779 by 5 places to correct for GCC's representation. */
11783 }
11787 machine_mode mode,
11789 {
11799 /* This will return true to show const_vector is legal for use as either
11800 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
11801 also update INFO to show how the immediate should be generated. */
11810 {
11812 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
11813 move immediate path. */
11816 else
11817 {
11826 else
11830 }
11831 }
11844 else
11848 }
11852 machine_mode mode)
11853 {
11854 machine_mode vmode;
11860 }
11862 /* Split operands into moves from op[1] + op[2] into op[0]. */
11864 void
11866 {
11877 {
11878 /* No-op move. Can't split to nothing; emit something. */
11881 }
11883 /* Preserve register attributes for variable tracking. */
11888 /* Special case of reversed high/low parts. */
11891 {
11895 }
11897 {
11898 /* Try to avoid unnecessary moves if part of the result
11899 is in the right place already. */
11904 }
11905 else
11906 {
11911 }
11912 }
11914 /* vec_perm support. */
11916 #define MAX_VECT_LEN 16
11918 struct expand_vec_perm_d
11919 {
11922 machine_mode vmode;
11926 };
11928 /* Generate a variable permutation. */
11930 static void
11932 {
11943 {
11945 {
11946 /* Expand the argument to a V16QI mode by duplicating it. */
11950 }
11951 else
11952 {
11954 }
11955 }
11956 else
11957 {
11958 rtx pair;
11961 {
11965 }
11966 else
11967 {
11971 }
11972 }
11973 }
11975 void
11977 {
11981 rtx mask;
11983 /* The TBL instruction does not use a modulo index, so we must take care
11984 of that ourselves. */
11989 /* For big-endian, we also need to reverse the index within the vector
11990 (but not which vector). */
11992 {
11993 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
11998 }
12000 }
12002 /* Recognize patterns suitable for the TRN instructions. */
12003 static bool
12005 {
12014 /* Note that these are little-endian tests.
12015 We correct for big-endian later. */
12020 else
12025 {
12030 }
12032 /* Success! */
12039 {
12042 }
12046 {
12048 {
12061 }
12062 }
12063 else
12064 {
12066 {
12079 }
12080 }
12084 }
12086 /* Recognize patterns suitable for the UZP instructions. */
12087 static bool
12089 {
12098 /* Note that these are little-endian tests.
12099 We correct for big-endian later. */
12104 else
12109 {
12113 }
12115 /* Success! */
12122 {
12125 }
12129 {
12131 {
12144 }
12145 }
12146 else
12147 {
12149 {
12162 }
12163 }
12167 }
12169 /* Recognize patterns suitable for the ZIP instructions. */
12170 static bool
12172 {
12181 /* Note that these are little-endian tests.
12182 We correct for big-endian later. */
12185 /* Do Nothing. */
12186 ;
12189 else
12194 {
12201 }
12203 /* Success! */
12210 {
12213 }
12217 {
12219 {
12232 }
12233 }
12234 else
12235 {
12237 {
12250 }
12251 }
12255 }
12257 /* Recognize patterns for the EXT insn. */
12259 static bool
12261 {
12264 rtx offset;
12268 /* Check if the extracted indices are increasing by one. */
12270 {
12273 {
12274 /* We'll pass the same vector in twice, so allow indices to wrap. */
12276 }
12279 }
12282 {
12295 }
12297 /* Success! */
12301 /* The case where (location == 0) is a no-op for both big- and little-endian,
12302 and is removed by the mid-end at optimization levels -O1 and higher. */
12305 {
12306 /* After setup, we want the high elements of the first vector (stored
12307 at the LSB end of the register), and the low elements of the second
12308 vector (stored at the MSB end of the register). So swap. */
12310 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
12312 }
12317 }
12319 /* Recognize patterns for the REV insns. */
12321 static bool
12323 {
12332 {
12335 {
12340 }
12344 {
12351 }
12355 {
12366 }
12370 }
12374 {
12375 /* This is guaranteed to be true as the value of diff
12376 is 7, 3, 1 and we should have enough elements in the
12377 queue to generate this. Getting a vector mask with a
12378 value of diff other than these values implies that
12379 something is wrong by the time we get here. */
12383 }
12385 /* Success! */
12391 }
12393 static bool
12395 {
12398 rtx in0;
12401 rtx lane;
12405 {
12408 }
12410 /* The generic preparation in aarch64_expand_vec_perm_const_1
12411 swaps the operand order and the permute indices if it finds
12412 d->perm[0] to be in the second operand. Thus, we can always
12413 use d->op0 and need not do any extra arithmetic to get the
12414 correct lane number. */
12419 {
12434 }
12438 }
12440 static bool
12442 {
12450 /* Generic code will try constant permutation twice. Once with the
12451 original mode and again with the elements lowered to QImode.
12452 So wait and don't do the selector expansion ourselves. */
12457 {
12460 /* If big-endian and two vectors we end up with a weird mixed-endian
12461 mode on NEON. Reverse the index within each word but not the word
12462 itself. */
12465 }
12471 }
12473 static bool
12475 {
12476 /* The pattern matching functions above are written to look for a small
12477 number to begin the sequence (0, 1, N/2). If we begin with an index
12478 from the second operand, we can swap the operands. */
12480 {
12488 }
12491 {
12505 }
12507 }
12509 /* Expand a vec_perm_const pattern. */
12511 bool
12513 {
12527 {
12532 }
12535 {
12544 /* The elements of PERM do not suggest that only the first operand
12545 is used, but both operands are identical. Allow easier matching
12546 of the permutation by folding the permutation into the single
12547 input vector. */
12548 /* Fall Through. */
12560 }
12563 }
12565 static bool
12568 {
12578 /* Calculate whether all elements are in one vector. */
12580 {
12584 }
12586 /* If all elements are from the second vector, reindex as if from the
12587 first vector. */
12592 /* Check whether the mask can be applied to a single vector. */
12605 }
12607 rtx
12609 {
12610 /* We have to reverse each vector because we dont have
12611 a permuted load that can reverse-load according to ABI rules. */
12612 rtx mask;
12626 }
12628 /* Implement MODES_TIEABLE_P. */
12630 bool
12632 {
12636 /* We specifically want to allow elements of "structure" modes to
12637 be tieable to the structure. This more general condition allows
12638 other rarer situations too. */
12645 }
12647 /* Return a new RTX holding the result of moving POINTER forward by
12648 AMOUNT bytes. */
12650 static rtx
12652 {
12657 }
12659 /* Return a new RTX holding the result of moving POINTER forward by the
12660 size of the mode it points to. */
12662 static rtx
12664 {
12668 }
12670 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
12671 MODE bytes. */
12673 static void
12675 machine_mode mode)
12676 {
12679 /* "Cast" the pointers to the correct mode. */
12682 /* Emit the memcpy. */
12685 /* Move the pointers forward. */
12688 }
12690 /* Expand movmem, as if from a __builtin_memcpy. Return true if
12691 we succeed, otherwise return false. */
12693 bool
12695 {
12699 rtx base;
12702 /* When optimizing for size, give a better estimate of the length of a
12703 memcpy call, but use the default otherwise. */
12706 /* We can't do anything smart if the amount to copy is not constant. */
12712 /* Try to keep the number of instructions low. For cases below 16 bytes we
12713 need to make at most two moves. For cases above 16 bytes it will be one
12714 move for each 16 byte chunk, then at most two additional moves. */
12724 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
12725 1-byte chunk. */
12727 {
12729 {
12732 }
12738 }
12740 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
12741 4-byte chunk, partially overlapping with the previously copied chunk. */
12743 {
12747 {
12753 }
12755 }
12757 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
12758 them, then (if applicable) an 8-byte chunk. */
12760 {
12762 {
12765 }
12766 else
12767 {
12770 }
12771 }
12773 /* Finish the final bytes of the copy. We can always do this in one
12774 instruction. We either copy the exact amount we need, or partially
12775 overlap with the previous chunk we copied and copy 8-bytes. */
12784 else
12785 {
12787 {
12791 }
12792 else
12793 {
12799 }
12800 }
12803 }
12805 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
12807 static unsigned HOST_WIDE_INT
12809 {
12811 }
12813 static bool
12818 {
12819 /* STORE_BY_PIECES can be used when copying a constant string, but
12820 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
12821 For now we always fail this and let the move_by_pieces code copy
12822 the string from read-only memory. */
12827 }
12829 static rtx
12832 {
12836 insn_code icode;
12847 {
12875 }
12880 {
12883 }
12892 {
12895 }
12901 }
12903 static rtx
12906 {
12910 insn_code icode;
12922 {
12950 }
12955 {
12958 }
12966 {
12971 }
12982 {
12985 }
12991 }
12993 #undef TARGET_GEN_CCMP_FIRST
12994 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
12996 #undef TARGET_GEN_CCMP_NEXT
12997 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
12999 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
13000 instruction fusion of some sort. */
13002 static bool
13004 {
13006 }
13009 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
13010 should be kept together during scheduling. */
13012 static bool
13014 {
13015 rtx set_dest;
13018 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
13026 {
13027 /* We are trying to match:
13028 prev (mov) == (set (reg r0) (const_int imm16))
13029 curr (movk) == (set (zero_extract (reg r0)
13030 (const_int 16)
13031 (const_int 16))
13032 (const_int imm16_1)) */
13044 {
13046 }
13047 }
13051 {
13053 /* We're trying to match:
13054 prev (adrp) == (set (reg r1)
13055 (high (symbol_ref ("SYM"))))
13056 curr (add) == (set (reg r0)
13057 (lo_sum (reg r1)
13058 (symbol_ref ("SYM"))))
13059 Note that r0 need not necessarily be the same as r1, especially
13060 during pre-regalloc scheduling. */
13064 {
13072 }
13073 }
13077 {
13079 /* We're trying to match:
13080 prev (movk) == (set (zero_extract (reg r0)
13081 (const_int 16)
13082 (const_int 32))
13083 (const_int imm16_1))
13084 curr (movk) == (set (zero_extract (reg r0)
13085 (const_int 16)
13086 (const_int 48))
13087 (const_int imm16_2)) */
13103 }
13106 {
13107 /* We're trying to match:
13108 prev (adrp) == (set (reg r0)
13109 (high (symbol_ref ("SYM"))))
13110 curr (ldr) == (set (reg r1)
13111 (mem (lo_sum (reg r0)
13112 (symbol_ref ("SYM")))))
13113 or
13114 curr (ldr) == (set (reg r1)
13115 (zero_extend (mem
13116 (lo_sum (reg r0)
13117 (symbol_ref ("SYM")))))) */
13120 {
13133 }
13134 }
13142 {
13145 /* FIXME: this misses some which is considered simple arthematic
13146 instructions for ThunderX. Simple shifts are missed here. */
13152 }
13155 }
13157 /* Return true iff the instruction fusion described by OP is enabled. */
13159 bool
13161 {
13163 }
13165 /* If MEM is in the form of [base+offset], extract the two parts
13166 of address and set to BASE and OFFSET, otherwise return false
13167 after clearing BASE and OFFSET. */
13169 bool
13171 {
13172 rtx addr;
13179 {
13183 }
13187 {
13191 }
13197 }
13199 /* Types for scheduling fusion. */
13200 enum sched_fusion_type
13201 {
13203 SCHED_FUSION_LD_SIGN_EXTEND,
13204 SCHED_FUSION_LD_ZERO_EXTEND,
13205 SCHED_FUSION_LD,
13206 SCHED_FUSION_ST,
13207 SCHED_FUSION_NUM
13208 };
13210 /* If INSN is a load or store of address in the form of [base+offset],
13211 extract the two parts and set to BASE and OFFSET. Return scheduling
13212 fusion type this INSN is. */
13214 static enum sched_fusion_type
13216 {
13234 {
13239 }
13241 {
13246 }
13251 {
13254 }
13255 else
13262 }
13264 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
13266 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
13267 and PRI are only calculated for these instructions. For other instruction,
13268 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
13269 type instruction fusion can be added by returning different priorities.
13271 It's important that irrelevant instructions get the largest FUSION_PRI. */
13273 static void
13276 {
13286 {
13290 }
13292 /* Set FUSION_PRI according to fusion type and base register. */
13295 /* Calculate PRI. */
13298 /* INSN with smaller offset goes first. */
13302 else
13307 }
13309 /* Given OPERANDS of consecutive load/store, check if we can merge
13310 them into ldp/stp. LOAD is true if they are load instructions.
13311 MODE is the mode of memory operands. */
13313 bool
13316 {
13322 {
13330 }
13331 else
13332 {
13337 }
13339 /* The mems cannot be volatile. */
13343 /* Check if the addresses are in the form of [base+offset]. */
13351 /* Check if the bases are same. */
13358 /* Check if the offsets are consecutive. */
13362 /* Check if the addresses are clobbered by load. */
13364 {
13368 /* In increasing order, the last load can clobber the address. */
13371 }
13375 else
13380 else
13383 /* Check if the registers are of same class. */
13388 }
13390 /* Given OPERANDS of consecutive load/store, check if we can merge
13391 them into ldp/stp by adjusting the offset. LOAD is true if they
13392 are load instructions. MODE is the mode of memory operands.
13394 Given below consecutive stores:
13396 str w1, [xb, 0x100]
13397 str w1, [xb, 0x104]
13398 str w1, [xb, 0x108]
13399 str w1, [xb, 0x10c]
13401 Though the offsets are out of the range supported by stp, we can
13402 still pair them after adjusting the offset, like:
13404 add scratch, xb, 0x100
13405 stp w1, w1, [scratch]
13406 stp w1, w1, [scratch, 0x8]
13408 The peephole patterns detecting this opportunity should guarantee
13409 the scratch register is avaliable. */
13411 bool
13414 {
13421 {
13434 }
13435 else
13436 {
13445 }
13446 /* Skip if memory operand is by itslef valid for ldp/stp. */
13450 /* The mems cannot be volatile. */
13455 /* Check if the addresses are in the form of [base+offset]. */
13469 /* Check if the bases are same. */
13480 /* Check if the offsets are consecutive. */
13489 /* Check if the addresses are clobbered by load. */
13491 {
13497 /* In increasing order, the last load can clobber the address. */
13500 }
13504 else
13509 else
13514 else
13519 else
13522 /* Check if the registers are of same class. */
13527 }
13529 /* Given OPERANDS of consecutive load/store, this function pairs them
13530 into ldp/stp after adjusting the offset. It depends on the fact
13531 that addresses of load/store instructions are in increasing order.
13532 MODE is the mode of memory operands. CODE is the rtl operator
13533 which should be applied to all memory operands, it's SIGN_EXTEND,
13534 ZERO_EXTEND or UNKNOWN. */
13536 bool
13539 {
13545 {
13550 }
13551 else
13552 {
13558 }
13563 /* Adjust offset thus it can fit in ldp/stp instruction. */
13571 /* Further adjust to make sure all offsets are OK. */
13573 {
13576 }
13578 /* Make sure the adjustment can be done with ADD/SUB instructions. */
13583 {
13586 }
13588 /* Create new memory references. */
13592 /* Check if the adjusted address is OK for ldp/stp. */
13611 {
13616 }
13618 {
13623 }
13626 {
13631 }
13632 else
13633 {
13638 }
13640 /* Emit adjusting instruction. */
13642 /* Emit ldp/stp instructions. */
13650 }
13652 /* Return 1 if pseudo register should be created and used to hold
13653 GOT address for PIC code. */
13655 bool
13657 {
13659 }
13661 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
13663 static int
13665 {
13667 {
13674 }
13677 }
13680 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
13681 return the log2 of that value. Otherwise return -1. */
13683 int
13685 {
13700 }
13702 /* If X is a vector of equal CONST_DOUBLE values and that value is
13703 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
13705 int
13707 {
13723 }
13725 /* Implement TARGET_PROMOTED_TYPE to promote __fp16 to float. */
13726 static tree
13728 {
13732 }
13734 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
13736 static bool
13738 optimization_type opt_type)
13739 {
13741 {
13747 }
13748 }
13750 #undef TARGET_ADDRESS_COST
13751 #define TARGET_ADDRESS_COST aarch64_address_cost
13753 /* This hook will determines whether unnamed bitfields affect the alignment
13754 of the containing structure. The hook returns true if the structure
13755 should inherit the alignment requirements of an unnamed bitfield's
13756 type. */
13757 #undef TARGET_ALIGN_ANON_BITFIELD
13758 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
13760 #undef TARGET_ASM_ALIGNED_DI_OP
13763 #undef TARGET_ASM_ALIGNED_HI_OP
13766 #undef TARGET_ASM_ALIGNED_SI_OP
13769 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
13770 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
13771 hook_bool_const_tree_hwi_hwi_const_tree_true
13773 #undef TARGET_ASM_FILE_START
13774 #define TARGET_ASM_FILE_START aarch64_start_file
13776 #undef TARGET_ASM_OUTPUT_MI_THUNK
13777 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
13779 #undef TARGET_ASM_SELECT_RTX_SECTION
13780 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
13782 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
13783 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
13785 #undef TARGET_BUILD_BUILTIN_VA_LIST
13786 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
13788 #undef TARGET_CALLEE_COPIES
13789 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
13791 #undef TARGET_CAN_ELIMINATE
13792 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
13794 #undef TARGET_CAN_INLINE_P
13795 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
13797 #undef TARGET_CANNOT_FORCE_CONST_MEM
13798 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
13800 #undef TARGET_CASE_VALUES_THRESHOLD
13801 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
13803 #undef TARGET_CONDITIONAL_REGISTER_USAGE
13804 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
13806 /* Only the least significant bit is used for initialization guard
13807 variables. */
13808 #undef TARGET_CXX_GUARD_MASK_BIT
13809 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
13811 #undef TARGET_C_MODE_FOR_SUFFIX
13812 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
13814 #ifdef TARGET_BIG_ENDIAN_DEFAULT
13815 #undef TARGET_DEFAULT_TARGET_FLAGS
13816 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
13817 #endif
13819 #undef TARGET_CLASS_MAX_NREGS
13820 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
13822 #undef TARGET_BUILTIN_DECL
13823 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
13825 #undef TARGET_BUILTIN_RECIPROCAL
13826 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
13828 #undef TARGET_EXPAND_BUILTIN
13829 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
13831 #undef TARGET_EXPAND_BUILTIN_VA_START
13832 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
13834 #undef TARGET_FOLD_BUILTIN
13835 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
13837 #undef TARGET_FUNCTION_ARG
13838 #define TARGET_FUNCTION_ARG aarch64_function_arg
13840 #undef TARGET_FUNCTION_ARG_ADVANCE
13841 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
13843 #undef TARGET_FUNCTION_ARG_BOUNDARY
13844 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
13846 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
13847 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
13849 #undef TARGET_FUNCTION_VALUE
13850 #define TARGET_FUNCTION_VALUE aarch64_function_value
13852 #undef TARGET_FUNCTION_VALUE_REGNO_P
13853 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
13855 #undef TARGET_FRAME_POINTER_REQUIRED
13856 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
13858 #undef TARGET_GIMPLE_FOLD_BUILTIN
13859 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
13861 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
13862 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
13864 #undef TARGET_INIT_BUILTINS
13865 #define TARGET_INIT_BUILTINS aarch64_init_builtins
13867 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
13868 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
13869 aarch64_ira_change_pseudo_allocno_class
13871 #undef TARGET_LEGITIMATE_ADDRESS_P
13872 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
13874 #undef TARGET_LEGITIMATE_CONSTANT_P
13875 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
13877 #undef TARGET_LIBGCC_CMP_RETURN_MODE
13878 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
13880 #undef TARGET_LRA_P
13881 #define TARGET_LRA_P hook_bool_void_true
13883 #undef TARGET_MANGLE_TYPE
13884 #define TARGET_MANGLE_TYPE aarch64_mangle_type
13886 #undef TARGET_MEMORY_MOVE_COST
13887 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
13889 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
13890 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
13892 #undef TARGET_MUST_PASS_IN_STACK
13893 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
13895 /* This target hook should return true if accesses to volatile bitfields
13896 should use the narrowest mode possible. It should return false if these
13897 accesses should use the bitfield container type. */
13898 #undef TARGET_NARROW_VOLATILE_BITFIELD
13899 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
13901 #undef TARGET_OPTION_OVERRIDE
13902 #define TARGET_OPTION_OVERRIDE aarch64_override_options
13904 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
13905 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
13906 aarch64_override_options_after_change
13908 #undef TARGET_OPTION_SAVE
13909 #define TARGET_OPTION_SAVE aarch64_option_save
13911 #undef TARGET_OPTION_RESTORE
13912 #define TARGET_OPTION_RESTORE aarch64_option_restore
13914 #undef TARGET_OPTION_PRINT
13915 #define TARGET_OPTION_PRINT aarch64_option_print
13917 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
13918 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
13920 #undef TARGET_SET_CURRENT_FUNCTION
13921 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
13923 #undef TARGET_PASS_BY_REFERENCE
13924 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
13926 #undef TARGET_PREFERRED_RELOAD_CLASS
13927 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
13929 #undef TARGET_SCHED_REASSOCIATION_WIDTH
13930 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
13932 #undef TARGET_PROMOTED_TYPE
13933 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
13935 #undef TARGET_SECONDARY_RELOAD
13936 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
13938 #undef TARGET_SHIFT_TRUNCATION_MASK
13939 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
13941 #undef TARGET_SETUP_INCOMING_VARARGS
13942 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
13944 #undef TARGET_STRUCT_VALUE_RTX
13945 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
13947 #undef TARGET_REGISTER_MOVE_COST
13948 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
13950 #undef TARGET_RETURN_IN_MEMORY
13951 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
13953 #undef TARGET_RETURN_IN_MSB
13954 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
13956 #undef TARGET_RTX_COSTS
13957 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
13959 #undef TARGET_SCHED_ISSUE_RATE
13960 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
13962 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
13963 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
13964 aarch64_sched_first_cycle_multipass_dfa_lookahead
13966 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
13967 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
13968 aarch64_first_cycle_multipass_dfa_lookahead_guard
13970 #undef TARGET_TRAMPOLINE_INIT
13971 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
13973 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
13974 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
13976 #undef TARGET_VECTOR_MODE_SUPPORTED_P
13977 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
13979 #undef TARGET_ARRAY_MODE_SUPPORTED_P
13980 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
13982 #undef TARGET_VECTORIZE_ADD_STMT_COST
13983 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
13985 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
13986 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
13987 aarch64_builtin_vectorization_cost
13989 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
13990 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
13992 #undef TARGET_VECTORIZE_BUILTINS
13993 #define TARGET_VECTORIZE_BUILTINS
13995 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
13996 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
13997 aarch64_builtin_vectorized_function
13999 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
14000 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
14001 aarch64_autovectorize_vector_sizes
14003 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
14004 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
14005 aarch64_atomic_assign_expand_fenv
14007 /* Section anchor support. */
14009 #undef TARGET_MIN_ANCHOR_OFFSET
14010 #define TARGET_MIN_ANCHOR_OFFSET -256
14012 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
14013 byte offset; we can do much more for larger data types, but have no way
14014 to determine the size of the access. We assume accesses are aligned. */
14015 #undef TARGET_MAX_ANCHOR_OFFSET
14016 #define TARGET_MAX_ANCHOR_OFFSET 4095
14018 #undef TARGET_VECTOR_ALIGNMENT
14019 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
14021 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
14022 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
14023 aarch64_simd_vector_alignment_reachable
14025 /* vec_perm support. */
14027 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
14028 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
14029 aarch64_vectorize_vec_perm_const_ok
14031 #undef TARGET_INIT_LIBFUNCS
14032 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
14034 #undef TARGET_FIXED_CONDITION_CODE_REGS
14035 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
14037 #undef TARGET_FLAGS_REGNUM
14038 #define TARGET_FLAGS_REGNUM CC_REGNUM
14040 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
14041 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
14043 #undef TARGET_ASAN_SHADOW_OFFSET
14044 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
14046 #undef TARGET_LEGITIMIZE_ADDRESS
14047 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
14049 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
14050 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
14051 aarch64_use_by_pieces_infrastructure_p
14053 #undef TARGET_CAN_USE_DOLOOP_P
14054 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
14056 #undef TARGET_SCHED_MACRO_FUSION_P
14057 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
14059 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
14060 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
14062 #undef TARGET_SCHED_FUSION_PRIORITY
14063 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
14065 #undef TARGET_UNSPEC_MAY_TRAP_P
14066 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
14068 #undef TARGET_USE_PSEUDO_PIC_REG
14069 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
14071 #undef TARGET_PRINT_OPERAND
14072 #define TARGET_PRINT_OPERAND aarch64_print_operand
14074 #undef TARGET_PRINT_OPERAND_ADDRESS
14075 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
14077 #undef TARGET_OPTAB_SUPPORTED_P
14078 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
14080 #undef TARGET_OMIT_STRUCT_RETURN_REG
14081 #define TARGET_OMIT_STRUCT_RETURN_REG true