gcc/rtl.def

   1 /* This file contains the definitions and documentation for the
   2    Register Transfer Expressions (rtx's) that make up the
   3    Register Transfer Language (rtl) used in the Back End of the GNU compiler.
   4    Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004,
   5    2005, 2006, 2007
   6    Free Software Foundation, Inc.
   7
   8 This file is part of GCC.
   9
  10 GCC is free software; you can redistribute it and/or modify it under
  11 the terms of the GNU General Public License as published by the Free
  12 Software Foundation; either version 3, or (at your option) any later
  13 version.
  14
  15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  18 for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with GCC; see the file COPYING3.  If not see
  22 <http://www.gnu.org/licenses/>.  */
  23
  24
  25 /* Expression definitions and descriptions for all targets are in this file.
  26    Some will not be used for some targets.
  27
  28    The fields in the cpp macro call "DEF_RTL_EXPR()"
  29    are used to create declarations in the C source of the compiler.
  30
  31    The fields are:
  32
  33    1.  The internal name of the rtx used in the C source.
  34    It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
  35    By convention these are in UPPER_CASE.
  36
  37    2.  The name of the rtx in the external ASCII format read by
  38    read_rtx(), and printed by print_rtx().
  39    These names are stored in rtx_name[].
  40    By convention these are the internal (field 1) names in lower_case.
  41
  42    3.  The print format, and type of each rtx->u.fld[] (field) in this rtx.
  43    These formats are stored in rtx_format[].
  44    The meaning of the formats is documented in front of this array in rtl.c
  45
  46    4.  The class of the rtx.  These are stored in rtx_class and are accessed
  47    via the GET_RTX_CLASS macro.  They are defined as follows:
  48
  49      RTX_CONST_OBJ
  50          an rtx code that can be used to represent a constant object
  51          (e.g, CONST_INT)
  52      RTX_OBJ
  53          an rtx code that can be used to represent an object (e.g, REG, MEM)
  54      RTX_COMPARE
  55          an rtx code for a comparison (e.g, LT, GT)
  56      RTX_COMM_COMPARE
  57          an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
  58      RTX_UNARY
  59          an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
  60      RTX_COMM_ARITH
  61          an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
  62      RTX_TERNARY
  63          an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
  64      RTX_BIN_ARITH
  65          an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
  66      RTX_BITFIELD_OPS
  67          an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
  68      RTX_INSN
  69          an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
  70      RTX_MATCH
  71          an rtx code for something that matches in insns (e.g, MATCH_DUP)
  72      RTX_AUTOINC
  73          an rtx code for autoincrement addressing modes (e.g. POST_DEC)
  74      RTX_EXTRA
  75          everything else
  76
  77    All of the expressions that appear only in machine descriptions,
  78    not in RTL used by the compiler itself, are at the end of the file.  */
  79
  80 /* Unknown, or no such operation; the enumeration constant should have
  81    value zero.  */
  82 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
  83
  84 /* ---------------------------------------------------------------------
  85    Expressions used in constructing lists.
  86    --------------------------------------------------------------------- */
  87
  88 /* a linked list of expressions */
  89 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
  90
  91 /* a linked list of instructions.
  92    The insns are represented in print by their uids.  */
  93 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
  94
  95 /* SEQUENCE appears in the result of a `gen_...' function
  96    for a DEFINE_EXPAND that wants to make several insns.
  97    Its elements are the bodies of the insns that should be made.
  98    `emit_insn' takes the SEQUENCE apart and makes separate insns.  */
  99 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
 100
 101 /* Refers to the address of its argument.  This is only used in alias.c.  */
 102 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
 103
 104 /* ----------------------------------------------------------------------
 105    Expression types used for things in the instruction chain.
 106
 107    All formats must start with "iuu" to handle the chain.
 108    Each insn expression holds an rtl instruction and its semantics
 109    during back-end processing.
 110    See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
 111
 112    ---------------------------------------------------------------------- */
 113
 114 /* An instruction that cannot jump.  */
 115 DEF_RTL_EXPR(INSN, "insn", "iuuBieie", RTX_INSN)
 116
 117 /* An instruction that can possibly jump.
 118    Fields ( rtx->u.fld[] ) have exact same meaning as INSN's.  */
 119 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieie0", RTX_INSN)
 120
 121 /* An instruction that can possibly call a subroutine
 122    but which will not change which instruction comes next
 123    in the current function.
 124    Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
 125    All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's.  */
 126 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieiee", RTX_INSN)
 127
 128 /* A marker that indicates that control will not flow through.  */
 129 DEF_RTL_EXPR(BARRIER, "barrier", "iuu00000", RTX_EXTRA)
 130
 131 /* Holds a label that is followed by instructions.
 132    Operand:
 133    4: is used in jump.c for the use-count of the label.
 134    5: is used in the sh backend.
 135    6: is a number that is unique in the entire compilation.
 136    7: is the user-given name of the label, if any.  */
 137 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
 138
 139 /* Say where in the code a source line starts, for symbol table's sake.
 140    Operand:
 141    4: note-specific data
 142    5: enum insn_note
 143    6: unique number if insn_note == note_insn_deleted_label.  */
 144 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
 145
 146 /* ----------------------------------------------------------------------
 147    Top level constituents of INSN, JUMP_INSN and CALL_INSN.
 148    ---------------------------------------------------------------------- */
 149
 150 /* Conditionally execute code.
 151    Operand 0 is the condition that if true, the code is executed.
 152    Operand 1 is the code to be executed (typically a SET).
 153
 154    Semantics are that there are no side effects if the condition
 155    is false.  This pattern is created automatically by the if_convert
 156    pass run after reload or by target-specific splitters.  */
 157 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
 158
 159 /* Several operations to be done in parallel (perhaps under COND_EXEC).  */
 160 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
 161
 162 #ifdef USE_MAPPED_LOCATION
 163 /* A string that is passed through to the assembler as input.
 164      One can obviously pass comments through by using the
 165      assembler comment syntax.
 166      These occur in an insn all by themselves as the PATTERN.
 167      They also appear inside an ASM_OPERANDS
 168      as a convenient way to hold a string.  */
 169 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
 170
 171 /* An assembler instruction with operands.
 172    1st operand is the instruction template.
 173    2nd operand is the constraint for the output.
 174    3rd operand is the number of the output this expression refers to.
 175      When an insn stores more than one value, a separate ASM_OPERANDS
 176      is made for each output; this integer distinguishes them.
 177    4th is a vector of values of input operands.
 178    5th is a vector of modes and constraints for the input operands.
 179      Each element is an ASM_INPUT containing a constraint string
 180      and whose mode indicates the mode of the input operand.
 181    6th is the source line number.  */
 182 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
 183 #else
 184 /* A string that is passed through to the assembler as input.
 185      One can obviously pass comments through by using the
 186      assembler comment syntax.
 187      These occur in an insn all by themselves as the PATTERN.
 188      They also appear inside an ASM_OPERANDS
 189      as a convenient way to hold a string.  */
 190 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "ssi", RTX_EXTRA)
 191
 192 /* An assembler instruction with operands.
 193    1st operand is the instruction template.
 194    2nd operand is the constraint for the output.
 195    3rd operand is the number of the output this expression refers to.
 196      When an insn stores more than one value, a separate ASM_OPERANDS
 197      is made for each output; this integer distinguishes them.
 198    4th is a vector of values of input operands.
 199    5th is a vector of modes and constraints for the input operands.
 200      Each element is an ASM_INPUT containing a constraint string
 201      and whose mode indicates the mode of the input operand.
 202    6th is the name of the containing source file.
 203    7th is the source line number.  */
 204 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
 205 #endif
 206
 207 /* A machine-specific operation.
 208    1st operand is a vector of operands being used by the operation so that
 209      any needed reloads can be done.
 210    2nd operand is a unique value saying which of a number of machine-specific
 211      operations is to be performed.
 212    (Note that the vector must be the first operand because of the way that
 213    genrecog.c record positions within an insn.)
 214
 215    UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
 216    or inside an expression.
 217    UNSPEC by itself or as a component of a PARALLEL
 218    is currently considered not deletable.
 219
 220    FIXME: Replace all uses of UNSPEC that appears by itself or as a component
 221    of a PARALLEL with USE.
 222    */
 223 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
 224
 225 /* Similar, but a volatile operation and one which may trap.  */
 226 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
 227
 228 /* Vector of addresses, stored as full words.  */
 229 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want.  */
 230 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
 231
 232 /* Vector of address differences X0 - BASE, X1 - BASE, ...
 233    First operand is BASE; the vector contains the X's.
 234    The machine mode of this rtx says how much space to leave
 235    for each difference and is adjusted by branch shortening if
 236    CASE_VECTOR_SHORTEN_MODE is defined.
 237    The third and fourth operands store the target labels with the
 238    minimum and maximum addresses respectively.
 239    The fifth operand stores flags for use by branch shortening.
 240   Set at the start of shorten_branches:
 241    min_align: the minimum alignment for any of the target labels.
 242    base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
 243    min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
 244    max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
 245    min_after_base: true iff minimum address target label is after BASE.
 246    max_after_base: true iff maximum address target label is after BASE.
 247   Set by the actual branch shortening process:
 248    offset_unsigned: true iff offsets have to be treated as unsigned.
 249    scale: scaling that is necessary to make offsets fit into the mode.
 250
 251    The third, fourth and fifth operands are only valid when
 252    CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
 253    compilations.  */
 254
 255 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
 256
 257 /* Memory prefetch, with attributes supported on some targets.
 258    Operand 1 is the address of the memory to fetch.
 259    Operand 2 is 1 for a write access, 0 otherwise.
 260    Operand 3 is the level of temporal locality; 0 means there is no
 261    temporal locality and 1, 2, and 3 are for increasing levels of temporal
 262    locality.
 263
 264    The attributes specified by operands 2 and 3 are ignored for targets
 265    whose prefetch instructions do not support them.  */
 266 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
 267
 268 /* ----------------------------------------------------------------------
 269    At the top level of an instruction (perhaps under PARALLEL).
 270    ---------------------------------------------------------------------- */
 271
 272 /* Assignment.
 273    Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
 274    Operand 2 is the value stored there.
 275    ALL assignment must use SET.
 276    Instructions that do multiple assignments must use multiple SET,
 277    under PARALLEL.  */
 278 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
 279
 280 /* Indicate something is used in a way that we don't want to explain.
 281    For example, subroutine calls will use the register
 282    in which the static chain is passed.
 283
 284    USE can not appear as an operand of other rtx except for PARALLEL.
 285    USE is not deletable, as it indicates that the operand
 286    is used in some unknown way.  */
 287 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
 288
 289 /* Indicate something is clobbered in a way that we don't want to explain.
 290    For example, subroutine calls will clobber some physical registers
 291    (the ones that are by convention not saved).
 292
 293    CLOBBER can not appear as an operand of other rtx except for PARALLEL.
 294    CLOBBER of a hard register appearing by itself (not within PARALLEL)
 295    is considered undeletable before reload.  */
 296 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
 297
 298 /* Call a subroutine.
 299    Operand 1 is the address to call.
 300    Operand 2 is the number of arguments.  */
 301
 302 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
 303
 304 /* Return from a subroutine.  */
 305
 306 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
 307
 308 /* Conditional trap.
 309    Operand 1 is the condition.
 310    Operand 2 is the trap code.
 311    For an unconditional trap, make the condition (const_int 1).  */
 312 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
 313
 314 /* Placeholder for _Unwind_Resume before we know if a function call
 315    or a branch is needed.  Operand 1 is the exception region from
 316    which control is flowing.  */
 317 DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
 318
 319 /* ----------------------------------------------------------------------
 320    Primitive values for use in expressions.
 321    ---------------------------------------------------------------------- */
 322
 323 /* numeric integer constant */
 324 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
 325
 326 /* fixed-point constant */
 327 DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ)
 328
 329 /* numeric floating point constant.
 330    Operands hold the value.  They are all 'w' and there may be from 2 to 6;
 331    see real.h.  */
 332 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
 333
 334 /* Describes a vector constant.  */
 335 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
 336
 337 /* String constant.  Used for attributes in machine descriptions and
 338    for special cases in DWARF2 debug output.  NOT used for source-
 339    language string constants.  */
 340 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
 341
 342 /* This is used to encapsulate an expression whose value is constant
 343    (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
 344    recognized as a constant operand rather than by arithmetic instructions.  */
 345
 346 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
 347
 348 /* program counter.  Ordinary jumps are represented
 349    by a SET whose first operand is (PC).  */
 350 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
 351
 352 /* Used in the cselib routines to describe a value.  Objects of this
 353    kind are only allocated in cselib.c, in an alloc pool instead of
 354    in GC memory.  The only operand of a VALUE is a cselib_val_struct.  */
 355 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
 356
 357 /* A register.  The "operand" is the register number, accessed with
 358    the REGNO macro.  If this number is less than FIRST_PSEUDO_REGISTER
 359    than a hardware register is being referred to.  The second operand
 360    holds the original register number - this will be different for a
 361    pseudo register that got turned into a hard register.  The third
 362    operand points to a reg_attrs structure.
 363    This rtx needs to have as many (or more) fields as a MEM, since we
 364    can change REG rtx's into MEMs during reload.  */
 365 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
 366
 367 /* A scratch register.  This represents a register used only within a
 368    single insn.  It will be turned into a REG during register allocation
 369    or reload unless the constraint indicates that the register won't be
 370    needed, in which case it can remain a SCRATCH.  This code is
 371    marked as having one operand so it can be turned into a REG.  */
 372 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
 373
 374 /* One word of a multi-word value.
 375    The first operand is the complete value; the second says which word.
 376    The WORDS_BIG_ENDIAN flag controls whether word number 0
 377    (as numbered in a SUBREG) is the most or least significant word.
 378
 379    This is also used to refer to a value in a different machine mode.
 380    For example, it can be used to refer to a SImode value as if it were
 381    Qimode, or vice versa.  Then the word number is always 0.  */
 382 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
 383
 384 /* This one-argument rtx is used for move instructions
 385    that are guaranteed to alter only the low part of a destination.
 386    Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
 387    has an unspecified effect on the high part of REG,
 388    but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
 389    is guaranteed to alter only the bits of REG that are in HImode.
 390
 391    The actual instruction used is probably the same in both cases,
 392    but the register constraints may be tighter when STRICT_LOW_PART
 393    is in use.  */
 394
 395 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
 396
 397 /* (CONCAT a b) represents the virtual concatenation of a and b
 398    to make a value that has as many bits as a and b put together.
 399    This is used for complex values.  Normally it appears only
 400    in DECL_RTLs and during RTL generation, but not in the insn chain.  */
 401 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
 402
 403 /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
 404    all An to make a value.  This is an extension of CONCAT to larger
 405    number of components.  Like CONCAT, it should not appear in the
 406    insn chain.  Every element of the CONCATN is the same size.  */
 407 DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
 408
 409 /* A memory location; operand is the address.  The second operand is the
 410    alias set to which this MEM belongs.  We use `0' instead of `w' for this
 411    field so that the field need not be specified in machine descriptions.  */
 412 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
 413
 414 /* Reference to an assembler label in the code for this function.
 415    The operand is a CODE_LABEL found in the insn chain.  */
 416 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
 417
 418 /* Reference to a named label:
 419    Operand 0: label name
 420    Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
 421    Operand 2: tree from which this symbol is derived, or null.
 422    This is either a DECL node, or some kind of constant.  */
 423 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
 424
 425 /* The condition code register is represented, in our imagination,
 426    as a register holding a value that can be compared to zero.
 427    In fact, the machine has already compared them and recorded the
 428    results; but instructions that look at the condition code
 429    pretend to be looking at the entire value and comparing it.  */
 430 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
 431
 432 /* ----------------------------------------------------------------------
 433    Expressions for operators in an rtl pattern
 434    ---------------------------------------------------------------------- */
 435
 436 /* if_then_else.  This is used in representing ordinary
 437    conditional jump instructions.
 438      Operand:
 439      0:  condition
 440      1:  then expr
 441      2:  else expr */
 442 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
 443
 444 /* Comparison, produces a condition code result.  */
 445 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
 446
 447 /* plus */
 448 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
 449
 450 /* Operand 0 minus operand 1.  */
 451 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
 452
 453 /* Minus operand 0.  */
 454 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
 455
 456 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
 457
 458 /* Multiplication with signed saturation */
 459 DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH)
 460 /* Multiplication with unsigned saturation */
 461 DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH)
 462
 463 /* Operand 0 divided by operand 1.  */
 464 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
 465 /* Division with signed saturation */
 466 DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH)
 467 /* Division with unsigned saturation */
 468 DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH)
 469
 470 /* Remainder of operand 0 divided by operand 1.  */
 471 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
 472
 473 /* Unsigned divide and remainder.  */
 474 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
 475 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
 476
 477 /* Bitwise operations.  */
 478 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
 479 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
 480 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
 481 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
 482
 483 /* Operand:
 484      0:  value to be shifted.
 485      1:  number of bits.  */
 486 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
 487 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
 488 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
 489 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
 490 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
 491
 492 /* Minimum and maximum values of two operands.  We need both signed and
 493    unsigned forms.  (We cannot use MIN for SMIN because it conflicts
 494    with a macro of the same name.)   The signed variants should be used
 495    with floating point.  Further, if both operands are zeros, or if either
 496    operand is NaN, then it is unspecified which of the two operands is
 497    returned as the result.  */
 498
 499 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
 500 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
 501 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
 502 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
 503
 504 /* These unary operations are used to represent incrementation
 505    and decrementation as they occur in memory addresses.
 506    The amount of increment or decrement are not represented
 507    because they can be understood from the machine-mode of the
 508    containing MEM.  These operations exist in only two cases:
 509    1. pushes onto the stack.
 510    2. created automatically by the life_analysis pass in flow.c.  */
 511 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
 512 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
 513 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
 514 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
 515
 516 /* These binary operations are used to represent generic address
 517    side-effects in memory addresses, except for simple incrementation
 518    or decrementation which use the above operations.  They are
 519    created automatically by the life_analysis pass in flow.c.
 520    The first operand is a REG which is used as the address.
 521    The second operand is an expression that is assigned to the
 522    register, either before (PRE_MODIFY) or after (POST_MODIFY)
 523    evaluating the address.
 524    Currently, the compiler can only handle second operands of the
 525    form (plus (reg) (reg)) and (plus (reg) (const_int)), where
 526    the first operand of the PLUS has to be the same register as
 527    the first operand of the *_MODIFY.  */
 528 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
 529 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
 530
 531 /* Comparison operations.  The ordered comparisons exist in two
 532    flavors, signed and unsigned.  */
 533 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
 534 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
 535 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
 536 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
 537 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
 538 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
 539 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
 540 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
 541 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
 542 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
 543
 544 /* Additional floating point unordered comparison flavors.  */
 545 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
 546 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
 547
 548 /* These are equivalent to unordered or ...  */
 549 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
 550 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
 551 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
 552 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
 553 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
 554
 555 /* This is an ordered NE, ie !UNEQ, ie false for NaN.  */
 556 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
 557
 558 /* Represents the result of sign-extending the sole operand.
 559    The machine modes of the operand and of the SIGN_EXTEND expression
 560    determine how much sign-extension is going on.  */
 561 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
 562
 563 /* Similar for zero-extension (such as unsigned short to int).  */
 564 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
 565
 566 /* Similar but here the operand has a wider mode.  */
 567 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
 568
 569 /* Similar for extending floating-point values (such as SFmode to DFmode).  */
 570 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
 571 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
 572
 573 /* Conversion of fixed point operand to floating point value.  */
 574 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
 575
 576 /* With fixed-point machine mode:
 577    Conversion of floating point operand to fixed point value.
 578    Value is defined only when the operand's value is an integer.
 579    With floating-point machine mode (and operand with same mode):
 580    Operand is rounded toward zero to produce an integer value
 581    represented in floating point.  */
 582 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
 583
 584 /* Conversion of unsigned fixed point operand to floating point value.  */
 585 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
 586
 587 /* With fixed-point machine mode:
 588    Conversion of floating point operand to *unsigned* fixed point value.
 589    Value is defined only when the operand's value is an integer.  */
 590 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
 591
 592 /* Conversions involving fractional fixed-point types without saturation,
 593    including:
 594      fractional to fractional (of different precision),
 595      signed integer to fractional,
 596      fractional to signed integer,
 597      floating point to fractional,
 598      fractional to floating point.
 599    NOTE: fractional can be either signed or unsigned for conversions.  */
 600 DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY)
 601
 602 /* Conversions involving fractional fixed-point types and unsigned integer
 603    without saturation, including:
 604      unsigned integer to fractional,
 605      fractional to unsigned integer.
 606    NOTE: fractional can be either signed or unsigned for conversions.  */
 607 DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY)
 608
 609 /* Conversions involving fractional fixed-point types with saturation,
 610    including:
 611      fractional to fractional (of different precision),
 612      signed integer to fractional,
 613      floating point to fractional.
 614    NOTE: fractional can be either signed or unsigned for conversions.  */
 615 DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY)
 616
 617 /* Conversions involving fractional fixed-point types and unsigned integer
 618    with saturation, including:
 619      unsigned integer to fractional.
 620    NOTE: fractional can be either signed or unsigned for conversions.  */
 621 DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY)
 622
 623 /* Absolute value */
 624 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
 625
 626 /* Square root */
 627 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
 628
 629 /* Swap bytes.  */
 630 DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
 631
 632 /* Find first bit that is set.
 633    Value is 1 + number of trailing zeros in the arg.,
 634    or 0 if arg is 0.  */
 635 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
 636
 637 /* Count leading zeros.  */
 638 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
 639
 640 /* Count trailing zeros.  */
 641 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
 642
 643 /* Population count (number of 1 bits).  */
 644 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
 645
 646 /* Population parity (number of 1 bits modulo 2).  */
 647 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
 648
 649 /* Reference to a signed bit-field of specified size and position.
 650    Operand 0 is the memory unit (usually SImode or QImode) which
 651    contains the field's first bit.  Operand 1 is the width, in bits.
 652    Operand 2 is the number of bits in the memory unit before the
 653    first bit of this field.
 654    If BITS_BIG_ENDIAN is defined, the first bit is the msb and
 655    operand 2 counts from the msb of the memory unit.
 656    Otherwise, the first bit is the lsb and operand 2 counts from
 657    the lsb of the memory unit.
 658    This kind of expression can not appear as an lvalue in RTL.  */
 659 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
 660
 661 /* Similar for unsigned bit-field.
 662    But note!  This kind of expression _can_ appear as an lvalue.  */
 663 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
 664
 665 /* For RISC machines.  These save memory when splitting insns.  */
 666
 667 /* HIGH are the high-order bits of a constant expression.  */
 668 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
 669
 670 /* LO_SUM is the sum of a register and the low-order bits
 671    of a constant expression.  */
 672 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
 673
 674 /* Describes a merge operation between two vector values.
 675    Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
 676    that specifies where the parts of the result are taken from.  Set bits
 677    indicate operand 0, clear bits indicate operand 1.  The parts are defined
 678    by the mode of the vectors.  */
 679 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
 680
 681 /* Describes an operation that selects parts of a vector.
 682    Operands 0 is the source vector, operand 1 is a PARALLEL that contains
 683    a CONST_INT for each of the subparts of the result vector, giving the
 684    number of the source subpart that should be stored into it.  */
 685 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
 686
 687 /* Describes a vector concat operation.  Operands 0 and 1 are the source
 688    vectors, the result is a vector that is as long as operands 0 and 1
 689    combined and is the concatenation of the two source vectors.  */
 690 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
 691
 692 /* Describes an operation that converts a small vector into a larger one by
 693    duplicating the input values.  The output vector mode must have the same
 694    submodes as the input vector mode, and the number of output parts must be
 695    an integer multiple of the number of input parts.  */
 696 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
 697
 698 /* Addition with signed saturation */
 699 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
 700
 701 /* Addition with unsigned saturation */
 702 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
 703
 704 /* Operand 0 minus operand 1, with signed saturation.  */
 705 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
 706
 707 /* Negation with signed saturation.  */
 708 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
 709 /* Negation with unsigned saturation.  */
 710 DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY)
 711
 712 /* Absolute value with signed saturation.  */
 713 DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
 714
 715 /* Shift left with signed saturation.  */
 716 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
 717
 718 /* Shift left with unsigned saturation.  */
 719 DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH)
 720
 721 /* Operand 0 minus operand 1, with unsigned saturation.  */
 722 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
 723
 724 /* Signed saturating truncate.  */
 725 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
 726
 727 /* Unsigned saturating truncate.  */
 728 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
 729
 730 /* Information about the variable and its location.  */
 731 /* Changed 'te' to 'tei'; the 'i' field is for recording
 732    initialization status of variables.  */
 733 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "tei", RTX_EXTRA)
 734
 735 /* All expressions from this point forward appear only in machine
 736    descriptions.  */
 737 #ifdef GENERATOR_FILE
 738
 739 /* Include a secondary machine-description file at this point.  */
 740 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
 741
 742 /* Pattern-matching operators:  */
 743
 744 /* Use the function named by the second arg (the string)
 745    as a predicate; if matched, store the structure that was matched
 746    in the operand table at index specified by the first arg (the integer).
 747    If the second arg is the null string, the structure is just stored.
 748
 749    A third string argument indicates to the register allocator restrictions
 750    on where the operand can be allocated.
 751
 752    If the target needs no restriction on any instruction this field should
 753    be the null string.
 754
 755    The string is prepended by:
 756    '=' to indicate the operand is only written to.
 757    '+' to indicate the operand is both read and written to.
 758
 759    Each character in the string represents an allocable class for an operand.
 760    'g' indicates the operand can be any valid class.
 761    'i' indicates the operand can be immediate (in the instruction) data.
 762    'r' indicates the operand can be in a register.
 763    'm' indicates the operand can be in memory.
 764    'o' a subset of the 'm' class.  Those memory addressing modes that
 765        can be offset at compile time (have a constant added to them).
 766
 767    Other characters indicate target dependent operand classes and
 768    are described in each target's machine description.
 769
 770    For instructions with more than one operand, sets of classes can be
 771    separated by a comma to indicate the appropriate multi-operand constraints.
 772    There must be a 1 to 1 correspondence between these sets of classes in
 773    all operands for an instruction.
 774    */
 775 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
 776
 777 /* Match a SCRATCH or a register.  When used to generate rtl, a
 778    SCRATCH is generated.  As for MATCH_OPERAND, the mode specifies
 779    the desired mode and the first argument is the operand number.
 780    The second argument is the constraint.  */
 781 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
 782
 783 /* Apply a predicate, AND match recursively the operands of the rtx.
 784    Operand 0 is the operand-number, as in match_operand.
 785    Operand 1 is a predicate to apply (as a string, a function name).
 786    Operand 2 is a vector of expressions, each of which must match
 787    one subexpression of the rtx this construct is matching.  */
 788 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
 789
 790 /* Match a PARALLEL of arbitrary length.  The predicate is applied
 791    to the PARALLEL and the initial expressions in the PARALLEL are matched.
 792    Operand 0 is the operand-number, as in match_operand.
 793    Operand 1 is a predicate to apply to the PARALLEL.
 794    Operand 2 is a vector of expressions, each of which must match the
 795    corresponding element in the PARALLEL.  */
 796 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
 797
 798 /* Match only something equal to what is stored in the operand table
 799    at the index specified by the argument.  Use with MATCH_OPERAND.  */
 800 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
 801
 802 /* Match only something equal to what is stored in the operand table
 803    at the index specified by the argument.  Use with MATCH_OPERATOR.  */
 804 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
 805
 806 /* Match only something equal to what is stored in the operand table
 807    at the index specified by the argument.  Use with MATCH_PARALLEL.  */
 808 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
 809
 810 /* Appears only in define_predicate/define_special_predicate
 811    expressions.  Evaluates true only if the operand has an RTX code
 812    from the set given by the argument (a comma-separated list).  If the
 813    second argument is present and nonempty, it is a sequence of digits
 814    and/or letters which indicates the subexpression to test, using the
 815    same syntax as genextract/genrecog's location strings: 0-9 for
 816    XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
 817    the result of the one before it.  */
 818 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
 819
 820 /* Appears only in define_predicate/define_special_predicate
 821     expressions.  The argument is a C expression to be injected at this
 822     point in the predicate formula.  */
 823 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
 824
 825 /* Insn (and related) definitions.  */
 826
 827 /* Definition of the pattern for one kind of instruction.
 828    Operand:
 829    0: names this instruction.
 830       If the name is the null string, the instruction is in the
 831       machine description just to be recognized, and will never be emitted by
 832       the tree to rtl expander.
 833    1: is the pattern.
 834    2: is a string which is a C expression
 835       giving an additional condition for recognizing this pattern.
 836       A null string means no extra condition.
 837    3: is the action to execute if this pattern is matched.
 838       If this assembler code template starts with a * then it is a fragment of
 839       C code to run to decide on a template to use.  Otherwise, it is the
 840       template to use.
 841    4: optionally, a vector of attributes for this insn.
 842      */
 843 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
 844
 845 /* Definition of a peephole optimization.
 846    1st operand: vector of insn patterns to match
 847    2nd operand: C expression that must be true
 848    3rd operand: template or C code to produce assembler output.
 849    4: optionally, a vector of attributes for this insn.
 850
 851    This form is deprecated; use define_peephole2 instead.  */
 852 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
 853
 854 /* Definition of a split operation.
 855    1st operand: insn pattern to match
 856    2nd operand: C expression that must be true
 857    3rd operand: vector of insn patterns to place into a SEQUENCE
 858    4th operand: optionally, some C code to execute before generating the
 859         insns.  This might, for example, create some RTX's and store them in
 860         elements of `recog_data.operand' for use by the vector of
 861         insn-patterns.
 862         (`operands' is an alias here for `recog_data.operand').  */
 863 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
 864
 865 /* Definition of an insn and associated split.
 866    This is the concatenation, with a few modifications, of a define_insn
 867    and a define_split which share the same pattern.
 868    Operand:
 869    0: names this instruction.
 870       If the name is the null string, the instruction is in the
 871       machine description just to be recognized, and will never be emitted by
 872       the tree to rtl expander.
 873    1: is the pattern.
 874    2: is a string which is a C expression
 875       giving an additional condition for recognizing this pattern.
 876       A null string means no extra condition.
 877    3: is the action to execute if this pattern is matched.
 878       If this assembler code template starts with a * then it is a fragment of
 879       C code to run to decide on a template to use.  Otherwise, it is the
 880       template to use.
 881    4: C expression that must be true for split.  This may start with "&&"
 882       in which case the split condition is the logical and of the insn
 883       condition and what follows the "&&" of this operand.
 884    5: vector of insn patterns to place into a SEQUENCE
 885    6: optionally, some C code to execute before generating the
 886         insns.  This might, for example, create some RTX's and store them in
 887         elements of `recog_data.operand' for use by the vector of
 888         insn-patterns.
 889         (`operands' is an alias here for `recog_data.operand').
 890    7: optionally, a vector of attributes for this insn.  */
 891 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
 892
 893 /* Definition of an RTL peephole operation.
 894    Follows the same arguments as define_split.  */
 895 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
 896
 897 /* Define how to generate multiple insns for a standard insn name.
 898    1st operand: the insn name.
 899    2nd operand: vector of insn-patterns.
 900         Use match_operand to substitute an element of `recog_data.operand'.
 901    3rd operand: C expression that must be true for this to be available.
 902         This may not test any operands.
 903    4th operand: Extra C code to execute before generating the insns.
 904         This might, for example, create some RTX's and store them in
 905         elements of `recog_data.operand' for use by the vector of
 906         insn-patterns.
 907         (`operands' is an alias here for `recog_data.operand').  */
 908 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
 909
 910 /* Define a requirement for delay slots.
 911    1st operand: Condition involving insn attributes that, if true,
 912                 indicates that the insn requires the number of delay slots
 913                 shown.
 914    2nd operand: Vector whose length is the three times the number of delay
 915                 slots required.
 916                 Each entry gives three conditions, each involving attributes.
 917                 The first must be true for an insn to occupy that delay slot
 918                 location.  The second is true for all insns that can be
 919                 annulled if the branch is true and the third is true for all
 920                 insns that can be annulled if the branch is false.
 921
 922    Multiple DEFINE_DELAYs may be present.  They indicate differing
 923    requirements for delay slots.  */
 924 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
 925
 926 /* Define attribute computation for `asm' instructions.  */
 927 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
 928
 929 /* Definition of a conditional execution meta operation.  Automatically
 930    generates new instances of DEFINE_INSN, selected by having attribute
 931    "predicable" true.  The new pattern will contain a COND_EXEC and the
 932    predicate at top-level.
 933
 934    Operand:
 935    0: The predicate pattern.  The top-level form should match a
 936       relational operator.  Operands should have only one alternative.
 937    1: A C expression giving an additional condition for recognizing
 938       the generated pattern.
 939    2: A template or C code to produce assembler output.  */
 940 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
 941
 942 /* Definition of an operand predicate.  The difference between
 943    DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
 944    not warn about a match_operand with no mode if it has a predicate
 945    defined with DEFINE_SPECIAL_PREDICATE.
 946
 947    Operand:
 948    0: The name of the predicate.
 949    1: A boolean expression which computes whether or not the predicate
 950       matches.  This expression can use IOR, AND, NOT, MATCH_OPERAND,
 951       MATCH_CODE, and MATCH_TEST.  It must be specific enough that genrecog
 952       can calculate the set of RTX codes that can possibly match.
 953    2: A C function body which must return true for the predicate to match.
 954       Optional.  Use this when the test is too complicated to fit into a
 955       match_test expression.  */
 956 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
 957 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
 958
 959 /* Definition of a register operand constraint.  This simply maps the
 960    constraint string to a register class.
 961
 962    Operand:
 963    0: The name of the constraint (often, but not always, a single letter).
 964    1: A C expression which evaluates to the appropriate register class for
 965       this constraint.  If this is not just a constant, it should look only
 966       at -m switches and the like.
 967    2: A docstring for this constraint, in Texinfo syntax; not currently
 968       used, in future will be incorporated into the manual's list of
 969       machine-specific operand constraints.  */
 970 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
 971
 972 /* Definition of a non-register operand constraint.  These look at the
 973    operand and decide whether it fits the constraint.
 974
 975    DEFINE_CONSTRAINT gets no special treatment if it fails to match.
 976    It is appropriate for constant-only constraints, and most others.
 977
 978    DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
 979    to match, if it doesn't already, by converting the operand to the form
 980    (mem (reg X)) where X is a base register.  It is suitable for constraints
 981    that describe a subset of all memory references.
 982
 983    DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
 984    to match, if it doesn't already, by converting the operand to the form
 985    (reg X) where X is a base register.  It is suitable for constraints that
 986    describe a subset of all address references.
 987
 988    When in doubt, use plain DEFINE_CONSTRAINT.
 989
 990    Operand:
 991    0: The name of the constraint (often, but not always, a single letter).
 992    1: A docstring for this constraint, in Texinfo syntax; not currently
 993       used, in future will be incorporated into the manual's list of
 994       machine-specific operand constraints.
 995    2: A boolean expression which computes whether or not the constraint
 996       matches.  It should follow the same rules as a define_predicate
 997       expression, including the bit about specifying the set of RTX codes
 998       that could possibly match.  MATCH_TEST subexpressions may make use of
 999       these variables:
1000         `op'    - the RTL object defining the operand.
1001         `mode'  - the mode of `op'.
1002         `ival'  - INTVAL(op), if op is a CONST_INT.
1003         `hval'  - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
1004         `lval'  - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
1005         `rval'  - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
1006                   CONST_DOUBLE.
1007       Do not use ival/hval/lval/rval if op is not the appropriate kind of
1008       RTL object.  */
1009 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
1010 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
1011 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
1012
1013
1014 /* Constructions for CPU pipeline description described by NDFAs.  */
1015
1016 /* (define_cpu_unit string [string]) describes cpu functional
1017    units (separated by comma).
1018
1019    1st operand: Names of cpu functional units.
1020    2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
1021
1022    All define_reservations, define_cpu_units, and
1023    define_query_cpu_units should have unique names which may not be
1024    "nothing".  */
1025 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
1026
1027 /* (define_query_cpu_unit string [string]) describes cpu functional
1028    units analogously to define_cpu_unit.  The reservation of such
1029    units can be queried for automaton state.  */
1030 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
1031
1032 /* (exclusion_set string string) means that each CPU functional unit
1033    in the first string can not be reserved simultaneously with any
1034    unit whose name is in the second string and vise versa.  CPU units
1035    in the string are separated by commas.  For example, it is useful
1036    for description CPU with fully pipelined floating point functional
1037    unit which can execute simultaneously only single floating point
1038    insns or only double floating point insns.  All CPU functional
1039    units in a set should belong to the same automaton.  */
1040 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
1041
1042 /* (presence_set string string) means that each CPU functional unit in
1043    the first string can not be reserved unless at least one of pattern
1044    of units whose names are in the second string is reserved.  This is
1045    an asymmetric relation.  CPU units or unit patterns in the strings
1046    are separated by commas.  Pattern is one unit name or unit names
1047    separated by white-spaces.
1048
1049    For example, it is useful for description that slot1 is reserved
1050    after slot0 reservation for a VLIW processor.  We could describe it
1051    by the following construction
1052
1053       (presence_set "slot1" "slot0")
1054
1055    Or slot1 is reserved only after slot0 and unit b0 reservation.  In
1056    this case we could write
1057
1058       (presence_set "slot1" "slot0 b0")
1059
1060    All CPU functional units in a set should belong to the same
1061    automaton.  */
1062 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1063
1064 /* (final_presence_set string string) is analogous to `presence_set'.
1065    The difference between them is when checking is done.  When an
1066    instruction is issued in given automaton state reflecting all
1067    current and planned unit reservations, the automaton state is
1068    changed.  The first state is a source state, the second one is a
1069    result state.  Checking for `presence_set' is done on the source
1070    state reservation, checking for `final_presence_set' is done on the
1071    result reservation.  This construction is useful to describe a
1072    reservation which is actually two subsequent reservations.  For
1073    example, if we use
1074
1075       (presence_set "slot1" "slot0")
1076
1077    the following insn will be never issued (because slot1 requires
1078    slot0 which is absent in the source state).
1079
1080       (define_reservation "insn_and_nop" "slot0 + slot1")
1081
1082    but it can be issued if we use analogous `final_presence_set'.  */
1083 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1084
1085 /* (absence_set string string) means that each CPU functional unit in
1086    the first string can be reserved only if each pattern of units
1087    whose names are in the second string is not reserved.  This is an
1088    asymmetric relation (actually exclusion set is analogous to this
1089    one but it is symmetric).  CPU units or unit patterns in the string
1090    are separated by commas.  Pattern is one unit name or unit names
1091    separated by white-spaces.
1092
1093    For example, it is useful for description that slot0 can not be
1094    reserved after slot1 or slot2 reservation for a VLIW processor.  We
1095    could describe it by the following construction
1096
1097       (absence_set "slot2" "slot0, slot1")
1098
1099    Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1100    slot1 and unit b1 are reserved .  In this case we could write
1101
1102       (absence_set "slot2" "slot0 b0, slot1 b1")
1103
1104    All CPU functional units in a set should to belong the same
1105    automaton.  */
1106 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1107
1108 /* (final_absence_set string string) is analogous to `absence_set' but
1109    checking is done on the result (state) reservation.  See comments
1110    for `final_presence_set'.  */
1111 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1112
1113 /* (define_bypass number out_insn_names in_insn_names) names bypass
1114    with given latency (the first number) from insns given by the first
1115    string (see define_insn_reservation) into insns given by the second
1116    string.  Insn names in the strings are separated by commas.  The
1117    third operand is optional name of function which is additional
1118    guard for the bypass.  The function will get the two insns as
1119    parameters.  If the function returns zero the bypass will be
1120    ignored for this case.  Additional guard is necessary to recognize
1121    complicated bypasses, e.g. when consumer is load address.  */
1122 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1123
1124 /* (define_automaton string) describes names of automata generated and
1125    used for pipeline hazards recognition.  The names are separated by
1126    comma.  Actually it is possibly to generate the single automaton
1127    but unfortunately it can be very large.  If we use more one
1128    automata, the summary size of the automata usually is less than the
1129    single one.  The automaton name is used in define_cpu_unit and
1130    define_query_cpu_unit.  All automata should have unique names.  */
1131 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1132
1133 /* (automata_option string) describes option for generation of
1134    automata.  Currently there are the following options:
1135
1136    o "no-minimization" which makes no minimization of automata.  This
1137      is only worth to do when we are debugging the description and
1138      need to look more accurately at reservations of states.
1139
1140    o "time" which means printing additional time statistics about
1141       generation of automata.
1142
1143    o "v" which means generation of file describing the result
1144      automata.  The file has suffix `.dfa' and can be used for the
1145      description verification and debugging.
1146
1147    o "w" which means generation of warning instead of error for
1148      non-critical errors.
1149
1150    o "ndfa" which makes nondeterministic finite state automata.
1151
1152    o "progress" which means output of a progress bar showing how many
1153      states were generated so far for automaton being processed.  */
1154 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1155
1156 /* (define_reservation string string) names reservation (the first
1157    string) of cpu functional units (the 2nd string).  Sometimes unit
1158    reservations for different insns contain common parts.  In such
1159    case, you can describe common part and use its name (the 1st
1160    parameter) in regular expression in define_insn_reservation.  All
1161    define_reservations, define_cpu_units, and define_query_cpu_units
1162    should have unique names which may not be "nothing".  */
1163 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1164
1165 /* (define_insn_reservation name default_latency condition regexpr)
1166    describes reservation of cpu functional units (the 3nd operand) for
1167    instruction which is selected by the condition (the 2nd parameter).
1168    The first parameter is used for output of debugging information.
1169    The reservations are described by a regular expression according
1170    the following syntax:
1171
1172        regexp = regexp "," oneof
1173               | oneof
1174
1175        oneof = oneof "|" allof
1176              | allof
1177
1178        allof = allof "+" repeat
1179              | repeat
1180
1181        repeat = element "*" number
1182               | element
1183
1184        element = cpu_function_unit_name
1185                | reservation_name
1186                | result_name
1187                | "nothing"
1188                | "(" regexp ")"
1189
1190        1. "," is used for describing start of the next cycle in
1191        reservation.
1192
1193        2. "|" is used for describing the reservation described by the
1194        first regular expression *or* the reservation described by the
1195        second regular expression *or* etc.
1196
1197        3. "+" is used for describing the reservation described by the
1198        first regular expression *and* the reservation described by the
1199        second regular expression *and* etc.
1200
1201        4. "*" is used for convenience and simply means sequence in
1202        which the regular expression are repeated NUMBER times with
1203        cycle advancing (see ",").
1204
1205        5. cpu functional unit name which means its reservation.
1206
1207        6. reservation name -- see define_reservation.
1208
1209        7. string "nothing" means no units reservation.  */
1210
1211 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1212
1213 /* Expressions used for insn attributes.  */
1214
1215 /* Definition of an insn attribute.
1216    1st operand: name of the attribute
1217    2nd operand: comma-separated list of possible attribute values
1218    3rd operand: expression for the default value of the attribute.  */
1219 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1220
1221 /* Marker for the name of an attribute.  */
1222 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1223
1224 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1225    in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1226    pattern.
1227
1228    (set_attr "name" "value") is equivalent to
1229    (set (attr "name") (const_string "value"))  */
1230 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1231
1232 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1233    specify that attribute values are to be assigned according to the
1234    alternative matched.
1235
1236    The following three expressions are equivalent:
1237
1238    (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1239                             (eq_attrq "alternative" "2") (const_string "a2")]
1240                            (const_string "a3")))
1241    (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1242                                  (const_string "a3")])
1243    (set_attr "att" "a1,a2,a3")
1244  */
1245 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1246
1247 /* A conditional expression true if the value of the specified attribute of
1248    the current insn equals the specified value.  The first operand is the
1249    attribute name and the second is the comparison value.  */
1250 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1251
1252 /* A special case of the above representing a set of alternatives.  The first
1253    operand is bitmap of the set, the second one is the default value.  */
1254 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1255
1256 /* A conditional expression which is true if the specified flag is
1257    true for the insn being scheduled in reorg.
1258
1259    genattr.c defines the following flags which can be tested by
1260    (attr_flag "foo") expressions in eligible_for_delay.
1261
1262    forward, backward, very_likely, likely, very_unlikely, and unlikely.  */
1263
1264 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1265
1266 /* General conditional. The first operand is a vector composed of pairs of
1267    expressions.  The first element of each pair is evaluated, in turn.
1268    The value of the conditional is the second expression of the first pair
1269    whose first expression evaluates nonzero.  If none of the expressions is
1270    true, the second operand will be used as the value of the conditional.  */
1271 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1272
1273 #endif /* GENERATOR_FILE */
1274
1275 /*
1276 Local variables:
1277 mode:c
1278 End:
1279 */