| blob | c4f6771d619f74aea5e22a8958f96802fb137ef2 |
1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #ifndef _BFIN_CONFIG
22 #define _BFIN_CONFIG
24 #define OBJECT_FORMAT_ELF
26 #define BRT 1
27 #define BRF 0
29 /* Print subsidiary information on the compiler version in use. */
32 /* Run-time compilation parameters selecting different hardware subsets. */
36 /* Predefinition in the preprocessor for this target machine */
37 #ifndef TARGET_CPU_CPP_BUILTINS
38 #define TARGET_CPU_CPP_BUILTINS() \
39 do \
40 { \
45 \
46 switch (bfin_cpu_type) \
47 { \
48 case BFIN_CPU_BF512: \
51 break; \
52 case BFIN_CPU_BF514: \
55 break; \
56 case BFIN_CPU_BF516: \
59 break; \
60 case BFIN_CPU_BF518: \
63 break; \
64 case BFIN_CPU_BF522: \
67 break; \
68 case BFIN_CPU_BF523: \
71 break; \
72 case BFIN_CPU_BF524: \
75 break; \
76 case BFIN_CPU_BF525: \
79 break; \
80 case BFIN_CPU_BF526: \
83 break; \
84 case BFIN_CPU_BF527: \
87 break; \
88 case BFIN_CPU_BF531: \
90 break; \
91 case BFIN_CPU_BF532: \
93 break; \
94 case BFIN_CPU_BF533: \
96 break; \
97 case BFIN_CPU_BF534: \
99 break; \
100 case BFIN_CPU_BF536: \
102 break; \
103 case BFIN_CPU_BF537: \
105 break; \
106 case BFIN_CPU_BF538: \
108 break; \
109 case BFIN_CPU_BF539: \
111 break; \
112 case BFIN_CPU_BF542: \
115 break; \
116 case BFIN_CPU_BF544: \
119 break; \
120 case BFIN_CPU_BF548: \
123 break; \
124 case BFIN_CPU_BF547: \
127 break; \
128 case BFIN_CPU_BF549: \
131 break; \
132 case BFIN_CPU_BF561: \
134 break; \
135 } \
136 \
137 if (bfin_si_revision != -1) \
138 { \
140 char *buf = XALLOCAVEC (char, 7); \
141 \
144 } \
145 \
146 if (bfin_workarounds) \
148 if (ENABLE_WA_SPECULATIVE_LOADS) \
150 if (ENABLE_WA_SPECULATIVE_SYNCS) \
152 if (ENABLE_WA_INDIRECT_CALLS) \
154 if (ENABLE_WA_RETS) \
156 \
157 if (TARGET_FDPIC) \
158 { \
161 } \
162 if (TARGET_ID_SHARED_LIBRARY \
163 && !TARGET_SEP_DATA) \
165 if (flag_no_builtin) \
167 if (TARGET_MULTICORE) \
169 if (TARGET_COREA) \
171 if (TARGET_COREB) \
173 if (TARGET_SDRAM) \
175 } \
176 while (0)
177 #endif
180 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
181 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
182 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
183 "
184 #ifndef SUBTARGET_DRIVER_SELF_SPECS
185 # define SUBTARGET_DRIVER_SELF_SPECS
186 #endif
189 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \
190 "
192 /* A C string constant that tells the GCC driver program options to pass to
193 the assembler. It can also specify how to translate options you give to GNU
194 CC into options for GCC to pass to the assembler. See the file `sun3.h'
195 for an example of this.
197 Do not define this macro if it does not need to do anything.
199 Defined in svr4.h. */
200 #undef ASM_SPEC
202 %{G*} %{v} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \
203 %{mno-fdpic:-mnopic} %{mfdpic}"
206 %{h*} %{v:-V} \
207 %{b} \
208 %{mfdpic:-melf32bfinfd -z text} \
209 %{static:-dn -Bstatic} \
210 %{shared:-G -Bdynamic} \
211 %{symbolic:-Bsymbolic} \
212 %{G*} \
213 %{YP,*} \
214 %{Qy:} %{!Qn:-Qy} \
215 -init __init -fini __fini "
217 /* Generate DSP instructions, like DSP halfword loads */
218 #define TARGET_DSP (1)
220 #define TARGET_DEFAULT 0
222 /* Maximum number of library ids we permit */
223 #define MAX_LIBRARY_ID 255
227 /* Sometimes certain combinations of command options do not make
228 sense on a particular target machine. You can define a macro
229 `OVERRIDE_OPTIONS' to take account of this. This macro, if
230 defined, is executed once just after all the command options have
231 been parsed.
233 Don't use this macro to turn on various extra optimizations for
234 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
236 #define OVERRIDE_OPTIONS override_options ()
238 #define FUNCTION_MODE SImode
239 #define Pmode SImode
241 /* store-condition-codes instructions store 0 for false
242 This is the value stored for true. */
243 #define STORE_FLAG_VALUE 1
245 /* Define this if pushing a word on the stack
246 makes the stack pointer a smaller address. */
247 #define STACK_GROWS_DOWNWARD
249 #define STACK_PUSH_CODE PRE_DEC
251 /* Define this to nonzero if the nominal address of the stack frame
252 is at the high-address end of the local variables;
253 that is, each additional local variable allocated
254 goes at a more negative offset in the frame. */
255 #define FRAME_GROWS_DOWNWARD 1
257 /* We define a dummy ARGP register; the parameters start at offset 0 from
258 it. */
259 #define FIRST_PARM_OFFSET(DECL) 0
261 /* Offset within stack frame to start allocating local variables at.
262 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
263 first local allocated. Otherwise, it is the offset to the BEGINNING
264 of the first local allocated. */
265 #define STARTING_FRAME_OFFSET 0
267 /* Register to use for pushing function arguments. */
268 #define STACK_POINTER_REGNUM REG_P6
270 /* Base register for access to local variables of the function. */
271 #define FRAME_POINTER_REGNUM REG_P7
273 /* A dummy register that will be eliminated to either FP or SP. */
274 #define ARG_POINTER_REGNUM REG_ARGP
276 /* `PIC_OFFSET_TABLE_REGNUM'
277 The register number of the register used to address a table of
278 static data addresses in memory. In some cases this register is
279 defined by a processor's "application binary interface" (ABI).
280 When this macro is defined, RTL is generated for this register
281 once, as with the stack pointer and frame pointer registers. If
282 this macro is not defined, it is up to the machine-dependent files
283 to allocate such a register (if necessary). */
284 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
286 #define FDPIC_FPTR_REGNO REG_P1
287 #define FDPIC_REGNO REG_P3
288 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
290 /* A static chain register for nested functions. We need to use a
291 call-clobbered register for this. */
292 #define STATIC_CHAIN_REGNUM REG_P2
294 /* Define this if functions should assume that stack space has been
295 allocated for arguments even when their values are passed in
296 registers.
298 The value of this macro is the size, in bytes, of the area reserved for
299 arguments passed in registers.
301 This space can either be allocated by the caller or be a part of the
302 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
303 says which. */
304 #define FIXED_STACK_AREA 12
305 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
307 /* Define this if the above stack space is to be considered part of the
308 * space allocated by the caller. */
309 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
311 /* Define this if the maximum size of all the outgoing args is to be
312 accumulated and pushed during the prologue. The amount can be
313 found in the variable crtl->outgoing_args_size. */
314 #define ACCUMULATE_OUTGOING_ARGS 1
316 /* Value should be nonzero if functions must have frame pointers.
317 Zero means the frame pointer need not be set up (and parms
318 may be accessed via the stack pointer) in functions that seem suitable.
319 This is computed in `reload', in reload1.c.
320 */
321 #define FRAME_POINTER_REQUIRED (bfin_frame_pointer_required ())
323 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
325 /* If defined, a C expression to compute the alignment for a local
326 variable. TYPE is the data type, and ALIGN is the alignment that
327 the object would ordinarily have. The value of this macro is used
328 instead of that alignment to align the object.
330 If this macro is not defined, then ALIGN is used.
332 One use of this macro is to increase alignment of medium-size
333 data to make it all fit in fewer cache lines. */
335 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
337 /* Make strings word-aligned so strcpy from constants will be faster. */
338 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
339 (TREE_CODE (EXP) == STRING_CST \
340 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
342 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
343 #define TRAMPOLINE_TEMPLATE(FILE) \
344 if (TARGET_FDPIC) \
345 { \
355 } \
356 else \
357 { \
363 }
365 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
366 initialize_trampoline (TRAMP, FNADDR, CXT)
367 \f
368 /* Definitions for register eliminations.
370 This is an array of structures. Each structure initializes one pair
371 of eliminable registers. The "from" register number is given first,
372 followed by "to". Eliminations of the same "from" register are listed
373 in order of preference.
375 There are two registers that can always be eliminated on the i386.
376 The frame pointer and the arg pointer can be replaced by either the
377 hard frame pointer or to the stack pointer, depending upon the
378 circumstances. The hard frame pointer is not used before reload and
379 so it is not eligible for elimination. */
381 #define ELIMINABLE_REGS \
382 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
383 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
384 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
386 /* Given FROM and TO register numbers, say whether this elimination is
387 allowed. Frame pointer elimination is automatically handled.
389 All other eliminations are valid. */
391 #define CAN_ELIMINATE(FROM, TO) \
392 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
394 /* Define the offset between two registers, one to be eliminated, and the other
395 its replacement, at the start of a routine. */
397 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
398 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
399 \f
400 /* This processor has
401 8 data register for doing arithmetic
402 8 pointer register for doing addressing, including
403 1 stack pointer P6
404 1 frame pointer P7
405 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
406 1 condition code flag register CC
407 5 return address registers RETS/I/X/N/E
408 1 arithmetic status register (ASTAT). */
410 #define FIRST_PSEUDO_REGISTER 50
412 #define D_REGNO_P(X) ((X) <= REG_R7)
413 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
414 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
415 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
416 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
417 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
418 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
419 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
420 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
422 #define REGISTER_NAMES { \
432 }
434 #define SHORT_REGISTER_NAMES { \
440 #define HIGH_REGISTER_NAMES { \
446 #define DREGS_PAIR_NAMES { \
449 #define BYTE_REGISTER_NAMES { \
453 /* 1 for registers that have pervasive standard uses
454 and are not available for the register allocator. */
456 #define FIXED_REGISTERS \
458 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
460 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
462 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
464 1, 1 \
465 }
467 /* 1 for registers not available across function calls.
468 These must include the FIXED_REGISTERS and also any
469 registers that can be used without being saved.
470 The latter must include the registers where values are returned
471 and the register where structure-value addresses are passed.
472 Aside from that, you can include as many other registers as you like. */
474 #define CALL_USED_REGISTERS \
476 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
478 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
480 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
482 1, 1 \
483 }
485 /* Order in which to allocate registers. Each register must be
486 listed once, even those in FIXED_REGISTERS. List frame pointer
487 late and fixed registers last. Note that, in general, we prefer
488 registers listed in CALL_USED_REGISTERS, keeping the others
489 available for storage of persistent values. */
491 #define REG_ALLOC_ORDER \
492 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
493 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
494 REG_A0, REG_A1, \
495 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
496 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
497 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
498 REG_ASTAT, REG_SEQSTAT, REG_USP, \
499 REG_CC, REG_ARGP, \
500 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
501 }
503 /* Macro to conditionally modify fixed_regs/call_used_regs. */
504 #define CONDITIONAL_REGISTER_USAGE \
505 { \
506 conditional_register_usage(); \
507 if (TARGET_FDPIC) \
508 call_used_regs[FDPIC_REGNO] = 1; \
509 if (!TARGET_FDPIC && flag_pic) \
510 { \
511 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
512 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
513 } \
514 }
516 /* Define the classes of registers for register constraints in the
517 machine description. Also define ranges of constants.
519 One of the classes must always be named ALL_REGS and include all hard regs.
520 If there is more than one class, another class must be named NO_REGS
521 and contain no registers.
523 The name GENERAL_REGS must be the name of a class (or an alias for
524 another name such as ALL_REGS). This is the class of registers
525 that is allowed by "g" or "r" in a register constraint.
526 Also, registers outside this class are allocated only when
527 instructions express preferences for them.
529 The classes must be numbered in nondecreasing order; that is,
530 a larger-numbered class must never be contained completely
531 in a smaller-numbered class.
533 For any two classes, it is very desirable that there be another
534 class that represents their union. */
537 enum reg_class
538 {
539 NO_REGS,
540 IREGS,
541 BREGS,
542 LREGS,
543 MREGS,
544 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
545 DAGREGS,
546 EVEN_AREGS,
547 ODD_AREGS,
548 AREGS,
549 CCREGS,
550 EVEN_DREGS,
551 ODD_DREGS,
552 D0REGS,
553 D1REGS,
554 D2REGS,
555 D3REGS,
556 D4REGS,
557 D5REGS,
558 D6REGS,
559 D7REGS,
560 DREGS,
561 P0REGS,
562 FDPIC_REGS,
563 FDPIC_FPTR_REGS,
564 PREGS_CLOBBERED,
565 PREGS,
566 IPREGS,
567 DPREGS,
568 MOST_REGS,
569 LT_REGS,
570 LC_REGS,
571 LB_REGS,
572 PROLOGUE_REGS,
573 NON_A_CC_REGS,
574 ALL_REGS, LIM_REG_CLASSES
575 };
577 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
579 #define GENERAL_REGS DPREGS
581 /* Give names of register classes as strings for dump file. */
583 #define REG_CLASS_NAMES \
621 /* An initializer containing the contents of the register classes, as integers
622 which are bit masks. The Nth integer specifies the contents of class N.
623 The way the integer MASK is interpreted is that register R is in the class
624 if `MASK & (1 << R)' is 1.
626 When the machine has more than 32 registers, an integer does not suffice.
627 Then the integers are replaced by sub-initializers, braced groupings
628 containing several integers. Each sub-initializer must be suitable as an
629 initializer for the type `HARD_REG_SET' which is defined in
630 `hard-reg-set.h'. */
632 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
633 MOST_REGS as the union of DPREGS and DAGREGS. */
635 #define REG_CLASS_CONTENTS \
674 #define IREG_POSSIBLE_P(OUTER) \
675 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
676 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
677 || (OUTER) == MEM || (OUTER) == ADDRESS)
679 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \
680 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
682 #define INDEX_REG_CLASS PREGS
684 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
685 (P_REGNO_P (X) || (X) == REG_ARGP \
686 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
687 && I_REGNO_P (X)))
689 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
690 ((X) >= FIRST_PSEUDO_REGISTER \
691 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
693 #ifdef REG_OK_STRICT
694 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
695 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
696 #else
697 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
698 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
699 #endif
701 #define REGNO_OK_FOR_INDEX_P(X) 0
703 /* The same information, inverted:
704 Return the class number of the smallest class containing
705 reg number REGNO. This could be a conditional expression
706 or could index an array. */
708 #define REGNO_REG_CLASS(REGNO) \
709 ((REGNO) == REG_R0 ? D0REGS \
710 : (REGNO) == REG_R1 ? D1REGS \
711 : (REGNO) == REG_R2 ? D2REGS \
712 : (REGNO) == REG_R3 ? D3REGS \
713 : (REGNO) == REG_R4 ? D4REGS \
714 : (REGNO) == REG_R5 ? D5REGS \
715 : (REGNO) == REG_R6 ? D6REGS \
716 : (REGNO) == REG_R7 ? D7REGS \
717 : (REGNO) == REG_P0 ? P0REGS \
718 : (REGNO) < REG_I0 ? PREGS \
719 : (REGNO) == REG_ARGP ? PREGS \
720 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
721 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
722 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
723 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
724 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
725 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
726 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
727 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
728 : (REGNO) == REG_CC ? CCREGS \
729 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
730 : NO_REGS)
732 /* The following macro defines cover classes for Integrated Register
733 Allocator. Cover classes is a set of non-intersected register
734 classes covering all hard registers used for register allocation
735 purpose. Any move between two registers of a cover class should be
736 cheaper than load or store of the registers. The macro value is
737 array of register classes with LIM_REG_CLASSES used as the end
738 marker. */
740 #define IRA_COVER_CLASSES \
741 { \
742 MOST_REGS, AREGS, CCREGS, LIM_REG_CLASSES \
743 }
745 /* When defined, the compiler allows registers explicitly used in the
746 rtl to be used as spill registers but prevents the compiler from
747 extending the lifetime of these registers. */
748 #define SMALL_REGISTER_CLASSES 1
750 #define CLASS_LIKELY_SPILLED_P(CLASS) \
751 ((CLASS) == PREGS_CLOBBERED \
752 || (CLASS) == PROLOGUE_REGS \
753 || (CLASS) == P0REGS \
754 || (CLASS) == D0REGS \
755 || (CLASS) == D1REGS \
756 || (CLASS) == D2REGS \
757 || (CLASS) == CCREGS)
759 /* Do not allow to store a value in REG_CC for any mode */
760 /* Do not allow to store value in pregs if mode is not SI*/
761 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
763 /* Return the maximum number of consecutive registers
764 needed to represent mode MODE in a register of class CLASS. */
765 #define CLASS_MAX_NREGS(CLASS, MODE) \
766 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
767 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
769 #define HARD_REGNO_NREGS(REGNO, MODE) \
770 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
771 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
772 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
774 /* A C expression that is nonzero if hard register TO can be
775 considered for use as a rename register for FROM register */
776 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
778 /* A C expression that is nonzero if it is desirable to choose
779 register allocation so as to avoid move instructions between a
780 value of mode MODE1 and a value of mode MODE2.
782 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
783 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
784 MODE2)' must be zero. */
785 #define MODES_TIEABLE_P(MODE1, MODE2) \
786 ((MODE1) == (MODE2) \
787 || ((GET_MODE_CLASS (MODE1) == MODE_INT \
788 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \
789 && (GET_MODE_CLASS (MODE2) == MODE_INT \
790 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \
791 && (MODE1) != BImode && (MODE2) != BImode \
792 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
793 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
795 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
796 A C expression that places additional restrictions on the register
797 class to use when it is necessary to copy value X into a register
798 in class CLASS. The value is a register class; perhaps CLASS, or
799 perhaps another, smaller class. */
800 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
801 (GET_CODE (X) == POST_INC \
802 || GET_CODE (X) == POST_DEC \
803 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
805 /* Function Calling Conventions. */
807 /* The type of the current function; normal functions are of type
808 SUBROUTINE. */
813 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
815 /* Flags for the call/call_value rtl operations set up by function_arg */
827 /* Define where to put the arguments to a function.
828 Value is zero to push the argument on the stack,
829 or a hard register in which to store the argument.
831 MODE is the argument's machine mode.
832 TYPE is the data type of the argument (as a tree).
833 This is null for libcalls where that information may
834 not be available.
835 CUM is a variable of type CUMULATIVE_ARGS which gives info about
836 the preceding args and about the function being called.
837 NAMED is nonzero if this argument is a named parameter
838 (otherwise it is an extra parameter matching an ellipsis). */
840 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
841 (function_arg (&CUM, MODE, TYPE, NAMED))
843 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
846 /* Initialize a variable CUM of type CUMULATIVE_ARGS
847 for a call to a function whose data type is FNTYPE.
848 For a library call, FNTYPE is 0. */
849 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
850 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
852 /* Update the data in CUM to advance over an argument
853 of mode MODE and data type TYPE.
854 (TYPE is null for libcalls where that information may not be available.) */
855 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
856 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
858 #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0
860 /* Define how to find the value returned by a function.
861 VALTYPE is the data type of the value (as a tree).
862 If the precise function being called is known, FUNC is its FUNCTION_DECL;
863 otherwise, FUNC is 0.
864 */
866 #define VALUE_REGNO(MODE) (REG_R0)
868 #define FUNCTION_VALUE(VALTYPE, FUNC) \
869 gen_rtx_REG (TYPE_MODE (VALTYPE), \
870 VALUE_REGNO(TYPE_MODE(VALTYPE)))
872 /* Define how to find the value returned by a library function
873 assuming the value has mode MODE. */
875 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
877 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
879 #define DEFAULT_PCC_STRUCT_RETURN 0
881 /* Before the prologue, the return address is in the RETS register. */
882 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
884 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
886 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
888 /* Call instructions don't modify the stack pointer on the Blackfin. */
889 #define INCOMING_FRAME_SP_OFFSET 0
891 /* Describe how we implement __builtin_eh_return. */
892 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
893 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
894 #define EH_RETURN_HANDLER_RTX \
895 gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
897 /* Addressing Modes */
899 /* Recognize any constant value that is a valid address. */
900 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
902 /* Nonzero if the constant value X is a legitimate general operand.
903 symbol_ref are not legitimate and will be put into constant pool.
904 See force_const_mem().
905 If -mno-pool, all constants are legitimate.
906 */
907 #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X)
909 /* A number, the maximum number of registers that can appear in a
910 valid memory address. Note that it is up to you to specify a
911 value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS'
912 would ever accept. */
913 #define MAX_REGS_PER_ADDRESS 1
915 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
916 that is a valid memory address for an instruction.
917 The MODE argument is the machine mode for the MEM expression
918 that wants to use this address.
920 Blackfin addressing modes are as follows:
922 [preg]
923 [preg + imm16]
925 B [ Preg + uimm15 ]
926 W [ Preg + uimm16m2 ]
927 [ Preg + uimm17m4 ]
929 [preg++]
930 [preg--]
931 [--sp]
932 */
934 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
935 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
937 #ifdef REG_OK_STRICT
938 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
939 do { \
940 if (bfin_legitimate_address_p (MODE, X, 1)) \
941 goto WIN; \
942 } while (0);
943 #else
944 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
945 do { \
946 if (bfin_legitimate_address_p (MODE, X, 0)) \
947 goto WIN; \
948 } while (0);
949 #endif
951 /* Try machine-dependent ways of modifying an illegitimate address
952 to be legitimate. If we find one, return the new, valid address.
953 This macro is used in only one place: `memory_address' in explow.c.
955 OLDX is the address as it was before break_out_memory_refs was called.
956 In some cases it is useful to look at this to decide what needs to be done.
958 MODE and WIN are passed so that this macro can use
959 GO_IF_LEGITIMATE_ADDRESS.
961 It is always safe for this macro to do nothing. It exists to recognize
962 opportunities to optimize the output.
963 */
964 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
965 do { \
966 rtx _q = legitimize_address(X, OLDX, MODE); \
967 if (_q) { X = _q; goto WIN; } \
968 } while (0)
970 #define HAVE_POST_INCREMENT 1
971 #define HAVE_POST_DECREMENT 1
972 #define HAVE_PRE_DECREMENT 1
974 /* `LEGITIMATE_PIC_OPERAND_P (X)'
975 A C expression that is nonzero if X is a legitimate immediate
976 operand on the target machine when generating position independent
977 code. You can assume that X satisfies `CONSTANT_P', so you need
978 not check this. You can also assume FLAG_PIC is true, so you need
979 not check it either. You need not define this macro if all
980 constants (including `SYMBOL_REF') can be immediate operands when
981 generating position independent code. */
982 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
984 #define SYMBOLIC_CONST(X) \
985 (GET_CODE (X) == SYMBOL_REF \
986 || GET_CODE (X) == LABEL_REF \
987 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
989 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
991 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
992 is done just by pretending it is already truncated. */
993 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
995 /* Max number of bytes we can move from memory to memory
996 in one reasonably fast instruction. */
997 #define MOVE_MAX UNITS_PER_WORD
999 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1000 move-instruction pairs, we will do a movmem or libcall instead. */
1002 #define MOVE_RATIO(speed) 5
1004 /* STORAGE LAYOUT: target machine storage layout
1005 Define this macro as a C expression which is nonzero if accessing
1006 less than a word of memory (i.e. a `char' or a `short') is no
1007 faster than accessing a word of memory, i.e., if such access
1008 require more than one instruction or if there is no difference in
1009 cost between byte and (aligned) word loads.
1011 When this macro is not defined, the compiler will access a field by
1012 finding the smallest containing object; when it is defined, a
1013 fullword load will be used if alignment permits. Unless bytes
1014 accesses are faster than word accesses, using word accesses is
1015 preferable since it may eliminate subsequent memory access if
1016 subsequent accesses occur to other fields in the same word of the
1017 structure, but to different bytes. */
1018 #define SLOW_BYTE_ACCESS 0
1019 #define SLOW_SHORT_ACCESS 0
1021 /* Define this if most significant bit is lowest numbered
1022 in instructions that operate on numbered bit-fields. */
1023 #define BITS_BIG_ENDIAN 0
1025 /* Define this if most significant byte of a word is the lowest numbered.
1026 We can't access bytes but if we could we would in the Big Endian order. */
1027 #define BYTES_BIG_ENDIAN 0
1029 /* Define this if most significant word of a multiword number is numbered. */
1030 #define WORDS_BIG_ENDIAN 0
1032 /* number of bits in an addressable storage unit */
1033 #define BITS_PER_UNIT 8
1035 /* Width in bits of a "word", which is the contents of a machine register.
1036 Note that this is not necessarily the width of data type `int';
1037 if using 16-bit ints on a 68000, this would still be 32.
1038 But on a machine with 16-bit registers, this would be 16. */
1039 #define BITS_PER_WORD 32
1041 /* Width of a word, in units (bytes). */
1042 #define UNITS_PER_WORD 4
1044 /* Width in bits of a pointer.
1045 See also the macro `Pmode1' defined below. */
1046 #define POINTER_SIZE 32
1048 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1049 #define POINTER_BOUNDARY 32
1051 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1052 #define PARM_BOUNDARY 32
1054 /* Boundary (in *bits*) on which stack pointer should be aligned. */
1055 #define STACK_BOUNDARY 32
1057 /* Allocation boundary (in *bits*) for the code of a function. */
1058 #define FUNCTION_BOUNDARY 32
1060 /* Alignment of field after `int : 0' in a structure. */
1061 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
1063 /* No data type wants to be aligned rounder than this. */
1064 #define BIGGEST_ALIGNMENT 32
1066 /* Define this if move instructions will actually fail to work
1067 when given unaligned data. */
1068 #define STRICT_ALIGNMENT 1
1070 /* (shell-command "rm c-decl.o stor-layout.o")
1071 * never define PCC_BITFIELD_TYPE_MATTERS
1072 * really cause some alignment problem
1073 */
1075 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
1076 BITS_PER_UNIT)
1078 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
1079 BITS_PER_UNIT)
1082 /* what is the 'type' of size_t */
1085 /* Define this as 1 if `char' should by default be signed; else as 0. */
1086 #define DEFAULT_SIGNED_CHAR 1
1087 #define FLOAT_TYPE_SIZE BITS_PER_WORD
1088 #define SHORT_TYPE_SIZE 16
1089 #define CHAR_TYPE_SIZE 8
1090 #define INT_TYPE_SIZE 32
1091 #define LONG_TYPE_SIZE 32
1092 #define LONG_LONG_TYPE_SIZE 64
1094 /* Note: Fix this to depend on target switch. -- lev */
1096 /* Note: Try to implement double and force long double. -- tonyko
1097 * #define __DOUBLES_ARE_FLOATS__
1098 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
1099 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
1100 * #define DOUBLES_ARE_FLOATS 1
1101 */
1103 #define DOUBLE_TYPE_SIZE 64
1104 #define LONG_DOUBLE_TYPE_SIZE 64
1106 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
1107 A macro to update M and UNSIGNEDP when an object whose type is
1108 TYPE and which has the specified mode and signedness is to be
1109 stored in a register. This macro is only called when TYPE is a
1110 scalar type.
1112 On most RISC machines, which only have operations that operate on
1113 a full register, define this macro to set M to `word_mode' if M is
1114 an integer mode narrower than `BITS_PER_WORD'. In most cases,
1115 only integer modes should be widened because wider-precision
1116 floating-point operations are usually more expensive than their
1117 narrower counterparts.
1119 For most machines, the macro definition does not change UNSIGNEDP.
1120 However, some machines, have instructions that preferentially
1121 handle either signed or unsigned quantities of certain modes. For
1122 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
1123 instructions sign-extend the result to 64 bits. On such machines,
1124 set UNSIGNEDP according to which kind of extension is more
1125 efficient.
1127 Do not define this macro if it would never modify M.*/
1129 #define BFIN_PROMOTE_MODE_P(MODE) \
1130 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
1131 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
1133 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1134 if (BFIN_PROMOTE_MODE_P(MODE)) \
1135 { \
1136 if (MODE == QImode) \
1137 UNSIGNEDP = 1; \
1138 else if (MODE == HImode) \
1139 UNSIGNEDP = 0; \
1140 (MODE) = SImode; \
1141 }
1143 /* Describing Relative Costs of Operations */
1145 /* Do not put function addr into constant pool */
1146 #define NO_FUNCTION_CSE 1
1148 /* A C expression for the cost of moving data from a register in class FROM to
1149 one in class TO. The classes are expressed using the enumeration values
1150 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1151 interpreted relative to that.
1153 It is not required that the cost always equal 2 when FROM is the same as TO;
1154 on some machines it is expensive to move between registers if they are not
1155 general registers. */
1157 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1158 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
1160 /* A C expression for the cost of moving data of mode M between a
1161 register and memory. A value of 2 is the default; this cost is
1162 relative to those in `REGISTER_MOVE_COST'.
1164 If moving between registers and memory is more expensive than
1165 between two registers, you should define this macro to express the
1166 relative cost. */
1168 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1169 bfin_memory_move_cost ((MODE), (CLASS), (IN))
1171 /* Specify the machine mode that this machine uses
1172 for the index in the tablejump instruction. */
1173 #define CASE_VECTOR_MODE SImode
1175 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
1177 /* Define if operations between registers always perform the operation
1178 on the full register even if a narrower mode is specified.
1179 #define WORD_REGISTER_OPERATIONS
1180 */
1182 /* Evaluates to true if A and B are mac flags that can be used
1183 together in a single multiply insn. That is the case if they are
1184 both the same flag not involving M, or if one is a combination of
1185 the other with M. */
1186 #define MACFLAGS_MATCH_P(A, B) \
1187 ((A) == (B) \
1188 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
1189 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
1190 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
1191 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
1193 /* Switch into a generic section. */
1194 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
1196 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
1197 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1200 CODE_DIR,
1201 DATA_DIR,
1202 LAST_SECT_NM
1206 LONG_CONST_DIR,
1207 SHORT_CONST_DIR,
1208 BYTE_CONST_DIR,
1209 SPACE_DIR,
1210 INIT_DIR,
1211 LAST_DIR_NM
1214 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
1224 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1226 assemble_name (FILE, NAME); \
1229 } while (0)
1231 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1232 do { \
1234 assemble_name (FILE, NAME); \
1238 ASM_OUTPUT_LABEL(FILE, NAME); \
1239 } while (0)
1241 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1242 do { assemble_name (FILE, NAME); \
1244 } while (0)
1246 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1248 } while (0)
1250 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1251 do { char __buf[256]; \
1254 assemble_name (FILE, __buf); \
1257 } while (0)
1259 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1260 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1262 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1263 do { \
1264 char __buf[256]; \
1267 assemble_name (FILE, __buf); \
1270 assemble_name (FILE, __buf); \
1273 } while (0)
1275 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1276 do { \
1277 if ((LOG) != 0) \
1279 } while (0)
1281 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1282 do { \
1283 asm_output_skip (FILE, SIZE); \
1284 } while (0)
1286 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1287 do { \
1288 switch_to_section (data_section); \
1289 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1290 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1291 ASM_OUTPUT_LABEL (FILE, NAME); \
1293 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1294 } while (0)
1296 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1297 do { \
1298 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1299 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1303 #define FUNCTION_PROFILER(FILE, LABELNO) \
1304 do { \
1306 } while(0)
1308 #undef NO_PROFILE_COUNTERS
1309 #define NO_PROFILE_COUNTERS 1
1317 /* This works for GAS and some other assemblers. */
1320 /* DBX register number for a given compiler register number */
1321 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)