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2006-03-27 Andrew Stubbs <andrew.stubbs@st.com>
[official-gcc.git] / gcc / config / sh / crt1.asm
blobc110fa0742716c8ecd143d6f20b5f0f494d46ecb
1 /* Copyright (C) 2000, 2001, 2003, 2004, 2005 Free Software Foundation, Inc.
2 This file was pretty much copied from newlib.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the
8 Free Software Foundation; either version 2, or (at your option) any
9 later version.
10
11 In addition to the permissions in the GNU General Public License, the
12 Free Software Foundation gives you unlimited permission to link the
13 compiled version of this file into combinations with other programs,
14 and to distribute those combinations without any restriction coming
15 from the use of this file. (The General Public License restrictions
16 do apply in other respects; for example, they cover modification of
17 the file, and distribution when not linked into a combine
18 executable.)
19
20 GCC is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; see the file COPYING. If not, write to
27 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
28 Boston, MA 02110-1301, USA. */
29
30 #ifdef MMU_SUPPORT
31 /* Section used for exception/timer interrupt stack area */
32 .section .data.vbr.stack,"aw"
33 .align 4
34 .global __ST_VBR
35 __ST_VBR:
36 .zero 1024 * 2 /* ; 2k for VBR handlers */
37 /* Label at the highest stack address where the stack grows from */
38 __timer_stack:
39 #endif /* MMU_SUPPORT */
40
41 /* ;----------------------------------------
42 Normal newlib crt1.asm */
43
44 #ifdef __SH5__
45 .section .data,"aw"
46 .global ___data
47 ___data:
48
49 .section .rodata,"a"
50 .global ___rodata
51 ___rodata:
52
53 #define ICCR_BASE 0x01600000
54 #define OCCR_BASE 0x01e00000
55 #define MMUIR_BASE 0x00000000
56 #define MMUDR_BASE 0x00800000
57
58 #define PTE_ENABLED 1
59 #define PTE_DISABLED 0
60
61 #define PTE_SHARED (1 << 1)
62 #define PTE_NOT_SHARED 0
63
64 #define PTE_CB_UNCACHEABLE 0
65 #define PTE_CB_DEVICE 1
66 #define PTE_CB_CACHEABLE_WB 2
67 #define PTE_CB_CACHEABLE_WT 3
68
69 #define PTE_SZ_4KB (0 << 3)
70 #define PTE_SZ_64KB (1 << 3)
71 #define PTE_SZ_1MB (2 << 3)
72 #define PTE_SZ_512MB (3 << 3)
73
74 #define PTE_PRR (1 << 6)
75 #define PTE_PRX (1 << 7)
76 #define PTE_PRW (1 << 8)
77 #define PTE_PRU (1 << 9)
78
79 #define SR_MMU_BIT 31
80 #define SR_BL_BIT 28
81
82 #define ALIGN_4KB (0xfff)
83 #define ALIGN_1MB (0xfffff)
84 #define ALIGN_512MB (0x1fffffff)
85
86 #define DYNACON_BASE 0x0f000000
87 #define DM_CB_DLINK_BASE 0x0c000000
88 #define DM_DB_DLINK_BASE 0x0b000000
89
90 #define FEMI_AREA_0 0x00000000
91 #define FEMI_AREA_1 0x04000000
92 #define FEMI_AREA_2 0x05000000
93 #define FEMI_AREA_3 0x06000000
94 #define FEMI_AREA_4 0x07000000
95 #define FEMI_CB 0x08000000
96
97 #define EMI_BASE 0X80000000
98
99 #define DMA_BASE 0X0e000000
100
101 #define CPU_BASE 0X0d000000
102
103 #define PERIPH_BASE 0X09000000
104 #define DMAC_BASE 0x0e000000
105 #define INTC_BASE 0x0a000000
106 #define CPRC_BASE 0x0a010000
107 #define TMU_BASE 0x0a020000
108 #define SCIF_BASE 0x0a030000
109 #define RTC_BASE 0x0a040000
110
111
112
113 #define LOAD_CONST32(val, reg) \
114 movi ((val) >> 16) & 65535, reg; \
115 shori (val) & 65535, reg
116
117 #define LOAD_PTEH_VAL(sym, align, bits, scratch_reg, reg) \
118 LOAD_ADDR (sym, reg); \
119 LOAD_CONST32 ((align), scratch_reg); \
120 andc reg, scratch_reg, reg; \
121 LOAD_CONST32 ((bits), scratch_reg); \
122 or reg, scratch_reg, reg
123
124 #define LOAD_PTEL_VAL(sym, align, bits, scratch_reg, reg) \
125 LOAD_ADDR (sym, reg); \
126 LOAD_CONST32 ((align), scratch_reg); \
127 andc reg, scratch_reg, reg; \
128 LOAD_CONST32 ((bits), scratch_reg); \
129 or reg, scratch_reg, reg
130
131 #define SET_PTE(pte_addr_reg, pteh_val_reg, ptel_val_reg) \
132 putcfg pte_addr_reg, 0, r63; \
133 putcfg pte_addr_reg, 1, ptel_val_reg; \
134 putcfg pte_addr_reg, 0, pteh_val_reg
135
136 #if __SH5__ == 64
137 .section .text,"ax"
138 #define LOAD_ADDR(sym, reg) \
139 movi (sym >> 48) & 65535, reg; \
140 shori (sym >> 32) & 65535, reg; \
141 shori (sym >> 16) & 65535, reg; \
142 shori sym & 65535, reg
143 #else
144 .mode SHmedia
145 .section .text..SHmedia32,"ax"
146 #define LOAD_ADDR(sym, reg) \
147 movi (sym >> 16) & 65535, reg; \
148 shori sym & 65535, reg
149 #endif
150 .global start
151 start:
152 LOAD_ADDR (_stack, r15)
153
154 #ifdef MMU_SUPPORT
155 ! Set up the VM using the MMU and caches
156
157 ! .vm_ep is first instruction to execute
158 ! after VM initialization
159 pt/l .vm_ep, tr1
160
161 ! Configure instruction cache (ICCR)
162 movi 3, r2
163 movi 0, r3
164 LOAD_ADDR (ICCR_BASE, r1)
165 putcfg r1, 0, r2
166 putcfg r1, 1, r3
167
168 ! movi 7, r2 ! write through
169 ! Configure operand cache (OCCR)
170 LOAD_ADDR (OCCR_BASE, r1)
171 putcfg r1, 0, r2
172 putcfg r1, 1, r3
173
174 ! Disable all PTE translations
175 LOAD_ADDR (MMUIR_BASE, r1)
176 LOAD_ADDR (MMUDR_BASE, r2)
177 movi 64, r3
178 pt/l .disable_ptes_loop, tr0
179 .disable_ptes_loop:
180 putcfg r1, 0, r63
181 putcfg r2, 0, r63
182 addi r1, 16, r1
183 addi r2, 16, r2
184 addi r3, -1, r3
185 bgt r3, r63, tr0
186
187 LOAD_ADDR (MMUIR_BASE, r1)
188
189 ! FEMI instruction mappings
190 ! Area 0 - 1Mb cacheable at 0x00000000
191 ! Area 1 - None
192 ! Area 2 - 1Mb cacheable at 0x05000000
193 ! - 1Mb cacheable at 0x05100000
194 ! Area 3 - None
195 ! Area 4 - None
196
197 ! Map a 1Mb page for instructions at 0x00000000
198 LOAD_PTEH_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
199 LOAD_PTEL_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRX | PTE_PRU, r25, r3)
200 SET_PTE (r1, r2, r3)
201
202 ! Map a 1Mb page for instructions at 0x05000000
203 addi r1, 16, r1
204 LOAD_PTEH_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
205 LOAD_PTEL_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRX | PTE_PRU, r25, r3)
206 SET_PTE (r1, r2, r3)
207
208 ! Map a 1Mb page for instructions at 0x05100000
209 addi r1, 16, r1
210 LOAD_PTEH_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
211 LOAD_PTEL_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRX | PTE_PRU, r25, r3)
212 SET_PTE (r1, r2, r3)
213
214 ! Map a 512M page for instructions at EMI base
215 addi r1, 16, r1
216 LOAD_PTEH_VAL (EMI_BASE, ALIGN_512MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
217 LOAD_PTEL_VAL (EMI_BASE, ALIGN_512MB, PTE_CB_CACHEABLE_WB | PTE_SZ_512MB | PTE_PRX | PTE_PRU, r25, r3)
218 SET_PTE (r1, r2, r3)
219
220 ! Map a 4K page for instructions at DM_DB_DLINK_BASE
221 addi r1, 16, r1
222 LOAD_PTEH_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
223 LOAD_PTEL_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_CB_CACHEABLE_WB | PTE_SZ_4KB | PTE_PRX | PTE_PRU, r25, r3)
224 SET_PTE (r1, r2, r3)
225
226 LOAD_ADDR (MMUDR_BASE, r1)
227
228 ! FEMI data mappings
229 ! Area 0 - 1Mb cacheable at 0x00000000
230 ! Area 1 - 1Mb device at 0x04000000
231 ! Area 2 - 1Mb cacheable at 0x05000000
232 ! - 1Mb cacheable at 0x05100000
233 ! Area 3 - None
234 ! Area 4 - None
235 ! CB - 1Mb device at 0x08000000
236
237 ! Map a 1Mb page for data at 0x00000000
238 LOAD_PTEH_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
239 LOAD_PTEL_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
240 SET_PTE (r1, r2, r3)
241
242 ! Map a 1Mb page for data at 0x04000000
243 addi r1, 16, r1
244 LOAD_PTEH_VAL (FEMI_AREA_1, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
245 LOAD_PTEL_VAL (FEMI_AREA_1, ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
246 SET_PTE (r1, r2, r3)
247
248 ! Map a 1Mb page for data at 0x05000000
249 addi r1, 16, r1
250 LOAD_PTEH_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
251 LOAD_PTEL_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
252 SET_PTE (r1, r2, r3)
253
254 ! Map a 1Mb page for data at 0x05100000
255 addi r1, 16, r1
256 LOAD_PTEH_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
257 LOAD_PTEL_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
258 SET_PTE (r1, r2, r3)
259
260 ! Map a 4K page for registers at 0x08000000
261 addi r1, 16, r1
262 LOAD_PTEH_VAL (FEMI_CB, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
263 LOAD_PTEL_VAL (FEMI_CB, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
264 SET_PTE (r1, r2, r3)
265
266 ! Map a 512M page for data at EMI
267 addi r1, 16, r1
268 LOAD_PTEH_VAL (EMI_BASE, ALIGN_512MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
269 LOAD_PTEL_VAL (EMI_BASE, ALIGN_512MB, PTE_CB_CACHEABLE_WB | PTE_SZ_512MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
270 SET_PTE (r1, r2, r3)
271
272 ! Map a 4K page for DYNACON at DYNACON_BASE
273 addi r1, 16, r1
274 LOAD_PTEH_VAL (DYNACON_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
275 LOAD_PTEL_VAL (DYNACON_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
276 SET_PTE (r1, r2, r3)
277
278 ! Map a 4K page for instructions at DM_DB_DLINK_BASE
279 addi r1, 16, r1
280 LOAD_PTEH_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
281 LOAD_PTEL_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_CB_CACHEABLE_WB | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
282 SET_PTE (r1, r2, r3)
283
284 ! Map a 4K page for data at DM_DB_DLINK_BASE+0x1000
285 addi r1, 16, r1
286 LOAD_PTEH_VAL ((DM_DB_DLINK_BASE+0x1000), ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
287 LOAD_PTEL_VAL ((DM_DB_DLINK_BASE+0x1000), ALIGN_4KB, PTE_CB_UNCACHEABLE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
288 SET_PTE (r1, r2, r3)
289
290 ! Map a 4K page for stack DM_DB_DLINK_BASE+0x2000
291 addi r1, 16, r1
292 LOAD_PTEH_VAL ((DM_DB_DLINK_BASE+0x2000), ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
293 LOAD_PTEL_VAL ((DM_DB_DLINK_BASE+0x2000), ALIGN_4KB, PTE_CB_CACHEABLE_WB | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
294 SET_PTE (r1, r2, r3)
295
296 ! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK
297 ! 0x0c000000 - 0x0c0fffff
298 addi r1, 16, r1
299 LOAD_PTEH_VAL (DM_CB_DLINK_BASE, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
300 LOAD_PTEL_VAL (DM_CB_DLINK_BASE, ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
301 SET_PTE (r1, r2, r3)
302
303 ! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK
304 ! 0x0c100000 - 0x0c1fffff
305 addi r1, 16, r1
306 LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
307 LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x100000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
308 SET_PTE (r1, r2, r3)
309
310 ! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK
311 ! 0x0c200000 - 0x0c2fffff
312 addi r1, 16, r1
313 LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x200000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
314 LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x200000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
315 SET_PTE (r1, r2, r3)
316
317 ! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK
318 ! 0x0c400000 - 0x0c4fffff
319 addi r1, 16, r1
320 LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x400000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
321 LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x400000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
322 SET_PTE (r1, r2, r3)
323
324 ! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK
325 ! 0x0c800000 - 0x0c8fffff
326 addi r1, 16, r1
327 LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x800000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
328 LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x800000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
329 SET_PTE (r1, r2, r3)
330
331 ! Map a 4K page for DMA control registers
332 addi r1, 16, r1
333 LOAD_PTEH_VAL (DMA_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
334 LOAD_PTEL_VAL (DMA_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
335 SET_PTE (r1, r2, r3)
336
337 ! Map lots of 4K pages for peripherals
338
339 ! /* peripheral */
340 addi r1, 16, r1
341 LOAD_PTEH_VAL (PERIPH_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
342 LOAD_PTEL_VAL (PERIPH_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
343 SET_PTE (r1, r2, r3)
344 ! /* dmac */
345 addi r1, 16, r1
346 LOAD_PTEH_VAL (DMAC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
347 LOAD_PTEL_VAL (DMAC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
348 SET_PTE (r1, r2, r3)
349 ! /* intc */
350 addi r1, 16, r1
351 LOAD_PTEH_VAL (INTC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
352 LOAD_PTEL_VAL (INTC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
353 SET_PTE (r1, r2, r3)
354 ! /* rtc */
355 addi r1, 16, r1
356 LOAD_PTEH_VAL (RTC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
357 LOAD_PTEL_VAL (RTC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
358 SET_PTE (r1, r2, r3)
359 ! /* dmac */
360 addi r1, 16, r1
361 LOAD_PTEH_VAL (TMU_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
362 LOAD_PTEL_VAL (TMU_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
363 SET_PTE (r1, r2, r3)
364 ! /* scif */
365 addi r1, 16, r1
366 LOAD_PTEH_VAL (SCIF_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
367 LOAD_PTEL_VAL (SCIF_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
368 SET_PTE (r1, r2, r3)
369 ! /* cprc */
370 addi r1, 16, r1
371 LOAD_PTEH_VAL (CPRC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
372 LOAD_PTEL_VAL (CPRC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
373 SET_PTE (r1, r2, r3)
374
375 ! Map CPU WPC registers
376 addi r1, 16, r1
377 LOAD_PTEH_VAL (CPU_BASE, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
378 LOAD_PTEL_VAL (CPU_BASE, ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
379 SET_PTE (r1, r2, r3)
380 addi r1, 16, r1
381
382 LOAD_PTEH_VAL ((CPU_BASE+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
383 LOAD_PTEL_VAL ((CPU_BASE+0x100000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
384 SET_PTE (r1, r2, r3)
385
386 addi r1, 16, r1
387 LOAD_PTEH_VAL ((CPU_BASE+0x200000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
388 LOAD_PTEL_VAL ((CPU_BASE+0x200000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
389 SET_PTE (r1, r2, r3)
390
391 addi r1, 16, r1
392 LOAD_PTEH_VAL ((CPU_BASE+0x400000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
393 LOAD_PTEL_VAL ((CPU_BASE+0x400000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
394 SET_PTE (r1, r2, r3)
395
396 ! Switch over to virtual addressing and enabled cache
397 getcon sr, r1
398 movi 1, r2
399 shlli r2, SR_BL_BIT, r2
400 or r1, r2, r1
401 putcon r1, ssr
402 getcon sr, r1
403 movi 1, r2
404 shlli r2, SR_MMU_BIT, r2
405 or r1, r2, r1
406 putcon r1, ssr
407 gettr tr1, r1
408 putcon r1, spc
409 synco
410 rte
411
412 ! VM entry point. From now on, we are in VM mode.
413 .vm_ep:
414
415 ! Install the trap handler, by seeding vbr with the
416 ! correct value, and by assigning sr.bl = 0.
417
418 LOAD_ADDR (vbr_start, r1)
419 putcon r1, vbr
420 movi ~(1<<28), r1
421 getcon sr, r2
422 and r1, r2, r2
423 putcon r2, sr
424 #endif /* MMU_SUPPORT */
425
426 pt/l .Lzero_bss_loop, tr0
427 pt/l _init, tr5
428 pt/l ___setup_argv_and_call_main, tr6
429 pt/l _exit, tr7
430
431 ! zero out bss
432 LOAD_ADDR (_edata, r0)
433 LOAD_ADDR (_end, r1)
434 .Lzero_bss_loop:
435 stx.q r0, r63, r63
436 addi r0, 8, r0
437 bgt/l r1, r0, tr0
438
439 LOAD_ADDR (___data, r26)
440 LOAD_ADDR (___rodata, r27)
441
442 #ifdef __SH_FPU_ANY__
443 getcon sr, r0
444 ! enable the FP unit, by resetting SR.FD
445 ! also zero out SR.FR, SR.SZ and SR.PR, as mandated by the ABI
446 movi 0, r1
447 shori 0xf000, r1
448 andc r0, r1, r0
449 putcon r0, sr
450 #if __SH5__ == 32
451 pt/l ___set_fpscr, tr0
452 movi 0, r4
453 blink tr0, r18
454 #endif
455 #endif
456
457 ! arrange for exit to call fini
458 pt/l _atexit, tr1
459 LOAD_ADDR (_fini, r2)
460 blink tr1, r18
461
462 ! call init
463 blink tr5, r18
464
465 ! call the mainline
466 blink tr6, r18
467
468 ! call exit
469 blink tr7, r18
470 ! We should never return from _exit but in case we do we would enter the
471 ! the following tight loop. This avoids executing any data that might follow.
472 limbo:
473 pt/l limbo, tr0
474 blink tr0, r63
475
476 #ifdef MMU_SUPPORT
477 ! All these traps are handled in the same place.
478 .balign 256
479 vbr_start:
480 pt/l handler, tr0 ! tr0 trashed.
481 blink tr0, r63
482 .balign 256
483 vbr_100:
484 pt/l handler, tr0 ! tr0 trashed.
485 blink tr0, r63
486 vbr_100_end:
487 .balign 256
488 vbr_200:
489 pt/l handler, tr0 ! tr0 trashed.
490 blink tr0, r63
491 .balign 256
492 vbr_300:
493 pt/l handler, tr0 ! tr0 trashed.
494 blink tr0, r63
495 .balign 256
496 vbr_400: ! Should be at vbr+0x400
497 handler:
498 /* If the trap handler is there call it */
499 LOAD_ADDR (__superh_trap_handler, r2)
500 pta chandler,tr2
501 beq r2, r63, tr2 /* If zero, ie not present branch around to chandler */
502 /* Now call the trap handler with as much of the context unchanged as possible.
503 Move trapping address into R18 to make it look like the trap point */
504 getcon spc, r18
505 pt/l __superh_trap_handler, tr0
506 blink tr0, r7
507 chandler:
508 getcon spc, r62
509 getcon expevt, r2
510 pt/l _exit, tr0
511 blink tr0, r63
512
513 /* Simulated trap handler */
514 .section .text..SHmedia32,"ax"
515 gcc2_compiled.:
516 .section .debug_abbrev
517 .Ldebug_abbrev0:
518 .section .text..SHmedia32
519 .Ltext0:
520 .section .debug_info
521 .Ldebug_info0:
522 .section .debug_line
523 .Ldebug_line0:
524 .section .text..SHmedia32,"ax"
525 .align 5
526 .global __superh_trap_handler
527 .type __superh_trap_handler,@function
528 __superh_trap_handler:
529 .LFB1:
530 ptabs r18, tr0
531 addi.l r15, -8, r15
532 st.l r15, 4, r14
533 addi.l r15, -8, r15
534 add.l r15, r63, r14
535 st.l r14, 0, r2
536 ptabs r7, tr0
537 addi.l r14, 8, r14
538 add.l r14, r63, r15
539 ld.l r15, 4, r14
540 addi.l r15, 8, r15
541 blink tr0, r63
542 .LFE1:
543 .Lfe1:
544 .size __superh_trap_handler,.Lfe1-__superh_trap_handler
545
546 .section .text..SHmedia32
547 .Letext0:
548
549 .section .debug_info
550 .ualong 0xa7
551 .uaword 0x2
552 .ualong .Ldebug_abbrev0
553 .byte 0x4
554 .byte 0x1
555 .ualong .Ldebug_line0
556 .ualong .Letext0
557 .ualong .Ltext0
558 .string "trap_handler.c"
559
560 .string "xxxxxxxxxxxxxxxxxxxxxxxxxxxx"
561
562 .string "GNU C 2.97-sh5-010522"
563
564 .byte 0x1
565 .byte 0x2
566 .ualong 0x9a
567 .byte 0x1
568 .string "_superh_trap_handler"
569
570 .byte 0x1
571 .byte 0x2
572 .byte 0x1
573 .ualong .LFB1
574 .ualong .LFE1
575 .byte 0x1
576 .byte 0x5e
577 .byte 0x3
578 .string "trap_reason"
579
580 .byte 0x1
581 .byte 0x1
582 .ualong 0x9a
583 .byte 0x2
584 .byte 0x91
585 .byte 0x0
586 .byte 0x0
587 .byte 0x4
588 .string "unsigned int"
589
590 .byte 0x4
591 .byte 0x7
592 .byte 0x0
593
594 .section .debug_abbrev
595 .byte 0x1
596 .byte 0x11
597 .byte 0x1
598 .byte 0x10
599 .byte 0x6
600 .byte 0x12
601 .byte 0x1
602 .byte 0x11
603 .byte 0x1
604 .byte 0x3
605 .byte 0x8
606 .byte 0x1b
607 .byte 0x8
608 .byte 0x25
609 .byte 0x8
610 .byte 0x13
611 .byte 0xb
612 .byte 0,0
613 .byte 0x2
614 .byte 0x2e
615 .byte 0x1
616 .byte 0x1
617 .byte 0x13
618 .byte 0x3f
619 .byte 0xc
620 .byte 0x3
621 .byte 0x8
622 .byte 0x3a
623 .byte 0xb
624 .byte 0x3b
625 .byte 0xb
626 .byte 0x27
627 .byte 0xc
628 .byte 0x11
629 .byte 0x1
630 .byte 0x12
631 .byte 0x1
632 .byte 0x40
633 .byte 0xa
634 .byte 0,0
635 .byte 0x3
636 .byte 0x5
637 .byte 0x0
638 .byte 0x3
639 .byte 0x8
640 .byte 0x3a
641 .byte 0xb
642 .byte 0x3b
643 .byte 0xb
644 .byte 0x49
645 .byte 0x13
646 .byte 0x2
647 .byte 0xa
648 .byte 0,0
649 .byte 0x4
650 .byte 0x24
651 .byte 0x0
652 .byte 0x3
653 .byte 0x8
654 .byte 0xb
655 .byte 0xb
656 .byte 0x3e
657 .byte 0xb
658 .byte 0,0
659 .byte 0
660
661 .section .debug_pubnames
662 .ualong 0x27
663 .uaword 0x2
664 .ualong .Ldebug_info0
665 .ualong 0xab
666 .ualong 0x5b
667 .string "_superh_trap_handler"
668
669 .ualong 0x0
670
671 .section .debug_aranges
672 .ualong 0x1c
673 .uaword 0x2
674 .ualong .Ldebug_info0
675 .byte 0x4
676 .byte 0x0
677 .uaword 0x0,0
678 .ualong .Ltext0
679 .ualong .Letext0-.Ltext0
680 .ualong 0x0
681 .ualong 0x0
682 .ident "GCC: (GNU) 2.97-sh5-010522"
683 #endif /* MMU_SUPPORT */
684 #else /* ! __SH5__ */
685
686 ! make a place to keep any previous value of the vbr register
687 ! this will only have a value if it has been set by redboot (for example)
688 .section .bss
689 old_vbr:
690 .long 0
691 #ifdef PROFILE
692 profiling_enabled:
693 .long 0
694 #endif
695
696
697 .section .text
698 .global start
699 .import ___rtos_profiler_start_timer
700 .weak ___rtos_profiler_start_timer
701 start:
702 mov.l stack_k,r15
703
704 #if defined (__SH3__) || (defined (__SH_FPU_ANY__) && ! defined (__SH2A__)) || defined (__SH4_NOFPU__)
705 #define VBR_SETUP
706 ! before zeroing the bss ...
707 ! if the vbr is already set to vbr_start then the program has been restarted
708 ! (i.e. it is not the first time the program has been run since reset)
709 ! reset the vbr to its old value before old_vbr (in bss) is wiped
710 ! this ensures that the later code does not create a circular vbr chain
711 stc vbr, r1
712 mov.l vbr_start_k, r2
713 cmp/eq r1, r2
714 bf 0f
715 ! reset the old vbr value
716 mov.l old_vbr_k, r1
717 mov.l @r1, r2
718 ldc r2, vbr
719 0:
720 #endif /* VBR_SETUP */
721
722 ! zero out bss
723 mov.l edata_k,r0
724 mov.l end_k,r1
725 mov #0,r2
726 start_l:
727 mov.l r2,@r0
728 add #4,r0
729 cmp/ge r0,r1
730 bt start_l
731
732 #if defined (__SH_FPU_ANY__)
733 mov.l set_fpscr_k, r1
734 mov #4,r4
735 jsr @r1
736 shll16 r4 ! Set DN bit (flush denormal inputs to zero)
737 lds r3,fpscr ! Switch to default precision
738 #endif /* defined (__SH_FPU_ANY__) */
739
740 #ifdef VBR_SETUP
741 ! save the existing contents of the vbr
742 ! there will only be a prior value when using something like redboot
743 ! otherwise it will be zero
744 stc vbr, r1
745 mov.l old_vbr_k, r2
746 mov.l r1, @r2
747 ! setup vbr
748 mov.l vbr_start_k, r1
749 ldc r1,vbr
750 #endif /* VBR_SETUP */
751
752 ! if an rtos is exporting a timer start fn,
753 ! then pick up an SR which does not enable ints
754 ! (the rtos will take care of this)
755 mov.l rtos_start_fn, r0
756 mov.l sr_initial_bare, r1
757 tst r0, r0
758 bt set_sr
759
760 mov.l sr_initial_rtos, r1
761
762 set_sr:
763 ! Set status register (sr)
764 ldc r1, sr
765
766 ! arrange for exit to call fini
767 mov.l atexit_k,r0
768 mov.l fini_k,r4
769 jsr @r0
770 nop
771
772 #ifdef PROFILE
773 ! arrange for exit to call _mcleanup (via stop_profiling)
774 mova stop_profiling,r0
775 mov.l atexit_k,r1
776 jsr @r1
777 mov r0, r4
778
779 ! Call profiler startup code
780 mov.l monstartup_k, r0
781 mov.l start_k, r4
782 mov.l etext_k, r5
783 jsr @r0
784 nop
785
786 ! enable profiling trap
787 ! until now any trap 33s will have been ignored
788 ! This means that all library functions called before this point
789 ! (directly or indirectly) may have the profiling trap at the start.
790 ! Therefore, only mcount itself may not have the extra header.
791 mov.l profiling_enabled_k2, r0
792 mov #1, r1
793 mov.l r1, @r0
794 #endif /* PROFILE */
795
796 ! call init
797 mov.l init_k,r0
798 jsr @r0
799 nop
800
801 ! call the mainline
802 mov.l main_k,r0
803 jsr @r0
804 nop
805
806 ! call exit
807 mov r0,r4
808 mov.l exit_k,r0
809 jsr @r0
810 nop
811
812 .balign 4
813 #ifdef PROFILE
814 stop_profiling:
815 # stop mcount counting
816 mov.l profiling_enabled_k2, r0
817 mov #0, r1
818 mov.l r1, @r0
819
820 # call mcleanup
821 mov.l mcleanup_k, r0
822 jmp @r0
823 nop
824
825 .balign 4
826 mcleanup_k:
827 .long __mcleanup
828 monstartup_k:
829 .long ___monstartup
830 profiling_enabled_k2:
831 .long profiling_enabled
832 start_k:
833 .long _start
834 etext_k:
835 .long __etext
836 #endif /* PROFILE */
837
838 .align 2
839 #if defined (__SH_FPU_ANY__)
840 set_fpscr_k:
841 .long ___set_fpscr
842 #endif /* defined (__SH_FPU_ANY__) */
843
844 stack_k:
845 .long _stack
846 edata_k:
847 .long _edata
848 end_k:
849 .long _end
850 main_k:
851 .long ___setup_argv_and_call_main
852 exit_k:
853 .long _exit
854 atexit_k:
855 .long _atexit
856 init_k:
857 .long _init
858 fini_k:
859 .long _fini
860 #ifdef VBR_SETUP
861 old_vbr_k:
862 .long old_vbr
863 vbr_start_k:
864 .long vbr_start
865 #endif /* VBR_SETUP */
866
867 sr_initial_rtos:
868 ! Privileged mode RB 1 BL 0. Keep BL 0 to allow default trap handlers to work.
869 ! Whether profiling or not, keep interrupts masked,
870 ! the RTOS will enable these if required.
871 .long 0x600000f1
872
873 rtos_start_fn:
874 .long ___rtos_profiler_start_timer
875
876 #ifdef PROFILE
877 sr_initial_bare:
878 ! Privileged mode RB 1 BL 0. Keep BL 0 to allow default trap handlers to work.
879 ! For bare machine, we need to enable interrupts to get profiling working
880 .long 0x60000001
881 #else
882
883 sr_initial_bare:
884 ! Privileged mode RB 1 BL 0. Keep BL 0 to allow default trap handlers to work.
885 ! Keep interrupts disabled - the application will enable as required.
886 .long 0x600000f1
887 #endif
888
889 ! supplied for backward compatibility only, in case of linking
890 ! code whose main() was compiled with an older version of GCC.
891 .global ___main
892 ___main:
893 rts
894 nop
895 #ifdef VBR_SETUP
896 ! Exception handlers
897 .balign 256
898 vbr_start:
899 mov.l 2f, r0 ! load the old vbr setting (if any)
900 mov.l @r0, r0
901 cmp/eq #0, r0
902 bf 1f
903 ! no previous vbr - jump to own generic handler
904 bra handler
905 nop
906 1: ! there was a previous handler - chain them
907 jmp @r0
908 nop
909 .balign 4
910 2:
911 .long old_vbr
912
913 .balign 256
914 vbr_100:
915 #ifdef PROFILE
916 ! Note on register usage.
917 ! we use r0..r3 as scratch in this code. If we are here due to a trapa for profiling
918 ! then this is OK as we are just before executing any function code.
919 ! The other r4..r7 we save explicityl on the stack
920 ! Remaining registers are saved by normal ABI conventions and we assert we do not
921 ! use floating point registers.
922 mov.l expevt_k1, r1
923 mov.l @r1, r1
924 mov.l event_mask, r0
925 and r0,r1
926 mov.l trapcode_k, r2
927 cmp/eq r1,r2
928 bt 1f
929 bra handler_100 ! if not a trapa, go to default handler
930 nop
931 1:
932 mov.l trapa_k, r0
933 mov.l @r0, r0
934 shlr2 r0 ! trapa code is shifted by 2.
935 cmp/eq #33, r0
936 bt 2f
937 bra handler_100
938 nop
939 2:
940
941 ! If here then it looks like we have trap #33
942 ! Now we need to call mcount with the following convention
943 ! Save and restore r4..r7
944 mov.l r4,@-r15
945 mov.l r5,@-r15
946 mov.l r6,@-r15
947 mov.l r7,@-r15
948 sts.l pr,@-r15
949
950 ! r4 is frompc.
951 ! r5 is selfpc
952 ! r0 is the branch back address.
953 ! The code sequence emitted by gcc for the profiling trap is
954 ! .align 2
955 ! trapa #33
956 ! .align 2
957 ! .long lab Where lab is planted by the compiler. This is the address
958 ! of a datum that needs to be incremented.
959 sts pr, r4 ! frompc
960 stc spc, r5 ! selfpc
961 mov #2, r2
962 not r2, r2 ! pattern to align to 4
963 and r2, r5 ! r5 now has aligned address
964 ! add #4, r5 ! r5 now has address of address
965 mov r5, r2 ! Remember it.
966 ! mov.l @r5, r5 ! r5 has value of lable (lab in above example)
967 add #8, r2
968 ldc r2, spc ! our return address avoiding address word
969
970 ! only call mcount if profiling is enabled
971 mov.l profiling_enabled_k, r0
972 mov.l @r0, r0
973 cmp/eq #0, r0
974 bt 3f
975 ! call mcount
976 mov.l mcount_k, r2
977 jsr @r2
978 nop
979 3:
980 lds.l @r15+,pr
981 mov.l @r15+,r7
982 mov.l @r15+,r6
983 mov.l @r15+,r5
984 mov.l @r15+,r4
985 rte
986 nop
987 .balign 4
988 event_mask:
989 .long 0xfff
990 trapcode_k:
991 .long 0x160
992 expevt_k1:
993 .long 0xff000024 ! Address of expevt
994 trapa_k:
995 .long 0xff000020
996 mcount_k:
997 .long __call_mcount
998 profiling_enabled_k:
999 .long profiling_enabled
1000 #endif
1001 ! Non profiling case.
1002 handler_100:
1003 mov.l 2f, r0 ! load the old vbr setting (if any)
1004 mov.l @r0, r0
1005 cmp/eq #0, r0
1006 bf 1f
1007 ! no previous vbr - jump to own generic handler
1008 bra handler
1009 nop
1010 1: ! there was a previous handler - chain them
1011 add #0x7f, r0 ! 0x7f
1012 add #0x7f, r0 ! 0xfe
1013 add #0x2, r0 ! add 0x100 without corrupting another register
1014 jmp @r0
1015 nop
1016 .balign 4
1017 2:
1018 .long old_vbr
1019
1020 .balign 256
1021 vbr_200:
1022 mov.l 2f, r0 ! load the old vbr setting (if any)
1023 mov.l @r0, r0
1024 cmp/eq #0, r0
1025 bf 1f
1026 ! no previous vbr - jump to own generic handler
1027 bra handler
1028 nop
1029 1: ! there was a previous handler - chain them
1030 add #0x7f, r0 ! 0x7f
1031 add #0x7f, r0 ! 0xfe
1032 add #0x7f, r0 ! 0x17d
1033 add #0x7f, r0 ! 0x1fc
1034 add #0x4, r0 ! add 0x200 without corrupting another register
1035 jmp @r0
1036 nop
1037 .balign 4
1038 2:
1039 .long old_vbr
1040
1041 .balign 256
1042 vbr_300:
1043 mov.l 2f, r0 ! load the old vbr setting (if any)
1044 mov.l @r0, r0
1045 cmp/eq #0, r0
1046 bf 1f
1047 ! no previous vbr - jump to own generic handler
1048 bra handler
1049 nop
1050 1: ! there was a previous handler - chain them
1051 rotcr r0
1052 rotcr r0
1053 add #0x7f, r0 ! 0x1fc
1054 add #0x41, r0 ! 0x300
1055 rotcl r0
1056 rotcl r0 ! Add 0x300 without corrupting another register
1057 jmp @r0
1058 nop
1059 .balign 4
1060 2:
1061 .long old_vbr
1062
1063 .balign 256
1064 vbr_400: ! Should be at vbr+0x400
1065 mov.l 2f, r0 ! load the old vbr setting (if any)
1066 mov.l @r0, r0
1067 cmp/eq #0, r0
1068 ! no previous vbr - jump to own generic handler
1069 bt handler
1070 ! there was a previous handler - chain them
1071 rotcr r0
1072 rotcr r0
1073 add #0x7f, r0 ! 0x1fc
1074 add #0x7f, r0 ! 0x3f8
1075 add #0x02, r0 ! 0x400
1076 rotcl r0
1077 rotcl r0 ! Add 0x400 without corrupting another register
1078 jmp @r0
1079 nop
1080 .balign 4
1081 2:
1082 .long old_vbr
1083 handler:
1084 /* If the trap handler is there call it */
1085 mov.l superh_trap_handler_k, r0
1086 cmp/eq #0, r0 ! True if zero.
1087 bf 3f
1088 bra chandler
1089 nop
1090 3:
1091 ! Here handler available, call it.
1092 /* Now call the trap handler with as much of the context unchanged as possible.
1093 Move trapping address into PR to make it look like the trap point */
1094 stc spc, r1
1095 lds r1, pr
1096 mov.l expevt_k, r4
1097 mov.l @r4, r4 ! r4 is value of expevt, first parameter.
1098 mov r1, r5 ! Remember trapping pc.
1099 mov r1, r6 ! Remember trapping pc.
1100 mov.l chandler_k, r1
1101 mov.l superh_trap_handler_k, r2
1102 ! jmp to trap handler to avoid disturbing pr.
1103 jmp @r2
1104 nop
1105
1106 .balign 256
1107 vbr_500:
1108 mov.l 2f, r0 ! load the old vbr setting (if any)
1109 mov.l @r0, r0
1110 cmp/eq #0, r0
1111 ! no previous vbr - jump to own generic handler
1112 bt handler
1113 ! there was a previous handler - chain them
1114 rotcr r0
1115 rotcr r0
1116 add #0x7f, r0 ! 0x1fc
1117 add #0x7f, r0 ! 0x3f8
1118 add #0x42, r0 ! 0x500
1119 rotcl r0
1120 rotcl r0 ! Add 0x500 without corrupting another register
1121 jmp @r0
1122 nop
1123 .balign 4
1124 2:
1125 .long old_vbr
1126
1127 .balign 256
1128 vbr_600:
1129 #ifdef PROFILE
1130 ! Should be at vbr+0x600
1131 ! Now we are in the land of interrupts so need to save more state.
1132 ! Save register state
1133 mov.l interrupt_stack_k, r15 ! r15 has been saved to sgr.
1134 mov.l r0,@-r15
1135 mov.l r1,@-r15
1136 mov.l r2,@-r15
1137 mov.l r3,@-r15
1138 mov.l r4,@-r15
1139 mov.l r5,@-r15
1140 mov.l r6,@-r15
1141 mov.l r7,@-r15
1142 sts.l pr,@-r15
1143 ! Pass interrupted pc to timer_handler as first parameter (r4).
1144 stc spc, r4
1145 mov.l timer_handler_k, r0
1146 jsr @r0
1147 nop
1148 lds.l @r15+,pr
1149 mov.l @r15+,r7
1150 mov.l @r15+,r6
1151 mov.l @r15+,r5
1152 mov.l @r15+,r4
1153 mov.l @r15+,r3
1154 mov.l @r15+,r2
1155 mov.l @r15+,r1
1156 mov.l @r15+,r0
1157 stc sgr, r15 ! Restore r15, destroyed by this sequence.
1158 rte
1159 nop
1160 #else
1161 mov.l 2f, r0 ! Load the old vbr setting (if any).
1162 mov.l @r0, r0
1163 cmp/eq #0, r0
1164 ! no previous vbr - jump to own handler
1165 bt chandler
1166 ! there was a previous handler - chain them
1167 rotcr r0
1168 rotcr r0
1169 add #0x7f, r0 ! 0x1fc
1170 add #0x7f, r0 ! 0x3f8
1171 add #0x7f, r0 ! 0x5f4
1172 add #0x03, r0 ! 0x600
1173 rotcl r0
1174 rotcl r0 ! Add 0x600 without corrupting another register
1175 jmp @r0
1176 nop
1177 .balign 4
1178 2:
1179 .long old_vbr
1180 #endif /* PROFILE code */
1181 chandler:
1182 mov.l expevt_k, r4
1183 mov.l @r4, r4 ! r4 is value of expevt hence making this the return code
1184 mov.l handler_exit_k,r0
1185 jsr @r0
1186 nop
1187 ! We should never return from _exit but in case we do we would enter the
1188 ! the following tight loop
1189 limbo:
1190 bra limbo
1191 nop
1192 .balign 4
1193 #ifdef PROFILE
1194 interrupt_stack_k:
1195 .long __timer_stack ! The high end of the stack
1196 timer_handler_k:
1197 .long __profil_counter
1198 #endif
1199 expevt_k:
1200 .long 0xff000024 ! Address of expevt
1201 chandler_k:
1202 .long chandler
1203 superh_trap_handler_k:
1204 .long __superh_trap_handler
1205 handler_exit_k:
1206 .long _exit
1207 .align 2
1208 ! Simulated compile of trap handler.
1209 .section .debug_abbrev,"",@progbits
1210 .Ldebug_abbrev0:
1211 .section .debug_info,"",@progbits
1212 .Ldebug_info0:
1213 .section .debug_line,"",@progbits
1214 .Ldebug_line0:
1215 .text
1216 .Ltext0:
1217 .align 5
1218 .type __superh_trap_handler,@function
1219 __superh_trap_handler:
1220 .LFB1:
1221 mov.l r14,@-r15
1222 .LCFI0:
1223 add #-4,r15
1224 .LCFI1:
1225 mov r15,r14
1226 .LCFI2:
1227 mov.l r4,@r14
1228 lds r1, pr
1229 add #4,r14
1230 mov r14,r15
1231 mov.l @r15+,r14
1232 rts
1233 nop
1234 .LFE1:
1235 .Lfe1:
1236 .size __superh_trap_handler,.Lfe1-__superh_trap_handler
1237 .section .debug_frame,"",@progbits
1238 .Lframe0:
1239 .ualong .LECIE0-.LSCIE0
1240 .LSCIE0:
1241 .ualong 0xffffffff
1242 .byte 0x1
1243 .string ""
1244 .uleb128 0x1
1245 .sleb128 -4
1246 .byte 0x11
1247 .byte 0xc
1248 .uleb128 0xf
1249 .uleb128 0x0
1250 .align 2
1251 .LECIE0:
1252 .LSFDE0:
1253 .ualong .LEFDE0-.LASFDE0
1254 .LASFDE0:
1255 .ualong .Lframe0
1256 .ualong .LFB1
1257 .ualong .LFE1-.LFB1
1258 .byte 0x4
1259 .ualong .LCFI0-.LFB1
1260 .byte 0xe
1261 .uleb128 0x4
1262 .byte 0x4
1263 .ualong .LCFI1-.LCFI0
1264 .byte 0xe
1265 .uleb128 0x8
1266 .byte 0x8e
1267 .uleb128 0x1
1268 .byte 0x4
1269 .ualong .LCFI2-.LCFI1
1270 .byte 0xd
1271 .uleb128 0xe
1272 .align 2
1273 .LEFDE0:
1274 .text
1275 .Letext0:
1276 .section .debug_info
1277 .ualong 0xb3
1278 .uaword 0x2
1279 .ualong .Ldebug_abbrev0
1280 .byte 0x4
1281 .uleb128 0x1
1282 .ualong .Ldebug_line0
1283 .ualong .Letext0
1284 .ualong .Ltext0
1285 .string "trap_handler.c"
1286 .string "xxxxxxxxxxxxxxxxxxxxxxxxxxxx"
1287 .string "GNU C 3.2 20020529 (experimental)"
1288 .byte 0x1
1289 .uleb128 0x2
1290 .ualong 0xa6
1291 .byte 0x1
1292 .string "_superh_trap_handler"
1293 .byte 0x1
1294 .byte 0x2
1295 .byte 0x1
1296 .ualong .LFB1
1297 .ualong .LFE1
1298 .byte 0x1
1299 .byte 0x5e
1300 .uleb128 0x3
1301 .string "trap_reason"
1302 .byte 0x1
1303 .byte 0x1
1304 .ualong 0xa6
1305 .byte 0x2
1306 .byte 0x91
1307 .sleb128 0
1308 .byte 0x0
1309 .uleb128 0x4
1310 .string "unsigned int"
1311 .byte 0x4
1312 .byte 0x7
1313 .byte 0x0
1314 .section .debug_abbrev
1315 .uleb128 0x1
1316 .uleb128 0x11
1317 .byte 0x1
1318 .uleb128 0x10
1319 .uleb128 0x6
1320 .uleb128 0x12
1321 .uleb128 0x1
1322 .uleb128 0x11
1323 .uleb128 0x1
1324 .uleb128 0x3
1325 .uleb128 0x8
1326 .uleb128 0x1b
1327 .uleb128 0x8
1328 .uleb128 0x25
1329 .uleb128 0x8
1330 .uleb128 0x13
1331 .uleb128 0xb
1332 .byte 0x0
1333 .byte 0x0
1334 .uleb128 0x2
1335 .uleb128 0x2e
1336 .byte 0x1
1337 .uleb128 0x1
1338 .uleb128 0x13
1339 .uleb128 0x3f
1340 .uleb128 0xc
1341 .uleb128 0x3
1342 .uleb128 0x8
1343 .uleb128 0x3a
1344 .uleb128 0xb
1345 .uleb128 0x3b
1346 .uleb128 0xb
1347 .uleb128 0x27
1348 .uleb128 0xc
1349 .uleb128 0x11
1350 .uleb128 0x1
1351 .uleb128 0x12
1352 .uleb128 0x1
1353 .uleb128 0x40
1354 .uleb128 0xa
1355 .byte 0x0
1356 .byte 0x0
1357 .uleb128 0x3
1358 .uleb128 0x5
1359 .byte 0x0
1360 .uleb128 0x3
1361 .uleb128 0x8
1362 .uleb128 0x3a
1363 .uleb128 0xb
1364 .uleb128 0x3b
1365 .uleb128 0xb
1366 .uleb128 0x49
1367 .uleb128 0x13
1368 .uleb128 0x2
1369 .uleb128 0xa
1370 .byte 0x0
1371 .byte 0x0
1372 .uleb128 0x4
1373 .uleb128 0x24
1374 .byte 0x0
1375 .uleb128 0x3
1376 .uleb128 0x8
1377 .uleb128 0xb
1378 .uleb128 0xb
1379 .uleb128 0x3e
1380 .uleb128 0xb
1381 .byte 0x0
1382 .byte 0x0
1383 .byte 0x0
1384 .section .debug_pubnames,"",@progbits
1385 .ualong 0x27
1386 .uaword 0x2
1387 .ualong .Ldebug_info0
1388 .ualong 0xb7
1389 .ualong 0x67
1390 .string "_superh_trap_handler"
1391 .ualong 0x0
1392 .section .debug_aranges,"",@progbits
1393 .ualong 0x1c
1394 .uaword 0x2
1395 .ualong .Ldebug_info0
1396 .byte 0x4
1397 .byte 0x0
1398 .uaword 0x0
1399 .uaword 0x0
1400 .ualong .Ltext0
1401 .ualong .Letext0-.Ltext0
1402 .ualong 0x0
1403 .ualong 0x0
1404 #endif /* VBR_SETUP */
1405 #endif /* ! __SH5__ */
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