1 /* Scheduler hooks for IA-32 which implement atom+ specific logic.
2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
28 #include "insn-config.h"
29 #include "insn-attr.h"
34 #include "sched-int.h"
36 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
37 execution. It is applied if
38 (1) IMUL instruction is on the top of list;
39 (2) There exists the only producer of independent IMUL instruction in
41 Return index of IMUL producer if it was found and -1 otherwise. */
43 do_reorder_for_imul (rtx_insn
**ready
, int n_ready
)
46 rtx set
, insn1
, insn2
;
47 sd_iterator_def sd_it
;
55 /* Check that IMUL instruction is on the top of ready list. */
56 insn
= ready
[n_ready
- 1];
57 set
= single_set (insn
);
60 if (!(GET_CODE (SET_SRC (set
)) == MULT
61 && GET_MODE (SET_SRC (set
)) == SImode
))
64 /* Search for producer of independent IMUL instruction. */
65 for (i
= n_ready
- 2; i
>= 0; i
--)
68 if (!NONDEBUG_INSN_P (insn
))
70 /* Skip IMUL instruction. */
71 insn2
= PATTERN (insn
);
72 if (GET_CODE (insn2
) == PARALLEL
)
73 insn2
= XVECEXP (insn2
, 0, 0);
74 if (GET_CODE (insn2
) == SET
75 && GET_CODE (SET_SRC (insn2
)) == MULT
76 && GET_MODE (SET_SRC (insn2
)) == SImode
)
79 FOR_EACH_DEP (insn
, SD_LIST_FORW
, sd_it
, dep
)
83 if (!NONDEBUG_INSN_P (con
))
85 insn1
= PATTERN (con
);
86 if (GET_CODE (insn1
) == PARALLEL
)
87 insn1
= XVECEXP (insn1
, 0, 0);
89 if (GET_CODE (insn1
) == SET
90 && GET_CODE (SET_SRC (insn1
)) == MULT
91 && GET_MODE (SET_SRC (insn1
)) == SImode
)
93 sd_iterator_def sd_it1
;
95 /* Check if there is no other dependee for IMUL. */
97 FOR_EACH_DEP (con
, SD_LIST_BACK
, sd_it1
, dep1
)
100 pro
= DEP_PRO (dep1
);
101 if (!NONDEBUG_INSN_P (pro
))
116 /* Try to find the best candidate on the top of ready list if two insns
117 have the same priority - candidate is best if its dependees were
118 scheduled earlier. Applied for Silvermont only.
119 Return true if top 2 insns must be interchanged. */
121 swap_top_of_ready_list (rtx_insn
**ready
, int n_ready
)
123 rtx_insn
*top
= ready
[n_ready
- 1];
124 rtx_insn
*next
= ready
[n_ready
- 2];
126 sd_iterator_def sd_it
;
130 #define INSN_TICK(INSN) (HID (INSN)->tick)
132 if (!TARGET_SILVERMONT
&& !TARGET_INTEL
)
135 if (!NONDEBUG_INSN_P (top
))
137 if (!NONJUMP_INSN_P (top
))
139 if (!NONDEBUG_INSN_P (next
))
141 if (!NONJUMP_INSN_P (next
))
143 set
= single_set (top
);
146 set
= single_set (next
);
150 if (INSN_PRIORITY_KNOWN (top
) && INSN_PRIORITY_KNOWN (next
))
152 if (INSN_PRIORITY (top
) != INSN_PRIORITY (next
))
154 /* Determine winner more precise. */
155 FOR_EACH_DEP (top
, SD_LIST_RES_BACK
, sd_it
, dep
)
159 if (!NONDEBUG_INSN_P (pro
))
161 if (INSN_TICK (pro
) > clock1
)
162 clock1
= INSN_TICK (pro
);
164 FOR_EACH_DEP (next
, SD_LIST_RES_BACK
, sd_it
, dep
)
168 if (!NONDEBUG_INSN_P (pro
))
170 if (INSN_TICK (pro
) > clock2
)
171 clock2
= INSN_TICK (pro
);
174 if (clock1
== clock2
)
176 /* Determine winner - load must win. */
177 enum attr_memory memory1
, memory2
;
178 memory1
= get_attr_memory (top
);
179 memory2
= get_attr_memory (next
);
180 if (memory2
== MEMORY_LOAD
&& memory1
!= MEMORY_LOAD
)
183 return (bool) (clock2
< clock1
);
189 /* Perform possible reodering of ready list for Atom/Silvermont only.
190 Return issue rate. */
192 ix86_atom_sched_reorder (FILE *dump
, int sched_verbose
, rtx_insn
**ready
,
193 int *pn_ready
, int clock_var
)
196 int n_ready
= *pn_ready
;
201 /* Set up issue rate. */
202 issue_rate
= ix86_issue_rate ();
204 /* Do reodering for BONNELL/SILVERMONT only. */
205 if (!TARGET_BONNELL
&& !TARGET_SILVERMONT
&& !TARGET_INTEL
)
208 /* Nothing to do if ready list contains only 1 instruction. */
212 /* Do reodering for post-reload scheduler only. */
213 if (!reload_completed
)
216 if ((index
= do_reorder_for_imul (ready
, n_ready
)) >= 0)
218 if (sched_verbose
> 1)
219 fprintf (dump
, ";;\tatom sched_reorder: put %d insn on top\n",
220 INSN_UID (ready
[index
]));
222 /* Put IMUL producer (ready[index]) at the top of ready list. */
224 for (i
= index
; i
< n_ready
- 1; i
++)
225 ready
[i
] = ready
[i
+ 1];
226 ready
[n_ready
- 1] = insn
;
230 /* Skip selective scheduling since HID is not populated in it. */
233 && swap_top_of_ready_list (ready
, n_ready
))
235 if (sched_verbose
> 1)
236 fprintf (dump
, ";;\tslm sched_reorder: swap %d and %d insns\n",
237 INSN_UID (ready
[n_ready
- 1]), INSN_UID (ready
[n_ready
- 2]));
238 /* Swap 2 top elements of ready list. */
239 insn
= ready
[n_ready
- 1];
240 ready
[n_ready
- 1] = ready
[n_ready
- 2];
241 ready
[n_ready
- 2] = insn
;