1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "diagnostic-core.h"
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
42 #include "basic-block.h"
48 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
49 #include "addresses.h"
52 /* Forward declarations */
53 static void set_of_1 (rtx
, const_rtx
, void *);
54 static bool covers_regno_p (const_rtx
, unsigned int);
55 static bool covers_regno_no_parallel_p (const_rtx
, unsigned int);
56 static int computed_jump_p_1 (const_rtx
);
57 static void parms_set (rtx
, const_rtx
, void *);
59 static unsigned HOST_WIDE_INT
cached_nonzero_bits (const_rtx
, machine_mode
,
60 const_rtx
, machine_mode
,
61 unsigned HOST_WIDE_INT
);
62 static unsigned HOST_WIDE_INT
nonzero_bits1 (const_rtx
, machine_mode
,
63 const_rtx
, machine_mode
,
64 unsigned HOST_WIDE_INT
);
65 static unsigned int cached_num_sign_bit_copies (const_rtx
, machine_mode
, const_rtx
,
68 static unsigned int num_sign_bit_copies1 (const_rtx
, machine_mode
, const_rtx
,
69 machine_mode
, unsigned int);
71 rtx_subrtx_bound_info rtx_all_subrtx_bounds
[NUM_RTX_CODE
];
72 rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds
[NUM_RTX_CODE
];
74 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
75 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
76 SIGN_EXTEND then while narrowing we also have to enforce the
77 representation and sign-extend the value to mode DESTINATION_REP.
79 If the value is already sign-extended to DESTINATION_REP mode we
80 can just switch to DESTINATION mode on it. For each pair of
81 integral modes SOURCE and DESTINATION, when truncating from SOURCE
82 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
83 contains the number of high-order bits in SOURCE that have to be
84 copies of the sign-bit so that we can do this mode-switch to
88 num_sign_bit_copies_in_rep
[MAX_MODE_INT
+ 1][MAX_MODE_INT
+ 1];
90 /* Store X into index I of ARRAY. ARRAY is known to have at least I
91 elements. Return the new base of ARRAY. */
94 typename
T::value_type
*
95 generic_subrtx_iterator
<T
>::add_single_to_queue (array_type
&array
,
97 size_t i
, value_type x
)
99 if (base
== array
.stack
)
106 gcc_checking_assert (i
== LOCAL_ELEMS
);
107 /* A previous iteration might also have moved from the stack to the
108 heap, in which case the heap array will already be big enough. */
109 if (vec_safe_length (array
.heap
) <= i
)
110 vec_safe_grow (array
.heap
, i
+ 1);
111 base
= array
.heap
->address ();
112 memcpy (base
, array
.stack
, sizeof (array
.stack
));
113 base
[LOCAL_ELEMS
] = x
;
116 unsigned int length
= array
.heap
->length ();
119 gcc_checking_assert (base
== array
.heap
->address ());
125 gcc_checking_assert (i
== length
);
126 vec_safe_push (array
.heap
, x
);
127 return array
.heap
->address ();
131 /* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
132 number of elements added to the worklist. */
134 template <typename T
>
136 generic_subrtx_iterator
<T
>::add_subrtxes_to_queue (array_type
&array
,
138 size_t end
, rtx_type x
)
140 enum rtx_code code
= GET_CODE (x
);
141 const char *format
= GET_RTX_FORMAT (code
);
142 size_t orig_end
= end
;
143 if (__builtin_expect (INSN_P (x
), false))
145 /* Put the pattern at the top of the queue, since that's what
146 we're likely to want most. It also allows for the SEQUENCE
148 for (int i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; --i
)
149 if (format
[i
] == 'e')
151 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
152 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
155 base
= add_single_to_queue (array
, base
, end
++, subx
);
159 for (int i
= 0; format
[i
]; ++i
)
160 if (format
[i
] == 'e')
162 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
163 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
166 base
= add_single_to_queue (array
, base
, end
++, subx
);
168 else if (format
[i
] == 'E')
170 unsigned int length
= GET_NUM_ELEM (x
->u
.fld
[i
].rt_rtvec
);
171 rtx
*vec
= x
->u
.fld
[i
].rt_rtvec
->elem
;
172 if (__builtin_expect (end
+ length
<= LOCAL_ELEMS
, true))
173 for (unsigned int j
= 0; j
< length
; j
++)
174 base
[end
++] = T::get_value (vec
[j
]);
176 for (unsigned int j
= 0; j
< length
; j
++)
177 base
= add_single_to_queue (array
, base
, end
++,
178 T::get_value (vec
[j
]));
179 if (code
== SEQUENCE
&& end
== length
)
180 /* If the subrtxes of the sequence fill the entire array then
181 we know that no other parts of a containing insn are queued.
182 The caller is therefore iterating over the sequence as a
183 PATTERN (...), so we also want the patterns of the
185 for (unsigned int j
= 0; j
< length
; j
++)
187 typename
T::rtx_type x
= T::get_rtx (base
[j
]);
189 base
[j
] = T::get_value (PATTERN (x
));
192 return end
- orig_end
;
195 template <typename T
>
197 generic_subrtx_iterator
<T
>::free_array (array_type
&array
)
199 vec_free (array
.heap
);
202 template <typename T
>
203 const size_t generic_subrtx_iterator
<T
>::LOCAL_ELEMS
;
205 template class generic_subrtx_iterator
<const_rtx_accessor
>;
206 template class generic_subrtx_iterator
<rtx_var_accessor
>;
207 template class generic_subrtx_iterator
<rtx_ptr_accessor
>;
209 /* Return 1 if the value of X is unstable
210 (would be different at a different point in the program).
211 The frame pointer, arg pointer, etc. are considered stable
212 (within one function) and so is anything marked `unchanging'. */
215 rtx_unstable_p (const_rtx x
)
217 const RTX_CODE code
= GET_CODE (x
);
224 return !MEM_READONLY_P (x
) || rtx_unstable_p (XEXP (x
, 0));
233 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
234 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
235 /* The arg pointer varies if it is not a fixed register. */
236 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
238 /* ??? When call-clobbered, the value is stable modulo the restore
239 that must happen after a call. This currently screws up local-alloc
240 into believing that the restore is not needed. */
241 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& x
== pic_offset_table_rtx
)
246 if (MEM_VOLATILE_P (x
))
255 fmt
= GET_RTX_FORMAT (code
);
256 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
259 if (rtx_unstable_p (XEXP (x
, i
)))
262 else if (fmt
[i
] == 'E')
265 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
266 if (rtx_unstable_p (XVECEXP (x
, i
, j
)))
273 /* Return 1 if X has a value that can vary even between two
274 executions of the program. 0 means X can be compared reliably
275 against certain constants or near-constants.
276 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
277 zero, we are slightly more conservative.
278 The frame pointer and the arg pointer are considered constant. */
281 rtx_varies_p (const_rtx x
, bool for_alias
)
294 return !MEM_READONLY_P (x
) || rtx_varies_p (XEXP (x
, 0), for_alias
);
303 /* Note that we have to test for the actual rtx used for the frame
304 and arg pointers and not just the register number in case we have
305 eliminated the frame and/or arg pointer and are using it
307 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
308 /* The arg pointer varies if it is not a fixed register. */
309 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
311 if (x
== pic_offset_table_rtx
312 /* ??? When call-clobbered, the value is stable modulo the restore
313 that must happen after a call. This currently screws up
314 local-alloc into believing that the restore is not needed, so we
315 must return 0 only if we are called from alias analysis. */
316 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
|| for_alias
))
321 /* The operand 0 of a LO_SUM is considered constant
322 (in fact it is related specifically to operand 1)
323 during alias analysis. */
324 return (! for_alias
&& rtx_varies_p (XEXP (x
, 0), for_alias
))
325 || rtx_varies_p (XEXP (x
, 1), for_alias
);
328 if (MEM_VOLATILE_P (x
))
337 fmt
= GET_RTX_FORMAT (code
);
338 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
341 if (rtx_varies_p (XEXP (x
, i
), for_alias
))
344 else if (fmt
[i
] == 'E')
347 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
348 if (rtx_varies_p (XVECEXP (x
, i
, j
), for_alias
))
355 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
356 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
357 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
358 references on strict alignment machines. */
361 rtx_addr_can_trap_p_1 (const_rtx x
, HOST_WIDE_INT offset
, HOST_WIDE_INT size
,
362 machine_mode mode
, bool unaligned_mems
)
364 enum rtx_code code
= GET_CODE (x
);
366 /* The offset must be a multiple of the mode size if we are considering
367 unaligned memory references on strict alignment machines. */
368 if (STRICT_ALIGNMENT
&& unaligned_mems
&& GET_MODE_SIZE (mode
) != 0)
370 HOST_WIDE_INT actual_offset
= offset
;
372 #ifdef SPARC_STACK_BOUNDARY_HACK
373 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
374 the real alignment of %sp. However, when it does this, the
375 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
376 if (SPARC_STACK_BOUNDARY_HACK
377 && (x
== stack_pointer_rtx
|| x
== hard_frame_pointer_rtx
))
378 actual_offset
-= STACK_POINTER_OFFSET
;
381 if (actual_offset
% GET_MODE_SIZE (mode
) != 0)
388 if (SYMBOL_REF_WEAK (x
))
390 if (!CONSTANT_POOL_ADDRESS_P (x
))
393 HOST_WIDE_INT decl_size
;
398 size
= GET_MODE_SIZE (mode
);
402 /* If the size of the access or of the symbol is unknown,
404 decl
= SYMBOL_REF_DECL (x
);
406 /* Else check that the access is in bounds. TODO: restructure
407 expr_size/tree_expr_size/int_expr_size and just use the latter. */
410 else if (DECL_P (decl
) && DECL_SIZE_UNIT (decl
))
411 decl_size
= (tree_fits_shwi_p (DECL_SIZE_UNIT (decl
))
412 ? tree_to_shwi (DECL_SIZE_UNIT (decl
))
414 else if (TREE_CODE (decl
) == STRING_CST
)
415 decl_size
= TREE_STRING_LENGTH (decl
);
416 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl
)))
417 decl_size
= int_size_in_bytes (TREE_TYPE (decl
));
421 return (decl_size
<= 0 ? offset
!= 0 : offset
+ size
> decl_size
);
430 /* Stack references are assumed not to trap, but we need to deal with
431 nonsensical offsets. */
432 if (x
== frame_pointer_rtx
)
434 HOST_WIDE_INT adj_offset
= offset
- STARTING_FRAME_OFFSET
;
436 size
= GET_MODE_SIZE (mode
);
437 if (FRAME_GROWS_DOWNWARD
)
439 if (adj_offset
< frame_offset
|| adj_offset
+ size
- 1 >= 0)
444 if (adj_offset
< 0 || adj_offset
+ size
- 1 >= frame_offset
)
449 /* ??? Need to add a similar guard for nonsensical offsets. */
450 if (x
== hard_frame_pointer_rtx
451 || x
== stack_pointer_rtx
452 /* The arg pointer varies if it is not a fixed register. */
453 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
455 /* All of the virtual frame registers are stack references. */
456 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
457 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
462 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
463 mode
, unaligned_mems
);
466 /* An address is assumed not to trap if:
467 - it is the pic register plus a constant. */
468 if (XEXP (x
, 0) == pic_offset_table_rtx
&& CONSTANT_P (XEXP (x
, 1)))
471 /* - or it is an address that can't trap plus a constant integer. */
472 if (CONST_INT_P (XEXP (x
, 1))
473 && !rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
+ INTVAL (XEXP (x
, 1)),
474 size
, mode
, unaligned_mems
))
481 return rtx_addr_can_trap_p_1 (XEXP (x
, 1), offset
, size
,
482 mode
, unaligned_mems
);
489 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
490 mode
, unaligned_mems
);
496 /* If it isn't one of the case above, it can cause a trap. */
500 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
503 rtx_addr_can_trap_p (const_rtx x
)
505 return rtx_addr_can_trap_p_1 (x
, 0, 0, VOIDmode
, false);
508 /* Return true if X is an address that is known to not be zero. */
511 nonzero_address_p (const_rtx x
)
513 const enum rtx_code code
= GET_CODE (x
);
518 return !SYMBOL_REF_WEAK (x
);
524 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
525 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
526 || x
== stack_pointer_rtx
527 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
529 /* All of the virtual frame registers are stack references. */
530 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
531 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
536 return nonzero_address_p (XEXP (x
, 0));
539 /* Handle PIC references. */
540 if (XEXP (x
, 0) == pic_offset_table_rtx
541 && CONSTANT_P (XEXP (x
, 1)))
546 /* Similar to the above; allow positive offsets. Further, since
547 auto-inc is only allowed in memories, the register must be a
549 if (CONST_INT_P (XEXP (x
, 1))
550 && INTVAL (XEXP (x
, 1)) > 0)
552 return nonzero_address_p (XEXP (x
, 0));
555 /* Similarly. Further, the offset is always positive. */
562 return nonzero_address_p (XEXP (x
, 0));
565 return nonzero_address_p (XEXP (x
, 1));
571 /* If it isn't one of the case above, might be zero. */
575 /* Return 1 if X refers to a memory location whose address
576 cannot be compared reliably with constant addresses,
577 or if X refers to a BLKmode memory object.
578 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
579 zero, we are slightly more conservative. */
582 rtx_addr_varies_p (const_rtx x
, bool for_alias
)
593 return GET_MODE (x
) == BLKmode
|| rtx_varies_p (XEXP (x
, 0), for_alias
);
595 fmt
= GET_RTX_FORMAT (code
);
596 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
599 if (rtx_addr_varies_p (XEXP (x
, i
), for_alias
))
602 else if (fmt
[i
] == 'E')
605 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
606 if (rtx_addr_varies_p (XVECEXP (x
, i
, j
), for_alias
))
612 /* Return the CALL in X if there is one. */
615 get_call_rtx_from (rtx x
)
619 if (GET_CODE (x
) == PARALLEL
)
620 x
= XVECEXP (x
, 0, 0);
621 if (GET_CODE (x
) == SET
)
623 if (GET_CODE (x
) == CALL
&& MEM_P (XEXP (x
, 0)))
628 /* Return the value of the integer term in X, if one is apparent;
630 Only obvious integer terms are detected.
631 This is used in cse.c with the `related_value' field. */
634 get_integer_term (const_rtx x
)
636 if (GET_CODE (x
) == CONST
)
639 if (GET_CODE (x
) == MINUS
640 && CONST_INT_P (XEXP (x
, 1)))
641 return - INTVAL (XEXP (x
, 1));
642 if (GET_CODE (x
) == PLUS
643 && CONST_INT_P (XEXP (x
, 1)))
644 return INTVAL (XEXP (x
, 1));
648 /* If X is a constant, return the value sans apparent integer term;
650 Only obvious integer terms are detected. */
653 get_related_value (const_rtx x
)
655 if (GET_CODE (x
) != CONST
)
658 if (GET_CODE (x
) == PLUS
659 && CONST_INT_P (XEXP (x
, 1)))
661 else if (GET_CODE (x
) == MINUS
662 && CONST_INT_P (XEXP (x
, 1)))
667 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
668 to somewhere in the same object or object_block as SYMBOL. */
671 offset_within_block_p (const_rtx symbol
, HOST_WIDE_INT offset
)
675 if (GET_CODE (symbol
) != SYMBOL_REF
)
683 if (CONSTANT_POOL_ADDRESS_P (symbol
)
684 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
687 decl
= SYMBOL_REF_DECL (symbol
);
688 if (decl
&& offset
< int_size_in_bytes (TREE_TYPE (decl
)))
692 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol
)
693 && SYMBOL_REF_BLOCK (symbol
)
694 && SYMBOL_REF_BLOCK_OFFSET (symbol
) >= 0
695 && ((unsigned HOST_WIDE_INT
) offset
+ SYMBOL_REF_BLOCK_OFFSET (symbol
)
696 < (unsigned HOST_WIDE_INT
) SYMBOL_REF_BLOCK (symbol
)->size
))
702 /* Split X into a base and a constant offset, storing them in *BASE_OUT
703 and *OFFSET_OUT respectively. */
706 split_const (rtx x
, rtx
*base_out
, rtx
*offset_out
)
708 if (GET_CODE (x
) == CONST
)
711 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
713 *base_out
= XEXP (x
, 0);
714 *offset_out
= XEXP (x
, 1);
719 *offset_out
= const0_rtx
;
722 /* Return the number of places FIND appears within X. If COUNT_DEST is
723 zero, we do not count occurrences inside the destination of a SET. */
726 count_occurrences (const_rtx x
, const_rtx find
, int count_dest
)
730 const char *format_ptr
;
749 count
= count_occurrences (XEXP (x
, 0), find
, count_dest
);
751 count
+= count_occurrences (XEXP (x
, 1), find
, count_dest
);
755 if (MEM_P (find
) && rtx_equal_p (x
, find
))
760 if (SET_DEST (x
) == find
&& ! count_dest
)
761 return count_occurrences (SET_SRC (x
), find
, count_dest
);
768 format_ptr
= GET_RTX_FORMAT (code
);
771 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
773 switch (*format_ptr
++)
776 count
+= count_occurrences (XEXP (x
, i
), find
, count_dest
);
780 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
781 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
, count_dest
);
789 /* Return TRUE if OP is a register or subreg of a register that
790 holds an unsigned quantity. Otherwise, return FALSE. */
793 unsigned_reg_p (rtx op
)
797 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op
))))
800 if (GET_CODE (op
) == SUBREG
801 && SUBREG_PROMOTED_SIGN (op
))
808 /* Nonzero if register REG appears somewhere within IN.
809 Also works if REG is not a register; in this case it checks
810 for a subexpression of IN that is Lisp "equal" to REG. */
813 reg_mentioned_p (const_rtx reg
, const_rtx in
)
825 if (GET_CODE (in
) == LABEL_REF
)
826 return reg
== LABEL_REF_LABEL (in
);
828 code
= GET_CODE (in
);
832 /* Compare registers by number. */
834 return REG_P (reg
) && REGNO (in
) == REGNO (reg
);
836 /* These codes have no constituent expressions
844 /* These are kept unique for a given value. */
851 if (GET_CODE (reg
) == code
&& rtx_equal_p (reg
, in
))
854 fmt
= GET_RTX_FORMAT (code
);
856 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
861 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
862 if (reg_mentioned_p (reg
, XVECEXP (in
, i
, j
)))
865 else if (fmt
[i
] == 'e'
866 && reg_mentioned_p (reg
, XEXP (in
, i
)))
872 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
873 no CODE_LABEL insn. */
876 no_labels_between_p (const rtx_insn
*beg
, const rtx_insn
*end
)
881 for (p
= NEXT_INSN (beg
); p
!= end
; p
= NEXT_INSN (p
))
887 /* Nonzero if register REG is used in an insn between
888 FROM_INSN and TO_INSN (exclusive of those two). */
891 reg_used_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
892 const rtx_insn
*to_insn
)
896 if (from_insn
== to_insn
)
899 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
900 if (NONDEBUG_INSN_P (insn
)
901 && (reg_overlap_mentioned_p (reg
, PATTERN (insn
))
902 || (CALL_P (insn
) && find_reg_fusage (insn
, USE
, reg
))))
907 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
908 is entirely replaced by a new value and the only use is as a SET_DEST,
909 we do not consider it a reference. */
912 reg_referenced_p (const_rtx x
, const_rtx body
)
916 switch (GET_CODE (body
))
919 if (reg_overlap_mentioned_p (x
, SET_SRC (body
)))
922 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
923 of a REG that occupies all of the REG, the insn references X if
924 it is mentioned in the destination. */
925 if (GET_CODE (SET_DEST (body
)) != CC0
926 && GET_CODE (SET_DEST (body
)) != PC
927 && !REG_P (SET_DEST (body
))
928 && ! (GET_CODE (SET_DEST (body
)) == SUBREG
929 && REG_P (SUBREG_REG (SET_DEST (body
)))
930 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (body
))))
931 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
932 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (body
)))
933 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
934 && reg_overlap_mentioned_p (x
, SET_DEST (body
)))
939 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
940 if (reg_overlap_mentioned_p (x
, ASM_OPERANDS_INPUT (body
, i
)))
947 return reg_overlap_mentioned_p (x
, body
);
950 return reg_overlap_mentioned_p (x
, TRAP_CONDITION (body
));
953 return reg_overlap_mentioned_p (x
, XEXP (body
, 0));
956 case UNSPEC_VOLATILE
:
957 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
958 if (reg_overlap_mentioned_p (x
, XVECEXP (body
, 0, i
)))
963 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
964 if (reg_referenced_p (x
, XVECEXP (body
, 0, i
)))
969 if (MEM_P (XEXP (body
, 0)))
970 if (reg_overlap_mentioned_p (x
, XEXP (XEXP (body
, 0), 0)))
975 if (reg_overlap_mentioned_p (x
, COND_EXEC_TEST (body
)))
977 return reg_referenced_p (x
, COND_EXEC_CODE (body
));
984 /* Nonzero if register REG is set or clobbered in an insn between
985 FROM_INSN and TO_INSN (exclusive of those two). */
988 reg_set_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
989 const rtx_insn
*to_insn
)
991 const rtx_insn
*insn
;
993 if (from_insn
== to_insn
)
996 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
997 if (INSN_P (insn
) && reg_set_p (reg
, insn
))
1002 /* Internals of reg_set_between_p. */
1004 reg_set_p (const_rtx reg
, const_rtx insn
)
1006 /* After delay slot handling, call and branch insns might be in a
1007 sequence. Check all the elements there. */
1008 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
1010 for (int i
= 0; i
< XVECLEN (PATTERN (insn
), 0); ++i
)
1011 if (reg_set_p (reg
, XVECEXP (PATTERN (insn
), 0, i
)))
1017 /* We can be passed an insn or part of one. If we are passed an insn,
1018 check if a side-effect of the insn clobbers REG. */
1020 && (FIND_REG_INC_NOTE (insn
, reg
)
1023 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
1024 && overlaps_hard_reg_set_p (regs_invalidated_by_call
,
1025 GET_MODE (reg
), REGNO (reg
)))
1027 || find_reg_fusage (insn
, CLOBBER
, reg
)))))
1030 return set_of (reg
, insn
) != NULL_RTX
;
1033 /* Similar to reg_set_between_p, but check all registers in X. Return 0
1034 only if none of them are modified between START and END. Return 1 if
1035 X contains a MEM; this routine does use memory aliasing. */
1038 modified_between_p (const_rtx x
, const rtx_insn
*start
, const rtx_insn
*end
)
1040 const enum rtx_code code
= GET_CODE (x
);
1061 if (modified_between_p (XEXP (x
, 0), start
, end
))
1063 if (MEM_READONLY_P (x
))
1065 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
1066 if (memory_modified_in_insn_p (x
, insn
))
1072 return reg_set_between_p (x
, start
, end
);
1078 fmt
= GET_RTX_FORMAT (code
);
1079 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1081 if (fmt
[i
] == 'e' && modified_between_p (XEXP (x
, i
), start
, end
))
1084 else if (fmt
[i
] == 'E')
1085 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1086 if (modified_between_p (XVECEXP (x
, i
, j
), start
, end
))
1093 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1094 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1095 does use memory aliasing. */
1098 modified_in_p (const_rtx x
, const_rtx insn
)
1100 const enum rtx_code code
= GET_CODE (x
);
1117 if (modified_in_p (XEXP (x
, 0), insn
))
1119 if (MEM_READONLY_P (x
))
1121 if (memory_modified_in_insn_p (x
, insn
))
1127 return reg_set_p (x
, insn
);
1133 fmt
= GET_RTX_FORMAT (code
);
1134 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1136 if (fmt
[i
] == 'e' && modified_in_p (XEXP (x
, i
), insn
))
1139 else if (fmt
[i
] == 'E')
1140 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1141 if (modified_in_p (XVECEXP (x
, i
, j
), insn
))
1148 /* Helper function for set_of. */
1156 set_of_1 (rtx x
, const_rtx pat
, void *data1
)
1158 struct set_of_data
*const data
= (struct set_of_data
*) (data1
);
1159 if (rtx_equal_p (x
, data
->pat
)
1160 || (!MEM_P (x
) && reg_overlap_mentioned_p (data
->pat
, x
)))
1164 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1165 (either directly or via STRICT_LOW_PART and similar modifiers). */
1167 set_of (const_rtx pat
, const_rtx insn
)
1169 struct set_of_data data
;
1170 data
.found
= NULL_RTX
;
1172 note_stores (INSN_P (insn
) ? PATTERN (insn
) : insn
, set_of_1
, &data
);
1176 /* Add all hard register in X to *PSET. */
1178 find_all_hard_regs (const_rtx x
, HARD_REG_SET
*pset
)
1180 subrtx_iterator::array_type array
;
1181 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
1183 const_rtx x
= *iter
;
1184 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1185 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1189 /* This function, called through note_stores, collects sets and
1190 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1193 record_hard_reg_sets (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
1195 HARD_REG_SET
*pset
= (HARD_REG_SET
*)data
;
1196 if (REG_P (x
) && HARD_REGISTER_P (x
))
1197 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1200 /* Examine INSN, and compute the set of hard registers written by it.
1201 Store it in *PSET. Should only be called after reload. */
1203 find_all_hard_reg_sets (const rtx_insn
*insn
, HARD_REG_SET
*pset
, bool implicit
)
1207 CLEAR_HARD_REG_SET (*pset
);
1208 note_stores (PATTERN (insn
), record_hard_reg_sets
, pset
);
1212 IOR_HARD_REG_SET (*pset
, call_used_reg_set
);
1214 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
1215 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1217 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1218 if (REG_NOTE_KIND (link
) == REG_INC
)
1219 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1222 /* Like record_hard_reg_sets, but called through note_uses. */
1224 record_hard_reg_uses (rtx
*px
, void *data
)
1226 find_all_hard_regs (*px
, (HARD_REG_SET
*) data
);
1229 /* Given an INSN, return a SET expression if this insn has only a single SET.
1230 It may also have CLOBBERs, USEs, or SET whose output
1231 will not be used, which we ignore. */
1234 single_set_2 (const rtx_insn
*insn
, const_rtx pat
)
1237 int set_verified
= 1;
1240 if (GET_CODE (pat
) == PARALLEL
)
1242 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1244 rtx sub
= XVECEXP (pat
, 0, i
);
1245 switch (GET_CODE (sub
))
1252 /* We can consider insns having multiple sets, where all
1253 but one are dead as single set insns. In common case
1254 only single set is present in the pattern so we want
1255 to avoid checking for REG_UNUSED notes unless necessary.
1257 When we reach set first time, we just expect this is
1258 the single set we are looking for and only when more
1259 sets are found in the insn, we check them. */
1262 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (set
))
1263 && !side_effects_p (set
))
1269 set
= sub
, set_verified
= 0;
1270 else if (!find_reg_note (insn
, REG_UNUSED
, SET_DEST (sub
))
1271 || side_effects_p (sub
))
1283 /* Given an INSN, return nonzero if it has more than one SET, else return
1287 multiple_sets (const_rtx insn
)
1292 /* INSN must be an insn. */
1293 if (! INSN_P (insn
))
1296 /* Only a PARALLEL can have multiple SETs. */
1297 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1299 for (i
= 0, found
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1300 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
1302 /* If we have already found a SET, then return now. */
1310 /* Either zero or one SET. */
1314 /* Return nonzero if the destination of SET equals the source
1315 and there are no side effects. */
1318 set_noop_p (const_rtx set
)
1320 rtx src
= SET_SRC (set
);
1321 rtx dst
= SET_DEST (set
);
1323 if (dst
== pc_rtx
&& src
== pc_rtx
)
1326 if (MEM_P (dst
) && MEM_P (src
))
1327 return rtx_equal_p (dst
, src
) && !side_effects_p (dst
);
1329 if (GET_CODE (dst
) == ZERO_EXTRACT
)
1330 return rtx_equal_p (XEXP (dst
, 0), src
)
1331 && ! BYTES_BIG_ENDIAN
&& XEXP (dst
, 2) == const0_rtx
1332 && !side_effects_p (src
);
1334 if (GET_CODE (dst
) == STRICT_LOW_PART
)
1335 dst
= XEXP (dst
, 0);
1337 if (GET_CODE (src
) == SUBREG
&& GET_CODE (dst
) == SUBREG
)
1339 if (SUBREG_BYTE (src
) != SUBREG_BYTE (dst
))
1341 src
= SUBREG_REG (src
);
1342 dst
= SUBREG_REG (dst
);
1345 /* It is a NOOP if destination overlaps with selected src vector
1347 if (GET_CODE (src
) == VEC_SELECT
1348 && REG_P (XEXP (src
, 0)) && REG_P (dst
)
1349 && HARD_REGISTER_P (XEXP (src
, 0))
1350 && HARD_REGISTER_P (dst
))
1353 rtx par
= XEXP (src
, 1);
1354 rtx src0
= XEXP (src
, 0);
1355 int c0
= INTVAL (XVECEXP (par
, 0, 0));
1356 HOST_WIDE_INT offset
= GET_MODE_UNIT_SIZE (GET_MODE (src0
)) * c0
;
1358 for (i
= 1; i
< XVECLEN (par
, 0); i
++)
1359 if (INTVAL (XVECEXP (par
, 0, i
)) != c0
+ i
)
1362 simplify_subreg_regno (REGNO (src0
), GET_MODE (src0
),
1363 offset
, GET_MODE (dst
)) == (int) REGNO (dst
);
1366 return (REG_P (src
) && REG_P (dst
)
1367 && REGNO (src
) == REGNO (dst
));
1370 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1374 noop_move_p (const rtx_insn
*insn
)
1376 rtx pat
= PATTERN (insn
);
1378 if (INSN_CODE (insn
) == NOOP_MOVE_INSN_CODE
)
1381 /* Insns carrying these notes are useful later on. */
1382 if (find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1385 /* Check the code to be executed for COND_EXEC. */
1386 if (GET_CODE (pat
) == COND_EXEC
)
1387 pat
= COND_EXEC_CODE (pat
);
1389 if (GET_CODE (pat
) == SET
&& set_noop_p (pat
))
1392 if (GET_CODE (pat
) == PARALLEL
)
1395 /* If nothing but SETs of registers to themselves,
1396 this insn can also be deleted. */
1397 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1399 rtx tem
= XVECEXP (pat
, 0, i
);
1401 if (GET_CODE (tem
) == USE
1402 || GET_CODE (tem
) == CLOBBER
)
1405 if (GET_CODE (tem
) != SET
|| ! set_noop_p (tem
))
1415 /* Return nonzero if register in range [REGNO, ENDREGNO)
1416 appears either explicitly or implicitly in X
1417 other than being stored into.
1419 References contained within the substructure at LOC do not count.
1420 LOC may be zero, meaning don't ignore anything. */
1423 refers_to_regno_p (unsigned int regno
, unsigned int endregno
, const_rtx x
,
1427 unsigned int x_regno
;
1432 /* The contents of a REG_NONNEG note is always zero, so we must come here
1433 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1437 code
= GET_CODE (x
);
1442 x_regno
= REGNO (x
);
1444 /* If we modifying the stack, frame, or argument pointer, it will
1445 clobber a virtual register. In fact, we could be more precise,
1446 but it isn't worth it. */
1447 if ((x_regno
== STACK_POINTER_REGNUM
1448 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1449 || x_regno
== ARG_POINTER_REGNUM
1451 || x_regno
== FRAME_POINTER_REGNUM
)
1452 && regno
>= FIRST_VIRTUAL_REGISTER
&& regno
<= LAST_VIRTUAL_REGISTER
)
1455 return endregno
> x_regno
&& regno
< END_REGNO (x
);
1458 /* If this is a SUBREG of a hard reg, we can see exactly which
1459 registers are being modified. Otherwise, handle normally. */
1460 if (REG_P (SUBREG_REG (x
))
1461 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
1463 unsigned int inner_regno
= subreg_regno (x
);
1464 unsigned int inner_endregno
1465 = inner_regno
+ (inner_regno
< FIRST_PSEUDO_REGISTER
1466 ? subreg_nregs (x
) : 1);
1468 return endregno
> inner_regno
&& regno
< inner_endregno
;
1474 if (&SET_DEST (x
) != loc
1475 /* Note setting a SUBREG counts as referring to the REG it is in for
1476 a pseudo but not for hard registers since we can
1477 treat each word individually. */
1478 && ((GET_CODE (SET_DEST (x
)) == SUBREG
1479 && loc
!= &SUBREG_REG (SET_DEST (x
))
1480 && REG_P (SUBREG_REG (SET_DEST (x
)))
1481 && REGNO (SUBREG_REG (SET_DEST (x
))) >= FIRST_PSEUDO_REGISTER
1482 && refers_to_regno_p (regno
, endregno
,
1483 SUBREG_REG (SET_DEST (x
)), loc
))
1484 || (!REG_P (SET_DEST (x
))
1485 && refers_to_regno_p (regno
, endregno
, SET_DEST (x
), loc
))))
1488 if (code
== CLOBBER
|| loc
== &SET_SRC (x
))
1497 /* X does not match, so try its subexpressions. */
1499 fmt
= GET_RTX_FORMAT (code
);
1500 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1502 if (fmt
[i
] == 'e' && loc
!= &XEXP (x
, i
))
1510 if (refers_to_regno_p (regno
, endregno
, XEXP (x
, i
), loc
))
1513 else if (fmt
[i
] == 'E')
1516 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1517 if (loc
!= &XVECEXP (x
, i
, j
)
1518 && refers_to_regno_p (regno
, endregno
, XVECEXP (x
, i
, j
), loc
))
1525 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1526 we check if any register number in X conflicts with the relevant register
1527 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1528 contains a MEM (we don't bother checking for memory addresses that can't
1529 conflict because we expect this to be a rare case. */
1532 reg_overlap_mentioned_p (const_rtx x
, const_rtx in
)
1534 unsigned int regno
, endregno
;
1536 /* If either argument is a constant, then modifying X can not
1537 affect IN. Here we look at IN, we can profitably combine
1538 CONSTANT_P (x) with the switch statement below. */
1539 if (CONSTANT_P (in
))
1543 switch (GET_CODE (x
))
1545 case STRICT_LOW_PART
:
1548 /* Overly conservative. */
1553 regno
= REGNO (SUBREG_REG (x
));
1554 if (regno
< FIRST_PSEUDO_REGISTER
)
1555 regno
= subreg_regno (x
);
1556 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
1557 ? subreg_nregs (x
) : 1);
1562 endregno
= END_REGNO (x
);
1564 return refers_to_regno_p (regno
, endregno
, in
, (rtx
*) 0);
1574 fmt
= GET_RTX_FORMAT (GET_CODE (in
));
1575 for (i
= GET_RTX_LENGTH (GET_CODE (in
)) - 1; i
>= 0; i
--)
1578 if (reg_overlap_mentioned_p (x
, XEXP (in
, i
)))
1581 else if (fmt
[i
] == 'E')
1584 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; --j
)
1585 if (reg_overlap_mentioned_p (x
, XVECEXP (in
, i
, j
)))
1595 return reg_mentioned_p (x
, in
);
1601 /* If any register in here refers to it we return true. */
1602 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1603 if (XEXP (XVECEXP (x
, 0, i
), 0) != 0
1604 && reg_overlap_mentioned_p (XEXP (XVECEXP (x
, 0, i
), 0), in
))
1610 gcc_assert (CONSTANT_P (x
));
1615 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1616 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1617 ignored by note_stores, but passed to FUN.
1619 FUN receives three arguments:
1620 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1621 2. the SET or CLOBBER rtx that does the store,
1622 3. the pointer DATA provided to note_stores.
1624 If the item being stored in or clobbered is a SUBREG of a hard register,
1625 the SUBREG will be passed. */
1628 note_stores (const_rtx x
, void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1632 if (GET_CODE (x
) == COND_EXEC
)
1633 x
= COND_EXEC_CODE (x
);
1635 if (GET_CODE (x
) == SET
|| GET_CODE (x
) == CLOBBER
)
1637 rtx dest
= SET_DEST (x
);
1639 while ((GET_CODE (dest
) == SUBREG
1640 && (!REG_P (SUBREG_REG (dest
))
1641 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
1642 || GET_CODE (dest
) == ZERO_EXTRACT
1643 || GET_CODE (dest
) == STRICT_LOW_PART
)
1644 dest
= XEXP (dest
, 0);
1646 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1647 each of whose first operand is a register. */
1648 if (GET_CODE (dest
) == PARALLEL
)
1650 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1651 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
1652 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
1655 (*fun
) (dest
, x
, data
);
1658 else if (GET_CODE (x
) == PARALLEL
)
1659 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1660 note_stores (XVECEXP (x
, 0, i
), fun
, data
);
1663 /* Like notes_stores, but call FUN for each expression that is being
1664 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1665 FUN for each expression, not any interior subexpressions. FUN receives a
1666 pointer to the expression and the DATA passed to this function.
1668 Note that this is not quite the same test as that done in reg_referenced_p
1669 since that considers something as being referenced if it is being
1670 partially set, while we do not. */
1673 note_uses (rtx
*pbody
, void (*fun
) (rtx
*, void *), void *data
)
1678 switch (GET_CODE (body
))
1681 (*fun
) (&COND_EXEC_TEST (body
), data
);
1682 note_uses (&COND_EXEC_CODE (body
), fun
, data
);
1686 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1687 note_uses (&XVECEXP (body
, 0, i
), fun
, data
);
1691 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1692 note_uses (&PATTERN (XVECEXP (body
, 0, i
)), fun
, data
);
1696 (*fun
) (&XEXP (body
, 0), data
);
1700 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1701 (*fun
) (&ASM_OPERANDS_INPUT (body
, i
), data
);
1705 (*fun
) (&TRAP_CONDITION (body
), data
);
1709 (*fun
) (&XEXP (body
, 0), data
);
1713 case UNSPEC_VOLATILE
:
1714 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1715 (*fun
) (&XVECEXP (body
, 0, i
), data
);
1719 if (MEM_P (XEXP (body
, 0)))
1720 (*fun
) (&XEXP (XEXP (body
, 0), 0), data
);
1725 rtx dest
= SET_DEST (body
);
1727 /* For sets we replace everything in source plus registers in memory
1728 expression in store and operands of a ZERO_EXTRACT. */
1729 (*fun
) (&SET_SRC (body
), data
);
1731 if (GET_CODE (dest
) == ZERO_EXTRACT
)
1733 (*fun
) (&XEXP (dest
, 1), data
);
1734 (*fun
) (&XEXP (dest
, 2), data
);
1737 while (GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
)
1738 dest
= XEXP (dest
, 0);
1741 (*fun
) (&XEXP (dest
, 0), data
);
1746 /* All the other possibilities never store. */
1747 (*fun
) (pbody
, data
);
1752 /* Return nonzero if X's old contents don't survive after INSN.
1753 This will be true if X is (cc0) or if X is a register and
1754 X dies in INSN or because INSN entirely sets X.
1756 "Entirely set" means set directly and not through a SUBREG, or
1757 ZERO_EXTRACT, so no trace of the old contents remains.
1758 Likewise, REG_INC does not count.
1760 REG may be a hard or pseudo reg. Renumbering is not taken into account,
1761 but for this use that makes no difference, since regs don't overlap
1762 during their lifetimes. Therefore, this function may be used
1763 at any time after deaths have been computed.
1765 If REG is a hard reg that occupies multiple machine registers, this
1766 function will only return 1 if each of those registers will be replaced
1770 dead_or_set_p (const_rtx insn
, const_rtx x
)
1772 unsigned int regno
, end_regno
;
1775 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
1776 if (GET_CODE (x
) == CC0
)
1779 gcc_assert (REG_P (x
));
1782 end_regno
= END_REGNO (x
);
1783 for (i
= regno
; i
< end_regno
; i
++)
1784 if (! dead_or_set_regno_p (insn
, i
))
1790 /* Return TRUE iff DEST is a register or subreg of a register and
1791 doesn't change the number of words of the inner register, and any
1792 part of the register is TEST_REGNO. */
1795 covers_regno_no_parallel_p (const_rtx dest
, unsigned int test_regno
)
1797 unsigned int regno
, endregno
;
1799 if (GET_CODE (dest
) == SUBREG
1800 && (((GET_MODE_SIZE (GET_MODE (dest
))
1801 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
1802 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
1803 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)))
1804 dest
= SUBREG_REG (dest
);
1809 regno
= REGNO (dest
);
1810 endregno
= END_REGNO (dest
);
1811 return (test_regno
>= regno
&& test_regno
< endregno
);
1814 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
1815 any member matches the covers_regno_no_parallel_p criteria. */
1818 covers_regno_p (const_rtx dest
, unsigned int test_regno
)
1820 if (GET_CODE (dest
) == PARALLEL
)
1822 /* Some targets place small structures in registers for return
1823 values of functions, and those registers are wrapped in
1824 PARALLELs that we may see as the destination of a SET. */
1827 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1829 rtx inner
= XEXP (XVECEXP (dest
, 0, i
), 0);
1830 if (inner
!= NULL_RTX
1831 && covers_regno_no_parallel_p (inner
, test_regno
))
1838 return covers_regno_no_parallel_p (dest
, test_regno
);
1841 /* Utility function for dead_or_set_p to check an individual register. */
1844 dead_or_set_regno_p (const_rtx insn
, unsigned int test_regno
)
1848 /* See if there is a death note for something that includes TEST_REGNO. */
1849 if (find_regno_note (insn
, REG_DEAD
, test_regno
))
1853 && find_regno_fusage (insn
, CLOBBER
, test_regno
))
1856 pattern
= PATTERN (insn
);
1858 /* If a COND_EXEC is not executed, the value survives. */
1859 if (GET_CODE (pattern
) == COND_EXEC
)
1862 if (GET_CODE (pattern
) == SET
)
1863 return covers_regno_p (SET_DEST (pattern
), test_regno
);
1864 else if (GET_CODE (pattern
) == PARALLEL
)
1868 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
1870 rtx body
= XVECEXP (pattern
, 0, i
);
1872 if (GET_CODE (body
) == COND_EXEC
)
1873 body
= COND_EXEC_CODE (body
);
1875 if ((GET_CODE (body
) == SET
|| GET_CODE (body
) == CLOBBER
)
1876 && covers_regno_p (SET_DEST (body
), test_regno
))
1884 /* Return the reg-note of kind KIND in insn INSN, if there is one.
1885 If DATUM is nonzero, look for one whose datum is DATUM. */
1888 find_reg_note (const_rtx insn
, enum reg_note kind
, const_rtx datum
)
1892 gcc_checking_assert (insn
);
1894 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
1895 if (! INSN_P (insn
))
1899 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1900 if (REG_NOTE_KIND (link
) == kind
)
1905 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1906 if (REG_NOTE_KIND (link
) == kind
&& datum
== XEXP (link
, 0))
1911 /* Return the reg-note of kind KIND in insn INSN which applies to register
1912 number REGNO, if any. Return 0 if there is no such reg-note. Note that
1913 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
1914 it might be the case that the note overlaps REGNO. */
1917 find_regno_note (const_rtx insn
, enum reg_note kind
, unsigned int regno
)
1921 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
1922 if (! INSN_P (insn
))
1925 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1926 if (REG_NOTE_KIND (link
) == kind
1927 /* Verify that it is a register, so that scratch and MEM won't cause a
1929 && REG_P (XEXP (link
, 0))
1930 && REGNO (XEXP (link
, 0)) <= regno
1931 && END_REGNO (XEXP (link
, 0)) > regno
)
1936 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
1940 find_reg_equal_equiv_note (const_rtx insn
)
1947 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1948 if (REG_NOTE_KIND (link
) == REG_EQUAL
1949 || REG_NOTE_KIND (link
) == REG_EQUIV
)
1951 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
1952 insns that have multiple sets. Checking single_set to
1953 make sure of this is not the proper check, as explained
1954 in the comment in set_unique_reg_note.
1956 This should be changed into an assert. */
1957 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
1964 /* Check whether INSN is a single_set whose source is known to be
1965 equivalent to a constant. Return that constant if so, otherwise
1969 find_constant_src (const rtx_insn
*insn
)
1973 set
= single_set (insn
);
1976 x
= avoid_constant_pool_reference (SET_SRC (set
));
1981 note
= find_reg_equal_equiv_note (insn
);
1982 if (note
&& CONSTANT_P (XEXP (note
, 0)))
1983 return XEXP (note
, 0);
1988 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
1989 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
1992 find_reg_fusage (const_rtx insn
, enum rtx_code code
, const_rtx datum
)
1994 /* If it's not a CALL_INSN, it can't possibly have a
1995 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2005 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
2007 link
= XEXP (link
, 1))
2008 if (GET_CODE (XEXP (link
, 0)) == code
2009 && rtx_equal_p (datum
, XEXP (XEXP (link
, 0), 0)))
2014 unsigned int regno
= REGNO (datum
);
2016 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2017 to pseudo registers, so don't bother checking. */
2019 if (regno
< FIRST_PSEUDO_REGISTER
)
2021 unsigned int end_regno
= END_REGNO (datum
);
2024 for (i
= regno
; i
< end_regno
; i
++)
2025 if (find_regno_fusage (insn
, code
, i
))
2033 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2034 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2037 find_regno_fusage (const_rtx insn
, enum rtx_code code
, unsigned int regno
)
2041 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2042 to pseudo registers, so don't bother checking. */
2044 if (regno
>= FIRST_PSEUDO_REGISTER
2048 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
2052 if (GET_CODE (op
= XEXP (link
, 0)) == code
2053 && REG_P (reg
= XEXP (op
, 0))
2054 && REGNO (reg
) <= regno
2055 && END_REGNO (reg
) > regno
)
2063 /* Return true if KIND is an integer REG_NOTE. */
2066 int_reg_note_p (enum reg_note kind
)
2068 return kind
== REG_BR_PROB
;
2071 /* Allocate a register note with kind KIND and datum DATUM. LIST is
2072 stored as the pointer to the next register note. */
2075 alloc_reg_note (enum reg_note kind
, rtx datum
, rtx list
)
2079 gcc_checking_assert (!int_reg_note_p (kind
));
2084 case REG_LABEL_TARGET
:
2085 case REG_LABEL_OPERAND
:
2087 /* These types of register notes use an INSN_LIST rather than an
2088 EXPR_LIST, so that copying is done right and dumps look
2090 note
= alloc_INSN_LIST (datum
, list
);
2091 PUT_REG_NOTE_KIND (note
, kind
);
2095 note
= alloc_EXPR_LIST (kind
, datum
, list
);
2102 /* Add register note with kind KIND and datum DATUM to INSN. */
2105 add_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
2107 REG_NOTES (insn
) = alloc_reg_note (kind
, datum
, REG_NOTES (insn
));
2110 /* Add an integer register note with kind KIND and datum DATUM to INSN. */
2113 add_int_reg_note (rtx insn
, enum reg_note kind
, int datum
)
2115 gcc_checking_assert (int_reg_note_p (kind
));
2116 REG_NOTES (insn
) = gen_rtx_INT_LIST ((machine_mode
) kind
,
2117 datum
, REG_NOTES (insn
));
2120 /* Add a register note like NOTE to INSN. */
2123 add_shallow_copy_of_reg_note (rtx_insn
*insn
, rtx note
)
2125 if (GET_CODE (note
) == INT_LIST
)
2126 add_int_reg_note (insn
, REG_NOTE_KIND (note
), XINT (note
, 0));
2128 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
2131 /* Remove register note NOTE from the REG_NOTES of INSN. */
2134 remove_note (rtx insn
, const_rtx note
)
2138 if (note
== NULL_RTX
)
2141 if (REG_NOTES (insn
) == note
)
2142 REG_NOTES (insn
) = XEXP (note
, 1);
2144 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2145 if (XEXP (link
, 1) == note
)
2147 XEXP (link
, 1) = XEXP (note
, 1);
2151 switch (REG_NOTE_KIND (note
))
2155 df_notes_rescan (as_a
<rtx_insn
*> (insn
));
2162 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes. */
2165 remove_reg_equal_equiv_notes (rtx_insn
*insn
)
2169 loc
= ®_NOTES (insn
);
2172 enum reg_note kind
= REG_NOTE_KIND (*loc
);
2173 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
2174 *loc
= XEXP (*loc
, 1);
2176 loc
= &XEXP (*loc
, 1);
2180 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2183 remove_reg_equal_equiv_notes_for_regno (unsigned int regno
)
2190 /* This loop is a little tricky. We cannot just go down the chain because
2191 it is being modified by some actions in the loop. So we just iterate
2192 over the head. We plan to drain the list anyway. */
2193 while ((eq_use
= DF_REG_EQ_USE_CHAIN (regno
)) != NULL
)
2195 rtx_insn
*insn
= DF_REF_INSN (eq_use
);
2196 rtx note
= find_reg_equal_equiv_note (insn
);
2198 /* This assert is generally triggered when someone deletes a REG_EQUAL
2199 or REG_EQUIV note by hacking the list manually rather than calling
2203 remove_note (insn
, note
);
2207 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2208 return 1 if it is found. A simple equality test is used to determine if
2212 in_insn_list_p (const rtx_insn_list
*listp
, const rtx_insn
*node
)
2216 for (x
= listp
; x
; x
= XEXP (x
, 1))
2217 if (node
== XEXP (x
, 0))
2223 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2224 remove that entry from the list if it is found.
2226 A simple equality test is used to determine if NODE matches. */
2229 remove_node_from_expr_list (const_rtx node
, rtx_expr_list
**listp
)
2231 rtx_expr_list
*temp
= *listp
;
2232 rtx prev
= NULL_RTX
;
2236 if (node
== temp
->element ())
2238 /* Splice the node out of the list. */
2240 XEXP (prev
, 1) = temp
->next ();
2242 *listp
= temp
->next ();
2248 temp
= temp
->next ();
2252 /* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2253 remove that entry from the list if it is found.
2255 A simple equality test is used to determine if NODE matches. */
2258 remove_node_from_insn_list (const rtx_insn
*node
, rtx_insn_list
**listp
)
2260 rtx_insn_list
*temp
= *listp
;
2265 if (node
== temp
->insn ())
2267 /* Splice the node out of the list. */
2269 XEXP (prev
, 1) = temp
->next ();
2271 *listp
= temp
->next ();
2277 temp
= temp
->next ();
2281 /* Nonzero if X contains any volatile instructions. These are instructions
2282 which may cause unpredictable machine state instructions, and thus no
2283 instructions or register uses should be moved or combined across them.
2284 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2287 volatile_insn_p (const_rtx x
)
2289 const RTX_CODE code
= GET_CODE (x
);
2307 case UNSPEC_VOLATILE
:
2312 if (MEM_VOLATILE_P (x
))
2319 /* Recursively scan the operands of this expression. */
2322 const char *const fmt
= GET_RTX_FORMAT (code
);
2325 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2329 if (volatile_insn_p (XEXP (x
, i
)))
2332 else if (fmt
[i
] == 'E')
2335 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2336 if (volatile_insn_p (XVECEXP (x
, i
, j
)))
2344 /* Nonzero if X contains any volatile memory references
2345 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2348 volatile_refs_p (const_rtx x
)
2350 const RTX_CODE code
= GET_CODE (x
);
2366 case UNSPEC_VOLATILE
:
2372 if (MEM_VOLATILE_P (x
))
2379 /* Recursively scan the operands of this expression. */
2382 const char *const fmt
= GET_RTX_FORMAT (code
);
2385 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2389 if (volatile_refs_p (XEXP (x
, i
)))
2392 else if (fmt
[i
] == 'E')
2395 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2396 if (volatile_refs_p (XVECEXP (x
, i
, j
)))
2404 /* Similar to above, except that it also rejects register pre- and post-
2408 side_effects_p (const_rtx x
)
2410 const RTX_CODE code
= GET_CODE (x
);
2427 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2428 when some combination can't be done. If we see one, don't think
2429 that we can simplify the expression. */
2430 return (GET_MODE (x
) != VOIDmode
);
2439 case UNSPEC_VOLATILE
:
2445 if (MEM_VOLATILE_P (x
))
2452 /* Recursively scan the operands of this expression. */
2455 const char *fmt
= GET_RTX_FORMAT (code
);
2458 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2462 if (side_effects_p (XEXP (x
, i
)))
2465 else if (fmt
[i
] == 'E')
2468 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2469 if (side_effects_p (XVECEXP (x
, i
, j
)))
2477 /* Return nonzero if evaluating rtx X might cause a trap.
2478 FLAGS controls how to consider MEMs. A nonzero means the context
2479 of the access may have changed from the original, such that the
2480 address may have become invalid. */
2483 may_trap_p_1 (const_rtx x
, unsigned flags
)
2489 /* We make no distinction currently, but this function is part of
2490 the internal target-hooks ABI so we keep the parameter as
2491 "unsigned flags". */
2492 bool code_changed
= flags
!= 0;
2496 code
= GET_CODE (x
);
2499 /* Handle these cases quickly. */
2511 return targetm
.unspec_may_trap_p (x
, flags
);
2513 case UNSPEC_VOLATILE
:
2519 return MEM_VOLATILE_P (x
);
2521 /* Memory ref can trap unless it's a static var or a stack slot. */
2523 /* Recognize specific pattern of stack checking probes. */
2524 if (flag_stack_check
2525 && MEM_VOLATILE_P (x
)
2526 && XEXP (x
, 0) == stack_pointer_rtx
)
2528 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
2529 reference; moving it out of context such as when moving code
2530 when optimizing, might cause its address to become invalid. */
2532 || !MEM_NOTRAP_P (x
))
2534 HOST_WIDE_INT size
= MEM_SIZE_KNOWN_P (x
) ? MEM_SIZE (x
) : 0;
2535 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), 0, size
,
2536 GET_MODE (x
), code_changed
);
2541 /* Division by a non-constant might trap. */
2546 if (HONOR_SNANS (x
))
2548 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)))
2549 return flag_trapping_math
;
2550 if (!CONSTANT_P (XEXP (x
, 1)) || (XEXP (x
, 1) == const0_rtx
))
2555 /* An EXPR_LIST is used to represent a function call. This
2556 certainly may trap. */
2565 /* Some floating point comparisons may trap. */
2566 if (!flag_trapping_math
)
2568 /* ??? There is no machine independent way to check for tests that trap
2569 when COMPARE is used, though many targets do make this distinction.
2570 For instance, sparc uses CCFPE for compares which generate exceptions
2571 and CCFP for compares which do not generate exceptions. */
2574 /* But often the compare has some CC mode, so check operand
2576 if (HONOR_NANS (XEXP (x
, 0))
2577 || HONOR_NANS (XEXP (x
, 1)))
2583 if (HONOR_SNANS (x
))
2585 /* Often comparison is CC mode, so check operand modes. */
2586 if (HONOR_SNANS (XEXP (x
, 0))
2587 || HONOR_SNANS (XEXP (x
, 1)))
2592 /* Conversion of floating point might trap. */
2593 if (flag_trapping_math
&& HONOR_NANS (XEXP (x
, 0)))
2600 /* These operations don't trap even with floating point. */
2604 /* Any floating arithmetic may trap. */
2605 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)) && flag_trapping_math
)
2609 fmt
= GET_RTX_FORMAT (code
);
2610 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2614 if (may_trap_p_1 (XEXP (x
, i
), flags
))
2617 else if (fmt
[i
] == 'E')
2620 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2621 if (may_trap_p_1 (XVECEXP (x
, i
, j
), flags
))
2628 /* Return nonzero if evaluating rtx X might cause a trap. */
2631 may_trap_p (const_rtx x
)
2633 return may_trap_p_1 (x
, 0);
2636 /* Same as above, but additionally return nonzero if evaluating rtx X might
2637 cause a fault. We define a fault for the purpose of this function as a
2638 erroneous execution condition that cannot be encountered during the normal
2639 execution of a valid program; the typical example is an unaligned memory
2640 access on a strict alignment machine. The compiler guarantees that it
2641 doesn't generate code that will fault from a valid program, but this
2642 guarantee doesn't mean anything for individual instructions. Consider
2643 the following example:
2645 struct S { int d; union { char *cp; int *ip; }; };
2647 int foo(struct S *s)
2655 on a strict alignment machine. In a valid program, foo will never be
2656 invoked on a structure for which d is equal to 1 and the underlying
2657 unique field of the union not aligned on a 4-byte boundary, but the
2658 expression *s->ip might cause a fault if considered individually.
2660 At the RTL level, potentially problematic expressions will almost always
2661 verify may_trap_p; for example, the above dereference can be emitted as
2662 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
2663 However, suppose that foo is inlined in a caller that causes s->cp to
2664 point to a local character variable and guarantees that s->d is not set
2665 to 1; foo may have been effectively translated into pseudo-RTL as:
2668 (set (reg:SI) (mem:SI (%fp - 7)))
2670 (set (reg:QI) (mem:QI (%fp - 7)))
2672 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
2673 memory reference to a stack slot, but it will certainly cause a fault
2674 on a strict alignment machine. */
2677 may_trap_or_fault_p (const_rtx x
)
2679 return may_trap_p_1 (x
, 1);
2682 /* Return nonzero if X contains a comparison that is not either EQ or NE,
2683 i.e., an inequality. */
2686 inequality_comparisons_p (const_rtx x
)
2690 const enum rtx_code code
= GET_CODE (x
);
2718 len
= GET_RTX_LENGTH (code
);
2719 fmt
= GET_RTX_FORMAT (code
);
2721 for (i
= 0; i
< len
; i
++)
2725 if (inequality_comparisons_p (XEXP (x
, i
)))
2728 else if (fmt
[i
] == 'E')
2731 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2732 if (inequality_comparisons_p (XVECEXP (x
, i
, j
)))
2740 /* Replace any occurrence of FROM in X with TO. The function does
2741 not enter into CONST_DOUBLE for the replace.
2743 Note that copying is not done so X must not be shared unless all copies
2744 are to be modified. */
2747 replace_rtx (rtx x
, rtx from
, rtx to
)
2755 /* Allow this function to make replacements in EXPR_LISTs. */
2759 if (GET_CODE (x
) == SUBREG
)
2761 rtx new_rtx
= replace_rtx (SUBREG_REG (x
), from
, to
);
2763 if (CONST_INT_P (new_rtx
))
2765 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
2766 GET_MODE (SUBREG_REG (x
)),
2771 SUBREG_REG (x
) = new_rtx
;
2775 else if (GET_CODE (x
) == ZERO_EXTEND
)
2777 rtx new_rtx
= replace_rtx (XEXP (x
, 0), from
, to
);
2779 if (CONST_INT_P (new_rtx
))
2781 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
2782 new_rtx
, GET_MODE (XEXP (x
, 0)));
2786 XEXP (x
, 0) = new_rtx
;
2791 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
2792 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
2795 XEXP (x
, i
) = replace_rtx (XEXP (x
, i
), from
, to
);
2796 else if (fmt
[i
] == 'E')
2797 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2798 XVECEXP (x
, i
, j
) = replace_rtx (XVECEXP (x
, i
, j
), from
, to
);
2804 /* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
2805 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
2808 replace_label (rtx
*loc
, rtx old_label
, rtx new_label
, bool update_label_nuses
)
2810 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
2812 if (JUMP_TABLE_DATA_P (x
))
2815 rtvec vec
= XVEC (x
, GET_CODE (x
) == ADDR_DIFF_VEC
);
2816 int len
= GET_NUM_ELEM (vec
);
2817 for (int i
= 0; i
< len
; ++i
)
2819 rtx ref
= RTVEC_ELT (vec
, i
);
2820 if (XEXP (ref
, 0) == old_label
)
2822 XEXP (ref
, 0) = new_label
;
2823 if (update_label_nuses
)
2825 ++LABEL_NUSES (new_label
);
2826 --LABEL_NUSES (old_label
);
2833 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
2834 field. This is not handled by the iterator because it doesn't
2835 handle unprinted ('0') fields. */
2836 if (JUMP_P (x
) && JUMP_LABEL (x
) == old_label
)
2837 JUMP_LABEL (x
) = new_label
;
2839 subrtx_ptr_iterator::array_type array
;
2840 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
2845 if (GET_CODE (x
) == SYMBOL_REF
2846 && CONSTANT_POOL_ADDRESS_P (x
))
2848 rtx c
= get_pool_constant (x
);
2849 if (rtx_referenced_p (old_label
, c
))
2851 /* Create a copy of constant C; replace the label inside
2852 but do not update LABEL_NUSES because uses in constant pool
2854 rtx new_c
= copy_rtx (c
);
2855 replace_label (&new_c
, old_label
, new_label
, false);
2857 /* Add the new constant NEW_C to constant pool and replace
2858 the old reference to constant by new reference. */
2859 rtx new_mem
= force_const_mem (get_pool_mode (x
), new_c
);
2860 *loc
= replace_rtx (x
, x
, XEXP (new_mem
, 0));
2864 if ((GET_CODE (x
) == LABEL_REF
2865 || GET_CODE (x
) == INSN_LIST
)
2866 && XEXP (x
, 0) == old_label
)
2868 XEXP (x
, 0) = new_label
;
2869 if (update_label_nuses
)
2871 ++LABEL_NUSES (new_label
);
2872 --LABEL_NUSES (old_label
);
2880 replace_label_in_insn (rtx_insn
*insn
, rtx old_label
, rtx new_label
,
2881 bool update_label_nuses
)
2883 rtx insn_as_rtx
= insn
;
2884 replace_label (&insn_as_rtx
, old_label
, new_label
, update_label_nuses
);
2885 gcc_checking_assert (insn_as_rtx
== insn
);
2888 /* Return true if X is referenced in BODY. */
2891 rtx_referenced_p (const_rtx x
, const_rtx body
)
2893 subrtx_iterator::array_type array
;
2894 FOR_EACH_SUBRTX (iter
, array
, body
, ALL
)
2895 if (const_rtx y
= *iter
)
2897 /* Check if a label_ref Y refers to label X. */
2898 if (GET_CODE (y
) == LABEL_REF
2900 && LABEL_REF_LABEL (y
) == x
)
2903 if (rtx_equal_p (x
, y
))
2906 /* If Y is a reference to pool constant traverse the constant. */
2907 if (GET_CODE (y
) == SYMBOL_REF
2908 && CONSTANT_POOL_ADDRESS_P (y
))
2909 iter
.substitute (get_pool_constant (y
));
2914 /* If INSN is a tablejump return true and store the label (before jump table) to
2915 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
2918 tablejump_p (const rtx_insn
*insn
, rtx
*labelp
, rtx_jump_table_data
**tablep
)
2926 label
= JUMP_LABEL (insn
);
2927 if (label
!= NULL_RTX
&& !ANY_RETURN_P (label
)
2928 && (table
= NEXT_INSN (as_a
<rtx_insn
*> (label
))) != NULL_RTX
2929 && JUMP_TABLE_DATA_P (table
))
2934 *tablep
= as_a
<rtx_jump_table_data
*> (table
);
2940 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
2941 constant that is not in the constant pool and not in the condition
2942 of an IF_THEN_ELSE. */
2945 computed_jump_p_1 (const_rtx x
)
2947 const enum rtx_code code
= GET_CODE (x
);
2964 return ! (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
2965 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
2968 return (computed_jump_p_1 (XEXP (x
, 1))
2969 || computed_jump_p_1 (XEXP (x
, 2)));
2975 fmt
= GET_RTX_FORMAT (code
);
2976 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2979 && computed_jump_p_1 (XEXP (x
, i
)))
2982 else if (fmt
[i
] == 'E')
2983 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2984 if (computed_jump_p_1 (XVECEXP (x
, i
, j
)))
2991 /* Return nonzero if INSN is an indirect jump (aka computed jump).
2993 Tablejumps and casesi insns are not considered indirect jumps;
2994 we can recognize them by a (use (label_ref)). */
2997 computed_jump_p (const rtx_insn
*insn
)
3002 rtx pat
= PATTERN (insn
);
3004 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3005 if (JUMP_LABEL (insn
) != NULL
)
3008 if (GET_CODE (pat
) == PARALLEL
)
3010 int len
= XVECLEN (pat
, 0);
3011 int has_use_labelref
= 0;
3013 for (i
= len
- 1; i
>= 0; i
--)
3014 if (GET_CODE (XVECEXP (pat
, 0, i
)) == USE
3015 && (GET_CODE (XEXP (XVECEXP (pat
, 0, i
), 0))
3018 has_use_labelref
= 1;
3022 if (! has_use_labelref
)
3023 for (i
= len
- 1; i
>= 0; i
--)
3024 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
3025 && SET_DEST (XVECEXP (pat
, 0, i
)) == pc_rtx
3026 && computed_jump_p_1 (SET_SRC (XVECEXP (pat
, 0, i
))))
3029 else if (GET_CODE (pat
) == SET
3030 && SET_DEST (pat
) == pc_rtx
3031 && computed_jump_p_1 (SET_SRC (pat
)))
3039 /* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3040 the equivalent add insn and pass the result to FN, using DATA as the
3044 for_each_inc_dec_find_inc_dec (rtx mem
, for_each_inc_dec_fn fn
, void *data
)
3046 rtx x
= XEXP (mem
, 0);
3047 switch (GET_CODE (x
))
3052 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3053 rtx r1
= XEXP (x
, 0);
3054 rtx c
= gen_int_mode (size
, GET_MODE (r1
));
3055 return fn (mem
, x
, r1
, r1
, c
, data
);
3061 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3062 rtx r1
= XEXP (x
, 0);
3063 rtx c
= gen_int_mode (-size
, GET_MODE (r1
));
3064 return fn (mem
, x
, r1
, r1
, c
, data
);
3070 rtx r1
= XEXP (x
, 0);
3071 rtx add
= XEXP (x
, 1);
3072 return fn (mem
, x
, r1
, add
, NULL
, data
);
3080 /* Traverse *LOC looking for MEMs that have autoinc addresses.
3081 For each such autoinc operation found, call FN, passing it
3082 the innermost enclosing MEM, the operation itself, the RTX modified
3083 by the operation, two RTXs (the second may be NULL) that, once
3084 added, represent the value to be held by the modified RTX
3085 afterwards, and DATA. FN is to return 0 to continue the
3086 traversal or any other value to have it returned to the caller of
3087 for_each_inc_dec. */
3090 for_each_inc_dec (rtx x
,
3091 for_each_inc_dec_fn fn
,
3094 subrtx_var_iterator::array_type array
;
3095 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
3100 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
3102 int res
= for_each_inc_dec_find_inc_dec (mem
, fn
, data
);
3105 iter
.skip_subrtxes ();
3112 /* Searches X for any reference to REGNO, returning the rtx of the
3113 reference found if any. Otherwise, returns NULL_RTX. */
3116 regno_use_in (unsigned int regno
, rtx x
)
3122 if (REG_P (x
) && REGNO (x
) == regno
)
3125 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3126 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3130 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
3133 else if (fmt
[i
] == 'E')
3134 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3135 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
3142 /* Return a value indicating whether OP, an operand of a commutative
3143 operation, is preferred as the first or second operand. The higher
3144 the value, the stronger the preference for being the first operand.
3145 We use negative values to indicate a preference for the first operand
3146 and positive values for the second operand. */
3149 commutative_operand_precedence (rtx op
)
3151 enum rtx_code code
= GET_CODE (op
);
3153 /* Constants always come the second operand. Prefer "nice" constants. */
3154 if (code
== CONST_INT
)
3156 if (code
== CONST_WIDE_INT
)
3158 if (code
== CONST_DOUBLE
)
3160 if (code
== CONST_FIXED
)
3162 op
= avoid_constant_pool_reference (op
);
3163 code
= GET_CODE (op
);
3165 switch (GET_RTX_CLASS (code
))
3168 if (code
== CONST_INT
)
3170 if (code
== CONST_WIDE_INT
)
3172 if (code
== CONST_DOUBLE
)
3174 if (code
== CONST_FIXED
)
3179 /* SUBREGs of objects should come second. */
3180 if (code
== SUBREG
&& OBJECT_P (SUBREG_REG (op
)))
3185 /* Complex expressions should be the first, so decrease priority
3186 of objects. Prefer pointer objects over non pointer objects. */
3187 if ((REG_P (op
) && REG_POINTER (op
))
3188 || (MEM_P (op
) && MEM_POINTER (op
)))
3192 case RTX_COMM_ARITH
:
3193 /* Prefer operands that are themselves commutative to be first.
3194 This helps to make things linear. In particular,
3195 (and (and (reg) (reg)) (not (reg))) is canonical. */
3199 /* If only one operand is a binary expression, it will be the first
3200 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3201 is canonical, although it will usually be further simplified. */
3205 /* Then prefer NEG and NOT. */
3206 if (code
== NEG
|| code
== NOT
)
3214 /* Return 1 iff it is necessary to swap operands of commutative operation
3215 in order to canonicalize expression. */
3218 swap_commutative_operands_p (rtx x
, rtx y
)
3220 return (commutative_operand_precedence (x
)
3221 < commutative_operand_precedence (y
));
3224 /* Return 1 if X is an autoincrement side effect and the register is
3225 not the stack pointer. */
3227 auto_inc_p (const_rtx x
)
3229 switch (GET_CODE (x
))
3237 /* There are no REG_INC notes for SP. */
3238 if (XEXP (x
, 0) != stack_pointer_rtx
)
3246 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3248 loc_mentioned_in_p (rtx
*loc
, const_rtx in
)
3257 code
= GET_CODE (in
);
3258 fmt
= GET_RTX_FORMAT (code
);
3259 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3263 if (loc
== &XEXP (in
, i
) || loc_mentioned_in_p (loc
, XEXP (in
, i
)))
3266 else if (fmt
[i
] == 'E')
3267 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
3268 if (loc
== &XVECEXP (in
, i
, j
)
3269 || loc_mentioned_in_p (loc
, XVECEXP (in
, i
, j
)))
3275 /* Helper function for subreg_lsb. Given a subreg's OUTER_MODE, INNER_MODE,
3276 and SUBREG_BYTE, return the bit offset where the subreg begins
3277 (counting from the least significant bit of the operand). */
3280 subreg_lsb_1 (machine_mode outer_mode
,
3281 machine_mode inner_mode
,
3282 unsigned int subreg_byte
)
3284 unsigned int bitpos
;
3288 /* A paradoxical subreg begins at bit position 0. */
3289 if (GET_MODE_PRECISION (outer_mode
) > GET_MODE_PRECISION (inner_mode
))
3292 if (WORDS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
3293 /* If the subreg crosses a word boundary ensure that
3294 it also begins and ends on a word boundary. */
3295 gcc_assert (!((subreg_byte
% UNITS_PER_WORD
3296 + GET_MODE_SIZE (outer_mode
)) > UNITS_PER_WORD
3297 && (subreg_byte
% UNITS_PER_WORD
3298 || GET_MODE_SIZE (outer_mode
) % UNITS_PER_WORD
)));
3300 if (WORDS_BIG_ENDIAN
)
3301 word
= (GET_MODE_SIZE (inner_mode
)
3302 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) / UNITS_PER_WORD
;
3304 word
= subreg_byte
/ UNITS_PER_WORD
;
3305 bitpos
= word
* BITS_PER_WORD
;
3307 if (BYTES_BIG_ENDIAN
)
3308 byte
= (GET_MODE_SIZE (inner_mode
)
3309 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) % UNITS_PER_WORD
;
3311 byte
= subreg_byte
% UNITS_PER_WORD
;
3312 bitpos
+= byte
* BITS_PER_UNIT
;
3317 /* Given a subreg X, return the bit offset where the subreg begins
3318 (counting from the least significant bit of the reg). */
3321 subreg_lsb (const_rtx x
)
3323 return subreg_lsb_1 (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
3327 /* Fill in information about a subreg of a hard register.
3328 xregno - A regno of an inner hard subreg_reg (or what will become one).
3329 xmode - The mode of xregno.
3330 offset - The byte offset.
3331 ymode - The mode of a top level SUBREG (or what may become one).
3332 info - Pointer to structure to fill in.
3334 Rather than considering one particular inner register (and thus one
3335 particular "outer" register) in isolation, this function really uses
3336 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
3337 function does not check whether adding INFO->offset to XREGNO gives
3338 a valid hard register; even if INFO->offset + XREGNO is out of range,
3339 there might be another register of the same type that is in range.
3340 Likewise it doesn't check whether HARD_REGNO_MODE_OK accepts the new
3341 register, since that can depend on things like whether the final
3342 register number is even or odd. Callers that want to check whether
3343 this particular subreg can be replaced by a simple (reg ...) should
3344 use simplify_subreg_regno. */
3347 subreg_get_info (unsigned int xregno
, machine_mode xmode
,
3348 unsigned int offset
, machine_mode ymode
,
3349 struct subreg_info
*info
)
3351 int nregs_xmode
, nregs_ymode
;
3352 int mode_multiple
, nregs_multiple
;
3353 int offset_adj
, y_offset
, y_offset_adj
;
3354 int regsize_xmode
, regsize_ymode
;
3357 gcc_assert (xregno
< FIRST_PSEUDO_REGISTER
);
3361 /* If there are holes in a non-scalar mode in registers, we expect
3362 that it is made up of its units concatenated together. */
3363 if (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
))
3365 machine_mode xmode_unit
;
3367 nregs_xmode
= HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode
);
3368 if (GET_MODE_INNER (xmode
) == VOIDmode
)
3371 xmode_unit
= GET_MODE_INNER (xmode
);
3372 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode_unit
));
3373 gcc_assert (nregs_xmode
3374 == (GET_MODE_NUNITS (xmode
)
3375 * HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode_unit
)));
3376 gcc_assert (hard_regno_nregs
[xregno
][xmode
]
3377 == (hard_regno_nregs
[xregno
][xmode_unit
]
3378 * GET_MODE_NUNITS (xmode
)));
3380 /* You can only ask for a SUBREG of a value with holes in the middle
3381 if you don't cross the holes. (Such a SUBREG should be done by
3382 picking a different register class, or doing it in memory if
3383 necessary.) An example of a value with holes is XCmode on 32-bit
3384 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3385 3 for each part, but in memory it's two 128-bit parts.
3386 Padding is assumed to be at the end (not necessarily the 'high part')
3388 if ((offset
/ GET_MODE_SIZE (xmode_unit
) + 1
3389 < GET_MODE_NUNITS (xmode
))
3390 && (offset
/ GET_MODE_SIZE (xmode_unit
)
3391 != ((offset
+ GET_MODE_SIZE (ymode
) - 1)
3392 / GET_MODE_SIZE (xmode_unit
))))
3394 info
->representable_p
= false;
3399 nregs_xmode
= hard_regno_nregs
[xregno
][xmode
];
3401 nregs_ymode
= hard_regno_nregs
[xregno
][ymode
];
3403 /* Paradoxical subregs are otherwise valid. */
3406 && GET_MODE_PRECISION (ymode
) > GET_MODE_PRECISION (xmode
))
3408 info
->representable_p
= true;
3409 /* If this is a big endian paradoxical subreg, which uses more
3410 actual hard registers than the original register, we must
3411 return a negative offset so that we find the proper highpart
3413 if (GET_MODE_SIZE (ymode
) > UNITS_PER_WORD
3414 ? REG_WORDS_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
3415 info
->offset
= nregs_xmode
- nregs_ymode
;
3418 info
->nregs
= nregs_ymode
;
3422 /* If registers store different numbers of bits in the different
3423 modes, we cannot generally form this subreg. */
3424 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
)
3425 && !HARD_REGNO_NREGS_HAS_PADDING (xregno
, ymode
)
3426 && (GET_MODE_SIZE (xmode
) % nregs_xmode
) == 0
3427 && (GET_MODE_SIZE (ymode
) % nregs_ymode
) == 0)
3429 regsize_xmode
= GET_MODE_SIZE (xmode
) / nregs_xmode
;
3430 regsize_ymode
= GET_MODE_SIZE (ymode
) / nregs_ymode
;
3431 if (!rknown
&& regsize_xmode
> regsize_ymode
&& nregs_ymode
> 1)
3433 info
->representable_p
= false;
3435 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3436 info
->offset
= offset
/ regsize_xmode
;
3439 if (!rknown
&& regsize_ymode
> regsize_xmode
&& nregs_xmode
> 1)
3441 info
->representable_p
= false;
3443 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3444 info
->offset
= offset
/ regsize_xmode
;
3447 /* Quick exit for the simple and common case of extracting whole
3448 subregisters from a multiregister value. */
3449 /* ??? It would be better to integrate this into the code below,
3450 if we can generalize the concept enough and figure out how
3451 odd-sized modes can coexist with the other weird cases we support. */
3453 && WORDS_BIG_ENDIAN
== REG_WORDS_BIG_ENDIAN
3454 && regsize_xmode
== regsize_ymode
3455 && (offset
% regsize_ymode
) == 0)
3457 info
->representable_p
= true;
3458 info
->nregs
= nregs_ymode
;
3459 info
->offset
= offset
/ regsize_ymode
;
3460 gcc_assert (info
->offset
+ info
->nregs
<= nregs_xmode
);
3465 /* Lowpart subregs are otherwise valid. */
3466 if (!rknown
&& offset
== subreg_lowpart_offset (ymode
, xmode
))
3468 info
->representable_p
= true;
3471 if (offset
== 0 || nregs_xmode
== nregs_ymode
)
3474 info
->nregs
= nregs_ymode
;
3479 /* This should always pass, otherwise we don't know how to verify
3480 the constraint. These conditions may be relaxed but
3481 subreg_regno_offset would need to be redesigned. */
3482 gcc_assert ((GET_MODE_SIZE (xmode
) % GET_MODE_SIZE (ymode
)) == 0);
3483 gcc_assert ((nregs_xmode
% nregs_ymode
) == 0);
3485 if (WORDS_BIG_ENDIAN
!= REG_WORDS_BIG_ENDIAN
3486 && GET_MODE_SIZE (xmode
) > UNITS_PER_WORD
)
3488 HOST_WIDE_INT xsize
= GET_MODE_SIZE (xmode
);
3489 HOST_WIDE_INT ysize
= GET_MODE_SIZE (ymode
);
3490 HOST_WIDE_INT off_low
= offset
& (ysize
- 1);
3491 HOST_WIDE_INT off_high
= offset
& ~(ysize
- 1);
3492 offset
= (xsize
- ysize
- off_high
) | off_low
;
3494 /* The XMODE value can be seen as a vector of NREGS_XMODE
3495 values. The subreg must represent a lowpart of given field.
3496 Compute what field it is. */
3497 offset_adj
= offset
;
3498 offset_adj
-= subreg_lowpart_offset (ymode
,
3499 mode_for_size (GET_MODE_BITSIZE (xmode
)
3503 /* Size of ymode must not be greater than the size of xmode. */
3504 mode_multiple
= GET_MODE_SIZE (xmode
) / GET_MODE_SIZE (ymode
);
3505 gcc_assert (mode_multiple
!= 0);
3507 y_offset
= offset
/ GET_MODE_SIZE (ymode
);
3508 y_offset_adj
= offset_adj
/ GET_MODE_SIZE (ymode
);
3509 nregs_multiple
= nregs_xmode
/ nregs_ymode
;
3511 gcc_assert ((offset_adj
% GET_MODE_SIZE (ymode
)) == 0);
3512 gcc_assert ((mode_multiple
% nregs_multiple
) == 0);
3516 info
->representable_p
= (!(y_offset_adj
% (mode_multiple
/ nregs_multiple
)));
3519 info
->offset
= (y_offset
/ (mode_multiple
/ nregs_multiple
)) * nregs_ymode
;
3520 info
->nregs
= nregs_ymode
;
3523 /* This function returns the regno offset of a subreg expression.
3524 xregno - A regno of an inner hard subreg_reg (or what will become one).
3525 xmode - The mode of xregno.
3526 offset - The byte offset.
3527 ymode - The mode of a top level SUBREG (or what may become one).
3528 RETURN - The regno offset which would be used. */
3530 subreg_regno_offset (unsigned int xregno
, machine_mode xmode
,
3531 unsigned int offset
, machine_mode ymode
)
3533 struct subreg_info info
;
3534 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3538 /* This function returns true when the offset is representable via
3539 subreg_offset in the given regno.
3540 xregno - A regno of an inner hard subreg_reg (or what will become one).
3541 xmode - The mode of xregno.
3542 offset - The byte offset.
3543 ymode - The mode of a top level SUBREG (or what may become one).
3544 RETURN - Whether the offset is representable. */
3546 subreg_offset_representable_p (unsigned int xregno
, machine_mode xmode
,
3547 unsigned int offset
, machine_mode ymode
)
3549 struct subreg_info info
;
3550 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3551 return info
.representable_p
;
3554 /* Return the number of a YMODE register to which
3556 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
3558 can be simplified. Return -1 if the subreg can't be simplified.
3560 XREGNO is a hard register number. */
3563 simplify_subreg_regno (unsigned int xregno
, machine_mode xmode
,
3564 unsigned int offset
, machine_mode ymode
)
3566 struct subreg_info info
;
3567 unsigned int yregno
;
3569 #ifdef CANNOT_CHANGE_MODE_CLASS
3570 /* Give the backend a chance to disallow the mode change. */
3571 if (GET_MODE_CLASS (xmode
) != MODE_COMPLEX_INT
3572 && GET_MODE_CLASS (xmode
) != MODE_COMPLEX_FLOAT
3573 && REG_CANNOT_CHANGE_MODE_P (xregno
, xmode
, ymode
)
3574 /* We can use mode change in LRA for some transformations. */
3575 && ! lra_in_progress
)
3579 /* We shouldn't simplify stack-related registers. */
3580 if ((!reload_completed
|| frame_pointer_needed
)
3581 && xregno
== FRAME_POINTER_REGNUM
)
3584 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
3585 && xregno
== ARG_POINTER_REGNUM
)
3588 if (xregno
== STACK_POINTER_REGNUM
3589 /* We should convert hard stack register in LRA if it is
3591 && ! lra_in_progress
)
3594 /* Try to get the register offset. */
3595 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3596 if (!info
.representable_p
)
3599 /* Make sure that the offsetted register value is in range. */
3600 yregno
= xregno
+ info
.offset
;
3601 if (!HARD_REGISTER_NUM_P (yregno
))
3604 /* See whether (reg:YMODE YREGNO) is valid.
3606 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
3607 This is a kludge to work around how complex FP arguments are passed
3608 on IA-64 and should be fixed. See PR target/49226. */
3609 if (!HARD_REGNO_MODE_OK (yregno
, ymode
)
3610 && HARD_REGNO_MODE_OK (xregno
, xmode
))
3613 return (int) yregno
;
3616 /* Return the final regno that a subreg expression refers to. */
3618 subreg_regno (const_rtx x
)
3621 rtx subreg
= SUBREG_REG (x
);
3622 int regno
= REGNO (subreg
);
3624 ret
= regno
+ subreg_regno_offset (regno
,
3632 /* Return the number of registers that a subreg expression refers
3635 subreg_nregs (const_rtx x
)
3637 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x
)), x
);
3640 /* Return the number of registers that a subreg REG with REGNO
3641 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
3642 changed so that the regno can be passed in. */
3645 subreg_nregs_with_regno (unsigned int regno
, const_rtx x
)
3647 struct subreg_info info
;
3648 rtx subreg
= SUBREG_REG (x
);
3650 subreg_get_info (regno
, GET_MODE (subreg
), SUBREG_BYTE (x
), GET_MODE (x
),
3656 struct parms_set_data
3662 /* Helper function for noticing stores to parameter registers. */
3664 parms_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
3666 struct parms_set_data
*const d
= (struct parms_set_data
*) data
;
3667 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
3668 && TEST_HARD_REG_BIT (d
->regs
, REGNO (x
)))
3670 CLEAR_HARD_REG_BIT (d
->regs
, REGNO (x
));
3675 /* Look backward for first parameter to be loaded.
3676 Note that loads of all parameters will not necessarily be
3677 found if CSE has eliminated some of them (e.g., an argument
3678 to the outer function is passed down as a parameter).
3679 Do not skip BOUNDARY. */
3681 find_first_parameter_load (rtx_insn
*call_insn
, rtx_insn
*boundary
)
3683 struct parms_set_data parm
;
3685 rtx_insn
*before
, *first_set
;
3687 /* Since different machines initialize their parameter registers
3688 in different orders, assume nothing. Collect the set of all
3689 parameter registers. */
3690 CLEAR_HARD_REG_SET (parm
.regs
);
3692 for (p
= CALL_INSN_FUNCTION_USAGE (call_insn
); p
; p
= XEXP (p
, 1))
3693 if (GET_CODE (XEXP (p
, 0)) == USE
3694 && REG_P (XEXP (XEXP (p
, 0), 0)))
3696 gcc_assert (REGNO (XEXP (XEXP (p
, 0), 0)) < FIRST_PSEUDO_REGISTER
);
3698 /* We only care about registers which can hold function
3700 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p
, 0), 0))))
3703 SET_HARD_REG_BIT (parm
.regs
, REGNO (XEXP (XEXP (p
, 0), 0)));
3707 first_set
= call_insn
;
3709 /* Search backward for the first set of a register in this set. */
3710 while (parm
.nregs
&& before
!= boundary
)
3712 before
= PREV_INSN (before
);
3714 /* It is possible that some loads got CSEed from one call to
3715 another. Stop in that case. */
3716 if (CALL_P (before
))
3719 /* Our caller needs either ensure that we will find all sets
3720 (in case code has not been optimized yet), or take care
3721 for possible labels in a way by setting boundary to preceding
3723 if (LABEL_P (before
))
3725 gcc_assert (before
== boundary
);
3729 if (INSN_P (before
))
3731 int nregs_old
= parm
.nregs
;
3732 note_stores (PATTERN (before
), parms_set
, &parm
);
3733 /* If we found something that did not set a parameter reg,
3734 we're done. Do not keep going, as that might result
3735 in hoisting an insn before the setting of a pseudo
3736 that is used by the hoisted insn. */
3737 if (nregs_old
!= parm
.nregs
)
3746 /* Return true if we should avoid inserting code between INSN and preceding
3747 call instruction. */
3750 keep_with_call_p (const rtx_insn
*insn
)
3754 if (INSN_P (insn
) && (set
= single_set (insn
)) != NULL
)
3756 if (REG_P (SET_DEST (set
))
3757 && REGNO (SET_DEST (set
)) < FIRST_PSEUDO_REGISTER
3758 && fixed_regs
[REGNO (SET_DEST (set
))]
3759 && general_operand (SET_SRC (set
), VOIDmode
))
3761 if (REG_P (SET_SRC (set
))
3762 && targetm
.calls
.function_value_regno_p (REGNO (SET_SRC (set
)))
3763 && REG_P (SET_DEST (set
))
3764 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3766 /* There may be a stack pop just after the call and before the store
3767 of the return register. Search for the actual store when deciding
3768 if we can break or not. */
3769 if (SET_DEST (set
) == stack_pointer_rtx
)
3771 /* This CONST_CAST is okay because next_nonnote_insn just
3772 returns its argument and we assign it to a const_rtx
3775 = next_nonnote_insn (const_cast<rtx_insn
*> (insn
));
3776 if (i2
&& keep_with_call_p (i2
))
3783 /* Return true if LABEL is a target of JUMP_INSN. This applies only
3784 to non-complex jumps. That is, direct unconditional, conditional,
3785 and tablejumps, but not computed jumps or returns. It also does
3786 not apply to the fallthru case of a conditional jump. */
3789 label_is_jump_target_p (const_rtx label
, const rtx_insn
*jump_insn
)
3791 rtx tmp
= JUMP_LABEL (jump_insn
);
3792 rtx_jump_table_data
*table
;
3797 if (tablejump_p (jump_insn
, NULL
, &table
))
3799 rtvec vec
= table
->get_labels ();
3800 int i
, veclen
= GET_NUM_ELEM (vec
);
3802 for (i
= 0; i
< veclen
; ++i
)
3803 if (XEXP (RTVEC_ELT (vec
, i
), 0) == label
)
3807 if (find_reg_note (jump_insn
, REG_LABEL_TARGET
, label
))
3814 /* Return an estimate of the cost of computing rtx X.
3815 One use is in cse, to decide which expression to keep in the hash table.
3816 Another is in rtl generation, to pick the cheapest way to multiply.
3817 Other uses like the latter are expected in the future.
3819 X appears as operand OPNO in an expression with code OUTER_CODE.
3820 SPEED specifies whether costs optimized for speed or size should
3824 rtx_cost (rtx x
, enum rtx_code outer_code
, int opno
, bool speed
)
3835 /* A size N times larger than UNITS_PER_WORD likely needs N times as
3836 many insns, taking N times as long. */
3837 factor
= GET_MODE_SIZE (GET_MODE (x
)) / UNITS_PER_WORD
;
3841 /* Compute the default costs of certain things.
3842 Note that targetm.rtx_costs can override the defaults. */
3844 code
= GET_CODE (x
);
3848 /* Multiplication has time-complexity O(N*N), where N is the
3849 number of units (translated from digits) when using
3850 schoolbook long multiplication. */
3851 total
= factor
* factor
* COSTS_N_INSNS (5);
3857 /* Similarly, complexity for schoolbook long division. */
3858 total
= factor
* factor
* COSTS_N_INSNS (7);
3861 /* Used in combine.c as a marker. */
3865 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
3866 the mode for the factor. */
3867 factor
= GET_MODE_SIZE (GET_MODE (SET_DEST (x
))) / UNITS_PER_WORD
;
3872 total
= factor
* COSTS_N_INSNS (1);
3882 /* If we can't tie these modes, make this expensive. The larger
3883 the mode, the more expensive it is. */
3884 if (! MODES_TIEABLE_P (GET_MODE (x
), GET_MODE (SUBREG_REG (x
))))
3885 return COSTS_N_INSNS (2 + factor
);
3889 if (targetm
.rtx_costs (x
, code
, outer_code
, opno
, &total
, speed
))
3894 /* Sum the costs of the sub-rtx's, plus cost of this operation,
3895 which is already in total. */
3897 fmt
= GET_RTX_FORMAT (code
);
3898 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3900 total
+= rtx_cost (XEXP (x
, i
), code
, i
, speed
);
3901 else if (fmt
[i
] == 'E')
3902 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3903 total
+= rtx_cost (XVECEXP (x
, i
, j
), code
, i
, speed
);
3908 /* Fill in the structure C with information about both speed and size rtx
3909 costs for X, which is operand OPNO in an expression with code OUTER. */
3912 get_full_rtx_cost (rtx x
, enum rtx_code outer
, int opno
,
3913 struct full_rtx_costs
*c
)
3915 c
->speed
= rtx_cost (x
, outer
, opno
, true);
3916 c
->size
= rtx_cost (x
, outer
, opno
, false);
3920 /* Return cost of address expression X.
3921 Expect that X is properly formed address reference.
3923 SPEED parameter specify whether costs optimized for speed or size should
3927 address_cost (rtx x
, machine_mode mode
, addr_space_t as
, bool speed
)
3929 /* We may be asked for cost of various unusual addresses, such as operands
3930 of push instruction. It is not worthwhile to complicate writing
3931 of the target hook by such cases. */
3933 if (!memory_address_addr_space_p (mode
, x
, as
))
3936 return targetm
.address_cost (x
, mode
, as
, speed
);
3939 /* If the target doesn't override, compute the cost as with arithmetic. */
3942 default_address_cost (rtx x
, machine_mode
, addr_space_t
, bool speed
)
3944 return rtx_cost (x
, MEM
, 0, speed
);
3948 unsigned HOST_WIDE_INT
3949 nonzero_bits (const_rtx x
, machine_mode mode
)
3951 return cached_nonzero_bits (x
, mode
, NULL_RTX
, VOIDmode
, 0);
3955 num_sign_bit_copies (const_rtx x
, machine_mode mode
)
3957 return cached_num_sign_bit_copies (x
, mode
, NULL_RTX
, VOIDmode
, 0);
3960 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
3961 It avoids exponential behavior in nonzero_bits1 when X has
3962 identical subexpressions on the first or the second level. */
3964 static unsigned HOST_WIDE_INT
3965 cached_nonzero_bits (const_rtx x
, machine_mode mode
, const_rtx known_x
,
3966 machine_mode known_mode
,
3967 unsigned HOST_WIDE_INT known_ret
)
3969 if (x
== known_x
&& mode
== known_mode
)
3972 /* Try to find identical subexpressions. If found call
3973 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
3974 precomputed value for the subexpression as KNOWN_RET. */
3976 if (ARITHMETIC_P (x
))
3978 rtx x0
= XEXP (x
, 0);
3979 rtx x1
= XEXP (x
, 1);
3981 /* Check the first level. */
3983 return nonzero_bits1 (x
, mode
, x0
, mode
,
3984 cached_nonzero_bits (x0
, mode
, known_x
,
3985 known_mode
, known_ret
));
3987 /* Check the second level. */
3988 if (ARITHMETIC_P (x0
)
3989 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
3990 return nonzero_bits1 (x
, mode
, x1
, mode
,
3991 cached_nonzero_bits (x1
, mode
, known_x
,
3992 known_mode
, known_ret
));
3994 if (ARITHMETIC_P (x1
)
3995 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
3996 return nonzero_bits1 (x
, mode
, x0
, mode
,
3997 cached_nonzero_bits (x0
, mode
, known_x
,
3998 known_mode
, known_ret
));
4001 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
4004 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4005 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4006 is less useful. We can't allow both, because that results in exponential
4007 run time recursion. There is a nullstone testcase that triggered
4008 this. This macro avoids accidental uses of num_sign_bit_copies. */
4009 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4011 /* Given an expression, X, compute which bits in X can be nonzero.
4012 We don't care about bits outside of those defined in MODE.
4014 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
4015 an arithmetic operation, we can do better. */
4017 static unsigned HOST_WIDE_INT
4018 nonzero_bits1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4019 machine_mode known_mode
,
4020 unsigned HOST_WIDE_INT known_ret
)
4022 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
4023 unsigned HOST_WIDE_INT inner_nz
;
4025 machine_mode inner_mode
;
4026 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
4028 /* For floating-point and vector values, assume all bits are needed. */
4029 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
)
4030 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4033 /* If X is wider than MODE, use its mode instead. */
4034 if (GET_MODE_PRECISION (GET_MODE (x
)) > mode_width
)
4036 mode
= GET_MODE (x
);
4037 nonzero
= GET_MODE_MASK (mode
);
4038 mode_width
= GET_MODE_PRECISION (mode
);
4041 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
4042 /* Our only callers in this case look for single bit values. So
4043 just return the mode mask. Those tests will then be false. */
4046 #ifndef WORD_REGISTER_OPERATIONS
4047 /* If MODE is wider than X, but both are a single word for both the host
4048 and target machines, we can compute this from which bits of the
4049 object might be nonzero in its own mode, taking into account the fact
4050 that on many CISC machines, accessing an object in a wider mode
4051 causes the high-order bits to become undefined. So they are
4052 not known to be zero. */
4054 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
4055 && GET_MODE_PRECISION (GET_MODE (x
)) <= BITS_PER_WORD
4056 && GET_MODE_PRECISION (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
4057 && GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (GET_MODE (x
)))
4059 nonzero
&= cached_nonzero_bits (x
, GET_MODE (x
),
4060 known_x
, known_mode
, known_ret
);
4061 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
4066 code
= GET_CODE (x
);
4070 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
4071 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4072 all the bits above ptr_mode are known to be zero. */
4073 /* As we do not know which address space the pointer is referring to,
4074 we can do this only if the target does not support different pointer
4075 or address modes depending on the address space. */
4076 if (target_default_pointer_address_modes_p ()
4077 && POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4079 nonzero
&= GET_MODE_MASK (ptr_mode
);
4082 /* Include declared information about alignment of pointers. */
4083 /* ??? We don't properly preserve REG_POINTER changes across
4084 pointer-to-integer casts, so we can't trust it except for
4085 things that we know must be pointers. See execute/960116-1.c. */
4086 if ((x
== stack_pointer_rtx
4087 || x
== frame_pointer_rtx
4088 || x
== arg_pointer_rtx
)
4089 && REGNO_POINTER_ALIGN (REGNO (x
)))
4091 unsigned HOST_WIDE_INT alignment
4092 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
4094 #ifdef PUSH_ROUNDING
4095 /* If PUSH_ROUNDING is defined, it is possible for the
4096 stack to be momentarily aligned only to that amount,
4097 so we pick the least alignment. */
4098 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
4099 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
4103 nonzero
&= ~(alignment
- 1);
4107 unsigned HOST_WIDE_INT nonzero_for_hook
= nonzero
;
4108 rtx new_rtx
= rtl_hooks
.reg_nonzero_bits (x
, mode
, known_x
,
4109 known_mode
, known_ret
,
4113 nonzero_for_hook
&= cached_nonzero_bits (new_rtx
, mode
, known_x
,
4114 known_mode
, known_ret
);
4116 return nonzero_for_hook
;
4120 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
4121 /* If X is negative in MODE, sign-extend the value. */
4123 && mode_width
< BITS_PER_WORD
4124 && (UINTVAL (x
) & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
4126 return UINTVAL (x
) | (HOST_WIDE_INT_M1U
<< mode_width
);
4132 #ifdef LOAD_EXTEND_OP
4133 /* In many, if not most, RISC machines, reading a byte from memory
4134 zeros the rest of the register. Noticing that fact saves a lot
4135 of extra zero-extends. */
4136 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
4137 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
4142 case UNEQ
: case LTGT
:
4143 case GT
: case GTU
: case UNGT
:
4144 case LT
: case LTU
: case UNLT
:
4145 case GE
: case GEU
: case UNGE
:
4146 case LE
: case LEU
: case UNLE
:
4147 case UNORDERED
: case ORDERED
:
4148 /* If this produces an integer result, we know which bits are set.
4149 Code here used to clear bits outside the mode of X, but that is
4151 /* Mind that MODE is the mode the caller wants to look at this
4152 operation in, and not the actual operation mode. We can wind
4153 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4154 that describes the results of a vector compare. */
4155 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
4156 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
4157 nonzero
= STORE_FLAG_VALUE
;
4162 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4163 and num_sign_bit_copies. */
4164 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4165 == GET_MODE_PRECISION (GET_MODE (x
)))
4169 if (GET_MODE_PRECISION (GET_MODE (x
)) < mode_width
)
4170 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
4175 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4176 and num_sign_bit_copies. */
4177 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4178 == GET_MODE_PRECISION (GET_MODE (x
)))
4184 nonzero
&= (cached_nonzero_bits (XEXP (x
, 0), mode
,
4185 known_x
, known_mode
, known_ret
)
4186 & GET_MODE_MASK (mode
));
4190 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4191 known_x
, known_mode
, known_ret
);
4192 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4193 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4197 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4198 Otherwise, show all the bits in the outer mode but not the inner
4200 inner_nz
= cached_nonzero_bits (XEXP (x
, 0), mode
,
4201 known_x
, known_mode
, known_ret
);
4202 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4204 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4205 if (val_signbit_known_set_p (GET_MODE (XEXP (x
, 0)), inner_nz
))
4206 inner_nz
|= (GET_MODE_MASK (mode
)
4207 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
4210 nonzero
&= inner_nz
;
4214 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4215 known_x
, known_mode
, known_ret
)
4216 & cached_nonzero_bits (XEXP (x
, 1), mode
,
4217 known_x
, known_mode
, known_ret
);
4221 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
4223 unsigned HOST_WIDE_INT nonzero0
4224 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4225 known_x
, known_mode
, known_ret
);
4227 /* Don't call nonzero_bits for the second time if it cannot change
4229 if ((nonzero
& nonzero0
) != nonzero
)
4231 | cached_nonzero_bits (XEXP (x
, 1), mode
,
4232 known_x
, known_mode
, known_ret
);
4236 case PLUS
: case MINUS
:
4238 case DIV
: case UDIV
:
4239 case MOD
: case UMOD
:
4240 /* We can apply the rules of arithmetic to compute the number of
4241 high- and low-order zero bits of these operations. We start by
4242 computing the width (position of the highest-order nonzero bit)
4243 and the number of low-order zero bits for each value. */
4245 unsigned HOST_WIDE_INT nz0
4246 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4247 known_x
, known_mode
, known_ret
);
4248 unsigned HOST_WIDE_INT nz1
4249 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4250 known_x
, known_mode
, known_ret
);
4251 int sign_index
= GET_MODE_PRECISION (GET_MODE (x
)) - 1;
4252 int width0
= floor_log2 (nz0
) + 1;
4253 int width1
= floor_log2 (nz1
) + 1;
4254 int low0
= floor_log2 (nz0
& -nz0
);
4255 int low1
= floor_log2 (nz1
& -nz1
);
4256 unsigned HOST_WIDE_INT op0_maybe_minusp
4257 = nz0
& ((unsigned HOST_WIDE_INT
) 1 << sign_index
);
4258 unsigned HOST_WIDE_INT op1_maybe_minusp
4259 = nz1
& ((unsigned HOST_WIDE_INT
) 1 << sign_index
);
4260 unsigned int result_width
= mode_width
;
4266 result_width
= MAX (width0
, width1
) + 1;
4267 result_low
= MIN (low0
, low1
);
4270 result_low
= MIN (low0
, low1
);
4273 result_width
= width0
+ width1
;
4274 result_low
= low0
+ low1
;
4279 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4280 result_width
= width0
;
4285 result_width
= width0
;
4290 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4291 result_width
= MIN (width0
, width1
);
4292 result_low
= MIN (low0
, low1
);
4297 result_width
= MIN (width0
, width1
);
4298 result_low
= MIN (low0
, low1
);
4304 if (result_width
< mode_width
)
4305 nonzero
&= ((unsigned HOST_WIDE_INT
) 1 << result_width
) - 1;
4308 nonzero
&= ~(((unsigned HOST_WIDE_INT
) 1 << result_low
) - 1);
4313 if (CONST_INT_P (XEXP (x
, 1))
4314 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
4315 nonzero
&= ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
4319 /* If this is a SUBREG formed for a promoted variable that has
4320 been zero-extended, we know that at least the high-order bits
4321 are zero, though others might be too. */
4323 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
4324 nonzero
= GET_MODE_MASK (GET_MODE (x
))
4325 & cached_nonzero_bits (SUBREG_REG (x
), GET_MODE (x
),
4326 known_x
, known_mode
, known_ret
);
4328 inner_mode
= GET_MODE (SUBREG_REG (x
));
4329 /* If the inner mode is a single word for both the host and target
4330 machines, we can compute this from which bits of the inner
4331 object might be nonzero. */
4332 if (GET_MODE_PRECISION (inner_mode
) <= BITS_PER_WORD
4333 && (GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
))
4335 nonzero
&= cached_nonzero_bits (SUBREG_REG (x
), mode
,
4336 known_x
, known_mode
, known_ret
);
4338 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
4339 /* If this is a typical RISC machine, we only have to worry
4340 about the way loads are extended. */
4341 if ((LOAD_EXTEND_OP (inner_mode
) == SIGN_EXTEND
4342 ? val_signbit_known_set_p (inner_mode
, nonzero
)
4343 : LOAD_EXTEND_OP (inner_mode
) != ZERO_EXTEND
)
4344 || !MEM_P (SUBREG_REG (x
)))
4347 /* On many CISC machines, accessing an object in a wider mode
4348 causes the high-order bits to become undefined. So they are
4349 not known to be zero. */
4350 if (GET_MODE_PRECISION (GET_MODE (x
))
4351 > GET_MODE_PRECISION (inner_mode
))
4352 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
4353 & ~GET_MODE_MASK (inner_mode
));
4362 /* The nonzero bits are in two classes: any bits within MODE
4363 that aren't in GET_MODE (x) are always significant. The rest of the
4364 nonzero bits are those that are significant in the operand of
4365 the shift when shifted the appropriate number of bits. This
4366 shows that high-order bits are cleared by the right shift and
4367 low-order bits by left shifts. */
4368 if (CONST_INT_P (XEXP (x
, 1))
4369 && INTVAL (XEXP (x
, 1)) >= 0
4370 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
4371 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
4373 machine_mode inner_mode
= GET_MODE (x
);
4374 unsigned int width
= GET_MODE_PRECISION (inner_mode
);
4375 int count
= INTVAL (XEXP (x
, 1));
4376 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
4377 unsigned HOST_WIDE_INT op_nonzero
4378 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4379 known_x
, known_mode
, known_ret
);
4380 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
4381 unsigned HOST_WIDE_INT outer
= 0;
4383 if (mode_width
> width
)
4384 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
4386 if (code
== LSHIFTRT
)
4388 else if (code
== ASHIFTRT
)
4392 /* If the sign bit may have been nonzero before the shift, we
4393 need to mark all the places it could have been copied to
4394 by the shift as possibly nonzero. */
4395 if (inner
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
4396 inner
|= (((unsigned HOST_WIDE_INT
) 1 << count
) - 1)
4399 else if (code
== ASHIFT
)
4402 inner
= ((inner
<< (count
% width
)
4403 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
4405 nonzero
&= (outer
| inner
);
4411 /* This is at most the number of bits in the mode. */
4412 nonzero
= ((unsigned HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
4416 /* If CLZ has a known value at zero, then the nonzero bits are
4417 that value, plus the number of bits in the mode minus one. */
4418 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4420 |= ((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
4426 /* If CTZ has a known value at zero, then the nonzero bits are
4427 that value, plus the number of bits in the mode minus one. */
4428 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4430 |= ((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
4436 /* This is at most the number of bits in the mode minus 1. */
4437 nonzero
= ((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
4446 unsigned HOST_WIDE_INT nonzero_true
4447 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4448 known_x
, known_mode
, known_ret
);
4450 /* Don't call nonzero_bits for the second time if it cannot change
4452 if ((nonzero
& nonzero_true
) != nonzero
)
4453 nonzero
&= nonzero_true
4454 | cached_nonzero_bits (XEXP (x
, 2), mode
,
4455 known_x
, known_mode
, known_ret
);
4466 /* See the macro definition above. */
4467 #undef cached_num_sign_bit_copies
4470 /* The function cached_num_sign_bit_copies is a wrapper around
4471 num_sign_bit_copies1. It avoids exponential behavior in
4472 num_sign_bit_copies1 when X has identical subexpressions on the
4473 first or the second level. */
4476 cached_num_sign_bit_copies (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4477 machine_mode known_mode
,
4478 unsigned int known_ret
)
4480 if (x
== known_x
&& mode
== known_mode
)
4483 /* Try to find identical subexpressions. If found call
4484 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
4485 the precomputed value for the subexpression as KNOWN_RET. */
4487 if (ARITHMETIC_P (x
))
4489 rtx x0
= XEXP (x
, 0);
4490 rtx x1
= XEXP (x
, 1);
4492 /* Check the first level. */
4495 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4496 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4500 /* Check the second level. */
4501 if (ARITHMETIC_P (x0
)
4502 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4504 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
4505 cached_num_sign_bit_copies (x1
, mode
, known_x
,
4509 if (ARITHMETIC_P (x1
)
4510 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4512 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4513 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4518 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
4521 /* Return the number of bits at the high-order end of X that are known to
4522 be equal to the sign bit. X will be used in mode MODE; if MODE is
4523 VOIDmode, X will be used in its own mode. The returned value will always
4524 be between 1 and the number of bits in MODE. */
4527 num_sign_bit_copies1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4528 machine_mode known_mode
,
4529 unsigned int known_ret
)
4531 enum rtx_code code
= GET_CODE (x
);
4532 unsigned int bitwidth
= GET_MODE_PRECISION (mode
);
4533 int num0
, num1
, result
;
4534 unsigned HOST_WIDE_INT nonzero
;
4536 /* If we weren't given a mode, use the mode of X. If the mode is still
4537 VOIDmode, we don't know anything. Likewise if one of the modes is
4540 if (mode
== VOIDmode
)
4541 mode
= GET_MODE (x
);
4543 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
))
4544 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4547 /* For a smaller object, just ignore the high bits. */
4548 if (bitwidth
< GET_MODE_PRECISION (GET_MODE (x
)))
4550 num0
= cached_num_sign_bit_copies (x
, GET_MODE (x
),
4551 known_x
, known_mode
, known_ret
);
4553 num0
- (int) (GET_MODE_PRECISION (GET_MODE (x
)) - bitwidth
));
4556 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_PRECISION (GET_MODE (x
)))
4558 #ifndef WORD_REGISTER_OPERATIONS
4559 /* If this machine does not do all register operations on the entire
4560 register and MODE is wider than the mode of X, we can say nothing
4561 at all about the high-order bits. */
4564 /* Likewise on machines that do, if the mode of the object is smaller
4565 than a word and loads of that size don't sign extend, we can say
4566 nothing about the high order bits. */
4567 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
4568 #ifdef LOAD_EXTEND_OP
4569 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
4580 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
4581 /* If pointers extend signed and this is a pointer in Pmode, say that
4582 all the bits above ptr_mode are known to be sign bit copies. */
4583 /* As we do not know which address space the pointer is referring to,
4584 we can do this only if the target does not support different pointer
4585 or address modes depending on the address space. */
4586 if (target_default_pointer_address_modes_p ()
4587 && ! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4588 && mode
== Pmode
&& REG_POINTER (x
))
4589 return GET_MODE_PRECISION (Pmode
) - GET_MODE_PRECISION (ptr_mode
) + 1;
4593 unsigned int copies_for_hook
= 1, copies
= 1;
4594 rtx new_rtx
= rtl_hooks
.reg_num_sign_bit_copies (x
, mode
, known_x
,
4595 known_mode
, known_ret
,
4599 copies
= cached_num_sign_bit_copies (new_rtx
, mode
, known_x
,
4600 known_mode
, known_ret
);
4602 if (copies
> 1 || copies_for_hook
> 1)
4603 return MAX (copies
, copies_for_hook
);
4605 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
4610 #ifdef LOAD_EXTEND_OP
4611 /* Some RISC machines sign-extend all loads of smaller than a word. */
4612 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
4613 return MAX (1, ((int) bitwidth
4614 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1));
4619 /* If the constant is negative, take its 1's complement and remask.
4620 Then see how many zero bits we have. */
4621 nonzero
= UINTVAL (x
) & GET_MODE_MASK (mode
);
4622 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
4623 && (nonzero
& ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4624 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
4626 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
4629 /* If this is a SUBREG for a promoted object that is sign-extended
4630 and we are looking at it in a wider mode, we know that at least the
4631 high-order bits are known to be sign bit copies. */
4633 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_SIGNED_P (x
))
4635 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4636 known_x
, known_mode
, known_ret
);
4637 return MAX ((int) bitwidth
4638 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1,
4642 /* For a smaller object, just ignore the high bits. */
4643 if (bitwidth
<= GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x
))))
4645 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
,
4646 known_x
, known_mode
, known_ret
);
4647 return MAX (1, (num0
4648 - (int) (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x
)))
4652 #ifdef WORD_REGISTER_OPERATIONS
4653 #ifdef LOAD_EXTEND_OP
4654 /* For paradoxical SUBREGs on machines where all register operations
4655 affect the entire register, just look inside. Note that we are
4656 passing MODE to the recursive call, so the number of sign bit copies
4657 will remain relative to that mode, not the inner mode. */
4659 /* This works only if loads sign extend. Otherwise, if we get a
4660 reload for the inner part, it may be loaded from the stack, and
4661 then we lose all sign bit copies that existed before the store
4664 if (paradoxical_subreg_p (x
)
4665 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
4666 && MEM_P (SUBREG_REG (x
)))
4667 return cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4668 known_x
, known_mode
, known_ret
);
4674 if (CONST_INT_P (XEXP (x
, 1)))
4675 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
4679 return (bitwidth
- GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4680 + cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4681 known_x
, known_mode
, known_ret
));
4684 /* For a smaller object, just ignore the high bits. */
4685 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4686 known_x
, known_mode
, known_ret
);
4687 return MAX (1, (num0
- (int) (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4691 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4692 known_x
, known_mode
, known_ret
);
4694 case ROTATE
: case ROTATERT
:
4695 /* If we are rotating left by a number of bits less than the number
4696 of sign bit copies, we can just subtract that amount from the
4698 if (CONST_INT_P (XEXP (x
, 1))
4699 && INTVAL (XEXP (x
, 1)) >= 0
4700 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
4702 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4703 known_x
, known_mode
, known_ret
);
4704 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
4705 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
4710 /* In general, this subtracts one sign bit copy. But if the value
4711 is known to be positive, the number of sign bit copies is the
4712 same as that of the input. Finally, if the input has just one bit
4713 that might be nonzero, all the bits are copies of the sign bit. */
4714 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4715 known_x
, known_mode
, known_ret
);
4716 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
4717 return num0
> 1 ? num0
- 1 : 1;
4719 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
4724 && (((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
4729 case IOR
: case AND
: case XOR
:
4730 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
4731 /* Logical operations will preserve the number of sign-bit copies.
4732 MIN and MAX operations always return one of the operands. */
4733 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4734 known_x
, known_mode
, known_ret
);
4735 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4736 known_x
, known_mode
, known_ret
);
4738 /* If num1 is clearing some of the top bits then regardless of
4739 the other term, we are guaranteed to have at least that many
4740 high-order zero bits. */
4743 && bitwidth
<= HOST_BITS_PER_WIDE_INT
4744 && CONST_INT_P (XEXP (x
, 1))
4745 && (UINTVAL (XEXP (x
, 1))
4746 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) == 0)
4749 /* Similarly for IOR when setting high-order bits. */
4752 && bitwidth
<= HOST_BITS_PER_WIDE_INT
4753 && CONST_INT_P (XEXP (x
, 1))
4754 && (UINTVAL (XEXP (x
, 1))
4755 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4758 return MIN (num0
, num1
);
4760 case PLUS
: case MINUS
:
4761 /* For addition and subtraction, we can have a 1-bit carry. However,
4762 if we are subtracting 1 from a positive number, there will not
4763 be such a carry. Furthermore, if the positive number is known to
4764 be 0 or 1, we know the result is either -1 or 0. */
4766 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
4767 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
4769 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
4770 if ((((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
4771 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
4772 : bitwidth
- floor_log2 (nonzero
) - 1);
4775 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4776 known_x
, known_mode
, known_ret
);
4777 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4778 known_x
, known_mode
, known_ret
);
4779 result
= MAX (1, MIN (num0
, num1
) - 1);
4784 /* The number of bits of the product is the sum of the number of
4785 bits of both terms. However, unless one of the terms if known
4786 to be positive, we must allow for an additional bit since negating
4787 a negative number can remove one sign bit copy. */
4789 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4790 known_x
, known_mode
, known_ret
);
4791 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4792 known_x
, known_mode
, known_ret
);
4794 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
4796 && (bitwidth
> HOST_BITS_PER_WIDE_INT
4797 || (((nonzero_bits (XEXP (x
, 0), mode
)
4798 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4799 && ((nonzero_bits (XEXP (x
, 1), mode
)
4800 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1)))
4804 return MAX (1, result
);
4807 /* The result must be <= the first operand. If the first operand
4808 has the high bit set, we know nothing about the number of sign
4810 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
4812 else if ((nonzero_bits (XEXP (x
, 0), mode
)
4813 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4816 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4817 known_x
, known_mode
, known_ret
);
4820 /* The result must be <= the second operand. If the second operand
4821 has (or just might have) the high bit set, we know nothing about
4822 the number of sign bit copies. */
4823 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
4825 else if ((nonzero_bits (XEXP (x
, 1), mode
)
4826 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4829 return cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4830 known_x
, known_mode
, known_ret
);
4833 /* Similar to unsigned division, except that we have to worry about
4834 the case where the divisor is negative, in which case we have
4836 result
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4837 known_x
, known_mode
, known_ret
);
4839 && (bitwidth
> HOST_BITS_PER_WIDE_INT
4840 || (nonzero_bits (XEXP (x
, 1), mode
)
4841 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
4847 result
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4848 known_x
, known_mode
, known_ret
);
4850 && (bitwidth
> HOST_BITS_PER_WIDE_INT
4851 || (nonzero_bits (XEXP (x
, 1), mode
)
4852 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
4858 /* Shifts by a constant add to the number of bits equal to the
4860 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4861 known_x
, known_mode
, known_ret
);
4862 if (CONST_INT_P (XEXP (x
, 1))
4863 && INTVAL (XEXP (x
, 1)) > 0
4864 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
4865 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
4870 /* Left shifts destroy copies. */
4871 if (!CONST_INT_P (XEXP (x
, 1))
4872 || INTVAL (XEXP (x
, 1)) < 0
4873 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
4874 || INTVAL (XEXP (x
, 1)) >= GET_MODE_PRECISION (GET_MODE (x
)))
4877 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4878 known_x
, known_mode
, known_ret
);
4879 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
4882 num0
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4883 known_x
, known_mode
, known_ret
);
4884 num1
= cached_num_sign_bit_copies (XEXP (x
, 2), mode
,
4885 known_x
, known_mode
, known_ret
);
4886 return MIN (num0
, num1
);
4888 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
4889 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
4890 case GEU
: case GTU
: case LEU
: case LTU
:
4891 case UNORDERED
: case ORDERED
:
4892 /* If the constant is negative, take its 1's complement and remask.
4893 Then see how many zero bits we have. */
4894 nonzero
= STORE_FLAG_VALUE
;
4895 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
4896 && (nonzero
& ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4897 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
4899 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
4905 /* If we haven't been able to figure it out by one of the above rules,
4906 see if some of the high-order bits are known to be zero. If so,
4907 count those bits and return one less than that amount. If we can't
4908 safely compute the mask for this mode, always return BITWIDTH. */
4910 bitwidth
= GET_MODE_PRECISION (mode
);
4911 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
4914 nonzero
= nonzero_bits (x
, mode
);
4915 return nonzero
& ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))
4916 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1;
4919 /* Calculate the rtx_cost of a single instruction. A return value of
4920 zero indicates an instruction pattern without a known cost. */
4923 insn_rtx_cost (rtx pat
, bool speed
)
4928 /* Extract the single set rtx from the instruction pattern.
4929 We can't use single_set since we only have the pattern. */
4930 if (GET_CODE (pat
) == SET
)
4932 else if (GET_CODE (pat
) == PARALLEL
)
4935 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
4937 rtx x
= XVECEXP (pat
, 0, i
);
4938 if (GET_CODE (x
) == SET
)
4951 cost
= set_src_cost (SET_SRC (set
), speed
);
4952 return cost
> 0 ? cost
: COSTS_N_INSNS (1);
4955 /* Returns estimate on cost of computing SEQ. */
4958 seq_cost (const rtx_insn
*seq
, bool speed
)
4963 for (; seq
; seq
= NEXT_INSN (seq
))
4965 set
= single_set (seq
);
4967 cost
+= set_rtx_cost (set
, speed
);
4975 /* Given an insn INSN and condition COND, return the condition in a
4976 canonical form to simplify testing by callers. Specifically:
4978 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
4979 (2) Both operands will be machine operands; (cc0) will have been replaced.
4980 (3) If an operand is a constant, it will be the second operand.
4981 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
4982 for GE, GEU, and LEU.
4984 If the condition cannot be understood, or is an inequality floating-point
4985 comparison which needs to be reversed, 0 will be returned.
4987 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
4989 If EARLIEST is nonzero, it is a pointer to a place where the earliest
4990 insn used in locating the condition was found. If a replacement test
4991 of the condition is desired, it should be placed in front of that
4992 insn and we will be sure that the inputs are still valid.
4994 If WANT_REG is nonzero, we wish the condition to be relative to that
4995 register, if possible. Therefore, do not canonicalize the condition
4996 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
4997 to be a compare to a CC mode register.
4999 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5003 canonicalize_condition (rtx_insn
*insn
, rtx cond
, int reverse
,
5004 rtx_insn
**earliest
,
5005 rtx want_reg
, int allow_cc_mode
, int valid_at_insn_p
)
5008 rtx_insn
*prev
= insn
;
5012 int reverse_code
= 0;
5014 basic_block bb
= BLOCK_FOR_INSN (insn
);
5016 code
= GET_CODE (cond
);
5017 mode
= GET_MODE (cond
);
5018 op0
= XEXP (cond
, 0);
5019 op1
= XEXP (cond
, 1);
5022 code
= reversed_comparison_code (cond
, insn
);
5023 if (code
== UNKNOWN
)
5029 /* If we are comparing a register with zero, see if the register is set
5030 in the previous insn to a COMPARE or a comparison operation. Perform
5031 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5034 while ((GET_RTX_CLASS (code
) == RTX_COMPARE
5035 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
5036 && op1
== CONST0_RTX (GET_MODE (op0
))
5039 /* Set nonzero when we find something of interest. */
5042 /* If comparison with cc0, import actual comparison from compare
5046 if ((prev
= prev_nonnote_insn (prev
)) == 0
5047 || !NONJUMP_INSN_P (prev
)
5048 || (set
= single_set (prev
)) == 0
5049 || SET_DEST (set
) != cc0_rtx
)
5052 op0
= SET_SRC (set
);
5053 op1
= CONST0_RTX (GET_MODE (op0
));
5058 /* If this is a COMPARE, pick up the two things being compared. */
5059 if (GET_CODE (op0
) == COMPARE
)
5061 op1
= XEXP (op0
, 1);
5062 op0
= XEXP (op0
, 0);
5065 else if (!REG_P (op0
))
5068 /* Go back to the previous insn. Stop if it is not an INSN. We also
5069 stop if it isn't a single set or if it has a REG_INC note because
5070 we don't want to bother dealing with it. */
5072 prev
= prev_nonnote_nondebug_insn (prev
);
5075 || !NONJUMP_INSN_P (prev
)
5076 || FIND_REG_INC_NOTE (prev
, NULL_RTX
)
5077 /* In cfglayout mode, there do not have to be labels at the
5078 beginning of a block, or jumps at the end, so the previous
5079 conditions would not stop us when we reach bb boundary. */
5080 || BLOCK_FOR_INSN (prev
) != bb
)
5083 set
= set_of (op0
, prev
);
5086 && (GET_CODE (set
) != SET
5087 || !rtx_equal_p (SET_DEST (set
), op0
)))
5090 /* If this is setting OP0, get what it sets it to if it looks
5094 machine_mode inner_mode
= GET_MODE (SET_DEST (set
));
5095 #ifdef FLOAT_STORE_FLAG_VALUE
5096 REAL_VALUE_TYPE fsfv
;
5099 /* ??? We may not combine comparisons done in a CCmode with
5100 comparisons not done in a CCmode. This is to aid targets
5101 like Alpha that have an IEEE compliant EQ instruction, and
5102 a non-IEEE compliant BEQ instruction. The use of CCmode is
5103 actually artificial, simply to prevent the combination, but
5104 should not affect other platforms.
5106 However, we must allow VOIDmode comparisons to match either
5107 CCmode or non-CCmode comparison, because some ports have
5108 modeless comparisons inside branch patterns.
5110 ??? This mode check should perhaps look more like the mode check
5111 in simplify_comparison in combine. */
5112 if (((GET_MODE_CLASS (mode
) == MODE_CC
)
5113 != (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5115 && inner_mode
!= VOIDmode
)
5117 if (GET_CODE (SET_SRC (set
)) == COMPARE
5120 && val_signbit_known_set_p (inner_mode
,
5122 #ifdef FLOAT_STORE_FLAG_VALUE
5124 && SCALAR_FLOAT_MODE_P (inner_mode
)
5125 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5126 REAL_VALUE_NEGATIVE (fsfv
)))
5129 && COMPARISON_P (SET_SRC (set
))))
5131 else if (((code
== EQ
5133 && val_signbit_known_set_p (inner_mode
,
5135 #ifdef FLOAT_STORE_FLAG_VALUE
5137 && SCALAR_FLOAT_MODE_P (inner_mode
)
5138 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5139 REAL_VALUE_NEGATIVE (fsfv
)))
5142 && COMPARISON_P (SET_SRC (set
)))
5147 else if ((code
== EQ
|| code
== NE
)
5148 && GET_CODE (SET_SRC (set
)) == XOR
)
5149 /* Handle sequences like:
5152 ...(eq|ne op0 (const_int 0))...
5156 (eq op0 (const_int 0)) reduces to (eq X Y)
5157 (ne op0 (const_int 0)) reduces to (ne X Y)
5159 This is the form used by MIPS16, for example. */
5165 else if (reg_set_p (op0
, prev
))
5166 /* If this sets OP0, but not directly, we have to give up. */
5171 /* If the caller is expecting the condition to be valid at INSN,
5172 make sure X doesn't change before INSN. */
5173 if (valid_at_insn_p
)
5174 if (modified_in_p (x
, prev
) || modified_between_p (x
, prev
, insn
))
5176 if (COMPARISON_P (x
))
5177 code
= GET_CODE (x
);
5180 code
= reversed_comparison_code (x
, prev
);
5181 if (code
== UNKNOWN
)
5186 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5192 /* If constant is first, put it last. */
5193 if (CONSTANT_P (op0
))
5194 code
= swap_condition (code
), tem
= op0
, op0
= op1
, op1
= tem
;
5196 /* If OP0 is the result of a comparison, we weren't able to find what
5197 was really being compared, so fail. */
5199 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5202 /* Canonicalize any ordered comparison with integers involving equality
5203 if we can do computations in the relevant mode and we do not
5206 if (GET_MODE_CLASS (GET_MODE (op0
)) != MODE_CC
5207 && CONST_INT_P (op1
)
5208 && GET_MODE (op0
) != VOIDmode
5209 && GET_MODE_PRECISION (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
)
5211 HOST_WIDE_INT const_val
= INTVAL (op1
);
5212 unsigned HOST_WIDE_INT uconst_val
= const_val
;
5213 unsigned HOST_WIDE_INT max_val
5214 = (unsigned HOST_WIDE_INT
) GET_MODE_MASK (GET_MODE (op0
));
5219 if ((unsigned HOST_WIDE_INT
) const_val
!= max_val
>> 1)
5220 code
= LT
, op1
= gen_int_mode (const_val
+ 1, GET_MODE (op0
));
5223 /* When cross-compiling, const_val might be sign-extended from
5224 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
5226 if ((const_val
& max_val
)
5227 != ((unsigned HOST_WIDE_INT
) 1
5228 << (GET_MODE_PRECISION (GET_MODE (op0
)) - 1)))
5229 code
= GT
, op1
= gen_int_mode (const_val
- 1, GET_MODE (op0
));
5233 if (uconst_val
< max_val
)
5234 code
= LTU
, op1
= gen_int_mode (uconst_val
+ 1, GET_MODE (op0
));
5238 if (uconst_val
!= 0)
5239 code
= GTU
, op1
= gen_int_mode (uconst_val
- 1, GET_MODE (op0
));
5247 /* Never return CC0; return zero instead. */
5251 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5254 /* Given a jump insn JUMP, return the condition that will cause it to branch
5255 to its JUMP_LABEL. If the condition cannot be understood, or is an
5256 inequality floating-point comparison which needs to be reversed, 0 will
5259 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5260 insn used in locating the condition was found. If a replacement test
5261 of the condition is desired, it should be placed in front of that
5262 insn and we will be sure that the inputs are still valid. If EARLIEST
5263 is null, the returned condition will be valid at INSN.
5265 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
5266 compare CC mode register.
5268 VALID_AT_INSN_P is the same as for canonicalize_condition. */
5271 get_condition (rtx_insn
*jump
, rtx_insn
**earliest
, int allow_cc_mode
,
5272 int valid_at_insn_p
)
5278 /* If this is not a standard conditional jump, we can't parse it. */
5280 || ! any_condjump_p (jump
))
5282 set
= pc_set (jump
);
5284 cond
= XEXP (SET_SRC (set
), 0);
5286 /* If this branches to JUMP_LABEL when the condition is false, reverse
5289 = GET_CODE (XEXP (SET_SRC (set
), 2)) == LABEL_REF
5290 && LABEL_REF_LABEL (XEXP (SET_SRC (set
), 2)) == JUMP_LABEL (jump
);
5292 return canonicalize_condition (jump
, cond
, reverse
, earliest
, NULL_RTX
,
5293 allow_cc_mode
, valid_at_insn_p
);
5296 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
5297 TARGET_MODE_REP_EXTENDED.
5299 Note that we assume that the property of
5300 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
5301 narrower than mode B. I.e., if A is a mode narrower than B then in
5302 order to be able to operate on it in mode B, mode A needs to
5303 satisfy the requirements set by the representation of mode B. */
5306 init_num_sign_bit_copies_in_rep (void)
5308 machine_mode mode
, in_mode
;
5310 for (in_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); in_mode
!= VOIDmode
;
5311 in_mode
= GET_MODE_WIDER_MODE (mode
))
5312 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= in_mode
;
5313 mode
= GET_MODE_WIDER_MODE (mode
))
5317 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
5318 extends to the next widest mode. */
5319 gcc_assert (targetm
.mode_rep_extended (mode
, in_mode
) == UNKNOWN
5320 || GET_MODE_WIDER_MODE (mode
) == in_mode
);
5322 /* We are in in_mode. Count how many bits outside of mode
5323 have to be copies of the sign-bit. */
5324 for (i
= mode
; i
!= in_mode
; i
= GET_MODE_WIDER_MODE (i
))
5326 machine_mode wider
= GET_MODE_WIDER_MODE (i
);
5328 if (targetm
.mode_rep_extended (i
, wider
) == SIGN_EXTEND
5329 /* We can only check sign-bit copies starting from the
5330 top-bit. In order to be able to check the bits we
5331 have already seen we pretend that subsequent bits
5332 have to be sign-bit copies too. */
5333 || num_sign_bit_copies_in_rep
[in_mode
][mode
])
5334 num_sign_bit_copies_in_rep
[in_mode
][mode
]
5335 += GET_MODE_PRECISION (wider
) - GET_MODE_PRECISION (i
);
5340 /* Suppose that truncation from the machine mode of X to MODE is not a
5341 no-op. See if there is anything special about X so that we can
5342 assume it already contains a truncated value of MODE. */
5345 truncated_to_mode (machine_mode mode
, const_rtx x
)
5347 /* This register has already been used in MODE without explicit
5349 if (REG_P (x
) && rtl_hooks
.reg_truncated_to_mode (mode
, x
))
5352 /* See if we already satisfy the requirements of MODE. If yes we
5353 can just switch to MODE. */
5354 if (num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
]
5355 && (num_sign_bit_copies (x
, GET_MODE (x
))
5356 >= num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
] + 1))
5362 /* Return true if RTX code CODE has a single sequence of zero or more
5363 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
5364 entry in that case. */
5367 setup_reg_subrtx_bounds (unsigned int code
)
5369 const char *format
= GET_RTX_FORMAT ((enum rtx_code
) code
);
5371 for (; format
[i
] != 'e'; ++i
)
5374 /* No subrtxes. Leave start and count as 0. */
5376 if (format
[i
] == 'E' || format
[i
] == 'V')
5380 /* Record the sequence of 'e's. */
5381 rtx_all_subrtx_bounds
[code
].start
= i
;
5384 while (format
[i
] == 'e');
5385 rtx_all_subrtx_bounds
[code
].count
= i
- rtx_all_subrtx_bounds
[code
].start
;
5386 /* rtl-iter.h relies on this. */
5387 gcc_checking_assert (rtx_all_subrtx_bounds
[code
].count
<= 3);
5389 for (; format
[i
]; ++i
)
5390 if (format
[i
] == 'E' || format
[i
] == 'V' || format
[i
] == 'e')
5396 /* Initialize rtx_all_subrtx_bounds. */
5401 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
5403 if (!setup_reg_subrtx_bounds (i
))
5404 rtx_all_subrtx_bounds
[i
].count
= UCHAR_MAX
;
5405 if (GET_RTX_CLASS (i
) != RTX_CONST_OBJ
)
5406 rtx_nonconst_subrtx_bounds
[i
] = rtx_all_subrtx_bounds
[i
];
5409 init_num_sign_bit_copies_in_rep ();
5412 /* Check whether this is a constant pool constant. */
5414 constant_pool_constant_p (rtx x
)
5416 x
= avoid_constant_pool_reference (x
);
5417 return CONST_DOUBLE_P (x
);
5420 /* If M is a bitmask that selects a field of low-order bits within an item but
5421 not the entire word, return the length of the field. Return -1 otherwise.
5422 M is used in machine mode MODE. */
5425 low_bitmask_len (machine_mode mode
, unsigned HOST_WIDE_INT m
)
5427 if (mode
!= VOIDmode
)
5429 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
5431 m
&= GET_MODE_MASK (mode
);
5434 return exact_log2 (m
+ 1);
5437 /* Return the mode of MEM's address. */
5440 get_address_mode (rtx mem
)
5444 gcc_assert (MEM_P (mem
));
5445 mode
= GET_MODE (XEXP (mem
, 0));
5446 if (mode
!= VOIDmode
)
5448 return targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (mem
));
5451 /* Split up a CONST_DOUBLE or integer constant rtx
5452 into two rtx's for single words,
5453 storing in *FIRST the word that comes first in memory in the target
5454 and in *SECOND the other.
5456 TODO: This function needs to be rewritten to work on any size
5460 split_double (rtx value
, rtx
*first
, rtx
*second
)
5462 if (CONST_INT_P (value
))
5464 if (HOST_BITS_PER_WIDE_INT
>= (2 * BITS_PER_WORD
))
5466 /* In this case the CONST_INT holds both target words.
5467 Extract the bits from it into two word-sized pieces.
5468 Sign extend each half to HOST_WIDE_INT. */
5469 unsigned HOST_WIDE_INT low
, high
;
5470 unsigned HOST_WIDE_INT mask
, sign_bit
, sign_extend
;
5471 unsigned bits_per_word
= BITS_PER_WORD
;
5473 /* Set sign_bit to the most significant bit of a word. */
5475 sign_bit
<<= bits_per_word
- 1;
5477 /* Set mask so that all bits of the word are set. We could
5478 have used 1 << BITS_PER_WORD instead of basing the
5479 calculation on sign_bit. However, on machines where
5480 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
5481 compiler warning, even though the code would never be
5483 mask
= sign_bit
<< 1;
5486 /* Set sign_extend as any remaining bits. */
5487 sign_extend
= ~mask
;
5489 /* Pick the lower word and sign-extend it. */
5490 low
= INTVAL (value
);
5495 /* Pick the higher word, shifted to the least significant
5496 bits, and sign-extend it. */
5497 high
= INTVAL (value
);
5498 high
>>= bits_per_word
- 1;
5501 if (high
& sign_bit
)
5502 high
|= sign_extend
;
5504 /* Store the words in the target machine order. */
5505 if (WORDS_BIG_ENDIAN
)
5507 *first
= GEN_INT (high
);
5508 *second
= GEN_INT (low
);
5512 *first
= GEN_INT (low
);
5513 *second
= GEN_INT (high
);
5518 /* The rule for using CONST_INT for a wider mode
5519 is that we regard the value as signed.
5520 So sign-extend it. */
5521 rtx high
= (INTVAL (value
) < 0 ? constm1_rtx
: const0_rtx
);
5522 if (WORDS_BIG_ENDIAN
)
5534 else if (GET_CODE (value
) == CONST_WIDE_INT
)
5536 /* All of this is scary code and needs to be converted to
5537 properly work with any size integer. */
5538 gcc_assert (CONST_WIDE_INT_NUNITS (value
) == 2);
5539 if (WORDS_BIG_ENDIAN
)
5541 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5542 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5546 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5547 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5550 else if (!CONST_DOUBLE_P (value
))
5552 if (WORDS_BIG_ENDIAN
)
5554 *first
= const0_rtx
;
5560 *second
= const0_rtx
;
5563 else if (GET_MODE (value
) == VOIDmode
5564 /* This is the old way we did CONST_DOUBLE integers. */
5565 || GET_MODE_CLASS (GET_MODE (value
)) == MODE_INT
)
5567 /* In an integer, the words are defined as most and least significant.
5568 So order them by the target's convention. */
5569 if (WORDS_BIG_ENDIAN
)
5571 *first
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5572 *second
= GEN_INT (CONST_DOUBLE_LOW (value
));
5576 *first
= GEN_INT (CONST_DOUBLE_LOW (value
));
5577 *second
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5584 REAL_VALUE_FROM_CONST_DOUBLE (r
, value
);
5586 /* Note, this converts the REAL_VALUE_TYPE to the target's
5587 format, splits up the floating point double and outputs
5588 exactly 32 bits of it into each of l[0] and l[1] --
5589 not necessarily BITS_PER_WORD bits. */
5590 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
5592 /* If 32 bits is an entire word for the target, but not for the host,
5593 then sign-extend on the host so that the number will look the same
5594 way on the host that it would on the target. See for instance
5595 simplify_unary_operation. The #if is needed to avoid compiler
5598 #if HOST_BITS_PER_LONG > 32
5599 if (BITS_PER_WORD
< HOST_BITS_PER_LONG
&& BITS_PER_WORD
== 32)
5601 if (l
[0] & ((long) 1 << 31))
5602 l
[0] |= ((long) (-1) << 32);
5603 if (l
[1] & ((long) 1 << 31))
5604 l
[1] |= ((long) (-1) << 32);
5608 *first
= GEN_INT (l
[0]);
5609 *second
= GEN_INT (l
[1]);
5613 /* Return true if X is a sign_extract or zero_extract from the least
5617 lsb_bitfield_op_p (rtx x
)
5619 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_BITFIELD_OPS
)
5621 machine_mode mode
= GET_MODE (XEXP (x
, 0));
5622 HOST_WIDE_INT len
= INTVAL (XEXP (x
, 1));
5623 HOST_WIDE_INT pos
= INTVAL (XEXP (x
, 2));
5625 return (pos
== (BITS_BIG_ENDIAN
? GET_MODE_PRECISION (mode
) - len
: 0));
5630 /* Strip outer address "mutations" from LOC and return a pointer to the
5631 inner value. If OUTER_CODE is nonnull, store the code of the innermost
5632 stripped expression there.
5634 "Mutations" either convert between modes or apply some kind of
5635 extension, truncation or alignment. */
5638 strip_address_mutations (rtx
*loc
, enum rtx_code
*outer_code
)
5642 enum rtx_code code
= GET_CODE (*loc
);
5643 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
5644 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
5645 used to convert between pointer sizes. */
5646 loc
= &XEXP (*loc
, 0);
5647 else if (lsb_bitfield_op_p (*loc
))
5648 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
5649 acts as a combined truncation and extension. */
5650 loc
= &XEXP (*loc
, 0);
5651 else if (code
== AND
&& CONST_INT_P (XEXP (*loc
, 1)))
5652 /* (and ... (const_int -X)) is used to align to X bytes. */
5653 loc
= &XEXP (*loc
, 0);
5654 else if (code
== SUBREG
5655 && !OBJECT_P (SUBREG_REG (*loc
))
5656 && subreg_lowpart_p (*loc
))
5657 /* (subreg (operator ...) ...) inside and is used for mode
5659 loc
= &SUBREG_REG (*loc
);
5667 /* Return true if CODE applies some kind of scale. The scaled value is
5668 is the first operand and the scale is the second. */
5671 binary_scale_code_p (enum rtx_code code
)
5673 return (code
== MULT
5675 /* Needed by ARM targets. */
5679 || code
== ROTATERT
);
5682 /* If *INNER can be interpreted as a base, return a pointer to the inner term
5683 (see address_info). Return null otherwise. */
5686 get_base_term (rtx
*inner
)
5688 if (GET_CODE (*inner
) == LO_SUM
)
5689 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5692 || GET_CODE (*inner
) == SUBREG
5693 || GET_CODE (*inner
) == SCRATCH
)
5698 /* If *INNER can be interpreted as an index, return a pointer to the inner term
5699 (see address_info). Return null otherwise. */
5702 get_index_term (rtx
*inner
)
5704 /* At present, only constant scales are allowed. */
5705 if (binary_scale_code_p (GET_CODE (*inner
)) && CONSTANT_P (XEXP (*inner
, 1)))
5706 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5709 || GET_CODE (*inner
) == SUBREG
5710 || GET_CODE (*inner
) == SCRATCH
)
5715 /* Set the segment part of address INFO to LOC, given that INNER is the
5719 set_address_segment (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5721 gcc_assert (!info
->segment
);
5722 info
->segment
= loc
;
5723 info
->segment_term
= inner
;
5726 /* Set the base part of address INFO to LOC, given that INNER is the
5730 set_address_base (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5732 gcc_assert (!info
->base
);
5734 info
->base_term
= inner
;
5737 /* Set the index part of address INFO to LOC, given that INNER is the
5741 set_address_index (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5743 gcc_assert (!info
->index
);
5745 info
->index_term
= inner
;
5748 /* Set the displacement part of address INFO to LOC, given that INNER
5749 is the constant term. */
5752 set_address_disp (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5754 gcc_assert (!info
->disp
);
5756 info
->disp_term
= inner
;
5759 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
5760 rest of INFO accordingly. */
5763 decompose_incdec_address (struct address_info
*info
)
5765 info
->autoinc_p
= true;
5767 rtx
*base
= &XEXP (*info
->inner
, 0);
5768 set_address_base (info
, base
, base
);
5769 gcc_checking_assert (info
->base
== info
->base_term
);
5771 /* These addresses are only valid when the size of the addressed
5773 gcc_checking_assert (info
->mode
!= VOIDmode
);
5776 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
5777 of INFO accordingly. */
5780 decompose_automod_address (struct address_info
*info
)
5782 info
->autoinc_p
= true;
5784 rtx
*base
= &XEXP (*info
->inner
, 0);
5785 set_address_base (info
, base
, base
);
5786 gcc_checking_assert (info
->base
== info
->base_term
);
5788 rtx plus
= XEXP (*info
->inner
, 1);
5789 gcc_assert (GET_CODE (plus
) == PLUS
);
5791 info
->base_term2
= &XEXP (plus
, 0);
5792 gcc_checking_assert (rtx_equal_p (*info
->base_term
, *info
->base_term2
));
5794 rtx
*step
= &XEXP (plus
, 1);
5795 rtx
*inner_step
= strip_address_mutations (step
);
5796 if (CONSTANT_P (*inner_step
))
5797 set_address_disp (info
, step
, inner_step
);
5799 set_address_index (info
, step
, inner_step
);
5802 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
5803 values in [PTR, END). Return a pointer to the end of the used array. */
5806 extract_plus_operands (rtx
*loc
, rtx
**ptr
, rtx
**end
)
5809 if (GET_CODE (x
) == PLUS
)
5811 ptr
= extract_plus_operands (&XEXP (x
, 0), ptr
, end
);
5812 ptr
= extract_plus_operands (&XEXP (x
, 1), ptr
, end
);
5816 gcc_assert (ptr
!= end
);
5822 /* Evaluate the likelihood of X being a base or index value, returning
5823 positive if it is likely to be a base, negative if it is likely to be
5824 an index, and 0 if we can't tell. Make the magnitude of the return
5825 value reflect the amount of confidence we have in the answer.
5827 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
5830 baseness (rtx x
, machine_mode mode
, addr_space_t as
,
5831 enum rtx_code outer_code
, enum rtx_code index_code
)
5833 /* Believe *_POINTER unless the address shape requires otherwise. */
5834 if (REG_P (x
) && REG_POINTER (x
))
5836 if (MEM_P (x
) && MEM_POINTER (x
))
5839 if (REG_P (x
) && HARD_REGISTER_P (x
))
5841 /* X is a hard register. If it only fits one of the base
5842 or index classes, choose that interpretation. */
5843 int regno
= REGNO (x
);
5844 bool base_p
= ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
5845 bool index_p
= REGNO_OK_FOR_INDEX_P (regno
);
5846 if (base_p
!= index_p
)
5847 return base_p
? 1 : -1;
5852 /* INFO->INNER describes a normal, non-automodified address.
5853 Fill in the rest of INFO accordingly. */
5856 decompose_normal_address (struct address_info
*info
)
5858 /* Treat the address as the sum of up to four values. */
5860 size_t n_ops
= extract_plus_operands (info
->inner
, ops
,
5861 ops
+ ARRAY_SIZE (ops
)) - ops
;
5863 /* If there is more than one component, any base component is in a PLUS. */
5865 info
->base_outer_code
= PLUS
;
5867 /* Try to classify each sum operand now. Leave those that could be
5868 either a base or an index in OPS. */
5871 for (size_t in
= 0; in
< n_ops
; ++in
)
5874 rtx
*inner
= strip_address_mutations (loc
);
5875 if (CONSTANT_P (*inner
))
5876 set_address_disp (info
, loc
, inner
);
5877 else if (GET_CODE (*inner
) == UNSPEC
)
5878 set_address_segment (info
, loc
, inner
);
5881 /* The only other possibilities are a base or an index. */
5882 rtx
*base_term
= get_base_term (inner
);
5883 rtx
*index_term
= get_index_term (inner
);
5884 gcc_assert (base_term
|| index_term
);
5886 set_address_index (info
, loc
, index_term
);
5887 else if (!index_term
)
5888 set_address_base (info
, loc
, base_term
);
5891 gcc_assert (base_term
== index_term
);
5893 inner_ops
[out
] = base_term
;
5899 /* Classify the remaining OPS members as bases and indexes. */
5902 /* If we haven't seen a base or an index yet, assume that this is
5903 the base. If we were confident that another term was the base
5904 or index, treat the remaining operand as the other kind. */
5906 set_address_base (info
, ops
[0], inner_ops
[0]);
5908 set_address_index (info
, ops
[0], inner_ops
[0]);
5912 /* In the event of a tie, assume the base comes first. */
5913 if (baseness (*inner_ops
[0], info
->mode
, info
->as
, PLUS
,
5915 >= baseness (*inner_ops
[1], info
->mode
, info
->as
, PLUS
,
5916 GET_CODE (*ops
[0])))
5918 set_address_base (info
, ops
[0], inner_ops
[0]);
5919 set_address_index (info
, ops
[1], inner_ops
[1]);
5923 set_address_base (info
, ops
[1], inner_ops
[1]);
5924 set_address_index (info
, ops
[0], inner_ops
[0]);
5928 gcc_assert (out
== 0);
5931 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
5932 or VOIDmode if not known. AS is the address space associated with LOC.
5933 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
5936 decompose_address (struct address_info
*info
, rtx
*loc
, machine_mode mode
,
5937 addr_space_t as
, enum rtx_code outer_code
)
5939 memset (info
, 0, sizeof (*info
));
5942 info
->addr_outer_code
= outer_code
;
5944 info
->inner
= strip_address_mutations (loc
, &outer_code
);
5945 info
->base_outer_code
= outer_code
;
5946 switch (GET_CODE (*info
->inner
))
5952 decompose_incdec_address (info
);
5957 decompose_automod_address (info
);
5961 decompose_normal_address (info
);
5966 /* Describe address operand LOC in INFO. */
5969 decompose_lea_address (struct address_info
*info
, rtx
*loc
)
5971 decompose_address (info
, loc
, VOIDmode
, ADDR_SPACE_GENERIC
, ADDRESS
);
5974 /* Describe the address of MEM X in INFO. */
5977 decompose_mem_address (struct address_info
*info
, rtx x
)
5979 gcc_assert (MEM_P (x
));
5980 decompose_address (info
, &XEXP (x
, 0), GET_MODE (x
),
5981 MEM_ADDR_SPACE (x
), MEM
);
5984 /* Update INFO after a change to the address it describes. */
5987 update_address (struct address_info
*info
)
5989 decompose_address (info
, info
->outer
, info
->mode
, info
->as
,
5990 info
->addr_outer_code
);
5993 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
5994 more complicated than that. */
5997 get_index_scale (const struct address_info
*info
)
5999 rtx index
= *info
->index
;
6000 if (GET_CODE (index
) == MULT
6001 && CONST_INT_P (XEXP (index
, 1))
6002 && info
->index_term
== &XEXP (index
, 0))
6003 return INTVAL (XEXP (index
, 1));
6005 if (GET_CODE (index
) == ASHIFT
6006 && CONST_INT_P (XEXP (index
, 1))
6007 && info
->index_term
== &XEXP (index
, 0))
6008 return (HOST_WIDE_INT
) 1 << INTVAL (XEXP (index
, 1));
6010 if (info
->index
== info
->index_term
)
6016 /* Return the "index code" of INFO, in the form required by
6020 get_index_code (const struct address_info
*info
)
6023 return GET_CODE (*info
->index
);
6026 return GET_CODE (*info
->disp
);
6031 /* Return true if X contains a thread-local symbol. */
6034 tls_referenced_p (const_rtx x
)
6036 if (!targetm
.have_tls
)
6039 subrtx_iterator::array_type array
;
6040 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6041 if (GET_CODE (*iter
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (*iter
) != 0)