| blob | 4b7e665d2c59ea8c296f7a3a4389c796569db0f0 |
1 ;; Machine description the Motorola MCore
2 ;; Copyright (C) 1993-2014 Free Software Foundation, Inc.
3 ;; Contributed by Motorola.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; -------------------------------------------------------------------------
26 ;; Attributes
27 ;; -------------------------------------------------------------------------
29 ; Target CPU.
31 (define_attr "type" "brcond,branch,jmp,load,store,move,alu,shift"
32 (const_string "alu"))
34 ;; If a branch destination is within -2048..2047 bytes away from the
35 ;; instruction it can be 2 bytes long. All other conditional branches
36 ;; are 10 bytes long, and all other unconditional branches are 8 bytes.
37 ;;
38 ;; the assembler handles the long-branch span case for us if we use
39 ;; the "jb*" mnemonics for jumps/branches. This pushes the span
40 ;; calculations and the literal table placement into the assembler,
41 ;; where their interactions can be managed in a single place.
43 ;; All MCORE instructions are two bytes long.
45 (define_attr "length" "" (const_int 2))
47 ;; Scheduling. We only model a simple load latency.
48 (define_insn_reservation "any_insn" 1
49 (eq_attr "type" "!load")
50 "nothing")
51 (define_insn_reservation "memory" 2
52 (eq_attr "type" "load")
53 "nothing")
55 (include "predicates.md")
56 (include "constraints.md")
58 ;; -------------------------------------------------------------------------
59 ;; Test and bit test
60 ;; -------------------------------------------------------------------------
62 (define_insn ""
63 [(set (reg:SI 17)
64 (sign_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
65 (const_int 1)
66 (match_operand:SI 1 "mcore_literal_K_operand" "K")))]
67 ""
68 "btsti %0,%1"
69 [(set_attr "type" "shift")])
71 (define_insn ""
72 [(set (reg:SI 17)
73 (zero_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
74 (const_int 1)
75 (match_operand:SI 1 "mcore_literal_K_operand" "K")))]
76 ""
77 "btsti %0,%1"
78 [(set_attr "type" "shift")])
80 ;;; This is created by combine.
81 (define_insn ""
82 [(set (reg:CC 17)
83 (ne:CC (zero_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
84 (const_int 1)
85 (match_operand:SI 1 "mcore_literal_K_operand" "K"))
86 (const_int 0)))]
87 ""
88 "btsti %0,%1"
89 [(set_attr "type" "shift")])
92 ;; Created by combine from conditional patterns below (see sextb/btsti rx,31)
94 (define_insn ""
95 [(set (reg:CC 17)
96 (ne:CC (lshiftrt:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
97 (const_int 7))
98 (const_int 0)))]
99 "GET_CODE(operands[0]) == SUBREG &&
100 GET_MODE(SUBREG_REG(operands[0])) == QImode"
101 "btsti %0,7"
102 [(set_attr "type" "shift")])
104 (define_insn ""
105 [(set (reg:CC 17)
106 (ne:CC (lshiftrt:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
107 (const_int 15))
108 (const_int 0)))]
109 "GET_CODE(operands[0]) == SUBREG &&
110 GET_MODE(SUBREG_REG(operands[0])) == HImode"
111 "btsti %0,15"
112 [(set_attr "type" "shift")])
114 (define_split
115 [(set (pc)
116 (if_then_else (ne (eq:CC (zero_extract:SI
117 (match_operand:SI 0 "mcore_arith_reg_operand" "")
118 (const_int 1)
119 (match_operand:SI 1 "mcore_literal_K_operand" ""))
120 (const_int 0))
121 (const_int 0))
122 (label_ref (match_operand 2 "" ""))
123 (pc)))]
124 ""
125 [(set (reg:CC 17)
126 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))
127 (set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
128 (label_ref (match_dup 2))
129 (pc)))]
130 "")
132 (define_split
133 [(set (pc)
134 (if_then_else (eq (ne:CC (zero_extract:SI
135 (match_operand:SI 0 "mcore_arith_reg_operand" "")
136 (const_int 1)
137 (match_operand:SI 1 "mcore_literal_K_operand" ""))
138 (const_int 0))
139 (const_int 0))
140 (label_ref (match_operand 2 "" ""))
141 (pc)))]
142 ""
143 [(set (reg:CC 17)
144 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))
145 (set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
146 (label_ref (match_dup 2))
147 (pc)))]
148 "")
150 ;; XXX - disabled by nickc because it fails on libiberty/fnmatch.c
151 ;;
152 ;; ; Experimental - relax immediates for and, andn, or, and tst to allow
153 ;; ; any immediate value (or an immediate at all -- or, andn, & tst).
154 ;; ; This is done to allow bit field masks to fold together in combine.
155 ;; ; The reload phase will force the immediate into a register at the
156 ;; ; very end. This helps in some cases, but hurts in others: we'd
157 ;; ; really like to cse these immediates. However, there is a phase
158 ;; ; ordering problem here. cse picks up individual masks and cse's
159 ;; ; those, but not folded masks (cse happens before combine). It's
160 ;; ; not clear what the best solution is because we really want cse
161 ;; ; before combine (leaving the bit field masks alone). To pick up
162 ;; ; relaxed immediates use -mrelax-immediates. It might take some
163 ;; ; experimenting to see which does better (i.e. regular imms vs.
164 ;; ; arbitrary imms) for a particular code. BRC
165 ;;
166 ;; (define_insn ""
167 ;; [(set (reg:CC 17)
168 ;; (ne:CC (and:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
169 ;; (match_operand:SI 1 "mcore_arith_any_imm_operand" "rI"))
170 ;; (const_int 0)))]
171 ;; "TARGET_RELAX_IMM"
172 ;; "tst %0,%1")
173 ;;
174 ;; (define_insn ""
175 ;; [(set (reg:CC 17)
176 ;; (ne:CC (and:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
177 ;; (match_operand:SI 1 "mcore_arith_M_operand" "r"))
178 ;; (const_int 0)))]
179 ;; "!TARGET_RELAX_IMM"
180 ;; "tst %0,%1")
182 (define_insn ""
183 [(set (reg:CC 17)
184 (ne:CC (and:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
185 (match_operand:SI 1 "mcore_arith_M_operand" "r"))
186 (const_int 0)))]
187 ""
188 "tst %0,%1")
191 (define_split
192 [(parallel[
193 (set (reg:CC 17)
194 (ne:CC (ne:SI (leu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "")
195 (match_operand:SI 1 "mcore_arith_reg_operand" ""))
196 (const_int 0))
197 (const_int 0)))
198 (clobber (match_operand:CC 2 "mcore_arith_reg_operand" ""))])]
199 ""
200 [(set (reg:CC 17) (ne:SI (match_dup 0) (const_int 0)))
201 (set (reg:CC 17) (leu:CC (match_dup 0) (match_dup 1)))])
203 ;; -------------------------------------------------------------------------
204 ;; SImode signed integer comparisons
205 ;; -------------------------------------------------------------------------
207 (define_insn "decne_t"
208 [(set (reg:CC 17) (ne:CC (plus:SI (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
209 (const_int -1))
210 (const_int 0)))
211 (set (match_dup 0)
212 (plus:SI (match_dup 0)
213 (const_int -1)))]
214 ""
215 "decne %0")
217 ;; The combiner seems to prefer the following to the former.
218 ;;
219 (define_insn ""
220 [(set (reg:CC 17) (ne:CC (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
221 (const_int 1)))
222 (set (match_dup 0)
223 (plus:SI (match_dup 0)
224 (const_int -1)))]
225 ""
226 "decne %0")
228 (define_insn "cmpnesi_t"
229 [(set (reg:CC 17) (ne:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
230 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
231 ""
232 "cmpne %0,%1")
234 (define_insn "cmpneisi_t"
235 [(set (reg:CC 17) (ne:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
236 (match_operand:SI 1 "mcore_arith_K_operand" "K")))]
237 ""
238 "cmpnei %0,%1")
240 (define_insn "cmpgtsi_t"
241 [(set (reg:CC 17) (gt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
242 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
243 ""
244 "cmplt %1,%0")
246 (define_insn ""
247 [(set (reg:CC 17) (gt:CC (plus:SI
248 (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
249 (const_int -1))
250 (const_int 0)))
251 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
252 ""
253 "decgt %0")
255 (define_insn "cmpltsi_t"
256 [(set (reg:CC 17) (lt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
257 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
258 ""
259 "cmplt %0,%1")
261 ; cmplti is 1-32
262 (define_insn "cmpltisi_t"
263 [(set (reg:CC 17) (lt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
264 (match_operand:SI 1 "mcore_arith_J_operand" "J")))]
265 ""
266 "cmplti %0,%1")
268 ; covers cmplti x,0
269 (define_insn ""
270 [(set (reg:CC 17) (lt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
271 (const_int 0)))]
272 ""
273 "btsti %0,31")
275 (define_insn ""
276 [(set (reg:CC 17) (lt:CC (plus:SI
277 (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
278 (const_int -1))
279 (const_int 0)))
280 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
281 ""
282 "declt %0")
284 ;; -------------------------------------------------------------------------
285 ;; SImode unsigned integer comparisons
286 ;; -------------------------------------------------------------------------
288 (define_insn "cmpgeusi_t"
289 [(set (reg:CC 17) (geu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
290 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
291 ""
292 "cmphs %0,%1")
294 (define_insn "cmpgeusi_0"
295 [(set (reg:CC 17) (geu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
296 (const_int 0)))]
297 ""
298 "cmpnei %0, 0")
300 (define_insn "cmpleusi_t"
301 [(set (reg:CC 17) (leu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
302 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
303 ""
304 "cmphs %1,%0")
306 ;; -------------------------------------------------------------------------
307 ;; Logical operations
308 ;; -------------------------------------------------------------------------
310 ;; Logical AND clearing a single bit. andsi3 knows that we have this
311 ;; pattern and allows the constant literal pass through.
312 ;;
314 ;; RBE 2/97: don't need this pattern any longer...
315 ;; RBE: I don't think we need both "S" and exact_log2() clauses.
316 ;;(define_insn ""
317 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
318 ;; (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
319 ;; (match_operand:SI 2 "const_int_operand" "S")))]
320 ;; "mcore_arith_S_operand (operands[2])"
321 ;; "bclri %0,%Q2")
322 ;;
324 (define_insn "andnsi3"
325 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
326 (and:SI (not:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))
327 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
328 ""
329 "andn %0,%1")
331 (define_expand "andsi3"
332 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
333 (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
334 (match_operand:SI 2 "nonmemory_operand" "")))]
335 ""
336 "
337 {
338 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0
339 && ! mcore_arith_S_operand (operands[2]))
340 {
341 HOST_WIDE_INT not_value = ~ INTVAL (operands[2]);
343 if ( CONST_OK_FOR_I (not_value)
344 || CONST_OK_FOR_M (not_value)
345 || CONST_OK_FOR_N (not_value))
346 {
347 operands[2] = copy_to_mode_reg (SImode, GEN_INT (not_value));
348 emit_insn (gen_andnsi3 (operands[0], operands[2], operands[1]));
349 DONE;
350 }
351 }
353 if (! mcore_arith_K_S_operand (operands[2], SImode))
354 operands[2] = copy_to_mode_reg (SImode, operands[2]);
355 }")
357 (define_insn ""
358 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
359 (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0,r,0")
360 (match_operand:SI 2 "mcore_arith_any_imm_operand" "r,K,0,S")))]
361 "TARGET_RELAX_IMM"
362 "*
363 {
364 switch (which_alternative)
365 {
366 case 0: return \"and %0,%2\";
367 case 1: return \"andi %0,%2\";
368 case 2: return \"and %0,%1\";
369 /* case -1: return \"bclri %0,%Q2\"; will not happen */
370 case 3: return mcore_output_bclri (operands[0], INTVAL (operands[2]));
371 default: gcc_unreachable ();
372 }
373 }")
375 ;; This was the old "S" which was "!(2^n)" */
376 ;; case -1: return \"bclri %0,%Q2\"; will not happen */
378 (define_insn ""
379 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
380 (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0,r,0")
381 (match_operand:SI 2 "mcore_arith_K_S_operand" "r,K,0,S")))]
382 "!TARGET_RELAX_IMM"
383 "*
384 {
385 switch (which_alternative)
386 {
387 case 0: return \"and %0,%2\";
388 case 1: return \"andi %0,%2\";
389 case 2: return \"and %0,%1\";
390 case 3: return mcore_output_bclri (operands[0], INTVAL (operands[2]));
391 default: gcc_unreachable ();
392 }
393 }")
395 ;(define_insn "iorsi3"
396 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
397 ; (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
398 ; (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
399 ; ""
400 ; "or %0,%2")
402 ; need an expand to resolve ambiguity betw. the two iors below.
403 (define_expand "iorsi3"
404 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
405 (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
406 (match_operand:SI 2 "nonmemory_operand" "")))]
407 ""
408 "
409 {
410 if (! mcore_arith_M_operand (operands[2], SImode))
411 operands[2] = copy_to_mode_reg (SImode, operands[2]);
412 }")
414 (define_insn ""
415 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
416 (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
417 (match_operand:SI 2 "mcore_arith_any_imm_operand" "r,M,T")))]
418 "TARGET_RELAX_IMM"
419 "*
420 {
421 switch (which_alternative)
422 {
423 case 0: return \"or %0,%2\";
424 case 1: return \"bseti %0,%P2\";
425 case 2: return mcore_output_bseti (operands[0], INTVAL (operands[2]));
426 default: gcc_unreachable ();
427 }
428 }")
430 (define_insn ""
431 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
432 (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
433 (match_operand:SI 2 "mcore_arith_M_operand" "r,M,T")))]
434 "!TARGET_RELAX_IMM"
435 "*
436 {
437 switch (which_alternative)
438 {
439 case 0: return \"or %0,%2\";
440 case 1: return \"bseti %0,%P2\";
441 case 2: return mcore_output_bseti (operands[0], INTVAL (operands[2]));
442 default: gcc_unreachable ();
443 }
444 }")
446 ;(define_insn ""
447 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
448 ; (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
449 ; (match_operand:SI 2 "const_int_operand" "M")))]
450 ; "exact_log2 (INTVAL (operands[2])) >= 0"
451 ; "bseti %0,%P2")
453 ;(define_insn ""
454 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
455 ; (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
456 ; (match_operand:SI 2 "const_int_operand" "i")))]
457 ; "mcore_num_ones (INTVAL (operands[2])) < 3"
458 ; "* return mcore_output_bseti (operands[0], INTVAL (operands[2]));")
460 (define_insn "xorsi3"
461 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
462 (xor:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
463 (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
464 ""
465 "xor %0,%2")
467 ;; -------------------------------------------------------------------------
468 ;; Shifts and rotates
469 ;; -------------------------------------------------------------------------
471 ;; Only allow these if the shift count is a convenient constant.
472 (define_expand "rotlsi3"
473 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
474 (rotate:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
475 (match_operand:SI 2 "nonmemory_operand" "")))]
476 ""
477 "if (! mcore_literal_K_operand (operands[2], SImode))
478 FAIL;
479 ")
481 ;; We can only do constant rotates, which is what this pattern provides.
482 ;; The combiner will put it together for us when we do:
483 ;; (x << N) | (x >> (32 - N))
484 (define_insn ""
485 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
486 (rotate:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
487 (match_operand:SI 2 "mcore_literal_K_operand" "K")))]
488 ""
489 "rotli %0,%2"
490 [(set_attr "type" "shift")])
492 (define_insn "ashlsi3"
493 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
494 (ashift:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0")
495 (match_operand:SI 2 "mcore_arith_K_operand_not_0" "r,K")))]
496 ""
497 "@
498 lsl %0,%2
499 lsli %0,%2"
500 [(set_attr "type" "shift")])
502 (define_insn ""
503 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
504 (ashift:SI (const_int 1)
505 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
506 ""
507 "bgenr %0,%1"
508 [(set_attr "type" "shift")])
510 (define_insn "ashrsi3"
511 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
512 (ashiftrt:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0")
513 (match_operand:SI 2 "mcore_arith_K_operand_not_0" "r,K")))]
514 ""
515 "@
516 asr %0,%2
517 asri %0,%2"
518 [(set_attr "type" "shift")])
520 (define_insn "lshrsi3"
521 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
522 (lshiftrt:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0")
523 (match_operand:SI 2 "mcore_arith_K_operand_not_0" "r,K")))]
524 ""
525 "@
526 lsr %0,%2
527 lsri %0,%2"
528 [(set_attr "type" "shift")])
530 ;(define_expand "ashldi3"
531 ; [(parallel[(set (match_operand:DI 0 "mcore_arith_reg_operand" "")
532 ; (ashift:DI (match_operand:DI 1 "mcore_arith_reg_operand" "")
533 ; (match_operand:DI 2 "immediate_operand" "")))
534 ;
535 ; (clobber (reg:CC 17))])]
536 ;
537 ; ""
538 ; "
539 ;{
540 ; if (GET_CODE (operands[2]) != CONST_INT
541 ; || INTVAL (operands[2]) != 1)
542 ; FAIL;
543 ;}")
544 ;
545 ;(define_insn ""
546 ; [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=r")
547 ; (ashift:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
548 ; (const_int 1)))
549 ; (clobber (reg:CC 17))]
550 ; ""
551 ; "lsli %R0,0\;rotli %0,0"
552 ; [(set_attr "length" "4") (set_attr "type" "shift")])
554 ;; -------------------------------------------------------------------------
555 ;; Index instructions
556 ;; -------------------------------------------------------------------------
557 ;; The second of each set of patterns is borrowed from the alpha.md file.
558 ;; These variants of the above insns can occur if the second operand
559 ;; is the frame pointer. This is a kludge, but there doesn't
560 ;; seem to be a way around it. Only recognize them while reloading.
562 ;; We must use reload_operand for some operands in case frame pointer
563 ;; elimination put a MEM with invalid address there. Otherwise,
564 ;; the result of the substitution will not match this pattern, and reload
565 ;; will not be able to correctly fix the result.
567 ;; indexing longlongs or doubles (8 bytes)
569 (define_insn "indexdi_t"
570 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
571 (plus:SI (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
572 (const_int 8))
573 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
574 ""
575 "*
576 if (! mcore_is_same_reg (operands[1], operands[2]))
577 {
578 output_asm_insn (\"ixw\\t%0,%1\", operands);
579 output_asm_insn (\"ixw\\t%0,%1\", operands);
580 }
581 else
582 {
583 output_asm_insn (\"ixh\\t%0,%1\", operands);
584 output_asm_insn (\"ixh\\t%0,%1\", operands);
585 }
586 return \"\";
587 "
588 ;; if operands[1] == operands[2], the first option above is wrong! -- dac
589 ;; was this... -- dac
590 ;; ixw %0,%1\;ixw %0,%1"
592 [(set_attr "length" "4")])
594 (define_insn ""
595 [(set (match_operand:SI 0 "mcore_reload_operand" "=r,r,r")
596 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "mcore_reload_operand" "r,r,r")
597 (const_int 8))
598 (match_operand:SI 2 "mcore_arith_reg_operand" "0,0,0"))
599 (match_operand:SI 3 "mcore_addsub_operand" "r,J,L")))]
600 "reload_in_progress"
601 "@
602 ixw %0,%1\;ixw %0,%1\;addu %0,%3
603 ixw %0,%1\;ixw %0,%1\;addi %0,%3
604 ixw %0,%1\;ixw %0,%1\;subi %0,%M3"
605 [(set_attr "length" "6")])
607 ;; indexing longs (4 bytes)
609 (define_insn "indexsi_t"
610 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
611 (plus:SI (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
612 (const_int 4))
613 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
614 ""
615 "ixw %0,%1")
617 (define_insn ""
618 [(set (match_operand:SI 0 "mcore_reload_operand" "=r,r,r")
619 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "mcore_reload_operand" "r,r,r")
620 (const_int 4))
621 (match_operand:SI 2 "mcore_arith_reg_operand" "0,0,0"))
622 (match_operand:SI 3 "mcore_addsub_operand" "r,J,L")))]
623 "reload_in_progress"
624 "@
625 ixw %0,%1\;addu %0,%3
626 ixw %0,%1\;addi %0,%3
627 ixw %0,%1\;subi %0,%M3"
628 [(set_attr "length" "4")])
630 ;; indexing shorts (2 bytes)
632 (define_insn "indexhi_t"
633 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
634 (plus:SI (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
635 (const_int 2))
636 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
637 ""
638 "ixh %0,%1")
640 (define_insn ""
641 [(set (match_operand:SI 0 "mcore_reload_operand" "=r,r,r")
642 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "mcore_reload_operand" "r,r,r")
643 (const_int 2))
644 (match_operand:SI 2 "mcore_arith_reg_operand" "0,0,0"))
645 (match_operand:SI 3 "mcore_addsub_operand" "r,J,L")))]
646 "reload_in_progress"
647 "@
648 ixh %0,%1\;addu %0,%3
649 ixh %0,%1\;addi %0,%3
650 ixh %0,%1\;subi %0,%M3"
651 [(set_attr "length" "4")])
653 ;;
654 ;; Other sizes may be handy for indexing.
655 ;; the tradeoffs to consider when adding these are
656 ;; code size, execution time [vs. mul it is easy to win],
657 ;; and register pressure -- these patterns don't use an extra
658 ;; register to build the offset from the base
659 ;; and whether the compiler will not come up with some other idiom.
660 ;;
662 ;; -------------------------------------------------------------------------
663 ;; Addition, Subtraction instructions
664 ;; -------------------------------------------------------------------------
666 (define_expand "addsi3"
667 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
668 (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
669 (match_operand:SI 2 "nonmemory_operand" "")))]
670 ""
671 "
672 {
673 /* If this is an add to the frame pointer, then accept it as is so
674 that we can later fold in the fp/sp offset from frame pointer
675 elimination. */
676 if (flag_omit_frame_pointer
677 && GET_CODE (operands[1]) == REG
678 && (REGNO (operands[1]) == VIRTUAL_STACK_VARS_REGNUM
679 || REGNO (operands[1]) == FRAME_POINTER_REGNUM))
680 {
681 emit_insn (gen_addsi3_fp (operands[0], operands[1], operands[2]));
682 DONE;
683 }
685 /* Convert adds to subtracts if this makes loading the constant cheaper.
686 But only if we are allowed to generate new pseudos. */
687 if (! (reload_in_progress || reload_completed)
688 && GET_CODE (operands[2]) == CONST_INT
689 && INTVAL (operands[2]) < -32)
690 {
691 HOST_WIDE_INT neg_value = - INTVAL (operands[2]);
693 if ( CONST_OK_FOR_I (neg_value)
694 || CONST_OK_FOR_M (neg_value)
695 || CONST_OK_FOR_N (neg_value))
696 {
697 operands[2] = copy_to_mode_reg (SImode, GEN_INT (neg_value));
698 emit_insn (gen_subsi3 (operands[0], operands[1], operands[2]));
699 DONE;
700 }
701 }
703 if (! mcore_addsub_operand (operands[2], SImode))
704 operands[2] = copy_to_mode_reg (SImode, operands[2]);
705 }")
707 ;; RBE: for some constants which are not in the range which allows
708 ;; us to do a single operation, we will try a paired addi/addi instead
709 ;; of a movi/addi. This relieves some register pressure at the expense
710 ;; of giving away some potential constant reuse.
711 ;;
712 ;; RBE 6/17/97: this didn't buy us anything, but I keep the pattern
713 ;; for later reference
714 ;;
715 ;; (define_insn "addsi3_i2"
716 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
717 ;; (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
718 ;; (match_operand:SI 2 "const_int_operand" "g")))]
719 ;; "GET_CODE(operands[2]) == CONST_INT
720 ;; && ((INTVAL (operands[2]) > 32 && INTVAL(operands[2]) <= 64)
721 ;; || (INTVAL (operands[2]) < -32 && INTVAL(operands[2]) >= -64))"
722 ;; "*
723 ;; {
724 ;; HOST_WIDE_INT n = INTVAL(operands[2]);
725 ;; if (n > 0)
726 ;; {
727 ;; operands[2] = GEN_INT(n - 32);
728 ;; return \"addi\\t%0,32\;addi\\t%0,%2\";
729 ;; }
730 ;; else
731 ;; {
732 ;; n = (-n);
733 ;; operands[2] = GEN_INT(n - 32);
734 ;; return \"subi\\t%0,32\;subi\\t%0,%2\";
735 ;; }
736 ;; }"
737 ;; [(set_attr "length" "4")])
739 (define_insn "addsi3_i"
740 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
741 (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
742 (match_operand:SI 2 "mcore_addsub_operand" "r,J,L")))]
743 ""
744 "@
745 addu %0,%2
746 addi %0,%2
747 subi %0,%M2")
749 ;; This exists so that address computations based on the frame pointer
750 ;; can be folded in when frame pointer elimination occurs. Ordinarily
751 ;; this would be bad because it allows insns which would require reloading,
752 ;; but without it, we get multiple adds where one would do.
754 (define_insn "addsi3_fp"
755 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
756 (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
757 (match_operand:SI 2 "immediate_operand" "r,J,L")))]
758 "flag_omit_frame_pointer
759 && (reload_in_progress || reload_completed || REGNO (operands[1]) == FRAME_POINTER_REGNUM)"
760 "@
761 addu %0,%2
762 addi %0,%2
763 subi %0,%M2")
765 ;; RBE: for some constants which are not in the range which allows
766 ;; us to do a single operation, we will try a paired addi/addi instead
767 ;; of a movi/addi. This relieves some register pressure at the expense
768 ;; of giving away some potential constant reuse.
769 ;;
770 ;; RBE 6/17/97: this didn't buy us anything, but I keep the pattern
771 ;; for later reference
772 ;;
773 ;; (define_insn "subsi3_i2"
774 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
775 ;; (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
776 ;; (match_operand:SI 2 "const_int_operand" "g")))]
777 ;; "TARGET_RBETEST && GET_CODE(operands[2]) == CONST_INT
778 ;; && ((INTVAL (operands[2]) > 32 && INTVAL(operands[2]) <= 64)
779 ;; || (INTVAL (operands[2]) < -32 && INTVAL(operands[2]) >= -64))"
780 ;; "*
781 ;; {
782 ;; HOST_WIDE_INT n = INTVAL(operands[2]);
783 ;; if ( n > 0)
784 ;; {
785 ;; operands[2] = GEN_INT( n - 32);
786 ;; return \"subi\\t%0,32\;subi\\t%0,%2\";
787 ;; }
788 ;; else
789 ;; {
790 ;; n = (-n);
791 ;; operands[2] = GEN_INT(n - 32);
792 ;; return \"addi\\t%0,32\;addi\\t%0,%2\";
793 ;; }
794 ;; }"
795 ;; [(set_attr "length" "4")])
797 ;(define_insn "subsi3"
798 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
799 ; (minus:SI (match_operand:SI 1 "mcore_arith_K_operand" "0,0,r,K")
800 ; (match_operand:SI 2 "mcore_arith_J_operand" "r,J,0,0")))]
801 ; ""
802 ; "@
803 ; sub %0,%2
804 ; subi %0,%2
805 ; rsub %0,%1
806 ; rsubi %0,%1")
808 (define_insn "subsi3"
809 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
810 (minus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0,r")
811 (match_operand:SI 2 "mcore_arith_J_operand" "r,J,0")))]
812 ""
813 "@
814 subu %0,%2
815 subi %0,%2
816 rsub %0,%1")
818 (define_insn ""
819 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
820 (minus:SI (match_operand:SI 1 "mcore_literal_K_operand" "K")
821 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
822 ""
823 "rsubi %0,%1")
825 (define_insn "adddi3"
826 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
827 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
828 (match_operand:DI 2 "mcore_arith_reg_operand" "r")))
829 (clobber (reg:CC 17))]
830 ""
831 "*
832 {
833 if (TARGET_LITTLE_END)
834 return \"cmplt %0,%0\;addc %0,%2\;addc %R0,%R2\";
835 return \"cmplt %R0,%R0\;addc %R0,%R2\;addc %0,%2\";
836 }"
837 [(set_attr "length" "6")])
839 ;; special case for "longlong += 1"
840 (define_insn ""
841 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
842 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
843 (const_int 1)))
844 (clobber (reg:CC 17))]
845 ""
846 "*
847 {
848 if (TARGET_LITTLE_END)
849 return \"addi %0,1\;cmpnei %0,0\;incf %R0\";
850 return \"addi %R0,1\;cmpnei %R0,0\;incf %0\";
851 }"
852 [(set_attr "length" "6")])
854 ;; special case for "longlong -= 1"
855 (define_insn ""
856 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
857 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
858 (const_int -1)))
859 (clobber (reg:CC 17))]
860 ""
861 "*
862 {
863 if (TARGET_LITTLE_END)
864 return \"cmpnei %0,0\;decf %R0\;subi %0,1\";
865 return \"cmpnei %R0,0\;decf %0\;subi %R0,1\";
866 }"
867 [(set_attr "length" "6")])
869 ;; special case for "longlong += const_int"
870 ;; we have to use a register for the const_int because we don't
871 ;; have an unsigned compare immediate... only +/- 1 get to
872 ;; play the no-extra register game because they compare with 0.
873 ;; This winds up working out for any literal that is synthesized
874 ;; with a single instruction. The more complicated ones look
875 ;; like the get broken into subreg's to get initialized too soon
876 ;; for us to catch here. -- RBE 4/25/96
877 ;; only allow for-sure positive values.
879 (define_insn ""
880 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
881 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
882 (match_operand:SI 2 "const_int_operand" "r")))
883 (clobber (reg:CC 17))]
884 "GET_CODE (operands[2]) == CONST_INT
885 && INTVAL (operands[2]) > 0 && ! (INTVAL (operands[2]) & 0x80000000)"
886 "*
887 {
888 gcc_assert (GET_MODE (operands[2]) == SImode);
889 if (TARGET_LITTLE_END)
890 return \"addu %0,%2\;cmphs %0,%2\;incf %R0\";
891 return \"addu %R0,%2\;cmphs %R0,%2\;incf %0\";
892 }"
893 [(set_attr "length" "6")])
895 ;; optimize "long long" + "unsigned long"
896 ;; won't trigger because of how the extension is expanded upstream.
897 ;; (define_insn ""
898 ;; [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
899 ;; (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
900 ;; (zero_extend:DI (match_operand:SI 2 "mcore_arith_reg_operand" "r"))))
901 ;; (clobber (reg:CC 17))]
902 ;; "0"
903 ;; "cmplt %R0,%R0\;addc %R0,%2\;inct %0"
904 ;; [(set_attr "length" "6")])
906 ;; optimize "long long" + "signed long"
907 ;; won't trigger because of how the extension is expanded upstream.
908 ;; (define_insn ""
909 ;; [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
910 ;; (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
911 ;; (sign_extend:DI (match_operand:SI 2 "mcore_arith_reg_operand" "r"))))
912 ;; (clobber (reg:CC 17))]
913 ;; "0"
914 ;; "cmplt %R0,%R0\;addc %R0,%2\;inct %0\;btsti %2,31\;dect %0"
915 ;; [(set_attr "length" "6")])
917 (define_insn "subdi3"
918 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
919 (minus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
920 (match_operand:DI 2 "mcore_arith_reg_operand" "r")))
921 (clobber (reg:CC 17))]
922 ""
923 "*
924 {
925 if (TARGET_LITTLE_END)
926 return \"cmphs %0,%0\;subc %0,%2\;subc %R0,%R2\";
927 return \"cmphs %R0,%R0\;subc %R0,%R2\;subc %0,%2\";
928 }"
929 [(set_attr "length" "6")])
931 ;; -------------------------------------------------------------------------
932 ;; Multiplication instructions
933 ;; -------------------------------------------------------------------------
935 (define_insn "mulsi3"
936 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
937 (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
938 (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
939 ""
940 "mult %0,%2")
942 ;;
943 ;; 32/32 signed division -- added to the MCORE instruction set spring 1997
944 ;;
945 ;; Different constraints based on the architecture revision...
946 ;;
947 (define_expand "divsi3"
948 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
949 (div:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
950 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
951 "TARGET_DIV"
952 "")
954 ;; MCORE Revision 1.50: restricts the divisor to be in r1. (6/97)
955 ;;
956 (define_insn ""
957 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
958 (div:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
959 (match_operand:SI 2 "mcore_arith_reg_operand" "b")))]
960 "TARGET_DIV"
961 "divs %0,%2")
963 ;;
964 ;; 32/32 signed division -- added to the MCORE instruction set spring 1997
965 ;;
966 ;; Different constraints based on the architecture revision...
967 ;;
968 (define_expand "udivsi3"
969 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
970 (udiv:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
971 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
972 "TARGET_DIV"
973 "")
975 ;; MCORE Revision 1.50: restricts the divisor to be in r1. (6/97)
976 (define_insn ""
977 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
978 (udiv:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
979 (match_operand:SI 2 "mcore_arith_reg_operand" "b")))]
980 "TARGET_DIV"
981 "divu %0,%2")
983 ;; -------------------------------------------------------------------------
984 ;; Unary arithmetic
985 ;; -------------------------------------------------------------------------
987 (define_insn "negsi2"
988 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
989 (neg:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
990 ""
991 "*
992 {
993 return \"rsubi %0,0\";
994 }")
997 (define_insn "abssi2"
998 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
999 (abs:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1000 ""
1001 "abs %0")
1003 (define_insn "negdi2"
1004 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
1005 (neg:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")))
1006 (clobber (reg:CC 17))]
1007 ""
1008 "*
1009 {
1010 if (TARGET_LITTLE_END)
1011 return \"cmpnei %0,0\\n\\trsubi %0,0\\n\\tnot %R0\\n\\tincf %R0\";
1012 return \"cmpnei %R0,0\\n\\trsubi %R0,0\\n\\tnot %0\\n\\tincf %0\";
1013 }"
1014 [(set_attr "length" "8")])
1016 (define_insn "one_cmplsi2"
1017 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1018 (not:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1019 ""
1020 "not %0")
1022 ;; -------------------------------------------------------------------------
1023 ;; Zero extension instructions
1024 ;; -------------------------------------------------------------------------
1026 (define_expand "zero_extendhisi2"
1027 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1028 (zero_extend:SI (match_operand:HI 1 "mcore_arith_reg_operand" "")))]
1029 ""
1030 "")
1032 (define_insn ""
1033 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
1034 (zero_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
1035 ""
1036 "@
1037 zexth %0
1038 ld.h %0,%1"
1039 [(set_attr "type" "shift,load")])
1041 ;; ldh gives us a free zero-extension. The combiner picks up on this.
1042 (define_insn ""
1043 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1044 (zero_extend:SI (mem:HI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))))]
1045 ""
1046 "ld.h %0,(%1)"
1047 [(set_attr "type" "load")])
1049 (define_insn ""
1050 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1051 (zero_extend:SI (mem:HI (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
1052 (match_operand:SI 2 "const_int_operand" "")))))]
1053 "(INTVAL (operands[2]) >= 0) &&
1054 (INTVAL (operands[2]) < 32) &&
1055 ((INTVAL (operands[2])&1) == 0)"
1056 "ld.h %0,(%1,%2)"
1057 [(set_attr "type" "load")])
1059 (define_expand "zero_extendqisi2"
1060 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1061 (zero_extend:SI (match_operand:QI 1 "general_operand" "")))]
1062 ""
1063 "")
1065 ;; RBE: XXX: we don't recognize that the xtrb3 kills the CC register.
1066 (define_insn ""
1067 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b,r")
1068 (zero_extend:SI (match_operand:QI 1 "general_operand" "0,r,m")))]
1069 ""
1070 "@
1071 zextb %0
1072 xtrb3 %0,%1
1073 ld.b %0,%1"
1074 [(set_attr "type" "shift,shift,load")])
1076 ;; ldb gives us a free zero-extension. The combiner picks up on this.
1077 (define_insn ""
1078 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1079 (zero_extend:SI (mem:QI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))))]
1080 ""
1081 "ld.b %0,(%1)"
1082 [(set_attr "type" "load")])
1084 (define_insn ""
1085 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1086 (zero_extend:SI (mem:QI (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
1087 (match_operand:SI 2 "const_int_operand" "")))))]
1088 "(INTVAL (operands[2]) >= 0) &&
1089 (INTVAL (operands[2]) < 16)"
1090 "ld.b %0,(%1,%2)"
1091 [(set_attr "type" "load")])
1093 (define_expand "zero_extendqihi2"
1094 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "")
1095 (zero_extend:HI (match_operand:QI 1 "general_operand" "")))]
1096 ""
1097 "")
1099 ;; RBE: XXX: we don't recognize that the xtrb3 kills the CC register.
1100 (define_insn ""
1101 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r,b,r")
1102 (zero_extend:HI (match_operand:QI 1 "general_operand" "0,r,m")))]
1103 ""
1104 "@
1105 zextb %0
1106 xtrb3 %0,%1
1107 ld.b %0,%1"
1108 [(set_attr "type" "shift,shift,load")])
1110 ;; ldb gives us a free zero-extension. The combiner picks up on this.
1111 ;; this doesn't catch references that are into a structure.
1112 ;; note that normally the compiler uses the above insn, unless it turns
1113 ;; out that we're dealing with a volatile...
1114 (define_insn ""
1115 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
1116 (zero_extend:HI (mem:QI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))))]
1117 ""
1118 "ld.b %0,(%1)"
1119 [(set_attr "type" "load")])
1121 (define_insn ""
1122 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
1123 (zero_extend:HI (mem:QI (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
1124 (match_operand:SI 2 "const_int_operand" "")))))]
1125 "(INTVAL (operands[2]) >= 0) &&
1126 (INTVAL (operands[2]) < 16)"
1127 "ld.b %0,(%1,%2)"
1128 [(set_attr "type" "load")])
1131 ;; -------------------------------------------------------------------------
1132 ;; Sign extension instructions
1133 ;; -------------------------------------------------------------------------
1135 (define_expand "extendsidi2"
1136 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=r")
1137 (match_operand:SI 1 "mcore_arith_reg_operand" "r"))]
1138 ""
1139 "
1140 {
1141 int low, high;
1143 if (TARGET_LITTLE_END)
1144 low = 0, high = 4;
1145 else
1146 low = 4, high = 0;
1148 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], low),
1149 operands[1]));
1150 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], high),
1151 gen_rtx_ASHIFTRT (SImode,
1152 gen_rtx_SUBREG (SImode, operands[0], low),
1153 GEN_INT (31))));
1154 DONE;
1155 }"
1156 )
1158 (define_insn "extendhisi2"
1159 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1160 (sign_extend:SI (match_operand:HI 1 "mcore_arith_reg_operand" "0")))]
1161 ""
1162 "sexth %0")
1164 (define_insn "extendqisi2"
1165 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1166 (sign_extend:SI (match_operand:QI 1 "mcore_arith_reg_operand" "0")))]
1167 ""
1168 "sextb %0")
1170 (define_insn "extendqihi2"
1171 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
1172 (sign_extend:HI (match_operand:QI 1 "mcore_arith_reg_operand" "0")))]
1173 ""
1174 "sextb %0")
1176 ;; -------------------------------------------------------------------------
1177 ;; Move instructions
1178 ;; -------------------------------------------------------------------------
1180 ;; SImode
1182 (define_expand "movsi"
1183 [(set (match_operand:SI 0 "general_operand" "")
1184 (match_operand:SI 1 "general_operand" ""))]
1185 ""
1186 "
1187 {
1188 if (GET_CODE (operands[0]) == MEM)
1189 operands[1] = force_reg (SImode, operands[1]);
1190 }")
1192 (define_insn ""
1193 [(set (match_operand:SI 0 "mcore_general_movdst_operand" "=r,r,a,r,a,r,m")
1194 (match_operand:SI 1 "mcore_general_movsrc_operand" "r,P,i,c,R,m,r"))]
1195 "(register_operand (operands[0], SImode)
1196 || register_operand (operands[1], SImode))"
1197 "* return mcore_output_move (insn, operands, SImode);"
1198 [(set_attr "type" "move,move,move,move,load,load,store")])
1200 ;;
1201 ;; HImode
1202 ;;
1204 (define_expand "movhi"
1205 [(set (match_operand:HI 0 "general_operand" "")
1206 (match_operand:HI 1 "general_operand" ""))]
1207 ""
1208 "
1209 {
1210 if (GET_CODE (operands[0]) == MEM)
1211 operands[1] = force_reg (HImode, operands[1]);
1212 else if (CONSTANT_P (operands[1])
1213 && (GET_CODE (operands[1]) != CONST_INT
1214 || (! CONST_OK_FOR_I (INTVAL (operands[1]))
1215 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1216 && ! CONST_OK_FOR_N (INTVAL (operands[1]))))
1217 && ! reload_completed && ! reload_in_progress)
1218 {
1219 rtx reg = gen_reg_rtx (SImode);
1220 emit_insn (gen_movsi (reg, operands[1]));
1221 operands[1] = gen_lowpart (HImode, reg);
1222 }
1223 }")
1225 (define_insn ""
1226 [(set (match_operand:HI 0 "mcore_general_movdst_operand" "=r,r,a,r,r,m")
1227 (match_operand:HI 1 "mcore_general_movsrc_operand" "r,P,i,c,m,r"))]
1228 "(register_operand (operands[0], HImode)
1229 || register_operand (operands[1], HImode))"
1230 "* return mcore_output_move (insn, operands, HImode);"
1231 [(set_attr "type" "move,move,move,move,load,store")])
1233 ;;
1234 ;; QImode
1235 ;;
1237 (define_expand "movqi"
1238 [(set (match_operand:QI 0 "general_operand" "")
1239 (match_operand:QI 1 "general_operand" ""))]
1240 ""
1241 "
1242 {
1243 if (GET_CODE (operands[0]) == MEM)
1244 operands[1] = force_reg (QImode, operands[1]);
1245 else if (CONSTANT_P (operands[1])
1246 && (GET_CODE (operands[1]) != CONST_INT
1247 || (! CONST_OK_FOR_I (INTVAL (operands[1]))
1248 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1249 && ! CONST_OK_FOR_N (INTVAL (operands[1]))))
1250 && ! reload_completed && ! reload_in_progress)
1251 {
1252 rtx reg = gen_reg_rtx (SImode);
1253 emit_insn (gen_movsi (reg, operands[1]));
1254 operands[1] = gen_lowpart (QImode, reg);
1255 }
1256 }")
1258 (define_insn ""
1259 [(set (match_operand:QI 0 "mcore_general_movdst_operand" "=r,r,a,r,r,m")
1260 (match_operand:QI 1 "mcore_general_movsrc_operand" "r,P,i,c,m,r"))]
1261 "(register_operand (operands[0], QImode)
1262 || register_operand (operands[1], QImode))"
1263 "* return mcore_output_move (insn, operands, QImode);"
1264 [(set_attr "type" "move,move,move,move,load,store")])
1267 ;; DImode
1269 (define_expand "movdi"
1270 [(set (match_operand:DI 0 "general_operand" "")
1271 (match_operand:DI 1 "general_operand" ""))]
1272 ""
1273 "
1274 {
1275 if (GET_CODE (operands[0]) == MEM)
1276 operands[1] = force_reg (DImode, operands[1]);
1277 else if (GET_CODE (operands[1]) == CONST_INT
1278 && ! CONST_OK_FOR_I (INTVAL (operands[1]))
1279 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1280 && ! CONST_OK_FOR_N (INTVAL (operands[1])))
1281 {
1282 int i;
1283 for (i = 0; i < UNITS_PER_WORD * 2; i += UNITS_PER_WORD)
1284 emit_move_insn (simplify_gen_subreg (SImode, operands[0], DImode, i),
1285 simplify_gen_subreg (SImode, operands[1], DImode, i));
1286 DONE;
1287 }
1288 }")
1290 (define_insn "movdi_i"
1291 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,a,r,m")
1292 (match_operand:DI 1 "mcore_general_movsrc_operand" "I,M,N,r,R,m,r"))]
1293 ""
1294 "* return mcore_output_movedouble (operands, DImode);"
1295 [(set_attr "length" "4") (set_attr "type" "move,move,move,move,load,load,store")])
1297 ;; SFmode
1299 (define_expand "movsf"
1300 [(set (match_operand:SF 0 "general_operand" "")
1301 (match_operand:SF 1 "general_operand" ""))]
1302 ""
1303 "
1304 {
1305 if (GET_CODE (operands[0]) == MEM)
1306 operands[1] = force_reg (SFmode, operands[1]);
1307 }")
1309 (define_insn "movsf_i"
1310 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
1311 (match_operand:SF 1 "general_operand" "r,m,r"))]
1312 ""
1313 "@
1314 mov %0,%1
1315 ld.w %0,%1
1316 st.w %1,%0"
1317 [(set_attr "type" "move,load,store")])
1319 ;; DFmode
1321 (define_expand "movdf"
1322 [(set (match_operand:DF 0 "general_operand" "")
1323 (match_operand:DF 1 "general_operand" ""))]
1324 ""
1325 "
1326 {
1327 if (GET_CODE (operands[0]) == MEM)
1328 operands[1] = force_reg (DFmode, operands[1]);
1329 }")
1331 (define_insn "movdf_k"
1332 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
1333 (match_operand:DF 1 "general_operand" "r,m,r"))]
1334 ""
1335 "* return mcore_output_movedouble (operands, DFmode);"
1336 [(set_attr "length" "4") (set_attr "type" "move,load,store")])
1339 ;; Load/store multiple
1341 ;; ??? This is not currently used.
1342 (define_insn "ldm"
1343 [(set (match_operand:TI 0 "mcore_arith_reg_operand" "=r")
1344 (mem:TI (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
1345 ""
1346 "ldq %U0,(%1)")
1348 ;; ??? This is not currently used.
1349 (define_insn "stm"
1350 [(set (mem:TI (match_operand:SI 0 "mcore_arith_reg_operand" "r"))
1351 (match_operand:TI 1 "mcore_arith_reg_operand" "r"))]
1352 ""
1353 "stq %U1,(%0)")
1355 (define_expand "load_multiple"
1356 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
1357 (match_operand:SI 1 "" ""))
1358 (use (match_operand:SI 2 "" ""))])]
1359 ""
1360 "
1361 {
1362 int regno, count, i;
1364 /* Support only loading a constant number of registers from memory and
1365 only if at least two registers. The last register must be r15. */
1366 if (GET_CODE (operands[2]) != CONST_INT
1367 || INTVAL (operands[2]) < 2
1368 || GET_CODE (operands[1]) != MEM
1369 || XEXP (operands[1], 0) != stack_pointer_rtx
1370 || GET_CODE (operands[0]) != REG
1371 || REGNO (operands[0]) + INTVAL (operands[2]) != 16)
1372 FAIL;
1374 count = INTVAL (operands[2]);
1375 regno = REGNO (operands[0]);
1377 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1379 for (i = 0; i < count; i++)
1380 XVECEXP (operands[3], 0, i)
1381 = gen_rtx_SET (VOIDmode,
1382 gen_rtx_REG (SImode, regno + i),
1383 gen_rtx_MEM (SImode, plus_constant (Pmode, stack_pointer_rtx,
1384 i * 4)));
1385 }")
1387 (define_insn ""
1388 [(match_parallel 0 "mcore_load_multiple_operation"
1389 [(set (match_operand:SI 1 "mcore_arith_reg_operand" "=r")
1390 (mem:SI (match_operand:SI 2 "register_operand" "r")))])]
1391 "GET_CODE (operands[2]) == REG && REGNO (operands[2]) == STACK_POINTER_REGNUM"
1392 "ldm %1-r15,(%2)")
1394 (define_expand "store_multiple"
1395 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
1396 (match_operand:SI 1 "" ""))
1397 (use (match_operand:SI 2 "" ""))])]
1398 ""
1399 "
1400 {
1401 int regno, count, i;
1403 /* Support only storing a constant number of registers to memory and
1404 only if at least two registers. The last register must be r15. */
1405 if (GET_CODE (operands[2]) != CONST_INT
1406 || INTVAL (operands[2]) < 2
1407 || GET_CODE (operands[0]) != MEM
1408 || XEXP (operands[0], 0) != stack_pointer_rtx
1409 || GET_CODE (operands[1]) != REG
1410 || REGNO (operands[1]) + INTVAL (operands[2]) != 16)
1411 FAIL;
1413 count = INTVAL (operands[2]);
1414 regno = REGNO (operands[1]);
1416 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1418 for (i = 0; i < count; i++)
1419 XVECEXP (operands[3], 0, i)
1420 = gen_rtx_SET (VOIDmode,
1421 gen_rtx_MEM (SImode, plus_constant (Pmode, stack_pointer_rtx,
1422 i * 4)),
1423 gen_rtx_REG (SImode, regno + i));
1424 }")
1426 (define_insn ""
1427 [(match_parallel 0 "mcore_store_multiple_operation"
1428 [(set (mem:SI (match_operand:SI 2 "register_operand" "r"))
1429 (match_operand:SI 1 "mcore_arith_reg_operand" "r"))])]
1430 "GET_CODE (operands[2]) == REG && REGNO (operands[2]) == STACK_POINTER_REGNUM"
1431 "stm %1-r15,(%2)")
1433 ;; ------------------------------------------------------------------------
1434 ;; Define the real conditional branch instructions.
1435 ;; ------------------------------------------------------------------------
1437 ;; At top-level, condition test are eq/ne, because we
1438 ;; are comparing against the condition register (which
1439 ;; has the result of the true relational test
1441 (define_insn "branch_true"
1442 [(set (pc) (if_then_else (ne (reg:CC 17) (const_int 0))
1443 (label_ref (match_operand 0 "" ""))
1444 (pc)))]
1445 ""
1446 "jbt %l0"
1447 [(set_attr "type" "brcond")])
1449 (define_insn "branch_false"
1450 [(set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
1451 (label_ref (match_operand 0 "" ""))
1452 (pc)))]
1453 ""
1454 "jbf %l0"
1455 [(set_attr "type" "brcond")])
1457 (define_insn "inverse_branch_true"
1458 [(set (pc) (if_then_else (ne (reg:CC 17) (const_int 0))
1459 (pc)
1460 (label_ref (match_operand 0 "" ""))))]
1461 ""
1462 "jbf %l0"
1463 [(set_attr "type" "brcond")])
1465 (define_insn "inverse_branch_false"
1466 [(set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
1467 (pc)
1468 (label_ref (match_operand 0 "" ""))))]
1469 ""
1470 "jbt %l0"
1471 [(set_attr "type" "brcond")])
1473 ;; Conditional branch insns
1475 (define_expand "cbranchsi4"
1476 [(set (pc)
1477 (if_then_else (match_operator 0 "ordered_comparison_operator"
1478 [(match_operand:SI 1 "mcore_compare_operand")
1479 (match_operand:SI 2 "nonmemory_operand")])
1480 (label_ref (match_operand 3 ""))
1481 (pc)))]
1482 ""
1483 "
1484 {
1485 bool invert;
1486 invert = mcore_gen_compare (GET_CODE (operands[0]),
1487 operands[1], operands[2]);
1489 if (invert)
1490 emit_jump_insn (gen_branch_false (operands[3]));
1491 else
1492 emit_jump_insn (gen_branch_true (operands[3]));
1493 DONE;
1494 }")
1498 ;; ------------------------------------------------------------------------
1499 ;; Jump and linkage insns
1500 ;; ------------------------------------------------------------------------
1502 (define_insn "jump_real"
1503 [(set (pc)
1504 (label_ref (match_operand 0 "" "")))]
1505 ""
1506 "jbr %l0"
1507 [(set_attr "type" "branch")])
1509 (define_expand "jump"
1510 [(set (pc) (label_ref (match_operand 0 "" "")))]
1511 ""
1512 "
1513 {
1514 emit_jump_insn (gen_jump_real (operand0));
1515 DONE;
1516 }
1517 ")
1519 (define_insn "indirect_jump"
1520 [(set (pc)
1521 (match_operand:SI 0 "mcore_arith_reg_operand" "r"))]
1522 ""
1523 "jmp %0"
1524 [(set_attr "type" "jmp")])
1526 (define_expand "call"
1527 [(parallel[(call (match_operand:SI 0 "" "")
1528 (match_operand 1 "" ""))
1529 (clobber (reg:SI 15))])]
1530 ""
1531 "
1532 {
1533 if (GET_CODE (operands[0]) == MEM
1534 && ! register_operand (XEXP (operands[0], 0), SImode)
1535 && ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
1536 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1537 force_reg (Pmode, XEXP (operands[0], 0)));
1538 }")
1540 (define_insn "call_internal"
1541 [(call (mem:SI (match_operand:SI 0 "mcore_call_address_operand" "riR"))
1542 (match_operand 1 "" ""))
1543 (clobber (reg:SI 15))]
1544 ""
1545 "* return mcore_output_call (operands, 0);")
1547 (define_expand "call_value"
1548 [(parallel[(set (match_operand 0 "register_operand" "")
1549 (call (match_operand:SI 1 "" "")
1550 (match_operand 2 "" "")))
1551 (clobber (reg:SI 15))])]
1552 ""
1553 "
1554 {
1555 if (GET_CODE (operands[0]) == MEM
1556 && ! register_operand (XEXP (operands[0], 0), SImode)
1557 && ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
1558 operands[1] = gen_rtx_MEM (GET_MODE (operands[1]),
1559 force_reg (Pmode, XEXP (operands[1], 0)));
1560 }")
1562 (define_insn "call_value_internal"
1563 [(set (match_operand 0 "register_operand" "=r")
1564 (call (mem:SI (match_operand:SI 1 "mcore_call_address_operand" "riR"))
1565 (match_operand 2 "" "")))
1566 (clobber (reg:SI 15))]
1567 ""
1568 "* return mcore_output_call (operands, 1);")
1570 (define_insn "call_value_struct"
1571 [(parallel [(set (match_parallel 0 ""
1572 [(expr_list (match_operand 3 "register_operand" "") (match_operand 4 "immediate_operand" ""))
1573 (expr_list (match_operand 5 "register_operand" "") (match_operand 6 "immediate_operand" ""))])
1574 (call (match_operand:SI 1 "" "")
1575 (match_operand 2 "" "")))
1576 (clobber (reg:SI 15))])]
1577 ""
1578 "* return mcore_output_call (operands, 1);"
1579 )
1582 ;; ------------------------------------------------------------------------
1583 ;; Misc insns
1584 ;; ------------------------------------------------------------------------
1586 (define_insn "nop"
1587 [(const_int 0)]
1588 ""
1589 "or r0,r0")
1591 (define_insn "tablejump"
1592 [(set (pc)
1593 (match_operand:SI 0 "mcore_arith_reg_operand" "r"))
1594 (use (label_ref (match_operand 1 "" "")))]
1595 ""
1596 "jmp %0"
1597 [(set_attr "type" "jmp")])
1599 (define_insn "*return"
1600 [(return)]
1601 "reload_completed && ! mcore_naked_function_p ()"
1602 "jmp r15"
1603 [(set_attr "type" "jmp")])
1605 (define_insn "*no_return"
1606 [(return)]
1607 "reload_completed && mcore_naked_function_p ()"
1608 ""
1609 [(set_attr "length" "0")]
1610 )
1612 (define_expand "prologue"
1613 [(const_int 0)]
1614 ""
1615 "mcore_expand_prolog (); DONE;")
1617 (define_expand "epilogue"
1618 [(return)]
1619 ""
1620 "mcore_expand_epilog ();")
1622 ;; ------------------------------------------------------------------------
1623 ;; Scc instructions
1624 ;; ------------------------------------------------------------------------
1626 (define_insn "mvc"
1627 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1628 (ne:SI (reg:CC 17) (const_int 0)))]
1629 ""
1630 "mvc %0"
1631 [(set_attr "type" "move")])
1633 (define_insn "mvcv"
1634 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1635 (eq:SI (reg:CC 17) (const_int 0)))]
1636 ""
1637 "mvcv %0"
1638 [(set_attr "type" "move")])
1640 ; in 0.97 use (LE 0) with (LT 1) and complement c. BRC
1641 (define_split
1642 [(parallel[
1643 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1644 (ne:SI (gt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
1645 (const_int 0))
1646 (const_int 0)))
1647 (clobber (reg:SI 17))])]
1648 ""
1649 [(set (reg:CC 17)
1650 (lt:CC (match_dup 1) (const_int 1)))
1651 (set (match_dup 0) (eq:SI (reg:CC 17) (const_int 0)))])
1654 (define_expand "cstoresi4"
1655 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1656 (match_operator:SI 1 "ordered_comparison_operator"
1657 [(match_operand:SI 2 "mcore_compare_operand" "")
1658 (match_operand:SI 3 "nonmemory_operand" "")]))]
1659 ""
1660 "
1661 {
1662 bool invert;
1663 invert = mcore_gen_compare (GET_CODE (operands[1]),
1664 operands[2], operands[3]);
1666 if (invert)
1667 emit_insn (gen_mvcv (operands[0]));
1668 else
1669 emit_insn (gen_mvc (operands[0]));
1670 DONE;
1671 }")
1673 (define_insn "incscc"
1674 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1675 (plus:SI (ne (reg:CC 17) (const_int 0))
1676 (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1677 ""
1678 "inct %0")
1680 (define_insn "incscc_false"
1681 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1682 (plus:SI (eq (reg:CC 17) (const_int 0))
1683 (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1684 ""
1685 "incf %0")
1687 (define_insn "decscc"
1688 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1689 (minus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
1690 (ne (reg:CC 17) (const_int 0))))]
1691 ""
1692 "dect %0")
1694 (define_insn "decscc_false"
1695 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1696 (minus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
1697 (eq (reg:CC 17) (const_int 0))))]
1698 ""
1699 "decf %0")
1701 ;; ------------------------------------------------------------------------
1702 ;; Conditional move patterns.
1703 ;; ------------------------------------------------------------------------
1705 (define_expand "smaxsi3"
1706 [(set (reg:CC 17)
1707 (lt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
1708 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
1709 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1710 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
1711 (match_dup 1) (match_dup 2)))]
1712 ""
1713 "")
1715 (define_split
1716 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1717 (smax:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
1718 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
1719 ""
1720 [(set (reg:CC 17)
1721 (lt:SI (match_dup 1) (match_dup 2)))
1722 (set (match_dup 0)
1723 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
1724 (match_dup 1) (match_dup 2)))]
1725 "")
1727 ; no tstgt in 0.97, so just use cmplti (btsti x,31) and reverse move
1728 ; condition BRC
1729 (define_split
1730 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1731 (smax:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
1732 (const_int 0)))]
1733 ""
1734 [(set (reg:CC 17)
1735 (lt:CC (match_dup 1) (const_int 0)))
1736 (set (match_dup 0)
1737 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
1738 (match_dup 1) (const_int 0)))]
1739 "")
1741 (define_expand "sminsi3"
1742 [(set (reg:CC 17)
1743 (lt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
1744 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
1745 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1746 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
1747 (match_dup 1) (match_dup 2)))]
1748 ""
1749 "")
1751 (define_split
1752 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1753 (smin:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
1754 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
1755 ""
1756 [(set (reg:CC 17)
1757 (lt:SI (match_dup 1) (match_dup 2)))
1758 (set (match_dup 0)
1759 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
1760 (match_dup 1) (match_dup 2)))]
1761 "")
1763 ;(define_split
1764 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1765 ; (smin:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
1766 ; (const_int 0)))]
1767 ; ""
1768 ; [(set (reg:CC 17)
1769 ; (gt:CC (match_dup 1) (const_int 0)))
1770 ; (set (match_dup 0)
1771 ; (if_then_else:SI (eq (reg:CC 17) (const_int 0))
1772 ; (match_dup 1) (const_int 0)))]
1773 ; "")
1775 ; changed these unsigned patterns to use geu instead of ltu. it appears
1776 ; that the c-torture & ssrl test suites didn't catch these! only showed
1777 ; up in friedman's clib work. BRC 7/7/95
1779 (define_expand "umaxsi3"
1780 [(set (reg:CC 17)
1781 (geu:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
1782 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
1783 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1784 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
1785 (match_dup 2) (match_dup 1)))]
1786 ""
1787 "")
1789 (define_split
1790 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1791 (umax:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
1792 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
1793 ""
1794 [(set (reg:CC 17)
1795 (geu:SI (match_dup 1) (match_dup 2)))
1796 (set (match_dup 0)
1797 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
1798 (match_dup 2) (match_dup 1)))]
1799 "")
1801 (define_expand "uminsi3"
1802 [(set (reg:CC 17)
1803 (geu:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
1804 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
1805 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1806 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
1807 (match_dup 2) (match_dup 1)))]
1808 ""
1809 "")
1811 (define_split
1812 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1813 (umin:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
1814 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
1815 ""
1816 [(set (reg:CC 17)
1817 (geu:SI (match_dup 1) (match_dup 2)))
1818 (set (match_dup 0)
1819 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
1820 (match_dup 2) (match_dup 1)))]
1821 "")
1823 ;; ------------------------------------------------------------------------
1824 ;; conditional move patterns really start here
1825 ;; ------------------------------------------------------------------------
1827 ;; the "movtK" patterns are experimental. they are intended to account for
1828 ;; gcc's mucking on code such as:
1829 ;;
1830 ;; free_ent = ((block_compress) ? 257 : 256 );
1831 ;;
1832 ;; these patterns help to get a tstne/bgeni/inct (or equivalent) sequence
1833 ;; when both arms have constants that are +/- 1 of each other.
1834 ;;
1835 ;; note in the following patterns that the "movtK" ones should be the first
1836 ;; one defined in each sequence. this is because the general pattern also
1837 ;; matches, so use ordering to determine priority (it's easier this way than
1838 ;; adding conditions to the general patterns). BRC
1839 ;;
1840 ;; the U and Q constraints are necessary to ensure that reload does the
1841 ;; 'right thing'. U constrains the operand to 0 and Q to 1 for use in the
1842 ;; clrt & clrf and clrt/inct & clrf/incf patterns. BRC 6/26
1843 ;;
1844 ;; ??? there appears to be some problems with these movtK patterns for ops
1845 ;; other than eq & ne. need to fix. 6/30 BRC
1847 ;; ------------------------------------------------------------------------
1848 ;; ne
1849 ;; ------------------------------------------------------------------------
1851 ; experimental conditional move with two constants +/- 1 BRC
1853 (define_insn "movtK_1"
1854 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1855 (if_then_else:SI
1856 (ne (reg:CC 17) (const_int 0))
1857 (match_operand:SI 1 "mcore_arith_O_operand" "O")
1858 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
1859 " GET_CODE (operands[1]) == CONST_INT
1860 && GET_CODE (operands[2]) == CONST_INT
1861 && ( (INTVAL (operands[1]) - INTVAL (operands[2]) == 1)
1862 || (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
1863 "* return mcore_output_cmov (operands, 1, NULL);"
1864 [(set_attr "length" "4")])
1866 (define_insn "movt0"
1867 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
1868 (if_then_else:SI
1869 (ne (reg:CC 17) (const_int 0))
1870 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
1871 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
1872 ""
1873 "@
1874 movt %0,%1
1875 movf %0,%2
1876 clrt %0
1877 clrf %0")
1879 ;; ------------------------------------------------------------------------
1880 ;; eq
1881 ;; ------------------------------------------------------------------------
1883 ; experimental conditional move with two constants +/- 1 BRC
1884 (define_insn "movtK_2"
1885 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1886 (if_then_else:SI
1887 (eq (reg:CC 17) (const_int 0))
1888 (match_operand:SI 1 "mcore_arith_O_operand" "O")
1889 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
1890 " GET_CODE (operands[1]) == CONST_INT
1891 && GET_CODE (operands[2]) == CONST_INT
1892 && ( (INTVAL (operands[1]) - INTVAL (operands[2]) == 1)
1893 || (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
1894 "* return mcore_output_cmov (operands, 0, NULL);"
1895 [(set_attr "length" "4")])
1897 (define_insn "movf0"
1898 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
1899 (if_then_else:SI
1900 (eq (reg:CC 17) (const_int 0))
1901 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
1902 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
1903 ""
1904 "@
1905 movf %0,%1
1906 movt %0,%2
1907 clrf %0
1908 clrt %0")
1910 ; turns lsli rx,imm/btsti rx,31 into btsti rx,imm. not done by a peephole
1911 ; because the instructions are not adjacent (peepholes are related by posn -
1912 ; not by dataflow). BRC
1914 (define_insn ""
1915 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
1916 (if_then_else:SI (eq (zero_extract:SI
1917 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
1918 (const_int 1)
1919 (match_operand:SI 2 "mcore_literal_K_operand" "K,K,K,K"))
1920 (const_int 0))
1921 (match_operand:SI 3 "mcore_arith_imm_operand" "r,0,U,0")
1922 (match_operand:SI 4 "mcore_arith_imm_operand" "0,r,0,U")))]
1923 ""
1924 "@
1925 btsti %1,%2\;movf %0,%3
1926 btsti %1,%2\;movt %0,%4
1927 btsti %1,%2\;clrf %0
1928 btsti %1,%2\;clrt %0"
1929 [(set_attr "length" "4")])
1931 ; turns sextb rx/btsti rx,31 into btsti rx,7. must be QImode to be safe. BRC
1933 (define_insn ""
1934 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
1935 (if_then_else:SI (eq (lshiftrt:SI
1936 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
1937 (const_int 7))
1938 (const_int 0))
1939 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
1940 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
1941 "GET_CODE (operands[1]) == SUBREG &&
1942 GET_MODE (SUBREG_REG (operands[1])) == QImode"
1943 "@
1944 btsti %1,7\;movf %0,%2
1945 btsti %1,7\;movt %0,%3
1946 btsti %1,7\;clrf %0
1947 btsti %1,7\;clrt %0"
1948 [(set_attr "length" "4")])
1951 ;; ------------------------------------------------------------------------
1952 ;; ne
1953 ;; ------------------------------------------------------------------------
1955 ;; Combine creates this from an andn instruction in a scc sequence.
1956 ;; We must recognize it to get conditional moves generated.
1958 ; experimental conditional move with two constants +/- 1 BRC
1959 (define_insn "movtK_3"
1960 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1961 (if_then_else:SI
1962 (ne (match_operand:SI 1 "mcore_arith_reg_operand" "r")
1963 (const_int 0))
1964 (match_operand:SI 2 "mcore_arith_O_operand" "O")
1965 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
1966 " GET_CODE (operands[2]) == CONST_INT
1967 && GET_CODE (operands[3]) == CONST_INT
1968 && ( (INTVAL (operands[2]) - INTVAL (operands[3]) == 1)
1969 || (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
1970 "*
1971 {
1972 rtx out_operands[4];
1973 out_operands[0] = operands[0];
1974 out_operands[1] = operands[2];
1975 out_operands[2] = operands[3];
1976 out_operands[3] = operands[1];
1978 return mcore_output_cmov (out_operands, 1, \"cmpnei %3,0\");
1980 }"
1981 [(set_attr "length" "6")])
1983 (define_insn "movt2"
1984 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
1985 (if_then_else:SI (ne (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
1986 (const_int 0))
1987 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
1988 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
1989 ""
1990 "@
1991 cmpnei %1,0\;movt %0,%2
1992 cmpnei %1,0\;movf %0,%3
1993 cmpnei %1,0\;clrt %0
1994 cmpnei %1,0\;clrf %0"
1995 [(set_attr "length" "4")])
1997 ; turns lsli rx,imm/btsti rx,31 into btsti rx,imm. not done by a peephole
1998 ; because the instructions are not adjacent (peepholes are related by posn -
1999 ; not by dataflow). BRC
2001 (define_insn ""
2002 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2003 (if_then_else:SI (ne (zero_extract:SI
2004 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2005 (const_int 1)
2006 (match_operand:SI 2 "mcore_literal_K_operand" "K,K,K,K"))
2007 (const_int 0))
2008 (match_operand:SI 3 "mcore_arith_imm_operand" "r,0,U,0")
2009 (match_operand:SI 4 "mcore_arith_imm_operand" "0,r,0,U")))]
2010 ""
2011 "@
2012 btsti %1,%2\;movt %0,%3
2013 btsti %1,%2\;movf %0,%4
2014 btsti %1,%2\;clrt %0
2015 btsti %1,%2\;clrf %0"
2016 [(set_attr "length" "4")])
2018 ; turns sextb rx/btsti rx,31 into btsti rx,7. must be QImode to be safe. BRC
2020 (define_insn ""
2021 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2022 (if_then_else:SI (ne (lshiftrt:SI
2023 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2024 (const_int 7))
2025 (const_int 0))
2026 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2027 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2028 "GET_CODE (operands[1]) == SUBREG &&
2029 GET_MODE (SUBREG_REG (operands[1])) == QImode"
2030 "@
2031 btsti %1,7\;movt %0,%2
2032 btsti %1,7\;movf %0,%3
2033 btsti %1,7\;clrt %0
2034 btsti %1,7\;clrf %0"
2035 [(set_attr "length" "4")])
2037 ;; ------------------------------------------------------------------------
2038 ;; eq/eq
2039 ;; ------------------------------------------------------------------------
2041 ; experimental conditional move with two constants +/- 1 BRC
2042 (define_insn "movtK_4"
2043 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2044 (if_then_else:SI
2045 (eq (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2046 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2047 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2048 "GET_CODE (operands[1]) == CONST_INT &&
2049 GET_CODE (operands[2]) == CONST_INT &&
2050 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2051 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2052 "* return mcore_output_cmov(operands, 1, NULL);"
2053 [(set_attr "length" "4")])
2055 (define_insn "movt3"
2056 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2057 (if_then_else:SI
2058 (eq (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2059 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2060 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2061 ""
2062 "@
2063 movt %0,%1
2064 movf %0,%2
2065 clrt %0
2066 clrf %0")
2068 ;; ------------------------------------------------------------------------
2069 ;; eq/ne
2070 ;; ------------------------------------------------------------------------
2072 ; experimental conditional move with two constants +/- 1 BRC
2073 (define_insn "movtK_5"
2074 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2075 (if_then_else:SI
2076 (eq (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2077 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2078 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2079 "GET_CODE (operands[1]) == CONST_INT &&
2080 GET_CODE (operands[2]) == CONST_INT &&
2081 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2082 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2083 "* return mcore_output_cmov (operands, 0, NULL);"
2084 [(set_attr "length" "4")])
2086 (define_insn "movf1"
2087 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2088 (if_then_else:SI
2089 (eq (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2090 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2091 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2092 ""
2093 "@
2094 movf %0,%1
2095 movt %0,%2
2096 clrf %0
2097 clrt %0")
2099 ;; ------------------------------------------------------------------------
2100 ;; eq
2101 ;; ------------------------------------------------------------------------
2103 ;; Combine creates this from an andn instruction in a scc sequence.
2104 ;; We must recognize it to get conditional moves generated.
2106 ; experimental conditional move with two constants +/- 1 BRC
2108 (define_insn "movtK_6"
2109 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2110 (if_then_else:SI
2111 (eq (match_operand:SI 1 "mcore_arith_reg_operand" "r")
2112 (const_int 0))
2113 (match_operand:SI 2 "mcore_arith_O_operand" "O")
2114 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
2115 "GET_CODE (operands[1]) == CONST_INT &&
2116 GET_CODE (operands[2]) == CONST_INT &&
2117 ((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
2118 (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
2119 "*
2120 {
2121 rtx out_operands[4];
2122 out_operands[0] = operands[0];
2123 out_operands[1] = operands[2];
2124 out_operands[2] = operands[3];
2125 out_operands[3] = operands[1];
2127 return mcore_output_cmov (out_operands, 0, \"cmpnei %3,0\");
2128 }"
2129 [(set_attr "length" "6")])
2131 (define_insn "movf3"
2132 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2133 (if_then_else:SI (eq (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2134 (const_int 0))
2135 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2136 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2137 ""
2138 "@
2139 cmpnei %1,0\;movf %0,%2
2140 cmpnei %1,0\;movt %0,%3
2141 cmpnei %1,0\;clrf %0
2142 cmpnei %1,0\;clrt %0"
2143 [(set_attr "length" "4")])
2145 ;; ------------------------------------------------------------------------
2146 ;; ne/eq
2147 ;; ------------------------------------------------------------------------
2149 ; experimental conditional move with two constants +/- 1 BRC
2150 (define_insn "movtK_7"
2151 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2152 (if_then_else:SI
2153 (ne (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2154 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2155 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2156 "GET_CODE (operands[1]) == CONST_INT &&
2157 GET_CODE (operands[2]) == CONST_INT &&
2158 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2159 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2160 "* return mcore_output_cmov (operands, 0, NULL);"
2161 [(set_attr "length" "4")])
2163 (define_insn "movf4"
2164 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2165 (if_then_else:SI
2166 (ne (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2167 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2168 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2169 ""
2170 "@
2171 movf %0,%1
2172 movt %0,%2
2173 clrf %0
2174 clrt %0")
2176 ;; ------------------------------------------------------------------------
2177 ;; ne/ne
2178 ;; ------------------------------------------------------------------------
2180 ; experimental conditional move with two constants +/- 1 BRC
2181 (define_insn "movtK_8"
2182 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2183 (if_then_else:SI
2184 (ne (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2185 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2186 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2187 "GET_CODE (operands[1]) == CONST_INT &&
2188 GET_CODE (operands[2]) == CONST_INT &&
2189 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2190 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2191 "* return mcore_output_cmov (operands, 1, NULL);"
2192 [(set_attr "length" "4")])
2194 (define_insn "movt4"
2195 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2196 (if_then_else:SI
2197 (ne (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2198 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2199 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2200 ""
2201 "@
2202 movt %0,%1
2203 movf %0,%2
2204 clrt %0
2205 clrf %0")
2207 ;; Also need patterns to recognize lt/ge, since otherwise the compiler will
2208 ;; try to output not/asri/tstne/movf.
2210 ;; ------------------------------------------------------------------------
2211 ;; lt
2212 ;; ------------------------------------------------------------------------
2214 ; experimental conditional move with two constants +/- 1 BRC
2215 (define_insn "movtK_9"
2216 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2217 (if_then_else:SI
2218 (lt (match_operand:SI 1 "mcore_arith_reg_operand" "r")
2219 (const_int 0))
2220 (match_operand:SI 2 "mcore_arith_O_operand" "O")
2221 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
2222 "GET_CODE (operands[2]) == CONST_INT &&
2223 GET_CODE (operands[3]) == CONST_INT &&
2224 ((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
2225 (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
2226 "*
2227 {
2228 rtx out_operands[4];
2229 out_operands[0] = operands[0];
2230 out_operands[1] = operands[2];
2231 out_operands[2] = operands[3];
2232 out_operands[3] = operands[1];
2234 return mcore_output_cmov (out_operands, 1, \"btsti %3,31\");
2235 }"
2236 [(set_attr "length" "6")])
2238 (define_insn "movt5"
2239 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2240 (if_then_else:SI (lt (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2241 (const_int 0))
2242 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2243 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2244 ""
2245 "@
2246 btsti %1,31\;movt %0,%2
2247 btsti %1,31\;movf %0,%3
2248 btsti %1,31\;clrt %0
2249 btsti %1,31\;clrf %0"
2250 [(set_attr "length" "4")])
2253 ;; ------------------------------------------------------------------------
2254 ;; ge
2255 ;; ------------------------------------------------------------------------
2257 ; experimental conditional move with two constants +/- 1 BRC
2258 (define_insn "movtK_10"
2259 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2260 (if_then_else:SI
2261 (ge (match_operand:SI 1 "mcore_arith_reg_operand" "r")
2262 (const_int 0))
2263 (match_operand:SI 2 "mcore_arith_O_operand" "O")
2264 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
2265 "GET_CODE (operands[2]) == CONST_INT &&
2266 GET_CODE (operands[3]) == CONST_INT &&
2267 ((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
2268 (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
2269 "*
2270 {
2271 rtx out_operands[4];
2272 out_operands[0] = operands[0];
2273 out_operands[1] = operands[2];
2274 out_operands[2] = operands[3];
2275 out_operands[3] = operands[1];
2277 return mcore_output_cmov (out_operands, 0, \"btsti %3,31\");
2278 }"
2279 [(set_attr "length" "6")])
2281 (define_insn "movf5"
2282 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2283 (if_then_else:SI (ge (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2284 (const_int 0))
2285 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2286 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2287 ""
2288 "@
2289 btsti %1,31\;movf %0,%2
2290 btsti %1,31\;movt %0,%3
2291 btsti %1,31\;clrf %0
2292 btsti %1,31\;clrt %0"
2293 [(set_attr "length" "4")])
2295 ;; ------------------------------------------------------------------------
2296 ;; Bitfield extract (xtrbN)
2297 ;; ------------------------------------------------------------------------
2299 ; sometimes we're better off using QI/HI mode and letting the machine indep.
2300 ; part expand insv and extv.
2301 ;
2302 ; e.g., sequences like:a [an insertion]
2303 ;
2304 ; ldw r8,(r6)
2305 ; movi r7,0x00ffffff
2306 ; and r8,r7 r7 dead
2307 ; stw r8,(r6) r8 dead
2308 ;
2309 ; become:
2310 ;
2311 ; movi r8,0
2312 ; stb r8,(r6) r8 dead
2313 ;
2314 ; it looks like always using SI mode is a win except in this type of code
2315 ; (when adjacent bit fields collapse on a byte or halfword boundary). when
2316 ; expanding with SI mode, non-adjacent bit field masks fold, but with QI/HI
2317 ; mode, they do not. one thought is to add some peepholes to cover cases
2318 ; like the above, but this is not a general solution.
2319 ;
2320 ; -mword-bitfields expands/inserts using SI mode. otherwise, do it with
2321 ; the smallest mode possible (using the machine indep. expansions). BRC
2323 ;(define_expand "extv"
2324 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2325 ; (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2326 ; (match_operand:SI 2 "const_int_operand" "")
2327 ; (match_operand:SI 3 "const_int_operand" "")))
2328 ; (clobber (reg:CC 17))]
2329 ; ""
2330 ; "
2331 ;{
2332 ; if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) % 8 != 0)
2333 ; {
2334 ; if (TARGET_W_FIELD)
2335 ; {
2336 ; rtx lshft = GEN_INT (32 - (INTVAL (operands[2]) + INTVAL (operands[3])));
2337 ; rtx rshft = GEN_INT (32 - INTVAL (operands[2]));
2338 ;
2339 ; emit_insn (gen_rtx_SET (SImode, operands[0], operands[1]));
2340 ; emit_insn (gen_rtx_SET (SImode, operands[0],
2341 ; gen_rtx_ASHIFT (SImode, operands[0], lshft)));
2342 ; emit_insn (gen_rtx_SET (SImode, operands[0],
2343 ; gen_rtx_ASHIFTRT (SImode, operands[0], rshft)));
2344 ; DONE;
2345 ; }
2346 ; else
2347 ; FAIL;
2348 ; }
2349 ;}")
2351 (define_expand "extv"
2352 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2353 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2354 (match_operand:SI 2 "const_int_operand" "")
2355 (match_operand:SI 3 "const_int_operand" "")))
2356 (clobber (reg:CC 17))]
2357 ""
2358 "
2359 {
2360 if (INTVAL (operands[2]) == 8 && INTVAL (operands[3]) % 8 == 0)
2361 {
2362 /* 8-bit field, aligned properly, use the xtrb[0123]+sext sequence. */
2363 /* not DONE, not FAIL, but let the RTL get generated.... */
2364 }
2365 else if (TARGET_W_FIELD)
2366 {
2367 /* Arbitrary placement; note that the tree->rtl generator will make
2368 something close to this if we return FAIL */
2369 rtx lshft = GEN_INT (32 - (INTVAL (operands[2]) + INTVAL (operands[3])));
2370 rtx rshft = GEN_INT (32 - INTVAL (operands[2]));
2371 rtx tmp1 = gen_reg_rtx (SImode);
2372 rtx tmp2 = gen_reg_rtx (SImode);
2374 emit_insn (gen_rtx_SET (SImode, tmp1, operands[1]));
2375 emit_insn (gen_rtx_SET (SImode, tmp2,
2376 gen_rtx_ASHIFT (SImode, tmp1, lshft)));
2377 emit_insn (gen_rtx_SET (SImode, operands[0],
2378 gen_rtx_ASHIFTRT (SImode, tmp2, rshft)));
2379 DONE;
2380 }
2381 else
2382 {
2383 /* Let the caller choose an alternate sequence. */
2384 FAIL;
2385 }
2386 }")
2388 (define_expand "extzv"
2389 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2390 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2391 (match_operand:SI 2 "const_int_operand" "")
2392 (match_operand:SI 3 "const_int_operand" "")))
2393 (clobber (reg:CC 17))]
2394 ""
2395 "
2396 {
2397 if (INTVAL (operands[2]) == 8 && INTVAL (operands[3]) % 8 == 0)
2398 {
2399 /* 8-bit field, aligned properly, use the xtrb[0123] sequence. */
2400 /* Let the template generate some RTL.... */
2401 }
2402 else if (CONST_OK_FOR_K ((1 << INTVAL (operands[2])) - 1))
2403 {
2404 /* A narrow bit-field (<=5 bits) means we can do a shift to put
2405 it in place and then use an andi to extract it.
2406 This is as good as a shiftleft/shiftright. */
2408 rtx shifted;
2409 rtx mask = GEN_INT ((1 << INTVAL (operands[2])) - 1);
2411 if (INTVAL (operands[3]) == 0)
2412 {
2413 shifted = operands[1];
2414 }
2415 else
2416 {
2417 rtx rshft = GEN_INT (INTVAL (operands[3]));
2418 shifted = gen_reg_rtx (SImode);
2419 emit_insn (gen_rtx_SET (SImode, shifted,
2420 gen_rtx_LSHIFTRT (SImode, operands[1], rshft)));
2421 }
2422 emit_insn (gen_rtx_SET (SImode, operands[0],
2423 gen_rtx_AND (SImode, shifted, mask)));
2424 DONE;
2425 }
2426 else if (TARGET_W_FIELD)
2427 {
2428 /* Arbitrary pattern; play shift/shift games to get it.
2429 * this is pretty much what the caller will do if we say FAIL */
2430 rtx lshft = GEN_INT (32 - (INTVAL (operands[2]) + INTVAL (operands[3])));
2431 rtx rshft = GEN_INT (32 - INTVAL (operands[2]));
2432 rtx tmp1 = gen_reg_rtx (SImode);
2433 rtx tmp2 = gen_reg_rtx (SImode);
2435 emit_insn (gen_rtx_SET (SImode, tmp1, operands[1]));
2436 emit_insn (gen_rtx_SET (SImode, tmp2,
2437 gen_rtx_ASHIFT (SImode, tmp1, lshft)));
2438 emit_insn (gen_rtx_SET (SImode, operands[0],
2439 gen_rtx_LSHIFTRT (SImode, tmp2, rshft)));
2440 DONE;
2441 }
2442 else
2443 {
2444 /* Make the compiler figure out some alternative mechanism. */
2445 FAIL;
2446 }
2448 /* Emit the RTL pattern; something will match it later. */
2449 }")
2451 (define_expand "insv"
2452 [(set (zero_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "")
2453 (match_operand:SI 1 "const_int_operand" "")
2454 (match_operand:SI 2 "const_int_operand" ""))
2455 (match_operand:SI 3 "general_operand" ""))
2456 (clobber (reg:CC 17))]
2457 ""
2458 "
2459 {
2460 if (mcore_expand_insv (operands))
2461 {
2462 DONE;
2463 }
2464 else
2465 {
2466 FAIL;
2467 }
2468 }")
2470 ;;
2471 ;; the xtrb[0123] instructions handily get at 8-bit fields on nice boundaries.
2472 ;; but then, they do force you through r1.
2473 ;;
2474 ;; the combiner will build such patterns for us, so we'll make them available
2475 ;; for its use.
2476 ;;
2477 ;; Note that we have both SIGNED and UNSIGNED versions of these...
2478 ;;
2480 ;;
2481 ;; These no longer worry about the clobbering of CC bit; not sure this is
2482 ;; good...
2483 ;;
2484 ;; the SIGNED versions of these
2485 ;;
2486 (define_insn ""
2487 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b")
2488 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,r") (const_int 8) (const_int 24)))]
2489 ""
2490 "@
2491 asri %0,24
2492 xtrb0 %0,%1\;sextb %0"
2493 [(set_attr "type" "shift")])
2495 (define_insn ""
2496 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
2497 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 16)))]
2498 ""
2499 "xtrb1 %0,%1\;sextb %0"
2500 [(set_attr "type" "shift")])
2502 (define_insn ""
2503 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
2504 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 8)))]
2505 ""
2506 "xtrb2 %0,%1\;sextb %0"
2507 [(set_attr "type" "shift")])
2509 (define_insn ""
2510 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2511 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0") (const_int 8) (const_int 0)))]
2512 ""
2513 "sextb %0"
2514 [(set_attr "type" "shift")])
2516 ;; the UNSIGNED uses of xtrb[0123]
2517 ;;
2518 (define_insn ""
2519 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b")
2520 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,r") (const_int 8) (const_int 24)))]
2521 ""
2522 "@
2523 lsri %0,24
2524 xtrb0 %0,%1"
2525 [(set_attr "type" "shift")])
2527 (define_insn ""
2528 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
2529 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 16)))]
2530 ""
2531 "xtrb1 %0,%1"
2532 [(set_attr "type" "shift")])
2534 (define_insn ""
2535 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
2536 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 8)))]
2537 ""
2538 "xtrb2 %0,%1"
2539 [(set_attr "type" "shift")])
2541 ;; This can be peepholed if it follows a ldb ...
2542 (define_insn ""
2543 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b")
2544 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,r") (const_int 8) (const_int 0)))]
2545 ""
2546 "@
2547 zextb %0
2548 xtrb3 %0,%1\;zextb %0"
2549 [(set_attr "type" "shift")])
2552 ;; ------------------------------------------------------------------------
2553 ;; Block move - adapted from m88k.md
2554 ;; ------------------------------------------------------------------------
2556 (define_expand "movmemsi"
2557 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
2558 (mem:BLK (match_operand:BLK 1 "" "")))
2559 (use (match_operand:SI 2 "general_operand" ""))
2560 (use (match_operand:SI 3 "immediate_operand" ""))])]
2561 ""
2562 "
2563 {
2564 if (mcore_expand_block_move (operands))
2565 DONE;
2566 else
2567 FAIL;
2568 }")
2570 ;; ;;; ??? These patterns are meant to be generated from expand_block_move,
2571 ;; ;;; but they currently are not.
2572 ;;
2573 ;; (define_insn ""
2574 ;; [(set (match_operand:QI 0 "mcore_arith_reg_operand" "=r")
2575 ;; (match_operand:BLK 1 "mcore_general_movsrc_operand" "m"))]
2576 ;; ""
2577 ;; "ld.b %0,%1"
2578 ;; [(set_attr "type" "load")])
2579 ;;
2580 ;; (define_insn ""
2581 ;; [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
2582 ;; (match_operand:BLK 1 "mcore_general_movsrc_operand" "m"))]
2583 ;; ""
2584 ;; "ld.h %0,%1"
2585 ;; [(set_attr "type" "load")])
2586 ;;
2587 ;; (define_insn ""
2588 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2589 ;; (match_operand:BLK 1 "mcore_general_movsrc_operand" "m"))]
2590 ;; ""
2591 ;; "ld.w %0,%1"
2592 ;; [(set_attr "type" "load")])
2593 ;;
2594 ;; (define_insn ""
2595 ;; [(set (match_operand:BLK 0 "mcore_general_movdst_operand" "=m")
2596 ;; (match_operand:QI 1 "mcore_arith_reg_operand" "r"))]
2597 ;; ""
2598 ;; "st.b %1,%0"
2599 ;; [(set_attr "type" "store")])
2600 ;;
2601 ;; (define_insn ""
2602 ;; [(set (match_operand:BLK 0 "mcore_general_movdst_operand" "=m")
2603 ;; (match_operand:HI 1 "mcore_arith_reg_operand" "r"))]
2604 ;; ""
2605 ;; "st.h %1,%0"
2606 ;; [(set_attr "type" "store")])
2607 ;;
2608 ;; (define_insn ""
2609 ;; [(set (match_operand:BLK 0 "mcore_general_movdst_operand" "=m")
2610 ;; (match_operand:SI 1 "mcore_arith_reg_operand" "r"))]
2611 ;; ""
2612 ;; "st.w %1,%0"
2613 ;; [(set_attr "type" "store")])
2614 \f
2615 ;; ------------------------------------------------------------------------
2616 ;; Misc Optimizing quirks
2617 ;; ------------------------------------------------------------------------
2619 ;; pair to catch constructs like: (int *)((p+=4)-4) which happen
2620 ;; in stdarg/varargs traversal. This changes a 3 insn sequence to a 2
2621 ;; insn sequence. -- RBE 11/30/95
2622 (define_insn ""
2623 [(parallel[
2624 (set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2625 (match_operand:SI 1 "mcore_arith_reg_operand" "+r"))
2626 (set (match_dup 1) (plus:SI (match_dup 1) (match_operand 2 "mcore_arith_any_imm_operand" "")))])]
2627 "GET_CODE(operands[2]) == CONST_INT"
2628 "#"
2629 [(set_attr "length" "4")])
2631 (define_split
2632 [(parallel[
2633 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2634 (match_operand:SI 1 "mcore_arith_reg_operand" ""))
2635 (set (match_dup 1) (plus:SI (match_dup 1) (match_operand 2 "mcore_arith_any_imm_operand" "")))])]
2636 "GET_CODE(operands[2]) == CONST_INT &&
2637 operands[0] != operands[1]"
2638 [(set (match_dup 0) (match_dup 1))
2639 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))])
2641 \f
2642 ;;; Peepholes
2644 ; note: in the following patterns, use mcore_is_dead() to ensure that the
2645 ; reg we may be trashing really is dead. reload doesn't always mark
2646 ; deaths, so mcore_is_dead() (see mcore.c) scans forward to find its death. BRC
2648 ;;; A peephole to convert the 3 instruction sequence generated by reload
2649 ;;; to load a FP-offset address into a 2 instruction sequence.
2650 ;;; ??? This probably never matches anymore.
2651 (define_peephole
2652 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
2653 (match_operand:SI 1 "const_int_operand" "J"))
2654 (set (match_dup 0) (neg:SI (match_dup 0)))
2655 (set (match_dup 0)
2656 (plus:SI (match_dup 0)
2657 (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
2658 "CONST_OK_FOR_J (INTVAL (operands[1]))"
2659 "error\;mov %0,%2\;subi %0,%1")
2661 ;; Moves of inlinable constants are done late, so when a 'not' is generated
2662 ;; it is never combined with the following 'and' to generate an 'andn' b/c
2663 ;; the combiner never sees it. use a peephole to pick up this case (happens
2664 ;; mostly with bitfields) BRC
2666 (define_peephole
2667 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
2668 (match_operand:SI 1 "const_int_operand" "i"))
2669 (set (match_operand:SI 2 "mcore_arith_reg_operand" "r")
2670 (and:SI (match_dup 2) (match_dup 0)))]
2671 "mcore_const_trick_uses_not (INTVAL (operands[1])) &&
2672 operands[0] != operands[2] &&
2673 mcore_is_dead (insn, operands[0])"
2674 "* return mcore_output_andn (insn, operands);")
2676 ; when setting or clearing just two bits, it's cheapest to use two bseti's
2677 ; or bclri's. only happens when relaxing immediates. BRC
2679 (define_peephole
2680 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2681 (match_operand:SI 1 "const_int_operand" ""))
2682 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
2683 (ior:SI (match_dup 2) (match_dup 0)))]
2684 "TARGET_HARDLIT
2685 && mcore_num_ones (INTVAL (operands[1])) == 2
2686 && mcore_is_dead (insn, operands[0])"
2687 "* return mcore_output_bseti (operands[2], INTVAL (operands[1]));")
2689 (define_peephole
2690 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2691 (match_operand:SI 1 "const_int_operand" ""))
2692 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
2693 (and:SI (match_dup 2) (match_dup 0)))]
2694 "TARGET_HARDLIT && mcore_num_zeros (INTVAL (operands[1])) == 2 &&
2695 mcore_is_dead (insn, operands[0])"
2696 "* return mcore_output_bclri (operands[2], INTVAL (operands[1]));")
2698 ; change an and with a mask that has a single cleared bit into a bclri. this
2699 ; handles QI and HI mode values using the knowledge that the most significant
2700 ; bits don't matter.
2702 (define_peephole
2703 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2704 (match_operand:SI 1 "const_int_operand" ""))
2705 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
2706 (and:SI (match_operand:SI 3 "mcore_arith_reg_operand" "")
2707 (match_dup 0)))]
2708 "GET_CODE (operands[3]) == SUBREG &&
2709 GET_MODE (SUBREG_REG (operands[3])) == QImode &&
2710 mcore_num_zeros (INTVAL (operands[1]) | 0xffffff00) == 1 &&
2711 mcore_is_dead (insn, operands[0])"
2712 "*
2713 if (! mcore_is_same_reg (operands[2], operands[3]))
2714 output_asm_insn (\"mov\\t%2,%3\", operands);
2715 return mcore_output_bclri (operands[2], INTVAL (operands[1]) | 0xffffff00);")
2717 /* Do not fold these together -- mode is lost at final output phase. */
2719 (define_peephole
2720 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2721 (match_operand:SI 1 "const_int_operand" ""))
2722 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
2723 (and:SI (match_operand:SI 3 "mcore_arith_reg_operand" "")
2724 (match_dup 0)))]
2725 "GET_CODE (operands[3]) == SUBREG &&
2726 GET_MODE (SUBREG_REG (operands[3])) == HImode &&
2727 mcore_num_zeros (INTVAL (operands[1]) | 0xffff0000) == 1 &&
2728 operands[2] == operands[3] &&
2729 mcore_is_dead (insn, operands[0])"
2730 "*
2731 if (! mcore_is_same_reg (operands[2], operands[3]))
2732 output_asm_insn (\"mov\\t%2,%3\", operands);
2733 return mcore_output_bclri (operands[2], INTVAL (operands[1]) | 0xffff0000);")
2735 ; This peephole helps when using -mwide-bitfields to widen fields so they
2736 ; collapse. This, however, has the effect that a narrower mode is not used
2737 ; when desirable.
2738 ;
2739 ; e.g., sequences like:
2740 ;
2741 ; ldw r8,(r6)
2742 ; movi r7,0x00ffffff
2743 ; and r8,r7 r7 dead
2744 ; stw r8,(r6) r8 dead
2745 ;
2746 ; get peepholed to become:
2747 ;
2748 ; movi r8,0
2749 ; stb r8,(r6) r8 dead
2750 ;
2751 ; Do only easy addresses that have no offset. This peephole is also applied
2752 ; to halfwords. We need to check that the load is non-volatile before we get
2753 ; rid of it.
2755 (define_peephole
2756 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2757 (match_operand:SI 1 "memory_operand" ""))
2758 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
2759 (match_operand:SI 3 "const_int_operand" ""))
2760 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))
2761 (set (match_operand:SI 4 "memory_operand" "") (match_dup 0))]
2762 "mcore_is_dead (insn, operands[0]) &&
2763 ! MEM_VOLATILE_P (operands[1]) &&
2764 mcore_is_dead (insn, operands[2]) &&
2765 (mcore_byte_offset (INTVAL (operands[3])) > -1 ||
2766 mcore_halfword_offset (INTVAL (operands[3])) > -1) &&
2767 ! MEM_VOLATILE_P (operands[4]) &&
2768 GET_CODE (XEXP (operands[4], 0)) == REG"
2769 "*
2770 {
2771 int ofs;
2772 machine_mode mode;
2773 rtx base_reg = XEXP (operands[4], 0);
2775 if ((ofs = mcore_byte_offset (INTVAL (operands[3]))) > -1)
2776 mode = QImode;
2777 else if ((ofs = mcore_halfword_offset (INTVAL (operands[3]))) > -1)
2778 mode = HImode;
2779 else
2780 gcc_unreachable ();
2782 if (ofs > 0)
2783 operands[4] = gen_rtx_MEM (mode,
2784 gen_rtx_PLUS (SImode, base_reg, GEN_INT(ofs)));
2785 else
2786 operands[4] = gen_rtx_MEM (mode, base_reg);
2788 if (mode == QImode)
2789 return \"movi %0,0\\n\\tst.b %0,%4\";
2791 return \"movi %0,0\\n\\tst.h %0,%4\";
2792 }")
2794 ; from sop11. get btsti's for (LT A 0) where A is a QI or HI value
2796 (define_peephole
2797 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
2798 (sign_extend:SI (match_operand:QI 1 "mcore_arith_reg_operand" "0")))
2799 (set (reg:CC 17)
2800 (lt:CC (match_dup 0)
2801 (const_int 0)))]
2802 "mcore_is_dead (insn, operands[0])"
2803 "btsti %0,7")
2805 (define_peephole
2806 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
2807 (sign_extend:SI (match_operand:HI 1 "mcore_arith_reg_operand" "0")))
2808 (set (reg:CC 17)
2809 (lt:CC (match_dup 0)
2810 (const_int 0)))]
2811 "mcore_is_dead (insn, operands[0])"
2812 "btsti %0,15")
2814 ; Pick up a tst. This combination happens because the immediate is not
2815 ; allowed to fold into one of the operands of the tst. Does not happen
2816 ; when relaxing immediates. BRC
2818 (define_peephole
2819 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2820 (match_operand:SI 1 "mcore_arith_reg_operand" ""))
2821 (set (match_dup 0)
2822 (and:SI (match_dup 0)
2823 (match_operand:SI 2 "mcore_literal_K_operand" "")))
2824 (set (reg:CC 17) (ne:CC (match_dup 0) (const_int 0)))]
2825 "mcore_is_dead (insn, operands[0])"
2826 "movi %0,%2\;tst %1,%0")
2828 (define_peephole
2829 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2830 (if_then_else:SI (ne (zero_extract:SI
2831 (match_operand:SI 1 "mcore_arith_reg_operand" "")
2832 (const_int 1)
2833 (match_operand:SI 2 "mcore_literal_K_operand" ""))
2834 (const_int 0))
2835 (match_operand:SI 3 "mcore_arith_imm_operand" "")
2836 (match_operand:SI 4 "mcore_arith_imm_operand" "")))
2837 (set (reg:CC 17) (ne:CC (match_dup 0) (const_int 0)))]
2838 ""
2839 "*
2840 {
2841 unsigned int op0 = REGNO (operands[0]);
2843 if (GET_CODE (operands[3]) == REG)
2844 {
2845 if (REGNO (operands[3]) == op0 && GET_CODE (operands[4]) == CONST_INT
2846 && INTVAL (operands[4]) == 0)
2847 return \"btsti %1,%2\\n\\tclrf %0\";
2848 else if (GET_CODE (operands[4]) == REG)
2849 {
2850 if (REGNO (operands[4]) == op0)
2851 return \"btsti %1,%2\\n\\tmovf %0,%3\";
2852 else if (REGNO (operands[3]) == op0)
2853 return \"btsti %1,%2\\n\\tmovt %0,%4\";
2854 }
2856 gcc_unreachable ();
2857 }
2858 else if (GET_CODE (operands[3]) == CONST_INT
2859 && INTVAL (operands[3]) == 0
2860 && GET_CODE (operands[4]) == REG)
2861 return \"btsti %1,%2\\n\\tclrt %0\";
2863 gcc_unreachable ();
2864 }")
2866 ; experimental - do the constant folding ourselves. note that this isn't
2867 ; re-applied like we'd really want. i.e., four ands collapse into two
2868 ; instead of one. this is because peepholes are applied as a sliding
2869 ; window. the peephole does not generate new rtl's, but instead slides
2870 ; across the rtl's generating machine instructions. it would be nice
2871 ; if the peephole optimizer is changed to re-apply patterns and to gen
2872 ; new rtl's. this is more flexible. the pattern below helps when we're
2873 ; not using relaxed immediates. BRC
2875 ;(define_peephole
2876 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2877 ; (match_operand:SI 1 "const_int_operand" ""))
2878 ; (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
2879 ; (and:SI (match_dup 2) (match_dup 0)))
2880 ; (set (match_dup 0)
2881 ; (match_operand:SI 3 "const_int_operand" ""))
2882 ; (set (match_dup 2)
2883 ; (and:SI (match_dup 2) (match_dup 0)))]
2884 ; "!TARGET_RELAX_IMM && mcore_is_dead (insn, operands[0]) &&
2885 ; mcore_const_ok_for_inline (INTVAL (operands[1]) & INTVAL (operands[3]))"
2886 ; "*
2887 ;{
2888 ; rtx out_operands[2];
2889 ; out_operands[0] = operands[0];
2890 ; out_operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[3]));
2891 ;
2892 ; output_inline_const (SImode, out_operands);
2893 ;
2894 ; output_asm_insn (\"and %2,%0\", operands);
2895 ;
2896 ; return \"\";
2897 ;}")
2899 ; BRC: for inlining get rid of extra test - experimental
2900 ;(define_peephole
2901 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
2902 ; (ne:SI (reg:CC 17) (const_int 0)))
2903 ; (set (reg:CC 17) (ne:CC (match_dup 0) (const_int 0)))
2904 ; (set (pc)
2905 ; (if_then_else (eq (reg:CC 17) (const_int 0))
2906 ; (label_ref (match_operand 1 "" ""))
2907 ; (pc)))]
2908 ; ""
2909 ; "*
2910 ;{
2911 ; if (get_attr_length (insn) == 10)
2912 ; {
2913 ; output_asm_insn (\"bt 2f\\n\\tjmpi [1f]\", operands);
2914 ; output_asm_insn (\".align 2\\n1:\", operands);
2915 ; output_asm_insn (\".long %1\\n2:\", operands);
2916 ; return \"\";
2917 ; }
2918 ; return \"bf %l1\";
2919 ;}")
2921 \f
2922 ;;; Special patterns for dealing with the constant pool.
2924 ;;; 4 byte integer in line.
2926 (define_insn "consttable_4"
2927 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 0)]
2928 ""
2929 "*
2930 {
2931 assemble_integer (operands[0], 4, BITS_PER_WORD, 1);
2932 return \"\";
2933 }"
2934 [(set_attr "length" "4")])
2936 ;;; align to a four byte boundary.
2938 (define_insn "align_4"
2939 [(unspec_volatile [(const_int 0)] 1)]
2940 ""
2941 ".align 2")
2943 ;;; Handle extra constant pool entries created during final pass.
2945 (define_insn "consttable_end"
2946 [(unspec_volatile [(const_int 0)] 2)]
2947 ""
2948 "* return mcore_output_jump_label_table ();")
2949 \f
2950 ;;
2951 ;; Stack allocation -- in particular, for alloca().
2952 ;; this is *not* what we use for entry into functions.
2953 ;;
2954 ;; This is how we allocate stack space. If we are allocating a
2955 ;; constant amount of space and we know it is less than 4096
2956 ;; bytes, we need do nothing.
2957 ;;
2958 ;; If it is more than 4096 bytes, we need to probe the stack
2959 ;; periodically.
2960 ;;
2961 ;; operands[1], the distance is a POSITIVE number indicating that we
2962 ;; are allocating stack space
2963 ;;
2964 (define_expand "allocate_stack"
2965 [(set (reg:SI 0)
2966 (plus:SI (reg:SI 0)
2967 (match_operand:SI 1 "general_operand" "")))
2968 (set (match_operand:SI 0 "register_operand" "=r")
2969 (match_dup 2))]
2970 ""
2971 "
2972 {
2973 /* If he wants no probing, just do it for him. */
2974 if (mcore_stack_increment == 0)
2975 {
2976 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,operands[1]));
2977 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
2978 DONE;
2979 }
2981 /* For small constant growth, we unroll the code. */
2982 if (GET_CODE (operands[1]) == CONST_INT
2983 && INTVAL (operands[1]) < 8 * STACK_UNITS_MAXSTEP)
2984 {
2985 HOST_WIDE_INT left = INTVAL(operands[1]);
2987 /* If it's a long way, get close enough for a last shot. */
2988 if (left >= STACK_UNITS_MAXSTEP)
2989 {
2990 rtx tmp = gen_reg_rtx (Pmode);
2991 emit_insn (gen_movsi (tmp, GEN_INT (STACK_UNITS_MAXSTEP)));
2992 do
2993 {
2994 rtx memref = gen_rtx_MEM (SImode, stack_pointer_rtx);
2996 MEM_VOLATILE_P (memref) = 1;
2997 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
2998 emit_insn (gen_movsi (memref, stack_pointer_rtx));
2999 left -= STACK_UNITS_MAXSTEP;
3000 }
3001 while (left > STACK_UNITS_MAXSTEP);
3002 }
3003 /* Perform the final adjustment. */
3004 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-left)));
3005 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
3006 DONE;
3007 }
3008 else
3009 {
3010 rtx_code_label *out_label = 0;
3011 rtx_code_label *loop_label = gen_label_rtx ();
3012 rtx step = gen_reg_rtx (Pmode);
3013 rtx tmp = gen_reg_rtx (Pmode);
3014 rtx test, memref;
3016 #if 1
3017 emit_insn (gen_movsi (tmp, operands[1]));
3018 emit_insn (gen_movsi (step, GEN_INT (STACK_UNITS_MAXSTEP)));
3020 if (GET_CODE (operands[1]) != CONST_INT)
3021 {
3022 out_label = gen_label_rtx ();
3023 test = gen_rtx_GEU (VOIDmode, step, tmp); /* quick out */
3024 emit_jump_insn (gen_cbranchsi4 (test, step, tmp, out_label));
3025 }
3027 /* Run a loop that steps it incrementally. */
3028 emit_label (loop_label);
3030 /* Extend a step, probe, and adjust remaining count. */
3031 emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx, step));
3032 memref = gen_rtx_MEM (SImode, stack_pointer_rtx);
3033 MEM_VOLATILE_P (memref) = 1;
3034 emit_insn(gen_movsi(memref, stack_pointer_rtx));
3035 emit_insn(gen_subsi3(tmp, tmp, step));
3037 /* Loop condition -- going back up. */
3038 test = gen_rtx_LTU (VOIDmode, step, tmp);
3039 emit_jump_insn (gen_cbranchsi4 (test, step, tmp, loop_label));
3041 if (out_label)
3042 emit_label (out_label);
3044 /* Bump the residual. */
3045 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
3046 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
3047 DONE;
3048 #else
3049 /* simple one-shot -- ensure register and do a subtract.
3050 * This does NOT comply with the ABI. */
3051 emit_insn (gen_movsi (tmp, operands[1]));
3052 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
3053 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
3054 DONE;
3055 #endif
3056 }
3057 }")