1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "stor-layout.h"
33 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
40 #include "insn-attr.h"
42 #include "diagnostic-core.h"
47 #include "target-def.h"
50 #include "dominance.h"
56 #include "cfgcleanup.h"
58 #include "basic-block.h"
60 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
61 #include "sched-int.h"
62 #include "insn-codes.h"
69 enum reg_class regno_reg_class
[] =
71 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
72 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
73 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
74 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
75 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
76 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
81 /* The minimum number of integer registers that we want to save with the
82 movem instruction. Using two movel instructions instead of a single
83 moveml is about 15% faster for the 68020 and 68030 at no expense in
85 #define MIN_MOVEM_REGS 3
87 /* The minimum number of floating point registers that we want to save
88 with the fmovem instruction. */
89 #define MIN_FMOVEM_REGS 1
91 /* Structure describing stack frame layout. */
94 /* Stack pointer to frame pointer offset. */
97 /* Offset of FPU registers. */
98 HOST_WIDE_INT foffset
;
100 /* Frame size in bytes (rounded up). */
103 /* Data and address register. */
105 unsigned int reg_mask
;
109 unsigned int fpu_mask
;
111 /* Offsets relative to ARG_POINTER. */
112 HOST_WIDE_INT frame_pointer_offset
;
113 HOST_WIDE_INT stack_pointer_offset
;
115 /* Function which the above information refers to. */
119 /* Current frame information calculated by m68k_compute_frame_layout(). */
120 static struct m68k_frame current_frame
;
122 /* Structure describing an m68k address.
124 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
125 with null fields evaluating to 0. Here:
127 - BASE satisfies m68k_legitimate_base_reg_p
128 - INDEX satisfies m68k_legitimate_index_reg_p
129 - OFFSET satisfies m68k_legitimate_constant_address_p
131 INDEX is either HImode or SImode. The other fields are SImode.
133 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
134 the address is (BASE)+. */
135 struct m68k_address
{
143 static int m68k_sched_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
144 static int m68k_sched_issue_rate (void);
145 static int m68k_sched_variable_issue (FILE *, int, rtx_insn
*, int);
146 static void m68k_sched_md_init_global (FILE *, int, int);
147 static void m68k_sched_md_finish_global (FILE *, int);
148 static void m68k_sched_md_init (FILE *, int, int);
149 static void m68k_sched_dfa_pre_advance_cycle (void);
150 static void m68k_sched_dfa_post_advance_cycle (void);
151 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
153 static bool m68k_can_eliminate (const int, const int);
154 static void m68k_conditional_register_usage (void);
155 static bool m68k_legitimate_address_p (machine_mode
, rtx
, bool);
156 static void m68k_option_override (void);
157 static void m68k_override_options_after_change (void);
158 static rtx
find_addr_reg (rtx
);
159 static const char *singlemove_string (rtx
*);
160 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
161 HOST_WIDE_INT
, tree
);
162 static rtx
m68k_struct_value_rtx (tree
, int);
163 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
164 tree args
, int flags
,
166 static void m68k_compute_frame_layout (void);
167 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
168 static bool m68k_ok_for_sibcall_p (tree
, tree
);
169 static bool m68k_tls_symbol_p (rtx
);
170 static rtx
m68k_legitimize_address (rtx
, rtx
, machine_mode
);
171 static bool m68k_rtx_costs (rtx
, int, int, int, int *, bool);
172 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
173 static bool m68k_return_in_memory (const_tree
, const_tree
);
175 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
176 static void m68k_trampoline_init (rtx
, tree
, rtx
);
177 static int m68k_return_pops_args (tree
, tree
, int);
178 static rtx
m68k_delegitimize_address (rtx
);
179 static void m68k_function_arg_advance (cumulative_args_t
, machine_mode
,
181 static rtx
m68k_function_arg (cumulative_args_t
, machine_mode
,
183 static bool m68k_cannot_force_const_mem (machine_mode mode
, rtx x
);
184 static bool m68k_output_addr_const_extra (FILE *, rtx
);
185 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
187 /* Initialize the GCC target structure. */
189 #if INT_OP_GROUP == INT_OP_DOT_WORD
190 #undef TARGET_ASM_ALIGNED_HI_OP
191 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
194 #if INT_OP_GROUP == INT_OP_NO_DOT
195 #undef TARGET_ASM_BYTE_OP
196 #define TARGET_ASM_BYTE_OP "\tbyte\t"
197 #undef TARGET_ASM_ALIGNED_HI_OP
198 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
199 #undef TARGET_ASM_ALIGNED_SI_OP
200 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
203 #if INT_OP_GROUP == INT_OP_DC
204 #undef TARGET_ASM_BYTE_OP
205 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
206 #undef TARGET_ASM_ALIGNED_HI_OP
207 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
208 #undef TARGET_ASM_ALIGNED_SI_OP
209 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
212 #undef TARGET_ASM_UNALIGNED_HI_OP
213 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
214 #undef TARGET_ASM_UNALIGNED_SI_OP
215 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
217 #undef TARGET_ASM_OUTPUT_MI_THUNK
218 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
219 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
220 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
222 #undef TARGET_ASM_FILE_START_APP_OFF
223 #define TARGET_ASM_FILE_START_APP_OFF true
225 #undef TARGET_LEGITIMIZE_ADDRESS
226 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
228 #undef TARGET_SCHED_ADJUST_COST
229 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
231 #undef TARGET_SCHED_ISSUE_RATE
232 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
234 #undef TARGET_SCHED_VARIABLE_ISSUE
235 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
237 #undef TARGET_SCHED_INIT_GLOBAL
238 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
240 #undef TARGET_SCHED_FINISH_GLOBAL
241 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
243 #undef TARGET_SCHED_INIT
244 #define TARGET_SCHED_INIT m68k_sched_md_init
246 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
247 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
249 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
250 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
252 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
253 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
254 m68k_sched_first_cycle_multipass_dfa_lookahead
256 #undef TARGET_OPTION_OVERRIDE
257 #define TARGET_OPTION_OVERRIDE m68k_option_override
259 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
260 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
262 #undef TARGET_RTX_COSTS
263 #define TARGET_RTX_COSTS m68k_rtx_costs
265 #undef TARGET_ATTRIBUTE_TABLE
266 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
268 #undef TARGET_PROMOTE_PROTOTYPES
269 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
271 #undef TARGET_STRUCT_VALUE_RTX
272 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
274 #undef TARGET_CANNOT_FORCE_CONST_MEM
275 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
277 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
278 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
280 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
281 #undef TARGET_RETURN_IN_MEMORY
282 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
286 #undef TARGET_HAVE_TLS
287 #define TARGET_HAVE_TLS (true)
289 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
290 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
293 #undef TARGET_LEGITIMATE_ADDRESS_P
294 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
296 #undef TARGET_CAN_ELIMINATE
297 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
299 #undef TARGET_CONDITIONAL_REGISTER_USAGE
300 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
302 #undef TARGET_TRAMPOLINE_INIT
303 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
305 #undef TARGET_RETURN_POPS_ARGS
306 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
308 #undef TARGET_DELEGITIMIZE_ADDRESS
309 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
311 #undef TARGET_FUNCTION_ARG
312 #define TARGET_FUNCTION_ARG m68k_function_arg
314 #undef TARGET_FUNCTION_ARG_ADVANCE
315 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
317 #undef TARGET_LEGITIMATE_CONSTANT_P
318 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
320 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
321 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
323 /* The value stored by TAS. */
324 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
325 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
327 static const struct attribute_spec m68k_attribute_table
[] =
329 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
330 affects_type_identity } */
331 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
333 { "interrupt_handler", 0, 0, true, false, false,
334 m68k_handle_fndecl_attribute
, false },
335 { "interrupt_thread", 0, 0, true, false, false,
336 m68k_handle_fndecl_attribute
, false },
337 { NULL
, 0, 0, false, false, false, NULL
, false }
340 struct gcc_target targetm
= TARGET_INITIALIZER
;
342 /* Base flags for 68k ISAs. */
343 #define FL_FOR_isa_00 FL_ISA_68000
344 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
345 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
346 generated 68881 code for 68020 and 68030 targets unless explicitly told
348 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
349 | FL_BITFIELD | FL_68881 | FL_CAS)
350 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
351 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
353 /* Base flags for ColdFire ISAs. */
354 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
355 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
356 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
357 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
358 /* ISA_C is not upwardly compatible with ISA_B. */
359 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
363 /* Traditional 68000 instruction sets. */
369 /* ColdFire instruction set variants. */
377 /* Information about one of the -march, -mcpu or -mtune arguments. */
378 struct m68k_target_selection
380 /* The argument being described. */
383 /* For -mcpu, this is the device selected by the option.
384 For -mtune and -march, it is a representative device
385 for the microarchitecture or ISA respectively. */
386 enum target_device device
;
388 /* The M68K_DEVICE fields associated with DEVICE. See the comment
389 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
391 enum uarch_type microarch
;
396 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
397 static const struct m68k_target_selection all_devices
[] =
399 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
400 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
401 #include "m68k-devices.def"
403 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
406 /* A list of all ISAs, mapping each one to a representative device.
407 Used for -march selection. */
408 static const struct m68k_target_selection all_isas
[] =
410 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
411 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
412 #include "m68k-isas.def"
414 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
417 /* A list of all microarchitectures, mapping each one to a representative
418 device. Used for -mtune selection. */
419 static const struct m68k_target_selection all_microarchs
[] =
421 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
422 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
423 #include "m68k-microarchs.def"
424 #undef M68K_MICROARCH
425 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
428 /* The entries associated with the -mcpu, -march and -mtune settings,
429 or null for options that have not been used. */
430 const struct m68k_target_selection
*m68k_cpu_entry
;
431 const struct m68k_target_selection
*m68k_arch_entry
;
432 const struct m68k_target_selection
*m68k_tune_entry
;
434 /* Which CPU we are generating code for. */
435 enum target_device m68k_cpu
;
437 /* Which microarchitecture to tune for. */
438 enum uarch_type m68k_tune
;
440 /* Which FPU to use. */
441 enum fpu_type m68k_fpu
;
443 /* The set of FL_* flags that apply to the target processor. */
444 unsigned int m68k_cpu_flags
;
446 /* The set of FL_* flags that apply to the processor to be tuned for. */
447 unsigned int m68k_tune_flags
;
449 /* Asm templates for calling or jumping to an arbitrary symbolic address,
450 or NULL if such calls or jumps are not supported. The address is held
452 const char *m68k_symbolic_call
;
453 const char *m68k_symbolic_jump
;
455 /* Enum variable that corresponds to m68k_symbolic_call values. */
456 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
459 /* Implement TARGET_OPTION_OVERRIDE. */
462 m68k_option_override (void)
464 const struct m68k_target_selection
*entry
;
465 unsigned long target_mask
;
467 if (global_options_set
.x_m68k_arch_option
)
468 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
470 if (global_options_set
.x_m68k_cpu_option
)
471 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
473 if (global_options_set
.x_m68k_tune_option
)
474 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
482 -march=ARCH should generate code that runs any processor
483 implementing architecture ARCH. -mcpu=CPU should override -march
484 and should generate code that runs on processor CPU, making free
485 use of any instructions that CPU understands. -mtune=UARCH applies
486 on top of -mcpu or -march and optimizes the code for UARCH. It does
487 not change the target architecture. */
490 /* Complain if the -march setting is for a different microarchitecture,
491 or includes flags that the -mcpu setting doesn't. */
493 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
494 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
495 warning (0, "-mcpu=%s conflicts with -march=%s",
496 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
498 entry
= m68k_cpu_entry
;
501 entry
= m68k_arch_entry
;
504 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
506 m68k_cpu_flags
= entry
->flags
;
508 /* Use the architecture setting to derive default values for
512 /* ColdFire is lenient about alignment. */
513 if (!TARGET_COLDFIRE
)
514 target_mask
|= MASK_STRICT_ALIGNMENT
;
516 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
517 target_mask
|= MASK_BITFIELD
;
518 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
519 target_mask
|= MASK_CF_HWDIV
;
520 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
521 target_mask
|= MASK_HARD_FLOAT
;
522 target_flags
|= target_mask
& ~target_flags_explicit
;
524 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
525 m68k_cpu
= entry
->device
;
528 m68k_tune
= m68k_tune_entry
->microarch
;
529 m68k_tune_flags
= m68k_tune_entry
->flags
;
531 #ifdef M68K_DEFAULT_TUNE
532 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
534 enum target_device dev
;
535 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
536 m68k_tune_flags
= all_devices
[dev
].flags
;
541 m68k_tune
= entry
->microarch
;
542 m68k_tune_flags
= entry
->flags
;
545 /* Set the type of FPU. */
546 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
547 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
550 /* Sanity check to ensure that msep-data and mid-sahred-library are not
551 * both specified together. Doing so simply doesn't make sense.
553 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
554 error ("cannot specify both -msep-data and -mid-shared-library");
556 /* If we're generating code for a separate A5 relative data segment,
557 * we've got to enable -fPIC as well. This might be relaxable to
558 * -fpic but it hasn't been tested properly.
560 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
563 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
564 error if the target does not support them. */
565 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
566 error ("-mpcrel -fPIC is not currently supported on selected cpu");
568 /* ??? A historic way of turning on pic, or is this intended to
569 be an embedded thing that doesn't have the same name binding
570 significance that it does on hosted ELF systems? */
571 if (TARGET_PCREL
&& flag_pic
== 0)
576 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
578 m68k_symbolic_jump
= "jra %a0";
580 else if (TARGET_ID_SHARED_LIBRARY
)
581 /* All addresses must be loaded from the GOT. */
583 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
586 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
588 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
591 /* No unconditional long branch */;
592 else if (TARGET_PCREL
)
593 m68k_symbolic_jump
= "bra%.l %c0";
595 m68k_symbolic_jump
= "bra%.l %p0";
596 /* Turn off function cse if we are doing PIC. We always want
597 function call to be done as `bsr foo@PLTPC'. */
598 /* ??? It's traditional to do this for -mpcrel too, but it isn't
599 clear how intentional that is. */
600 flag_no_function_cse
= 1;
603 switch (m68k_symbolic_call_var
)
605 case M68K_SYMBOLIC_CALL_JSR
:
606 m68k_symbolic_call
= "jsr %a0";
609 case M68K_SYMBOLIC_CALL_BSR_C
:
610 m68k_symbolic_call
= "bsr%.l %c0";
613 case M68K_SYMBOLIC_CALL_BSR_P
:
614 m68k_symbolic_call
= "bsr%.l %p0";
617 case M68K_SYMBOLIC_CALL_NONE
:
618 gcc_assert (m68k_symbolic_call
== NULL
);
625 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
626 if (align_labels
> 2)
628 warning (0, "-falign-labels=%d is not supported", align_labels
);
633 warning (0, "-falign-loops=%d is not supported", align_loops
);
638 if (stack_limit_rtx
!= NULL_RTX
&& !TARGET_68020
)
640 warning (0, "-fstack-limit- options are not supported on this cpu");
641 stack_limit_rtx
= NULL_RTX
;
644 SUBTARGET_OVERRIDE_OPTIONS
;
646 /* Setup scheduling options. */
648 m68k_sched_cpu
= CPU_CFV1
;
650 m68k_sched_cpu
= CPU_CFV2
;
652 m68k_sched_cpu
= CPU_CFV3
;
654 m68k_sched_cpu
= CPU_CFV4
;
657 m68k_sched_cpu
= CPU_UNKNOWN
;
658 flag_schedule_insns
= 0;
659 flag_schedule_insns_after_reload
= 0;
660 flag_modulo_sched
= 0;
661 flag_live_range_shrinkage
= 0;
664 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
666 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
667 m68k_sched_mac
= MAC_CF_EMAC
;
668 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
669 m68k_sched_mac
= MAC_CF_MAC
;
671 m68k_sched_mac
= MAC_NO
;
675 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
678 m68k_override_options_after_change (void)
680 if (m68k_sched_cpu
== CPU_UNKNOWN
)
682 flag_schedule_insns
= 0;
683 flag_schedule_insns_after_reload
= 0;
684 flag_modulo_sched
= 0;
685 flag_live_range_shrinkage
= 0;
689 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
690 given argument and NAME is the argument passed to -mcpu. Return NULL
691 if -mcpu was not passed. */
694 m68k_cpp_cpu_ident (const char *prefix
)
698 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
701 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
702 given argument and NAME is the name of the representative device for
703 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
706 m68k_cpp_cpu_family (const char *prefix
)
710 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
713 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
714 "interrupt_handler" attribute and interrupt_thread if FUNC has an
715 "interrupt_thread" attribute. Otherwise, return
716 m68k_fk_normal_function. */
718 enum m68k_function_kind
719 m68k_get_function_kind (tree func
)
723 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
725 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
727 return m68k_fk_interrupt_handler
;
729 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
731 return m68k_fk_interrupt_handler
;
733 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
735 return m68k_fk_interrupt_thread
;
737 return m68k_fk_normal_function
;
740 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
741 struct attribute_spec.handler. */
743 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
744 tree args ATTRIBUTE_UNUSED
,
745 int flags ATTRIBUTE_UNUSED
,
748 if (TREE_CODE (*node
) != FUNCTION_DECL
)
750 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
752 *no_add_attrs
= true;
755 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
757 error ("multiple interrupt attributes not allowed");
758 *no_add_attrs
= true;
762 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
764 error ("interrupt_thread is available only on fido");
765 *no_add_attrs
= true;
772 m68k_compute_frame_layout (void)
776 enum m68k_function_kind func_kind
=
777 m68k_get_function_kind (current_function_decl
);
778 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
779 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
781 /* Only compute the frame once per function.
782 Don't cache information until reload has been completed. */
783 if (current_frame
.funcdef_no
== current_function_funcdef_no
787 current_frame
.size
= (get_frame_size () + 3) & -4;
791 /* Interrupt thread does not need to save any register. */
792 if (!interrupt_thread
)
793 for (regno
= 0; regno
< 16; regno
++)
794 if (m68k_save_reg (regno
, interrupt_handler
))
796 mask
|= 1 << (regno
- D0_REG
);
799 current_frame
.offset
= saved
* 4;
800 current_frame
.reg_no
= saved
;
801 current_frame
.reg_mask
= mask
;
803 current_frame
.foffset
= 0;
805 if (TARGET_HARD_FLOAT
)
807 /* Interrupt thread does not need to save any register. */
808 if (!interrupt_thread
)
809 for (regno
= 16; regno
< 24; regno
++)
810 if (m68k_save_reg (regno
, interrupt_handler
))
812 mask
|= 1 << (regno
- FP0_REG
);
815 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
816 current_frame
.offset
+= current_frame
.foffset
;
818 current_frame
.fpu_no
= saved
;
819 current_frame
.fpu_mask
= mask
;
821 /* Remember what function this frame refers to. */
822 current_frame
.funcdef_no
= current_function_funcdef_no
;
825 /* Worker function for TARGET_CAN_ELIMINATE. */
828 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
830 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
834 m68k_initial_elimination_offset (int from
, int to
)
837 /* The arg pointer points 8 bytes before the start of the arguments,
838 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
839 frame pointer in most frames. */
840 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
841 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
842 return argptr_offset
;
844 m68k_compute_frame_layout ();
846 gcc_assert (to
== STACK_POINTER_REGNUM
);
849 case ARG_POINTER_REGNUM
:
850 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
851 case FRAME_POINTER_REGNUM
:
852 return current_frame
.offset
+ current_frame
.size
;
858 /* Refer to the array `regs_ever_live' to determine which registers
859 to save; `regs_ever_live[I]' is nonzero if register number I
860 is ever used in the function. This function is responsible for
861 knowing which registers should not be saved even if used.
862 Return true if we need to save REGNO. */
865 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
867 if (flag_pic
&& regno
== PIC_REG
)
869 if (crtl
->saves_all_registers
)
871 if (crtl
->uses_pic_offset_table
)
873 /* Reload may introduce constant pool references into a function
874 that thitherto didn't need a PIC register. Note that the test
875 above will not catch that case because we will only set
876 crtl->uses_pic_offset_table when emitting
877 the address reloads. */
878 if (crtl
->uses_const_pool
)
882 if (crtl
->calls_eh_return
)
887 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
888 if (test
== INVALID_REGNUM
)
895 /* Fixed regs we never touch. */
896 if (fixed_regs
[regno
])
899 /* The frame pointer (if it is such) is handled specially. */
900 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
903 /* Interrupt handlers must also save call_used_regs
904 if they are live or when calling nested functions. */
905 if (interrupt_handler
)
907 if (df_regs_ever_live_p (regno
))
910 if (!crtl
->is_leaf
&& call_used_regs
[regno
])
914 /* Never need to save registers that aren't touched. */
915 if (!df_regs_ever_live_p (regno
))
918 /* Otherwise save everything that isn't call-clobbered. */
919 return !call_used_regs
[regno
];
922 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
923 the lowest memory address. COUNT is the number of registers to be
924 moved, with register REGNO + I being moved if bit I of MASK is set.
925 STORE_P specifies the direction of the move and ADJUST_STACK_P says
926 whether or not this is pre-decrement (if STORE_P) or post-increment
927 (if !STORE_P) operation. */
930 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
931 unsigned int count
, unsigned int regno
,
932 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
935 rtx body
, addr
, src
, operands
[2];
938 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
939 mode
= reg_raw_mode
[regno
];
944 src
= plus_constant (Pmode
, base
,
946 * GET_MODE_SIZE (mode
)
947 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
948 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
951 for (; mask
!= 0; mask
>>= 1, regno
++)
954 addr
= plus_constant (Pmode
, base
, offset
);
955 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
956 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
957 XVECEXP (body
, 0, i
++)
958 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
959 offset
+= GET_MODE_SIZE (mode
);
961 gcc_assert (i
== XVECLEN (body
, 0));
963 return emit_insn (body
);
966 /* Make INSN a frame-related instruction. */
969 m68k_set_frame_related (rtx_insn
*insn
)
974 RTX_FRAME_RELATED_P (insn
) = 1;
975 body
= PATTERN (insn
);
976 if (GET_CODE (body
) == PARALLEL
)
977 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
978 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
981 /* Emit RTL for the "prologue" define_expand. */
984 m68k_expand_prologue (void)
986 HOST_WIDE_INT fsize_with_regs
;
987 rtx limit
, src
, dest
;
989 m68k_compute_frame_layout ();
991 if (flag_stack_usage_info
)
992 current_function_static_stack_size
993 = current_frame
.size
+ current_frame
.offset
;
995 /* If the stack limit is a symbol, we can check it here,
996 before actually allocating the space. */
997 if (crtl
->limit_stack
998 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
1000 limit
= plus_constant (Pmode
, stack_limit_rtx
, current_frame
.size
+ 4);
1001 if (!m68k_legitimate_constant_p (Pmode
, limit
))
1003 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
1004 limit
= gen_rtx_REG (Pmode
, D0_REG
);
1006 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
1007 stack_pointer_rtx
, limit
),
1008 stack_pointer_rtx
, limit
,
1012 fsize_with_regs
= current_frame
.size
;
1013 if (TARGET_COLDFIRE
)
1015 /* ColdFire's move multiple instructions do not allow pre-decrement
1016 addressing. Add the size of movem saves to the initial stack
1017 allocation instead. */
1018 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1019 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1020 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1021 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1024 if (frame_pointer_needed
)
1026 if (fsize_with_regs
== 0 && TUNE_68040
)
1028 /* On the 68040, two separate moves are faster than link.w 0. */
1029 dest
= gen_frame_mem (Pmode
,
1030 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1031 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1032 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1033 stack_pointer_rtx
));
1035 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1036 m68k_set_frame_related
1037 (emit_insn (gen_link (frame_pointer_rtx
,
1038 GEN_INT (-4 - fsize_with_regs
))));
1041 m68k_set_frame_related
1042 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1043 m68k_set_frame_related
1044 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1046 GEN_INT (-fsize_with_regs
))));
1049 /* If the frame pointer is needed, emit a special barrier that
1050 will prevent the scheduler from moving stores to the frame
1051 before the stack adjustment. */
1052 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1054 else if (fsize_with_regs
!= 0)
1055 m68k_set_frame_related
1056 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1058 GEN_INT (-fsize_with_regs
))));
1060 if (current_frame
.fpu_mask
)
1062 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1064 m68k_set_frame_related
1065 (m68k_emit_movem (stack_pointer_rtx
,
1066 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1067 current_frame
.fpu_no
, FP0_REG
,
1068 current_frame
.fpu_mask
, true, true));
1073 /* If we're using moveml to save the integer registers,
1074 the stack pointer will point to the bottom of the moveml
1075 save area. Find the stack offset of the first FP register. */
1076 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1079 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1080 m68k_set_frame_related
1081 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1082 current_frame
.fpu_no
, FP0_REG
,
1083 current_frame
.fpu_mask
, true, false));
1087 /* If the stack limit is not a symbol, check it here.
1088 This has the disadvantage that it may be too late... */
1089 if (crtl
->limit_stack
)
1091 if (REG_P (stack_limit_rtx
))
1092 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1094 stack_pointer_rtx
, stack_limit_rtx
,
1097 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1098 warning (0, "stack limit expression is not supported");
1101 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1103 /* Store each register separately in the same order moveml does. */
1106 for (i
= 16; i
-- > 0; )
1107 if (current_frame
.reg_mask
& (1 << i
))
1109 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1110 dest
= gen_frame_mem (SImode
,
1111 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1112 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1117 if (TARGET_COLDFIRE
)
1118 /* The required register save space has already been allocated.
1119 The first register should be stored at (%sp). */
1120 m68k_set_frame_related
1121 (m68k_emit_movem (stack_pointer_rtx
, 0,
1122 current_frame
.reg_no
, D0_REG
,
1123 current_frame
.reg_mask
, true, false));
1125 m68k_set_frame_related
1126 (m68k_emit_movem (stack_pointer_rtx
,
1127 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1128 current_frame
.reg_no
, D0_REG
,
1129 current_frame
.reg_mask
, true, true));
1132 if (!TARGET_SEP_DATA
1133 && crtl
->uses_pic_offset_table
)
1134 emit_insn (gen_load_got (pic_offset_table_rtx
));
1137 /* Return true if a simple (return) instruction is sufficient for this
1138 instruction (i.e. if no epilogue is needed). */
1141 m68k_use_return_insn (void)
1143 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1146 m68k_compute_frame_layout ();
1147 return current_frame
.offset
== 0;
1150 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1151 SIBCALL_P says which.
1153 The function epilogue should not depend on the current stack pointer!
1154 It should use the frame pointer only, if there is a frame pointer.
1155 This is mandatory because of alloca; we also take advantage of it to
1156 omit stack adjustments before returning. */
1159 m68k_expand_epilogue (bool sibcall_p
)
1161 HOST_WIDE_INT fsize
, fsize_with_regs
;
1162 bool big
, restore_from_sp
;
1164 m68k_compute_frame_layout ();
1166 fsize
= current_frame
.size
;
1168 restore_from_sp
= false;
1170 /* FIXME : crtl->is_leaf below is too strong.
1171 What we really need to know there is if there could be pending
1172 stack adjustment needed at that point. */
1173 restore_from_sp
= (!frame_pointer_needed
1174 || (!cfun
->calls_alloca
&& crtl
->is_leaf
));
1176 /* fsize_with_regs is the size we need to adjust the sp when
1177 popping the frame. */
1178 fsize_with_regs
= fsize
;
1179 if (TARGET_COLDFIRE
&& restore_from_sp
)
1181 /* ColdFire's move multiple instructions do not allow post-increment
1182 addressing. Add the size of movem loads to the final deallocation
1184 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1185 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1186 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1187 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1190 if (current_frame
.offset
+ fsize
>= 0x8000
1192 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1195 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1196 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1198 /* ColdFire's move multiple instructions do not support the
1199 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1200 stack-based restore. */
1201 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1202 GEN_INT (-(current_frame
.offset
+ fsize
)));
1203 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1204 gen_rtx_REG (Pmode
, A1_REG
),
1205 frame_pointer_rtx
));
1206 restore_from_sp
= true;
1210 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1216 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1218 /* Restore each register separately in the same order moveml does. */
1220 HOST_WIDE_INT offset
;
1222 offset
= current_frame
.offset
+ fsize
;
1223 for (i
= 0; i
< 16; i
++)
1224 if (current_frame
.reg_mask
& (1 << i
))
1230 /* Generate the address -OFFSET(%fp,%a1.l). */
1231 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1232 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1233 addr
= plus_constant (Pmode
, addr
, -offset
);
1235 else if (restore_from_sp
)
1236 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1238 addr
= plus_constant (Pmode
, frame_pointer_rtx
, -offset
);
1239 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1240 gen_frame_mem (SImode
, addr
));
1241 offset
-= GET_MODE_SIZE (SImode
);
1244 else if (current_frame
.reg_mask
)
1247 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1248 gen_rtx_REG (Pmode
, A1_REG
),
1250 -(current_frame
.offset
+ fsize
),
1251 current_frame
.reg_no
, D0_REG
,
1252 current_frame
.reg_mask
, false, false);
1253 else if (restore_from_sp
)
1254 m68k_emit_movem (stack_pointer_rtx
, 0,
1255 current_frame
.reg_no
, D0_REG
,
1256 current_frame
.reg_mask
, false,
1259 m68k_emit_movem (frame_pointer_rtx
,
1260 -(current_frame
.offset
+ fsize
),
1261 current_frame
.reg_no
, D0_REG
,
1262 current_frame
.reg_mask
, false, false);
1265 if (current_frame
.fpu_no
> 0)
1268 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1269 gen_rtx_REG (Pmode
, A1_REG
),
1271 -(current_frame
.foffset
+ fsize
),
1272 current_frame
.fpu_no
, FP0_REG
,
1273 current_frame
.fpu_mask
, false, false);
1274 else if (restore_from_sp
)
1276 if (TARGET_COLDFIRE
)
1280 /* If we used moveml to restore the integer registers, the
1281 stack pointer will still point to the bottom of the moveml
1282 save area. Find the stack offset of the first FP
1284 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1287 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1288 m68k_emit_movem (stack_pointer_rtx
, offset
,
1289 current_frame
.fpu_no
, FP0_REG
,
1290 current_frame
.fpu_mask
, false, false);
1293 m68k_emit_movem (stack_pointer_rtx
, 0,
1294 current_frame
.fpu_no
, FP0_REG
,
1295 current_frame
.fpu_mask
, false, true);
1298 m68k_emit_movem (frame_pointer_rtx
,
1299 -(current_frame
.foffset
+ fsize
),
1300 current_frame
.fpu_no
, FP0_REG
,
1301 current_frame
.fpu_mask
, false, false);
1304 if (frame_pointer_needed
)
1305 emit_insn (gen_unlink (frame_pointer_rtx
));
1306 else if (fsize_with_regs
)
1307 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1309 GEN_INT (fsize_with_regs
)));
1311 if (crtl
->calls_eh_return
)
1312 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1314 EH_RETURN_STACKADJ_RTX
));
1317 emit_jump_insn (ret_rtx
);
1320 /* Return true if X is a valid comparison operator for the dbcc
1323 Note it rejects floating point comparison operators.
1324 (In the future we could use Fdbcc).
1326 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1329 valid_dbcc_comparison_p_2 (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
)
1331 switch (GET_CODE (x
))
1333 case EQ
: case NE
: case GTU
: case LTU
:
1337 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1339 case GT
: case LT
: case GE
: case LE
:
1340 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1346 /* Return nonzero if flags are currently in the 68881 flag register. */
1348 flags_in_68881 (void)
1350 /* We could add support for these in the future */
1351 return cc_status
.flags
& CC_IN_68881
;
1354 /* Return true if PARALLEL contains register REGNO. */
1356 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1360 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1363 if (GET_CODE (parallel
) != PARALLEL
)
1366 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1370 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1371 if (REG_P (x
) && REGNO (x
) == regno
)
1378 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1381 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1383 enum m68k_function_kind kind
;
1385 /* We cannot use sibcalls for nested functions because we use the
1386 static chain register for indirect calls. */
1387 if (CALL_EXPR_STATIC_CHAIN (exp
))
1390 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1392 /* Check that the return value locations are the same. For
1393 example that we aren't returning a value from the sibling in
1394 a D0 register but then need to transfer it to a A0 register. */
1398 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1400 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1402 /* Check that the values are equal or that the result the callee
1403 function returns is superset of what the current function returns. */
1404 if (!(rtx_equal_p (cfun_value
, call_value
)
1405 || (REG_P (cfun_value
)
1406 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1410 kind
= m68k_get_function_kind (current_function_decl
);
1411 if (kind
== m68k_fk_normal_function
)
1412 /* We can always sibcall from a normal function, because it's
1413 undefined if it is calling an interrupt function. */
1416 /* Otherwise we can only sibcall if the function kind is known to be
1418 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1424 /* On the m68k all args are always pushed. */
1427 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1428 machine_mode mode ATTRIBUTE_UNUSED
,
1429 const_tree type ATTRIBUTE_UNUSED
,
1430 bool named ATTRIBUTE_UNUSED
)
1436 m68k_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1437 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1439 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1441 *cum
+= (mode
!= BLKmode
1442 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1443 : (int_size_in_bytes (type
) + 3) & ~3);
1446 /* Convert X to a legitimate function call memory reference and return the
1450 m68k_legitimize_call_address (rtx x
)
1452 gcc_assert (MEM_P (x
));
1453 if (call_operand (XEXP (x
, 0), VOIDmode
))
1455 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1458 /* Likewise for sibling calls. */
1461 m68k_legitimize_sibcall_address (rtx x
)
1463 gcc_assert (MEM_P (x
));
1464 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1467 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1468 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1471 /* Convert X to a legitimate address and return it if successful. Otherwise
1474 For the 68000, we handle X+REG by loading X into a register R and
1475 using R+REG. R will go in an address reg and indexing will be used.
1476 However, if REG is a broken-out memory address or multiplication,
1477 nothing needs to be done because REG can certainly go in an address reg. */
1480 m68k_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
1482 if (m68k_tls_symbol_p (x
))
1483 return m68k_legitimize_tls_address (x
);
1485 if (GET_CODE (x
) == PLUS
)
1487 int ch
= (x
) != (oldx
);
1490 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1492 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1495 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1497 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1500 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1504 if (GET_CODE (XEXP (x
, 1)) == REG
1505 && GET_CODE (XEXP (x
, 0)) == REG
)
1507 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1510 x
= force_operand (x
, 0);
1514 if (memory_address_p (mode
, x
))
1517 if (GET_CODE (XEXP (x
, 0)) == REG
1518 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1519 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1520 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1522 rtx temp
= gen_reg_rtx (Pmode
);
1523 rtx val
= force_operand (XEXP (x
, 1), 0);
1524 emit_move_insn (temp
, val
);
1527 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1528 && GET_CODE (XEXP (x
, 0)) == REG
)
1529 x
= force_operand (x
, 0);
1531 else if (GET_CODE (XEXP (x
, 1)) == REG
1532 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1533 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1534 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1536 rtx temp
= gen_reg_rtx (Pmode
);
1537 rtx val
= force_operand (XEXP (x
, 0), 0);
1538 emit_move_insn (temp
, val
);
1541 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1542 && GET_CODE (XEXP (x
, 1)) == REG
)
1543 x
= force_operand (x
, 0);
1551 /* Output a dbCC; jCC sequence. Note we do not handle the
1552 floating point version of this sequence (Fdbcc). We also
1553 do not handle alternative conditions when CC_NO_OVERFLOW is
1554 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1555 kick those out before we get here. */
1558 output_dbcc_and_branch (rtx
*operands
)
1560 switch (GET_CODE (operands
[3]))
1563 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1567 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1571 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1575 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1579 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1583 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1587 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1591 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1595 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1599 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1606 /* If the decrement is to be done in SImode, then we have
1607 to compensate for the fact that dbcc decrements in HImode. */
1608 switch (GET_MODE (operands
[0]))
1611 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1623 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1626 enum rtx_code op_code
= GET_CODE (op
);
1628 /* This does not produce a useful cc. */
1631 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1632 below. Swap the operands and change the op if these requirements
1633 are not fulfilled. */
1634 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1638 operand1
= operand2
;
1640 op_code
= swap_condition (op_code
);
1642 loperands
[0] = operand1
;
1643 if (GET_CODE (operand1
) == REG
)
1644 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1646 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1647 if (operand2
!= const0_rtx
)
1649 loperands
[2] = operand2
;
1650 if (GET_CODE (operand2
) == REG
)
1651 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1653 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1655 loperands
[4] = gen_label_rtx ();
1656 if (operand2
!= const0_rtx
)
1657 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1660 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1661 output_asm_insn ("tst%.l %0", loperands
);
1663 output_asm_insn ("cmp%.w #0,%0", loperands
);
1665 output_asm_insn ("jne %l4", loperands
);
1667 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1668 output_asm_insn ("tst%.l %1", loperands
);
1670 output_asm_insn ("cmp%.w #0,%1", loperands
);
1673 loperands
[5] = dest
;
1678 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1679 CODE_LABEL_NUMBER (loperands
[4]));
1680 output_asm_insn ("seq %5", loperands
);
1684 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1685 CODE_LABEL_NUMBER (loperands
[4]));
1686 output_asm_insn ("sne %5", loperands
);
1690 loperands
[6] = gen_label_rtx ();
1691 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1692 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1693 CODE_LABEL_NUMBER (loperands
[4]));
1694 output_asm_insn ("sgt %5", loperands
);
1695 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1696 CODE_LABEL_NUMBER (loperands
[6]));
1700 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1701 CODE_LABEL_NUMBER (loperands
[4]));
1702 output_asm_insn ("shi %5", loperands
);
1706 loperands
[6] = gen_label_rtx ();
1707 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1708 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1709 CODE_LABEL_NUMBER (loperands
[4]));
1710 output_asm_insn ("slt %5", loperands
);
1711 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1712 CODE_LABEL_NUMBER (loperands
[6]));
1716 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1717 CODE_LABEL_NUMBER (loperands
[4]));
1718 output_asm_insn ("scs %5", loperands
);
1722 loperands
[6] = gen_label_rtx ();
1723 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1724 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1725 CODE_LABEL_NUMBER (loperands
[4]));
1726 output_asm_insn ("sge %5", loperands
);
1727 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1728 CODE_LABEL_NUMBER (loperands
[6]));
1732 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1733 CODE_LABEL_NUMBER (loperands
[4]));
1734 output_asm_insn ("scc %5", loperands
);
1738 loperands
[6] = gen_label_rtx ();
1739 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1740 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1741 CODE_LABEL_NUMBER (loperands
[4]));
1742 output_asm_insn ("sle %5", loperands
);
1743 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1744 CODE_LABEL_NUMBER (loperands
[6]));
1748 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1749 CODE_LABEL_NUMBER (loperands
[4]));
1750 output_asm_insn ("sls %5", loperands
);
1760 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx_insn
*insn
, int signpos
)
1762 operands
[0] = countop
;
1763 operands
[1] = dataop
;
1765 if (GET_CODE (countop
) == CONST_INT
)
1767 register int count
= INTVAL (countop
);
1768 /* If COUNT is bigger than size of storage unit in use,
1769 advance to the containing unit of same size. */
1770 if (count
> signpos
)
1772 int offset
= (count
& ~signpos
) / 8;
1773 count
= count
& signpos
;
1774 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1776 if (count
== signpos
)
1777 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1779 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1781 /* These three statements used to use next_insns_test_no...
1782 but it appears that this should do the same job. */
1784 && next_insn_tests_no_inequality (insn
))
1787 && next_insn_tests_no_inequality (insn
))
1790 && next_insn_tests_no_inequality (insn
))
1792 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1793 On some m68k variants unfortunately that's slower than btst.
1794 On 68000 and higher, that should also work for all HImode operands. */
1795 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1797 if (count
== 3 && DATA_REG_P (operands
[1])
1798 && next_insn_tests_no_inequality (insn
))
1800 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1801 return "move%.w %1,%%ccr";
1803 if (count
== 2 && DATA_REG_P (operands
[1])
1804 && next_insn_tests_no_inequality (insn
))
1806 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1807 return "move%.w %1,%%ccr";
1809 /* count == 1 followed by bvc/bvs and
1810 count == 0 followed by bcc/bcs are also possible, but need
1811 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1814 cc_status
.flags
= CC_NOT_NEGATIVE
;
1816 return "btst %0,%1";
1819 /* Return true if X is a legitimate base register. STRICT_P says
1820 whether we need strict checking. */
1823 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1825 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1826 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1831 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1832 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1835 /* Return true if X is a legitimate index register. STRICT_P says
1836 whether we need strict checking. */
1839 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1841 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1846 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1847 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1850 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1851 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1852 ADDRESS if so. STRICT_P says whether we need strict checking. */
1855 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1859 /* Check for a scale factor. */
1861 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1862 && GET_CODE (x
) == MULT
1863 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1864 && (INTVAL (XEXP (x
, 1)) == 2
1865 || INTVAL (XEXP (x
, 1)) == 4
1866 || (INTVAL (XEXP (x
, 1)) == 8
1867 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1869 scale
= INTVAL (XEXP (x
, 1));
1873 /* Check for a word extension. */
1874 if (!TARGET_COLDFIRE
1875 && GET_CODE (x
) == SIGN_EXTEND
1876 && GET_MODE (XEXP (x
, 0)) == HImode
)
1879 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1881 address
->scale
= scale
;
1889 /* Return true if X is an illegitimate symbolic constant. */
1892 m68k_illegitimate_symbolic_constant_p (rtx x
)
1896 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1898 split_const (x
, &base
, &offset
);
1899 if (GET_CODE (base
) == SYMBOL_REF
1900 && !offset_within_block_p (base
, INTVAL (offset
)))
1903 return m68k_tls_reference_p (x
, false);
1906 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1909 m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1911 return m68k_illegitimate_symbolic_constant_p (x
);
1914 /* Return true if X is a legitimate constant address that can reach
1915 bytes in the range [X, X + REACH). STRICT_P says whether we need
1919 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1923 if (!CONSTANT_ADDRESS_P (x
))
1927 && !(strict_p
&& TARGET_PCREL
)
1928 && symbolic_operand (x
, VOIDmode
))
1931 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1933 split_const (x
, &base
, &offset
);
1934 if (GET_CODE (base
) == SYMBOL_REF
1935 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1939 return !m68k_tls_reference_p (x
, false);
1942 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1943 labels will become jump tables. */
1946 m68k_jump_table_ref_p (rtx x
)
1948 if (GET_CODE (x
) != LABEL_REF
)
1951 rtx_insn
*insn
= as_a
<rtx_insn
*> (XEXP (x
, 0));
1952 if (!NEXT_INSN (insn
) && !PREV_INSN (insn
))
1955 insn
= next_nonnote_insn (insn
);
1956 return insn
&& JUMP_TABLE_DATA_P (insn
);
1959 /* Return true if X is a legitimate address for values of mode MODE.
1960 STRICT_P says whether strict checking is needed. If the address
1961 is valid, describe its components in *ADDRESS. */
1964 m68k_decompose_address (machine_mode mode
, rtx x
,
1965 bool strict_p
, struct m68k_address
*address
)
1969 memset (address
, 0, sizeof (*address
));
1971 if (mode
== BLKmode
)
1974 reach
= GET_MODE_SIZE (mode
);
1976 /* Check for (An) (mode 2). */
1977 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1983 /* Check for -(An) and (An)+ (modes 3 and 4). */
1984 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1985 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1987 address
->code
= GET_CODE (x
);
1988 address
->base
= XEXP (x
, 0);
1992 /* Check for (d16,An) (mode 5). */
1993 if (GET_CODE (x
) == PLUS
1994 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1995 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1996 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1998 address
->base
= XEXP (x
, 0);
1999 address
->offset
= XEXP (x
, 1);
2003 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2004 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2006 if (GET_CODE (x
) == PLUS
2007 && XEXP (x
, 0) == pic_offset_table_rtx
)
2009 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2010 they are invalid in this context. */
2011 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
2013 address
->base
= XEXP (x
, 0);
2014 address
->offset
= XEXP (x
, 1);
2019 /* The ColdFire FPU only accepts addressing modes 2-5. */
2020 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2023 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2024 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2025 All these modes are variations of mode 7. */
2026 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2028 address
->offset
= x
;
2032 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2035 ??? do_tablejump creates these addresses before placing the target
2036 label, so we have to assume that unplaced labels are jump table
2037 references. It seems unlikely that we would ever generate indexed
2038 accesses to unplaced labels in other cases. */
2039 if (GET_CODE (x
) == PLUS
2040 && m68k_jump_table_ref_p (XEXP (x
, 1))
2041 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2043 address
->offset
= XEXP (x
, 1);
2047 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2048 (bd,An,Xn.SIZE*SCALE) addresses. */
2052 /* Check for a nonzero base displacement. */
2053 if (GET_CODE (x
) == PLUS
2054 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2056 address
->offset
= XEXP (x
, 1);
2060 /* Check for a suppressed index register. */
2061 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2067 /* Check for a suppressed base register. Do not allow this case
2068 for non-symbolic offsets as it effectively gives gcc freedom
2069 to treat data registers as base registers, which can generate
2072 && symbolic_operand (address
->offset
, VOIDmode
)
2073 && m68k_decompose_index (x
, strict_p
, address
))
2078 /* Check for a nonzero base displacement. */
2079 if (GET_CODE (x
) == PLUS
2080 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2081 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2083 address
->offset
= XEXP (x
, 1);
2088 /* We now expect the sum of a base and an index. */
2089 if (GET_CODE (x
) == PLUS
)
2091 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2092 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2094 address
->base
= XEXP (x
, 0);
2098 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2099 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2101 address
->base
= XEXP (x
, 1);
2108 /* Return true if X is a legitimate address for values of mode MODE.
2109 STRICT_P says whether strict checking is needed. */
2112 m68k_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2114 struct m68k_address address
;
2116 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2119 /* Return true if X is a memory, describing its address in ADDRESS if so.
2120 Apply strict checking if called during or after reload. */
2123 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2126 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2127 reload_in_progress
|| reload_completed
,
2131 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2134 m68k_legitimate_constant_p (machine_mode mode
, rtx x
)
2136 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2139 /* Return true if X matches the 'Q' constraint. It must be a memory
2140 with a base address and no constant offset or index. */
2143 m68k_matches_q_p (rtx x
)
2145 struct m68k_address address
;
2147 return (m68k_legitimate_mem_p (x
, &address
)
2148 && address
.code
== UNKNOWN
2154 /* Return true if X matches the 'U' constraint. It must be a base address
2155 with a constant offset and no index. */
2158 m68k_matches_u_p (rtx x
)
2160 struct m68k_address address
;
2162 return (m68k_legitimate_mem_p (x
, &address
)
2163 && address
.code
== UNKNOWN
2169 /* Return GOT pointer. */
2174 if (pic_offset_table_rtx
== NULL_RTX
)
2175 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2177 crtl
->uses_pic_offset_table
= 1;
2179 return pic_offset_table_rtx
;
2182 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2184 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2185 RELOC_TLSIE
, RELOC_TLSLE
};
2187 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2189 /* Wrap symbol X into unspec representing relocation RELOC.
2190 BASE_REG - register that should be added to the result.
2191 TEMP_REG - if non-null, temporary register. */
2194 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2198 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2200 if (TARGET_COLDFIRE
&& use_x_p
)
2201 /* When compiling with -mx{got, tls} switch the code will look like this:
2203 move.l <X>@<RELOC>,<TEMP_REG>
2204 add.l <BASE_REG>,<TEMP_REG> */
2206 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2207 to put @RELOC after reference. */
2208 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2210 x
= gen_rtx_CONST (Pmode
, x
);
2212 if (temp_reg
== NULL
)
2214 gcc_assert (can_create_pseudo_p ());
2215 temp_reg
= gen_reg_rtx (Pmode
);
2218 emit_move_insn (temp_reg
, x
);
2219 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2224 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2226 x
= gen_rtx_CONST (Pmode
, x
);
2228 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2234 /* Helper for m68k_unwrap_symbol.
2235 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2236 sets *RELOC_PTR to relocation type for the symbol. */
2239 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2240 enum m68k_reloc
*reloc_ptr
)
2242 if (GET_CODE (orig
) == CONST
)
2245 enum m68k_reloc dummy
;
2249 if (reloc_ptr
== NULL
)
2252 /* Handle an addend. */
2253 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2254 && CONST_INT_P (XEXP (x
, 1)))
2257 if (GET_CODE (x
) == UNSPEC
)
2259 switch (XINT (x
, 1))
2261 case UNSPEC_RELOC16
:
2262 orig
= XVECEXP (x
, 0, 0);
2263 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2266 case UNSPEC_RELOC32
:
2267 if (unwrap_reloc32_p
)
2269 orig
= XVECEXP (x
, 0, 0);
2270 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2283 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2284 UNSPEC_RELOC32 wrappers. */
2287 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2289 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2292 /* Prescan insn before outputing assembler for it. */
2295 m68k_final_prescan_insn (rtx_insn
*insn ATTRIBUTE_UNUSED
,
2296 rtx
*operands
, int n_operands
)
2300 /* Combine and, possibly, other optimizations may do good job
2302 (const (unspec [(symbol)]))
2304 (const (plus (unspec [(symbol)])
2306 The problem with this is emitting @TLS or @GOT decorations.
2307 The decoration is emitted when processing (unspec), so the
2308 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2310 It seems that the easiest solution to this is to convert such
2312 (const (unspec [(plus (symbol)
2314 Note, that the top level of operand remains intact, so we don't have
2315 to patch up anything outside of the operand. */
2317 subrtx_var_iterator::array_type array
;
2318 for (i
= 0; i
< n_operands
; ++i
)
2324 FOR_EACH_SUBRTX_VAR (iter
, array
, op
, ALL
)
2327 if (m68k_unwrap_symbol (x
, true) != x
)
2331 gcc_assert (GET_CODE (x
) == CONST
);
2334 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2339 unspec
= XEXP (plus
, 0);
2340 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2341 addend
= XEXP (plus
, 1);
2342 gcc_assert (CONST_INT_P (addend
));
2344 /* We now have all the pieces, rearrange them. */
2346 /* Move symbol to plus. */
2347 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2349 /* Move plus inside unspec. */
2350 XVECEXP (unspec
, 0, 0) = plus
;
2352 /* Move unspec to top level of const. */
2353 XEXP (x
, 0) = unspec
;
2355 iter
.skip_subrtxes ();
2361 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2362 If REG is non-null, use it; generate new pseudo otherwise. */
2365 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2369 if (reg
== NULL_RTX
)
2371 gcc_assert (can_create_pseudo_p ());
2372 reg
= gen_reg_rtx (Pmode
);
2375 insn
= emit_move_insn (reg
, x
);
2376 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2378 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2383 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2387 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2389 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2391 x
= gen_rtx_MEM (Pmode
, x
);
2392 MEM_READONLY_P (x
) = 1;
2397 /* Legitimize PIC addresses. If the address is already
2398 position-independent, we return ORIG. Newly generated
2399 position-independent addresses go to REG. If we need more
2400 than one register, we lose.
2402 An address is legitimized by making an indirect reference
2403 through the Global Offset Table with the name of the symbol
2406 The assembler and linker are responsible for placing the
2407 address of the symbol in the GOT. The function prologue
2408 is responsible for initializing a5 to the starting address
2411 The assembler is also responsible for translating a symbol name
2412 into a constant displacement from the start of the GOT.
2414 A quick example may make things a little clearer:
2416 When not generating PIC code to store the value 12345 into _foo
2417 we would generate the following code:
2421 When generating PIC two transformations are made. First, the compiler
2422 loads the address of foo into a register. So the first transformation makes:
2427 The code in movsi will intercept the lea instruction and call this
2428 routine which will transform the instructions into:
2430 movel a5@(_foo:w), a0
2434 That (in a nutshell) is how *all* symbol and label references are
2438 legitimize_pic_address (rtx orig
, machine_mode mode ATTRIBUTE_UNUSED
,
2443 /* First handle a simple SYMBOL_REF or LABEL_REF */
2444 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2448 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2449 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2451 else if (GET_CODE (orig
) == CONST
)
2455 /* Make sure this has not already been legitimized. */
2456 if (m68k_unwrap_symbol (orig
, true) != orig
)
2461 /* legitimize both operands of the PLUS */
2462 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2464 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2465 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2466 base
== reg
? 0 : reg
);
2468 if (GET_CODE (orig
) == CONST_INT
)
2469 pic_ref
= plus_constant (Pmode
, base
, INTVAL (orig
));
2471 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2477 /* The __tls_get_addr symbol. */
2478 static GTY(()) rtx m68k_tls_get_addr
;
2480 /* Return SYMBOL_REF for __tls_get_addr. */
2483 m68k_get_tls_get_addr (void)
2485 if (m68k_tls_get_addr
== NULL_RTX
)
2486 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2488 return m68k_tls_get_addr
;
2491 /* Return libcall result in A0 instead of usual D0. */
2492 static bool m68k_libcall_value_in_a0_p
= false;
2494 /* Emit instruction sequence that calls __tls_get_addr. X is
2495 the TLS symbol we are referencing and RELOC is the symbol type to use
2496 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2497 emitted. A pseudo register with result of __tls_get_addr call is
2501 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2507 /* Emit the call sequence. */
2510 /* FIXME: Unfortunately, emit_library_call_value does not
2511 consider (plus (%a5) (const (unspec))) to be a good enough
2512 operand for push, so it forces it into a register. The bad
2513 thing about this is that combiner, due to copy propagation and other
2514 optimizations, sometimes can not later fix this. As a consequence,
2515 additional register may be allocated resulting in a spill.
2516 For reference, see args processing loops in
2517 calls.c:emit_library_call_value_1.
2518 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2519 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2521 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2522 is the simpliest way of generating a call. The difference between
2523 __tls_get_addr() and libcall is that the result is returned in D0
2524 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2525 which temporarily switches returning the result to A0. */
2527 m68k_libcall_value_in_a0_p
= true;
2528 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2529 Pmode
, 1, x
, Pmode
);
2530 m68k_libcall_value_in_a0_p
= false;
2532 insns
= get_insns ();
2535 gcc_assert (can_create_pseudo_p ());
2536 dest
= gen_reg_rtx (Pmode
);
2537 emit_libcall_block (insns
, dest
, a0
, eqv
);
2542 /* The __tls_get_addr symbol. */
2543 static GTY(()) rtx m68k_read_tp
;
2545 /* Return SYMBOL_REF for __m68k_read_tp. */
2548 m68k_get_m68k_read_tp (void)
2550 if (m68k_read_tp
== NULL_RTX
)
2551 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2553 return m68k_read_tp
;
2556 /* Emit instruction sequence that calls __m68k_read_tp.
2557 A pseudo register with result of __m68k_read_tp call is returned. */
2560 m68k_call_m68k_read_tp (void)
2569 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2570 is the simpliest way of generating a call. The difference between
2571 __m68k_read_tp() and libcall is that the result is returned in D0
2572 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2573 which temporarily switches returning the result to A0. */
2575 /* Emit the call sequence. */
2576 m68k_libcall_value_in_a0_p
= true;
2577 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2579 m68k_libcall_value_in_a0_p
= false;
2580 insns
= get_insns ();
2583 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2584 share the m68k_read_tp result with other IE/LE model accesses. */
2585 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2587 gcc_assert (can_create_pseudo_p ());
2588 dest
= gen_reg_rtx (Pmode
);
2589 emit_libcall_block (insns
, dest
, a0
, eqv
);
2594 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2595 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2599 m68k_legitimize_tls_address (rtx orig
)
2601 switch (SYMBOL_REF_TLS_MODEL (orig
))
2603 case TLS_MODEL_GLOBAL_DYNAMIC
:
2604 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2607 case TLS_MODEL_LOCAL_DYNAMIC
:
2613 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2614 share the LDM result with other LD model accesses. */
2615 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2618 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2620 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2622 if (can_create_pseudo_p ())
2623 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2629 case TLS_MODEL_INITIAL_EXEC
:
2634 a0
= m68k_call_m68k_read_tp ();
2636 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2637 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2639 if (can_create_pseudo_p ())
2640 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2646 case TLS_MODEL_LOCAL_EXEC
:
2651 a0
= m68k_call_m68k_read_tp ();
2653 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2655 if (can_create_pseudo_p ())
2656 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2669 /* Return true if X is a TLS symbol. */
2672 m68k_tls_symbol_p (rtx x
)
2674 if (!TARGET_HAVE_TLS
)
2677 if (GET_CODE (x
) != SYMBOL_REF
)
2680 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2683 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2684 though illegitimate one.
2685 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2688 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2690 if (!TARGET_HAVE_TLS
)
2695 subrtx_var_iterator::array_type array
;
2696 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
2700 /* Note: this is not the same as m68k_tls_symbol_p. */
2701 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0)
2704 /* Don't recurse into legitimate TLS references. */
2705 if (m68k_tls_reference_p (x
, true))
2706 iter
.skip_subrtxes ();
2712 enum m68k_reloc reloc
= RELOC_GOT
;
2714 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2715 && TLS_RELOC_P (reloc
));
2721 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2723 /* Return the type of move that should be used for integer I. */
2726 m68k_const_method (HOST_WIDE_INT i
)
2733 /* The ColdFire doesn't have byte or word operations. */
2734 /* FIXME: This may not be useful for the m68060 either. */
2735 if (!TARGET_COLDFIRE
)
2737 /* if -256 < N < 256 but N is not in range for a moveq
2738 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2739 if (USE_MOVQ (i
^ 0xff))
2741 /* Likewise, try with not.w */
2742 if (USE_MOVQ (i
^ 0xffff))
2744 /* This is the only value where neg.w is useful */
2749 /* Try also with swap. */
2751 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2756 /* Try using MVZ/MVS with an immediate value to load constants. */
2757 if (i
>= 0 && i
<= 65535)
2759 if (i
>= -32768 && i
<= 32767)
2763 /* Otherwise, use move.l */
2767 /* Return the cost of moving constant I into a data register. */
2770 const_int_cost (HOST_WIDE_INT i
)
2772 switch (m68k_const_method (i
))
2775 /* Constants between -128 and 127 are cheap due to moveq. */
2783 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2793 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2794 int *total
, bool speed ATTRIBUTE_UNUSED
)
2799 /* Constant zero is super cheap due to clr instruction. */
2800 if (x
== const0_rtx
)
2803 *total
= const_int_cost (INTVAL (x
));
2813 /* Make 0.0 cheaper than other floating constants to
2814 encourage creating tstsf and tstdf insns. */
2815 if (outer_code
== COMPARE
2816 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2822 /* These are vaguely right for a 68020. */
2823 /* The costs for long multiply have been adjusted to work properly
2824 in synth_mult on the 68020, relative to an average of the time
2825 for add and the time for shift, taking away a little more because
2826 sometimes move insns are needed. */
2827 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2832 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2833 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2835 : TARGET_COLDFIRE ? 3 : 13)
2840 : TUNE_68000_10 ? 5 \
2841 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2842 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2844 : TARGET_COLDFIRE ? 2 : 8)
2847 (TARGET_CF_HWDIV ? 11 \
2848 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2851 /* An lea costs about three times as much as a simple add. */
2852 if (GET_MODE (x
) == SImode
2853 && GET_CODE (XEXP (x
, 1)) == REG
2854 && GET_CODE (XEXP (x
, 0)) == MULT
2855 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2856 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2857 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2858 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2859 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2861 /* lea an@(dx:l:i),am */
2862 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2872 *total
= COSTS_N_INSNS(1);
2877 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2879 if (INTVAL (XEXP (x
, 1)) < 16)
2880 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2882 /* We're using clrw + swap for these cases. */
2883 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2886 *total
= COSTS_N_INSNS (10); /* Worst case. */
2889 /* A shift by a big integer takes an extra instruction. */
2890 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2891 && (INTVAL (XEXP (x
, 1)) == 16))
2893 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2896 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2897 && !(INTVAL (XEXP (x
, 1)) > 0
2898 && INTVAL (XEXP (x
, 1)) <= 8))
2900 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2906 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2907 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2908 && GET_MODE (x
) == SImode
)
2909 *total
= COSTS_N_INSNS (MULW_COST
);
2910 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2911 *total
= COSTS_N_INSNS (MULW_COST
);
2913 *total
= COSTS_N_INSNS (MULL_COST
);
2920 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2921 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2922 else if (TARGET_CF_HWDIV
)
2923 *total
= COSTS_N_INSNS (18);
2925 *total
= COSTS_N_INSNS (43); /* div.l */
2929 if (outer_code
== COMPARE
)
2938 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2942 output_move_const_into_data_reg (rtx
*operands
)
2946 i
= INTVAL (operands
[1]);
2947 switch (m68k_const_method (i
))
2950 return "mvzw %1,%0";
2952 return "mvsw %1,%0";
2954 return "moveq %1,%0";
2957 operands
[1] = GEN_INT (i
^ 0xff);
2958 return "moveq %1,%0\n\tnot%.b %0";
2961 operands
[1] = GEN_INT (i
^ 0xffff);
2962 return "moveq %1,%0\n\tnot%.w %0";
2965 return "moveq #-128,%0\n\tneg%.w %0";
2970 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2971 return "moveq %1,%0\n\tswap %0";
2974 return "move%.l %1,%0";
2980 /* Return true if I can be handled by ISA B's mov3q instruction. */
2983 valid_mov3q_const (HOST_WIDE_INT i
)
2985 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2988 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2989 I is the value of OPERANDS[1]. */
2992 output_move_simode_const (rtx
*operands
)
2998 src
= INTVAL (operands
[1]);
3000 && (DATA_REG_P (dest
) || MEM_P (dest
))
3001 /* clr insns on 68000 read before writing. */
3002 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3003 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
3005 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
3006 return "mov3q%.l %1,%0";
3007 else if (src
== 0 && ADDRESS_REG_P (dest
))
3008 return "sub%.l %0,%0";
3009 else if (DATA_REG_P (dest
))
3010 return output_move_const_into_data_reg (operands
);
3011 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3013 if (valid_mov3q_const (src
))
3014 return "mov3q%.l %1,%0";
3015 return "move%.w %1,%0";
3017 else if (MEM_P (dest
)
3018 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3019 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3020 && IN_RANGE (src
, -0x8000, 0x7fff))
3022 if (valid_mov3q_const (src
))
3023 return "mov3q%.l %1,%-";
3026 return "move%.l %1,%0";
3030 output_move_simode (rtx
*operands
)
3032 if (GET_CODE (operands
[1]) == CONST_INT
)
3033 return output_move_simode_const (operands
);
3034 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3035 || GET_CODE (operands
[1]) == CONST
)
3036 && push_operand (operands
[0], SImode
))
3038 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3039 || GET_CODE (operands
[1]) == CONST
)
3040 && ADDRESS_REG_P (operands
[0]))
3041 return "lea %a1,%0";
3042 return "move%.l %1,%0";
3046 output_move_himode (rtx
*operands
)
3048 if (GET_CODE (operands
[1]) == CONST_INT
)
3050 if (operands
[1] == const0_rtx
3051 && (DATA_REG_P (operands
[0])
3052 || GET_CODE (operands
[0]) == MEM
)
3053 /* clr insns on 68000 read before writing. */
3054 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3055 || !(GET_CODE (operands
[0]) == MEM
3056 && MEM_VOLATILE_P (operands
[0]))))
3058 else if (operands
[1] == const0_rtx
3059 && ADDRESS_REG_P (operands
[0]))
3060 return "sub%.l %0,%0";
3061 else if (DATA_REG_P (operands
[0])
3062 && INTVAL (operands
[1]) < 128
3063 && INTVAL (operands
[1]) >= -128)
3064 return "moveq %1,%0";
3065 else if (INTVAL (operands
[1]) < 0x8000
3066 && INTVAL (operands
[1]) >= -0x8000)
3067 return "move%.w %1,%0";
3069 else if (CONSTANT_P (operands
[1]))
3070 return "move%.l %1,%0";
3071 return "move%.w %1,%0";
3075 output_move_qimode (rtx
*operands
)
3077 /* 68k family always modifies the stack pointer by at least 2, even for
3078 byte pushes. The 5200 (ColdFire) does not do this. */
3080 /* This case is generated by pushqi1 pattern now. */
3081 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3082 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3083 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3084 && ! ADDRESS_REG_P (operands
[1])
3085 && ! TARGET_COLDFIRE
));
3087 /* clr and st insns on 68000 read before writing. */
3088 if (!ADDRESS_REG_P (operands
[0])
3089 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3090 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3092 if (operands
[1] == const0_rtx
)
3094 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3095 && GET_CODE (operands
[1]) == CONST_INT
3096 && (INTVAL (operands
[1]) & 255) == 255)
3102 if (GET_CODE (operands
[1]) == CONST_INT
3103 && DATA_REG_P (operands
[0])
3104 && INTVAL (operands
[1]) < 128
3105 && INTVAL (operands
[1]) >= -128)
3106 return "moveq %1,%0";
3107 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3108 return "sub%.l %0,%0";
3109 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3110 return "move%.l %1,%0";
3111 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3112 from address registers. */
3113 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3114 return "move%.w %1,%0";
3115 return "move%.b %1,%0";
3119 output_move_stricthi (rtx
*operands
)
3121 if (operands
[1] == const0_rtx
3122 /* clr insns on 68000 read before writing. */
3123 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3124 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3126 return "move%.w %1,%0";
3130 output_move_strictqi (rtx
*operands
)
3132 if (operands
[1] == const0_rtx
3133 /* clr insns on 68000 read before writing. */
3134 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3135 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3137 return "move%.b %1,%0";
3140 /* Return the best assembler insn template
3141 for moving operands[1] into operands[0] as a fullword. */
3144 singlemove_string (rtx
*operands
)
3146 if (GET_CODE (operands
[1]) == CONST_INT
)
3147 return output_move_simode_const (operands
);
3148 return "move%.l %1,%0";
3152 /* Output assembler or rtl code to perform a doubleword move insn
3153 with operands OPERANDS.
3154 Pointers to 3 helper functions should be specified:
3155 HANDLE_REG_ADJUST to adjust a register by a small value,
3156 HANDLE_COMPADR to compute an address and
3157 HANDLE_MOVSI to move 4 bytes. */
3160 handle_move_double (rtx operands
[2],
3161 void (*handle_reg_adjust
) (rtx
, int),
3162 void (*handle_compadr
) (rtx
[2]),
3163 void (*handle_movsi
) (rtx
[2]))
3167 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3172 rtx addreg0
= 0, addreg1
= 0;
3173 int dest_overlapped_low
= 0;
3174 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3179 /* First classify both operands. */
3181 if (REG_P (operands
[0]))
3183 else if (offsettable_memref_p (operands
[0]))
3185 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3187 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3189 else if (GET_CODE (operands
[0]) == MEM
)
3194 if (REG_P (operands
[1]))
3196 else if (CONSTANT_P (operands
[1]))
3198 else if (offsettable_memref_p (operands
[1]))
3200 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3202 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3204 else if (GET_CODE (operands
[1]) == MEM
)
3209 /* Check for the cases that the operand constraints are not supposed
3210 to allow to happen. Generating code for these cases is
3212 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3214 /* If one operand is decrementing and one is incrementing
3215 decrement the former register explicitly
3216 and change that operand into ordinary indexing. */
3218 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3220 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3222 handle_reg_adjust (operands
[0], -size
);
3224 if (GET_MODE (operands
[1]) == XFmode
)
3225 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3226 else if (GET_MODE (operands
[0]) == DFmode
)
3227 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3229 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3232 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3234 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3236 handle_reg_adjust (operands
[1], -size
);
3238 if (GET_MODE (operands
[1]) == XFmode
)
3239 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3240 else if (GET_MODE (operands
[1]) == DFmode
)
3241 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3243 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3247 /* If an operand is an unoffsettable memory ref, find a register
3248 we can increment temporarily to make it refer to the second word. */
3250 if (optype0
== MEMOP
)
3251 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3253 if (optype1
== MEMOP
)
3254 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3256 /* Ok, we can do one word at a time.
3257 Normally we do the low-numbered word first,
3258 but if either operand is autodecrementing then we
3259 do the high-numbered word first.
3261 In either case, set up in LATEHALF the operands to use
3262 for the high-numbered word and in some cases alter the
3263 operands in OPERANDS to be suitable for the low-numbered word. */
3267 if (optype0
== REGOP
)
3269 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3270 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3272 else if (optype0
== OFFSOP
)
3274 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3275 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3279 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3280 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3283 if (optype1
== REGOP
)
3285 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3286 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3288 else if (optype1
== OFFSOP
)
3290 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3291 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3293 else if (optype1
== CNSTOP
)
3295 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3300 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
3301 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
3302 operands
[1] = GEN_INT (l
[0]);
3303 middlehalf
[1] = GEN_INT (l
[1]);
3304 latehalf
[1] = GEN_INT (l
[2]);
3308 /* No non-CONST_DOUBLE constant should ever appear
3310 gcc_assert (!CONSTANT_P (operands
[1]));
3315 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3316 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3320 /* size is not 12: */
3322 if (optype0
== REGOP
)
3323 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3324 else if (optype0
== OFFSOP
)
3325 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3327 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3329 if (optype1
== REGOP
)
3330 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3331 else if (optype1
== OFFSOP
)
3332 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3333 else if (optype1
== CNSTOP
)
3334 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3336 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3339 /* If insn is effectively movd N(REG),-(REG) then we will do the high
3340 word first. We should use the adjusted operand 1 (which is N+4(REG))
3341 for the low word as well, to compensate for the first decrement of
3343 if (optype0
== PUSHOP
3344 && reg_overlap_mentioned_p (XEXP (XEXP (operands
[0], 0), 0), operands
[1]))
3345 operands
[1] = middlehalf
[1] = latehalf
[1];
3347 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3348 if the upper part of reg N does not appear in the MEM, arrange to
3349 emit the move late-half first. Otherwise, compute the MEM address
3350 into the upper part of N and use that as a pointer to the memory
3352 if (optype0
== REGOP
3353 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3355 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3357 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3358 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3360 /* If both halves of dest are used in the src memory address,
3361 compute the address into latehalf of dest.
3362 Note that this can't happen if the dest is two data regs. */
3364 xops
[0] = latehalf
[0];
3365 xops
[1] = XEXP (operands
[1], 0);
3367 handle_compadr (xops
);
3368 if (GET_MODE (operands
[1]) == XFmode
)
3370 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3371 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3372 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3376 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3377 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3381 && reg_overlap_mentioned_p (middlehalf
[0],
3382 XEXP (operands
[1], 0)))
3384 /* Check for two regs used by both source and dest.
3385 Note that this can't happen if the dest is all data regs.
3386 It can happen if the dest is d6, d7, a0.
3387 But in that case, latehalf is an addr reg, so
3388 the code at compadr does ok. */
3390 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3391 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3394 /* JRV says this can't happen: */
3395 gcc_assert (!addreg0
&& !addreg1
);
3397 /* Only the middle reg conflicts; simply put it last. */
3398 handle_movsi (operands
);
3399 handle_movsi (latehalf
);
3400 handle_movsi (middlehalf
);
3404 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3405 /* If the low half of dest is mentioned in the source memory
3406 address, the arrange to emit the move late half first. */
3407 dest_overlapped_low
= 1;
3410 /* If one or both operands autodecrementing,
3411 do the two words, high-numbered first. */
3413 /* Likewise, the first move would clobber the source of the second one,
3414 do them in the other order. This happens only for registers;
3415 such overlap can't happen in memory unless the user explicitly
3416 sets it up, and that is an undefined circumstance. */
3418 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3419 || (optype0
== REGOP
&& optype1
== REGOP
3420 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3421 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3422 || dest_overlapped_low
)
3424 /* Make any unoffsettable addresses point at high-numbered word. */
3426 handle_reg_adjust (addreg0
, size
- 4);
3428 handle_reg_adjust (addreg1
, size
- 4);
3431 handle_movsi (latehalf
);
3433 /* Undo the adds we just did. */
3435 handle_reg_adjust (addreg0
, -4);
3437 handle_reg_adjust (addreg1
, -4);
3441 handle_movsi (middlehalf
);
3444 handle_reg_adjust (addreg0
, -4);
3446 handle_reg_adjust (addreg1
, -4);
3449 /* Do low-numbered word. */
3451 handle_movsi (operands
);
3455 /* Normal case: do the two words, low-numbered first. */
3457 m68k_final_prescan_insn (NULL
, operands
, 2);
3458 handle_movsi (operands
);
3460 /* Do the middle one of the three words for long double */
3464 handle_reg_adjust (addreg0
, 4);
3466 handle_reg_adjust (addreg1
, 4);
3468 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3469 handle_movsi (middlehalf
);
3472 /* Make any unoffsettable addresses point at high-numbered word. */
3474 handle_reg_adjust (addreg0
, 4);
3476 handle_reg_adjust (addreg1
, 4);
3479 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3480 handle_movsi (latehalf
);
3482 /* Undo the adds we just did. */
3484 handle_reg_adjust (addreg0
, -(size
- 4));
3486 handle_reg_adjust (addreg1
, -(size
- 4));
3491 /* Output assembler code to adjust REG by N. */
3493 output_reg_adjust (rtx reg
, int n
)
3497 gcc_assert (GET_MODE (reg
) == SImode
3498 && -12 <= n
&& n
!= 0 && n
<= 12);
3503 s
= "add%.l #12,%0";
3507 s
= "addq%.l #8,%0";
3511 s
= "addq%.l #4,%0";
3515 s
= "sub%.l #12,%0";
3519 s
= "subq%.l #8,%0";
3523 s
= "subq%.l #4,%0";
3531 output_asm_insn (s
, ®
);
3534 /* Emit rtl code to adjust REG by N. */
3536 emit_reg_adjust (rtx reg1
, int n
)
3540 gcc_assert (GET_MODE (reg1
) == SImode
3541 && -12 <= n
&& n
!= 0 && n
<= 12);
3543 reg1
= copy_rtx (reg1
);
3544 reg2
= copy_rtx (reg1
);
3547 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3549 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3554 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3556 output_compadr (rtx operands
[2])
3558 output_asm_insn ("lea %a1,%0", operands
);
3561 /* Output the best assembler insn for moving operands[1] into operands[0]
3564 output_movsi (rtx operands
[2])
3566 output_asm_insn (singlemove_string (operands
), operands
);
3569 /* Copy OP and change its mode to MODE. */
3571 copy_operand (rtx op
, machine_mode mode
)
3573 /* ??? This looks really ugly. There must be a better way
3574 to change a mode on the operand. */
3575 if (GET_MODE (op
) != VOIDmode
)
3578 op
= gen_rtx_REG (mode
, REGNO (op
));
3582 PUT_MODE (op
, mode
);
3589 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3591 emit_movsi (rtx operands
[2])
3593 operands
[0] = copy_operand (operands
[0], SImode
);
3594 operands
[1] = copy_operand (operands
[1], SImode
);
3596 emit_insn (gen_movsi (operands
[0], operands
[1]));
3599 /* Output assembler code to perform a doubleword move insn
3600 with operands OPERANDS. */
3602 output_move_double (rtx
*operands
)
3604 handle_move_double (operands
,
3605 output_reg_adjust
, output_compadr
, output_movsi
);
3610 /* Output rtl code to perform a doubleword move insn
3611 with operands OPERANDS. */
3613 m68k_emit_move_double (rtx operands
[2])
3615 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3618 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3619 new rtx with the correct mode. */
3622 force_mode (machine_mode mode
, rtx orig
)
3624 if (mode
== GET_MODE (orig
))
3627 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3630 return gen_rtx_REG (mode
, REGNO (orig
));
3634 fp_reg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
3636 return reg_renumber
&& FP_REG_P (op
);
3639 /* Emit insns to move operands[1] into operands[0].
3641 Return 1 if we have written out everything that needs to be done to
3642 do the move. Otherwise, return 0 and the caller will emit the move
3645 Note SCRATCH_REG may not be in the proper mode depending on how it
3646 will be used. This routine is responsible for creating a new copy
3647 of SCRATCH_REG in the proper mode. */
3650 emit_move_sequence (rtx
*operands
, machine_mode mode
, rtx scratch_reg
)
3652 register rtx operand0
= operands
[0];
3653 register rtx operand1
= operands
[1];
3657 && reload_in_progress
&& GET_CODE (operand0
) == REG
3658 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3659 operand0
= reg_equiv_mem (REGNO (operand0
));
3660 else if (scratch_reg
3661 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3662 && GET_CODE (SUBREG_REG (operand0
)) == REG
3663 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3665 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3666 the code which tracks sets/uses for delete_output_reload. */
3667 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3668 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3669 SUBREG_BYTE (operand0
));
3670 operand0
= alter_subreg (&temp
, true);
3674 && reload_in_progress
&& GET_CODE (operand1
) == REG
3675 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3676 operand1
= reg_equiv_mem (REGNO (operand1
));
3677 else if (scratch_reg
3678 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3679 && GET_CODE (SUBREG_REG (operand1
)) == REG
3680 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3682 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3683 the code which tracks sets/uses for delete_output_reload. */
3684 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3685 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3686 SUBREG_BYTE (operand1
));
3687 operand1
= alter_subreg (&temp
, true);
3690 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3691 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3692 != XEXP (operand0
, 0)))
3693 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3694 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3695 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3696 != XEXP (operand1
, 0)))
3697 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3699 /* Handle secondary reloads for loads/stores of FP registers where
3700 the address is symbolic by using the scratch register */
3701 if (fp_reg_operand (operand0
, mode
)
3702 && ((GET_CODE (operand1
) == MEM
3703 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3704 || ((GET_CODE (operand1
) == SUBREG
3705 && GET_CODE (XEXP (operand1
, 0)) == MEM
3706 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3709 if (GET_CODE (operand1
) == SUBREG
)
3710 operand1
= XEXP (operand1
, 0);
3712 /* SCRATCH_REG will hold an address. We want
3713 it in SImode regardless of what mode it was originally given
3715 scratch_reg
= force_mode (SImode
, scratch_reg
);
3717 /* D might not fit in 14 bits either; for such cases load D into
3719 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3721 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3722 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3724 XEXP (XEXP (operand1
, 0), 0),
3728 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3729 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
3730 gen_rtx_MEM (mode
, scratch_reg
)));
3733 else if (fp_reg_operand (operand1
, mode
)
3734 && ((GET_CODE (operand0
) == MEM
3735 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3736 || ((GET_CODE (operand0
) == SUBREG
)
3737 && GET_CODE (XEXP (operand0
, 0)) == MEM
3738 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3741 if (GET_CODE (operand0
) == SUBREG
)
3742 operand0
= XEXP (operand0
, 0);
3744 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3745 it in SIMODE regardless of what mode it was originally given
3747 scratch_reg
= force_mode (SImode
, scratch_reg
);
3749 /* D might not fit in 14 bits either; for such cases load D into
3751 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3753 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3754 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3757 XEXP (XEXP (operand0
, 0),
3762 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3763 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
3767 /* Handle secondary reloads for loads of FP registers from constant
3768 expressions by forcing the constant into memory.
3770 use scratch_reg to hold the address of the memory location.
3772 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3773 NO_REGS when presented with a const_int and an register class
3774 containing only FP registers. Doing so unfortunately creates
3775 more problems than it solves. Fix this for 2.5. */
3776 else if (fp_reg_operand (operand0
, mode
)
3777 && CONSTANT_P (operand1
)
3782 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3783 it in SIMODE regardless of what mode it was originally given
3785 scratch_reg
= force_mode (SImode
, scratch_reg
);
3787 /* Force the constant into memory and put the address of the
3788 memory location into scratch_reg. */
3789 xoperands
[0] = scratch_reg
;
3790 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3791 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
3793 /* Now load the destination register. */
3794 emit_insn (gen_rtx_SET (mode
, operand0
,
3795 gen_rtx_MEM (mode
, scratch_reg
)));
3799 /* Now have insn-emit do whatever it normally does. */
3803 /* Split one or more DImode RTL references into pairs of SImode
3804 references. The RTL can be REG, offsettable MEM, integer constant, or
3805 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3806 split and "num" is its length. lo_half and hi_half are output arrays
3807 that parallel "operands". */
3810 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3814 rtx op
= operands
[num
];
3816 /* simplify_subreg refuses to split volatile memory addresses,
3817 but we still have to handle it. */
3818 if (GET_CODE (op
) == MEM
)
3820 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3821 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3825 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3826 GET_MODE (op
) == VOIDmode
3827 ? DImode
: GET_MODE (op
), 4);
3828 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3829 GET_MODE (op
) == VOIDmode
3830 ? DImode
: GET_MODE (op
), 0);
3835 /* Split X into a base and a constant offset, storing them in *BASE
3836 and *OFFSET respectively. */
3839 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3842 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3844 *offset
+= INTVAL (XEXP (x
, 1));
3850 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3851 instruction. STORE_P says whether the move is a load or store.
3853 If the instruction uses post-increment or pre-decrement addressing,
3854 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3855 adjustment. This adjustment will be made by the first element of
3856 PARALLEL, with the loads or stores starting at element 1. If the
3857 instruction does not use post-increment or pre-decrement addressing,
3858 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3859 start at element 0. */
3862 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3863 HOST_WIDE_INT automod_offset
, bool store_p
)
3865 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3866 HOST_WIDE_INT offset
, mem_offset
;
3868 enum reg_class rclass
;
3870 len
= XVECLEN (pattern
, 0);
3871 first
= (automod_base
!= NULL
);
3875 /* Stores must be pre-decrement and loads must be post-increment. */
3876 if (store_p
!= (automod_offset
< 0))
3879 /* Work out the base and offset for lowest memory location. */
3880 base
= automod_base
;
3881 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3885 /* Allow any valid base and offset in the first access. */
3892 for (i
= first
; i
< len
; i
++)
3894 /* We need a plain SET. */
3895 set
= XVECEXP (pattern
, 0, i
);
3896 if (GET_CODE (set
) != SET
)
3899 /* Check that we have a memory location... */
3900 mem
= XEXP (set
, !store_p
);
3901 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3904 /* ...with the right address. */
3907 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3908 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3909 There are no mode restrictions for 680x0 besides the
3910 automodification rules enforced above. */
3912 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3917 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3918 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3922 /* Check that we have a register of the required mode and class. */
3923 reg
= XEXP (set
, store_p
);
3925 || !HARD_REGISTER_P (reg
)
3926 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3931 /* The register must belong to RCLASS and have a higher number
3932 than the register in the previous SET. */
3933 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3934 || REGNO (last_reg
) >= REGNO (reg
))
3939 /* Work out which register class we need. */
3940 if (INT_REGNO_P (REGNO (reg
)))
3941 rclass
= GENERAL_REGS
;
3942 else if (FP_REGNO_P (REGNO (reg
)))
3949 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3952 /* If we have an automodification, check whether the final offset is OK. */
3953 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3956 /* Reject unprofitable cases. */
3957 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3963 /* Return the assembly code template for a movem or fmovem instruction
3964 whose pattern is given by PATTERN. Store the template's operands
3967 If the instruction uses post-increment or pre-decrement addressing,
3968 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3969 is true if this is a store instruction. */
3972 m68k_output_movem (rtx
*operands
, rtx pattern
,
3973 HOST_WIDE_INT automod_offset
, bool store_p
)
3978 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3980 first
= (automod_offset
!= 0);
3981 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3983 /* When using movem with pre-decrement addressing, register X + D0_REG
3984 is controlled by bit 15 - X. For all other addressing modes,
3985 register X + D0_REG is controlled by bit X. Confusingly, the
3986 register mask for fmovem is in the opposite order to that for
3990 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3991 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3992 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3993 if (automod_offset
< 0)
3995 if (FP_REGNO_P (regno
))
3996 mask
|= 1 << (regno
- FP0_REG
);
3998 mask
|= 1 << (15 - (regno
- D0_REG
));
4002 if (FP_REGNO_P (regno
))
4003 mask
|= 1 << (7 - (regno
- FP0_REG
));
4005 mask
|= 1 << (regno
- D0_REG
);
4010 if (automod_offset
== 0)
4011 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4012 else if (automod_offset
< 0)
4013 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4015 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4016 operands
[1] = GEN_INT (mask
);
4017 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4020 return "fmovem %1,%a0";
4022 return "fmovem %a0,%1";
4027 return "movem%.l %1,%a0";
4029 return "movem%.l %a0,%1";
4033 /* Return a REG that occurs in ADDR with coefficient 1.
4034 ADDR can be effectively incremented by incrementing REG. */
4037 find_addr_reg (rtx addr
)
4039 while (GET_CODE (addr
) == PLUS
)
4041 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4042 addr
= XEXP (addr
, 0);
4043 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4044 addr
= XEXP (addr
, 1);
4045 else if (CONSTANT_P (XEXP (addr
, 0)))
4046 addr
= XEXP (addr
, 1);
4047 else if (CONSTANT_P (XEXP (addr
, 1)))
4048 addr
= XEXP (addr
, 0);
4052 gcc_assert (GET_CODE (addr
) == REG
);
4056 /* Output assembler code to perform a 32-bit 3-operand add. */
4059 output_addsi3 (rtx
*operands
)
4061 if (! operands_match_p (operands
[0], operands
[1]))
4063 if (!ADDRESS_REG_P (operands
[1]))
4065 rtx tmp
= operands
[1];
4067 operands
[1] = operands
[2];
4071 /* These insns can result from reloads to access
4072 stack slots over 64k from the frame pointer. */
4073 if (GET_CODE (operands
[2]) == CONST_INT
4074 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4075 return "move%.l %2,%0\n\tadd%.l %1,%0";
4076 if (GET_CODE (operands
[2]) == REG
)
4077 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4078 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4080 if (GET_CODE (operands
[2]) == CONST_INT
)
4082 if (INTVAL (operands
[2]) > 0
4083 && INTVAL (operands
[2]) <= 8)
4084 return "addq%.l %2,%0";
4085 if (INTVAL (operands
[2]) < 0
4086 && INTVAL (operands
[2]) >= -8)
4088 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4089 return "subq%.l %2,%0";
4091 /* On the CPU32 it is faster to use two addql instructions to
4092 add a small integer (8 < N <= 16) to a register.
4093 Likewise for subql. */
4094 if (TUNE_CPU32
&& REG_P (operands
[0]))
4096 if (INTVAL (operands
[2]) > 8
4097 && INTVAL (operands
[2]) <= 16)
4099 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4100 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4102 if (INTVAL (operands
[2]) < -8
4103 && INTVAL (operands
[2]) >= -16)
4105 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4106 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4109 if (ADDRESS_REG_P (operands
[0])
4110 && INTVAL (operands
[2]) >= -0x8000
4111 && INTVAL (operands
[2]) < 0x8000)
4114 return "add%.w %2,%0";
4116 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4119 return "add%.l %2,%0";
4122 /* Store in cc_status the expressions that the condition codes will
4123 describe after execution of an instruction whose pattern is EXP.
4124 Do not alter them if the instruction would not alter the cc's. */
4126 /* On the 68000, all the insns to store in an address register fail to
4127 set the cc's. However, in some cases these instructions can make it
4128 possibly invalid to use the saved cc's. In those cases we clear out
4129 some or all of the saved cc's so they won't be used. */
4132 notice_update_cc (rtx exp
, rtx insn
)
4134 if (GET_CODE (exp
) == SET
)
4136 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4138 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4140 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4141 cc_status
.value1
= 0;
4142 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4143 cc_status
.value2
= 0;
4145 /* fmoves to memory or data registers do not set the condition
4146 codes. Normal moves _do_ set the condition codes, but not in
4147 a way that is appropriate for comparison with 0, because -0.0
4148 would be treated as a negative nonzero number. Note that it
4149 isn't appropriate to conditionalize this restriction on
4150 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4151 we care about the difference between -0.0 and +0.0. */
4152 else if (!FP_REG_P (SET_DEST (exp
))
4153 && SET_DEST (exp
) != cc0_rtx
4154 && (FP_REG_P (SET_SRC (exp
))
4155 || GET_CODE (SET_SRC (exp
)) == FIX
4156 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4158 /* A pair of move insns doesn't produce a useful overall cc. */
4159 else if (!FP_REG_P (SET_DEST (exp
))
4160 && !FP_REG_P (SET_SRC (exp
))
4161 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4162 && (GET_CODE (SET_SRC (exp
)) == REG
4163 || GET_CODE (SET_SRC (exp
)) == MEM
4164 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4166 else if (SET_DEST (exp
) != pc_rtx
)
4168 cc_status
.flags
= 0;
4169 cc_status
.value1
= SET_DEST (exp
);
4170 cc_status
.value2
= SET_SRC (exp
);
4173 else if (GET_CODE (exp
) == PARALLEL
4174 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4176 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4177 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4179 if (ADDRESS_REG_P (dest
))
4181 else if (dest
!= pc_rtx
)
4183 cc_status
.flags
= 0;
4184 cc_status
.value1
= dest
;
4185 cc_status
.value2
= src
;
4190 if (cc_status
.value2
!= 0
4191 && ADDRESS_REG_P (cc_status
.value2
)
4192 && GET_MODE (cc_status
.value2
) == QImode
)
4194 if (cc_status
.value2
!= 0)
4195 switch (GET_CODE (cc_status
.value2
))
4197 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4198 case ROTATE
: case ROTATERT
:
4199 /* These instructions always clear the overflow bit, and set
4200 the carry to the bit shifted out. */
4201 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4204 case PLUS
: case MINUS
: case MULT
:
4205 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4206 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4207 cc_status
.flags
|= CC_NO_OVERFLOW
;
4210 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4211 ends with a move insn moving r2 in r2's mode.
4212 Thus, the cc's are set for r2.
4213 This can set N bit spuriously. */
4214 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4219 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4221 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4222 cc_status
.value2
= 0;
4223 /* Check for PRE_DEC in dest modifying a register used in src. */
4224 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
4225 && GET_CODE (XEXP (cc_status
.value1
, 0)) == PRE_DEC
4227 && reg_overlap_mentioned_p (XEXP (XEXP (cc_status
.value1
, 0), 0),
4229 cc_status
.value2
= 0;
4230 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4231 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4232 cc_status
.flags
= CC_IN_68881
;
4233 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4234 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4236 cc_status
.flags
= CC_IN_68881
;
4237 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4238 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4239 cc_status
.flags
|= CC_REVERSED
;
4244 output_move_const_double (rtx
*operands
)
4246 int code
= standard_68881_constant_p (operands
[1]);
4250 static char buf
[40];
4252 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4255 return "fmove%.d %1,%0";
4259 output_move_const_single (rtx
*operands
)
4261 int code
= standard_68881_constant_p (operands
[1]);
4265 static char buf
[40];
4267 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4270 return "fmove%.s %f1,%0";
4273 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4274 from the "fmovecr" instruction.
4275 The value, anded with 0xff, gives the code to use in fmovecr
4276 to get the desired constant. */
4278 /* This code has been fixed for cross-compilation. */
4280 static int inited_68881_table
= 0;
4282 static const char *const strings_68881
[7] = {
4292 static const int codes_68881
[7] = {
4302 REAL_VALUE_TYPE values_68881
[7];
4304 /* Set up values_68881 array by converting the decimal values
4305 strings_68881 to binary. */
4308 init_68881_table (void)
4315 for (i
= 0; i
< 7; i
++)
4319 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4320 values_68881
[i
] = r
;
4322 inited_68881_table
= 1;
4326 standard_68881_constant_p (rtx x
)
4331 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4332 used at all on those chips. */
4336 if (! inited_68881_table
)
4337 init_68881_table ();
4339 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4341 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
4343 for (i
= 0; i
< 6; i
++)
4345 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
4346 return (codes_68881
[i
]);
4349 if (GET_MODE (x
) == SFmode
)
4352 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
4353 return (codes_68881
[6]);
4355 /* larger powers of ten in the constants ram are not used
4356 because they are not equal to a `double' C constant. */
4360 /* If X is a floating-point constant, return the logarithm of X base 2,
4361 or 0 if X is not a power of 2. */
4364 floating_exact_log2 (rtx x
)
4366 REAL_VALUE_TYPE r
, r1
;
4369 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4371 if (REAL_VALUES_LESS (r
, dconst1
))
4374 exp
= real_exponent (&r
);
4375 real_2expN (&r1
, exp
, DFmode
);
4376 if (REAL_VALUES_EQUAL (r1
, r
))
4382 /* A C compound statement to output to stdio stream STREAM the
4383 assembler syntax for an instruction operand X. X is an RTL
4386 CODE is a value that can be used to specify one of several ways
4387 of printing the operand. It is used when identical operands
4388 must be printed differently depending on the context. CODE
4389 comes from the `%' specification that was used to request
4390 printing of the operand. If the specification was just `%DIGIT'
4391 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4392 is the ASCII code for LTR.
4394 If X is a register, this macro should print the register's name.
4395 The names can be found in an array `reg_names' whose type is
4396 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4398 When the machine description has a specification `%PUNCT' (a `%'
4399 followed by a punctuation character), this macro is called with
4400 a null pointer for X and the punctuation character for CODE.
4402 The m68k specific codes are:
4404 '.' for dot needed in Motorola-style opcode names.
4405 '-' for an operand pushing on the stack:
4406 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4407 '+' for an operand pushing on the stack:
4408 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4409 '@' for a reference to the top word on the stack:
4410 sp@, (sp) or (%sp) depending on the style of syntax.
4411 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4412 but & in SGS syntax).
4413 '!' for the cc register (used in an `and to cc' insn).
4414 '$' for the letter `s' in an op code, but only on the 68040.
4415 '&' for the letter `d' in an op code, but only on the 68040.
4416 '/' for register prefix needed by longlong.h.
4417 '?' for m68k_library_id_string
4419 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4420 'd' to force memory addressing to be absolute, not relative.
4421 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4422 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4423 or print pair of registers as rx:ry.
4424 'p' print an address with @PLTPC attached, but only if the operand
4425 is not locally-bound. */
4428 print_operand (FILE *file
, rtx op
, int letter
)
4433 fprintf (file
, ".");
4435 else if (letter
== '#')
4436 asm_fprintf (file
, "%I");
4437 else if (letter
== '-')
4438 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4439 else if (letter
== '+')
4440 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4441 else if (letter
== '@')
4442 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4443 else if (letter
== '!')
4444 asm_fprintf (file
, "%Rfpcr");
4445 else if (letter
== '$')
4448 fprintf (file
, "s");
4450 else if (letter
== '&')
4453 fprintf (file
, "d");
4455 else if (letter
== '/')
4456 asm_fprintf (file
, "%R");
4457 else if (letter
== '?')
4458 asm_fprintf (file
, m68k_library_id_string
);
4459 else if (letter
== 'p')
4461 output_addr_const (file
, op
);
4462 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4463 fprintf (file
, "@PLTPC");
4465 else if (GET_CODE (op
) == REG
)
4468 /* Print out the second register name of a register pair.
4469 I.e., R (6) => 7. */
4470 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4472 fputs (M68K_REGNAME(REGNO (op
)), file
);
4474 else if (GET_CODE (op
) == MEM
)
4476 output_address (XEXP (op
, 0));
4477 if (letter
== 'd' && ! TARGET_68020
4478 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4479 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4480 && INTVAL (XEXP (op
, 0)) < 0x8000
4481 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4482 fprintf (file
, MOTOROLA
? ".l" : ":l");
4484 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4488 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4489 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
4490 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4492 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4496 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4497 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
4498 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4499 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4501 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4505 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4506 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
4507 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4511 /* Use `print_operand_address' instead of `output_addr_const'
4512 to ensure that we print relevant PIC stuff. */
4513 asm_fprintf (file
, "%I");
4515 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4516 print_operand_address (file
, op
);
4518 output_addr_const (file
, op
);
4522 /* Return string for TLS relocation RELOC. */
4525 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4527 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4528 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4535 if (flag_pic
== 1 && TARGET_68020
)
4576 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4579 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4581 if (GET_CODE (x
) == UNSPEC
)
4583 switch (XINT (x
, 1))
4585 case UNSPEC_RELOC16
:
4586 case UNSPEC_RELOC32
:
4587 output_addr_const (file
, XVECEXP (x
, 0, 0));
4588 fputs (m68k_get_reloc_decoration
4589 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4600 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4603 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4605 gcc_assert (size
== 4);
4606 fputs ("\t.long\t", file
);
4607 output_addr_const (file
, x
);
4608 fputs ("@TLSLDO+0x8000", file
);
4611 /* In the name of slightly smaller debug output, and to cater to
4612 general assembler lossage, recognize various UNSPEC sequences
4613 and turn them back into a direct symbol reference. */
4616 m68k_delegitimize_address (rtx orig_x
)
4619 struct m68k_address addr
;
4622 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4627 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4630 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4631 || addr
.offset
== NULL_RTX
4632 || GET_CODE (addr
.offset
) != CONST
)
4635 unspec
= XEXP (addr
.offset
, 0);
4636 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4637 unspec
= XEXP (unspec
, 0);
4638 if (GET_CODE (unspec
) != UNSPEC
4639 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4640 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4642 x
= XVECEXP (unspec
, 0, 0);
4643 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4644 if (unspec
!= XEXP (addr
.offset
, 0))
4645 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4648 rtx idx
= addr
.index
;
4649 if (addr
.scale
!= 1)
4650 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4651 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4654 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4656 x
= replace_equiv_address_nv (orig_x
, x
);
4661 /* A C compound statement to output to stdio stream STREAM the
4662 assembler syntax for an instruction operand that is a memory
4663 reference whose address is ADDR. ADDR is an RTL expression.
4665 Note that this contains a kludge that knows that the only reason
4666 we have an address (plus (label_ref...) (reg...)) when not generating
4667 PIC code is in the insn before a tablejump, and we know that m68k.md
4668 generates a label LInnn: on such an insn.
4670 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4671 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4673 This routine is responsible for distinguishing between -fpic and -fPIC
4674 style relocations in an address. When generating -fpic code the
4675 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4676 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4679 print_operand_address (FILE *file
, rtx addr
)
4681 struct m68k_address address
;
4683 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4686 if (address
.code
== PRE_DEC
)
4687 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4688 M68K_REGNAME (REGNO (address
.base
)));
4689 else if (address
.code
== POST_INC
)
4690 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4691 M68K_REGNAME (REGNO (address
.base
)));
4692 else if (!address
.base
&& !address
.index
)
4694 /* A constant address. */
4695 gcc_assert (address
.offset
== addr
);
4696 if (GET_CODE (addr
) == CONST_INT
)
4698 /* (xxx).w or (xxx).l. */
4699 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4700 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4702 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4704 else if (TARGET_PCREL
)
4706 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4708 output_addr_const (file
, addr
);
4709 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4713 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4714 name ends in `.<letter>', as the last 2 characters can be
4715 mistaken as a size suffix. Put the name in parentheses. */
4716 if (GET_CODE (addr
) == SYMBOL_REF
4717 && strlen (XSTR (addr
, 0)) > 2
4718 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4721 output_addr_const (file
, addr
);
4725 output_addr_const (file
, addr
);
4732 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4733 label being accessed, otherwise it is -1. */
4734 labelno
= (address
.offset
4736 && GET_CODE (address
.offset
) == LABEL_REF
4737 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4741 /* Print the "offset(base" component. */
4743 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4747 output_addr_const (file
, address
.offset
);
4751 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4753 /* Print the ",index" component, if any. */
4758 fprintf (file
, "%s.%c",
4759 M68K_REGNAME (REGNO (address
.index
)),
4760 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4761 if (address
.scale
!= 1)
4762 fprintf (file
, "*%d", address
.scale
);
4766 else /* !MOTOROLA */
4768 if (!address
.offset
&& !address
.index
)
4769 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4772 /* Print the "base@(offset" component. */
4774 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4778 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4779 fprintf (file
, "@(");
4781 output_addr_const (file
, address
.offset
);
4783 /* Print the ",index" component, if any. */
4786 fprintf (file
, ",%s:%c",
4787 M68K_REGNAME (REGNO (address
.index
)),
4788 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4789 if (address
.scale
!= 1)
4790 fprintf (file
, ":%d", address
.scale
);
4798 /* Check for cases where a clr insns can be omitted from code using
4799 strict_low_part sets. For example, the second clrl here is not needed:
4800 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4802 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4803 insn we are checking for redundancy. TARGET is the register set by the
4807 strict_low_part_peephole_ok (machine_mode mode
, rtx_insn
*first_insn
,
4810 rtx_insn
*p
= first_insn
;
4812 while ((p
= PREV_INSN (p
)))
4814 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4820 /* If it isn't an insn, then give up. */
4824 if (reg_set_p (target
, p
))
4826 rtx set
= single_set (p
);
4829 /* If it isn't an easy to recognize insn, then give up. */
4833 dest
= SET_DEST (set
);
4835 /* If this sets the entire target register to zero, then our
4836 first_insn is redundant. */
4837 if (rtx_equal_p (dest
, target
)
4838 && SET_SRC (set
) == const0_rtx
)
4840 else if (GET_CODE (dest
) == STRICT_LOW_PART
4841 && GET_CODE (XEXP (dest
, 0)) == REG
4842 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4843 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4844 <= GET_MODE_SIZE (mode
)))
4845 /* This is a strict low part set which modifies less than
4846 we are using, so it is safe. */
4856 /* Operand predicates for implementing asymmetric pc-relative addressing
4857 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4858 when used as a source operand, but not as a destination operand.
4860 We model this by restricting the meaning of the basic predicates
4861 (general_operand, memory_operand, etc) to forbid the use of this
4862 addressing mode, and then define the following predicates that permit
4863 this addressing mode. These predicates can then be used for the
4864 source operands of the appropriate instructions.
4866 n.b. While it is theoretically possible to change all machine patterns
4867 to use this addressing more where permitted by the architecture,
4868 it has only been implemented for "common" cases: SImode, HImode, and
4869 QImode operands, and only for the principle operations that would
4870 require this addressing mode: data movement and simple integer operations.
4872 In parallel with these new predicates, two new constraint letters
4873 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4874 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4875 In the pcrel case 's' is only valid in combination with 'a' registers.
4876 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4877 of how these constraints are used.
4879 The use of these predicates is strictly optional, though patterns that
4880 don't will cause an extra reload register to be allocated where one
4883 lea (abc:w,%pc),%a0 ; need to reload address
4884 moveq &1,%d1 ; since write to pc-relative space
4885 movel %d1,%a0@ ; is not allowed
4887 lea (abc:w,%pc),%a1 ; no need to reload address here
4888 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4890 For more info, consult tiemann@cygnus.com.
4893 All of the ugliness with predicates and constraints is due to the
4894 simple fact that the m68k does not allow a pc-relative addressing
4895 mode as a destination. gcc does not distinguish between source and
4896 destination addresses. Hence, if we claim that pc-relative address
4897 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4898 end up with invalid code. To get around this problem, we left
4899 pc-relative modes as invalid addresses, and then added special
4900 predicates and constraints to accept them.
4902 A cleaner way to handle this is to modify gcc to distinguish
4903 between source and destination addresses. We can then say that
4904 pc-relative is a valid source address but not a valid destination
4905 address, and hopefully avoid a lot of the predicate and constraint
4906 hackery. Unfortunately, this would be a pretty big change. It would
4907 be a useful change for a number of ports, but there aren't any current
4908 plans to undertake this.
4910 ***************************************************************************/
4914 output_andsi3 (rtx
*operands
)
4917 if (GET_CODE (operands
[2]) == CONST_INT
4918 && (INTVAL (operands
[2]) | 0xffff) == -1
4919 && (DATA_REG_P (operands
[0])
4920 || offsettable_memref_p (operands
[0]))
4921 && !TARGET_COLDFIRE
)
4923 if (GET_CODE (operands
[0]) != REG
)
4924 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4925 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4926 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4928 if (operands
[2] == const0_rtx
)
4930 return "and%.w %2,%0";
4932 if (GET_CODE (operands
[2]) == CONST_INT
4933 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4934 && (DATA_REG_P (operands
[0])
4935 || offsettable_memref_p (operands
[0])))
4937 if (DATA_REG_P (operands
[0]))
4938 operands
[1] = GEN_INT (logval
);
4941 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4942 operands
[1] = GEN_INT (logval
% 8);
4944 /* This does not set condition codes in a standard way. */
4946 return "bclr %1,%0";
4948 return "and%.l %2,%0";
4952 output_iorsi3 (rtx
*operands
)
4954 register int logval
;
4955 if (GET_CODE (operands
[2]) == CONST_INT
4956 && INTVAL (operands
[2]) >> 16 == 0
4957 && (DATA_REG_P (operands
[0])
4958 || offsettable_memref_p (operands
[0]))
4959 && !TARGET_COLDFIRE
)
4961 if (GET_CODE (operands
[0]) != REG
)
4962 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4963 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4965 if (INTVAL (operands
[2]) == 0xffff)
4966 return "mov%.w %2,%0";
4967 return "or%.w %2,%0";
4969 if (GET_CODE (operands
[2]) == CONST_INT
4970 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4971 && (DATA_REG_P (operands
[0])
4972 || offsettable_memref_p (operands
[0])))
4974 if (DATA_REG_P (operands
[0]))
4975 operands
[1] = GEN_INT (logval
);
4978 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4979 operands
[1] = GEN_INT (logval
% 8);
4982 return "bset %1,%0";
4984 return "or%.l %2,%0";
4988 output_xorsi3 (rtx
*operands
)
4990 register int logval
;
4991 if (GET_CODE (operands
[2]) == CONST_INT
4992 && INTVAL (operands
[2]) >> 16 == 0
4993 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4994 && !TARGET_COLDFIRE
)
4996 if (! DATA_REG_P (operands
[0]))
4997 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4998 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5000 if (INTVAL (operands
[2]) == 0xffff)
5002 return "eor%.w %2,%0";
5004 if (GET_CODE (operands
[2]) == CONST_INT
5005 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5006 && (DATA_REG_P (operands
[0])
5007 || offsettable_memref_p (operands
[0])))
5009 if (DATA_REG_P (operands
[0]))
5010 operands
[1] = GEN_INT (logval
);
5013 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5014 operands
[1] = GEN_INT (logval
% 8);
5017 return "bchg %1,%0";
5019 return "eor%.l %2,%0";
5022 /* Return the instruction that should be used for a call to address X,
5023 which is known to be in operand 0. */
5028 if (symbolic_operand (x
, VOIDmode
))
5029 return m68k_symbolic_call
;
5034 /* Likewise sibling calls. */
5037 output_sibcall (rtx x
)
5039 if (symbolic_operand (x
, VOIDmode
))
5040 return m68k_symbolic_jump
;
5046 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5047 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5050 rtx this_slot
, offset
, addr
, mem
, tmp
;
5053 /* Avoid clobbering the struct value reg by using the
5054 static chain reg as a temporary. */
5055 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5057 /* Pretend to be a post-reload pass while generating rtl. */
5058 reload_completed
= 1;
5060 /* The "this" pointer is stored at 4(%sp). */
5061 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
,
5062 stack_pointer_rtx
, 4));
5064 /* Add DELTA to THIS. */
5067 /* Make the offset a legitimate operand for memory addition. */
5068 offset
= GEN_INT (delta
);
5069 if ((delta
< -8 || delta
> 8)
5070 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5072 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5073 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5075 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5076 copy_rtx (this_slot
), offset
));
5079 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5080 if (vcall_offset
!= 0)
5082 /* Set the static chain register to *THIS. */
5083 emit_move_insn (tmp
, this_slot
);
5084 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5086 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5087 addr
= plus_constant (Pmode
, tmp
, vcall_offset
);
5088 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5090 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, addr
));
5094 /* Load the offset into %d0 and add it to THIS. */
5095 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5096 gen_rtx_MEM (Pmode
, addr
));
5097 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5098 copy_rtx (this_slot
),
5099 gen_rtx_REG (Pmode
, D0_REG
)));
5102 /* Jump to the target function. Use a sibcall if direct jumps are
5103 allowed, otherwise load the address into a register first. */
5104 mem
= DECL_RTL (function
);
5105 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5107 gcc_assert (flag_pic
);
5109 if (!TARGET_SEP_DATA
)
5111 /* Use the static chain register as a temporary (call-clobbered)
5112 GOT pointer for this function. We can use the static chain
5113 register because it isn't live on entry to the thunk. */
5114 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5115 emit_insn (gen_load_got (pic_offset_table_rtx
));
5117 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5118 mem
= replace_equiv_address (mem
, tmp
);
5120 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5121 SIBLING_CALL_P (insn
) = 1;
5123 /* Run just enough of rest_of_compilation. */
5124 insn
= get_insns ();
5125 split_all_insns_noflow ();
5126 final_start_function (insn
, file
, 1);
5127 final (insn
, file
, 1);
5128 final_end_function ();
5130 /* Clean up the vars set above. */
5131 reload_completed
= 0;
5133 /* Restore the original PIC register. */
5135 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5138 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5141 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5142 int incoming ATTRIBUTE_UNUSED
)
5144 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5147 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5149 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5150 unsigned int new_reg
)
5153 /* Interrupt functions can only use registers that have already been
5154 saved by the prologue, even if they would normally be
5157 if ((m68k_get_function_kind (current_function_decl
)
5158 == m68k_fk_interrupt_handler
)
5159 && !df_regs_ever_live_p (new_reg
))
5165 /* Value is true if hard register REGNO can hold a value of machine-mode
5166 MODE. On the 68000, we let the cpu registers can hold any mode, but
5167 restrict the 68881 registers to floating-point modes. */
5170 m68k_regno_mode_ok (int regno
, machine_mode mode
)
5172 if (DATA_REGNO_P (regno
))
5174 /* Data Registers, can hold aggregate if fits in. */
5175 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5178 else if (ADDRESS_REGNO_P (regno
))
5180 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5183 else if (FP_REGNO_P (regno
))
5185 /* FPU registers, hold float or complex float of long double or
5187 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5188 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5189 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5195 /* Implement SECONDARY_RELOAD_CLASS. */
5198 m68k_secondary_reload_class (enum reg_class rclass
,
5199 machine_mode mode
, rtx x
)
5203 regno
= true_regnum (x
);
5205 /* If one operand of a movqi is an address register, the other
5206 operand must be a general register or constant. Other types
5207 of operand must be reloaded through a data register. */
5208 if (GET_MODE_SIZE (mode
) == 1
5209 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5210 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5213 /* PC-relative addresses must be loaded into an address register first. */
5215 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5216 && symbolic_operand (x
, VOIDmode
))
5222 /* Implement PREFERRED_RELOAD_CLASS. */
5225 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5227 enum reg_class secondary_class
;
5229 /* If RCLASS might need a secondary reload, try restricting it to
5230 a class that doesn't. */
5231 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5232 if (secondary_class
!= NO_REGS
5233 && reg_class_subset_p (secondary_class
, rclass
))
5234 return secondary_class
;
5236 /* Prefer to use moveq for in-range constants. */
5237 if (GET_CODE (x
) == CONST_INT
5238 && reg_class_subset_p (DATA_REGS
, rclass
)
5239 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5242 /* ??? Do we really need this now? */
5243 if (GET_CODE (x
) == CONST_DOUBLE
5244 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5246 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5255 /* Return floating point values in a 68881 register. This makes 68881 code
5256 a little bit faster. It also makes -msoft-float code incompatible with
5257 hard-float code, so people have to be careful not to mix the two.
5258 For ColdFire it was decided the ABI incompatibility is undesirable.
5259 If there is need for a hard-float ABI it is probably worth doing it
5260 properly and also passing function arguments in FP registers. */
5262 m68k_libcall_value (machine_mode mode
)
5269 return gen_rtx_REG (mode
, FP0_REG
);
5275 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5278 /* Location in which function value is returned.
5279 NOTE: Due to differences in ABIs, don't call this function directly,
5280 use FUNCTION_VALUE instead. */
5282 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5286 mode
= TYPE_MODE (valtype
);
5292 return gen_rtx_REG (mode
, FP0_REG
);
5298 /* If the function returns a pointer, push that into %a0. */
5299 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5300 /* For compatibility with the large body of existing code which
5301 does not always properly declare external functions returning
5302 pointer types, the m68k/SVR4 convention is to copy the value
5303 returned for pointer functions from a0 to d0 in the function
5304 epilogue, so that callers that have neglected to properly
5305 declare the callee can still find the correct return value in
5307 return gen_rtx_PARALLEL
5310 gen_rtx_EXPR_LIST (VOIDmode
,
5311 gen_rtx_REG (mode
, A0_REG
),
5313 gen_rtx_EXPR_LIST (VOIDmode
,
5314 gen_rtx_REG (mode
, D0_REG
),
5316 else if (POINTER_TYPE_P (valtype
))
5317 return gen_rtx_REG (mode
, A0_REG
);
5319 return gen_rtx_REG (mode
, D0_REG
);
5322 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5323 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5325 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5327 machine_mode mode
= TYPE_MODE (type
);
5329 if (mode
== BLKmode
)
5332 /* If TYPE's known alignment is less than the alignment of MODE that
5333 would contain the structure, then return in memory. We need to
5334 do so to maintain the compatibility between code compiled with
5335 -mstrict-align and that compiled with -mno-strict-align. */
5336 if (AGGREGATE_TYPE_P (type
)
5337 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5344 /* CPU to schedule the program for. */
5345 enum attr_cpu m68k_sched_cpu
;
5347 /* MAC to schedule the program for. */
5348 enum attr_mac m68k_sched_mac
;
5356 /* Integer register. */
5362 /* Implicit mem reference (e.g. stack). */
5365 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5368 /* Memory with offset but without indexing. EA mode 5. */
5371 /* Memory with indexing. EA mode 6. */
5374 /* Memory referenced by absolute address. EA mode 7. */
5377 /* Immediate operand that doesn't require extension word. */
5380 /* Immediate 16 bit operand. */
5383 /* Immediate 32 bit operand. */
5387 /* Return type of memory ADDR_RTX refers to. */
5388 static enum attr_op_type
5389 sched_address_type (machine_mode mode
, rtx addr_rtx
)
5391 struct m68k_address address
;
5393 if (symbolic_operand (addr_rtx
, VOIDmode
))
5394 return OP_TYPE_MEM7
;
5396 if (!m68k_decompose_address (mode
, addr_rtx
,
5397 reload_completed
, &address
))
5399 gcc_assert (!reload_completed
);
5400 /* Reload will likely fix the address to be in the register. */
5401 return OP_TYPE_MEM234
;
5404 if (address
.scale
!= 0)
5405 return OP_TYPE_MEM6
;
5407 if (address
.base
!= NULL_RTX
)
5409 if (address
.offset
== NULL_RTX
)
5410 return OP_TYPE_MEM234
;
5412 return OP_TYPE_MEM5
;
5415 gcc_assert (address
.offset
!= NULL_RTX
);
5417 return OP_TYPE_MEM7
;
5420 /* Return X or Y (depending on OPX_P) operand of INSN. */
5422 sched_get_operand (rtx_insn
*insn
, bool opx_p
)
5426 if (recog_memoized (insn
) < 0)
5429 extract_constrain_insn_cached (insn
);
5432 i
= get_attr_opx (insn
);
5434 i
= get_attr_opy (insn
);
5436 if (i
>= recog_data
.n_operands
)
5439 return recog_data
.operand
[i
];
5442 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5443 If ADDRESS_P is true, return type of memory location operand refers to. */
5444 static enum attr_op_type
5445 sched_attr_op_type (rtx_insn
*insn
, bool opx_p
, bool address_p
)
5449 op
= sched_get_operand (insn
, opx_p
);
5453 gcc_assert (!reload_completed
);
5458 return sched_address_type (QImode
, op
);
5460 if (memory_operand (op
, VOIDmode
))
5461 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5463 if (register_operand (op
, VOIDmode
))
5465 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5466 || (reload_completed
&& FP_REG_P (op
)))
5472 if (GET_CODE (op
) == CONST_INT
)
5478 /* Check for quick constants. */
5479 switch (get_attr_type (insn
))
5482 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5483 return OP_TYPE_IMM_Q
;
5485 gcc_assert (!reload_completed
);
5489 if (USE_MOVQ (ival
))
5490 return OP_TYPE_IMM_Q
;
5492 gcc_assert (!reload_completed
);
5496 if (valid_mov3q_const (ival
))
5497 return OP_TYPE_IMM_Q
;
5499 gcc_assert (!reload_completed
);
5506 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5507 return OP_TYPE_IMM_W
;
5509 return OP_TYPE_IMM_L
;
5512 if (GET_CODE (op
) == CONST_DOUBLE
)
5514 switch (GET_MODE (op
))
5517 return OP_TYPE_IMM_W
;
5521 return OP_TYPE_IMM_L
;
5528 if (GET_CODE (op
) == CONST
5529 || symbolic_operand (op
, VOIDmode
)
5532 switch (GET_MODE (op
))
5535 return OP_TYPE_IMM_Q
;
5538 return OP_TYPE_IMM_W
;
5541 return OP_TYPE_IMM_L
;
5544 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5546 return OP_TYPE_IMM_W
;
5548 return OP_TYPE_IMM_L
;
5552 gcc_assert (!reload_completed
);
5554 if (FLOAT_MODE_P (GET_MODE (op
)))
5560 /* Implement opx_type attribute.
5561 Return type of INSN's operand X.
5562 If ADDRESS_P is true, return type of memory location operand refers to. */
5564 m68k_sched_attr_opx_type (rtx_insn
*insn
, int address_p
)
5566 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5572 return OPX_TYPE_FPN
;
5575 return OPX_TYPE_MEM1
;
5577 case OP_TYPE_MEM234
:
5578 return OPX_TYPE_MEM234
;
5581 return OPX_TYPE_MEM5
;
5584 return OPX_TYPE_MEM6
;
5587 return OPX_TYPE_MEM7
;
5590 return OPX_TYPE_IMM_Q
;
5593 return OPX_TYPE_IMM_W
;
5596 return OPX_TYPE_IMM_L
;
5603 /* Implement opy_type attribute.
5604 Return type of INSN's operand Y.
5605 If ADDRESS_P is true, return type of memory location operand refers to. */
5607 m68k_sched_attr_opy_type (rtx_insn
*insn
, int address_p
)
5609 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5615 return OPY_TYPE_FPN
;
5618 return OPY_TYPE_MEM1
;
5620 case OP_TYPE_MEM234
:
5621 return OPY_TYPE_MEM234
;
5624 return OPY_TYPE_MEM5
;
5627 return OPY_TYPE_MEM6
;
5630 return OPY_TYPE_MEM7
;
5633 return OPY_TYPE_IMM_Q
;
5636 return OPY_TYPE_IMM_W
;
5639 return OPY_TYPE_IMM_L
;
5646 /* Return size of INSN as int. */
5648 sched_get_attr_size_int (rtx_insn
*insn
)
5652 switch (get_attr_type (insn
))
5655 /* There should be no references to m68k_sched_attr_size for 'ignore'
5669 switch (get_attr_opx_type (insn
))
5675 case OPX_TYPE_MEM234
:
5676 case OPY_TYPE_IMM_Q
:
5681 /* Here we assume that most absolute references are short. */
5683 case OPY_TYPE_IMM_W
:
5687 case OPY_TYPE_IMM_L
:
5695 switch (get_attr_opy_type (insn
))
5701 case OPY_TYPE_MEM234
:
5702 case OPY_TYPE_IMM_Q
:
5707 /* Here we assume that most absolute references are short. */
5709 case OPY_TYPE_IMM_W
:
5713 case OPY_TYPE_IMM_L
:
5723 gcc_assert (!reload_completed
);
5731 /* Return size of INSN as attribute enum value. */
5733 m68k_sched_attr_size (rtx_insn
*insn
)
5735 switch (sched_get_attr_size_int (insn
))
5751 /* Return operand X or Y (depending on OPX_P) of INSN,
5752 if it is a MEM, or NULL overwise. */
5753 static enum attr_op_type
5754 sched_get_opxy_mem_type (rtx_insn
*insn
, bool opx_p
)
5758 switch (get_attr_opx_type (insn
))
5763 case OPX_TYPE_IMM_Q
:
5764 case OPX_TYPE_IMM_W
:
5765 case OPX_TYPE_IMM_L
:
5769 case OPX_TYPE_MEM234
:
5772 return OP_TYPE_MEM1
;
5775 return OP_TYPE_MEM6
;
5783 switch (get_attr_opy_type (insn
))
5788 case OPY_TYPE_IMM_Q
:
5789 case OPY_TYPE_IMM_W
:
5790 case OPY_TYPE_IMM_L
:
5794 case OPY_TYPE_MEM234
:
5797 return OP_TYPE_MEM1
;
5800 return OP_TYPE_MEM6
;
5808 /* Implement op_mem attribute. */
5810 m68k_sched_attr_op_mem (rtx_insn
*insn
)
5812 enum attr_op_type opx
;
5813 enum attr_op_type opy
;
5815 opx
= sched_get_opxy_mem_type (insn
, true);
5816 opy
= sched_get_opxy_mem_type (insn
, false);
5818 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5821 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5823 switch (get_attr_opx_access (insn
))
5839 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5841 switch (get_attr_opx_access (insn
))
5857 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5860 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5862 switch (get_attr_opx_access (insn
))
5868 gcc_assert (!reload_completed
);
5873 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5875 switch (get_attr_opx_access (insn
))
5881 gcc_assert (!reload_completed
);
5886 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5889 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5891 switch (get_attr_opx_access (insn
))
5897 gcc_assert (!reload_completed
);
5902 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5903 gcc_assert (!reload_completed
);
5907 /* Data for ColdFire V4 index bypass.
5908 Producer modifies register that is used as index in consumer with
5912 /* Producer instruction. */
5915 /* Consumer instruction. */
5918 /* Scale of indexed memory access within consumer.
5919 Or zero if bypass should not be effective at the moment. */
5921 } sched_cfv4_bypass_data
;
5923 /* An empty state that is used in m68k_sched_adjust_cost. */
5924 static state_t sched_adjust_cost_state
;
5926 /* Implement adjust_cost scheduler hook.
5927 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5929 m68k_sched_adjust_cost (rtx_insn
*insn
, rtx link ATTRIBUTE_UNUSED
,
5930 rtx_insn
*def_insn
, int cost
)
5934 if (recog_memoized (def_insn
) < 0
5935 || recog_memoized (insn
) < 0)
5938 if (sched_cfv4_bypass_data
.scale
== 1)
5939 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5941 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5942 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5943 that the data in sched_cfv4_bypass_data is up to date. */
5944 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5945 && sched_cfv4_bypass_data
.con
== insn
);
5950 sched_cfv4_bypass_data
.pro
= NULL
;
5951 sched_cfv4_bypass_data
.con
= NULL
;
5952 sched_cfv4_bypass_data
.scale
= 0;
5955 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5956 && sched_cfv4_bypass_data
.con
== NULL
5957 && sched_cfv4_bypass_data
.scale
== 0);
5959 /* Don't try to issue INSN earlier than DFA permits.
5960 This is especially useful for instructions that write to memory,
5961 as their true dependence (default) latency is better to be set to 0
5962 to workaround alias analysis limitations.
5963 This is, in fact, a machine independent tweak, so, probably,
5964 it should be moved to haifa-sched.c: insn_cost (). */
5965 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5972 /* Return maximal number of insns that can be scheduled on a single cycle. */
5974 m68k_sched_issue_rate (void)
5976 switch (m68k_sched_cpu
)
5992 /* Maximal length of instruction for current CPU.
5993 E.g. it is 3 for any ColdFire core. */
5994 static int max_insn_size
;
5996 /* Data to model instruction buffer of CPU. */
5999 /* True if instruction buffer model is modeled for current CPU. */
6002 /* Size of the instruction buffer in words. */
6005 /* Number of filled words in the instruction buffer. */
6008 /* Additional information about instruction buffer for CPUs that have
6009 a buffer of instruction records, rather then a plain buffer
6010 of instruction words. */
6011 struct _sched_ib_records
6013 /* Size of buffer in records. */
6016 /* Array to hold data on adjustements made to the size of the buffer. */
6019 /* Index of the above array. */
6023 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6027 static struct _sched_ib sched_ib
;
6029 /* ID of memory unit. */
6030 static int sched_mem_unit_code
;
6032 /* Implementation of the targetm.sched.variable_issue () hook.
6033 It is called after INSN was issued. It returns the number of insns
6034 that can possibly get scheduled on the current cycle.
6035 It is used here to determine the effect of INSN on the instruction
6038 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6039 int sched_verbose ATTRIBUTE_UNUSED
,
6040 rtx_insn
*insn
, int can_issue_more
)
6044 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6046 switch (m68k_sched_cpu
)
6050 insn_size
= sched_get_attr_size_int (insn
);
6054 insn_size
= sched_get_attr_size_int (insn
);
6056 /* ColdFire V3 and V4 cores have instruction buffers that can
6057 accumulate up to 8 instructions regardless of instructions'
6058 sizes. So we should take care not to "prefetch" 24 one-word
6059 or 12 two-words instructions.
6060 To model this behavior we temporarily decrease size of the
6061 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6065 adjust
= max_insn_size
- insn_size
;
6066 sched_ib
.size
-= adjust
;
6068 if (sched_ib
.filled
> sched_ib
.size
)
6069 sched_ib
.filled
= sched_ib
.size
;
6071 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6074 ++sched_ib
.records
.adjust_index
;
6075 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6076 sched_ib
.records
.adjust_index
= 0;
6078 /* Undo adjustement we did 7 instructions ago. */
6080 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6085 gcc_assert (!sched_ib
.enabled_p
);
6093 if (insn_size
> sched_ib
.filled
)
6094 /* Scheduling for register pressure does not always take DFA into
6095 account. Workaround instruction buffer not being filled enough. */
6097 gcc_assert (sched_pressure
== SCHED_PRESSURE_WEIGHTED
);
6098 insn_size
= sched_ib
.filled
;
6103 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6104 || asm_noperands (PATTERN (insn
)) >= 0)
6105 insn_size
= sched_ib
.filled
;
6109 sched_ib
.filled
-= insn_size
;
6111 return can_issue_more
;
6114 /* Return how many instructions should scheduler lookahead to choose the
6117 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6119 return m68k_sched_issue_rate () - 1;
6122 /* Implementation of targetm.sched.init_global () hook.
6123 It is invoked once per scheduling pass and is used here
6124 to initialize scheduler constants. */
6126 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6127 int sched_verbose ATTRIBUTE_UNUSED
,
6128 int n_insns ATTRIBUTE_UNUSED
)
6130 #ifdef ENABLE_CHECKING
6131 /* Check that all instructions have DFA reservations and
6132 that all instructions can be issued from a clean state. */
6137 state
= alloca (state_size ());
6139 for (insn
= get_insns (); insn
!= NULL
; insn
= NEXT_INSN (insn
))
6141 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6143 gcc_assert (insn_has_dfa_reservation_p (insn
));
6145 state_reset (state
);
6146 if (state_transition (state
, insn
) >= 0)
6153 /* Setup target cpu. */
6155 /* ColdFire V4 has a set of features to keep its instruction buffer full
6156 (e.g., a separate memory bus for instructions) and, hence, we do not model
6157 buffer for this CPU. */
6158 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6160 switch (m68k_sched_cpu
)
6163 sched_ib
.filled
= 0;
6170 sched_ib
.records
.n_insns
= 0;
6171 sched_ib
.records
.adjust
= NULL
;
6176 sched_ib
.records
.n_insns
= 8;
6177 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6184 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6186 sched_adjust_cost_state
= xmalloc (state_size ());
6187 state_reset (sched_adjust_cost_state
);
6190 emit_insn (gen_ib ());
6191 sched_ib
.insn
= get_insns ();
6195 /* Scheduling pass is now finished. Free/reset static variables. */
6197 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6198 int verbose ATTRIBUTE_UNUSED
)
6200 sched_ib
.insn
= NULL
;
6202 free (sched_adjust_cost_state
);
6203 sched_adjust_cost_state
= NULL
;
6205 sched_mem_unit_code
= 0;
6207 free (sched_ib
.records
.adjust
);
6208 sched_ib
.records
.adjust
= NULL
;
6209 sched_ib
.records
.n_insns
= 0;
6213 /* Implementation of targetm.sched.init () hook.
6214 It is invoked each time scheduler starts on the new block (basic block or
6215 extended basic block). */
6217 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6218 int sched_verbose ATTRIBUTE_UNUSED
,
6219 int n_insns ATTRIBUTE_UNUSED
)
6221 switch (m68k_sched_cpu
)
6229 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6231 memset (sched_ib
.records
.adjust
, 0,
6232 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6233 sched_ib
.records
.adjust_index
= 0;
6237 gcc_assert (!sched_ib
.enabled_p
);
6245 if (sched_ib
.enabled_p
)
6246 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6247 the first cycle. Workaround that. */
6248 sched_ib
.filled
= -2;
6251 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6252 It is invoked just before current cycle finishes and is used here
6253 to track if instruction buffer got its two words this cycle. */
6255 m68k_sched_dfa_pre_advance_cycle (void)
6257 if (!sched_ib
.enabled_p
)
6260 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6262 sched_ib
.filled
+= 2;
6264 if (sched_ib
.filled
> sched_ib
.size
)
6265 sched_ib
.filled
= sched_ib
.size
;
6269 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6270 It is invoked just after new cycle begins and is used here
6271 to setup number of filled words in the instruction buffer so that
6272 instructions which won't have all their words prefetched would be
6273 stalled for a cycle. */
6275 m68k_sched_dfa_post_advance_cycle (void)
6279 if (!sched_ib
.enabled_p
)
6282 /* Setup number of prefetched instruction words in the instruction
6284 i
= max_insn_size
- sched_ib
.filled
;
6288 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6289 /* Pick up scheduler state. */
6294 /* Return X or Y (depending on OPX_P) operand of INSN,
6295 if it is an integer register, or NULL overwise. */
6297 sched_get_reg_operand (rtx_insn
*insn
, bool opx_p
)
6303 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6305 op
= sched_get_operand (insn
, true);
6306 gcc_assert (op
!= NULL
);
6308 if (!reload_completed
&& !REG_P (op
))
6314 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6316 op
= sched_get_operand (insn
, false);
6317 gcc_assert (op
!= NULL
);
6319 if (!reload_completed
&& !REG_P (op
))
6327 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6330 sched_mem_operand_p (rtx_insn
*insn
, bool opx_p
)
6332 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6343 /* Return X or Y (depending on OPX_P) operand of INSN,
6344 if it is a MEM, or NULL overwise. */
6346 sched_get_mem_operand (rtx_insn
*insn
, bool must_read_p
, bool must_write_p
)
6366 if (opy_p
&& sched_mem_operand_p (insn
, false))
6367 return sched_get_operand (insn
, false);
6369 if (opx_p
&& sched_mem_operand_p (insn
, true))
6370 return sched_get_operand (insn
, true);
6376 /* Return non-zero if PRO modifies register used as part of
6379 m68k_sched_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6384 pro_x
= sched_get_reg_operand (pro
, true);
6388 con_mem_read
= sched_get_mem_operand (con
, true, false);
6389 gcc_assert (con_mem_read
!= NULL
);
6391 if (reg_mentioned_p (pro_x
, con_mem_read
))
6397 /* Helper function for m68k_sched_indexed_address_bypass_p.
6398 if PRO modifies register used as index in CON,
6399 return scale of indexed memory access in CON. Return zero overwise. */
6401 sched_get_indexed_address_scale (rtx_insn
*pro
, rtx_insn
*con
)
6405 struct m68k_address address
;
6407 reg
= sched_get_reg_operand (pro
, true);
6411 mem
= sched_get_mem_operand (con
, true, false);
6412 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6414 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6418 if (REGNO (reg
) == REGNO (address
.index
))
6420 gcc_assert (address
.scale
!= 0);
6421 return address
.scale
;
6427 /* Return non-zero if PRO modifies register used
6428 as index with scale 2 or 4 in CON. */
6430 m68k_sched_indexed_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6432 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6433 && sched_cfv4_bypass_data
.con
== NULL
6434 && sched_cfv4_bypass_data
.scale
== 0);
6436 switch (sched_get_indexed_address_scale (pro
, con
))
6439 /* We can't have a variable latency bypass, so
6440 remember to adjust the insn cost in adjust_cost hook. */
6441 sched_cfv4_bypass_data
.pro
= pro
;
6442 sched_cfv4_bypass_data
.con
= con
;
6443 sched_cfv4_bypass_data
.scale
= 1;
6455 /* We generate a two-instructions program at M_TRAMP :
6456 movea.l &CHAIN_VALUE,%a0
6458 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6461 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6463 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6466 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6468 mem
= adjust_address (m_tramp
, HImode
, 0);
6469 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6470 mem
= adjust_address (m_tramp
, SImode
, 2);
6471 emit_move_insn (mem
, chain_value
);
6473 mem
= adjust_address (m_tramp
, HImode
, 6);
6474 emit_move_insn (mem
, GEN_INT(0x4EF9));
6475 mem
= adjust_address (m_tramp
, SImode
, 8);
6476 emit_move_insn (mem
, fnaddr
);
6478 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6481 /* On the 68000, the RTS insn cannot pop anything.
6482 On the 68010, the RTD insn may be used to pop them if the number
6483 of args is fixed, but if the number is variable then the caller
6484 must pop them all. RTD can't be used for library calls now
6485 because the library is compiled with the Unix compiler.
6486 Use of RTD is a selectable option, since it is incompatible with
6487 standard Unix calling sequences. If the option is not selected,
6488 the caller must always pop the args. */
6491 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6495 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6496 && (!stdarg_p (funtype
)))
6500 /* Make sure everything's fine if we *don't* have a given processor.
6501 This assumes that putting a register in fixed_regs will keep the
6502 compiler's mitts completely off it. We don't bother to zero it out
6503 of register classes. */
6506 m68k_conditional_register_usage (void)
6510 if (!TARGET_HARD_FLOAT
)
6512 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6513 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6514 if (TEST_HARD_REG_BIT (x
, i
))
6515 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6518 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6522 m68k_init_sync_libfuncs (void)
6524 init_sync_libfuncs (UNITS_PER_WORD
);
6527 /* Implements EPILOGUE_USES. All registers are live on exit from an
6528 interrupt routine. */
6530 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
6532 return (reload_completed
6533 && (m68k_get_function_kind (current_function_decl
)
6534 == m68k_fk_interrupt_handler
));
6537 #include "gt-m68k.h"