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gcc/ada/
[official-gcc.git] / gcc / config / aarch64 / aarch64.h
blob5fca0782b6687277d4b549e415e88e7042113c4d
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2014 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21
22 #ifndef GCC_AARCH64_H
23 #define GCC_AARCH64_H
24
25 /* Target CPU builtins. */
26 #define TARGET_CPU_CPP_BUILTINS() \
27 do \
28 { \
29 builtin_define ("__aarch64__"); \
30 builtin_define ("__ARM_64BIT_STATE"); \
31 builtin_define ("__ARM_ARCH_ISA_A64"); \
32 builtin_define ("__ARM_FEATURE_CLZ"); \
33 builtin_define ("__ARM_FEATURE_IDIV"); \
34 builtin_define ("__ARM_FEATURE_UNALIGNED"); \
35 builtin_define ("__ARM_PCS_AAPCS64"); \
36 builtin_define_with_int_value \
37 ("__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE / 8); \
38 builtin_define_with_int_value \
39 ("__ARM_SIZEOF_MINIMAL_ENUM", \
40 flag_short_enums? 1 : 4); \
41 if (TARGET_BIG_END) \
42 { \
43 builtin_define ("__AARCH64EB__"); \
44 builtin_define ("__ARM_BIG_ENDIAN"); \
45 } \
46 else \
47 builtin_define ("__AARCH64EL__"); \
48 \
49 if (TARGET_SIMD) \
50 builtin_define ("__ARM_NEON"); \
51 \
52 if (TARGET_CRC32) \
53 builtin_define ("__ARM_FEATURE_CRC32"); \
54 \
55 switch (aarch64_cmodel) \
56 { \
57 case AARCH64_CMODEL_TINY: \
58 case AARCH64_CMODEL_TINY_PIC: \
59 builtin_define ("__AARCH64_CMODEL_TINY__"); \
60 break; \
61 case AARCH64_CMODEL_SMALL: \
62 case AARCH64_CMODEL_SMALL_PIC: \
63 builtin_define ("__AARCH64_CMODEL_SMALL__");\
64 break; \
65 case AARCH64_CMODEL_LARGE: \
66 builtin_define ("__AARCH64_CMODEL_LARGE__"); \
67 break; \
68 default: \
69 break; \
70 } \
71 \
72 if (TARGET_ILP32) \
73 { \
74 cpp_define (parse_in, "_ILP32"); \
75 cpp_define (parse_in, "__ILP32__"); \
76 } \
77 if (TARGET_CRYPTO) \
78 builtin_define ("__ARM_FEATURE_CRYPTO"); \
79 } while (0)
80
81 \f
82
83 /* Target machine storage layout. */
84
85 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
86 if (GET_MODE_CLASS (MODE) == MODE_INT \
87 && GET_MODE_SIZE (MODE) < 4) \
88 { \
89 if (MODE == QImode || MODE == HImode) \
90 { \
91 MODE = SImode; \
92 } \
93 }
94
95 /* Bits are always numbered from the LSBit. */
96 #define BITS_BIG_ENDIAN 0
97
98 /* Big/little-endian flavour. */
99 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
100 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
101
102 /* AdvSIMD is supported in the default configuration, unless disabled by
103 -mgeneral-regs-only or by the +nosimd extension. */
104 #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD)
105 #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP)
106
107 #define UNITS_PER_WORD 8
108
109 #define UNITS_PER_VREG 16
110
111 #define PARM_BOUNDARY 64
112
113 #define STACK_BOUNDARY 128
114
115 #define FUNCTION_BOUNDARY 32
116
117 #define EMPTY_FIELD_BOUNDARY 32
118
119 #define BIGGEST_ALIGNMENT 128
120
121 #define SHORT_TYPE_SIZE 16
122
123 #define INT_TYPE_SIZE 32
124
125 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
126
127 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
128
129 #define LONG_LONG_TYPE_SIZE 64
130
131 #define FLOAT_TYPE_SIZE 32
132
133 #define DOUBLE_TYPE_SIZE 64
134
135 #define LONG_DOUBLE_TYPE_SIZE 128
136
137 /* The architecture reserves all bits of the address for hardware use,
138 so the vbit must go into the delta field of pointers to member
139 functions. This is the same config as that in the AArch32
140 port. */
141 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
142
143 /* Make strings word-aligned so that strcpy from constants will be
144 faster. */
145 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
146 ((TREE_CODE (EXP) == STRING_CST \
147 && !optimize_size \
148 && (ALIGN) < BITS_PER_WORD) \
149 ? BITS_PER_WORD : ALIGN)
150
151 #define DATA_ALIGNMENT(EXP, ALIGN) \
152 ((((ALIGN) < BITS_PER_WORD) \
153 && (TREE_CODE (EXP) == ARRAY_TYPE \
154 || TREE_CODE (EXP) == UNION_TYPE \
155 || TREE_CODE (EXP) == RECORD_TYPE)) \
156 ? BITS_PER_WORD : (ALIGN))
157
158 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
159
160 #define STRUCTURE_SIZE_BOUNDARY 8
161
162 /* Defined by the ABI */
163 #define WCHAR_TYPE "unsigned int"
164 #define WCHAR_TYPE_SIZE 32
165
166 /* Using long long breaks -ansi and -std=c90, so these will need to be
167 made conditional for an LLP64 ABI. */
168
169 #define SIZE_TYPE "long unsigned int"
170
171 #define PTRDIFF_TYPE "long int"
172
173 #define PCC_BITFIELD_TYPE_MATTERS 1
174
175
176 /* Instruction tuning/selection flags. */
177
178 /* Bit values used to identify processor capabilities. */
179 #define AARCH64_FL_SIMD (1 << 0) /* Has SIMD instructions. */
180 #define AARCH64_FL_FP (1 << 1) /* Has FP. */
181 #define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */
182 #define AARCH64_FL_SLOWMUL (1 << 3) /* A slow multiply core. */
183 #define AARCH64_FL_CRC (1 << 4) /* Has CRC. */
184
185 /* Has FP and SIMD. */
186 #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD)
187
188 /* Has FP without SIMD. */
189 #define AARCH64_FL_FPQ16 (AARCH64_FL_FP & ~AARCH64_FL_SIMD)
190
191 /* Architecture flags that effect instruction selection. */
192 #define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD)
193
194 /* Macros to test ISA flags. */
195 extern unsigned long aarch64_isa_flags;
196 #define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC)
197 #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO)
198 #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP)
199 #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD)
200
201 /* Macros to test tuning flags. */
202 extern unsigned long aarch64_tune_flags;
203 #define AARCH64_TUNE_SLOWMUL (aarch64_tune_flags & AARCH64_FL_SLOWMUL)
204
205 /* Crypto is an optional extension to AdvSIMD. */
206 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
207
208 /* CRC instructions that can be enabled through +crc arch extension. */
209 #define TARGET_CRC32 (AARCH64_ISA_CRC)
210
211 /* Standard register usage. */
212
213 /* 31 64-bit general purpose registers R0-R30:
214 R30 LR (link register)
215 R29 FP (frame pointer)
216 R19-R28 Callee-saved registers
217 R18 The platform register; use as temporary register.
218 R17 IP1 The second intra-procedure-call temporary register
219 (can be used by call veneers and PLT code); otherwise use
220 as a temporary register
221 R16 IP0 The first intra-procedure-call temporary register (can
222 be used by call veneers and PLT code); otherwise use as a
223 temporary register
224 R9-R15 Temporary registers
225 R8 Structure value parameter / temporary register
226 R0-R7 Parameter/result registers
227
228 SP stack pointer, encoded as X/R31 where permitted.
229 ZR zero register, encoded as X/R31 elsewhere
230
231 32 x 128-bit floating-point/vector registers
232 V16-V31 Caller-saved (temporary) registers
233 V8-V15 Callee-saved registers
234 V0-V7 Parameter/result registers
235
236 The vector register V0 holds scalar B0, H0, S0 and D0 in its least
237 significant bits. Unlike AArch32 S1 is not packed into D0,
238 etc. */
239
240 /* Note that we don't mark X30 as a call-clobbered register. The idea is
241 that it's really the call instructions themselves which clobber X30.
242 We don't care what the called function does with it afterwards.
243
244 This approach makes it easier to implement sibcalls. Unlike normal
245 calls, sibcalls don't clobber X30, so the register reaches the
246 called function intact. EPILOGUE_USES says that X30 is useful
247 to the called function. */
248
249 #define FIXED_REGISTERS \
250 { \
251 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \
252 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \
253 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \
254 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \
255 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \
256 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \
257 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \
258 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \
259 1, 1, 1, /* SFP, AP, CC */ \
260 }
261
262 #define CALL_USED_REGISTERS \
263 { \
264 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \
265 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \
266 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \
267 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \
268 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \
269 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \
270 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \
271 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \
272 1, 1, 1, /* SFP, AP, CC */ \
273 }
274
275 #define REGISTER_NAMES \
276 { \
277 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \
278 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \
279 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \
280 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \
281 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
282 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
283 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
284 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
285 "sfp", "ap", "cc", \
286 }
287
288 /* Generate the register aliases for core register N */
289 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \
290 {"w" # N, R0_REGNUM + (N)}
291
292 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \
293 {"d" # N, V0_REGNUM + (N)}, \
294 {"s" # N, V0_REGNUM + (N)}, \
295 {"h" # N, V0_REGNUM + (N)}, \
296 {"b" # N, V0_REGNUM + (N)}
297
298 /* Provide aliases for all of the ISA defined register name forms.
299 These aliases are convenient for use in the clobber lists of inline
300 asm statements. */
301
302 #define ADDITIONAL_REGISTER_NAMES \
303 { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \
304 R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \
305 R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \
306 R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \
307 R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \
308 R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \
309 R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \
310 R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \
311 V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \
312 V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \
313 V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \
314 V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \
315 V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \
316 V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \
317 V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \
318 V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \
319 }
320
321 /* Say that the epilogue uses the return address register. Note that
322 in the case of sibcalls, the values "used by the epilogue" are
323 considered live at the start of the called function. */
324
325 #define EPILOGUE_USES(REGNO) \
326 ((REGNO) == LR_REGNUM)
327
328 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
329 the stack pointer does not matter. The value is tested only in
330 functions that have frame pointers. */
331 #define EXIT_IGNORE_STACK 1
332
333 #define STATIC_CHAIN_REGNUM R18_REGNUM
334 #define HARD_FRAME_POINTER_REGNUM R29_REGNUM
335 #define FRAME_POINTER_REGNUM SFP_REGNUM
336 #define STACK_POINTER_REGNUM SP_REGNUM
337 #define ARG_POINTER_REGNUM AP_REGNUM
338 #define FIRST_PSEUDO_REGISTER 67
339
340 /* The number of (integer) argument register available. */
341 #define NUM_ARG_REGS 8
342 #define NUM_FP_ARG_REGS 8
343
344 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
345 four members. */
346 #define HA_MAX_NUM_FLDS 4
347
348 /* External dwarf register number scheme. These number are used to
349 identify registers in dwarf debug information, the values are
350 defined by the AArch64 ABI. The numbering scheme is independent of
351 GCC's internal register numbering scheme. */
352
353 #define AARCH64_DWARF_R0 0
354
355 /* The number of R registers, note 31! not 32. */
356 #define AARCH64_DWARF_NUMBER_R 31
357
358 #define AARCH64_DWARF_SP 31
359 #define AARCH64_DWARF_V0 64
360
361 /* The number of V registers. */
362 #define AARCH64_DWARF_NUMBER_V 32
363
364 /* For signal frames we need to use an alternative return column. This
365 value must not correspond to a hard register and must be out of the
366 range of DWARF_FRAME_REGNUM(). */
367 #define DWARF_ALT_FRAME_RETURN_COLUMN \
368 (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V)
369
370 /* We add 1 extra frame register for use as the
371 DWARF_ALT_FRAME_RETURN_COLUMN. */
372 #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1)
373
374
375 #define DBX_REGISTER_NUMBER(REGNO) aarch64_dbx_register_number (REGNO)
376 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders
377 can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same
378 as the default definition in dwarf2out.c. */
379 #undef DWARF_FRAME_REGNUM
380 #define DWARF_FRAME_REGNUM(REGNO) DBX_REGISTER_NUMBER (REGNO)
381
382 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
383
384 #define HARD_REGNO_NREGS(REGNO, MODE) aarch64_hard_regno_nregs (REGNO, MODE)
385
386 #define HARD_REGNO_MODE_OK(REGNO, MODE) aarch64_hard_regno_mode_ok (REGNO, MODE)
387
388 #define MODES_TIEABLE_P(MODE1, MODE2) aarch64_modes_tieable_p (MODE1, MODE2)
389
390 #define DWARF2_UNWIND_INFO 1
391
392 /* Use R0 through R3 to pass exception handling information. */
393 #define EH_RETURN_DATA_REGNO(N) \
394 ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM)
395
396 /* Select a format to encode pointers in exception handling data. */
397 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
398 aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL))
399
400 /* The register that holds the return address in exception handlers. */
401 #define AARCH64_EH_STACKADJ_REGNUM (R0_REGNUM + 4)
402 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, AARCH64_EH_STACKADJ_REGNUM)
403
404 /* Don't use __builtin_setjmp until we've defined it. */
405 #undef DONT_USE_BUILTIN_SETJMP
406 #define DONT_USE_BUILTIN_SETJMP 1
407
408 /* Register in which the structure value is to be returned. */
409 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM
410
411 /* Non-zero if REGNO is part of the Core register set.
412
413 The rather unusual way of expressing this check is to avoid
414 warnings when building the compiler when R0_REGNUM is 0 and REGNO
415 is unsigned. */
416 #define GP_REGNUM_P(REGNO) \
417 (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM))
418
419 #define FP_REGNUM_P(REGNO) \
420 (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM))
421
422 #define FP_LO_REGNUM_P(REGNO) \
423 (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM))
424
425 \f
426 /* Register and constant classes. */
427
428 enum reg_class
429 {
430 NO_REGS,
431 CALLER_SAVE_REGS,
432 GENERAL_REGS,
433 STACK_REG,
434 POINTER_REGS,
435 FP_LO_REGS,
436 FP_REGS,
437 ALL_REGS,
438 LIM_REG_CLASSES /* Last */
439 };
440
441 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
442
443 #define REG_CLASS_NAMES \
444 { \
445 "NO_REGS", \
446 "CALLER_SAVE_REGS", \
447 "GENERAL_REGS", \
448 "STACK_REG", \
449 "POINTER_REGS", \
450 "FP_LO_REGS", \
451 "FP_REGS", \
452 "ALL_REGS" \
453 }
454
455 #define REG_CLASS_CONTENTS \
456 { \
457 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
458 { 0x0007ffff, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \
459 { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \
460 { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
461 { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \
462 { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \
463 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \
464 { 0xffffffff, 0xffffffff, 0x00000007 } /* ALL_REGS */ \
465 }
466
467 #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO)
468
469 #define INDEX_REG_CLASS GENERAL_REGS
470 #define BASE_REG_CLASS POINTER_REGS
471
472 /* Register pairs used to eliminate unneeded registers that point into
473 the stack frame. */
474 #define ELIMINABLE_REGS \
475 { \
476 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
477 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
478 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
479 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
480 }
481
482 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
483 (OFFSET) = aarch64_initial_elimination_offset (FROM, TO)
484
485 /* CPU/ARCH option handling. */
486 #include "config/aarch64/aarch64-opts.h"
487
488 enum target_cpus
489 {
490 #define AARCH64_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \
491 TARGET_CPU_##INTERNAL_IDENT,
492 #include "aarch64-cores.def"
493 #undef AARCH64_CORE
494 TARGET_CPU_generic
495 };
496
497 /* If there is no CPU defined at configure, use generic as default. */
498 #ifndef TARGET_CPU_DEFAULT
499 #define TARGET_CPU_DEFAULT \
500 (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6))
501 #endif
502
503 /* If inserting NOP before a mult-accumulate insn remember to adjust the
504 length so that conditional branching code is updated appropriately. */
505 #define ADJUST_INSN_LENGTH(insn, length) \
506 do \
507 { \
508 if (aarch64_madd_needs_nop (insn)) \
509 length += 4; \
510 } while (0)
511
512 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
513 aarch64_final_prescan_insn (INSN); \
514
515 /* The processor for which instructions should be scheduled. */
516 extern enum aarch64_processor aarch64_tune;
517
518 /* RTL generation support. */
519 #define INIT_EXPANDERS aarch64_init_expanders ()
520 \f
521
522 /* Stack layout; function entry, exit and calling. */
523 #define STACK_GROWS_DOWNWARD 1
524
525 #define FRAME_GROWS_DOWNWARD 1
526
527 #define STARTING_FRAME_OFFSET 0
528
529 #define ACCUMULATE_OUTGOING_ARGS 1
530
531 #define FIRST_PARM_OFFSET(FNDECL) 0
532
533 /* Fix for VFP */
534 #define LIBCALL_VALUE(MODE) \
535 gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM)
536
537 #define DEFAULT_PCC_STRUCT_RETURN 0
538
539 #define AARCH64_ROUND_UP(X, ALIGNMENT) \
540 (((X) + ((ALIGNMENT) - 1)) & ~((ALIGNMENT) - 1))
541
542 #define AARCH64_ROUND_DOWN(X, ALIGNMENT) \
543 ((X) & ~((ALIGNMENT) - 1))
544
545 #ifdef HOST_WIDE_INT
546 struct GTY (()) aarch64_frame
547 {
548 HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
549
550 /* The number of extra stack bytes taken up by register varargs.
551 This area is allocated by the callee at the very top of the
552 frame. This value is rounded up to a multiple of
553 STACK_BOUNDARY. */
554 HOST_WIDE_INT saved_varargs_size;
555
556 HOST_WIDE_INT saved_regs_size;
557 /* Padding if needed after the all the callee save registers have
558 been saved. */
559 HOST_WIDE_INT padding0;
560 HOST_WIDE_INT hardfp_offset; /* HARD_FRAME_POINTER_REGNUM */
561
562 /* Offset from the base of the frame (incomming SP) to the
563 hard_frame_pointer. This value is always a multiple of
564 STACK_BOUNDARY. */
565 HOST_WIDE_INT hard_fp_offset;
566
567 /* The size of the frame. This value is the offset from base of the
568 * frame (incomming SP) to the stack_pointer. This value is always
569 * a multiple of STACK_BOUNDARY. */
570
571 unsigned wb_candidate1;
572 unsigned wb_candidate2;
573
574 HOST_WIDE_INT frame_size;
575
576 bool laid_out;
577 };
578
579 typedef struct GTY (()) machine_function
580 {
581 struct aarch64_frame frame;
582 } machine_function;
583 #endif
584
585 /* Which ABI to use. */
586 enum aarch64_abi_type
587 {
588 AARCH64_ABI_LP64 = 0,
589 AARCH64_ABI_ILP32 = 1
590 };
591
592 #ifndef AARCH64_ABI_DEFAULT
593 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64
594 #endif
595
596 #define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32)
597
598 enum arm_pcs
599 {
600 ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */
601 ARM_PCS_UNKNOWN
602 };
603
604
605
606
607 /* We can't use machine_mode inside a generator file because it
608 hasn't been created yet; we shouldn't be using any code that
609 needs the real definition though, so this ought to be safe. */
610 #ifdef GENERATOR_FILE
611 #define MACHMODE int
612 #else
613 #include "insn-modes.h"
614 #define MACHMODE machine_mode
615 #endif
616
617
618 /* AAPCS related state tracking. */
619 typedef struct
620 {
621 enum arm_pcs pcs_variant;
622 int aapcs_arg_processed; /* No need to lay out this argument again. */
623 int aapcs_ncrn; /* Next Core register number. */
624 int aapcs_nextncrn; /* Next next core register number. */
625 int aapcs_nvrn; /* Next Vector register number. */
626 int aapcs_nextnvrn; /* Next Next Vector register number. */
627 rtx aapcs_reg; /* Register assigned to this argument. This
628 is NULL_RTX if this parameter goes on
629 the stack. */
630 MACHMODE aapcs_vfp_rmode;
631 int aapcs_stack_words; /* If the argument is passed on the stack, this
632 is the number of words needed, after rounding
633 up. Only meaningful when
634 aapcs_reg == NULL_RTX. */
635 int aapcs_stack_size; /* The total size (in words, per 8 byte) of the
636 stack arg area so far. */
637 } CUMULATIVE_ARGS;
638
639 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
640 (aarch64_pad_arg_upward (MODE, TYPE) ? upward : downward)
641
642 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
643 (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
644
645 #define PAD_VARARGS_DOWN 0
646
647 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
648 aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS)
649
650 #define FUNCTION_ARG_REGNO_P(REGNO) \
651 aarch64_function_arg_regno_p(REGNO)
652 \f
653
654 /* ISA Features. */
655
656 /* Addressing modes, etc. */
657 #define HAVE_POST_INCREMENT 1
658 #define HAVE_PRE_INCREMENT 1
659 #define HAVE_POST_DECREMENT 1
660 #define HAVE_PRE_DECREMENT 1
661 #define HAVE_POST_MODIFY_DISP 1
662 #define HAVE_PRE_MODIFY_DISP 1
663
664 #define MAX_REGS_PER_ADDRESS 2
665
666 #define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X)
667
668 /* Try a machine-dependent way of reloading an illegitimate address
669 operand. If we find one, push the reload and jump to WIN. This
670 macro is used in only one place: `find_reloads_address' in reload.c. */
671
672 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
673 do { \
674 rtx new_x = aarch64_legitimize_reload_address (&(X), MODE, OPNUM, TYPE, \
675 IND_L); \
676 if (new_x) \
677 { \
678 X = new_x; \
679 goto WIN; \
680 } \
681 } while (0)
682
683 #define REGNO_OK_FOR_BASE_P(REGNO) \
684 aarch64_regno_ok_for_base_p (REGNO, true)
685
686 #define REGNO_OK_FOR_INDEX_P(REGNO) \
687 aarch64_regno_ok_for_index_p (REGNO, true)
688
689 #define LEGITIMATE_PIC_OPERAND_P(X) \
690 aarch64_legitimate_pic_operand_p (X)
691
692 #define CASE_VECTOR_MODE Pmode
693
694 #define DEFAULT_SIGNED_CHAR 0
695
696 /* An integer expression for the size in bits of the largest integer machine
697 mode that should actually be used. We allow pairs of registers. */
698 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
699
700 /* Maximum bytes moved by a single instruction (load/store pair). */
701 #define MOVE_MAX (UNITS_PER_WORD * 2)
702
703 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */
704 #define AARCH64_CALL_RATIO 8
705
706 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure.
707 move_by_pieces will continually copy the largest safe chunks. So a
708 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient
709 for both size and speed of copy, so we will instead use the "movmem"
710 standard name to implement the copy. This logic does not apply when
711 targeting -mstrict-align, so keep a sensible default in that case. */
712 #define MOVE_RATIO(speed) \
713 (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2))
714
715 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
716 of the length of a memset call, but use the default otherwise. */
717 #define CLEAR_RATIO(speed) \
718 ((speed) ? 15 : AARCH64_CALL_RATIO)
719
720 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when
721 optimizing for size adjust the ratio to account for the overhead of loading
722 the constant. */
723 #define SET_RATIO(speed) \
724 ((speed) ? 15 : AARCH64_CALL_RATIO - 2)
725
726 /* STORE_BY_PIECES_P can be used when copying a constant string, but
727 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
728 For now we always fail this and let the move_by_pieces code copy
729 the string from read-only memory. */
730 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
731
732 /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is
733 rarely a good idea in straight-line code since it adds an extra address
734 dependency between each instruction. Better to use incrementing offsets. */
735 #define USE_LOAD_POST_INCREMENT(MODE) 0
736 #define USE_LOAD_POST_DECREMENT(MODE) 0
737 #define USE_LOAD_PRE_INCREMENT(MODE) 0
738 #define USE_LOAD_PRE_DECREMENT(MODE) 0
739 #define USE_STORE_POST_INCREMENT(MODE) 0
740 #define USE_STORE_POST_DECREMENT(MODE) 0
741 #define USE_STORE_PRE_INCREMENT(MODE) 0
742 #define USE_STORE_PRE_DECREMENT(MODE) 0
743
744 /* ?? #define WORD_REGISTER_OPERATIONS */
745
746 /* Define if loading from memory in MODE, an integral mode narrower than
747 BITS_PER_WORD will either zero-extend or sign-extend. The value of this
748 macro should be the code that says which one of the two operations is
749 implicitly done, or UNKNOWN if none. */
750 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
751
752 /* Define this macro to be non-zero if instructions will fail to work
753 if given data not on the nominal alignment. */
754 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
755
756 /* Define this macro to be non-zero if accessing less than a word of
757 memory is no faster than accessing a word of memory, i.e., if such
758 accesses require more than one instruction or if there is no
759 difference in cost.
760 Although there's no difference in instruction count or cycles,
761 in AArch64 we don't want to expand to a sub-word to a 64-bit access
762 if we don't have to, for power-saving reasons. */
763 #define SLOW_BYTE_ACCESS 0
764
765 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
766
767 #define NO_FUNCTION_CSE 1
768
769 /* Specify the machine mode that the hardware addresses have.
770 After generation of rtl, the compiler makes no further distinction
771 between pointers and any other objects of this machine mode. */
772 #define Pmode DImode
773
774 /* A C expression whose value is zero if pointers that need to be extended
775 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
776 greater then zero if they are zero-extended and less then zero if the
777 ptr_extend instruction should be used. */
778 #define POINTERS_EXTEND_UNSIGNED 1
779
780 /* Mode of a function address in a call instruction (for indexing purposes). */
781 #define FUNCTION_MODE Pmode
782
783 #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y)
784
785 #define REVERSIBLE_CC_MODE(MODE) 1
786
787 #define REVERSE_CONDITION(CODE, MODE) \
788 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
789 ? reverse_condition_maybe_unordered (CODE) \
790 : reverse_condition (CODE))
791
792 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
793 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE))
794 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
795 ((VALUE) = ((MODE) == SImode ? 32 : 64), 2)
796
797 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
798
799 #define RETURN_ADDR_RTX aarch64_return_addr
800
801 /* 3 insns + padding + 2 pointer-sized entries. */
802 #define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32)
803
804 /* Trampolines contain dwords, so must be dword aligned. */
805 #define TRAMPOLINE_ALIGNMENT 64
806
807 /* Put trampolines in the text section so that mapping symbols work
808 correctly. */
809 #define TRAMPOLINE_SECTION text_section
810
811 /* To start with. */
812 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) 2
813 \f
814
815 /* Assembly output. */
816
817 /* For now we'll make all jump tables pc-relative. */
818 #define CASE_VECTOR_PC_RELATIVE 1
819
820 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
821 ((min < -0x1fff0 || max > 0x1fff0) ? SImode \
822 : (min < -0x1f0 || max > 0x1f0) ? HImode \
823 : QImode)
824
825 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
826 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
827
828 #define PRINT_OPERAND(STREAM, X, CODE) aarch64_print_operand (STREAM, X, CODE)
829
830 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
831 aarch64_print_operand_address (STREAM, X)
832
833 #define MCOUNT_NAME "_mcount"
834
835 #define NO_PROFILE_COUNTERS 1
836
837 /* Emit rtl for profiling. Output assembler code to FILE
838 to call "_mcount" for profiling a function entry. */
839 #define PROFILE_HOOK(LABEL) \
840 { \
841 rtx fun, lr; \
842 lr = get_hard_reg_initial_val (Pmode, LR_REGNUM); \
843 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \
844 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lr, Pmode); \
845 }
846
847 /* All the work done in PROFILE_HOOK, but still required. */
848 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
849
850 /* For some reason, the Linux headers think they know how to define
851 these macros. They don't!!! */
852 #undef ASM_APP_ON
853 #undef ASM_APP_OFF
854 #define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n"
855 #define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n"
856
857 #define CONSTANT_POOL_BEFORE_FUNCTION 0
858
859 /* This definition should be relocated to aarch64-elf-raw.h. This macro
860 should be undefined in aarch64-linux.h and a clear_cache pattern
861 implmented to emit either the call to __aarch64_sync_cache_range()
862 directly or preferably the appropriate sycall or cache clear
863 instructions inline. */
864 #define CLEAR_INSN_CACHE(beg, end) \
865 extern void __aarch64_sync_cache_range (void *, void *); \
866 __aarch64_sync_cache_range (beg, end)
867
868 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
869 aarch64_cannot_change_mode_class (FROM, TO, CLASS)
870
871 #define SHIFT_COUNT_TRUNCATED !TARGET_SIMD
872
873 /* Choose appropriate mode for caller saves, so we do the minimum
874 required size of load/store. */
875 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
876 aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE))
877
878 /* Callee only saves lower 64-bits of a 128-bit register. Tell the
879 compiler the callee clobbers the top 64-bits when restoring the
880 bottom 64-bits. */
881 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
882 (FP_REGNUM_P (REGNO) && GET_MODE_SIZE (MODE) > 8)
883
884 /* Check TLS Descriptors mechanism is selected. */
885 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS)
886
887 extern enum aarch64_code_model aarch64_cmodel;
888
889 /* When using the tiny addressing model conditional and unconditional branches
890 can span the whole of the available address space (1MB). */
891 #define HAS_LONG_COND_BRANCH \
892 (aarch64_cmodel == AARCH64_CMODEL_TINY \
893 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
894
895 #define HAS_LONG_UNCOND_BRANCH \
896 (aarch64_cmodel == AARCH64_CMODEL_TINY \
897 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
898
899 /* Modes valid for AdvSIMD Q registers. */
900 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \
901 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
902 || (MODE) == V4SFmode || (MODE) == V2DImode || mode == V2DFmode)
903
904 #define ENDIAN_LANE_N(mode, n) \
905 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n)
906
907 /* Support for a configure-time default CPU, etc. We currently support
908 --with-arch and --with-cpu. Both are ignored if either is specified
909 explicitly on the command line at run time. */
910 #define OPTION_DEFAULT_SPECS \
911 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
912 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" },
913
914 #define BIG_LITTLE_SPEC \
915 " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}"
916
917 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv);
918 #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \
919 { "rewrite_mcpu", aarch64_rewrite_mcpu },
920
921 #define ASM_CPU_SPEC \
922 BIG_LITTLE_SPEC
923
924 #define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS
925
926 #define EXTRA_SPECS \
927 { "asm_cpu_spec", ASM_CPU_SPEC }
928
929 #endif /* GCC_AARCH64_H */
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