1 ;;- Machine description for Renesas / SuperH SH.
2 ;; Copyright (C) 1993-2015 Free Software Foundation, Inc.
3 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
4 ;; Improved by Jim Wilson (wilson@cygnus.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
23 ;; ??? Should prepend a * to all pattern names which are not used.
24 ;; This will make the compiler smaller, and rebuilds after changes faster.
26 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
27 ;; sequences. Especially the sequences for arithmetic right shifts.
29 ;; ??? Should check all DImode patterns for consistency and usefulness.
31 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
32 ;; way to generate them.
34 ;; BSR is not generated by the compiler proper, but when relaxing, it
35 ;; generates .uses pseudo-ops that allow linker relaxation to create
36 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
38 ;; Special constraints for SH machine description:
45 ;; Special formats used for outputting SH instructions:
47 ;; %. -- print a .s if insn needs delay slot
48 ;; %@ -- print rte/rts if is/isn't an interrupt function
49 ;; %# -- output a nop if there is nothing to put in the delay slot
50 ;; %O -- print a constant without the #
51 ;; %R -- print the lsw reg of a double
52 ;; %S -- print the msw reg of a double
53 ;; %T -- print next word of a double REG or MEM
55 ;; Special predicates:
57 ;; arith_operand -- operand is valid source for arithmetic op
58 ;; arith_reg_operand -- operand is valid register for arithmetic op
59 ;; general_movdst_operand -- operand is valid move destination
60 ;; general_movsrc_operand -- operand is valid move source
61 ;; logical_operand -- operand is valid source for logical op
63 ;; -------------------------------------------------------------------------
65 ;; -------------------------------------------------------------------------
79 ;; Virtual FPSCR - bits that are used by FP ops.
82 ;; Virtual FPSCR - bits that are updated by FP ops.
119 (FPSCR_PR 524288) ;; 1 << 19
120 (FPSCR_SZ 1048576) ;; 1 << 20
121 (FPSCR_FR 2097152) ;; 1 << 21
124 (define_c_enum "unspec" [
125 ;; These are used with unspec.
164 ;; (unspec [VAL SHIFT] UNSPEC_EXTRACT_S16) computes (short) (VAL >> SHIFT).
165 ;; UNSPEC_EXTRACT_U16 is the unsigned equivalent.
168 ;; (unspec [TARGET ANCHOR] UNSPEC_SYMOFF) == TARGET - ANCHOR.
170 ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .).
173 UNSPEC_BUILTIN_STRLEN
176 (define_c_enum "unspecv" [
177 ;; These are used with unspec_volatile.
194 ;; -------------------------------------------------------------------------
196 ;; -------------------------------------------------------------------------
201 "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a,sh5"
202 (const (symbol_ref "sh_cpu_attr")))
204 (define_attr "endian" "big,little"
205 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
206 (const_string "little") (const_string "big"))))
208 ;; Indicate if the default fpu mode is single precision.
209 (define_attr "fpu_single" "yes,no"
210 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
211 (const_string "yes") (const_string "no"))))
213 (define_attr "fmovd" "yes,no"
214 (const (if_then_else (symbol_ref "TARGET_FMOVD")
215 (const_string "yes") (const_string "no"))))
217 (define_attr "pipe_model" "sh1,sh4,sh5media"
219 (cond [(symbol_ref "TARGET_SHMEDIA") (const_string "sh5media")
220 (symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
221 (const_string "sh1"))))
223 ;; cbranch conditional branch instructions
224 ;; jump unconditional jumps
225 ;; arith ordinary arithmetic
226 ;; arith3 a compound insn that behaves similarly to a sequence of
227 ;; three insns of type arith
228 ;; arith3b like above, but might end with a redirected branch
230 ;; load_si Likewise, SImode variant for general register.
231 ;; fload Likewise, but load to fp register.
233 ;; fstore floating point register to memory
234 ;; move general purpose register to register
235 ;; movi8 8-bit immediate to general purpose register
236 ;; mt_group other sh4 mt instructions
237 ;; fmove register to register, floating point
238 ;; smpy word precision integer multiply
239 ;; dmpy longword or doublelongword precision integer multiply
241 ;; pload load of pr reg, which can't be put into delay slot of rts
242 ;; prset copy register to pr reg, ditto
243 ;; pstore store of pr reg, which can't be put into delay slot of jsr
244 ;; prget copy pr to register, ditto
245 ;; pcload pc relative load of constant value
246 ;; pcfload Likewise, but load to fp register.
247 ;; pcload_si Likewise, SImode variant for general register.
248 ;; rte return from exception
249 ;; sfunc special function call with known used registers
250 ;; call function call
252 ;; fpscr_toggle toggle a bit in the fpscr
253 ;; fdiv floating point divide (or square root)
254 ;; gp_fpul move from general purpose register to fpul
255 ;; fpul_gp move from fpul to general purpose register
256 ;; mac_gp move from mac[lh] to general purpose register
257 ;; gp_mac move from general purpose register to mac[lh]
258 ;; mac_mem move from mac[lh] to memory
259 ;; mem_mac move from memory to mac[lh]
260 ;; dfp_arith,dfp_mul, fp_cmp,dfp_cmp,dfp_conv
261 ;; ftrc_s fix_truncsfsi2_i4
262 ;; dfdiv double precision floating point divide (or square root)
263 ;; cwb ic_invalidate_line_i
264 ;; movua SH4a unaligned load
265 ;; fsrra square root reciprocal approximate
266 ;; fsca sine and cosine approximate
267 ;; tls_load load TLS related address
268 ;; arith_media SHmedia arithmetic, logical, and shift instructions
269 ;; cbranch_media SHmedia conditional branch instructions
270 ;; cmp_media SHmedia compare instructions
271 ;; dfdiv_media SHmedia double precision divide and square root
272 ;; dfmul_media SHmedia double precision multiply instruction
273 ;; dfparith_media SHmedia double precision floating point arithmetic
274 ;; dfpconv_media SHmedia double precision floating point conversions
275 ;; dmpy_media SHmedia longword multiply
276 ;; fcmp_media SHmedia floating point compare instructions
277 ;; fdiv_media SHmedia single precision divide and square root
278 ;; fload_media SHmedia floating point register load instructions
279 ;; fmove_media SHmedia floating point register moves (inc. fabs and fneg)
280 ;; fparith_media SHmedia single precision floating point arithmetic
281 ;; fpconv_media SHmedia single precision floating point conversions
282 ;; fstore_media SHmedia floating point register store instructions
283 ;; gettr_media SHmedia gettr instruction
284 ;; invalidate_line_media SHmedia invalidate_line sequence
285 ;; jump_media SHmedia unconditional branch instructions
286 ;; load_media SHmedia general register load instructions
287 ;; pt_media SHmedia pt instruction (expanded by assembler)
288 ;; ptabs_media SHmedia ptabs instruction
289 ;; store_media SHmedia general register store instructions
290 ;; mcmp_media SHmedia multimedia compare, absolute, saturating ops
291 ;; mac_media SHmedia mac-style fixed point operations
292 ;; d2mpy_media SHmedia: two 32-bit integer multiplies
293 ;; atrans_media SHmedia approximate transcendental functions
294 ;; ustore_media SHmedia unaligned stores
295 ;; nil no-op move, will be deleted.
298 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,
299 fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore,
300 prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s,
301 dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,
302 gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,
303 arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,
304 dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,
305 fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,
306 jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,
307 d2mpy_media,atrans_media,ustore_media,nil,other"
308 (const_string "other"))
310 ;; We define a new attribute namely "insn_class".We use
311 ;; this for the DFA based pipeline description.
313 ;; mt_group SH4 "mt" group instructions.
315 ;; ex_group SH4 "ex" group instructions.
317 ;; ls_group SH4 "ls" group instructions.
319 (define_attr "insn_class"
320 "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
321 (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
322 (eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group")
323 (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,
324 store,fstore,gp_fpul,fpul_gp") (const_string "ls_group")
325 (eq_attr "type" "cbranch,jump") (const_string "br_group")
326 (eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
327 (const_string "fe_group")
328 (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,
329 prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb,
330 gp_mac,mac_mem,mem_mac") (const_string "co_group")]
331 (const_string "none")))
333 ;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
334 ;; so these do not belong in an insn group, although they are modeled
335 ;; with their own define_insn_reservations.
337 ;; Indicate what precision must be selected in fpscr for this insn, if any.
338 (define_attr "fp_mode" "single,double,none" (const_string "none"))
340 ;; Indicate if the fpu mode is set by this instruction
341 ;; "unknown" must have the value as "none" in fp_mode, and means
342 ;; that the instruction/abi has left the processor in an unknown
344 ;; "none" means that nothing has changed and no mode is set.
345 ;; This attribute is only used for the Renesas ABI.
346 (define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
348 ; If a conditional branch destination is within -252..258 bytes away
349 ; from the instruction it can be 2 bytes long. Something in the
350 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
351 ; branches are initially assumed to be 16 bytes long.
352 ; In machine_dependent_reorg, we split all branches that are longer than
355 ;; The maximum range used for SImode constant pool entries is 1018. A final
356 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
357 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
358 ;; instruction around the pool table, 2 bytes of alignment before the table,
359 ;; and 30 bytes of alignment after the table. That gives a maximum total
360 ;; pool size of 1058 bytes.
361 ;; Worst case code/pool content size ratio is 1:2 (using asms).
362 ;; Thus, in the worst case, there is one instruction in front of a maximum
363 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
364 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
365 ;; If we have a forward branch, the initial table will be put after the
366 ;; unconditional branch.
368 ;; ??? We could do much better by keeping track of the actual pcloads within
369 ;; the branch range and in the pcload range in front of the branch range.
371 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
373 (define_attr "short_cbranch_p" "no,yes"
374 (cond [(match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
376 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
378 (match_test "NEXT_INSN (PREV_INSN (insn)) != insn")
380 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
382 ] (const_string "no")))
384 (define_attr "med_branch_p" "no,yes"
385 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
388 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
390 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
393 ] (const_string "no")))
395 (define_attr "med_cbranch_p" "no,yes"
396 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
399 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
401 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
404 ] (const_string "no")))
406 (define_attr "braf_branch_p" "no,yes"
407 (cond [(match_test "! TARGET_SH2")
409 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
412 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
414 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
417 ] (const_string "no")))
419 (define_attr "braf_cbranch_p" "no,yes"
420 (cond [(match_test "! TARGET_SH2")
422 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
425 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
427 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
430 ] (const_string "no")))
432 ;; An unconditional jump in the range -4092..4098 can be 2 bytes long.
433 ;; For wider ranges, we need a combination of a code and a data part.
434 ;; If we can get a scratch register for a long range jump, the code
435 ;; part can be 4 bytes long; otherwise, it must be 8 bytes long.
436 ;; If the jump is in the range -32764..32770, the data part can be 2 bytes
437 ;; long; otherwise, it must be 6 bytes long.
439 ;; All other instructions are two bytes long by default.
441 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
442 ;; but getattrtab doesn't understand this.
443 (define_attr "length" ""
444 (cond [(eq_attr "type" "cbranch")
445 (cond [(eq_attr "short_cbranch_p" "yes")
447 (eq_attr "med_cbranch_p" "yes")
449 (eq_attr "braf_cbranch_p" "yes")
451 ;; ??? using pc is not computed transitively.
452 (ne (match_dup 0) (match_dup 0))
454 (match_test "flag_pic")
457 (eq_attr "type" "jump")
458 (cond [(eq_attr "med_branch_p" "yes")
460 (and (match_test "prev_nonnote_insn (insn)")
461 (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
463 (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
464 (symbol_ref "code_for_indirect_jump_scratch"))))
465 (cond [(eq_attr "braf_branch_p" "yes")
467 (not (match_test "flag_pic"))
469 (match_test "TARGET_SH2")
470 (const_int 10)] (const_int 18))
471 (eq_attr "braf_branch_p" "yes")
473 ;; ??? using pc is not computed transitively.
474 (ne (match_dup 0) (match_dup 0))
476 (match_test "flag_pic")
479 (eq_attr "type" "pt_media")
480 (if_then_else (match_test "TARGET_SHMEDIA64")
481 (const_int 20) (const_int 12))
482 (and (eq_attr "type" "jump_media")
483 (match_test "TARGET_SH5_CUT2_WORKAROUND"))
485 ] (if_then_else (match_test "TARGET_SHMEDIA")
489 ;; DFA descriptions for the pipelines
492 (include "shmedia.md")
495 (include "iterators.md")
496 (include "predicates.md")
497 (include "constraints.md")
499 ;; Definitions for filling delay slots
501 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
503 (define_attr "banked" "yes,no"
504 (cond [(match_test "sh_loads_bankedreg_p (insn)")
505 (const_string "yes")]
506 (const_string "no")))
508 ;; ??? This should be (nil) instead of (const_int 0)
509 (define_attr "hit_stack" "yes,no"
510 (cond [(not (match_test "find_regno_note (insn, REG_INC, SP_REG)"))
512 (const_string "yes")))
514 (define_attr "interrupt_function" "no,yes"
515 (const (symbol_ref "current_function_interrupt")))
517 (define_attr "in_delay_slot" "yes,no"
518 (cond [(eq_attr "type" "cbranch") (const_string "no")
519 (eq_attr "type" "pcload,pcload_si") (const_string "no")
520 (eq_attr "type" "fpscr_toggle") (const_string "no")
521 (eq_attr "needs_delay_slot" "yes") (const_string "no")
522 (eq_attr "length" "2") (const_string "yes")
523 ] (const_string "no")))
525 (define_attr "cond_delay_slot" "yes,no"
526 (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
527 ] (const_string "no")))
529 (define_attr "is_sfunc" ""
530 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
532 (define_attr "is_mac_media" ""
533 (if_then_else (eq_attr "type" "mac_media") (const_int 1) (const_int 0)))
535 (define_attr "branch_zero" "yes,no"
536 (cond [(eq_attr "type" "!cbranch") (const_string "no")
537 (ne (symbol_ref "(next_active_insn (insn)\
538 == (prev_active_insn\
539 (XEXP (SET_SRC (PATTERN (insn)), 1))))\
540 && get_attr_length (next_active_insn (insn)) == 2")
542 (const_string "yes")]
543 (const_string "no")))
545 ;; SH4 Double-precision computation with double-precision result -
546 ;; the two halves are ready at different times.
547 (define_attr "dfp_comp" "yes,no"
548 (cond [(eq_attr "type" "dfp_arith,dfp_mul,dfp_conv,dfdiv") (const_string "yes")]
549 (const_string "no")))
551 ;; Insns for which the latency of a preceding fp insn is decreased by one.
552 (define_attr "late_fp_use" "yes,no" (const_string "no"))
553 ;; And feeding insns for which this relevant.
554 (define_attr "any_fp_comp" "yes,no"
555 (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
556 (const_string "yes")]
557 (const_string "no")))
559 (define_attr "any_int_load" "yes,no"
560 (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
561 (const_string "yes")]
562 (const_string "no")))
564 (define_attr "highpart" "user, ignore, extend, depend, must_split"
565 (const_string "user"))
568 (eq_attr "needs_delay_slot" "yes")
569 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
571 ;; Since a normal return (rts) implicitly uses the PR register,
572 ;; we can't allow PR register loads in an rts delay slot.
573 ;; On the SH1* and SH2*, the rte instruction reads the return pc from the
574 ;; stack, and thus we can't put a pop instruction in its delay slot.
575 ;; On the SH3* and SH4*, the rte instruction does not use the stack, so a
576 ;; pop instruction can go in the delay slot, unless it references a banked
577 ;; register (the register bank is switched by rte).
579 (eq_attr "type" "return")
580 [(and (eq_attr "in_delay_slot" "yes")
581 (ior (and (eq_attr "interrupt_function" "no")
582 (eq_attr "type" "!pload,prset"))
583 (and (eq_attr "interrupt_function" "yes")
584 (ior (match_test "TARGET_SH3") (eq_attr "hit_stack" "no"))
585 (eq_attr "banked" "no"))))
588 ;; Since a call implicitly uses the PR register, we can't allow
589 ;; a PR register store in a jsr delay slot.
592 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
593 [(and (eq_attr "in_delay_slot" "yes")
594 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
596 ;; Conditional branches with delay slots are available starting with SH2.
598 (and (eq_attr "type" "cbranch") (match_test "TARGET_SH2"))
599 [(eq_attr "cond_delay_slot" "yes") (nil) (nil)])
601 ;; -------------------------------------------------------------------------
602 ;; SImode signed integer comparisons
603 ;; -------------------------------------------------------------------------
605 ;; Patterns to generate the tst instruction which are usually formed by
607 ;; The canonical form here being used is (eq (and (op) (op)) 0).
608 ;; For some bit patterns, such as contiguous bits, we also must accept
609 ;; zero_extract forms. Single bit tests are also handled via zero_extract
610 ;; patterns in the 'bit field extract patterns' section. All variants
611 ;; are eventually converted to the 'tstsi_t' insn.
612 ;; As long as pseudos can be created (before RA), 'tstsi_t' will also accept
613 ;; constants that won't fit into 8 bits. After having captured the constant
614 ;; we can decide better whether/how to load it into a register and do other
615 ;; post-combine optimizations such as bypassing sign/zero extensions.
616 (define_insn_and_split "tstsi_t"
618 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "%z,r")
619 (match_operand:SI 1 "arith_or_int_operand" "K08,?r"))
622 && (can_create_pseudo_p () || arith_reg_operand (operands[1], SImode)
623 || satisfies_constraint_K08 (operands[1]))"
625 "TARGET_SH1 && can_create_pseudo_p () && CONST_INT_P (operands[1])
626 && !sh_in_recog_treg_set_expr ()"
629 gcc_assert (CONST_INT_P (operands[1]));
631 HOST_WIDE_INT op1val = INTVAL (operands[1]);
632 bool op0_dead_after_this =
633 sh_reg_dead_or_unused_after_insn (curr_insn, REGNO (operands[0]));
639 "tstsi_t: trying to optimize const_int 0x%08x\n",
642 /* See if we can convert a test with a reg and a constant into
643 something simpler, if the reg is known to be zero or sign
645 sh_extending_set_of_reg eop0 = sh_find_extending_set_of_reg (operands[0],
647 if (eop0.ext_code != UNKNOWN)
649 /* Adjust the constant, trying to eliminate bits that are not
650 contributing to the result. */
651 if (eop0.from_mode == QImode)
653 | (eop0.ext_code == SIGN_EXTEND && (op1val & 0xFFFFFF80)
655 else if (eop0.from_mode == HImode)
657 | (eop0.ext_code == SIGN_EXTEND && (op1val & 0xFFFF8000)
658 ? 0x8000 : 0)) & 0xFFFF;
661 fprintf (dump_file, "tstsi_t: using effective const_int: 0x%08x\n",
664 /* Try to bypass the sign/zero extension first if op0 dies after
666 if (op0_dead_after_this && eop0.can_use_as_unextended_reg ())
669 fprintf (dump_file, "tstsi_t: bypassing sign/zero extension\n");
671 operands[0] = eop0.use_as_unextended_reg (curr_insn);
673 else if ((eop0.from_mode == QImode && op1val == 0xFF)
674 || (eop0.from_mode == HImode && op1val == 0xFFFF))
677 fprintf (dump_file, "tstsi_t: converting to cmpeqsi_t\n");
678 emit_insn (gen_cmpeqsi_t (eop0.use_as_extended_reg (curr_insn),
682 else if (eop0.ext_code == SIGN_EXTEND
683 && ((eop0.from_mode == QImode && op1val == 0x80)
684 || (eop0.from_mode == HImode && op1val == 0x8000)))
687 fprintf (dump_file, "tstsi_t: converting to cmpgesi_t\n");
688 emit_insn (gen_cmpgesi_t (eop0.use_as_extended_reg (curr_insn),
692 else if (!CONST_OK_FOR_K08 (op1val))
695 fprintf (dump_file, "tstsi_t: converting const_int to signed "
698 /* If here we haven't done anything yet. Convert the constant
699 to a signed value to reduce the constant pool size. */
700 operands[0] = eop0.use_as_extended_reg (curr_insn);
702 if (eop0.from_mode == QImode)
703 op1val |= (op1val & 0x80) ? 0xFFFFFFFFFFFFFF00LL : 0;
704 else if (eop0.from_mode == HImode)
705 op1val |= (op1val & 0x8000) ? 0xFFFFFFFFFFFF0000LL : 0;
708 operands[0] = eop0.use_as_extended_reg (curr_insn);
713 fprintf (dump_file, "tstsi_t: using const_int 0x%08x\n",
716 /* Try to fit the constant into 8 bits by shuffling the value in the
718 Doing that usually results in smaller code as the constants in the
719 pools are avoided (32 bit constant = load + constant = 6 bytes).
720 However, if the constant load (LS insn) can be hoisted insn dependencies
721 can be avoided and chances for parallel execution increase. The common
727 FIXME: For now we do that only when optimizing for size until there is
730 FIXME: If there are multiple tst insns in the block with the same
731 constant, avoid the #imm variant to avoid R0 loads. Use the 'tst Rn,Rm'
732 variant instead and load the constant into a reg. For that we'd need
733 to do some analysis. */
735 if (CONST_OK_FOR_K08 (op1val))
739 else if ((op1val & 0xFFFF) == 0
740 && CONST_OK_FOR_K08 (op1val >> 16) && optimize_size)
742 /* Use a swap.w insn to do a shift + reg copy (to R0) in one insn. */
743 op1val = op1val >> 16;
744 rtx r = gen_reg_rtx (SImode);
745 emit_insn (gen_rotlsi3_16 (r, operands[0]));
748 else if ((op1val & 0xFF) == 0
749 && CONST_OK_FOR_K08 (op1val >> 8) && optimize_size)
751 /* Use a swap.b insn to do a shift + reg copy (to R0) in one insn. */
752 op1val = op1val >> 8;
753 rtx r = gen_reg_rtx (SImode);
754 emit_insn (gen_swapbsi2 (r, operands[0]));
757 else if ((op1val & 3) == 0
758 && CONST_OK_FOR_K08 (op1val >> 2) && optimize_size)
760 op1val = op1val >> 2;
761 rtx r = gen_reg_rtx (SImode);
762 emit_insn (gen_lshrsi3_k (r, operands[0], GEN_INT (2)));
765 else if ((op1val & 1) == 0
766 && CONST_OK_FOR_K08 (op1val >> 1) && optimize_size)
768 op1val = op1val >> 1;
769 rtx r = gen_reg_rtx (SImode);
770 emit_insn (gen_shlr (r, operands[0]));
774 operands[1] = GEN_INT (op1val);
776 if (!satisfies_constraint_K08 (operands[1]))
777 operands[1] = force_reg (SImode, operands[1]);
779 emit_insn (gen_tstsi_t (operands[0], operands[1]));
782 [(set_attr "type" "mt_group")])
784 ;; This pattern is used by combine when testing QI/HImode subregs with a
785 ;; negative constant. Ignore high bits by masking them out in the constant.
786 (define_insn_and_split "*tst<mode>_t"
789 (and:QIHI (match_operand:QIHI 0 "arith_reg_operand")
790 (match_operand 1 "const_int_operand")) 0)
792 "TARGET_SH1 && can_create_pseudo_p ()"
796 (eq:SI (and:SI (match_dup 0) (match_dup 1)) (const_int 0)))]
798 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
799 operands[1] = GEN_INT (INTVAL (operands[1])
800 & (<MODE>mode == HImode ? 0xFFFF : 0xFF));
803 ;; This pattern might be risky because it also tests the upper bits and not
804 ;; only the subreg. We have to check whether the operands have been sign
805 ;; or zero extended. In the worst case, a zero extension has to be inserted
806 ;; to mask out the unwanted bits.
807 (define_insn_and_split "*tst<mode>_t_subregs"
811 (and:SI (match_operand:SI 0 "arith_reg_operand")
812 (match_operand:SI 1 "arith_reg_operand")) <lowpart_le>)
814 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()"
816 "&& !sh_in_recog_treg_set_expr ()"
819 sh_split_tst_subregs (curr_insn, <MODE>mode, <lowpart_le>, operands);
823 (define_insn_and_split "*tst<mode>_t_subregs"
827 (and:SI (match_operand:SI 0 "arith_reg_operand")
828 (match_operand:SI 1 "arith_reg_operand")) <lowpart_be>)
830 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()"
832 "&& !sh_in_recog_treg_set_expr ()"
835 sh_split_tst_subregs (curr_insn, <MODE>mode, <lowpart_be>, operands);
839 ;; Extract contiguous bits and compare them against zero.
840 ;; Notice that this will not be used for single bits. Special single bit
841 ;; extraction patterns are in the 'bit field extract patterns' section.
842 (define_insn_and_split "*tst<mode>_t_zero_extract"
844 (eq:SI (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
845 (match_operand 1 "const_int_operand")
846 (match_operand 2 "const_int_operand"))
848 "TARGET_SH1 && can_create_pseudo_p ()"
852 (eq:SI (and:SI (match_dup 0) (match_dup 1)) (const_int 0)))]
854 operands[1] = GEN_INT (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]));
855 if (GET_MODE (operands[0]) != SImode)
856 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
859 ;; Convert '(reg << shift) & mask' into 'reg & (mask >> shift)'.
860 ;; The shifted-out bits in the mask will always be zero, since the
861 ;; shifted-in bits in the reg will also be always zero.
862 (define_insn_and_split "*tstsi_t_shift_mask"
864 (eq:SI (and:SI (ashift:SI (match_operand:SI 0 "arith_reg_operand")
865 (match_operand 1 "const_int_operand"))
866 (match_operand 2 "const_int_operand"))
868 "TARGET_SH1 && can_create_pseudo_p ()"
872 (eq:SI (and:SI (match_dup 0) (match_dup 2)) (const_int 0)))]
874 operands[2] = GEN_INT (INTVAL (operands[2]) >> INTVAL (operands[1]));
877 (define_insn "cmpeqsi_t"
879 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
880 (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
886 [(set_attr "type" "mt_group")])
888 ;; Sometimes combine fails to form the (eq (and (op) (op)) 0) tst insn.
889 ;; Try to fix that in the split1 pass by looking for the previous set
890 ;; of the tested op. Also see if there is a preceeding sign/zero
891 ;; extension that can be avoided.
894 (eq:SI (match_operand:SI 0 "arith_reg_operand") (const_int 0)))]
895 "TARGET_SH1 && can_create_pseudo_p () && optimize
896 && !sh_in_recog_treg_set_expr ()"
897 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
900 fprintf (dump_file, "cmpeqsi_t: trying to optimize const_int 0\n");
902 /* If the tested reg is not dead after this insn, it's probably used by
903 something else after the comparison. It's probably better to leave
905 if (find_regno_note (curr_insn, REG_DEAD, REGNO (operands[0])) == NULL_RTX)
908 /* FIXME: Maybe also search the predecessor basic blocks to catch
910 set_of_reg op = sh_find_set_of_reg (operands[0], curr_insn,
911 prev_nonnote_insn_bb);
913 if (op.set_src != NULL && GET_CODE (op.set_src) == AND
914 && !sh_insn_operands_modified_between_p (op.insn, op.insn, curr_insn))
917 fprintf (dump_file, "cmpeqsi_t: found preceeding and in insn %d\n",
920 if (!(arith_reg_operand (XEXP (op.set_src, 0), SImode)
921 && (arith_reg_operand (XEXP (op.set_src, 1), SImode)
922 || CONST_INT_P (XEXP (op.set_src, 1)))))
925 /* Assume that the operands of the andsi insn are compatible with the
926 operands of the tstsi_t insn, which is generally the case. */
928 fprintf (dump_file, "cmpeqsi_t: replacing with tstsi_t\n");
929 emit_insn (gen_tstsi_t (XEXP (op.set_src, 0), XEXP (op.set_src, 1)));
933 /* Converting HImode into tests against 0xFFFF tends to increase the code
934 size, as it will create constant pool entries. Disable it for now. */
935 const bool enable_himode = false;
937 /* FIXME: try to keep the (eq (reg) (const_int 0)). Even if the zero
938 extended reg is used after this insn, if we know that _before_ the zero
939 extension the value was loaded via sign extending mem load, we can just
940 use the value of the mem load directly. */
941 sh_extending_set_of_reg eop = sh_find_extending_set_of_reg (operands[0],
944 if (eop.ext_code != UNKNOWN
945 && (eop.from_mode == QImode || (eop.from_mode == HImode && enable_himode))
946 && eop.can_use_as_unextended_reg ()
947 && !reg_used_between_p (operands[0], eop.insn, curr_insn))
949 /* Bypass the sign/zero extension and test against the bit mask, but
950 only if it's the only use of the sign/zero extracted value.
951 Otherwise we'd be introducing new constants in the pool. */
953 fprintf (dump_file, "cmpeqsi_t: bypassing sign/zero extension in "
954 "insn %d and using tstsi_t\n", INSN_UID (op.insn));
956 emit_insn (gen_tstsi_t (
957 eop.use_as_unextended_reg (curr_insn),
958 GEN_INT (eop.from_mode == QImode ? 0xFF : 0xFFFF)));
963 fprintf (dump_file, "cmpeqsi_t: nothing optimized\n");
967 ;; FIXME: For some reason, on SH4A and SH2A combine fails to simplify this
968 ;; pattern by itself. What this actually does is:
969 ;; x == 0: (1 >> 0-0) & 1 = 1
970 ;; x != 0: (1 >> 0-x) & 1 = 0
971 ;; Without this the test pr51244-8.c fails on SH2A and SH4A.
972 (define_insn_and_split "*cmpeqsi_t"
976 (neg:SI (match_operand:SI 0 "arith_reg_operand" "r")))
981 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))])
983 (define_insn "cmpgtsi_t"
985 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
986 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
991 [(set_attr "type" "mt_group")])
993 (define_insn "cmpgesi_t"
995 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
996 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
1001 [(set_attr "type" "mt_group")])
1003 ;; Recombine a cmp/pz followed by a nott into a shll.
1004 ;; On non-SH2A recombine a cmp/pz followed by a movrt into shll-movt.
1005 ;; On SH2A cmp/pz-movrt is slightly better, as it does not mutate the input.
1007 [(set (reg:SI T_REG)
1008 (ge:SI (match_operand:SI 0 "arith_reg_operand") (const_int 0)))]
1010 "TARGET_SH1 && can_create_pseudo_p () && optimize
1011 && !sh_in_recog_treg_set_expr ()"
1015 fprintf (dump_file, "cmpgesi_t: trying to optimize for const_int 0\n");
1017 rtx_insn* i = next_nonnote_insn_bb (curr_insn);
1021 fprintf (dump_file, "cmpgesi_t: following insn is \n");
1022 print_rtl_single (dump_file, i);
1023 fprintf (dump_file, "\n");
1026 if (sh_is_nott_insn (i))
1030 "cmpgesi_t: replacing (cmp/pz, nott) with (shll)\n");
1031 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
1032 set_insn_deleted (i);
1036 /* On non-SH2A negc is used as movrt replacement, which sets T = 1.
1037 Thus we can remove it only if T is marked as dead afterwards. */
1038 if (rtx dest_reg = !TARGET_SH2A
1039 && sh_reg_dead_or_unused_after_insn (i, T_REG)
1040 ? sh_movrt_set_dest (i) : NULL)
1044 "cmpgesi_t: replacing (cmp/pz, movrt) with (shll, movt)\n");
1045 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
1046 add_reg_note (emit_insn (gen_movt (dest_reg, get_t_reg_rtx ())),
1047 REG_DEAD, get_t_reg_rtx ());
1048 set_insn_deleted (i);
1053 fprintf (dump_file, "cmpgesi_t: nothing optimized\n");
1058 ;; FIXME: This is actually wrong. There is no way to literally move a
1059 ;; general reg to t reg. Luckily, it seems that this pattern will be only
1060 ;; used when the general reg is known be either '0' or '1' during combine.
1061 ;; What we actually need is reg != 0 -> T, but we have only reg == 0 -> T.
1062 ;; Due to interactions with other patterns, combine fails to pick the latter
1063 ;; and invert the dependent logic.
1064 (define_insn "*negtstsi"
1065 [(set (reg:SI T_REG) (match_operand:SI 0 "arith_reg_operand" "r"))]
1066 "TARGET_SH1 && !sh_in_recog_treg_set_expr ()"
1068 [(set_attr "type" "mt_group")])
1070 ;; Some integer sign comparison patterns can be realized with the div0s insn.
1071 ;; div0s Rm,Rn T = (Rm >> 31) ^ (Rn >> 31)
1073 ;; The 'cmp_div0s' pattern is our canonical form, into which all the other
1074 ;; variations are converted. The negative forms will split into a trailing
1075 ;; nott sequence, which will be eliminated either by the
1076 ;; 'any_treg_expr_to_reg' pattern, or by the 'sh_treg_combine' pass.
1077 (define_insn "cmp_div0s"
1078 [(set (reg:SI T_REG)
1079 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
1080 (match_operand:SI 1 "arith_reg_operand" "r"))
1084 [(set_attr "type" "arith")])
1086 (define_insn_and_split "*cmp_div0s_1"
1087 [(set (reg:SI T_REG)
1088 (xor:SI (ge:SI (match_operand:SI 0 "arith_reg_operand")
1090 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1092 "TARGET_SH1 && can_create_pseudo_p ()"
1095 [(set (reg:SI T_REG)
1096 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))])
1098 (define_insn_and_split "*cmp_div0s_2"
1099 [(set (reg:SI T_REG)
1100 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1102 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1104 "TARGET_SH1 && can_create_pseudo_p ()"
1107 [(set (reg:SI T_REG)
1108 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))])
1110 (define_insn_and_split "*cmp_div0s_3"
1111 [(set (reg:SI T_REG)
1112 (eq:SI (ge:SI (match_operand:SI 0 "arith_reg_operand")
1114 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1116 "TARGET_SH1 && can_create_pseudo_p ()"
1119 [(set (reg:SI T_REG)
1120 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1121 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1123 (define_insn_and_split "*cmp_div0s_4"
1124 [(set (reg:SI T_REG)
1125 (ge:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1126 (match_operand:SI 1 "arith_reg_operand"))
1128 "TARGET_SH1 && can_create_pseudo_p ()"
1131 [(set (reg:SI T_REG)
1132 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1133 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1135 (define_insn_and_split "*cmp_div0s_5"
1136 [(set (reg:SI T_REG)
1137 (xor:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1139 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1141 "TARGET_SH1 && can_create_pseudo_p ()"
1144 [(set (reg:SI T_REG)
1145 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1146 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1148 (define_insn_and_split "*cmp_div0s_6"
1149 [(set (reg:SI T_REG)
1150 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1152 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
1154 "TARGET_SH1 && can_create_pseudo_p ()"
1157 [(set (reg:SI T_REG)
1158 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1159 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1161 ;; -------------------------------------------------------------------------
1162 ;; SImode compare and branch
1163 ;; -------------------------------------------------------------------------
1165 (define_expand "cbranchsi4"
1167 (if_then_else (match_operator 0 "comparison_operator"
1168 [(match_operand:SI 1 "arith_operand" "")
1169 (match_operand:SI 2 "arith_operand" "")])
1170 (label_ref (match_operand 3 "" ""))
1172 (clobber (reg:SI T_REG))]
1176 emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1],
1177 operands[2], operands[3]));
1179 expand_cbranchsi4 (operands, LAST_AND_UNUSED_RTX_CODE, -1);
1184 ;; Combine patterns to invert compare and branch operations for which we
1185 ;; don't have actual comparison insns. These patterns are used in cases
1186 ;; which appear after the initial cbranchsi expansion, which also does
1187 ;; some condition inversion.
1190 (if_then_else (ne (match_operand:SI 0 "arith_reg_operand" "")
1191 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1192 (label_ref (match_operand 2))
1194 (clobber (reg:SI T_REG))]
1196 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (match_dup 1)))
1197 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1198 (label_ref (match_dup 2))
1201 ;; FIXME: Similar to the *cmpeqsi_t pattern above, for some reason, on SH4A
1202 ;; and SH2A combine fails to simplify this pattern by itself.
1203 ;; What this actually does is:
1204 ;; x == 0: (1 >> 0-0) & 1 = 1
1205 ;; x != 0: (1 >> 0-x) & 1 = 0
1206 ;; Without this the test pr51244-8.c fails on SH2A and SH4A.
1210 (eq (and:SI (lshiftrt:SI
1212 (neg:SI (match_operand:SI 0 "arith_reg_operand" "")))
1215 (label_ref (match_operand 2))
1217 (clobber (reg:SI T_REG))]
1219 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))
1220 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1221 (label_ref (match_dup 2))
1224 ;; FIXME: These could probably use code iterators for the compare op.
1227 (if_then_else (le (match_operand:SI 0 "arith_reg_operand" "")
1228 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1229 (label_ref (match_operand 2))
1231 (clobber (reg:SI T_REG))]
1233 [(set (reg:SI T_REG) (gt:SI (match_dup 0) (match_dup 1)))
1234 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1235 (label_ref (match_dup 2))
1240 (if_then_else (lt (match_operand:SI 0 "arith_reg_operand" "")
1241 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1242 (label_ref (match_operand 2))
1244 (clobber (reg:SI T_REG))]
1246 [(set (reg:SI T_REG) (ge:SI (match_dup 0) (match_dup 1)))
1247 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1248 (label_ref (match_dup 2))
1253 (if_then_else (leu (match_operand:SI 0 "arith_reg_operand" "")
1254 (match_operand:SI 1 "arith_reg_operand" ""))
1255 (label_ref (match_operand 2))
1257 (clobber (reg:SI T_REG))]
1259 [(set (reg:SI T_REG) (gtu:SI (match_dup 0) (match_dup 1)))
1260 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1261 (label_ref (match_dup 2))
1266 (if_then_else (ltu (match_operand:SI 0 "arith_reg_operand" "")
1267 (match_operand:SI 1 "arith_reg_operand" ""))
1268 (label_ref (match_operand 2))
1270 (clobber (reg:SI T_REG))]
1272 [(set (reg:SI T_REG) (geu:SI (match_dup 0) (match_dup 1)))
1273 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1274 (label_ref (match_dup 2))
1277 ;; -------------------------------------------------------------------------
1278 ;; SImode unsigned integer comparisons
1279 ;; -------------------------------------------------------------------------
1281 ;; Usually comparisons of 'unsigned int >= 0' are optimized away completely.
1282 ;; However, especially when optimizations are off (e.g. -O0) such comparisons
1283 ;; might remain and we have to handle them. If the '>= 0' case wasn't
1284 ;; handled here, something else would just load a '0' into the second operand
1285 ;; and do the comparison. We can do slightly better by just setting the
1287 (define_insn_and_split "cmpgeusi_t"
1288 [(set (reg:SI T_REG)
1289 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1290 (match_operand:SI 1 "arith_reg_or_0_operand" "r")))]
1293 "&& satisfies_constraint_Z (operands[1])"
1294 [(set (reg:SI T_REG) (const_int 1))]
1296 [(set_attr "type" "mt_group")])
1298 (define_insn "cmpgtusi_t"
1299 [(set (reg:SI T_REG)
1300 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1301 (match_operand:SI 1 "arith_reg_operand" "r")))]
1304 [(set_attr "type" "mt_group")])
1306 ;; -------------------------------------------------------------------------
1307 ;; DImode compare and branch
1308 ;; -------------------------------------------------------------------------
1310 ;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism.
1311 ;; Therefore, we aim to have a set of three branches that go straight to the
1312 ;; destination, i.e. only one of them is taken at any one time.
1313 ;; This mechanism should also be slightly better for the sh4-200.
1315 (define_expand "cbranchdi4"
1317 (if_then_else (match_operator 0 "comparison_operator"
1318 [(match_operand:DI 1 "arith_operand" "")
1319 (match_operand:DI 2 "arith_operand" "")])
1320 (label_ref (match_operand 3 "" ""))
1322 (clobber (match_dup 4))
1323 (clobber (reg:SI T_REG))]
1324 "TARGET_CBRANCHDI4 || TARGET_SH2 || TARGET_SHMEDIA"
1326 enum rtx_code comparison;
1330 emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1],
1331 operands[2], operands[3]));
1334 else if (!TARGET_CBRANCHDI4)
1336 sh_emit_compare_and_branch (operands, DImode);
1341 if (expand_cbranchdi4 (operands, LAST_AND_UNUSED_RTX_CODE))
1344 comparison = prepare_cbranch_operands (operands, DImode,
1345 LAST_AND_UNUSED_RTX_CODE);
1346 if (comparison != GET_CODE (operands[0]))
1348 = gen_rtx_fmt_ee (comparison, VOIDmode, operands[1], operands[2]);
1349 operands[4] = gen_rtx_SCRATCH (SImode);
1353 (define_insn_and_split "cbranchdi4_i"
1355 (if_then_else (match_operator 0 "comparison_operator"
1356 [(match_operand:DI 1 "arith_operand" "r,r")
1357 (match_operand:DI 2 "arith_operand" "rN,I08")])
1358 (label_ref (match_operand 3 "" ""))
1360 (clobber (match_scratch:SI 4 "=X,&r"))
1361 (clobber (reg:SI T_REG))]
1364 "&& reload_completed"
1367 if (!expand_cbranchdi4 (operands, GET_CODE (operands[0])))
1372 ;; -------------------------------------------------------------------------
1373 ;; DImode signed integer comparisons
1374 ;; -------------------------------------------------------------------------
1377 [(set (reg:SI T_REG)
1378 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
1379 (match_operand:DI 1 "arith_operand" "r"))
1383 return output_branchy_insn (EQ, "tst\t%S1,%S0;bf\t%l9;tst\t%R1,%R0",
1386 [(set_attr "length" "6")
1387 (set_attr "type" "arith3b")])
1389 (define_insn "cmpeqdi_t"
1390 [(set (reg:SI T_REG)
1391 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1392 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
1395 static const char* alt[] =
1402 "cmp/eq %S1,%S0" "\n"
1404 " cmp/eq %R1,%R0" "\n"
1407 return alt[which_alternative];
1409 [(set_attr "length" "6")
1410 (set_attr "type" "arith3b")])
1413 [(set (reg:SI T_REG)
1414 (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
1415 (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
1416 ;; If we applied this split when not optimizing, it would only be
1417 ;; applied during the machine-dependent reorg, when no new basic blocks
1419 "TARGET_SH1 && reload_completed && optimize"
1420 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
1421 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1422 (label_ref (match_dup 6))
1424 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
1427 operands[2] = gen_highpart (SImode, operands[0]);
1428 operands[3] = operands[1] == const0_rtx
1430 : gen_highpart (SImode, operands[1]);
1431 operands[4] = gen_lowpart (SImode, operands[0]);
1432 operands[5] = gen_lowpart (SImode, operands[1]);
1433 operands[6] = gen_label_rtx ();
1436 (define_insn "cmpgtdi_t"
1437 [(set (reg:SI T_REG)
1438 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1439 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1442 static const char* alt[] =
1444 "cmp/eq %S1,%S0" "\n"
1446 " cmp/gt %S1,%S0" "\n"
1447 " cmp/hi %R1,%R0" "\n"
1453 " cmp/hi %S0,%R0" "\n"
1456 return alt[which_alternative];
1458 [(set_attr "length" "8")
1459 (set_attr "type" "arith3")])
1461 (define_insn "cmpgedi_t"
1462 [(set (reg:SI T_REG)
1463 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1464 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1467 static const char* alt[] =
1469 "cmp/eq %S1,%S0" "\n"
1471 " cmp/ge %S1,%S0" "\n"
1472 " cmp/hs %R1,%R0" "\n"
1477 return alt[which_alternative];
1479 [(set_attr "length" "8,2")
1480 (set_attr "type" "arith3,mt_group")])
1482 ;; -------------------------------------------------------------------------
1483 ;; DImode unsigned integer comparisons
1484 ;; -------------------------------------------------------------------------
1486 (define_insn "cmpgeudi_t"
1487 [(set (reg:SI T_REG)
1488 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1489 (match_operand:DI 1 "arith_reg_operand" "r")))]
1492 return "cmp/eq %S1,%S0" "\n"
1494 " cmp/hs %S1,%S0" "\n"
1495 " cmp/hs %R1,%R0" "\n"
1498 [(set_attr "length" "8")
1499 (set_attr "type" "arith3")])
1501 (define_insn "cmpgtudi_t"
1502 [(set (reg:SI T_REG)
1503 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1504 (match_operand:DI 1 "arith_reg_operand" "r")))]
1507 return "cmp/eq %S1,%S0" "\n"
1509 " cmp/hi %S1,%S0" "\n"
1510 " cmp/hi %R1,%R0" "\n"
1513 [(set_attr "length" "8")
1514 (set_attr "type" "arith3")])
1516 (define_insn "cmpeqsi_media"
1517 [(set (match_operand:SI 0 "register_operand" "=r")
1518 (eq:SI (match_operand:SI 1 "logical_operand" "%r")
1519 (match_operand:SI 2 "cmp_operand" "Nr")))]
1522 [(set_attr "type" "cmp_media")])
1524 (define_insn "cmpeqdi_media"
1525 [(set (match_operand:SI 0 "register_operand" "=r")
1526 (eq:SI (match_operand:DI 1 "register_operand" "%r")
1527 (match_operand:DI 2 "cmp_operand" "Nr")))]
1530 [(set_attr "type" "cmp_media")])
1532 (define_insn "cmpgtsi_media"
1533 [(set (match_operand:SI 0 "register_operand" "=r")
1534 (gt:SI (match_operand:SI 1 "cmp_operand" "Nr")
1535 (match_operand:SI 2 "cmp_operand" "rN")))]
1537 "cmpgt %N1, %N2, %0"
1538 [(set_attr "type" "cmp_media")])
1540 (define_insn "cmpgtdi_media"
1541 [(set (match_operand:SI 0 "register_operand" "=r")
1542 (gt:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
1543 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
1545 "cmpgt %N1, %N2, %0"
1546 [(set_attr "type" "cmp_media")])
1548 (define_insn "cmpgtusi_media"
1549 [(set (match_operand:SI 0 "register_operand" "=r")
1550 (gtu:SI (match_operand:SI 1 "cmp_operand" "Nr")
1551 (match_operand:SI 2 "cmp_operand" "rN")))]
1553 "cmpgtu %N1, %N2, %0"
1554 [(set_attr "type" "cmp_media")])
1556 (define_insn "cmpgtudi_media"
1557 [(set (match_operand:SI 0 "register_operand" "=r")
1558 (gtu:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
1559 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
1561 "cmpgtu %N1, %N2, %0"
1562 [(set_attr "type" "cmp_media")])
1564 ; This pattern is for combine.
1565 (define_insn "*cmpne0sisi_media"
1566 [(set (match_operand:SI 0 "register_operand" "=r")
1567 (ne:SI (match_operand:SI 1 "arith_reg_operand" "r") (const_int 0)))]
1570 [(set_attr "type" "cmp_media")])
1572 ;; -------------------------------------------------------------------------
1573 ;; Conditional move instructions
1574 ;; -------------------------------------------------------------------------
1576 ;; The insn names may seem reversed, but note that cmveq performs the move
1577 ;; if op1 == 0, and cmvne does it if op1 != 0.
1579 (define_insn "movdicc_false"
1580 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1581 (if_then_else:DI (eq (match_operand:DI 1 "arith_reg_operand" "r")
1583 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
1584 (match_operand:DI 3 "arith_reg_operand" "0")))]
1587 [(set_attr "type" "arith_media")])
1589 (define_insn "movdicc_true"
1590 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1591 (if_then_else:DI (ne (match_operand:DI 1 "arith_reg_operand" "r")
1593 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
1594 (match_operand:DI 3 "arith_reg_operand" "0")))]
1597 [(set_attr "type" "arith_media")])
1600 [(set (match_operand:DI 0 "arith_reg_dest" "")
1601 (if_then_else:DI (match_operator 3 "equality_comparison_operator"
1602 [(match_operand:DI 1 "arith_reg_operand" "")
1604 (match_operand:DI 2 "arith_reg_dest" "")
1606 (set (match_dup 2) (match_dup 0))]
1607 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1609 (if_then_else:DI (match_dup 3) (match_dup 0) (match_dup 2)))]
1611 operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
1612 VOIDmode, operands[1], CONST0_RTX (DImode));
1616 [(set (match_operand:DI 0 "general_movdst_operand" "")
1617 (match_operand:DI 1 "arith_reg_or_0_operand" ""))
1618 (set (match_operand:DI 2 "arith_reg_dest" "")
1619 (if_then_else:DI (match_operator 4 "equality_comparison_operator"
1620 [(match_operand:DI 3 "arith_reg_operand" "")
1624 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1626 (if_then_else:DI (match_dup 4) (match_dup 1) (match_dup 2)))]
1629 (define_expand "movdicc"
1630 [(set (match_operand:DI 0 "register_operand" "")
1631 (if_then_else:DI (match_operand 1 "comparison_operator" "")
1632 (match_operand:DI 2 "register_operand" "")
1633 (match_operand:DI 3 "register_operand" "")))]
1636 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
1637 && GET_MODE (XEXP (operands[1], 0)) == DImode
1638 && XEXP (operands[1], 1) == const0_rtx)
1642 if (!can_create_pseudo_p ())
1645 operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
1646 GET_CODE (operands[1]),
1647 XEXP (operands[1], 0),
1648 XEXP (operands[1], 1));
1654 ;; Add SImode variants for cmveq / cmvne to compensate for not promoting
1655 ;; SImode to DImode.
1656 (define_insn "movsicc_false"
1657 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1658 (if_then_else:SI (eq (match_operand:SI 1 "arith_reg_operand" "r")
1660 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1661 (match_operand:SI 3 "arith_reg_operand" "0")))]
1664 [(set_attr "type" "arith_media")])
1666 (define_insn "movsicc_true"
1667 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1668 (if_then_else:SI (ne (match_operand:SI 1 "arith_reg_operand" "r")
1670 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1671 (match_operand:SI 3 "arith_reg_operand" "0")))]
1674 [(set_attr "type" "arith_media")])
1677 [(set (match_operand:SI 0 "arith_reg_dest" "")
1678 (if_then_else:SI (match_operator 3 "equality_comparison_operator"
1679 [(match_operand:SI 1 "arith_reg_operand" "")
1681 (match_operand:SI 2 "arith_reg_dest" "")
1683 (set (match_dup 2) (match_dup 0))]
1684 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1686 (if_then_else:SI (match_dup 3) (match_dup 0) (match_dup 2)))]
1688 operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
1689 VOIDmode, operands[1], CONST0_RTX (SImode));
1693 [(set (match_operand:SI 0 "general_movdst_operand" "")
1694 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1695 (set (match_operand:SI 2 "arith_reg_dest" "")
1696 (if_then_else:SI (match_operator 4 "equality_comparison_operator"
1697 [(match_operand:SI 3 "arith_reg_operand" "")
1701 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])
1702 && (!REG_P (operands[1]) || GENERAL_REGISTER_P (REGNO (operands[1])))"
1704 (if_then_else:SI (match_dup 4) (match_dup 1) (match_dup 2)))]
1706 replace_rtx (operands[4], operands[0], operands[1]);
1709 ;; The register allocator is rather clumsy in handling multi-way conditional
1710 ;; moves, so allow the combiner to make them, and we split them up after
1712 (define_insn_and_split "*movsicc_umin"
1713 [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
1714 (umin:SI (if_then_else:SI
1715 (eq (match_operand:SI 1 "arith_reg_operand" "r")
1717 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1718 (match_operand:SI 3 "register_operand" "0"))
1719 (match_operand:SI 4 "arith_reg_or_0_operand" "r")))
1720 (clobber (match_scratch:SI 5 "=&r"))]
1721 "TARGET_SHMEDIA && !can_create_pseudo_p ()"
1723 "TARGET_SHMEDIA && reload_completed"
1726 emit_insn (gen_movsicc_false (operands[0], operands[1], operands[2],
1728 emit_insn (gen_cmpgtusi_media (operands[5], operands[4], operands[0]));
1729 emit_insn (gen_movsicc_false (operands[0], operands[5], operands[4],
1734 (define_insn "*movsicc_t_false"
1735 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1736 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1737 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1738 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1739 "TARGET_PRETEND_CMOVE
1740 && (arith_reg_operand (operands[1], SImode)
1741 || (immediate_operand (operands[1], SImode)
1742 && satisfies_constraint_I08 (operands[1])))"
1748 [(set_attr "type" "mt_group,arith") ;; poor approximation
1749 (set_attr "length" "4")])
1751 (define_insn "*movsicc_t_true"
1752 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1753 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1754 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1755 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1756 "TARGET_PRETEND_CMOVE
1757 && (arith_reg_operand (operands[1], SImode)
1758 || (immediate_operand (operands[1], SImode)
1759 && satisfies_constraint_I08 (operands[1])))"
1765 [(set_attr "type" "mt_group,arith") ;; poor approximation
1766 (set_attr "length" "4")])
1768 (define_expand "movsicc"
1769 [(set (match_operand:SI 0 "arith_reg_dest" "")
1770 (if_then_else:SI (match_operand 1 "comparison_operator" "")
1771 (match_operand:SI 2 "arith_reg_or_0_operand" "")
1772 (match_operand:SI 3 "arith_reg_operand" "")))]
1773 "TARGET_SHMEDIA || TARGET_PRETEND_CMOVE"
1775 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
1776 && GET_MODE (XEXP (operands[1], 0)) == SImode
1778 || (REG_P (XEXP (operands[1], 0))
1779 && REGNO (XEXP (operands[1], 0)) == T_REG))
1780 && XEXP (operands[1], 1) == const0_rtx)
1783 else if (TARGET_PRETEND_CMOVE)
1785 enum rtx_code code = GET_CODE (operands[1]);
1786 enum rtx_code new_code = code;
1787 rtx op0 = XEXP (operands[1], 0);
1788 rtx op1 = XEXP (operands[1], 1);
1790 if (! currently_expanding_to_rtl)
1794 case LT: case LE: case LEU: case LTU:
1795 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT)
1798 new_code = reverse_condition (code);
1800 case EQ: case GT: case GE: case GEU: case GTU:
1805 sh_emit_scc_to_t (new_code, op0, op1);
1806 operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode,
1807 gen_rtx_REG (SImode, T_REG), const0_rtx);
1811 if (!can_create_pseudo_p ())
1814 operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
1815 GET_CODE (operands[1]),
1816 XEXP (operands[1], 0),
1817 XEXP (operands[1], 1));
1823 (define_expand "movqicc"
1824 [(set (match_operand:QI 0 "register_operand" "")
1825 (if_then_else:QI (match_operand 1 "comparison_operator" "")
1826 (match_operand:QI 2 "register_operand" "")
1827 (match_operand:QI 3 "register_operand" "")))]
1830 operands[0] = simplify_gen_subreg (SImode, operands[0], QImode, 0);
1831 operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0);
1832 operands[3] = simplify_gen_subreg (SImode, operands[3], QImode, 0);
1833 emit (gen_movsicc (operands[0], operands[1], operands[2], operands[3]));
1837 ;; -------------------------------------------------------------------------
1838 ;; Addition instructions
1839 ;; -------------------------------------------------------------------------
1841 (define_expand "adddi3"
1842 [(set (match_operand:DI 0 "arith_reg_operand")
1843 (plus:DI (match_operand:DI 1 "arith_reg_operand")
1844 (match_operand:DI 2 "arith_operand")))]
1849 operands[2] = force_reg (DImode, operands[2]);
1850 emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
1855 (define_insn "*adddi3_media"
1856 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
1857 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1858 (match_operand:DI 2 "arith_operand" "r,I10")))]
1863 [(set_attr "type" "arith_media")])
1865 (define_insn "*adddisi3_media"
1866 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r,r") 0)
1867 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1868 (match_operand:DI 2 "arith_operand" "r,I10")))]
1873 [(set_attr "type" "arith_media")
1874 (set_attr "highpart" "ignore")])
1876 (define_insn "adddi3z_media"
1877 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1879 (plus:SI (match_operand:SI 1 "extend_reg_operand" "r")
1880 (match_operand:SI 2 "extend_reg_or_0_operand" "rN"))))]
1882 "addz.l %1, %N2, %0"
1883 [(set_attr "type" "arith_media")
1884 (set_attr "highpart" "ignore")])
1886 (define_insn_and_split "adddi3_compact"
1887 [(set (match_operand:DI 0 "arith_reg_dest")
1888 (plus:DI (match_operand:DI 1 "arith_reg_operand")
1889 (match_operand:DI 2 "arith_reg_operand")))
1890 (clobber (reg:SI T_REG))]
1893 "&& can_create_pseudo_p ()"
1896 emit_insn (gen_clrt ());
1897 emit_insn (gen_addc (gen_lowpart (SImode, operands[0]),
1898 gen_lowpart (SImode, operands[1]),
1899 gen_lowpart (SImode, operands[2])));
1900 emit_insn (gen_addc (gen_highpart (SImode, operands[0]),
1901 gen_highpart (SImode, operands[1]),
1902 gen_highpart (SImode, operands[2])));
1907 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1908 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1909 (match_operand:SI 2 "arith_reg_operand" "r"))
1912 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
1915 [(set_attr "type" "arith")])
1917 ;; A simplified version of the addc insn, where the exact value of the
1918 ;; T bit doesn't matter. This is easier for combine to pick up.
1919 ;; We allow a reg or 0 for one of the operands in order to be able to
1920 ;; do 'reg + T' sequences.
1921 (define_insn_and_split "*addc"
1922 [(set (match_operand:SI 0 "arith_reg_dest")
1923 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1924 (match_operand:SI 2 "arith_reg_or_0_operand"))
1925 (match_operand 3 "treg_set_expr")))
1926 (clobber (reg:SI T_REG))]
1927 "TARGET_SH1 && can_create_pseudo_p ()"
1932 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
1933 if (ti.has_trailing_nott ())
1935 if (operands[2] == const0_rtx)
1937 /* op1 + 0 + (1 - T) = op1 + 1 - T = op1 - (-1) - T */
1938 remove_insn (ti.trailing_nott ());
1939 emit_insn (gen_subc (operands[0], operands[1],
1940 force_reg (SImode, GEN_INT (-1))));
1943 else if (!TARGET_SH2A)
1945 /* op1 + op2 + (1 - T) = op1 - (0 - op2 - 1) - T = op1 - ~op2 - T
1946 On SH2A keep the nott insn, because nott-addc sequence doesn't
1947 mutate the inputs. */
1948 remove_insn (ti.trailing_nott ());
1949 rtx tmp = gen_reg_rtx (SImode);
1950 emit_insn (gen_one_cmplsi2 (tmp, operands[2]));
1951 emit_insn (gen_subc (operands[0], operands[1], tmp));
1956 emit_insn (gen_addc (operands[0], operands[1],
1957 force_reg (SImode, operands[2])));
1961 (define_insn_and_split "*addc"
1962 [(set (match_operand:SI 0 "arith_reg_dest")
1963 (plus:SI (plus:SI (match_operand 1 "treg_set_expr")
1964 (match_operand:SI 2 "arith_reg_operand"))
1965 (match_operand:SI 3 "arith_reg_operand")))
1966 (clobber (reg:SI T_REG))]
1967 "TARGET_SH1 && can_create_pseudo_p ()"
1970 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1972 (clobber (reg:SI T_REG))])])
1974 (define_insn_and_split "*addc"
1975 [(set (match_operand:SI 0 "arith_reg_dest")
1976 (plus:SI (match_operand 1 "treg_set_expr")
1977 (plus:SI (match_operand:SI 2 "arith_reg_operand")
1978 (match_operand:SI 3 "arith_reg_operand"))))
1979 (clobber (reg:SI T_REG))]
1980 "TARGET_SH1 && can_create_pseudo_p ()"
1983 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1985 (clobber (reg:SI T_REG))])])
1987 ;; Sometimes combine will try to do 'reg + (0-reg) + 1' if the *addc pattern
1988 ;; matched. Split this up into a simple sub add sequence, as this will save
1989 ;; us one sett insn.
1990 (define_insn_and_split "*minus_plus_one"
1991 [(set (match_operand:SI 0 "arith_reg_dest" "")
1992 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
1993 (match_operand:SI 2 "arith_reg_operand" ""))
1998 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
1999 (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))])
2002 ;; The tree optimiziers canonicalize
2007 ;; On SH2A an add-bclr sequence will be used to handle this.
2008 ;; On non-SH2A re-emit the add-and sequence to improve register utilization.
2009 (define_insn_and_split "*round_int_even"
2010 [(set (match_operand:SI 0 "arith_reg_dest")
2011 (and:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
2014 "TARGET_SH1 && !TARGET_SH2A && can_create_pseudo_p ()
2015 && !reg_overlap_mentioned_p (operands[0], operands[1])"
2018 [(set (match_dup 0) (const_int -2))
2019 (set (match_dup 2) (plus:SI (match_dup 1) (const_int 1)))
2020 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))]
2022 operands[2] = gen_reg_rtx (SImode);
2025 ;; If the *round_int_even pattern is combined with another plus,
2026 ;; convert it into an addc pattern to emit an shlr-addc sequence.
2027 ;; This split is taken by combine on non-SH2A and SH2A.
2029 [(set (match_operand:SI 0 "arith_reg_dest")
2030 (plus:SI (and:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
2033 (match_operand:SI 2 "arith_reg_operand")))]
2034 "TARGET_SH1 && can_create_pseudo_p ()"
2035 [(parallel [(set (match_dup 0)
2036 (plus:SI (plus:SI (match_dup 1) (match_dup 2))
2037 (and:SI (match_dup 1) (const_int 1))))
2038 (clobber (reg:SI T_REG))])])
2040 ;; Split 'reg + T' into 'reg + 0 + T' to utilize the addc insn.
2041 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
2042 ;; operation, as opposed to sequences such as
2046 ;; Even if the constant is not CSE-ed, a sequence such as
2049 ;; can be scheduled much better since the load of the constant can be
2050 ;; done earlier, before any comparison insns that store the result in
2052 ;; However, avoid things like 'reg + 1', which would expand into a
2053 ;; 3 insn sequence, instead of add #imm8.
2054 (define_insn_and_split "*addc_t_r"
2055 [(set (match_operand:SI 0 "arith_reg_dest")
2056 (plus:SI (match_operand 1 "treg_set_expr_not_const01")
2057 (match_operand:SI 2 "arith_reg_operand")))
2058 (clobber (reg:SI T_REG))]
2059 "TARGET_SH1 && can_create_pseudo_p ()"
2062 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (const_int 0))
2064 (clobber (reg:SI T_REG))])])
2066 (define_insn_and_split "*addc_r_t"
2067 [(set (match_operand:SI 0 "arith_reg_dest")
2068 (plus:SI (match_operand:SI 1 "arith_reg_operand")
2069 (match_operand 2 "treg_set_expr_not_const01")))
2070 (clobber (reg:SI T_REG))]
2071 "TARGET_SH1 && can_create_pseudo_p ()"
2074 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (const_int 0))
2076 (clobber (reg:SI T_REG))])])
2078 ;; Convert '2 * reg + T' into 'reg + reg + T'.
2079 (define_insn_and_split "*addc_2r_t"
2080 [(set (match_operand:SI 0 "arith_reg_dest")
2081 (plus:SI (match_operand 1 "treg_set_expr")
2082 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
2084 (clobber (reg:SI T_REG))]
2085 "TARGET_SH1 && can_create_pseudo_p ()"
2088 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 2))
2090 (clobber (reg:SI T_REG))])])
2092 (define_insn_and_split "*addc_2r_t"
2093 [(set (match_operand:SI 0 "arith_reg_dest")
2094 (plus:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
2096 (match_operand 2 "treg_set_expr")))
2097 (clobber (reg:SI T_REG))]
2098 "TARGET_SH1 && can_create_pseudo_p ()"
2101 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 1))
2103 (clobber (reg:SI T_REG))])])
2105 ;; Convert '(op2 + T) - op3' into 'op2 + (-op3) + T'
2106 (define_insn_and_split "*addc_negreg_t"
2107 [(set (match_operand:SI 0 "arith_reg_dest")
2108 (minus:SI (plus:SI (match_operand 1 "treg_set_expr")
2109 (match_operand:SI 2 "arith_reg_operand"))
2110 (match_operand:SI 3 "arith_reg_operand")))
2111 (clobber (reg:SI T_REG))]
2112 "TARGET_SH1 && can_create_pseudo_p ()"
2115 [(set (match_dup 4) (neg:SI (match_dup 3)))
2116 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 4))
2118 (clobber (reg:SI T_REG))])]
2120 operands[4] = gen_reg_rtx (SImode);
2123 (define_expand "addsi3"
2124 [(set (match_operand:SI 0 "arith_reg_operand" "")
2125 (plus:SI (match_operand:SI 1 "arith_operand" "")
2126 (match_operand:SI 2 "arith_or_int_operand" "")))]
2130 operands[1] = force_reg (SImode, operands[1]);
2131 else if (! arith_operand (operands[2], SImode))
2133 if (reg_overlap_mentioned_p (operands[0], operands[1]))
2138 (define_insn "addsi3_media"
2139 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
2140 (plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r")
2141 (match_operand:SI 2 "arith_operand" "r,I10")))]
2146 [(set_attr "type" "arith_media")
2147 (set_attr "highpart" "ignore")])
2149 (define_insn "addsidi3_media"
2150 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
2151 (sign_extend:DI (plus:SI (match_operand:SI 1 "extend_reg_operand"
2153 (match_operand:SI 2 "arith_operand"
2159 [(set_attr "type" "arith_media")
2160 (set_attr "highpart" "ignore")])
2162 ;; The *addsi3_compact is made an insn_and_split and accepts actually
2163 ;; impossible constraints to make LRA's register elimination work well on SH.
2164 ;; The problem is that LRA expects something like
2165 ;; (set rA (plus rB (const_int N)))
2166 ;; to work. We can do that, but we have to split out an additional reg-reg
2167 ;; copy or constant load before the actual add insn.
2168 ;; Use u constraint for that case to avoid the invalid value in the stack
2170 (define_insn_and_split "*addsi3_compact"
2171 [(set (match_operand:SI 0 "arith_reg_dest" "=r,&u")
2172 (plus:SI (match_operand:SI 1 "arith_operand" "%0,r")
2173 (match_operand:SI 2 "arith_or_int_operand" "rI08,rn")))]
2175 && ((rtx_equal_p (operands[0], operands[1])
2176 && arith_operand (operands[2], SImode))
2177 || ! reg_overlap_mentioned_p (operands[0], operands[1]))"
2182 && ! reg_overlap_mentioned_p (operands[0], operands[1])"
2183 [(set (match_dup 0) (match_dup 2))
2184 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
2186 /* Prefer 'mov r0,r1; add #imm8,r1' over 'mov #imm8,r1; add r0,r1' */
2187 if (satisfies_constraint_I08 (operands[2]))
2188 std::swap (operands[1], operands[2]);
2190 [(set_attr "type" "arith")])
2192 ;; -------------------------------------------------------------------------
2193 ;; Subtraction instructions
2194 ;; -------------------------------------------------------------------------
2196 (define_expand "subdi3"
2197 [(set (match_operand:DI 0 "arith_reg_operand" "")
2198 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "")
2199 (match_operand:DI 2 "arith_reg_operand" "")))]
2204 operands[1] = force_reg (DImode, operands[1]);
2205 emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2]));
2210 (define_insn "*subdi3_media"
2211 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2212 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
2213 (match_operand:DI 2 "arith_reg_operand" "r")))]
2216 [(set_attr "type" "arith_media")])
2218 (define_insn "subdisi3_media"
2219 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
2220 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
2221 (match_operand:DI 2 "arith_reg_operand" "r")))]
2224 [(set_attr "type" "arith_media")
2225 (set_attr "highpart" "ignore")])
2227 (define_insn_and_split "subdi3_compact"
2228 [(set (match_operand:DI 0 "arith_reg_dest")
2229 (minus:DI (match_operand:DI 1 "arith_reg_operand")
2230 (match_operand:DI 2 "arith_reg_operand")))
2231 (clobber (reg:SI T_REG))]
2234 "&& can_create_pseudo_p ()"
2237 emit_insn (gen_clrt ());
2238 emit_insn (gen_subc (gen_lowpart (SImode, operands[0]),
2239 gen_lowpart (SImode, operands[1]),
2240 gen_lowpart (SImode, operands[2])));
2241 emit_insn (gen_subc (gen_highpart (SImode, operands[0]),
2242 gen_highpart (SImode, operands[1]),
2243 gen_highpart (SImode, operands[2])));
2248 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2249 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2250 (match_operand:SI 2 "arith_reg_operand" "r"))
2253 (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
2258 [(set_attr "type" "arith")])
2260 ;; A simplified version of the subc insn, where the exact value of the
2261 ;; T bit doesn't matter. This is easier for combine to pick up.
2262 ;; We allow a reg or 0 for one of the operands in order to be able to
2263 ;; do 'reg - T' sequences. Reload will load the constant 0 into the reg
2265 (define_insn_and_split "*subc"
2266 [(set (match_operand:SI 0 "arith_reg_dest")
2267 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
2268 (match_operand:SI 2 "arith_reg_or_0_operand"))
2269 (match_operand 3 "treg_set_expr")))
2270 (clobber (reg:SI T_REG))]
2271 "TARGET_SH1 && can_create_pseudo_p ()"
2276 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
2277 if (ti.has_trailing_nott ())
2279 if (operands[2] == const0_rtx)
2281 /* op1 - (1 - T) = op1 - 1 + T = op1 + (-1) + T */
2282 remove_insn (ti.trailing_nott ());
2283 emit_insn (gen_addc (operands[0], operands[1],
2284 force_reg (SImode, GEN_INT (-1))));
2287 else if (!TARGET_SH2A)
2289 /* op1 - op2 - (1 - T) = op1 + (0 - op2 - 1) + T = op1 + ~op2 + T
2290 On SH2A keep the nott insn, because nott-subc sequence doesn't
2291 mutate the inputs. */
2292 remove_insn (ti.trailing_nott ());
2293 rtx tmp = gen_reg_rtx (SImode);
2294 emit_insn (gen_one_cmplsi2 (tmp, operands[2]));
2295 emit_insn (gen_addc (operands[0], operands[1], tmp));
2300 emit_insn (gen_subc (operands[0], operands[1],
2301 force_reg (SImode, operands[2])));
2305 ;; Convert reg - T - reg = reg - reg - T
2306 (define_insn_and_split "*subc"
2307 [(set (match_operand:SI 0 "arith_reg_dest")
2308 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
2309 (match_operand 2 "treg_set_expr"))
2310 (match_operand:SI 3 "arith_reg_operand")))
2311 (clobber (reg:SI T_REG))]
2312 "TARGET_SH1 && can_create_pseudo_p ()"
2315 [(parallel [(set (match_dup 0)
2316 (minus:SI (minus:SI (match_dup 1) (match_dup 3))
2318 (clobber (reg:SI T_REG))])])
2320 ;; Split reg - reg - 1 into a sett subc sequence, as it can be scheduled
2321 ;; better, if the sett insn can be done early.
2322 ;; Notice that combine turns 'a - b - 1' into 'a + (~b)'.
2323 (define_insn_and_split "*subc"
2324 [(set (match_operand:SI 0 "arith_reg_dest" "")
2325 (plus:SI (not:SI (match_operand:SI 1 "arith_reg_operand" ""))
2326 (match_operand:SI 2 "arith_reg_operand" "")))
2327 (clobber (reg:SI T_REG))]
2328 "TARGET_SH1 && can_create_pseudo_p ()"
2331 [(parallel [(set (match_dup 0)
2332 (minus:SI (minus:SI (match_dup 2) (match_dup 1))
2334 (clobber (reg:SI T_REG))])])
2336 ;; Split 'reg - T' into 'reg - 0 - T' to utilize the subc insn.
2337 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
2338 ;; operation, as opposed to sequences such as
2342 ;; Even if the constant is not CSE-ed, a sequence such as
2345 ;; can be scheduled much better since the load of the constant can be
2346 ;; done earlier, before any comparison insns that store the result in
2348 ;; However, avoid things like 'reg - 1', which would expand into a
2349 ;; 3 insn sequence, instead of add #imm8.
2350 (define_insn_and_split "*subc"
2351 [(set (match_operand:SI 0 "arith_reg_dest" "")
2352 (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
2353 (match_operand 2 "treg_set_expr_not_const01")))
2354 (clobber (reg:SI T_REG))]
2355 "TARGET_SH1 && can_create_pseudo_p ()"
2358 [(parallel [(set (match_dup 0)
2359 (minus:SI (minus:SI (match_dup 1) (const_int 0))
2361 (clobber (reg:SI T_REG))])])
2364 ;; (1 - T) - op2 = 1 - op2 - T
2365 (define_insn_and_split "*subc_negt_reg"
2366 [(set (match_operand:SI 0 "arith_reg_dest")
2367 (minus:SI (match_operand 1 "treg_set_expr_not_const01")
2368 (match_operand:SI 2 "arith_reg_operand")))
2369 (clobber (reg:SI T_REG))]
2370 "TARGET_SH1 && can_create_pseudo_p ()"
2375 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
2376 if (ti.remove_trailing_nott ())
2378 /* (1 - T) - op2 = 1 - op2 - T */
2379 emit_insn (gen_subc (operands[0],
2380 force_reg (SImode, GEN_INT (1)), operands[2]));
2384 /* T - op2: use movt,sub sequence. */
2385 rtx tmp = gen_reg_rtx (SImode);
2386 emit_insn (gen_movt (tmp, get_t_reg_rtx ()));
2387 emit_insn (gen_subsi3 (operands[0], tmp, operands[2]));
2393 ;; op1 - (1 - T) + op3 = op1 - 1 + T + op3
2394 ;; (op1 - T) + op3 = op1 - (-op3) - T
2395 (define_insn_and_split "*subc_negreg_t"
2396 [(set (match_operand:SI 0 "arith_reg_dest")
2397 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
2398 (match_operand 2 "treg_set_expr"))
2399 (match_operand:SI 3 "arith_reg_operand")))
2400 (clobber (reg:SI T_REG))]
2401 "TARGET_SH1 && can_create_pseudo_p ()"
2406 sh_treg_insns ti = sh_split_treg_set_expr (operands[2], curr_insn);
2407 if (ti.remove_trailing_nott ())
2409 /* op1 - (1 - T) + op3 = (op1 - 1) + op3 + T */
2410 rtx tmp = gen_reg_rtx (SImode);
2411 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (-1)));
2412 emit_insn (gen_addc (operands[0], tmp, operands[3]));
2416 /* (op1 - T) + op3' = 'op1 - (-op3) - T */
2417 rtx tmp = gen_reg_rtx (SImode);
2418 emit_insn (gen_negsi2 (tmp, operands[3]));
2419 emit_insn (gen_subc (operands[0], operands[1], tmp));
2424 (define_insn "*subsi3_internal"
2425 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2426 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2427 (match_operand:SI 2 "arith_reg_operand" "r")))]
2430 [(set_attr "type" "arith")])
2432 (define_insn_and_split "*subsi3_media"
2433 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2434 (minus:SI (match_operand:SI 1 "minuend_operand" "rN")
2435 (match_operand:SI 2 "extend_reg_operand" "r")))]
2437 && (operands[1] != constm1_rtx
2438 || (GET_CODE (operands[2]) != TRUNCATE
2439 && GET_CODE (operands[2]) != SUBREG))"
2441 "operands[1] == constm1_rtx"
2442 [(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))]
2444 [(set_attr "type" "arith_media")
2445 (set_attr "highpart" "ignore")])
2448 [(set (match_operand:SI 0 "arith_reg_dest" "")
2449 (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
2450 "general_extend_operand"
2452 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
2453 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
2454 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
2458 [(set (match_operand:SI 0 "arith_reg_dest" "")
2459 (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
2460 "general_extend_operand"
2462 "TARGET_SHMEDIA && TARGET_BIG_ENDIAN"
2463 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
2464 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
2472 ;; since this will sometimes save one instruction.
2473 ;; Otherwise we might get a sequence like
2477 ;; if the source and dest regs are the same.
2478 (define_expand "subsi3"
2479 [(set (match_operand:SI 0 "arith_reg_operand" "")
2480 (minus:SI (match_operand:SI 1 "arith_operand" "")
2481 (match_operand:SI 2 "arith_reg_operand" "")))]
2484 if (TARGET_SH1 && CONST_INT_P (operands[1]))
2486 emit_insn (gen_negsi2 (operands[0], operands[2]));
2487 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
2492 if (!can_create_pseudo_p ()
2493 && ! arith_reg_or_0_operand (operands[1], SImode))
2495 if (operands[1] != const0_rtx && GET_CODE (operands[1]) != SUBREG)
2496 operands[1] = force_reg (SImode, operands[1]);
2500 ;; -------------------------------------------------------------------------
2501 ;; Division instructions
2502 ;; -------------------------------------------------------------------------
2504 ;; We take advantage of the library routines which don't clobber as many
2505 ;; registers as a normal function call would.
2507 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
2508 ;; also has an effect on the register that holds the address of the sfunc.
2509 ;; To make this work, we have an extra dummy insn that shows the use
2510 ;; of this register for reorg.
2512 (define_insn "use_sfunc_addr"
2513 [(set (reg:SI PR_REG)
2514 (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
2515 "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
2517 [(set_attr "length" "0")])
2519 (define_insn "udivsi3_sh2a"
2520 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2521 (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0")
2522 (match_operand:SI 2 "arith_reg_operand" "z")))]
2525 [(set_attr "type" "arith")
2526 (set_attr "in_delay_slot" "no")])
2528 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
2529 ;; hard register 0. If we used hard register 0, then the next instruction
2530 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
2531 ;; gets allocated to a stack slot that needs its address reloaded, then
2532 ;; there is nothing to prevent reload from using r0 to reload the address.
2533 ;; This reload would clobber the value in r0 we are trying to store.
2534 ;; If we let reload allocate r0, then this problem can never happen.
2535 (define_insn "udivsi3_i1"
2536 [(set (match_operand:SI 0 "register_operand" "=z")
2537 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2538 (clobber (reg:SI T_REG))
2539 (clobber (reg:SI PR_REG))
2540 (clobber (reg:SI R1_REG))
2541 (clobber (reg:SI R4_REG))
2542 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2543 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2545 [(set_attr "type" "sfunc")
2546 (set_attr "needs_delay_slot" "yes")])
2548 ; Since shmedia-nofpu code could be linked against shcompact code, and
2549 ; the udivsi3 libcall has the same name, we must consider all registers
2550 ; clobbered that are in the union of the registers clobbered by the
2551 ; shmedia and the shcompact implementation. Note, if the shcompact
2552 ; implementation actually used shcompact code, we'd need to clobber
2553 ; also r23 and fr23.
2554 (define_insn "udivsi3_i1_media"
2555 [(set (match_operand:SI 0 "register_operand" "=z")
2556 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2557 (clobber (reg:SI T_MEDIA_REG))
2558 (clobber (reg:SI PR_MEDIA_REG))
2559 (clobber (reg:SI R20_REG))
2560 (clobber (reg:SI R21_REG))
2561 (clobber (reg:SI R22_REG))
2562 (clobber (reg:DI TR0_REG))
2563 (clobber (reg:DI TR1_REG))
2564 (clobber (reg:DI TR2_REG))
2565 (use (match_operand 1 "target_reg_operand" "b"))]
2566 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2568 [(set_attr "type" "sfunc")
2569 (set_attr "needs_delay_slot" "yes")])
2571 (define_expand "udivsi3_i4_media"
2573 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
2575 (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
2576 (set (match_dup 5) (float:DF (match_dup 3)))
2577 (set (match_dup 6) (float:DF (match_dup 4)))
2578 (set (match_dup 7) (div:DF (match_dup 5) (match_dup 6)))
2579 (set (match_dup 8) (fix:DI (match_dup 7)))
2580 (set (match_operand:SI 0 "register_operand" "")
2581 (truncate:SI (match_dup 8)))]
2582 "TARGET_SHMEDIA_FPU"
2584 operands[3] = gen_reg_rtx (DImode);
2585 operands[4] = gen_reg_rtx (DImode);
2586 operands[5] = gen_reg_rtx (DFmode);
2587 operands[6] = gen_reg_rtx (DFmode);
2588 operands[7] = gen_reg_rtx (DFmode);
2589 operands[8] = gen_reg_rtx (DImode);
2592 (define_insn "udivsi3_i4"
2593 [(set (match_operand:SI 0 "register_operand" "=y")
2594 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2595 (clobber (reg:SI T_REG))
2596 (clobber (reg:SI PR_REG))
2597 (clobber (reg:DF DR0_REG))
2598 (clobber (reg:DF DR2_REG))
2599 (clobber (reg:DF DR4_REG))
2600 (clobber (reg:SI R0_REG))
2601 (clobber (reg:SI R1_REG))
2602 (clobber (reg:SI R4_REG))
2603 (clobber (reg:SI R5_REG))
2604 (clobber (reg:SI FPSCR_STAT_REG))
2605 (use (match_operand:SI 1 "arith_reg_operand" "r"))
2606 (use (reg:SI FPSCR_MODES_REG))]
2607 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2609 [(set_attr "type" "sfunc")
2610 (set_attr "fp_mode" "double")
2611 (set_attr "needs_delay_slot" "yes")])
2613 (define_insn "udivsi3_i4_single"
2614 [(set (match_operand:SI 0 "register_operand" "=y")
2615 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2616 (clobber (reg:SI T_REG))
2617 (clobber (reg:SI PR_REG))
2618 (clobber (reg:DF DR0_REG))
2619 (clobber (reg:DF DR2_REG))
2620 (clobber (reg:DF DR4_REG))
2621 (clobber (reg:SI R0_REG))
2622 (clobber (reg:SI R1_REG))
2623 (clobber (reg:SI R4_REG))
2624 (clobber (reg:SI R5_REG))
2625 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2626 "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
2627 && TARGET_FPU_SINGLE"
2629 [(set_attr "type" "sfunc")
2630 (set_attr "needs_delay_slot" "yes")])
2632 (define_insn "udivsi3_i4_int"
2633 [(set (match_operand:SI 0 "register_operand" "=z")
2634 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2635 (clobber (reg:SI T_REG))
2636 (clobber (reg:SI R1_REG))
2637 (clobber (reg:SI PR_REG))
2638 (clobber (reg:SI MACH_REG))
2639 (clobber (reg:SI MACL_REG))
2640 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2643 [(set_attr "type" "sfunc")
2644 (set_attr "needs_delay_slot" "yes")])
2647 (define_expand "udivsi3"
2648 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
2649 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
2650 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
2651 (parallel [(set (match_operand:SI 0 "register_operand" "")
2652 (udiv:SI (reg:SI R4_REG)
2654 (clobber (reg:SI T_REG))
2655 (clobber (reg:SI PR_REG))
2656 (clobber (reg:SI R4_REG))
2657 (use (match_dup 3))])]
2662 operands[3] = gen_reg_rtx (Pmode);
2663 /* Emit the move of the address to a pseudo outside of the libcall. */
2664 if (TARGET_DIVIDE_CALL_TABLE)
2666 /* libgcc2:__udivmoddi4 is not supposed to use an actual division, since
2667 that causes problems when the divide code is supposed to come from a
2668 separate library. Division by zero is undefined, so dividing 1 can be
2669 implemented by comparing with the divisor. */
2670 if (operands[1] == const1_rtx && currently_expanding_to_rtl)
2672 rtx test = gen_rtx_GEU (VOIDmode, operands[1], operands[2]);
2673 emit_insn (gen_cstoresi4 (operands[0], test,
2674 operands[1], operands[2]));
2677 else if (operands[2] == const0_rtx)
2679 emit_move_insn (operands[0], operands[2]);
2682 function_symbol (operands[3], "__udivsi3_i4i", SFUNC_GOT);
2683 last = gen_udivsi3_i4_int (operands[0], operands[3]);
2685 else if (TARGET_DIVIDE_CALL_FP)
2687 function_symbol (operands[3], "__udivsi3_i4", SFUNC_STATIC);
2688 if (TARGET_FPU_SINGLE)
2689 last = gen_udivsi3_i4_single (operands[0], operands[3]);
2691 last = gen_udivsi3_i4 (operands[0], operands[3]);
2693 else if (TARGET_SHMEDIA_FPU)
2695 operands[1] = force_reg (SImode, operands[1]);
2696 operands[2] = force_reg (SImode, operands[2]);
2697 emit_insn (gen_udivsi3_i4_media (operands[0], operands[1], operands[2]));
2700 else if (TARGET_SH2A)
2702 operands[1] = force_reg (SImode, operands[1]);
2703 operands[2] = force_reg (SImode, operands[2]);
2704 emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2]));
2707 else if (TARGET_SH5)
2709 function_symbol (operands[3],
2710 TARGET_FPU_ANY ? "__udivsi3_i4" : "__udivsi3",
2714 last = gen_udivsi3_i1_media (operands[0], operands[3]);
2715 else if (TARGET_FPU_ANY)
2716 last = gen_udivsi3_i4_single (operands[0], operands[3]);
2718 last = gen_udivsi3_i1 (operands[0], operands[3]);
2722 function_symbol (operands[3], "__udivsi3", SFUNC_STATIC);
2723 last = gen_udivsi3_i1 (operands[0], operands[3]);
2725 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2726 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2731 (define_insn "divsi3_sh2a"
2732 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2733 (div:SI (match_operand:SI 1 "arith_reg_operand" "0")
2734 (match_operand:SI 2 "arith_reg_operand" "z")))]
2737 [(set_attr "type" "arith")
2738 (set_attr "in_delay_slot" "no")])
2740 (define_insn "divsi3_i1"
2741 [(set (match_operand:SI 0 "register_operand" "=z")
2742 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2743 (clobber (reg:SI T_REG))
2744 (clobber (reg:SI PR_REG))
2745 (clobber (reg:SI R1_REG))
2746 (clobber (reg:SI R2_REG))
2747 (clobber (reg:SI R3_REG))
2748 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2749 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2751 [(set_attr "type" "sfunc")
2752 (set_attr "needs_delay_slot" "yes")])
2754 (define_insn "divsi3_i1_media"
2755 [(set (match_operand:SI 0 "register_operand" "=z")
2756 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2757 (clobber (reg:SI T_MEDIA_REG))
2758 (clobber (reg:SI PR_MEDIA_REG))
2759 (clobber (reg:SI R1_REG))
2760 (clobber (reg:SI R20_REG))
2761 (clobber (reg:SI R21_REG))
2762 (clobber (reg:SI TR0_REG))
2763 (use (match_operand 1 "target_reg_operand" "b"))]
2764 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2766 [(set_attr "type" "sfunc")])
2768 (define_insn "divsi3_media_2"
2769 [(set (match_operand:SI 0 "register_operand" "=z")
2770 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2771 (clobber (reg:SI T_MEDIA_REG))
2772 (clobber (reg:SI PR_MEDIA_REG))
2773 (clobber (reg:SI R1_REG))
2774 (clobber (reg:SI R21_REG))
2775 (clobber (reg:SI TR0_REG))
2776 (use (reg:SI R20_REG))
2777 (use (match_operand 1 "target_reg_operand" "b"))]
2778 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2780 [(set_attr "type" "sfunc")])
2782 ;; This pattern acts as a placeholder for -mdiv=inv:call to carry
2783 ;; hard reg clobbers and data dependencies that we need when we want
2784 ;; to rematerialize the division into a call.
2785 (define_insn_and_split "divsi_inv_call"
2786 [(set (match_operand:SI 0 "register_operand" "=r")
2787 (div:SI (match_operand:SI 1 "register_operand" "r")
2788 (match_operand:SI 2 "register_operand" "r")))
2789 (clobber (reg:SI R4_REG))
2790 (clobber (reg:SI R5_REG))
2791 (clobber (reg:SI T_MEDIA_REG))
2792 (clobber (reg:SI PR_MEDIA_REG))
2793 (clobber (reg:SI R1_REG))
2794 (clobber (reg:SI R21_REG))
2795 (clobber (reg:SI TR0_REG))
2796 (clobber (reg:SI R20_REG))
2797 (use (match_operand:SI 3 "register_operand" "r"))]
2800 "&& (reload_in_progress || reload_completed)"
2801 [(set (match_dup 0) (match_dup 3))]
2803 [(set_attr "highpart" "must_split")])
2805 ;; This is the combiner pattern for -mdiv=inv:call .
2806 (define_insn_and_split "*divsi_inv_call_combine"
2807 [(set (match_operand:SI 0 "register_operand" "=z")
2808 (div:SI (match_operand:SI 1 "register_operand" "r")
2809 (match_operand:SI 2 "register_operand" "r")))
2810 (clobber (reg:SI R4_REG))
2811 (clobber (reg:SI R5_REG))
2812 (clobber (reg:SI T_MEDIA_REG))
2813 (clobber (reg:SI PR_MEDIA_REG))
2814 (clobber (reg:SI R1_REG))
2815 (clobber (reg:SI R21_REG))
2816 (clobber (reg:SI TR0_REG))
2817 (clobber (reg:SI R20_REG))
2818 (use (unspec:SI [(match_dup 1)
2819 (match_operand:SI 3 "" "")
2820 (unspec:SI [(match_operand:SI 4 "" "")
2822 (match_operand:DI 5 "" "")]
2824 (match_operand:DI 6 "" "")
2827 UNSPEC_DIV_INV_M3))]
2830 "&& (reload_in_progress || reload_completed)"
2833 const char *name = sh_divsi3_libfunc;
2834 enum sh_function_kind kind = SFUNC_GOT;
2837 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
2838 emit_move_insn (gen_rtx_REG (SImode, R5_REG), operands[2]);
2839 while (TARGET_DIVIDE_INV_CALL2)
2841 rtx x = operands[3];
2843 if (GET_CODE (x) != UNSPEC || XINT (x, 1) != UNSPEC_DIV_INV_M1)
2845 x = XVECEXP (x, 0, 0);
2846 name = "__sdivsi3_2";
2847 kind = SFUNC_STATIC;
2848 emit_move_insn (gen_rtx_REG (DImode, R20_REG), x);
2851 sym = function_symbol (NULL, name, kind);
2852 emit_insn (gen_divsi3_media_2 (operands[0], sym));
2855 [(set_attr "highpart" "must_split")])
2857 (define_expand "divsi3_i4_media"
2858 [(set (match_dup 3) (float:DF (match_operand:SI 1 "register_operand" "r")))
2859 (set (match_dup 4) (float:DF (match_operand:SI 2 "register_operand" "r")))
2860 (set (match_dup 5) (div:DF (match_dup 3) (match_dup 4)))
2861 (set (match_operand:SI 0 "register_operand" "=r")
2862 (fix:SI (match_dup 5)))]
2863 "TARGET_SHMEDIA_FPU"
2865 operands[3] = gen_reg_rtx (DFmode);
2866 operands[4] = gen_reg_rtx (DFmode);
2867 operands[5] = gen_reg_rtx (DFmode);
2870 (define_insn "divsi3_i4"
2871 [(set (match_operand:SI 0 "register_operand" "=y")
2872 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2873 (clobber (reg:SI PR_REG))
2874 (clobber (reg:DF DR0_REG))
2875 (clobber (reg:DF DR2_REG))
2876 (clobber (reg:SI FPSCR_STAT_REG))
2877 (use (match_operand:SI 1 "arith_reg_operand" "r"))
2878 (use (reg:SI FPSCR_MODES_REG))]
2879 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2881 [(set_attr "type" "sfunc")
2882 (set_attr "fp_mode" "double")
2883 (set_attr "needs_delay_slot" "yes")])
2885 (define_insn "divsi3_i4_single"
2886 [(set (match_operand:SI 0 "register_operand" "=y")
2887 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2888 (clobber (reg:SI PR_REG))
2889 (clobber (reg:DF DR0_REG))
2890 (clobber (reg:DF DR2_REG))
2891 (clobber (reg:SI R2_REG))
2892 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2893 "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
2894 && TARGET_FPU_SINGLE"
2896 [(set_attr "type" "sfunc")
2897 (set_attr "needs_delay_slot" "yes")])
2899 (define_insn "divsi3_i4_int"
2900 [(set (match_operand:SI 0 "register_operand" "=z")
2901 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2902 (clobber (reg:SI T_REG))
2903 (clobber (reg:SI PR_REG))
2904 (clobber (reg:SI R1_REG))
2905 (clobber (reg:SI MACH_REG))
2906 (clobber (reg:SI MACL_REG))
2907 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2910 [(set_attr "type" "sfunc")
2911 (set_attr "needs_delay_slot" "yes")])
2913 (define_expand "divsi3"
2914 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
2915 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
2916 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
2917 (parallel [(set (match_operand:SI 0 "register_operand" "")
2918 (div:SI (reg:SI R4_REG)
2920 (clobber (reg:SI T_REG))
2921 (clobber (reg:SI PR_REG))
2922 (clobber (reg:SI R1_REG))
2923 (clobber (reg:SI R2_REG))
2924 (clobber (reg:SI R3_REG))
2925 (use (match_dup 3))])]
2930 operands[3] = gen_reg_rtx (Pmode);
2931 /* Emit the move of the address to a pseudo outside of the libcall. */
2932 if (TARGET_DIVIDE_CALL_TABLE)
2934 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2935 last = gen_divsi3_i4_int (operands[0], operands[3]);
2937 else if (TARGET_DIVIDE_CALL_FP)
2939 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
2940 if (TARGET_FPU_SINGLE)
2941 last = gen_divsi3_i4_single (operands[0], operands[3]);
2943 last = gen_divsi3_i4 (operands[0], operands[3]);
2945 else if (TARGET_SH2A)
2947 operands[1] = force_reg (SImode, operands[1]);
2948 operands[2] = force_reg (SImode, operands[2]);
2949 emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2]));
2952 else if (TARGET_DIVIDE_INV)
2954 rtx dividend = operands[1];
2955 rtx divisor = operands[2];
2957 rtx nsb_res = gen_reg_rtx (DImode);
2958 rtx norm64 = gen_reg_rtx (DImode);
2959 rtx tab_ix = gen_reg_rtx (DImode);
2960 rtx norm32 = gen_reg_rtx (SImode);
2961 rtx i92 = force_reg (DImode, GEN_INT (92));
2962 rtx scratch0a = gen_reg_rtx (DImode);
2963 rtx scratch0b = gen_reg_rtx (DImode);
2964 rtx inv0 = gen_reg_rtx (SImode);
2965 rtx scratch1a = gen_reg_rtx (DImode);
2966 rtx scratch1b = gen_reg_rtx (DImode);
2967 rtx shift = gen_reg_rtx (DImode);
2969 rtx inv1 = gen_reg_rtx (SImode);
2970 rtx scratch2a = gen_reg_rtx (DImode);
2971 rtx scratch2b = gen_reg_rtx (SImode);
2972 rtx inv2 = gen_reg_rtx (SImode);
2973 rtx scratch3a = gen_reg_rtx (DImode);
2974 rtx scratch3b = gen_reg_rtx (DImode);
2975 rtx scratch3c = gen_reg_rtx (DImode);
2976 rtx scratch3d = gen_reg_rtx (SImode);
2977 rtx scratch3e = gen_reg_rtx (DImode);
2978 rtx result = gen_reg_rtx (SImode);
2980 if (! arith_reg_or_0_operand (dividend, SImode))
2981 dividend = force_reg (SImode, dividend);
2982 if (! arith_reg_operand (divisor, SImode))
2983 divisor = force_reg (SImode, divisor);
2984 if (flag_pic && Pmode != DImode)
2986 tab_base = gen_rtx_SYMBOL_REF (Pmode, "__div_table");
2987 tab_base = gen_datalabel_ref (tab_base);
2988 tab_base = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, tab_base));
2992 tab_base = gen_rtx_SYMBOL_REF (DImode, "__div_table");
2993 tab_base = gen_datalabel_ref (tab_base);
2994 tab_base = force_reg (DImode, tab_base);
2996 if (TARGET_DIVIDE_INV20U)
2997 i2p27 = force_reg (DImode, GEN_INT (-2 << 27));
2999 i2p27 = GEN_INT (0);
3000 if (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)
3001 i43 = force_reg (DImode, GEN_INT (43));
3004 emit_insn (gen_nsbdi (nsb_res,
3005 simplify_gen_subreg (DImode, divisor, SImode, 0)));
3006 emit_insn (gen_ashldi3_media (norm64,
3007 gen_rtx_SUBREG (DImode, divisor, 0),
3009 emit_insn (gen_ashrdi3_media (tab_ix, norm64, GEN_INT (58)));
3010 emit_insn (gen_ashrdisi3_media_high (norm32, norm64, GEN_INT (32)));
3011 emit_insn (gen_divsi_inv_m1 (inv1, tab_base, tab_ix, norm32,
3012 inv0, scratch0a, scratch0b,
3013 scratch1a, scratch1b));
3014 emit_insn (gen_subdi3 (shift, i92, nsb_res));
3015 emit_insn (gen_divsi_inv_m2 (inv2, norm32, inv1, i92,
3017 emit_insn (gen_divsi_inv_m3 (result, dividend, inv1, inv2, shift,
3019 scratch3a, scratch3b, scratch3c,
3020 scratch2a, scratch2b, scratch3d, scratch3e));
3021 if (TARGET_DIVIDE_INV_CALL || TARGET_DIVIDE_INV_CALL2)
3022 emit_insn (gen_divsi_inv_call (operands[0], dividend, divisor, result));
3023 else if (TARGET_DIVIDE_INV_FP)
3024 emit_insn (gen_divsi_inv_fp (operands[0], dividend, divisor, result,
3025 gen_reg_rtx (SImode), gen_reg_rtx (SImode),
3026 gen_reg_rtx (DFmode), gen_reg_rtx (DFmode),
3027 gen_reg_rtx (DFmode)));
3029 emit_move_insn (operands[0], result);
3032 else if (TARGET_SHMEDIA_FPU && TARGET_DIVIDE_FP)
3034 operands[1] = force_reg (SImode, operands[1]);
3035 operands[2] = force_reg (SImode, operands[2]);
3036 emit_insn (gen_divsi3_i4_media (operands[0], operands[1], operands[2]));
3039 else if (TARGET_SH5)
3041 if (TARGET_DIVIDE_CALL2)
3043 rtx tab_base = gen_rtx_SYMBOL_REF (Pmode, "__div_table");
3044 tab_base = gen_datalabel_ref (tab_base);
3045 emit_move_insn (gen_rtx_REG (Pmode, R20_REG), tab_base);
3047 if (TARGET_FPU_ANY && TARGET_SH1)
3048 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
3049 else if (TARGET_DIVIDE_CALL2)
3050 function_symbol (operands[3], "__sdivsi3_2", SFUNC_STATIC);
3052 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
3055 last = ((TARGET_DIVIDE_CALL2 ? gen_divsi3_media_2 : gen_divsi3_i1_media)
3056 (operands[0], operands[3]));
3057 else if (TARGET_FPU_ANY)
3058 last = gen_divsi3_i4_single (operands[0], operands[3]);
3060 last = gen_divsi3_i1 (operands[0], operands[3]);
3064 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
3065 last = gen_divsi3_i1 (operands[0], operands[3]);
3067 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
3068 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
3073 ;; operands: scratch, tab_base, tab_ix
3074 ;; These are unspecs because we could generate an indexed addressing mode
3075 ;; even if -m5-32media, where INDEX_REG_CLASS == NO_REGS, and this would
3076 ;; confuse reload. See PR27117.
3077 (define_insn "divsi_inv_qitable"
3078 [(set (match_operand:DI 0 "register_operand" "=r")
3079 (zero_extend:DI (unspec:QI [(match_operand:DI 1 "register_operand" "r")
3080 (match_operand:DI 2 "register_operand" "r")]
3081 UNSPEC_DIV_INV_TABLE)))]
3084 [(set_attr "type" "load_media")
3085 (set_attr "highpart" "user")])
3087 ;; operands: scratch, tab_base, tab_ix
3088 (define_insn "divsi_inv_hitable"
3089 [(set (match_operand:DI 0 "register_operand" "=r")
3090 (sign_extend:DI (unspec:HI [(match_operand:DI 1 "register_operand" "r")
3091 (match_operand:DI 2 "register_operand" "r")]
3092 UNSPEC_DIV_INV_TABLE)))]
3095 [(set_attr "type" "load_media")
3096 (set_attr "highpart" "user")])
3098 ;; operands: inv0, tab_base, tab_ix, norm32
3099 ;; scratch equiv in sdivsi3_2: r19, r21
3100 (define_expand "divsi_inv_m0"
3101 [(set (match_operand:SI 0 "register_operand" "=r")
3102 (unspec:SI [(match_operand:DI 1 "register_operand" "r")
3103 (match_operand:DI 2 "register_operand" "r")
3104 (match_operand:SI 3 "register_operand" "r")]
3106 (clobber (match_operand:DI 4 "register_operand" "=r"))
3107 (clobber (match_operand:DI 5 "register_operand" "=r"))]
3114 ldx.ub r20, r21, r19 // u0.8
3116 muls.l r25, r19, r19 // s2.38
3117 ldx.w r20, r21, r21 // s2.14
3118 shari r19, 24, r19 // truncate to s2.14
3119 sub r21, r19, r19 // some 11 bit inverse in s1.14
3122 rtx inv0 = operands[0];
3123 rtx tab_base = operands[1];
3124 rtx tab_ix = operands[2];
3125 rtx norm32 = operands[3];
3126 rtx scratch0 = operands[4];
3127 rtx scratch0_si = gen_lowpart (SImode, scratch0);
3128 rtx scratch1 = operands[5];
3130 emit_insn (gen_divsi_inv_qitable (scratch0, tab_base, tab_ix));
3131 emit_insn (gen_ashldi3_media (scratch1, tab_ix, GEN_INT (1)));
3132 emit_insn (gen_mulsidi3_media (scratch0, norm32, scratch0_si));
3133 emit_insn (gen_divsi_inv_hitable (scratch1, tab_base, scratch1));
3134 emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (24)));
3135 emit_insn (gen_subdisi3_media (inv0, scratch1, scratch0));
3139 ;; operands: inv1, tab_base, tab_ix, norm32
3140 (define_insn_and_split "divsi_inv_m1"
3141 [(set (match_operand:SI 0 "register_operand" "=r")
3142 (unspec:SI [(match_operand:DI 1 "register_operand" "r")
3143 (match_operand:DI 2 "register_operand" "r")
3144 (match_operand:SI 3 "register_operand" "r")]
3146 (clobber (match_operand:SI 4 "register_operand" "=r"))
3147 (clobber (match_operand:DI 5 "register_operand" "=r"))
3148 (clobber (match_operand:DI 6 "register_operand" "=r"))
3149 (clobber (match_operand:DI 7 "register_operand" "=r"))
3150 (clobber (match_operand:DI 8 "register_operand" "=r"))]
3153 "&& !can_create_pseudo_p ()"
3157 muls.l r19, r19, r18 // u0.28
3158 muls.l r25, r18, r18 // s2.58
3159 shlli r19, 45, r0 // multiply by two and convert to s2.58
3161 shari r18, 28, r18 // some 18 bit inverse in s1.30
3164 rtx inv1 = operands[0];
3165 rtx tab_base = operands[1];
3166 rtx tab_ix = operands[2];
3167 rtx norm32 = operands[3];
3168 rtx inv0 = operands[4];
3169 rtx inv0_di = simplify_gen_subreg (DImode, inv0, SImode, 0);
3170 rtx scratch0a = operands[5];
3171 rtx scratch0b = operands[6];
3172 rtx scratch0 = operands[7];
3173 rtx scratch1 = operands[8];
3174 rtx scratch1_si = gen_lowpart (SImode, scratch1);
3176 emit_insn (gen_divsi_inv_m0 (inv0, tab_base, tab_ix, norm32,
3177 scratch0a, scratch0b));
3178 emit_insn (gen_mulsidi3_media (scratch1, inv0, inv0));
3179 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
3180 emit_insn (gen_ashldi3_media (scratch0, inv0_di, GEN_INT (45)));
3181 emit_insn (gen_subdi3 (scratch1, scratch0, scratch1));
3182 emit_insn (gen_ashrdisi3_media_opaque (inv1, scratch1, GEN_INT (28)));
3186 ;; operands: inv2, norm32, inv1, i92
3187 (define_insn_and_split "divsi_inv_m2"
3188 [(set (match_operand:SI 0 "register_operand" "=r")
3189 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
3190 (match_operand:SI 2 "register_operand" "r")
3191 (match_operand:DI 3 "register_operand" "r")]
3193 (clobber (match_operand:DI 4 "register_operand" "=r"))]
3196 "&& !can_create_pseudo_p ()"
3200 muls.l r18, r25, r0 // s2.60
3201 shari r0, 16, r0 // s-16.44
3203 muls.l r0, r18, r19 // s-16.74
3204 shari r19, 30, r19 // s-16.44
3206 rtx inv2 = operands[0];
3207 rtx norm32 = operands[1];
3208 rtx inv1 = operands[2];
3209 rtx i92 = operands[3];
3210 rtx scratch0 = operands[4];
3211 rtx scratch0_si = gen_lowpart (SImode, scratch0);
3213 emit_insn (gen_mulsidi3_media (scratch0, inv1, norm32));
3214 emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (16)));
3215 emit_insn (gen_subdi3 (scratch0, i92, scratch0));
3216 emit_insn (gen_mulsidi3_media (scratch0, scratch0_si, inv1));
3217 emit_insn (gen_ashrdisi3_media_opaque (inv2, scratch0, GEN_INT (30)));
3221 (define_insn_and_split "divsi_inv_m3"
3222 [(set (match_operand:SI 0 "register_operand" "=r")
3223 (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
3224 (match_operand:SI 2 "register_operand" "r")
3225 (match_operand:SI 3 "register_operand" "r")
3226 (match_operand:DI 4 "register_operand" "r")
3227 (match_operand:DI 5 "arith_reg_or_0_operand" "rN")
3228 (match_operand:DI 6 "arith_reg_or_0_operand" "rN")]
3230 (clobber (match_operand:DI 7 "register_operand" "=r"))
3231 (clobber (match_operand:DI 8 "register_operand" "=r"))
3232 (clobber (match_operand:DI 9 "register_operand" "=r"))
3233 (clobber (match_operand:DI 10 "register_operand" "=r"))
3234 (clobber (match_operand:SI 11 "register_operand" "=r"))
3235 (clobber (match_operand:SI 12 "register_operand" "=r"))
3236 (clobber (match_operand:DI 13 "register_operand" "=r"))]
3239 "&& !can_create_pseudo_p ()"
3243 r0: result r1: shift r4: dividend r18: inv1 r19: inv2
3244 r0: scratch0 r19: scratch1 r21: scratch2
3246 muls.l r18, r4, r25 // s32.30
3247 muls.l r19, r4, r19 // s15.30
3249 shari r19, 14, r19 // s18.-14
3255 rtx result = operands[0];
3256 rtx dividend = operands[1];
3257 rtx inv1 = operands[2];
3258 rtx inv2 = operands[3];
3259 rtx shift = operands[4];
3260 rtx scratch0 = operands[7];
3261 rtx scratch1 = operands[8];
3262 rtx scratch2 = operands[9];
3264 if (satisfies_constraint_N (dividend))
3266 emit_move_insn (result, dividend);
3270 emit_insn (gen_mulsidi3_media (scratch0, inv1, dividend));
3271 emit_insn (gen_mulsidi3_media (scratch1, inv2, dividend));
3272 emit_insn (gen_ashrdi3_media (scratch2, scratch0, GEN_INT (63)));
3273 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (14)));
3274 emit_insn (gen_adddi3 (scratch0, scratch0, scratch1));
3275 emit_insn (gen_ashrdi3_media (scratch0, scratch0, shift));
3276 emit_insn (gen_subdisi3_media (result, scratch0, scratch2));
3280 ;; operands: quotient, dividend, inv1, inv2, shift, i2p27, i43
3281 ;; inv1: tab_base, tab_ix, norm32
3282 ;; inv2: norm32, inv1, i92
3283 (define_insn_and_split "divsi_inv_m1_3"
3284 [(set (match_operand:SI 0 "register_operand" "=r")
3285 (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
3286 (unspec:SI [(match_operand:DI 2 "register_operand" "r")
3287 (match_operand:DI 3 "register_operand" "r")
3288 (match_operand:SI 4 "register_operand" "r")]
3290 (unspec:SI [(match_dup 4)
3291 (unspec:SI [(match_dup 2)
3293 (match_dup 4)] UNSPEC_DIV_INV_M1)
3294 (match_operand:SI 5 "" "")]
3296 (match_operand:DI 6 "register_operand" "r")
3297 (match_operand:DI 7 "arith_reg_or_0_operand" "rN")
3298 (match_operand:DI 8 "arith_reg_or_0_operand" "rN")]
3300 (clobber (match_operand:DI 9 "register_operand" "=r"))
3301 (clobber (match_operand:DI 10 "register_operand" "=r"))
3302 (clobber (match_operand:DI 11 "register_operand" "=r"))
3303 (clobber (match_operand:DI 12 "register_operand" "=r"))
3304 (clobber (match_operand:SI 13 "register_operand" "=r"))
3305 (clobber (match_operand:SI 14 "register_operand" "=r"))
3306 (clobber (match_operand:DI 15 "register_operand" "=r"))]
3308 && (TARGET_DIVIDE_INV_MINLAT
3309 || TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
3311 "&& !can_create_pseudo_p ()"
3314 rtx result = operands[0];
3315 rtx dividend = operands[1];
3316 rtx tab_base = operands[2];
3317 rtx tab_ix = operands[3];
3318 rtx norm32 = operands[4];
3319 /* rtx i92 = operands[5]; */
3320 rtx shift = operands[6];
3321 rtx i2p27 = operands[7];
3322 rtx i43 = operands[8];
3323 rtx scratch0 = operands[9];
3324 rtx scratch0_si = gen_lowpart (SImode, scratch0);
3325 rtx scratch1 = operands[10];
3326 rtx scratch1_si = gen_lowpart (SImode, scratch1);
3327 rtx scratch2 = operands[11];
3328 rtx scratch3 = operands[12];
3329 rtx scratch4 = operands[13];
3330 rtx scratch4_di = simplify_gen_subreg (DImode, scratch4, SImode, 0);
3331 rtx scratch5 = operands[14];
3332 rtx scratch5_di = simplify_gen_subreg (DImode, scratch5, SImode, 0);
3333 rtx scratch6 = operands[15];
3335 emit_insn (gen_divsi_inv_m0 (scratch4, tab_base, tab_ix, norm32,
3336 scratch0, scratch1));
3337 /* inv0 == scratch4 */
3338 if (! TARGET_DIVIDE_INV20U)
3340 emit_insn (gen_mulsidi3_media (scratch0, scratch4, scratch4));
3342 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch0_si));
3346 emit_insn (gen_mulsidi3_media (scratch1, scratch4, scratch4));
3347 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
3349 emit_insn (gen_ashldi3_media (scratch2, scratch4_di, GEN_INT (45)));
3350 emit_insn (gen_subdi3 (scratch1, scratch2, scratch1));
3351 emit_insn (gen_ashrdisi3_media_opaque (scratch4, scratch1, GEN_INT (28)));
3352 /* inv1 == scratch4 */
3354 if (TARGET_DIVIDE_INV_MINLAT)
3356 emit_insn (gen_mulsidi3_media (scratch1, scratch4, norm32));
3357 emit_insn (gen_mulsidi3_media (scratch2, dividend, scratch4));
3358 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (16)));
3359 emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch4));
3360 emit_insn (gen_ashrdi3_media (scratch3, scratch2, GEN_INT (63)));
3361 emit_insn (gen_ashrsi3_media (scratch5, dividend, GEN_INT (14)));
3362 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (30)));
3363 emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch5));
3364 emit_insn (gen_xordi3 (scratch0, scratch3, i2p27));
3365 emit_insn (gen_adddi3 (scratch2, scratch2, scratch0));
3366 emit_insn (gen_subdi3 (scratch2, scratch2, scratch1));
3370 rtx label = gen_rtx_LABEL_REF (Pmode, gen_label_rtx ());
3371 /* Use separate scratch regs for nsb and sign to allow scheduling. */
3372 emit_insn (gen_nsbdi (scratch6,
3373 simplify_gen_subreg (DImode, dividend, SImode, 0)));
3374 emit_insn (gen_xorsi3 (scratch5, dividend, norm32));
3375 emit_insn (gen_ashrdi3_media (scratch3, scratch5_di, GEN_INT (63)));
3376 emit_insn (gen_divsi_inv20 (scratch2,
3377 norm32, scratch4, dividend,
3378 scratch6, scratch3, i43,
3379 /* scratch0 may be shared with i2p27. */
3380 scratch0, scratch1, scratch5,
3381 label, label, i2p27));
3383 emit_insn (gen_ashrdi3_media (scratch2, scratch2, shift));
3384 emit_insn (gen_subdisi3_media (result, scratch2, scratch3));
3388 (define_insn "divsi_inv20"
3389 [(set (match_operand:DI 0 "register_operand" "=&r")
3390 (unspec:DI [(match_operand:SI 1 "register_operand" "r")
3391 (match_operand:SI 2 "register_operand" "r")
3392 (match_operand:SI 3 "register_operand" "r")
3393 (match_operand:DI 4 "register_operand" "r")
3394 (match_operand:DI 5 "register_operand" "r")
3395 (match_operand:DI 6 "register_operand" "r")
3396 (match_operand:DI 12 "register_operand" "r")
3397 (match_operand 10 "target_operand" "b")
3398 (match_operand 11 "immediate_operand" "i")]
3400 (clobber (match_operand:DI 7 "register_operand" "=&r"))
3401 (clobber (match_operand:DI 8 "register_operand" "=&r"))
3402 (clobber (match_operand:SI 9 "register_operand" "=r"))]
3404 && (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
3406 /* operands: %0 div_result, %1 norm32, %2 inv1, %3 dividend,
3407 %4 dividend_nsb, %5 result_sign, %6 i43, %12 i2p27,
3408 %7 round_scratch, %8 scratch0 (di), %9 scratch1 (si)
3409 %10 label (tr), %11 label (imm)
3411 muls.l inv1, norm32, scratch0 // s2.60
3412 muls.l inv1, dividend, result // s32.30
3413 xor i2p27, result_sign, round_scratch
3414 bge/u dividend_nsb, i43, tr.. (label)
3415 shari scratch0, 16, scratch0 // s-16.44
3416 muls.l sratch0_si, inv1, scratch0 // s-16.74
3417 sub result, round_scratch, result
3418 shari dividend, 14, scratch1 // s19.-14
3419 shari scratch0, 30, scratch0 // s-16.44
3420 muls.l scratch0, scratch1, round_scratch // s15.30
3422 sub result, round_scratch, result */
3424 const bool likely = TARGET_DIVIDE_INV20L;
3427 "muls.l %2, %3, %0" "\n"
3428 " xor %12, %5, %7" "\n"
3429 " bge/l %4, %6, %10" "\n"
3430 " muls.l %2, %1, %8" "\n"
3431 " shari %8, 16, %8" "\n"
3432 " muls.l %8, %2, %8" "\n"
3433 " shari %3, 14, %9" "\n"
3434 " shari %8, 30, %8" "\n"
3435 " muls.l %8, %9, %8" "\n"
3436 " sub %0, %8, %0" "\n"
3437 "%11: add %0, %7, %0";
3440 "muls.l %2, %1, %8" "\n"
3441 " muls.l %2, %3, %0" "\n"
3442 " xor %12, %5, %7" "\n"
3443 " bge/u %4, %6, %10" "\n"
3444 " shari %8, 16, %8" "\n"
3445 " muls.l %8, %2, %8" "\n"
3446 " sub %0, %7, %0" "\n"
3447 " shari %3, 14, %9" "\n"
3448 " shari %8, 30, %8" "\n"
3449 " muls.l %8, %9, %7" "\n"
3450 "%11: sub %0, %7, %0";
3453 (define_insn_and_split "divsi_inv_fp"
3454 [(set (match_operand:SI 0 "general_movdst_operand" "=rf")
3455 (div:SI (match_operand:SI 1 "general_movsrc_operand" "rf")
3456 (match_operand:SI 2 "register_operand" "rf")))
3457 (use (match_operand:SI 3 "general_movsrc_operand" "r"))
3458 (clobber (match_operand:SI 4 "register_operand" "=r"))
3459 (clobber (match_operand:SI 5 "register_operand" "=r"))
3460 (clobber (match_operand:DF 6 "register_operand" "=r"))
3461 (clobber (match_operand:DF 7 "register_operand" "=r"))
3462 (clobber (match_operand:DF 8 "register_operand" "=r"))]
3463 "TARGET_SHMEDIA_FPU"
3465 "&& (reload_in_progress || reload_completed)"
3466 [(set (match_dup 0) (match_dup 3))]
3468 [(set_attr "highpart" "must_split")])
3470 ;; If a matching group of divide-by-inverse instructions is in the same
3471 ;; basic block after gcse & loop optimizations, we want to transform them
3472 ;; to a straight division using floating point for TARGET_DIVIDE_INV_FP.
3473 (define_insn_and_split "*divsi_inv_fp_combine"
3474 [(set (match_operand:SI 0 "register_operand" "=f")
3475 (div:SI (match_operand:SI 1 "register_operand" "f")
3476 (match_operand:SI 2 "register_operand" "f")))
3477 (use (unspec:SI [(match_dup 1)
3478 (match_operand:SI 3 "" "")
3479 (unspec:SI [(match_operand:SI 4 "" "")
3481 (match_operand:DI 5 "" "")] UNSPEC_DIV_INV_M2)
3482 (match_operand:DI 6 "" "")
3484 (const_int 0)] UNSPEC_DIV_INV_M3))
3485 (clobber (match_operand:SI 7 "fp_arith_reg_operand" ""))
3486 (clobber (match_operand:SI 8 "fp_arith_reg_operand" ""))
3487 (clobber (match_operand:DF 9 "fp_arith_reg_operand" ""))
3488 (clobber (match_operand:DF 10 "fp_arith_reg_operand" ""))
3489 (clobber (match_operand:DF 11 "fp_arith_reg_operand" ""))]
3490 "TARGET_SHMEDIA_FPU && TARGET_DIVIDE_INV_FP && !can_create_pseudo_p ()"
3493 [(set (match_dup 9) (float:DF (match_dup 1)))
3494 (set (match_dup 10) (float:DF (match_dup 2)))
3495 (set (match_dup 11) (div:DF (match_dup 9) (match_dup 10)))
3497 (fix:SI (match_dup 11)))
3498 (set (match_dup 0) (match_dup 8))]
3500 if (! fp_arith_reg_operand (operands[1], SImode))
3502 emit_move_insn (operands[7], operands[1]);
3503 operands[1] = operands[7];
3505 if (! fp_arith_reg_operand (operands[2], SImode))
3507 emit_move_insn (operands[8], operands[2]);
3508 operands[2] = operands[8];
3511 [(set_attr "highpart" "must_split")])
3513 ;; -------------------------------------------------------------------------
3514 ;; Multiplication instructions
3515 ;; -------------------------------------------------------------------------
3517 (define_insn "umulhisi3_i"
3518 [(set (reg:SI MACL_REG)
3519 (mult:SI (zero_extend:SI
3520 (match_operand:HI 0 "arith_reg_operand" "r"))
3522 (match_operand:HI 1 "arith_reg_operand" "r"))))]
3525 [(set_attr "type" "smpy")])
3527 (define_insn "mulhisi3_i"
3528 [(set (reg:SI MACL_REG)
3529 (mult:SI (sign_extend:SI
3530 (match_operand:HI 0 "arith_reg_operand" "r"))
3532 (match_operand:HI 1 "arith_reg_operand" "r"))))]
3535 [(set_attr "type" "smpy")])
3537 (define_expand "mulhisi3"
3538 [(set (reg:SI MACL_REG)
3539 (mult:SI (sign_extend:SI
3540 (match_operand:HI 1 "arith_reg_operand" ""))
3542 (match_operand:HI 2 "arith_reg_operand" ""))))
3543 (set (match_operand:SI 0 "arith_reg_operand" "")
3550 macl = gen_rtx_REG (SImode, MACL_REG);
3552 emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
3553 insn = get_insns ();
3555 /* expand_binop can't find a suitable code in umul_widen_optab to
3556 make a REG_EQUAL note from, so make one here.
3557 See also smulsi3_highpart.
3558 ??? Alternatively, we could put this at the calling site of expand_binop,
3559 i.e. expand_expr. */
3560 /* Use emit_libcall_block for loop invariant code motion and to make
3561 a REG_EQUAL note. */
3562 emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
3567 (define_expand "umulhisi3"
3568 [(set (reg:SI MACL_REG)
3569 (mult:SI (zero_extend:SI
3570 (match_operand:HI 1 "arith_reg_operand" ""))
3572 (match_operand:HI 2 "arith_reg_operand" ""))))
3573 (set (match_operand:SI 0 "arith_reg_operand" "")
3580 macl = gen_rtx_REG (SImode, MACL_REG);
3582 emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
3583 insn = get_insns ();
3585 /* expand_binop can't find a suitable code in umul_widen_optab to
3586 make a REG_EQUAL note from, so make one here.
3587 See also smulsi3_highpart.
3588 ??? Alternatively, we could put this at the calling site of expand_binop,
3589 i.e. expand_expr. */
3590 /* Use emit_libcall_block for loop invariant code motion and to make
3591 a REG_EQUAL note. */
3592 emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
3597 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
3598 ;; a call to a routine which clobbers known registers.
3600 [(set (match_operand:SI 1 "register_operand" "=z")
3601 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
3602 (clobber (reg:SI MACL_REG))
3603 (clobber (reg:SI T_REG))
3604 (clobber (reg:SI PR_REG))
3605 (clobber (reg:SI R3_REG))
3606 (clobber (reg:SI R2_REG))
3607 (clobber (reg:SI R1_REG))
3608 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
3611 [(set_attr "type" "sfunc")
3612 (set_attr "needs_delay_slot" "yes")])
3614 (define_expand "mulsi3_call"
3615 [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
3616 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
3617 (parallel[(set (match_operand:SI 0 "register_operand" "")
3618 (mult:SI (reg:SI R4_REG)
3620 (clobber (reg:SI MACL_REG))
3621 (clobber (reg:SI T_REG))
3622 (clobber (reg:SI PR_REG))
3623 (clobber (reg:SI R3_REG))
3624 (clobber (reg:SI R2_REG))
3625 (clobber (reg:SI R1_REG))
3626 (use (match_operand:SI 3 "register_operand" ""))])]
3630 (define_insn "mul_r"
3631 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3632 (mult:SI (match_operand:SI 1 "arith_reg_operand" "0")
3633 (match_operand:SI 2 "arith_reg_operand" "z")))]
3636 [(set_attr "type" "dmpy")])
3638 (define_insn "mul_l"
3639 [(set (reg:SI MACL_REG)
3640 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
3641 (match_operand:SI 1 "arith_reg_operand" "r")))]
3644 [(set_attr "type" "dmpy")])
3646 (define_expand "mulsi3"
3647 [(set (reg:SI MACL_REG)
3648 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
3649 (match_operand:SI 2 "arith_reg_operand" "")))
3650 (set (match_operand:SI 0 "arith_reg_operand" "")
3656 /* The address must be set outside the libcall,
3657 since it goes into a pseudo. */
3658 rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC);
3659 rtx addr = force_reg (SImode, sym);
3660 rtx insns = gen_mulsi3_call (operands[0], operands[1],
3666 rtx macl = gen_rtx_REG (SImode, MACL_REG);
3668 emit_insn (gen_mul_l (operands[1], operands[2]));
3669 /* consec_sets_giv can only recognize the first insn that sets a
3670 giv as the giv insn. So we must tag this also with a REG_EQUAL
3672 emit_insn (gen_movsi_i ((operands[0]), macl));
3677 (define_insn "mulsidi3_i"
3678 [(set (reg:SI MACH_REG)
3682 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3683 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3685 (set (reg:SI MACL_REG)
3686 (mult:SI (match_dup 0)
3690 [(set_attr "type" "dmpy")])
3692 (define_expand "mulsidi3"
3693 [(set (match_operand:DI 0 "arith_reg_dest" "")
3694 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3695 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))]
3696 "TARGET_SH2 || TARGET_SHMEDIA"
3700 emit_insn (gen_mulsidi3_compact (operands[0], operands[1], operands[2]));
3705 (define_insn "mulsidi3_media"
3706 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3707 (mult:DI (sign_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
3708 (sign_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
3711 [(set_attr "type" "dmpy_media")
3712 (set_attr "highpart" "ignore")])
3714 (define_insn_and_split "mulsidi3_compact"
3715 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3717 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
3718 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
3719 (clobber (reg:SI MACH_REG))
3720 (clobber (reg:SI MACL_REG))]
3726 rtx low_dst = gen_lowpart (SImode, operands[0]);
3727 rtx high_dst = gen_highpart (SImode, operands[0]);
3729 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
3731 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
3732 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
3733 /* We need something to tag the possible REG_EQUAL notes on to. */
3734 emit_move_insn (operands[0], operands[0]);
3738 (define_insn "umulsidi3_i"
3739 [(set (reg:SI MACH_REG)
3743 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3744 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3746 (set (reg:SI MACL_REG)
3747 (mult:SI (match_dup 0)
3751 [(set_attr "type" "dmpy")])
3753 (define_expand "umulsidi3"
3754 [(set (match_operand:DI 0 "arith_reg_dest" "")
3755 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3756 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))]
3757 "TARGET_SH2 || TARGET_SHMEDIA"
3761 emit_insn (gen_umulsidi3_compact (operands[0], operands[1], operands[2]));
3766 (define_insn "umulsidi3_media"
3767 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3768 (mult:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
3769 (zero_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
3772 [(set_attr "type" "dmpy_media")
3773 (set_attr "highpart" "ignore")])
3775 (define_insn_and_split "umulsidi3_compact"
3776 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3778 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
3779 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
3780 (clobber (reg:SI MACH_REG))
3781 (clobber (reg:SI MACL_REG))]
3787 rtx low_dst = gen_lowpart (SImode, operands[0]);
3788 rtx high_dst = gen_highpart (SImode, operands[0]);
3790 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
3792 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
3793 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
3794 /* We need something to tag the possible REG_EQUAL notes on to. */
3795 emit_move_insn (operands[0], operands[0]);
3799 (define_insn "smulsi3_highpart_i"
3800 [(set (reg:SI MACH_REG)
3804 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3805 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3807 (clobber (reg:SI MACL_REG))]
3810 [(set_attr "type" "dmpy")])
3812 (define_expand "smulsi3_highpart"
3814 [(set (reg:SI MACH_REG)
3818 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3819 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
3821 (clobber (reg:SI MACL_REG))])
3822 (set (match_operand:SI 0 "arith_reg_operand" "")
3829 mach = gen_rtx_REG (SImode, MACH_REG);
3831 emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
3832 insn = get_insns ();
3834 /* expand_binop can't find a suitable code in mul_highpart_optab to
3835 make a REG_EQUAL note from, so make one here.
3836 See also {,u}mulhisi.
3837 ??? Alternatively, we could put this at the calling site of expand_binop,
3838 i.e. expand_mult_highpart. */
3839 /* Use emit_libcall_block for loop invariant code motion and to make
3840 a REG_EQUAL note. */
3841 emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
3846 (define_insn "umulsi3_highpart_i"
3847 [(set (reg:SI MACH_REG)
3851 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3852 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3854 (clobber (reg:SI MACL_REG))]
3857 [(set_attr "type" "dmpy")])
3859 (define_expand "umulsi3_highpart"
3861 [(set (reg:SI MACH_REG)
3865 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3866 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
3868 (clobber (reg:SI MACL_REG))])
3869 (set (match_operand:SI 0 "arith_reg_operand" "")
3876 mach = gen_rtx_REG (SImode, MACH_REG);
3878 emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
3879 insn = get_insns ();
3881 /* Use emit_libcall_block for loop invariant code motion and to make
3882 a REG_EQUAL note. */
3883 emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
3888 (define_insn_and_split "muldi3"
3889 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3890 (mult:DI (match_operand:DI 1 "arith_reg_operand" "r")
3891 (match_operand:DI 2 "arith_reg_operand" "r")))
3892 (clobber (match_scratch:DI 3 "=&r"))
3893 (clobber (match_scratch:DI 4 "=r"))]
3899 rtx op3_v2si, op2_v2si;
3901 op3_v2si = operands[3];
3902 if (GET_CODE (op3_v2si) == SIGN_EXTEND)
3904 op3_v2si = XEXP (op3_v2si, 0);
3905 op3_v2si = simplify_gen_subreg (DImode, op3_v2si, GET_MODE (op3_v2si), 0);
3907 op3_v2si = simplify_gen_subreg (V2SImode, op3_v2si, DImode, 0);
3908 op2_v2si = operands[2];
3909 if (GET_CODE (op2_v2si) == SIGN_EXTEND)
3911 op2_v2si = XEXP (op2_v2si, 0);
3912 op2_v2si = simplify_gen_subreg (DImode, op2_v2si, GET_MODE (op2_v2si), 0);
3914 op2_v2si = simplify_gen_subreg (V2SImode, op2_v2si, DImode, 0);
3915 emit_insn (gen_rotldi3 (operands[3], operands[1], GEN_INT (32)));
3916 emit_insn (gen_mulv2si3 (op3_v2si, op3_v2si, op2_v2si));
3917 emit_insn (gen_umulsidi3_media (operands[4],
3918 sh_gen_truncate (SImode, operands[1], 0),
3919 sh_gen_truncate (SImode, operands[2], 0)));
3920 emit_insn (gen_anddi3 (operands[0], operands[3], GEN_INT (0xffffffff00000000LL)));
3921 emit_insn (gen_ashldi3_media (operands[3], operands[3], GEN_INT (32)));
3922 emit_insn (gen_adddi3 (operands[0], operands[3], operands[0]));
3923 emit_insn (gen_adddi3 (operands[0], operands[4], operands[0]));
3927 ;; -------------------------------------------------------------------------
3928 ;; Logical operations
3929 ;; -------------------------------------------------------------------------
3931 (define_expand "andsi3"
3932 [(set (match_operand:SI 0 "arith_reg_operand" "")
3933 (and:SI (match_operand:SI 1 "logical_reg_operand" "")
3934 (match_operand:SI 2 "logical_and_operand" "")))]
3937 /* If it is possible to turn the and insn into a zero extension
3938 already, redundant zero extensions will be folded, which results
3940 Ideally the splitter of *andsi_compact would be enough, if redundant
3941 zero extensions were detected after the combine pass, which does not
3942 happen at the moment. */
3945 if (satisfies_constraint_Jmb (operands[2]))
3947 emit_insn (gen_zero_extendqisi2 (operands[0],
3948 gen_lowpart (QImode, operands[1])));
3951 else if (satisfies_constraint_Jmw (operands[2]))
3953 emit_insn (gen_zero_extendhisi2 (operands[0],
3954 gen_lowpart (HImode, operands[1])));
3960 (define_insn_and_split "*andsi_compact"
3961 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r,z,r")
3962 (and:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,0,0")
3963 (match_operand:SI 2 "logical_and_operand" "Jmb,Jmw,K08,r")))]
3971 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
3973 if (satisfies_constraint_Jmb (operands[2]))
3974 operands[1] = gen_lowpart (QImode, operands[1]);
3975 else if (satisfies_constraint_Jmw (operands[2]))
3976 operands[1] = gen_lowpart (HImode, operands[1]);
3980 [(set_attr "type" "arith")])
3982 (define_insn "*andsi3_media"
3983 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3984 (and:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3985 (match_operand:SI 2 "logical_operand" "r,I10")))]
3990 [(set_attr "type" "arith_media")])
3992 (define_insn "*andsi3_bclr"
3993 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3994 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
3995 (match_operand:SI 2 "const_int_operand" "Psz")))]
3996 "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
3998 [(set_attr "type" "arith")])
4000 (define_insn_and_split "anddi3"
4001 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r,r")
4002 (and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
4003 (match_operand:DI 2 "and_operand" "r,I10,J16")))]
4010 && ! logical_operand (operands[2], DImode)"
4013 if ((unsigned)INTVAL (operands[2]) == (unsigned) 0xffffffff)
4014 emit_insn (gen_mshflo_l_di (operands[0], operands[1], CONST0_RTX (DImode)));
4016 emit_insn (gen_mshfhi_l_di (operands[0], CONST0_RTX (DImode), operands[1]));
4019 [(set_attr "type" "arith_media")])
4021 (define_insn "andcsi3"
4022 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4023 (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
4024 (not:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
4027 [(set_attr "type" "arith_media")])
4029 (define_insn "andcdi3"
4030 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4031 (and:DI (match_operand:DI 1 "arith_reg_operand" "r")
4032 (not:DI (match_operand:DI 2 "arith_reg_operand" "r"))))]
4035 [(set_attr "type" "arith_media")])
4037 (define_expand "iorsi3"
4038 [(set (match_operand:SI 0 "arith_reg_operand" "")
4039 (ior:SI (match_operand:SI 1 "logical_reg_operand" "")
4040 (match_operand:SI 2 "logical_operand" "")))]
4044 (define_insn "*iorsi3_compact"
4045 [(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
4046 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
4047 (match_operand:SI 2 "logical_operand" "r,K08")))]
4049 && !(TARGET_SH2A && satisfies_constraint_Pso (operands[2]))"
4051 [(set_attr "type" "arith")])
4053 (define_insn "*iorsi3_media"
4054 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4055 (ior:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
4056 (match_operand:SI 2 "logical_operand" "r,I10")))]
4061 [(set_attr "type" "arith_media")])
4063 (define_insn "*iorsi3_bset"
4064 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4065 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
4066 (match_operand:SI 2 "const_int_operand" "Pso")))]
4067 "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
4069 [(set_attr "type" "arith")])
4071 (define_insn "iordi3"
4072 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
4073 (ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
4074 (match_operand:DI 2 "logical_operand" "r,I10")))]
4079 [(set_attr "type" "arith_media")])
4081 (define_insn_and_split "*logical_sidi3"
4082 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
4083 (sign_extend:DI (match_operator:SI 3 "logical_operator"
4084 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
4085 (match_operand:SI 2 "logical_operand" "r,I10")])))]
4088 "&& reload_completed"
4089 [(set (match_dup 0) (match_dup 3))]
4092 = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
4093 simplify_gen_subreg (DImode, operands[1], SImode, 0),
4094 simplify_gen_subreg (DImode, operands[2], SImode, 0));
4097 (define_insn_and_split "*logical_sidisi3"
4098 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4099 (truncate:SI (sign_extend:DI
4100 (match_operator:SI 3 "logical_operator"
4101 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
4102 (match_operand:SI 2 "logical_operand" "r,I10")]))))]
4106 [(set (match_dup 0) (match_dup 3))])
4108 (define_insn_and_split "*logical_sidi3_2"
4109 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
4110 (sign_extend:DI (truncate:SI (sign_extend:DI
4111 (match_operator:SI 3 "logical_operator"
4112 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
4113 (match_operand:SI 2 "logical_operand" "r,I10")])))))]
4117 [(set (match_dup 0) (sign_extend:DI (match_dup 3)))])
4119 (define_expand "xorsi3"
4120 [(set (match_operand:SI 0 "arith_reg_operand" "")
4121 (xor:SI (match_operand:SI 1 "logical_reg_operand" "")
4122 (match_operand:SI 2 "xor_operand" "")))]
4126 (define_insn "*xorsi3_compact"
4127 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
4128 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
4129 (match_operand:SI 2 "logical_operand" "K08,r")))]
4132 [(set_attr "type" "arith")])
4134 ;; The *logical_op_t pattern helps combine eliminating sign/zero extensions
4135 ;; of results where one of the inputs is a T bit store. Notice that this
4136 ;; pattern must not match during reload. If reload picks this pattern it
4137 ;; will be impossible to split it afterwards.
4138 (define_insn_and_split "*logical_op_t"
4139 [(set (match_operand:SI 0 "arith_reg_dest")
4140 (match_operator:SI 3 "logical_operator"
4141 [(match_operand:SI 1 "arith_reg_operand")
4142 (match_operand:SI 2 "t_reg_operand")]))]
4143 "TARGET_SH1 && can_create_pseudo_p ()"
4146 [(set (match_dup 4) (reg:SI T_REG))
4147 (set (match_dup 0) (match_dup 3))]
4149 operands[4] = gen_reg_rtx (SImode);
4150 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
4151 operands[1], operands[4]);
4154 (define_insn "*xorsi3_media"
4155 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4156 (xor:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
4157 (match_operand:SI 2 "xor_operand" "r,I06")))]
4162 [(set_attr "type" "arith_media")])
4164 (define_insn "xordi3"
4165 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
4166 (xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
4167 (match_operand:DI 2 "xor_operand" "r,I06")))]
4172 [(set_attr "type" "arith_media")])
4174 ;; Combiner bridge pattern for 2 * sign extend -> logical op -> truncate.
4175 ;; converts 2 * sign extend -> logical op into logical op -> sign extend
4177 [(set (match_operand:DI 0 "arith_reg_dest" "")
4178 (sign_extend:DI (match_operator 4 "binary_logical_operator"
4179 [(match_operand 1 "any_register_operand" "")
4180 (match_operand 2 "any_register_operand" "")])))]
4182 [(set (match_dup 5) (match_dup 4))
4183 (set (match_dup 0) (sign_extend:DI (match_dup 5)))]
4185 machine_mode inmode = GET_MODE (operands[1]);
4188 if (GET_CODE (operands[0]) == SUBREG)
4190 offset = SUBREG_BYTE (operands[0]);
4191 operands[0] = SUBREG_REG (operands[0]);
4193 gcc_assert (REG_P (operands[0]));
4194 if (TARGET_BIG_ENDIAN)
4195 offset += 8 - GET_MODE_SIZE (inmode);
4196 operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset);
4199 ;; -------------------------------------------------------------------------
4200 ;; Shifts and rotates
4201 ;; -------------------------------------------------------------------------
4203 ;; Let combine see that we can get the MSB and LSB into the T bit
4204 ;; via shll and shlr. This allows it to plug it into insns that can have
4205 ;; the T bit as an input (e.g. addc).
4206 ;; FIXME: On SH2A use bld #0,Rn instead of shlr to avoid mutating the input.
4207 (define_insn_and_split "*reg_lsb_t"
4208 [(set (reg:SI T_REG)
4209 (and:SI (match_operand:SI 0 "arith_reg_operand")
4211 "TARGET_SH1 && can_create_pseudo_p ()"
4216 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[0]));
4219 (define_insn_and_split "*reg_msb_t"
4220 [(set (reg:SI T_REG)
4221 (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
4223 "TARGET_SH1 && can_create_pseudo_p ()"
4228 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
4231 (define_expand "rotldi3"
4232 [(set (match_operand:DI 0 "arith_reg_dest" "")
4233 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "")
4234 (match_operand:HI 2 "mextr_bit_offset" "")))]
4237 if (! mextr_bit_offset (operands[2], HImode))
4241 (define_insn "rotldi3_mextr"
4242 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4243 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
4244 (match_operand:HI 2 "mextr_bit_offset" "i")))]
4247 static char templ[16];
4248 sprintf (templ, "mextr%d %%1,%%1,%%0",
4249 8 - (int) (INTVAL (operands[2]) >> 3));
4252 [(set_attr "type" "arith_media")])
4254 (define_expand "rotrdi3"
4255 [(set (match_operand:DI 0 "arith_reg_dest" "")
4256 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "")
4257 (match_operand:HI 2 "mextr_bit_offset" "")))]
4260 if (! mextr_bit_offset (operands[2], HImode))
4264 (define_insn "rotrdi3_mextr"
4265 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4266 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
4267 (match_operand:HI 2 "mextr_bit_offset" "i")))]
4270 static char templ[16];
4271 sprintf (templ, "mextr%d %%1,%%1,%%0", (int) INTVAL (operands[2]) >> 3);
4274 [(set_attr "type" "arith_media")])
4277 [(set (match_operand:DI 0 "arith_reg_dest" "")
4278 (ior:DI (zero_extend:DI (mem:QI (match_operand 1
4279 "ua_address_operand" "")))
4280 (ashift:DI (match_operand:DI 2 "arith_reg_operand" "")
4282 (clobber (match_operand:DI 3 "register_operand" ""))]
4284 [(match_dup 4) (match_dup 5)]
4286 operands[4] = ((TARGET_LITTLE_ENDIAN ? gen_ldhi_q : gen_ldlo_q)
4287 (operands[3], operands[1]));
4288 operands[5] = gen_mextr_rl (operands[0], operands[3], operands[2],
4289 GEN_INT (56), GEN_INT (8));
4292 (define_expand "rotrsi3"
4293 [(set (match_operand:SI 0 "arith_reg_dest")
4294 (rotatert:SI (match_operand:SI 1 "arith_reg_operand")
4295 (match_operand:SI 2 "const_int_operand")))]
4298 HOST_WIDE_INT ival = INTVAL (operands[2]);
4301 emit_insn (gen_rotrsi3_1 (operands[0], operands[1]));
4308 (define_insn "rotrsi3_1"
4309 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4310 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
4313 (and:SI (match_dup 1) (const_int 1)))]
4316 [(set_attr "type" "arith")])
4318 ;; A slimplified version of rotr for combine.
4319 (define_insn "*rotrsi3_1"
4320 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4321 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
4323 (clobber (reg:SI T_REG))]
4326 [(set_attr "type" "arith")])
4328 (define_insn "rotlsi3_1"
4329 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4330 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
4333 (lshiftrt:SI (match_dup 1) (const_int 31)))]
4336 [(set_attr "type" "arith")])
4338 ;; A simplified version of rotl for combine.
4339 (define_insn "*rotlsi3_1"
4340 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4341 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
4343 (clobber (reg:SI T_REG))]
4346 [(set_attr "type" "arith")])
4348 (define_insn "rotlsi3_31"
4349 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4350 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
4352 (clobber (reg:SI T_REG))]
4355 [(set_attr "type" "arith")])
4357 (define_insn "rotlsi3_16"
4358 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4359 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
4363 [(set_attr "type" "arith")])
4365 (define_expand "rotlsi3"
4366 [(set (match_operand:SI 0 "arith_reg_dest")
4367 (rotate:SI (match_operand:SI 1 "arith_reg_operand")
4368 (match_operand:SI 2 "const_int_operand")))]
4371 static const char rot_tab[] = {
4372 000, 000, 000, 000, 000, 000, 010, 001,
4373 001, 001, 011, 013, 003, 003, 003, 003,
4374 003, 003, 003, 003, 003, 013, 012, 002,
4375 002, 002, 010, 000, 000, 000, 000, 000,
4378 int count = INTVAL (operands[2]);
4379 int choice = rot_tab[count];
4380 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
4386 emit_move_insn (operands[0], operands[1]);
4387 count -= (count & 16) * 2;
4390 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
4397 parts[0] = gen_reg_rtx (SImode);
4398 parts[1] = gen_reg_rtx (SImode);
4399 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
4400 emit_move_insn (parts[choice-1], operands[1]);
4401 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
4402 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
4403 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
4404 count = (count & ~16) - 8;
4408 for (; count > 0; count--)
4409 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
4410 for (; count < 0; count++)
4411 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
4416 (define_insn "rotlhi3_8"
4417 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4418 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
4422 [(set_attr "type" "arith")])
4424 (define_expand "rotlhi3"
4425 [(set (match_operand:HI 0 "arith_reg_operand")
4426 (rotate:HI (match_operand:HI 1 "arith_reg_operand")
4427 (match_operand:HI 2 "const_int_operand")))]
4430 if (INTVAL (operands[2]) != 8)
4434 ;; The rotcr and rotcl insns are used primarily in DImode shifts by one.
4435 ;; They can also be used to implement things like
4437 ;; int x0 = (y >> 1) | (t << 31); // rotcr
4438 ;; int x1 = (y << 1) | t; // rotcl
4439 (define_insn "rotcr"
4440 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4441 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4443 (ashift:SI (match_operand:SI 2 "t_reg_operand")
4446 (and:SI (match_dup 1) (const_int 1)))]
4449 [(set_attr "type" "arith")])
4451 (define_insn "rotcl"
4452 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4453 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4455 (match_operand:SI 2 "t_reg_operand")))
4457 (lshiftrt:SI (match_dup 1) (const_int 31)))]
4460 [(set_attr "type" "arith")])
4462 ;; Simplified rotcr version for combine, which allows arbitrary shift
4463 ;; amounts for the reg. If the shift amount is '1' rotcr can be used
4464 ;; directly. Otherwise we have to insert a shift in between.
4465 (define_insn_and_split "*rotcr"
4466 [(set (match_operand:SI 0 "arith_reg_dest")
4467 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_or_0_operand")
4468 (match_operand:SI 2 "const_int_operand"))
4469 (ashift:SI (match_operand 3 "arith_reg_or_treg_set_expr")
4471 (clobber (reg:SI T_REG))]
4472 "TARGET_SH1 && can_create_pseudo_p ()"
4477 rtx prev_set_t_insn = NULL_RTX;
4479 if (!arith_reg_operand (operands[3], SImode))
4481 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
4482 if (!ti.was_treg_operand ())
4483 prev_set_t_insn = ti.first_insn ();
4485 operands[3] = get_t_reg_rtx ();
4487 if (TARGET_SH2A && ti.has_trailing_nott () && operands[1] == const0_rtx)
4489 /* Convert to a movrt, rotr sequence. */
4490 remove_insn (ti.trailing_nott ());
4491 rtx tmp = gen_reg_rtx (SImode);
4492 emit_insn (gen_movnegt (tmp, get_t_reg_rtx ()));
4493 emit_insn (gen_rotrsi3_1 (operands[0], tmp));
4498 if (operands[1] == const0_rtx)
4500 operands[1] = gen_reg_rtx (SImode);
4501 emit_insn (gen_movt (operands[1], get_t_reg_rtx ()));
4504 if (INTVAL (operands[2]) > 1)
4506 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
4507 rtx tmp_t_reg = NULL_RTX;
4509 /* If we're going to emit a shift sequence that clobbers the T_REG,
4510 try to find the previous insn that sets the T_REG and emit the
4511 shift insn before that insn, to remove the T_REG dependency.
4512 If the insn that sets the T_REG cannot be found, store the T_REG
4513 in a temporary reg and restore it after the shift. */
4514 if (sh_lshrsi_clobbers_t_reg_p (shift_count)
4515 && ! sh_dynamicalize_shift_p (shift_count))
4517 if (prev_set_t_insn == NULL)
4518 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
4520 /* Skip the nott insn, which was probably inserted by the splitter
4521 of *rotcr_neg_t. Don't use one of the recog functions
4522 here during insn splitting, since that causes problems in later
4524 if (prev_set_t_insn != NULL_RTX)
4526 rtx pat = PATTERN (prev_set_t_insn);
4527 if (GET_CODE (pat) == SET
4528 && t_reg_operand (XEXP (pat, 0), SImode)
4529 && negt_reg_operand (XEXP (pat, 1), SImode))
4530 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
4533 if (! (prev_set_t_insn != NULL_RTX
4534 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
4535 && ! reg_referenced_p (get_t_reg_rtx (),
4536 PATTERN (prev_set_t_insn))))
4538 prev_set_t_insn = NULL_RTX;
4539 tmp_t_reg = gen_reg_rtx (SImode);
4540 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
4544 rtx shift_result = gen_reg_rtx (SImode);
4545 rtx shift_insn = gen_lshrsi3 (shift_result, operands[1], shift_count);
4546 operands[1] = shift_result;
4548 /* Emit the shift insn before the insn that sets T_REG, if possible. */
4549 if (prev_set_t_insn != NULL_RTX)
4550 emit_insn_before (shift_insn, prev_set_t_insn);
4552 emit_insn (shift_insn);
4554 /* Restore T_REG if it has been saved before. */
4555 if (tmp_t_reg != NULL_RTX)
4556 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
4559 /* For the rotcr insn to work, operands[3] must be in T_REG.
4560 If it is not we can get it there by shifting it right one bit.
4561 In this case T_REG is not an input for this insn, thus we don't have to
4562 pay attention as of where to insert the shlr insn. */
4563 if (! t_reg_operand (operands[3], SImode))
4565 /* We don't care about the shifted result here, only the T_REG. */
4566 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
4567 operands[3] = get_t_reg_rtx ();
4570 emit_insn (gen_rotcr (operands[0], operands[1], operands[3]));
4574 ;; If combine tries the same as above but with swapped operands, split
4575 ;; it so that it will try the pattern above.
4577 [(set (match_operand:SI 0 "arith_reg_dest")
4578 (ior:SI (ashift:SI (match_operand 1 "arith_reg_or_treg_set_expr")
4580 (lshiftrt:SI (match_operand:SI 2 "arith_reg_or_0_operand")
4581 (match_operand:SI 3 "const_int_operand"))))]
4582 "TARGET_SH1 && can_create_pseudo_p ()"
4583 [(parallel [(set (match_dup 0)
4584 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
4585 (ashift:SI (match_dup 1) (const_int 31))))
4586 (clobber (reg:SI T_REG))])])
4588 ;; Basically the same as the rotcr pattern above, but for rotcl.
4589 ;; FIXME: Fold copy pasted split code for rotcr and rotcl.
4590 (define_insn_and_split "*rotcl"
4591 [(set (match_operand:SI 0 "arith_reg_dest")
4592 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4593 (match_operand:SI 2 "const_int_operand"))
4594 (and:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
4596 (clobber (reg:SI T_REG))]
4599 "&& can_create_pseudo_p ()"
4602 gcc_assert (INTVAL (operands[2]) > 0);
4604 if (INTVAL (operands[2]) > 1)
4606 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
4607 rtx prev_set_t_insn = NULL_RTX;
4608 rtx tmp_t_reg = NULL_RTX;
4610 /* If we're going to emit a shift sequence that clobbers the T_REG,
4611 try to find the previous insn that sets the T_REG and emit the
4612 shift insn before that insn, to remove the T_REG dependency.
4613 If the insn that sets the T_REG cannot be found, store the T_REG
4614 in a temporary reg and restore it after the shift. */
4615 if (sh_ashlsi_clobbers_t_reg_p (shift_count)
4616 && ! sh_dynamicalize_shift_p (shift_count))
4618 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
4620 /* Skip the nott insn, which was probably inserted by the splitter
4621 of *rotcl_neg_t. Don't use one of the recog functions
4622 here during insn splitting, since that causes problems in later
4624 if (prev_set_t_insn != NULL_RTX)
4626 rtx pat = PATTERN (prev_set_t_insn);
4627 if (GET_CODE (pat) == SET
4628 && t_reg_operand (XEXP (pat, 0), SImode)
4629 && negt_reg_operand (XEXP (pat, 1), SImode))
4630 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
4633 if (! (prev_set_t_insn != NULL_RTX
4634 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
4635 && ! reg_referenced_p (get_t_reg_rtx (),
4636 PATTERN (prev_set_t_insn))))
4638 prev_set_t_insn = NULL_RTX;
4639 tmp_t_reg = gen_reg_rtx (SImode);
4640 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
4644 rtx shift_result = gen_reg_rtx (SImode);
4645 rtx shift_insn = gen_ashlsi3 (shift_result, operands[1], shift_count);
4646 operands[1] = shift_result;
4648 /* Emit the shift insn before the insn that sets T_REG, if possible. */
4649 if (prev_set_t_insn != NULL_RTX)
4650 emit_insn_before (shift_insn, prev_set_t_insn);
4652 emit_insn (shift_insn);
4654 /* Restore T_REG if it has been saved before. */
4655 if (tmp_t_reg != NULL_RTX)
4656 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
4659 /* For the rotcl insn to work, operands[3] must be in T_REG.
4660 If it is not we can get it there by shifting it right one bit.
4661 In this case T_REG is not an input for this insn, thus we don't have to
4662 pay attention as of where to insert the shlr insn. */
4663 if (! t_reg_operand (operands[3], SImode))
4665 /* We don't care about the shifted result here, only the T_REG. */
4666 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
4667 operands[3] = get_t_reg_rtx ();
4670 emit_insn (gen_rotcl (operands[0], operands[1], operands[3]));
4674 ;; rotcl combine pattern variations
4675 (define_insn_and_split "*rotcl"
4676 [(set (match_operand:SI 0 "arith_reg_dest")
4677 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4678 (match_operand:SI 2 "const_int_operand"))
4679 (match_operand 3 "treg_set_expr")))
4680 (clobber (reg:SI T_REG))]
4683 "&& can_create_pseudo_p ()"
4684 [(parallel [(set (match_dup 0)
4685 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4686 (and:SI (match_dup 3) (const_int 1))))
4687 (clobber (reg:SI T_REG))])]
4689 sh_split_treg_set_expr (operands[3], curr_insn);
4690 operands[3] = get_t_reg_rtx ();
4693 (define_insn_and_split "*rotcl"
4694 [(set (match_operand:SI 0 "arith_reg_dest")
4695 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
4697 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4698 (match_operand:SI 3 "const_int_operand"))))
4699 (clobber (reg:SI T_REG))]
4702 "&& can_create_pseudo_p ()"
4703 [(parallel [(set (match_dup 0)
4704 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4705 (and:SI (match_dup 1) (const_int 1))))
4706 (clobber (reg:SI T_REG))])])
4708 (define_insn_and_split "*rotcl"
4709 [(set (match_operand:SI 0 "arith_reg_dest")
4710 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4711 (match_operand:SI 2 "const_int_operand"))
4712 (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
4714 (clobber (reg:SI T_REG))]
4717 "&& can_create_pseudo_p ()"
4718 [(parallel [(set (match_dup 0)
4719 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4720 (and:SI (reg:SI T_REG) (const_int 1))))
4721 (clobber (reg:SI T_REG))])]
4723 /* We don't care about the result of the left shift, only the T_REG. */
4724 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
4727 (define_insn_and_split "*rotcl"
4728 [(set (match_operand:SI 0 "arith_reg_dest")
4729 (ior:SI (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
4731 (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4732 (match_operand:SI 2 "const_int_operand"))))
4733 (clobber (reg:SI T_REG))]
4736 "&& can_create_pseudo_p ()"
4737 [(parallel [(set (match_dup 0)
4738 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4739 (and:SI (reg:SI T_REG) (const_int 1))))
4740 (clobber (reg:SI T_REG))])]
4742 /* We don't care about the result of the left shift, only the T_REG. */
4743 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
4746 (define_insn_and_split "*rotcl"
4747 [(set (match_operand:SI 0 "arith_reg_dest")
4748 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4749 (match_operand 2 "const_int_operand"))
4750 (zero_extract:SI (match_operand:SI 3 "arith_reg_operand")
4752 (match_operand 4 "const_int_operand"))))
4753 (clobber (reg:SI T_REG))]
4756 "&& can_create_pseudo_p ()"
4757 [(parallel [(set (match_dup 0)
4758 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4759 (and:SI (match_dup 5) (const_int 1))))
4760 (clobber (reg:SI T_REG))])]
4762 if (TARGET_SH2A && satisfies_constraint_K03 (operands[4]))
4764 /* On SH2A we can use the bld insn to zero extract a single bit
4766 operands[5] = get_t_reg_rtx ();
4767 emit_insn (gen_bldsi_reg (operands[3], operands[4]));
4771 /* If we can't use the bld insn we have to emit a tst + nott sequence
4772 to get the extracted bit into the T bit.
4773 This will probably be worse than pre-shifting the operand. */
4774 operands[5] = gen_reg_rtx (SImode);
4775 emit_insn (gen_lshrsi3 (operands[5], operands[3], operands[4]));
4779 ;; rotcr combine bridge pattern which will make combine try out more
4780 ;; complex patterns.
4781 (define_insn_and_split "*rotcr"
4782 [(set (match_operand:SI 0 "arith_reg_dest")
4783 (ashift:SI (match_operand 1 "treg_set_expr") (const_int 31)))]
4784 "TARGET_SH1 && can_create_pseudo_p ()"
4787 [(parallel [(set (match_dup 0)
4788 (ior:SI (lshiftrt:SI (const_int 0) (const_int 1))
4789 (ashift:SI (match_dup 1) (const_int 31))))
4790 (clobber (reg:SI T_REG))])])
4792 (define_insn_and_split "*rotcr"
4793 [(set (match_operand:SI 0 "arith_reg_dest")
4794 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
4795 (const_int -2147483648)) ;; 0xffffffff80000000
4796 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4798 (clobber (reg:SI T_REG))]
4801 "&& can_create_pseudo_p ()"
4804 rtx tmp = gen_reg_rtx (SImode);
4805 emit_insn (gen_shll (tmp, operands[1]));
4806 emit_insn (gen_rotcr (operands[0], operands[2], get_t_reg_rtx ()));
4810 ;; rotcr combine patterns for rotating in the negated T_REG value.
4811 (define_insn_and_split "*rotcr_neg_t"
4812 [(set (match_operand:SI 0 "arith_reg_dest")
4813 (ior:SI (match_operand:SI 1 "negt_reg_shl31_operand")
4814 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4815 (match_operand:SI 3 "const_int_operand"))))
4816 (clobber (reg:SI T_REG))]
4819 "&& can_create_pseudo_p ()"
4820 [(parallel [(set (match_dup 0)
4821 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
4822 (ashift:SI (reg:SI T_REG) (const_int 31))))
4823 (clobber (reg:SI T_REG))])]
4825 emit_insn (gen_nott (get_t_reg_rtx ()));
4828 (define_insn_and_split "*rotcr_neg_t"
4829 [(set (match_operand:SI 0 "arith_reg_dest")
4830 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
4831 (match_operand:SI 2 "const_int_operand"))
4832 (match_operand:SI 3 "negt_reg_shl31_operand")))
4833 (clobber (reg:SI T_REG))]
4836 "&& can_create_pseudo_p ()"
4837 [(parallel [(set (match_dup 0)
4838 (ior:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4839 (ashift:SI (reg:SI T_REG) (const_int 31))))
4840 (clobber (reg:SI T_REG))])]
4842 emit_insn (gen_nott (get_t_reg_rtx ()));
4845 ;; rotcl combine patterns for rotating in the negated T_REG value.
4846 ;; For some strange reason these have to be specified as splits which combine
4847 ;; will pick up. If they are specified as insn_and_split like the
4848 ;; *rotcr_neg_t patterns above, combine would recognize them successfully
4849 ;; but not emit them on non-SH2A targets.
4851 [(set (match_operand:SI 0 "arith_reg_dest")
4852 (ior:SI (match_operand:SI 1 "negt_reg_operand")
4853 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4854 (match_operand:SI 3 "const_int_operand"))))]
4856 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
4857 (parallel [(set (match_dup 0)
4858 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4859 (and:SI (reg:SI T_REG) (const_int 1))))
4860 (clobber (reg:SI T_REG))])])
4863 [(set (match_operand:SI 0 "arith_reg_dest")
4864 (ior:SI (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4865 (match_operand:SI 3 "const_int_operand"))
4866 (match_operand:SI 1 "negt_reg_operand")))]
4868 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
4869 (parallel [(set (match_dup 0)
4870 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4871 (and:SI (reg:SI T_REG) (const_int 1))))
4872 (clobber (reg:SI T_REG))])])
4874 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4875 ;; SImode shift left
4877 (define_expand "ashlsi3"
4878 [(set (match_operand:SI 0 "arith_reg_operand" "")
4879 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
4880 (match_operand:SI 2 "shift_count_operand" "")))]
4885 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
4887 operands[2] = GEN_INT (-INTVAL (operands[2]));
4888 emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2]));
4891 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
4895 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
4896 operands[2] = force_reg (SImode, operands[2]);
4898 /* If the ashlsi3_* insn is going to clobber the T_REG it must be
4900 if (CONST_INT_P (operands[2])
4901 && sh_ashlsi_clobbers_t_reg_p (operands[2])
4902 && ! sh_dynamicalize_shift_p (operands[2]))
4904 emit_insn (gen_ashlsi3_n_clobbers_t (operands[0], operands[1],
4909 /* Expand a library call for the dynamic shift. */
4910 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
4912 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
4913 rtx funcaddr = gen_reg_rtx (Pmode);
4914 function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC);
4915 emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr));
4921 (define_insn "ashlsi3_k"
4922 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4923 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
4924 (match_operand:SI 2 "p27_shift_count_operand" "M,P27")))]
4929 [(set_attr "type" "arith")])
4931 (define_insn_and_split "ashlsi3_d"
4932 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4933 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4934 (match_operand:SI 2 "shift_count_operand" "r")))]
4937 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
4938 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
4941 if (satisfies_constraint_P27 (operands[2]))
4943 emit_insn (gen_ashlsi3_k (operands[0], operands[1], operands[2]));
4946 else if (! satisfies_constraint_P27 (operands[2]))
4948 /* This must happen before reload, otherwise the constant will be moved
4949 into a register due to the "r" constraint, after which this split
4950 cannot be done anymore.
4951 Unfortunately the move insn will not always be eliminated.
4952 Also, here we must not create a shift sequence that clobbers the
4954 emit_move_insn (operands[0], operands[1]);
4955 gen_shifty_op (ASHIFT, operands);
4961 [(set_attr "type" "dyn_shift")])
4963 ;; If dynamic shifts are not available use a library function.
4964 ;; By specifying the pattern we reduce the number of call clobbered regs.
4965 ;; In order to make combine understand the truncation of the shift amount
4966 ;; operand we have to allow it to use pseudo regs for the shift operands.
4967 (define_insn "ashlsi3_d_call"
4968 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
4969 (ashift:SI (reg:SI R4_REG)
4970 (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
4972 (use (match_operand:SI 2 "arith_reg_operand" "r"))
4973 (clobber (reg:SI T_REG))
4974 (clobber (reg:SI PR_REG))]
4975 "TARGET_SH1 && !TARGET_DYNSHIFT"
4977 [(set_attr "type" "sfunc")
4978 (set_attr "needs_delay_slot" "yes")])
4980 (define_insn_and_split "ashlsi3_n"
4981 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4982 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4983 (match_operand:SI 2 "not_p27_shift_count_operand" "")))]
4984 "TARGET_SH1 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
4986 "&& (reload_completed
4987 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4990 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4992 /* If this pattern was picked and dynamic shifts are supported, switch
4993 to dynamic shift pattern before reload. */
4994 operands[2] = force_reg (SImode, operands[2]);
4995 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
4998 gen_shifty_op (ASHIFT, operands);
5003 (define_insn_and_split "ashlsi3_n_clobbers_t"
5004 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5005 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
5006 (match_operand:SI 2 "not_p27_shift_count_operand" "")))
5007 (clobber (reg:SI T_REG))]
5008 "TARGET_SH1 && sh_ashlsi_clobbers_t_reg_p (operands[2])"
5010 "&& (reload_completed || INTVAL (operands[2]) == 31
5011 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
5014 if (INTVAL (operands[2]) == 31)
5016 /* If the shift amount is 31 we split into a different sequence before
5017 reload so that it gets a chance to allocate R0 for the sequence.
5018 If it fails to do so (due to pressure on R0), it will take one insn
5019 more for the and. */
5020 emit_insn (gen_andsi3 (operands[0], operands[1], const1_rtx));
5021 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
5023 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
5025 /* If this pattern was picked and dynamic shifts are supported, switch
5026 to dynamic shift pattern before reload. */
5027 operands[2] = force_reg (SImode, operands[2]);
5028 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
5031 gen_shifty_op (ASHIFT, operands);
5037 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5038 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
5040 (lt:SI (match_dup 1) (const_int 0)))]
5043 [(set_attr "type" "arith")])
5045 (define_insn "*ashlsi_c_void"
5046 [(set (reg:SI T_REG)
5047 (lt:SI (match_operand:SI 0 "arith_reg_operand" "r") (const_int 0)))
5048 (clobber (match_scratch:SI 1 "=0"))]
5049 "TARGET_SH1 && cse_not_expected"
5051 [(set_attr "type" "arith")])
5054 [(set (match_operand:SI 0 "arith_reg_dest" "") (const_int 0))
5056 (gt:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand" "")))]
5058 && peep2_reg_dead_p (2, operands[0])
5059 && peep2_reg_dead_p (2, operands[1])"
5062 emit_insn (gen_shll (operands[1], operands[1]));
5066 (define_insn "ashlsi3_media"
5067 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5068 (ashift:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
5069 (match_operand:SI 2 "shift_count_operand" "r,n")))]
5074 [(set_attr "type" "arith_media")
5075 (set_attr "highpart" "ignore")])
5077 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5078 ;; HImode shift left
5080 (define_expand "ashlhi3"
5081 [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "")
5082 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
5083 (match_operand:SI 2 "nonmemory_operand" "")))
5084 (clobber (reg:SI T_REG))])]
5087 if (!CONST_INT_P (operands[2]))
5089 /* It may be possible to call gen_ashlhi3 directly with more generic
5090 operands. Make sure operands[1] is a HImode register here. */
5091 if (!arith_reg_operand (operands[1], HImode))
5092 operands[1] = copy_to_mode_reg (HImode, operands[1]);
5095 (define_insn "ashlhi3_k"
5096 [(set (match_operand:HI 0 "arith_reg_dest" "=r,r")
5097 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
5098 (match_operand:HI 2 "const_int_operand" "M,P27")))]
5099 "TARGET_SH1 && satisfies_constraint_P27 (operands[2])"
5103 [(set_attr "type" "arith")])
5105 (define_insn_and_split "*ashlhi3_n"
5106 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
5107 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
5108 (match_operand:HI 2 "const_int_operand" "n")))
5109 (clobber (reg:SI T_REG))]
5112 "&& reload_completed"
5113 [(use (reg:SI R0_REG))]
5115 gen_shifty_hi_op (ASHIFT, operands);
5119 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5120 ;; DImode shift left
5122 (define_expand "ashldi3"
5123 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
5124 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
5125 (match_operand:DI 2 "immediate_operand" "")))
5126 (clobber (reg:SI T_REG))])]
5131 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
5133 operands[2] = GEN_INT (-INTVAL (operands[2]));
5134 emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
5137 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
5140 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
5142 emit_insn (gen_ashldi3_k (operands[0], operands[1]));
5145 else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 32)
5147 emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2]));
5154 ;; Expander for DImode shift left with SImode operations.
5155 (define_expand "ashldi3_std"
5156 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5157 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
5158 (match_operand:DI 2 "const_int_operand" "n")))]
5159 "TARGET_SH1 && INTVAL (operands[2]) < 32"
5161 rtx low_src = gen_lowpart (SImode, operands[1]);
5162 rtx high_src = gen_highpart (SImode, operands[1]);
5163 rtx dst = gen_reg_rtx (DImode);
5164 rtx low_dst = gen_lowpart (SImode, dst);
5165 rtx high_dst = gen_highpart (SImode, dst);
5166 rtx tmp0 = gen_reg_rtx (SImode);
5167 rtx tmp1 = gen_reg_rtx (SImode);
5169 emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2]))));
5170 emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2]));
5171 emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2]));
5172 emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1));
5173 emit_move_insn (operands[0], dst);
5177 (define_insn_and_split "ashldi3_k"
5178 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5179 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
5181 (clobber (reg:SI T_REG))]
5184 "&& reload_completed"
5187 rtx high = gen_highpart (SImode, operands[0]);
5188 rtx low = gen_lowpart (SImode, operands[0]);
5189 emit_insn (gen_shll (low, low));
5190 emit_insn (gen_rotcl (high, high, get_t_reg_rtx ()));
5194 (define_insn "ashldi3_media"
5195 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
5196 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
5197 (match_operand:DI 2 "shift_count_operand" "r,n")))]
5202 [(set_attr "type" "arith_media")])
5204 (define_insn "*ashldisi3_media"
5205 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
5206 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
5207 (match_operand:DI 2 "const_int_operand" "n")))]
5208 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
5209 "shlli.l %1, %2, %0"
5210 [(set_attr "type" "arith_media")
5211 (set_attr "highpart" "ignore")])
5213 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5214 ;; SImode arithmetic shift right
5216 ;; We can't do HImode right shifts correctly unless we start out with an
5217 ;; explicit zero / sign extension; doing that would result in worse overall
5218 ;; code, so just let the machine independent code widen the mode.
5219 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
5221 (define_expand "ashrsi3"
5222 [(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
5223 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
5224 (match_operand:SI 2 "nonmemory_operand" "")))
5225 (clobber (reg:SI T_REG))])]
5230 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
5232 operands[2] = GEN_INT (-INTVAL (operands[2]));
5233 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
5236 emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2]));
5239 if (expand_ashiftrt (operands))
5246 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5247 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5250 (and:SI (match_dup 1) (const_int 1)))]
5253 [(set_attr "type" "arith")])
5255 (define_insn "ashrsi3_k"
5256 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5257 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5258 (match_operand:SI 2 "const_int_operand" "M")))
5259 (clobber (reg:SI T_REG))]
5260 "TARGET_SH1 && INTVAL (operands[2]) == 1"
5262 [(set_attr "type" "arith")])
5264 (define_insn_and_split "ashrsi2_16"
5265 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5266 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
5271 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
5272 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
5274 operands[2] = gen_lowpart (HImode, operands[0]);
5277 (define_insn_and_split "ashrsi2_31"
5278 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5279 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5281 (clobber (reg:SI T_REG))]
5287 emit_insn (gen_shll (operands[0], operands[1]));
5288 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
5292 ;; If the shift amount is changed by combine it will try to plug the
5293 ;; use on the symbol of the library function and the PR clobber.
5294 (define_insn_and_split "*ashrsi2_31"
5295 [(set (match_operand:SI 0 "arith_reg_dest")
5296 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand")
5298 (clobber (reg:SI T_REG))
5299 (clobber (reg:SI PR_REG))
5300 (use (match_operand:SI 2 "symbol_ref_operand"))]
5304 [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))
5305 (clobber (reg:SI T_REG))])])
5307 (define_insn "ashrsi3_d"
5308 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5309 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5310 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
5313 [(set_attr "type" "dyn_shift")])
5315 (define_insn "ashrsi3_n"
5316 [(set (reg:SI R4_REG)
5317 (ashiftrt:SI (reg:SI R4_REG)
5318 (match_operand:SI 0 "const_int_operand" "i")))
5319 (clobber (reg:SI T_REG))
5320 (clobber (reg:SI PR_REG))
5321 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
5324 [(set_attr "type" "sfunc")
5325 (set_attr "needs_delay_slot" "yes")])
5327 (define_insn "ashrsi3_media"
5328 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5329 (ashiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
5330 (match_operand:SI 2 "shift_count_operand" "r,n")))]
5335 [(set_attr "type" "arith_media")
5336 (set_attr "highpart" "ignore")])
5338 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5339 ;; DImode arithmetic shift right
5341 (define_expand "ashrdi3"
5342 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
5343 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
5344 (match_operand:DI 2 "immediate_operand" "")))
5345 (clobber (reg:SI T_REG))])]
5350 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
5352 operands[2] = GEN_INT (-INTVAL (operands[2]));
5353 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
5356 emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
5359 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
5363 (define_insn_and_split "ashrdi3_k"
5364 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5365 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
5367 (clobber (reg:SI T_REG))]
5370 "&& reload_completed"
5373 rtx high = gen_highpart (SImode, operands[0]);
5374 rtx low = gen_lowpart (SImode, operands[0]);
5375 emit_insn (gen_shar (high, high));
5376 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
5380 (define_insn "ashrdi3_media"
5381 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
5382 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
5383 (match_operand:DI 2 "shift_count_operand" "r,n")))]
5385 && (arith_reg_dest (operands[0], DImode)
5386 || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 32))"
5390 [(set_attr "type" "arith_media")])
5392 (define_insn "*ashrdisi3_media"
5393 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
5394 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5395 (match_operand:DI 2 "const_int_operand" "n")))]
5396 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
5397 "shari.l %1, %2, %0"
5398 [(set_attr "type" "arith_media")
5399 (set_attr "highpart" "ignore")])
5401 (define_insn "ashrdisi3_media_high"
5402 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5404 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5405 (match_operand:DI 2 "const_int_operand" "n"))))]
5406 "TARGET_SHMEDIA && INTVAL (operands[2]) >= 32"
5408 [(set_attr "type" "arith_media")])
5410 (define_insn "ashrdisi3_media_opaque"
5411 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5412 (unspec:SI [(match_operand:DI 1 "arith_reg_operand" "r")
5413 (match_operand:DI 2 "const_int_operand" "n")]
5417 [(set_attr "type" "arith_media")])
5419 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5420 ;; SImode logical shift right
5422 (define_expand "lshrsi3"
5423 [(set (match_operand:SI 0 "arith_reg_dest" "")
5424 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
5425 (match_operand:SI 2 "shift_count_operand" "")))]
5430 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
5432 operands[2] = GEN_INT (-INTVAL (operands[2]));
5433 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
5436 emit_insn (gen_lshrsi3_media (operands[0], operands[1], operands[2]));
5440 /* If a dynamic shift is supposed to be used, expand the lshrsi3_d insn
5441 here, otherwise the pattern will never match due to the shift amount reg
5444 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
5446 rtx neg_count = force_reg (SImode,
5447 gen_int_mode (- INTVAL (operands[2]), SImode));
5448 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
5452 if (TARGET_DYNSHIFT && ! CONST_INT_P (operands[2]))
5454 rtx neg_count = gen_reg_rtx (SImode);
5455 emit_insn (gen_negsi2 (neg_count, operands[2]));
5456 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
5460 /* If the lshrsi3_* insn is going to clobber the T_REG it must be
5462 if (CONST_INT_P (operands[2])
5463 && sh_lshrsi_clobbers_t_reg_p (operands[2])
5464 && ! sh_dynamicalize_shift_p (operands[2]))
5466 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1],
5471 /* Expand a library call for the dynamic shift. */
5472 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
5474 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
5475 rtx funcaddr = gen_reg_rtx (Pmode);
5476 function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC);
5477 emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr));
5482 (define_insn "lshrsi3_k"
5483 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5484 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5485 (match_operand:SI 2 "p27_rshift_count_operand" "P27")))]
5488 [(set_attr "type" "arith")])
5490 (define_insn_and_split "lshrsi3_d"
5491 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5492 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5493 (neg:SI (match_operand:SI 2 "shift_count_operand" "r"))))]
5496 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
5497 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
5500 if (satisfies_constraint_P27 (operands[2]))
5502 /* This will not be done for a shift amount of 1, because it would
5503 clobber the T_REG. */
5504 emit_insn (gen_lshrsi3_k (operands[0], operands[1], operands[2]));
5507 else if (! satisfies_constraint_P27 (operands[2]))
5509 /* This must happen before reload, otherwise the constant will be moved
5510 into a register due to the "r" constraint, after which this split
5511 cannot be done anymore.
5512 Unfortunately the move insn will not always be eliminated.
5513 Also, here we must not create a shift sequence that clobbers the
5515 emit_move_insn (operands[0], operands[1]);
5516 gen_shifty_op (LSHIFTRT, operands);
5522 [(set_attr "type" "dyn_shift")])
5524 ;; If dynamic shifts are not available use a library function.
5525 ;; By specifying the pattern we reduce the number of call clobbered regs.
5526 ;; In order to make combine understand the truncation of the shift amount
5527 ;; operand we have to allow it to use pseudo regs for the shift operands.
5528 (define_insn "lshrsi3_d_call"
5529 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
5530 (lshiftrt:SI (reg:SI R4_REG)
5531 (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
5533 (use (match_operand:SI 2 "arith_reg_operand" "r"))
5534 (clobber (reg:SI T_REG))
5535 (clobber (reg:SI PR_REG))]
5536 "TARGET_SH1 && !TARGET_DYNSHIFT"
5538 [(set_attr "type" "sfunc")
5539 (set_attr "needs_delay_slot" "yes")])
5541 (define_insn_and_split "lshrsi3_n"
5542 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5543 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5544 (match_operand:SI 2 "not_p27_rshift_count_operand")))]
5545 "TARGET_SH1 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
5547 "&& (reload_completed
5548 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
5551 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
5553 /* If this pattern was picked and dynamic shifts are supported, switch
5554 to dynamic shift pattern before reload. */
5555 operands[2] = force_reg (SImode,
5556 gen_int_mode (- INTVAL (operands[2]), SImode));
5557 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
5560 gen_shifty_op (LSHIFTRT, operands);
5565 ;; The lshrsi3_n_clobbers_t pattern also works as a simplified version of
5566 ;; the shlr pattern.
5567 (define_insn_and_split "lshrsi3_n_clobbers_t"
5568 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5569 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5570 (match_operand:SI 2 "not_p27_rshift_count_operand")))
5571 (clobber (reg:SI T_REG))]
5572 "TARGET_SH1 && sh_lshrsi_clobbers_t_reg_p (operands[2])"
5574 "&& (reload_completed || INTVAL (operands[2]) == 31
5575 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
5578 if (INTVAL (operands[2]) == 31)
5580 emit_insn (gen_shll (operands[0], operands[1]));
5581 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
5583 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
5585 /* If this pattern was picked and dynamic shifts are supported, switch
5586 to dynamic shift pattern before reload. */
5587 operands[2] = force_reg (SImode,
5588 gen_int_mode (- INTVAL (operands[2]), SImode));
5589 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
5592 gen_shifty_op (LSHIFTRT, operands);
5598 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5599 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5602 (and:SI (match_dup 1) (const_int 1)))]
5605 [(set_attr "type" "arith")])
5607 (define_insn "lshrsi3_media"
5608 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5609 (lshiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
5610 (match_operand:SI 2 "shift_count_operand" "r,n")))]
5615 [(set_attr "type" "arith_media")
5616 (set_attr "highpart" "ignore")])
5618 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5619 ;; DImode logical shift right
5621 (define_expand "lshrdi3"
5622 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
5623 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
5624 (match_operand:DI 2 "immediate_operand" "")))
5625 (clobber (reg:SI T_REG))])]
5630 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
5632 operands[2] = GEN_INT (-INTVAL (operands[2]));
5633 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
5636 emit_insn (gen_lshrdi3_media (operands[0], operands[1], operands[2]));
5639 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
5643 (define_insn_and_split "lshrdi3_k"
5644 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5645 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
5647 (clobber (reg:SI T_REG))]
5650 "&& reload_completed"
5653 rtx high = gen_highpart (SImode, operands[0]);
5654 rtx low = gen_lowpart (SImode, operands[0]);
5655 emit_insn (gen_shlr (high, high));
5656 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
5660 (define_insn "lshrdi3_media"
5661 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
5662 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
5663 (match_operand:DI 2 "shift_count_operand" "r,n")))]
5665 && (arith_reg_dest (operands[0], DImode)
5666 || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 32))"
5670 [(set_attr "type" "arith_media")])
5672 (define_insn "*lshrdisi3_media"
5673 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
5674 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5675 (match_operand:DI 2 "const_int_operand" "n")))]
5676 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
5677 "shlri.l %1, %2, %0"
5678 [(set_attr "type" "arith_media")
5679 (set_attr "highpart" "ignore")])
5681 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5682 ;; Combined left/right shifts
5685 [(set (match_operand:SI 0 "register_operand" "")
5686 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
5687 (match_operand:SI 2 "const_int_operand" ""))
5688 (match_operand:SI 3 "const_int_operand" "")))]
5689 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
5690 [(use (reg:SI R0_REG))]
5692 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
5698 [(set (match_operand:SI 0 "register_operand" "")
5699 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
5700 (match_operand:SI 2 "const_int_operand" ""))
5701 (match_operand:SI 3 "const_int_operand" "")))
5702 (clobber (reg:SI T_REG))]
5703 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
5704 [(use (reg:SI R0_REG))]
5706 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
5712 [(set (match_operand:SI 0 "register_operand" "=r")
5713 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
5714 (match_operand:SI 2 "const_int_operand" "n"))
5715 (match_operand:SI 3 "const_int_operand" "n")))
5716 (clobber (reg:SI T_REG))]
5717 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1"
5719 [(set (attr "length")
5720 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
5722 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
5724 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
5726 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
5728 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
5730 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
5732 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
5733 (const_string "16")]
5734 (const_string "18")))
5735 (set_attr "type" "arith")])
5738 [(set (match_operand:SI 0 "register_operand" "=z")
5739 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
5740 (match_operand:SI 2 "const_int_operand" "n"))
5741 (match_operand:SI 3 "const_int_operand" "n")))
5742 (clobber (reg:SI T_REG))]
5743 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2"
5745 [(set (attr "length")
5746 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
5748 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
5750 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
5752 (const_string "10")))
5753 (set_attr "type" "arith")])
5755 ;; shift left / and combination with a scratch register: The combine pass
5756 ;; does not accept the individual instructions, even though they are
5757 ;; cheap. But it needs a precise description so that it is usable after
5759 (define_insn "and_shl_scratch"
5760 [(set (match_operand:SI 0 "register_operand" "=r,&r")
5764 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
5765 (match_operand:SI 2 "const_int_operand" "N,n"))
5766 (match_operand:SI 3 "" "0,r"))
5767 (match_operand:SI 4 "const_int_operand" "n,n"))
5768 (match_operand:SI 5 "const_int_operand" "n,n")))
5769 (clobber (reg:SI T_REG))]
5772 [(set (attr "length")
5773 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
5775 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
5777 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
5779 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
5780 (const_string "10")]
5781 (const_string "12")))
5782 (set_attr "type" "arith")])
5785 [(set (match_operand:SI 0 "register_operand" "")
5789 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
5790 (match_operand:SI 2 "const_int_operand" ""))
5791 (match_operand:SI 3 "register_operand" ""))
5792 (match_operand:SI 4 "const_int_operand" ""))
5793 (match_operand:SI 5 "const_int_operand" "")))
5794 (clobber (reg:SI T_REG))]
5796 [(use (reg:SI R0_REG))]
5798 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
5800 if (INTVAL (operands[2]))
5802 gen_shifty_op (LSHIFTRT, operands);
5804 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
5805 operands[2] = operands[4];
5806 gen_shifty_op (ASHIFT, operands);
5807 if (INTVAL (operands[5]))
5809 operands[2] = operands[5];
5810 gen_shifty_op (LSHIFTRT, operands);
5815 ;; signed left/right shift combination.
5817 [(set (match_operand:SI 0 "register_operand" "")
5819 (ashift:SI (match_operand:SI 1 "register_operand" "")
5820 (match_operand:SI 2 "const_int_operand" ""))
5821 (match_operand:SI 3 "const_int_operand" "")
5823 (clobber (reg:SI T_REG))]
5825 [(use (reg:SI R0_REG))]
5827 if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1]))
5832 (define_insn "shl_sext_ext"
5833 [(set (match_operand:SI 0 "register_operand" "=r")
5835 (ashift:SI (match_operand:SI 1 "register_operand" "0")
5836 (match_operand:SI 2 "const_int_operand" "n"))
5837 (match_operand:SI 3 "const_int_operand" "n")
5839 (clobber (reg:SI T_REG))]
5840 "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
5842 [(set (attr "length")
5843 (cond [(match_test "shl_sext_length (insn)")
5845 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
5847 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
5849 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
5851 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
5853 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
5855 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
5857 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
5858 (const_string "16")]
5859 (const_string "18")))
5860 (set_attr "type" "arith")])
5862 (define_insn "shl_sext_sub"
5863 [(set (match_operand:SI 0 "register_operand" "=z")
5865 (ashift:SI (match_operand:SI 1 "register_operand" "0")
5866 (match_operand:SI 2 "const_int_operand" "n"))
5867 (match_operand:SI 3 "const_int_operand" "n")
5869 (clobber (reg:SI T_REG))]
5870 "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
5872 [(set (attr "length")
5873 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
5875 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
5877 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
5879 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
5880 (const_string "12")]
5881 (const_string "14")))
5882 (set_attr "type" "arith")])
5884 ;; The xtrct_left and xtrct_right patterns are used in expansions of DImode
5885 ;; shifts by 16, and allow the xtrct instruction to be generated from C
5887 (define_insn "xtrct_left"
5888 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5889 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5891 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
5895 [(set_attr "type" "arith")])
5897 (define_insn "xtrct_right"
5898 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5899 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5901 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
5905 [(set_attr "type" "arith")])
5907 ;; -------------------------------------------------------------------------
5909 ;; -------------------------------------------------------------------------
5912 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5913 (neg:SI (plus:SI (reg:SI T_REG)
5914 (match_operand:SI 1 "arith_reg_operand" "r"))))
5916 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
5920 [(set_attr "type" "arith")])
5922 ;; A simplified version of the negc insn, where the exact value of the
5923 ;; T bit doesn't matter. This is easier for combine to pick up.
5924 ;; Notice that '0 - x - 1' is the same as '~x', thus we don't specify
5925 ;; extra patterns for this case.
5926 (define_insn_and_split "*negc"
5927 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5928 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
5929 (match_operand 2 "treg_set_expr")))
5930 (clobber (reg:SI T_REG))]
5931 "TARGET_SH1 && can_create_pseudo_p ()"
5936 sh_split_treg_set_expr (operands[2], curr_insn);
5937 emit_insn (gen_negc (operands[0], operands[1]));
5941 (define_insn "*negdi_media"
5942 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5943 (neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
5946 [(set_attr "type" "arith_media")])
5948 ;; Don't split into individual negc insns immediately so that neg:DI (abs:DI)
5950 (define_expand "negdi2"
5951 [(parallel [(set (match_operand:DI 0 "arith_reg_dest")
5952 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
5953 (clobber (reg:SI T_REG))])]
5956 (define_insn_and_split "*negdi2"
5957 [(set (match_operand:DI 0 "arith_reg_dest")
5958 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
5959 (clobber (reg:SI T_REG))]
5962 "&& can_create_pseudo_p ()"
5965 emit_insn (gen_clrt ());
5966 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
5967 gen_lowpart (SImode, operands[1])));
5968 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
5969 gen_highpart (SImode, operands[1])));
5973 (define_insn "negsi2"
5974 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5975 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
5978 [(set_attr "type" "arith")])
5980 (define_insn_and_split "one_cmplsi2"
5981 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5982 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
5985 "&& can_create_pseudo_p ()"
5986 [(set (reg:SI T_REG) (ge:SI (match_dup 1) (const_int 0)))
5987 (set (match_dup 0) (reg:SI T_REG))]
5990 If the result of 'unsigned int <= 0x7FFFFFFF' ends up as the following
5993 (set (reg0) (not:SI (reg0) (reg1)))
5994 (parallel [(set (reg2) (lshiftrt:SI (reg0) (const_int 31)))
5995 (clobber (reg:SI T_REG))])
5997 ... match and combine the sequence manually in the split pass after the
5998 combine pass. Notice that combine does try the target pattern of this
5999 split, but if the pattern is added it interferes with other patterns, in
6000 particular with the div0s comparisons.
6001 This could also be done with a peephole but doing it here before register
6002 allocation can save one temporary.
6003 When we're here, the not:SI pattern obviously has been matched already
6004 and we only have to see whether the following insn is the left shift. */
6006 rtx_insn *i = next_nonnote_insn_bb (curr_insn);
6007 if (i == NULL_RTX || !NONJUMP_INSN_P (i))
6010 rtx p = PATTERN (i);
6011 if (GET_CODE (p) != PARALLEL || XVECLEN (p, 0) != 2)
6014 rtx p0 = XVECEXP (p, 0, 0);
6015 rtx p1 = XVECEXP (p, 0, 1);
6017 if (/* (set (reg2) (lshiftrt:SI (reg0) (const_int 31))) */
6018 GET_CODE (p0) == SET
6019 && GET_CODE (XEXP (p0, 1)) == LSHIFTRT
6020 && REG_P (XEXP (XEXP (p0, 1), 0))
6021 && REGNO (XEXP (XEXP (p0, 1), 0)) == REGNO (operands[0])
6022 && CONST_INT_P (XEXP (XEXP (p0, 1), 1))
6023 && INTVAL (XEXP (XEXP (p0, 1), 1)) == 31
6025 /* (clobber (reg:SI T_REG)) */
6026 && GET_CODE (p1) == CLOBBER && REG_P (XEXP (p1, 0))
6027 && REGNO (XEXP (p1, 0)) == T_REG)
6029 operands[0] = XEXP (p0, 0);
6030 set_insn_deleted (i);
6035 [(set_attr "type" "arith")])
6037 (define_expand "one_cmpldi2"
6038 [(set (match_operand:DI 0 "arith_reg_dest" "")
6039 (xor:DI (match_operand:DI 1 "arith_reg_operand" "")
6041 "TARGET_SHMEDIA" "")
6043 (define_expand "abs<mode>2"
6044 [(parallel [(set (match_operand:SIDI 0 "arith_reg_dest")
6045 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
6046 (clobber (reg:SI T_REG))])]
6049 (define_insn_and_split "*abs<mode>2"
6050 [(set (match_operand:SIDI 0 "arith_reg_dest")
6051 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
6052 (clobber (reg:SI T_REG))]
6055 "&& can_create_pseudo_p ()"
6058 if (<MODE>mode == SImode)
6059 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
6062 rtx high_src = gen_highpart (SImode, operands[1]);
6063 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
6066 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
6071 (define_insn_and_split "*negabs<mode>2"
6072 [(set (match_operand:SIDI 0 "arith_reg_dest")
6073 (neg:SIDI (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand"))))
6074 (clobber (reg:SI T_REG))]
6077 "&& can_create_pseudo_p ()"
6080 if (<MODE>mode == SImode)
6081 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
6084 rtx high_src = gen_highpart (SImode, operands[1]);
6085 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
6088 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
6093 ;; The SH4 202 can do zero-offset branches without pipeline stalls.
6094 ;; This can be used as some kind of conditional execution, which is useful
6096 ;; Actually the instruction scheduling should decide whether to use a
6097 ;; zero-offset branch or not for any generic case involving a single
6098 ;; instruction on SH4 202.
6099 (define_insn_and_split "negsi_cond"
6100 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
6102 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand" "M,N"))
6103 (match_operand:SI 1 "arith_reg_operand" "0,0")
6104 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
6105 "TARGET_SH1 && TARGET_ZDCBRANCH"
6107 static const char* alt[] =
6117 return alt[which_alternative];
6119 "TARGET_SH1 && ! TARGET_ZDCBRANCH"
6122 rtx skip_neg_label = gen_label_rtx ();
6124 emit_move_insn (operands[0], operands[1]);
6126 emit_jump_insn (INTVAL (operands[3])
6127 ? gen_branch_true (skip_neg_label)
6128 : gen_branch_false (skip_neg_label));
6130 emit_label_after (skip_neg_label,
6131 emit_insn (gen_negsi2 (operands[0], operands[1])));
6134 [(set_attr "type" "arith") ;; poor approximation
6135 (set_attr "length" "4")])
6137 (define_insn_and_split "negdi_cond"
6138 [(set (match_operand:DI 0 "arith_reg_dest")
6140 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand"))
6141 (match_operand:DI 1 "arith_reg_operand")
6142 (neg:DI (match_operand:DI 2 "arith_reg_operand"))))
6143 (clobber (reg:SI T_REG))]
6146 "&& can_create_pseudo_p ()"
6149 rtx skip_neg_label = gen_label_rtx ();
6151 emit_move_insn (operands[0], operands[1]);
6153 emit_jump_insn (INTVAL (operands[3])
6154 ? gen_branch_true (skip_neg_label)
6155 : gen_branch_false (skip_neg_label));
6157 if (!INTVAL (operands[3]))
6158 emit_insn (gen_clrt ());
6160 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
6161 gen_lowpart (SImode, operands[1])));
6162 emit_label_after (skip_neg_label,
6163 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
6164 gen_highpart (SImode, operands[1]))));
6168 (define_expand "bswapsi2"
6169 [(set (match_operand:SI 0 "arith_reg_dest" "")
6170 (bswap:SI (match_operand:SI 1 "arith_reg_operand" "")))]
6173 if (! can_create_pseudo_p ())
6177 rtx tmp0 = gen_reg_rtx (SImode);
6178 rtx tmp1 = gen_reg_rtx (SImode);
6180 emit_insn (gen_swapbsi2 (tmp0, operands[1]));
6181 emit_insn (gen_rotlsi3_16 (tmp1, tmp0));
6182 emit_insn (gen_swapbsi2 (operands[0], tmp1));
6187 (define_insn "swapbsi2"
6188 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6189 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
6190 (const_int -65536)) ;; 0xFFFF0000
6191 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
6193 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
6194 (const_int 255)))))]
6197 [(set_attr "type" "arith")])
6199 ;; The *swapbisi2_and_shl8 pattern helps the combine pass simplifying
6200 ;; partial byte swap expressions such as...
6201 ;; ((x & 0xFF) << 8) | ((x >> 8) & 0xFF).
6202 ;; ...which are currently not handled by the tree optimizers.
6203 ;; The combine pass will not initially try to combine the full expression,
6204 ;; but only some sub-expressions. In such a case the *swapbisi2_and_shl8
6205 ;; pattern acts as an intermediate pattern that will eventually lead combine
6206 ;; to the swapbsi2 pattern above.
6207 ;; As a side effect this also improves code that does (x & 0xFF) << 8
6208 ;; or (x << 8) & 0xFF00.
6209 (define_insn_and_split "*swapbisi2_and_shl8"
6210 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6211 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
6214 (match_operand:SI 2 "arith_reg_operand" "r")))]
6215 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
6217 "&& can_create_pseudo_p ()"
6220 rtx tmp0 = gen_reg_rtx (SImode);
6221 rtx tmp1 = gen_reg_rtx (SImode);
6223 emit_insn (gen_zero_extendqisi2 (tmp0, gen_lowpart (QImode, operands[1])));
6224 emit_insn (gen_swapbsi2 (tmp1, tmp0));
6225 emit_insn (gen_iorsi3 (operands[0], tmp1, operands[2]));
6229 ;; The *swapbhisi2 pattern is, like the *swapbisi2_and_shl8 pattern, another
6230 ;; intermediate pattern that will help the combine pass arriving at swapbsi2.
6231 (define_insn_and_split "*swapbhisi2"
6232 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6233 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
6236 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))))]
6237 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
6239 "&& can_create_pseudo_p ()"
6242 rtx tmp = gen_reg_rtx (SImode);
6244 emit_insn (gen_zero_extendhisi2 (tmp, gen_lowpart (HImode, operands[1])));
6245 emit_insn (gen_swapbsi2 (operands[0], tmp));
6249 ;; In some cases the swapbsi2 pattern might leave a sequence such as...
6253 ;; which can be simplified to...
6256 [(set (match_operand:SI 0 "arith_reg_dest" "")
6257 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
6258 (const_int -65536)) ;; 0xFFFF0000
6259 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
6261 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
6263 (set (match_operand:SI 2 "arith_reg_dest" "")
6265 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
6267 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
6268 (const_int -65536)) ;; 0xFFFF0000
6269 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
6271 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
6272 (const_int 255)))))])
6274 ;; -------------------------------------------------------------------------
6275 ;; Zero extension instructions
6276 ;; -------------------------------------------------------------------------
6278 (define_insn "zero_extendsidi2"
6279 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
6280 (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "r")))]
6282 "addz.l %1, r63, %0"
6283 [(set_attr "type" "arith_media")
6284 (set_attr "highpart" "extend")])
6286 (define_insn "zero_extendhidi2"
6287 [(set (match_operand:DI 0 "register_operand" "=r,r")
6288 (zero_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6293 [(set_attr "type" "*,load_media")
6294 (set (attr "highpart")
6295 (cond [(match_test "sh_contains_memref_p (insn)")
6296 (const_string "user")]
6297 (const_string "ignore")))])
6300 [(set (match_operand:DI 0 "register_operand" "")
6301 (zero_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
6302 "TARGET_SHMEDIA && reload_completed"
6303 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
6304 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))]
6306 if (GET_CODE (operands[1]) == TRUNCATE)
6307 operands[1] = XEXP (operands[1], 0);
6310 ;; ??? when a truncated input to a zero_extend is reloaded, reload will
6311 ;; reload the entire truncate expression.
6312 (define_insn_and_split "*loaddi_trunc"
6313 [(set (match_operand 0 "any_register_operand" "=r")
6314 (truncate (match_operand:DI 1 "memory_operand" "m")))]
6315 "TARGET_SHMEDIA && reload_completed"
6317 "TARGET_SHMEDIA && reload_completed"
6318 [(set (match_dup 0) (match_dup 1))]
6320 operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
6323 (define_insn "zero_extendqidi2"
6324 [(set (match_operand:DI 0 "register_operand" "=r,r")
6325 (zero_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6330 [(set_attr "type" "arith_media,load_media")
6331 (set (attr "highpart")
6332 (cond [(match_test "sh_contains_memref_p (insn)")
6333 (const_string "user")]
6334 (const_string "ignore")))])
6336 (define_expand "zero_extend<mode>si2"
6337 [(set (match_operand:SI 0 "arith_reg_dest")
6338 (zero_extend:SI (match_operand:QIHI 1 "zero_extend_operand")))])
6340 (define_insn_and_split "*zero_extend<mode>si2_compact"
6341 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6342 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
6345 "&& can_create_pseudo_p ()"
6346 [(set (match_dup 0) (match_dup 2))]
6348 /* Sometimes combine fails to combine a T bit or negated T bit store to a
6349 reg with a following zero extension. In the split pass after combine,
6350 try to figure out how the extended reg was set. If it originated from
6351 the T bit we can replace the zero extension with a reg move, which will
6352 be eliminated. Notice that this also helps the *cbranch_t splitter when
6353 it tries to post-combine tests and conditional branches, as it does not
6354 check for zero extensions. */
6355 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
6356 if (operands[2] == NULL_RTX)
6359 [(set_attr "type" "arith")])
6361 (define_insn "*zero_extendhisi2_media"
6362 [(set (match_operand:SI 0 "register_operand" "=r,r")
6363 (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6368 [(set_attr "type" "arith_media,load_media")
6369 (set (attr "highpart")
6370 (cond [(match_test "sh_contains_memref_p (insn)")
6371 (const_string "user")]
6372 (const_string "ignore")))])
6375 [(set (match_operand:SI 0 "register_operand" "")
6376 (zero_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
6377 "TARGET_SHMEDIA && reload_completed"
6378 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
6379 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
6381 rtx op1 = operands[1];
6383 if (GET_CODE (op1) == TRUNCATE)
6384 op1 = XEXP (op1, 0);
6386 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6387 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6390 (define_insn "*zero_extendqisi2_media"
6391 [(set (match_operand:SI 0 "register_operand" "=r,r")
6392 (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6397 [(set_attr "type" "arith_media,load_media")
6398 (set (attr "highpart")
6399 (cond [(match_test "sh_contains_memref_p (insn)")
6400 (const_string "user")]
6401 (const_string "ignore")))])
6403 (define_insn "zero_extendqihi2"
6404 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
6405 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
6408 [(set_attr "type" "arith")])
6410 ;; SH2A supports two zero extending load instructions: movu.b and movu.w.
6411 ;; They could also be used for simple memory addresses like @Rn by setting
6412 ;; the displacement value to zero. However, doing so too early results in
6413 ;; missed opportunities for other optimizations such as post-inc or index
6414 ;; addressing loads.
6415 ;; We don't allow the zero extending loads to match during RTL expansion
6416 ;; (see zero_extend_operand predicate), as this would pessimize other
6417 ;; optimization opportunities such as bit extractions of unsigned mems,
6418 ;; where the zero extraction is irrelevant. If the zero extracting mem
6419 ;; loads are emitted early it will be more difficult to change them back
6420 ;; to sign extending loads (which are preferred).
6421 ;; The combine pass will also try to combine mem loads and zero extends,
6422 ;; which is prevented by 'sh_legitimate_combined_insn'.
6423 (define_insn "*zero_extend<mode>si2_disp_mem"
6424 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
6426 (match_operand:QIHI 1 "zero_extend_movu_operand" "Sdd,Sra")))]
6430 movu.<bw> @(0,%t1),%0"
6431 [(set_attr "type" "load")
6432 (set_attr "length" "4")])
6434 ;; Convert the zero extending loads in sequences such as:
6435 ;; movu.b @(1,r5),r0 movu.w @(2,r5),r0
6436 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
6438 ;; back to sign extending loads like:
6439 ;; mov.b @(1,r5),r0 mov.w @(2,r5),r0
6440 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
6442 ;; if the extension type is irrelevant. The sign extending mov.{b|w} insn
6443 ;; is only 2 bytes in size if the displacement is {K04|K05}.
6444 ;; If the displacement is greater it doesn't matter, so we convert anyways.
6446 [(set (match_operand:SI 0 "arith_reg_dest" "")
6447 (zero_extend:SI (match_operand 1 "displacement_mem_operand" "")))
6448 (set (match_operand 2 "nonimmediate_operand" "")
6449 (match_operand 3 "arith_reg_operand" ""))]
6451 && REGNO (operands[0]) == REGNO (operands[3])
6452 && peep2_reg_dead_p (2, operands[0])
6453 && GET_MODE_SIZE (GET_MODE (operands[2]))
6454 <= GET_MODE_SIZE (GET_MODE (operands[1]))"
6455 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
6456 (set (match_dup 2) (match_dup 3))])
6458 ;; Fold sequences such as
6462 ;; movu.b @(0,r3),r7
6463 ;; This does not reduce the code size but the number of instructions is
6464 ;; halved, which results in faster code.
6466 [(set (match_operand:SI 0 "arith_reg_dest" "")
6467 (sign_extend:SI (match_operand 1 "simple_mem_operand" "")))
6468 (set (match_operand:SI 2 "arith_reg_dest" "")
6469 (zero_extend:SI (match_operand 3 "arith_reg_operand" "")))]
6471 && GET_MODE (operands[1]) == GET_MODE (operands[3])
6472 && (GET_MODE (operands[1]) == QImode || GET_MODE (operands[1]) == HImode)
6473 && REGNO (operands[0]) == REGNO (operands[3])
6474 && (REGNO (operands[2]) == REGNO (operands[0])
6475 || peep2_reg_dead_p (2, operands[0]))"
6476 [(set (match_dup 2) (zero_extend:SI (match_dup 4)))]
6479 = replace_equiv_address (operands[1],
6480 gen_rtx_PLUS (SImode, XEXP (operands[1], 0),
6484 ;; -------------------------------------------------------------------------
6485 ;; Sign extension instructions
6486 ;; -------------------------------------------------------------------------
6488 ;; ??? This should be a define expand.
6489 ;; ??? Or perhaps it should be dropped?
6491 ;; convert_move generates good code for SH[1-4].
6492 (define_insn "extendsidi2"
6493 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6494 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,?f")))]
6500 [(set_attr "type" "arith_media,load_media,fpconv_media")
6501 (set (attr "highpart")
6502 (cond [(match_test "sh_contains_memref_p (insn)")
6503 (const_string "user")]
6504 (const_string "extend")))])
6506 (define_insn "extendhidi2"
6507 [(set (match_operand:DI 0 "register_operand" "=r,r")
6508 (sign_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6513 [(set_attr "type" "*,load_media")
6514 (set (attr "highpart")
6515 (cond [(match_test "sh_contains_memref_p (insn)")
6516 (const_string "user")]
6517 (const_string "ignore")))])
6520 [(set (match_operand:DI 0 "register_operand" "")
6521 (sign_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
6522 "TARGET_SHMEDIA && reload_completed"
6523 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
6524 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))]
6526 if (GET_CODE (operands[1]) == TRUNCATE)
6527 operands[1] = XEXP (operands[1], 0);
6530 (define_insn "extendqidi2"
6531 [(set (match_operand:DI 0 "register_operand" "=r,r")
6532 (sign_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6537 [(set_attr "type" "*,load_media")
6538 (set (attr "highpart")
6539 (cond [(match_test "sh_contains_memref_p (insn)")
6540 (const_string "user")]
6541 (const_string "ignore")))])
6544 [(set (match_operand:DI 0 "register_operand" "")
6545 (sign_extend:DI (match_operand:QI 1 "extend_reg_operand" "")))]
6546 "TARGET_SHMEDIA && reload_completed"
6547 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 56)))
6548 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))]
6550 if (GET_CODE (operands[1]) == TRUNCATE)
6551 operands[1] = XEXP (operands[1], 0);
6554 (define_expand "extend<mode>si2"
6555 [(set (match_operand:SI 0 "arith_reg_dest")
6556 (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))])
6558 (define_insn "*extendhisi2_media"
6559 [(set (match_operand:SI 0 "register_operand" "=r,r")
6560 (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6565 [(set_attr "type" "arith_media,load_media")
6566 (set (attr "highpart")
6567 (cond [(match_test "sh_contains_memref_p (insn)")
6568 (const_string "user")]
6569 (const_string "ignore")))])
6572 [(set (match_operand:SI 0 "register_operand" "")
6573 (sign_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
6574 "TARGET_SHMEDIA && reload_completed"
6575 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
6576 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
6578 rtx op1 = operands[1];
6579 if (GET_CODE (op1) == TRUNCATE)
6580 op1 = XEXP (op1, 0);
6582 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6583 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6586 (define_insn_and_split "*extend<mode>si2_compact_reg"
6587 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6588 (sign_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
6591 "&& can_create_pseudo_p ()"
6592 [(set (match_dup 0) (match_dup 2))]
6594 /* Sometimes combine fails to combine a T bit or negated T bit store to a
6595 reg with a following sign extension. In the split pass after combine,
6596 try to figure the extended reg was set. If it originated from the T
6597 bit we can replace the sign extension with a reg move, which will be
6599 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
6600 if (operands[2] == NULL_RTX)
6603 [(set_attr "type" "arith")])
6605 ;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute.
6607 (define_insn "*extend<mode>si2_compact_mem_disp"
6608 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
6612 (match_operand:SI 1 "arith_reg_operand" "%r,r")
6613 (match_operand:SI 2 "const_int_operand" "<disp04>,N")))))]
6614 "TARGET_SH1 && ! TARGET_SH2A
6615 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
6617 mov.<bw> @(%O2,%1),%0
6619 [(set_attr "type" "load")])
6621 (define_insn "*extend<mode>si2_compact_mem_disp"
6622 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r")
6626 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
6627 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>")))))]
6628 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
6630 mov.<bw> @(%O2,%1),%0
6632 mov.<bw> @(%O2,%1),%0"
6633 [(set_attr "type" "load")
6634 (set_attr "length" "2,2,4")])
6636 ;; The *_snd patterns will take care of other QImode/HImode addressing
6637 ;; modes than displacement addressing. They must be defined _after_ the
6638 ;; displacement addressing patterns. Otherwise the displacement addressing
6639 ;; patterns will not be picked.
6640 (define_insn "*extend<mode>si2_compact_snd"
6641 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6643 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand" "Snd")))]
6646 [(set_attr "type" "load")])
6648 (define_insn "*extendqisi2_media"
6649 [(set (match_operand:SI 0 "register_operand" "=r,r")
6650 (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6655 [(set_attr "type" "arith_media,load_media")
6656 (set (attr "highpart")
6657 (cond [(match_test "sh_contains_memref_p (insn)")
6658 (const_string "user")]
6659 (const_string "ignore")))])
6662 [(set (match_operand:SI 0 "register_operand" "")
6663 (sign_extend:SI (match_operand:QI 1 "extend_reg_operand" "")))]
6664 "TARGET_SHMEDIA && reload_completed"
6665 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24)))
6666 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
6668 rtx op1 = operands[1];
6669 if (GET_CODE (op1) == TRUNCATE)
6670 op1 = XEXP (op1, 0);
6672 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6673 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6676 (define_expand "extendqihi2"
6677 [(set (match_operand:HI 0 "arith_reg_dest")
6678 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand")))]
6681 (define_insn "*extendqihi2_compact_reg"
6682 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
6683 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
6686 [(set_attr "type" "arith")])
6688 ;; It would seem useful to combine the truncXi patterns into the movXi
6689 ;; patterns, but unary operators are ignored when matching constraints,
6690 ;; so we need separate patterns.
6691 (define_insn "truncdisi2"
6692 [(set (match_operand:SI 0 "general_movdst_operand" "=r,m,m,f,r,f")
6693 (truncate:SI (match_operand:DI 1 "register_operand" "r,r,f,r,f,f")))]
6702 [(set_attr "type" "arith_media,store_media,fstore_media,fload_media,
6703 fpconv_media,fmove_media")
6704 (set (attr "highpart")
6705 (cond [(match_test "sh_contains_memref_p (insn)")
6706 (const_string "user")]
6707 (const_string "extend")))])
6709 (define_insn "truncdihi2"
6710 [(set (match_operand:HI 0 "general_movdst_operand" "=?r,m")
6711 (truncate:HI (match_operand:DI 1 "register_operand" "r,r")))]
6714 static const char* alt[] =
6716 "shlli %1,48,%0" "\n"
6721 return alt[which_alternative];
6723 [(set_attr "type" "arith_media,store_media")
6724 (set_attr "length" "8,4")
6725 (set (attr "highpart")
6726 (cond [(match_test "sh_contains_memref_p (insn)")
6727 (const_string "user")]
6728 (const_string "extend")))])
6730 ; N.B. This should agree with LOAD_EXTEND_OP and movqi.
6731 ; Because we use zero extension, we can't provide signed QImode compares
6732 ; using a simple compare or conditional branch insn.
6733 (define_insn "truncdiqi2"
6734 [(set (match_operand:QI 0 "general_movdst_operand" "=r,m")
6735 (truncate:QI (match_operand:DI 1 "register_operand" "r,r")))]
6740 [(set_attr "type" "arith_media,store")
6741 (set (attr "highpart")
6742 (cond [(match_test "sh_contains_memref_p (insn)")
6743 (const_string "user")]
6744 (const_string "extend")))])
6746 ;; -------------------------------------------------------------------------
6747 ;; Move instructions
6748 ;; -------------------------------------------------------------------------
6750 ;; define push and pop so it is easy for sh.c
6751 ;; We can't use push and pop on SHcompact because the stack must always
6752 ;; be 8-byte aligned.
6753 (define_expand "push"
6754 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6755 (match_operand:SI 0 "register_operand" "r,l,x"))]
6756 "TARGET_SH1 && ! TARGET_SH5"
6759 (define_expand "pop"
6760 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
6761 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
6762 "TARGET_SH1 && ! TARGET_SH5"
6765 (define_expand "push_e"
6766 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
6767 (match_operand:SF 0 "" ""))
6768 (use (reg:SI FPSCR_MODES_REG))
6769 (clobber (scratch:SI))])]
6770 "TARGET_SH1 && ! TARGET_SH5"
6773 (define_insn "push_fpul"
6774 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
6775 "TARGET_SH2E && ! TARGET_SH5"
6777 [(set_attr "type" "fstore")
6778 (set_attr "late_fp_use" "yes")
6779 (set_attr "hit_stack" "yes")])
6781 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
6783 (define_expand "push_4"
6784 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
6785 (match_operand:DF 0 "" ""))
6786 (use (reg:SI FPSCR_MODES_REG))
6787 (clobber (scratch:SI))])]
6788 "TARGET_SH1 && ! TARGET_SH5"
6791 (define_expand "pop_e"
6792 [(parallel [(set (match_operand:SF 0 "" "")
6793 (mem:SF (post_inc:SI (reg:SI SP_REG))))
6794 (use (reg:SI FPSCR_MODES_REG))
6795 (clobber (scratch:SI))])]
6796 "TARGET_SH1 && ! TARGET_SH5"
6799 (define_insn "pop_fpul"
6800 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
6801 "TARGET_SH2E && ! TARGET_SH5"
6803 [(set_attr "type" "load")
6804 (set_attr "hit_stack" "yes")])
6806 (define_expand "pop_4"
6807 [(parallel [(set (match_operand:DF 0 "" "")
6808 (mem:DF (post_inc:SI (reg:SI SP_REG))))
6809 (use (reg:SI FPSCR_MODES_REG))
6810 (clobber (scratch:SI))])]
6811 "TARGET_SH1 && ! TARGET_SH5"
6814 (define_expand "push_fpscr"
6821 gen_frame_mem (SImode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)))),
6822 REG_INC, stack_pointer_rtx);
6826 (define_expand "pop_fpscr"
6833 gen_frame_mem (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)))),
6834 REG_INC, stack_pointer_rtx);
6838 ;; The clrt and sett patterns can happen as the result of optimization and
6840 ;; Comparisons might get simplified to a move of zero or 1 into the T reg.
6841 ;; In this case they might not disappear completely, because the T reg is
6842 ;; a fixed hard reg.
6843 ;; When DImode operations that use the T reg as carry/borrow are split into
6844 ;; individual SImode operations, the T reg is usually cleared before the
6845 ;; first SImode insn.
6847 [(set (reg:SI T_REG) (const_int 0))]
6850 [(set_attr "type" "mt_group")])
6853 [(set (reg:SI T_REG) (const_int 1))]
6856 [(set_attr "type" "mt_group")])
6858 ;; Use the combine pass to transform sequences such as
6862 ;; mov.l @(r0,r4),r0
6868 ;; See also PR 39423.
6869 ;; Notice that these patterns have a T_REG clobber, because the shift
6870 ;; sequence that will be split out might clobber the T_REG. Ideally, the
6871 ;; clobber would be added conditionally, depending on the result of
6872 ;; sh_ashlsi_clobbers_t_reg_p. When splitting out the shifts we must go
6873 ;; through the ashlsi3 expander in order to get the right shift insn --
6874 ;; a T_REG clobbering or non-clobbering shift sequence or dynamic shift.
6875 ;; FIXME: Combine never tries this kind of patterns for DImode.
6876 (define_insn_and_split "*movsi_index_disp_load"
6877 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6878 (match_operand:SI 1 "mem_index_disp_operand" "m"))
6879 (clobber (reg:SI T_REG))]
6882 "&& can_create_pseudo_p ()"
6883 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
6884 (set (match_dup 0) (match_dup 7))]
6886 rtx mem = operands[1];
6887 rtx plus0_rtx = XEXP (mem, 0);
6888 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6889 rtx mult_rtx = XEXP (plus1_rtx, 0);
6891 operands[1] = XEXP (mult_rtx, 0);
6892 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6893 operands[3] = XEXP (plus1_rtx, 1);
6894 operands[4] = XEXP (plus0_rtx, 1);
6895 operands[5] = gen_reg_rtx (SImode);
6896 operands[6] = gen_reg_rtx (SImode);
6898 replace_equiv_address (mem,
6899 gen_rtx_PLUS (SImode, operands[6], operands[4]));
6901 emit_insn (gen_ashlsi3 (operands[5], operands[1], operands[2]));
6904 (define_insn_and_split "*movhi_index_disp_load"
6905 [(set (match_operand:SI 0 "arith_reg_dest")
6906 (SZ_EXTEND:SI (match_operand:HI 1 "mem_index_disp_operand")))
6907 (clobber (reg:SI T_REG))]
6910 "&& can_create_pseudo_p ()"
6913 rtx mem = operands[1];
6914 rtx plus0_rtx = XEXP (mem, 0);
6915 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6916 rtx mult_rtx = XEXP (plus1_rtx, 0);
6918 rtx op_1 = XEXP (mult_rtx, 0);
6919 rtx op_2 = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6920 rtx op_3 = XEXP (plus1_rtx, 1);
6921 rtx op_4 = XEXP (plus0_rtx, 1);
6922 rtx op_5 = gen_reg_rtx (SImode);
6923 rtx op_6 = gen_reg_rtx (SImode);
6924 rtx op_7 = replace_equiv_address (mem, gen_rtx_PLUS (SImode, op_6, op_4));
6926 emit_insn (gen_ashlsi3 (op_5, op_1, op_2));
6927 emit_insn (gen_addsi3 (op_6, op_5, op_3));
6929 if (<CODE> == SIGN_EXTEND)
6931 emit_insn (gen_extendhisi2 (operands[0], op_7));
6934 else if (<CODE> == ZERO_EXTEND)
6936 /* On SH2A the movu.w insn can be used for zero extending loads. */
6938 emit_insn (gen_zero_extendhisi2 (operands[0], op_7));
6941 emit_insn (gen_extendhisi2 (operands[0], op_7));
6942 emit_insn (gen_zero_extendhisi2 (operands[0],
6943 gen_lowpart (HImode, operands[0])));
6951 (define_insn_and_split "*mov<mode>_index_disp_store"
6952 [(set (match_operand:HISI 0 "mem_index_disp_operand" "=m")
6953 (match_operand:HISI 1 "arith_reg_operand" "r"))
6954 (clobber (reg:SI T_REG))]
6957 "&& can_create_pseudo_p ()"
6958 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
6959 (set (match_dup 7) (match_dup 1))]
6961 rtx mem = operands[0];
6962 rtx plus0_rtx = XEXP (mem, 0);
6963 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6964 rtx mult_rtx = XEXP (plus1_rtx, 0);
6966 operands[0] = XEXP (mult_rtx, 0);
6967 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6968 operands[3] = XEXP (plus1_rtx, 1);
6969 operands[4] = XEXP (plus0_rtx, 1);
6970 operands[5] = gen_reg_rtx (SImode);
6971 operands[6] = gen_reg_rtx (SImode);
6973 replace_equiv_address (mem,
6974 gen_rtx_PLUS (SImode, operands[6], operands[4]));
6976 emit_insn (gen_ashlsi3 (operands[5], operands[0], operands[2]));
6979 ;; t/r must come after r/r, lest reload will try to reload stuff like
6980 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
6981 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
6982 (define_insn "movsi_i"
6983 [(set (match_operand:SI 0 "general_movdst_operand"
6984 "=r,r,r,r,r,r,m,<,<,x,l,x,l,r")
6985 (match_operand:SI 1 "general_movsrc_operand"
6986 "Q,r,I08,mr,x,l,r,x,l,r,r,>,>,i"))]
6990 && (register_operand (operands[0], SImode)
6991 || register_operand (operands[1], SImode))"
7007 [(set_attr "type" "pcload_si,move,movi8,load_si,mac_gp,prget,store,mac_mem,
7008 pstore,gp_mac,prset,mem_mac,pload,pcload_si")
7009 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
7011 ;; t/r must come after r/r, lest reload will try to reload stuff like
7012 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
7013 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
7014 ;; will require a reload.
7015 ;; ??? We can't include f/f because we need the proper FPSCR setting when
7016 ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
7017 (define_insn "movsi_ie"
7018 [(set (match_operand:SI 0 "general_movdst_operand"
7019 "=r,r,r,r,r,r,r,r,mr,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
7020 (match_operand:SI 1 "general_movsrc_operand"
7021 "Q,r,I08,I20,I28,mr,x,l,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
7022 "(TARGET_SH2E || TARGET_SH2A)
7023 && ((register_operand (operands[0], SImode)
7024 && !fpscr_operand (operands[0], SImode))
7025 || (register_operand (operands[1], SImode)
7026 && !fpscr_operand (operands[1], SImode)))"
7051 ! move optimized away"
7052 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
7053 mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,
7054 pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
7055 (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
7056 (set_attr_alternative "length"
7063 (match_test "TARGET_SH2A")
7064 (const_int 4) (const_int 2))
7068 (match_test "TARGET_SH2A")
7069 (const_int 4) (const_int 2))
7086 (define_insn "movsi_i_lowpart"
7087 [(set (strict_low_part
7088 (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
7089 (match_operand:SI 1 "general_movsrc_operand" "Q,r,I08,mr,x,l,r,i"))]
7091 && (register_operand (operands[0], SImode)
7092 || register_operand (operands[1], SImode))"
7102 [(set_attr "type" "pcload,move,arith,load,mac_gp,prget,store,pcload")])
7104 (define_insn_and_split "load_ra"
7105 [(set (match_operand:SI 0 "general_movdst_operand" "")
7106 (unspec:SI [(match_operand:SI 1 "register_operand" "")] UNSPEC_RA))]
7109 "&& ! currently_expanding_to_rtl"
7110 [(set (match_dup 0) (match_dup 1))]
7112 if (TARGET_SHCOMPACT && crtl->saves_all_registers)
7113 operands[1] = gen_frame_mem (SImode, return_address_pointer_rtx);
7116 ;; The '?'s in the following constraints may not reflect the time taken
7117 ;; to perform the move. They are there to discourage the use of floating-
7118 ;; point registers for storing integer values.
7119 (define_insn "*movsi_media"
7120 [(set (match_operand:SI 0 "general_movdst_operand"
7121 "=r,r,r,r,m,f?,m,f?,r,f?,*b,r,b")
7122 (match_operand:SI 1 "general_movsrc_operand"
7123 "r,I16Css,nCpg,m,rZ,m,f?,rZ,f?,f?,r,*b,Csy"))]
7125 && (register_operand (operands[0], SImode)
7126 || sh_register_operand (operands[1], SImode)
7127 || GET_CODE (operands[1]) == TRUNCATE)"
7142 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
7143 fload_media,fstore_media,fload_media,fpconv_media,
7144 fmove_media,ptabs_media,gettr_media,pt_media")
7145 (set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12")
7146 (set (attr "highpart")
7147 (cond [(match_test "sh_contains_memref_p (insn)")
7148 (const_string "user")]
7149 (const_string "ignore")))])
7151 (define_insn "*movsi_media_nofpu"
7152 [(set (match_operand:SI 0 "general_movdst_operand"
7153 "=r,r,r,r,m,*b,r,*b")
7154 (match_operand:SI 1 "general_movsrc_operand"
7155 "r,I16Css,nCpg,m,rZ,r,*b,Csy"))]
7157 && (register_operand (operands[0], SImode)
7158 || sh_register_operand (operands[1], SImode)
7159 || GET_CODE (operands[1]) == TRUNCATE)"
7169 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
7170 ptabs_media,gettr_media,pt_media")
7171 (set_attr "length" "4,4,8,4,4,4,4,12")
7172 (set (attr "highpart")
7173 (cond [(match_test "sh_contains_memref_p (insn)")
7174 (const_string "user")]
7175 (const_string "ignore")))])
7177 (define_expand "movsi_const"
7178 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
7179 (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s")
7180 (const_int 16)] UNSPEC_EXTRACT_S16)))
7182 (ior:SI (ashift:SI (match_dup 0) (const_int 16))
7183 (const:SI (unspec:SI [(match_dup 1)
7184 (const_int 0)] UNSPEC_EXTRACT_U16))))]
7185 "TARGET_SHMEDIA && reload_completed
7186 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7188 if (GET_CODE (operands[1]) == LABEL_REF
7189 && GET_CODE (XEXP (operands[1], 0)) == CODE_LABEL)
7190 LABEL_NUSES (XEXP (operands[1], 0)) += 2;
7191 else if (GOTOFF_P (operands[1]))
7193 rtx unspec = XEXP (operands[1], 0);
7195 if (! UNSPEC_GOTOFF_P (unspec))
7197 unspec = XEXP (unspec, 0);
7198 if (! UNSPEC_GOTOFF_P (unspec))
7201 if (GET_CODE (XVECEXP (unspec , 0, 0)) == LABEL_REF
7202 && (GET_CODE (XEXP (XVECEXP (unspec, 0, 0), 0)) == CODE_LABEL))
7203 LABEL_NUSES (XEXP (XVECEXP (unspec, 0, 0), 0)) += 2;
7207 (define_expand "movsi_const_16bit"
7208 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
7209 (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s")
7210 (const_int 0)] UNSPEC_EXTRACT_S16)))]
7211 "TARGET_SHMEDIA && flag_pic && reload_completed
7212 && GET_CODE (operands[1]) == SYMBOL_REF"
7216 [(set (match_operand:SI 0 "arith_reg_dest" "")
7217 (match_operand:SI 1 "immediate_operand" ""))]
7218 "TARGET_SHMEDIA && reload_completed
7219 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7222 rtx insn = emit_insn (gen_movsi_const (operands[0], operands[1]));
7224 set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1]));
7230 [(set (match_operand:SI 0 "register_operand" "")
7231 (match_operand:SI 1 "immediate_operand" ""))]
7232 "TARGET_SHMEDIA && reload_completed
7233 && ((CONST_INT_P (operands[1])
7234 && ! satisfies_constraint_I16 (operands[1]))
7235 || GET_CODE (operands[1]) == CONST_DOUBLE)"
7236 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
7238 (define_expand "movsi"
7239 [(set (match_operand:SI 0 "general_movdst_operand" "")
7240 (match_operand:SI 1 "general_movsrc_operand" ""))]
7243 prepare_move_operands (operands, SImode);
7246 (define_expand "ic_invalidate_line"
7247 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
7248 (match_dup 1)] UNSPEC_ICACHE)
7249 (clobber (scratch:SI))])]
7250 "TARGET_HARD_SH4 || TARGET_SH5"
7254 emit_insn (gen_ic_invalidate_line_media (operands[0]));
7257 else if (TARGET_SHCOMPACT)
7259 operands[1] = function_symbol (NULL, "__ic_invalidate", SFUNC_STATIC);
7260 operands[1] = force_reg (Pmode, operands[1]);
7261 emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1]));
7264 else if (TARGET_SH4A || TARGET_SH4_300)
7266 emit_insn (gen_ic_invalidate_line_sh4a (operands[0]));
7269 operands[0] = force_reg (Pmode, operands[0]);
7270 operands[1] = force_reg (Pmode, GEN_INT (trunc_int_for_mode (0xf0000008,
7274 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
7275 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
7276 ;; the requirement *1*00 for associative address writes. The alignment of
7277 ;; %0 implies that its least significant bit is cleared,
7278 ;; thus we clear the V bit of a matching entry if there is one.
7279 (define_insn "ic_invalidate_line_i"
7280 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
7281 (match_operand:SI 1 "register_operand" "r")]
7283 (clobber (match_scratch:SI 2 "=&r"))]
7286 return "ocbwb @%0" "\n"
7287 " extu.w %0,%2" "\n"
7291 [(set_attr "length" "8")
7292 (set_attr "type" "cwb")])
7294 (define_insn "ic_invalidate_line_sh4a"
7295 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
7297 "TARGET_SH4A || TARGET_SH4_300"
7299 return "ocbwb @%0" "\n"
7303 [(set_attr "length" "16") ;; FIXME: Why 16 and not 6? Looks like typo.
7304 (set_attr "type" "cwb")])
7306 ;; ??? could make arg 0 an offsettable memory operand to allow to save
7307 ;; an add in the code that calculates the address.
7308 (define_insn "ic_invalidate_line_media"
7309 [(unspec_volatile [(match_operand 0 "any_register_operand" "r")]
7313 return "ocbwb %0,0" "\n"
7318 [(set_attr "length" "16")
7319 (set_attr "type" "invalidate_line_media")])
7321 (define_insn "ic_invalidate_line_compact"
7322 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
7323 (match_operand:SI 1 "register_operand" "r")]
7325 (clobber (reg:SI PR_REG))]
7328 [(set_attr "type" "sfunc")
7329 (set_attr "needs_delay_slot" "yes")])
7331 (define_expand "initialize_trampoline"
7332 [(match_operand:SI 0 "" "")
7333 (match_operand:SI 1 "" "")
7334 (match_operand:SI 2 "" "")]
7339 tramp = force_reg (Pmode, operands[0]);
7340 sfun = force_reg (Pmode, function_symbol (NULL, "__init_trampoline",
7342 emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]);
7343 emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]);
7345 emit_insn (gen_initialize_trampoline_compact (tramp, sfun));
7349 (define_insn "initialize_trampoline_compact"
7350 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
7351 (match_operand:SI 1 "register_operand" "r")
7352 (reg:SI R2_REG) (reg:SI R3_REG)]
7355 (clobber (reg:SI PR_REG))]
7358 [(set_attr "type" "sfunc")
7359 (set_attr "needs_delay_slot" "yes")])
7361 (define_expand "mov<mode>"
7362 [(set (match_operand:QIHI 0 "general_movdst_operand")
7363 (match_operand:QIHI 1 "general_movsrc_operand"))]
7366 if (can_create_pseudo_p () && CONST_INT_P (operands[1])
7367 && REG_P (operands[0]) && REGNO (operands[0]) != R0_REG)
7369 rtx reg = gen_reg_rtx(SImode);
7370 emit_move_insn (reg, operands[1]);
7371 operands[1] = gen_lowpart (<MODE>mode, reg);
7374 prepare_move_operands (operands, <MODE>mode);
7377 ;; Specifying the displacement addressing load / store patterns separately
7378 ;; before the generic movqi / movhi pattern allows controlling the order
7379 ;; in which load / store insns are selected in a more fine grained way.
7380 ;; FIXME: The non-SH2A and SH2A variants should be combined by adding
7381 ;; "enabled" attribute as it is done in other targets.
7382 (define_insn "*mov<mode>_store_mem_disp04"
7384 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r")
7385 (match_operand:SI 1 "const_int_operand" "<disp04>,N")))
7386 (match_operand:QIHI 2 "arith_reg_operand" "z,r"))]
7387 "TARGET_SH1 && sh_legitimate_index_p (<MODE>mode, operands[1], false, true)"
7389 mov.<bw> %2,@(%O1,%0)
7391 [(set_attr "type" "store")])
7393 (define_insn "*mov<mode>_store_mem_disp12"
7395 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
7396 (match_operand:SI 1 "const_int_operand" "<disp12>")))
7397 (match_operand:QIHI 2 "arith_reg_operand" "r"))]
7398 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[1], true, true)"
7399 "mov.<bw> %2,@(%O1,%0)"
7400 [(set_attr "type" "store")
7401 (set_attr "length" "4")])
7403 (define_insn "*mov<mode>_load_mem_disp04"
7404 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r")
7406 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
7407 (match_operand:SI 2 "const_int_operand" "<disp04>,N"))))]
7408 "TARGET_SH1 && ! TARGET_SH2A
7409 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
7411 mov.<bw> @(%O2,%1),%0
7413 [(set_attr "type" "load")])
7415 (define_insn "*mov<mode>_load_mem_disp12"
7416 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r,r")
7419 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
7420 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>"))))]
7421 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
7423 mov.<bw> @(%O2,%1),%0
7425 mov.<bw> @(%O2,%1),%0"
7426 [(set_attr "type" "load")
7427 (set_attr "length" "2,2,4")])
7429 ;; The order of the constraint alternatives is important here.
7430 ;; Q/r has to come first, otherwise PC relative loads might wrongly get
7431 ;; placed into delay slots. Since there is no QImode PC relative load, the
7432 ;; Q constraint and general_movsrc_operand will reject it for QImode.
7433 ;; The Sid/Ssd alternatives should come before Sdd in order to avoid
7434 ;; a preference of using r0 als the register operand for addressing modes
7435 ;; other than displacement addressing.
7436 ;; The Sdd alternatives allow only r0 as register operand, even though on
7437 ;; SH2A any register could be allowed by switching to a 32 bit insn.
7438 ;; Generally sticking to the r0 is preferrable, since it generates smaller
7439 ;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.
7440 (define_insn "*mov<mode>"
7441 [(set (match_operand:QIHI 0 "general_movdst_operand"
7442 "=r,r,r,Sid,^zr,Ssd,r, Sdd,z, r,l")
7443 (match_operand:QIHI 1 "general_movsrc_operand"
7444 "Q,r,i,^zr,Sid,r, Ssd,z, Sdd,l,r"))]
7446 && (arith_reg_operand (operands[0], <MODE>mode)
7447 || arith_reg_operand (operands[1], <MODE>mode))"
7460 [(set_attr "type" "pcload,move,movi8,store,load,store,load,store,load,prget,prset")
7461 (set (attr "length")
7462 (cond [(and (match_operand 0 "displacement_mem_operand")
7463 (not (match_operand 0 "short_displacement_mem_operand")))
7465 (and (match_operand 1 "displacement_mem_operand")
7466 (not (match_operand 1 "short_displacement_mem_operand")))
7470 (define_insn "*movqi_media"
7471 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
7472 (match_operand:QI 1 "general_movsrc_operand" "r,I16Css,m,rZ"))]
7474 && (arith_reg_operand (operands[0], QImode)
7475 || extend_reg_or_0_operand (operands[1], QImode))"
7481 [(set_attr "type" "arith_media,arith_media,load_media,store_media")
7482 (set (attr "highpart")
7483 (cond [(match_test "sh_contains_memref_p (insn)")
7484 (const_string "user")]
7485 (const_string "ignore")))])
7487 (define_expand "reload_inqi"
7488 [(set (match_operand:SI 2 "" "=&r")
7489 (match_operand:QI 1 "inqhi_operand" ""))
7490 (set (match_operand:QI 0 "arith_reg_operand" "=r")
7491 (truncate:QI (match_dup 3)))]
7494 rtx inner = XEXP (operands[1], 0);
7495 int regno = REGNO (inner);
7497 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
7498 operands[1] = gen_rtx_REG (SImode, regno);
7499 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
7502 (define_insn "*movhi_media"
7503 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m")
7504 (match_operand:HI 1 "general_movsrc_operand" "r,I16Css,n,m,rZ"))]
7506 && (arith_reg_operand (operands[0], HImode)
7507 || arith_reg_or_0_operand (operands[1], HImode))"
7514 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
7515 (set (attr "highpart")
7516 (cond [(match_test "sh_contains_memref_p (insn)")
7517 (const_string "user")]
7518 (const_string "ignore")))])
7521 [(set (match_operand:HI 0 "register_operand" "")
7522 (match_operand:HI 1 "immediate_operand" ""))]
7523 "TARGET_SHMEDIA && reload_completed
7524 && ! satisfies_constraint_I16 (operands[1])"
7525 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
7527 (define_expand "reload_inhi"
7528 [(set (match_operand:SI 2 "" "=&r")
7529 (match_operand:HI 1 "inqhi_operand" ""))
7530 (set (match_operand:HI 0 "arith_reg_operand" "=r")
7531 (truncate:HI (match_dup 3)))]
7534 rtx inner = XEXP (operands[1], 0);
7535 int regno = REGNO (inner);
7537 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
7538 operands[1] = gen_rtx_REG (SImode, regno);
7539 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
7542 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
7543 ;; compiled with -m2 -ml -O3 -funroll-loops
7544 (define_insn "*movdi_i"
7545 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
7546 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I08,i,x,r"))]
7548 && (arith_reg_operand (operands[0], DImode)
7549 || arith_reg_operand (operands[1], DImode))"
7551 return output_movedouble (insn, operands, DImode);
7553 [(set_attr "length" "4")
7554 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
7556 ;; If the output is a register and the input is memory or a register, we have
7557 ;; to be careful and see which word needs to be loaded first.
7559 [(set (match_operand:DI 0 "general_movdst_operand" "")
7560 (match_operand:DI 1 "general_movsrc_operand" ""))]
7561 "TARGET_SH1 && reload_completed"
7562 [(set (match_dup 2) (match_dup 3))
7563 (set (match_dup 4) (match_dup 5))]
7567 if ((MEM_P (operands[0])
7568 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
7569 || (MEM_P (operands[1])
7570 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
7573 switch (GET_CODE (operands[0]))
7576 regno = REGNO (operands[0]);
7579 regno = subreg_regno (operands[0]);
7588 if (regno == -1 || ! refers_to_regno_p (regno, operands[1]))
7590 operands[2] = operand_subword (operands[0], 0, 0, DImode);
7591 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7592 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7593 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7597 operands[2] = operand_subword (operands[0], 1, 0, DImode);
7598 operands[3] = operand_subword (operands[1], 1, 0, DImode);
7599 operands[4] = operand_subword (operands[0], 0, 0, DImode);
7600 operands[5] = operand_subword (operands[1], 0, 0, DImode);
7603 if (operands[2] == 0 || operands[3] == 0
7604 || operands[4] == 0 || operands[5] == 0)
7608 ;; The '?'s in the following constraints may not reflect the time taken
7609 ;; to perform the move. They are there to discourage the use of floating-
7610 ;; point registers for storing integer values.
7611 (define_insn "*movdi_media"
7612 [(set (match_operand:DI 0 "general_movdst_operand"
7613 "=r,r,r,rl,m,f?,m,f?,r,f?,*b,r,*b")
7614 (match_operand:DI 1 "general_movsrc_operand"
7615 "r,I16Css,nCpgF,m,rlZ,m,f?,rZ,f?,f?,r,*b,Csy"))]
7617 && (register_operand (operands[0], DImode)
7618 || sh_register_operand (operands[1], DImode))"
7633 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
7634 fload_media,fstore_media,fload_media,dfpconv_media,
7635 fmove_media,ptabs_media,gettr_media,pt_media")
7636 (set_attr "length" "4,4,16,4,4,4,4,4,4,4,4,4,*")])
7638 (define_insn "*movdi_media_nofpu"
7639 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b,r,*b");
7640 (match_operand:DI 1 "general_movsrc_operand" "r,I16Css,nCpgF,m,rlZ,r,*b,Csy"))]
7642 && (register_operand (operands[0], DImode)
7643 || sh_register_operand (operands[1], DImode))"
7653 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
7654 ptabs_media,gettr_media,pt_media")
7655 (set_attr "length" "4,4,16,4,4,4,4,*")])
7657 (define_insn "*movdi_media_I16"
7658 [(set (match_operand:DI 0 "ext_dest_operand" "=r")
7659 (match_operand:DI 1 "const_int_operand" "I16"))]
7660 "TARGET_SHMEDIA && reload_completed"
7662 [(set_attr "type" "arith_media")
7663 (set_attr "length" "4")])
7666 [(set (match_operand:DI 0 "arith_reg_dest" "")
7667 (match_operand:DI 1 "immediate_operand" ""))]
7668 "TARGET_SHMEDIA && reload_completed
7669 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7670 [(set (match_dup 0) (match_dup 1))]
7674 if (TARGET_SHMEDIA64)
7675 insn = emit_insn (gen_movdi_const (operands[0], operands[1]));
7677 insn = emit_insn (gen_movdi_const_32bit (operands[0], operands[1]));
7679 set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1]));
7684 (define_expand "movdi_const"
7685 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7686 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7687 (const_int 48)] UNSPEC_EXTRACT_S16)))
7689 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7690 (const:DI (unspec:DI [(match_dup 1)
7691 (const_int 32)] UNSPEC_EXTRACT_U16))))
7693 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7694 (const:DI (unspec:DI [(match_dup 1)
7695 (const_int 16)] UNSPEC_EXTRACT_U16))))
7697 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7698 (const:DI (unspec:DI [(match_dup 1)
7699 (const_int 0)] UNSPEC_EXTRACT_U16))))]
7700 "TARGET_SHMEDIA64 && reload_completed
7701 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7703 sh_mark_label (operands[1], 4);
7706 (define_expand "movdi_const_32bit"
7707 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7708 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7709 (const_int 16)] UNSPEC_EXTRACT_S16)))
7711 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7712 (const:DI (unspec:DI [(match_dup 1)
7713 (const_int 0)] UNSPEC_EXTRACT_U16))))]
7714 "TARGET_SHMEDIA32 && reload_completed
7715 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7717 sh_mark_label (operands[1], 2);
7720 (define_expand "movdi_const_16bit"
7721 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7722 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7723 (const_int 0)] UNSPEC_EXTRACT_S16)))]
7724 "TARGET_SHMEDIA && flag_pic && reload_completed
7725 && GET_CODE (operands[1]) == SYMBOL_REF"
7729 [(set (match_operand:DI 0 "ext_dest_operand" "")
7730 (match_operand:DI 1 "immediate_operand" ""))]
7731 "TARGET_SHMEDIA && reload_completed
7732 && CONST_INT_P (operands[1])
7733 && ! satisfies_constraint_I16 (operands[1])"
7734 [(set (match_dup 0) (match_dup 2))
7737 unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
7738 unsigned HOST_WIDE_INT low = val;
7739 unsigned HOST_WIDE_INT high = val;
7740 unsigned HOST_WIDE_INT sign;
7741 unsigned HOST_WIDE_INT val2 = val ^ (val-1);
7743 /* Zero-extend the 16 least-significant bits. */
7746 /* Arithmetic shift right the word by 16 bits. */
7748 if (GET_CODE (operands[0]) == SUBREG
7749 && GET_MODE (SUBREG_REG (operands[0])) == SImode)
7758 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
7764 /* If we can't generate the constant with a two-insn movi / shori
7765 sequence, try some other strategies. */
7766 if (! CONST_OK_FOR_I16 (high))
7768 /* Try constant load / left shift. We know VAL != 0. */
7769 val2 = val ^ (val-1);
7772 int trailing_zeroes = exact_log2 ((val2 >> 16) + 1) + 15;
7774 if (CONST_OK_FOR_I16 (val >> trailing_zeroes)
7775 || (! CONST_OK_FOR_I16 (high >> 16)
7776 && CONST_OK_FOR_I16 (val >> (trailing_zeroes + 16))))
7778 val2 = (HOST_WIDE_INT) val >> trailing_zeroes;
7779 operands[1] = gen_ashldi3_media (operands[0], operands[0],
7780 GEN_INT (trailing_zeroes));
7784 /* Try constant load / right shift. */
7785 val2 = (val >> 15) + 1;
7786 if (val2 == (val2 & -val2))
7788 int shift = 49 - exact_log2 (val2);
7790 val2 = trunc_int_for_mode (val << shift, DImode);
7791 if (CONST_OK_FOR_I16 (val2))
7793 operands[1] = gen_lshrdi3_media (operands[0], operands[0],
7799 val2 = val & 0xffff;
7800 if ((val >> 16 & 0xffff) == val2
7801 && (val >> 32 & 0xffff) == val2
7802 && (val >> 48 & 0xffff) == val2)
7804 val2 = (HOST_WIDE_INT) val >> 48;
7805 operands[1] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
7806 operands[1] = gen_mperm_w0 (operands[1], operands[1]);
7809 /* Try movi / mshflo.l */
7810 val2 = (HOST_WIDE_INT) val >> 32;
7811 if (val2 == ((unsigned HOST_WIDE_INT)
7812 trunc_int_for_mode (val, SImode)))
7814 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
7818 /* Try movi / mshflo.l w/ r63. */
7819 val2 = val + ((HOST_WIDE_INT) -1 << 32);
7820 if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2))
7822 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
7828 operands[1] = gen_shori_media (operands[0], operands[0], GEN_INT (low));
7831 operands[2] = GEN_INT (val2);
7835 [(set (match_operand:DI 0 "ext_dest_operand" "")
7836 (match_operand:DI 1 "immediate_operand" ""))]
7837 "TARGET_SHMEDIA && reload_completed
7838 && GET_CODE (operands[1]) == CONST_DOUBLE"
7839 [(set (match_dup 0) (match_dup 2))
7841 (ior:DI (ashift:DI (match_dup 0) (const_int 16)) (match_dup 1)))]
7843 unsigned HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
7844 unsigned HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
7845 unsigned HOST_WIDE_INT val = low;
7846 unsigned HOST_WIDE_INT sign;
7848 /* Zero-extend the 16 least-significant bits. */
7850 operands[1] = GEN_INT (val);
7852 /* Arithmetic shift right the double-word by 16 bits. */
7854 low |= (high & 0xffff) << (HOST_BITS_PER_WIDE_INT - 16);
7857 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
7861 /* This will only be true if high is a sign-extension of low, i.e.,
7862 it must be either 0 or (unsigned)-1, and be zero iff the
7863 most-significant bit of low is set. */
7864 if (high + (low >> (HOST_BITS_PER_WIDE_INT - 1)) == 0)
7865 operands[2] = GEN_INT (low);
7867 operands[2] = immed_double_const (low, high, DImode);
7870 (define_insn "shori_media"
7871 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
7872 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0,0")
7874 (match_operand:DI 2 "immediate_operand" "K16Csu,nF")))]
7875 "TARGET_SHMEDIA && (reload_completed || arith_reg_dest (operands[0], DImode))"
7879 [(set_attr "type" "arith_media,*")])
7881 (define_insn "*shori_media_si"
7882 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
7883 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
7885 (match_operand:SI 2 "immediate_operand" "K16Csu")))]
7889 (define_expand "movdi"
7890 [(set (match_operand:DI 0 "general_movdst_operand" "")
7891 (match_operand:DI 1 "general_movsrc_operand" ""))]
7894 prepare_move_operands (operands, DImode);
7897 (define_insn "movdf_media"
7898 [(set (match_operand:DF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
7899 (match_operand:DF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
7901 && (register_operand (operands[0], DFmode)
7902 || sh_register_operand (operands[1], DFmode))"
7913 [(set_attr "type" "fmove_media,fload_media,dfpconv_media,arith_media,*,
7914 fload_media,fstore_media,load_media,store_media")])
7916 (define_insn "movdf_media_nofpu"
7917 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
7918 (match_operand:DF 1 "general_movsrc_operand" "r,F,m,rZ"))]
7920 && (register_operand (operands[0], DFmode)
7921 || sh_register_operand (operands[1], DFmode))"
7927 [(set_attr "type" "arith_media,*,load_media,store_media")])
7930 [(set (match_operand:DF 0 "arith_reg_dest" "")
7931 (match_operand:DF 1 "immediate_operand" ""))]
7932 "TARGET_SHMEDIA && reload_completed"
7933 [(set (match_dup 3) (match_dup 2))]
7935 int endian = WORDS_BIG_ENDIAN ? 1 : 0;
7937 REAL_VALUE_TYPE value;
7939 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
7940 REAL_VALUE_TO_TARGET_DOUBLE (value, values);
7942 if (HOST_BITS_PER_WIDE_INT >= 64)
7943 operands[2] = immed_double_const ((unsigned long) values[endian]
7944 | ((HOST_WIDE_INT) values[1 - endian]
7948 gcc_assert (HOST_BITS_PER_WIDE_INT == 32);
7949 operands[2] = immed_double_const (values[endian], values[1 - endian],
7953 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
7956 ;; FIXME: This should be a define_insn_and_split.
7957 (define_insn "movdf_k"
7958 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
7959 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
7961 && (! (TARGET_SH4 || TARGET_SH2A_DOUBLE) || reload_completed
7962 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
7963 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
7964 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
7965 && (arith_reg_operand (operands[0], DFmode)
7966 || arith_reg_operand (operands[1], DFmode))"
7968 return output_movedouble (insn, operands, DFmode);
7970 [(set_attr "length" "4")
7971 (set_attr "type" "move,pcload,load,store")])
7973 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
7974 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
7975 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
7976 ;; the d/m/c/X alternative, which is split later into single-precision
7977 ;; instructions. And when not optimizing, no splits are done before fixing
7978 ;; up pcloads, so we need usable length information for that.
7979 (define_insn "movdf_i4"
7980 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
7981 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
7982 (use (reg:SI FPSCR_MODES_REG))
7983 (clobber (match_scratch:SI 2 "=X,X,&z,X,X,X,X,X,X,X"))]
7984 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7985 && (arith_reg_operand (operands[0], DFmode)
7986 || arith_reg_operand (operands[1], DFmode))"
7988 switch (which_alternative)
7992 return "fmov %1,%0";
7993 else if (REGNO (operands[0]) != REGNO (operands[1]) + 1)
7994 return "fmov %R1,%R0" "\n"
7997 return "fmov %S1,%S0" "\n"
8001 return "fmov.d %1,%0";
8006 [(set_attr_alternative "length"
8007 [(if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 8))
8009 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
8010 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
8011 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
8013 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
8014 ;; We can't use 4-byte push/pop on SHcompact, so we have to
8015 ;; increment or decrement r15 explicitly.
8017 (match_test "TARGET_SHCOMPACT")
8018 (const_int 10) (const_int 8))
8020 (match_test "TARGET_SHCOMPACT")
8021 (const_int 10) (const_int 8))])
8022 (set_attr "type" "fmove,move,pcfload,fload,fstore,pcload,load,store,load,fload")
8023 (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*")
8024 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
8025 (const_string "double")
8026 (const_string "none")))])
8028 ;; Moving DFmode between fp/general registers through memory
8029 ;; (the top of the stack) is faster than moving through fpul even for
8030 ;; little endian. Because the type of an instruction is important for its
8031 ;; scheduling, it is beneficial to split these operations, rather than
8032 ;; emitting them in one single chunk, even if this will expose a stack
8033 ;; use that will prevent scheduling of other stack accesses beyond this
8036 [(set (match_operand:DF 0 "register_operand")
8037 (match_operand:DF 1 "register_operand"))
8038 (use (reg:SI FPSCR_MODES_REG))
8039 (clobber (match_scratch:SI 2))]
8040 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed
8041 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
8046 if (TARGET_SH5 && true_regnum (operands[1]) < 16)
8048 emit_move_insn (stack_pointer_rtx,
8049 plus_constant (Pmode, stack_pointer_rtx, -8));
8050 tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx);
8053 tos = gen_tmp_stack_mem (DFmode,
8054 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
8055 insn = emit_insn (gen_movdf_i4 (tos, operands[1]));
8056 if (! (TARGET_SH5 && true_regnum (operands[1]) < 16))
8057 add_reg_note (insn, REG_INC, stack_pointer_rtx);
8058 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
8059 tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx);
8061 tos = gen_tmp_stack_mem (DFmode,
8062 gen_rtx_POST_INC (Pmode, stack_pointer_rtx));
8063 insn = emit_insn (gen_movdf_i4 (operands[0], tos));
8064 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
8065 emit_move_insn (stack_pointer_rtx,
8066 plus_constant (Pmode, stack_pointer_rtx, 8));
8068 add_reg_note (insn, REG_INC, stack_pointer_rtx);
8072 ;; local-alloc sometimes allocates scratch registers even when not required,
8073 ;; so we must be prepared to handle these.
8075 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
8077 [(set (match_operand:DF 0 "general_movdst_operand" "")
8078 (match_operand:DF 1 "general_movsrc_operand" ""))
8079 (use (reg:SI FPSCR_MODES_REG))
8080 (clobber (match_scratch:SI 2))]
8081 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
8083 && true_regnum (operands[0]) < 16
8084 && true_regnum (operands[1]) < 16"
8085 [(set (match_dup 0) (match_dup 1))]
8087 /* If this was a reg <-> mem operation with base + index reg addressing,
8088 we have to handle this in a special way. */
8089 rtx mem = operands[0];
8091 if (! memory_operand (mem, DFmode))
8096 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
8097 mem = SUBREG_REG (mem);
8100 rtx addr = XEXP (mem, 0);
8101 if (GET_CODE (addr) == PLUS
8102 && REG_P (XEXP (addr, 0))
8103 && REG_P (XEXP (addr, 1)))
8106 rtx reg0 = gen_rtx_REG (Pmode, 0);
8107 rtx regop = operands[store_p], word0 ,word1;
8109 if (GET_CODE (regop) == SUBREG)
8110 alter_subreg (®op, true);
8111 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
8115 mem = copy_rtx (mem);
8116 PUT_MODE (mem, SImode);
8117 word0 = gen_rtx_SUBREG (SImode, regop, 0);
8118 alter_subreg (&word0, true);
8119 word1 = gen_rtx_SUBREG (SImode, regop, 4);
8120 alter_subreg (&word1, true);
8121 if (store_p || ! refers_to_regno_p (REGNO (word0), addr))
8124 ? gen_movsi_ie (mem, word0)
8125 : gen_movsi_ie (word0, mem));
8126 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
8127 mem = copy_rtx (mem);
8129 ? gen_movsi_ie (mem, word1)
8130 : gen_movsi_ie (word1, mem));
8131 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
8135 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
8136 emit_insn (gen_movsi_ie (word1, mem));
8137 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
8138 mem = copy_rtx (mem);
8139 emit_insn (gen_movsi_ie (word0, mem));
8146 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
8148 [(set (match_operand:DF 0 "register_operand" "")
8149 (match_operand:DF 1 "memory_operand" ""))
8150 (use (reg:SI FPSCR_MODES_REG))
8151 (clobber (reg:SI R0_REG))]
8152 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed"
8153 [(parallel [(set (match_dup 0) (match_dup 1))
8154 (use (reg:SI FPSCR_MODES_REG))
8155 (clobber (scratch:SI))])]
8158 (define_expand "reload_indf__frn"
8159 [(parallel [(set (match_operand:DF 0 "register_operand" "=a")
8160 (match_operand:DF 1 "immediate_operand" "FQ"))
8161 (use (reg:SI FPSCR_MODES_REG))
8162 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
8166 (define_expand "reload_outdf__RnFRm"
8167 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
8168 (match_operand:DF 1 "register_operand" "af,r"))
8169 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
8173 ;; Simplify no-op moves.
8175 [(set (match_operand:SF 0 "register_operand" "")
8176 (match_operand:SF 1 "register_operand" ""))
8177 (use (reg:SI FPSCR_MODES_REG))
8178 (clobber (match_scratch:SI 2))]
8179 "TARGET_SH2E && reload_completed
8180 && true_regnum (operands[0]) == true_regnum (operands[1])"
8181 [(set (match_dup 0) (match_dup 0))]
8184 ;; fmovd substitute post-reload splits
8186 [(set (match_operand:DF 0 "register_operand" "")
8187 (match_operand:DF 1 "register_operand" ""))
8188 (use (reg:SI FPSCR_MODES_REG))
8189 (clobber (match_scratch:SI 2))]
8190 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
8191 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
8192 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
8195 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
8196 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst),
8197 gen_rtx_REG (SFmode, src)));
8198 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst + 1),
8199 gen_rtx_REG (SFmode, src + 1)));
8204 [(set (match_operand:DF 0 "register_operand" "")
8205 (mem:DF (match_operand:SI 1 "register_operand" "")))
8206 (use (reg:SI FPSCR_MODES_REG))
8207 (clobber (match_scratch:SI 2))]
8208 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
8209 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
8210 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
8213 int regno = true_regnum (operands[0]);
8215 rtx mem = SET_SRC (XVECEXP (PATTERN (curr_insn), 0, 0));
8217 = change_address (mem, SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
8218 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
8219 regno + SH_REG_MSW_OFFSET),
8221 add_reg_note (insn, REG_INC, operands[1]);
8222 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
8223 regno + SH_REG_LSW_OFFSET),
8224 change_address (mem, SFmode, NULL_RTX)));
8229 [(set (match_operand:DF 0 "register_operand" "")
8230 (match_operand:DF 1 "memory_operand" ""))
8231 (use (reg:SI FPSCR_MODES_REG))
8232 (clobber (match_scratch:SI 2))]
8233 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
8234 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
8237 int regno = true_regnum (operands[0]);
8239 rtx mem2 = change_address (operands[1], SFmode, NULL_RTX);
8240 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
8241 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
8243 operands[1] = copy_rtx (mem2);
8244 addr = XEXP (mem2, 0);
8246 switch (GET_CODE (addr))
8249 /* This is complicated. If the register is an arithmetic register
8250 we can just fall through to the REG+DISP case below. Otherwise
8251 we have to use a combination of POST_INC and REG addressing... */
8252 if (! arith_reg_operand (operands[1], SFmode))
8254 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
8255 insn = emit_insn (gen_movsf_ie (reg0, mem2));
8256 add_reg_note (insn, REG_INC, XEXP (addr, 0));
8258 emit_insn (gen_movsf_ie (reg1, operands[1]));
8260 /* If we have modified the stack pointer, the value that we have
8261 read with post-increment might be modified by an interrupt,
8262 so write it back. */
8263 if (REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
8264 emit_insn (gen_push_e (reg0));
8266 emit_insn (gen_addsi3 (XEXP (operands[1], 0), XEXP (operands[1], 0),
8273 emit_insn (gen_movsf_ie (reg0, operands[1]));
8274 operands[1] = copy_rtx (operands[1]);
8275 XEXP (operands[1], 0) = plus_constant (Pmode, addr, 4);
8276 emit_insn (gen_movsf_ie (reg1, operands[1]));
8280 insn = emit_insn (gen_movsf_ie (reg0, operands[1]));
8281 add_reg_note (insn, REG_INC, XEXP (addr, 0));
8283 insn = emit_insn (gen_movsf_ie (reg1, operands[1]));
8284 add_reg_note (insn, REG_INC, XEXP (addr, 0));
8296 [(set (match_operand:DF 0 "memory_operand" "")
8297 (match_operand:DF 1 "register_operand" ""))
8298 (use (reg:SI FPSCR_MODES_REG))
8299 (clobber (match_scratch:SI 2))]
8300 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
8301 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
8304 int regno = true_regnum (operands[1]);
8306 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
8307 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
8309 operands[0] = copy_rtx (operands[0]);
8310 PUT_MODE (operands[0], SFmode);
8311 addr = XEXP (operands[0], 0);
8313 switch (GET_CODE (addr))
8316 /* This is complicated. If the register is an arithmetic register
8317 we can just fall through to the REG+DISP case below. Otherwise
8318 we have to use a combination of REG and PRE_DEC addressing... */
8319 if (! arith_reg_operand (operands[0], SFmode))
8321 emit_insn (gen_addsi3 (addr, addr, GEN_INT (4)));
8322 emit_insn (gen_movsf_ie (operands[0], reg1));
8324 operands[0] = copy_rtx (operands[0]);
8325 XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr);
8327 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
8328 add_reg_note (insn, REG_INC, XEXP (addr, 0));
8334 /* Since REG+DISP addressing has already been decided upon by gcc
8335 we can rely upon it having chosen an arithmetic register as the
8336 register component of the address. Just emit the lower numbered
8337 register first, to the lower address, then the higher numbered
8338 register to the higher address. */
8339 emit_insn (gen_movsf_ie (operands[0], reg0));
8341 operands[0] = copy_rtx (operands[0]);
8342 XEXP (operands[0], 0) = plus_constant (Pmode, addr, 4);
8344 emit_insn (gen_movsf_ie (operands[0], reg1));
8348 /* This is easy. Output the word to go to the higher address
8349 first (ie the word in the higher numbered register) then the
8350 word to go to the lower address. */
8352 insn = emit_insn (gen_movsf_ie (operands[0], reg1));
8353 add_reg_note (insn, REG_INC, XEXP (addr, 0));
8355 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
8356 add_reg_note (insn, REG_INC, XEXP (addr, 0));
8368 ;; If the output is a register and the input is memory or a register, we have
8369 ;; to be careful and see which word needs to be loaded first.
8371 [(set (match_operand:DF 0 "general_movdst_operand" "")
8372 (match_operand:DF 1 "general_movsrc_operand" ""))]
8373 "TARGET_SH1 && reload_completed"
8374 [(set (match_dup 2) (match_dup 3))
8375 (set (match_dup 4) (match_dup 5))]
8379 if ((MEM_P (operands[0])
8380 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
8381 || (MEM_P (operands[1])
8382 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
8385 switch (GET_CODE (operands[0]))
8388 regno = REGNO (operands[0]);
8391 regno = subreg_regno (operands[0]);
8400 if (regno == -1 || ! refers_to_regno_p (regno, operands[1]))
8402 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
8403 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
8404 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
8405 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
8409 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
8410 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
8411 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
8412 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
8415 if (operands[2] == 0 || operands[3] == 0
8416 || operands[4] == 0 || operands[5] == 0)
8420 (define_expand "movdf"
8421 [(set (match_operand:DF 0 "general_movdst_operand" "")
8422 (match_operand:DF 1 "general_movsrc_operand" ""))]
8425 prepare_move_operands (operands, DFmode);
8428 if (TARGET_SHMEDIA_FPU)
8429 emit_insn (gen_movdf_media (operands[0], operands[1]));
8431 emit_insn (gen_movdf_media_nofpu (operands[0], operands[1]));
8434 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
8436 emit_insn (gen_movdf_i4 (operands[0], operands[1]));
8441 ;;This is incompatible with the way gcc uses subregs.
8442 ;;(define_insn "movv2sf_i"
8443 ;; [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,m")
8444 ;; (match_operand:V2SF 1 "nonimmediate_operand" "f,m,f"))]
8445 ;; "TARGET_SHMEDIA_FPU
8446 ;; && (fp_arith_reg_operand (operands[0], V2SFmode)
8447 ;; || fp_arith_reg_operand (operands[1], V2SFmode))"
8451 ;; fst%M0.p %m0, %1"
8452 ;; [(set_attr "type" "*,fload_media,fstore_media")])
8453 (define_insn_and_split "movv2sf_i"
8454 [(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
8455 (match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
8456 "TARGET_SHMEDIA_FPU"
8458 "TARGET_SHMEDIA_FPU && reload_completed"
8459 [(set (match_dup 0) (match_dup 1))]
8461 operands[0] = simplify_gen_subreg (DFmode, operands[0], V2SFmode, 0);
8462 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2SFmode, 0);
8465 (define_expand "movv2sf"
8466 [(set (match_operand:V2SF 0 "general_movdst_operand" "")
8467 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
8468 "TARGET_SHMEDIA_FPU"
8470 prepare_move_operands (operands, V2SFmode);
8473 (define_expand "addv2sf3"
8474 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8475 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8476 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8477 "TARGET_SHMEDIA_FPU"
8479 sh_expand_binop_v2sf (PLUS, operands[0], operands[1], operands[2]);
8483 (define_expand "subv2sf3"
8484 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8485 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8486 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8487 "TARGET_SHMEDIA_FPU"
8489 sh_expand_binop_v2sf (MINUS, operands[0], operands[1], operands[2]);
8493 (define_expand "mulv2sf3"
8494 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8495 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8496 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8497 "TARGET_SHMEDIA_FPU"
8499 sh_expand_binop_v2sf (MULT, operands[0], operands[1], operands[2]);
8503 (define_expand "divv2sf3"
8504 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8505 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8506 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8507 "TARGET_SHMEDIA_FPU"
8509 sh_expand_binop_v2sf (DIV, operands[0], operands[1], operands[2]);
8513 (define_insn_and_split "*movv4sf_i"
8514 [(set (match_operand:V4SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
8515 (match_operand:V4SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
8516 "TARGET_SHMEDIA_FPU"
8518 "&& reload_completed"
8521 for (int i = 0; i < 4/2; i++)
8525 if (MEM_P (operands[0]))
8526 x = adjust_address (operands[0], V2SFmode,
8527 i * GET_MODE_SIZE (V2SFmode));
8529 x = simplify_gen_subreg (V2SFmode, operands[0], V4SFmode, i * 8);
8531 if (MEM_P (operands[1]))
8532 y = adjust_address (operands[1], V2SFmode,
8533 i * GET_MODE_SIZE (V2SFmode));
8535 y = simplify_gen_subreg (V2SFmode, operands[1], V4SFmode, i * 8);
8537 emit_insn (gen_movv2sf_i (x, y));
8542 [(set_attr "length" "8")])
8544 (define_expand "movv4sf"
8545 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
8546 (match_operand:V4SF 1 "general_operand" ""))]
8547 "TARGET_SHMEDIA_FPU"
8549 prepare_move_operands (operands, V4SFmode);
8552 (define_insn_and_split "*movv16sf_i"
8553 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
8554 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
8555 "TARGET_SHMEDIA_FPU"
8557 "&& reload_completed"
8560 for (int i = 0; i < 16/2; i++)
8564 if (MEM_P (operands[0]))
8565 x = adjust_address (operands[0], V2SFmode,
8566 i * GET_MODE_SIZE (V2SFmode));
8569 x = gen_rtx_SUBREG (V2SFmode, operands[0], i * 8);
8570 alter_subreg (&x, true);
8573 if (MEM_P (operands[1]))
8574 y = adjust_address (operands[1], V2SFmode,
8575 i * GET_MODE_SIZE (V2SFmode));
8578 y = gen_rtx_SUBREG (V2SFmode, operands[1], i * 8);
8579 alter_subreg (&y, true);
8582 emit_insn (gen_movv2sf_i (x, y));
8587 [(set_attr "length" "32")])
8589 (define_expand "movv16sf"
8590 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
8591 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
8592 "TARGET_SHMEDIA_FPU"
8594 prepare_move_operands (operands, V16SFmode);
8597 (define_insn "movsf_media"
8598 [(set (match_operand:SF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
8599 (match_operand:SF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
8601 && (register_operand (operands[0], SFmode)
8602 || sh_register_operand (operands[1], SFmode))"
8613 [(set_attr "type" "fmove_media,fload_media,fpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")
8614 (set (attr "highpart")
8615 (cond [(match_test "sh_contains_memref_p (insn)")
8616 (const_string "user")]
8617 (const_string "ignore")))])
8619 (define_insn "movsf_media_nofpu"
8620 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m")
8621 (match_operand:SF 1 "general_movsrc_operand" "r,F,m,rZ"))]
8623 && (register_operand (operands[0], SFmode)
8624 || sh_register_operand (operands[1], SFmode))"
8630 [(set_attr "type" "arith_media,*,load_media,store_media")
8631 (set (attr "highpart")
8632 (cond [(match_test "sh_contains_memref_p (insn)")
8633 (const_string "user")]
8634 (const_string "ignore")))])
8637 [(set (match_operand:SF 0 "arith_reg_dest" "")
8638 (match_operand:SF 1 "immediate_operand" ""))]
8639 "TARGET_SHMEDIA && reload_completed
8640 && ! FP_REGISTER_P (true_regnum (operands[0]))"
8641 [(set (match_dup 3) (match_dup 2))]
8644 REAL_VALUE_TYPE value;
8646 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
8647 REAL_VALUE_TO_TARGET_SINGLE (value, values);
8648 operands[2] = GEN_INT (values);
8650 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
8653 (define_insn "movsf_i"
8654 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
8655 (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
8658 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
8659 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
8660 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
8661 && (arith_reg_operand (operands[0], SFmode)
8662 || arith_reg_operand (operands[1], SFmode))"
8671 [(set_attr "type" "move,move,pcload,load,store,move,move")])
8673 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
8674 ;; update_flow_info would not know where to put REG_EQUAL notes
8675 ;; when the destination changes mode.
8676 (define_insn "movsf_ie"
8677 [(set (match_operand:SF 0 "general_movdst_operand"
8678 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,<,y,y")
8679 (match_operand:SF 1 "general_movsrc_operand"
8680 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
8681 (use (reg:SI FPSCR_MODES_REG))
8682 (clobber (match_scratch:SI 2 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
8684 && (arith_reg_operand (operands[0], SFmode) || fpul_operand (operands[0], SFmode)
8685 || arith_reg_operand (operands[1], SFmode) || fpul_operand (operands[1], SFmode)
8686 || arith_reg_operand (operands[2], SImode))"
8706 ! move optimized away"
8707 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
8708 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
8709 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
8710 (set_attr_alternative "length"
8717 (match_test "TARGET_SH2A")
8718 (const_int 4) (const_int 2))
8720 (match_test "TARGET_SH2A")
8721 (const_int 4) (const_int 2))
8724 (match_test "TARGET_SH2A")
8725 (const_int 4) (const_int 2))
8727 (match_test "TARGET_SH2A")
8728 (const_int 4) (const_int 2))
8738 (set_attr_alternative "fp_mode"
8739 [(if_then_else (eq_attr "fmovd" "yes")
8740 (const_string "single") (const_string "none"))
8741 (const_string "none")
8742 (const_string "single")
8743 (const_string "single")
8744 (const_string "none")
8745 (if_then_else (eq_attr "fmovd" "yes")
8746 (const_string "single") (const_string "none"))
8747 (if_then_else (eq_attr "fmovd" "yes")
8748 (const_string "single") (const_string "none"))
8749 (const_string "none")
8750 (const_string "none")
8751 (const_string "none")
8752 (const_string "none")
8753 (const_string "none")
8754 (const_string "none")
8755 (const_string "none")
8756 (const_string "none")
8757 (const_string "none")
8758 (const_string "none")
8759 (const_string "none")
8760 (const_string "none")])])
8762 (define_insn_and_split "movsf_ie_ra"
8763 [(set (match_operand:SF 0 "general_movdst_operand"
8764 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,<,y,y")
8765 (match_operand:SF 1 "general_movsrc_operand"
8766 "f,r,G,H,FQ,m,f,FQ,m,r,y,f,>,fr,y,r,y,>,y"))
8767 (use (reg:SI FPSCR_MODES_REG))
8768 (clobber (match_scratch:SF 2 "=r,r,X,X,&z,r,r,X,r,r,r,r,r,y,r,r,r,r,r"))
8771 && (arith_reg_operand (operands[0], SFmode)
8772 || fpul_operand (operands[0], SFmode)
8773 || arith_reg_operand (operands[1], SFmode)
8774 || fpul_operand (operands[1], SFmode))"
8794 ! move optimized away"
8796 && sh_movsf_ie_ra_split_p (operands[0], operands[1], operands[2])"
8799 if (! rtx_equal_p (operands[0], operands[1]))
8801 emit_insn (gen_movsf_ie (operands[2], operands[1]));
8802 emit_insn (gen_movsf_ie (operands[0], operands[2]));
8805 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
8806 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
8807 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
8808 (set_attr_alternative "length"
8815 (match_test "TARGET_SH2A")
8816 (const_int 4) (const_int 2))
8818 (match_test "TARGET_SH2A")
8819 (const_int 4) (const_int 2))
8822 (match_test "TARGET_SH2A")
8823 (const_int 4) (const_int 2))
8825 (match_test "TARGET_SH2A")
8826 (const_int 4) (const_int 2))
8836 (set_attr_alternative "fp_mode"
8837 [(if_then_else (eq_attr "fmovd" "yes")
8838 (const_string "single") (const_string "none"))
8839 (const_string "none")
8840 (const_string "single")
8841 (const_string "single")
8842 (const_string "none")
8843 (if_then_else (eq_attr "fmovd" "yes")
8844 (const_string "single") (const_string "none"))
8845 (if_then_else (eq_attr "fmovd" "yes")
8846 (const_string "single") (const_string "none"))
8847 (const_string "none")
8848 (const_string "none")
8849 (const_string "none")
8850 (const_string "none")
8851 (const_string "none")
8852 (const_string "none")
8853 (const_string "none")
8854 (const_string "none")
8855 (const_string "none")
8856 (const_string "none")
8857 (const_string "none")
8858 (const_string "none")])])
8861 [(set (match_operand:SF 0 "register_operand" "")
8862 (match_operand:SF 1 "register_operand" ""))
8863 (use (reg:SI FPSCR_MODES_REG))
8864 (clobber (reg:SI FPUL_REG))]
8866 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
8867 (use (reg:SI FPSCR_MODES_REG))
8868 (clobber (scratch:SI))])
8869 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
8870 (use (reg:SI FPSCR_MODES_REG))
8871 (clobber (scratch:SI))])]
8874 (define_expand "movsf"
8875 [(set (match_operand:SF 0 "general_movdst_operand" "")
8876 (match_operand:SF 1 "general_movsrc_operand" ""))]
8879 prepare_move_operands (operands, SFmode);
8882 if (TARGET_SHMEDIA_FPU)
8883 emit_insn (gen_movsf_media (operands[0], operands[1]));
8885 emit_insn (gen_movsf_media_nofpu (operands[0], operands[1]));
8890 if (lra_in_progress)
8892 if (GET_CODE (operands[0]) == SCRATCH)
8894 emit_insn (gen_movsf_ie_ra (operands[0], operands[1]));
8898 emit_insn (gen_movsf_ie (operands[0], operands[1]));
8903 (define_insn "mov_nop"
8904 [(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
8907 [(set_attr "length" "0")
8908 (set_attr "type" "nil")])
8910 (define_expand "reload_insf__frn"
8911 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
8912 (match_operand:SF 1 "immediate_operand" "FQ"))
8913 (use (reg:SI FPSCR_MODES_REG))
8914 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
8918 (define_expand "reload_insi__i_fpul"
8919 [(parallel [(set (match_operand:SI 0 "fpul_operand" "=y")
8920 (match_operand:SI 1 "immediate_operand" "i"))
8921 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
8925 (define_expand "ptabs"
8926 [(set (match_operand 0 "" "=b") (match_operand 1 "" "r"))]
8929 if (!TARGET_PT_FIXED)
8931 rtx eq = operands[1];
8933 /* ??? For canonical RTL we really should remove any CONST from EQ
8934 before wrapping it in the AND, and finally wrap the EQ into a
8935 const if is constant. However, for reload we must expose the
8936 input register or symbolic constant, and we can't have
8937 different insn structures outside of the operands for different
8938 alternatives of the same pattern. */
8939 eq = gen_rtx_EQ (SImode, gen_rtx_AND (Pmode, eq, GEN_INT (3)),
8942 = (gen_rtx_IF_THEN_ELSE
8945 gen_rtx_MEM (PDImode, operands[1]),
8946 gen_rtx_fmt_e (TARGET_SHMEDIA32 ? SIGN_EXTEND : TRUNCATE,
8947 PDImode, operands[1])));
8951 ;; expanded by ptabs expander.
8952 (define_insn "*extendsipdi_media"
8953 [(set (match_operand:PDI 0 "target_reg_operand" "=b,b");
8954 (if_then_else:PDI (eq (and:SI (match_operand:SI 1 "target_operand"
8958 (mem:PDI (match_dup 1))
8959 (sign_extend:PDI (match_dup 1))))]
8960 "TARGET_SHMEDIA && !TARGET_PT_FIXED"
8964 [(set_attr "type" "ptabs_media,pt_media")
8965 (set_attr "length" "4,*")])
8967 (define_insn "*truncdipdi_media"
8968 [(set (match_operand:PDI 0 "target_reg_operand" "=b,b");
8969 (if_then_else:PDI (eq (and:DI (match_operand:DI 1 "target_operand"
8973 (mem:PDI (match_dup 1))
8974 (truncate:PDI (match_dup 1))))]
8975 "TARGET_SHMEDIA && !TARGET_PT_FIXED"
8979 [(set_attr "type" "ptabs_media,pt_media")
8980 (set_attr "length" "4,*")])
8982 (define_insn "*movsi_y"
8983 [(set (match_operand:SI 0 "register_operand" "=y,y")
8984 (match_operand:SI 1 "immediate_operand" "Qi,I08"))
8985 (clobber (match_scratch:SI 2 "=&z,r"))]
8987 && (reload_in_progress || reload_completed)"
8989 [(set_attr "length" "4")
8990 (set_attr "type" "pcload,move")])
8993 [(set (match_operand:SI 0 "register_operand" "")
8994 (match_operand:SI 1 "immediate_operand" ""))
8995 (clobber (match_operand:SI 2 "register_operand" ""))]
8997 [(set (match_dup 2) (match_dup 1))
8998 (set (match_dup 0) (match_dup 2))]
9001 ;; ------------------------------------------------------------------------
9002 ;; Define the real conditional branch instructions.
9003 ;; ------------------------------------------------------------------------
9005 (define_expand "branch_true"
9006 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
9007 (label_ref (match_operand 0))
9011 (define_expand "branch_false"
9012 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
9013 (label_ref (match_operand 0))
9017 (define_insn_and_split "*cbranch_t"
9018 [(set (pc) (if_then_else (match_operand 1 "cbranch_treg_value")
9019 (label_ref (match_operand 0))
9023 return output_branch (sh_eval_treg_value (operands[1]), insn, operands);
9028 /* Try to canonicalize the branch condition if it is not one of:
9029 (ne (reg:SI T_REG) (const_int 0))
9030 (eq (reg:SI T_REG) (const_int 0))
9032 Instead of splitting out a new insn, we modify the current insn's
9033 operands as needed. This preserves things such as REG_DEAD notes. */
9035 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
9036 && REG_P (XEXP (operands[1], 0)) && REGNO (XEXP (operands[1], 0)) == T_REG
9037 && XEXP (operands[1], 1) == const0_rtx)
9040 int branch_cond = sh_eval_treg_value (operands[1]);
9041 rtx new_cond_rtx = NULL_RTX;
9043 if (branch_cond == 0)
9044 new_cond_rtx = gen_rtx_EQ (VOIDmode, get_t_reg_rtx (), const0_rtx);
9045 else if (branch_cond == 1)
9046 new_cond_rtx = gen_rtx_NE (VOIDmode, get_t_reg_rtx (), const0_rtx);
9048 if (new_cond_rtx != NULL_RTX)
9049 validate_change (curr_insn, &XEXP (XEXP (PATTERN (curr_insn), 1), 0),
9050 new_cond_rtx, false);
9053 [(set_attr "type" "cbranch")])
9055 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
9056 ;; which destination is too far away.
9057 ;; The const_int_operand is distinct for each branch target; it avoids
9058 ;; unwanted matches with redundant_insn.
9059 (define_insn "block_branch_redirect"
9060 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
9063 [(set_attr "length" "0")])
9065 ;; This one has the additional purpose to record a possible scratch register
9066 ;; for the following branch.
9067 ;; ??? Unfortunately, just setting the scratch register is not good enough,
9068 ;; because the insn then might be deemed dead and deleted. And we can't
9069 ;; make the use in the jump insn explicit because that would disable
9070 ;; delay slot scheduling from the target.
9071 (define_insn "indirect_jump_scratch"
9072 [(set (match_operand:SI 0 "register_operand" "=r")
9073 (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
9074 (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
9077 [(set_attr "length" "0")])
9079 ;; This one is used to preemt an insn from beyond the bra / braf / jmp
9080 ;; being pulled into the delay slot of a condbranch that has been made to
9081 ;; jump around the unconditional jump because it was out of range.
9082 (define_insn "stuff_delay_slot"
9084 (unspec [(match_operand:SI 0 "const_int_operand" "") (pc)
9085 (match_operand:SI 1 "const_int_operand" "")] UNSPEC_BBR))]
9088 [(set_attr "length" "0")
9089 (set_attr "cond_delay_slot" "yes")])
9091 ;; Conditional branch insns
9093 (define_expand "cbranchint4_media"
9095 (if_then_else (match_operator 0 "shmedia_cbranch_comparison_operator"
9096 [(match_operand 1 "" "")
9097 (match_operand 2 "" "")])
9098 (match_operand 3 "" "")
9102 machine_mode mode = GET_MODE (operands[1]);
9103 if (mode == VOIDmode)
9104 mode = GET_MODE (operands[2]);
9105 if (GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
9107 operands[1] = force_reg (mode, operands[1]);
9108 if (CONSTANT_P (operands[2])
9109 && (! satisfies_constraint_I06 (operands[2])))
9110 operands[2] = force_reg (mode, operands[2]);
9114 if (operands[1] != const0_rtx)
9115 operands[1] = force_reg (mode, operands[1]);
9116 if (operands[2] != const0_rtx)
9117 operands[2] = force_reg (mode, operands[2]);
9119 switch (GET_CODE (operands[0]))
9125 operands[0] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[0])),
9126 VOIDmode, operands[2], operands[1]);
9127 operands[1] = XEXP (operands[0], 0);
9128 operands[2] = XEXP (operands[0], 1);
9131 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
9132 VOIDmode, operands[1], operands[2]);
9135 operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]);
9138 (define_expand "cbranchfp4_media"
9140 (if_then_else (match_operator 0 "sh_float_comparison_operator"
9141 [(match_operand 1 "" "")
9142 (match_operand 2 "" "")])
9143 (match_operand 3 "" "")
9147 rtx tmp = gen_reg_rtx (SImode);
9149 if (GET_CODE (operands[0]) == NE)
9150 cmp = gen_rtx_EQ (SImode, operands[1], operands[2]);
9152 cmp = gen_rtx_fmt_ee (GET_CODE (operands[0]), SImode,
9153 operands[1], operands[2]);
9155 emit_insn (gen_cstore4_media (tmp, cmp, operands[1], operands[2]));
9157 if (GET_CODE (cmp) == GET_CODE (operands[0]))
9158 operands[0] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
9160 operands[0] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
9162 operands[2] = const0_rtx;
9163 operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]);
9166 (define_insn "*beq_media_i"
9168 (if_then_else (match_operator 3 "equality_comparison_operator"
9169 [(match_operand:DI 1 "arith_reg_operand" "r,r")
9170 (match_operand:DI 2 "arith_operand" "r,I06")])
9171 (match_operand 0 "target_operand" "b,b")
9176 b%o3i%' %1, %2, %0%>"
9177 [(set_attr "type" "cbranch_media")])
9179 (define_insn "*beq_media_i32"
9181 (if_then_else (match_operator 3 "equality_comparison_operator"
9182 [(match_operand:SI 1 "arith_reg_operand" "r,r")
9183 (match_operand:SI 2 "arith_operand" "r,I06")])
9184 (match_operand 0 "target_operand" "b,b")
9189 b%o3i%' %1, %2, %0%>"
9190 [(set_attr "type" "cbranch_media")])
9192 (define_insn "*bgt_media_i"
9194 (if_then_else (match_operator 3 "greater_comparison_operator"
9195 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
9196 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
9197 (match_operand 0 "target_operand" "b")
9200 "b%o3%' %N1, %N2, %0%>"
9201 [(set_attr "type" "cbranch_media")])
9203 (define_insn "*bgt_media_i32"
9205 (if_then_else (match_operator 3 "greater_comparison_operator"
9206 [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
9207 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")])
9208 (match_operand 0 "target_operand" "b")
9211 "b%o3%' %N1, %N2, %0%>"
9212 [(set_attr "type" "cbranch_media")])
9214 ;; These are only needed to make invert_jump() happy - otherwise, jump
9215 ;; optimization will be silently disabled.
9216 (define_insn "*blt_media_i"
9218 (if_then_else (match_operator 3 "less_comparison_operator"
9219 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
9220 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
9221 (match_operand 0 "target_operand" "b")
9224 "b%o3%' %N2, %N1, %0%>"
9225 [(set_attr "type" "cbranch_media")])
9227 (define_insn "*blt_media_i32"
9229 (if_then_else (match_operator 3 "less_comparison_operator"
9230 [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
9231 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")])
9232 (match_operand 0 "target_operand" "b")
9235 "b%o3%' %N2, %N1, %0%>"
9236 [(set_attr "type" "cbranch_media")])
9238 ;; combiner splitter for test-and-branch on single bit in register. This
9239 ;; is endian dependent because the non-paradoxical subreg looks different
9244 (match_operator 3 "equality_comparison_operator"
9247 (subreg:DI (match_operand:SI 1 "extend_reg_operand" "") 0)
9249 (match_operand 2 "const_int_operand" "")) 0)
9251 (match_operand 0 "target_operand" "")
9253 (clobber (match_operand:SI 4 "arith_reg_dest" ""))]
9254 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
9255 [(set (match_dup 4) (ashift:SI (match_dup 1) (match_dup 5)))
9256 (set (pc) (if_then_else (match_dup 6) (match_dup 0) (pc)))]
9258 operands[5] = GEN_INT (31 - INTVAL (operands[2]));
9259 operands[6] = (GET_CODE (operands[3]) == EQ
9260 ? gen_rtx_GE (VOIDmode, operands[4], const0_rtx)
9261 : gen_rtx_GT (VOIDmode, const0_rtx, operands[4]));
9264 ; operand 0 is the loop count pseudo register
9265 ; operand 1 is the label to jump to at the top of the loop
9266 (define_expand "doloop_end"
9267 [(parallel [(set (pc)
9268 (if_then_else (ne:SI (match_operand:SI 0 "" "")
9270 (label_ref (match_operand 1 "" ""))
9273 (plus:SI (match_dup 0) (const_int -1)))
9274 (clobber (reg:SI T_REG))])]
9277 if (GET_MODE (operands[0]) != SImode)
9279 emit_jump_insn (gen_doloop_end_split (operands[0], operands[1], operands[0]));
9283 (define_insn_and_split "doloop_end_split"
9285 (if_then_else (ne:SI (match_operand:SI 2 "arith_reg_dest" "0")
9287 (label_ref (match_operand 1 "" ""))
9289 (set (match_operand:SI 0 "arith_reg_dest" "=r")
9290 (plus:SI (match_dup 2) (const_int -1)))
9291 (clobber (reg:SI T_REG))]
9295 [(parallel [(set (reg:SI T_REG)
9296 (eq:SI (match_dup 2) (const_int 1)))
9297 (set (match_dup 0) (plus:SI (match_dup 2) (const_int -1)))])
9298 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
9299 (label_ref (match_dup 1))
9302 [(set_attr "type" "cbranch")])
9304 ;; ------------------------------------------------------------------------
9305 ;; Jump and linkage insns
9306 ;; ------------------------------------------------------------------------
9308 (define_insn "jump_compact"
9310 (label_ref (match_operand 0 "" "")))]
9311 "TARGET_SH1 && !CROSSING_JUMP_P (insn)"
9313 /* The length is 16 if the delay slot is unfilled. */
9314 if (get_attr_length(insn) > 4)
9315 return output_far_jump(insn, operands[0]);
9319 [(set_attr "type" "jump")
9320 (set_attr "needs_delay_slot" "yes")])
9322 (define_insn "*jump_compact_crossing"
9324 (label_ref (match_operand 0 "" "")))]
9326 && flag_reorder_blocks_and_partition
9327 && CROSSING_JUMP_P (insn)"
9329 /* The length is 16 if the delay slot is unfilled. */
9330 return output_far_jump(insn, operands[0]);
9332 [(set_attr "type" "jump")
9333 (set_attr "length" "16")])
9335 ;; ??? It would be much saner to explicitly use the scratch register
9336 ;; in the jump insn, and have indirect_jump_scratch only set it,
9337 ;; but fill_simple_delay_slots would refuse to do delay slot filling
9338 ;; from the target then, as it uses simplejump_p.
9339 ;;(define_insn "jump_compact_far"
9341 ;; (label_ref (match_operand 0 "" "")))
9342 ;; (use (match_operand 1 "register_operand" "r")]
9344 ;; "* return output_far_jump(insn, operands[0], operands[1]);"
9345 ;; [(set_attr "type" "jump")
9346 ;; (set_attr "needs_delay_slot" "yes")])
9348 (define_insn "jump_media"
9350 (match_operand 0 "target_operand" "b"))]
9353 [(set_attr "type" "jump_media")])
9355 (define_expand "jump"
9357 (label_ref (match_operand 0 "" "")))]
9361 emit_jump_insn (gen_jump_compact (operands[0]));
9362 else if (TARGET_SHMEDIA)
9364 if (reload_in_progress || reload_completed)
9366 emit_jump_insn (gen_jump_media (gen_rtx_LABEL_REF (Pmode, operands[0])));
9371 (define_insn "force_mode_for_call"
9372 [(use (reg:SI FPSCR_MODES_REG))]
9375 [(set_attr "length" "0")
9376 (set (attr "fp_mode")
9377 (if_then_else (eq_attr "fpu_single" "yes")
9378 (const_string "single") (const_string "double")))])
9380 (define_insn "calli"
9381 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9382 (match_operand 1 "" ""))
9383 (use (reg:SI FPSCR_MODES_REG))
9384 (clobber (reg:SI PR_REG))]
9387 if (TARGET_SH2A && (dbr_sequence_length () == 0))
9392 [(set_attr "type" "call")
9393 (set (attr "fp_mode")
9394 (if_then_else (eq_attr "fpu_single" "yes")
9395 (const_string "single") (const_string "double")))
9396 (set_attr "needs_delay_slot" "yes")
9397 (set_attr "fp_set" "unknown")])
9399 ;; This is TBR relative jump instruction for SH2A architecture.
9400 ;; Its use is enabled by assigning an attribute "function_vector"
9401 ;; and the vector number to a function during its declaration.
9402 (define_insn "calli_tbr_rel"
9403 [(call (mem (match_operand:SI 0 "symbol_ref_operand" ""))
9404 (match_operand 1 "" ""))
9405 (use (reg:SI FPSCR_MODES_REG))
9406 (clobber (reg:SI PR_REG))]
9407 "TARGET_SH2A && sh2a_is_function_vector_call (operands[0])"
9409 unsigned HOST_WIDE_INT vect_num;
9410 vect_num = sh2a_get_function_vector_number (operands[0]);
9411 operands[2] = GEN_INT (vect_num * 4);
9413 return "jsr/n @@(%O2,tbr)";
9415 [(set_attr "type" "call")
9416 (set (attr "fp_mode")
9417 (if_then_else (eq_attr "fpu_single" "yes")
9418 (const_string "single") (const_string "double")))
9419 (set_attr "needs_delay_slot" "no")
9420 (set_attr "fp_set" "unknown")])
9422 ;; This is a pc-rel call, using bsrf, for use with PIC.
9423 (define_insn "calli_pcrel"
9424 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9425 (match_operand 1 "" ""))
9426 (use (reg:SI FPSCR_MODES_REG))
9427 (use (reg:SI PIC_REG))
9428 (use (match_operand 2 "" ""))
9429 (clobber (reg:SI PR_REG))]
9432 return "bsrf %0" "\n"
9435 [(set_attr "type" "call")
9436 (set (attr "fp_mode")
9437 (if_then_else (eq_attr "fpu_single" "yes")
9438 (const_string "single") (const_string "double")))
9439 (set_attr "needs_delay_slot" "yes")
9440 (set_attr "fp_set" "unknown")])
9442 (define_insn_and_split "call_pcrel"
9443 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
9444 (match_operand 1 "" ""))
9445 (use (reg:SI FPSCR_MODES_REG))
9446 (use (reg:SI PIC_REG))
9447 (clobber (reg:SI PR_REG))
9448 (clobber (match_scratch:SI 2 "=r"))]
9454 rtx lab = PATTERN (gen_call_site ());
9456 if (SYMBOL_REF_LOCAL_P (operands[0]))
9457 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
9459 emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
9460 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab)));
9463 [(set_attr "type" "call")
9464 (set (attr "fp_mode")
9465 (if_then_else (eq_attr "fpu_single" "yes")
9466 (const_string "single") (const_string "double")))
9467 (set_attr "needs_delay_slot" "yes")
9468 (set_attr "fp_set" "unknown")])
9470 (define_insn "call_compact"
9471 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9472 (match_operand 1 "" ""))
9473 (match_operand 2 "immediate_operand" "n")
9474 (use (reg:SI R0_REG))
9475 (use (reg:SI R1_REG))
9476 (use (reg:SI FPSCR_MODES_REG))
9477 (clobber (reg:SI PR_REG))]
9478 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9480 [(set_attr "type" "call")
9481 (set (attr "fp_mode")
9482 (if_then_else (eq_attr "fpu_single" "yes")
9483 (const_string "single") (const_string "double")))
9484 (set_attr "needs_delay_slot" "yes")])
9486 (define_insn "call_compact_rettramp"
9487 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9488 (match_operand 1 "" ""))
9489 (match_operand 2 "immediate_operand" "n")
9490 (use (reg:SI R0_REG))
9491 (use (reg:SI R1_REG))
9492 (use (reg:SI FPSCR_MODES_REG))
9493 (clobber (reg:SI R10_REG))
9494 (clobber (reg:SI PR_REG))]
9495 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9497 [(set_attr "type" "call")
9498 (set (attr "fp_mode")
9499 (if_then_else (eq_attr "fpu_single" "yes")
9500 (const_string "single") (const_string "double")))
9501 (set_attr "needs_delay_slot" "yes")])
9503 (define_insn "call_media"
9504 [(call (mem:DI (match_operand 0 "target_reg_operand" "b"))
9505 (match_operand 1 "" ""))
9506 (clobber (reg:DI PR_MEDIA_REG))]
9509 [(set_attr "type" "jump_media")])
9511 (define_insn "call_valuei"
9512 [(set (match_operand 0 "" "=rf")
9513 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9514 (match_operand 2 "" "")))
9515 (use (reg:SI FPSCR_MODES_REG))
9516 (clobber (reg:SI PR_REG))]
9519 if (TARGET_SH2A && (dbr_sequence_length () == 0))
9524 [(set_attr "type" "call")
9525 (set (attr "fp_mode")
9526 (if_then_else (eq_attr "fpu_single" "yes")
9527 (const_string "single") (const_string "double")))
9528 (set_attr "needs_delay_slot" "yes")
9529 (set_attr "fp_set" "unknown")])
9531 ;; This is TBR relative jump instruction for SH2A architecture.
9532 ;; Its use is enabled by assigning an attribute "function_vector"
9533 ;; and the vector number to a function during its declaration.
9534 (define_insn "call_valuei_tbr_rel"
9535 [(set (match_operand 0 "" "=rf")
9536 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9537 (match_operand 2 "" "")))
9538 (use (reg:SI FPSCR_MODES_REG))
9539 (clobber (reg:SI PR_REG))]
9540 "TARGET_SH2A && sh2a_is_function_vector_call (operands[1])"
9542 unsigned HOST_WIDE_INT vect_num;
9543 vect_num = sh2a_get_function_vector_number (operands[1]);
9544 operands[3] = GEN_INT (vect_num * 4);
9546 return "jsr/n @@(%O3,tbr)";
9548 [(set_attr "type" "call")
9549 (set (attr "fp_mode")
9550 (if_then_else (eq_attr "fpu_single" "yes")
9551 (const_string "single") (const_string "double")))
9552 (set_attr "needs_delay_slot" "no")
9553 (set_attr "fp_set" "unknown")])
9555 (define_insn "call_valuei_pcrel"
9556 [(set (match_operand 0 "" "=rf")
9557 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9558 (match_operand 2 "" "")))
9559 (use (reg:SI FPSCR_MODES_REG))
9560 (use (reg:SI PIC_REG))
9561 (use (match_operand 3 "" ""))
9562 (clobber (reg:SI PR_REG))]
9565 return "bsrf %1" "\n"
9568 [(set_attr "type" "call")
9569 (set (attr "fp_mode")
9570 (if_then_else (eq_attr "fpu_single" "yes")
9571 (const_string "single") (const_string "double")))
9572 (set_attr "needs_delay_slot" "yes")
9573 (set_attr "fp_set" "unknown")])
9575 (define_insn_and_split "call_value_pcrel"
9576 [(set (match_operand 0 "" "=rf")
9577 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9578 (match_operand 2 "" "")))
9579 (use (reg:SI FPSCR_MODES_REG))
9580 (use (reg:SI PIC_REG))
9581 (clobber (reg:SI PR_REG))
9582 (clobber (match_scratch:SI 3 "=r"))]
9588 rtx lab = PATTERN (gen_call_site ());
9590 if (SYMBOL_REF_LOCAL_P (operands[1]))
9591 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
9593 emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
9594 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
9595 operands[2], copy_rtx (lab)));
9598 [(set_attr "type" "call")
9599 (set (attr "fp_mode")
9600 (if_then_else (eq_attr "fpu_single" "yes")
9601 (const_string "single") (const_string "double")))
9602 (set_attr "needs_delay_slot" "yes")
9603 (set_attr "fp_set" "unknown")])
9605 (define_insn "call_value_compact"
9606 [(set (match_operand 0 "" "=rf")
9607 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9608 (match_operand 2 "" "")))
9609 (match_operand 3 "immediate_operand" "n")
9610 (use (reg:SI R0_REG))
9611 (use (reg:SI R1_REG))
9612 (use (reg:SI FPSCR_MODES_REG))
9613 (clobber (reg:SI PR_REG))]
9614 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9616 [(set_attr "type" "call")
9617 (set (attr "fp_mode")
9618 (if_then_else (eq_attr "fpu_single" "yes")
9619 (const_string "single") (const_string "double")))
9620 (set_attr "needs_delay_slot" "yes")])
9622 (define_insn "call_value_compact_rettramp"
9623 [(set (match_operand 0 "" "=rf")
9624 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9625 (match_operand 2 "" "")))
9626 (match_operand 3 "immediate_operand" "n")
9627 (use (reg:SI R0_REG))
9628 (use (reg:SI R1_REG))
9629 (use (reg:SI FPSCR_MODES_REG))
9630 (clobber (reg:SI R10_REG))
9631 (clobber (reg:SI PR_REG))]
9632 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9634 [(set_attr "type" "call")
9635 (set (attr "fp_mode")
9636 (if_then_else (eq_attr "fpu_single" "yes")
9637 (const_string "single") (const_string "double")))
9638 (set_attr "needs_delay_slot" "yes")])
9640 (define_insn "call_value_media"
9641 [(set (match_operand 0 "" "=rf")
9642 (call (mem:DI (match_operand 1 "target_reg_operand" "b"))
9643 (match_operand 2 "" "")))
9644 (clobber (reg:DI PR_MEDIA_REG))]
9647 [(set_attr "type" "jump_media")])
9649 (define_expand "call"
9650 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9651 (match_operand 1 "" ""))
9652 (match_operand 2 "" "")
9653 (use (reg:SI FPSCR_MODES_REG))
9654 (clobber (reg:SI PR_REG))])]
9659 operands[0] = shmedia_prepare_call_address (operands[0], 0);
9660 emit_call_insn (gen_call_media (operands[0], operands[1]));
9663 else if (TARGET_SHCOMPACT && operands[2] && INTVAL (operands[2]))
9665 rtx cookie_rtx = operands[2];
9666 long cookie = INTVAL (cookie_rtx);
9667 rtx func = XEXP (operands[0], 0);
9672 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9674 rtx reg = gen_reg_rtx (Pmode);
9676 emit_insn (gen_symGOTPLT2reg (reg, func));
9680 func = legitimize_pic_address (func, Pmode, 0);
9683 r0 = gen_rtx_REG (SImode, R0_REG);
9684 r1 = gen_rtx_REG (SImode, R1_REG);
9686 /* Since such a call function may use all call-clobbered
9687 registers, we force a mode switch earlier, so that we don't
9688 run out of registers when adjusting fpscr for the call. */
9689 emit_insn (gen_force_mode_for_call ());
9692 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9693 operands[0] = force_reg (SImode, operands[0]);
9695 emit_move_insn (r0, func);
9696 emit_move_insn (r1, cookie_rtx);
9698 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9699 emit_call_insn (gen_call_compact_rettramp (operands[0], operands[1],
9702 emit_call_insn (gen_call_compact (operands[0], operands[1],
9707 else if (TARGET_SHCOMPACT && flag_pic
9708 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9709 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9711 rtx reg = gen_reg_rtx (Pmode);
9713 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[0], 0)));
9714 XEXP (operands[0], 0) = reg;
9716 if (!flag_pic && TARGET_SH2A
9717 && MEM_P (operands[0])
9718 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
9720 if (sh2a_is_function_vector_call (XEXP (operands[0], 0)))
9722 emit_call_insn (gen_calli_tbr_rel (XEXP (operands[0], 0),
9727 if (flag_pic && TARGET_SH2
9728 && MEM_P (operands[0])
9729 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
9731 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
9736 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
9737 operands[1] = operands[2];
9740 emit_call_insn (gen_calli (operands[0], operands[1]));
9744 (define_insn "call_pop_compact"
9745 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9746 (match_operand 1 "" ""))
9747 (match_operand 2 "immediate_operand" "n")
9748 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9749 (match_operand 3 "immediate_operand" "n")))
9750 (use (reg:SI R0_REG))
9751 (use (reg:SI R1_REG))
9752 (use (reg:SI FPSCR_MODES_REG))
9753 (clobber (reg:SI PR_REG))]
9754 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9756 [(set_attr "type" "call")
9757 (set (attr "fp_mode")
9758 (if_then_else (eq_attr "fpu_single" "yes")
9759 (const_string "single") (const_string "double")))
9760 (set_attr "needs_delay_slot" "yes")])
9762 (define_insn "call_pop_compact_rettramp"
9763 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9764 (match_operand 1 "" ""))
9765 (match_operand 2 "immediate_operand" "n")
9766 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9767 (match_operand 3 "immediate_operand" "n")))
9768 (use (reg:SI R0_REG))
9769 (use (reg:SI R1_REG))
9770 (use (reg:SI FPSCR_MODES_REG))
9771 (clobber (reg:SI R10_REG))
9772 (clobber (reg:SI PR_REG))]
9773 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9775 [(set_attr "type" "call")
9776 (set (attr "fp_mode")
9777 (if_then_else (eq_attr "fpu_single" "yes")
9778 (const_string "single") (const_string "double")))
9779 (set_attr "needs_delay_slot" "yes")])
9781 (define_expand "call_pop"
9782 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9783 (match_operand 1 "" ""))
9784 (match_operand 2 "" "")
9785 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9786 (match_operand 3 "" "")))])]
9794 gcc_assert (operands[2] && INTVAL (operands[2]));
9795 cookie_rtx = operands[2];
9796 cookie = INTVAL (cookie_rtx);
9797 func = XEXP (operands[0], 0);
9801 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9803 rtx reg = gen_reg_rtx (Pmode);
9804 emit_insn (gen_symGOTPLT2reg (reg, func));
9808 func = legitimize_pic_address (func, Pmode, 0);
9811 r0 = gen_rtx_REG (SImode, R0_REG);
9812 r1 = gen_rtx_REG (SImode, R1_REG);
9814 /* Since such a call function may use all call-clobbered
9815 registers, we force a mode switch earlier, so that we don't
9816 run out of registers when adjusting fpscr for the call. */
9817 emit_insn (gen_force_mode_for_call ());
9819 operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
9821 operands[0] = force_reg (SImode, operands[0]);
9823 emit_move_insn (r0, func);
9824 emit_move_insn (r1, cookie_rtx);
9826 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9827 emit_call_insn (gen_call_pop_compact_rettramp
9828 (operands[0], operands[1], operands[2], operands[3]));
9830 emit_call_insn (gen_call_pop_compact
9831 (operands[0], operands[1], operands[2], operands[3]));
9836 (define_expand "call_value"
9837 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
9838 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
9839 (match_operand 2 "" "")))
9840 (match_operand 3 "" "")
9841 (use (reg:SI FPSCR_MODES_REG))
9842 (clobber (reg:SI PR_REG))])]
9847 operands[1] = shmedia_prepare_call_address (operands[1], 0);
9848 emit_call_insn (gen_call_value_media (operands[0], operands[1],
9852 else if (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]))
9854 rtx cookie_rtx = operands[3];
9855 long cookie = INTVAL (cookie_rtx);
9856 rtx func = XEXP (operands[1], 0);
9861 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9863 rtx reg = gen_reg_rtx (Pmode);
9865 emit_insn (gen_symGOTPLT2reg (reg, func));
9869 func = legitimize_pic_address (func, Pmode, 0);
9872 r0 = gen_rtx_REG (SImode, R0_REG);
9873 r1 = gen_rtx_REG (SImode, R1_REG);
9875 /* Since such a call function may use all call-clobbered
9876 registers, we force a mode switch earlier, so that we don't
9877 run out of registers when adjusting fpscr for the call. */
9878 emit_insn (gen_force_mode_for_call ());
9881 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9882 operands[1] = force_reg (SImode, operands[1]);
9884 emit_move_insn (r0, func);
9885 emit_move_insn (r1, cookie_rtx);
9887 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9888 emit_call_insn (gen_call_value_compact_rettramp (operands[0],
9893 emit_call_insn (gen_call_value_compact (operands[0], operands[1],
9894 operands[2], operands[3]));
9898 else if (TARGET_SHCOMPACT && flag_pic
9899 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9900 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9902 rtx reg = gen_reg_rtx (Pmode);
9904 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[1], 0)));
9905 XEXP (operands[1], 0) = reg;
9907 if (!flag_pic && TARGET_SH2A
9908 && MEM_P (operands[1])
9909 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
9911 if (sh2a_is_function_vector_call (XEXP (operands[1], 0)))
9913 emit_call_insn (gen_call_valuei_tbr_rel (operands[0],
9914 XEXP (operands[1], 0), operands[2]));
9918 if (flag_pic && TARGET_SH2
9919 && MEM_P (operands[1])
9920 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
9922 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
9927 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
9929 emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
9933 (define_insn "sibcalli"
9934 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
9935 (match_operand 1 "" ""))
9936 (use (reg:SI FPSCR_MODES_REG))
9940 [(set_attr "needs_delay_slot" "yes")
9941 (set (attr "fp_mode")
9942 (if_then_else (eq_attr "fpu_single" "yes")
9943 (const_string "single") (const_string "double")))
9944 (set_attr "type" "jump_ind")])
9946 (define_insn "sibcalli_pcrel"
9947 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
9948 (match_operand 1 "" ""))
9949 (use (match_operand 2 "" ""))
9950 (use (reg:SI FPSCR_MODES_REG))
9954 return "braf %0" "\n"
9957 [(set_attr "needs_delay_slot" "yes")
9958 (set (attr "fp_mode")
9959 (if_then_else (eq_attr "fpu_single" "yes")
9960 (const_string "single") (const_string "double")))
9961 (set_attr "type" "jump_ind")])
9963 ;; This uses an unspec to describe that the symbol_ref is very close.
9964 (define_insn "sibcalli_thunk"
9965 [(call (mem:SI (unspec:SI [(match_operand:SI 0 "symbol_ref_operand" "")]
9967 (match_operand 1 "" ""))
9968 (use (reg:SI FPSCR_MODES_REG))
9972 [(set_attr "needs_delay_slot" "yes")
9973 (set (attr "fp_mode")
9974 (if_then_else (eq_attr "fpu_single" "yes")
9975 (const_string "single") (const_string "double")))
9976 (set_attr "type" "jump")
9977 (set_attr "length" "2")])
9979 (define_insn_and_split "sibcall_pcrel"
9980 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
9981 (match_operand 1 "" ""))
9982 (use (reg:SI FPSCR_MODES_REG))
9983 (clobber (match_scratch:SI 2 "=k"))
9990 rtx lab = PATTERN (gen_call_site ());
9993 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
9994 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
9996 SIBLING_CALL_P (call_insn) = 1;
9999 [(set_attr "needs_delay_slot" "yes")
10000 (set (attr "fp_mode")
10001 (if_then_else (eq_attr "fpu_single" "yes")
10002 (const_string "single") (const_string "double")))
10003 (set_attr "type" "jump_ind")])
10005 (define_insn "sibcall_compact"
10006 [(call (mem:SI (match_operand:SI 0 "register_operand" "k,k"))
10007 (match_operand 1 "" ""))
10009 (use (match_operand:SI 2 "register_operand" "z,x"))
10010 (use (reg:SI R1_REG))
10011 (use (reg:SI FPSCR_MODES_REG))
10012 ;; We want to make sure the `x' above will only match MACH_REG
10013 ;; because sibcall_epilogue may clobber MACL_REG.
10014 (clobber (reg:SI MACL_REG))]
10017 static const char* alt[] =
10024 return alt[which_alternative];
10026 [(set_attr "needs_delay_slot" "yes,no")
10027 (set_attr "length" "2,4")
10028 (set (attr "fp_mode") (const_string "single"))
10029 (set_attr "type" "jump_ind")])
10031 (define_insn "sibcall_media"
10032 [(call (mem:DI (match_operand 0 "target_reg_operand" "k"))
10033 (match_operand 1 "" ""))
10034 (use (reg:SI PR_MEDIA_REG))
10038 [(set_attr "type" "jump_media")])
10040 (define_expand "sibcall"
10042 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
10043 (match_operand 1 "" ""))
10044 (match_operand 2 "" "")
10045 (use (reg:SI FPSCR_MODES_REG))
10049 if (TARGET_SHMEDIA)
10051 operands[0] = shmedia_prepare_call_address (operands[0], 1);
10052 emit_call_insn (gen_sibcall_media (operands[0], operands[1]));
10055 else if (TARGET_SHCOMPACT && operands[2]
10056 && (INTVAL (operands[2]) & ~ CALL_COOKIE_RET_TRAMP (1)))
10058 rtx cookie_rtx = operands[2];
10059 long cookie = INTVAL (cookie_rtx);
10060 rtx func = XEXP (operands[0], 0);
10065 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
10067 rtx reg = gen_reg_rtx (Pmode);
10069 emit_insn (gen_symGOT2reg (reg, func));
10073 func = legitimize_pic_address (func, Pmode, 0);
10076 /* FIXME: if we could tell whether all argument registers are
10077 already taken, we could decide whether to force the use of
10078 MACH_REG or to stick to R0_REG. Unfortunately, there's no
10079 simple way to tell. We could use the CALL_COOKIE, but we
10080 can't currently tell a register used for regular argument
10081 passing from one that is unused. If we leave it up to reload
10082 to decide which register to use, it seems to always choose
10083 R0_REG, which leaves no available registers in SIBCALL_REGS
10084 to hold the address of the trampoline. */
10085 mach = gen_rtx_REG (SImode, MACH_REG);
10086 r1 = gen_rtx_REG (SImode, R1_REG);
10088 /* Since such a call function may use all call-clobbered
10089 registers, we force a mode switch earlier, so that we don't
10090 run out of registers when adjusting fpscr for the call. */
10091 emit_insn (gen_force_mode_for_call ());
10094 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
10095 operands[0] = force_reg (SImode, operands[0]);
10097 /* We don't need a return trampoline, since the callee will
10098 return directly to the upper caller. */
10099 if (cookie & CALL_COOKIE_RET_TRAMP (1))
10101 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
10102 cookie_rtx = GEN_INT (cookie);
10105 emit_move_insn (mach, func);
10106 emit_move_insn (r1, cookie_rtx);
10108 emit_call_insn (gen_sibcall_compact (operands[0], operands[1], mach));
10111 else if (TARGET_SHCOMPACT && flag_pic
10112 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
10113 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
10115 rtx reg = gen_reg_rtx (Pmode);
10117 emit_insn (gen_symGOT2reg (reg, XEXP (operands[0], 0)));
10118 XEXP (operands[0], 0) = reg;
10120 if (flag_pic && TARGET_SH2
10121 && MEM_P (operands[0])
10122 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
10123 /* The PLT needs the PIC register, but the epilogue would have
10124 to restore it, so we can only use PC-relative PIC calls for
10125 static functions. */
10126 && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
10128 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
10132 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
10134 emit_call_insn (gen_sibcalli (operands[0], operands[1]));
10138 (define_insn "sibcall_valuei"
10139 [(set (match_operand 0 "" "=rf")
10140 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
10141 (match_operand 2 "" "")))
10142 (use (reg:SI FPSCR_MODES_REG))
10146 [(set_attr "needs_delay_slot" "yes")
10147 (set (attr "fp_mode")
10148 (if_then_else (eq_attr "fpu_single" "yes")
10149 (const_string "single") (const_string "double")))
10150 (set_attr "type" "jump_ind")])
10152 (define_insn "sibcall_valuei_pcrel"
10153 [(set (match_operand 0 "" "=rf")
10154 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
10155 (match_operand 2 "" "")))
10156 (use (match_operand 3 "" ""))
10157 (use (reg:SI FPSCR_MODES_REG))
10161 return "braf %1" "\n"
10164 [(set_attr "needs_delay_slot" "yes")
10165 (set (attr "fp_mode")
10166 (if_then_else (eq_attr "fpu_single" "yes")
10167 (const_string "single") (const_string "double")))
10168 (set_attr "type" "jump_ind")])
10170 (define_insn_and_split "sibcall_value_pcrel"
10171 [(set (match_operand 0 "" "=rf")
10172 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
10173 (match_operand 2 "" "")))
10174 (use (reg:SI FPSCR_MODES_REG))
10175 (clobber (match_scratch:SI 3 "=k"))
10182 rtx lab = PATTERN (gen_call_site ());
10185 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
10186 call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
10190 SIBLING_CALL_P (call_insn) = 1;
10193 [(set_attr "needs_delay_slot" "yes")
10194 (set (attr "fp_mode")
10195 (if_then_else (eq_attr "fpu_single" "yes")
10196 (const_string "single") (const_string "double")))
10197 (set_attr "type" "jump_ind")])
10199 (define_insn "sibcall_value_compact"
10200 [(set (match_operand 0 "" "=rf,rf")
10201 (call (mem:SI (match_operand:SI 1 "register_operand" "k,k"))
10202 (match_operand 2 "" "")))
10204 (use (match_operand:SI 3 "register_operand" "z,x"))
10205 (use (reg:SI R1_REG))
10206 (use (reg:SI FPSCR_MODES_REG))
10207 ;; We want to make sure the `x' above will only match MACH_REG
10208 ;; because sibcall_epilogue may clobber MACL_REG.
10209 (clobber (reg:SI MACL_REG))]
10212 static const char* alt[] =
10219 return alt[which_alternative];
10221 [(set_attr "needs_delay_slot" "yes,no")
10222 (set_attr "length" "2,4")
10223 (set (attr "fp_mode") (const_string "single"))
10224 (set_attr "type" "jump_ind")])
10226 (define_insn "sibcall_value_media"
10227 [(set (match_operand 0 "" "=rf")
10228 (call (mem:DI (match_operand 1 "target_reg_operand" "k"))
10229 (match_operand 2 "" "")))
10230 (use (reg:SI PR_MEDIA_REG))
10234 [(set_attr "type" "jump_media")])
10236 (define_expand "sibcall_value"
10238 [(set (match_operand 0 "arith_reg_operand" "")
10239 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
10240 (match_operand 2 "" "")))
10241 (match_operand 3 "" "")
10242 (use (reg:SI FPSCR_MODES_REG))
10246 if (TARGET_SHMEDIA)
10248 operands[1] = shmedia_prepare_call_address (operands[1], 1);
10249 emit_call_insn (gen_sibcall_value_media (operands[0], operands[1],
10253 else if (TARGET_SHCOMPACT && operands[3]
10254 && (INTVAL (operands[3]) & ~ CALL_COOKIE_RET_TRAMP (1)))
10256 rtx cookie_rtx = operands[3];
10257 long cookie = INTVAL (cookie_rtx);
10258 rtx func = XEXP (operands[1], 0);
10263 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
10265 rtx reg = gen_reg_rtx (Pmode);
10267 emit_insn (gen_symGOT2reg (reg, func));
10271 func = legitimize_pic_address (func, Pmode, 0);
10274 /* FIXME: if we could tell whether all argument registers are
10275 already taken, we could decide whether to force the use of
10276 MACH_REG or to stick to R0_REG. Unfortunately, there's no
10277 simple way to tell. We could use the CALL_COOKIE, but we
10278 can't currently tell a register used for regular argument
10279 passing from one that is unused. If we leave it up to reload
10280 to decide which register to use, it seems to always choose
10281 R0_REG, which leaves no available registers in SIBCALL_REGS
10282 to hold the address of the trampoline. */
10283 mach = gen_rtx_REG (SImode, MACH_REG);
10284 r1 = gen_rtx_REG (SImode, R1_REG);
10286 /* Since such a call function may use all call-clobbered
10287 registers, we force a mode switch earlier, so that we don't
10288 run out of registers when adjusting fpscr for the call. */
10289 emit_insn (gen_force_mode_for_call ());
10292 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
10293 operands[1] = force_reg (SImode, operands[1]);
10295 /* We don't need a return trampoline, since the callee will
10296 return directly to the upper caller. */
10297 if (cookie & CALL_COOKIE_RET_TRAMP (1))
10299 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
10300 cookie_rtx = GEN_INT (cookie);
10303 emit_move_insn (mach, func);
10304 emit_move_insn (r1, cookie_rtx);
10306 emit_call_insn (gen_sibcall_value_compact (operands[0], operands[1],
10307 operands[2], mach));
10310 else if (TARGET_SHCOMPACT && flag_pic
10311 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
10312 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
10314 rtx reg = gen_reg_rtx (Pmode);
10316 emit_insn (gen_symGOT2reg (reg, XEXP (operands[1], 0)));
10317 XEXP (operands[1], 0) = reg;
10319 if (flag_pic && TARGET_SH2
10320 && MEM_P (operands[1])
10321 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
10322 /* The PLT needs the PIC register, but the epilogue would have
10323 to restore it, so we can only use PC-relative PIC calls for
10324 static functions. */
10325 && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
10327 emit_call_insn (gen_sibcall_value_pcrel (operands[0],
10328 XEXP (operands[1], 0),
10333 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
10335 emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
10339 (define_insn "call_value_pop_compact"
10340 [(set (match_operand 0 "" "=rf")
10341 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
10342 (match_operand 2 "" "")))
10343 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
10344 (match_operand 4 "immediate_operand" "n")))
10345 (match_operand 3 "immediate_operand" "n")
10346 (use (reg:SI R0_REG))
10347 (use (reg:SI R1_REG))
10348 (use (reg:SI FPSCR_MODES_REG))
10349 (clobber (reg:SI PR_REG))]
10350 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
10352 [(set_attr "type" "call")
10353 (set (attr "fp_mode")
10354 (if_then_else (eq_attr "fpu_single" "yes")
10355 (const_string "single") (const_string "double")))
10356 (set_attr "needs_delay_slot" "yes")])
10358 (define_insn "call_value_pop_compact_rettramp"
10359 [(set (match_operand 0 "" "=rf")
10360 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
10361 (match_operand 2 "" "")))
10362 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
10363 (match_operand 4 "immediate_operand" "n")))
10364 (match_operand 3 "immediate_operand" "n")
10365 (use (reg:SI R0_REG))
10366 (use (reg:SI R1_REG))
10367 (use (reg:SI FPSCR_MODES_REG))
10368 (clobber (reg:SI R10_REG))
10369 (clobber (reg:SI PR_REG))]
10370 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
10372 [(set_attr "type" "call")
10373 (set (attr "fp_mode")
10374 (if_then_else (eq_attr "fpu_single" "yes")
10375 (const_string "single") (const_string "double")))
10376 (set_attr "needs_delay_slot" "yes")])
10378 (define_expand "call_value_pop"
10379 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
10380 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
10381 (match_operand 2 "" "")))
10382 (match_operand 3 "" "")
10383 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
10384 (match_operand 4 "" "")))])]
10392 gcc_assert (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]));
10393 cookie_rtx = operands[3];
10394 cookie = INTVAL (cookie_rtx);
10395 func = XEXP (operands[1], 0);
10399 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
10401 rtx reg = gen_reg_rtx (Pmode);
10403 emit_insn (gen_symGOTPLT2reg (reg, func));
10407 func = legitimize_pic_address (func, Pmode, 0);
10410 r0 = gen_rtx_REG (SImode, R0_REG);
10411 r1 = gen_rtx_REG (SImode, R1_REG);
10413 /* Since such a call function may use all call-clobbered
10414 registers, we force a mode switch earlier, so that we don't
10415 run out of registers when adjusting fpscr for the call. */
10416 emit_insn (gen_force_mode_for_call ());
10418 operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
10420 operands[1] = force_reg (SImode, operands[1]);
10422 emit_move_insn (r0, func);
10423 emit_move_insn (r1, cookie_rtx);
10425 if (cookie & CALL_COOKIE_RET_TRAMP (1))
10426 emit_call_insn (gen_call_value_pop_compact_rettramp
10427 (operands[0], operands[1], operands[2],
10428 operands[3], operands[4]));
10430 emit_call_insn (gen_call_value_pop_compact
10431 (operands[0], operands[1], operands[2],
10432 operands[3], operands[4]));
10437 (define_expand "sibcall_epilogue"
10441 sh_expand_epilogue (true);
10442 if (TARGET_SHCOMPACT)
10447 /* If epilogue clobbers r0, preserve it in macl. */
10448 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10449 if ((set = single_set (insn))
10450 && REG_P (SET_DEST (set))
10451 && REGNO (SET_DEST (set)) == R0_REG)
10453 rtx r0 = gen_rtx_REG (SImode, R0_REG);
10454 rtx tmp = gen_rtx_REG (SImode, MACL_REG);
10456 /* We can't tell at this point whether the sibcall is a
10457 sibcall_compact and, if it is, whether it uses r0 or
10458 mach as operand 2, so let the instructions that
10459 preserve r0 be optimized away if r0 turns out to be
10461 emit_insn_before (gen_rtx_SET (tmp, r0), insn);
10462 emit_move_insn (r0, tmp);
10469 (define_insn "indirect_jump_compact"
10471 (match_operand:SI 0 "arith_reg_operand" "r"))]
10474 [(set_attr "needs_delay_slot" "yes")
10475 (set_attr "type" "jump_ind")])
10477 (define_expand "indirect_jump"
10479 (match_operand 0 "register_operand" ""))]
10482 if (GET_MODE (operands[0]) != Pmode)
10483 operands[0] = gen_rtx_SUBREG (Pmode, operands[0], 0);
10486 ;; The use of operand 1 / 2 helps us distinguish case table jumps
10487 ;; which can be present in structured code from indirect jumps which can not
10488 ;; be present in structured code. This allows -fprofile-arcs to work.
10490 ;; For SH1 processors.
10491 (define_insn "casesi_jump_1"
10493 (match_operand:SI 0 "register_operand" "r"))
10494 (use (label_ref (match_operand 1 "" "")))]
10497 [(set_attr "needs_delay_slot" "yes")
10498 (set_attr "type" "jump_ind")])
10500 ;; For all later processors.
10501 (define_insn "casesi_jump_2"
10502 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
10503 (label_ref (match_operand 1 "" ""))))
10504 (use (label_ref (match_operand 2 "" "")))]
10506 && (! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn)"
10508 [(set_attr "needs_delay_slot" "yes")
10509 (set_attr "type" "jump_ind")])
10511 (define_insn "casesi_jump_media"
10512 [(set (pc) (match_operand 0 "target_reg_operand" "b"))
10513 (use (label_ref (match_operand 1 "" "")))]
10516 [(set_attr "type" "jump_media")])
10518 ;; Call subroutine returning any type.
10519 ;; ??? This probably doesn't work.
10520 (define_expand "untyped_call"
10521 [(parallel [(call (match_operand 0 "" "")
10523 (match_operand 1 "" "")
10524 (match_operand 2 "" "")])]
10525 "(TARGET_SH2E || TARGET_SH2A) || TARGET_SHMEDIA"
10527 if (! TARGET_SHMEDIA)
10529 /* RA does not know that the call sets the function value registers.
10530 We avoid problems by claiming that those registers are clobbered
10532 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
10534 rtx set = XVECEXP (operands[2], 0, i);
10535 emit_clobber (SET_SRC (set));
10539 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
10541 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
10543 rtx set = XVECEXP (operands[2], 0, i);
10544 emit_move_insn (SET_DEST (set), SET_SRC (set));
10547 /* The optimizer does not know that the call sets the function value
10548 registers we stored in the result block. We avoid problems by
10549 claiming that all hard registers are used and clobbered at this
10551 emit_insn (gen_blockage ());
10556 ;; ------------------------------------------------------------------------
10558 ;; ------------------------------------------------------------------------
10560 (define_insn "dect"
10561 [(set (reg:SI T_REG)
10562 (eq:SI (match_operand:SI 1 "arith_reg_dest" "0") (const_int 1)))
10563 (set (match_operand:SI 0 "arith_reg_dest" "=r")
10564 (plus:SI (match_dup 1) (const_int -1)))]
10567 [(set_attr "type" "arith")])
10574 ;; Load address of a label. This is only generated by the casesi expand,
10575 ;; and by machine_dependent_reorg (fixing up fp moves).
10576 ;; This must use unspec, because this only works for labels that are
10578 (define_insn "mova"
10579 [(set (reg:SI R0_REG)
10580 (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
10583 [(set_attr "in_delay_slot" "no")
10584 (set_attr "type" "arith")])
10586 ;; machine_dependent_reorg will make this a `mova'.
10587 (define_insn "mova_const"
10588 [(set (reg:SI R0_REG)
10589 (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
10592 [(set_attr "in_delay_slot" "no")
10593 (set_attr "type" "arith")])
10595 (define_expand "GOTaddr2picreg"
10596 [(set (reg:SI R0_REG)
10597 (unspec:SI [(const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC))]
10599 (set (match_dup 0) (const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC)))
10600 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
10603 if (TARGET_VXWORKS_RTP)
10605 rtx gott_base = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
10606 rtx gott_index = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
10607 emit_insn (gen_vxworks_picreg (gott_base, gott_index));
10611 operands[0] = gen_rtx_REG (Pmode, PIC_REG);
10612 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
10614 if (TARGET_SHMEDIA)
10616 rtx tr = gen_rtx_REG (Pmode, TR0_REG);
10617 rtx pic = operands[0];
10618 rtx lab = PATTERN (gen_call_site ());
10621 equiv = operands[1];
10622 operands[1] = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, operands[1], lab),
10623 UNSPEC_PCREL_SYMOFF);
10624 operands[1] = gen_rtx_CONST (Pmode, operands[1]);
10626 if (Pmode == SImode)
10628 emit_insn (gen_movsi_const (pic, operands[1]));
10629 emit_insn (gen_ptrel_si (tr, pic, copy_rtx (lab)));
10633 emit_insn (gen_movdi_const (pic, operands[1]));
10634 emit_insn (gen_ptrel_di (tr, pic, copy_rtx (lab)));
10637 insn = emit_move_insn (operands[0], tr);
10639 set_unique_reg_note (insn, REG_EQUAL, equiv);
10645 ;; A helper for GOTaddr2picreg to finish up the initialization of the
10647 (define_expand "vxworks_picreg"
10648 [(set (reg:SI PIC_REG)
10649 (const:SI (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_PIC)))
10650 (set (reg:SI R0_REG)
10651 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC)))
10652 (set (reg:SI PIC_REG)
10653 (mem:SI (reg:SI PIC_REG)))
10654 (set (reg:SI PIC_REG)
10655 (mem:SI (plus:SI (reg:SI PIC_REG)
10656 (reg:SI R0_REG))))]
10657 "TARGET_VXWORKS_RTP")
10659 (define_insn "*ptb"
10660 [(set (match_operand 0 "target_reg_operand" "=b")
10661 (const (unspec [(match_operand 1 "" "Csy")]
10662 UNSPEC_DATALABEL)))]
10663 "TARGET_SHMEDIA && flag_pic
10664 && satisfies_constraint_Csy (operands[1])"
10665 "ptb/u datalabel %1, %0"
10666 [(set_attr "type" "ptabs_media")
10667 (set_attr "length" "*")])
10669 (define_insn "ptrel_si"
10670 [(set (match_operand:SI 0 "target_reg_operand" "=b")
10671 (plus:SI (match_operand:SI 1 "register_operand" "r")
10673 (match_operand:SI 2 "" "")]
10675 "%O2: ptrel/u %1, %0"
10676 [(set_attr "type" "ptabs_media")])
10678 (define_insn "ptrel_di"
10679 [(set (match_operand:DI 0 "target_reg_operand" "=b")
10680 (plus:DI (match_operand:DI 1 "register_operand" "r")
10682 (match_operand:DI 2 "" "")]
10684 "%O2: ptrel/u %1, %0"
10685 [(set_attr "type" "ptabs_media")])
10687 (define_expand "builtin_setjmp_receiver"
10688 [(match_operand 0 "" "")]
10691 emit_insn (gen_GOTaddr2picreg ());
10695 (define_expand "call_site"
10696 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
10699 static HOST_WIDE_INT i = 0;
10700 operands[0] = GEN_INT (i);
10704 ;; op0 = op1 + r12 but hide it before reload completed. See the comment
10705 ;; in symGOT_load expand.
10706 (define_insn_and_split "chk_guard_add"
10707 [(set (match_operand:SI 0 "register_operand" "=&r")
10708 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
10713 "TARGET_SH1 && reload_completed"
10714 [(set (match_dup 0) (reg:SI PIC_REG))
10715 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
10717 [(set_attr "type" "arith")])
10719 (define_expand "sym_label2reg"
10720 [(set (match_operand:SI 0 "" "")
10721 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
10722 (const (plus:SI (match_operand:SI 2 "" "")
10727 (define_expand "symGOT_load"
10728 [(set (match_dup 2) (match_operand 1 "" ""))
10729 (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
10730 (set (match_operand 0 "" "") (mem (match_dup 3)))]
10734 bool stack_chk_guard_p = false;
10736 operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
10737 operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
10739 if (!TARGET_SHMEDIA
10740 && flag_stack_protect
10741 && GET_CODE (operands[1]) == CONST
10742 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
10743 && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
10744 && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
10745 "__stack_chk_guard") == 0)
10746 stack_chk_guard_p = true;
10748 /* Use R0 to avoid long R0 liveness which stack-protector tends to
10751 && stack_chk_guard_p && ! reload_in_progress && ! reload_completed)
10752 operands[2] = gen_rtx_REG (Pmode, R0_REG);
10754 if (TARGET_SHMEDIA)
10756 rtx reg = operands[2];
10758 if (Pmode == DImode)
10761 emit_insn (gen_movdi_const_32bit (reg, operands[1]));
10763 emit_insn (gen_movdi_const_16bit (reg, operands[1]));
10768 emit_insn (gen_movsi_const (reg, operands[1]));
10770 emit_insn (gen_movsi_const_16bit (reg, operands[1]));
10774 emit_move_insn (operands[2], operands[1]);
10776 /* When stack protector inserts codes after the result is set to
10777 R0, @(rX, r12) will cause a spill failure for R0. Use a unspec
10778 insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
10779 when rX is a GOT address for the guard symbol. Ugly but doesn't
10780 matter because this is a rare situation. */
10781 if (stack_chk_guard_p)
10782 emit_insn (gen_chk_guard_add (operands[3], operands[2]));
10784 emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2],
10785 gen_rtx_REG (Pmode, PIC_REG)));
10787 /* N.B. This is not constant for a GOTPLT relocation. */
10788 mem = gen_rtx_MEM (Pmode, operands[3]);
10789 MEM_NOTRAP_P (mem) = 1;
10790 /* ??? Should we have a special alias set for the GOT? */
10791 emit_move_insn (operands[0], mem);
10796 (define_expand "sym2GOT"
10797 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOT))]
10801 (define_expand "symGOT2reg"
10802 [(match_operand 0 "" "") (match_operand 1 "" "")]
10807 gotsym = gen_sym2GOT (operands[1]);
10808 PUT_MODE (gotsym, Pmode);
10809 insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
10811 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
10816 (define_expand "symGOTPLT2reg"
10817 [(match_operand 0 "" "") (match_operand 1 "" "")]
10820 rtx pltsym = gen_rtx_CONST (Pmode,
10821 gen_rtx_UNSPEC (Pmode,
10822 gen_rtvec (1, operands[1]),
10824 emit_insn (gen_symGOT_load (operands[0], pltsym));
10828 (define_expand "sym2GOTOFF"
10829 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTOFF))]
10833 (define_expand "symGOTOFF2reg"
10834 [(match_operand 0 "" "") (match_operand 1 "" "")]
10837 rtx gotoffsym, insn;
10838 rtx t = (!can_create_pseudo_p ()
10840 : gen_reg_rtx (GET_MODE (operands[0])));
10842 gotoffsym = gen_sym2GOTOFF (operands[1]);
10843 PUT_MODE (gotoffsym, Pmode);
10844 emit_move_insn (t, gotoffsym);
10845 insn = emit_move_insn (operands[0],
10846 gen_rtx_PLUS (Pmode, t,
10847 gen_rtx_REG (Pmode, PIC_REG)));
10849 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
10854 (define_expand "symPLT_label2reg"
10855 [(set (match_operand:SI 0 "" "")
10858 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PLT))
10859 (const:SI (plus:SI (match_operand:SI 2 "" "")
10860 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))
10861 ;; Even though the PIC register is not really used by the call
10862 ;; sequence in which this is expanded, the PLT code assumes the PIC
10863 ;; register is set, so we must not skip its initialization. Since
10864 ;; we only use this expand as part of calling sequences, and never
10865 ;; to take the address of a function, this is the best point to
10866 ;; insert the (use). Using the PLT to take the address of a
10867 ;; function would be wrong, not only because the PLT entry could
10868 ;; then be called from a function that doesn't initialize the PIC
10869 ;; register to the proper GOT, but also because pointers to the
10870 ;; same function might not compare equal, should they be set by
10871 ;; different shared libraries.
10872 (use (reg:SI PIC_REG))]
10876 (define_expand "sym2PIC"
10877 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC))]
10881 ;; -------------------------------------------------------------------------
10882 ;; TLS code generation.
10884 ;; FIXME: The multi-insn asm blocks should be converted to use
10885 ;; define_insn_and_split.
10886 ;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
10887 ;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
10890 (define_insn "tls_global_dynamic"
10891 [(set (match_operand:SI 0 "register_operand" "=&z")
10892 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
10895 (use (reg:SI FPSCR_MODES_REG))
10896 (use (reg:SI PIC_REG))
10897 (clobber (reg:SI PR_REG))
10898 (clobber (scratch:SI))]
10901 return "mov.l 1f,r4" "\n"
10903 " mov.l 2f,r1" "\n"
10910 "1: .long %a1@TLSGD" "\n"
10911 "2: .long __tls_get_addr@PLT" "\n"
10914 [(set_attr "type" "tls_load")
10915 (set_attr "length" "26")])
10917 (define_insn "tls_local_dynamic"
10918 [(set (match_operand:SI 0 "register_operand" "=&z")
10919 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
10922 (use (reg:SI FPSCR_MODES_REG))
10923 (use (reg:SI PIC_REG))
10924 (clobber (reg:SI PR_REG))
10925 (clobber (scratch:SI))]
10928 return "mov.l 1f,r4" "\n"
10930 " mov.l 2f,r1" "\n"
10937 "1: .long %a1@TLSLDM" "\n"
10938 "2: .long __tls_get_addr@PLT" "\n"
10941 [(set_attr "type" "tls_load")
10942 (set_attr "length" "26")])
10944 (define_expand "sym2DTPOFF"
10945 [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
10949 (define_expand "symDTPOFF2reg"
10950 [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
10954 rtx t = (!can_create_pseudo_p ()
10956 : gen_reg_rtx (GET_MODE (operands[0])));
10958 dtpoffsym = gen_sym2DTPOFF (operands[1]);
10959 PUT_MODE (dtpoffsym, Pmode);
10960 emit_move_insn (t, dtpoffsym);
10961 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, operands[2]));
10965 (define_expand "sym2GOTTPOFF"
10966 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
10970 (define_insn "tls_initial_exec"
10971 [(set (match_operand:SI 0 "register_operand" "=&r")
10972 (unspec:SI [(match_operand:SI 1 "" "")]
10974 (use (reg:SI GBR_REG))
10975 (use (reg:SI PIC_REG))
10976 (clobber (reg:SI R0_REG))]
10979 return "mov.l 1f,r0" "\n"
10981 " mov.l @(r0,r12),r0" "\n"
10985 "1: .long %a1" "\n"
10988 [(set_attr "type" "tls_load")
10989 (set_attr "length" "16")])
10991 (define_expand "sym2TPOFF"
10992 [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
10996 (define_expand "symTPOFF2reg"
10997 [(match_operand 0 "" "") (match_operand 1 "" "")]
11002 tpoffsym = gen_sym2TPOFF (operands[1]);
11003 PUT_MODE (tpoffsym, Pmode);
11004 emit_move_insn (operands[0], tpoffsym);
11008 ;;------------------------------------------------------------------------------
11009 ;; Thread pointer getter and setter.
11011 ;; On SH the thread pointer is kept in the GBR.
11012 ;; These patterns are usually expanded from the respective built-in functions.
11013 (define_expand "get_thread_pointersi"
11014 [(set (match_operand:SI 0 "arith_reg_dest") (reg:SI GBR_REG))]
11017 ;; The store_gbr insn can also be used on !TARGET_SH1 for doing TLS accesses.
11018 (define_insn "store_gbr"
11019 [(set (match_operand:SI 0 "arith_reg_dest" "=r") (reg:SI GBR_REG))]
11022 [(set_attr "type" "tls_load")])
11024 (define_expand "set_thread_pointersi"
11025 [(set (reg:SI GBR_REG)
11026 (unspec_volatile:SI [(match_operand:SI 0 "arith_reg_operand")]
11030 (define_insn "load_gbr"
11031 [(set (reg:SI GBR_REG)
11032 (unspec_volatile:SI [(match_operand:SI 0 "arith_reg_operand" "r")]
11036 [(set_attr "type" "move")])
11038 ;;------------------------------------------------------------------------------
11039 ;; Thread pointer relative memory loads and stores.
11041 ;; On SH there are GBR displacement address modes which can be utilized to
11042 ;; access memory behind the thread pointer.
11043 ;; Since we do not allow using GBR for general purpose memory accesses, these
11044 ;; GBR addressing modes are formed by the combine pass.
11045 ;; This could be done with fewer patterns than below by using a mem predicate
11046 ;; for the GBR mem, but then reload would try to reload addresses with a
11047 ;; zero displacement for some strange reason.
11049 (define_insn "*mov<mode>_gbr_load"
11050 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
11051 (mem:QIHISI (plus:SI (reg:SI GBR_REG)
11052 (match_operand:QIHISI 1 "gbr_displacement"))))]
11054 "mov.<bwl> @(%O1,gbr),%0"
11055 [(set_attr "type" "load")])
11057 (define_insn "*mov<mode>_gbr_load"
11058 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
11059 (mem:QIHISI (reg:SI GBR_REG)))]
11061 "mov.<bwl> @(0,gbr),%0"
11062 [(set_attr "type" "load")])
11064 (define_insn "*mov<mode>_gbr_load"
11065 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
11067 (mem:QIHI (plus:SI (reg:SI GBR_REG)
11068 (match_operand:QIHI 1 "gbr_displacement")))))]
11070 "mov.<bw> @(%O1,gbr),%0"
11071 [(set_attr "type" "load")])
11073 (define_insn "*mov<mode>_gbr_load"
11074 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
11075 (sign_extend:SI (mem:QIHI (reg:SI GBR_REG))))]
11077 "mov.<bw> @(0,gbr),%0"
11078 [(set_attr "type" "load")])
11080 (define_insn "*mov<mode>_gbr_store"
11081 [(set (mem:QIHISI (plus:SI (reg:SI GBR_REG)
11082 (match_operand:QIHISI 0 "gbr_displacement")))
11083 (match_operand:QIHISI 1 "register_operand" "z"))]
11085 "mov.<bwl> %1,@(%O0,gbr)"
11086 [(set_attr "type" "store")])
11088 (define_insn "*mov<mode>_gbr_store"
11089 [(set (mem:QIHISI (reg:SI GBR_REG))
11090 (match_operand:QIHISI 0 "register_operand" "z"))]
11092 "mov.<bwl> %0,@(0,gbr)"
11093 [(set_attr "type" "store")])
11095 ;; DImode memory accesses have to be split in two SImode accesses.
11096 ;; Split them before reload, so that it gets a better chance to figure out
11097 ;; how to deal with the R0 restriction for the individual SImode accesses.
11098 ;; Do not match this insn during or after reload because it can't be split
11100 (define_insn_and_split "*movdi_gbr_load"
11101 [(set (match_operand:DI 0 "arith_reg_dest")
11102 (match_operand:DI 1 "gbr_address_mem"))]
11103 "TARGET_SH1 && can_create_pseudo_p ()"
11106 [(set (match_dup 3) (match_dup 5))
11107 (set (match_dup 4) (match_dup 6))]
11109 /* Swap low/high part load order on little endian, so that the result reg
11110 of the second load can be used better. */
11111 int off = TARGET_LITTLE_ENDIAN ? 1 : 0;
11112 operands[3 + off] = gen_lowpart (SImode, operands[0]);
11113 operands[5 + off] = gen_lowpart (SImode, operands[1]);
11114 operands[4 - off] = gen_highpart (SImode, operands[0]);
11115 operands[6 - off] = gen_highpart (SImode, operands[1]);
11118 (define_insn_and_split "*movdi_gbr_store"
11119 [(set (match_operand:DI 0 "gbr_address_mem")
11120 (match_operand:DI 1 "register_operand"))]
11121 "TARGET_SH1 && can_create_pseudo_p ()"
11124 [(set (match_dup 3) (match_dup 5))
11125 (set (match_dup 4) (match_dup 6))]
11127 /* Swap low/high part store order on big endian, so that stores of function
11128 call results can save a reg copy. */
11129 int off = TARGET_LITTLE_ENDIAN ? 0 : 1;
11130 operands[3 + off] = gen_lowpart (SImode, operands[0]);
11131 operands[5 + off] = gen_lowpart (SImode, operands[1]);
11132 operands[4 - off] = gen_highpart (SImode, operands[0]);
11133 operands[6 - off] = gen_highpart (SImode, operands[1]);
11136 ;; Sometimes memory accesses do not get combined with the store_gbr insn,
11137 ;; in particular when the displacements are in the range of the regular move
11138 ;; insns. Thus, in the first split pass after the combine pass we search
11139 ;; for missed opportunities and try to fix them up ourselves.
11140 ;; If an equivalent GBR address can be determined the load / store is split
11141 ;; into one of the GBR load / store patterns.
11142 ;; All of that must happen before reload (GBR address modes use R0 as the
11143 ;; other operand) and there's no point of doing it if the GBR is not
11144 ;; referenced in a function at all.
11146 [(set (match_operand:QIHISIDI 0 "register_operand")
11147 (match_operand:QIHISIDI 1 "memory_operand"))]
11148 "TARGET_SH1 && !reload_in_progress && !reload_completed
11149 && df_regs_ever_live_p (GBR_REG)"
11150 [(set (match_dup 0) (match_dup 1))]
11152 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
11153 if (gbr_mem != NULL_RTX)
11154 operands[1] = replace_equiv_address (operands[1], gbr_mem);
11160 [(set (match_operand:SI 0 "register_operand")
11161 (sign_extend:SI (match_operand:QIHI 1 "memory_operand")))]
11162 "TARGET_SH1 && !reload_in_progress && !reload_completed
11163 && df_regs_ever_live_p (GBR_REG)"
11164 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
11166 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
11167 if (gbr_mem != NULL_RTX)
11168 operands[1] = replace_equiv_address (operands[1], gbr_mem);
11173 ;; On SH2A we've got movu.b and movu.w for doing zero-extending mem loads.
11174 ;; Split those so that a GBR load can be used.
11176 [(set (match_operand:SI 0 "register_operand")
11177 (zero_extend:SI (match_operand:QIHI 1 "memory_operand")))]
11178 "TARGET_SH2A && !reload_in_progress && !reload_completed
11179 && df_regs_ever_live_p (GBR_REG)"
11180 [(set (match_dup 2) (match_dup 1))
11181 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
11183 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
11184 if (gbr_mem != NULL_RTX)
11186 operands[2] = gen_reg_rtx (GET_MODE (operands[1]));
11187 operands[1] = replace_equiv_address (operands[1], gbr_mem);
11194 [(set (match_operand:QIHISIDI 0 "memory_operand")
11195 (match_operand:QIHISIDI 1 "register_operand"))]
11196 "TARGET_SH1 && !reload_in_progress && !reload_completed
11197 && df_regs_ever_live_p (GBR_REG)"
11198 [(set (match_dup 0) (match_dup 1))]
11200 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[0]);
11201 if (gbr_mem != NULL_RTX)
11202 operands[0] = replace_equiv_address (operands[0], gbr_mem);
11207 ;;------------------------------------------------------------------------------
11208 ;; case instruction for switch statements.
11210 ;; operand 0 is index
11211 ;; operand 1 is the minimum bound
11212 ;; operand 2 is the maximum bound - minimum bound + 1
11213 ;; operand 3 is CODE_LABEL for the table;
11214 ;; operand 4 is the CODE_LABEL to go to if index out of range.
11215 (define_expand "casesi"
11216 [(match_operand:SI 0 "arith_reg_operand" "")
11217 (match_operand:SI 1 "arith_reg_operand" "")
11218 (match_operand:SI 2 "arith_reg_operand" "")
11219 (match_operand 3 "" "") (match_operand 4 "" "")]
11222 rtx reg = gen_reg_rtx (SImode);
11223 rtx reg2 = gen_reg_rtx (SImode);
11224 if (TARGET_SHMEDIA)
11226 rtx reg = gen_reg_rtx (DImode);
11227 rtx reg2 = gen_reg_rtx (DImode);
11228 rtx reg3 = gen_reg_rtx (Pmode);
11229 rtx reg4 = gen_reg_rtx (Pmode);
11230 rtx reg5 = gen_reg_rtx (Pmode);
11233 operands[0] = convert_modes (DImode, SImode, operands[0], 0);
11234 operands[1] = convert_modes (DImode, SImode, operands[1], 0);
11235 operands[2] = convert_modes (DImode, SImode, operands[2], 1);
11237 test = gen_rtx_GT (VOIDmode, operands[1], operands[0]);
11238 emit_jump_insn (gen_cbranchdi4 (test, operands[1], operands[0],
11240 emit_move_insn (reg, gen_rtx_MINUS (DImode, operands[0], operands[1]));
11241 test = gen_rtx_GTU (VOIDmode, reg, operands[2]);
11242 emit_jump_insn (gen_cbranchdi4 (test, reg, operands[2], operands[4]));
11243 emit_insn (gen_casesi_shift_media (reg2, reg, operands[3]));
11244 emit_move_insn (reg3, gen_datalabel_ref (gen_rtx_LABEL_REF
11245 (Pmode, operands[3])));
11246 /* Messy: can we subreg to clean this up? */
11247 if (Pmode == DImode)
11248 load = gen_casesi_load_media (reg4, reg3, reg2, operands[3]);
11250 load = gen_casesi_load_media (reg4,
11251 gen_rtx_SUBREG (DImode, reg3, 0),
11252 reg2, operands[3]);
11253 PUT_MODE (SET_SRC (load), Pmode);
11255 /* ??? The following add could be eliminated if we used ptrel. */
11256 emit_move_insn (reg5, gen_rtx_PLUS (Pmode, reg3, reg4));
11257 emit_jump_insn (gen_casesi_jump_media (reg5, operands[3]));
11261 operands[1] = copy_to_mode_reg (SImode, operands[1]);
11262 operands[2] = copy_to_mode_reg (SImode, operands[2]);
11263 /* If optimizing, casesi_worker depends on the mode of the instruction
11264 before label it 'uses' - operands[3]. */
11265 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
11267 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
11269 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
11271 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
11272 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
11273 operands[3], but to lab. We will fix this up in
11274 machine_dependent_reorg. */
11279 (define_expand "casesi_0"
11280 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
11281 (set (match_dup 4) (minus:SI (match_dup 4)
11282 (match_operand:SI 1 "arith_operand" "")))
11283 (set (reg:SI T_REG)
11284 (gtu:SI (match_dup 4)
11285 (match_operand:SI 2 "arith_reg_operand" "")))
11287 (if_then_else (ne (reg:SI T_REG)
11289 (label_ref (match_operand 3 "" ""))
11294 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
11295 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
11296 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
11297 (define_insn "casesi_worker_0"
11298 [(set (match_operand:SI 0 "register_operand" "=r,r")
11299 (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
11300 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
11301 (clobber (match_scratch:SI 3 "=X,1"))
11302 (clobber (match_scratch:SI 4 "=&z,z"))]
11307 [(set (match_operand:SI 0 "register_operand" "")
11308 (unspec:SI [(match_operand:SI 1 "register_operand" "")
11309 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
11310 (clobber (match_scratch:SI 3 ""))
11311 (clobber (match_scratch:SI 4 ""))]
11312 "TARGET_SH1 && ! TARGET_SH2 && reload_completed"
11313 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
11314 (parallel [(set (match_dup 0)
11315 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
11316 (label_ref (match_dup 2))] UNSPEC_CASESI))
11317 (clobber (match_dup 3))])
11318 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
11320 if (GET_CODE (operands[2]) == CODE_LABEL)
11321 LABEL_NUSES (operands[2])++;
11325 [(set (match_operand:SI 0 "register_operand" "")
11326 (unspec:SI [(match_operand:SI 1 "register_operand" "")
11327 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
11328 (clobber (match_scratch:SI 3 ""))
11329 (clobber (match_scratch:SI 4 ""))]
11330 "TARGET_SH2 && reload_completed"
11331 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
11332 (parallel [(set (match_dup 0)
11333 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
11334 (label_ref (match_dup 2))] UNSPEC_CASESI))
11335 (clobber (match_dup 3))])]
11337 if (GET_CODE (operands[2]) == CODE_LABEL)
11338 LABEL_NUSES (operands[2])++;
11341 (define_insn "casesi_worker_1"
11342 [(set (match_operand:SI 0 "register_operand" "=r,r")
11343 (unspec:SI [(reg:SI R0_REG)
11344 (match_operand:SI 1 "register_operand" "0,r")
11345 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
11346 (clobber (match_scratch:SI 3 "=X,1"))]
11349 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
11351 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
11353 switch (GET_MODE (diff_vec))
11356 return "shll2 %1" "\n"
11357 " mov.l @(r0,%1),%0";
11359 return "add %1,%1" "\n"
11360 " mov.w @(r0,%1),%0";
11362 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
11363 return "mov.b @(r0,%1),%0" "\n"
11366 return "mov.b @(r0,%1),%0";
11369 gcc_unreachable ();
11372 [(set_attr "length" "4")])
11374 (define_insn "casesi_worker_2"
11375 [(set (match_operand:SI 0 "register_operand" "=r,r")
11376 (unspec:SI [(reg:SI R0_REG)
11377 (match_operand:SI 1 "register_operand" "0,r")
11378 (label_ref (match_operand 2 "" ""))
11379 (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))
11380 (clobber (match_operand:SI 4 "" "=X,1"))]
11381 "TARGET_SH2 && reload_completed && flag_pic"
11383 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
11384 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
11386 switch (GET_MODE (diff_vec))
11389 return "shll2 %1" "\n"
11391 " mova %O3,r0" "\n"
11392 " mov.l @(r0,%1),%0";
11394 return "add %1,%1" "\n"
11396 " mova %O3,r0" "\n"
11397 " mov.w @(r0,%1),%0";
11399 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
11400 return "add r0,%1" "\n"
11401 " mova %O3,r0" "\n"
11402 " mov.b @(r0,%1),%0" "\n"
11405 return "add r0,%1" "\n"
11406 " mova %O3,r0" "\n"
11407 " mov.b @(r0,%1),%0";
11409 gcc_unreachable ();
11412 [(set_attr "length" "8")])
11414 (define_insn "casesi_shift_media"
11415 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
11416 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
11417 (unspec:DI [(label_ref:DI (match_operand 2 "" ""))]
11421 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
11423 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
11425 switch (GET_MODE (diff_vec))
11428 return "shlli %1, 2, %0";
11430 return "shlli %1, 1, %0";
11432 if (rtx_equal_p (operands[0], operands[1]))
11434 return "add %1, r63, %0";
11436 gcc_unreachable ();
11439 [(set_attr "type" "arith_media")])
11441 (define_insn "casesi_load_media"
11442 [(set (match_operand 0 "any_arith_reg_dest" "=r")
11443 (mem (unspec [(match_operand:DI 1 "arith_reg_operand" "r")
11444 (match_operand:DI 2 "arith_reg_operand" "r")
11445 (label_ref:DI (match_operand 3 "" ""))] UNSPEC_CASESI)))]
11448 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[3])));
11450 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
11452 switch (GET_MODE (diff_vec))
11455 return "ldx.l %1, %2, %0";
11458 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
11459 return "ldx.uw %1, %2, %0";
11461 return "ldx.w %1, %2, %0";
11463 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
11464 return "ldx.ub %1, %2, %0";
11465 return "ldx.b %1, %2, %0";
11467 gcc_unreachable ();
11470 [(set_attr "type" "load_media")])
11472 (define_expand "simple_return"
11474 "sh_can_use_simple_return_p ()")
11476 (define_expand "return"
11478 "reload_completed && epilogue_completed"
11480 if (TARGET_SHMEDIA)
11482 emit_jump_insn (gen_return_media ());
11486 if (TARGET_SHCOMPACT
11487 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1)))
11489 emit_jump_insn (gen_shcompact_return_tramp ());
11494 (define_insn "*<code>_i"
11496 "TARGET_SH1 && ! (TARGET_SHCOMPACT
11497 && (crtl->args.info.call_cookie
11498 & CALL_COOKIE_RET_TRAMP (1)))
11499 && reload_completed
11500 && ! sh_cfun_trap_exit_p ()"
11502 if (TARGET_SH2A && (dbr_sequence_length () == 0)
11503 && !current_function_interrupt)
11508 [(set_attr "type" "return")
11509 (set_attr "needs_delay_slot" "yes")])
11511 ;; trapa has no delay slot.
11512 (define_insn "*return_trapa"
11514 "TARGET_SH1 && !TARGET_SHCOMPACT
11515 && reload_completed"
11517 [(set_attr "type" "return")])
11519 (define_expand "shcompact_return_tramp"
11522 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
11524 rtx reg = gen_rtx_REG (Pmode, R0_REG);
11526 function_symbol (reg, "__GCC_shcompact_return_trampoline", SFUNC_STATIC);
11527 emit_jump_insn (gen_shcompact_return_tramp_i ());
11531 (define_insn "shcompact_return_tramp_i"
11532 [(parallel [(return) (use (reg:SI R0_REG))])]
11534 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
11536 [(set_attr "type" "jump_ind")
11537 (set_attr "needs_delay_slot" "yes")])
11539 (define_insn "return_media_i"
11540 [(parallel [(return) (use (match_operand 0 "target_reg_operand" "k"))])]
11541 "TARGET_SHMEDIA && reload_completed"
11543 [(set_attr "type" "jump_media")])
11545 (define_insn "return_media_rte"
11547 "TARGET_SHMEDIA && reload_completed && current_function_interrupt"
11549 [(set_attr "type" "jump_media")])
11551 (define_expand "return_media"
11553 "TARGET_SHMEDIA && reload_completed"
11555 int tr_regno = sh_media_register_for_return ();
11558 if (current_function_interrupt)
11560 emit_jump_insn (gen_return_media_rte ());
11565 rtx r18 = gen_rtx_REG (Pmode, PR_MEDIA_REG);
11567 gcc_assert (call_really_used_regs[TR0_REG] && !fixed_regs[TR0_REG]);
11568 tr_regno = TR0_REG;
11569 tr = gen_rtx_REG (Pmode, tr_regno);
11570 emit_move_insn (tr, r18);
11573 tr = gen_rtx_REG (Pmode, tr_regno);
11575 emit_jump_insn (gen_return_media_i (tr));
11579 (define_insn "shcompact_preserve_incoming_args"
11580 [(set (match_operand:SI 0 "register_operand" "+r")
11581 (unspec:SI [(match_dup 0)] UNSPEC_COMPACT_ARGS))]
11584 [(set_attr "length" "0")])
11586 (define_insn "shcompact_incoming_args"
11587 [(set (reg:SI R2_REG) (unspec:SI [(reg:SI R2_REG)] UNSPEC_COMPACT_ARGS))
11588 (set (reg:SI R3_REG) (unspec:SI [(reg:SI R3_REG)] UNSPEC_COMPACT_ARGS))
11589 (set (reg:SI R4_REG) (unspec:SI [(reg:SI R4_REG)] UNSPEC_COMPACT_ARGS))
11590 (set (reg:SI R5_REG) (unspec:SI [(reg:SI R5_REG)] UNSPEC_COMPACT_ARGS))
11591 (set (reg:SI R6_REG) (unspec:SI [(reg:SI R6_REG)] UNSPEC_COMPACT_ARGS))
11592 (set (reg:SI R7_REG) (unspec:SI [(reg:SI R7_REG)] UNSPEC_COMPACT_ARGS))
11593 (set (reg:SI R8_REG) (unspec:SI [(reg:SI R8_REG)] UNSPEC_COMPACT_ARGS))
11594 (set (reg:SI R9_REG) (unspec:SI [(reg:SI R9_REG)] UNSPEC_COMPACT_ARGS))
11595 (set (mem:BLK (reg:SI MACL_REG))
11596 (unspec:BLK [(reg:SI MACH_REG)] UNSPEC_COMPACT_ARGS))
11597 (use (reg:SI R0_REG))
11598 (clobber (reg:SI R0_REG))
11599 (clobber (reg:SI MACL_REG))
11600 (clobber (reg:SI MACH_REG))
11601 (clobber (reg:SI PR_REG))]
11604 [(set_attr "needs_delay_slot" "yes")])
11606 (define_insn "shmedia_save_restore_regs_compact"
11607 [(set (reg:SI SP_REG)
11608 (plus:SI (reg:SI SP_REG)
11609 (match_operand:SI 0 "immediate_operand" "i")))
11610 (use (reg:SI R0_REG))
11611 (clobber (reg:SI PR_REG))]
11613 && (INTVAL (operands[0]) == SHMEDIA_REGS_STACK_ADJUST ()
11614 || INTVAL (operands[0]) == - SHMEDIA_REGS_STACK_ADJUST ())"
11616 [(set_attr "needs_delay_slot" "yes")])
11618 (define_expand "prologue"
11622 sh_expand_prologue ();
11626 (define_expand "epilogue"
11630 sh_expand_epilogue (false);
11632 || (TARGET_SHCOMPACT
11633 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))))
11635 emit_jump_insn (gen_return ());
11640 (define_expand "eh_return"
11641 [(use (match_operand 0 "register_operand" ""))]
11644 rtx ra = operands[0];
11646 if (TARGET_SHMEDIA64)
11647 emit_insn (gen_eh_set_ra_di (ra));
11649 emit_insn (gen_eh_set_ra_si (ra));
11654 ;; Clobber the return address on the stack. We can't expand this
11655 ;; until we know where it will be put in the stack frame.
11657 (define_insn "eh_set_ra_si"
11658 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
11660 (clobber (match_scratch:SI 1 "=&r"))]
11661 "! TARGET_SHMEDIA64"
11664 (define_insn "eh_set_ra_di"
11665 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
11667 (clobber (match_scratch:DI 1 "=&r"))]
11672 [(unspec_volatile [(match_operand 0 "register_operand" "")]
11674 (clobber (match_scratch 1 ""))]
11678 sh_set_return_address (operands[0], operands[1]);
11682 (define_insn "blockage"
11683 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
11686 [(set_attr "length" "0")])
11688 ;; Define movml instructions for SH2A target. Currently they are
11689 ;; used to push and pop all banked registers only.
11691 (define_insn "movml_push_banked"
11692 [(set (match_operand:SI 0 "register_operand" "=r")
11693 (plus (match_dup 0) (const_int -32)))
11694 (set (mem:SI (plus:SI (match_dup 0) (const_int 28))) (reg:SI R7_REG))
11695 (set (mem:SI (plus:SI (match_dup 0) (const_int 24))) (reg:SI R6_REG))
11696 (set (mem:SI (plus:SI (match_dup 0) (const_int 20))) (reg:SI R5_REG))
11697 (set (mem:SI (plus:SI (match_dup 0) (const_int 16))) (reg:SI R4_REG))
11698 (set (mem:SI (plus:SI (match_dup 0) (const_int 12))) (reg:SI R3_REG))
11699 (set (mem:SI (plus:SI (match_dup 0) (const_int 8))) (reg:SI R2_REG))
11700 (set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG))
11701 (set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))]
11702 "TARGET_SH2A && REGNO (operands[0]) == 15"
11704 [(set_attr "in_delay_slot" "no")])
11706 (define_insn "movml_pop_banked"
11707 [(set (match_operand:SI 0 "register_operand" "=r")
11708 (plus (match_dup 0) (const_int 32)))
11709 (set (reg:SI R0_REG) (mem:SI (plus:SI (match_dup 0) (const_int -32))))
11710 (set (reg:SI R1_REG) (mem:SI (plus:SI (match_dup 0) (const_int -28))))
11711 (set (reg:SI R2_REG) (mem:SI (plus:SI (match_dup 0) (const_int -24))))
11712 (set (reg:SI R3_REG) (mem:SI (plus:SI (match_dup 0) (const_int -20))))
11713 (set (reg:SI R4_REG) (mem:SI (plus:SI (match_dup 0) (const_int -16))))
11714 (set (reg:SI R5_REG) (mem:SI (plus:SI (match_dup 0) (const_int -12))))
11715 (set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8))))
11716 (set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))]
11717 "TARGET_SH2A && REGNO (operands[0]) == 15"
11719 [(set_attr "in_delay_slot" "no")])
11721 ;; ------------------------------------------------------------------------
11722 ;; Scc instructions
11723 ;; ------------------------------------------------------------------------
11725 (define_insn "movt"
11726 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11727 (match_operand:SI 1 "t_reg_operand"))]
11730 [(set_attr "type" "arith")])
11732 (define_insn "movrt"
11733 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11734 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
11737 [(set_attr "type" "arith")])
11739 (define_expand "cstore4_media"
11740 [(set (match_operand:SI 0 "register_operand" "=r")
11741 (match_operator:SI 1 "sh_float_comparison_operator"
11742 [(match_operand 2 "logical_operand" "")
11743 (match_operand 3 "cmp_operand" "")]))]
11746 machine_mode mode = GET_MODE (operands[2]);
11747 enum rtx_code code = GET_CODE (operands[1]);
11749 if (mode == VOIDmode)
11750 mode = GET_MODE (operands[3]);
11751 if (operands[2] == const0_rtx)
11753 if (code == EQ || code == NE)
11754 operands[2] = operands[3], operands[3] = const0_rtx;
11757 operands[2] = force_reg (mode, operands[2]);
11758 if (operands[3] != const0_rtx)
11759 operands[3] = force_reg (mode, operands[3]);
11765 swap = invert = !FLOAT_MODE_P (mode);
11770 swap = FLOAT_MODE_P (mode), invert = !swap;
11775 swap = true, invert = false;
11782 swap = invert = false;
11786 swap = invert = true;
11790 gcc_unreachable ();
11795 std::swap (operands[2], operands[3]);
11796 code = swap_condition (code);
11801 rtx tem = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
11802 code = reverse_condition (code);
11803 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]);
11804 emit_insn (gen_cstore4_media (tem, operands[1],
11805 operands[2], operands[3]));
11808 operands[3] = const0_rtx;
11811 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]);
11814 (define_expand "cstoresi4"
11815 [(set (match_operand:SI 0 "register_operand" "=r")
11816 (match_operator:SI 1 "comparison_operator"
11817 [(match_operand:SI 2 "cmpsi_operand" "")
11818 (match_operand:SI 3 "arith_operand" "")]))]
11819 "TARGET_SH1 || TARGET_SHMEDIA"
11821 if (TARGET_SHMEDIA)
11823 emit_insn (gen_cstore4_media (operands[0], operands[1],
11824 operands[2], operands[3]));
11828 if (sh_expand_t_scc (operands))
11831 if (! currently_expanding_to_rtl)
11834 sh_emit_compare_and_set (operands, SImode);
11838 (define_expand "cstoredi4"
11839 [(set (match_operand:SI 0 "register_operand" "=r")
11840 (match_operator:SI 1 "comparison_operator"
11841 [(match_operand:DI 2 "arith_operand" "")
11842 (match_operand:DI 3 "arith_operand" "")]))]
11843 "TARGET_SH2 || TARGET_SHMEDIA"
11845 if (TARGET_SHMEDIA)
11847 emit_insn (gen_cstore4_media (operands[0], operands[1],
11848 operands[2], operands[3]));
11852 if (sh_expand_t_scc (operands))
11855 if (! currently_expanding_to_rtl)
11858 sh_emit_compare_and_set (operands, DImode);
11862 ;; Move the complement of the T reg to a reg.
11863 ;; On SH2A the movrt insn can be used.
11864 ;; On anything else than SH2A this has to be done with multiple instructions.
11865 ;; One obvious way would be:
11870 ;; However, this puts pressure on r0 in most cases and thus the following is
11876 ;; If the constant -1 can be CSE-ed or lifted out of a loop it effectively
11877 ;; becomes a one instruction operation. Moreover, care must be taken that
11878 ;; the insn can still be combined with inverted compare and branch code
11879 ;; around it. On the other hand, if a function returns the complement of
11880 ;; a previous comparison result in the T bit, the xor #1,r0 approach might
11881 ;; lead to better code.
11882 (define_expand "movnegt"
11883 [(set (match_operand:SI 0 "arith_reg_dest" "")
11884 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
11888 emit_insn (gen_movrt (operands[0], operands[1]));
11891 rtx val = force_reg (SImode, gen_int_mode (-1, SImode));
11892 emit_insn (gen_movrt_negc (operands[0], operands[1], val));
11897 (define_insn_and_split "movrt_negc"
11898 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11899 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
11900 (set (reg:SI T_REG) (const_int 1))
11901 (use (match_operand:SI 2 "arith_reg_operand" "r"))]
11904 "&& !sh_in_recog_treg_set_expr ()"
11907 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
11912 [(set_attr "type" "arith")])
11914 ;; The -1 constant will not be CSE-ed for the *movrt_negc pattern, but the
11915 ;; pattern can be used by the combine pass. Using a scratch reg for the
11916 ;; -1 constant results in slightly better register allocations compared to
11917 ;; generating a pseudo reg before reload.
11918 (define_insn_and_split "*movrt_negc"
11919 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11920 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
11921 (clobber (match_scratch:SI 2 "=r"))
11922 (clobber (reg:SI T_REG))]
11923 "TARGET_SH1 && ! TARGET_SH2A"
11925 "&& !sh_in_recog_treg_set_expr ()"
11928 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
11930 else if (reload_completed)
11932 emit_move_insn (operands[2], gen_int_mode (-1, SImode));
11933 emit_insn (gen_movrt_negc (operands[0], operands[1], operands[2]));
11940 ;; Store the negated T bit in a reg using r0 and xor. This one doesn't
11941 ;; clobber the T bit, which is useful when storing the T bit and the
11942 ;; negated T bit in parallel. On SH2A the movrt insn can be used for that.
11943 ;; Usually we don't want this insn to be matched, except for cases where the
11944 ;; T bit clobber is really not appreciated. Hence the extra use on T_REG.
11945 (define_insn_and_split "movrt_xor"
11946 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
11947 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
11948 (use (reg:SI T_REG))]
11951 "&& reload_completed"
11952 [(set (match_dup 0) (reg:SI T_REG))
11953 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))])
11955 ;; Use negc to store the T bit in a MSB of a reg in the following way:
11956 ;; T = 0: 0x80000000 -> reg
11957 ;; T = 1: 0x7FFFFFFF -> reg
11958 ;; This works because 0 - 0x80000000 = 0x80000000.
11959 (define_insn_and_split "*mov_t_msb_neg"
11960 [(set (match_operand:SI 0 "arith_reg_dest")
11961 (minus:SI (const_int -2147483648) ;; 0x80000000
11962 (match_operand 1 "treg_set_expr")))
11963 (clobber (reg:SI T_REG))]
11964 "TARGET_SH1 && can_create_pseudo_p ()"
11969 if (negt_reg_operand (operands[1], VOIDmode))
11971 emit_insn (gen_addc (operands[0],
11972 force_reg (SImode, const0_rtx),
11973 force_reg (SImode, GEN_INT (2147483647))));
11977 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
11978 if (ti.remove_trailing_nott ())
11979 emit_insn (gen_addc (operands[0],
11980 force_reg (SImode, const0_rtx),
11981 force_reg (SImode, GEN_INT (2147483647))));
11983 emit_insn (gen_negc (operands[0],
11984 force_reg (SImode, GEN_INT (-2147483648LL))));
11989 ;; 0x7fffffff + (1-T) = 0 - 0x80000000 - T
11990 (define_insn_and_split "*mov_t_msb_neg"
11991 [(set (match_operand:SI 0 "arith_reg_dest")
11992 (plus:SI (match_operand 1 "treg_set_expr")
11993 (const_int 2147483647))) ;; 0x7fffffff
11994 (clobber (reg:SI T_REG))]
11997 "&& can_create_pseudo_p ()"
12000 if (negt_reg_operand (operands[1], VOIDmode))
12002 emit_insn (gen_negc (operands[0],
12003 force_reg (SImode, GEN_INT (-2147483648LL))));
12007 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
12008 if (ti.remove_trailing_nott ())
12009 emit_insn (gen_negc (operands[0],
12010 force_reg (SImode, GEN_INT (-2147483648LL))));
12012 emit_insn (gen_addc (operands[0],
12013 force_reg (SImode, const0_rtx),
12014 force_reg (SImode, GEN_INT (2147483647))));
12018 (define_insn_and_split "*mov_t_msb_neg"
12019 [(set (match_operand:SI 0 "arith_reg_dest")
12020 (if_then_else:SI (match_operand 1 "treg_set_expr")
12021 (match_operand 2 "const_int_operand")
12022 (match_operand 3 "const_int_operand")))
12023 (clobber (reg:SI T_REG))]
12024 "TARGET_SH1 && can_create_pseudo_p ()
12025 && ((INTVAL (operands[2]) == -2147483648LL
12026 && INTVAL (operands[3]) == 2147483647LL)
12027 || (INTVAL (operands[2]) == 2147483647LL
12028 && INTVAL (operands[3]) == -2147483648LL))"
12033 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
12035 if (INTVAL (operands[2]) == -2147483648LL)
12037 if (ti.remove_trailing_nott ())
12038 emit_insn (gen_negc (operands[0],
12039 force_reg (SImode, GEN_INT (-2147483648LL))));
12041 emit_insn (gen_addc (operands[0],
12042 force_reg (SImode, const0_rtx),
12043 force_reg (SImode, operands[3])));
12046 else if (INTVAL (operands[2]) == 2147483647LL)
12048 if (ti.remove_trailing_nott ())
12049 emit_insn (gen_addc (operands[0],
12050 force_reg (SImode, const0_rtx),
12051 force_reg (SImode, GEN_INT (2147483647LL))));
12053 emit_insn (gen_negc (operands[0],
12054 force_reg (SImode, GEN_INT (-2147483648LL))));
12058 gcc_unreachable ();
12061 ;; The *negnegt pattern helps the combine pass to figure out how to fold
12062 ;; an explicit double T bit negation.
12063 (define_insn_and_split "*negnegt"
12064 [(set (reg:SI T_REG)
12065 (eq:SI (match_operand 0 "negt_reg_operand" "") (const_int 0)))]
12071 ;; Store (negated) T bit as all zeros or ones in a reg.
12072 ;; subc Rn,Rn ! Rn = Rn - Rn - T; T = T
12073 ;; not Rn,Rn ! Rn = 0 - Rn
12074 (define_insn_and_split "mov_neg_si_t"
12075 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
12076 (neg:SI (match_operand 1 "treg_set_expr")))]
12079 gcc_assert (t_reg_operand (operands[1], VOIDmode));
12080 return "subc %0,%0";
12082 "&& can_create_pseudo_p () && !t_reg_operand (operands[1], VOIDmode)"
12085 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
12086 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
12088 if (ti.remove_trailing_nott ())
12089 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
12093 [(set_attr "type" "arith")])
12095 ;; The *movtt pattern eliminates redundant T bit to T bit moves / tests.
12096 (define_insn_and_split "*movtt"
12097 [(set (reg:SI T_REG)
12098 (eq:SI (match_operand 0 "t_reg_operand" "") (const_int 1)))]
12104 ;; Invert the T bit.
12105 ;; On SH2A we can use the nott insn. On anything else this must be done with
12106 ;; multiple insns like:
12109 ;; This requires an additional pseudo. The SH specific sh_treg_combine RTL
12110 ;; pass will look for this insn. Disallow using it if pseudos can't be
12112 ;; Don't split the nott inside the splitting of a treg_set_expr, or else
12113 ;; surrounding insns might not see and recombine it. Defer the splitting
12114 ;; of the nott until after the whole insn containing the treg_set_expr
12116 (define_insn_and_split "nott"
12117 [(set (reg:SI T_REG)
12118 (xor:SI (match_operand:SI 0 "t_reg_operand") (const_int 1)))]
12119 "TARGET_SH2A || (TARGET_SH1 && can_create_pseudo_p ())"
12121 gcc_assert (TARGET_SH2A);
12124 "!TARGET_SH2A && can_create_pseudo_p () && !sh_in_recog_treg_set_expr ()"
12125 [(set (match_dup 0) (reg:SI T_REG))
12126 (set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
12128 operands[0] = gen_reg_rtx (SImode);
12131 ;; Store T bit as MSB in a reg.
12132 ;; T = 0: 0x00000000 -> reg
12133 ;; T = 1: 0x80000000 -> reg
12134 (define_insn_and_split "*movt_msb"
12135 [(set (match_operand:SI 0 "arith_reg_dest")
12136 (mult:SI (match_operand:SI 1 "t_reg_operand")
12137 (const_int -2147483648))) ;; 0xffffffff80000000
12138 (clobber (reg:SI T_REG))]
12142 [(set (match_dup 0) (ashift:SI (reg:SI T_REG) (const_int 31)))])
12144 ;; Store inverted T bit as MSB in a reg.
12145 ;; T = 0: 0x80000000 -> reg
12146 ;; T = 1: 0x00000000 -> reg
12147 ;; On SH2A we can get away without clobbering the T_REG using the movrt insn.
12148 ;; On non SH2A we resort to the following sequence:
12152 ;; The T bit value will be modified during the sequence, but the rotcr insn
12153 ;; will restore its original value.
12154 (define_insn_and_split "*negt_msb"
12155 [(set (match_operand:SI 0 "arith_reg_dest")
12156 (match_operand:SI 1 "negt_reg_shl31_operand"))]
12159 "&& can_create_pseudo_p ()"
12162 rtx tmp = gen_reg_rtx (SImode);
12166 emit_insn (gen_movrt (tmp, get_t_reg_rtx ()));
12167 emit_insn (gen_rotrsi3 (operands[0], tmp, const1_rtx));
12171 emit_move_insn (tmp, get_t_reg_rtx ());
12172 emit_insn (gen_cmpeqsi_t (tmp, const0_rtx));
12173 emit_insn (gen_rotcr (operands[0], tmp, get_t_reg_rtx ()));
12178 ;; The *cset_zero patterns convert optimizations such as
12179 ;; "if (test) x = 0;"
12181 ;; "x &= -(test == 0);"
12182 ;; back to conditional branch sequences if zero-displacement branches
12184 ;; FIXME: These patterns can be removed when conditional execution patterns
12185 ;; are implemented, since ifcvt will not perform these optimizations if
12186 ;; conditional execution is supported.
12187 (define_insn "*cset_zero"
12188 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
12189 (and:SI (plus:SI (match_operand:SI 1 "t_reg_operand")
12191 (match_operand:SI 2 "arith_reg_operand" "0")))]
12192 "TARGET_SH1 && TARGET_ZDCBRANCH"
12194 return "bf 0f" "\n"
12198 [(set_attr "type" "arith") ;; poor approximation
12199 (set_attr "length" "4")])
12201 (define_insn "*cset_zero"
12202 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
12203 (if_then_else:SI (match_operand:SI 1 "cbranch_treg_value")
12204 (match_operand:SI 2 "arith_reg_operand" "0")
12206 "TARGET_SH1 && TARGET_ZDCBRANCH"
12208 int tval = sh_eval_treg_value (operands[1]);
12210 return "bt 0f" "\n"
12213 else if (tval == false)
12214 return "bf 0f" "\n"
12218 gcc_unreachable ();
12220 [(set_attr "type" "arith") ;; poor approximation
12221 (set_attr "length" "4")])
12223 (define_expand "cstoresf4"
12224 [(set (match_operand:SI 0 "register_operand" "=r")
12225 (match_operator:SI 1 "sh_float_comparison_operator"
12226 [(match_operand:SF 2 "arith_operand" "")
12227 (match_operand:SF 3 "arith_operand" "")]))]
12228 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12230 if (TARGET_SHMEDIA)
12232 emit_insn (gen_cstore4_media (operands[0], operands[1],
12233 operands[2], operands[3]));
12237 if (! currently_expanding_to_rtl)
12240 sh_emit_compare_and_set (operands, SFmode);
12244 (define_expand "cstoredf4"
12245 [(set (match_operand:SI 0 "register_operand" "=r")
12246 (match_operator:SI 1 "sh_float_comparison_operator"
12247 [(match_operand:DF 2 "arith_operand" "")
12248 (match_operand:DF 3 "arith_operand" "")]))]
12249 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12251 if (TARGET_SHMEDIA)
12253 emit_insn (gen_cstore4_media (operands[0], operands[1],
12254 operands[2], operands[3]));
12258 if (! currently_expanding_to_rtl)
12261 sh_emit_compare_and_set (operands, DFmode);
12265 ;; Sometimes the T bit result of insns is needed in normal registers.
12266 ;; Instead of open coding all the pattern variations, use the treg_set_expr
12267 ;; predicate to match any T bit output insn and split it out after.
12268 ;; This pattern should be below all other related patterns so that it is
12269 ;; considered as a last resort option during matching. This allows
12270 ;; overriding it with special case patterns.
12271 (define_insn_and_split "any_treg_expr_to_reg"
12272 [(set (match_operand:SI 0 "arith_reg_dest")
12273 (match_operand 1 "treg_set_expr"))
12274 (clobber (reg:SI T_REG))]
12275 "TARGET_SH1 && can_create_pseudo_p ()"
12277 "&& !sh_in_recog_treg_set_expr ()"
12281 fprintf (dump_file, "splitting any_treg_expr_to_reg\n");
12283 if (t_reg_operand (operands[1], VOIDmode))
12286 fprintf (dump_file, "t_reg_operand: emitting movt\n");
12287 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
12290 if (negt_reg_operand (operands[1], VOIDmode))
12293 fprintf (dump_file, "negt_reg_operand: emitting movrt\n");
12294 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
12298 /* If the split out insns ended with a nott, emit a movrt sequence,
12299 otherwise a normal movt. */
12300 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
12301 rtx_insn* i = NULL;
12302 if (ti.remove_trailing_nott ())
12304 /* Emit this same insn_and_split again. However, the next time it
12305 is split, it will emit the actual negc/movrt insn. This gives
12306 other surrounding insns the chance to see the trailing movrt. */
12308 fprintf (dump_file,
12309 "any_treg_expr_to_reg: replacing trailing nott with movrt\n");
12310 i = emit_insn (gen_any_treg_expr_to_reg (
12311 operands[0], gen_rtx_XOR (SImode, get_t_reg_rtx (),
12316 i = emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
12318 fprintf (dump_file, "any_treg_expr_to_reg: appending movt\n");
12321 add_reg_note (i, REG_UNUSED, get_t_reg_rtx ());
12325 ;; -------------------------------------------------------------------------
12326 ;; Instructions to cope with inline literal tables
12327 ;; -------------------------------------------------------------------------
12329 ;; 2 byte integer in line
12330 (define_insn "consttable_2"
12331 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
12332 (match_operand 1 "" "")]
12336 if (operands[1] != const0_rtx)
12337 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
12340 [(set_attr "length" "2")
12341 (set_attr "in_delay_slot" "no")])
12343 ;; 4 byte integer in line
12344 (define_insn "consttable_4"
12345 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
12346 (match_operand 1 "" "")]
12350 if (operands[1] != const0_rtx)
12352 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
12353 mark_symbol_refs_as_used (operands[0]);
12357 [(set_attr "length" "4")
12358 (set_attr "in_delay_slot" "no")])
12360 ;; 8 byte integer in line
12361 (define_insn "consttable_8"
12362 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
12363 (match_operand 1 "" "")]
12367 if (operands[1] != const0_rtx)
12368 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
12371 [(set_attr "length" "8")
12372 (set_attr "in_delay_slot" "no")])
12374 ;; 4 byte floating point
12375 (define_insn "consttable_sf"
12376 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
12377 (match_operand 1 "" "")]
12381 if (operands[1] != const0_rtx)
12384 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
12385 assemble_real (d, SFmode, GET_MODE_ALIGNMENT (SFmode));
12389 [(set_attr "length" "4")
12390 (set_attr "in_delay_slot" "no")])
12392 ;; 8 byte floating point
12393 (define_insn "consttable_df"
12394 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
12395 (match_operand 1 "" "")]
12399 if (operands[1] != const0_rtx)
12402 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
12403 assemble_real (d, DFmode, GET_MODE_ALIGNMENT (DFmode));
12407 [(set_attr "length" "8")
12408 (set_attr "in_delay_slot" "no")])
12410 ;; Alignment is needed for some constant tables; it may also be added for
12411 ;; Instructions at the start of loops, or after unconditional branches.
12412 ;; ??? We would get more accurate lengths if we did instruction
12413 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
12414 ;; here is too conservative.
12416 ;; align to a two byte boundary
12417 (define_expand "align_2"
12418 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
12422 ;; Align to a four byte boundary.
12423 ;; align_4 and align_log are instructions for the starts of loops, or
12424 ;; after unconditional branches, which may take up extra room.
12425 (define_expand "align_4"
12426 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
12430 ;; Align to a cache line boundary.
12431 (define_insn "align_log"
12432 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
12435 [(set_attr "length" "0")
12436 (set_attr "in_delay_slot" "no")])
12438 ;; Emitted at the end of the literal table, used to emit the
12439 ;; 32bit branch labels if needed.
12440 (define_insn "consttable_end"
12441 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
12444 return output_jump_label_table ();
12446 [(set_attr "in_delay_slot" "no")])
12448 ;; Emitted at the end of the window in the literal table.
12449 (define_insn "consttable_window_end"
12450 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
12453 [(set_attr "length" "0")
12454 (set_attr "in_delay_slot" "no")])
12456 ;; -------------------------------------------------------------------------
12457 ;; Minimum / maximum operations.
12458 ;; -------------------------------------------------------------------------
12460 ;; The SH2A clips.b and clips.w insns do a signed min-max function. If smin
12461 ;; and smax standard name patterns are defined, they will be used during
12462 ;; initial expansion and combine will then be able to form the actual min-max
12464 ;; The clips.b and clips.w set the SR.CS bit if the value in the register is
12465 ;; clipped, but there is currently no way of making use of this information.
12466 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
12467 (define_expand "<code>si3"
12468 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
12469 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
12470 (match_operand 2 "const_int_operand")))
12471 (clobber (reg:SI T_REG))])]
12474 /* Force the comparison value into a register, because greater-than
12475 comparisons can work only on registers. Combine will be able to pick up
12476 the constant value from the REG_EQUAL note when trying to form a min-max
12478 operands[2] = force_reg (SImode, operands[2]);
12482 ;; smax (smin (...))
12484 ;; smin (smax (...))
12485 (define_insn_and_split "*clips"
12486 [(set (match_operand:SI 0 "arith_reg_dest")
12487 (smax:SI (smin:SI (match_operand:SI 1 "arith_reg_operand")
12488 (match_operand 2 "clips_max_const_int"))
12489 (match_operand 3 "clips_min_const_int")))]
12493 [(set (match_dup 0)
12494 (smin:SI (smax:SI (match_dup 1) (match_dup 3)) (match_dup 2)))])
12496 (define_insn "*clips"
12497 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
12498 (smin:SI (smax:SI (match_operand:SI 1 "arith_reg_operand" "0")
12499 (match_operand 2 "clips_min_const_int"))
12500 (match_operand 3 "clips_max_const_int")))]
12503 if (INTVAL (operands[3]) == 127)
12504 return "clips.b %0";
12505 else if (INTVAL (operands[3]) == 32767)
12506 return "clips.w %0";
12508 gcc_unreachable ();
12510 [(set_attr "type" "arith")])
12512 ;; If the expanded smin or smax patterns were not combined, split them into
12513 ;; a compare and branch sequence, because there are no real smin or smax
12515 (define_insn_and_split "*<code>si3"
12516 [(set (match_operand:SI 0 "arith_reg_dest")
12517 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
12518 (match_operand:SI 2 "arith_reg_or_0_or_1_operand")))
12519 (clobber (reg:SI T_REG))]
12520 "TARGET_SH2A && can_create_pseudo_p ()"
12525 rtx skip_label = gen_label_rtx ();
12526 emit_move_insn (operands[0], operands[1]);
12528 rtx cmp_val = operands[2];
12529 if (satisfies_constraint_M (cmp_val))
12530 cmp_val = const0_rtx;
12532 emit_insn (gen_cmpgtsi_t (operands[0], cmp_val));
12533 emit_jump_insn (<CODE> == SMIN
12534 ? gen_branch_false (skip_label)
12535 : gen_branch_true (skip_label));
12537 emit_label_after (skip_label, emit_move_insn (operands[0], operands[2]));
12541 ;; The SH2A clipu.b and clipu.w insns can be used to implement a min function
12542 ;; with a register and a constant.
12543 ;; The clipu.b and clipu.w set the SR.CS bit if the value in the register is
12544 ;; clipped, but there is currently no way of making use of this information.
12545 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
12546 (define_expand "uminsi3"
12547 [(set (match_operand:SI 0 "arith_reg_dest")
12548 (umin:SI (match_operand:SI 1 "arith_reg_operand")
12549 (match_operand 2 "const_int_operand")))]
12552 if (INTVAL (operands[2]) == 1)
12554 emit_insn (gen_clipu_one (operands[0], operands[1]));
12557 else if (! clipu_max_const_int (operands[2], VOIDmode))
12561 (define_insn "*clipu"
12562 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
12563 (umin:SI (match_operand:SI 1 "arith_reg_operand" "0")
12564 (match_operand 2 "clipu_max_const_int")))]
12567 if (INTVAL (operands[2]) == 255)
12568 return "clipu.b %0";
12569 else if (INTVAL (operands[2]) == 65535)
12570 return "clipu.w %0";
12572 gcc_unreachable ();
12574 [(set_attr "type" "arith")])
12576 (define_insn_and_split "clipu_one"
12577 [(set (match_operand:SI 0 "arith_reg_dest")
12578 (umin:SI (match_operand:SI 1 "arith_reg_operand") (const_int 1)))
12579 (clobber (reg:SI T_REG))]
12582 "&& can_create_pseudo_p ()"
12585 emit_insn (gen_cmpeqsi_t (operands[1], const0_rtx));
12586 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
12590 ;; -------------------------------------------------------------------------
12592 ;; -------------------------------------------------------------------------
12594 ;; String/block move insn.
12596 (define_expand "movmemsi"
12597 [(parallel [(set (mem:BLK (match_operand:BLK 0))
12598 (mem:BLK (match_operand:BLK 1)))
12599 (use (match_operand:SI 2 "nonmemory_operand"))
12600 (use (match_operand:SI 3 "immediate_operand"))
12601 (clobber (reg:SI PR_REG))
12602 (clobber (reg:SI R4_REG))
12603 (clobber (reg:SI R5_REG))
12604 (clobber (reg:SI R0_REG))])]
12605 "TARGET_SH1 && ! TARGET_SH5"
12607 if (expand_block_move (operands))
12613 (define_insn "block_move_real"
12614 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12615 (mem:BLK (reg:SI R5_REG)))
12616 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12617 (clobber (reg:SI PR_REG))
12618 (clobber (reg:SI R0_REG))])]
12619 "TARGET_SH1 && ! TARGET_HARD_SH4"
12621 [(set_attr "type" "sfunc")
12622 (set_attr "needs_delay_slot" "yes")])
12624 (define_insn "block_lump_real"
12625 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12626 (mem:BLK (reg:SI R5_REG)))
12627 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12628 (use (reg:SI R6_REG))
12629 (clobber (reg:SI PR_REG))
12630 (clobber (reg:SI T_REG))
12631 (clobber (reg:SI R4_REG))
12632 (clobber (reg:SI R5_REG))
12633 (clobber (reg:SI R6_REG))
12634 (clobber (reg:SI R0_REG))])]
12635 "TARGET_SH1 && ! TARGET_HARD_SH4"
12637 [(set_attr "type" "sfunc")
12638 (set_attr "needs_delay_slot" "yes")])
12640 (define_insn "block_move_real_i4"
12641 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12642 (mem:BLK (reg:SI R5_REG)))
12643 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12644 (clobber (reg:SI PR_REG))
12645 (clobber (reg:SI R0_REG))
12646 (clobber (reg:SI R1_REG))
12647 (clobber (reg:SI R2_REG))])]
12650 [(set_attr "type" "sfunc")
12651 (set_attr "needs_delay_slot" "yes")])
12653 (define_insn "block_lump_real_i4"
12654 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12655 (mem:BLK (reg:SI R5_REG)))
12656 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12657 (use (reg:SI R6_REG))
12658 (clobber (reg:SI PR_REG))
12659 (clobber (reg:SI T_REG))
12660 (clobber (reg:SI R4_REG))
12661 (clobber (reg:SI R5_REG))
12662 (clobber (reg:SI R6_REG))
12663 (clobber (reg:SI R0_REG))
12664 (clobber (reg:SI R1_REG))
12665 (clobber (reg:SI R2_REG))
12666 (clobber (reg:SI R3_REG))])]
12669 [(set_attr "type" "sfunc")
12670 (set_attr "needs_delay_slot" "yes")])
12672 ;; byte compare pattern
12674 ;; !((temp & 0xF000) && (temp & 0x0F00) && (temp & 0x00F0) && (temp & 0x000F))
12675 (define_insn "cmpstr_t"
12676 [(set (reg:SI T_REG)
12681 (xor:SI (match_operand:SI 0 "arith_reg_operand" "r")
12682 (match_operand:SI 1 "arith_reg_operand" "r"))
12683 (const_int 8) (const_int 0))
12684 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
12685 (const_int 8) (const_int 8)))
12686 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
12687 (const_int 8) (const_int 16)))
12688 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
12689 (const_int 8) (const_int 24)))
12693 [(set_attr "type" "mt_group")])
12695 (define_expand "cmpstrsi"
12696 [(set (match_operand:SI 0 "register_operand")
12697 (compare:SI (match_operand:BLK 1 "memory_operand")
12698 (match_operand:BLK 2 "memory_operand")))
12699 (use (match_operand 3 "immediate_operand"))]
12700 "TARGET_SH1 && optimize"
12702 if (! optimize_insn_for_size_p () && sh_expand_cmpstr (operands))
12708 (define_expand "cmpstrnsi"
12709 [(set (match_operand:SI 0 "register_operand")
12710 (compare:SI (match_operand:BLK 1 "memory_operand")
12711 (match_operand:BLK 2 "memory_operand")))
12712 (use (match_operand:SI 3 "immediate_operand"))
12713 (use (match_operand:SI 4 "immediate_operand"))]
12714 "TARGET_SH1 && optimize"
12716 if (! optimize_insn_for_size_p () && sh_expand_cmpnstr (operands))
12722 (define_expand "strlensi"
12723 [(set (match_operand:SI 0 "register_operand")
12724 (unspec:SI [(match_operand:BLK 1 "memory_operand")
12725 (match_operand:SI 2 "immediate_operand")
12726 (match_operand:SI 3 "immediate_operand")]
12727 UNSPEC_BUILTIN_STRLEN))]
12728 "TARGET_SH1 && optimize"
12730 if (! optimize_insn_for_size_p () && sh_expand_strlen (operands))
12736 (define_expand "setmemqi"
12737 [(parallel [(set (match_operand:BLK 0 "memory_operand")
12738 (match_operand 2 "const_int_operand"))
12739 (use (match_operand:QI 1 "const_int_operand"))
12740 (use (match_operand:QI 3 "const_int_operand"))])]
12741 "TARGET_SH1 && optimize"
12743 if (optimize_insn_for_size_p ())
12746 sh_expand_setmem (operands);
12751 ;; -------------------------------------------------------------------------
12752 ;; Floating point instructions.
12753 ;; -------------------------------------------------------------------------
12755 ;; FIXME: For now we disallow any memory operands for fpscr loads/stores,
12756 ;; except for post-inc loads and pre-dec stores for push/pop purposes.
12757 ;; This avoids problems with reload. As a consequence, user initiated fpscr
12758 ;; stores to memory will always be ferried through a general register.
12759 ;; User initiated fpscr loads always have to undergo bit masking to preserve
12760 ;; the current fpu mode settings for the compiler generated code. Thus such
12761 ;; fpscr loads will always have to go through general registers anyways.
12762 (define_insn "lds_fpscr"
12763 [(set (reg:SI FPSCR_REG)
12764 (match_operand:SI 0 "fpscr_movsrc_operand" "r,>"))
12765 (set (reg:SI FPSCR_STAT_REG)
12766 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_STAT))
12767 (set (reg:SI FPSCR_MODES_REG)
12768 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
12773 [(set_attr "type" "gp_fpscr,mem_fpscr")])
12775 ;; A move fpscr -> reg schedules like a move mac -> reg. Thus we use mac_gp
12777 (define_insn "sts_fpscr"
12778 [(set (match_operand:SI 0 "fpscr_movdst_operand" "=r,<")
12779 (reg:SI FPSCR_REG))
12780 (use (reg:SI FPSCR_STAT_REG))
12781 (use (reg:SI FPSCR_MODES_REG))]
12786 [(set_attr "type" "mac_gp,fstore")])
12788 (define_expand "set_fpscr"
12789 [(parallel [(set (reg:SI FPSCR_REG)
12790 (match_operand:SI 0 "general_operand"))
12791 (set (reg:SI FPSCR_STAT_REG)
12792 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))])]
12795 /* We have to mask out the FR, SZ and PR bits. To do that, we need to
12796 get the current FPSCR value first.
12797 (a & ~mask) | (b & mask) = a ^ ((a ^ b) & mask) */
12799 rtx mask = force_reg (SImode, GEN_INT (FPSCR_FR | FPSCR_SZ | FPSCR_PR));
12801 rtx a = force_reg (SImode, operands[0]);
12803 rtx b = gen_reg_rtx (SImode);
12804 emit_insn (gen_sts_fpscr (b));
12806 rtx a_xor_b = gen_reg_rtx (SImode);
12807 emit_insn (gen_xorsi3 (a_xor_b, a, b));
12809 rtx a_xor_b_and_mask = gen_reg_rtx (SImode);
12810 emit_insn (gen_andsi3 (a_xor_b_and_mask, a_xor_b, mask));
12812 rtx r = gen_reg_rtx (SImode);
12813 emit_insn (gen_xorsi3 (r, a_xor_b_and_mask, a));
12814 emit_insn (gen_lds_fpscr (r));
12819 ;; ??? This uses the fp unit, but has no type indicating that.
12820 ;; If we did that, this would either give a bogus latency or introduce
12821 ;; a bogus FIFO constraint.
12822 ;; Since this insn is currently only used for prologues/epilogues,
12823 ;; it is probably best to claim no function unit, which matches the
12824 ;; current setting.
12825 (define_insn "toggle_sz"
12826 [(set (reg:SI FPSCR_REG)
12827 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_SZ)))
12828 (set (reg:SI FPSCR_MODES_REG)
12829 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
12830 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12832 [(set_attr "type" "fpscr_toggle") (set_attr "fp_set" "unknown")])
12834 ;; Toggle FPU precision PR mode.
12836 (define_insn "toggle_pr"
12837 [(set (reg:SI FPSCR_REG)
12838 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_PR)))
12839 (set (reg:SI FPSCR_MODES_REG)
12840 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
12843 [(set_attr "type" "fpscr_toggle")])
12845 (define_expand "addsf3"
12846 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12847 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand")
12848 (match_operand:SF 2 "fp_arith_reg_operand")))]
12849 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12853 emit_insn (gen_addsf3_i (operands[0], operands[1], operands[2]));
12858 (define_insn "*addsf3_media"
12859 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12860 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12861 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12862 "TARGET_SHMEDIA_FPU"
12863 "fadd.s %1, %2, %0"
12864 [(set_attr "type" "fparith_media")])
12866 (define_insn_and_split "unary_sf_op"
12867 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12872 (parallel [(not:BI (match_operand 3 "const_int_operand" "n"))]))
12873 (match_operator:SF 2 "unary_float_operator"
12874 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12875 (parallel [(match_operand 4
12876 "const_int_operand" "n")]))]))
12877 (parallel [(not:BI (match_dup 3)) (match_dup 3)])))]
12878 "TARGET_SHMEDIA_FPU"
12880 "TARGET_SHMEDIA_FPU && reload_completed"
12881 [(set (match_dup 5) (match_dup 6))]
12883 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12884 rtx op1 = gen_rtx_REG (SFmode,
12885 (true_regnum (operands[1])
12886 + (INTVAL (operands[4]) ^ endian)));
12888 operands[7] = gen_rtx_REG (SFmode,
12889 (true_regnum (operands[0])
12890 + (INTVAL (operands[3]) ^ endian)));
12891 operands[6] = gen_rtx_fmt_e (GET_CODE (operands[2]), SFmode, op1);
12893 [(set_attr "type" "fparith_media")])
12895 (define_insn_and_split "binary_sf_op0"
12896 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12898 (match_operator:SF 3 "binary_float_operator"
12899 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12900 (parallel [(const_int 0)]))
12901 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
12902 (parallel [(const_int 0)]))])
12905 (parallel [(const_int 1)]))))]
12906 "TARGET_SHMEDIA_FPU"
12908 "&& reload_completed"
12909 [(set (match_dup 4) (match_dup 5))]
12911 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12912 rtx op1 = gen_rtx_REG (SFmode,
12913 true_regnum (operands[1]) + endian);
12914 rtx op2 = gen_rtx_REG (SFmode,
12915 true_regnum (operands[2]) + endian);
12917 operands[4] = gen_rtx_REG (SFmode,
12918 true_regnum (operands[0]) + endian);
12919 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
12921 [(set_attr "type" "fparith_media")])
12923 (define_insn_and_split "binary_sf_op1"
12924 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12928 (parallel [(const_int 0)]))
12929 (match_operator:SF 3 "binary_float_operator"
12930 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12931 (parallel [(const_int 1)]))
12932 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
12933 (parallel [(const_int 1)]))])))]
12934 "TARGET_SHMEDIA_FPU"
12936 "&& reload_completed"
12937 [(set (match_dup 4) (match_dup 5))]
12939 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12940 rtx op1 = gen_rtx_REG (SFmode, true_regnum (operands[1]) + (1 ^ endian));
12941 rtx op2 = gen_rtx_REG (SFmode, true_regnum (operands[2]) + (1 ^ endian));
12943 operands[4] = gen_rtx_REG (SFmode, true_regnum (operands[0]) + (1 ^ endian));
12944 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
12946 [(set_attr "type" "fparith_media")])
12948 (define_insn "addsf3_i"
12949 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12950 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
12951 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12952 (clobber (reg:SI FPSCR_STAT_REG))
12953 (use (reg:SI FPSCR_MODES_REG))]
12956 [(set_attr "type" "fp")
12957 (set_attr "fp_mode" "single")])
12959 (define_expand "subsf3"
12960 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12961 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
12962 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
12963 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12967 emit_insn (gen_subsf3_i (operands[0], operands[1], operands[2]));
12972 (define_insn "*subsf3_media"
12973 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12974 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12975 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12976 "TARGET_SHMEDIA_FPU"
12977 "fsub.s %1, %2, %0"
12978 [(set_attr "type" "fparith_media")])
12980 (define_insn "subsf3_i"
12981 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12982 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
12983 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12984 (clobber (reg:SI FPSCR_STAT_REG))
12985 (use (reg:SI FPSCR_MODES_REG))]
12988 [(set_attr "type" "fp")
12989 (set_attr "fp_mode" "single")])
12991 (define_expand "mulsf3"
12992 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12993 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
12994 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
12995 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12999 emit_insn (gen_mulsf3_i (operands[0], operands[1], operands[2]));
13004 (define_insn "*mulsf3_media"
13005 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13006 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
13007 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
13008 "TARGET_SHMEDIA_FPU"
13009 "fmul.s %1, %2, %0"
13010 [(set_attr "type" "fparith_media")])
13012 (define_insn "mulsf3_i"
13013 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13014 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
13015 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
13016 (clobber (reg:SI FPSCR_STAT_REG))
13017 (use (reg:SI FPSCR_MODES_REG))]
13020 [(set_attr "type" "fp")
13021 (set_attr "fp_mode" "single")])
13023 ;; FMA (fused multiply-add) patterns
13024 (define_expand "fmasf4"
13025 [(set (match_operand:SF 0 "fp_arith_reg_operand")
13026 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand")
13027 (match_operand:SF 2 "fp_arith_reg_operand")
13028 (match_operand:SF 3 "fp_arith_reg_operand")))]
13029 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
13033 emit_insn (gen_fmasf4_i (operands[0], operands[1], operands[2],
13039 (define_insn "fmasf4_i"
13040 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13041 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "w")
13042 (match_operand:SF 2 "fp_arith_reg_operand" "f")
13043 (match_operand:SF 3 "fp_arith_reg_operand" "0")))
13044 (clobber (reg:SI FPSCR_STAT_REG))
13045 (use (reg:SI FPSCR_MODES_REG))]
13048 [(set_attr "type" "fp")
13049 (set_attr "fp_mode" "single")])
13051 (define_insn "fmasf4_media"
13052 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13053 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
13054 (match_operand:SF 2 "fp_arith_reg_operand" "f")
13055 (match_operand:SF 3 "fp_arith_reg_operand" "0")))]
13056 "TARGET_SHMEDIA_FPU"
13057 "fmac.s %1, %2, %0"
13058 [(set_attr "type" "fparith_media")])
13060 ;; For some cases such as 'a * b + a' the FMA pattern is not generated by
13061 ;; previous transformations. If FMA is generally allowed, let the combine
13062 ;; pass utilize it.
13063 (define_insn_and_split "*fmasf4"
13064 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13065 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
13066 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
13067 (match_operand:SF 3 "arith_reg_operand" "0")))
13068 (clobber (reg:SI FPSCR_STAT_REG))
13069 (use (reg:SI FPSCR_MODES_REG))]
13070 "TARGET_SH2E && flag_fp_contract_mode != FP_CONTRACT_OFF"
13072 "&& can_create_pseudo_p ()"
13073 [(parallel [(set (match_dup 0)
13074 (fma:SF (match_dup 1) (match_dup 2) (match_dup 3)))
13075 (clobber (reg:SI FPSCR_STAT_REG))
13076 (use (reg:SI FPSCR_MODES_REG))])]
13078 /* Change 'b * a + a' into 'a * b + a'.
13079 This is better for register allocation. */
13080 if (REGNO (operands[2]) == REGNO (operands[3]))
13081 std::swap (operands[1], operands[2]);
13083 [(set_attr "type" "fp")
13084 (set_attr "fp_mode" "single")])
13086 (define_insn "*fmasf4_media"
13087 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13088 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
13089 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
13090 (match_operand:SF 3 "fp_arith_reg_operand" "0")))]
13091 "TARGET_SHMEDIA_FPU && flag_fp_contract_mode != FP_CONTRACT_OFF"
13092 "fmac.s %1, %2, %0"
13093 [(set_attr "type" "fparith_media")])
13095 (define_expand "divsf3"
13096 [(set (match_operand:SF 0 "fp_arith_reg_operand")
13097 (div:SF (match_operand:SF 1 "fp_arith_reg_operand")
13098 (match_operand:SF 2 "fp_arith_reg_operand")))]
13099 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
13103 emit_insn (gen_divsf3_i (operands[0], operands[1], operands[2]));
13108 (define_insn "*divsf3_media"
13109 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13110 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
13111 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
13112 "TARGET_SHMEDIA_FPU"
13113 "fdiv.s %1, %2, %0"
13114 [(set_attr "type" "fdiv_media")])
13116 (define_insn "divsf3_i"
13117 [(set (match_operand:SF 0 "fp_arith_reg_dest" "=f")
13118 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
13119 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
13120 (clobber (reg:SI FPSCR_STAT_REG))
13121 (use (reg:SI FPSCR_MODES_REG))]
13124 [(set_attr "type" "fdiv")
13125 (set_attr "fp_mode" "single")])
13127 (define_insn "floatdisf2"
13128 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13129 (float:SF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
13130 "TARGET_SHMEDIA_FPU"
13132 [(set_attr "type" "fpconv_media")])
13134 (define_expand "floatsisf2"
13135 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
13136 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
13137 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
13139 if (!TARGET_SHMEDIA_FPU)
13141 emit_insn (gen_floatsisf2_i4 (operands[0], operands[1]));
13146 (define_insn "*floatsisf2_media"
13147 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13148 (float:SF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
13149 "TARGET_SHMEDIA_FPU"
13151 [(set_attr "type" "fpconv_media")])
13153 (define_insn "floatsisf2_i4"
13154 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13155 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
13156 (clobber (reg:SI FPSCR_STAT_REG))
13157 (use (reg:SI FPSCR_MODES_REG))]
13160 [(set_attr "type" "fp")
13161 (set_attr "fp_mode" "single")])
13163 (define_insn "fix_truncsfdi2"
13164 [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f")
13165 (fix:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
13166 "TARGET_SHMEDIA_FPU"
13168 [(set_attr "type" "fpconv_media")])
13170 (define_expand "fix_truncsfsi2"
13171 [(set (match_operand:SI 0 "fpul_operand" "=y")
13172 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
13173 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
13175 if (!TARGET_SHMEDIA_FPU)
13177 emit_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1]));
13182 (define_insn "*fix_truncsfsi2_media"
13183 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
13184 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
13185 "TARGET_SHMEDIA_FPU"
13187 [(set_attr "type" "fpconv_media")])
13189 (define_insn "fix_truncsfsi2_i4"
13190 [(set (match_operand:SI 0 "fpul_operand" "=y")
13191 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
13192 (clobber (reg:SI FPSCR_STAT_REG))
13193 (use (reg:SI FPSCR_MODES_REG))]
13196 [(set_attr "type" "ftrc_s")
13197 (set_attr "fp_mode" "single")])
13199 (define_insn "cmpgtsf_t"
13200 [(set (reg:SI T_REG)
13201 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
13202 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
13203 (clobber (reg:SI FPSCR_STAT_REG))
13204 (use (reg:SI FPSCR_MODES_REG))]
13205 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
13207 [(set_attr "type" "fp_cmp")
13208 (set_attr "fp_mode" "single")])
13210 (define_insn "cmpeqsf_t"
13211 [(set (reg:SI T_REG)
13212 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
13213 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
13214 (clobber (reg:SI FPSCR_STAT_REG))
13215 (use (reg:SI FPSCR_MODES_REG))]
13216 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
13218 [(set_attr "type" "fp_cmp")
13219 (set_attr "fp_mode" "single")])
13221 (define_insn "ieee_ccmpeqsf_t"
13222 [(set (reg:SI T_REG)
13223 (ior:SI (reg:SI T_REG)
13224 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
13225 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
13226 (clobber (reg:SI FPSCR_STAT_REG))
13227 (use (reg:SI FPSCR_MODES_REG))]
13228 "TARGET_IEEE && TARGET_SH2E"
13230 return output_ieee_ccmpeq (insn, operands);
13232 [(set_attr "length" "4")
13233 (set_attr "fp_mode" "single")])
13235 (define_insn "cmpeqsf_media"
13236 [(set (match_operand:SI 0 "register_operand" "=r")
13237 (eq:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
13238 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
13239 "TARGET_SHMEDIA_FPU"
13240 "fcmpeq.s %1, %2, %0"
13241 [(set_attr "type" "fcmp_media")])
13243 (define_insn "cmpgtsf_media"
13244 [(set (match_operand:SI 0 "register_operand" "=r")
13245 (gt:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
13246 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
13247 "TARGET_SHMEDIA_FPU"
13248 "fcmpgt.s %1, %2, %0"
13249 [(set_attr "type" "fcmp_media")])
13251 (define_insn "cmpgesf_media"
13252 [(set (match_operand:SI 0 "register_operand" "=r")
13253 (ge:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
13254 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
13255 "TARGET_SHMEDIA_FPU"
13256 "fcmpge.s %1, %2, %0"
13257 [(set_attr "type" "fcmp_media")])
13259 (define_insn "cmpunsf_media"
13260 [(set (match_operand:SI 0 "register_operand" "=r")
13261 (unordered:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
13262 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
13263 "TARGET_SHMEDIA_FPU"
13264 "fcmpun.s %1, %2, %0"
13265 [(set_attr "type" "fcmp_media")])
13267 (define_expand "cbranchsf4"
13269 (if_then_else (match_operator 0 "sh_float_comparison_operator"
13270 [(match_operand:SF 1 "arith_operand" "")
13271 (match_operand:SF 2 "arith_operand" "")])
13272 (match_operand 3 "" "")
13274 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
13276 if (TARGET_SHMEDIA)
13277 emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2],
13280 sh_emit_compare_and_branch (operands, SFmode);
13284 (define_expand "negsf2"
13285 [(set (match_operand:SF 0 "fp_arith_reg_operand")
13286 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
13287 "TARGET_SH2E || TARGET_SHMEDIA_FPU")
13289 (define_insn "*negsf2_media"
13290 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13291 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
13292 "TARGET_SHMEDIA_FPU"
13294 [(set_attr "type" "fmove_media")])
13296 (define_insn "*negsf2_i"
13297 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13298 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
13301 [(set_attr "type" "fmove")])
13303 (define_expand "sqrtsf2"
13304 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
13305 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
13306 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
13310 emit_insn (gen_sqrtsf2_i (operands[0], operands[1]));
13315 (define_insn "*sqrtsf2_media"
13316 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13317 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
13318 "TARGET_SHMEDIA_FPU"
13320 [(set_attr "type" "fdiv_media")])
13322 (define_insn "sqrtsf2_i"
13323 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13324 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
13325 (clobber (reg:SI FPSCR_STAT_REG))
13326 (use (reg:SI FPSCR_MODES_REG))]
13329 [(set_attr "type" "fdiv")
13330 (set_attr "fp_mode" "single")])
13332 (define_insn "rsqrtsf2"
13333 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13334 (div:SF (match_operand:SF 1 "immediate_operand" "i")
13335 (sqrt:SF (match_operand:SF 2 "fp_arith_reg_operand" "0"))))
13336 (clobber (reg:SI FPSCR_STAT_REG))
13337 (use (reg:SI FPSCR_MODES_REG))]
13338 "TARGET_FPU_ANY && TARGET_FSRRA
13339 && operands[1] == CONST1_RTX (SFmode)"
13341 [(set_attr "type" "fsrra")
13342 (set_attr "fp_mode" "single")])
13344 ;; When the sincos pattern is defined, the builtin functions sin and cos
13345 ;; will be expanded to the sincos pattern and one of the output values will
13347 (define_expand "sincossf3"
13348 [(set (match_operand:SF 0 "nonimmediate_operand")
13349 (unspec:SF [(match_operand:SF 2 "fp_arith_reg_operand")] UNSPEC_FCOSA))
13350 (set (match_operand:SF 1 "nonimmediate_operand")
13351 (unspec:SF [(match_dup 2)] UNSPEC_FSINA))]
13352 "TARGET_FPU_ANY && TARGET_FSCA"
13354 rtx scaled = gen_reg_rtx (SFmode);
13355 rtx truncated = gen_reg_rtx (SImode);
13356 rtx fsca = gen_reg_rtx (V2SFmode);
13357 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
13359 emit_insn (gen_mulsf3 (scaled, operands[2], scale_reg));
13360 emit_insn (gen_fix_truncsfsi2 (truncated, scaled));
13361 emit_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf ()));
13363 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 4));
13364 emit_move_insn (operands[1], gen_rtx_SUBREG (SFmode, fsca, 0));
13368 (define_insn_and_split "fsca"
13369 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
13371 (unspec:SF [(mult:SF
13372 (float:SF (match_operand:SI 1 "fpul_fsca_operand" "y"))
13373 (match_operand:SF 2 "fsca_scale_factor" "i"))
13375 (unspec:SF [(mult:SF (float:SF (match_dup 1)) (match_dup 2))
13377 (clobber (reg:SI FPSCR_STAT_REG))
13378 (use (reg:SI FPSCR_MODES_REG))]
13379 "TARGET_FPU_ANY && TARGET_FSCA"
13381 "&& !fpul_operand (operands[1], SImode)"
13384 /* If operands[1] is something like (fix:SF (float:SF (reg:SI))) reduce it
13385 to a simple reg, otherwise reload will have trouble reloading the
13386 pseudo into fpul. */
13387 rtx x = XEXP (operands[1], 0);
13388 while (x != NULL_RTX && !fpul_operand (x, SImode))
13390 gcc_assert (GET_CODE (x) == FIX || GET_CODE (x) == FLOAT);
13393 gcc_assert (x != NULL_RTX && fpul_operand (x, SImode));
13394 emit_insn (gen_fsca (operands[0], x, operands[2]));
13397 [(set_attr "type" "fsca")
13398 (set_attr "fp_mode" "single")])
13400 (define_expand "abssf2"
13401 [(set (match_operand:SF 0 "fp_arith_reg_operand")
13402 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
13403 "TARGET_SH2E || TARGET_SHMEDIA_FPU")
13405 (define_insn "*abssf2_media"
13406 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13407 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
13408 "TARGET_SHMEDIA_FPU"
13410 [(set_attr "type" "fmove_media")])
13412 (define_insn "*abssf2_i"
13413 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13414 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
13417 [(set_attr "type" "fmove")])
13419 (define_expand "adddf3"
13420 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13421 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
13422 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
13423 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13425 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13427 emit_insn (gen_adddf3_i (operands[0], operands[1], operands[2]));
13432 (define_insn "*adddf3_media"
13433 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13434 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
13435 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13436 "TARGET_SHMEDIA_FPU"
13437 "fadd.d %1, %2, %0"
13438 [(set_attr "type" "dfparith_media")])
13440 (define_insn "adddf3_i"
13441 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13442 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
13443 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
13444 (clobber (reg:SI FPSCR_STAT_REG))
13445 (use (reg:SI FPSCR_MODES_REG))]
13446 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13448 [(set_attr "type" "dfp_arith")
13449 (set_attr "fp_mode" "double")])
13451 (define_expand "subdf3"
13452 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13453 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
13454 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
13455 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13457 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13459 emit_insn (gen_subdf3_i (operands[0], operands[1], operands[2]));
13464 (define_insn "*subdf3_media"
13465 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13466 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
13467 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13468 "TARGET_SHMEDIA_FPU"
13469 "fsub.d %1, %2, %0"
13470 [(set_attr "type" "dfparith_media")])
13472 (define_insn "subdf3_i"
13473 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13474 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
13475 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
13476 (clobber (reg:SI FPSCR_STAT_REG))
13477 (use (reg:SI FPSCR_MODES_REG))]
13478 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13480 [(set_attr "type" "dfp_arith")
13481 (set_attr "fp_mode" "double")])
13483 (define_expand "muldf3"
13484 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13485 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
13486 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
13487 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13489 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13491 emit_insn (gen_muldf3_i (operands[0], operands[1], operands[2]));
13496 (define_insn "*muldf3_media"
13497 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13498 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
13499 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13500 "TARGET_SHMEDIA_FPU"
13501 "fmul.d %1, %2, %0"
13502 [(set_attr "type" "dfmul_media")])
13504 (define_insn "muldf3_i"
13505 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13506 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
13507 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
13508 (clobber (reg:SI FPSCR_STAT_REG))
13509 (use (reg:SI FPSCR_MODES_REG))]
13510 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13512 [(set_attr "type" "dfp_mul")
13513 (set_attr "fp_mode" "double")])
13515 (define_expand "divdf3"
13516 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13517 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
13518 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
13519 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13521 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13523 emit_insn (gen_divdf3_i (operands[0], operands[1], operands[2]));
13528 (define_insn "*divdf3_media"
13529 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13530 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
13531 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13532 "TARGET_SHMEDIA_FPU"
13533 "fdiv.d %1, %2, %0"
13534 [(set_attr "type" "dfdiv_media")])
13536 (define_insn "divdf3_i"
13537 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13538 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
13539 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
13540 (clobber (reg:SI FPSCR_STAT_REG))
13541 (use (reg:SI FPSCR_MODES_REG))]
13542 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13544 [(set_attr "type" "dfdiv")
13545 (set_attr "fp_mode" "double")])
13547 (define_insn "floatdidf2"
13548 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13549 (float:DF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
13550 "TARGET_SHMEDIA_FPU"
13552 [(set_attr "type" "dfpconv_media")])
13554 (define_expand "floatsidf2"
13555 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13556 (float:DF (match_operand:SI 1 "fpul_operand" "")))]
13557 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13559 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13561 emit_insn (gen_floatsidf2_i (operands[0], operands[1]));
13566 (define_insn "*floatsidf2_media"
13567 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13568 (float:DF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
13569 "TARGET_SHMEDIA_FPU"
13571 [(set_attr "type" "dfpconv_media")])
13573 (define_insn "floatsidf2_i"
13574 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13575 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
13576 (clobber (reg:SI FPSCR_STAT_REG))
13577 (use (reg:SI FPSCR_MODES_REG))]
13578 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13580 [(set_attr "type" "dfp_conv")
13581 (set_attr "fp_mode" "double")])
13583 (define_insn "fix_truncdfdi2"
13584 [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f")
13585 (fix:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13586 "TARGET_SHMEDIA_FPU"
13588 [(set_attr "type" "dfpconv_media")])
13590 (define_expand "fix_truncdfsi2"
13591 [(set (match_operand:SI 0 "fpul_operand" "")
13592 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
13593 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13595 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13597 emit_insn (gen_fix_truncdfsi2_i (operands[0], operands[1]));
13602 (define_insn "*fix_truncdfsi2_media"
13603 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
13604 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13605 "TARGET_SHMEDIA_FPU"
13607 [(set_attr "type" "dfpconv_media")])
13609 (define_insn "fix_truncdfsi2_i"
13610 [(set (match_operand:SI 0 "fpul_operand" "=y")
13611 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13612 (clobber (reg:SI FPSCR_STAT_REG))
13613 (use (reg:SI FPSCR_MODES_REG))]
13614 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13616 [(set_attr "type" "dfp_conv")
13617 (set_attr "dfp_comp" "no")
13618 (set_attr "fp_mode" "double")])
13620 (define_insn "cmpgtdf_t"
13621 [(set (reg:SI T_REG)
13622 (gt:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
13623 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13624 (clobber (reg:SI FPSCR_STAT_REG))
13625 (use (reg:SI FPSCR_MODES_REG))]
13626 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13628 [(set_attr "type" "dfp_cmp")
13629 (set_attr "fp_mode" "double")])
13631 (define_insn "cmpeqdf_t"
13632 [(set (reg:SI T_REG)
13633 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
13634 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13635 (clobber (reg:SI FPSCR_STAT_REG))
13636 (use (reg:SI FPSCR_MODES_REG))]
13637 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13639 [(set_attr "type" "dfp_cmp")
13640 (set_attr "fp_mode" "double")])
13642 (define_insn "*ieee_ccmpeqdf_t"
13643 [(set (reg:SI T_REG)
13644 (ior:SI (reg:SI T_REG)
13645 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
13646 (match_operand:DF 1 "fp_arith_reg_operand" "f"))))
13647 (clobber (reg:SI FPSCR_STAT_REG))
13648 (use (reg:SI FPSCR_MODES_REG))]
13649 "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13651 return output_ieee_ccmpeq (insn, operands);
13653 [(set_attr "length" "4")
13654 (set_attr "fp_mode" "double")])
13656 (define_insn "cmpeqdf_media"
13657 [(set (match_operand:SI 0 "register_operand" "=r")
13658 (eq:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13659 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13660 "TARGET_SHMEDIA_FPU"
13661 "fcmpeq.d %1,%2,%0"
13662 [(set_attr "type" "fcmp_media")])
13664 (define_insn "cmpgtdf_media"
13665 [(set (match_operand:SI 0 "register_operand" "=r")
13666 (gt:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13667 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13668 "TARGET_SHMEDIA_FPU"
13669 "fcmpgt.d %1,%2,%0"
13670 [(set_attr "type" "fcmp_media")])
13672 (define_insn "cmpgedf_media"
13673 [(set (match_operand:SI 0 "register_operand" "=r")
13674 (ge:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13675 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13676 "TARGET_SHMEDIA_FPU"
13677 "fcmpge.d %1,%2,%0"
13678 [(set_attr "type" "fcmp_media")])
13680 (define_insn "cmpundf_media"
13681 [(set (match_operand:SI 0 "register_operand" "=r")
13682 (unordered:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13683 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13684 "TARGET_SHMEDIA_FPU"
13685 "fcmpun.d %1,%2,%0"
13686 [(set_attr "type" "fcmp_media")])
13688 (define_expand "cbranchdf4"
13690 (if_then_else (match_operator 0 "sh_float_comparison_operator"
13691 [(match_operand:DF 1 "arith_operand" "")
13692 (match_operand:DF 2 "arith_operand" "")])
13693 (match_operand 3 "" "")
13695 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13697 if (TARGET_SHMEDIA)
13698 emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2],
13701 sh_emit_compare_and_branch (operands, DFmode);
13705 (define_expand "negdf2"
13706 [(set (match_operand:DF 0 "fp_arith_reg_operand")
13707 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
13708 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU")
13710 (define_insn "*negdf2_media"
13711 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13712 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13713 "TARGET_SHMEDIA_FPU"
13715 [(set_attr "type" "fmove_media")])
13717 (define_insn "*negdf2_i"
13718 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13719 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
13720 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13722 [(set_attr "type" "fmove")])
13724 (define_expand "sqrtdf2"
13725 [(set (match_operand:DF 0 "fp_arith_reg_operand")
13726 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
13727 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13729 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13731 emit_insn (gen_sqrtdf2_i (operands[0], operands[1]));
13736 (define_insn "*sqrtdf2_media"
13737 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13738 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13739 "TARGET_SHMEDIA_FPU"
13741 [(set_attr "type" "dfdiv_media")])
13743 (define_insn "sqrtdf2_i"
13744 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13745 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
13746 (clobber (reg:SI FPSCR_STAT_REG))
13747 (use (reg:SI FPSCR_MODES_REG))]
13748 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13750 [(set_attr "type" "dfdiv")
13751 (set_attr "fp_mode" "double")])
13753 (define_expand "absdf2"
13754 [(set (match_operand:DF 0 "fp_arith_reg_operand")
13755 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
13756 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU")
13758 (define_insn "*absdf2_media"
13759 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13760 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13761 "TARGET_SHMEDIA_FPU"
13763 [(set_attr "type" "fmove_media")])
13765 (define_insn "*absdf2_i"
13766 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13767 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
13768 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13770 [(set_attr "type" "fmove")])
13772 (define_expand "extendsfdf2"
13773 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13774 (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
13775 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13777 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13779 emit_insn (gen_extendsfdf2_i4 (operands[0], operands[1]));
13784 (define_insn "*extendsfdf2_media"
13785 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13786 (float_extend:DF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
13787 "TARGET_SHMEDIA_FPU"
13789 [(set_attr "type" "dfpconv_media")])
13791 (define_insn "extendsfdf2_i4"
13792 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13793 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
13794 (clobber (reg:SI FPSCR_STAT_REG))
13795 (use (reg:SI FPSCR_MODES_REG))]
13796 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13798 [(set_attr "type" "fp")
13799 (set_attr "fp_mode" "double")])
13801 (define_expand "truncdfsf2"
13802 [(set (match_operand:SF 0 "fpul_operand" "")
13803 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
13804 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13806 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13808 emit_insn (gen_truncdfsf2_i4 (operands[0], operands[1]));
13813 (define_insn "*truncdfsf2_media"
13814 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13815 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13816 "TARGET_SHMEDIA_FPU"
13818 [(set_attr "type" "dfpconv_media")])
13820 (define_insn "truncdfsf2_i4"
13821 [(set (match_operand:SF 0 "fpul_operand" "=y")
13822 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13823 (clobber (reg:SI FPSCR_STAT_REG))
13824 (use (reg:SI FPSCR_MODES_REG))]
13825 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13827 [(set_attr "type" "fp")
13828 (set_attr "fp_mode" "double")])
13830 ;; -------------------------------------------------------------------------
13831 ;; Bit field extract patterns.
13832 ;; -------------------------------------------------------------------------
13834 ;; These give better code for packed bitfields, because they allow
13835 ;; auto-increment addresses to be generated.
13837 (define_expand "insv"
13838 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
13839 (match_operand:SI 1 "immediate_operand" "")
13840 (match_operand:SI 2 "immediate_operand" ""))
13841 (match_operand:SI 3 "general_operand" ""))]
13842 "TARGET_SH1 && TARGET_BIG_ENDIAN"
13844 rtx addr_target, orig_address, shift_reg, qi_val;
13845 HOST_WIDE_INT bitsize, size, v = 0;
13846 rtx x = operands[3];
13848 if (TARGET_SH2A && TARGET_BITOPS
13849 && (satisfies_constraint_Sbw (operands[0])
13850 || satisfies_constraint_Sbv (operands[0]))
13851 && satisfies_constraint_M (operands[1])
13852 && satisfies_constraint_K03 (operands[2]))
13854 if (satisfies_constraint_N (operands[3]))
13856 emit_insn (gen_bclr_m2a (operands[0], operands[2]));
13859 else if (satisfies_constraint_M (operands[3]))
13861 emit_insn (gen_bset_m2a (operands[0], operands[2]));
13864 else if ((REG_P (operands[3]) && REGNO (operands[3]) == T_REG)
13865 && satisfies_constraint_M (operands[1]))
13867 emit_insn (gen_bst_m2a (operands[0], operands[2]));
13870 else if (REG_P (operands[3])
13871 && satisfies_constraint_M (operands[1]))
13873 emit_insn (gen_bldsi_reg (operands[3], const0_rtx));
13874 emit_insn (gen_bst_m2a (operands[0], operands[2]));
13878 /* ??? expmed doesn't care for non-register predicates. */
13879 if (! memory_operand (operands[0], VOIDmode)
13880 || ! immediate_operand (operands[1], VOIDmode)
13881 || ! immediate_operand (operands[2], VOIDmode)
13882 || ! general_operand (x, VOIDmode))
13884 /* If this isn't a 16 / 24 / 32 bit field, or if
13885 it doesn't start on a byte boundary, then fail. */
13886 bitsize = INTVAL (operands[1]);
13887 if (bitsize < 16 || bitsize > 32 || bitsize % 8 != 0
13888 || (INTVAL (operands[2]) % 8) != 0)
13891 size = bitsize / 8;
13892 orig_address = XEXP (operands[0], 0);
13893 shift_reg = gen_reg_rtx (SImode);
13894 if (CONST_INT_P (x))
13897 qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode)));
13901 emit_insn (gen_movsi (shift_reg, operands[3]));
13902 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
13904 addr_target = copy_addr_to_reg (plus_constant (Pmode,
13905 orig_address, size - 1));
13907 operands[0] = replace_equiv_address (operands[0], addr_target);
13908 emit_insn (gen_movqi (operands[0], qi_val));
13912 if (CONST_INT_P (x))
13914 = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode)));
13917 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
13918 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
13920 emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx));
13921 emit_insn (gen_movqi (operands[0], qi_val));
13927 (define_insn "movua"
13928 [(set (match_operand:SI 0 "register_operand" "=z")
13929 (unspec:SI [(match_operand:BLK 1 "unaligned_load_operand" "Sua>")]
13933 [(set_attr "type" "movua")])
13935 ;; We shouldn't need this, but cse replaces increments with references
13936 ;; to other regs before flow has a chance to create post_inc
13937 ;; addressing modes, and only postreload's cse_move2add brings the
13938 ;; increments back to a usable form.
13940 [(set (match_operand:SI 0 "register_operand" "")
13941 (sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" ""))
13942 (const_int 32) (const_int 0)))
13943 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
13944 "TARGET_SH4A && REGNO (operands[0]) != REGNO (operands[1])"
13945 [(set (match_operand:SI 0 "register_operand" "")
13946 (sign_extract:SI (mem:SI (post_inc:SI
13947 (match_operand:SI 1 "register_operand" "")))
13948 (const_int 32) (const_int 0)))]
13951 (define_expand "extv"
13952 [(set (match_operand:SI 0 "register_operand" "")
13953 (sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
13954 (match_operand 2 "const_int_operand" "")
13955 (match_operand 3 "const_int_operand" "")))]
13956 "TARGET_SH4A || TARGET_SH2A"
13958 if (TARGET_SH2A && TARGET_BITOPS
13959 && (satisfies_constraint_Sbw (operands[1])
13960 || satisfies_constraint_Sbv (operands[1]))
13961 && satisfies_constraint_M (operands[2])
13962 && satisfies_constraint_K03 (operands[3]))
13964 emit_insn (gen_bldsign_m2a (operands[1], operands[3]));
13965 if (REGNO (operands[0]) != T_REG)
13966 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
13970 && INTVAL (operands[2]) == 32
13971 && INTVAL (operands[3]) == 0
13972 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
13974 rtx src = adjust_address (operands[1], BLKmode, 0);
13975 set_mem_size (src, 4);
13976 emit_insn (gen_movua (operands[0], src));
13983 (define_expand "extzv"
13984 [(set (match_operand:SI 0 "register_operand" "")
13985 (zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
13986 (match_operand 2 "const_int_operand" "")
13987 (match_operand 3 "const_int_operand" "")))]
13988 "TARGET_SH4A || TARGET_SH2A"
13990 if (TARGET_SH2A && TARGET_BITOPS
13991 && (satisfies_constraint_Sbw (operands[1])
13992 || satisfies_constraint_Sbv (operands[1]))
13993 && satisfies_constraint_M (operands[2])
13994 && satisfies_constraint_K03 (operands[3]))
13996 emit_insn (gen_bld_m2a (operands[1], operands[3]));
13997 if (REGNO (operands[0]) != T_REG)
13998 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
14002 && INTVAL (operands[2]) == 32
14003 && INTVAL (operands[3]) == 0
14004 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
14006 rtx src = adjust_address (operands[1], BLKmode, 0);
14007 set_mem_size (src, 4);
14008 emit_insn (gen_movua (operands[0], src));
14015 ;; -------------------------------------------------------------------------
14016 ;; Extract negated single bit and zero extend it.
14017 ;; Generally we don't care about the exact xor const_int value, as long
14018 ;; as it contains the extracted bit. For simplicity, the pattern variations
14019 ;; that convert everything into the primary '*neg_zero_extract_0' pattern use
14020 ;; a xor const_int -1 value.
14022 (define_insn_and_split "*neg_zero_extract_0"
14023 [(set (reg:SI T_REG)
14024 (zero_extract:SI (xor:QIHISI (match_operand:QIHISI 0 "arith_reg_operand")
14025 (match_operand 1 "const_int_operand"))
14027 (match_operand 2 "const_int_operand")))]
14028 "TARGET_SH1 && can_create_pseudo_p ()
14029 && INTVAL (operands[1]) & (1LL << INTVAL (operands[2]))"
14032 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 2))
14035 if (INTVAL (operands[2]) == 31 && <MODE>mode == SImode)
14037 /* Use cmp/pz to extract bit 31 into the T bit. */
14038 emit_insn (gen_cmpgesi_t (operands[0], const0_rtx));
14042 operands[2] = GEN_INT ((1 << INTVAL (operands[2])));
14043 if (GET_MODE (operands[0]) != SImode)
14044 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
14047 (define_insn_and_split "*neg_zero_extract_1"
14048 [(set (reg:SI T_REG)
14049 (and:SI (not:SI (match_operand:SI 0 "arith_reg_operand"))
14054 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
14055 (const_int 1) (const_int 0)))])
14057 ;; x & (1 << n) == 0: 0x00000000 + 1 = 1
14058 ;; x & (1 << n) != 0: 0xFFFFFFFF + 1 = 0
14059 (define_insn_and_split "*neg_zero_extract_2"
14060 [(set (reg:SI T_REG)
14061 (plus:SI (sign_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
14063 (match_operand 1 "const_int_operand"))
14065 "TARGET_SH1 && can_create_pseudo_p ()"
14068 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
14069 (const_int 1) (match_dup 1)))])
14071 ;; (signed)x >> 31 + 1 = (x >= 0) ^ 1
14072 (define_insn_and_split "*neg_zero_extract_3"
14073 [(set (reg:SI T_REG)
14074 (plus:SI (ashiftrt:SI (match_operand:SI 0 "arith_reg_operand")
14077 "TARGET_SH1 && can_create_pseudo_p ()"
14080 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
14081 (const_int 1) (const_int 31)))])
14083 ;; This is required for some bit patterns of DImode subregs.
14084 ;; It looks like combine gets confused by the DImode right shift and fails
14085 ;; to simplify things.
14086 (define_insn_and_split "*neg_zero_extract_4"
14087 [(set (reg:SI T_REG)
14089 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
14090 (match_operand 1 "const_int_operand"))
14091 (match_operand 2 "const_int_operand"))
14092 (not:SI (ashift:SI (match_operand:SI 3 "arith_reg_operand")
14093 (match_operand 4 "const_int_operand"))))
14095 "TARGET_SH1 && can_create_pseudo_p ()
14096 && INTVAL (operands[4]) > 0
14097 && INTVAL (operands[1]) & (1LL << INTVAL (operands[2]))"
14100 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
14101 (const_int 1) (match_dup 2)))])
14103 (define_insn_and_split "*neg_zero_extract_5"
14104 [(set (reg:SI T_REG)
14105 (and:SI (not:SI (subreg:SI
14106 (lshiftrt:DI (match_operand:DI 0 "arith_reg_operand")
14107 (match_operand 1 "const_int_operand"))
14110 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()
14111 && INTVAL (operands[1]) < 32"
14114 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
14115 (const_int 1) (match_dup 1)))]
14117 operands[0] = gen_lowpart (SImode, operands[0]);
14120 (define_insn_and_split "*neg_zero_extract_6"
14121 [(set (reg:SI T_REG)
14122 (and:SI (not:SI (subreg:SI
14123 (lshiftrt:DI (match_operand:DI 0 "arith_reg_operand")
14124 (match_operand 1 "const_int_operand"))
14127 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()
14128 && INTVAL (operands[1]) < 32"
14131 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
14132 (const_int 1) (match_dup 1)))]
14134 operands[0] = gen_lowpart (SImode, operands[0]);
14137 ;; -------------------------------------------------------------------------
14138 ;; Extract single bit and zero extend it.
14139 ;; All patterns store the result bit in the T bit, although that is not
14140 ;; always possible to do with a single insn and a nott must be appended.
14141 ;; The trailing nott will be optimized away in most cases. E.g. if the
14142 ;; extracted bit is fed into a branch condition, the condition can be
14143 ;; inverted and the nott will be eliminated.
14144 ;; FIXME: In cases where the trailing nott can't be eliminated, try to
14145 ;; convert it into a (not, tst) sequence, which could be better on non-SH2A.
14147 ;; On SH2A the 'bld<mode>_reg' insn will be used if the bit position fits.
14148 (define_insn_and_split "*zero_extract_0"
14149 [(set (reg:SI T_REG)
14150 (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
14152 (match_operand 1 "const_int_operand")))]
14153 "TARGET_SH1 && can_create_pseudo_p ()
14154 && !(TARGET_SH2A && satisfies_constraint_K03 (operands[1]))"
14157 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 1))
14159 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]
14161 if (INTVAL (operands[1]) == 31 && <MODE>mode == SImode)
14163 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
14167 operands[1] = GEN_INT (1 << INTVAL (operands[1]));
14168 if (GET_MODE (operands[0]) != SImode)
14169 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
14172 ;; This is required for some bit patterns of DImode subregs.
14173 ;; It looks like combine gets confused by the DImode right shift and fails
14174 ;; to simplify things.
14175 (define_insn_and_split "*zero_extract_1"
14176 [(set (reg:SI T_REG)
14177 (subreg:SI (zero_extract:DI (match_operand:SI 0 "arith_reg_operand")
14179 (match_operand 1 "const_int_operand"))
14181 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()
14182 && INTVAL (operands[1]) < 32"
14185 [(set (reg:SI T_REG)
14186 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))])
14188 (define_insn_and_split "*zero_extract_2"
14189 [(set (reg:SI T_REG)
14190 (subreg:SI (zero_extract:DI (match_operand:SI 0 "arith_reg_operand")
14192 (match_operand 1 "const_int_operand"))
14194 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()
14195 && INTVAL (operands[1]) < 32"
14198 [(set (reg:SI T_REG)
14199 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))])
14201 ;; -------------------------------------------------------------------------
14202 ;; SH2A instructions for bitwise operations.
14203 ;; FIXME: Convert multiple instruction insns to insn_and_split.
14204 ;; FIXME: Use iterators to fold at least and,xor,or insn variations.
14206 ;; Clear a bit in a memory location.
14207 (define_insn "bclr_m2a"
14208 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
14210 (not:QI (ashift:QI (const_int 1)
14211 (match_operand:QI 1 "const_int_operand" "K03,K03")))
14213 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
14216 bclr.b %1,@(0,%t0)"
14217 [(set_attr "length" "4,4")])
14219 (define_insn "bclrmem_m2a"
14220 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
14221 (and:QI (match_dup 0)
14222 (match_operand:QI 1 "const_int_operand" "Psz,Psz")))]
14223 "TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS"
14226 bclr.b %W1,@(0,%t0)"
14227 [(set_attr "length" "4,4")])
14229 ;; Set a bit in a memory location.
14230 (define_insn "bset_m2a"
14231 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
14233 (ashift:QI (const_int 1)
14234 (match_operand:QI 1 "const_int_operand" "K03,K03"))
14236 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
14239 bset.b %1,@(0,%t0)"
14240 [(set_attr "length" "4,4")])
14242 (define_insn "bsetmem_m2a"
14243 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
14244 (ior:QI (match_dup 0)
14245 (match_operand:QI 1 "const_int_operand" "Pso,Pso")))]
14246 "TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS"
14249 bset.b %V1,@(0,%t0)"
14250 [(set_attr "length" "4,4")])
14252 ;;; Transfer the contents of the T bit to a specified bit of memory.
14253 (define_insn "bst_m2a"
14254 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,m")
14255 (if_then_else (eq (reg:SI T_REG) (const_int 0))
14257 (not:QI (ashift:QI (const_int 1)
14258 (match_operand:QI 1 "const_int_operand" "K03,K03")))
14261 (ashift:QI (const_int 1) (match_dup 1))
14263 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
14267 [(set_attr "length" "4")])
14269 ;; Store a specified bit of memory in the T bit.
14270 (define_insn "bld_m2a"
14271 [(set (reg:SI T_REG)
14273 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,Sbv")
14275 (match_operand 1 "const_int_operand" "K03,K03")))]
14276 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
14280 [(set_attr "length" "4,4")])
14282 ;; Store a specified bit of memory in the T bit.
14283 (define_insn "bldsign_m2a"
14284 [(set (reg:SI T_REG)
14286 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
14288 (match_operand 1 "const_int_operand" "K03,K03")))]
14289 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
14293 [(set_attr "length" "4,4")])
14295 ;; Store a specified bit of the LSB 8 bits of a register in the T bit.
14296 (define_insn "bld<mode>_reg"
14297 [(set (reg:SI T_REG)
14298 (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand" "r")
14300 (match_operand 1 "const_int_operand" "K03")))]
14301 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
14304 ;; Take logical and of a specified bit of memory with the T bit and
14305 ;; store its result in the T bit.
14306 (define_insn "band_m2a"
14307 [(set (reg:SI T_REG)
14308 (and:SI (reg:SI T_REG)
14310 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
14312 (match_operand 1 "const_int_operand" "K03,K03"))))]
14313 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
14316 band.b %1,@(0,%t0)"
14317 [(set_attr "length" "4,4")])
14319 (define_insn "bandreg_m2a"
14320 [(set (match_operand:SI 0 "register_operand" "=r,r")
14321 (and:SI (zero_extract:SI
14322 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
14324 (match_operand 2 "const_int_operand" "K03,K03"))
14325 (match_operand:SI 3 "register_operand" "r,r")))]
14326 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
14328 static const char* alt[] =
14330 "band.b %2,%1" "\n"
14333 "band.b %2,@(0,%t1)" "\n"
14336 return alt[which_alternative];
14338 [(set_attr "length" "6,6")])
14340 ;; Take logical or of a specified bit of memory with the T bit and
14341 ;; store its result in the T bit.
14342 (define_insn "bor_m2a"
14343 [(set (reg:SI T_REG)
14344 (ior:SI (reg:SI T_REG)
14346 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
14348 (match_operand 1 "const_int_operand" "K03,K03"))))]
14349 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
14353 [(set_attr "length" "4,4")])
14355 (define_insn "borreg_m2a"
14356 [(set (match_operand:SI 0 "register_operand" "=r,r")
14357 (ior:SI (zero_extract:SI
14358 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
14360 (match_operand 2 "const_int_operand" "K03,K03"))
14361 (match_operand:SI 3 "register_operand" "=r,r")))]
14362 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
14364 static const char* alt[] =
14369 "bor.b %2,@(0,%t1)" "\n"
14372 return alt[which_alternative];
14374 [(set_attr "length" "6,6")])
14376 ;; Take exclusive or of a specified bit of memory with the T bit and
14377 ;; store its result in the T bit.
14378 (define_insn "bxor_m2a"
14379 [(set (reg:SI T_REG)
14380 (xor:SI (reg:SI T_REG)
14382 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
14384 (match_operand 1 "const_int_operand" "K03,K03"))))]
14385 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
14388 bxor.b %1,@(0,%t0)"
14389 [(set_attr "length" "4,4")])
14391 (define_insn "bxorreg_m2a"
14392 [(set (match_operand:SI 0 "register_operand" "=r,r")
14393 (xor:SI (zero_extract:SI
14394 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
14396 (match_operand 2 "const_int_operand" "K03,K03"))
14397 (match_operand:SI 3 "register_operand" "=r,r")))]
14398 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
14400 static const char* alt[] =
14402 "bxor.b %2,%1" "\n"
14405 "bxor.b %2,@(0,%t1)" "\n"
14408 return alt[which_alternative];
14410 [(set_attr "length" "6,6")])
14412 ;; -------------------------------------------------------------------------
14414 ;; -------------------------------------------------------------------------
14415 ;; This matches cases where the bit in a memory location is set.
14417 [(set (match_operand:SI 0 "register_operand")
14418 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
14420 (ior:SI (match_dup 0)
14421 (match_operand:SI 2 "const_int_operand")))
14423 (match_operand 3 "arith_reg_operand"))]
14424 "TARGET_SH2A && TARGET_BITOPS
14425 && satisfies_constraint_Pso (operands[2])
14426 && REGNO (operands[0]) == REGNO (operands[3])"
14427 [(set (match_dup 1)
14428 (ior:QI (match_dup 1) (match_dup 2)))]
14431 ;; This matches cases where the bit in a memory location is cleared.
14433 [(set (match_operand:SI 0 "register_operand")
14434 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
14436 (and:SI (match_dup 0)
14437 (match_operand:SI 2 "const_int_operand")))
14439 (match_operand 3 "arith_reg_operand"))]
14440 "TARGET_SH2A && TARGET_BITOPS
14441 && satisfies_constraint_Psz (operands[2])
14442 && REGNO (operands[0]) == REGNO (operands[3])"
14443 [(set (match_dup 1)
14444 (and:QI (match_dup 1) (match_dup 2)))]
14447 ;; This matches cases where a stack pointer increment at the start of the
14448 ;; epilogue combines with a stack slot read loading the return value.
14450 [(set (match_operand:SI 0 "arith_reg_operand" "")
14451 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
14452 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
14453 "TARGET_SH1 && REGNO (operands[1]) != REGNO (operands[0])"
14456 ;; See the comment on the dt combiner pattern above.
14458 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
14459 (plus:SI (match_dup 0)
14461 (set (reg:SI T_REG)
14462 (eq:SI (match_dup 0) (const_int 0)))]
14466 ;; The following peepholes fold load sequences for which reload was not
14467 ;; able to generate a displacement addressing move insn.
14468 ;; This can happen when reload has to transform a move insn
14469 ;; without displacement into one with displacement. Or when reload can't
14470 ;; fit a displacement into the insn's constraints. In the latter case, the
14471 ;; load destination reg remains at r0, which reload compensates by inserting
14472 ;; another mov insn.
14476 ;; mov.{b,w} @(r0,r15),r0
14479 ;; mov.{b,w} @(54,r15),r3
14482 [(set (match_operand:SI 0 "arith_reg_dest" "")
14483 (match_operand:SI 1 "const_int_operand" ""))
14484 (set (match_operand:SI 2 "arith_reg_dest" "")
14486 (mem:QI (plus:SI (match_dup 0)
14487 (match_operand:SI 3 "arith_reg_operand" "")))))
14488 (set (match_operand:QI 4 "arith_reg_dest" "")
14489 (match_operand:QI 5 "arith_reg_operand" ""))]
14491 && sh_legitimate_index_p (QImode, operands[1], true, true)
14492 && REGNO (operands[2]) == REGNO (operands[5])
14493 && peep2_reg_dead_p (3, operands[5])"
14494 [(set (match_dup 4) (mem:QI (plus:SI (match_dup 3) (match_dup 1))))]
14498 [(set (match_operand:SI 0 "arith_reg_dest" "")
14499 (match_operand:SI 1 "const_int_operand" ""))
14500 (set (match_operand:SI 2 "arith_reg_dest" "")
14502 (mem:HI (plus:SI (match_dup 0)
14503 (match_operand:SI 3 "arith_reg_operand" "")))))
14504 (set (match_operand:HI 4 "arith_reg_dest" "")
14505 (match_operand:HI 5 "arith_reg_operand" ""))]
14507 && sh_legitimate_index_p (HImode, operands[1], true, true)
14508 && REGNO (operands[2]) == REGNO (operands[5])
14509 && peep2_reg_dead_p (3, operands[5])"
14510 [(set (match_dup 4) (mem:HI (plus:SI (match_dup 3) (match_dup 1))))]
14515 ;; mov.{b,w} @(r0,r15),r1
14517 ;; mov.{b,w} @(54,r15),r1
14520 [(set (match_operand:SI 0 "arith_reg_dest" "")
14521 (match_operand:SI 1 "const_int_operand" ""))
14522 (set (match_operand:SI 2 "arith_reg_dest" "")
14524 (mem:QI (plus:SI (match_dup 0)
14525 (match_operand:SI 3 "arith_reg_operand" "")))))]
14527 && sh_legitimate_index_p (QImode, operands[1], true, true)
14528 && (peep2_reg_dead_p (2, operands[0])
14529 || REGNO (operands[0]) == REGNO (operands[2]))"
14530 [(set (match_dup 2)
14531 (sign_extend:SI (mem:QI (plus:SI (match_dup 3) (match_dup 1)))))]
14535 [(set (match_operand:SI 0 "arith_reg_dest" "")
14536 (match_operand:SI 1 "const_int_operand" ""))
14537 (set (match_operand:SI 2 "arith_reg_dest" "")
14539 (mem:HI (plus:SI (match_dup 0)
14540 (match_operand:SI 3 "arith_reg_operand" "")))))]
14542 && sh_legitimate_index_p (HImode, operands[1], true, true)
14543 && (peep2_reg_dead_p (2, operands[0])
14544 || REGNO (operands[0]) == REGNO (operands[2]))"
14545 [(set (match_dup 2)
14546 (sign_extend:SI (mem:HI (plus:SI (match_dup 3) (match_dup 1)))))]
14550 ;; mov.{b,w} @(r0,r15),r0
14553 ;; mov.{b,w} @(r0,r15),r3
14555 ;; This can happen when initially a displacement address is picked, where
14556 ;; the destination reg is fixed to r0, and then the address is transformed
14557 ;; into 'r0 + reg'.
14559 [(set (match_operand:SI 0 "arith_reg_dest" "")
14561 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
14562 (match_operand:SI 2 "arith_reg_operand" "")))))
14563 (set (match_operand:QI 3 "arith_reg_dest" "")
14564 (match_operand:QI 4 "arith_reg_operand" ""))]
14566 && REGNO (operands[0]) == REGNO (operands[4])
14567 && peep2_reg_dead_p (2, operands[0])"
14568 [(set (match_dup 3)
14569 (mem:QI (plus:SI (match_dup 1) (match_dup 2))))]
14573 [(set (match_operand:SI 0 "arith_reg_dest" "")
14575 (mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
14576 (match_operand:SI 2 "arith_reg_operand" "")))))
14577 (set (match_operand:HI 3 "arith_reg_dest" "")
14578 (match_operand:HI 4 "arith_reg_operand" ""))]
14580 && REGNO (operands[0]) == REGNO (operands[4])
14581 && peep2_reg_dead_p (2, operands[0])"
14582 [(set (match_dup 3)
14583 (mem:HI (plus:SI (match_dup 1) (match_dup 2))))]
14587 ;; mov b,c -> extu.bw a,c
14589 [(set (match_operand:SI 0 "arith_reg_dest")
14590 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand")))
14591 (set (match_operand:SI 2 "arith_reg_dest")
14593 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
14594 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))])
14597 ;; extu.bw r1,r1 -> extu.bw r0,r1
14599 [(set (match_operand 0 "arith_reg_dest")
14600 (match_operand 1 "arith_reg_operand"))
14601 (set (match_operand:SI 2 "arith_reg_dest")
14602 (zero_extend:SI (match_operand:QIHI 3 "arith_reg_operand")))]
14604 && REGNO (operands[0]) == REGNO (operands[3])
14605 && (REGNO (operands[0]) == REGNO (operands[2])
14606 || peep2_reg_dead_p (2, operands[0]))"
14607 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))]
14609 operands[1] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
14613 ;; mov b,a -> < nop >
14615 [(set (match_operand 0 "register_operand")
14616 (match_operand 1 "register_operand"))
14617 (set (match_operand 2 "register_operand")
14618 (match_operand 3 "register_operand"))]
14620 && REGNO (operands[0]) == REGNO (operands[3])
14621 && REGNO (operands[1]) == REGNO (operands[2])
14622 && peep2_reg_dead_p (2, operands[3])"
14626 ;; and r4,r1 -> mov r1,r0
14627 ;; mov r1,r0 and #3,r0
14628 (define_code_iterator ANDIORXOR [and ior xor])
14630 [(set (match_operand:SI 0 "register_operand")
14631 (match_operand:SI 1 "const_logical_operand"))
14632 (set (match_operand:SI 2) (ANDIORXOR:SI (match_dup 2) (match_dup 0)))
14633 (set (reg:SI R0_REG) (match_dup 2))]
14635 && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2])"
14636 [(set (reg:SI R0_REG) (match_dup 2))
14637 (set (reg:SI R0_REG) (ANDIORXOR:SI (reg:SI R0_REG) (match_dup 1)))])
14639 ;; ... r2,r0 ... r2,r0
14640 ;; or r1,r0 -> or r0,r1
14643 (define_code_iterator ANDIORXORPLUS [and ior xor plus])
14645 [(set (match_operand:SI 0 "arith_reg_dest")
14646 (ANDIORXORPLUS:SI (match_dup 0) (match_operand:SI 1 "arith_reg_dest")))
14647 (set (match_dup 1) (match_dup 0))]
14648 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
14649 [(set (match_dup 1) (ANDIORXORPLUS:SI (match_dup 1) (match_dup 0)))])
14652 ;; add #-48,r0 -> add #-48,r12
14653 ;; mov.l r0,@(4,r10) mov.l r12,@(4,r10)
14656 [(set (match_operand:SI 0 "arith_reg_dest")
14657 (match_operand:SI 1 "arith_reg_dest"))
14658 (set (match_dup 0) (plus:SI (match_dup 0)
14659 (match_operand:SI 2 "const_int_operand")))
14660 (set (match_operand:SI 3 "general_movdst_operand") (match_dup 0))]
14662 && peep2_reg_dead_p (2, operands[1]) && peep2_reg_dead_p (3, operands[0])"
14665 emit_insn (gen_addsi3 (operands[1], operands[1], operands[2]));
14666 sh_check_add_incdec_notes (emit_move_insn (operands[3], operands[1]));
14669 ;; mov.l @(r0,r9),r1
14670 ;; mov r1,r0 -> mov @(r0,r9),r0
14672 [(set (match_operand:SI 0 "arith_reg_dest")
14673 (match_operand:SI 1 "general_movsrc_operand"))
14674 (set (match_operand:SI 2 "arith_reg_dest")
14676 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
14679 sh_check_add_incdec_notes (emit_move_insn (operands[2], operands[1]));
14683 [(set (match_operand:QIHI 0 "register_operand")
14684 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand"))
14685 (set (match_operand:QIHI 2 "register_operand")
14687 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
14690 sh_check_add_incdec_notes (emit_move_insn (operands[2], operands[1]));
14694 [(set (match_operand:SI 0 "arith_reg_dest")
14695 (sign_extend:SI (match_operand:QIHI 1 "movsrc_no_disp_mem_operand")))
14696 (set (match_operand:SI 2 "arith_reg_dest")
14698 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
14701 sh_check_add_incdec_notes (emit_insn (gen_extend<mode>si2 (operands[2],
14705 ;; mov.w @(18,r1),r0 (r0 = HImode)
14706 ;; mov r0,r1 (r0 = r1 = HImode) mov.w @(18,r1),r0
14707 ;; ... ..,r13 (r13 = SImode) -> ... ..,r13
14708 ;; tst r1,r13 tst r0,r13
14710 [(set (match_operand 0 "arith_reg_dest")
14711 (match_operand 1 "arith_reg_dest"))
14712 (set (match_operand:SI 2 "arith_reg_dest")
14713 (match_operand:SI 3))
14714 (set (reg:SI T_REG)
14715 (eq:SI (and:SI (match_operand:SI 4 "arith_reg_operand")
14716 (match_operand:SI 5 "arith_reg_operand"))
14719 && peep2_reg_dead_p (3, operands[0])
14720 && !reg_overlap_mentioned_p (operands[0], operands[3])
14721 && (REGNO (operands[0]) == REGNO (operands[4])
14722 || REGNO (operands[0]) == REGNO (operands[5]))
14723 && (REGNO (operands[2]) == REGNO (operands[4])
14724 || REGNO (operands[2]) == REGNO (operands[5]))"
14727 if (REGNO (operands[1]) == REGNO (operands[2]))
14728 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));
14730 sh_check_add_incdec_notes (emit_insn (gen_rtx_SET (operands[2],
14732 emit_insn (gen_tstsi_t (operands[2],
14733 gen_rtx_REG (SImode, (REGNO (operands[1])))));
14736 ;; mov.w @(18,r1),r0 (r0 = HImode)
14737 ;; ... ..,r13 (r13 = SImode) mov.w @(18,r1),r0
14738 ;; mov r0,r1 (r0 = r1 = HImode) -> ... ..,r13
14739 ;; tst r1,r13 tst r0,r13
14741 [(set (match_operand:SI 2 "arith_reg_dest")
14742 (match_operand:SI 3))
14743 (set (match_operand 0 "arith_reg_dest")
14744 (match_operand 1 "arith_reg_operand"))
14745 (set (reg:SI T_REG)
14746 (eq:SI (and:SI (match_operand:SI 4 "arith_reg_operand")
14747 (match_operand:SI 5 "arith_reg_operand"))
14750 && peep2_reg_dead_p (3, operands[0])
14751 && !reg_overlap_mentioned_p (operands[0], operands[3])
14752 && (REGNO (operands[0]) == REGNO (operands[4])
14753 || REGNO (operands[0]) == REGNO (operands[5]))
14754 && (REGNO (operands[2]) == REGNO (operands[4])
14755 || REGNO (operands[2]) == REGNO (operands[5]))"
14758 sh_check_add_incdec_notes (emit_insn (gen_rtx_SET (operands[2],
14760 emit_insn (gen_tstsi_t (operands[2],
14761 gen_rtx_REG (SImode, (REGNO (operands[1])))));
14765 [(set (match_operand:SI 0 "register_operand" "=r")
14766 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
14767 (set (mem:SF (match_dup 0))
14768 (match_operand:SF 2 "general_movsrc_operand" ""))]
14769 "TARGET_SH1 && REGNO (operands[0]) == 0
14770 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
14771 || (GET_CODE (operands[2]) == SUBREG
14772 && REGNO (SUBREG_REG (operands[2])) < 16))
14773 && reg_unused_after (operands[0], insn)"
14774 "mov.l %2,@(%0,%1)")
14777 [(set (match_operand:SI 0 "register_operand" "=r")
14778 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
14779 (set (match_operand:SF 2 "general_movdst_operand" "")
14781 (mem:SF (match_dup 0)))]
14782 "TARGET_SH1 && REGNO (operands[0]) == 0
14783 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
14784 || (GET_CODE (operands[2]) == SUBREG
14785 && REGNO (SUBREG_REG (operands[2])) < 16))
14786 && reg_unused_after (operands[0], insn)"
14787 "mov.l @(%0,%1),%2")
14790 [(set (match_operand:SI 0 "register_operand" "=r")
14791 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
14792 (set (mem:SF (match_dup 0))
14793 (match_operand:SF 2 "general_movsrc_operand" ""))]
14794 "TARGET_SH2E && REGNO (operands[0]) == 0
14795 && ((REG_P (operands[2])
14796 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
14797 || (GET_CODE (operands[2]) == SUBREG
14798 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
14799 && reg_unused_after (operands[0], insn)"
14800 "fmov{.s|} %2,@(%0,%1)")
14803 [(set (match_operand:SI 0 "register_operand" "=r")
14804 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
14805 (set (match_operand:SF 2 "general_movdst_operand" "")
14807 (mem:SF (match_dup 0)))]
14808 "TARGET_SH2E && REGNO (operands[0]) == 0
14809 && ((REG_P (operands[2])
14810 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
14811 || (GET_CODE (operands[2]) == SUBREG
14812 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
14813 && reg_unused_after (operands[0], insn)"
14814 "fmov{.s|} @(%0,%1),%2")
14816 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF).
14817 (define_insn "sp_switch_1"
14818 [(set (reg:SI SP_REG) (unspec_volatile [(match_operand:SI 0 "" "")]
14819 UNSPECV_SP_SWITCH_B))]
14822 return "mov.l r0,@-r15" "\n"
14823 " mov.l %0,r0" "\n"
14824 " mov.l @r0,r0" "\n"
14825 " mov.l r15,@-r0" "\n"
14828 [(set_attr "length" "10")])
14830 ;; Switch back to the original stack for interrupt functions with the
14831 ;; sp_switch attribute.
14832 (define_insn "sp_switch_2"
14833 [(unspec_volatile [(const_int 0)]
14834 UNSPECV_SP_SWITCH_E)]
14837 return "mov.l @r15,r15" "\n"
14840 [(set_attr "length" "4")])
14842 ;; -------------------------------------------------------------------------
14843 ;; Integer vector moves
14844 ;; -------------------------------------------------------------------------
14846 (define_expand "movv8qi"
14847 [(set (match_operand:V8QI 0 "general_movdst_operand" "")
14848 (match_operand:V8QI 1 "general_movsrc_operand" ""))]
14851 prepare_move_operands (operands, V8QImode);
14854 (define_insn "movv8qi_i"
14855 [(set (match_operand:V8QI 0 "general_movdst_operand" "=r,r,r,rl,m")
14856 (match_operand:V8QI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14858 && (register_operand (operands[0], V8QImode)
14859 || sh_register_operand (operands[1], V8QImode))"
14866 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14867 (set_attr "length" "4,4,16,4,4")])
14870 [(set (match_operand:V8QI 0 "arith_reg_dest" "")
14871 (subreg:V8QI (const_int 0) 0))]
14873 [(set (match_dup 0)
14874 (const_vector:V8QI [(const_int 0) (const_int 0) (const_int 0)
14875 (const_int 0) (const_int 0) (const_int 0)
14876 (const_int 0) (const_int 0)]))])
14879 [(set (match_operand 0 "arith_reg_dest" "")
14880 (match_operand 1 "sh_rep_vec" ""))]
14881 "TARGET_SHMEDIA && reload_completed
14882 && GET_MODE (operands[0]) == GET_MODE (operands[1])
14883 && sh_vector_mode_supported_p (GET_MODE (operands[0]))
14884 && GET_MODE_SIZE (GET_MODE (operands[0])) == 8
14885 && (XVECEXP (operands[1], 0, 0) != const0_rtx
14886 || XVECEXP (operands[1], 0, 1) != const0_rtx)
14887 && (XVECEXP (operands[1], 0, 0) != constm1_rtx
14888 || XVECEXP (operands[1], 0, 1) != constm1_rtx)"
14889 [(set (match_dup 0) (match_dup 1))
14892 int unit_size = GET_MODE_UNIT_SIZE (GET_MODE (operands[1]));
14893 rtx elt1 = XVECEXP (operands[1], 0, 1);
14896 operands[2] = gen_mshflo_l (operands[0], operands[0], operands[0]);
14900 operands[0] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
14901 operands[2] = gen_mperm_w0 (operands[0], operands[0]);
14903 operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
14904 operands[1] = XVECEXP (operands[1], 0, 0);
14907 if (CONST_INT_P (operands[1]) && CONST_INT_P (elt1))
14909 = GEN_INT (TARGET_LITTLE_ENDIAN
14910 ? (INTVAL (operands[1]) & 0xff) + (INTVAL (elt1) << 8)
14911 : (INTVAL (operands[1]) << 8) + (INTVAL (elt1) & 0xff));
14914 operands[0] = gen_rtx_REG (V2QImode, true_regnum (operands[0]));
14916 = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, operands[1], elt1));
14922 [(set (match_operand 0 "arith_reg_dest" "")
14923 (match_operand 1 "sh_const_vec" ""))]
14924 "TARGET_SHMEDIA && reload_completed
14925 && GET_MODE (operands[0]) == GET_MODE (operands[1])
14926 && sh_vector_mode_supported_p (GET_MODE (operands[0]))"
14927 [(set (match_dup 0) (match_dup 1))]
14929 rtx v = operands[1];
14930 machine_mode new_mode
14931 = mode_for_size (GET_MODE_BITSIZE (GET_MODE (v)), MODE_INT, 0);
14933 operands[0] = gen_rtx_REG (new_mode, true_regnum (operands[0]));
14935 = simplify_subreg (new_mode, operands[1], GET_MODE (operands[1]), 0);
14938 (define_expand "movv2hi"
14939 [(set (match_operand:V2HI 0 "general_movdst_operand" "")
14940 (match_operand:V2HI 1 "general_movsrc_operand" ""))]
14943 prepare_move_operands (operands, V2HImode);
14946 (define_insn "movv2hi_i"
14947 [(set (match_operand:V2HI 0 "general_movdst_operand" "=r,r,r,rl,m")
14948 (match_operand:V2HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14950 && (register_operand (operands[0], V2HImode)
14951 || sh_register_operand (operands[1], V2HImode))"
14958 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14959 (set_attr "length" "4,4,16,4,4")
14960 (set (attr "highpart")
14961 (cond [(match_test "sh_contains_memref_p (insn)")
14962 (const_string "user")]
14963 (const_string "ignore")))])
14965 (define_expand "movv4hi"
14966 [(set (match_operand:V4HI 0 "general_movdst_operand" "")
14967 (match_operand:V4HI 1 "general_movsrc_operand" ""))]
14970 prepare_move_operands (operands, V4HImode);
14973 (define_insn "movv4hi_i"
14974 [(set (match_operand:V4HI 0 "general_movdst_operand" "=r,r,r,rl,m")
14975 (match_operand:V4HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14977 && (register_operand (operands[0], V4HImode)
14978 || sh_register_operand (operands[1], V4HImode))"
14985 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14986 (set_attr "length" "4,4,16,4,4")
14987 (set_attr "highpart" "depend")])
14989 (define_expand "movv2si"
14990 [(set (match_operand:V2SI 0 "general_movdst_operand" "")
14991 (match_operand:V2SI 1 "general_movsrc_operand" ""))]
14994 prepare_move_operands (operands, V2SImode);
14997 (define_insn "movv2si_i"
14998 [(set (match_operand:V2SI 0 "general_movdst_operand" "=r,r,r,rl,m")
14999 (match_operand:V2SI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
15001 && (register_operand (operands[0], V2SImode)
15002 || sh_register_operand (operands[1], V2SImode))"
15009 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
15010 (set_attr "length" "4,4,16,4,4")
15011 (set_attr "highpart" "depend")])
15013 ;; -------------------------------------------------------------------------
15014 ;; Multimedia Intrinsics
15015 ;; -------------------------------------------------------------------------
15017 (define_insn "absv2si2"
15018 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15019 (abs:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")))]
15022 [(set_attr "type" "mcmp_media")
15023 (set_attr "highpart" "depend")])
15025 (define_insn "absv4hi2"
15026 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15027 (abs:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")))]
15030 [(set_attr "type" "mcmp_media")
15031 (set_attr "highpart" "depend")])
15033 (define_insn "addv2si3"
15034 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15035 (plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
15036 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
15038 "madd.l %1, %2, %0"
15039 [(set_attr "type" "arith_media")
15040 (set_attr "highpart" "depend")])
15042 (define_insn "addv4hi3"
15043 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15044 (plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
15045 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
15047 "madd.w %1, %2, %0"
15048 [(set_attr "type" "arith_media")
15049 (set_attr "highpart" "depend")])
15051 (define_insn_and_split "addv2hi3"
15052 [(set (match_operand:V2HI 0 "arith_reg_dest" "=r")
15053 (plus:V2HI (match_operand:V2HI 1 "extend_reg_operand" "%r")
15054 (match_operand:V2HI 2 "extend_reg_operand" "r")))]
15060 rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0);
15061 rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0);
15062 rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0);
15063 rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0);
15064 rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0);
15066 emit_insn (gen_addv4hi3 (v4hi_dst, src0, src1));
15067 emit_insn (gen_truncdisi2 (si_dst, di_dst));
15070 [(set_attr "highpart" "must_split")])
15072 (define_insn "ssaddv2si3"
15073 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15074 (ss_plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
15075 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
15077 "madds.l %1, %2, %0"
15078 [(set_attr "type" "mcmp_media")
15079 (set_attr "highpart" "depend")])
15081 (define_insn "usaddv8qi3"
15082 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
15083 (us_plus:V8QI (match_operand:V8QI 1 "arith_reg_operand" "%r")
15084 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
15086 "madds.ub %1, %2, %0"
15087 [(set_attr "type" "mcmp_media")
15088 (set_attr "highpart" "depend")])
15090 (define_insn "ssaddv4hi3"
15091 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15092 (ss_plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
15093 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
15095 "madds.w %1, %2, %0"
15096 [(set_attr "type" "mcmp_media")
15097 (set_attr "highpart" "depend")])
15099 (define_insn "negcmpeqv8qi"
15100 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
15102 (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
15103 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
15105 "mcmpeq.b %N1, %N2, %0"
15106 [(set_attr "type" "mcmp_media")
15107 (set_attr "highpart" "depend")])
15109 (define_insn "negcmpeqv2si"
15110 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15112 (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
15113 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
15115 "mcmpeq.l %N1, %N2, %0"
15116 [(set_attr "type" "mcmp_media")
15117 (set_attr "highpart" "depend")])
15119 (define_insn "negcmpeqv4hi"
15120 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15122 (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
15123 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
15125 "mcmpeq.w %N1, %N2, %0"
15126 [(set_attr "type" "mcmp_media")
15127 (set_attr "highpart" "depend")])
15129 (define_insn "negcmpgtuv8qi"
15130 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
15131 (neg:V8QI (gtu:V8QI
15132 (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
15133 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
15135 "mcmpgt.ub %N1, %N2, %0"
15136 [(set_attr "type" "mcmp_media")
15137 (set_attr "highpart" "depend")])
15139 (define_insn "negcmpgtv2si"
15140 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15142 (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
15143 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
15145 "mcmpgt.l %N1, %N2, %0"
15146 [(set_attr "type" "mcmp_media")
15147 (set_attr "highpart" "depend")])
15149 (define_insn "negcmpgtv4hi"
15150 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15152 (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
15153 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
15155 "mcmpgt.w %N1, %N2, %0"
15156 [(set_attr "type" "mcmp_media")
15157 (set_attr "highpart" "depend")])
15159 (define_insn "mcmv"
15160 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15161 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15162 (match_operand:DI 2 "arith_reg_operand" "r"))
15163 (and:DI (match_operand:DI 3 "arith_reg_operand" "0")
15164 (not:DI (match_dup 2)))))]
15167 [(set_attr "type" "arith_media")
15168 (set_attr "highpart" "depend")])
15170 (define_insn "mcnvs_lw"
15171 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15173 (ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ"))
15175 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
15177 "mcnvs.lw %N1, %N2, %0"
15178 [(set_attr "type" "mcmp_media")])
15180 (define_insn "mcnvs_wb"
15181 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
15183 (ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
15185 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
15187 "mcnvs.wb %N1, %N2, %0"
15188 [(set_attr "type" "mcmp_media")])
15190 (define_insn "mcnvs_wub"
15191 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
15193 (us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
15195 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
15197 "mcnvs.wub %N1, %N2, %0"
15198 [(set_attr "type" "mcmp_media")])
15200 (define_insn "mextr_rl"
15201 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15202 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15203 (match_operand:HI 3 "mextr_bit_offset" "i"))
15204 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15205 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
15206 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
15208 static char templ[21];
15209 sprintf (templ, "mextr%d %%N1, %%N2, %%0",
15210 (int) INTVAL (operands[3]) >> 3);
15213 [(set_attr "type" "arith_media")])
15215 (define_insn "*mextr_lr"
15216 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15217 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15218 (match_operand:HI 3 "mextr_bit_offset" "i"))
15219 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15220 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
15221 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
15223 static char templ[21];
15224 sprintf (templ, "mextr%d %%N2, %%N1, %%0",
15225 (int) INTVAL (operands[4]) >> 3);
15228 [(set_attr "type" "arith_media")])
15230 ; mextrN can be modelled with vec_select / vec_concat, but the selection
15231 ; vector then varies depending on endianness.
15232 (define_expand "mextr1"
15233 [(match_operand:DI 0 "arith_reg_dest" "")
15234 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15235 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
15238 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
15239 GEN_INT (1 * 8), GEN_INT (7 * 8)));
15243 (define_expand "mextr2"
15244 [(match_operand:DI 0 "arith_reg_dest" "")
15245 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15246 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
15249 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
15250 GEN_INT (2 * 8), GEN_INT (6 * 8)));
15254 (define_expand "mextr3"
15255 [(match_operand:DI 0 "arith_reg_dest" "")
15256 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15257 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
15260 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
15261 GEN_INT (3 * 8), GEN_INT (5 * 8)));
15265 (define_expand "mextr4"
15266 [(match_operand:DI 0 "arith_reg_dest" "")
15267 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15268 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
15271 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
15272 GEN_INT (4 * 8), GEN_INT (4 * 8)));
15276 (define_expand "mextr5"
15277 [(match_operand:DI 0 "arith_reg_dest" "")
15278 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15279 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
15282 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
15283 GEN_INT (5 * 8), GEN_INT (3 * 8)));
15287 (define_expand "mextr6"
15288 [(match_operand:DI 0 "arith_reg_dest" "")
15289 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15290 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
15293 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
15294 GEN_INT (6 * 8), GEN_INT (2 * 8)));
15298 (define_expand "mextr7"
15299 [(match_operand:DI 0 "arith_reg_dest" "")
15300 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15301 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
15304 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
15305 GEN_INT (7 * 8), GEN_INT (1 * 8)));
15309 (define_expand "mmacfx_wl"
15310 [(match_operand:V2SI 0 "arith_reg_dest" "")
15311 (match_operand:V2HI 1 "extend_reg_operand" "")
15312 (match_operand:V2HI 2 "extend_reg_operand" "")
15313 (match_operand:V2SI 3 "arith_reg_operand" "")]
15316 emit_insn (gen_mmacfx_wl_i (operands[0], operands[3],
15317 operands[1], operands[2]));
15321 ;; This could be highpart ignore if it only had inputs 2 or 3, but input 1
15323 (define_insn "mmacfx_wl_i"
15324 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15326 (match_operand:V2SI 1 "arith_reg_operand" "0")
15331 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
15332 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
15335 "mmacfx.wl %2, %3, %0"
15336 [(set_attr "type" "mac_media")
15337 (set_attr "highpart" "depend")])
15339 (define_expand "mmacnfx_wl"
15340 [(match_operand:V2SI 0 "arith_reg_dest" "")
15341 (match_operand:V2HI 1 "extend_reg_operand" "")
15342 (match_operand:V2HI 2 "extend_reg_operand" "")
15343 (match_operand:V2SI 3 "arith_reg_operand" "")]
15346 emit_insn (gen_mmacnfx_wl_i (operands[0], operands[3],
15347 operands[1], operands[2]));
15351 (define_insn "mmacnfx_wl_i"
15352 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15354 (match_operand:V2SI 1 "arith_reg_operand" "0")
15359 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
15360 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
15363 "mmacnfx.wl %2, %3, %0"
15364 [(set_attr "type" "mac_media")
15365 (set_attr "highpart" "depend")])
15367 (define_insn "mulv2si3"
15368 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15369 (mult:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
15370 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
15372 "mmul.l %1, %2, %0"
15373 [(set_attr "type" "d2mpy_media")
15374 (set_attr "highpart" "depend")])
15376 (define_insn "mulv4hi3"
15377 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15378 (mult:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
15379 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
15381 "mmul.w %1, %2, %0"
15382 [(set_attr "type" "dmpy_media")
15383 (set_attr "highpart" "depend")])
15385 (define_insn "mmulfx_l"
15386 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15390 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
15391 (sign_extend:V2DI (match_operand:V2SI 2 "arith_reg_operand" "r")))
15394 "mmulfx.l %1, %2, %0"
15395 [(set_attr "type" "d2mpy_media")
15396 (set_attr "highpart" "depend")])
15398 (define_insn "mmulfx_w"
15399 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15403 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
15404 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
15407 "mmulfx.w %1, %2, %0"
15408 [(set_attr "type" "dmpy_media")
15409 (set_attr "highpart" "depend")])
15411 (define_insn "mmulfxrp_w"
15412 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15417 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
15418 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
15422 "mmulfxrp.w %1, %2, %0"
15423 [(set_attr "type" "dmpy_media")
15424 (set_attr "highpart" "depend")])
15427 (define_expand "mmulhi_wl"
15428 [(match_operand:V2SI 0 "arith_reg_dest" "")
15429 (match_operand:V4HI 1 "arith_reg_operand" "")
15430 (match_operand:V4HI 2 "arith_reg_operand" "")]
15433 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul23_wl : gen_mmul01_wl)
15434 (operands[0], operands[1], operands[2]));
15438 (define_expand "mmullo_wl"
15439 [(match_operand:V2SI 0 "arith_reg_dest" "")
15440 (match_operand:V4HI 1 "arith_reg_operand" "")
15441 (match_operand:V4HI 2 "arith_reg_operand" "")]
15444 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul01_wl : gen_mmul23_wl)
15445 (operands[0], operands[1], operands[2]));
15449 (define_insn "mmul23_wl"
15450 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15453 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
15454 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
15455 (parallel [(const_int 2) (const_int 3)])))]
15458 return (TARGET_LITTLE_ENDIAN
15459 ? "mmulhi.wl %1, %2, %0"
15460 : "mmullo.wl %1, %2, %0");
15462 [(set_attr "type" "dmpy_media")
15463 (set (attr "highpart")
15464 (cond [(eq_attr "endian" "big") (const_string "ignore")]
15465 (const_string "user")))])
15467 (define_insn "mmul01_wl"
15468 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15471 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
15472 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
15473 (parallel [(const_int 0) (const_int 1)])))]
15476 return (TARGET_LITTLE_ENDIAN
15477 ? "mmullo.wl %1, %2, %0"
15478 : "mmulhi.wl %1, %2, %0");
15480 [(set_attr "type" "dmpy_media")
15481 (set (attr "highpart")
15482 (cond [(eq_attr "endian" "little") (const_string "ignore")]
15483 (const_string "user")))])
15486 (define_expand "mmulsum_wq"
15487 [(match_operand:DI 0 "arith_reg_dest" "")
15488 (match_operand:V4HI 1 "arith_reg_operand" "")
15489 (match_operand:V4HI 2 "arith_reg_operand" "")
15490 (match_operand:DI 3 "arith_reg_operand" "")]
15493 emit_insn (gen_mmulsum_wq_i (operands[0], operands[3],
15494 operands[1], operands[2]));
15498 (define_insn "mmulsum_wq_i"
15499 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15500 (plus:DI (match_operand:DI 1 "arith_reg_operand" "0")
15505 (sign_extend:V4DI (match_operand:V4HI 2 "arith_reg_operand" "r"))
15506 (sign_extend:V4DI (match_operand:V4HI 3 "arith_reg_operand" "r")))
15507 (parallel [(const_int 0)]))
15508 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
15509 (sign_extend:V4DI (match_dup 3)))
15510 (parallel [(const_int 1)])))
15512 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
15513 (sign_extend:V4DI (match_dup 3)))
15514 (parallel [(const_int 2)]))
15515 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
15516 (sign_extend:V4DI (match_dup 3)))
15517 (parallel [(const_int 3)]))))))]
15519 "mmulsum.wq %2, %3, %0"
15520 [(set_attr "type" "mac_media")])
15522 (define_expand "mperm_w"
15523 [(match_operand:V4HI 0 "arith_reg_dest" "=r")
15524 (match_operand:V4HI 1 "arith_reg_operand" "r")
15525 (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")]
15528 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mperm_w_little : gen_mperm_w_big)
15529 (operands[0], operands[1], operands[2]));
15533 ; This use of vec_select isn't exactly correct according to rtl.texi
15534 ; (because not constant), but it seems a straightforward extension.
15535 (define_insn "mperm_w_little"
15536 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15538 (match_operand:V4HI 1 "arith_reg_operand" "r")
15540 [(zero_extract:QI (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")
15541 (const_int 2) (const_int 0))
15542 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 2))
15543 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 4))
15544 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 6))])))]
15545 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
15546 "mperm.w %1, %N2, %0"
15547 [(set_attr "type" "arith_media")])
15549 (define_insn "mperm_w_big"
15550 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15552 (match_operand:V4HI 1 "arith_reg_operand" "r")
15554 [(zero_extract:QI (not:QI (match_operand:QI 2
15555 "extend_reg_or_0_operand" "rZ"))
15556 (const_int 2) (const_int 0))
15557 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 2))
15558 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 4))
15559 (zero_extract:QI (not:QI (match_dup 2))
15560 (const_int 2) (const_int 6))])))]
15561 "TARGET_SHMEDIA && TARGET_BIG_ENDIAN"
15562 "mperm.w %1, %N2, %0"
15563 [(set_attr "type" "arith_media")])
15565 (define_insn "mperm_w0"
15566 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15567 (vec_duplicate:V4HI (truncate:HI (match_operand 1
15568 "trunc_hi_operand" "r"))))]
15570 "mperm.w %1, r63, %0"
15571 [(set_attr "type" "arith_media")
15572 (set_attr "highpart" "ignore")])
15574 (define_expand "msad_ubq"
15575 [(match_operand:DI 0 "arith_reg_dest" "")
15576 (match_operand:V8QI 1 "arith_reg_or_0_operand" "")
15577 (match_operand:V8QI 2 "arith_reg_or_0_operand" "")
15578 (match_operand:DI 3 "arith_reg_operand" "")]
15581 emit_insn (gen_msad_ubq_i (operands[0], operands[3],
15582 operands[1], operands[2]));
15586 (define_insn "msad_ubq_i"
15587 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15592 (match_operand:DI 1 "arith_reg_operand" "0")
15593 (abs:DI (vec_select:DI
15596 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
15598 (match_operand:V8QI 3 "arith_reg_or_0_operand" "rZ")))
15599 (parallel [(const_int 0)]))))
15600 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
15601 (zero_extend:V8DI (match_dup 3)))
15602 (parallel [(const_int 1)]))))
15604 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
15605 (zero_extend:V8DI (match_dup 3)))
15606 (parallel [(const_int 2)])))
15607 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
15608 (zero_extend:V8DI (match_dup 3)))
15609 (parallel [(const_int 3)])))))
15612 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
15613 (zero_extend:V8DI (match_dup 3)))
15614 (parallel [(const_int 4)])))
15615 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
15616 (zero_extend:V8DI (match_dup 3)))
15617 (parallel [(const_int 5)]))))
15619 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
15620 (zero_extend:V8DI (match_dup 3)))
15621 (parallel [(const_int 6)])))
15622 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
15623 (zero_extend:V8DI (match_dup 3)))
15624 (parallel [(const_int 7)])))))))]
15626 "msad.ubq %N2, %N3, %0"
15627 [(set_attr "type" "mac_media")])
15629 (define_insn "mshalds_l"
15630 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15633 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
15634 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
15635 (const_int 31)))))]
15637 "mshalds.l %1, %2, %0"
15638 [(set_attr "type" "mcmp_media")
15639 (set_attr "highpart" "depend")])
15641 (define_insn "mshalds_w"
15642 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15645 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
15646 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
15647 (const_int 15)))))]
15649 "mshalds.w %1, %2, %0"
15650 [(set_attr "type" "mcmp_media")
15651 (set_attr "highpart" "depend")])
15653 (define_insn "ashrv2si3"
15654 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15655 (ashiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
15656 (match_operand:DI 2 "arith_reg_operand" "r")))]
15658 "mshard.l %1, %2, %0"
15659 [(set_attr "type" "arith_media")
15660 (set_attr "highpart" "depend")])
15662 (define_insn "ashrv4hi3"
15663 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15664 (ashiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
15665 (match_operand:DI 2 "arith_reg_operand" "r")))]
15667 "mshard.w %1, %2, %0"
15668 [(set_attr "type" "arith_media")
15669 (set_attr "highpart" "depend")])
15671 (define_insn "mshards_q"
15672 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
15674 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
15675 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ"))))]
15677 "mshards.q %1, %N2, %0"
15678 [(set_attr "type" "mcmp_media")])
15680 (define_expand "mshfhi_b"
15681 [(match_operand:V8QI 0 "arith_reg_dest" "")
15682 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
15683 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
15686 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_b : gen_mshf0_b)
15687 (operands[0], operands[1], operands[2]));
15691 (define_expand "mshflo_b"
15692 [(match_operand:V8QI 0 "arith_reg_dest" "")
15693 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
15694 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
15697 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_b : gen_mshf4_b)
15698 (operands[0], operands[1], operands[2]));
15702 (define_insn "mshf4_b"
15704 (match_operand:V8QI 0 "arith_reg_dest" "=r")
15706 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
15707 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
15708 (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13)
15709 (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))]
15712 return (TARGET_LITTLE_ENDIAN
15713 ? "mshfhi.b %N1, %N2, %0"
15714 : "mshflo.b %N1, %N2, %0");
15716 [(set_attr "type" "arith_media")
15717 (set (attr "highpart")
15718 (cond [(eq_attr "endian" "big") (const_string "ignore")]
15719 (const_string "user")))])
15721 (define_insn "mshf0_b"
15723 (match_operand:V8QI 0 "arith_reg_dest" "=r")
15725 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
15726 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
15727 (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9)
15728 (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))]
15731 return (TARGET_LITTLE_ENDIAN
15732 ? "mshflo.b %N1, %N2, %0"
15733 : "mshfhi.b %N1, %N2, %0");
15735 [(set_attr "type" "arith_media")
15736 (set (attr "highpart")
15737 (cond [(eq_attr "endian" "little") (const_string "ignore")]
15738 (const_string "user")))])
15740 (define_expand "mshfhi_l"
15741 [(match_operand:V2SI 0 "arith_reg_dest" "")
15742 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
15743 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
15746 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_l : gen_mshf0_l)
15747 (operands[0], operands[1], operands[2]));
15751 (define_expand "mshflo_l"
15752 [(match_operand:V2SI 0 "arith_reg_dest" "")
15753 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
15754 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
15757 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_l : gen_mshf4_l)
15758 (operands[0], operands[1], operands[2]));
15762 (define_insn "mshf4_l"
15763 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15765 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
15766 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
15767 (parallel [(const_int 1) (const_int 3)])))]
15770 return (TARGET_LITTLE_ENDIAN
15771 ? "mshfhi.l %N1, %N2, %0"
15772 : "mshflo.l %N1, %N2, %0");
15774 [(set_attr "type" "arith_media")
15775 (set (attr "highpart")
15776 (cond [(eq_attr "endian" "big") (const_string "ignore")]
15777 (const_string "user")))])
15779 (define_insn "mshf0_l"
15780 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15782 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
15783 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
15784 (parallel [(const_int 0) (const_int 2)])))]
15787 return (TARGET_LITTLE_ENDIAN
15788 ? "mshflo.l %N1, %N2, %0"
15789 : "mshfhi.l %N1, %N2, %0");
15791 [(set_attr "type" "arith_media")
15792 (set (attr "highpart")
15793 (cond [(eq_attr "endian" "little") (const_string "ignore")]
15794 (const_string "user")))])
15796 (define_expand "mshfhi_w"
15797 [(match_operand:V4HI 0 "arith_reg_dest" "")
15798 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15799 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
15802 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_w : gen_mshf0_w)
15803 (operands[0], operands[1], operands[2]));
15807 (define_expand "mshflo_w"
15808 [(match_operand:V4HI 0 "arith_reg_dest" "")
15809 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15810 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
15813 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_w : gen_mshf4_w)
15814 (operands[0], operands[1], operands[2]));
15818 (define_insn "mshf4_w"
15819 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15821 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15822 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
15823 (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))]
15826 return (TARGET_LITTLE_ENDIAN
15827 ? "mshfhi.w %N1, %N2, %0"
15828 : "mshflo.w %N1, %N2, %0");
15830 [(set_attr "type" "arith_media")
15831 (set (attr "highpart")
15832 (cond [(eq_attr "endian" "big") (const_string "ignore")]
15833 (const_string "user")))])
15835 (define_insn "mshf0_w"
15836 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15838 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15839 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
15840 (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))]
15843 return (TARGET_LITTLE_ENDIAN
15844 ? "mshflo.w %N1, %N2, %0"
15845 : "mshfhi.w %N1, %N2, %0");
15847 [(set_attr "type" "arith_media")
15848 (set (attr "highpart")
15849 (cond [(eq_attr "endian" "little") (const_string "ignore")]
15850 (const_string "user")))])
15852 (define_insn "mshflo_w_x"
15853 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15855 (vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rZ")
15856 (match_operand:V2HI 2 "extend_reg_or_0_operand" "rZ"))
15857 (parallel [(const_int 2) (const_int 0) (const_int 3) (const_int 1)])))]
15859 "mshflo.w %N1, %N2, %0"
15860 [(set_attr "type" "arith_media")
15861 (set_attr "highpart" "ignore")])
15863 ;; These are useful to expand ANDs and as combiner patterns.
15864 (define_insn_and_split "mshfhi_l_di"
15865 [(set (match_operand:DI 0 "arith_reg_dest" "=r,f")
15866 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ,f")
15868 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ,?f")
15869 (const_int -4294967296))))]
15872 mshfhi.l %N1, %N2, %0
15874 "TARGET_SHMEDIA && reload_completed
15875 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
15876 [(set (match_dup 3) (match_dup 4))
15877 (set (match_dup 5) (match_dup 6))]
15879 operands[3] = gen_lowpart (SImode, operands[0]);
15880 operands[4] = gen_highpart (SImode, operands[1]);
15881 operands[5] = gen_highpart (SImode, operands[0]);
15882 operands[6] = gen_highpart (SImode, operands[2]);
15884 [(set_attr "type" "arith_media")])
15886 (define_insn "*mshfhi_l_di_rev"
15887 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15888 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15889 (const_int -4294967296))
15890 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15893 "mshfhi.l %N2, %N1, %0"
15894 [(set_attr "type" "arith_media")])
15897 [(set (match_operand:DI 0 "arith_reg_dest" "")
15898 (ior:DI (zero_extend:DI (match_operand:SI 1
15899 "extend_reg_or_0_operand" ""))
15900 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "")
15901 (const_int -4294967296))))
15902 (clobber (match_operand:DI 3 "arith_reg_dest" ""))]
15906 emit_insn (gen_ashldi3_media (operands[3],
15907 simplify_gen_subreg (DImode, operands[1],
15910 emit_insn (gen_mshfhi_l_di (operands[0], operands[3], operands[2]));
15914 (define_insn "mshflo_l_di"
15915 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15916 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15917 (const_int 4294967295))
15918 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15922 "mshflo.l %N1, %N2, %0"
15923 [(set_attr "type" "arith_media")
15924 (set_attr "highpart" "ignore")])
15926 (define_insn "*mshflo_l_di_rev"
15927 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15928 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15930 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15931 (const_int 4294967295))))]
15934 "mshflo.l %N2, %N1, %0"
15935 [(set_attr "type" "arith_media")
15936 (set_attr "highpart" "ignore")])
15938 ;; Combiner pattern for trampoline initialization.
15939 (define_insn_and_split "*double_shori"
15940 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15941 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
15943 (match_operand:DI 2 "const_int_operand" "n")))]
15945 && ! (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)"
15947 "rtx_equal_p (operands[0], operands[1])"
15950 HOST_WIDE_INT v = INTVAL (operands[2]);
15952 emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v >> 16)));
15953 emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v & 65535)));
15956 [(set_attr "highpart" "ignore")])
15958 (define_insn "*mshflo_l_di_x"
15959 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15960 (ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand"
15962 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15965 "mshflo.l %N1, %N2, %0"
15966 [(set_attr "type" "arith_media")
15967 (set_attr "highpart" "ignore")])
15969 (define_insn_and_split "concat_v2sf"
15970 [(set (match_operand:V2SF 0 "register_operand" "=r,f,f?")
15971 ;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,0,f")
15972 (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,f,f")
15973 (match_operand:SF 2 "register_operand" "rZ,f,f")))]
15976 mshflo.l %N1, %N2, %0
15979 "TARGET_SHMEDIA && reload_completed
15980 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
15981 [(set (match_dup 3) (match_dup 1))
15982 (set (match_dup 4) (match_dup 2))]
15984 operands[3] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 0);
15985 operands[4] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 4);
15987 [(set_attr "type" "arith_media")
15988 (set_attr "highpart" "ignore")])
15990 (define_insn "*mshflo_l_di_x_rev"
15991 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15992 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15995 (match_operand:SI 2 "extend_reg_or_0_operand" "rZ"))))]
15997 "mshflo.l %N2, %N1, %0"
15998 [(set_attr "type" "arith_media")
15999 (set_attr "highpart" "ignore")])
16001 (define_insn "ashlv2si3"
16002 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
16003 (ashift:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
16004 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
16006 "mshlld.l %1, %2, %0"
16007 [(set_attr "type" "arith_media")
16008 (set_attr "highpart" "depend")])
16011 [(set (match_operand 0 "any_register_operand" "")
16012 (match_operator 3 "shift_operator"
16013 [(match_operand 1 "any_register_operand" "")
16014 (match_operand 2 "shift_count_reg_operand" "")]))]
16015 "TARGET_SHMEDIA && ! register_operand (operands[2], VOIDmode)"
16016 [(set (match_dup 0) (match_dup 3))]
16018 rtx count = operands[2];
16019 machine_mode outer_mode = GET_MODE (operands[2]), inner_mode;
16021 while (GET_CODE (count) == ZERO_EXTEND || GET_CODE (count) == SIGN_EXTEND
16022 || (GET_CODE (count) == SUBREG && SUBREG_BYTE (count) == 0)
16023 || GET_CODE (count) == TRUNCATE)
16024 count = XEXP (count, 0);
16025 inner_mode = GET_MODE (count);
16026 count = simplify_gen_subreg (outer_mode, count, inner_mode,
16027 subreg_lowpart_offset (outer_mode, inner_mode));
16028 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), GET_MODE (operands[3]),
16029 operands[1], count);
16032 (define_insn "ashlv4hi3"
16033 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
16034 (ashift:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
16035 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
16037 "mshlld.w %1, %2, %0"
16038 [(set_attr "type" "arith_media")
16039 (set_attr "highpart" "depend")])
16041 (define_insn "lshrv2si3"
16042 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
16043 (lshiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
16044 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
16046 "mshlrd.l %1, %2, %0"
16047 [(set_attr "type" "arith_media")
16048 (set_attr "highpart" "depend")])
16050 (define_insn "lshrv4hi3"
16051 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
16052 (lshiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
16053 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
16055 "mshlrd.w %1, %2, %0"
16056 [(set_attr "type" "arith_media")
16057 (set_attr "highpart" "depend")])
16059 (define_insn "subv2si3"
16060 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
16061 (minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
16062 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
16064 "msub.l %N1, %2, %0"
16065 [(set_attr "type" "arith_media")
16066 (set_attr "highpart" "depend")])
16068 (define_insn "subv4hi3"
16069 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
16070 (minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
16071 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
16073 "msub.w %N1, %2, %0"
16074 [(set_attr "type" "arith_media")
16075 (set_attr "highpart" "depend")])
16077 (define_insn_and_split "subv2hi3"
16078 [(set (match_operand:V2HI 0 "arith_reg_dest" "=r")
16079 (minus:V2HI (match_operand:V2HI 1 "arith_reg_or_0_operand" "rZ")
16080 (match_operand:V2HI 2 "arith_reg_operand" "r")))]
16086 rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0);
16087 rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0);
16088 rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0);
16089 rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0);
16090 rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0);
16092 emit_insn (gen_subv4hi3 (v4hi_dst, src0, src1));
16093 emit_insn (gen_truncdisi2 (si_dst, di_dst));
16096 [(set_attr "highpart" "must_split")])
16098 (define_insn "sssubv2si3"
16099 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
16100 (ss_minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
16101 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
16103 "msubs.l %N1, %2, %0"
16104 [(set_attr "type" "mcmp_media")
16105 (set_attr "highpart" "depend")])
16107 (define_insn "ussubv8qi3"
16108 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
16109 (us_minus:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
16110 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
16112 "msubs.ub %N1, %2, %0"
16113 [(set_attr "type" "mcmp_media")
16114 (set_attr "highpart" "depend")])
16116 (define_insn "sssubv4hi3"
16117 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
16118 (ss_minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
16119 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
16121 "msubs.w %N1, %2, %0"
16122 [(set_attr "type" "mcmp_media")
16123 (set_attr "highpart" "depend")])
16125 ;; -------------------------------------------------------------------------
16126 ;; Floating Point Intrinsics
16127 ;; -------------------------------------------------------------------------
16129 (define_insn "fcosa_s"
16130 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
16131 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
16135 [(set_attr "type" "atrans_media")])
16137 (define_insn "fsina_s"
16138 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
16139 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
16143 [(set_attr "type" "atrans_media")])
16145 (define_insn "fipr"
16146 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
16147 (plus:SF (plus:SF (vec_select:SF (mult:V4SF (match_operand:V4SF 1
16148 "fp_arith_reg_operand" "f")
16149 (match_operand:V4SF 2
16150 "fp_arith_reg_operand" "f"))
16151 (parallel [(const_int 0)]))
16152 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
16153 (parallel [(const_int 1)])))
16154 (plus:SF (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
16155 (parallel [(const_int 2)]))
16156 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
16157 (parallel [(const_int 3)])))))]
16159 "fipr.s %1, %2, %0"
16160 [(set_attr "type" "fparith_media")])
16162 (define_insn "fsrra_s"
16163 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
16164 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "f")]
16168 [(set_attr "type" "atrans_media")])
16170 (define_insn "ftrv"
16171 [(set (match_operand:V4SF 0 "fp_arith_reg_operand" "=f")
16175 (vec_select:V4SF (match_operand:V16SF 1 "fp_arith_reg_operand" "f")
16176 (parallel [(const_int 0) (const_int 5)
16177 (const_int 10) (const_int 15)]))
16178 (match_operand:V4SF 2 "fp_arith_reg_operand" "f"))
16180 (vec_select:V4SF (match_dup 1)
16181 (parallel [(const_int 4) (const_int 9)
16182 (const_int 14) (const_int 3)]))
16183 (vec_select:V4SF (match_dup 2)
16184 (parallel [(const_int 1) (const_int 2)
16185 (const_int 3) (const_int 0)]))))
16188 (vec_select:V4SF (match_dup 1)
16189 (parallel [(const_int 8) (const_int 13)
16190 (const_int 2) (const_int 7)]))
16191 (vec_select:V4SF (match_dup 2)
16192 (parallel [(const_int 2) (const_int 3)
16193 (const_int 0) (const_int 1)])))
16195 (vec_select:V4SF (match_dup 1)
16196 (parallel [(const_int 12) (const_int 1)
16197 (const_int 6) (const_int 11)]))
16198 (vec_select:V4SF (match_dup 2)
16199 (parallel [(const_int 3) (const_int 0)
16200 (const_int 1) (const_int 2)]))))))]
16202 "ftrv.s %1, %2, %0"
16203 [(set_attr "type" "fparith_media")])
16205 (define_insn "ldhi_l"
16206 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
16208 (mem:SI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p")
16211 (plus:SI (and:SI (match_dup 1) (const_int 3)) (const_int 1))
16215 [(set_attr "type" "load_media")])
16217 (define_insn "ldhi_q"
16218 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
16220 (mem:DI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p")
16223 (plus:SI (and:SI (match_dup 1) (const_int 7)) (const_int 1))
16227 [(set_attr "type" "load_media")])
16229 (define_insn_and_split "*ldhi_q_comb0"
16230 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
16232 (mem:DI (plus:SI (ior:SI (plus:SI
16233 (match_operand:SI 1 "register_operand" "r")
16234 (match_operand:SI 2 "ua_offset" "I06"))
16237 (plus:SI (and:SI (match_dup 1) (const_int 7))
16240 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0"
16245 emit_insn (gen_ldhi_q (operands[0],
16246 gen_rtx_PLUS (SImode, operands[1], operands[2])));
16250 (define_insn_and_split "*ldhi_q_comb1"
16251 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
16253 (mem:DI (plus:SI (ior:SI (plus:SI
16254 (match_operand:SI 1 "register_operand" "r")
16255 (match_operand:SI 2 "ua_offset" "I06"))
16258 (plus:SI (and:SI (plus:SI (match_dup 1)
16259 (match_operand:SI 3 "ua_offset" "I06"))
16263 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8)
16264 && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])"
16269 emit_insn (gen_ldhi_q (operands[0],
16270 gen_rtx_PLUS (SImode, operands[1], operands[2])));
16274 (define_insn "ldlo_l"
16275 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
16277 (mem:SI (and:SI (match_operand:QI 1 "ua_address_operand" "p")
16279 (minus:SI (const_int 4) (and:SI (match_dup 1) (const_int 3)))
16280 (and:SI (match_dup 1) (const_int 3))))]
16283 [(set_attr "type" "load_media")])
16285 (define_insn "ldlo_q"
16286 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
16288 (mem:DI (and:SI (match_operand:QI 1 "ua_address_operand" "p")
16290 (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7)))
16291 (and:SI (match_dup 1) (const_int 7))))]
16294 [(set_attr "type" "load_media")])
16296 (define_insn_and_split "*ldlo_q_comb0"
16297 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
16299 (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
16300 (match_operand:SI 2 "ua_offset" "I06"))
16302 (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7)))
16303 (and:SI (match_dup 1) (const_int 7))))]
16304 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0"
16309 emit_insn (gen_ldlo_q (operands[0],
16310 gen_rtx_PLUS (SImode, operands[1], operands[2])));
16314 (define_insn_and_split "*ldlo_q_comb1"
16315 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
16317 (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
16318 (match_operand:SI 2 "ua_offset" "I06"))
16320 (minus:SI (const_int 8)
16321 (and:SI (plus:SI (match_dup 1)
16322 (match_operand:SI 3 "ua_offset" "I06"))
16324 (and:SI (plus:SI (match_dup 1) (match_dup 3)) (const_int 7))))]
16325 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8)
16326 && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])"
16331 emit_insn (gen_ldlo_q (operands[0],
16332 gen_rtx_PLUS (SImode, operands[1], operands[2])));
16336 (define_insn "sthi_l"
16337 [(set (zero_extract:SI
16338 (mem:SI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p")
16341 (plus:SI (and:SI (match_dup 0) (const_int 3)) (const_int 1))
16343 (match_operand:SI 1 "arith_reg_operand" "r"))]
16346 [(set_attr "type" "ustore_media")])
16348 ;; All unaligned stores are considered to be 'narrow' because they typically
16349 ;; operate on less that a quadword, and when they operate on a full quadword,
16350 ;; the vanilla store high / store low sequence will cause a stall if not
16351 ;; scheduled apart.
16352 (define_insn "sthi_q"
16353 [(set (zero_extract:DI
16354 (mem:DI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p")
16357 (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1))
16359 (match_operand:DI 1 "arith_reg_operand" "r"))]
16362 [(set_attr "type" "ustore_media")])
16364 (define_insn_and_split "*sthi_q_comb0"
16365 [(set (zero_extract:DI
16366 (mem:DI (plus:SI (ior:SI (plus:SI
16367 (match_operand:SI 0 "register_operand" "r")
16368 (match_operand:SI 1 "ua_offset" "I06"))
16371 (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1))
16373 (match_operand:DI 2 "arith_reg_operand" "r"))]
16374 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0"
16379 emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
16384 (define_insn_and_split "*sthi_q_comb1"
16385 [(set (zero_extract:DI
16386 (mem:DI (plus:SI (ior:SI (plus:SI
16387 (match_operand:SI 0 "register_operand" "r")
16388 (match_operand:SI 1 "ua_offset" "I06"))
16391 (plus:SI (and:SI (plus:SI (match_dup 0)
16392 (match_operand:SI 2 "ua_offset" "I06"))
16396 (match_operand:DI 3 "arith_reg_operand" "r"))]
16397 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & -8)
16398 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])"
16403 emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
16408 ;; This is highpart user because the address is used as full 64 bit.
16409 (define_insn "stlo_l"
16410 [(set (zero_extract:SI
16411 (mem:SI (and:SI (match_operand:QI 0 "ua_address_operand" "p")
16413 (minus:SI (const_int 4) (and:SI (match_dup 0) (const_int 3)))
16414 (and:SI (match_dup 0) (const_int 3)))
16415 (match_operand:SI 1 "arith_reg_operand" "r"))]
16418 [(set_attr "type" "ustore_media")])
16420 (define_insn "stlo_q"
16421 [(set (zero_extract:DI
16422 (mem:DI (and:SI (match_operand:QI 0 "ua_address_operand" "p")
16424 (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7)))
16425 (and:SI (match_dup 0) (const_int 7)))
16426 (match_operand:DI 1 "arith_reg_operand" "r"))]
16429 [(set_attr "type" "ustore_media")])
16431 (define_insn_and_split "*stlo_q_comb0"
16432 [(set (zero_extract:DI
16433 (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
16434 (match_operand:SI 1 "ua_offset" "I06"))
16436 (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7)))
16437 (and:SI (match_dup 0) (const_int 7)))
16438 (match_operand:DI 2 "arith_reg_operand" "r"))]
16439 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0"
16444 emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
16449 (define_insn_and_split "*stlo_q_comb1"
16450 [(set (zero_extract:DI
16451 (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
16452 (match_operand:SI 1 "ua_offset" "I06"))
16454 (minus:SI (const_int 8)
16455 (and:SI (plus:SI (match_dup 0)
16456 (match_operand:SI 2 "ua_offset" "I06"))
16458 (and:SI (plus:SI (match_dup 0) (match_dup 2)) (const_int 7)))
16459 (match_operand:DI 3 "arith_reg_operand" "r"))]
16460 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])"
16465 emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
16470 (define_insn "ldhi_l64"
16471 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
16473 (mem:SI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p")
16476 (plus:DI (and:DI (match_dup 1) (const_int 3)) (const_int 1))
16480 [(set_attr "type" "load_media")])
16482 (define_insn "ldhi_q64"
16483 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
16485 (mem:DI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p")
16488 (plus:DI (and:DI (match_dup 1) (const_int 7)) (const_int 1))
16492 [(set_attr "type" "load_media")])
16494 (define_insn "ldlo_l64"
16495 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
16497 (mem:SI (and:DI (match_operand:QI 1 "ua_address_operand" "p")
16499 (minus:DI (const_int 4) (and:DI (match_dup 1) (const_int 3)))
16500 (and:DI (match_dup 1) (const_int 3))))]
16503 [(set_attr "type" "load_media")])
16505 (define_insn "ldlo_q64"
16506 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
16508 (mem:DI (and:DI (match_operand:QI 1 "ua_address_operand" "p")
16510 (minus:DI (const_int 8) (and:DI (match_dup 1) (const_int 7)))
16511 (and:DI (match_dup 1) (const_int 7))))]
16514 [(set_attr "type" "load_media")])
16516 (define_insn "sthi_l64"
16517 [(set (zero_extract:SI
16518 (mem:SI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p")
16521 (plus:DI (and:DI (match_dup 0) (const_int 3)) (const_int 1))
16523 (match_operand:SI 1 "arith_reg_operand" "r"))]
16526 [(set_attr "type" "ustore_media")])
16528 (define_insn "sthi_q64"
16529 [(set (zero_extract:DI
16530 (mem:DI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p")
16533 (plus:DI (and:DI (match_dup 0) (const_int 7)) (const_int 1))
16535 (match_operand:DI 1 "arith_reg_operand" "r"))]
16538 [(set_attr "type" "ustore_media")])
16540 (define_insn "stlo_l64"
16541 [(set (zero_extract:SI
16542 (mem:SI (and:DI (match_operand:QI 0 "ua_address_operand" "p")
16544 (minus:DI (const_int 4) (and:DI (match_dup 0) (const_int 3)))
16545 (and:DI (match_dup 0) (const_int 3)))
16546 (match_operand:SI 1 "arith_reg_operand" "r"))]
16549 [(set_attr "type" "ustore_media")])
16551 (define_insn "stlo_q64"
16552 [(set (zero_extract:DI
16553 (mem:DI (and:DI (match_operand:QI 0 "ua_address_operand" "p")
16555 (minus:DI (const_int 8) (and:DI (match_dup 0) (const_int 7)))
16556 (and:DI (match_dup 0) (const_int 7)))
16557 (match_operand:DI 1 "arith_reg_operand" "r"))]
16560 [(set_attr "type" "ustore_media")])
16563 [(set (match_operand:QI 0 "arith_reg_dest" "=r")
16564 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
16568 [(set_attr "type" "arith_media")])
16570 (define_insn "nsbsi"
16571 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
16573 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
16577 [(set_attr "type" "arith_media")])
16579 (define_insn "nsbdi"
16580 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
16582 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
16586 [(set_attr "type" "arith_media")])
16588 (define_expand "ffsdi2"
16589 [(set (match_operand:DI 0 "arith_reg_dest" "")
16590 (ffs:DI (match_operand:DI 1 "arith_reg_operand" "")))]
16593 rtx scratch = gen_reg_rtx (DImode);
16596 emit_insn (gen_adddi3 (scratch, operands[1], constm1_rtx));
16597 emit_insn (gen_xordi3 (scratch, operands[1], scratch));
16598 emit_insn (gen_lshrdi3_media (scratch, scratch, const1_rtx));
16599 emit_insn (gen_nsbdi (scratch, scratch));
16600 emit_insn (gen_adddi3 (scratch, scratch, GEN_INT (-64)));
16601 emit_insn (gen_movdicc_false (scratch, operands[1], const0_rtx, scratch));
16602 last = emit_insn (gen_subdi3 (operands[0], const0_rtx, scratch));
16603 set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (DImode, operands[0]));
16608 (define_expand "ffssi2"
16609 [(set (match_operand:SI 0 "arith_reg_dest" "")
16610 (ffs:SI (match_operand:SI 1 "arith_reg_operand" "")))]
16613 rtx scratch = gen_reg_rtx (SImode);
16614 rtx discratch = gen_reg_rtx (DImode);
16617 emit_insn (gen_adddi3 (discratch,
16618 simplify_gen_subreg (DImode, operands[1], SImode, 0),
16620 emit_insn (gen_andcdi3 (discratch,
16621 simplify_gen_subreg (DImode, operands[1], SImode, 0),
16623 emit_insn (gen_nsbsi (scratch, discratch));
16624 last = emit_insn (gen_subsi3 (operands[0],
16625 force_reg (SImode, GEN_INT (63)), scratch));
16626 set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (SImode, operands[0]));
16631 (define_insn "byterev"
16632 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
16633 (vec_select:V8QI (match_operand:V8QI 1 "arith_reg_operand" "r")
16634 (parallel [(const_int 7) (const_int 6) (const_int 5)
16635 (const_int 4) (const_int 3) (const_int 2)
16636 (const_int 1) (const_int 0)])))]
16639 [(set_attr "type" "arith_media")])
16641 ;; In user mode, the "pref" instruction will raise a RADDERR exception
16642 ;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable
16643 ;; implementation of __builtin_prefetch for VxWorks RTPs.
16644 (define_expand "prefetch"
16645 [(prefetch (match_operand 0 "address_operand" "")
16646 (match_operand:SI 1 "const_int_operand" "")
16647 (match_operand:SI 2 "const_int_operand" ""))]
16648 "(TARGET_SH2A || TARGET_SH3 || TARGET_SH5)
16649 && (TARGET_SHMEDIA || ! TARGET_VXWORKS_RTP)")
16651 (define_insn "*prefetch"
16652 [(prefetch (match_operand:SI 0 "register_operand" "r")
16653 (match_operand:SI 1 "const_int_operand" "n")
16654 (match_operand:SI 2 "const_int_operand" "n"))]
16655 "(TARGET_SH2A || TARGET_SH3 || TARGET_SHCOMPACT) && ! TARGET_VXWORKS_RTP"
16657 [(set_attr "type" "other")])
16659 (define_insn "*prefetch_media"
16660 [(prefetch (match_operand:QI 0 "address_operand" "p")
16661 (match_operand:SI 1 "const_int_operand" "n")
16662 (match_operand:SI 2 "const_int_operand" "n"))]
16665 operands[0] = gen_rtx_MEM (QImode, operands[0]);
16666 output_asm_insn ("ld%M0.b %m0,r63", operands);
16669 [(set_attr "type" "other")])
16671 (define_insn "alloco_i"
16672 [(set (mem:BLK (match_operand:QI 0 "cache_address_operand" "p"))
16673 (unspec:BLK [(const_int 0)] UNSPEC_ALLOCO))]
16678 if (GET_CODE (operands[0]) == PLUS)
16680 xops[0] = XEXP (operands[0], 0);
16681 xops[1] = XEXP (operands[0], 1);
16685 xops[0] = operands[0];
16686 xops[1] = const0_rtx;
16688 output_asm_insn ("alloco %0, %1", xops);
16691 [(set_attr "type" "other")])
16694 [(set (match_operand 0 "any_register_operand" "")
16695 (match_operand 1 "" ""))]
16696 "TARGET_SHMEDIA && reload_completed"
16697 [(set (match_dup 0) (match_dup 1))]
16699 if (!shmedia_cleanup_truncate (operands[1]))
16703 ;; -------------------------------------------------------------------------
16704 ;; Stack Protector Patterns
16705 ;; -------------------------------------------------------------------------
16707 (define_expand "stack_protect_set"
16708 [(set (match_operand 0 "memory_operand" "")
16709 (match_operand 1 "memory_operand" ""))]
16712 if (TARGET_SHMEDIA)
16714 if (TARGET_SHMEDIA64)
16715 emit_insn (gen_stack_protect_set_di_media (operands[0], operands[1]));
16717 emit_insn (gen_stack_protect_set_si_media (operands[0], operands[1]));
16720 emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
16725 (define_insn "stack_protect_set_si"
16726 [(set (match_operand:SI 0 "memory_operand" "=m")
16727 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
16728 (set (match_scratch:SI 2 "=&r") (const_int 0))]
16731 return "mov.l %1,%2" "\n"
16732 " mov.l %2,%0" "\n"
16735 [(set_attr "type" "other")
16736 (set_attr "length" "6")])
16738 (define_insn "stack_protect_set_si_media"
16739 [(set (match_operand:SI 0 "memory_operand" "=m")
16740 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
16741 (set (match_scratch:SI 2 "=&r") (const_int 0))]
16744 return "ld%M1.l %m1,%2" "\n"
16745 " st%M0.l %m0,%2" "\n"
16748 [(set_attr "type" "other")
16749 (set_attr "length" "12")])
16751 (define_insn "stack_protect_set_di_media"
16752 [(set (match_operand:DI 0 "memory_operand" "=m")
16753 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
16754 (set (match_scratch:DI 2 "=&r") (const_int 0))]
16757 return "ld%M1.q %m1,%2" "\n"
16758 " st%M0.q %m0,%2" "\n"
16761 [(set_attr "type" "other")
16762 (set_attr "length" "12")])
16764 (define_expand "stack_protect_test"
16765 [(match_operand 0 "memory_operand" "")
16766 (match_operand 1 "memory_operand" "")
16767 (match_operand 2 "" "")]
16770 if (TARGET_SHMEDIA)
16772 rtx tmp = gen_reg_rtx (GET_MODE (operands[0]));
16775 test = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
16776 if (TARGET_SHMEDIA64)
16778 emit_insn (gen_stack_protect_test_di_media (tmp, operands[0],
16780 emit_jump_insn (gen_cbranchdi4 (test, tmp, const0_rtx, operands[2]));
16784 emit_insn (gen_stack_protect_test_si_media (tmp, operands[0],
16786 emit_jump_insn (gen_cbranchsi4 (test, tmp, const0_rtx, operands[2]));
16791 emit_insn (gen_stack_protect_test_si (operands[0], operands[1]));
16792 emit_jump_insn (gen_branch_true (operands[2]));
16798 (define_insn "stack_protect_test_si"
16799 [(set (reg:SI T_REG)
16800 (unspec:SI [(match_operand:SI 0 "memory_operand" "m")
16801 (match_operand:SI 1 "memory_operand" "m")]
16803 (set (match_scratch:SI 2 "=&r") (const_int 0))
16804 (set (match_scratch:SI 3 "=&r") (const_int 0))]
16807 return "mov.l %0,%2" "\n"
16808 " mov.l %1,%3" "\n"
16809 " cmp/eq %2,%3" "\n"
16813 [(set_attr "type" "other")
16814 (set_attr "length" "10")])
16816 (define_insn "stack_protect_test_si_media"
16817 [(set (match_operand:SI 0 "register_operand" "=&r")
16818 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
16819 (match_operand:SI 2 "memory_operand" "m")]
16821 (set (match_scratch:SI 3 "=&r") (const_int 0))]
16824 return "ld%M1.l %m1,%0" "\n"
16825 " ld%M2.l %m2,%3" "\n"
16826 " cmpeq %0,%3,%0" "\n"
16829 [(set_attr "type" "other")
16830 (set_attr "length" "16")])
16832 (define_insn "stack_protect_test_di_media"
16833 [(set (match_operand:DI 0 "register_operand" "=&r")
16834 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
16835 (match_operand:DI 2 "memory_operand" "m")]
16837 (set (match_scratch:DI 3 "=&r") (const_int 0))]
16840 return "ld%M1.q %m1,%0" "\n"
16841 " ld%M2.q %m2,%3" "\n"
16842 " cmpeq %0,%3,%0" "\n"
16845 [(set_attr "type" "other")
16846 (set_attr "length" "16")])
16848 ;; -------------------------------------------------------------------------
16849 ;; Atomic operations
16850 ;; -------------------------------------------------------------------------
16852 (include "sync.md")