1 /* LRA (local register allocator) driver and LRA utilities.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* The Local Register Allocator (LRA) is a replacement of former
23 reload pass. It is focused to simplify code solving the reload
24 pass tasks, to make the code maintenance easier, and to implement new
25 perspective optimizations.
27 The major LRA design solutions are:
28 o division small manageable, separated sub-tasks
29 o reflection of all transformations and decisions in RTL as more
31 o insn constraints as a primary source of the info (minimizing
32 number of target-depended macros/hooks)
34 In brief LRA works by iterative insn process with the final goal is
35 to satisfy all insn and address constraints:
36 o New reload insns (in brief reloads) and reload pseudos might be
38 o Some pseudos might be spilled to assign hard registers to
40 o Changing spilled pseudos to stack memory or their equivalences;
41 o Allocation stack memory changes the address displacement and
42 new iteration is needed.
44 Here is block diagram of LRA passes:
46 ------------------------
47 --------------- | Undo inheritance for | ---------------
48 | Memory-memory | | spilled pseudos, | | New (and old) |
49 | move coalesce |<---| splits for pseudos got |<-- | pseudos |
50 --------------- | the same hard regs, | | assignment |
51 Start | | and optional reloads | ---------------
52 | | ------------------------ ^
53 V | ---------------- |
54 ----------- V | Update virtual | |
55 | Remove |----> ------------>| register | |
56 | scratches | ^ | displacements | |
57 ----------- | ---------------- |
60 ---------------- No ------------ pseudos -------------------
61 | Spilled pseudo | change |Constraints:| or insns | Inheritance/split |
62 | to memory |<-------| RTL |--------->| transformations |
63 | substitution | | transfor- | | in EBB scope |
64 ---------------- | mations | -------------------
67 -------------------------
68 | Hard regs substitution, |
69 | devirtalization, and |------> Finish
70 | restoring scratches got |
72 -------------------------
74 To speed up the process:
75 o We process only insns affected by changes on previous
77 o We don't use DFA-infrastructure because it results in much slower
78 compiler speed than a special IR described below does;
79 o We use a special insn representation for quick access to insn
80 info which is always *synchronized* with the current RTL;
81 o Insn IR is minimized by memory. It is divided on three parts:
82 o one specific for each insn in RTL (only operand locations);
83 o one common for all insns in RTL with the same insn code
84 (different operand attributes from machine descriptions);
85 o one oriented for maintenance of live info (list of pseudos).
87 o all insns where the pseudo is referenced;
88 o live info (conflicting hard regs, live ranges, # of
90 o data used for assigning (preferred hard regs, costs etc).
92 This file contains LRA driver, LRA utility functions and data, and
93 code for dealing with scratches. */
97 #include "coretypes.h"
99 #include "hard-reg-set.h"
103 #include "insn-config.h"
104 #include "insn-codes.h"
107 #include "addresses.h"
109 #include "function.h"
111 #include "basic-block.h"
113 #include "tree-pass.h"
121 /* Hard registers currently not available for allocation. It can
122 changed after some hard registers become not eliminable. */
123 HARD_REG_SET lra_no_alloc_regs
;
125 static int get_new_reg_value (void);
126 static void expand_reg_info (void);
127 static void invalidate_insn_recog_data (int);
128 static int get_insn_freq (rtx
);
129 static void invalidate_insn_data_regno_info (lra_insn_recog_data_t
, rtx
, int);
131 /* Expand all regno related info needed for LRA. */
133 expand_reg_data (int old
)
137 ira_expand_reg_equiv ();
138 for (int i
= (int) max_reg_num () - 1; i
>= old
; i
--)
139 lra_change_class (i
, ALL_REGS
, " Set", true);
142 /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL
143 or of VOIDmode, use MD_MODE for the new reg. Initialize its
144 register class to RCLASS. Print message about assigning class
145 RCLASS containing new register name TITLE unless it is NULL. Use
146 attributes of ORIGINAL if it is a register. The created register
147 will have unique held value. */
149 lra_create_new_reg_with_unique_value (enum machine_mode md_mode
, rtx original
,
150 enum reg_class rclass
, const char *title
)
152 enum machine_mode mode
;
155 if (original
== NULL_RTX
|| (mode
= GET_MODE (original
)) == VOIDmode
)
157 lra_assert (mode
!= VOIDmode
);
158 new_reg
= gen_reg_rtx (mode
);
159 if (original
== NULL_RTX
|| ! REG_P (original
))
161 if (lra_dump_file
!= NULL
)
162 fprintf (lra_dump_file
, " Creating newreg=%i", REGNO (new_reg
));
166 if (ORIGINAL_REGNO (original
) >= FIRST_PSEUDO_REGISTER
)
167 ORIGINAL_REGNO (new_reg
) = ORIGINAL_REGNO (original
);
168 REG_USERVAR_P (new_reg
) = REG_USERVAR_P (original
);
169 REG_POINTER (new_reg
) = REG_POINTER (original
);
170 REG_ATTRS (new_reg
) = REG_ATTRS (original
);
171 if (lra_dump_file
!= NULL
)
172 fprintf (lra_dump_file
, " Creating newreg=%i from oldreg=%i",
173 REGNO (new_reg
), REGNO (original
));
175 if (lra_dump_file
!= NULL
)
178 fprintf (lra_dump_file
, ", assigning class %s to%s%s r%d",
179 reg_class_names
[rclass
], *title
== '\0' ? "" : " ",
180 title
, REGNO (new_reg
));
181 fprintf (lra_dump_file
, "\n");
183 expand_reg_data (max_reg_num ());
184 setup_reg_classes (REGNO (new_reg
), rclass
, NO_REGS
, rclass
);
188 /* Analogous to the previous function but also inherits value of
191 lra_create_new_reg (enum machine_mode md_mode
, rtx original
,
192 enum reg_class rclass
, const char *title
)
197 = lra_create_new_reg_with_unique_value (md_mode
, original
, rclass
, title
);
198 if (original
!= NULL_RTX
&& REG_P (original
))
199 lra_assign_reg_val (REGNO (original
), REGNO (new_reg
));
203 /* Set up for REGNO unique hold value. */
205 lra_set_regno_unique_value (int regno
)
207 lra_reg_info
[regno
].val
= get_new_reg_value ();
210 /* Invalidate INSN related info used by LRA. The info should never be
213 lra_invalidate_insn_data (rtx insn
)
215 lra_invalidate_insn_regno_info (insn
);
216 invalidate_insn_recog_data (INSN_UID (insn
));
219 /* Mark INSN deleted and invalidate the insn related info used by
222 lra_set_insn_deleted (rtx insn
)
224 lra_invalidate_insn_data (insn
);
225 SET_INSN_DELETED (insn
);
228 /* Delete an unneeded INSN and any previous insns who sole purpose is
229 loading data that is dead in INSN. */
231 lra_delete_dead_insn (rtx insn
)
233 rtx prev
= prev_real_insn (insn
);
236 /* If the previous insn sets a register that dies in our insn,
238 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
239 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
240 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
241 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
242 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
243 lra_delete_dead_insn (prev
);
245 lra_set_insn_deleted (insn
);
248 /* Emit insn x = y + z. Return NULL if we failed to do it.
249 Otherwise, return the insn. We don't use gen_add3_insn as it might
252 emit_add3_insn (rtx x
, rtx y
, rtx z
)
256 last
= get_last_insn ();
258 if (have_addptr3_insn (x
, y
, z
))
260 insn
= gen_addptr3_insn (x
, y
, z
);
262 /* If the target provides an "addptr" pattern it hopefully does
263 for a reason. So falling back to the normal add would be
265 lra_assert (insn
!= NULL_RTX
);
270 insn
= emit_insn (gen_rtx_SET (VOIDmode
, x
,
271 gen_rtx_PLUS (GET_MODE (y
), y
, z
)));
272 if (recog_memoized (insn
) < 0)
274 delete_insns_since (last
);
280 /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the
283 emit_add2_insn (rtx x
, rtx y
)
287 insn
= emit_add3_insn (x
, x
, y
);
288 if (insn
== NULL_RTX
)
290 insn
= gen_add2_insn (x
, y
);
291 if (insn
!= NULL_RTX
)
297 /* Target checks operands through operand predicates to recognize an
298 insn. We should have a special precaution to generate add insns
299 which are frequent results of elimination.
301 Emit insns for x = y + z. X can be used to store intermediate
302 values and should be not in Y and Z when we use X to store an
303 intermediate value. Y + Z should form [base] [+ index[ * scale]] [
304 + disp] where base and index are registers, disp and scale are
305 constants. Y should contain base if it is present, Z should
306 contain disp if any. index[*scale] can be part of Y or Z. */
308 lra_emit_add (rtx x
, rtx y
, rtx z
)
312 rtx a1
, a2
, base
, index
, disp
, scale
, index_scale
;
315 insn
= emit_add3_insn (x
, y
, z
);
316 old
= max_reg_num ();
317 if (insn
!= NULL_RTX
)
321 disp
= a2
= NULL_RTX
;
322 if (GET_CODE (y
) == PLUS
)
336 index_scale
= scale
= NULL_RTX
;
337 if (GET_CODE (a1
) == MULT
)
340 index
= XEXP (a1
, 0);
341 scale
= XEXP (a1
, 1);
344 else if (a2
!= NULL_RTX
&& GET_CODE (a2
) == MULT
)
347 index
= XEXP (a2
, 0);
348 scale
= XEXP (a2
, 1);
356 if (! (REG_P (base
) || GET_CODE (base
) == SUBREG
)
357 || (index
!= NULL_RTX
358 && ! (REG_P (index
) || GET_CODE (index
) == SUBREG
))
359 || (disp
!= NULL_RTX
&& ! CONSTANT_P (disp
))
360 || (scale
!= NULL_RTX
&& ! CONSTANT_P (scale
)))
362 /* Probably we have no 3 op add. Last chance is to use 2-op
363 add insn. To succeed, don't move Z to X as an address
364 segment always comes in Y. Otherwise, we might fail when
365 adding the address segment to register. */
366 lra_assert (x
!= y
&& x
!= z
);
367 emit_move_insn (x
, y
);
368 insn
= emit_add2_insn (x
, z
);
369 lra_assert (insn
!= NULL_RTX
);
373 if (index_scale
== NULL_RTX
)
375 if (disp
== NULL_RTX
)
377 /* Generate x = index_scale; x = x + base. */
378 lra_assert (index_scale
!= NULL_RTX
&& base
!= NULL_RTX
);
379 emit_move_insn (x
, index_scale
);
380 insn
= emit_add2_insn (x
, base
);
381 lra_assert (insn
!= NULL_RTX
);
383 else if (scale
== NULL_RTX
)
385 /* Try x = base + disp. */
386 lra_assert (base
!= NULL_RTX
);
387 last
= get_last_insn ();
388 insn
= emit_move_insn (x
, gen_rtx_PLUS (GET_MODE (base
),
390 if (recog_memoized (insn
) < 0)
392 delete_insns_since (last
);
393 /* Generate x = disp; x = x + base. */
394 emit_move_insn (x
, disp
);
395 insn
= emit_add2_insn (x
, base
);
396 lra_assert (insn
!= NULL_RTX
);
398 /* Generate x = x + index. */
399 if (index
!= NULL_RTX
)
401 insn
= emit_add2_insn (x
, index
);
402 lra_assert (insn
!= NULL_RTX
);
407 /* Try x = index_scale; x = x + disp; x = x + base. */
408 last
= get_last_insn ();
409 insn
= emit_move_insn (x
, index_scale
);
411 if (recog_memoized (insn
) >= 0)
413 insn
= emit_add2_insn (x
, disp
);
414 if (insn
!= NULL_RTX
)
416 insn
= emit_add2_insn (x
, disp
);
417 if (insn
!= NULL_RTX
)
423 delete_insns_since (last
);
424 /* Generate x = disp; x = x + base; x = x + index_scale. */
425 emit_move_insn (x
, disp
);
426 insn
= emit_add2_insn (x
, base
);
427 lra_assert (insn
!= NULL_RTX
);
428 insn
= emit_add2_insn (x
, index_scale
);
429 lra_assert (insn
!= NULL_RTX
);
434 /* Functions emit_... can create pseudos -- so expand the pseudo
436 if (old
!= max_reg_num ())
437 expand_reg_data (old
);
440 /* The number of emitted reload insns so far. */
441 int lra_curr_reload_num
;
443 /* Emit x := y, processing special case when y = u + v or y = u + v *
444 scale + w through emit_add (Y can be an address which is base +
445 index reg * scale + displacement in general case). X may be used
446 as intermediate result therefore it should be not in Y. */
448 lra_emit_move (rtx x
, rtx y
)
452 if (GET_CODE (y
) != PLUS
)
454 if (rtx_equal_p (x
, y
))
456 old
= max_reg_num ();
457 emit_move_insn (x
, y
);
459 lra_reg_info
[ORIGINAL_REGNO (x
)].last_reload
= ++lra_curr_reload_num
;
460 /* Function emit_move can create pseudos -- so expand the pseudo
462 if (old
!= max_reg_num ())
463 expand_reg_data (old
);
466 lra_emit_add (x
, XEXP (y
, 0), XEXP (y
, 1));
469 /* Update insn operands which are duplication of operands whose
470 numbers are in array of NOPS (with end marker -1). The insn is
471 represented by its LRA internal representation ID. */
473 lra_update_dups (lra_insn_recog_data_t id
, signed char *nops
)
476 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
478 for (i
= 0; i
< static_id
->n_dups
; i
++)
479 for (j
= 0; (nop
= nops
[j
]) >= 0; j
++)
480 if (static_id
->dup_num
[i
] == nop
)
481 *id
->dup_loc
[i
] = *id
->operand_loc
[nop
];
486 /* This page contains code dealing with info about registers in the
489 /* Pools for insn reg info. */
490 static alloc_pool insn_reg_pool
;
492 /* Initiate pool for insn reg info. */
494 init_insn_regs (void)
497 = create_alloc_pool ("insn regs", sizeof (struct lra_insn_reg
), 100);
500 /* Create LRA insn related info about a reference to REGNO in INSN with
501 TYPE (in/out/inout), biggest reference mode MODE, flag that it is
502 reference through subreg (SUBREG_P), flag that is early clobbered
503 in the insn (EARLY_CLOBBER), and reference to the next insn reg
505 static struct lra_insn_reg
*
506 new_insn_reg (rtx insn
, int regno
, enum op_type type
, enum machine_mode mode
,
507 bool subreg_p
, bool early_clobber
, struct lra_insn_reg
*next
)
509 struct lra_insn_reg
*ir
;
511 ir
= (struct lra_insn_reg
*) pool_alloc (insn_reg_pool
);
513 ir
->biggest_mode
= mode
;
514 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (lra_reg_info
[regno
].biggest_mode
)
515 && NONDEBUG_INSN_P (insn
))
516 lra_reg_info
[regno
].biggest_mode
= mode
;
517 ir
->subreg_p
= subreg_p
;
518 ir
->early_clobber
= early_clobber
;
524 /* Free insn reg info IR. */
526 free_insn_reg (struct lra_insn_reg
*ir
)
528 pool_free (insn_reg_pool
, ir
);
531 /* Free insn reg info list IR. */
533 free_insn_regs (struct lra_insn_reg
*ir
)
535 struct lra_insn_reg
*next_ir
;
537 for (; ir
!= NULL
; ir
= next_ir
)
544 /* Finish pool for insn reg info. */
546 finish_insn_regs (void)
548 free_alloc_pool (insn_reg_pool
);
553 /* This page contains code dealing LRA insn info (or in other words
554 LRA internal insn representation). */
556 struct target_lra_int default_target_lra_int
;
557 #if SWITCHABLE_TARGET
558 struct target_lra_int
*this_target_lra_int
= &default_target_lra_int
;
561 /* Map INSN_CODE -> the static insn data. This info is valid during
562 all translation unit. */
563 struct lra_static_insn_data
*insn_code_data
[LAST_INSN_CODE
];
565 /* Debug insns are represented as a special insn with one input
566 operand which is RTL expression in var_location. */
568 /* The following data are used as static insn operand data for all
569 debug insns. If structure lra_operand_data is changed, the
570 initializer should be changed too. */
571 static struct lra_operand_data debug_operand_data
=
573 NULL
, /* alternative */
574 VOIDmode
, /* We are not interesting in the operand mode. */
579 /* The following data are used as static insn data for all debug
580 insns. If structure lra_static_insn_data is changed, the
581 initializer should be changed too. */
582 static struct lra_static_insn_data debug_insn_static_data
=
585 0, /* Duplication operands #. */
586 -1, /* Commutative operand #. */
587 1, /* Operands #. There is only one operand which is debug RTL
589 0, /* Duplications #. */
590 0, /* Alternatives #. We are not interesting in alternatives
591 because we does not proceed debug_insns for reloads. */
592 NULL
, /* Hard registers referenced in machine description. */
593 NULL
/* Descriptions of operands in alternatives. */
596 /* Called once per compiler work to initialize some LRA data related
599 init_insn_code_data_once (void)
601 memset (insn_code_data
, 0, sizeof (insn_code_data
));
602 memset (op_alt_data
, 0, sizeof (op_alt_data
));
605 /* Called once per compiler work to finalize some LRA data related to
608 finish_insn_code_data_once (void)
612 for (i
= 0; i
< LAST_INSN_CODE
; i
++)
614 if (insn_code_data
[i
] != NULL
)
615 free (insn_code_data
[i
]);
616 if (op_alt_data
[i
] != NULL
)
617 free (op_alt_data
[i
]);
621 /* Initialize LRA info about operands in insn alternatives. */
623 init_op_alt_data (void)
627 for (i
= 0; i
< LAST_INSN_CODE
; i
++)
628 if (op_alt_data
[i
] != NULL
)
630 free (op_alt_data
[i
]);
631 op_alt_data
[i
] = NULL
;
635 /* Return static insn data, allocate and setup if necessary. Although
636 dup_num is static data (it depends only on icode), to set it up we
637 need to extract insn first. So recog_data should be valid for
638 normal insn (ICODE >= 0) before the call. */
639 static struct lra_static_insn_data
*
640 get_static_insn_data (int icode
, int nop
, int ndup
, int nalt
)
642 struct lra_static_insn_data
*data
;
645 lra_assert (icode
< LAST_INSN_CODE
);
646 if (icode
>= 0 && (data
= insn_code_data
[icode
]) != NULL
)
648 lra_assert (nop
>= 0 && ndup
>= 0 && nalt
>= 0);
649 n_bytes
= sizeof (struct lra_static_insn_data
)
650 + sizeof (struct lra_operand_data
) * nop
651 + sizeof (int) * ndup
;
652 data
= XNEWVAR (struct lra_static_insn_data
, n_bytes
);
653 data
->n_operands
= nop
;
655 data
->n_alternatives
= nalt
;
656 data
->operand
= ((struct lra_operand_data
*)
657 ((char *) data
+ sizeof (struct lra_static_insn_data
)));
658 data
->dup_num
= ((int *) ((char *) data
->operand
659 + sizeof (struct lra_operand_data
) * nop
));
664 insn_code_data
[icode
] = data
;
665 for (i
= 0; i
< nop
; i
++)
667 data
->operand
[i
].constraint
668 = insn_data
[icode
].operand
[i
].constraint
;
669 data
->operand
[i
].mode
= insn_data
[icode
].operand
[i
].mode
;
670 data
->operand
[i
].strict_low
= insn_data
[icode
].operand
[i
].strict_low
;
671 data
->operand
[i
].is_operator
672 = insn_data
[icode
].operand
[i
].is_operator
;
673 data
->operand
[i
].type
674 = (data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
675 : data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
677 data
->operand
[i
].is_address
= false;
679 for (i
= 0; i
< ndup
; i
++)
680 data
->dup_num
[i
] = recog_data
.dup_num
[i
];
685 /* The current length of the following array. */
686 int lra_insn_recog_data_len
;
688 /* Map INSN_UID -> the insn recog data (NULL if unknown). */
689 lra_insn_recog_data_t
*lra_insn_recog_data
;
691 /* Initialize LRA data about insns. */
693 init_insn_recog_data (void)
695 lra_insn_recog_data_len
= 0;
696 lra_insn_recog_data
= NULL
;
700 /* Expand, if necessary, LRA data about insns. */
702 check_and_expand_insn_recog_data (int index
)
706 if (lra_insn_recog_data_len
> index
)
708 old
= lra_insn_recog_data_len
;
709 lra_insn_recog_data_len
= index
* 3 / 2 + 1;
710 lra_insn_recog_data
= XRESIZEVEC (lra_insn_recog_data_t
,
712 lra_insn_recog_data_len
);
713 for (i
= old
; i
< lra_insn_recog_data_len
; i
++)
714 lra_insn_recog_data
[i
] = NULL
;
717 /* Finish LRA DATA about insn. */
719 free_insn_recog_data (lra_insn_recog_data_t data
)
721 if (data
->operand_loc
!= NULL
)
722 free (data
->operand_loc
);
723 if (data
->dup_loc
!= NULL
)
724 free (data
->dup_loc
);
725 if (data
->arg_hard_regs
!= NULL
)
726 free (data
->arg_hard_regs
);
727 if (data
->icode
< 0 && NONDEBUG_INSN_P (data
->insn
))
729 if (data
->insn_static_data
->operand_alternative
!= NULL
)
730 free (data
->insn_static_data
->operand_alternative
);
731 free_insn_regs (data
->insn_static_data
->hard_regs
);
732 free (data
->insn_static_data
);
734 free_insn_regs (data
->regs
);
739 /* Finish LRA data about all insns. */
741 finish_insn_recog_data (void)
744 lra_insn_recog_data_t data
;
746 for (i
= 0; i
< lra_insn_recog_data_len
; i
++)
747 if ((data
= lra_insn_recog_data
[i
]) != NULL
)
748 free_insn_recog_data (data
);
750 free (lra_insn_recog_data
);
753 /* Setup info about operands in alternatives of LRA DATA of insn. */
755 setup_operand_alternative (lra_insn_recog_data_t data
)
758 int icode
= data
->icode
;
759 struct lra_static_insn_data
*static_data
= data
->insn_static_data
;
762 && (static_data
->operand_alternative
= op_alt_data
[icode
]) != NULL
)
764 static_data
->commutative
= -1;
765 nop
= static_data
->n_operands
;
768 static_data
->operand_alternative
= NULL
;
771 nalt
= static_data
->n_alternatives
;
772 static_data
->operand_alternative
= XNEWVEC (struct operand_alternative
,
774 memset (static_data
->operand_alternative
, 0,
775 nalt
* nop
* sizeof (struct operand_alternative
));
777 op_alt_data
[icode
] = static_data
->operand_alternative
;
778 for (i
= 0; i
< nop
; i
++)
781 struct operand_alternative
*op_alt_start
, *op_alt
;
782 const char *p
= static_data
->operand
[i
].constraint
;
784 static_data
->operand
[i
].early_clobber
= 0;
785 op_alt_start
= &static_data
->operand_alternative
[i
];
787 for (j
= 0; j
< nalt
; j
++)
789 op_alt
= op_alt_start
+ j
* nop
;
790 op_alt
->cl
= NO_REGS
;
791 op_alt
->constraint
= p
;
792 op_alt
->matches
= -1;
793 op_alt
->matched
= -1;
795 if (*p
== '\0' || *p
== ',')
797 op_alt
->anything_ok
= 1;
807 while (c
!= ',' && c
!= '\0');
808 if (c
== ',' || c
== '\0')
816 case '=': case '+': case '*':
817 case 'E': case 'F': case 'G': case 'H':
818 case 's': case 'i': case 'n':
819 case 'I': case 'J': case 'K': case 'L':
820 case 'M': case 'N': case 'O': case 'P':
821 /* These don't say anything we care about. */
825 /* We currently only support one commutative pair of
827 if (static_data
->commutative
< 0)
828 static_data
->commutative
= i
;
830 lra_assert (data
->icode
< 0); /* Asm */
832 /* The last operand should not be marked
834 lra_assert (i
!= nop
- 1);
838 op_alt
->reject
+= LRA_LOSER_COST_FACTOR
;
841 op_alt
->reject
+= LRA_MAX_REJECT
;
844 op_alt
->earlyclobber
= 1;
845 static_data
->operand
[i
].early_clobber
= 1;
848 case '0': case '1': case '2': case '3': case '4':
849 case '5': case '6': case '7': case '8': case '9':
852 op_alt
->matches
= strtoul (p
, &end
, 10);
853 static_data
->operand_alternative
854 [j
* nop
+ op_alt
->matches
].matched
= i
;
859 case TARGET_MEM_CONSTRAINT
:
860 op_alt
->memory_ok
= 1;
863 op_alt
->decmem_ok
= 1;
866 op_alt
->incmem_ok
= 1;
869 op_alt
->nonoffmem_ok
= 1;
872 op_alt
->offmem_ok
= 1;
875 op_alt
->anything_ok
= 1;
879 static_data
->operand
[i
].is_address
= true;
880 op_alt
->is_address
= 1;
881 op_alt
->cl
= (reg_class_subunion
[(int) op_alt
->cl
]
882 [(int) base_reg_class (VOIDmode
,
890 reg_class_subunion
[(int) op_alt
->cl
][(int) GENERAL_REGS
];
894 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
896 op_alt
->memory_ok
= 1;
899 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
901 static_data
->operand
[i
].is_address
= true;
902 op_alt
->is_address
= 1;
904 = (reg_class_subunion
906 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
912 = (reg_class_subunion
915 REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
918 p
+= CONSTRAINT_LEN (c
, p
);
924 /* Recursively process X and collect info about registers, which are
925 not the insn operands, in X with TYPE (in/out/inout) and flag that
926 it is early clobbered in the insn (EARLY_CLOBBER) and add the info
927 to LIST. X is a part of insn given by DATA. Return the result
929 static struct lra_insn_reg
*
930 collect_non_operand_hard_regs (rtx
*x
, lra_insn_recog_data_t data
,
931 struct lra_insn_reg
*list
,
932 enum op_type type
, bool early_clobber
)
934 int i
, j
, regno
, last
;
936 enum machine_mode mode
;
937 struct lra_insn_reg
*curr
;
939 enum rtx_code code
= GET_CODE (op
);
940 const char *fmt
= GET_RTX_FORMAT (code
);
942 for (i
= 0; i
< data
->insn_static_data
->n_operands
; i
++)
943 if (x
== data
->operand_loc
[i
])
944 /* It is an operand loc. Stop here. */
946 for (i
= 0; i
< data
->insn_static_data
->n_dups
; i
++)
947 if (x
== data
->dup_loc
[i
])
948 /* It is a dup loc. Stop here. */
950 mode
= GET_MODE (op
);
954 op
= SUBREG_REG (op
);
955 code
= GET_CODE (op
);
956 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (op
)))
958 mode
= GET_MODE (op
);
959 if (GET_MODE_SIZE (mode
) > REGMODE_NATURAL_SIZE (mode
))
965 if ((regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
)
967 for (last
= regno
+ hard_regno_nregs
[regno
][mode
];
970 if (! TEST_HARD_REG_BIT (lra_no_alloc_regs
, regno
)
971 || TEST_HARD_REG_BIT (eliminable_regset
, regno
))
973 for (curr
= list
; curr
!= NULL
; curr
= curr
->next
)
974 if (curr
->regno
== regno
&& curr
->subreg_p
== subreg_p
975 && curr
->biggest_mode
== mode
)
977 if (curr
->type
!= type
)
978 curr
->type
= OP_INOUT
;
979 if (curr
->early_clobber
!= early_clobber
)
980 curr
->early_clobber
= true;
985 /* This is a new hard regno or the info can not be
986 integrated into the found structure. */
990 /* This clobber is to inform popping floating
992 && ! (FIRST_STACK_REG
<= regno
993 && regno
<= LAST_STACK_REG
));
995 list
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
996 early_clobber
, list
);
1004 list
= collect_non_operand_hard_regs (&SET_DEST (op
), data
,
1005 list
, OP_OUT
, false);
1006 list
= collect_non_operand_hard_regs (&SET_SRC (op
), data
,
1007 list
, OP_IN
, false);
1010 /* We treat clobber of non-operand hard registers as early
1011 clobber (the behavior is expected from asm). */
1012 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
1013 list
, OP_OUT
, true);
1015 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
1016 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
1017 list
, OP_INOUT
, false);
1019 case PRE_MODIFY
: case POST_MODIFY
:
1020 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
1021 list
, OP_INOUT
, false);
1022 list
= collect_non_operand_hard_regs (&XEXP (op
, 1), data
,
1023 list
, OP_IN
, false);
1026 fmt
= GET_RTX_FORMAT (code
);
1027 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1030 list
= collect_non_operand_hard_regs (&XEXP (op
, i
), data
,
1031 list
, OP_IN
, false);
1032 else if (fmt
[i
] == 'E')
1033 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
1034 list
= collect_non_operand_hard_regs (&XVECEXP (op
, i
, j
), data
,
1035 list
, OP_IN
, false);
1041 /* Set up and return info about INSN. Set up the info if it is not set up
1043 lra_insn_recog_data_t
1044 lra_set_insn_recog_data (rtx insn
)
1046 lra_insn_recog_data_t data
;
1049 unsigned int uid
= INSN_UID (insn
);
1050 struct lra_static_insn_data
*insn_static_data
;
1052 check_and_expand_insn_recog_data (uid
);
1053 if (DEBUG_INSN_P (insn
))
1057 icode
= INSN_CODE (insn
);
1059 /* It might be a new simple insn which is not recognized yet. */
1060 INSN_CODE (insn
) = icode
= recog_memoized (insn
);
1062 data
= XNEW (struct lra_insn_recog_data
);
1063 lra_insn_recog_data
[uid
] = data
;
1065 data
->used_insn_alternative
= -1;
1066 data
->icode
= icode
;
1068 if (DEBUG_INSN_P (insn
))
1070 data
->insn_static_data
= &debug_insn_static_data
;
1071 data
->dup_loc
= NULL
;
1072 data
->arg_hard_regs
= NULL
;
1073 data
->enabled_alternatives
= ALL_ALTERNATIVES
;
1074 data
->operand_loc
= XNEWVEC (rtx
*, 1);
1075 data
->operand_loc
[0] = &INSN_VAR_LOCATION_LOC (insn
);
1081 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1082 const char *constraints
[MAX_RECOG_OPERANDS
];
1084 nop
= asm_noperands (PATTERN (insn
));
1085 data
->operand_loc
= data
->dup_loc
= NULL
;
1088 /* Its is a special insn like USE or CLOBBER. We should
1089 recognize any regular insn otherwise LRA can do nothing
1091 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
1092 || GET_CODE (PATTERN (insn
)) == CLOBBER
1093 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
1094 data
->insn_static_data
= insn_static_data
1095 = get_static_insn_data (-1, 0, 0, 1);
1099 /* expand_asm_operands makes sure there aren't too many
1101 lra_assert (nop
<= MAX_RECOG_OPERANDS
);
1103 data
->operand_loc
= XNEWVEC (rtx
*, nop
);
1104 /* Now get the operand values and constraints out of the
1106 decode_asm_operands (PATTERN (insn
), NULL
,
1108 constraints
, operand_mode
, NULL
);
1112 const char *p
= recog_data
.constraints
[0];
1114 for (p
= constraints
[0]; *p
; p
++)
1117 data
->insn_static_data
= insn_static_data
1118 = get_static_insn_data (-1, nop
, 0, n
);
1119 for (i
= 0; i
< nop
; i
++)
1121 insn_static_data
->operand
[i
].mode
= operand_mode
[i
];
1122 insn_static_data
->operand
[i
].constraint
= constraints
[i
];
1123 insn_static_data
->operand
[i
].strict_low
= false;
1124 insn_static_data
->operand
[i
].is_operator
= false;
1125 insn_static_data
->operand
[i
].is_address
= false;
1128 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1129 insn_static_data
->operand
[i
].type
1130 = (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1131 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1133 data
->enabled_alternatives
= ALL_ALTERNATIVES
;
1137 insn_extract (insn
);
1138 data
->insn_static_data
= insn_static_data
1139 = get_static_insn_data (icode
, insn_data
[icode
].n_operands
,
1140 insn_data
[icode
].n_dups
,
1141 insn_data
[icode
].n_alternatives
);
1142 n
= insn_static_data
->n_operands
;
1147 locs
= XNEWVEC (rtx
*, n
);
1148 memcpy (locs
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1150 data
->operand_loc
= locs
;
1151 n
= insn_static_data
->n_dups
;
1156 locs
= XNEWVEC (rtx
*, n
);
1157 memcpy (locs
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1159 data
->dup_loc
= locs
;
1160 data
->enabled_alternatives
= get_enabled_alternatives (insn
);
1162 if (GET_CODE (PATTERN (insn
)) == CLOBBER
|| GET_CODE (PATTERN (insn
)) == USE
)
1163 insn_static_data
->hard_regs
= NULL
;
1165 insn_static_data
->hard_regs
1166 = collect_non_operand_hard_regs (&PATTERN (insn
), data
,
1167 NULL
, OP_IN
, false);
1168 setup_operand_alternative (data
);
1169 data
->arg_hard_regs
= NULL
;
1173 int n_hard_regs
, regno
, arg_hard_regs
[FIRST_PSEUDO_REGISTER
];
1176 /* Finding implicit hard register usage. We believe it will be
1177 not changed whatever transformations are used. Call insns
1178 are such example. */
1179 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
1181 link
= XEXP (link
, 1))
1182 if (GET_CODE (XEXP (link
, 0)) == USE
1183 && REG_P (XEXP (XEXP (link
, 0), 0)))
1185 regno
= REGNO (XEXP (XEXP (link
, 0), 0));
1186 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
1187 /* It is an argument register. */
1188 for (i
= (hard_regno_nregs
1189 [regno
][GET_MODE (XEXP (XEXP (link
, 0), 0))]) - 1;
1192 arg_hard_regs
[n_hard_regs
++] = regno
+ i
;
1194 if (n_hard_regs
!= 0)
1196 arg_hard_regs
[n_hard_regs
++] = -1;
1197 data
->arg_hard_regs
= XNEWVEC (int, n_hard_regs
);
1198 memcpy (data
->arg_hard_regs
, arg_hard_regs
,
1199 sizeof (int) * n_hard_regs
);
1202 /* Some output operand can be recognized only from the context not
1203 from the constraints which are empty in this case. Call insn may
1204 contain a hard register in set destination with empty constraint
1205 and extract_insn treats them as an input. */
1206 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1210 struct lra_operand_data
*operand
= &insn_static_data
->operand
[i
];
1212 /* ??? Should we treat 'X' the same way. It looks to me that
1213 'X' means anything and empty constraint means we do not
1215 if (operand
->type
!= OP_IN
|| *operand
->constraint
!= '\0'
1216 || operand
->is_operator
)
1218 pat
= PATTERN (insn
);
1219 if (GET_CODE (pat
) == SET
)
1221 if (data
->operand_loc
[i
] != &SET_DEST (pat
))
1224 else if (GET_CODE (pat
) == PARALLEL
)
1226 for (j
= XVECLEN (pat
, 0) - 1; j
>= 0; j
--)
1228 set
= XVECEXP (PATTERN (insn
), 0, j
);
1229 if (GET_CODE (set
) == SET
1230 && &SET_DEST (set
) == data
->operand_loc
[i
])
1238 operand
->type
= OP_OUT
;
1243 /* Return info about insn give by UID. The info should be already set
1245 static lra_insn_recog_data_t
1246 get_insn_recog_data_by_uid (int uid
)
1248 lra_insn_recog_data_t data
;
1250 data
= lra_insn_recog_data
[uid
];
1251 lra_assert (data
!= NULL
);
1255 /* Invalidate all info about insn given by its UID. */
1257 invalidate_insn_recog_data (int uid
)
1259 lra_insn_recog_data_t data
;
1261 data
= lra_insn_recog_data
[uid
];
1262 lra_assert (data
!= NULL
);
1263 free_insn_recog_data (data
);
1264 lra_insn_recog_data
[uid
] = NULL
;
1267 /* Update all the insn info about INSN. It is usually called when
1268 something in the insn was changed. Return the updated info. */
1269 lra_insn_recog_data_t
1270 lra_update_insn_recog_data (rtx insn
)
1272 lra_insn_recog_data_t data
;
1274 unsigned int uid
= INSN_UID (insn
);
1275 struct lra_static_insn_data
*insn_static_data
;
1276 HOST_WIDE_INT sp_offset
= 0;
1278 check_and_expand_insn_recog_data (uid
);
1279 if ((data
= lra_insn_recog_data
[uid
]) != NULL
1280 && data
->icode
!= INSN_CODE (insn
))
1282 sp_offset
= data
->sp_offset
;
1283 invalidate_insn_data_regno_info (data
, insn
, get_insn_freq (insn
));
1284 invalidate_insn_recog_data (uid
);
1289 data
= lra_get_insn_recog_data (insn
);
1290 /* Initiate or restore SP offset. */
1291 data
->sp_offset
= sp_offset
;
1294 insn_static_data
= data
->insn_static_data
;
1295 data
->used_insn_alternative
= -1;
1296 if (DEBUG_INSN_P (insn
))
1298 if (data
->icode
< 0)
1301 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1302 const char *constraints
[MAX_RECOG_OPERANDS
];
1304 nop
= asm_noperands (PATTERN (insn
));
1307 lra_assert (nop
== data
->insn_static_data
->n_operands
);
1308 /* Now get the operand values and constraints out of the
1310 decode_asm_operands (PATTERN (insn
), NULL
,
1312 constraints
, operand_mode
, NULL
);
1313 #ifdef ENABLE_CHECKING
1317 for (i
= 0; i
< nop
; i
++)
1319 (insn_static_data
->operand
[i
].mode
== operand_mode
[i
]
1320 && insn_static_data
->operand
[i
].constraint
== constraints
[i
]
1321 && ! insn_static_data
->operand
[i
].is_operator
);
1325 #ifdef ENABLE_CHECKING
1329 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1331 (insn_static_data
->operand
[i
].type
1332 == (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1333 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1340 insn_extract (insn
);
1341 n
= insn_static_data
->n_operands
;
1343 memcpy (data
->operand_loc
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1344 n
= insn_static_data
->n_dups
;
1346 memcpy (data
->dup_loc
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1347 #if HAVE_ATTR_enabled
1348 #ifdef ENABLE_CHECKING
1351 alternative_mask enabled
;
1353 n
= insn_static_data
->n_alternatives
;
1354 enabled
= data
->enabled_alternatives
;
1355 lra_assert (n
>= 0);
1356 /* Cache the insn to prevent extract_insn call from
1357 get_attr_enabled. */
1358 recog_data
.insn
= insn
;
1359 for (i
= 0; i
< n
; i
++)
1361 which_alternative
= i
;
1362 lra_assert (TEST_BIT (enabled
, i
)
1363 == (bool) get_attr_enabled (insn
));
1372 /* Set up that INSN is using alternative ALT now. */
1374 lra_set_used_insn_alternative (rtx insn
, int alt
)
1376 lra_insn_recog_data_t data
;
1378 data
= lra_get_insn_recog_data (insn
);
1379 data
->used_insn_alternative
= alt
;
1382 /* Set up that insn with UID is using alternative ALT now. The insn
1383 info should be already set up. */
1385 lra_set_used_insn_alternative_by_uid (int uid
, int alt
)
1387 lra_insn_recog_data_t data
;
1389 check_and_expand_insn_recog_data (uid
);
1390 data
= lra_insn_recog_data
[uid
];
1391 lra_assert (data
!= NULL
);
1392 data
->used_insn_alternative
= alt
;
1397 /* This page contains code dealing with common register info and
1400 /* The size of the following array. */
1401 static int reg_info_size
;
1402 /* Common info about each register. */
1403 struct lra_reg
*lra_reg_info
;
1405 /* Last register value. */
1406 static int last_reg_value
;
1408 /* Return new register value. */
1410 get_new_reg_value (void)
1412 return ++last_reg_value
;
1415 /* Pools for copies. */
1416 static alloc_pool copy_pool
;
1418 /* Vec referring to pseudo copies. */
1419 static vec
<lra_copy_t
> copy_vec
;
1421 /* Initialize I-th element of lra_reg_info. */
1423 initialize_lra_reg_info_element (int i
)
1425 bitmap_initialize (&lra_reg_info
[i
].insn_bitmap
, ®_obstack
);
1427 lra_reg_info
[i
].no_stack_p
= false;
1429 CLEAR_HARD_REG_SET (lra_reg_info
[i
].conflict_hard_regs
);
1430 CLEAR_HARD_REG_SET (lra_reg_info
[i
].actual_call_used_reg_set
);
1431 lra_reg_info
[i
].preferred_hard_regno1
= -1;
1432 lra_reg_info
[i
].preferred_hard_regno2
= -1;
1433 lra_reg_info
[i
].preferred_hard_regno_profit1
= 0;
1434 lra_reg_info
[i
].preferred_hard_regno_profit2
= 0;
1435 lra_reg_info
[i
].biggest_mode
= VOIDmode
;
1436 lra_reg_info
[i
].live_ranges
= NULL
;
1437 lra_reg_info
[i
].nrefs
= lra_reg_info
[i
].freq
= 0;
1438 lra_reg_info
[i
].last_reload
= 0;
1439 lra_reg_info
[i
].restore_regno
= -1;
1440 lra_reg_info
[i
].val
= get_new_reg_value ();
1441 lra_reg_info
[i
].offset
= 0;
1442 lra_reg_info
[i
].copies
= NULL
;
1445 /* Initialize common reg info and copies. */
1447 init_reg_info (void)
1452 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1453 lra_reg_info
= XNEWVEC (struct lra_reg
, reg_info_size
);
1454 for (i
= 0; i
< reg_info_size
; i
++)
1455 initialize_lra_reg_info_element (i
);
1457 = create_alloc_pool ("lra copies", sizeof (struct lra_copy
), 100);
1458 copy_vec
.create (100);
1462 /* Finish common reg info and copies. */
1464 finish_reg_info (void)
1468 for (i
= 0; i
< reg_info_size
; i
++)
1469 bitmap_clear (&lra_reg_info
[i
].insn_bitmap
);
1470 free (lra_reg_info
);
1472 free_alloc_pool (copy_pool
);
1473 copy_vec
.release ();
1476 /* Expand common reg info if it is necessary. */
1478 expand_reg_info (void)
1480 int i
, old
= reg_info_size
;
1482 if (reg_info_size
> max_reg_num ())
1484 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1485 lra_reg_info
= XRESIZEVEC (struct lra_reg
, lra_reg_info
, reg_info_size
);
1486 for (i
= old
; i
< reg_info_size
; i
++)
1487 initialize_lra_reg_info_element (i
);
1490 /* Free all copies. */
1492 lra_free_copies (void)
1496 while (copy_vec
.length () != 0)
1498 cp
= copy_vec
.pop ();
1499 lra_reg_info
[cp
->regno1
].copies
= lra_reg_info
[cp
->regno2
].copies
= NULL
;
1500 pool_free (copy_pool
, cp
);
1504 /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution
1505 frequency is FREQ. */
1507 lra_create_copy (int regno1
, int regno2
, int freq
)
1512 lra_assert (regno1
!= regno2
);
1513 regno1_dest_p
= true;
1514 if (regno1
> regno2
)
1518 regno1_dest_p
= false;
1522 cp
= (lra_copy_t
) pool_alloc (copy_pool
);
1523 copy_vec
.safe_push (cp
);
1524 cp
->regno1_dest_p
= regno1_dest_p
;
1526 cp
->regno1
= regno1
;
1527 cp
->regno2
= regno2
;
1528 cp
->regno1_next
= lra_reg_info
[regno1
].copies
;
1529 lra_reg_info
[regno1
].copies
= cp
;
1530 cp
->regno2_next
= lra_reg_info
[regno2
].copies
;
1531 lra_reg_info
[regno2
].copies
= cp
;
1532 if (lra_dump_file
!= NULL
)
1533 fprintf (lra_dump_file
, " Creating copy r%d%sr%d@%d\n",
1534 regno1
, regno1_dest_p
? "<-" : "->", regno2
, freq
);
1537 /* Return N-th (0, 1, ...) copy. If there is no copy, return
1540 lra_get_copy (int n
)
1542 if (n
>= (int) copy_vec
.length ())
1549 /* This page contains code dealing with info about registers in
1552 /* Process X of insn UID recursively and add info (operand type is
1553 given by TYPE, flag of that it is early clobber is EARLY_CLOBBER)
1554 about registers in X to the insn DATA. */
1556 add_regs_to_insn_regno_info (lra_insn_recog_data_t data
, rtx x
, int uid
,
1557 enum op_type type
, bool early_clobber
)
1561 enum machine_mode mode
;
1564 struct lra_insn_reg
*curr
;
1566 code
= GET_CODE (x
);
1567 mode
= GET_MODE (x
);
1569 if (GET_CODE (x
) == SUBREG
)
1572 code
= GET_CODE (x
);
1573 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
)))
1575 mode
= GET_MODE (x
);
1576 if (GET_MODE_SIZE (mode
) > REGMODE_NATURAL_SIZE (mode
))
1583 if (regno
< FIRST_PSEUDO_REGISTER
1584 && TEST_HARD_REG_BIT (lra_no_alloc_regs
, regno
)
1585 && ! TEST_HARD_REG_BIT (eliminable_regset
, regno
))
1588 if (bitmap_set_bit (&lra_reg_info
[regno
].insn_bitmap
, uid
))
1590 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
1591 early_clobber
, data
->regs
);
1596 for (curr
= data
->regs
; curr
!= NULL
; curr
= curr
->next
)
1597 if (curr
->regno
== regno
)
1599 if (curr
->subreg_p
!= subreg_p
|| curr
->biggest_mode
!= mode
)
1600 /* The info can not be integrated into the found
1602 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
,
1603 subreg_p
, early_clobber
,
1607 if (curr
->type
!= type
)
1608 curr
->type
= OP_INOUT
;
1609 if (curr
->early_clobber
!= early_clobber
)
1610 curr
->early_clobber
= true;
1621 add_regs_to_insn_regno_info (data
, SET_DEST (x
), uid
, OP_OUT
, false);
1622 add_regs_to_insn_regno_info (data
, SET_SRC (x
), uid
, OP_IN
, false);
1625 /* We treat clobber of non-operand hard registers as early
1626 clobber (the behavior is expected from asm). */
1627 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_OUT
, true);
1629 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
1630 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_INOUT
, false);
1632 case PRE_MODIFY
: case POST_MODIFY
:
1633 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_INOUT
, false);
1634 add_regs_to_insn_regno_info (data
, XEXP (x
, 1), uid
, OP_IN
, false);
1637 if ((code
!= PARALLEL
&& code
!= EXPR_LIST
) || type
!= OP_OUT
)
1638 /* Some targets place small structures in registers for return
1639 values of functions, and those registers are wrapped in
1640 PARALLEL that we may see as the destination of a SET. Here
1643 (call_insn 13 12 14 2 (set (parallel:BLK [
1644 (expr_list:REG_DEP_TRUE (reg:DI 0 ax)
1646 (expr_list:REG_DEP_TRUE (reg:DI 1 dx)
1647 (const_int 8 [0x8]))
1649 (call (mem:QI (symbol_ref:DI (... */
1651 fmt
= GET_RTX_FORMAT (code
);
1652 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1655 add_regs_to_insn_regno_info (data
, XEXP (x
, i
), uid
, type
, false);
1656 else if (fmt
[i
] == 'E')
1658 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1659 add_regs_to_insn_regno_info (data
, XVECEXP (x
, i
, j
), uid
,
1666 /* Return execution frequency of INSN. */
1668 get_insn_freq (rtx insn
)
1670 basic_block bb
= BLOCK_FOR_INSN (insn
);
1672 gcc_checking_assert (bb
!= NULL
);
1673 return REG_FREQ_FROM_BB (bb
);
1676 /* Invalidate all reg info of INSN with DATA and execution frequency
1677 FREQ. Update common info about the invalidated registers. */
1679 invalidate_insn_data_regno_info (lra_insn_recog_data_t data
, rtx insn
,
1685 struct lra_insn_reg
*ir
, *next_ir
;
1687 uid
= INSN_UID (insn
);
1688 debug_p
= DEBUG_INSN_P (insn
);
1689 for (ir
= data
->regs
; ir
!= NULL
; ir
= next_ir
)
1694 bitmap_clear_bit (&lra_reg_info
[i
].insn_bitmap
, uid
);
1695 if (i
>= FIRST_PSEUDO_REGISTER
&& ! debug_p
)
1697 lra_reg_info
[i
].nrefs
--;
1698 lra_reg_info
[i
].freq
-= freq
;
1699 lra_assert (lra_reg_info
[i
].nrefs
>= 0 && lra_reg_info
[i
].freq
>= 0);
1705 /* Invalidate all reg info of INSN. Update common info about the
1706 invalidated registers. */
1708 lra_invalidate_insn_regno_info (rtx insn
)
1710 invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn
), insn
,
1711 get_insn_freq (insn
));
1714 /* Update common reg info from reg info of insn given by its DATA and
1715 execution frequency FREQ. */
1717 setup_insn_reg_info (lra_insn_recog_data_t data
, int freq
)
1720 struct lra_insn_reg
*ir
;
1722 for (ir
= data
->regs
; ir
!= NULL
; ir
= ir
->next
)
1723 if ((i
= ir
->regno
) >= FIRST_PSEUDO_REGISTER
)
1725 lra_reg_info
[i
].nrefs
++;
1726 lra_reg_info
[i
].freq
+= freq
;
1730 /* Set up insn reg info of INSN. Update common reg info from reg info
1733 lra_update_insn_regno_info (rtx insn
)
1736 lra_insn_recog_data_t data
;
1737 struct lra_static_insn_data
*static_data
;
1740 if (! INSN_P (insn
))
1742 data
= lra_get_insn_recog_data (insn
);
1743 static_data
= data
->insn_static_data
;
1744 freq
= get_insn_freq (insn
);
1745 invalidate_insn_data_regno_info (data
, insn
, freq
);
1746 uid
= INSN_UID (insn
);
1747 for (i
= static_data
->n_operands
- 1; i
>= 0; i
--)
1748 add_regs_to_insn_regno_info (data
, *data
->operand_loc
[i
], uid
,
1749 static_data
->operand
[i
].type
,
1750 static_data
->operand
[i
].early_clobber
);
1751 if ((code
= GET_CODE (PATTERN (insn
))) == CLOBBER
|| code
== USE
)
1752 add_regs_to_insn_regno_info (data
, XEXP (PATTERN (insn
), 0), uid
,
1753 code
== USE
? OP_IN
: OP_OUT
, false);
1754 if (NONDEBUG_INSN_P (insn
))
1755 setup_insn_reg_info (data
, freq
);
1758 /* Return reg info of insn given by it UID. */
1759 struct lra_insn_reg
*
1760 lra_get_insn_regs (int uid
)
1762 lra_insn_recog_data_t data
;
1764 data
= get_insn_recog_data_by_uid (uid
);
1770 /* This page contains code dealing with stack of the insns which
1771 should be processed by the next constraint pass. */
1773 /* Bitmap used to put an insn on the stack only in one exemplar. */
1774 static sbitmap lra_constraint_insn_stack_bitmap
;
1776 /* The stack itself. */
1777 vec
<rtx
> lra_constraint_insn_stack
;
1779 /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg
1780 info for INSN, otherwise only update it if INSN is not already on the
1783 lra_push_insn_1 (rtx insn
, bool always_update
)
1785 unsigned int uid
= INSN_UID (insn
);
1787 lra_update_insn_regno_info (insn
);
1788 if (uid
>= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap
))
1789 lra_constraint_insn_stack_bitmap
=
1790 sbitmap_resize (lra_constraint_insn_stack_bitmap
, 3 * uid
/ 2, 0);
1791 if (bitmap_bit_p (lra_constraint_insn_stack_bitmap
, uid
))
1793 bitmap_set_bit (lra_constraint_insn_stack_bitmap
, uid
);
1794 if (! always_update
)
1795 lra_update_insn_regno_info (insn
);
1796 lra_constraint_insn_stack
.safe_push (insn
);
1799 /* Put INSN on the stack. */
1801 lra_push_insn (rtx insn
)
1803 lra_push_insn_1 (insn
, false);
1806 /* Put INSN on the stack and update its reg info. */
1808 lra_push_insn_and_update_insn_regno_info (rtx insn
)
1810 lra_push_insn_1 (insn
, true);
1813 /* Put insn with UID on the stack. */
1815 lra_push_insn_by_uid (unsigned int uid
)
1817 lra_push_insn (lra_insn_recog_data
[uid
]->insn
);
1820 /* Take the last-inserted insns off the stack and return it. */
1824 rtx insn
= lra_constraint_insn_stack
.pop ();
1825 bitmap_clear_bit (lra_constraint_insn_stack_bitmap
, INSN_UID (insn
));
1829 /* Return the current size of the insn stack. */
1831 lra_insn_stack_length (void)
1833 return lra_constraint_insn_stack
.length ();
1836 /* Push insns FROM to TO (excluding it) going in reverse order. */
1838 push_insns (rtx from
, rtx to
)
1842 if (from
== NULL_RTX
)
1844 for (insn
= from
; insn
!= to
; insn
= PREV_INSN (insn
))
1846 lra_push_insn (insn
);
1849 /* Set up sp offset for insn in range [FROM, LAST]. The offset is
1850 taken from the next BB insn after LAST or zero if there in such
1853 setup_sp_offset (rtx from
, rtx last
)
1855 rtx before
= next_nonnote_insn_bb (last
);
1856 HOST_WIDE_INT offset
= (before
== NULL_RTX
|| ! INSN_P (before
)
1857 ? 0 : lra_get_insn_recog_data (before
)->sp_offset
);
1859 for (rtx insn
= from
; insn
!= NEXT_INSN (last
); insn
= NEXT_INSN (insn
))
1860 lra_get_insn_recog_data (insn
)->sp_offset
= offset
;
1863 /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the
1864 insns onto the stack. Print about emitting the insns with
1867 lra_process_new_insns (rtx insn
, rtx before
, rtx after
, const char *title
)
1871 if (before
== NULL_RTX
&& after
== NULL_RTX
)
1873 if (lra_dump_file
!= NULL
)
1875 dump_insn_slim (lra_dump_file
, insn
);
1876 if (before
!= NULL_RTX
)
1878 fprintf (lra_dump_file
," %s before:\n", title
);
1879 dump_rtl_slim (lra_dump_file
, before
, NULL_RTX
, -1, 0);
1881 if (after
!= NULL_RTX
)
1883 fprintf (lra_dump_file
, " %s after:\n", title
);
1884 dump_rtl_slim (lra_dump_file
, after
, NULL_RTX
, -1, 0);
1886 fprintf (lra_dump_file
, "\n");
1888 if (before
!= NULL_RTX
)
1890 emit_insn_before (before
, insn
);
1891 push_insns (PREV_INSN (insn
), PREV_INSN (before
));
1892 setup_sp_offset (before
, PREV_INSN (insn
));
1894 if (after
!= NULL_RTX
)
1896 for (last
= after
; NEXT_INSN (last
) != NULL_RTX
; last
= NEXT_INSN (last
))
1898 emit_insn_after (after
, insn
);
1899 push_insns (last
, insn
);
1900 setup_sp_offset (after
, last
);
1906 /* This page contains code dealing with scratches (changing them onto
1907 pseudos and restoring them from the pseudos).
1909 We change scratches into pseudos at the beginning of LRA to
1910 simplify dealing with them (conflicts, hard register assignments).
1912 If the pseudo denoting scratch was spilled it means that we do need
1913 a hard register for it. Such pseudos are transformed back to
1914 scratches at the end of LRA. */
1916 /* Description of location of a former scratch operand. */
1919 rtx insn
; /* Insn where the scratch was. */
1920 int nop
; /* Number of the operand which was a scratch. */
1923 typedef struct sloc
*sloc_t
;
1925 /* Locations of the former scratches. */
1926 static vec
<sloc_t
> scratches
;
1928 /* Bitmap of scratch regnos. */
1929 static bitmap_head scratch_bitmap
;
1931 /* Bitmap of scratch operands. */
1932 static bitmap_head scratch_operand_bitmap
;
1934 /* Return true if pseudo REGNO is made of SCRATCH. */
1936 lra_former_scratch_p (int regno
)
1938 return bitmap_bit_p (&scratch_bitmap
, regno
);
1941 /* Return true if the operand NOP of INSN is a former scratch. */
1943 lra_former_scratch_operand_p (rtx insn
, int nop
)
1945 return bitmap_bit_p (&scratch_operand_bitmap
,
1946 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ nop
) != 0;
1949 /* Change scratches onto pseudos and save their location. */
1951 remove_scratches (void)
1954 bool insn_changed_p
;
1958 lra_insn_recog_data_t id
;
1959 struct lra_static_insn_data
*static_id
;
1961 scratches
.create (get_max_uid ());
1962 bitmap_initialize (&scratch_bitmap
, ®_obstack
);
1963 bitmap_initialize (&scratch_operand_bitmap
, ®_obstack
);
1964 FOR_EACH_BB_FN (bb
, cfun
)
1965 FOR_BB_INSNS (bb
, insn
)
1968 id
= lra_get_insn_recog_data (insn
);
1969 static_id
= id
->insn_static_data
;
1970 insn_changed_p
= false;
1971 for (i
= 0; i
< static_id
->n_operands
; i
++)
1972 if (GET_CODE (*id
->operand_loc
[i
]) == SCRATCH
1973 && GET_MODE (*id
->operand_loc
[i
]) != VOIDmode
)
1975 insn_changed_p
= true;
1976 *id
->operand_loc
[i
] = reg
1977 = lra_create_new_reg (static_id
->operand
[i
].mode
,
1978 *id
->operand_loc
[i
], ALL_REGS
, NULL
);
1979 add_reg_note (insn
, REG_UNUSED
, reg
);
1980 lra_update_dup (id
, i
);
1981 loc
= XNEW (struct sloc
);
1984 scratches
.safe_push (loc
);
1985 bitmap_set_bit (&scratch_bitmap
, REGNO (*id
->operand_loc
[i
]));
1986 bitmap_set_bit (&scratch_operand_bitmap
,
1987 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ i
);
1988 if (lra_dump_file
!= NULL
)
1989 fprintf (lra_dump_file
,
1990 "Removing SCRATCH in insn #%u (nop %d)\n",
1991 INSN_UID (insn
), i
);
1994 /* Because we might use DF right after caller-saves sub-pass
1995 we need to keep DF info up to date. */
1996 df_insn_rescan (insn
);
2000 /* Changes pseudos created by function remove_scratches onto scratches. */
2002 restore_scratches (void)
2007 rtx last
= NULL_RTX
;
2008 lra_insn_recog_data_t id
= NULL
;
2010 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
2012 if (last
!= loc
->insn
)
2015 id
= lra_get_insn_recog_data (last
);
2017 if (REG_P (*id
->operand_loc
[loc
->nop
])
2018 && ((regno
= REGNO (*id
->operand_loc
[loc
->nop
]))
2019 >= FIRST_PSEUDO_REGISTER
)
2020 && lra_get_regno_hard_regno (regno
) < 0)
2022 /* It should be only case when scratch register with chosen
2023 constraint 'X' did not get memory or hard register. */
2024 lra_assert (lra_former_scratch_p (regno
));
2025 *id
->operand_loc
[loc
->nop
]
2026 = gen_rtx_SCRATCH (GET_MODE (*id
->operand_loc
[loc
->nop
]));
2027 lra_update_dup (id
, loc
->nop
);
2028 if (lra_dump_file
!= NULL
)
2029 fprintf (lra_dump_file
, "Restoring SCRATCH in insn #%u(nop %d)\n",
2030 INSN_UID (loc
->insn
), loc
->nop
);
2033 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
2035 scratches
.release ();
2036 bitmap_clear (&scratch_bitmap
);
2037 bitmap_clear (&scratch_operand_bitmap
);
2042 #ifdef ENABLE_CHECKING
2044 /* Function checks RTL for correctness. If FINAL_P is true, it is
2045 done at the end of LRA and the check is more rigorous. */
2047 check_rtl (bool final_p
)
2052 lra_assert (! final_p
|| reload_completed
);
2053 FOR_EACH_BB_FN (bb
, cfun
)
2054 FOR_BB_INSNS (bb
, insn
)
2055 if (NONDEBUG_INSN_P (insn
)
2056 && GET_CODE (PATTERN (insn
)) != USE
2057 && GET_CODE (PATTERN (insn
)) != CLOBBER
2058 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
)
2062 extract_insn (insn
);
2063 lra_assert (constrain_operands (1));
2066 /* LRA code is based on assumption that all addresses can be
2067 correctly decomposed. LRA can generate reloads for
2068 decomposable addresses. The decomposition code checks the
2069 correctness of the addresses. So we don't need to check
2070 the addresses here. Don't call insn_invalid_p here, it can
2071 change the code at this stage. */
2072 if (recog_memoized (insn
) < 0 && asm_noperands (PATTERN (insn
)) < 0)
2073 fatal_insn_not_found (insn
);
2076 #endif /* #ifdef ENABLE_CHECKING */
2078 /* Determine if the current function has an exception receiver block
2079 that reaches the exit block via non-exceptional edges */
2081 has_nonexceptional_receiver (void)
2085 basic_block
*tos
, *worklist
, bb
;
2087 /* If we're not optimizing, then just err on the safe side. */
2091 /* First determine which blocks can reach exit via normal paths. */
2092 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
2094 FOR_EACH_BB_FN (bb
, cfun
)
2095 bb
->flags
&= ~BB_REACHABLE
;
2097 /* Place the exit block on our worklist. */
2098 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
2099 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
2101 /* Iterate: find everything reachable from what we've already seen. */
2102 while (tos
!= worklist
)
2106 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
2107 if (e
->flags
& EDGE_ABNORMAL
)
2114 basic_block src
= e
->src
;
2116 if (!(src
->flags
& BB_REACHABLE
))
2118 src
->flags
|= BB_REACHABLE
;
2124 /* No exceptional block reached exit unexceptionally. */
2130 /* Process recursively X of INSN and add REG_INC notes if necessary. */
2132 add_auto_inc_notes (rtx insn
, rtx x
)
2134 enum rtx_code code
= GET_CODE (x
);
2138 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
2140 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
2144 /* Scan all X sub-expressions. */
2145 fmt
= GET_RTX_FORMAT (code
);
2146 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2149 add_auto_inc_notes (insn
, XEXP (x
, i
));
2150 else if (fmt
[i
] == 'E')
2151 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2152 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
2158 /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC.
2159 We change pseudos by hard registers without notification of DF and
2160 that can make the notes obsolete. DF-infrastructure does not deal
2161 with REG_INC notes -- so we should regenerate them here. */
2163 update_inc_notes (void)
2169 FOR_EACH_BB_FN (bb
, cfun
)
2170 FOR_BB_INSNS (bb
, insn
)
2171 if (NONDEBUG_INSN_P (insn
))
2173 pnote
= ®_NOTES (insn
);
2176 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
2177 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
2178 || REG_NOTE_KIND (*pnote
) == REG_INC
)
2179 *pnote
= XEXP (*pnote
, 1);
2181 pnote
= &XEXP (*pnote
, 1);
2184 add_auto_inc_notes (insn
, PATTERN (insn
));
2189 /* Set to 1 while in lra. */
2190 int lra_in_progress
;
2192 /* Start of pseudo regnos before the LRA. */
2193 int lra_new_regno_start
;
2195 /* Start of reload pseudo regnos before the new spill pass. */
2196 int lra_constraint_new_regno_start
;
2198 /* Inheritance pseudo regnos before the new spill pass. */
2199 bitmap_head lra_inheritance_pseudos
;
2201 /* Split regnos before the new spill pass. */
2202 bitmap_head lra_split_regs
;
2204 /* Reload pseudo regnos before the new assignmnet pass which still can
2205 be spilled after the assinment pass as memory is also accepted in
2206 insns for the reload pseudos. */
2207 bitmap_head lra_optional_reload_pseudos
;
2209 /* Pseudo regnos used for subreg reloads before the new assignment
2210 pass. Such pseudos still can be spilled after the assinment
2212 bitmap_head lra_subreg_reload_pseudos
;
2214 /* First UID of insns generated before a new spill pass. */
2215 int lra_constraint_new_insn_uid_start
;
2217 /* File used for output of LRA debug information. */
2218 FILE *lra_dump_file
;
2220 /* True if we should try spill into registers of different classes
2221 instead of memory. */
2222 bool lra_reg_spill_p
;
2224 /* Set up value LRA_REG_SPILL_P. */
2226 setup_reg_spill_flag (void)
2230 if (targetm
.spill_class
!= NULL
)
2231 for (cl
= 0; cl
< (int) LIM_REG_CLASSES
; cl
++)
2232 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
2233 if (targetm
.spill_class ((enum reg_class
) cl
,
2234 (enum machine_mode
) mode
) != NO_REGS
)
2236 lra_reg_spill_p
= true;
2239 lra_reg_spill_p
= false;
2242 /* True if the current function is too big to use regular algorithms
2243 in LRA. In other words, we should use simpler and faster algorithms
2244 in LRA. It also means we should not worry about generation code
2245 for caller saves. The value is set up in IRA. */
2248 /* Major LRA entry function. F is a file should be used to dump LRA
2254 bool live_p
, scratch_p
, inserted_p
;
2258 timevar_push (TV_LRA
);
2260 /* Make sure that the last insn is a note. Some subsequent passes
2262 emit_note (NOTE_INSN_DELETED
);
2264 COPY_HARD_REG_SET (lra_no_alloc_regs
, ira_no_alloc_regs
);
2269 init_insn_recog_data ();
2271 #ifdef ENABLE_CHECKING
2272 /* Some quick check on RTL generated by previous passes. */
2276 lra_in_progress
= 1;
2278 lra_live_range_iter
= lra_coalesce_iter
= 0;
2279 lra_constraint_iter
= lra_constraint_iter_after_spill
= 0;
2280 lra_inheritance_iter
= lra_undo_inheritance_iter
= 0;
2282 setup_reg_spill_flag ();
2284 /* Function remove_scratches can creates new pseudos for clobbers --
2285 so set up lra_constraint_new_regno_start before its call to
2286 permit changing reg classes for pseudos created by this
2288 lra_constraint_new_regno_start
= lra_new_regno_start
= max_reg_num ();
2289 remove_scratches ();
2290 scratch_p
= lra_constraint_new_regno_start
!= max_reg_num ();
2292 /* A function that has a non-local label that can reach the exit
2293 block via non-exceptional paths must save all call-saved
2295 if (cfun
->has_nonlocal_label
&& has_nonexceptional_receiver ())
2296 crtl
->saves_all_registers
= 1;
2298 if (crtl
->saves_all_registers
)
2299 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2300 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
2301 df_set_regs_ever_live (i
, true);
2303 /* We don't DF from now and avoid its using because it is to
2304 expensive when a lot of RTL changes are made. */
2305 df_set_flags (DF_NO_INSN_RESCAN
);
2306 lra_constraint_insn_stack
.create (get_max_uid ());
2307 lra_constraint_insn_stack_bitmap
= sbitmap_alloc (get_max_uid ());
2308 bitmap_clear (lra_constraint_insn_stack_bitmap
);
2309 lra_live_ranges_init ();
2310 lra_constraints_init ();
2311 lra_curr_reload_num
= 0;
2312 push_insns (get_last_insn (), NULL_RTX
);
2313 /* It is needed for the 1st coalescing. */
2314 lra_constraint_new_insn_uid_start
= get_max_uid ();
2315 bitmap_initialize (&lra_inheritance_pseudos
, ®_obstack
);
2316 bitmap_initialize (&lra_split_regs
, ®_obstack
);
2317 bitmap_initialize (&lra_optional_reload_pseudos
, ®_obstack
);
2318 bitmap_initialize (&lra_subreg_reload_pseudos
, ®_obstack
);
2320 if (get_frame_size () != 0 && crtl
->stack_alignment_needed
)
2321 /* If we have a stack frame, we must align it now. The stack size
2322 may be a part of the offset computation for register
2324 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
2330 /* We should try to assign hard registers to scratches even
2331 if there were no RTL transformations in
2333 if (! lra_constraints (lra_constraint_iter
== 0)
2334 && (lra_constraint_iter
> 1
2335 || (! scratch_p
&& ! caller_save_needed
)))
2337 /* Constraint transformations may result in that eliminable
2338 hard regs become uneliminable and pseudos which use them
2339 should be spilled. It is better to do it before pseudo
2342 For example, rs6000 can make
2343 RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started
2344 to use a constant pool. */
2345 lra_eliminate (false, false);
2346 /* Do inheritance only for regular algorithms. */
2349 if (flag_use_caller_save
)
2352 lra_clear_live_ranges ();
2353 /* As a side-effect of lra_create_live_ranges, we calculate
2354 actual_call_used_reg_set, which is needed during
2356 lra_create_live_ranges (true);
2361 lra_clear_live_ranges ();
2362 /* We need live ranges for lra_assign -- so build them. */
2363 lra_create_live_ranges (true);
2365 /* If we don't spill non-reload and non-inheritance pseudos,
2366 there is no sense to run memory-memory move coalescing.
2367 If inheritance pseudos were spilled, the memory-memory
2368 moves involving them will be removed by pass undoing
2374 bool spill_p
= !lra_assign ();
2376 if (lra_undo_inheritance ())
2382 lra_create_live_ranges (true);
2385 if (lra_coalesce ())
2389 lra_clear_live_ranges ();
2392 /* Don't clear optional reloads bitmap until all constraints are
2393 satisfied as we need to differ them from regular reloads. */
2394 bitmap_clear (&lra_optional_reload_pseudos
);
2395 bitmap_clear (&lra_subreg_reload_pseudos
);
2396 bitmap_clear (&lra_inheritance_pseudos
);
2397 bitmap_clear (&lra_split_regs
);
2398 if (! lra_need_for_spills_p ())
2402 /* We need full live info for spilling pseudos into
2403 registers instead of memory. */
2404 lra_create_live_ranges (lra_reg_spill_p
);
2408 /* Assignment of stack slots changes elimination offsets for
2409 some eliminations. So update the offsets here. */
2410 lra_eliminate (false, false);
2411 lra_constraint_new_regno_start
= max_reg_num ();
2412 lra_constraint_new_insn_uid_start
= get_max_uid ();
2413 lra_constraint_iter_after_spill
= 0;
2415 restore_scratches ();
2416 lra_eliminate (true, false);
2417 lra_final_code_change ();
2418 lra_in_progress
= 0;
2420 lra_clear_live_ranges ();
2421 lra_live_ranges_finish ();
2422 lra_constraints_finish ();
2424 sbitmap_free (lra_constraint_insn_stack_bitmap
);
2425 lra_constraint_insn_stack
.release ();
2426 finish_insn_recog_data ();
2427 regstat_free_n_sets_and_refs ();
2429 reload_completed
= 1;
2430 update_inc_notes ();
2432 inserted_p
= fixup_abnormal_edges ();
2434 /* We've possibly turned single trapping insn into multiple ones. */
2435 if (cfun
->can_throw_non_call_exceptions
)
2438 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
2439 bitmap_ones (blocks
);
2440 find_many_sub_basic_blocks (blocks
);
2441 sbitmap_free (blocks
);
2445 commit_edge_insertions ();
2447 /* Replacing pseudos with their memory equivalents might have
2448 created shared rtx. Subsequent passes would get confused
2449 by this, so unshare everything here. */
2450 unshare_all_rtl_again (get_insns ());
2452 #ifdef ENABLE_CHECKING
2456 timevar_pop (TV_LRA
);
2459 /* Called once per compiler to initialize LRA data once. */
2461 lra_init_once (void)
2463 init_insn_code_data_once ();
2466 /* Initialize LRA whenever register-related information is changed. */
2470 init_op_alt_data ();
2473 /* Called once per compiler to finish LRA data which are initialize
2476 lra_finish_once (void)
2478 finish_insn_code_data_once ();