1 /* Target Code for R8C/M16C/M32C
2 Copyright (C) 2005-2016 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
34 #include "diagnostic-core.h"
36 #include "insn-attr.h"
39 #include "stor-layout.h"
44 #include "tm-constrs.h"
47 /* This file should be included last. */
48 #include "target-def.h"
52 /* Used by m32c_pushm_popm. */
60 static bool m32c_function_needs_enter (void);
61 static tree
interrupt_handler (tree
*, tree
, tree
, int, bool *);
62 static tree
function_vector_handler (tree
*, tree
, tree
, int, bool *);
63 static int interrupt_p (tree node
);
64 static int bank_switch_p (tree node
);
65 static int fast_interrupt_p (tree node
);
66 static int interrupt_p (tree node
);
67 static bool m32c_asm_integer (rtx
, unsigned int, int);
68 static int m32c_comp_type_attributes (const_tree
, const_tree
);
69 static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
70 static struct machine_function
*m32c_init_machine_status (void);
71 static void m32c_insert_attributes (tree
, tree
*);
72 static bool m32c_legitimate_address_p (machine_mode
, rtx
, bool);
73 static bool m32c_addr_space_legitimate_address_p (machine_mode
, rtx
, bool, addr_space_t
);
74 static rtx
m32c_function_arg (cumulative_args_t
, machine_mode
,
76 static bool m32c_pass_by_reference (cumulative_args_t
, machine_mode
,
78 static void m32c_function_arg_advance (cumulative_args_t
, machine_mode
,
80 static unsigned int m32c_function_arg_boundary (machine_mode
, const_tree
);
81 static int m32c_pushm_popm (Push_Pop_Type
);
82 static bool m32c_strict_argument_naming (cumulative_args_t
);
83 static rtx
m32c_struct_value_rtx (tree
, int);
84 static rtx
m32c_subreg (machine_mode
, rtx
, machine_mode
, int);
85 static int need_to_save (int);
86 static rtx
m32c_function_value (const_tree
, const_tree
, bool);
87 static rtx
m32c_libcall_value (machine_mode
, const_rtx
);
89 /* Returns true if an address is specified, else false. */
90 static bool m32c_get_pragma_address (const char *varname
, unsigned *addr
);
92 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
94 #define streq(a,b) (strcmp ((a), (b)) == 0)
96 /* Internal support routines */
98 /* Debugging statements are tagged with DEBUG0 only so that they can
99 be easily enabled individually, by replacing the '0' with '1' as
105 #include "print-tree.h"
106 /* This is needed by some of the commented-out debug statements
108 static char const *class_names
[LIM_REG_CLASSES
] = REG_CLASS_NAMES
;
110 static int class_contents
[LIM_REG_CLASSES
][1] = REG_CLASS_CONTENTS
;
112 /* These are all to support encode_pattern(). */
113 static char pattern
[30], *patternp
;
114 static GTY(()) rtx patternr
[30];
115 #define RTX_IS(x) (streq (pattern, x))
117 /* Some macros to simplify the logic throughout this file. */
118 #define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
119 #define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
121 #define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
122 #define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
125 far_addr_space_p (rtx x
)
127 if (GET_CODE (x
) != MEM
)
130 fprintf(stderr
, "\033[35mfar_addr_space: "); debug_rtx(x
);
131 fprintf(stderr
, " = %d\033[0m\n", MEM_ADDR_SPACE (x
) == ADDR_SPACE_FAR
);
133 return MEM_ADDR_SPACE (x
) == ADDR_SPACE_FAR
;
136 /* We do most RTX matching by converting the RTX into a string, and
137 using string compares. This vastly simplifies the logic in many of
138 the functions in this file.
140 On exit, pattern[] has the encoded string (use RTX_IS("...") to
141 compare it) and patternr[] has pointers to the nodes in the RTX
142 corresponding to each character in the encoded string. The latter
143 is mostly used by print_operand().
145 Unrecognized patterns have '?' in them; this shows up when the
146 assembler complains about syntax errors.
150 encode_pattern_1 (rtx x
)
154 if (patternp
== pattern
+ sizeof (pattern
) - 2)
160 patternr
[patternp
- pattern
] = x
;
162 switch (GET_CODE (x
))
168 if (GET_MODE_SIZE (GET_MODE (x
)) !=
169 GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))))
171 if (GET_MODE (x
) == PSImode
172 && GET_CODE (XEXP (x
, 0)) == REG
)
174 encode_pattern_1 (XEXP (x
, 0));
179 encode_pattern_1 (XEXP (x
, 0));
184 encode_pattern_1 (XEXP (x
, 0));
189 encode_pattern_1 (XEXP (x
, 0));
193 encode_pattern_1 (XEXP (x
, 0));
194 encode_pattern_1 (XEXP (x
, 1));
198 encode_pattern_1 (XEXP (x
, 0));
202 encode_pattern_1 (XEXP (x
, 0));
206 encode_pattern_1 (XEXP (x
, 0));
207 encode_pattern_1 (XEXP (x
, 1));
211 encode_pattern_1 (XEXP (x
, 0));
228 *patternp
++ = '0' + XCINT (x
, 1, UNSPEC
);
229 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
230 encode_pattern_1 (XVECEXP (x
, 0, i
));
237 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
238 encode_pattern_1 (XVECEXP (x
, 0, i
));
242 encode_pattern_1 (XEXP (x
, 0));
244 encode_pattern_1 (XEXP (x
, 1));
249 fprintf (stderr
, "can't encode pattern %s\n",
250 GET_RTX_NAME (GET_CODE (x
)));
258 encode_pattern (rtx x
)
261 encode_pattern_1 (x
);
265 /* Since register names indicate the mode they're used in, we need a
266 way to determine which name to refer to the register with. Called
267 by print_operand(). */
270 reg_name_with_mode (int regno
, machine_mode mode
)
272 int mlen
= GET_MODE_SIZE (mode
);
273 if (regno
== R0_REGNO
&& mlen
== 1)
275 if (regno
== R0_REGNO
&& (mlen
== 3 || mlen
== 4))
277 if (regno
== R0_REGNO
&& mlen
== 6)
279 if (regno
== R0_REGNO
&& mlen
== 8)
281 if (regno
== R1_REGNO
&& mlen
== 1)
283 if (regno
== R1_REGNO
&& (mlen
== 3 || mlen
== 4))
285 if (regno
== A0_REGNO
&& TARGET_A16
&& (mlen
== 3 || mlen
== 4))
287 return reg_names
[regno
];
290 /* How many bytes a register uses on stack when it's pushed. We need
291 to know this because the push opcode needs to explicitly indicate
292 the size of the register, even though the name of the register
293 already tells it that. Used by m32c_output_reg_{push,pop}, which
294 is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}. */
297 reg_push_size (int regno
)
322 /* Given two register classes, find the largest intersection between
323 them. If there is no intersection, return RETURNED_IF_EMPTY
326 reduce_class (reg_class_t original_class
, reg_class_t limiting_class
,
327 reg_class_t returned_if_empty
)
331 reg_class_t best
= NO_REGS
;
332 unsigned int best_size
= 0;
334 if (original_class
== limiting_class
)
335 return original_class
;
337 cc
= reg_class_contents
[original_class
];
338 AND_HARD_REG_SET (cc
, reg_class_contents
[limiting_class
]);
340 for (i
= 0; i
< LIM_REG_CLASSES
; i
++)
342 if (hard_reg_set_subset_p (reg_class_contents
[i
], cc
))
343 if (best_size
< reg_class_size
[i
])
345 best
= (reg_class_t
) i
;
346 best_size
= reg_class_size
[i
];
351 return returned_if_empty
;
355 /* Used by m32c_register_move_cost to determine if a move is
356 impossibly expensive. */
358 class_can_hold_mode (reg_class_t rclass
, machine_mode mode
)
360 /* Cache the results: 0=untested 1=no 2=yes */
361 static char results
[LIM_REG_CLASSES
][MAX_MACHINE_MODE
];
363 if (results
[(int) rclass
][mode
] == 0)
366 results
[rclass
][mode
] = 1;
367 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
368 if (in_hard_reg_set_p (reg_class_contents
[(int) rclass
], mode
, r
)
369 && HARD_REGNO_MODE_OK (r
, mode
))
371 results
[rclass
][mode
] = 2;
377 fprintf (stderr
, "class %s can hold %s? %s\n",
378 class_names
[(int) rclass
], mode_name
[mode
],
379 (results
[rclass
][mode
] == 2) ? "yes" : "no");
381 return results
[(int) rclass
][mode
] == 2;
384 /* Run-time Target Specification. */
386 /* Memregs are memory locations that gcc treats like general
387 registers, as there are a limited number of true registers and the
388 m32c families can use memory in most places that registers can be
391 However, since memory accesses are more expensive than registers,
392 we allow the user to limit the number of memregs available, in
393 order to try to persuade gcc to try harder to use real registers.
395 Memregs are provided by lib1funcs.S.
398 int ok_to_change_target_memregs
= TRUE
;
400 /* Implements TARGET_OPTION_OVERRIDE. */
402 #undef TARGET_OPTION_OVERRIDE
403 #define TARGET_OPTION_OVERRIDE m32c_option_override
406 m32c_option_override (void)
408 /* We limit memregs to 0..16, and provide a default. */
409 if (global_options_set
.x_target_memregs
)
411 if (target_memregs
< 0 || target_memregs
> 16)
412 error ("invalid target memregs value '%d'", target_memregs
);
420 /* This target defaults to strict volatile bitfields. */
421 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
422 flag_strict_volatile_bitfields
= 1;
424 /* r8c/m16c have no 16-bit indirect call, so thunks are involved.
425 This is always worse than an absolute call. */
427 flag_no_function_cse
= 1;
429 /* This wants to put insns between compares and their jumps. */
430 /* FIXME: The right solution is to properly trace the flags register
431 values, but that is too much work for stage 4. */
432 flag_combine_stack_adjustments
= 0;
435 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
436 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m32c_override_options_after_change
439 m32c_override_options_after_change (void)
442 flag_no_function_cse
= 1;
445 /* Defining data structures for per-function information */
447 /* The usual; we set up our machine_function data. */
448 static struct machine_function
*
449 m32c_init_machine_status (void)
451 return ggc_cleared_alloc
<machine_function
> ();
454 /* Implements INIT_EXPANDERS. We just set up to call the above
457 m32c_init_expanders (void)
459 init_machine_status
= m32c_init_machine_status
;
464 /* Register Basics */
466 /* Basic Characteristics of Registers */
468 /* Whether a mode fits in a register is complex enough to warrant a
477 } nregs_table
[FIRST_PSEUDO_REGISTER
] =
479 { 1, 1, 2, 2, 4 }, /* r0 */
480 { 0, 1, 0, 0, 0 }, /* r2 */
481 { 1, 1, 2, 2, 0 }, /* r1 */
482 { 0, 1, 0, 0, 0 }, /* r3 */
483 { 0, 1, 1, 0, 0 }, /* a0 */
484 { 0, 1, 1, 0, 0 }, /* a1 */
485 { 0, 1, 1, 0, 0 }, /* sb */
486 { 0, 1, 1, 0, 0 }, /* fb */
487 { 0, 1, 1, 0, 0 }, /* sp */
488 { 1, 1, 1, 0, 0 }, /* pc */
489 { 0, 0, 0, 0, 0 }, /* fl */
490 { 1, 1, 1, 0, 0 }, /* ap */
491 { 1, 1, 2, 2, 4 }, /* mem0 */
492 { 1, 1, 2, 2, 4 }, /* mem1 */
493 { 1, 1, 2, 2, 4 }, /* mem2 */
494 { 1, 1, 2, 2, 4 }, /* mem3 */
495 { 1, 1, 2, 2, 4 }, /* mem4 */
496 { 1, 1, 2, 2, 0 }, /* mem5 */
497 { 1, 1, 2, 2, 0 }, /* mem6 */
498 { 1, 1, 0, 0, 0 }, /* mem7 */
501 /* Implements TARGET_CONDITIONAL_REGISTER_USAGE. We adjust the number
502 of available memregs, and select which registers need to be preserved
503 across calls based on the chip family. */
505 #undef TARGET_CONDITIONAL_REGISTER_USAGE
506 #define TARGET_CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage
508 m32c_conditional_register_usage (void)
512 if (0 <= target_memregs
&& target_memregs
<= 16)
514 /* The command line option is bytes, but our "registers" are
516 for (i
= (target_memregs
+1)/2; i
< 8; i
++)
518 fixed_regs
[MEM0_REGNO
+ i
] = 1;
519 CLEAR_HARD_REG_BIT (reg_class_contents
[MEM_REGS
], MEM0_REGNO
+ i
);
523 /* M32CM and M32C preserve more registers across function calls. */
526 call_used_regs
[R1_REGNO
] = 0;
527 call_used_regs
[R2_REGNO
] = 0;
528 call_used_regs
[R3_REGNO
] = 0;
529 call_used_regs
[A0_REGNO
] = 0;
530 call_used_regs
[A1_REGNO
] = 0;
534 /* How Values Fit in Registers */
536 /* Implements HARD_REGNO_NREGS. This is complicated by the fact that
537 different registers are different sizes from each other, *and* may
538 be different sizes in different chip families. */
540 m32c_hard_regno_nregs_1 (int regno
, machine_mode mode
)
542 if (regno
== FLG_REGNO
&& mode
== CCmode
)
544 if (regno
>= FIRST_PSEUDO_REGISTER
)
545 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
547 if (regno
>= MEM0_REGNO
&& regno
<= MEM7_REGNO
)
548 return (GET_MODE_SIZE (mode
) + 1) / 2;
550 if (GET_MODE_SIZE (mode
) <= 1)
551 return nregs_table
[regno
].qi_regs
;
552 if (GET_MODE_SIZE (mode
) <= 2)
553 return nregs_table
[regno
].hi_regs
;
554 if (regno
== A0_REGNO
&& mode
== SImode
&& TARGET_A16
)
556 if ((GET_MODE_SIZE (mode
) <= 3 || mode
== PSImode
) && TARGET_A24
)
557 return nregs_table
[regno
].pi_regs
;
558 if (GET_MODE_SIZE (mode
) <= 4)
559 return nregs_table
[regno
].si_regs
;
560 if (GET_MODE_SIZE (mode
) <= 8)
561 return nregs_table
[regno
].di_regs
;
566 m32c_hard_regno_nregs (int regno
, machine_mode mode
)
568 int rv
= m32c_hard_regno_nregs_1 (regno
, mode
);
572 /* Implements HARD_REGNO_MODE_OK. The above function does the work
573 already; just test its return value. */
575 m32c_hard_regno_ok (int regno
, machine_mode mode
)
577 return m32c_hard_regno_nregs_1 (regno
, mode
) != 0;
580 /* Implements MODES_TIEABLE_P. In general, modes aren't tieable since
581 registers are all different sizes. However, since most modes are
582 bigger than our registers anyway, it's easier to implement this
583 function that way, leaving QImode as the only unique case. */
585 m32c_modes_tieable_p (machine_mode m1
, machine_mode m2
)
587 if (GET_MODE_SIZE (m1
) == GET_MODE_SIZE (m2
))
591 if (m1
== QImode
|| m2
== QImode
)
598 /* Register Classes */
600 /* Implements REGNO_REG_CLASS. */
602 m32c_regno_reg_class (int regno
)
627 if (IS_MEM_REGNO (regno
))
633 /* Implements REGNO_OK_FOR_BASE_P. */
635 m32c_regno_ok_for_base_p (int regno
)
637 if (regno
== A0_REGNO
638 || regno
== A1_REGNO
|| regno
>= FIRST_PSEUDO_REGISTER
)
643 /* Implements TARGET_PREFERRED_RELOAD_CLASS. In general, prefer general
644 registers of the appropriate size. */
646 #undef TARGET_PREFERRED_RELOAD_CLASS
647 #define TARGET_PREFERRED_RELOAD_CLASS m32c_preferred_reload_class
650 m32c_preferred_reload_class (rtx x
, reg_class_t rclass
)
652 reg_class_t newclass
= rclass
;
655 fprintf (stderr
, "\npreferred_reload_class for %s is ",
656 class_names
[rclass
]);
658 if (rclass
== NO_REGS
)
659 rclass
= GET_MODE (x
) == QImode
? HL_REGS
: R03_REGS
;
661 if (reg_classes_intersect_p (rclass
, CR_REGS
))
663 switch (GET_MODE (x
))
669 /* newclass = HI_REGS; */
674 else if (newclass
== QI_REGS
&& GET_MODE_SIZE (GET_MODE (x
)) > 2)
676 else if (GET_MODE_SIZE (GET_MODE (x
)) > 4
677 && ! reg_class_subset_p (R03_REGS
, rclass
))
680 rclass
= reduce_class (rclass
, newclass
, rclass
);
682 if (GET_MODE (x
) == QImode
)
683 rclass
= reduce_class (rclass
, HL_REGS
, rclass
);
686 fprintf (stderr
, "%s\n", class_names
[rclass
]);
689 if (GET_CODE (x
) == MEM
690 && GET_CODE (XEXP (x
, 0)) == PLUS
691 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
692 fprintf (stderr
, "Glorm!\n");
697 /* Implements TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
699 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
700 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS m32c_preferred_output_reload_class
703 m32c_preferred_output_reload_class (rtx x
, reg_class_t rclass
)
705 return m32c_preferred_reload_class (x
, rclass
);
708 /* Implements LIMIT_RELOAD_CLASS. We basically want to avoid using
709 address registers for reloads since they're needed for address
712 m32c_limit_reload_class (machine_mode mode
, int rclass
)
715 fprintf (stderr
, "limit_reload_class for %s: %s ->",
716 mode_name
[mode
], class_names
[rclass
]);
720 rclass
= reduce_class (rclass
, HL_REGS
, rclass
);
721 else if (mode
== HImode
)
722 rclass
= reduce_class (rclass
, HI_REGS
, rclass
);
723 else if (mode
== SImode
)
724 rclass
= reduce_class (rclass
, SI_REGS
, rclass
);
726 if (rclass
!= A_REGS
)
727 rclass
= reduce_class (rclass
, DI_REGS
, rclass
);
730 fprintf (stderr
, " %s\n", class_names
[rclass
]);
735 /* Implements SECONDARY_RELOAD_CLASS. QImode have to be reloaded in
736 r0 or r1, as those are the only real QImode registers. CR regs get
737 reloaded through appropriately sized general or address
740 m32c_secondary_reload_class (int rclass
, machine_mode mode
, rtx x
)
742 int cc
= class_contents
[rclass
][0];
744 fprintf (stderr
, "\nsecondary reload class %s %s\n",
745 class_names
[rclass
], mode_name
[mode
]);
749 && GET_CODE (x
) == MEM
&& (cc
& ~class_contents
[R23_REGS
][0]) == 0)
751 if (reg_classes_intersect_p (rclass
, CR_REGS
)
752 && GET_CODE (x
) == REG
753 && REGNO (x
) >= SB_REGNO
&& REGNO (x
) <= SP_REGNO
)
754 return (TARGET_A16
|| mode
== HImode
) ? HI_REGS
: A_REGS
;
758 /* Implements TARGET_CLASS_LIKELY_SPILLED_P. A_REGS is needed for address
761 #undef TARGET_CLASS_LIKELY_SPILLED_P
762 #define TARGET_CLASS_LIKELY_SPILLED_P m32c_class_likely_spilled_p
765 m32c_class_likely_spilled_p (reg_class_t regclass
)
767 if (regclass
== A_REGS
)
770 return (reg_class_size
[(int) regclass
] == 1);
773 /* Implements TARGET_CLASS_MAX_NREGS. We calculate this according to its
774 documented meaning, to avoid potential inconsistencies with actual
775 class definitions. */
777 #undef TARGET_CLASS_MAX_NREGS
778 #define TARGET_CLASS_MAX_NREGS m32c_class_max_nregs
781 m32c_class_max_nregs (reg_class_t regclass
, machine_mode mode
)
784 unsigned char max
= 0;
786 for (rn
= 0; rn
< FIRST_PSEUDO_REGISTER
; rn
++)
787 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) regclass
], rn
))
789 unsigned char n
= m32c_hard_regno_nregs (rn
, mode
);
796 /* Implements CANNOT_CHANGE_MODE_CLASS. Only r0 and r1 can change to
797 QI (r0l, r1l) because the chip doesn't support QI ops on other
798 registers (well, it does on a0/a1 but if we let gcc do that, reload
799 suffers). Otherwise, we allow changes to larger modes. */
801 m32c_cannot_change_mode_class (machine_mode from
,
802 machine_mode to
, int rclass
)
806 fprintf (stderr
, "cannot change from %s to %s in %s\n",
807 mode_name
[from
], mode_name
[to
], class_names
[rclass
]);
810 /* If the larger mode isn't allowed in any of these registers, we
811 can't allow the change. */
812 for (rn
= 0; rn
< FIRST_PSEUDO_REGISTER
; rn
++)
813 if (class_contents
[rclass
][0] & (1 << rn
))
814 if (! m32c_hard_regno_ok (rn
, to
))
818 return (class_contents
[rclass
][0] & 0x1ffa);
820 if (class_contents
[rclass
][0] & 0x0005 /* r0, r1 */
821 && GET_MODE_SIZE (from
) > 1)
823 if (GET_MODE_SIZE (from
) > 2) /* all other regs */
829 /* Helpers for the rest of the file. */
830 /* TRUE if the rtx is a REG rtx for the given register. */
831 #define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
832 && REGNO (rtx) == regno)
833 /* TRUE if the rtx is a pseudo - specifically, one we can use as a
834 base register in address calculations (hence the "strict"
836 #define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
837 && (REGNO (rtx) == AP_REGNO \
838 || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
840 #define A0_OR_PSEUDO(x) (IS_REG(x, A0_REGNO) || REGNO (x) >= FIRST_PSEUDO_REGISTER)
842 /* Implements matching for constraints (see next function too). 'S' is
843 for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
844 call return values. */
846 m32c_matches_constraint_p (rtx value
, int constraint
)
848 encode_pattern (value
);
850 switch (constraint
) {
852 return (far_addr_space_p (value
)
854 && A0_OR_PSEUDO (patternr
[1])
855 && GET_MODE (patternr
[1]) == SImode
)
856 || (RTX_IS ("m+^Sri")
857 && A0_OR_PSEUDO (patternr
[4])
858 && GET_MODE (patternr
[4]) == HImode
)
859 || (RTX_IS ("m+^Srs")
860 && A0_OR_PSEUDO (patternr
[4])
861 && GET_MODE (patternr
[4]) == HImode
)
862 || (RTX_IS ("m+^S+ris")
863 && A0_OR_PSEUDO (patternr
[5])
864 && GET_MODE (patternr
[5]) == HImode
)
868 /* This is the common "src/dest" address */
870 if (GET_CODE (value
) == MEM
&& CONSTANT_P (XEXP (value
, 0)))
872 if (RTX_IS ("ms") || RTX_IS ("m+si"))
874 if (RTX_IS ("m++rii"))
876 if (REGNO (patternr
[3]) == FB_REGNO
877 && INTVAL (patternr
[4]) == 0)
882 else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
886 if (REGNO (r
) == SP_REGNO
)
888 return m32c_legitimate_address_p (GET_MODE (value
), XEXP (value
, 0), 1);
895 else if (RTX_IS ("m+ri"))
899 return (IS_REG (r
, A0_REGNO
) || IS_REG (r
, A1_REGNO
));
902 return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
904 return ((RTX_IS ("mr")
905 && (IS_REG (patternr
[1], SP_REGNO
)))
906 || (RTX_IS ("m+ri") && (IS_REG (patternr
[2], SP_REGNO
))));
908 return ((RTX_IS ("mr")
909 && (IS_REG (patternr
[1], FB_REGNO
)))
910 || (RTX_IS ("m+ri") && (IS_REG (patternr
[2], FB_REGNO
))));
912 return ((RTX_IS ("mr")
913 && (IS_REG (patternr
[1], SB_REGNO
)))
914 || (RTX_IS ("m+ri") && (IS_REG (patternr
[2], SB_REGNO
))));
916 /* Absolute addresses 0..0x1fff used for bit addressing (I/O ports) */
917 return (RTX_IS ("mi")
918 && !(INTVAL (patternr
[1]) & ~0x1fff));
920 return r1h_operand (value
, QImode
);
922 return GET_CODE (value
) == PARALLEL
;
928 /* STACK AND CALLING */
932 /* Implements RETURN_ADDR_RTX. Note that R8C and M16C push 24 bits
933 (yes, THREE bytes) onto the stack for the return address, but we
934 don't support pointers bigger than 16 bits on those chips. This
935 will likely wreak havoc with exception unwinding. FIXME. */
937 m32c_return_addr_rtx (int count
)
949 /* It's four bytes */
955 /* FIXME: it's really 3 bytes */
961 gen_rtx_MEM (mode
, plus_constant (Pmode
, gen_rtx_REG (Pmode
, FP_REGNO
),
963 return copy_to_mode_reg (mode
, ra_mem
);
966 /* Implements INCOMING_RETURN_ADDR_RTX. See comment above. */
968 m32c_incoming_return_addr_rtx (void)
971 return gen_rtx_MEM (PSImode
, gen_rtx_REG (PSImode
, SP_REGNO
));
974 /* Exception Handling Support */
976 /* Implements EH_RETURN_DATA_REGNO. Choose registers able to hold
979 m32c_eh_return_data_regno (int n
)
988 return INVALID_REGNUM
;
992 /* Implements EH_RETURN_STACKADJ_RTX. Saved and used later in
993 m32c_emit_eh_epilogue. */
995 m32c_eh_return_stackadj_rtx (void)
997 if (!cfun
->machine
->eh_stack_adjust
)
1001 sa
= gen_rtx_REG (Pmode
, R0_REGNO
);
1002 cfun
->machine
->eh_stack_adjust
= sa
;
1004 return cfun
->machine
->eh_stack_adjust
;
1007 /* Registers That Address the Stack Frame */
1009 /* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER. Note that
1010 the original spec called for dwarf numbers to vary with register
1011 width as well, for example, r0l, r0, and r2r0 would each have
1012 different dwarf numbers. GCC doesn't support this, and we don't do
1013 it, and gdb seems to like it this way anyway. */
1015 m32c_dwarf_frame_regnum (int n
)
1041 return DWARF_FRAME_REGISTERS
+ 1;
1045 /* The frame looks like this:
1047 ap -> +------------------------------
1048 | Return address (3 or 4 bytes)
1049 | Saved FB (2 or 4 bytes)
1050 fb -> +------------------------------
1053 | through r0 as needed
1054 sp -> +------------------------------
1057 /* We use this to wrap all emitted insns in the prologue. */
1061 RTX_FRAME_RELATED_P (x
) = 1;
1065 /* This maps register numbers to the PUSHM/POPM bitfield, and tells us
1066 how much the stack pointer moves for each, for each cpu family. */
1075 /* These are in reverse push (nearest-to-sp) order. */
1076 { R0_REGNO
, 0x80, 2, 2 },
1077 { R1_REGNO
, 0x40, 2, 2 },
1078 { R2_REGNO
, 0x20, 2, 2 },
1079 { R3_REGNO
, 0x10, 2, 2 },
1080 { A0_REGNO
, 0x08, 2, 4 },
1081 { A1_REGNO
, 0x04, 2, 4 },
1082 { SB_REGNO
, 0x02, 2, 4 },
1083 { FB_REGNO
, 0x01, 2, 4 }
1086 #define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
1088 /* Returns TRUE if we need to save/restore the given register. We
1089 save everything for exception handlers, so that any register can be
1090 unwound. For interrupt handlers, we save everything if the handler
1091 calls something else (because we don't know what *that* function
1092 might do), but try to be a bit smarter if the handler is a leaf
1093 function. We always save $a0, though, because we use that in the
1094 epilogue to copy $fb to $sp. */
1096 need_to_save (int regno
)
1098 if (fixed_regs
[regno
])
1100 if (crtl
->calls_eh_return
)
1102 if (regno
== FP_REGNO
)
1104 if (cfun
->machine
->is_interrupt
1105 && (!cfun
->machine
->is_leaf
1106 || (regno
== A0_REGNO
1107 && m32c_function_needs_enter ())
1110 if (df_regs_ever_live_p (regno
)
1111 && (!call_used_regs
[regno
] || cfun
->machine
->is_interrupt
))
1116 /* This function contains all the intelligence about saving and
1117 restoring registers. It always figures out the register save set.
1118 When called with PP_justcount, it merely returns the size of the
1119 save set (for eliminating the frame pointer, for example). When
1120 called with PP_pushm or PP_popm, it emits the appropriate
1121 instructions for saving (pushm) or restoring (popm) the
1124 m32c_pushm_popm (Push_Pop_Type ppt
)
1127 int byte_count
= 0, bytes
;
1129 rtx dwarf_set
[PUSHM_N
];
1131 int nosave_mask
= 0;
1133 if (crtl
->return_rtx
1134 && GET_CODE (crtl
->return_rtx
) == PARALLEL
1135 && !(crtl
->calls_eh_return
|| cfun
->machine
->is_interrupt
))
1137 rtx exp
= XVECEXP (crtl
->return_rtx
, 0, 0);
1138 rtx rv
= XEXP (exp
, 0);
1139 int rv_bytes
= GET_MODE_SIZE (GET_MODE (rv
));
1142 nosave_mask
|= 0x20; /* PSI, SI */
1144 nosave_mask
|= 0xf0; /* DF */
1146 nosave_mask
|= 0x50; /* DI */
1149 for (i
= 0; i
< (int) PUSHM_N
; i
++)
1151 /* Skip if neither register needs saving. */
1152 if (!need_to_save (pushm_info
[i
].reg1
))
1155 if (pushm_info
[i
].bit
& nosave_mask
)
1158 reg_mask
|= pushm_info
[i
].bit
;
1159 bytes
= TARGET_A16
? pushm_info
[i
].a16_bytes
: pushm_info
[i
].a24_bytes
;
1161 if (ppt
== PP_pushm
)
1163 machine_mode mode
= (bytes
== 2) ? HImode
: SImode
;
1166 /* Always use stack_pointer_rtx instead of calling
1167 rtx_gen_REG ourselves. Code elsewhere in GCC assumes
1168 that there is a single rtx representing the stack pointer,
1169 namely stack_pointer_rtx, and uses == to recognize it. */
1170 addr
= stack_pointer_rtx
;
1172 if (byte_count
!= 0)
1173 addr
= gen_rtx_PLUS (GET_MODE (addr
), addr
, GEN_INT (byte_count
));
1175 dwarf_set
[n_dwarfs
++] =
1176 gen_rtx_SET (gen_rtx_MEM (mode
, addr
),
1177 gen_rtx_REG (mode
, pushm_info
[i
].reg1
));
1178 F (dwarf_set
[n_dwarfs
- 1]);
1181 byte_count
+= bytes
;
1184 if (cfun
->machine
->is_interrupt
)
1186 cfun
->machine
->intr_pushm
= reg_mask
& 0xfe;
1191 if (cfun
->machine
->is_interrupt
)
1192 for (i
= MEM0_REGNO
; i
<= MEM7_REGNO
; i
++)
1193 if (need_to_save (i
))
1196 cfun
->machine
->intr_pushmem
[i
- MEM0_REGNO
] = 1;
1199 if (ppt
== PP_pushm
&& byte_count
)
1201 rtx note
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (n_dwarfs
+ 1));
1206 XVECEXP (note
, 0, 0)
1207 = gen_rtx_SET (stack_pointer_rtx
,
1208 gen_rtx_PLUS (GET_MODE (stack_pointer_rtx
),
1210 GEN_INT (-byte_count
)));
1211 F (XVECEXP (note
, 0, 0));
1213 for (i
= 0; i
< n_dwarfs
; i
++)
1214 XVECEXP (note
, 0, i
+ 1) = dwarf_set
[i
];
1216 pushm
= F (emit_insn (gen_pushm (GEN_INT (reg_mask
))));
1218 add_reg_note (pushm
, REG_FRAME_RELATED_EXPR
, note
);
1221 if (cfun
->machine
->is_interrupt
)
1222 for (i
= MEM0_REGNO
; i
<= MEM7_REGNO
; i
++)
1223 if (cfun
->machine
->intr_pushmem
[i
- MEM0_REGNO
])
1226 pushm
= emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode
, i
)));
1228 pushm
= emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode
, i
)));
1232 if (ppt
== PP_popm
&& byte_count
)
1234 if (cfun
->machine
->is_interrupt
)
1235 for (i
= MEM7_REGNO
; i
>= MEM0_REGNO
; i
--)
1236 if (cfun
->machine
->intr_pushmem
[i
- MEM0_REGNO
])
1239 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode
, i
)));
1241 emit_insn (gen_pophi_24 (gen_rtx_REG (HImode
, i
)));
1244 emit_insn (gen_popm (GEN_INT (reg_mask
)));
1250 /* Implements INITIAL_ELIMINATION_OFFSET. See the comment above that
1251 diagrams our call frame. */
1253 m32c_initial_elimination_offset (int from
, int to
)
1257 if (from
== AP_REGNO
)
1267 ofs
+= m32c_pushm_popm (PP_justcount
);
1268 ofs
+= get_frame_size ();
1271 /* Account for push rounding. */
1273 ofs
= (ofs
+ 1) & ~1;
1275 fprintf (stderr
, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from
,
1281 /* Passing Function Arguments on the Stack */
1283 /* Implements PUSH_ROUNDING. The R8C and M16C have byte stacks, the
1284 M32C has word stacks. */
1286 m32c_push_rounding (int n
)
1288 if (TARGET_R8C
|| TARGET_M16C
)
1290 return (n
+ 1) & ~1;
1293 /* Passing Arguments in Registers */
1295 /* Implements TARGET_FUNCTION_ARG. Arguments are passed partly in
1296 registers, partly on stack. If our function returns a struct, a
1297 pointer to a buffer for it is at the top of the stack (last thing
1298 pushed). The first few real arguments may be in registers as
1301 R8C/M16C: arg1 in r1 if it's QI or HI (else it's pushed on stack)
1302 arg2 in r2 if it's HI (else pushed on stack)
1304 M32C: arg1 in r0 if it's QI or HI (else it's pushed on stack)
1307 Structs are not passed in registers, even if they fit. Only
1308 integer and pointer types are passed in registers.
1310 Note that when arg1 doesn't fit in r1, arg2 may still be passed in
1312 #undef TARGET_FUNCTION_ARG
1313 #define TARGET_FUNCTION_ARG m32c_function_arg
1315 m32c_function_arg (cumulative_args_t ca_v
,
1316 machine_mode mode
, const_tree type
, bool named
)
1318 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
1320 /* Can return a reg, parallel, or 0 for stack */
1323 fprintf (stderr
, "func_arg %d (%s, %d)\n",
1324 ca
->parm_num
, mode_name
[mode
], named
);
1325 debug_tree ((tree
)type
);
1328 if (mode
== VOIDmode
)
1331 if (ca
->force_mem
|| !named
)
1334 fprintf (stderr
, "func arg: force %d named %d, mem\n", ca
->force_mem
,
1340 if (type
&& INTEGRAL_TYPE_P (type
) && POINTER_TYPE_P (type
))
1343 if (type
&& AGGREGATE_TYPE_P (type
))
1346 switch (ca
->parm_num
)
1349 if (GET_MODE_SIZE (mode
) == 1 || GET_MODE_SIZE (mode
) == 2)
1350 rv
= gen_rtx_REG (mode
, TARGET_A16
? R1_REGNO
: R0_REGNO
);
1354 if (TARGET_A16
&& GET_MODE_SIZE (mode
) == 2)
1355 rv
= gen_rtx_REG (mode
, R2_REGNO
);
1365 #undef TARGET_PASS_BY_REFERENCE
1366 #define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
1368 m32c_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
1369 machine_mode mode ATTRIBUTE_UNUSED
,
1370 const_tree type ATTRIBUTE_UNUSED
,
1371 bool named ATTRIBUTE_UNUSED
)
1376 /* Implements INIT_CUMULATIVE_ARGS. */
1378 m32c_init_cumulative_args (CUMULATIVE_ARGS
* ca
,
1380 rtx libname ATTRIBUTE_UNUSED
,
1382 int n_named_args ATTRIBUTE_UNUSED
)
1384 if (fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fndecl
))
1391 /* Implements TARGET_FUNCTION_ARG_ADVANCE. force_mem is set for
1392 functions returning structures, so we always reset that. Otherwise,
1393 we only need to know the sequence number of the argument to know what
1395 #undef TARGET_FUNCTION_ARG_ADVANCE
1396 #define TARGET_FUNCTION_ARG_ADVANCE m32c_function_arg_advance
1398 m32c_function_arg_advance (cumulative_args_t ca_v
,
1399 machine_mode mode ATTRIBUTE_UNUSED
,
1400 const_tree type ATTRIBUTE_UNUSED
,
1401 bool named ATTRIBUTE_UNUSED
)
1403 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
1411 /* Implements TARGET_FUNCTION_ARG_BOUNDARY. */
1412 #undef TARGET_FUNCTION_ARG_BOUNDARY
1413 #define TARGET_FUNCTION_ARG_BOUNDARY m32c_function_arg_boundary
1415 m32c_function_arg_boundary (machine_mode mode ATTRIBUTE_UNUSED
,
1416 const_tree type ATTRIBUTE_UNUSED
)
1418 return (TARGET_A16
? 8 : 16);
1421 /* Implements FUNCTION_ARG_REGNO_P. */
1423 m32c_function_arg_regno_p (int r
)
1426 return (r
== R0_REGNO
);
1427 return (r
== R1_REGNO
|| r
== R2_REGNO
);
1430 /* HImode and PSImode are the two "native" modes as far as GCC is
1431 concerned, but the chips also support a 32-bit mode which is used
1432 for some opcodes in R8C/M16C and for reset vectors and such. */
1433 #undef TARGET_VALID_POINTER_MODE
1434 #define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
1436 m32c_valid_pointer_mode (machine_mode mode
)
1446 /* How Scalar Function Values Are Returned */
1448 /* Implements TARGET_LIBCALL_VALUE. Most values are returned in $r0, or some
1449 combination of registers starting there (r2r0 for longs, r3r1r2r0
1450 for long long, r3r2r1r0 for doubles), except that that ABI
1451 currently doesn't work because it ends up using all available
1452 general registers and gcc often can't compile it. So, instead, we
1453 return anything bigger than 16 bits in "mem0" (effectively, a
1454 memory location). */
1456 #undef TARGET_LIBCALL_VALUE
1457 #define TARGET_LIBCALL_VALUE m32c_libcall_value
1460 m32c_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
1462 /* return reg or parallel */
1464 /* FIXME: GCC has difficulty returning large values in registers,
1465 because that ties up most of the general registers and gives the
1466 register allocator little to work with. Until we can resolve
1467 this, large values are returned in memory. */
1472 rv
= gen_rtx_PARALLEL (mode
, rtvec_alloc (4));
1473 XVECEXP (rv
, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode
,
1474 gen_rtx_REG (HImode
,
1477 XVECEXP (rv
, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode
,
1478 gen_rtx_REG (HImode
,
1481 XVECEXP (rv
, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode
,
1482 gen_rtx_REG (HImode
,
1485 XVECEXP (rv
, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode
,
1486 gen_rtx_REG (HImode
,
1492 if (TARGET_A24
&& GET_MODE_SIZE (mode
) > 2)
1496 rv
= gen_rtx_PARALLEL (mode
, rtvec_alloc (1));
1497 XVECEXP (rv
, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode
,
1505 if (GET_MODE_SIZE (mode
) > 2)
1506 return gen_rtx_REG (mode
, MEM0_REGNO
);
1507 return gen_rtx_REG (mode
, R0_REGNO
);
1510 /* Implements TARGET_FUNCTION_VALUE. Functions and libcalls have the same
1513 #undef TARGET_FUNCTION_VALUE
1514 #define TARGET_FUNCTION_VALUE m32c_function_value
1517 m32c_function_value (const_tree valtype
,
1518 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1519 bool outgoing ATTRIBUTE_UNUSED
)
1521 /* return reg or parallel */
1522 const machine_mode mode
= TYPE_MODE (valtype
);
1523 return m32c_libcall_value (mode
, NULL_RTX
);
1526 /* Implements TARGET_FUNCTION_VALUE_REGNO_P. */
1528 #undef TARGET_FUNCTION_VALUE_REGNO_P
1529 #define TARGET_FUNCTION_VALUE_REGNO_P m32c_function_value_regno_p
1532 m32c_function_value_regno_p (const unsigned int regno
)
1534 return (regno
== R0_REGNO
|| regno
== MEM0_REGNO
);
1537 /* How Large Values Are Returned */
1539 /* We return structures by pushing the address on the stack, even if
1540 we use registers for the first few "real" arguments. */
1541 #undef TARGET_STRUCT_VALUE_RTX
1542 #define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
1544 m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED
,
1545 int incoming ATTRIBUTE_UNUSED
)
1550 /* Function Entry and Exit */
1552 /* Implements EPILOGUE_USES. Interrupts restore all registers. */
1554 m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
1556 if (cfun
->machine
->is_interrupt
)
1561 /* Implementing the Varargs Macros */
1563 #undef TARGET_STRICT_ARGUMENT_NAMING
1564 #define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
1566 m32c_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
1571 /* Trampolines for Nested Functions */
1575 1 0000 75C43412 mov.w #0x1234,a0
1576 2 0004 FC000000 jmp.a label
1579 1 0000 BC563412 mov.l:s #0x123456,a0
1580 2 0004 CC000000 jmp.a label
1583 /* Implements TRAMPOLINE_SIZE. */
1585 m32c_trampoline_size (void)
1587 /* Allocate extra space so we can avoid the messy shifts when we
1588 initialize the trampoline; we just write past the end of the
1590 return TARGET_A16
? 8 : 10;
1593 /* Implements TRAMPOLINE_ALIGNMENT. */
1595 m32c_trampoline_alignment (void)
1600 /* Implements TARGET_TRAMPOLINE_INIT. */
1602 #undef TARGET_TRAMPOLINE_INIT
1603 #define TARGET_TRAMPOLINE_INIT m32c_trampoline_init
1605 m32c_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chainval
)
1607 rtx function
= XEXP (DECL_RTL (fndecl
), 0);
1609 #define A0(m,i) adjust_address (m_tramp, m, i)
1612 /* Note: we subtract a "word" because the moves want signed
1613 constants, not unsigned constants. */
1614 emit_move_insn (A0 (HImode
, 0), GEN_INT (0xc475 - 0x10000));
1615 emit_move_insn (A0 (HImode
, 2), chainval
);
1616 emit_move_insn (A0 (QImode
, 4), GEN_INT (0xfc - 0x100));
1617 /* We use 16-bit addresses here, but store the zero to turn it
1618 into a 24-bit offset. */
1619 emit_move_insn (A0 (HImode
, 5), function
);
1620 emit_move_insn (A0 (QImode
, 7), GEN_INT (0x00));
1624 /* Note that the PSI moves actually write 4 bytes. Make sure we
1625 write stuff out in the right order, and leave room for the
1626 extra byte at the end. */
1627 emit_move_insn (A0 (QImode
, 0), GEN_INT (0xbc - 0x100));
1628 emit_move_insn (A0 (PSImode
, 1), chainval
);
1629 emit_move_insn (A0 (QImode
, 4), GEN_INT (0xcc - 0x100));
1630 emit_move_insn (A0 (PSImode
, 5), function
);
1635 /* Addressing Modes */
1637 /* The r8c/m32c family supports a wide range of non-orthogonal
1638 addressing modes, including the ability to double-indirect on *some*
1639 of them. Not all insns support all modes, either, but we rely on
1640 predicates and constraints to deal with that. */
1641 #undef TARGET_LEGITIMATE_ADDRESS_P
1642 #define TARGET_LEGITIMATE_ADDRESS_P m32c_legitimate_address_p
1644 m32c_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1650 if (TARGET_A16
&& GET_MODE (x
) != HImode
&& GET_MODE (x
) != SImode
)
1652 if (TARGET_A24
&& GET_MODE (x
) != PSImode
)
1655 /* Wide references to memory will be split after reload, so we must
1656 ensure that all parts of such splits remain legitimate
1658 mode_adjust
= GET_MODE_SIZE (mode
) - 1;
1660 /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
1661 if (GET_CODE (x
) == PRE_DEC
1662 || GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_MODIFY
)
1664 return (GET_CODE (XEXP (x
, 0)) == REG
1665 && REGNO (XEXP (x
, 0)) == SP_REGNO
);
1669 /* This is the double indirection detection, but it currently
1670 doesn't work as cleanly as this code implies, so until we've had
1671 a chance to debug it, leave it disabled. */
1672 if (TARGET_A24
&& GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) != PLUS
)
1675 fprintf (stderr
, "double indirect\n");
1684 /* Most indexable registers can be used without displacements,
1685 although some of them will be emitted with an explicit zero
1686 to please the assembler. */
1687 switch (REGNO (patternr
[0]))
1693 if (TARGET_A16
&& GET_MODE (x
) == SImode
)
1699 if (IS_PSEUDO (patternr
[0], strict
))
1705 if (TARGET_A16
&& GET_MODE (x
) == SImode
)
1710 /* This is more interesting, because different base registers
1711 allow for different displacements - both range and signedness
1712 - and it differs from chip series to chip series too. */
1713 int rn
= REGNO (patternr
[1]);
1714 HOST_WIDE_INT offs
= INTVAL (patternr
[2]);
1720 /* The syntax only allows positive offsets, but when the
1721 offsets span the entire memory range, we can simulate
1722 negative offsets by wrapping. */
1724 return (offs
>= -65536 && offs
<= 65535 - mode_adjust
);
1726 return (offs
>= 0 && offs
<= 65535 - mode_adjust
);
1728 return (offs
>= -16777216 && offs
<= 16777215);
1732 return (offs
>= -128 && offs
<= 127 - mode_adjust
);
1733 return (offs
>= -65536 && offs
<= 65535 - mode_adjust
);
1736 return (offs
>= -128 && offs
<= 127 - mode_adjust
);
1739 if (IS_PSEUDO (patternr
[1], strict
))
1744 if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
1746 rtx reg
= patternr
[1];
1748 /* We don't know where the symbol is, so only allow base
1749 registers which support displacements spanning the whole
1751 switch (REGNO (reg
))
1755 /* $sb needs a secondary reload, but since it's involved in
1756 memory address reloads too, we don't deal with it very
1758 /* case SB_REGNO: */
1761 if (GET_CODE (reg
) == SUBREG
)
1763 if (IS_PSEUDO (reg
, strict
))
1771 /* Implements REG_OK_FOR_BASE_P. */
1773 m32c_reg_ok_for_base_p (rtx x
, int strict
)
1775 if (GET_CODE (x
) != REG
)
1786 if (IS_PSEUDO (x
, strict
))
1792 /* We have three choices for choosing fb->aN offsets. If we choose -128,
1793 we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,
1795 EB 4B FF mova -128[$fb],$a0
1796 D8 0C FF FF mov.w:Q #0,-1[$a0]
1798 Alternately, we subtract the frame size, and hopefully use 8-bit aN
1801 77 54 00 01 sub #256,$a0
1802 D8 08 01 mov.w:Q #0,1[$a0]
1804 If we don't offset (i.e. offset by zero), we end up with:
1806 D8 0C 00 FF mov.w:Q #0,-256[$a0]
1808 We have to subtract *something* so that we have a PLUS rtx to mark
1809 that we've done this reload. The -128 offset will never result in
1810 an 8-bit aN offset, and the payoff for the second case is five
1811 loads *if* those loads are within 256 bytes of the other end of the
1812 frame, so the third case seems best. Note that we subtract the
1813 zero, but detect that in the addhi3 pattern. */
1815 #define BIG_FB_ADJ 0
1817 /* Implements LEGITIMIZE_ADDRESS. The only address we really have to
1818 worry about is frame base offsets, as $fb has a limited
1819 displacement range. We deal with this by attempting to reload $fb
1820 itself into an address register; that seems to result in the best
1822 #undef TARGET_LEGITIMIZE_ADDRESS
1823 #define TARGET_LEGITIMIZE_ADDRESS m32c_legitimize_address
1825 m32c_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1829 fprintf (stderr
, "m32c_legitimize_address for mode %s\n", mode_name
[mode
]);
1831 fprintf (stderr
, "\n");
1834 if (GET_CODE (x
) == PLUS
1835 && GET_CODE (XEXP (x
, 0)) == REG
1836 && REGNO (XEXP (x
, 0)) == FB_REGNO
1837 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1838 && (INTVAL (XEXP (x
, 1)) < -128
1839 || INTVAL (XEXP (x
, 1)) > (128 - GET_MODE_SIZE (mode
))))
1841 /* reload FB to A_REGS */
1842 rtx temp
= gen_reg_rtx (Pmode
);
1844 emit_insn (gen_rtx_SET (temp
, XEXP (x
, 0)));
1851 /* Implements LEGITIMIZE_RELOAD_ADDRESS. See comment above. */
1853 m32c_legitimize_reload_address (rtx
* x
,
1856 int type
, int ind_levels ATTRIBUTE_UNUSED
)
1859 fprintf (stderr
, "\nm32c_legitimize_reload_address for mode %s\n",
1864 /* At one point, this function tried to get $fb copied to an address
1865 register, which in theory would maximize sharing, but gcc was
1866 *also* still trying to reload the whole address, and we'd run out
1867 of address registers. So we let gcc do the naive (but safe)
1868 reload instead, when the above function doesn't handle it for
1871 The code below is a second attempt at the above. */
1873 if (GET_CODE (*x
) == PLUS
1874 && GET_CODE (XEXP (*x
, 0)) == REG
1875 && REGNO (XEXP (*x
, 0)) == FB_REGNO
1876 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
1877 && (INTVAL (XEXP (*x
, 1)) < -128
1878 || INTVAL (XEXP (*x
, 1)) > (128 - GET_MODE_SIZE (mode
))))
1881 int offset
= INTVAL (XEXP (*x
, 1));
1882 int adjustment
= -BIG_FB_ADJ
;
1884 sum
= gen_rtx_PLUS (Pmode
, XEXP (*x
, 0),
1885 GEN_INT (adjustment
));
1886 *x
= gen_rtx_PLUS (Pmode
, sum
, GEN_INT (offset
- adjustment
));
1887 if (type
== RELOAD_OTHER
)
1888 type
= RELOAD_FOR_OTHER_ADDRESS
;
1889 push_reload (sum
, NULL_RTX
, &XEXP (*x
, 0), NULL
,
1890 A_REGS
, Pmode
, VOIDmode
, 0, 0, opnum
,
1891 (enum reload_type
) type
);
1895 if (GET_CODE (*x
) == PLUS
1896 && GET_CODE (XEXP (*x
, 0)) == PLUS
1897 && GET_CODE (XEXP (XEXP (*x
, 0), 0)) == REG
1898 && REGNO (XEXP (XEXP (*x
, 0), 0)) == FB_REGNO
1899 && GET_CODE (XEXP (XEXP (*x
, 0), 1)) == CONST_INT
1900 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
1903 if (type
== RELOAD_OTHER
)
1904 type
= RELOAD_FOR_OTHER_ADDRESS
;
1905 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1906 A_REGS
, Pmode
, VOIDmode
, 0, 0, opnum
,
1907 (enum reload_type
) type
);
1911 if (TARGET_A24
&& GET_MODE (*x
) == PSImode
)
1913 push_reload (*x
, NULL_RTX
, x
, NULL
,
1914 A_REGS
, PSImode
, VOIDmode
, 0, 0, opnum
,
1915 (enum reload_type
) type
);
1922 /* Return the appropriate mode for a named address pointer. */
1923 #undef TARGET_ADDR_SPACE_POINTER_MODE
1924 #define TARGET_ADDR_SPACE_POINTER_MODE m32c_addr_space_pointer_mode
1926 m32c_addr_space_pointer_mode (addr_space_t addrspace
)
1930 case ADDR_SPACE_GENERIC
:
1931 return TARGET_A24
? PSImode
: HImode
;
1932 case ADDR_SPACE_FAR
:
1939 /* Return the appropriate mode for a named address address. */
1940 #undef TARGET_ADDR_SPACE_ADDRESS_MODE
1941 #define TARGET_ADDR_SPACE_ADDRESS_MODE m32c_addr_space_address_mode
1943 m32c_addr_space_address_mode (addr_space_t addrspace
)
1947 case ADDR_SPACE_GENERIC
:
1948 return TARGET_A24
? PSImode
: HImode
;
1949 case ADDR_SPACE_FAR
:
1956 /* Like m32c_legitimate_address_p, except with named addresses. */
1957 #undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P
1958 #define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P \
1959 m32c_addr_space_legitimate_address_p
1961 m32c_addr_space_legitimate_address_p (machine_mode mode
, rtx x
,
1962 bool strict
, addr_space_t as
)
1964 if (as
== ADDR_SPACE_FAR
)
1971 if (GET_MODE (x
) != SImode
)
1973 switch (REGNO (patternr
[0]))
1979 if (IS_PSEUDO (patternr
[0], strict
))
1984 if (RTX_IS ("+^Sri"))
1986 int rn
= REGNO (patternr
[3]);
1987 HOST_WIDE_INT offs
= INTVAL (patternr
[4]);
1988 if (GET_MODE (patternr
[3]) != HImode
)
1993 return (offs
>= 0 && offs
<= 0xfffff);
1996 if (IS_PSEUDO (patternr
[3], strict
))
2001 if (RTX_IS ("+^Srs"))
2003 int rn
= REGNO (patternr
[3]);
2004 if (GET_MODE (patternr
[3]) != HImode
)
2012 if (IS_PSEUDO (patternr
[3], strict
))
2017 if (RTX_IS ("+^S+ris"))
2019 int rn
= REGNO (patternr
[4]);
2020 if (GET_MODE (patternr
[4]) != HImode
)
2028 if (IS_PSEUDO (patternr
[4], strict
))
2040 else if (as
!= ADDR_SPACE_GENERIC
)
2043 return m32c_legitimate_address_p (mode
, x
, strict
);
2046 /* Like m32c_legitimate_address, except with named address support. */
2047 #undef TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS
2048 #define TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS m32c_addr_space_legitimize_address
2050 m32c_addr_space_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
,
2053 if (as
!= ADDR_SPACE_GENERIC
)
2056 fprintf (stderr
, "\033[36mm32c_addr_space_legitimize_address for mode %s\033[0m\n", mode_name
[mode
]);
2058 fprintf (stderr
, "\n");
2061 if (GET_CODE (x
) != REG
)
2063 x
= force_reg (SImode
, x
);
2068 return m32c_legitimize_address (x
, oldx
, mode
);
2071 /* Determine if one named address space is a subset of another. */
2072 #undef TARGET_ADDR_SPACE_SUBSET_P
2073 #define TARGET_ADDR_SPACE_SUBSET_P m32c_addr_space_subset_p
2075 m32c_addr_space_subset_p (addr_space_t subset
, addr_space_t superset
)
2077 gcc_assert (subset
== ADDR_SPACE_GENERIC
|| subset
== ADDR_SPACE_FAR
);
2078 gcc_assert (superset
== ADDR_SPACE_GENERIC
|| superset
== ADDR_SPACE_FAR
);
2080 if (subset
== superset
)
2084 return (subset
== ADDR_SPACE_GENERIC
&& superset
== ADDR_SPACE_FAR
);
2087 #undef TARGET_ADDR_SPACE_CONVERT
2088 #define TARGET_ADDR_SPACE_CONVERT m32c_addr_space_convert
2089 /* Convert from one address space to another. */
2091 m32c_addr_space_convert (rtx op
, tree from_type
, tree to_type
)
2093 addr_space_t from_as
= TYPE_ADDR_SPACE (TREE_TYPE (from_type
));
2094 addr_space_t to_as
= TYPE_ADDR_SPACE (TREE_TYPE (to_type
));
2097 gcc_assert (from_as
== ADDR_SPACE_GENERIC
|| from_as
== ADDR_SPACE_FAR
);
2098 gcc_assert (to_as
== ADDR_SPACE_GENERIC
|| to_as
== ADDR_SPACE_FAR
);
2100 if (to_as
== ADDR_SPACE_GENERIC
&& from_as
== ADDR_SPACE_FAR
)
2102 /* This is unpredictable, as we're truncating off usable address
2105 result
= gen_reg_rtx (HImode
);
2106 emit_move_insn (result
, simplify_subreg (HImode
, op
, SImode
, 0));
2109 else if (to_as
== ADDR_SPACE_FAR
&& from_as
== ADDR_SPACE_GENERIC
)
2111 /* This always works. */
2112 result
= gen_reg_rtx (SImode
);
2113 emit_insn (gen_zero_extendhisi2 (result
, op
));
2120 /* Condition Code Status */
2122 #undef TARGET_FIXED_CONDITION_CODE_REGS
2123 #define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
2125 m32c_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
2128 *p2
= INVALID_REGNUM
;
2132 /* Describing Relative Costs of Operations */
2134 /* Implements TARGET_REGISTER_MOVE_COST. We make impossible moves
2135 prohibitively expensive, like trying to put QIs in r2/r3 (there are
2136 no opcodes to do that). We also discourage use of mem* registers
2137 since they're really memory. */
2139 #undef TARGET_REGISTER_MOVE_COST
2140 #define TARGET_REGISTER_MOVE_COST m32c_register_move_cost
2143 m32c_register_move_cost (machine_mode mode
, reg_class_t from
,
2146 int cost
= COSTS_N_INSNS (3);
2149 /* FIXME: pick real values, but not 2 for now. */
2150 COPY_HARD_REG_SET (cc
, reg_class_contents
[(int) from
]);
2151 IOR_HARD_REG_SET (cc
, reg_class_contents
[(int) to
]);
2154 && hard_reg_set_intersect_p (cc
, reg_class_contents
[R23_REGS
]))
2156 if (hard_reg_set_subset_p (cc
, reg_class_contents
[R23_REGS
]))
2157 cost
= COSTS_N_INSNS (1000);
2159 cost
= COSTS_N_INSNS (80);
2162 if (!class_can_hold_mode (from
, mode
) || !class_can_hold_mode (to
, mode
))
2163 cost
= COSTS_N_INSNS (1000);
2165 if (reg_classes_intersect_p (from
, CR_REGS
))
2166 cost
+= COSTS_N_INSNS (5);
2168 if (reg_classes_intersect_p (to
, CR_REGS
))
2169 cost
+= COSTS_N_INSNS (5);
2171 if (from
== MEM_REGS
|| to
== MEM_REGS
)
2172 cost
+= COSTS_N_INSNS (50);
2173 else if (reg_classes_intersect_p (from
, MEM_REGS
)
2174 || reg_classes_intersect_p (to
, MEM_REGS
))
2175 cost
+= COSTS_N_INSNS (10);
2178 fprintf (stderr
, "register_move_cost %s from %s to %s = %d\n",
2179 mode_name
[mode
], class_names
[(int) from
], class_names
[(int) to
],
2185 /* Implements TARGET_MEMORY_MOVE_COST. */
2187 #undef TARGET_MEMORY_MOVE_COST
2188 #define TARGET_MEMORY_MOVE_COST m32c_memory_move_cost
2191 m32c_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
2192 reg_class_t rclass ATTRIBUTE_UNUSED
,
2193 bool in ATTRIBUTE_UNUSED
)
2195 /* FIXME: pick real values. */
2196 return COSTS_N_INSNS (10);
2199 /* Here we try to describe when we use multiple opcodes for one RTX so
2200 that gcc knows when to use them. */
2201 #undef TARGET_RTX_COSTS
2202 #define TARGET_RTX_COSTS m32c_rtx_costs
2204 m32c_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
2205 int opno ATTRIBUTE_UNUSED
,
2206 int *total
, bool speed ATTRIBUTE_UNUSED
)
2208 int code
= GET_CODE (x
);
2212 if (REGNO (x
) >= MEM0_REGNO
&& REGNO (x
) <= MEM7_REGNO
)
2213 *total
+= COSTS_N_INSNS (500);
2215 *total
+= COSTS_N_INSNS (1);
2221 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
2223 /* mov.b r1l, r1h */
2224 *total
+= COSTS_N_INSNS (1);
2227 if (INTVAL (XEXP (x
, 1)) > 8
2228 || INTVAL (XEXP (x
, 1)) < -8)
2231 /* mov.b r1l, r1h */
2232 *total
+= COSTS_N_INSNS (2);
2247 if (outer_code
== SET
)
2249 *total
+= COSTS_N_INSNS (2);
2256 rtx dest
= XEXP (x
, 0);
2257 rtx addr
= XEXP (dest
, 0);
2258 switch (GET_CODE (addr
))
2261 *total
+= COSTS_N_INSNS (1);
2264 *total
+= COSTS_N_INSNS (3);
2267 *total
+= COSTS_N_INSNS (2);
2275 /* Reasonable default. */
2276 if (TARGET_A16
&& mode
== SImode
)
2277 *total
+= COSTS_N_INSNS (2);
2283 #undef TARGET_ADDRESS_COST
2284 #define TARGET_ADDRESS_COST m32c_address_cost
2286 m32c_address_cost (rtx addr
, machine_mode mode ATTRIBUTE_UNUSED
,
2287 addr_space_t as ATTRIBUTE_UNUSED
,
2288 bool speed ATTRIBUTE_UNUSED
)
2291 /* fprintf(stderr, "\naddress_cost\n");
2293 switch (GET_CODE (addr
))
2298 return COSTS_N_INSNS(1);
2299 if (0 < i
&& i
<= 255)
2300 return COSTS_N_INSNS(2);
2301 if (0 < i
&& i
<= 65535)
2302 return COSTS_N_INSNS(3);
2303 return COSTS_N_INSNS(4);
2305 return COSTS_N_INSNS(4);
2307 return COSTS_N_INSNS(1);
2309 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
2311 i
= INTVAL (XEXP (addr
, 1));
2313 return COSTS_N_INSNS(1);
2314 if (0 < i
&& i
<= 255)
2315 return COSTS_N_INSNS(2);
2316 if (0 < i
&& i
<= 65535)
2317 return COSTS_N_INSNS(3);
2319 return COSTS_N_INSNS(4);
2325 /* Defining the Output Assembler Language */
2327 /* Output of Data */
2329 /* We may have 24 bit sizes, which is the native address size.
2330 Currently unused, but provided for completeness. */
2331 #undef TARGET_ASM_INTEGER
2332 #define TARGET_ASM_INTEGER m32c_asm_integer
2334 m32c_asm_integer (rtx x
, unsigned int size
, int aligned_p
)
2339 fprintf (asm_out_file
, "\t.3byte\t");
2340 output_addr_const (asm_out_file
, x
);
2341 fputc ('\n', asm_out_file
);
2344 if (GET_CODE (x
) == SYMBOL_REF
)
2346 fprintf (asm_out_file
, "\t.long\t");
2347 output_addr_const (asm_out_file
, x
);
2348 fputc ('\n', asm_out_file
);
2353 return default_assemble_integer (x
, size
, aligned_p
);
2356 /* Output of Assembler Instructions */
2358 /* We use a lookup table because the addressing modes are non-orthogonal. */
2363 char const *pattern
;
2366 const conversions
[] = {
2369 { 0, "mr", "z[1]" },
2370 { 0, "m+ri", "3[2]" },
2371 { 0, "m+rs", "3[2]" },
2372 { 0, "m+^Zrs", "5[4]" },
2373 { 0, "m+^Zri", "5[4]" },
2374 { 0, "m+^Z+ris", "7+6[5]" },
2375 { 0, "m+^Srs", "5[4]" },
2376 { 0, "m+^Sri", "5[4]" },
2377 { 0, "m+^S+ris", "7+6[5]" },
2378 { 0, "m+r+si", "4+5[2]" },
2381 { 0, "m+si", "2+3" },
2383 { 0, "mmr", "[z[2]]" },
2384 { 0, "mm+ri", "[4[3]]" },
2385 { 0, "mm+rs", "[4[3]]" },
2386 { 0, "mm+r+si", "[5+6[3]]" },
2387 { 0, "mms", "[[2]]" },
2388 { 0, "mmi", "[[2]]" },
2389 { 0, "mm+si", "[4[3]]" },
2393 { 0, "+si", "#1+2" },
2399 { 'd', "+si", "1+2" },
2402 { 'D', "+si", "1+2" },
2413 /* This is in order according to the bitfield that pushm/popm use. */
2414 static char const *pushm_regs
[] = {
2415 "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
2418 /* Implements TARGET_PRINT_OPERAND. */
2420 #undef TARGET_PRINT_OPERAND
2421 #define TARGET_PRINT_OPERAND m32c_print_operand
2424 m32c_print_operand (FILE * file
, rtx x
, int code
)
2429 int unsigned_const
= 0;
2432 /* Multiplies; constants are converted to sign-extended format but
2433 we need unsigned, so 'u' and 'U' tell us what size unsigned we
2445 /* This one is only for debugging; you can put it in a pattern to
2446 force this error. */
2449 fprintf (stderr
, "dj: unreviewed pattern:");
2450 if (current_output_insn
)
2451 debug_rtx (current_output_insn
);
2454 /* PSImode operations are either .w or .l depending on the target. */
2458 fprintf (file
, "w");
2460 fprintf (file
, "l");
2463 /* Inverted conditionals. */
2466 switch (GET_CODE (x
))
2472 fputs ("gtu", file
);
2478 fputs ("geu", file
);
2484 fputs ("leu", file
);
2490 fputs ("ltu", file
);
2503 /* Regular conditionals. */
2506 switch (GET_CODE (x
))
2512 fputs ("leu", file
);
2518 fputs ("ltu", file
);
2524 fputs ("gtu", file
);
2530 fputs ("geu", file
);
2543 /* Used in negsi2 to do HImode ops on the two parts of an SImode
2545 if (code
== 'h' && GET_MODE (x
) == SImode
)
2547 x
= m32c_subreg (HImode
, x
, SImode
, 0);
2550 if (code
== 'H' && GET_MODE (x
) == SImode
)
2552 x
= m32c_subreg (HImode
, x
, SImode
, 2);
2555 if (code
== 'h' && GET_MODE (x
) == HImode
)
2557 x
= m32c_subreg (QImode
, x
, HImode
, 0);
2560 if (code
== 'H' && GET_MODE (x
) == HImode
)
2562 /* We can't actually represent this as an rtx. Do it here. */
2563 if (GET_CODE (x
) == REG
)
2568 fputs ("r0h", file
);
2571 fputs ("r1h", file
);
2577 /* This should be a MEM. */
2578 x
= m32c_subreg (QImode
, x
, HImode
, 1);
2581 /* This is for BMcond, which always wants word register names. */
2582 if (code
== 'h' && GET_MODE (x
) == QImode
)
2584 if (GET_CODE (x
) == REG
)
2585 x
= gen_rtx_REG (HImode
, REGNO (x
));
2588 /* 'x' and 'X' need to be ignored for non-immediates. */
2589 if ((code
== 'x' || code
== 'X') && GET_CODE (x
) != CONST_INT
)
2594 for (i
= 0; conversions
[i
].pattern
; i
++)
2595 if (conversions
[i
].code
== code
2596 && streq (conversions
[i
].pattern
, pattern
))
2598 for (j
= 0; conversions
[i
].format
[j
]; j
++)
2599 /* backslash quotes the next character in the output pattern. */
2600 if (conversions
[i
].format
[j
] == '\\')
2602 fputc (conversions
[i
].format
[j
+ 1], file
);
2605 /* Digits in the output pattern indicate that the
2606 corresponding RTX is to be output at that point. */
2607 else if (ISDIGIT (conversions
[i
].format
[j
]))
2609 rtx r
= patternr
[conversions
[i
].format
[j
] - '0'];
2610 switch (GET_CODE (r
))
2613 fprintf (file
, "%s",
2614 reg_name_with_mode (REGNO (r
), GET_MODE (r
)));
2623 int i
= (int) exact_log2 (v
);
2625 i
= (int) exact_log2 ((v
^ 0xffff) & 0xffff);
2627 i
= (int) exact_log2 ((v
^ 0xff) & 0xff);
2629 fprintf (file
, "%d", i
);
2633 /* Unsigned byte. */
2634 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2638 /* Unsigned word. */
2639 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2640 INTVAL (r
) & 0xffff);
2643 /* pushm and popm encode a register set into a single byte. */
2645 for (b
= 7; b
>= 0; b
--)
2646 if (INTVAL (r
) & (1 << b
))
2648 fprintf (file
, "%s%s", comma
, pushm_regs
[b
]);
2653 /* "Minus". Output -X */
2654 ival
= (-INTVAL (r
) & 0xffff);
2656 ival
= ival
- 0x10000;
2657 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
2661 if (conversions
[i
].format
[j
+ 1] == '[' && ival
< 0)
2663 /* We can simulate negative displacements by
2664 taking advantage of address space
2665 wrapping when the offset can span the
2666 entire address range. */
2668 patternr
[conversions
[i
].format
[j
+ 2] - '0'];
2669 if (GET_CODE (base
) == REG
)
2670 switch (REGNO (base
))
2675 ival
= 0x1000000 + ival
;
2677 ival
= 0x10000 + ival
;
2681 ival
= 0x10000 + ival
;
2685 else if (code
== 'd' && ival
< 0 && j
== 0)
2686 /* The "mova" opcode is used to do addition by
2687 computing displacements, but again, we need
2688 displacements to be unsigned *if* they're
2689 the only component of the displacement
2690 (i.e. no "symbol-4" type displacement). */
2691 ival
= (TARGET_A24
? 0x1000000 : 0x10000) + ival
;
2693 if (conversions
[i
].format
[j
] == '0')
2695 /* More conversions to unsigned. */
2696 if (unsigned_const
== 2)
2698 if (unsigned_const
== 1)
2701 if (streq (conversions
[i
].pattern
, "mi")
2702 || streq (conversions
[i
].pattern
, "mmi"))
2704 /* Integers used as addresses are unsigned. */
2705 ival
&= (TARGET_A24
? 0xffffff : 0xffff);
2707 if (force_sign
&& ival
>= 0)
2709 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
2714 /* We don't have const_double constants. If it
2715 happens, make it obvious. */
2716 fprintf (file
, "[const_double 0x%lx]",
2717 (unsigned long) CONST_DOUBLE_HIGH (r
));
2720 assemble_name (file
, XSTR (r
, 0));
2723 output_asm_label (r
);
2726 fprintf (stderr
, "don't know how to print this operand:");
2733 if (conversions
[i
].format
[j
] == 'z')
2735 /* Some addressing modes *must* have a displacement,
2736 so insert a zero here if needed. */
2738 for (k
= j
+ 1; conversions
[i
].format
[k
]; k
++)
2739 if (ISDIGIT (conversions
[i
].format
[k
]))
2741 rtx reg
= patternr
[conversions
[i
].format
[k
] - '0'];
2742 if (GET_CODE (reg
) == REG
2743 && (REGNO (reg
) == SB_REGNO
2744 || REGNO (reg
) == FB_REGNO
2745 || REGNO (reg
) == SP_REGNO
))
2750 /* Signed displacements off symbols need to have signs
2752 if (conversions
[i
].format
[j
] == '+'
2753 && (!code
|| code
== 'D' || code
== 'd')
2754 && ISDIGIT (conversions
[i
].format
[j
+ 1])
2755 && (GET_CODE (patternr
[conversions
[i
].format
[j
+ 1] - '0'])
2761 fputc (conversions
[i
].format
[j
], file
);
2765 if (!conversions
[i
].pattern
)
2767 fprintf (stderr
, "unconvertible operand %c `%s'", code
? code
: '-',
2770 fprintf (file
, "[%c.%s]", code
? code
: '-', pattern
);
2776 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P.
2778 See m32c_print_operand above for descriptions of what these do. */
2780 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
2781 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P m32c_print_operand_punct_valid_p
2784 m32c_print_operand_punct_valid_p (unsigned char c
)
2786 if (c
== '&' || c
== '!')
2792 /* Implements TARGET_PRINT_OPERAND_ADDRESS. Nothing unusual here. */
2794 #undef TARGET_PRINT_OPERAND_ADDRESS
2795 #define TARGET_PRINT_OPERAND_ADDRESS m32c_print_operand_address
2798 m32c_print_operand_address (FILE * stream
, machine_mode
/*mode*/, rtx address
)
2800 if (GET_CODE (address
) == MEM
)
2801 address
= XEXP (address
, 0);
2803 /* cf: gcc.dg/asm-4.c. */
2804 gcc_assert (GET_CODE (address
) == REG
);
2806 m32c_print_operand (stream
, address
, 0);
2809 /* Implements ASM_OUTPUT_REG_PUSH. Control registers are pushed
2810 differently than general registers. */
2812 m32c_output_reg_push (FILE * s
, int regno
)
2814 if (regno
== FLG_REGNO
)
2815 fprintf (s
, "\tpushc\tflg\n");
2817 fprintf (s
, "\tpush.%c\t%s\n",
2818 " bwll"[reg_push_size (regno
)], reg_names
[regno
]);
2821 /* Likewise for ASM_OUTPUT_REG_POP. */
2823 m32c_output_reg_pop (FILE * s
, int regno
)
2825 if (regno
== FLG_REGNO
)
2826 fprintf (s
, "\tpopc\tflg\n");
2828 fprintf (s
, "\tpop.%c\t%s\n",
2829 " bwll"[reg_push_size (regno
)], reg_names
[regno
]);
2832 /* Defining target-specific uses of `__attribute__' */
2834 /* Used to simplify the logic below. Find the attributes wherever
2836 #define M32C_ATTRIBUTES(decl) \
2837 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
2838 : DECL_ATTRIBUTES (decl) \
2839 ? (DECL_ATTRIBUTES (decl)) \
2840 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
2842 /* Returns TRUE if the given tree has the "interrupt" attribute. */
2844 interrupt_p (tree node ATTRIBUTE_UNUSED
)
2846 tree list
= M32C_ATTRIBUTES (node
);
2849 if (is_attribute_p ("interrupt", TREE_PURPOSE (list
)))
2851 list
= TREE_CHAIN (list
);
2853 return fast_interrupt_p (node
);
2856 /* Returns TRUE if the given tree has the "bank_switch" attribute. */
2858 bank_switch_p (tree node ATTRIBUTE_UNUSED
)
2860 tree list
= M32C_ATTRIBUTES (node
);
2863 if (is_attribute_p ("bank_switch", TREE_PURPOSE (list
)))
2865 list
= TREE_CHAIN (list
);
2870 /* Returns TRUE if the given tree has the "fast_interrupt" attribute. */
2872 fast_interrupt_p (tree node ATTRIBUTE_UNUSED
)
2874 tree list
= M32C_ATTRIBUTES (node
);
2877 if (is_attribute_p ("fast_interrupt", TREE_PURPOSE (list
)))
2879 list
= TREE_CHAIN (list
);
2885 interrupt_handler (tree
* node ATTRIBUTE_UNUSED
,
2886 tree name ATTRIBUTE_UNUSED
,
2887 tree args ATTRIBUTE_UNUSED
,
2888 int flags ATTRIBUTE_UNUSED
,
2889 bool * no_add_attrs ATTRIBUTE_UNUSED
)
2894 /* Returns TRUE if given tree has the "function_vector" attribute. */
2896 m32c_special_page_vector_p (tree func
)
2900 if (TREE_CODE (func
) != FUNCTION_DECL
)
2903 list
= M32C_ATTRIBUTES (func
);
2906 if (is_attribute_p ("function_vector", TREE_PURPOSE (list
)))
2908 list
= TREE_CHAIN (list
);
2914 function_vector_handler (tree
* node ATTRIBUTE_UNUSED
,
2915 tree name ATTRIBUTE_UNUSED
,
2916 tree args ATTRIBUTE_UNUSED
,
2917 int flags ATTRIBUTE_UNUSED
,
2918 bool * no_add_attrs ATTRIBUTE_UNUSED
)
2922 /* The attribute is not supported for R8C target. */
2923 warning (OPT_Wattributes
,
2924 "%qE attribute is not supported for R8C target",
2926 *no_add_attrs
= true;
2928 else if (TREE_CODE (*node
) != FUNCTION_DECL
)
2930 /* The attribute must be applied to functions only. */
2931 warning (OPT_Wattributes
,
2932 "%qE attribute applies only to functions",
2934 *no_add_attrs
= true;
2936 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
2938 /* The argument must be a constant integer. */
2939 warning (OPT_Wattributes
,
2940 "%qE attribute argument not an integer constant",
2942 *no_add_attrs
= true;
2944 else if (TREE_INT_CST_LOW (TREE_VALUE (args
)) < 18
2945 || TREE_INT_CST_LOW (TREE_VALUE (args
)) > 255)
2947 /* The argument value must be between 18 to 255. */
2948 warning (OPT_Wattributes
,
2949 "%qE attribute argument should be between 18 to 255",
2951 *no_add_attrs
= true;
2956 /* If the function is assigned the attribute 'function_vector', it
2957 returns the function vector number, otherwise returns zero. */
2959 current_function_special_page_vector (rtx x
)
2963 if ((GET_CODE(x
) == SYMBOL_REF
)
2964 && (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_FUNCVEC_FUNCTION
))
2967 tree t
= SYMBOL_REF_DECL (x
);
2969 if (TREE_CODE (t
) != FUNCTION_DECL
)
2972 list
= M32C_ATTRIBUTES (t
);
2975 if (is_attribute_p ("function_vector", TREE_PURPOSE (list
)))
2977 num
= TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list
)));
2981 list
= TREE_CHAIN (list
);
2990 #undef TARGET_ATTRIBUTE_TABLE
2991 #define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
2992 static const struct attribute_spec m32c_attribute_table
[] = {
2993 {"interrupt", 0, 0, false, false, false, interrupt_handler
, false},
2994 {"bank_switch", 0, 0, false, false, false, interrupt_handler
, false},
2995 {"fast_interrupt", 0, 0, false, false, false, interrupt_handler
, false},
2996 {"function_vector", 1, 1, true, false, false, function_vector_handler
,
2998 {0, 0, 0, 0, 0, 0, 0, false}
3001 #undef TARGET_COMP_TYPE_ATTRIBUTES
3002 #define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
3004 m32c_comp_type_attributes (const_tree type1 ATTRIBUTE_UNUSED
,
3005 const_tree type2 ATTRIBUTE_UNUSED
)
3007 /* 0=incompatible 1=compatible 2=warning */
3011 #undef TARGET_INSERT_ATTRIBUTES
3012 #define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
3014 m32c_insert_attributes (tree node ATTRIBUTE_UNUSED
,
3015 tree
* attr_ptr ATTRIBUTE_UNUSED
)
3018 /* See if we need to make #pragma address variables volatile. */
3020 if (TREE_CODE (node
) == VAR_DECL
)
3022 const char *name
= IDENTIFIER_POINTER (DECL_NAME (node
));
3023 if (m32c_get_pragma_address (name
, &addr
))
3025 TREE_THIS_VOLATILE (node
) = true;
3030 /* Hash table of pragma info. */
3031 static GTY(()) hash_map
<nofree_string_hash
, unsigned> *pragma_htab
;
3034 m32c_note_pragma_address (const char *varname
, unsigned address
)
3037 pragma_htab
= hash_map
<nofree_string_hash
, unsigned>::create_ggc (31);
3039 const char *name
= ggc_strdup (varname
);
3040 unsigned int *slot
= &pragma_htab
->get_or_insert (name
);
3045 m32c_get_pragma_address (const char *varname
, unsigned *address
)
3050 unsigned int *slot
= pragma_htab
->get (varname
);
3060 m32c_output_aligned_common (FILE *stream
, tree decl ATTRIBUTE_UNUSED
,
3062 int size
, int align
, int global
)
3066 if (m32c_get_pragma_address (name
, &address
))
3068 /* We never output these as global. */
3069 assemble_name (stream
, name
);
3070 fprintf (stream
, " = 0x%04x\n", address
);
3075 fprintf (stream
, "\t.local\t");
3076 assemble_name (stream
, name
);
3077 fprintf (stream
, "\n");
3079 fprintf (stream
, "\t.comm\t");
3080 assemble_name (stream
, name
);
3081 fprintf (stream
, ",%u,%u\n", size
, align
/ BITS_PER_UNIT
);
3086 /* This is a list of legal subregs of hard regs. */
3087 static const struct {
3088 unsigned char outer_mode_size
;
3089 unsigned char inner_mode_size
;
3090 unsigned char byte_mask
;
3091 unsigned char legal_when
;
3093 } legal_subregs
[] = {
3094 {1, 2, 0x03, 1, R0_REGNO
}, /* r0h r0l */
3095 {1, 2, 0x03, 1, R1_REGNO
}, /* r1h r1l */
3096 {1, 2, 0x01, 1, A0_REGNO
},
3097 {1, 2, 0x01, 1, A1_REGNO
},
3099 {1, 4, 0x01, 1, A0_REGNO
},
3100 {1, 4, 0x01, 1, A1_REGNO
},
3102 {2, 4, 0x05, 1, R0_REGNO
}, /* r2 r0 */
3103 {2, 4, 0x05, 1, R1_REGNO
}, /* r3 r1 */
3104 {2, 4, 0x05, 16, A0_REGNO
}, /* a1 a0 */
3105 {2, 4, 0x01, 24, A0_REGNO
}, /* a1 a0 */
3106 {2, 4, 0x01, 24, A1_REGNO
}, /* a1 a0 */
3108 {4, 8, 0x55, 1, R0_REGNO
}, /* r3 r1 r2 r0 */
3111 /* Returns TRUE if OP is a subreg of a hard reg which we don't
3112 support. We also bail on MEMs with illegal addresses. */
3114 m32c_illegal_subreg_p (rtx op
)
3118 machine_mode src_mode
, dest_mode
;
3120 if (GET_CODE (op
) == MEM
3121 && ! m32c_legitimate_address_p (Pmode
, XEXP (op
, 0), false))
3126 if (GET_CODE (op
) != SUBREG
)
3129 dest_mode
= GET_MODE (op
);
3130 offset
= SUBREG_BYTE (op
);
3131 op
= SUBREG_REG (op
);
3132 src_mode
= GET_MODE (op
);
3134 if (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (src_mode
))
3136 if (GET_CODE (op
) != REG
)
3138 if (REGNO (op
) >= MEM0_REGNO
)
3141 offset
= (1 << offset
);
3143 for (i
= 0; i
< ARRAY_SIZE (legal_subregs
); i
++)
3144 if (legal_subregs
[i
].outer_mode_size
== GET_MODE_SIZE (dest_mode
)
3145 && legal_subregs
[i
].regno
== REGNO (op
)
3146 && legal_subregs
[i
].inner_mode_size
== GET_MODE_SIZE (src_mode
)
3147 && legal_subregs
[i
].byte_mask
& offset
)
3149 switch (legal_subregs
[i
].legal_when
)
3166 /* Returns TRUE if we support a move between the first two operands.
3167 At the moment, we just want to discourage mem to mem moves until
3168 after reload, because reload has a hard time with our limited
3169 number of address registers, and we can get into a situation where
3170 we need three of them when we only have two. */
3172 m32c_mov_ok (rtx
* operands
, machine_mode mode ATTRIBUTE_UNUSED
)
3174 rtx op0
= operands
[0];
3175 rtx op1
= operands
[1];
3180 #define DEBUG_MOV_OK 0
3182 fprintf (stderr
, "m32c_mov_ok %s\n", mode_name
[mode
]);
3187 if (GET_CODE (op0
) == SUBREG
)
3188 op0
= XEXP (op0
, 0);
3189 if (GET_CODE (op1
) == SUBREG
)
3190 op1
= XEXP (op1
, 0);
3192 if (GET_CODE (op0
) == MEM
3193 && GET_CODE (op1
) == MEM
3194 && ! reload_completed
)
3197 fprintf (stderr
, " - no, mem to mem\n");
3203 fprintf (stderr
, " - ok\n");
3208 /* Returns TRUE if two consecutive HImode mov instructions, generated
3209 for moving an immediate double data to a double data type variable
3210 location, can be combined into single SImode mov instruction. */
3212 m32c_immd_dbl_mov (rtx
* operands ATTRIBUTE_UNUSED
,
3213 machine_mode mode ATTRIBUTE_UNUSED
)
3215 /* ??? This relied on the now-defunct MEM_SCALAR and MEM_IN_STRUCT_P
3222 /* Subregs are non-orthogonal for us, because our registers are all
3225 m32c_subreg (machine_mode outer
,
3226 rtx x
, machine_mode inner
, int byte
)
3230 /* Converting MEMs to different types that are the same size, we
3231 just rewrite them. */
3232 if (GET_CODE (x
) == SUBREG
3233 && SUBREG_BYTE (x
) == 0
3234 && GET_CODE (SUBREG_REG (x
)) == MEM
3235 && (GET_MODE_SIZE (GET_MODE (x
))
3236 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
3239 x
= gen_rtx_MEM (GET_MODE (x
), XEXP (SUBREG_REG (x
), 0));
3240 MEM_COPY_ATTRIBUTES (x
, SUBREG_REG (oldx
));
3243 /* Push/pop get done as smaller push/pops. */
3244 if (GET_CODE (x
) == MEM
3245 && (GET_CODE (XEXP (x
, 0)) == PRE_DEC
3246 || GET_CODE (XEXP (x
, 0)) == POST_INC
))
3247 return gen_rtx_MEM (outer
, XEXP (x
, 0));
3248 if (GET_CODE (x
) == SUBREG
3249 && GET_CODE (XEXP (x
, 0)) == MEM
3250 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == PRE_DEC
3251 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == POST_INC
))
3252 return gen_rtx_MEM (outer
, XEXP (XEXP (x
, 0), 0));
3254 if (GET_CODE (x
) != REG
)
3256 rtx r
= simplify_gen_subreg (outer
, x
, inner
, byte
);
3257 if (GET_CODE (r
) == SUBREG
3258 && GET_CODE (x
) == MEM
3259 && MEM_VOLATILE_P (x
))
3261 /* Volatile MEMs don't get simplified, but we need them to
3262 be. We are little endian, so the subreg byte is the
3264 r
= adjust_address_nv (x
, outer
, byte
);
3270 if (r
>= FIRST_PSEUDO_REGISTER
|| r
== AP_REGNO
)
3271 return simplify_gen_subreg (outer
, x
, inner
, byte
);
3273 if (IS_MEM_REGNO (r
))
3274 return simplify_gen_subreg (outer
, x
, inner
, byte
);
3276 /* This is where the complexities of our register layout are
3280 else if (outer
== HImode
)
3282 if (r
== R0_REGNO
&& byte
== 2)
3284 else if (r
== R0_REGNO
&& byte
== 4)
3286 else if (r
== R0_REGNO
&& byte
== 6)
3288 else if (r
== R1_REGNO
&& byte
== 2)
3290 else if (r
== A0_REGNO
&& byte
== 2)
3293 else if (outer
== SImode
)
3295 if (r
== R0_REGNO
&& byte
== 0)
3297 else if (r
== R0_REGNO
&& byte
== 4)
3302 fprintf (stderr
, "m32c_subreg %s %s %d\n",
3303 mode_name
[outer
], mode_name
[inner
], byte
);
3307 return gen_rtx_REG (outer
, nr
);
3310 /* Used to emit move instructions. We split some moves,
3311 and avoid mem-mem moves. */
3313 m32c_prepare_move (rtx
* operands
, machine_mode mode
)
3315 if (far_addr_space_p (operands
[0])
3316 && CONSTANT_P (operands
[1]))
3318 operands
[1] = force_reg (GET_MODE (operands
[0]), operands
[1]);
3320 if (TARGET_A16
&& mode
== PSImode
)
3321 return m32c_split_move (operands
, mode
, 1);
3322 if ((GET_CODE (operands
[0]) == MEM
)
3323 && (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
))
3325 rtx pmv
= XEXP (operands
[0], 0);
3326 rtx dest_reg
= XEXP (pmv
, 0);
3327 rtx dest_mod
= XEXP (pmv
, 1);
3329 emit_insn (gen_rtx_SET (dest_reg
, dest_mod
));
3330 operands
[0] = gen_rtx_MEM (mode
, dest_reg
);
3332 if (can_create_pseudo_p () && MEM_P (operands
[0]) && MEM_P (operands
[1]))
3333 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
3337 #define DEBUG_SPLIT 0
3339 /* Returns TRUE if the given PSImode move should be split. We split
3340 for all r8c/m16c moves, since it doesn't support them, and for
3341 POP.L as we can only *push* SImode. */
3343 m32c_split_psi_p (rtx
* operands
)
3346 fprintf (stderr
, "\nm32c_split_psi_p\n");
3347 debug_rtx (operands
[0]);
3348 debug_rtx (operands
[1]);
3353 fprintf (stderr
, "yes, A16\n");
3357 if (GET_CODE (operands
[1]) == MEM
3358 && GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3361 fprintf (stderr
, "yes, pop.l\n");
3366 fprintf (stderr
, "no, default\n");
3371 /* Split the given move. SPLIT_ALL is 0 if splitting is optional
3372 (define_expand), 1 if it is not optional (define_insn_and_split),
3373 and 3 for define_split (alternate api). */
3375 m32c_split_move (rtx
* operands
, machine_mode mode
, int split_all
)
3378 int parts
, si
, di
, rev
= 0;
3379 int rv
= 0, opi
= 2;
3380 machine_mode submode
= HImode
;
3381 rtx
*ops
, local_ops
[10];
3383 /* define_split modifies the existing operands, but the other two
3384 emit new insns. OPS is where we store the operand pairs, which
3395 /* Before splitting mem-mem moves, force one operand into a
3397 if (can_create_pseudo_p () && MEM_P (operands
[0]) && MEM_P (operands
[1]))
3400 fprintf (stderr
, "force_reg...\n");
3401 debug_rtx (operands
[1]);
3403 operands
[1] = force_reg (mode
, operands
[1]);
3405 debug_rtx (operands
[1]);
3412 fprintf (stderr
, "\nsplit_move %d all=%d\n", !can_create_pseudo_p (),
3414 debug_rtx (operands
[0]);
3415 debug_rtx (operands
[1]);
3418 /* Note that split_all is not used to select the api after this
3419 point, so it's safe to set it to 3 even with define_insn. */
3420 /* None of the chips can move SI operands to sp-relative addresses,
3421 so we always split those. */
3422 if (satisfies_constraint_Ss (operands
[0]))
3426 && (far_addr_space_p (operands
[0])
3427 || far_addr_space_p (operands
[1])))
3430 /* We don't need to split these. */
3433 && (mode
== SImode
|| mode
== PSImode
)
3434 && !(GET_CODE (operands
[1]) == MEM
3435 && GET_CODE (XEXP (operands
[1], 0)) == POST_INC
))
3438 /* First, enumerate the subregs we'll be dealing with. */
3439 for (si
= 0; si
< parts
; si
++)
3442 m32c_subreg (submode
, operands
[0], mode
,
3443 si
* GET_MODE_SIZE (submode
));
3445 m32c_subreg (submode
, operands
[1], mode
,
3446 si
* GET_MODE_SIZE (submode
));
3449 /* Split pushes by emitting a sequence of smaller pushes. */
3450 if (GET_CODE (d
[0]) == MEM
&& GET_CODE (XEXP (d
[0], 0)) == PRE_DEC
)
3452 for (si
= parts
- 1; si
>= 0; si
--)
3454 ops
[opi
++] = gen_rtx_MEM (submode
,
3455 gen_rtx_PRE_DEC (Pmode
,
3463 /* Likewise for pops. */
3464 else if (GET_CODE (s
[0]) == MEM
&& GET_CODE (XEXP (s
[0], 0)) == POST_INC
)
3466 for (di
= 0; di
< parts
; di
++)
3469 ops
[opi
++] = gen_rtx_MEM (submode
,
3470 gen_rtx_POST_INC (Pmode
,
3478 /* if d[di] == s[si] for any di < si, we'll early clobber. */
3479 for (di
= 0; di
< parts
- 1; di
++)
3480 for (si
= di
+ 1; si
< parts
; si
++)
3481 if (reg_mentioned_p (d
[di
], s
[si
]))
3485 for (si
= 0; si
< parts
; si
++)
3491 for (si
= parts
- 1; si
>= 0; si
--)
3498 /* Now emit any moves we may have accumulated. */
3499 if (rv
&& split_all
!= 3)
3502 for (i
= 2; i
< opi
; i
+= 2)
3503 emit_move_insn (ops
[i
], ops
[i
+ 1]);
3508 /* The m32c has a number of opcodes that act like memcpy, strcmp, and
3509 the like. For the R8C they expect one of the addresses to be in
3510 R1L:An so we need to arrange for that. Otherwise, it's just a
3511 matter of picking out the operands we want and emitting the right
3512 pattern for them. All these expanders, which correspond to
3513 patterns in blkmov.md, must return nonzero if they expand the insn,
3514 or zero if they should FAIL. */
3516 /* This is a memset() opcode. All operands are implied, so we need to
3517 arrange for them to be in the right registers. The opcode wants
3518 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3519 the count (HI), and $2 the value (QI). */
3521 m32c_expand_setmemhi(rtx
*operands
)
3523 rtx desta
, count
, val
;
3526 desta
= XEXP (operands
[0], 0);
3527 count
= operands
[1];
3530 desto
= gen_reg_rtx (Pmode
);
3531 counto
= gen_reg_rtx (HImode
);
3533 if (GET_CODE (desta
) != REG
3534 || REGNO (desta
) < FIRST_PSEUDO_REGISTER
)
3535 desta
= copy_to_mode_reg (Pmode
, desta
);
3537 /* This looks like an arbitrary restriction, but this is by far the
3538 most common case. For counts 8..14 this actually results in
3539 smaller code with no speed penalty because the half-sized
3540 constant can be loaded with a shorter opcode. */
3541 if (GET_CODE (count
) == CONST_INT
3542 && GET_CODE (val
) == CONST_INT
3543 && ! (INTVAL (count
) & 1)
3544 && (INTVAL (count
) > 1)
3545 && (INTVAL (val
) <= 7 && INTVAL (val
) >= -8))
3547 unsigned v
= INTVAL (val
) & 0xff;
3549 count
= copy_to_mode_reg (HImode
, GEN_INT (INTVAL (count
) / 2));
3550 val
= copy_to_mode_reg (HImode
, GEN_INT (v
));
3552 emit_insn (gen_setmemhi_whi_op (desto
, counto
, val
, desta
, count
));
3554 emit_insn (gen_setmemhi_wpsi_op (desto
, counto
, val
, desta
, count
));
3558 /* This is the generalized memset() case. */
3559 if (GET_CODE (val
) != REG
3560 || REGNO (val
) < FIRST_PSEUDO_REGISTER
)
3561 val
= copy_to_mode_reg (QImode
, val
);
3563 if (GET_CODE (count
) != REG
3564 || REGNO (count
) < FIRST_PSEUDO_REGISTER
)
3565 count
= copy_to_mode_reg (HImode
, count
);
3568 emit_insn (gen_setmemhi_bhi_op (desto
, counto
, val
, desta
, count
));
3570 emit_insn (gen_setmemhi_bpsi_op (desto
, counto
, val
, desta
, count
));
3575 /* This is a memcpy() opcode. All operands are implied, so we need to
3576 arrange for them to be in the right registers. The opcode wants
3577 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3578 is the source (MEM:BLK), and $2 the count (HI). */
3580 m32c_expand_movmemhi(rtx
*operands
)
3582 rtx desta
, srca
, count
;
3583 rtx desto
, srco
, counto
;
3585 desta
= XEXP (operands
[0], 0);
3586 srca
= XEXP (operands
[1], 0);
3587 count
= operands
[2];
3589 desto
= gen_reg_rtx (Pmode
);
3590 srco
= gen_reg_rtx (Pmode
);
3591 counto
= gen_reg_rtx (HImode
);
3593 if (GET_CODE (desta
) != REG
3594 || REGNO (desta
) < FIRST_PSEUDO_REGISTER
)
3595 desta
= copy_to_mode_reg (Pmode
, desta
);
3597 if (GET_CODE (srca
) != REG
3598 || REGNO (srca
) < FIRST_PSEUDO_REGISTER
)
3599 srca
= copy_to_mode_reg (Pmode
, srca
);
3601 /* Similar to setmem, but we don't need to check the value. */
3602 if (GET_CODE (count
) == CONST_INT
3603 && ! (INTVAL (count
) & 1)
3604 && (INTVAL (count
) > 1))
3606 count
= copy_to_mode_reg (HImode
, GEN_INT (INTVAL (count
) / 2));
3608 emit_insn (gen_movmemhi_whi_op (desto
, srco
, counto
, desta
, srca
, count
));
3610 emit_insn (gen_movmemhi_wpsi_op (desto
, srco
, counto
, desta
, srca
, count
));
3614 /* This is the generalized memset() case. */
3615 if (GET_CODE (count
) != REG
3616 || REGNO (count
) < FIRST_PSEUDO_REGISTER
)
3617 count
= copy_to_mode_reg (HImode
, count
);
3620 emit_insn (gen_movmemhi_bhi_op (desto
, srco
, counto
, desta
, srca
, count
));
3622 emit_insn (gen_movmemhi_bpsi_op (desto
, srco
, counto
, desta
, srca
, count
));
3627 /* This is a stpcpy() opcode. $0 is the destination (MEM:BLK) after
3628 the copy, which should point to the NUL at the end of the string,
3629 $1 is the destination (MEM:BLK), and $2 is the source (MEM:BLK).
3630 Since our opcode leaves the destination pointing *after* the NUL,
3631 we must emit an adjustment. */
3633 m32c_expand_movstr(rtx
*operands
)
3638 desta
= XEXP (operands
[1], 0);
3639 srca
= XEXP (operands
[2], 0);
3641 desto
= gen_reg_rtx (Pmode
);
3642 srco
= gen_reg_rtx (Pmode
);
3644 if (GET_CODE (desta
) != REG
3645 || REGNO (desta
) < FIRST_PSEUDO_REGISTER
)
3646 desta
= copy_to_mode_reg (Pmode
, desta
);
3648 if (GET_CODE (srca
) != REG
3649 || REGNO (srca
) < FIRST_PSEUDO_REGISTER
)
3650 srca
= copy_to_mode_reg (Pmode
, srca
);
3652 emit_insn (gen_movstr_op (desto
, srco
, desta
, srca
));
3653 /* desto ends up being a1, which allows this type of add through MOVA. */
3654 emit_insn (gen_addpsi3 (operands
[0], desto
, GEN_INT (-1)));
3659 /* This is a strcmp() opcode. $0 is the destination (HI) which holds
3660 <=>0 depending on the comparison, $1 is one string (MEM:BLK), and
3661 $2 is the other (MEM:BLK). We must do the comparison, and then
3662 convert the flags to a signed integer result. */
3664 m32c_expand_cmpstr(rtx
*operands
)
3668 src1a
= XEXP (operands
[1], 0);
3669 src2a
= XEXP (operands
[2], 0);
3671 if (GET_CODE (src1a
) != REG
3672 || REGNO (src1a
) < FIRST_PSEUDO_REGISTER
)
3673 src1a
= copy_to_mode_reg (Pmode
, src1a
);
3675 if (GET_CODE (src2a
) != REG
3676 || REGNO (src2a
) < FIRST_PSEUDO_REGISTER
)
3677 src2a
= copy_to_mode_reg (Pmode
, src2a
);
3679 emit_insn (gen_cmpstrhi_op (src1a
, src2a
, src1a
, src2a
));
3680 emit_insn (gen_cond_to_int (operands
[0]));
3686 typedef rtx (*shift_gen_func
)(rtx
, rtx
, rtx
);
3688 static shift_gen_func
3689 shift_gen_func_for (int mode
, int code
)
3691 #define GFF(m,c,f) if (mode == m && code == c) return f
3692 GFF(QImode
, ASHIFT
, gen_ashlqi3_i
);
3693 GFF(QImode
, ASHIFTRT
, gen_ashrqi3_i
);
3694 GFF(QImode
, LSHIFTRT
, gen_lshrqi3_i
);
3695 GFF(HImode
, ASHIFT
, gen_ashlhi3_i
);
3696 GFF(HImode
, ASHIFTRT
, gen_ashrhi3_i
);
3697 GFF(HImode
, LSHIFTRT
, gen_lshrhi3_i
);
3698 GFF(PSImode
, ASHIFT
, gen_ashlpsi3_i
);
3699 GFF(PSImode
, ASHIFTRT
, gen_ashrpsi3_i
);
3700 GFF(PSImode
, LSHIFTRT
, gen_lshrpsi3_i
);
3701 GFF(SImode
, ASHIFT
, TARGET_A16
? gen_ashlsi3_16
: gen_ashlsi3_24
);
3702 GFF(SImode
, ASHIFTRT
, TARGET_A16
? gen_ashrsi3_16
: gen_ashrsi3_24
);
3703 GFF(SImode
, LSHIFTRT
, TARGET_A16
? gen_lshrsi3_16
: gen_lshrsi3_24
);
3708 /* The m32c only has one shift, but it takes a signed count. GCC
3709 doesn't want this, so we fake it by negating any shift count when
3710 we're pretending to shift the other way. Also, the shift count is
3711 limited to -8..8. It's slightly better to use two shifts for 9..15
3712 than to load the count into r1h, so we do that too. */
3714 m32c_prepare_shift (rtx
* operands
, int scale
, int shift_code
)
3716 machine_mode mode
= GET_MODE (operands
[0]);
3717 shift_gen_func func
= shift_gen_func_for (mode
, shift_code
);
3720 if (GET_CODE (operands
[2]) == CONST_INT
)
3722 int maxc
= TARGET_A24
&& (mode
== PSImode
|| mode
== SImode
) ? 32 : 8;
3723 int count
= INTVAL (operands
[2]) * scale
;
3725 while (count
> maxc
)
3727 temp
= gen_reg_rtx (mode
);
3728 emit_insn (func (temp
, operands
[1], GEN_INT (maxc
)));
3732 while (count
< -maxc
)
3734 temp
= gen_reg_rtx (mode
);
3735 emit_insn (func (temp
, operands
[1], GEN_INT (-maxc
)));
3739 emit_insn (func (operands
[0], operands
[1], GEN_INT (count
)));
3743 temp
= gen_reg_rtx (QImode
);
3745 /* The pattern has a NEG that corresponds to this. */
3746 emit_move_insn (temp
, gen_rtx_NEG (QImode
, operands
[2]));
3747 else if (TARGET_A16
&& mode
== SImode
)
3748 /* We do this because the code below may modify this, we don't
3749 want to modify the origin of this value. */
3750 emit_move_insn (temp
, operands
[2]);
3752 /* We'll only use it for the shift, no point emitting a move. */
3755 if (TARGET_A16
&& GET_MODE_SIZE (mode
) == 4)
3757 /* The m16c has a limit of -16..16 for SI shifts, even when the
3758 shift count is in a register. Since there are so many targets
3759 of these shifts, it's better to expand the RTL here than to
3760 call a helper function.
3762 The resulting code looks something like this:
3774 We take advantage of the fact that "negative" shifts are
3775 undefined to skip one of the comparisons. */
3781 emit_move_insn (operands
[0], operands
[1]);
3784 label
= gen_label_rtx ();
3785 LABEL_NUSES (label
) ++;
3787 tempvar
= gen_reg_rtx (mode
);
3789 if (shift_code
== ASHIFT
)
3791 /* This is a left shift. We only need check positive counts. */
3792 emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode
, 0, 0),
3793 count
, GEN_INT (16), label
));
3794 emit_insn (func (tempvar
, operands
[0], GEN_INT (8)));
3795 emit_insn (func (operands
[0], tempvar
, GEN_INT (8)));
3796 insn
= emit_insn (gen_addqi3 (count
, count
, GEN_INT (-16)));
3797 emit_label_after (label
, insn
);
3801 /* This is a right shift. We only need check negative counts. */
3802 emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode
, 0, 0),
3803 count
, GEN_INT (-16), label
));
3804 emit_insn (func (tempvar
, operands
[0], GEN_INT (-8)));
3805 emit_insn (func (operands
[0], tempvar
, GEN_INT (-8)));
3806 insn
= emit_insn (gen_addqi3 (count
, count
, GEN_INT (16)));
3807 emit_label_after (label
, insn
);
3809 operands
[1] = operands
[0];
3810 emit_insn (func (operands
[0], operands
[0], count
));
3818 /* The m32c has a limited range of operations that work on PSImode
3819 values; we have to expand to SI, do the math, and truncate back to
3820 PSI. Yes, this is expensive, but hopefully gcc will learn to avoid
3823 m32c_expand_neg_mulpsi3 (rtx
* operands
)
3825 /* operands: a = b * i */
3826 rtx temp1
; /* b as SI */
3827 rtx scale
/* i as SI */;
3828 rtx temp2
; /* a*b as SI */
3830 temp1
= gen_reg_rtx (SImode
);
3831 temp2
= gen_reg_rtx (SImode
);
3832 if (GET_CODE (operands
[2]) != CONST_INT
)
3834 scale
= gen_reg_rtx (SImode
);
3835 emit_insn (gen_zero_extendpsisi2 (scale
, operands
[2]));
3838 scale
= copy_to_mode_reg (SImode
, operands
[2]);
3840 emit_insn (gen_zero_extendpsisi2 (temp1
, operands
[1]));
3841 temp2
= expand_simple_binop (SImode
, MULT
, temp1
, scale
, temp2
, 1, OPTAB_LIB
);
3842 emit_insn (gen_truncsipsi2 (operands
[0], temp2
));
3845 /* Pattern Output Functions */
3848 m32c_expand_movcc (rtx
*operands
)
3850 rtx rel
= operands
[1];
3852 if (GET_CODE (rel
) != EQ
&& GET_CODE (rel
) != NE
)
3854 if (GET_CODE (operands
[2]) != CONST_INT
3855 || GET_CODE (operands
[3]) != CONST_INT
)
3857 if (GET_CODE (rel
) == NE
)
3859 rtx tmp
= operands
[2];
3860 operands
[2] = operands
[3];
3862 rel
= gen_rtx_EQ (GET_MODE (rel
), XEXP (rel
, 0), XEXP (rel
, 1));
3865 emit_move_insn (operands
[0],
3866 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
3873 /* Used for the "insv" pattern. Return nonzero to fail, else done. */
3875 m32c_expand_insv (rtx
*operands
)
3880 if (INTVAL (operands
[1]) != 1)
3883 /* Our insv opcode (bset, bclr) can only insert a one-bit constant. */
3884 if (GET_CODE (operands
[3]) != CONST_INT
)
3886 if (INTVAL (operands
[3]) != 0
3887 && INTVAL (operands
[3]) != 1
3888 && INTVAL (operands
[3]) != -1)
3891 mask
= 1 << INTVAL (operands
[2]);
3894 if (GET_CODE (op0
) == SUBREG
3895 && SUBREG_BYTE (op0
) == 0)
3897 rtx sub
= SUBREG_REG (op0
);
3898 if (GET_MODE (sub
) == HImode
|| GET_MODE (sub
) == QImode
)
3902 if (!can_create_pseudo_p ()
3903 || (GET_CODE (op0
) == MEM
&& MEM_VOLATILE_P (op0
)))
3907 src0
= gen_reg_rtx (GET_MODE (op0
));
3908 emit_move_insn (src0
, op0
);
3911 if (GET_MODE (op0
) == HImode
3912 && INTVAL (operands
[2]) >= 8
3913 && GET_CODE (op0
) == MEM
)
3915 /* We are little endian. */
3916 rtx new_mem
= gen_rtx_MEM (QImode
, plus_constant (Pmode
,
3918 MEM_COPY_ATTRIBUTES (new_mem
, op0
);
3922 /* First, we generate a mask with the correct polarity. If we are
3923 storing a zero, we want an AND mask, so invert it. */
3924 if (INTVAL (operands
[3]) == 0)
3926 /* Storing a zero, use an AND mask */
3927 if (GET_MODE (op0
) == HImode
)
3932 /* Now we need to properly sign-extend the mask in case we need to
3933 fall back to an AND or OR opcode. */
3934 if (GET_MODE (op0
) == HImode
)
3945 switch ( (INTVAL (operands
[3]) ? 4 : 0)
3946 + ((GET_MODE (op0
) == HImode
) ? 2 : 0)
3947 + (TARGET_A24
? 1 : 0))
3949 case 0: p
= gen_andqi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3950 case 1: p
= gen_andqi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3951 case 2: p
= gen_andhi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3952 case 3: p
= gen_andhi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3953 case 4: p
= gen_iorqi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3954 case 5: p
= gen_iorqi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3955 case 6: p
= gen_iorhi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3956 case 7: p
= gen_iorhi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3957 default: p
= NULL_RTX
; break; /* Not reached, but silences a warning. */
3965 m32c_scc_pattern(rtx
*operands
, RTX_CODE code
)
3967 static char buf
[30];
3968 if (GET_CODE (operands
[0]) == REG
3969 && REGNO (operands
[0]) == R0_REGNO
)
3972 return "stzx\t#1,#0,r0l";
3974 return "stzx\t#0,#1,r0l";
3976 sprintf(buf
, "bm%s\t0,%%h0\n\tand.b\t#1,%%0", GET_RTX_NAME (code
));
3980 /* Encode symbol attributes of a SYMBOL_REF into its
3981 SYMBOL_REF_FLAGS. */
3983 m32c_encode_section_info (tree decl
, rtx rtl
, int first
)
3985 int extra_flags
= 0;
3987 default_encode_section_info (decl
, rtl
, first
);
3988 if (TREE_CODE (decl
) == FUNCTION_DECL
3989 && m32c_special_page_vector_p (decl
))
3991 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
3994 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
3997 /* Returns TRUE if the current function is a leaf, and thus we can
3998 determine which registers an interrupt function really needs to
3999 save. The logic below is mostly about finding the insn sequence
4000 that's the function, versus any sequence that might be open for the
4003 m32c_leaf_function_p (void)
4007 push_topmost_sequence ();
4008 rv
= leaf_function_p ();
4009 pop_topmost_sequence ();
4013 /* Returns TRUE if the current function needs to use the ENTER/EXIT
4014 opcodes. If the function doesn't need the frame base or stack
4015 pointer, it can use the simpler RTS opcode. */
4017 m32c_function_needs_enter (void)
4020 rtx sp
= gen_rtx_REG (Pmode
, SP_REGNO
);
4021 rtx fb
= gen_rtx_REG (Pmode
, FB_REGNO
);
4023 for (insn
= get_topmost_sequence ()->first
; insn
; insn
= NEXT_INSN (insn
))
4024 if (NONDEBUG_INSN_P (insn
))
4026 if (reg_mentioned_p (sp
, insn
))
4028 if (reg_mentioned_p (fb
, insn
))
4034 /* Mark all the subexpressions of the PARALLEL rtx PAR as
4035 frame-related. Return PAR.
4037 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
4038 PARALLEL rtx other than the first if they do not have the
4039 FRAME_RELATED flag set on them. So this function is handy for
4040 marking up 'enter' instructions. */
4042 m32c_all_frame_related (rtx par
)
4044 int len
= XVECLEN (par
, 0);
4047 for (i
= 0; i
< len
; i
++)
4048 F (XVECEXP (par
, 0, i
));
4053 /* Emits the prologue. See the frame layout comment earlier in this
4054 file. We can reserve up to 256 bytes with the ENTER opcode, beyond
4055 that we manually update sp. */
4057 m32c_emit_prologue (void)
4059 int frame_size
, extra_frame_size
= 0, reg_save_size
;
4060 int complex_prologue
= 0;
4062 cfun
->machine
->is_leaf
= m32c_leaf_function_p ();
4063 if (interrupt_p (cfun
->decl
))
4065 cfun
->machine
->is_interrupt
= 1;
4066 complex_prologue
= 1;
4068 else if (bank_switch_p (cfun
->decl
))
4069 warning (OPT_Wattributes
,
4070 "%<bank_switch%> has no effect on non-interrupt functions");
4072 reg_save_size
= m32c_pushm_popm (PP_justcount
);
4074 if (interrupt_p (cfun
->decl
))
4076 if (bank_switch_p (cfun
->decl
))
4077 emit_insn (gen_fset_b ());
4078 else if (cfun
->machine
->intr_pushm
)
4079 emit_insn (gen_pushm (GEN_INT (cfun
->machine
->intr_pushm
)));
4083 m32c_initial_elimination_offset (FB_REGNO
, SP_REGNO
) - reg_save_size
;
4085 && !m32c_function_needs_enter ())
4086 cfun
->machine
->use_rts
= 1;
4088 if (flag_stack_usage_info
)
4089 current_function_static_stack_size
= frame_size
;
4091 if (frame_size
> 254)
4093 extra_frame_size
= frame_size
- 254;
4096 if (cfun
->machine
->use_rts
== 0)
4097 F (emit_insn (m32c_all_frame_related
4099 ? gen_prologue_enter_16 (GEN_INT (frame_size
+ 2))
4100 : gen_prologue_enter_24 (GEN_INT (frame_size
+ 4)))));
4102 if (extra_frame_size
)
4104 complex_prologue
= 1;
4106 F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode
, SP_REGNO
),
4107 gen_rtx_REG (HImode
, SP_REGNO
),
4108 GEN_INT (-extra_frame_size
))));
4110 F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode
, SP_REGNO
),
4111 gen_rtx_REG (PSImode
, SP_REGNO
),
4112 GEN_INT (-extra_frame_size
))));
4115 complex_prologue
+= m32c_pushm_popm (PP_pushm
);
4117 /* This just emits a comment into the .s file for debugging. */
4118 if (complex_prologue
)
4119 emit_insn (gen_prologue_end ());
4122 /* Likewise, for the epilogue. The only exception is that, for
4123 interrupts, we must manually unwind the frame as the REIT opcode
4126 m32c_emit_epilogue (void)
4128 int popm_count
= m32c_pushm_popm (PP_justcount
);
4130 /* This just emits a comment into the .s file for debugging. */
4131 if (popm_count
> 0 || cfun
->machine
->is_interrupt
)
4132 emit_insn (gen_epilogue_start ());
4135 m32c_pushm_popm (PP_popm
);
4137 if (cfun
->machine
->is_interrupt
)
4139 machine_mode spmode
= TARGET_A16
? HImode
: PSImode
;
4141 /* REIT clears B flag and restores $fp for us, but we still
4142 have to fix up the stack. USE_RTS just means we didn't
4144 if (!cfun
->machine
->use_rts
)
4146 emit_move_insn (gen_rtx_REG (spmode
, A0_REGNO
),
4147 gen_rtx_REG (spmode
, FP_REGNO
));
4148 emit_move_insn (gen_rtx_REG (spmode
, SP_REGNO
),
4149 gen_rtx_REG (spmode
, A0_REGNO
));
4150 /* We can't just add this to the POPM because it would be in
4151 the wrong order, and wouldn't fix the stack if we're bank
4154 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode
, FP_REGNO
)));
4156 emit_insn (gen_poppsi (gen_rtx_REG (PSImode
, FP_REGNO
)));
4158 if (!bank_switch_p (cfun
->decl
) && cfun
->machine
->intr_pushm
)
4159 emit_insn (gen_popm (GEN_INT (cfun
->machine
->intr_pushm
)));
4161 /* The FREIT (Fast REturn from InTerrupt) instruction should be
4162 generated only for M32C/M32CM targets (generate the REIT
4163 instruction otherwise). */
4164 if (fast_interrupt_p (cfun
->decl
))
4166 /* Check if fast_attribute is set for M32C or M32CM. */
4169 emit_jump_insn (gen_epilogue_freit ());
4171 /* If fast_interrupt attribute is set for an R8C or M16C
4172 target ignore this attribute and generated REIT
4176 warning (OPT_Wattributes
,
4177 "%<fast_interrupt%> attribute directive ignored");
4178 emit_jump_insn (gen_epilogue_reit_16 ());
4181 else if (TARGET_A16
)
4182 emit_jump_insn (gen_epilogue_reit_16 ());
4184 emit_jump_insn (gen_epilogue_reit_24 ());
4186 else if (cfun
->machine
->use_rts
)
4187 emit_jump_insn (gen_epilogue_rts ());
4188 else if (TARGET_A16
)
4189 emit_jump_insn (gen_epilogue_exitd_16 ());
4191 emit_jump_insn (gen_epilogue_exitd_24 ());
4195 m32c_emit_eh_epilogue (rtx ret_addr
)
4197 /* R0[R2] has the stack adjustment. R1[R3] has the address to
4198 return to. We have to fudge the stack, pop everything, pop SP
4199 (fudged), and return (fudged). This is actually easier to do in
4200 assembler, so punt to libgcc. */
4201 emit_jump_insn (gen_eh_epilogue (ret_addr
, cfun
->machine
->eh_stack_adjust
));
4202 /* emit_clobber (gen_rtx_REG (HImode, R0L_REGNO)); */
4205 /* Indicate which flags must be properly set for a given conditional. */
4207 flags_needed_for_conditional (rtx cond
)
4209 switch (GET_CODE (cond
))
4233 /* Returns true if a compare insn is redundant because it would only
4234 set flags that are already set correctly. */
4236 m32c_compare_redundant (rtx_insn
*cmp
, rtx
*operands
)
4251 fprintf(stderr
, "\n\033[32mm32c_compare_redundant\033[0m\n");
4255 fprintf(stderr
, "operands[%d] = ", i
);
4256 debug_rtx(operands
[i
]);
4260 next
= next_nonnote_insn (cmp
);
4261 if (!next
|| !INSN_P (next
))
4264 fprintf(stderr
, "compare not followed by insn\n");
4269 if (GET_CODE (PATTERN (next
)) == SET
4270 && GET_CODE (XEXP ( PATTERN (next
), 1)) == IF_THEN_ELSE
)
4272 next
= XEXP (XEXP (PATTERN (next
), 1), 0);
4274 else if (GET_CODE (PATTERN (next
)) == SET
)
4276 /* If this is a conditional, flags_needed will be something
4277 other than FLAGS_N, which we test below. */
4278 next
= XEXP (PATTERN (next
), 1);
4283 fprintf(stderr
, "compare not followed by conditional\n");
4289 fprintf(stderr
, "conditional is: ");
4293 flags_needed
= flags_needed_for_conditional (next
);
4294 if (flags_needed
== FLAGS_N
)
4297 fprintf(stderr
, "compare not followed by conditional\n");
4303 /* Compare doesn't set overflow and carry the same way that
4304 arithmetic instructions do, so we can't replace those. */
4305 if (flags_needed
& FLAGS_OC
)
4310 prev
= prev_nonnote_insn (prev
);
4314 fprintf(stderr
, "No previous insn.\n");
4321 fprintf(stderr
, "Previous insn is a non-insn.\n");
4325 pp
= PATTERN (prev
);
4326 if (GET_CODE (pp
) != SET
)
4329 fprintf(stderr
, "Previous insn is not a SET.\n");
4333 pflags
= get_attr_flags (prev
);
4335 /* Looking up attributes of previous insns corrupted the recog
4337 INSN_UID (cmp
) = -1;
4338 recog (PATTERN (cmp
), cmp
, 0);
4340 if (pflags
== FLAGS_N
4341 && reg_mentioned_p (op0
, pp
))
4344 fprintf(stderr
, "intermediate non-flags insn uses op:\n");
4350 /* Check for comparisons against memory - between volatiles and
4351 aliases, we just can't risk this one. */
4352 if (GET_CODE (operands
[0]) == MEM
4353 || GET_CODE (operands
[0]) == MEM
)
4356 fprintf(stderr
, "comparisons with memory:\n");
4362 /* Check for PREV changing a register that's used to compute a
4363 value in CMP, even if it doesn't otherwise change flags. */
4364 if (GET_CODE (operands
[0]) == REG
4365 && rtx_referenced_p (SET_DEST (PATTERN (prev
)), operands
[0]))
4368 fprintf(stderr
, "sub-value affected, op0:\n");
4373 if (GET_CODE (operands
[1]) == REG
4374 && rtx_referenced_p (SET_DEST (PATTERN (prev
)), operands
[1]))
4377 fprintf(stderr
, "sub-value affected, op1:\n");
4383 } while (pflags
== FLAGS_N
);
4385 fprintf(stderr
, "previous flag-setting insn:\n");
4390 if (GET_CODE (pp
) == SET
4391 && GET_CODE (XEXP (pp
, 0)) == REG
4392 && REGNO (XEXP (pp
, 0)) == FLG_REGNO
4393 && GET_CODE (XEXP (pp
, 1)) == COMPARE
)
4395 /* Adjacent cbranches must have the same operands to be
4397 rtx pop0
= XEXP (XEXP (pp
, 1), 0);
4398 rtx pop1
= XEXP (XEXP (pp
, 1), 1);
4400 fprintf(stderr
, "adjacent cbranches\n");
4404 if (rtx_equal_p (op0
, pop0
)
4405 && rtx_equal_p (op1
, pop1
))
4408 fprintf(stderr
, "prev cmp not same\n");
4413 /* Else the previous insn must be a SET, with either the source or
4414 dest equal to operands[0], and operands[1] must be zero. */
4416 if (!rtx_equal_p (op1
, const0_rtx
))
4419 fprintf(stderr
, "operands[1] not const0_rtx\n");
4423 if (GET_CODE (pp
) != SET
)
4426 fprintf (stderr
, "pp not set\n");
4430 if (!rtx_equal_p (op0
, SET_SRC (pp
))
4431 && !rtx_equal_p (op0
, SET_DEST (pp
)))
4434 fprintf(stderr
, "operands[0] not found in set\n");
4440 fprintf(stderr
, "cmp flags %x prev flags %x\n", flags_needed
, pflags
);
4442 if ((pflags
& flags_needed
) == flags_needed
)
4448 /* Return the pattern for a compare. This will be commented out if
4449 the compare is redundant, else a normal pattern is returned. Thus,
4450 the assembler output says where the compare would have been. */
4452 m32c_output_compare (rtx_insn
*insn
, rtx
*operands
)
4454 static char templ
[] = ";cmp.b\t%1,%0";
4457 templ
[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands
[0]))];
4458 if (m32c_compare_redundant (insn
, operands
))
4461 fprintf(stderr
, "cbranch: cmp not needed\n");
4467 fprintf(stderr
, "cbranch: cmp needed: `%s'\n", templ
+ 1);
4472 #undef TARGET_ENCODE_SECTION_INFO
4473 #define TARGET_ENCODE_SECTION_INFO m32c_encode_section_info
4475 /* If the frame pointer isn't used, we detect it manually. But the
4476 stack pointer doesn't have as flexible addressing as the frame
4477 pointer, so we always assume we have it. */
4479 #undef TARGET_FRAME_POINTER_REQUIRED
4480 #define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true
4482 /* The Global `targetm' Variable. */
4484 struct gcc_target targetm
= TARGET_INITIALIZER
;
4486 #include "gt-m32c.h"