2 /* { dg-options "--param allow-store-data-races=0" } */
3 /* { dg-final { simulate-thread } } */
5 /* Test that setting <var.a> does not touch either <var.b> or <var.c>.
6 In the C++ memory model, non contiguous bitfields ("a" and "c"
7 here) should be considered as distinct memory locations, so we
8 can't use bit twiddling to set either one. */
11 #include "simulate-thread.h"
18 /* On x86-64, the volatile causes us to access <a> with a 32-bit
19 access, and thus trigger this test. */
20 volatile unsigned int a : 4;
26 __attribute__((noinline))
32 void simulate_thread_other_threads()
39 int simulate_thread_step_verify()
44 printf ("FAIL: Unexpected value: var.b is %d, should be %d\n",
50 printf ("FAIL: Unexpected value: var.c is %d, should be %d\n",
57 int simulate_thread_final_verify()
59 int ret = simulate_thread_step_verify();
62 printf ("FAIL: Unexpected value: var.a is %d, should be %d\n",
69 __attribute__((noinline))
70 void simulate_thread_main()
77 simulate_thread_main();
78 simulate_thread_done();