1 ;; Machine description of the Lattice Mico32 architecture for GNU C compiler.
2 ;; Contributed by Jon Beniston <jon@beniston.com>
4 ;; Copyright (C) 2009, 2010 Free Software Foundation, Inc.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; Include predicate and constraint definitions
23 (include "predicates.md")
24 (include "constraints.md")
29 [(RA_REGNUM 29) ; return address register.
33 ;; LM32 specific volatile operations
35 [(UNSPECV_BLOCKAGE 1)] ; prevent scheduling across pro/epilog boundaries
38 ;; LM32 specific operations
41 (UNSPEC_GOTOFF_HI16 3)
42 (UNSPEC_GOTOFF_LO16 4)]
45 ;; ---------------------------------
47 ;; ---------------------------------
50 "unknown,load,store,arith,compare,shift,multiply,divide,call,icall,ubranch,uibranch,cbranch"
51 (const_string "unknown"))
53 ;; ---------------------------------
54 ;; instruction lengths
55 ;; ---------------------------------
57 ; All instructions are 4 bytes
58 ; Except for branches that are out of range, and have to be implemented
60 (define_attr "length" ""
62 (eq_attr "type" "cbranch")
64 (lt (abs (minus (match_dup 2) (pc)))
74 ;; ---------------------------------
76 ;; ---------------------------------
78 (define_automaton "lm32")
80 (define_cpu_unit "x" "lm32")
81 (define_cpu_unit "m" "lm32")
82 (define_cpu_unit "w" "lm32")
84 (define_insn_reservation "singlecycle" 1
85 (eq_attr "type" "store,arith,call,icall,ubranch,uibranch,cbranch")
88 (define_insn_reservation "twocycle" 2
89 (eq_attr "type" "compare,shift,divide")
92 (define_insn_reservation "threecycle" 3
93 (eq_attr "type" "load,multiply")
96 ;; ---------------------------------
98 ;; ---------------------------------
100 (define_expand "movqi"
101 [(set (match_operand:QI 0 "general_operand" "")
102 (match_operand:QI 1 "general_operand" ""))]
106 if (can_create_pseudo_p ())
108 if (GET_CODE (operand0) == MEM)
110 /* Source operand for store must be in a register. */
111 operands[1] = force_reg (QImode, operands[1]);
116 (define_expand "movhi"
117 [(set (match_operand:HI 0 "general_operand" "")
118 (match_operand:HI 1 "general_operand" ""))]
122 if (can_create_pseudo_p ())
124 if (GET_CODE (operands[0]) == MEM)
126 /* Source operand for store must be in a register. */
127 operands[1] = force_reg (HImode, operands[1]);
132 (define_expand "movsi"
133 [(set (match_operand:SI 0 "general_operand" "")
134 (match_operand:SI 1 "general_operand" ""))]
138 if (can_create_pseudo_p ())
140 if (GET_CODE (operands[0]) == MEM
141 || (GET_CODE (operands[0]) == SUBREG
142 && GET_CODE (SUBREG_REG (operands[0])) == MEM))
144 /* Source operand for store must be in a register. */
145 operands[1] = force_reg (SImode, operands[1]);
149 if (flag_pic && symbolic_operand (operands[1], SImode))
151 if (GET_CODE (operands[1]) == LABEL_REF
152 || (GET_CODE (operands[1]) == SYMBOL_REF
153 && SYMBOL_REF_LOCAL_P (operands[1])
154 && !SYMBOL_REF_WEAK (operands[1])))
156 emit_insn (gen_movsi_gotoff_hi16 (operands[0], operands[1]));
157 emit_insn (gen_addsi3 (operands[0],
159 pic_offset_table_rtx));
160 emit_insn (gen_movsi_gotoff_lo16 (operands[0],
165 emit_insn (gen_movsi_got (operands[0], operands[1]));
166 crtl->uses_pic_offset_table = 1;
169 else if (flag_pic && GET_CODE (operands[1]) == CONST)
171 rtx op = XEXP (operands[1], 0);
172 if (GET_CODE (op) == PLUS)
174 rtx arg0 = XEXP (op, 0);
175 rtx arg1 = XEXP (op, 1);
176 if (GET_CODE (arg0) == LABEL_REF
177 || (GET_CODE (arg0) == SYMBOL_REF
178 && SYMBOL_REF_LOCAL_P (arg0)
179 && !SYMBOL_REF_WEAK (arg0)))
181 emit_insn (gen_movsi_gotoff_hi16 (operands[0], arg0));
182 emit_insn (gen_addsi3 (operands[0],
184 pic_offset_table_rtx));
185 emit_insn (gen_movsi_gotoff_lo16 (operands[0],
190 emit_insn (gen_movsi_got (operands[0], arg0));
191 emit_insn (gen_addsi3 (operands[0], operands[0], arg1));
192 crtl->uses_pic_offset_table = 1;
196 else if (!flag_pic && reloc_operand (operands[1], GET_MODE (operands[1])))
198 emit_insn (gen_rtx_SET (SImode, operands[0], gen_rtx_HIGH (SImode, operands[1])));
199 emit_insn (gen_rtx_SET (SImode, operands[0], gen_rtx_LO_SUM (SImode, operands[0], operands[1])));
202 else if (GET_CODE (operands[1]) == CONST_INT)
204 if (!(satisfies_constraint_K (operands[1])
205 || satisfies_constraint_L (operands[1])
206 || satisfies_constraint_U (operands[1])))
208 emit_insn (gen_movsi_insn (operands[0],
209 GEN_INT (INTVAL (operands[1]) & ~0xffff)));
210 emit_insn (gen_iorsi3 (operands[0],
212 GEN_INT (INTVAL (operands[1]) & 0xffff)));
218 (define_expand "movmemsi"
219 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
220 (match_operand:BLK 1 "general_operand" ""))
221 (use (match_operand:SI 2 "" ""))
222 (use (match_operand:SI 3 "const_int_operand" ""))])]
225 if (!lm32_expand_block_move (operands))
230 ;; ---------------------------------
232 ;; ---------------------------------
234 (define_insn "movsi_got"
235 [(set (match_operand:SI 0 "register_operand" "=r")
236 (unspec:SI [(match_operand 1 "" "")] UNSPEC_GOT))]
238 "lw %0, (gp+got(%1))"
239 [(set_attr "type" "load")]
242 (define_insn "movsi_gotoff_hi16"
243 [(set (match_operand:SI 0 "register_operand" "=r")
244 (unspec:SI [(match_operand 1 "" "")] UNSPEC_GOTOFF_HI16))]
246 "orhi %0, r0, gotoffhi16(%1)"
247 [(set_attr "type" "load")]
250 (define_insn "movsi_gotoff_lo16"
251 [(set (match_operand:SI 0 "register_operand" "=r")
252 (unspec:SI [(plus:SI (match_operand:SI 1 "register_operand" "0")
253 (match_operand 2 "" ""))] UNSPEC_GOTOFF_LO16))]
255 "addi %0, %1, gotofflo16(%2)"
256 [(set_attr "type" "arith")]
259 (define_insn "*movsi_lo_sum"
260 [(set (match_operand:SI 0 "register_operand" "=r")
261 (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
262 (match_operand:SI 2 "reloc_operand" "i")))]
265 [(set_attr "type" "arith")]
268 (define_insn "*movqi_insn"
269 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,m,r")
270 (match_operand:QI 1 "general_operand" "m,r,r,J,n"))]
271 "lm32_move_ok (QImode, operands)"
278 [(set_attr "type" "load,arith,store,store,arith")]
281 (define_insn "*movhi_insn"
282 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,m,r,r")
283 (match_operand:HI 1 "general_operand" "m,r,r,J,K,L"))]
284 "lm32_move_ok (HImode, operands)"
292 [(set_attr "type" "load,arith,store,store,arith,arith")]
295 (define_insn "movsi_insn"
296 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,m,r,r,r,r,r")
297 (match_operand:SI 1 "movsi_rhs_operand" "m,r,r,J,K,L,U,S,Y"))]
298 "lm32_move_ok (SImode, operands)"
309 [(set_attr "type" "load,arith,store,store,arith,arith,arith,arith,arith")]
312 ;; ---------------------------------
313 ;; sign and zero extension
314 ;; ---------------------------------
316 (define_insn "*extendqihi2"
317 [(set (match_operand:HI 0 "register_operand" "=r,r")
318 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
319 "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)"
323 [(set_attr "type" "load,arith")]
326 (define_insn "zero_extendqihi2"
327 [(set (match_operand:HI 0 "register_operand" "=r,r")
328 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
333 [(set_attr "type" "load,arith")]
336 (define_insn "*extendqisi2"
337 [(set (match_operand:SI 0 "register_operand" "=r,r")
338 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
339 "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)"
343 [(set_attr "type" "load,arith")]
346 (define_insn "zero_extendqisi2"
347 [(set (match_operand:SI 0 "register_operand" "=r,r")
348 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
353 [(set_attr "type" "load,arith")]
356 (define_insn "*extendhisi2"
357 [(set (match_operand:SI 0 "register_operand" "=r,r")
358 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
359 "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)"
363 [(set_attr "type" "load,arith")]
366 (define_insn "zero_extendhisi2"
367 [(set (match_operand:SI 0 "register_operand" "=r,r")
368 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
373 [(set_attr "type" "load,arith")]
376 ;; ---------------------------------
378 ;; ---------------------------------
380 (define_expand "cstoresi4"
381 [(set (match_operand:SI 0 "register_operand")
382 (match_operator:SI 1 "ordered_comparison_operator"
383 [(match_operand:SI 2 "register_operand")
384 (match_operand:SI 3 "register_or_int_operand")]))]
387 lm32_expand_scc (operands);
392 [(set (match_operand:SI 0 "register_operand" "=r,r")
393 (eq:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
394 (match_operand:SI 2 "register_or_K_operand" "r,K")))]
399 [(set_attr "type" "compare")]
403 [(set (match_operand:SI 0 "register_operand" "=r,r")
404 (ne:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
405 (match_operand:SI 2 "register_or_K_operand" "r,K")))]
410 [(set_attr "type" "compare")]
414 [(set (match_operand:SI 0 "register_operand" "=r,r")
415 (gt:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
416 (match_operand:SI 2 "register_or_K_operand" "r,K")))]
421 [(set_attr "type" "compare")]
425 [(set (match_operand:SI 0 "register_operand" "=r,r")
426 (ge:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
427 (match_operand:SI 2 "register_or_K_operand" "r,K")))]
432 [(set_attr "type" "compare")]
436 [(set (match_operand:SI 0 "register_operand" "=r,r")
437 (gtu:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
438 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
443 [(set_attr "type" "compare")]
447 [(set (match_operand:SI 0 "register_operand" "=r,r")
448 (geu:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
449 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
454 [(set_attr "type" "compare")]
457 ;; ---------------------------------
458 ;; unconditional branch
459 ;; ---------------------------------
462 [(set (pc) (label_ref (match_operand 0 "" "")))]
465 [(set_attr "type" "ubranch")]
468 (define_insn "indirect_jump"
469 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
472 [(set_attr "type" "uibranch")]
475 ;; ---------------------------------
476 ;; conditional branch
477 ;; ---------------------------------
479 (define_expand "cbranchsi4"
481 (if_then_else (match_operator 0 "comparison_operator"
482 [(match_operand:SI 1 "register_operand")
483 (match_operand:SI 2 "nonmemory_operand")])
484 (label_ref (match_operand 3 "" ""))
489 lm32_expand_conditional_branch (operands);
495 (if_then_else (eq:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
496 (match_operand:SI 1 "register_or_zero_operand" "rJ"))
497 (label_ref (match_operand 2 "" ""))
501 return get_attr_length (insn) == 4
503 : "bne %z0,%z1,8\n\tbi %2";
505 [(set_attr "type" "cbranch")])
509 (if_then_else (ne:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
510 (match_operand:SI 1 "register_or_zero_operand" "rJ"))
511 (label_ref (match_operand 2 "" ""))
515 return get_attr_length (insn) == 4
517 : "be %z0,%z1,8\n\tbi %2";
519 [(set_attr "type" "cbranch")])
523 (if_then_else (gt:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
524 (match_operand:SI 1 "register_or_zero_operand" "rJ"))
525 (label_ref (match_operand 2 "" ""))
529 return get_attr_length (insn) == 4
531 : "bge %z1,%z0,8\n\tbi %2";
533 [(set_attr "type" "cbranch")])
537 (if_then_else (ge:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
538 (match_operand:SI 1 "register_or_zero_operand" "rJ"))
539 (label_ref (match_operand 2 "" ""))
543 return get_attr_length (insn) == 4
545 : "bg %z1,%z0,8\n\tbi %2";
547 [(set_attr "type" "cbranch")])
551 (if_then_else (gtu:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
552 (match_operand:SI 1 "register_or_zero_operand" "rJ"))
553 (label_ref (match_operand 2 "" ""))
557 return get_attr_length (insn) == 4
559 : "bgeu %z1,%z0,8\n\tbi %2";
561 [(set_attr "type" "cbranch")])
565 (if_then_else (geu:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
566 (match_operand:SI 1 "register_or_zero_operand" "rJ"))
567 (label_ref (match_operand 2 "" ""))
571 return get_attr_length (insn) == 4
573 : "bgu %z1,%z0,8\n\tbi %2";
575 [(set_attr "type" "cbranch")])
577 ;; ---------------------------------
579 ;; ---------------------------------
581 (define_expand "call"
582 [(parallel [(call (match_operand 0 "" "")
583 (match_operand 1 "" ""))
584 (clobber (reg:SI RA_REGNUM))
589 rtx addr = XEXP (operands[0], 0);
590 if (!CONSTANT_ADDRESS_P (addr))
591 XEXP (operands[0], 0) = force_reg (Pmode, addr);
595 [(call (mem:SI (match_operand:SI 0 "call_operand" "r,s"))
596 (match_operand 1 "" ""))
597 (clobber (reg:SI RA_REGNUM))]
602 [(set_attr "type" "call,icall")]
605 (define_expand "call_value"
606 [(parallel [(set (match_operand 0 "" "")
607 (call (match_operand 1 "" "")
608 (match_operand 2 "" "")))
609 (clobber (reg:SI RA_REGNUM))
614 rtx addr = XEXP (operands[1], 0);
615 if (!CONSTANT_ADDRESS_P (addr))
616 XEXP (operands[1], 0) = force_reg (Pmode, addr);
619 (define_insn "*call_value"
620 [(set (match_operand 0 "register_operand" "=r,r")
621 (call (mem:SI (match_operand:SI 1 "call_operand" "r,s"))
622 (match_operand 2 "" "")))
623 (clobber (reg:SI RA_REGNUM))]
628 [(set_attr "type" "call,icall")]
631 (define_insn "return_internal"
632 [(use (match_operand:SI 0 "register_operand" "r"))
636 [(set_attr "type" "uibranch")]
639 (define_insn "return"
641 "lm32_can_use_return ()"
643 [(set_attr "type" "uibranch")]
646 ;; ---------------------------------
647 ;; switch/case statements
648 ;; ---------------------------------
650 (define_expand "tablejump"
651 [(set (pc) (match_operand 0 "register_operand" ""))
652 (use (label_ref (match_operand 1 "" "")))]
656 rtx target = operands[0];
659 /* For PIC, the table entry is relative to the start of the table. */
660 rtx label = gen_reg_rtx (SImode);
661 target = gen_reg_rtx (SImode);
662 emit_move_insn (label, gen_rtx_LABEL_REF (SImode, operands[1]));
663 emit_insn (gen_addsi3 (target, operands[0], label));
665 emit_jump_insn (gen_tablejumpsi (target, operands[1]));
669 (define_insn "tablejumpsi"
670 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
671 (use (label_ref (match_operand 1 "" "")))]
674 [(set_attr "type" "ubranch")]
677 ;; ---------------------------------
679 ;; ---------------------------------
681 (define_insn "addsi3"
682 [(set (match_operand:SI 0 "register_operand" "=r,r")
683 (plus:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
684 (match_operand:SI 2 "register_or_K_operand" "r,K")))]
689 [(set_attr "type" "arith")]
692 (define_insn "subsi3"
693 [(set (match_operand:SI 0 "register_operand" "=r")
694 (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
695 (match_operand:SI 2 "register_or_zero_operand" "rJ")))]
698 [(set_attr "type" "arith")]
701 (define_insn "mulsi3"
702 [(set (match_operand:SI 0 "register_operand" "=r,r")
703 (mult:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
704 (match_operand:SI 2 "register_or_K_operand" "r,K")))]
705 "TARGET_MULTIPLY_ENABLED"
709 [(set_attr "type" "multiply")]
712 (define_insn "udivsi3"
713 [(set (match_operand:SI 0 "register_operand" "=r")
714 (udiv:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
715 (match_operand:SI 2 "register_operand" "r")))]
716 "TARGET_DIVIDE_ENABLED"
718 [(set_attr "type" "divide")]
721 (define_insn "umodsi3"
722 [(set (match_operand:SI 0 "register_operand" "=r")
723 (umod:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
724 (match_operand:SI 2 "register_operand" "r")))]
725 "TARGET_DIVIDE_ENABLED"
727 [(set_attr "type" "divide")]
730 ;; ---------------------------------
731 ;; negation and inversion
732 ;; ---------------------------------
734 (define_insn "negsi2"
735 [(set (match_operand:SI 0 "register_operand" "=r")
736 (neg:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")))]
739 [(set_attr "type" "arith")]
742 (define_insn "one_cmplsi2"
743 [(set (match_operand:SI 0 "register_operand" "=r")
744 (not:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")))]
747 [(set_attr "type" "arith")]
750 ;; ---------------------------------
752 ;; ---------------------------------
754 (define_insn "andsi3"
755 [(set (match_operand:SI 0 "register_operand" "=r,r")
756 (and:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
757 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
762 [(set_attr "type" "arith")]
765 (define_insn "iorsi3"
766 [(set (match_operand:SI 0 "register_operand" "=r,r")
767 (ior:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
768 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
773 [(set_attr "type" "arith")]
776 (define_insn "xorsi3"
777 [(set (match_operand:SI 0 "register_operand" "=r,r")
778 (xor:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
779 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
784 [(set_attr "type" "arith")]
787 (define_insn "*norsi3"
788 [(set (match_operand:SI 0 "register_operand" "=r,r")
789 (not:SI (ior:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
790 (match_operand:SI 2 "register_or_L_operand" "r,L"))))]
795 [(set_attr "type" "arith")]
798 (define_insn "*xnorsi3"
799 [(set (match_operand:SI 0 "register_operand" "=r,r")
800 (not:SI (xor:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ,rJ")
801 (match_operand:SI 2 "register_or_L_operand" "r,L"))))]
806 [(set_attr "type" "arith")]
809 ;; ---------------------------------
811 ;; ---------------------------------
813 (define_expand "ashlsi3"
814 [(set (match_operand:SI 0 "register_operand" "")
815 (ashift:SI (match_operand:SI 1 "register_or_zero_operand" "")
816 (match_operand:SI 2 "register_or_L_operand" "")))]
819 if (!TARGET_BARREL_SHIFT_ENABLED)
822 && satisfies_constraint_L (operands[2])
823 && INTVAL (operands[2]) <= 8)
826 int shifts = INTVAL (operands[2]);
827 rtx one = GEN_INT (1);
830 emit_move_insn (operands[0], operands[1]);
832 emit_insn (gen_addsi3 (operands[0], operands[1], operands[1]));
833 for (i = 1; i < shifts; i++)
834 emit_insn (gen_addsi3 (operands[0], operands[0], operands[0]));
842 (define_insn "*ashlsi3"
843 [(set (match_operand:SI 0 "register_operand" "=r,r")
844 (ashift:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
845 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
846 "TARGET_BARREL_SHIFT_ENABLED"
850 [(set_attr "type" "shift")]
853 (define_expand "ashrsi3"
854 [(set (match_operand:SI 0 "register_operand" "")
855 (ashiftrt:SI (match_operand:SI 1 "register_or_zero_operand" "")
856 (match_operand:SI 2 "register_or_L_operand" "")))]
859 if (!TARGET_BARREL_SHIFT_ENABLED)
862 && satisfies_constraint_L (operands[2])
863 && INTVAL (operands[2]) <= 8)
866 int shifts = INTVAL (operands[2]);
867 rtx one = GEN_INT (1);
870 emit_move_insn (operands[0], operands[1]);
872 emit_insn (gen_ashrsi3_1bit (operands[0], operands[1], one));
873 for (i = 1; i < shifts; i++)
874 emit_insn (gen_ashrsi3_1bit (operands[0], operands[0], one));
882 (define_insn "*ashrsi3"
883 [(set (match_operand:SI 0 "register_operand" "=r,r")
884 (ashiftrt:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
885 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
886 "TARGET_BARREL_SHIFT_ENABLED"
890 [(set_attr "type" "shift")]
893 (define_insn "ashrsi3_1bit"
894 [(set (match_operand:SI 0 "register_operand" "=r")
895 (ashiftrt:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
896 (match_operand:SI 2 "constant_M_operand" "M")))]
897 "!TARGET_BARREL_SHIFT_ENABLED"
899 [(set_attr "type" "shift")]
902 (define_expand "lshrsi3"
903 [(set (match_operand:SI 0 "register_operand" "")
904 (lshiftrt:SI (match_operand:SI 1 "register_or_zero_operand" "")
905 (match_operand:SI 2 "register_or_L_operand" "")))]
908 if (!TARGET_BARREL_SHIFT_ENABLED)
911 && satisfies_constraint_L (operands[2])
912 && INTVAL (operands[2]) <= 8)
915 int shifts = INTVAL (operands[2]);
916 rtx one = GEN_INT (1);
919 emit_move_insn (operands[0], operands[1]);
921 emit_insn (gen_lshrsi3_1bit (operands[0], operands[1], one));
922 for (i = 1; i < shifts; i++)
923 emit_insn (gen_lshrsi3_1bit (operands[0], operands[0], one));
931 (define_insn "*lshrsi3"
932 [(set (match_operand:SI 0 "register_operand" "=r,r")
933 (lshiftrt:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
934 (match_operand:SI 2 "register_or_L_operand" "r,L")))]
935 "TARGET_BARREL_SHIFT_ENABLED"
939 [(set_attr "type" "shift")]
942 (define_insn "lshrsi3_1bit"
943 [(set (match_operand:SI 0 "register_operand" "=r")
944 (lshiftrt:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
945 (match_operand:SI 2 "constant_M_operand" "M")))]
946 "!TARGET_BARREL_SHIFT_ENABLED"
948 [(set_attr "type" "shift")]
951 ;; ---------------------------------
952 ;; function entry / exit
953 ;; ---------------------------------
955 (define_expand "prologue"
960 lm32_expand_prologue ();
964 (define_expand "epilogue"
969 lm32_expand_epilogue ();
973 ;; ---------------------------------
975 ;; ---------------------------------
981 [(set_attr "type" "arith")]
984 ;; ---------------------------------
986 ;; ---------------------------------
988 ;; used to stop the scheduler from
989 ;; scheduling code across certain boundaries
991 (define_insn "blockage"
992 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
995 [(set_attr "length" "0")]