1 ; Copyright (C) 2005, 2006, 2008, 2009, 2010, 2011
2 ; Free Software Foundation, Inc.
4 ; This file is part of GCC.
6 ; GCC is free software; you can redistribute it and/or modify it under
7 ; the terms of the GNU General Public License as published by the Free
8 ; Software Foundation; either version 3, or (at your option) any later
11 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 ; You should have received a copy of the GNU General Public License
17 ; along with GCC; see the file COPYING3. If not see
18 ; <http://www.gnu.org/licenses/>.
21 config/ia64/ia64-opts.h
23 ; Which cpu are we scheduling for.
25 enum processor_type ia64_tune = PROCESSOR_ITANIUM2
28 Target Report RejectNegative Mask(BIG_ENDIAN)
29 Generate big endian code
32 Target Report RejectNegative InverseMask(BIG_ENDIAN)
33 Generate little endian code
36 Target Report Mask(GNU_AS)
37 Generate code for GNU as
40 Target Report Mask(GNU_LD)
41 Generate code for GNU ld
44 Target Report Mask(VOL_ASM_STOP)
45 Emit stop bits before and after volatile extended asms
48 Target Mask(REG_NAMES)
49 Use in/loc/out register names
52 Target Report RejectNegative Mask(NO_SDATA)
55 Target Report RejectNegative InverseMask(NO_SDATA)
56 Enable use of sdata/scommon/sbss
59 Target Report RejectNegative Mask(NO_PIC)
60 Generate code without GP reg
63 Target Report RejectNegative Mask(CONST_GP)
64 gp is constant (but save/restore gp on indirect calls)
67 Target Report RejectNegative Mask(AUTO_PIC)
68 Generate self-relocatable code
70 minline-float-divide-min-latency
71 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 1)
72 Generate inline floating point division, optimize for latency
74 minline-float-divide-max-throughput
75 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 2) Init(2)
76 Generate inline floating point division, optimize for throughput
78 mno-inline-float-divide
79 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 0)
81 minline-int-divide-min-latency
82 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 1)
83 Generate inline integer division, optimize for latency
85 minline-int-divide-max-throughput
86 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 2)
87 Generate inline integer division, optimize for throughput
90 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 0)
91 Do not inline integer division
93 minline-sqrt-min-latency
94 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 1)
95 Generate inline square root, optimize for latency
97 minline-sqrt-max-throughput
98 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 2)
99 Generate inline square root, optimize for throughput
102 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 0)
103 Do not inline square root
106 Target Report Mask(DWARF2_ASM)
107 Enable Dwarf 2 line debug info via GNU as
110 Target Report Mask(EARLY_STOP_BITS)
111 Enable earlier placing stop bits for better scheduling
114 Target RejectNegative Joined Var(ia64_deferred_options) Defer
115 Specify range of registers to make fixed
118 Target RejectNegative Joined UInteger Var(ia64_tls_size) Init(22)
119 Specify bit size of immediate TLS offsets
122 Target RejectNegative Joined Enum(ia64_tune) Var(ia64_tune)
123 Schedule code for given CPU
126 Name(ia64_tune) Type(enum processor_type)
127 Known Itanium CPUs (for use with the -mtune= option):
130 Enum(ia64_tune) String(itanium2) Value(PROCESSOR_ITANIUM2)
133 Enum(ia64_tune) String(mckinley) Value(PROCESSOR_ITANIUM2)
136 Target Report Var(mflag_sched_br_data_spec) Init(0)
137 Use data speculation before reload
140 Target Report Var(mflag_sched_ar_data_spec) Init(1)
141 Use data speculation after reload
144 Target Report Var(mflag_sched_control_spec) Init(2)
145 Use control speculation
147 msched-br-in-data-spec
148 Target Report Var(mflag_sched_br_in_data_spec) Init(1)
149 Use in block data speculation before reload
151 msched-ar-in-data-spec
152 Target Report Var(mflag_sched_ar_in_data_spec) Init(1)
153 Use in block data speculation after reload
155 msched-in-control-spec
156 Target Report Var(mflag_sched_in_control_spec) Init(1)
157 Use in block control speculation
160 Target Report Var(mflag_sched_spec_ldc) Init(1)
161 Use simple data speculation check
163 msched-spec-control-ldc
164 Target Report Var(mflag_sched_spec_control_ldc) Init(0)
165 Use simple data speculation check for control speculation
167 msched-prefer-non-data-spec-insns
168 Target Report Var(mflag_sched_prefer_non_data_spec_insns) Init(0)
169 If set, data speculative instructions will be chosen for schedule only if there are no other choices at the moment
171 msched-prefer-non-control-spec-insns
172 Target Report Var(mflag_sched_prefer_non_control_spec_insns) Init(0)
173 If set, control speculative instructions will be chosen for schedule only if there are no other choices at the moment
175 msched-count-spec-in-critical-path
176 Target Report Var(mflag_sched_count_spec_in_critical_path) Init(0)
177 Count speculative dependencies while calculating priority of instructions
179 msched-stop-bits-after-every-cycle
180 Target Report Var(mflag_sched_stop_bits_after_every_cycle) Init(1)
181 Place a stop bit after every cycle when scheduling
183 msched-fp-mem-deps-zero-cost
184 Target Report Var(mflag_sched_fp_mem_deps_zero_cost) Init(0)
185 Assume that floating-point stores and loads are not likely to cause conflict when placed into one instruction group
187 msched-max-memory-insns=
188 Target RejectNegative Joined UInteger Var(ia64_max_memory_insns) Init(1)
189 Soft limit on number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same insn group. Frequently useful to prevent cache bank conflicts. Default value is 1
191 msched-max-memory-insns-hard-limit
192 Target Report Var(mflag_sched_mem_insns_hard_limit) Init(0)
193 Disallow more than 'msched-max-memory-insns' in instruction group. Otherwise, limit is 'soft' (prefer non-memory operations when limit is reached)
195 msel-sched-dont-check-control-spec
196 Target Report Var(mflag_sel_sched_dont_check_control_spec) Init(0)
197 Don't generate checks for control speculation in selective scheduling
199 ; This comment is to ensure we retain the blank line above.