1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; Some of the extend instructions accept a general_operand_src, which
26 ;; allows all the normal memory addressing modes. The length computations
27 ;; don't take this into account. The lengths in the MD file should be
28 ;; "worst case" and then be adjusted to their correct values by
29 ;; h8300_adjust_insn_length.
31 ;; On the H8/300H and H8/S, adds/subs operate on the 32bit "er"
32 ;; registers. Right now GCC doesn't expose the "e" half to the
33 ;; compiler, so using add/subs for addhi and subhi is safe. Long
34 ;; term, we want to expose the "e" half to the compiler (gives us 8
35 ;; more 16bit registers). At that point addhi and subhi can't use
38 ;; There's currently no way to have a insv/extzv expander for the H8/300H
39 ;; because word_mode is different for the H8/300 and H8/300H.
41 ;; Shifts/rotates by small constants should be handled by special
42 ;; patterns so we get the length and cc status correct.
44 ;; Bitfield operations no longer accept memory operands. We need
45 ;; to add variants which operate on memory back to the MD.
47 ;; ??? Implement remaining bit ops available on the h8300
49 ;; ----------------------------------------------------------------------
51 ;; ----------------------------------------------------------------------
61 ;; ----------------------------------------------------------------------
63 ;; ----------------------------------------------------------------------
65 (define_attr "cpu" "h8300,h8300h"
66 (const (symbol_ref "cpu_type")))
68 (define_attr "type" "branch,arith"
69 (const_string "arith"))
71 ;; The size of instructions in bytes.
73 (define_attr "length" ""
74 (cond [(eq_attr "type" "branch")
75 (if_then_else (and (ge (minus (match_dup 0) (pc))
77 (le (minus (match_dup 0) (pc))
80 (if_then_else (and (eq_attr "cpu" "h8300h")
81 (and (ge (minus (pc) (match_dup 0))
83 (le (minus (pc) (match_dup 0))
89 ;; The necessity of instruction length adjustment.
91 (define_attr "adjust_length" "yes,no"
92 (cond [(eq_attr "type" "branch") (const_string "no")]
93 (const_string "yes")))
95 ;; Condition code settings.
97 ;; none - insn does not affect cc
98 ;; none_0hit - insn does not affect cc but it does modify operand 0
99 ;; This attribute is used to keep track of when operand 0 changes.
100 ;; See the description of NOTICE_UPDATE_CC for more info.
101 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
102 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
103 ;; compare - compare instruction
104 ;; clobber - value of cc is unknown
106 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
107 (const_string "clobber"))
109 ;; ----------------------------------------------------------------------
111 ;; ----------------------------------------------------------------------
115 (define_insn "pushqi1_h8300"
116 [(parallel [(set (reg:HI SP_REG)
117 (plus:HI (reg:HI SP_REG) (const_int -2)))
118 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
119 (match_operand:QI 0 "register_operand" "r"))])]
122 [(set_attr "length" "2")
123 (set_attr "cc" "clobber")])
125 (define_insn "pushqi1_h8300hs"
126 [(parallel [(set (reg:SI SP_REG)
127 (plus:SI (reg:SI SP_REG) (const_int -4)))
128 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
129 (match_operand:QI 0 "register_operand" "r"))])]
130 "TARGET_H8300H || TARGET_H8300S"
132 [(set_attr "length" "4")
133 (set_attr "cc" "clobber")])
135 (define_expand "pushqi1"
136 [(use (match_operand:QI 0 "register_operand" ""))]
141 emit_insn (gen_pushqi1_h8300 (operands[0]));
143 emit_insn (gen_pushqi1_h8300hs (operands[0]));
148 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
149 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
151 && (register_operand (operands[0], QImode)
152 || register_operand (operands[1], QImode))"
160 [(set_attr "length" "2,2,2,2,4,4")
161 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
164 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
165 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
166 "(TARGET_H8300H || TARGET_H8300S)
167 && (register_operand (operands[0], QImode)
168 || register_operand (operands[1], QImode))"
176 [(set_attr "length" "2,2,2,2,8,8")
177 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
179 (define_expand "movqi"
180 [(set (match_operand:QI 0 "general_operand_dst" "")
181 (match_operand:QI 1 "general_operand_src" ""))]
185 /* One of the ops has to be in a register. */
186 if (!register_operand (operand0, QImode)
187 && !register_operand (operand1, QImode))
189 operands[1] = copy_to_mode_reg (QImode, operand1);
193 (define_insn "movstrictqi"
194 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
195 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
202 [(set_attr_alternative "length"
203 [(const_int 2) (const_int 2) (const_int 2)
204 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
205 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
209 (define_expand "pushhi1_h8300"
210 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
211 (match_operand:HI 0 "register_operand" ""))]
215 (define_insn "pushhi1_h8300hs"
216 [(parallel [(set (reg:SI SP_REG)
217 (plus:SI (reg:SI SP_REG) (const_int -4)))
218 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
219 (match_operand:HI 0 "register_operand" "r"))])]
220 "TARGET_H8300H || TARGET_H8300S"
222 [(set_attr "length" "4")
223 (set_attr "cc" "clobber")])
225 (define_expand "pushhi1"
226 [(use (match_operand:HI 0 "register_operand" ""))]
231 emit_insn (gen_pushhi1_h8300 (operands[0]));
233 emit_insn (gen_pushhi1_h8300hs (operands[0]));
238 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
239 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
241 && (register_operand (operands[0], HImode)
242 || register_operand (operands[1], HImode))
243 && !(GET_CODE (operands[0]) == MEM
244 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
245 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
246 && GET_CODE (operands[1]) == REG
247 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
255 [(set_attr "length" "2,2,2,4,4,4")
256 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
259 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
260 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
261 "(TARGET_H8300H || TARGET_H8300S)
262 && (register_operand (operands[0], HImode)
263 || register_operand (operands[1], HImode))"
271 [(set_attr "length" "2,2,2,4,8,8")
272 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
274 (define_expand "movhi"
275 [(set (match_operand:HI 0 "general_operand_dst" "")
276 (match_operand:HI 1 "general_operand_src" ""))]
280 /* One of the ops has to be in a register. */
281 if (!register_operand (operand1, HImode)
282 && !register_operand (operand0, HImode))
284 operands[1] = copy_to_mode_reg (HImode, operand1);
288 (define_insn "movstricthi"
289 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
290 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
297 [(set_attr_alternative "length"
298 [(const_int 2) (const_int 2) (const_int 4)
299 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
300 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
304 (define_expand "movsi"
305 [(set (match_operand:SI 0 "general_operand_dst" "")
306 (match_operand:SI 1 "general_operand_src" ""))]
312 if (do_movsi (operands))
317 /* One of the ops has to be in a register. */
318 if (!register_operand (operand1, SImode)
319 && !register_operand (operand0, SImode))
321 operands[1] = copy_to_mode_reg (SImode, operand1);
326 (define_expand "movsf"
327 [(set (match_operand:SF 0 "general_operand_dst" "")
328 (match_operand:SF 1 "general_operand_src" ""))]
334 if (do_movsi (operands))
339 /* One of the ops has to be in a register. */
340 if (!register_operand (operand1, SFmode)
341 && !register_operand (operand0, SFmode))
343 operands[1] = copy_to_mode_reg (SFmode, operand1);
348 (define_insn "movsi_h8300"
349 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
350 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
352 && (register_operand (operands[0], SImode)
353 || register_operand (operands[1], SImode))"
357 switch (which_alternative)
360 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
362 if (REGNO (operands[0]) < REGNO (operands[1]))
363 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
365 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
367 /* Make sure we don't trample the register we index with. */
368 if (GET_CODE (operands[1]) == MEM)
370 rtx inside = XEXP (operands[1], 0);
375 else if (GET_CODE (inside) == PLUS)
377 rtx lhs = XEXP (inside, 0);
378 rtx rhs = XEXP (inside, 1);
379 if (REG_P (lhs)) rn = REGNO (lhs);
380 if (REG_P (rhs)) rn = REGNO (rhs);
383 if (rn == REGNO (operands[0]))
385 /* Move the second word first. */
386 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
390 /* See if either half is zero. If so, use sub.w to clear
392 if (GET_CODE (operands[1]) == CONST_INT)
394 if ((INTVAL (operands[1]) & 0xffff) == 0)
395 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
396 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
397 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
399 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
402 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
404 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
406 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
411 [(set_attr "length" "4,4,8,8,4,4")
412 (set_attr "cc" "clobber")])
414 (define_insn "movsf_h8300"
415 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
416 (match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
418 && (register_operand (operands[0], SFmode)
419 || register_operand (operands[1], SFmode))"
422 /* Copy of the movsi stuff. */
424 switch (which_alternative)
427 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
429 if (REGNO (operands[0]) < REGNO (operands[1]))
430 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
432 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
434 /* Make sure we don't trample the register we index with. */
435 if (GET_CODE (operands[1]) == MEM)
437 rtx inside = XEXP (operands[1], 0);
442 else if (GET_CODE (inside) == PLUS)
444 rtx lhs = XEXP (inside, 0);
445 rtx rhs = XEXP (inside, 1);
446 if (REG_P (lhs)) rn = REGNO (lhs);
447 if (REG_P (rhs)) rn = REGNO (rhs);
450 if (rn == REGNO (operands[0]))
451 /* Move the second word first. */
452 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
454 /* Move the first word first. */
455 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
458 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
460 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
462 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
467 [(set_attr "length" "4,4,8,8,4,4")
468 (set_attr "cc" "clobber")])
470 (define_insn "movsi_h8300hs"
471 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,r,m,<,r,*a,*a,r")
472 (match_operand:SI 1 "general_operand_src" "I,r,i,m,r,r,>,I,r,*a"))]
473 "(TARGET_H8300S || TARGET_H8300H)
474 && (register_operand (operands[0], SImode)
475 || register_operand (operands[1], SImode))
476 && !(GET_CODE (operands[0]) == MEM
477 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
478 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
479 && GET_CODE (operands[1]) == REG
480 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
483 switch (which_alternative)
486 return \"sub.l %S0,%S0\";
490 return \"clrmac\;ldmac %1,macl\";
492 return \"stmac macl,%0\";
494 if (GET_CODE (operands[1]) == CONST_INT)
496 int val = INTVAL (operands[1]);
498 /* Look for constants which can be made by adding an 8-bit
499 number to zero in one of the two low bytes. */
500 if (val == (val & 0xff))
502 operands[1] = GEN_INT ((char) val & 0xff);
503 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
506 if (val == (val & 0xff00))
508 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
509 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
512 /* Look for constants that can be obtained by subs, inc, and
514 switch (val & 0xffffffff)
517 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
519 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
521 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
524 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
526 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
529 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
531 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
534 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
536 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
540 return \"mov.l %S1,%S0\";
542 [(set_attr "length" "2,2,6,10,10,4,4,2,6,4")
543 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
545 (define_insn "movsf_h8300h"
546 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
547 (match_operand:SF 1 "general_operand_src" "I,r,im,r,r,>"))]
548 "(TARGET_H8300H || TARGET_H8300S)
549 && (register_operand (operands[0], SFmode)
550 || register_operand (operands[1], SFmode))"
558 [(set_attr "length" "2,2,10,10,4,4")
559 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
561 ;; ----------------------------------------------------------------------
563 ;; ----------------------------------------------------------------------
566 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
568 (match_operand 1 "const_int_operand" "n,n")))]
571 [(set_attr "length" "2,4")
572 (set_attr "cc" "set_zn,set_zn")])
575 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
577 (match_operand 1 "const_int_operand" "n")))]
580 [(set_attr "length" "2")
581 (set_attr "cc" "set_zn")])
584 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "r,U")
586 (match_operand 1 "const_int_operand" "n,n")))]
587 "TARGET_H8300H || TARGET_H8300S"
589 [(set_attr "length" "2,8")
590 (set_attr "cc" "set_zn,set_zn")])
593 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
595 (match_operand 1 "const_int_operand" "n")))]
596 "(TARGET_H8300H || TARGET_H8300S)
597 && INTVAL (operands[1]) <= 15"
599 [(set_attr "length" "2")
600 (set_attr "cc" "set_zn")])
603 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
606 [(set_attr "length" "2")
607 (set_attr "cc" "set_znv")])
610 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
613 [(set_attr "length" "2")
614 (set_attr "cc" "set_znv")])
617 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
618 "TARGET_H8300H || TARGET_H8300S"
620 [(set_attr "length" "2")
621 (set_attr "cc" "set_znv")])
625 (compare:QI (match_operand:QI 0 "register_operand" "r")
626 (match_operand:QI 1 "nonmemory_operand" "rn")))]
629 [(set_attr "length" "2")
630 (set_attr "cc" "compare")])
632 (define_expand "cmphi"
634 (compare:HI (match_operand:HI 0 "register_operand" "")
635 (match_operand:HI 1 "nonmemory_operand" "")))]
639 /* Force operand1 into a register if we're compiling
641 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
642 operands[1] = force_reg (HImode, operands[1]);
647 (compare:HI (match_operand:HI 0 "register_operand" "r")
648 (match_operand:HI 1 "register_operand" "r")))]
651 [(set_attr "length" "2")
652 (set_attr "cc" "compare")])
656 (compare:HI (match_operand:HI 0 "register_operand" "r,r")
657 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
658 "TARGET_H8300H || TARGET_H8300S"
660 [(set_attr "length" "2,4")
661 (set_attr "cc" "compare,compare")])
665 (compare:SI (match_operand:SI 0 "register_operand" "r,r")
666 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
667 "TARGET_H8300H || TARGET_H8300S"
669 [(set_attr "length" "2,6")
670 (set_attr "cc" "compare,compare")])
672 ;; ----------------------------------------------------------------------
674 ;; ----------------------------------------------------------------------
676 (define_insn "addqi3"
677 [(set (match_operand:QI 0 "register_operand" "=r")
678 (plus:QI (match_operand:QI 1 "register_operand" "%0")
679 (match_operand:QI 2 "nonmemory_operand" "rn")))]
682 [(set_attr "length" "2")
683 (set_attr "cc" "set_zn")])
685 (define_expand "addhi3"
686 [(set (match_operand:HI 0 "register_operand" "")
687 (plus:HI (match_operand:HI 1 "register_operand" "")
688 (match_operand:HI 2 "nonmemory_operand" "")))]
693 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,&r")
694 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,g")
695 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r,r")))]
700 add.b %s2,%s0\;addx %t2,%t0
702 mov.w %T1,%T0\;add.w %T2,%T0"
703 [(set_attr "length" "2,2,4,2,6")
704 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
707 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
708 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
709 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r")))]
710 "TARGET_H8300H || TARGET_H8300S"
716 [(set_attr "length" "2,2,4,2")
717 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
720 [(set (match_operand:HI 0 "register_operand" "")
721 (plus:HI (match_dup 0)
722 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
725 "split_adds_subs (HImode, operands); DONE;")
727 (define_expand "addsi3"
728 [(set (match_operand:SI 0 "register_operand" "")
729 (plus:SI (match_operand:SI 1 "register_operand" "")
730 (match_operand:SI 2 "nonmemory_operand" "")))]
734 (define_insn "addsi_h8300"
735 [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
736 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
737 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
740 add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0
741 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0
742 mov.w %f1,%f0\;mov.w %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0"
743 [(set_attr "length" "8,6,10")
744 (set_attr "cc" "clobber")])
746 (define_insn "addsi_h8300h"
747 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
748 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
749 (match_operand:SI 2 "nonmemory_operand" "L,N,i,r")))]
750 "TARGET_H8300H || TARGET_H8300S"
756 [(set_attr "length" "2,2,6,2")
757 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
760 [(set (match_operand:SI 0 "register_operand" "")
761 (plus:SI (match_dup 0)
762 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
763 "TARGET_H8300H || TARGET_H8300S"
765 "split_adds_subs (SImode, operands); DONE;")
767 ;; ----------------------------------------------------------------------
768 ;; SUBTRACT INSTRUCTIONS
769 ;; ----------------------------------------------------------------------
771 (define_insn "subqi3"
772 [(set (match_operand:QI 0 "register_operand" "=r")
773 (minus:QI (match_operand:QI 1 "register_operand" "0")
774 (match_operand:QI 2 "register_operand" "r")))]
777 [(set_attr "length" "2")
778 (set_attr "cc" "set_zn")])
780 (define_expand "subhi3"
781 [(set (match_operand:HI 0 "register_operand" "")
782 (minus:HI (match_operand:HI 1 "general_operand" "")
783 (match_operand:HI 2 "nonmemory_operand" "")))]
788 [(set (match_operand:HI 0 "register_operand" "=r,&r")
789 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
790 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
794 add.b %E2,%s0\;addx %F2,%t0"
795 [(set_attr "length" "2,4")
796 (set_attr "cc" "set_zn,clobber")])
799 [(set (match_operand:HI 0 "register_operand" "=r,&r")
800 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
801 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
802 "TARGET_H8300H || TARGET_H8300S"
806 [(set_attr "length" "2,4")
807 (set_attr "cc" "set_zn,set_zn")])
809 (define_expand "subsi3"
810 [(set (match_operand:SI 0 "register_operand" "")
811 (minus:SI (match_operand:SI 1 "register_operand" "")
812 (match_operand:SI 2 "nonmemory_operand" "")))]
816 (define_insn "subsi3_h8300"
817 [(set (match_operand:SI 0 "register_operand" "=r")
818 (minus:SI (match_operand:SI 1 "register_operand" "0")
819 (match_operand:SI 2 "register_operand" "r")))]
821 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
822 [(set_attr "length" "6")
823 (set_attr "cc" "clobber")])
825 (define_insn "subsi3_h8300h"
826 [(set (match_operand:SI 0 "register_operand" "=r,r")
827 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
828 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
829 "TARGET_H8300H || TARGET_H8300S"
833 [(set_attr "length" "2,6")
834 (set_attr "cc" "set_zn,set_zn")])
836 ;; ----------------------------------------------------------------------
837 ;; MULTIPLY INSTRUCTIONS
838 ;; ----------------------------------------------------------------------
840 ;; Note that the H8/300 can only handle umulqihi3.
842 (define_insn "mulqihi3"
843 [(set (match_operand:HI 0 "register_operand" "=r")
844 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
845 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
846 "TARGET_H8300H || TARGET_H8300S"
848 [(set_attr "length" "4")
849 (set_attr "cc" "set_zn")])
851 (define_insn "mulhisi3"
852 [(set (match_operand:SI 0 "register_operand" "=r")
853 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
854 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
855 "TARGET_H8300H || TARGET_H8300S"
857 [(set_attr "length" "4")
858 (set_attr "cc" "set_zn")])
860 (define_insn "umulqihi3"
861 [(set (match_operand:HI 0 "register_operand" "=r")
862 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
863 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
866 [(set_attr "length" "2")
867 (set_attr "cc" "none_0hit")])
869 (define_insn "umulhisi3"
870 [(set (match_operand:SI 0 "register_operand" "=r")
871 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
872 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
873 "TARGET_H8300H || TARGET_H8300S"
875 [(set_attr "length" "2")
876 (set_attr "cc" "none_0hit")])
878 ;; This is a "bridge" instruction. Combine can't cram enough insns
879 ;; together to crate a MAC instruction directly, but it can create
880 ;; this instruction, which then allows combine to create the real
883 ;; Unfortunately, if combine doesn't create a MAC instruction, this
884 ;; insn must generate reasonably correct code. Egad.
886 [(set (match_operand:SI 0 "register_operand" "=a")
889 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
891 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
893 "clrmac\;mac @%2+,@%1+"
894 [(set_attr "length" "6")
895 (set_attr "cc" "none_0hit")])
898 [(set (match_operand:SI 0 "register_operand" "=a")
900 (sign_extend:SI (mem:HI
901 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
902 (sign_extend:SI (mem:HI
903 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
904 (match_operand:SI 3 "register_operand" "0")))]
907 [(set_attr "length" "4")
908 (set_attr "cc" "none_0hit")])
910 ;; ----------------------------------------------------------------------
911 ;; DIVIDE/MOD INSTRUCTIONS
912 ;; ----------------------------------------------------------------------
914 (define_insn "udivmodqi4"
915 [(set (match_operand:QI 0 "register_operand" "=r")
918 (match_operand:HI 1 "register_operand" "0")
919 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
920 (set (match_operand:QI 3 "register_operand" "=r")
924 (zero_extend:HI (match_dup 2)))))]
925 "TARGET_H8300H || TARGET_H8300S"
928 if (find_reg_note (insn, REG_UNUSED, operands[3]))
929 return \"divxu.b\\t%X2,%T0\";
931 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
933 [(set_attr "length" "4")
934 (set_attr "cc" "clobber")])
936 (define_insn "divmodqi4"
937 [(set (match_operand:QI 0 "register_operand" "=r")
940 (match_operand:HI 1 "register_operand" "0")
941 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
942 (set (match_operand:QI 3 "register_operand" "=r")
946 (sign_extend:HI (match_dup 2)))))]
947 "TARGET_H8300H || TARGET_H8300S"
950 if (find_reg_note (insn, REG_UNUSED, operands[3]))
951 return \"divxs.b\\t%X2,%T0\";
953 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
955 [(set_attr "length" "6")
956 (set_attr "cc" "clobber")])
958 (define_insn "udivmodhi4"
959 [(set (match_operand:HI 0 "register_operand" "=r")
962 (match_operand:SI 1 "register_operand" "0")
963 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
964 (set (match_operand:HI 3 "register_operand" "=r")
968 (zero_extend:SI (match_dup 2)))))]
969 "TARGET_H8300H || TARGET_H8300S"
972 if (find_reg_note (insn, REG_UNUSED, operands[3]))
973 return \"divxu.w\\t%T2,%S0\";
975 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
977 [(set_attr "length" "4")
978 (set_attr "cc" "clobber")])
980 (define_insn "divmodhi4"
981 [(set (match_operand:HI 0 "register_operand" "=r")
984 (match_operand:SI 1 "register_operand" "0")
985 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
986 (set (match_operand:HI 3 "register_operand" "=r")
990 (sign_extend:SI (match_dup 2)))))]
991 "TARGET_H8300H || TARGET_H8300S"
994 if (find_reg_note (insn, REG_UNUSED, operands[3]))
995 return \"divxs.w\\t%T2,%S0\";
997 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
999 [(set_attr "length" "6")
1000 (set_attr "cc" "clobber")])
1002 ;; ----------------------------------------------------------------------
1004 ;; ----------------------------------------------------------------------
1007 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1008 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1009 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
1010 "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)"
1014 [(set_attr "length" "2,8")
1015 (set_attr "adjust_length" "no")
1016 (set_attr "cc" "set_znv,none_0hit")])
1018 (define_expand "andqi3"
1019 [(set (match_operand:QI 0 "bit_operand" "")
1020 (and:QI (match_operand:QI 1 "bit_operand" "")
1021 (match_operand:QI 2 "nonmemory_operand" "")))]
1025 if (fix_bit_operand (operands, 'O', AND))
1029 (define_expand "andhi3"
1030 [(set (match_operand:HI 0 "register_operand" "")
1031 (and:HI (match_operand:HI 1 "register_operand" "")
1032 (match_operand:HI 2 "nonmemory_operand" "")))]
1037 [(set (match_operand:HI 0 "register_operand" "=r")
1038 (and:HI (match_operand:HI 1 "register_operand" "%0")
1039 (match_operand:HI 2 "nonmemory_operand" "rn")))]
1041 "* return output_logical_op (HImode, AND, operands);"
1042 [(set (attr "length")
1043 (symbol_ref "compute_logical_op_length (HImode, AND, operands)"))
1044 (set_attr "cc" "clobber")])
1047 [(set (match_operand:HI 0 "register_operand" "=r,r")
1048 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
1049 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
1050 "TARGET_H8300H || TARGET_H8300S"
1051 "* return output_logical_op (HImode, AND, operands);"
1052 [(set (attr "length")
1053 (symbol_ref "compute_logical_op_length (HImode, AND, operands)"))
1054 (set_attr "cc" "set_znv,clobber")])
1056 (define_insn "*andorhi3"
1057 [(set (match_operand:HI 0 "register_operand" "=r")
1058 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1059 (match_operand:HI 3 "const_int_operand" "n"))
1060 (match_operand:HI 1 "register_operand" "0")))]
1061 "exact_log2 (INTVAL (operands[3]) & 0xffff) != -1"
1064 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1065 if (INTVAL (operands[3]) > 128)
1067 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1068 return \"bld\\t%V3,%t2\;bst\\t%V3,%t0\";
1070 return \"bld\\t%V3,%s2\;bst\\t%V3,%s0\";
1072 [(set_attr "length" "4")
1073 (set_attr "cc" "clobber")])
1075 (define_expand "andsi3"
1076 [(set (match_operand:SI 0 "register_operand" "")
1077 (and:SI (match_operand:SI 1 "register_operand" "")
1078 (match_operand:SI 2 "nonmemory_operand" "")))]
1083 [(set (match_operand:SI 0 "register_operand" "=r")
1084 (and:SI (match_operand:SI 1 "register_operand" "%0")
1085 (match_operand:SI 2 "nonmemory_operand" "rn")))]
1087 "* return output_logical_op (SImode, AND, operands);"
1088 [(set (attr "length")
1089 (symbol_ref "compute_logical_op_length (SImode, AND, operands)"))
1090 (set_attr "cc" "clobber")])
1093 [(set (match_operand:SI 0 "register_operand" "=r,r")
1094 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
1095 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1096 "TARGET_H8300H || TARGET_H8300S"
1097 "* return output_logical_op (SImode, AND, operands);"
1098 [(set (attr "length")
1099 (symbol_ref "compute_logical_op_length (SImode, AND, operands)"))
1100 (set_attr "cc" "set_znv,clobber")])
1102 ;; ----------------------------------------------------------------------
1104 ;; ----------------------------------------------------------------------
1107 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1108 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1109 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1110 "register_operand (operands[0], QImode)
1111 || (GET_CODE (operands[2]) == CONST_INT
1112 && exact_log2 (INTVAL (operands[2]) & 0xff) != -1)"
1115 switch (which_alternative)
1118 return \"or\t%X2,%X0\";
1120 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
1121 return \"bset\t%V2,%R0\";
1126 [(set_attr "length" "2,8")
1127 (set_attr "adjust_length" "no")
1128 (set_attr "cc" "set_znv,none_0hit")])
1130 (define_expand "iorqi3"
1131 [(set (match_operand:QI 0 "bit_operand" "")
1132 (ior:QI (match_operand:QI 1 "bit_operand" "")
1133 (match_operand:QI 2 "nonmemory_operand" "")))]
1137 if (fix_bit_operand (operands, 'P', IOR))
1141 (define_expand "iorhi3"
1142 [(set (match_operand:HI 0 "register_operand" "")
1143 (ior:HI (match_operand:HI 1 "register_operand" "")
1144 (match_operand:HI 2 "nonmemory_operand" "")))]
1149 [(set (match_operand:HI 0 "general_operand" "=r,r")
1150 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
1151 (match_operand:HI 2 "general_operand" "J,rn")))]
1153 "* return output_logical_op (HImode, IOR, operands);"
1154 [(set (attr "length")
1155 (symbol_ref "compute_logical_op_length (HImode, IOR, operands)"))
1156 (set_attr "cc" "clobber,clobber")])
1159 [(set (match_operand:HI 0 "general_operand" "=r,r,r")
1160 (ior:HI (match_operand:HI 1 "general_operand" "%0,0,0")
1161 (match_operand:HI 2 "general_operand" "J,r,n")))]
1162 "TARGET_H8300H || TARGET_H8300S"
1163 "* return output_logical_op (HImode, IOR, operands);"
1164 [(set (attr "length")
1165 (symbol_ref "compute_logical_op_length (HImode, IOR, operands)"))
1166 (set_attr "cc" "clobber,set_znv,clobber")])
1168 (define_expand "iorsi3"
1169 [(set (match_operand:SI 0 "register_operand" "")
1170 (ior:SI (match_operand:SI 1 "register_operand" "")
1171 (match_operand:SI 2 "nonmemory_operand" "")))]
1176 [(set (match_operand:SI 0 "register_operand" "=r,r")
1177 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1178 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1180 "* return output_logical_op (SImode, IOR, operands);"
1181 [(set (attr "length")
1182 (symbol_ref "compute_logical_op_length (SImode, IOR, operands)"))
1183 (set_attr "cc" "clobber,clobber")])
1186 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1187 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0")
1188 (match_operand:SI 2 "nonmemory_operand" "J,r,n")))]
1189 "TARGET_H8300H || TARGET_H8300S"
1190 "* return output_logical_op (SImode, IOR, operands);"
1191 [(set (attr "length")
1192 (symbol_ref "compute_logical_op_length (SImode, IOR, operands)"))
1193 (set_attr "cc" "clobber,set_znv,clobber")])
1195 ;; ----------------------------------------------------------------------
1197 ;; ----------------------------------------------------------------------
1200 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1201 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1202 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1203 "register_operand (operands[0], QImode)
1204 || (GET_CODE (operands[2]) == CONST_INT
1205 && exact_log2 (INTVAL (operands[2]) & 0xff) != -1)"
1208 switch (which_alternative)
1211 return \"xor\t%X2,%X0\";
1213 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
1214 return \"bnot\t%V2,%R0\";
1219 [(set_attr "length" "2,8")
1220 (set_attr "adjust_length" "no")
1221 (set_attr "cc" "set_znv,none_0hit")])
1223 (define_expand "xorqi3"
1224 [(set (match_operand:QI 0 "bit_operand" "")
1225 (xor:QI (match_operand:QI 1 "bit_operand" "")
1226 (match_operand:QI 2 "nonmemory_operand" "")))]
1230 if (fix_bit_operand (operands, 'O', XOR))
1234 (define_expand "xorhi3"
1235 [(set (match_operand:HI 0 "register_operand" "")
1236 (xor:HI (match_operand:HI 1 "register_operand" "")
1237 (match_operand:HI 2 "nonmemory_operand" "")))]
1242 [(set (match_operand:HI 0 "register_operand" "=r,r")
1243 (xor:HI (match_operand:HI 1 "register_operand" "%0,0")
1244 (match_operand:HI 2 "nonmemory_operand" "J,rn")))]
1246 "* return output_logical_op (HImode, XOR, operands);"
1247 [(set (attr "length")
1248 (symbol_ref "compute_logical_op_length (HImode, XOR, operands)"))
1249 (set_attr "cc" "clobber,clobber")])
1252 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1253 (xor:HI (match_operand:HI 1 "register_operand" "%0,0,0")
1254 (match_operand:HI 2 "nonmemory_operand" "J,r,n")))]
1255 "TARGET_H8300H || TARGET_H8300S"
1256 "* return output_logical_op (HImode, XOR, operands);"
1257 [(set (attr "length")
1258 (symbol_ref "compute_logical_op_length (HImode, XOR, operands)"))
1259 (set_attr "cc" "clobber,set_znv,clobber")])
1261 (define_expand "xorsi3"
1262 [(set (match_operand:SI 0 "register_operand" "")
1263 (xor:SI (match_operand:SI 1 "register_operand" "")
1264 (match_operand:SI 2 "nonmemory_operand" "")))]
1269 [(set (match_operand:SI 0 "register_operand" "=r,r")
1270 (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
1271 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1273 "* return output_logical_op (SImode, XOR, operands);"
1274 [(set (attr "length")
1275 (symbol_ref "compute_logical_op_length (SImode, XOR, operands)"))
1276 (set_attr "cc" "clobber,clobber")])
1279 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1280 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0")
1281 (match_operand:SI 2 "nonmemory_operand" "J,r,n")))]
1282 "TARGET_H8300H || TARGET_H8300S"
1283 "* return output_logical_op (SImode, XOR, operands);"
1284 [(set (attr "length")
1285 (symbol_ref "compute_logical_op_length (SImode, XOR, operands)"))
1286 (set_attr "cc" "clobber,set_znv,clobber")])
1288 ;; ----------------------------------------------------------------------
1289 ;; NEGATION INSTRUCTIONS
1290 ;; ----------------------------------------------------------------------
1292 (define_insn "negqi2"
1293 [(set (match_operand:QI 0 "register_operand" "=r")
1294 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1297 [(set_attr "length" "2")
1298 (set_attr "cc" "set_zn")])
1300 (define_expand "neghi2"
1301 [(set (match_operand:HI 0 "register_operand" "")
1302 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1308 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1313 (define_expand "neghi2_h8300"
1315 (not:HI (match_operand:HI 1 "register_operand" "")))
1316 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1317 (set (match_operand:HI 0 "register_operand" "")
1320 "operands[2] = gen_reg_rtx (HImode);")
1322 (define_insn "neghi2_h8300h"
1323 [(set (match_operand:HI 0 "register_operand" "=r")
1324 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1325 "TARGET_H8300H || TARGET_H8300S"
1327 [(set_attr "length" "2")
1328 (set_attr "cc" "set_zn")])
1330 (define_expand "negsi2"
1331 [(set (match_operand:SI 0 "register_operand" "")
1332 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1338 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1343 (define_expand "negsi2_h8300"
1345 (not:SI (match_operand:SI 1 "register_operand" "")))
1346 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1347 (set (match_operand:SI 0 "register_operand" "")
1350 "operands[2] = gen_reg_rtx (SImode);")
1352 (define_insn "negsi2_h8300h"
1353 [(set (match_operand:SI 0 "register_operand" "=r")
1354 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1355 "TARGET_H8300H || TARGET_H8300S"
1357 [(set_attr "length" "2")
1358 (set_attr "cc" "set_zn")])
1360 ;; ----------------------------------------------------------------------
1362 ;; ----------------------------------------------------------------------
1364 (define_insn "one_cmplqi2"
1365 [(set (match_operand:QI 0 "register_operand" "=r")
1366 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1369 [(set_attr "length" "2")
1370 (set_attr "cc" "set_znv")])
1372 (define_expand "one_cmplhi2"
1373 [(set (match_operand:HI 0 "register_operand" "=r")
1374 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1379 [(set (match_operand:HI 0 "register_operand" "=r")
1380 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1383 [(set_attr "cc" "clobber")
1384 (set_attr "length" "4")])
1387 [(set (match_operand:HI 0 "register_operand" "=r")
1388 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1389 "TARGET_H8300H || TARGET_H8300S"
1391 [(set_attr "cc" "set_znv")
1392 (set_attr "length" "2")])
1394 (define_expand "one_cmplsi2"
1395 [(set (match_operand:SI 0 "register_operand" "=r")
1396 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1401 [(set (match_operand:SI 0 "register_operand" "=r")
1402 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1404 "not %w0\;not %x0\;not %y0\;not %z0"
1405 [(set_attr "cc" "clobber")
1406 (set_attr "length" "8")])
1409 [(set (match_operand:SI 0 "register_operand" "=r")
1410 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1411 "TARGET_H8300H || TARGET_H8300S"
1413 [(set_attr "cc" "set_znv")
1414 (set_attr "length" "2")])
1416 ;; ----------------------------------------------------------------------
1417 ;; JUMP INSTRUCTIONS
1418 ;; ----------------------------------------------------------------------
1420 ;; Conditional jump instructions
1422 (define_expand "ble"
1424 (if_then_else (le (cc0)
1426 (label_ref (match_operand 0 "" ""))
1431 (define_expand "bleu"
1433 (if_then_else (leu (cc0)
1435 (label_ref (match_operand 0 "" ""))
1440 (define_expand "bge"
1442 (if_then_else (ge (cc0)
1444 (label_ref (match_operand 0 "" ""))
1449 (define_expand "bgeu"
1451 (if_then_else (geu (cc0)
1453 (label_ref (match_operand 0 "" ""))
1458 (define_expand "blt"
1460 (if_then_else (lt (cc0)
1462 (label_ref (match_operand 0 "" ""))
1467 (define_expand "bltu"
1469 (if_then_else (ltu (cc0)
1471 (label_ref (match_operand 0 "" ""))
1476 (define_expand "bgt"
1478 (if_then_else (gt (cc0)
1480 (label_ref (match_operand 0 "" ""))
1485 (define_expand "bgtu"
1487 (if_then_else (gtu (cc0)
1489 (label_ref (match_operand 0 "" ""))
1494 (define_expand "beq"
1496 (if_then_else (eq (cc0)
1498 (label_ref (match_operand 0 "" ""))
1503 (define_expand "bne"
1505 (if_then_else (ne (cc0)
1507 (label_ref (match_operand 0 "" ""))
1512 (define_insn "branch_true"
1514 (if_then_else (match_operator 1 "comparison_operator"
1515 [(cc0) (const_int 0)])
1516 (label_ref (match_operand 0 "" ""))
1521 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1522 && (GET_CODE (operands[1]) == GT
1523 || GET_CODE (operands[1]) == GE
1524 || GET_CODE (operands[1]) == LE
1525 || GET_CODE (operands[1]) == LT))
1527 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1531 if (get_attr_length (insn) == 2)
1532 return \"b%j1 %l0\";
1533 else if (get_attr_length (insn) == 4)
1534 return \"b%j1 %l0:16\";
1536 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1538 [(set_attr "type" "branch")
1539 (set_attr "cc" "none")])
1541 (define_insn "branch_false"
1543 (if_then_else (match_operator 1 "comparison_operator"
1544 [(cc0) (const_int 0)])
1546 (label_ref (match_operand 0 "" ""))))]
1550 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1551 && (GET_CODE (operands[1]) == GT
1552 || GET_CODE (operands[1]) == GE
1553 || GET_CODE (operands[1]) == LE
1554 || GET_CODE (operands[1]) == LT))
1556 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1560 if (get_attr_length (insn) == 2)
1561 return \"b%k1 %l0\";
1562 else if (get_attr_length (insn) == 4)
1563 return \"b%k1 %l0:16\";
1565 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1567 [(set_attr "type" "branch")
1568 (set_attr "cc" "none")])
1570 ;; Unconditional and other jump instructions.
1574 (label_ref (match_operand 0 "" "")))]
1578 if (get_attr_length (insn) == 2)
1580 else if (get_attr_length (insn) == 4)
1581 return \"bra %l0:16\";
1583 return \"jmp @%l0\";
1585 [(set_attr "type" "branch")
1586 (set_attr "cc" "none")])
1588 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1590 (define_expand "tablejump"
1591 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1592 (use (label_ref (match_operand 1 "" "")))])]
1596 (define_insn "tablejump_h8300"
1597 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1598 (use (label_ref (match_operand 1 "" "")))]
1601 [(set_attr "cc" "none")
1602 (set_attr "length" "2")])
1604 (define_insn "tablejump_h8300h"
1605 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1606 (use (label_ref (match_operand 1 "" "")))]
1607 "TARGET_H8300H || TARGET_H8300S"
1609 [(set_attr "cc" "none")
1610 (set_attr "length" "2")])
1612 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1614 (define_expand "indirect_jump"
1615 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1619 (define_insn "indirect_jump_h8300"
1620 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1623 [(set_attr "cc" "none")
1624 (set_attr "length" "2")])
1626 (define_insn "indirect_jump_h8300h"
1627 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1628 "TARGET_H8300H || TARGET_H8300S"
1630 [(set_attr "cc" "none")
1631 (set_attr "length" "2")])
1633 ;; Call subroutine with no return value.
1635 ;; ??? Even though we use HImode here, this works on the H8/300H and H8/S.
1638 [(call (match_operand:QI 0 "call_insn_operand" "or")
1639 (match_operand:HI 1 "general_operand" "g"))]
1643 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1644 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1645 return \"jsr\\t@%0:8\";
1647 return \"jsr\\t%0\";
1649 [(set_attr "cc" "clobber")
1650 (set (attr "length")
1651 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1655 ;; Call subroutine, returning value in operand 0
1656 ;; (which must be a hard register).
1658 ;; ??? Even though we use HImode here, this works on the H8/300H and H8/S.
1660 (define_insn "call_value"
1661 [(set (match_operand 0 "" "=r")
1662 (call (match_operand:QI 1 "call_insn_operand" "or")
1663 (match_operand:HI 2 "general_operand" "g")))]
1667 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1668 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1669 return \"jsr\\t@%1:8\";
1671 return \"jsr\\t%1\";
1673 [(set_attr "cc" "clobber")
1674 (set (attr "length")
1675 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1683 [(set_attr "cc" "none")
1684 (set_attr "length" "2")])
1686 ;; ----------------------------------------------------------------------
1687 ;; EXTEND INSTRUCTIONS
1688 ;; ----------------------------------------------------------------------
1690 (define_expand "zero_extendqihi2"
1691 [(set (match_operand:HI 0 "register_operand" "")
1692 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
1697 [(set (match_operand:HI 0 "register_operand" "=r,r")
1698 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1702 mov.b %R1,%s0\;mov.b #0,%t0"
1703 [(set_attr "length" "2,10")
1704 (set_attr "cc" "clobber,clobber")])
1707 [(set (match_operand:HI 0 "register_operand" "=r,r")
1708 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1709 "TARGET_H8300H || TARGET_H8300S"
1712 mov.b %R1,%s0\;extu.w %T0"
1713 [(set_attr "length" "2,10")
1714 (set_attr "cc" "set_znv,set_znv")])
1716 ;; The compiler can synthesize a 300H variant of this which is
1717 ;; just as efficient as one that we'd create
1718 (define_insn "zero_extendqisi2"
1719 [(set (match_operand:SI 0 "register_operand" "=r,r")
1720 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1723 mov.b #0,%x0\;sub.w %e0,%e0
1724 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
1725 [(set_attr "length" "4,6")
1726 (set_attr "cc" "clobber,clobber")])
1728 (define_expand "zero_extendhisi2"
1729 [(set (match_operand:SI 0 "register_operand" "")
1730 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1734 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
1736 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1737 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
1741 mov.w %f1,%f0\;sub.w %e0,%e0
1742 mov.w %e1,%f0\;sub.w %e0,%e0"
1743 [(set_attr "length" "2,4,4")
1744 (set_attr "cc" "clobber,clobber,clobber")])
1747 [(set (match_operand:SI 0 "register_operand" "=r")
1748 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1749 "TARGET_H8300H || TARGET_H8300S"
1751 [(set_attr "length" "2")
1752 (set_attr "cc" "set_znv")])
1754 (define_expand "extendqihi2"
1755 [(set (match_operand:HI 0 "register_operand" "")
1756 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
1761 [(set (match_operand:HI 0 "register_operand" "=r,r")
1762 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1765 bld #7,%s0\;subx %t0,%t0
1766 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
1767 [(set_attr "length" "4,8")
1768 (set_attr "cc" "clobber,clobber")])
1771 [(set (match_operand:HI 0 "register_operand" "=r")
1772 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
1773 "TARGET_H8300H || TARGET_H8300S"
1775 [(set_attr "length" "2")
1776 (set_attr "cc" "set_znv")])
1778 ;; The compiler can synthesize a 300H variant of this which is
1779 ;; just as efficient as one that we'd create
1780 (define_insn "extendqisi2"
1781 [(set (match_operand:SI 0 "register_operand" "=r,r")
1782 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1785 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
1786 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
1787 [(set_attr "length" "8,10")
1788 (set_attr "cc" "clobber,clobber")])
1790 (define_expand "extendhisi2"
1791 [(set (match_operand:SI 0 "register_operand" "")
1792 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
1797 [(set (match_operand:SI 0 "register_operand" "=r,r")
1798 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1801 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
1802 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
1803 [(set_attr "length" "6,8")
1804 (set_attr "cc" "clobber,clobber")])
1807 [(set (match_operand:SI 0 "register_operand" "=r")
1808 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1809 "TARGET_H8300H || TARGET_H8300S"
1811 [(set_attr "length" "2")
1812 (set_attr "cc" "set_znv")])
1814 ;; ----------------------------------------------------------------------
1816 ;; ----------------------------------------------------------------------
1818 ;; We make some attempt to provide real efficient shifting. One example is
1819 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
1820 ;; reg and moving 0 into the former reg.
1822 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
1823 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
1824 ;; give the optimizer more cracks at the code. However, we wish to do things
1825 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1826 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
1827 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
1828 ;; to detect cases it can optimize.
1830 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
1831 ;; easier "do it at insn emit time" route.
1835 (define_expand "ashlqi3"
1836 [(set (match_operand:QI 0 "register_operand" "")
1837 (ashift:QI (match_operand:QI 1 "register_operand" "")
1838 (match_operand:QI 2 "nonmemory_operand" "")))]
1840 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE; else FAIL;")
1842 (define_expand "ashrqi3"
1843 [(set (match_operand:QI 0 "register_operand" "")
1844 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
1845 (match_operand:QI 2 "nonmemory_operand" "")))]
1847 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE; else FAIL;")
1849 (define_expand "lshrqi3"
1850 [(set (match_operand:QI 0 "register_operand" "")
1851 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1852 (match_operand:QI 2 "nonmemory_operand" "")))]
1854 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE; else FAIL;")
1857 [(set (match_operand:QI 0 "register_operand" "=r,r")
1858 (match_operator:QI 3 "nshift_operator"
1859 [ (match_operand:QI 1 "register_operand" "0,0")
1860 (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
1861 (clobber (match_scratch:QI 4 "=X,&r"))]
1863 "* return output_a_shift (operands);"
1864 [(set_attr "length" "20")
1865 (set_attr "cc" "clobber")])
1869 (define_expand "ashlhi3"
1870 [(set (match_operand:HI 0 "register_operand" "")
1871 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
1872 (match_operand:QI 2 "nonmemory_operand" "")))]
1874 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE; else FAIL;")
1876 (define_expand "lshrhi3"
1877 [(set (match_operand:HI 0 "register_operand" "")
1878 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
1879 (match_operand:QI 2 "nonmemory_operand" "")))]
1881 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE; else FAIL;")
1883 (define_expand "ashrhi3"
1884 [(set (match_operand:HI 0 "register_operand" "")
1885 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1886 (match_operand:QI 2 "nonmemory_operand" "")))]
1888 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE; else FAIL;")
1891 [(set (match_operand:HI 0 "register_operand" "=r,r")
1892 (match_operator:HI 3 "nshift_operator"
1893 [ (match_operand:HI 1 "register_operand" "0,0")
1894 (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
1895 (clobber (match_scratch:QI 4 "=X,&r"))]
1897 "* return output_a_shift (operands);"
1898 [(set_attr "length" "20")
1899 (set_attr "cc" "clobber")])
1903 (define_expand "ashlsi3"
1904 [(set (match_operand:SI 0 "register_operand" "")
1905 (ashift:SI (match_operand:SI 1 "general_operand" "")
1906 (match_operand:QI 2 "nonmemory_operand" "")))]
1908 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE; else FAIL;")
1910 (define_expand "lshrsi3"
1911 [(set (match_operand:SI 0 "register_operand" "")
1912 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
1913 (match_operand:QI 2 "nonmemory_operand" "")))]
1915 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE; else FAIL;")
1917 (define_expand "ashrsi3"
1918 [(set (match_operand:SI 0 "register_operand" "")
1919 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
1920 (match_operand:QI 2 "nonmemory_operand" "")))]
1922 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE; else FAIL;")
1925 [(set (match_operand:SI 0 "register_operand" "=r,r")
1926 (match_operator:SI 3 "nshift_operator"
1927 [ (match_operand:SI 1 "register_operand" "0,0")
1928 (match_operand:QI 2 "nonmemory_operand" "K,rn")]))
1929 (clobber (match_scratch:QI 4 "=X,&r"))]
1931 "* return output_a_shift (operands);"
1932 [(set_attr "length" "20")
1933 (set_attr "cc" "clobber")])
1935 ;; ----------------------------------------------------------------------
1937 ;; ----------------------------------------------------------------------
1939 (define_expand "rotlqi3"
1940 [(set (match_operand:QI 0 "register_operand" "")
1941 (rotate:QI (match_operand:QI 1 "register_operand" "")
1942 (match_operand:QI 2 "nonmemory_operand" "")))]
1944 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
1946 (define_insn "*rotlqi3_1"
1947 [(set (match_operand:QI 0 "register_operand" "=r")
1948 (rotate:QI (match_operand:QI 1 "register_operand" "0")
1949 (match_operand:QI 2 "immediate_operand" "")))]
1951 "* return emit_a_rotate (ROTATE, operands);"
1952 [(set_attr "length" "20")
1953 (set_attr "cc" "clobber")])
1955 (define_expand "rotlhi3"
1956 [(set (match_operand:HI 0 "register_operand" "")
1957 (rotate:HI (match_operand:HI 1 "register_operand" "")
1958 (match_operand:QI 2 "nonmemory_operand" "")))]
1960 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
1962 (define_insn "*rotlhi3_1"
1963 [(set (match_operand:HI 0 "register_operand" "=r")
1964 (rotate:HI (match_operand:HI 1 "register_operand" "0")
1965 (match_operand:QI 2 "immediate_operand" "")))]
1967 "* return emit_a_rotate (ROTATE, operands);"
1968 [(set_attr "length" "20")
1969 (set_attr "cc" "clobber")])
1971 (define_expand "rotlsi3"
1972 [(set (match_operand:SI 0 "register_operand" "")
1973 (rotate:SI (match_operand:SI 1 "register_operand" "")
1974 (match_operand:QI 2 "nonmemory_operand" "")))]
1975 "TARGET_H8300H || TARGET_H8300S"
1976 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
1978 (define_insn "*rotlsi3_1"
1979 [(set (match_operand:SI 0 "register_operand" "=r")
1980 (rotate:SI (match_operand:SI 1 "register_operand" "0")
1981 (match_operand:QI 2 "immediate_operand" "")))]
1982 "TARGET_H8300H || TARGET_H8300S"
1983 "* return emit_a_rotate (ROTATE, operands);"
1984 [(set_attr "length" "20")
1985 (set_attr "cc" "clobber")])
1987 ;; -----------------------------------------------------------------
1989 ;; -----------------------------------------------------------------
1990 ;; The H8/300 has given 1/8th of its opcode space to bitfield
1991 ;; instructions so let's use them as well as we can.
1993 ;; You'll never believe all these patterns perform one basic action --
1994 ;; load a bit from the source, optionally invert the bit, then store it
1995 ;; in the destination (which is known to be zero).
1997 ;; Combine obviously need some work to better identify this situation and
1998 ;; canonicalize the form better.
2001 ;; Normal loads with a 16bit destination.
2005 [(set (match_operand:HI 0 "register_operand" "=&r")
2006 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2008 (match_operand:HI 2 "immediate_operand" "n")))]
2010 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2011 [(set_attr "cc" "clobber")
2012 (set_attr "length" "6")])
2015 ;; Inverted loads with a 16bit destination.
2019 [(set (match_operand:HI 0 "register_operand" "=&r")
2020 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2021 (match_operand:HI 3 "const_int_operand" "n"))
2023 (match_operand:HI 2 "const_int_operand" "n")))]
2025 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2026 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2027 [(set_attr "cc" "clobber")
2028 (set_attr "length" "8")])
2031 ;; Normal loads with a 32bit destination.
2035 [(set (match_operand:SI 0 "register_operand" "=&r")
2036 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2038 (match_operand 2 "const_int_operand" "n")))]
2040 && INTVAL (operands[2]) < 16"
2041 "* return output_simode_bld (0, operands);"
2042 [(set_attr "cc" "clobber")
2043 (set_attr "length" "6")])
2046 [(set (match_operand:SI 0 "register_operand" "=r")
2047 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2049 (match_operand 2 "const_int_operand" "n")))]
2050 "(TARGET_H8300H || TARGET_H8300S)
2051 && INTVAL (operands[2]) < 16"
2052 "* return output_simode_bld (0, operands);"
2053 [(set_attr "cc" "clobber")
2054 (set_attr "length" "6")])
2057 ;; Inverted loads with a 32bit destination.
2061 [(set (match_operand:SI 0 "register_operand" "=&r")
2062 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2063 (match_operand:HI 3 "const_int_operand" "n"))
2065 (match_operand 2 "const_int_operand" "n")))]
2067 && INTVAL (operands[2]) < 16
2068 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2069 "* return output_simode_bld (1, operands);"
2070 [(set_attr "cc" "clobber")
2071 (set_attr "length" "6")])
2074 [(set (match_operand:SI 0 "register_operand" "=r")
2075 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
2076 (match_operand 3 "const_int_operand" "n"))
2078 (match_operand 2 "const_int_operand" "n")))]
2079 "(TARGET_H8300H || TARGET_H8300S)
2080 && INTVAL (operands[2]) < 16
2081 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2082 "* return output_simode_bld (1, operands);"
2083 [(set_attr "cc" "clobber")
2084 (set_attr "length" "6")])
2086 (define_expand "insv"
2087 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2088 (match_operand:HI 1 "general_operand" "")
2089 (match_operand:HI 2 "general_operand" ""))
2090 (match_operand:HI 3 "general_operand" ""))]
2094 /* We only have single bit bitfield instructions. */
2095 if (INTVAL (operands[1]) != 1)
2098 /* For now, we don't allow memory operands. */
2099 if (GET_CODE (operands[0]) == MEM
2100 || GET_CODE (operands[3]) == MEM)
2105 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2107 (match_operand:HI 1 "immediate_operand" "n"))
2108 (match_operand:HI 2 "register_operand" "r"))]
2110 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2111 [(set_attr "cc" "clobber")
2112 (set_attr "length" "4")])
2114 (define_expand "extzv"
2115 [(set (match_operand:HI 0 "register_operand" "")
2116 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2117 (match_operand:HI 2 "general_operand" "")
2118 (match_operand:HI 3 "general_operand" "")))]
2122 /* We only have single bit bitfield instructions. */
2123 if (INTVAL (operands[2]) != 1)
2126 /* For now, we don't allow memory operands. */
2127 if (GET_CODE (operands[1]) == MEM)
2131 ;; BAND, BOR, and BXOR patterns
2134 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2135 (match_operator:HI 4 "bit_operator"
2136 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2138 (match_operand:HI 2 "immediate_operand" "n"))
2139 (match_operand:HI 3 "bit_operand" "0")]))]
2141 "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1"
2142 [(set_attr "cc" "clobber")
2143 (set_attr "length" "6")
2144 (set_attr "adjust_length" "no")])
2147 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2148 (match_operator:HI 5 "bit_operator"
2149 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2151 (match_operand:HI 2 "immediate_operand" "n"))
2152 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2154 (match_operand:HI 4 "immediate_operand" "n"))]))]
2156 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3"
2157 [(set_attr "cc" "clobber")
2158 (set_attr "length" "6")
2159 (set_attr "adjust_length" "no")])
2161 ;; -----------------------------------------------------------------
2163 ;; -----------------------------------------------------------------
2166 [(set (match_operand:HI 0 "register_operand" "=r")
2167 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2168 (match_operand:HI 2 "register_operand" "0")))]
2169 "REG_P (operands[0])
2170 && REG_P (operands[1])
2171 && REGNO (operands[0]) != REGNO (operands[1])"
2173 [(set_attr "cc" "clobber")
2174 (set_attr "length" "2")])
2177 [(set (match_operand:SI 0 "register_operand" "=r")
2178 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2179 (match_operand:SI 2 "register_operand" "0")))]
2180 "(TARGET_H8300H || TARGET_H8300S)
2181 && REG_P (operands[0])
2182 && REG_P (operands[1])
2183 && (REGNO (operands[0]) != REGNO (operands[1]))"
2185 [(set_attr "cc" "clobber")
2186 (set_attr "length" "2")])
2189 [(set (match_operand:SI 0 "register_operand" "=r")
2190 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2191 (match_operand:SI 2 "register_operand" "0")))]
2192 "REG_P (operands[0])
2193 && REG_P (operands[1])
2194 && REGNO (operands[0]) != REGNO (operands[1])"
2196 [(set_attr "cc" "clobber")
2197 (set_attr "length" "2")])
2200 [(set (match_operand:HI 0 "register_operand" "=r")
2201 (xor:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2202 (match_operand:HI 2 "register_operand" "0")))]
2203 "REG_P (operands[0])
2204 && REG_P (operands[1])
2205 && REGNO (operands[0]) != REGNO (operands[1])"
2207 [(set_attr "cc" "clobber")
2208 (set_attr "length" "2")])
2211 [(set (match_operand:SI 0 "register_operand" "=r")
2212 (xor:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2213 (match_operand:SI 2 "register_operand" "0")))]
2214 "(TARGET_H8300H || TARGET_H8300S)
2215 && REG_P (operands[0])
2216 && REG_P (operands[1])
2217 && (REGNO (operands[0]) != REGNO (operands[1]))"
2219 [(set_attr "cc" "clobber")
2220 (set_attr "length" "2")])
2223 [(set (match_operand:SI 0 "register_operand" "=r")
2224 (xor:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2225 (match_operand:SI 2 "register_operand" "0")))]
2226 "REG_P (operands[0])
2227 && REG_P (operands[1])
2228 && REGNO (operands[0]) != REGNO (operands[1])"
2230 [(set_attr "cc" "clobber")
2231 (set_attr "length" "2")])
2234 [(set (match_operand:HI 0 "register_operand" "=r")
2235 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
2236 (ashift:HI (match_operand:HI 2 "register_operand" "r")
2238 "REG_P (operands[0])
2239 && REG_P (operands[2])
2240 && REGNO (operands[0]) != REGNO (operands[2])"
2242 [(set_attr "cc" "clobber")
2243 (set_attr "length" "2")])
2246 [(set (match_operand:SI 0 "register_operand" "=r")
2247 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
2248 (ashift:SI (match_operand:SI 2 "register_operand" "r")
2250 "(TARGET_H8300H || TARGET_H8300S)
2251 && REG_P (operands[0])
2252 && REG_P (operands[2])
2253 && (REGNO (operands[0]) != REGNO (operands[2]))"
2255 [(set_attr "cc" "clobber")
2256 (set_attr "length" "2")])