1 @c Copyright (C) 1988-2018 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Overview:: How the machine description is used.
23 * Patterns:: How to write instruction patterns.
24 * Example:: An explained example of a @code{define_insn} pattern.
25 * RTL Template:: The RTL template defines what insns match a pattern.
26 * Output Template:: The output template says how to make assembler code
28 * Output Statement:: For more generality, write C code to output
30 * Predicates:: Controlling what kinds of operands can be used
32 * Constraints:: Fine-tuning operand selection.
33 * Standard Names:: Names mark patterns to use for code generation.
34 * Pattern Ordering:: When the order of patterns makes a difference.
35 * Dependent Patterns:: Having one pattern may make you need another.
36 * Jump Patterns:: Special considerations for patterns for jump insns.
37 * Looping Patterns:: How to define patterns for special looping insns.
38 * Insn Canonicalizations::Canonicalization of Instructions
39 * Expander Definitions::Generating a sequence of several RTL insns
40 for a standard operation.
41 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
42 * Including Patterns:: Including Patterns in Machine Descriptions.
43 * Peephole Definitions::Defining machine-specific peephole optimizations.
44 * Insn Attributes:: Specifying the value of attributes for generated insns.
45 * Conditional Execution::Generating @code{define_insn} patterns for
47 * Define Subst:: Generating @code{define_insn} and @code{define_expand}
48 patterns from other patterns.
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 A @code{define_insn} expression is used to define instruction patterns
109 to which insns may be matched. A @code{define_insn} expression contains
110 an incomplete RTL expression, with pieces to be filled in later, operand
111 constraints that restrict how the pieces can be filled in, and an output
112 template or C code to generate the assembler output.
114 A @code{define_insn} is an RTL expression containing four or five operands:
118 An optional name @var{n}. When a name is present, the compiler
119 automically generates a C++ function @samp{gen_@var{n}} that takes
120 the operands of the instruction as arguments and returns the instruction's
121 rtx pattern. The compiler also assigns the instruction a unique code
122 @samp{CODE_FOR_@var{n}}, with all such codes belonging to an enum
123 called @code{insn_code}.
125 These names serve one of two purposes. The first is to indicate that the
126 instruction performs a certain standard job for the RTL-generation
127 pass of the compiler, such as a move, an addition, or a conditional
128 jump. The second is to help the target generate certain target-specific
129 operations, such as when implementing target-specific intrinsic functions.
131 It is better to prefix target-specific names with the name of the
132 target, to avoid any clash with current or future standard names.
134 The absence of a name is indicated by writing an empty string
135 where the name should go. Nameless instruction patterns are never
136 used for generating RTL code, but they may permit several simpler insns
137 to be combined later on.
139 For the purpose of debugging the compiler, you may also specify a
140 name beginning with the @samp{*} character. Such a name is used only
141 for identifying the instruction in RTL dumps; it is equivalent to having
142 a nameless pattern for all other purposes. Names beginning with the
143 @samp{*} character are not required to be unique.
145 The name may also have the form @samp{@@@var{n}}. This has the same
146 effect as a name @samp{@var{n}}, but in addition tells the compiler to
147 generate further helper functions; see @ref{Parameterized Names} for details.
150 The @dfn{RTL template}: This is a vector of incomplete RTL expressions
151 which describe the semantics of the instruction (@pxref{RTL Template}).
152 It is incomplete because it may contain @code{match_operand},
153 @code{match_operator}, and @code{match_dup} expressions that stand for
154 operands of the instruction.
156 If the vector has multiple elements, the RTL template is treated as a
157 @code{parallel} expression.
160 @cindex pattern conditions
161 @cindex conditions, in patterns
162 The condition: This is a string which contains a C expression. When the
163 compiler attempts to match RTL against a pattern, the condition is
164 evaluated. If the condition evaluates to @code{true}, the match is
165 permitted. The condition may be an empty string, which is treated
166 as always @code{true}.
168 @cindex named patterns and conditions
169 For a named pattern, the condition may not depend on the data in the
170 insn being matched, but only the target-machine-type flags. The compiler
171 needs to test these conditions during initialization in order to learn
172 exactly which named instructions are available in a particular run.
175 For nameless patterns, the condition is applied only when matching an
176 individual insn, and only after the insn has matched the pattern's
177 recognition template. The insn's operands may be found in the vector
180 An instruction condition cannot become more restrictive as compilation
181 progresses. If the condition accepts a particular RTL instruction at
182 one stage of compilation, it must continue to accept that instruction
183 until the final pass. For example, @samp{!reload_completed} and
184 @samp{can_create_pseudo_p ()} are both invalid instruction conditions,
185 because they are true during the earlier RTL passes and false during
186 the later ones. For the same reason, if a condition accepts an
187 instruction before register allocation, it cannot later try to control
188 register allocation by excluding certain register or value combinations.
190 Although a condition cannot become more restrictive as compilation
191 progresses, the condition for a nameless pattern @emph{can} become
192 more permissive. For example, a nameless instruction can require
193 @samp{reload_completed} to be true, in which case it only matches
194 after register allocation.
197 The @dfn{output template} or @dfn{output statement}: This is either
198 a string, or a fragment of C code which returns a string.
200 When simple substitution isn't general enough, you can specify a piece
201 of C code to compute the output. @xref{Output Statement}.
204 The @dfn{insn attributes}: This is an optional vector containing the values of
205 attributes for insns matching this pattern (@pxref{Insn Attributes}).
209 @section Example of @code{define_insn}
210 @cindex @code{define_insn} example
212 Here is an example of an instruction pattern, taken from the machine
213 description for the 68000/68020.
218 (match_operand:SI 0 "general_operand" "rm"))]
222 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
224 return \"cmpl #0,%0\";
229 This can also be written using braced strings:
234 (match_operand:SI 0 "general_operand" "rm"))]
237 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
243 This describes an instruction which sets the condition codes based on the
244 value of a general operand. It has no condition, so any insn with an RTL
245 description of the form shown may be matched to this pattern. The name
246 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL
247 generation pass that, when it is necessary to test such a value, an insn
248 to do so can be constructed using this pattern.
250 The output control string is a piece of C code which chooses which
251 output template to return based on the kind of operand and the specific
252 type of CPU for which code is being generated.
254 @samp{"rm"} is an operand constraint. Its meaning is explained below.
257 @section RTL Template
258 @cindex RTL insn template
259 @cindex generating insns
260 @cindex insns, generating
261 @cindex recognizing insns
262 @cindex insns, recognizing
264 The RTL template is used to define which insns match the particular pattern
265 and how to find their operands. For named patterns, the RTL template also
266 says how to construct an insn from specified operands.
268 Construction involves substituting specified operands into a copy of the
269 template. Matching involves determining the values that serve as the
270 operands in the insn being matched. Both of these activities are
271 controlled by special expression types that direct matching and
272 substitution of the operands.
275 @findex match_operand
276 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
277 This expression is a placeholder for operand number @var{n} of
278 the insn. When constructing an insn, operand number @var{n}
279 will be substituted at this point. When matching an insn, whatever
280 appears at this position in the insn will be taken as operand
281 number @var{n}; but it must satisfy @var{predicate} or this instruction
282 pattern will not match at all.
284 Operand numbers must be chosen consecutively counting from zero in
285 each instruction pattern. There may be only one @code{match_operand}
286 expression in the pattern for each operand number. Usually operands
287 are numbered in the order of appearance in @code{match_operand}
288 expressions. In the case of a @code{define_expand}, any operand numbers
289 used only in @code{match_dup} expressions have higher values than all
290 other operand numbers.
292 @var{predicate} is a string that is the name of a function that
293 accepts two arguments, an expression and a machine mode.
294 @xref{Predicates}. During matching, the function will be called with
295 the putative operand as the expression and @var{m} as the mode
296 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
297 which normally causes @var{predicate} to accept any mode). If it
298 returns zero, this instruction pattern fails to match.
299 @var{predicate} may be an empty string; then it means no test is to be
300 done on the operand, so anything which occurs in this position is
303 Most of the time, @var{predicate} will reject modes other than @var{m}---but
304 not always. For example, the predicate @code{address_operand} uses
305 @var{m} as the mode of memory ref that the address should be valid for.
306 Many predicates accept @code{const_int} nodes even though their mode is
309 @var{constraint} controls reloading and the choice of the best register
310 class to use for a value, as explained later (@pxref{Constraints}).
311 If the constraint would be an empty string, it can be omitted.
313 People are often unclear on the difference between the constraint and the
314 predicate. The predicate helps decide whether a given insn matches the
315 pattern. The constraint plays no role in this decision; instead, it
316 controls various decisions in the case of an insn which does match.
318 @findex match_scratch
319 @item (match_scratch:@var{m} @var{n} @var{constraint})
320 This expression is also a placeholder for operand number @var{n}
321 and indicates that operand must be a @code{scratch} or @code{reg}
324 When matching patterns, this is equivalent to
327 (match_operand:@var{m} @var{n} "scratch_operand" @var{constraint})
330 but, when generating RTL, it produces a (@code{scratch}:@var{m})
333 If the last few expressions in a @code{parallel} are @code{clobber}
334 expressions whose operands are either a hard register or
335 @code{match_scratch}, the combiner can add or delete them when
336 necessary. @xref{Side Effects}.
339 @item (match_dup @var{n})
340 This expression is also a placeholder for operand number @var{n}.
341 It is used when the operand needs to appear more than once in the
344 In construction, @code{match_dup} acts just like @code{match_operand}:
345 the operand is substituted into the insn being constructed. But in
346 matching, @code{match_dup} behaves differently. It assumes that operand
347 number @var{n} has already been determined by a @code{match_operand}
348 appearing earlier in the recognition template, and it matches only an
349 identical-looking expression.
351 Note that @code{match_dup} should not be used to tell the compiler that
352 a particular register is being used for two operands (example:
353 @code{add} that adds one register to another; the second register is
354 both an input operand and the output operand). Use a matching
355 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
356 operand is used in two places in the template, such as an instruction
357 that computes both a quotient and a remainder, where the opcode takes
358 two input operands but the RTL template has to refer to each of those
359 twice; once for the quotient pattern and once for the remainder pattern.
361 @findex match_operator
362 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
363 This pattern is a kind of placeholder for a variable RTL expression
366 When constructing an insn, it stands for an RTL expression whose
367 expression code is taken from that of operand @var{n}, and whose
368 operands are constructed from the patterns @var{operands}.
370 When matching an expression, it matches an expression if the function
371 @var{predicate} returns nonzero on that expression @emph{and} the
372 patterns @var{operands} match the operands of the expression.
374 Suppose that the function @code{commutative_operator} is defined as
375 follows, to match any expression whose operator is one of the
376 commutative arithmetic operators of RTL and whose mode is @var{mode}:
380 commutative_integer_operator (x, mode)
384 enum rtx_code code = GET_CODE (x);
385 if (GET_MODE (x) != mode)
387 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
388 || code == EQ || code == NE);
392 Then the following pattern will match any RTL expression consisting
393 of a commutative operator applied to two general operands:
396 (match_operator:SI 3 "commutative_operator"
397 [(match_operand:SI 1 "general_operand" "g")
398 (match_operand:SI 2 "general_operand" "g")])
401 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
402 because the expressions to be matched all contain two operands.
404 When this pattern does match, the two operands of the commutative
405 operator are recorded as operands 1 and 2 of the insn. (This is done
406 by the two instances of @code{match_operand}.) Operand 3 of the insn
407 will be the entire commutative expression: use @code{GET_CODE
408 (operands[3])} to see which commutative operator was used.
410 The machine mode @var{m} of @code{match_operator} works like that of
411 @code{match_operand}: it is passed as the second argument to the
412 predicate function, and that function is solely responsible for
413 deciding whether the expression to be matched ``has'' that mode.
415 When constructing an insn, argument 3 of the gen-function will specify
416 the operation (i.e.@: the expression code) for the expression to be
417 made. It should be an RTL expression, whose expression code is copied
418 into a new expression whose operands are arguments 1 and 2 of the
419 gen-function. The subexpressions of argument 3 are not used;
420 only its expression code matters.
422 When @code{match_operator} is used in a pattern for matching an insn,
423 it usually best if the operand number of the @code{match_operator}
424 is higher than that of the actual operands of the insn. This improves
425 register allocation because the register allocator often looks at
426 operands 1 and 2 of insns to see if it can do register tying.
428 There is no way to specify constraints in @code{match_operator}. The
429 operand of the insn which corresponds to the @code{match_operator}
430 never has any constraints because it is never reloaded as a whole.
431 However, if parts of its @var{operands} are matched by
432 @code{match_operand} patterns, those parts may have constraints of
436 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
437 Like @code{match_dup}, except that it applies to operators instead of
438 operands. When constructing an insn, operand number @var{n} will be
439 substituted at this point. But in matching, @code{match_op_dup} behaves
440 differently. It assumes that operand number @var{n} has already been
441 determined by a @code{match_operator} appearing earlier in the
442 recognition template, and it matches only an identical-looking
445 @findex match_parallel
446 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
447 This pattern is a placeholder for an insn that consists of a
448 @code{parallel} expression with a variable number of elements. This
449 expression should only appear at the top level of an insn pattern.
451 When constructing an insn, operand number @var{n} will be substituted at
452 this point. When matching an insn, it matches if the body of the insn
453 is a @code{parallel} expression with at least as many elements as the
454 vector of @var{subpat} expressions in the @code{match_parallel}, if each
455 @var{subpat} matches the corresponding element of the @code{parallel},
456 @emph{and} the function @var{predicate} returns nonzero on the
457 @code{parallel} that is the body of the insn. It is the responsibility
458 of the predicate to validate elements of the @code{parallel} beyond
459 those listed in the @code{match_parallel}.
461 A typical use of @code{match_parallel} is to match load and store
462 multiple expressions, which can contain a variable number of elements
463 in a @code{parallel}. For example,
467 [(match_parallel 0 "load_multiple_operation"
468 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
469 (match_operand:SI 2 "memory_operand" "m"))
471 (clobber (reg:SI 179))])]
476 This example comes from @file{a29k.md}. The function
477 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
478 that subsequent elements in the @code{parallel} are the same as the
479 @code{set} in the pattern, except that they are referencing subsequent
480 registers and memory locations.
482 An insn that matches this pattern might look like:
486 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
488 (clobber (reg:SI 179))
490 (mem:SI (plus:SI (reg:SI 100)
493 (mem:SI (plus:SI (reg:SI 100)
497 @findex match_par_dup
498 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
499 Like @code{match_op_dup}, but for @code{match_parallel} instead of
500 @code{match_operator}.
504 @node Output Template
505 @section Output Templates and Operand Substitution
506 @cindex output templates
507 @cindex operand substitution
509 @cindex @samp{%} in template
511 The @dfn{output template} is a string which specifies how to output the
512 assembler code for an instruction pattern. Most of the template is a
513 fixed string which is output literally. The character @samp{%} is used
514 to specify where to substitute an operand; it can also be used to
515 identify places where different variants of the assembler require
518 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
519 operand @var{n} at that point in the string.
521 @samp{%} followed by a letter and a digit says to output an operand in an
522 alternate fashion. Four letters have standard, built-in meanings described
523 below. The machine description macro @code{PRINT_OPERAND} can define
524 additional letters with nonstandard meanings.
526 @samp{%c@var{digit}} can be used to substitute an operand that is a
527 constant value without the syntax that normally indicates an immediate
530 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
531 the constant is negated before printing.
533 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
534 memory reference, with the actual operand treated as the address. This may
535 be useful when outputting a ``load address'' instruction, because often the
536 assembler syntax for such an instruction requires you to write the operand
537 as if it were a memory reference.
539 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
542 @samp{%=} outputs a number which is unique to each instruction in the
543 entire compilation. This is useful for making local labels to be
544 referred to more than once in a single template that generates multiple
545 assembler instructions.
547 @samp{%} followed by a punctuation character specifies a substitution that
548 does not use an operand. Only one case is standard: @samp{%%} outputs a
549 @samp{%} into the assembler code. Other nonstandard cases can be
550 defined in the @code{PRINT_OPERAND} macro. You must also define
551 which punctuation characters are valid with the
552 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
556 The template may generate multiple assembler instructions. Write the text
557 for the instructions, with @samp{\;} between them.
559 @cindex matching operands
560 When the RTL contains two operands which are required by constraint to match
561 each other, the output template must refer only to the lower-numbered operand.
562 Matching operands are not always identical, and the rest of the compiler
563 arranges to put the proper RTL expression for printing into the lower-numbered
566 One use of nonstandard letters or punctuation following @samp{%} is to
567 distinguish between different assembler languages for the same machine; for
568 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
569 requires periods in most opcode names, while MIT syntax does not. For
570 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
571 syntax. The same file of patterns is used for both kinds of output syntax,
572 but the character sequence @samp{%.} is used in each place where Motorola
573 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
574 defines the sequence to output a period; the macro for MIT syntax defines
577 @cindex @code{#} in template
578 As a special case, a template consisting of the single character @code{#}
579 instructs the compiler to first split the insn, and then output the
580 resulting instructions separately. This helps eliminate redundancy in the
581 output templates. If you have a @code{define_insn} that needs to emit
582 multiple assembler instructions, and there is a matching @code{define_split}
583 already defined, then you can simply use @code{#} as the output template
584 instead of writing an output template that emits the multiple assembler
587 Note that @code{#} only has an effect while generating assembly code;
588 it does not affect whether a split occurs earlier. An associated
589 @code{define_split} must exist and it must be suitable for use after
592 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
593 of the form @samp{@{option0|option1|option2@}} in the templates. These
594 describe multiple variants of assembler language syntax.
595 @xref{Instruction Output}.
597 @node Output Statement
598 @section C Statements for Assembler Output
599 @cindex output statements
600 @cindex C statements for assembler output
601 @cindex generating assembler output
603 Often a single fixed template string cannot produce correct and efficient
604 assembler code for all the cases that are recognized by a single
605 instruction pattern. For example, the opcodes may depend on the kinds of
606 operands; or some unfortunate combinations of operands may require extra
607 machine instructions.
609 If the output control string starts with a @samp{@@}, then it is actually
610 a series of templates, each on a separate line. (Blank lines and
611 leading spaces and tabs are ignored.) The templates correspond to the
612 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
613 if a target machine has a two-address add instruction @samp{addr} to add
614 into a register and another @samp{addm} to add a register to memory, you
615 might write this pattern:
618 (define_insn "addsi3"
619 [(set (match_operand:SI 0 "general_operand" "=r,m")
620 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
621 (match_operand:SI 2 "general_operand" "g,r")))]
628 @cindex @code{*} in template
629 @cindex asterisk in template
630 If the output control string starts with a @samp{*}, then it is not an
631 output template but rather a piece of C program that should compute a
632 template. It should execute a @code{return} statement to return the
633 template-string you want. Most such templates use C string literals, which
634 require doublequote characters to delimit them. To include these
635 doublequote characters in the string, prefix each one with @samp{\}.
637 If the output control string is written as a brace block instead of a
638 double-quoted string, it is automatically assumed to be C code. In that
639 case, it is not necessary to put in a leading asterisk, or to escape the
640 doublequotes surrounding C string literals.
642 The operands may be found in the array @code{operands}, whose C data type
645 It is very common to select different ways of generating assembler code
646 based on whether an immediate operand is within a certain range. Be
647 careful when doing this, because the result of @code{INTVAL} is an
648 integer on the host machine. If the host machine has more bits in an
649 @code{int} than the target machine has in the mode in which the constant
650 will be used, then some of the bits you get from @code{INTVAL} will be
651 superfluous. For proper results, you must carefully disregard the
652 values of those bits.
654 @findex output_asm_insn
655 It is possible to output an assembler instruction and then go on to output
656 or compute more of them, using the subroutine @code{output_asm_insn}. This
657 receives two arguments: a template-string and a vector of operands. The
658 vector may be @code{operands}, or it may be another array of @code{rtx}
659 that you declare locally and initialize yourself.
661 @findex which_alternative
662 When an insn pattern has multiple alternatives in its constraints, often
663 the appearance of the assembler code is determined mostly by which alternative
664 was matched. When this is so, the C code can test the variable
665 @code{which_alternative}, which is the ordinal number of the alternative
666 that was actually satisfied (0 for the first, 1 for the second alternative,
669 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
670 for registers and @samp{clrmem} for memory locations. Here is how
671 a pattern could use @code{which_alternative} to choose between them:
675 [(set (match_operand:SI 0 "general_operand" "=r,m")
679 return (which_alternative == 0
680 ? "clrreg %0" : "clrmem %0");
684 The example above, where the assembler code to generate was
685 @emph{solely} determined by the alternative, could also have been specified
686 as follows, having the output control string start with a @samp{@@}:
691 [(set (match_operand:SI 0 "general_operand" "=r,m")
700 If you just need a little bit of C code in one (or a few) alternatives,
701 you can use @samp{*} inside of a @samp{@@} multi-alternative template:
706 [(set (match_operand:SI 0 "general_operand" "=r,<,m")
711 * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\";
719 @cindex operand predicates
720 @cindex operator predicates
722 A predicate determines whether a @code{match_operand} or
723 @code{match_operator} expression matches, and therefore whether the
724 surrounding instruction pattern will be used for that combination of
725 operands. GCC has a number of machine-independent predicates, and you
726 can define machine-specific predicates as needed. By convention,
727 predicates used with @code{match_operand} have names that end in
728 @samp{_operand}, and those used with @code{match_operator} have names
729 that end in @samp{_operator}.
731 All predicates are boolean functions (in the mathematical sense) of
732 two arguments: the RTL expression that is being considered at that
733 position in the instruction pattern, and the machine mode that the
734 @code{match_operand} or @code{match_operator} specifies. In this
735 section, the first argument is called @var{op} and the second argument
736 @var{mode}. Predicates can be called from C as ordinary two-argument
737 functions; this can be useful in output templates or other
738 machine-specific code.
740 Operand predicates can allow operands that are not actually acceptable
741 to the hardware, as long as the constraints give reload the ability to
742 fix them up (@pxref{Constraints}). However, GCC will usually generate
743 better code if the predicates specify the requirements of the machine
744 instructions as closely as possible. Reload cannot fix up operands
745 that must be constants (``immediate operands''); you must use a
746 predicate that allows only constants, or else enforce the requirement
747 in the extra condition.
749 @cindex predicates and machine modes
750 @cindex normal predicates
751 @cindex special predicates
752 Most predicates handle their @var{mode} argument in a uniform manner.
753 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
754 any mode. If @var{mode} is anything else, then @var{op} must have the
755 same mode, unless @var{op} is a @code{CONST_INT} or integer
756 @code{CONST_DOUBLE}. These RTL expressions always have
757 @code{VOIDmode}, so it would be counterproductive to check that their
758 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
759 integer @code{CONST_DOUBLE} check that the value stored in the
760 constant will fit in the requested mode.
762 Predicates with this behavior are called @dfn{normal}.
763 @command{genrecog} can optimize the instruction recognizer based on
764 knowledge of how normal predicates treat modes. It can also diagnose
765 certain kinds of common errors in the use of normal predicates; for
766 instance, it is almost always an error to use a normal predicate
767 without specifying a mode.
769 Predicates that do something different with their @var{mode} argument
770 are called @dfn{special}. The generic predicates
771 @code{address_operand} and @code{pmode_register_operand} are special
772 predicates. @command{genrecog} does not do any optimizations or
773 diagnosis when special predicates are used.
776 * Machine-Independent Predicates:: Predicates available to all back ends.
777 * Defining Predicates:: How to write machine-specific predicate
781 @node Machine-Independent Predicates
782 @subsection Machine-Independent Predicates
783 @cindex machine-independent predicates
784 @cindex generic predicates
786 These are the generic predicates available to all back ends. They are
787 defined in @file{recog.c}. The first category of predicates allow
788 only constant, or @dfn{immediate}, operands.
790 @defun immediate_operand
791 This predicate allows any sort of constant that fits in @var{mode}.
792 It is an appropriate choice for instructions that take operands that
796 @defun const_int_operand
797 This predicate allows any @code{CONST_INT} expression that fits in
798 @var{mode}. It is an appropriate choice for an immediate operand that
799 does not allow a symbol or label.
802 @defun const_double_operand
803 This predicate accepts any @code{CONST_DOUBLE} expression that has
804 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
805 accept @code{CONST_INT}. It is intended for immediate floating point
810 The second category of predicates allow only some kind of machine
813 @defun register_operand
814 This predicate allows any @code{REG} or @code{SUBREG} expression that
815 is valid for @var{mode}. It is often suitable for arithmetic
816 instruction operands on a RISC machine.
819 @defun pmode_register_operand
820 This is a slight variant on @code{register_operand} which works around
821 a limitation in the machine-description reader.
824 (match_operand @var{n} "pmode_register_operand" @var{constraint})
831 (match_operand:P @var{n} "register_operand" @var{constraint})
835 would mean, if the machine-description reader accepted @samp{:P}
836 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
837 alias for some other mode, and might vary with machine-specific
838 options. @xref{Misc}.
841 @defun scratch_operand
842 This predicate allows hard registers and @code{SCRATCH} expressions,
843 but not pseudo-registers. It is used internally by @code{match_scratch};
844 it should not be used directly.
848 The third category of predicates allow only some kind of memory reference.
850 @defun memory_operand
851 This predicate allows any valid reference to a quantity of mode
852 @var{mode} in memory, as determined by the weak form of
853 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
856 @defun address_operand
857 This predicate is a little unusual; it allows any operand that is a
858 valid expression for the @emph{address} of a quantity of mode
859 @var{mode}, again determined by the weak form of
860 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
861 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
862 @code{memory_operand}, then @var{exp} is acceptable to
863 @code{address_operand}. Note that @var{exp} does not necessarily have
867 @defun indirect_operand
868 This is a stricter form of @code{memory_operand} which allows only
869 memory references with a @code{general_operand} as the address
870 expression. New uses of this predicate are discouraged, because
871 @code{general_operand} is very permissive, so it's hard to tell what
872 an @code{indirect_operand} does or does not allow. If a target has
873 different requirements for memory operands for different instructions,
874 it is better to define target-specific predicates which enforce the
875 hardware's requirements explicitly.
879 This predicate allows a memory reference suitable for pushing a value
880 onto the stack. This will be a @code{MEM} which refers to
881 @code{stack_pointer_rtx}, with a side effect in its address expression
882 (@pxref{Incdec}); which one is determined by the
883 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
887 This predicate allows a memory reference suitable for popping a value
888 off the stack. Again, this will be a @code{MEM} referring to
889 @code{stack_pointer_rtx}, with a side effect in its address
890 expression. However, this time @code{STACK_POP_CODE} is expected.
894 The fourth category of predicates allow some combination of the above
897 @defun nonmemory_operand
898 This predicate allows any immediate or register operand valid for @var{mode}.
901 @defun nonimmediate_operand
902 This predicate allows any register or memory operand valid for @var{mode}.
905 @defun general_operand
906 This predicate allows any immediate, register, or memory operand
907 valid for @var{mode}.
911 Finally, there are two generic operator predicates.
913 @defun comparison_operator
914 This predicate matches any expression which performs an arithmetic
915 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
919 @defun ordered_comparison_operator
920 This predicate matches any expression which performs an arithmetic
921 comparison in @var{mode} and whose expression code is valid for integer
922 modes; that is, the expression code will be one of @code{eq}, @code{ne},
923 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
924 @code{ge}, @code{geu}.
927 @node Defining Predicates
928 @subsection Defining Machine-Specific Predicates
929 @cindex defining predicates
930 @findex define_predicate
931 @findex define_special_predicate
933 Many machines have requirements for their operands that cannot be
934 expressed precisely using the generic predicates. You can define
935 additional predicates using @code{define_predicate} and
936 @code{define_special_predicate} expressions. These expressions have
941 The name of the predicate, as it will be referred to in
942 @code{match_operand} or @code{match_operator} expressions.
945 An RTL expression which evaluates to true if the predicate allows the
946 operand @var{op}, false if it does not. This expression can only use
947 the following RTL codes:
951 When written inside a predicate expression, a @code{MATCH_OPERAND}
952 expression evaluates to true if the predicate it names would allow
953 @var{op}. The operand number and constraint are ignored. Due to
954 limitations in @command{genrecog}, you can only refer to generic
955 predicates and predicates that have already been defined.
958 This expression evaluates to true if @var{op} or a specified
959 subexpression of @var{op} has one of a given list of RTX codes.
961 The first operand of this expression is a string constant containing a
962 comma-separated list of RTX code names (in lower case). These are the
963 codes for which the @code{MATCH_CODE} will be true.
965 The second operand is a string constant which indicates what
966 subexpression of @var{op} to examine. If it is absent or the empty
967 string, @var{op} itself is examined. Otherwise, the string constant
968 must be a sequence of digits and/or lowercase letters. Each character
969 indicates a subexpression to extract from the current expression; for
970 the first character this is @var{op}, for the second and subsequent
971 characters it is the result of the previous character. A digit
972 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
973 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
974 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
975 @code{MATCH_CODE} then examines the RTX code of the subexpression
976 extracted by the complete string. It is not possible to extract
977 components of an @code{rtvec} that is not at position 0 within its RTX
981 This expression has one operand, a string constant containing a C
982 expression. The predicate's arguments, @var{op} and @var{mode}, are
983 available with those names in the C expression. The @code{MATCH_TEST}
984 evaluates to true if the C expression evaluates to a nonzero value.
985 @code{MATCH_TEST} expressions must not have side effects.
991 The basic @samp{MATCH_} expressions can be combined using these
992 logical operators, which have the semantics of the C operators
993 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
994 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
995 arbitrary number of arguments; this has exactly the same effect as
996 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
1000 An optional block of C code, which should execute
1001 @samp{@w{return true}} if the predicate is found to match and
1002 @samp{@w{return false}} if it does not. It must not have any side
1003 effects. The predicate arguments, @var{op} and @var{mode}, are
1004 available with those names.
1006 If a code block is present in a predicate definition, then the RTL
1007 expression must evaluate to true @emph{and} the code block must
1008 execute @samp{@w{return true}} for the predicate to allow the operand.
1009 The RTL expression is evaluated first; do not re-check anything in the
1010 code block that was checked in the RTL expression.
1013 The program @command{genrecog} scans @code{define_predicate} and
1014 @code{define_special_predicate} expressions to determine which RTX
1015 codes are possibly allowed. You should always make this explicit in
1016 the RTL predicate expression, using @code{MATCH_OPERAND} and
1019 Here is an example of a simple predicate definition, from the IA64
1020 machine description:
1024 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
1025 (define_predicate "small_addr_symbolic_operand"
1026 (and (match_code "symbol_ref")
1027 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
1032 And here is another, showing the use of the C block.
1036 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
1037 (define_predicate "gr_register_operand"
1038 (match_operand 0 "register_operand")
1041 if (GET_CODE (op) == SUBREG)
1042 op = SUBREG_REG (op);
1045 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1050 Predicates written with @code{define_predicate} automatically include
1051 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1052 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1053 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1054 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1055 kind of constant fits in the requested mode. This is because
1056 target-specific predicates that take constants usually have to do more
1057 stringent value checks anyway. If you need the exact same treatment
1058 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1059 provide, use a @code{MATCH_OPERAND} subexpression to call
1060 @code{const_int_operand}, @code{const_double_operand}, or
1061 @code{immediate_operand}.
1063 Predicates written with @code{define_special_predicate} do not get any
1064 automatic mode checks, and are treated as having special mode handling
1065 by @command{genrecog}.
1067 The program @command{genpreds} is responsible for generating code to
1068 test predicates. It also writes a header file containing function
1069 declarations for all machine-specific predicates. It is not necessary
1070 to declare these predicates in @file{@var{cpu}-protos.h}.
1073 @c Most of this node appears by itself (in a different place) even
1074 @c when the INTERNALS flag is clear. Passages that require the internals
1075 @c manual's context are conditionalized to appear only in the internals manual.
1078 @section Operand Constraints
1079 @cindex operand constraints
1082 Each @code{match_operand} in an instruction pattern can specify
1083 constraints for the operands allowed. The constraints allow you to
1084 fine-tune matching within the set of operands allowed by the
1090 @section Constraints for @code{asm} Operands
1091 @cindex operand constraints, @code{asm}
1092 @cindex constraints, @code{asm}
1093 @cindex @code{asm} constraints
1095 Here are specific details on what constraint letters you can use with
1096 @code{asm} operands.
1098 Constraints can say whether
1099 an operand may be in a register, and which kinds of register; whether the
1100 operand can be a memory reference, and which kinds of address; whether the
1101 operand may be an immediate constant, and which possible values it may
1102 have. Constraints can also require two operands to match.
1103 Side-effects aren't allowed in operands of inline @code{asm}, unless
1104 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1105 that the side effects will happen exactly once in an instruction that can update
1106 the addressing register.
1110 * Simple Constraints:: Basic use of constraints.
1111 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1112 * Class Preferences:: Constraints guide which hard register to put things in.
1113 * Modifiers:: More precise control over effects of constraints.
1114 * Machine Constraints:: Existing constraints for some particular machines.
1115 * Disable Insn Alternatives:: Disable insn alternatives using attributes.
1116 * Define Constraints:: How to define machine-specific constraints.
1117 * C Constraint Interface:: How to test constraints from C code.
1123 * Simple Constraints:: Basic use of constraints.
1124 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1125 * Modifiers:: More precise control over effects of constraints.
1126 * Machine Constraints:: Special constraints for some particular machines.
1130 @node Simple Constraints
1131 @subsection Simple Constraints
1132 @cindex simple constraints
1134 The simplest kind of constraint is a string full of letters, each of
1135 which describes one kind of operand that is permitted. Here are
1136 the letters that are allowed:
1140 Whitespace characters are ignored and can be inserted at any position
1141 except the first. This enables each alternative for different operands to
1142 be visually aligned in the machine description even if they have different
1143 number of constraints and modifiers.
1145 @cindex @samp{m} in constraint
1146 @cindex memory references in constraints
1148 A memory operand is allowed, with any kind of address that the machine
1149 supports in general.
1150 Note that the letter used for the general memory constraint can be
1151 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1153 @cindex offsettable address
1154 @cindex @samp{o} in constraint
1156 A memory operand is allowed, but only if the address is
1157 @dfn{offsettable}. This means that adding a small integer (actually,
1158 the width in bytes of the operand, as determined by its machine mode)
1159 may be added to the address and the result is also a valid memory
1162 @cindex autoincrement/decrement addressing
1163 For example, an address which is constant is offsettable; so is an
1164 address that is the sum of a register and a constant (as long as a
1165 slightly larger constant is also within the range of address-offsets
1166 supported by the machine); but an autoincrement or autodecrement
1167 address is not offsettable. More complicated indirect/indexed
1168 addresses may or may not be offsettable depending on the other
1169 addressing modes that the machine supports.
1171 Note that in an output operand which can be matched by another
1172 operand, the constraint letter @samp{o} is valid only when accompanied
1173 by both @samp{<} (if the target machine has predecrement addressing)
1174 and @samp{>} (if the target machine has preincrement addressing).
1176 @cindex @samp{V} in constraint
1178 A memory operand that is not offsettable. In other words, anything that
1179 would fit the @samp{m} constraint but not the @samp{o} constraint.
1181 @cindex @samp{<} in constraint
1183 A memory operand with autodecrement addressing (either predecrement or
1184 postdecrement) is allowed. In inline @code{asm} this constraint is only
1185 allowed if the operand is used exactly once in an instruction that can
1186 handle the side effects. Not using an operand with @samp{<} in constraint
1187 string in the inline @code{asm} pattern at all or using it in multiple
1188 instructions isn't valid, because the side effects wouldn't be performed
1189 or would be performed more than once. Furthermore, on some targets
1190 the operand with @samp{<} in constraint string must be accompanied by
1191 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1192 or @code{%P0} on IA-64.
1194 @cindex @samp{>} in constraint
1196 A memory operand with autoincrement addressing (either preincrement or
1197 postincrement) is allowed. In inline @code{asm} the same restrictions
1198 as for @samp{<} apply.
1200 @cindex @samp{r} in constraint
1201 @cindex registers in constraints
1203 A register operand is allowed provided that it is in a general
1206 @cindex constants in constraints
1207 @cindex @samp{i} in constraint
1209 An immediate integer operand (one with constant value) is allowed.
1210 This includes symbolic constants whose values will be known only at
1211 assembly time or later.
1213 @cindex @samp{n} in constraint
1215 An immediate integer operand with a known numeric value is allowed.
1216 Many systems cannot support assembly-time constants for operands less
1217 than a word wide. Constraints for these operands should use @samp{n}
1218 rather than @samp{i}.
1220 @cindex @samp{I} in constraint
1221 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1222 Other letters in the range @samp{I} through @samp{P} may be defined in
1223 a machine-dependent fashion to permit immediate integer operands with
1224 explicit integer values in specified ranges. For example, on the
1225 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1226 This is the range permitted as a shift count in the shift
1229 @cindex @samp{E} in constraint
1231 An immediate floating operand (expression code @code{const_double}) is
1232 allowed, but only if the target floating point format is the same as
1233 that of the host machine (on which the compiler is running).
1235 @cindex @samp{F} in constraint
1237 An immediate floating operand (expression code @code{const_double} or
1238 @code{const_vector}) is allowed.
1240 @cindex @samp{G} in constraint
1241 @cindex @samp{H} in constraint
1242 @item @samp{G}, @samp{H}
1243 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1244 permit immediate floating operands in particular ranges of values.
1246 @cindex @samp{s} in constraint
1248 An immediate integer operand whose value is not an explicit integer is
1251 This might appear strange; if an insn allows a constant operand with a
1252 value not known at compile time, it certainly must allow any known
1253 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1254 better code to be generated.
1256 For example, on the 68000 in a fullword instruction it is possible to
1257 use an immediate operand; but if the immediate value is between @minus{}128
1258 and 127, better code results from loading the value into a register and
1259 using the register. This is because the load into the register can be
1260 done with a @samp{moveq} instruction. We arrange for this to happen
1261 by defining the letter @samp{K} to mean ``any integer outside the
1262 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1265 @cindex @samp{g} in constraint
1267 Any register, memory or immediate integer operand is allowed, except for
1268 registers that are not general registers.
1270 @cindex @samp{X} in constraint
1273 Any operand whatsoever is allowed, even if it does not satisfy
1274 @code{general_operand}. This is normally used in the constraint of
1275 a @code{match_scratch} when certain alternatives will not actually
1276 require a scratch register.
1279 Any operand whatsoever is allowed.
1282 @cindex @samp{0} in constraint
1283 @cindex digits in constraint
1284 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1285 An operand that matches the specified operand number is allowed. If a
1286 digit is used together with letters within the same alternative, the
1287 digit should come last.
1289 This number is allowed to be more than a single digit. If multiple
1290 digits are encountered consecutively, they are interpreted as a single
1291 decimal integer. There is scant chance for ambiguity, since to-date
1292 it has never been desirable that @samp{10} be interpreted as matching
1293 either operand 1 @emph{or} operand 0. Should this be desired, one
1294 can use multiple alternatives instead.
1296 @cindex matching constraint
1297 @cindex constraint, matching
1298 This is called a @dfn{matching constraint} and what it really means is
1299 that the assembler has only a single operand that fills two roles
1301 considered separate in the RTL insn. For example, an add insn has two
1302 input operands and one output operand in the RTL, but on most CISC
1305 which @code{asm} distinguishes. For example, an add instruction uses
1306 two input operands and an output operand, but on most CISC
1308 machines an add instruction really has only two operands, one of them an
1309 input-output operand:
1315 Matching constraints are used in these circumstances.
1316 More precisely, the two operands that match must include one input-only
1317 operand and one output-only operand. Moreover, the digit must be a
1318 smaller number than the number of the operand that uses it in the
1322 For operands to match in a particular case usually means that they
1323 are identical-looking RTL expressions. But in a few special cases
1324 specific kinds of dissimilarity are allowed. For example, @code{*x}
1325 as an input operand will match @code{*x++} as an output operand.
1326 For proper results in such cases, the output template should always
1327 use the output-operand's number when printing the operand.
1330 @cindex load address instruction
1331 @cindex push address instruction
1332 @cindex address constraints
1333 @cindex @samp{p} in constraint
1335 An operand that is a valid memory address is allowed. This is
1336 for ``load address'' and ``push address'' instructions.
1338 @findex address_operand
1339 @samp{p} in the constraint must be accompanied by @code{address_operand}
1340 as the predicate in the @code{match_operand}. This predicate interprets
1341 the mode specified in the @code{match_operand} as the mode of the memory
1342 reference for which the address would be valid.
1344 @cindex other register constraints
1345 @cindex extensible constraints
1346 @item @var{other-letters}
1347 Other letters can be defined in machine-dependent fashion to stand for
1348 particular classes of registers or other arbitrary operand types.
1349 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1350 for data, address and floating point registers.
1354 In order to have valid assembler code, each operand must satisfy
1355 its constraint. But a failure to do so does not prevent the pattern
1356 from applying to an insn. Instead, it directs the compiler to modify
1357 the code so that the constraint will be satisfied. Usually this is
1358 done by copying an operand into a register.
1360 Contrast, therefore, the two instruction patterns that follow:
1364 [(set (match_operand:SI 0 "general_operand" "=r")
1365 (plus:SI (match_dup 0)
1366 (match_operand:SI 1 "general_operand" "r")))]
1372 which has two operands, one of which must appear in two places, and
1376 [(set (match_operand:SI 0 "general_operand" "=r")
1377 (plus:SI (match_operand:SI 1 "general_operand" "0")
1378 (match_operand:SI 2 "general_operand" "r")))]
1384 which has three operands, two of which are required by a constraint to be
1385 identical. If we are considering an insn of the form
1388 (insn @var{n} @var{prev} @var{next}
1390 (plus:SI (reg:SI 6) (reg:SI 109)))
1395 the first pattern would not apply at all, because this insn does not
1396 contain two identical subexpressions in the right place. The pattern would
1397 say, ``That does not look like an add instruction; try other patterns''.
1398 The second pattern would say, ``Yes, that's an add instruction, but there
1399 is something wrong with it''. It would direct the reload pass of the
1400 compiler to generate additional insns to make the constraint true. The
1401 results might look like this:
1404 (insn @var{n2} @var{prev} @var{n}
1405 (set (reg:SI 3) (reg:SI 6))
1408 (insn @var{n} @var{n2} @var{next}
1410 (plus:SI (reg:SI 3) (reg:SI 109)))
1414 It is up to you to make sure that each operand, in each pattern, has
1415 constraints that can handle any RTL expression that could be present for
1416 that operand. (When multiple alternatives are in use, each pattern must,
1417 for each possible combination of operand expressions, have at least one
1418 alternative which can handle that combination of operands.) The
1419 constraints don't need to @emph{allow} any possible operand---when this is
1420 the case, they do not constrain---but they must at least point the way to
1421 reloading any possible operand so that it will fit.
1425 If the constraint accepts whatever operands the predicate permits,
1426 there is no problem: reloading is never necessary for this operand.
1428 For example, an operand whose constraints permit everything except
1429 registers is safe provided its predicate rejects registers.
1431 An operand whose predicate accepts only constant values is safe
1432 provided its constraints include the letter @samp{i}. If any possible
1433 constant value is accepted, then nothing less than @samp{i} will do;
1434 if the predicate is more selective, then the constraints may also be
1438 Any operand expression can be reloaded by copying it into a register.
1439 So if an operand's constraints allow some kind of register, it is
1440 certain to be safe. It need not permit all classes of registers; the
1441 compiler knows how to copy a register into another register of the
1442 proper class in order to make an instruction valid.
1444 @cindex nonoffsettable memory reference
1445 @cindex memory reference, nonoffsettable
1447 A nonoffsettable memory reference can be reloaded by copying the
1448 address into a register. So if the constraint uses the letter
1449 @samp{o}, all memory references are taken care of.
1452 A constant operand can be reloaded by allocating space in memory to
1453 hold it as preinitialized data. Then the memory reference can be used
1454 in place of the constant. So if the constraint uses the letters
1455 @samp{o} or @samp{m}, constant operands are not a problem.
1458 If the constraint permits a constant and a pseudo register used in an insn
1459 was not allocated to a hard register and is equivalent to a constant,
1460 the register will be replaced with the constant. If the predicate does
1461 not permit a constant and the insn is re-recognized for some reason, the
1462 compiler will crash. Thus the predicate must always recognize any
1463 objects allowed by the constraint.
1466 If the operand's predicate can recognize registers, but the constraint does
1467 not permit them, it can make the compiler crash. When this operand happens
1468 to be a register, the reload pass will be stymied, because it does not know
1469 how to copy a register temporarily into memory.
1471 If the predicate accepts a unary operator, the constraint applies to the
1472 operand. For example, the MIPS processor at ISA level 3 supports an
1473 instruction which adds two registers in @code{SImode} to produce a
1474 @code{DImode} result, but only if the registers are correctly sign
1475 extended. This predicate for the input operands accepts a
1476 @code{sign_extend} of an @code{SImode} register. Write the constraint
1477 to indicate the type of register that is required for the operand of the
1481 @node Multi-Alternative
1482 @subsection Multiple Alternative Constraints
1483 @cindex multiple alternative constraints
1485 Sometimes a single instruction has multiple alternative sets of possible
1486 operands. For example, on the 68000, a logical-or instruction can combine
1487 register or an immediate value into memory, or it can combine any kind of
1488 operand into a register; but it cannot combine one memory location into
1491 These constraints are represented as multiple alternatives. An alternative
1492 can be described by a series of letters for each operand. The overall
1493 constraint for an operand is made from the letters for this operand
1494 from the first alternative, a comma, the letters for this operand from
1495 the second alternative, a comma, and so on until the last alternative.
1496 All operands for a single instruction must have the same number of
1499 Here is how it is done for fullword logical-or on the 68000:
1502 (define_insn "iorsi3"
1503 [(set (match_operand:SI 0 "general_operand" "=m,d")
1504 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1505 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1509 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1510 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1511 2. The second alternative has @samp{d} (data register) for operand 0,
1512 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1513 @samp{%} in the constraints apply to all the alternatives; their
1514 meaning is explained in the next section (@pxref{Class Preferences}).
1516 If all the operands fit any one alternative, the instruction is valid.
1517 Otherwise, for each alternative, the compiler counts how many instructions
1518 must be added to copy the operands so that that alternative applies.
1519 The alternative requiring the least copying is chosen. If two alternatives
1520 need the same amount of copying, the one that comes first is chosen.
1521 These choices can be altered with the @samp{?} and @samp{!} characters:
1524 @cindex @samp{?} in constraint
1525 @cindex question mark
1527 Disparage slightly the alternative that the @samp{?} appears in,
1528 as a choice when no alternative applies exactly. The compiler regards
1529 this alternative as one unit more costly for each @samp{?} that appears
1532 @cindex @samp{!} in constraint
1533 @cindex exclamation point
1535 Disparage severely the alternative that the @samp{!} appears in.
1536 This alternative can still be used if it fits without reloading,
1537 but if reloading is needed, some other alternative will be used.
1539 @cindex @samp{^} in constraint
1542 This constraint is analogous to @samp{?} but it disparages slightly
1543 the alternative only if the operand with the @samp{^} needs a reload.
1545 @cindex @samp{$} in constraint
1548 This constraint is analogous to @samp{!} but it disparages severely
1549 the alternative only if the operand with the @samp{$} needs a reload.
1552 When an insn pattern has multiple alternatives in its constraints, often
1553 the appearance of the assembler code is determined mostly by which
1554 alternative was matched. When this is so, the C code for writing the
1555 assembler code can use the variable @code{which_alternative}, which is
1556 the ordinal number of the alternative that was actually satisfied (0 for
1557 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1561 So the first alternative for the 68000's logical-or could be written as
1562 @code{"+m" (output) : "ir" (input)}. The second could be @code{"+r"
1563 (output): "irm" (input)}. However, the fact that two memory locations
1564 cannot be used in a single instruction prevents simply using @code{"+rm"
1565 (output) : "irm" (input)}. Using multi-alternatives, this might be
1566 written as @code{"+m,r" (output) : "ir,irm" (input)}. This describes
1567 all the available alternatives to the compiler, allowing it to choose
1568 the most efficient one for the current conditions.
1570 There is no way within the template to determine which alternative was
1571 chosen. However you may be able to wrap your @code{asm} statements with
1572 builtins such as @code{__builtin_constant_p} to achieve the desired results.
1576 @node Class Preferences
1577 @subsection Register Class Preferences
1578 @cindex class preference constraints
1579 @cindex register class preference constraints
1581 @cindex voting between constraint alternatives
1582 The operand constraints have another function: they enable the compiler
1583 to decide which kind of hardware register a pseudo register is best
1584 allocated to. The compiler examines the constraints that apply to the
1585 insns that use the pseudo register, looking for the machine-dependent
1586 letters such as @samp{d} and @samp{a} that specify classes of registers.
1587 The pseudo register is put in whichever class gets the most ``votes''.
1588 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1589 favor of a general register. The machine description says which registers
1590 are considered general.
1592 Of course, on some machines all registers are equivalent, and no register
1593 classes are defined. Then none of this complexity is relevant.
1597 @subsection Constraint Modifier Characters
1598 @cindex modifiers in constraints
1599 @cindex constraint modifier characters
1601 @c prevent bad page break with this line
1602 Here are constraint modifier characters.
1605 @cindex @samp{=} in constraint
1607 Means that this operand is written to by this instruction:
1608 the previous value is discarded and replaced by new data.
1610 @cindex @samp{+} in constraint
1612 Means that this operand is both read and written by the instruction.
1614 When the compiler fixes up the operands to satisfy the constraints,
1615 it needs to know which operands are read by the instruction and
1616 which are written by it. @samp{=} identifies an operand which is only
1617 written; @samp{+} identifies an operand that is both read and written; all
1618 other operands are assumed to only be read.
1620 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1621 first character of the constraint string.
1623 @cindex @samp{&} in constraint
1624 @cindex earlyclobber operand
1626 Means (in a particular alternative) that this operand is an
1627 @dfn{earlyclobber} operand, which is written before the instruction is
1628 finished using the input operands. Therefore, this operand may not lie
1629 in a register that is read by the instruction or as part of any memory
1632 @samp{&} applies only to the alternative in which it is written. In
1633 constraints with multiple alternatives, sometimes one alternative
1634 requires @samp{&} while others do not. See, for example, the
1635 @samp{movdf} insn of the 68000.
1637 A operand which is read by the instruction can be tied to an earlyclobber
1638 operand if its only use as an input occurs before the early result is
1639 written. Adding alternatives of this form often allows GCC to produce
1640 better code when only some of the read operands can be affected by the
1641 earlyclobber. See, for example, the @samp{mulsi3} insn of the ARM@.
1643 Furthermore, if the @dfn{earlyclobber} operand is also a read/write
1644 operand, then that operand is written only after it's used.
1646 @samp{&} does not obviate the need to write @samp{=} or @samp{+}. As
1647 @dfn{earlyclobber} operands are always written, a read-only
1648 @dfn{earlyclobber} operand is ill-formed and will be rejected by the
1651 @cindex @samp{%} in constraint
1653 Declares the instruction to be commutative for this operand and the
1654 following operand. This means that the compiler may interchange the
1655 two operands if that is the cheapest way to make all operands fit the
1656 constraints. @samp{%} applies to all alternatives and must appear as
1657 the first character in the constraint. Only read-only operands can use
1661 This is often used in patterns for addition instructions
1662 that really have only two operands: the result must go in one of the
1663 arguments. Here for example, is how the 68000 halfword-add
1664 instruction is defined:
1667 (define_insn "addhi3"
1668 [(set (match_operand:HI 0 "general_operand" "=m,r")
1669 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1670 (match_operand:HI 2 "general_operand" "di,g")))]
1674 GCC can only handle one commutative pair in an asm; if you use more,
1675 the compiler may fail. Note that you need not use the modifier if
1676 the two alternatives are strictly identical; this would only waste
1677 time in the reload pass.
1679 The modifier is not operational after
1680 register allocation, so the result of @code{define_peephole2}
1681 and @code{define_split}s performed after reload cannot rely on
1682 @samp{%} to make the intended insn match.
1684 @cindex @samp{#} in constraint
1686 Says that all following characters, up to the next comma, are to be
1687 ignored as a constraint. They are significant only for choosing
1688 register preferences.
1690 @cindex @samp{*} in constraint
1692 Says that the following character should be ignored when choosing
1693 register preferences. @samp{*} has no effect on the meaning of the
1694 constraint as a constraint, and no effect on reloading. For LRA
1695 @samp{*} additionally disparages slightly the alternative if the
1696 following character matches the operand.
1698 Here is an example: the 68000 has an instruction to sign-extend a
1699 halfword in a data register, and can also sign-extend a value by
1700 copying it into an address register. While either kind of register is
1701 acceptable, the constraints on an address-register destination are
1702 less strict, so it is best if register allocation makes an address
1703 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1704 constraint letter (for data register) is ignored when computing
1705 register preferences.
1708 (define_insn "extendhisi2"
1709 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1711 (match_operand:HI 1 "general_operand" "0,g")))]
1717 @node Machine Constraints
1718 @subsection Constraints for Particular Machines
1719 @cindex machine specific constraints
1720 @cindex constraints, machine specific
1722 Whenever possible, you should use the general-purpose constraint letters
1723 in @code{asm} arguments, since they will convey meaning more readily to
1724 people reading your code. Failing that, use the constraint letters
1725 that usually have very similar meanings across architectures. The most
1726 commonly used constraints are @samp{m} and @samp{r} (for memory and
1727 general-purpose registers respectively; @pxref{Simple Constraints}), and
1728 @samp{I}, usually the letter indicating the most common
1729 immediate-constant format.
1731 Each architecture defines additional constraints. These constraints
1732 are used by the compiler itself for instruction generation, as well as
1733 for @code{asm} statements; therefore, some of the constraints are not
1734 particularly useful for @code{asm}. Here is a summary of some of the
1735 machine-dependent constraints available on some particular machines;
1736 it includes both constraints that are useful for @code{asm} and
1737 constraints that aren't. The compiler source file mentioned in the
1738 table heading for each architecture is the definitive reference for
1739 the meanings of that architecture's constraints.
1741 @c Please keep this table alphabetized by target!
1743 @item AArch64 family---@file{config/aarch64/constraints.md}
1746 The stack pointer register (@code{SP})
1749 Floating point register, Advanced SIMD vector register or SVE vector register
1752 One of the low eight SVE predicate registers (@code{P0} to @code{P7})
1755 Any of the SVE predicate registers (@code{P0} to @code{P15})
1758 Integer constant that is valid as an immediate operand in an @code{ADD}
1762 Integer constant that is valid as an immediate operand in a @code{SUB}
1763 instruction (once negated)
1766 Integer constant that can be used with a 32-bit logical instruction
1769 Integer constant that can be used with a 64-bit logical instruction
1772 Integer constant that is valid as an immediate operand in a 32-bit @code{MOV}
1773 pseudo instruction. The @code{MOV} may be assembled to one of several different
1774 machine instructions depending on the value
1777 Integer constant that is valid as an immediate operand in a 64-bit @code{MOV}
1781 An absolute symbolic address or a label reference
1784 Floating point constant zero
1787 Integer constant zero
1790 The high part (bits 12 and upwards) of the pc-relative address of a symbol
1791 within 4GB of the instruction
1794 A memory address which uses a single base register with no offset
1797 A memory address suitable for a load/store pair instruction in SI, DI, SF and
1803 @item ARC ---@file{config/arc/constraints.md}
1806 Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
1807 @code{r12}-@code{r15}. This constraint can only match when the @option{-mq}
1808 option is in effect.
1811 Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
1812 instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
1813 This constraint can only match when the @option{-mq}
1814 option is in effect.
1816 ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
1819 A signed 12-bit integer constant.
1822 constant for arithmetic/logical operations. This might be any constant
1823 that can be put into a long immediate by the assmbler or linker without
1824 involving a PIC relocation.
1827 A 3-bit unsigned integer constant.
1830 A 6-bit unsigned integer constant.
1833 One's complement of a 6-bit unsigned integer constant.
1836 Two's complement of a 6-bit unsigned integer constant.
1839 A 5-bit unsigned integer constant.
1842 A 7-bit unsigned integer constant.
1845 A 8-bit unsigned integer constant.
1848 Any const_double value.
1851 @item ARM family---@file{config/arm/constraints.md}
1855 In Thumb state, the core registers @code{r8}-@code{r15}.
1858 The stack pointer register.
1861 In Thumb State the core registers @code{r0}-@code{r7}. In ARM state this
1862 is an alias for the @code{r} constraint.
1865 VFP floating-point registers @code{s0}-@code{s31}. Used for 32 bit values.
1868 VFP floating-point registers @code{d0}-@code{d31} and the appropriate
1869 subset @code{d0}-@code{d15} based on command line options.
1870 Used for 64 bit values only. Not valid for Thumb1.
1873 The iWMMX co-processor registers.
1876 The iWMMX GR registers.
1879 The floating-point constant 0.0
1882 Integer that is valid as an immediate operand in a data processing
1883 instruction. That is, an integer in the range 0 to 255 rotated by a
1887 Integer in the range @minus{}4095 to 4095
1890 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1893 Integer that satisfies constraint @samp{I} when negated (twos complement)
1896 Integer in the range 0 to 32
1899 A memory reference where the exact address is in a single register
1900 (`@samp{m}' is preferable for @code{asm} statements)
1903 An item in the constant pool
1906 A symbol in the text segment of the current file
1909 A memory reference suitable for VFP load/store insns (reg+constant offset)
1912 A memory reference suitable for iWMMXt load/store instructions.
1915 A memory reference suitable for the ARMv4 ldrsb instruction.
1918 @item AVR family---@file{config/avr/constraints.md}
1921 Registers from r0 to r15
1924 Registers from r16 to r23
1927 Registers from r16 to r31
1930 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1933 Pointer register (r26--r31)
1936 Base pointer register (r28--r31)
1939 Stack pointer register (SPH:SPL)
1942 Temporary register r0
1945 Register pair X (r27:r26)
1948 Register pair Y (r29:r28)
1951 Register pair Z (r31:r30)
1954 Constant greater than @minus{}1, less than 64
1957 Constant greater than @minus{}64, less than 1
1966 Constant that fits in 8 bits
1969 Constant integer @minus{}1
1972 Constant integer 8, 16, or 24
1978 A floating point constant 0.0
1981 A memory address based on Y or Z pointer with displacement.
1984 @item Blackfin family---@file{config/bfin/constraints.md}
1993 A call clobbered P register.
1996 A single register. If @var{n} is in the range 0 to 7, the corresponding D
1997 register. If it is @code{A}, then the register P0.
2000 Even-numbered D register
2003 Odd-numbered D register
2006 Accumulator register.
2009 Even-numbered accumulator register.
2012 Odd-numbered accumulator register.
2024 Registers used for circular buffering, i.e. I, B, or L registers.
2039 Any D, P, B, M, I or L register.
2042 Additional registers typically used only in prologues and epilogues: RETS,
2043 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2046 Any register except accumulators or CC.
2049 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2052 Unsigned 16 bit integer (in the range 0 to 65535)
2055 Signed 7 bit integer (in the range @minus{}64 to 63)
2058 Unsigned 7 bit integer (in the range 0 to 127)
2061 Unsigned 5 bit integer (in the range 0 to 31)
2064 Signed 4 bit integer (in the range @minus{}8 to 7)
2067 Signed 3 bit integer (in the range @minus{}3 to 4)
2070 Unsigned 3 bit integer (in the range 0 to 7)
2073 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2076 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2077 use with either accumulator.
2080 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2081 use only with accumulator A1.
2090 An integer constant with exactly a single bit set.
2093 An integer constant with all bits set except exactly one.
2101 @item CR16 Architecture---@file{config/cr16/cr16.h}
2105 Registers from r0 to r14 (registers without stack pointer)
2108 Register from r0 to r11 (all 16-bit registers)
2111 Register from r12 to r15 (all 32-bit registers)
2114 Signed constant that fits in 4 bits
2117 Signed constant that fits in 5 bits
2120 Signed constant that fits in 6 bits
2123 Unsigned constant that fits in 4 bits
2126 Signed constant that fits in 32 bits
2129 Check for 64 bits wide constants for add/sub instructions
2132 Floating point constant that is legal for store immediate
2135 @item C-SKY---@file{config/csky/constraints.md}
2139 The mini registers r0 - r7.
2142 The low registers r0 - r15.
2148 HI and LO registers.
2160 Stack pointer register (SP).
2164 The C-SKY back end supports a large set of additional constraints
2165 that are only useful for instruction selection or splitting rather
2166 than inline asm, such as constraints representing constant integer
2167 ranges accepted by particular instruction encodings.
2168 Refer to the source code for details.
2171 @item Epiphany---@file{config/epiphany/constraints.md}
2174 An unsigned 16-bit constant.
2177 An unsigned 5-bit constant.
2180 A signed 11-bit constant.
2183 A signed 11-bit constant added to @minus{}1.
2184 Can only match when the @option{-m1reg-@var{reg}} option is active.
2187 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
2188 being a block of trailing zeroes.
2189 Can only match when the @option{-m1reg-@var{reg}} option is active.
2192 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
2193 rest being zeroes. Or to put it another way, one less than a power of two.
2194 Can only match when the @option{-m1reg-@var{reg}} option is active.
2197 Constant for arithmetic/logical operations.
2198 This is like @code{i}, except that for position independent code,
2199 no symbols / expressions needing relocations are allowed.
2202 Symbolic constant for call/jump instruction.
2205 The register class usable in short insns. This is a register class
2206 constraint, and can thus drive register allocation.
2207 This constraint won't match unless @option{-mprefer-short-insn-regs} is
2211 The the register class of registers that can be used to hold a
2212 sibcall call address. I.e., a caller-saved register.
2215 Core control register class.
2218 The register group usable in short insns.
2219 This constraint does not use a register class, so that it only
2220 passively matches suitable registers, and doesn't drive register allocation.
2224 Constant suitable for the addsi3_r pattern. This is a valid offset
2225 For byte, halfword, or word addressing.
2229 Matches the return address if it can be replaced with the link register.
2232 Matches the integer condition code register.
2235 Matches the return address if it is in a stack slot.
2238 Matches control register values to switch fp mode, which are encapsulated in
2239 @code{UNSPEC_FP_MODE}.
2242 @item FRV---@file{config/frv/frv.h}
2245 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2248 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2251 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2252 @code{icc0} to @code{icc3}).
2255 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2258 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2259 Odd registers are excluded not in the class but through the use of a machine
2260 mode larger than 4 bytes.
2263 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2266 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2267 Odd registers are excluded not in the class but through the use of a machine
2268 mode larger than 4 bytes.
2271 Register in the class @code{LR_REG} (the @code{lr} register).
2274 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2275 Register numbers not divisible by 4 are excluded not in the class but through
2276 the use of a machine mode larger than 8 bytes.
2279 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2282 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2285 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2288 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2291 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2292 Register numbers not divisible by 4 are excluded not in the class but through
2293 the use of a machine mode larger than 8 bytes.
2296 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2299 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2302 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2305 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2308 Floating point constant zero
2311 6-bit signed integer constant
2314 10-bit signed integer constant
2317 16-bit signed integer constant
2320 16-bit unsigned integer constant
2323 12-bit signed integer constant that is negative---i.e.@: in the
2324 range of @minus{}2048 to @minus{}1
2330 12-bit signed integer constant that is greater than zero---i.e.@: in the
2335 @item FT32---@file{config/ft32/constraints.md}
2344 A register indirect memory operand
2353 The constant zero or one
2356 A 16-bit signed constant (@minus{}32768 @dots{} 32767)
2359 A bitfield mask suitable for bext or bins
2362 An inverted bitfield mask suitable for bext or bins
2365 A 16-bit unsigned constant, multiple of 4 (0 @dots{} 65532)
2368 A 20-bit signed constant (@minus{}524288 @dots{} 524287)
2371 A constant for a bitfield width (1 @dots{} 16)
2374 A 10-bit signed constant (@minus{}512 @dots{} 511)
2378 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
2384 Floating point register
2387 Shift amount register
2390 Floating point register (deprecated)
2393 Upper floating point register (32-bit), floating point register (64-bit)
2399 Signed 11-bit integer constant
2402 Signed 14-bit integer constant
2405 Integer constant that can be deposited with a @code{zdepi} instruction
2408 Signed 5-bit integer constant
2414 Integer constant that can be loaded with a @code{ldil} instruction
2417 Integer constant whose value plus one is a power of 2
2420 Integer constant that can be used for @code{and} operations in @code{depi}
2421 and @code{extru} instructions
2430 Floating-point constant 0.0
2433 A @code{lo_sum} data-linkage-table memory operand
2436 A memory operand that can be used as the destination operand of an
2437 integer store instruction
2440 A scaled or unscaled indexed memory operand
2443 A memory operand for floating-point loads and stores
2446 A register indirect memory operand
2449 @item Intel IA-64---@file{config/ia64/ia64.h}
2452 General register @code{r0} to @code{r3} for @code{addl} instruction
2458 Predicate register (@samp{c} as in ``conditional'')
2461 Application register residing in M-unit
2464 Application register residing in I-unit
2467 Floating-point register
2470 Memory operand. If used together with @samp{<} or @samp{>},
2471 the operand can have postincrement and postdecrement which
2472 require printing with @samp{%Pn} on IA-64.
2475 Floating-point constant 0.0 or 1.0
2478 14-bit signed integer constant
2481 22-bit signed integer constant
2484 8-bit signed integer constant for logical instructions
2487 8-bit adjusted signed integer constant for compare pseudo-ops
2490 6-bit unsigned integer constant for shift counts
2493 9-bit signed integer constant for load and store postincrements
2499 0 or @minus{}1 for @code{dep} instruction
2502 Non-volatile memory for floating-point loads and stores
2505 Integer constant in the range 1 to 4 for @code{shladd} instruction
2508 Memory operand except postincrement and postdecrement. This is
2509 now roughly the same as @samp{m} when not used together with @samp{<}
2513 @item M32C---@file{config/m32c/m32c.c}
2518 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2521 Any control register, when they're 16 bits wide (nothing if control
2522 registers are 24 bits wide)
2525 Any control register, when they're 24 bits wide.
2534 $r0 or $r2, or $r2r0 for 32 bit values.
2537 $r1 or $r3, or $r3r1 for 32 bit values.
2540 A register that can hold a 64 bit value.
2543 $r0 or $r1 (registers with addressable high/low bytes)
2552 Address registers when they're 16 bits wide.
2555 Address registers when they're 24 bits wide.
2558 Registers that can hold QI values.
2561 Registers that can be used with displacements ($a0, $a1, $sb).
2564 Registers that can hold 32 bit values.
2567 Registers that can hold 16 bit values.
2570 Registers chat can hold 16 bit values, including all control
2574 $r0 through R1, plus $a0 and $a1.
2580 The memory-based pseudo-registers $mem0 through $mem15.
2583 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2584 bit registers for m32cm, m32c).
2587 Matches multiple registers in a PARALLEL to form a larger register.
2588 Used to match function return values.
2594 @minus{}128 @dots{} 127
2597 @minus{}32768 @dots{} 32767
2603 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2606 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2609 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2612 @minus{}65536 @dots{} @minus{}1
2615 An 8 bit value with exactly one bit set.
2618 A 16 bit value with exactly one bit set.
2621 The common src/dest memory addressing modes.
2624 Memory addressed using $a0 or $a1.
2627 Memory addressed with immediate addresses.
2630 Memory addressed using the stack pointer ($sp).
2633 Memory addressed using the frame base register ($fb).
2636 Memory addressed using the small base register ($sb).
2642 @item MicroBlaze---@file{config/microblaze/constraints.md}
2645 A general register (@code{r0} to @code{r31}).
2648 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2652 @item MIPS---@file{config/mips/constraints.md}
2655 A general-purpose register. This is equivalent to @code{r} unless
2656 generating MIPS16 code, in which case the MIPS16 register set is used.
2659 A floating-point register (if available).
2662 Formerly the @code{hi} register. This constraint is no longer supported.
2665 The @code{lo} register. Use this register to store values that are
2666 no bigger than a word.
2669 The concatenated @code{hi} and @code{lo} registers. Use this register
2670 to store doubleword values.
2673 A register suitable for use in an indirect jump. This will always be
2674 @code{$25} for @option{-mabicalls}.
2677 Register @code{$3}. Do not use this constraint in new code;
2678 it is retained only for compatibility with glibc.
2681 Equivalent to @code{r}; retained for backwards compatibility.
2684 A floating-point condition code register.
2687 A signed 16-bit constant (for arithmetic instructions).
2693 An unsigned 16-bit constant (for logic instructions).
2696 A signed 32-bit constant in which the lower 16 bits are zero.
2697 Such constants can be loaded using @code{lui}.
2700 A constant that cannot be loaded using @code{lui}, @code{addiu}
2704 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2707 A signed 15-bit constant.
2710 A constant in the range 1 to 65535 (inclusive).
2713 Floating-point zero.
2716 An address that can be used in a non-macro load or store.
2719 A memory operand whose address is formed by a base register and offset
2720 that is suitable for use in instructions with the same addressing mode
2721 as @code{ll} and @code{sc}.
2724 An address suitable for a @code{prefetch} instruction, or for any other
2725 instruction with the same addressing mode as @code{prefetch}.
2728 @item Motorola 680x0---@file{config/m68k/constraints.md}
2737 68881 floating-point register, if available
2740 Integer in the range 1 to 8
2743 16-bit signed number
2746 Signed number whose magnitude is greater than 0x80
2749 Integer in the range @minus{}8 to @minus{}1
2752 Signed number whose magnitude is greater than 0x100
2755 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2758 16 (for rotate using swap)
2761 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2764 Numbers that mov3q can handle
2767 Floating point constant that is not a 68881 constant
2770 Operands that satisfy 'm' when -mpcrel is in effect
2773 Operands that satisfy 's' when -mpcrel is not in effect
2776 Address register indirect addressing mode
2779 Register offset addressing
2794 Range of signed numbers that don't fit in 16 bits
2797 Integers valid for mvq
2800 Integers valid for a moveq followed by a swap
2803 Integers valid for mvz
2806 Integers valid for mvs
2812 Non-register operands allowed in clr
2816 @item Moxie---@file{config/moxie/constraints.md}
2825 A register indirect memory operand
2828 A constant in the range of 0 to 255.
2831 A constant in the range of 0 to @minus{}255.
2835 @item MSP430--@file{config/msp430/constraints.md}
2848 Integer constant -1^20..1^19.
2851 Integer constant 1-4.
2854 Memory references which do not require an extended MOVX instruction.
2857 Memory reference, labels only.
2860 Memory reference, stack only.
2864 @item NDS32---@file{config/nds32/constraints.md}
2867 LOW register class $r0 to $r7 constraint for V3/V3M ISA.
2869 LOW register class $r0 to $r7.
2871 MIDDLE register class $r0 to $r11, $r16 to $r19.
2873 HIGH register class $r12 to $r14, $r20 to $r31.
2875 Temporary assist register $ta (i.e.@: $r15).
2879 Unsigned immediate 3-bit value.
2881 Negative immediate 3-bit value in the range of @minus{}7--0.
2883 Unsigned immediate 4-bit value.
2885 Signed immediate 5-bit value.
2887 Unsigned immediate 5-bit value.
2889 Negative immediate 5-bit value in the range of @minus{}31--0.
2891 Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.
2893 Unsigned immediate 6-bit value constraint for addri36.sp instruction.
2895 Unsigned immediate 8-bit value.
2897 Unsigned immediate 9-bit value.
2899 Signed immediate 10-bit value.
2901 Signed immediate 11-bit value.
2903 Signed immediate 15-bit value.
2905 Unsigned immediate 15-bit value.
2907 A constant which is not in the range of imm15u but ok for bclr instruction.
2909 A constant which is not in the range of imm15u but ok for bset instruction.
2911 A constant which is not in the range of imm15u but ok for btgl instruction.
2913 A constant whose compliment value is in the range of imm15u
2914 and ok for bitci instruction.
2916 Signed immediate 16-bit value.
2918 Signed immediate 17-bit value.
2920 Signed immediate 19-bit value.
2922 Signed immediate 20-bit value.
2924 The immediate value that can be simply set high 20-bit.
2926 The immediate value 0xff.
2928 The immediate value 0xffff.
2930 The immediate value 0x01.
2932 The immediate value 0x7ff.
2934 The immediate value with power of 2.
2936 The immediate value with power of 2 minus 1.
2938 Memory constraint for 333 format.
2940 Memory constraint for 45 format.
2942 Memory constraint for 37 format.
2945 @item Nios II family---@file{config/nios2/constraints.md}
2949 Integer that is valid as an immediate operand in an
2950 instruction taking a signed 16-bit number. Range
2951 @minus{}32768 to 32767.
2954 Integer that is valid as an immediate operand in an
2955 instruction taking an unsigned 16-bit number. Range
2959 Integer that is valid as an immediate operand in an
2960 instruction taking only the upper 16-bits of a
2961 32-bit number. Range 32-bit numbers with the lower
2965 Integer that is valid as an immediate operand for a
2966 shift instruction. Range 0 to 31.
2969 Integer that is valid as an immediate operand for
2970 only the value 0. Can be used in conjunction with
2971 the format modifier @code{z} to use @code{r0}
2972 instead of @code{0} in the assembly output.
2975 Integer that is valid as an immediate operand for
2976 a custom instruction opcode. Range 0 to 255.
2979 An immediate operand for R2 andchi/andci instructions.
2982 Matches immediates which are addresses in the small
2983 data section and therefore can be added to @code{gp}
2984 as a 16-bit immediate to re-create their 32-bit value.
2987 Matches constants suitable as an operand for the rdprs and
2991 A memory operand suitable for Nios II R2 load/store
2992 exclusive instructions.
2995 A memory operand suitable for load/store IO and cache
3000 A @code{const} wrapped @code{UNSPEC} expression,
3001 representing a supported PIC or TLS relocation.
3006 @item PDP-11---@file{config/pdp11/constraints.md}
3009 Floating point registers AC0 through AC3. These can be loaded from/to
3010 memory with a single instruction.
3013 Odd numbered general registers (R1, R3, R5). These are used for
3014 16-bit multiply operations.
3017 A memory reference that is encoded within the opcode, but not
3018 auto-increment or auto-decrement.
3021 Any of the floating point registers (AC0 through AC5).
3024 Floating point constant 0.
3027 Floating point registers AC4 and AC5. These cannot be loaded from/to
3028 memory with a single instruction.
3031 An integer constant that fits in 16 bits.
3034 An integer constant whose low order 16 bits are zero.
3037 An integer constant that does not meet the constraints for codes
3038 @samp{I} or @samp{J}.
3041 The integer constant 1.
3044 The integer constant @minus{}1.
3047 The integer constant 0.
3050 Integer constants 0 through 3; shifts by these
3051 amounts are handled as multiple single-bit shifts rather than a single
3052 variable-length shift.
3055 A memory reference which requires an additional word (address or
3056 offset) after the opcode.
3059 A memory reference that is encoded within the opcode.
3063 @item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md}
3066 Address base register
3069 Floating point register (containing 64-bit value)
3072 Floating point register (containing 32-bit value)
3075 Altivec vector register
3078 Any VSX register if the @option{-mvsx} option was used or NO_REGS.
3080 When using any of the register constraints (@code{wa}, @code{wd},
3081 @code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk},
3082 @code{wl}, @code{wm}, @code{wo}, @code{wp}, @code{wq}, @code{ws},
3083 @code{wt}, @code{wu}, @code{wv}, @code{ww}, or @code{wy})
3084 that take VSX registers, you must use @code{%x<n>} in the template so
3085 that the correct register is used. Otherwise the register number
3086 output in the assembly file will be incorrect if an Altivec register
3087 is an operand of a VSX instruction that expects VSX register
3091 asm ("xvadddp %x0,%x1,%x2"
3093 : "wa" (v2), "wa" (v3));
3100 asm ("xvadddp %0,%1,%2"
3102 : "wa" (v2), "wa" (v3));
3108 If an instruction only takes Altivec registers, you do not want to use
3112 asm ("xsaddqp %0,%1,%2"
3114 : "v" (v2), "v" (v3));
3118 is correct because the @code{xsaddqp} instruction only takes Altivec
3122 asm ("xsaddqp %x0,%x1,%x2"
3124 : "v" (v2), "v" (v3));
3131 Altivec register if @option{-mcpu=power9} is used or NO_REGS.
3134 VSX vector register to hold vector double data or NO_REGS.
3137 VSX register if the @option{-mcpu=power9} and @option{-m64} options
3138 were used or NO_REGS.
3141 VSX vector register to hold vector float data or NO_REGS.
3144 If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
3147 Floating point register if direct moves are available, or NO_REGS.
3150 FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
3153 FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
3156 FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.
3159 Floating point register if the LFIWAX instruction is enabled or NO_REGS.
3162 VSX register if direct move instructions are enabled, or NO_REGS.
3165 No register (NO_REGS).
3168 VSX register to use for ISA 3.0 vector instructions, or NO_REGS.
3171 VSX register to use for IEEE 128-bit floating point TFmode, or NO_REGS.
3174 VSX register to use for IEEE 128-bit floating point, or NO_REGS.
3177 General purpose register if 64-bit instructions are enabled or NO_REGS.
3180 VSX vector register to hold scalar double values or NO_REGS.
3183 VSX vector register to hold 128 bit integer or NO_REGS.
3186 Altivec register to use for float/32-bit int loads/stores or NO_REGS.
3189 Altivec register to use for double loads/stores or NO_REGS.
3192 FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
3195 Floating point register if the STFIWX instruction is enabled or NO_REGS.
3198 FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
3201 Floating point register if the LFIWZX instruction is enabled or NO_REGS.
3204 Address base register if 64-bit instructions are enabled or NO_REGS.
3207 Signed 5-bit constant integer that can be loaded into an altivec register.
3210 Int constant that is the element number of the 64-bit scalar in a vector.
3213 Vector constant that can be loaded with the XXSPLTIB instruction.
3216 Memory operand suitable for power9 fusion load/stores.
3219 Memory operand suitable for TOC fusion memory references.
3222 Altivec register if @option{-mvsx-small-integer}.
3225 Floating point register if @option{-mvsx-small-integer}.
3228 FP register if @option{-mvsx-small-integer} and @option{-mpower9-vector}.
3231 Altivec register if @option{-mvsx-small-integer} and @option{-mpower9-vector}.
3234 Int constant that is the element number that the MFVSRLD instruction.
3238 Match vector constant with all 1's if the XXLORC instruction is available.
3241 A memory operand suitable for the ISA 3.0 vector d-form instructions.
3244 A memory address that will work with the @code{lq} and @code{stq}
3248 Vector constant that can be loaded with XXSPLTIB & sign extension.
3251 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
3257 @samp{LINK} register
3260 @samp{CR} register (condition register) number 0
3263 @samp{CR} register (condition register)
3266 @samp{XER[CA]} carry bit (part of the XER register)
3269 Signed 16-bit constant
3272 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
3273 @code{SImode} constants)
3276 Unsigned 16-bit constant
3279 Signed 16-bit constant shifted left 16 bits
3282 Constant larger than 31
3291 Constant whose negation is a signed 16-bit constant
3294 Floating point constant that can be loaded into a register with one
3295 instruction per word
3298 Integer/Floating point constant that can be loaded into a register using
3303 Normally, @code{m} does not allow addresses that update the base register.
3304 If @samp{<} or @samp{>} constraint is also used, they are allowed and
3305 therefore on PowerPC targets in that case it is only safe
3306 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
3307 accesses the operand exactly once. The @code{asm} statement must also
3308 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
3309 corresponding load or store instruction. For example:
3312 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
3318 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
3324 A ``stable'' memory operand; that is, one which does not include any
3325 automodification of the base register. This used to be useful when
3326 @samp{m} allowed automodification of the base register, but as those are now only
3327 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
3328 as @samp{m} without @samp{<} and @samp{>}.
3331 Memory operand that is an offset from a register (it is usually better
3332 to use @samp{m} or @samp{es} in @code{asm} statements)
3335 Memory operand that is an indexed or indirect from a register (it is
3336 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
3342 Address operand that is an indexed or indirect from a register (@samp{p} is
3343 preferable for @code{asm} statements)
3346 System V Release 4 small data area reference
3349 Vector constant that does not require memory
3352 Vector constant that is all zeros.
3356 @item RL78---@file{config/rl78/constraints.md}
3360 An integer constant in the range 1 @dots{} 7.
3362 An integer constant in the range 0 @dots{} 255.
3364 An integer constant in the range @minus{}255 @dots{} 0
3366 The integer constant 1.
3368 The integer constant -1.
3370 The integer constant 0.
3372 The integer constant 2.
3374 The integer constant -2.
3376 An integer constant in the range 1 @dots{} 15.
3378 The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
3380 The synthetic compare types--gt, lt, ge, and le.
3382 A memory reference with an absolute address.
3384 A memory reference using @code{BC} as a base register, with an optional offset.
3386 A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
3388 A memory reference using any 16-bit register pair for the address, for calls.
3390 A memory reference using @code{DE} as a base register, with an optional offset.
3392 A memory reference using @code{DE} as a base register, without any offset.
3394 Any memory reference to an address in the far address space.
3396 A memory reference using @code{HL} as a base register, with an optional one-byte offset.
3398 A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
3400 A memory reference using @code{HL} as a base register, without any offset.
3402 A memory reference using @code{SP} as a base register, with an optional one-byte offset.
3404 Any memory reference to an address in the near address space.
3406 The @code{AX} register.
3408 The @code{BC} register.
3410 The @code{DE} register.
3412 @code{A} through @code{L} registers.
3414 The @code{SP} register.
3416 The @code{HL} register.
3418 The 16-bit @code{R8} register.
3420 The 16-bit @code{R10} register.
3422 The registers reserved for interrupts (@code{R24} to @code{R31}).
3424 The @code{A} register.
3426 The @code{B} register.
3428 The @code{C} register.
3430 The @code{D} register.
3432 The @code{E} register.
3434 The @code{H} register.
3436 The @code{L} register.
3438 The virtual registers.
3440 The @code{PSW} register.
3442 The @code{X} register.
3446 @item RISC-V---@file{config/riscv/constraints.md}
3450 A floating-point register (if availiable).
3453 An I-type 12-bit signed immediate.
3459 A 5-bit unsigned immediate for CSR access instructions.
3462 An address that is held in a general-purpose register.
3466 @item RX---@file{config/rx/constraints.md}
3469 An address which does not involve register indirect addressing or
3470 pre/post increment/decrement addressing.
3476 A constant in the range @minus{}256 to 255, inclusive.
3479 A constant in the range @minus{}128 to 127, inclusive.
3482 A constant in the range @minus{}32768 to 32767, inclusive.
3485 A constant in the range @minus{}8388608 to 8388607, inclusive.
3488 A constant in the range 0 to 15, inclusive.
3492 @item S/390 and zSeries---@file{config/s390/s390.h}
3495 Address register (general purpose register except r0)
3498 Condition code register
3501 Data register (arbitrary general purpose register)
3504 Floating-point register
3507 Unsigned 8-bit constant (0--255)
3510 Unsigned 12-bit constant (0--4095)
3513 Signed 16-bit constant (@minus{}32768--32767)
3516 Value appropriate as displacement.
3519 for short displacement
3520 @item (@minus{}524288..524287)
3521 for long displacement
3525 Constant integer with a value of 0x7fffffff.
3528 Multiple letter constraint followed by 4 parameter letters.
3531 number of the part counting from most to least significant
3535 mode of the containing operand
3537 value of the other parts (F---all bits set)
3539 The constraint matches if the specified part of a constant
3540 has a value different from its other parts.
3543 Memory reference without index register and with short displacement.
3546 Memory reference with index register and short displacement.
3549 Memory reference without index register but with long displacement.
3552 Memory reference with index register and long displacement.
3555 Pointer with short displacement.
3558 Pointer with long displacement.
3561 Shift count operand.
3566 @item SPARC---@file{config/sparc/sparc.h}
3569 Floating-point register on the SPARC-V8 architecture and
3570 lower floating-point register on the SPARC-V9 architecture.
3573 Floating-point register. It is equivalent to @samp{f} on the
3574 SPARC-V8 architecture and contains both lower and upper
3575 floating-point registers on the SPARC-V9 architecture.
3578 Floating-point condition code register.
3581 Lower floating-point register. It is only valid on the SPARC-V9
3582 architecture when the Visual Instruction Set is available.
3585 Floating-point register. It is only valid on the SPARC-V9 architecture
3586 when the Visual Instruction Set is available.
3589 64-bit global or out register for the SPARC-V8+ architecture.
3592 The constant all-ones, for floating-point.
3595 Signed 5-bit constant
3601 Signed 13-bit constant
3607 32-bit constant with the low 12 bits clear (a constant that can be
3608 loaded with the @code{sethi} instruction)
3611 A constant in the range supported by @code{movcc} instructions (11-bit
3615 A constant in the range supported by @code{movrcc} instructions (10-bit
3619 Same as @samp{K}, except that it verifies that bits that are not in the
3620 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3621 modes wider than @code{SImode}
3630 Signed 13-bit constant, sign-extended to 32 or 64 bits
3636 Floating-point constant whose integral representation can
3637 be moved into an integer register using a single sethi
3641 Floating-point constant whose integral representation can
3642 be moved into an integer register using a single mov
3646 Floating-point constant whose integral representation can
3647 be moved into an integer register using a high/lo_sum
3648 instruction sequence
3651 Memory address aligned to an 8-byte boundary
3657 Memory address for @samp{e} constraint registers
3660 Memory address with only a base register
3667 @item SPU---@file{config/spu/spu.h}
3670 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3673 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3676 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3679 An immediate which can be loaded with @code{fsmbi}.
3682 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3685 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3688 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3691 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3694 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3697 An unsigned 7-bit constant for conversion/nop/channel instructions.
3700 A signed 10-bit constant for most arithmetic instructions.
3703 A signed 16 bit immediate for @code{stop}.
3706 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3709 An unsigned 7-bit constant whose 3 least significant bits are 0.
3712 An unsigned 3-bit constant for 16-byte rotates and shifts
3715 Call operand, reg, for indirect calls
3718 Call operand, symbol, for relative calls.
3721 Call operand, const_int, for absolute calls.
3724 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3727 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3730 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3733 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3737 @item TI C6X family---@file{config/c6x/constraints.md}
3740 Register file A (A0--A31).
3743 Register file B (B0--B31).
3746 Predicate registers in register file A (A0--A2 on C64X and
3747 higher, A1 and A2 otherwise).
3750 Predicate registers in register file B (B0--B2).
3753 A call-used register in register file B (B0--B9, B16--B31).
3756 Register file A, excluding predicate registers (A3--A31,
3757 plus A0 if not C64X or higher).
3760 Register file B, excluding predicate registers (B3--B31).
3763 Integer constant in the range 0 @dots{} 15.
3766 Integer constant in the range 0 @dots{} 31.
3769 Integer constant in the range @minus{}31 @dots{} 0.
3772 Integer constant in the range @minus{}16 @dots{} 15.
3775 Integer constant that can be the operand of an ADDA or a SUBA insn.
3778 Integer constant in the range 0 @dots{} 65535.
3781 Integer constant in the range @minus{}32768 @dots{} 32767.
3784 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3787 Integer constant that is a valid mask for the clr instruction.
3790 Integer constant that is a valid mask for the set instruction.
3793 Memory location with A base register.
3796 Memory location with B base register.
3800 On C64x+ targets, a GP-relative small data reference.
3803 Any kind of @code{SYMBOL_REF}, for use in a call address.
3806 Any kind of immediate operand, unless it matches the S0 constraint.
3809 Memory location with B base register, but not using a long offset.
3812 A memory operand with an address that cannot be used in an unaligned access.
3816 Register B14 (aka DP).
3820 @item TILE-Gx---@file{config/tilegx/constraints.md}
3833 Each of these represents a register constraint for an individual
3834 register, from r0 to r10.
3837 Signed 8-bit integer constant.
3840 Signed 16-bit integer constant.
3843 Unsigned 16-bit integer constant.
3846 Integer constant that fits in one signed byte when incremented by one
3847 (@minus{}129 @dots{} 126).
3850 Memory operand. If used together with @samp{<} or @samp{>}, the
3851 operand can have postincrement which requires printing with @samp{%In}
3852 and @samp{%in} on TILE-Gx. For example:
3855 asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
3859 A bit mask suitable for the BFINS instruction.
3862 Integer constant that is a byte tiled out eight times.
3865 The integer zero constant.
3868 Integer constant that is a sign-extended byte tiled out as four shorts.
3871 Integer constant that fits in one signed byte when incremented
3872 (@minus{}129 @dots{} 126), but excluding -1.
3875 Integer constant that has all 1 bits consecutive and starting at bit 0.
3878 A 16-bit fragment of a got, tls, or pc-relative reference.
3881 Memory operand except postincrement. This is roughly the same as
3882 @samp{m} when not used together with @samp{<} or @samp{>}.
3885 An 8-element vector constant with identical elements.
3888 A 4-element vector constant with identical elements.
3891 The integer constant 0xffffffff.
3894 The integer constant 0xffffffff00000000.
3898 @item TILEPro---@file{config/tilepro/constraints.md}
3911 Each of these represents a register constraint for an individual
3912 register, from r0 to r10.
3915 Signed 8-bit integer constant.
3918 Signed 16-bit integer constant.
3921 Nonzero integer constant with low 16 bits zero.
3924 Integer constant that fits in one signed byte when incremented by one
3925 (@minus{}129 @dots{} 126).
3928 Memory operand. If used together with @samp{<} or @samp{>}, the
3929 operand can have postincrement which requires printing with @samp{%In}
3930 and @samp{%in} on TILEPro. For example:
3933 asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
3937 A bit mask suitable for the MM instruction.
3940 Integer constant that is a byte tiled out four times.
3943 The integer zero constant.
3946 Integer constant that is a sign-extended byte tiled out as two shorts.
3949 Integer constant that fits in one signed byte when incremented
3950 (@minus{}129 @dots{} 126), but excluding -1.
3953 A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
3957 Memory operand except postincrement. This is roughly the same as
3958 @samp{m} when not used together with @samp{<} or @samp{>}.
3961 A 4-element vector constant with identical elements.
3964 A 2-element vector constant with identical elements.
3968 @item Visium---@file{config/visium/constraints.md}
3971 EAM register @code{mdb}
3974 EAM register @code{mdc}
3977 Floating point register
3981 Register for sibcall optimization
3985 General register, but not @code{r29}, @code{r30} and @code{r31}
3997 Floating-point constant 0.0
4000 Integer constant in the range 0 .. 65535 (16-bit immediate)
4003 Integer constant in the range 1 .. 31 (5-bit immediate)
4006 Integer constant in the range @minus{}65535 .. @minus{}1 (16-bit negative immediate)
4009 Integer constant @minus{}1
4018 @item x86 family---@file{config/i386/constraints.md}
4021 Legacy register---the eight integer registers available on all
4022 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
4023 @code{si}, @code{di}, @code{bp}, @code{sp}).
4026 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
4027 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
4030 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
4031 @code{c}, and @code{d}.
4035 Any register that can be used as the index in a base+index memory
4036 access: that is, any general register except the stack pointer.
4040 The @code{a} register.
4043 The @code{b} register.
4046 The @code{c} register.
4049 The @code{d} register.
4052 The @code{si} register.
4055 The @code{di} register.
4058 The @code{a} and @code{d} registers. This class is used for instructions
4059 that return double word results in the @code{ax:dx} register pair. Single
4060 word values will be allocated either in @code{ax} or @code{dx}.
4061 For example on i386 the following implements @code{rdtsc}:
4064 unsigned long long rdtsc (void)
4066 unsigned long long tick;
4067 __asm__ __volatile__("rdtsc":"=A"(tick));
4072 This is not correct on x86-64 as it would allocate tick in either @code{ax}
4073 or @code{dx}. You have to use the following variant instead:
4076 unsigned long long rdtsc (void)
4078 unsigned int tickl, tickh;
4079 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
4080 return ((unsigned long long)tickh << 32)|tickl;
4085 The call-clobbered integer registers.
4088 Any 80387 floating-point (stack) register.
4091 Top of 80387 floating-point stack (@code{%st(0)}).
4094 Second from top of 80387 floating-point stack (@code{%st(1)}).
4098 Any mask register that can be used as a predicate, i.e. @code{k1-k7}.
4111 Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).
4119 First SSE register (@code{%xmm0}).
4123 Any SSE register, when SSE2 and inter-unit moves are enabled.
4126 Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.
4129 Any MMX register, when inter-unit moves are enabled.
4132 Any MMX register, when inter-unit moves from vector registers are enabled.
4135 Any integer register when @code{TARGET_PARTIAL_REG_STALL} is disabled.
4138 Any integer register when zero extensions with @code{AND} are disabled.
4141 Any register that can be used as the GOT base when calling@*
4142 @code{___tls_get_addr}: that is, any general register except @code{a}
4143 and @code{sp} registers, for @option{-fno-plt} if linker supports it.
4144 Otherwise, @code{b} register.
4147 Any x87 register when 80387 floating-point arithmetic is enabled.
4150 Lower SSE register when avoiding REX prefix and all SSE registers otherwise.
4153 For AVX512VL, any EVEX-encodable SSE register (@code{%xmm0-%xmm31}),
4154 otherwise any SSE register.
4157 Any EVEX-encodable SSE register, that has number factor of four.
4160 Flags register operand.
4166 Vector memory operand.
4169 Constant memory operand.
4172 Memory operand without REX prefix.
4175 Sibcall memory operand.
4178 Call memory operand.
4181 Constant call address operand.
4184 SSE constant -1 operand.
4188 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
4191 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
4194 Signed 8-bit integer constant.
4197 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
4200 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
4203 Unsigned 8-bit integer constant (for @code{in} and @code{out}
4208 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
4212 Standard 80387 floating point constant.
4215 SSE constant zero operand.
4218 32-bit signed integer constant, or a symbolic reference known
4219 to fit that range (for immediate operands in sign-extending x86-64
4223 32-bit signed integer constant, or a symbolic reference known
4224 to fit that range (for sign-extending conversion operations that
4225 require non-@code{VOIDmode} immediate operands).
4228 32-bit unsigned integer constant, or a symbolic reference known
4229 to fit that range (for zero-extending conversion operations that
4230 require non-@code{VOIDmode} immediate operands).
4233 128-bit integer constant where both the high and low 64-bit word
4234 satisfy the @code{e} constraint.
4237 32-bit unsigned integer constant, or a symbolic reference known
4238 to fit that range (for immediate operands in zero-extending x86-64
4242 VSIB address operand.
4245 Address operand without segment register.
4249 @item Xstormy16---@file{config/stormy16/stormy16.h}
4264 Registers r0 through r7.
4267 Registers r0 and r1.
4273 Registers r8 and r9.
4276 A constant between 0 and 3 inclusive.
4279 A constant that has exactly one bit set.
4282 A constant that has exactly one bit clear.
4285 A constant between 0 and 255 inclusive.
4288 A constant between @minus{}255 and 0 inclusive.
4291 A constant between @minus{}3 and 0 inclusive.
4294 A constant between 1 and 4 inclusive.
4297 A constant between @minus{}4 and @minus{}1 inclusive.
4300 A memory reference that is a stack push.
4303 A memory reference that is a stack pop.
4306 A memory reference that refers to a constant address of known value.
4309 The register indicated by Rx (not implemented yet).
4312 A constant that is not between 2 and 15 inclusive.
4319 @item Xtensa---@file{config/xtensa/constraints.md}
4322 General-purpose 32-bit register
4325 One-bit boolean register
4328 MAC16 40-bit accumulator register
4331 Signed 12-bit integer constant, for use in MOVI instructions
4334 Signed 8-bit integer constant, for use in ADDI instructions
4337 Integer constant valid for BccI instructions
4340 Unsigned constant valid for BccUI instructions
4347 @node Disable Insn Alternatives
4348 @subsection Disable insn alternatives using the @code{enabled} attribute
4351 There are three insn attributes that may be used to selectively disable
4352 instruction alternatives:
4356 Says whether an alternative is available on the current subtarget.
4358 @item preferred_for_size
4359 Says whether an enabled alternative should be used in code that is
4362 @item preferred_for_speed
4363 Says whether an enabled alternative should be used in code that is
4364 optimized for speed.
4367 All these attributes should use @code{(const_int 1)} to allow an alternative
4368 or @code{(const_int 0)} to disallow it. The attributes must be a static
4369 property of the subtarget; they cannot for example depend on the
4370 current operands, on the current optimization level, on the location
4371 of the insn within the body of a loop, on whether register allocation
4372 has finished, or on the current compiler pass.
4374 The @code{enabled} attribute is a correctness property. It tells GCC to act
4375 as though the disabled alternatives were never defined in the first place.
4376 This is useful when adding new instructions to an existing pattern in
4377 cases where the new instructions are only available for certain cpu
4378 architecture levels (typically mapped to the @code{-march=} command-line
4381 In contrast, the @code{preferred_for_size} and @code{preferred_for_speed}
4382 attributes are strong optimization hints rather than correctness properties.
4383 @code{preferred_for_size} tells GCC which alternatives to consider when
4384 adding or modifying an instruction that GCC wants to optimize for size.
4385 @code{preferred_for_speed} does the same thing for speed. Note that things
4386 like code motion can lead to cases where code optimized for size uses
4387 alternatives that are not preferred for size, and similarly for speed.
4389 Although @code{define_insn}s can in principle specify the @code{enabled}
4390 attribute directly, it is often clearer to have subsiduary attributes
4391 for each architectural feature of interest. The @code{define_insn}s
4392 can then use these subsiduary attributes to say which alternatives
4393 require which features. The example below does this for @code{cpu_facility}.
4395 E.g. the following two patterns could easily be merged using the @code{enabled}
4400 (define_insn "*movdi_old"
4401 [(set (match_operand:DI 0 "register_operand" "=d")
4402 (match_operand:DI 1 "register_operand" " d"))]
4406 (define_insn "*movdi_new"
4407 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4408 (match_operand:DI 1 "register_operand" " d,d,f"))]
4421 (define_insn "*movdi_combined"
4422 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4423 (match_operand:DI 1 "register_operand" " d,d,f"))]
4429 [(set_attr "cpu_facility" "*,new,new")])
4433 with the @code{enabled} attribute defined like this:
4437 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
4439 (define_attr "enabled" ""
4440 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
4441 (and (eq_attr "cpu_facility" "new")
4442 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
4451 @node Define Constraints
4452 @subsection Defining Machine-Specific Constraints
4453 @cindex defining constraints
4454 @cindex constraints, defining
4456 Machine-specific constraints fall into two categories: register and
4457 non-register constraints. Within the latter category, constraints
4458 which allow subsets of all possible memory or address operands should
4459 be specially marked, to give @code{reload} more information.
4461 Machine-specific constraints can be given names of arbitrary length,
4462 but they must be entirely composed of letters, digits, underscores
4463 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
4464 must begin with a letter or underscore.
4466 In order to avoid ambiguity in operand constraint strings, no
4467 constraint can have a name that begins with any other constraint's
4468 name. For example, if @code{x} is defined as a constraint name,
4469 @code{xy} may not be, and vice versa. As a consequence of this rule,
4470 no constraint may begin with one of the generic constraint letters:
4471 @samp{E F V X g i m n o p r s}.
4473 Register constraints correspond directly to register classes.
4474 @xref{Register Classes}. There is thus not much flexibility in their
4477 @deffn {MD Expression} define_register_constraint name regclass docstring
4478 All three arguments are string constants.
4479 @var{name} is the name of the constraint, as it will appear in
4480 @code{match_operand} expressions. If @var{name} is a multi-letter
4481 constraint its length shall be the same for all constraints starting
4482 with the same letter. @var{regclass} can be either the
4483 name of the corresponding register class (@pxref{Register Classes}),
4484 or a C expression which evaluates to the appropriate register class.
4485 If it is an expression, it must have no side effects, and it cannot
4486 look at the operand. The usual use of expressions is to map some
4487 register constraints to @code{NO_REGS} when the register class
4488 is not available on a given subarchitecture.
4490 @var{docstring} is a sentence documenting the meaning of the
4491 constraint. Docstrings are explained further below.
4494 Non-register constraints are more like predicates: the constraint
4495 definition gives a boolean expression which indicates whether the
4498 @deffn {MD Expression} define_constraint name docstring exp
4499 The @var{name} and @var{docstring} arguments are the same as for
4500 @code{define_register_constraint}, but note that the docstring comes
4501 immediately after the name for these expressions. @var{exp} is an RTL
4502 expression, obeying the same rules as the RTL expressions in predicate
4503 definitions. @xref{Defining Predicates}, for details. If it
4504 evaluates true, the constraint matches; if it evaluates false, it
4505 doesn't. Constraint expressions should indicate which RTL codes they
4506 might match, just like predicate expressions.
4508 @code{match_test} C expressions have access to the
4509 following variables:
4513 The RTL object defining the operand.
4515 The machine mode of @var{op}.
4517 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
4519 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
4520 @code{const_double}.
4522 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
4523 @code{const_double}.
4525 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
4526 @code{const_double}.
4529 The @var{*val} variables should only be used once another piece of the
4530 expression has verified that @var{op} is the appropriate kind of RTL
4534 Most non-register constraints should be defined with
4535 @code{define_constraint}. The remaining two definition expressions
4536 are only appropriate for constraints that should be handled specially
4537 by @code{reload} if they fail to match.
4539 @deffn {MD Expression} define_memory_constraint name docstring exp
4540 Use this expression for constraints that match a subset of all memory
4541 operands: that is, @code{reload} can make them match by converting the
4542 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
4543 base register (from the register class specified by
4544 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
4546 For example, on the S/390, some instructions do not accept arbitrary
4547 memory references, but only those that do not make use of an index
4548 register. The constraint letter @samp{Q} is defined to represent a
4549 memory address of this type. If @samp{Q} is defined with
4550 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
4551 memory operand, because @code{reload} knows it can simply copy the
4552 memory address into a base register if required. This is analogous to
4553 the way an @samp{o} constraint can handle any memory operand.
4555 The syntax and semantics are otherwise identical to
4556 @code{define_constraint}.
4559 @deffn {MD Expression} define_special_memory_constraint name docstring exp
4560 Use this expression for constraints that match a subset of all memory
4561 operands: that is, @code{reload} can not make them match by reloading
4562 the address as it is described for @code{define_memory_constraint} or
4563 such address reload is undesirable with the performance point of view.
4565 For example, @code{define_special_memory_constraint} can be useful if
4566 specifically aligned memory is necessary or desirable for some insn
4569 The syntax and semantics are otherwise identical to
4570 @code{define_constraint}.
4573 @deffn {MD Expression} define_address_constraint name docstring exp
4574 Use this expression for constraints that match a subset of all address
4575 operands: that is, @code{reload} can make the constraint match by
4576 converting the operand to the form @samp{@w{(reg @var{X})}}, again
4577 with @var{X} a base register.
4579 Constraints defined with @code{define_address_constraint} can only be
4580 used with the @code{address_operand} predicate, or machine-specific
4581 predicates that work the same way. They are treated analogously to
4582 the generic @samp{p} constraint.
4584 The syntax and semantics are otherwise identical to
4585 @code{define_constraint}.
4588 For historical reasons, names beginning with the letters @samp{G H}
4589 are reserved for constraints that match only @code{const_double}s, and
4590 names beginning with the letters @samp{I J K L M N O P} are reserved
4591 for constraints that match only @code{const_int}s. This may change in
4592 the future. For the time being, constraints with these names must be
4593 written in a stylized form, so that @code{genpreds} can tell you did
4598 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
4600 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
4601 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
4604 @c the semicolons line up in the formatted manual
4606 It is fine to use names beginning with other letters for constraints
4607 that match @code{const_double}s or @code{const_int}s.
4609 Each docstring in a constraint definition should be one or more complete
4610 sentences, marked up in Texinfo format. @emph{They are currently unused.}
4611 In the future they will be copied into the GCC manual, in @ref{Machine
4612 Constraints}, replacing the hand-maintained tables currently found in
4613 that section. Also, in the future the compiler may use this to give
4614 more helpful diagnostics when poor choice of @code{asm} constraints
4615 causes a reload failure.
4617 If you put the pseudo-Texinfo directive @samp{@@internal} at the
4618 beginning of a docstring, then (in the future) it will appear only in
4619 the internals manual's version of the machine-specific constraint tables.
4620 Use this for constraints that should not appear in @code{asm} statements.
4622 @node C Constraint Interface
4623 @subsection Testing constraints from C
4624 @cindex testing constraints
4625 @cindex constraints, testing
4627 It is occasionally useful to test a constraint from C code rather than
4628 implicitly via the constraint string in a @code{match_operand}. The
4629 generated file @file{tm_p.h} declares a few interfaces for working
4630 with constraints. At present these are defined for all constraints
4631 except @code{g} (which is equivalent to @code{general_operand}).
4633 Some valid constraint names are not valid C identifiers, so there is a
4634 mangling scheme for referring to them from C@. Constraint names that
4635 do not contain angle brackets or underscores are left unchanged.
4636 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
4637 each @samp{>} with @samp{_g}. Here are some examples:
4639 @c the @c's prevent double blank lines in the printed manual.
4641 @multitable {Original} {Mangled}
4642 @item @strong{Original} @tab @strong{Mangled} @c
4643 @item @code{x} @tab @code{x} @c
4644 @item @code{P42x} @tab @code{P42x} @c
4645 @item @code{P4_x} @tab @code{P4__x} @c
4646 @item @code{P4>x} @tab @code{P4_gx} @c
4647 @item @code{P4>>} @tab @code{P4_g_g} @c
4648 @item @code{P4_g>} @tab @code{P4__g_g} @c
4652 Throughout this section, the variable @var{c} is either a constraint
4653 in the abstract sense, or a constant from @code{enum constraint_num};
4654 the variable @var{m} is a mangled constraint name (usually as part of
4655 a larger identifier).
4657 @deftp Enum constraint_num
4658 For each constraint except @code{g}, there is a corresponding
4659 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
4660 constraint. Functions that take an @code{enum constraint_num} as an
4661 argument expect one of these constants.
4664 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
4665 For each non-register constraint @var{m} except @code{g}, there is
4666 one of these functions; it returns @code{true} if @var{exp} satisfies the
4667 constraint. These functions are only visible if @file{rtl.h} was included
4668 before @file{tm_p.h}.
4671 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
4672 Like the @code{satisfies_constraint_@var{m}} functions, but the
4673 constraint to test is given as an argument, @var{c}. If @var{c}
4674 specifies a register constraint, this function will always return
4678 @deftypefun {enum reg_class} reg_class_for_constraint (enum constraint_num @var{c})
4679 Returns the register class associated with @var{c}. If @var{c} is not
4680 a register constraint, or those registers are not available for the
4681 currently selected subtarget, returns @code{NO_REGS}.
4684 Here is an example use of @code{satisfies_constraint_@var{m}}. In
4685 peephole optimizations (@pxref{Peephole Definitions}), operand
4686 constraint strings are ignored, so if there are relevant constraints,
4687 they must be tested in the C condition. In the example, the
4688 optimization is applied if operand 2 does @emph{not} satisfy the
4689 @samp{K} constraint. (This is a simplified version of a peephole
4690 definition from the i386 machine description.)
4694 [(match_scratch:SI 3 "r")
4695 (set (match_operand:SI 0 "register_operand" "")
4696 (mult:SI (match_operand:SI 1 "memory_operand" "")
4697 (match_operand:SI 2 "immediate_operand" "")))]
4699 "!satisfies_constraint_K (operands[2])"
4701 [(set (match_dup 3) (match_dup 1))
4702 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
4707 @node Standard Names
4708 @section Standard Pattern Names For Generation
4709 @cindex standard pattern names
4710 @cindex pattern names
4711 @cindex names, pattern
4713 Here is a table of the instruction names that are meaningful in the RTL
4714 generation pass of the compiler. Giving one of these names to an
4715 instruction pattern tells the RTL generation pass that it can use the
4716 pattern to accomplish a certain task.
4719 @cindex @code{mov@var{m}} instruction pattern
4720 @item @samp{mov@var{m}}
4721 Here @var{m} stands for a two-letter machine mode name, in lowercase.
4722 This instruction pattern moves data with that machine mode from operand
4723 1 to operand 0. For example, @samp{movsi} moves full-word data.
4725 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
4726 own mode is wider than @var{m}, the effect of this instruction is
4727 to store the specified value in the part of the register that corresponds
4728 to mode @var{m}. Bits outside of @var{m}, but which are within the
4729 same target word as the @code{subreg} are undefined. Bits which are
4730 outside the target word are left unchanged.
4732 This class of patterns is special in several ways. First of all, each
4733 of these names up to and including full word size @emph{must} be defined,
4734 because there is no other way to copy a datum from one place to another.
4735 If there are patterns accepting operands in larger modes,
4736 @samp{mov@var{m}} must be defined for integer modes of those sizes.
4738 Second, these patterns are not used solely in the RTL generation pass.
4739 Even the reload pass can generate move insns to copy values from stack
4740 slots into temporary registers. When it does so, one of the operands is
4741 a hard register and the other is an operand that can need to be reloaded
4745 Therefore, when given such a pair of operands, the pattern must generate
4746 RTL which needs no reloading and needs no temporary registers---no
4747 registers other than the operands. For example, if you support the
4748 pattern with a @code{define_expand}, then in such a case the
4749 @code{define_expand} mustn't call @code{force_reg} or any other such
4750 function which might generate new pseudo registers.
4752 This requirement exists even for subword modes on a RISC machine where
4753 fetching those modes from memory normally requires several insns and
4754 some temporary registers.
4756 @findex change_address
4757 During reload a memory reference with an invalid address may be passed
4758 as an operand. Such an address will be replaced with a valid address
4759 later in the reload pass. In this case, nothing may be done with the
4760 address except to use it as it stands. If it is copied, it will not be
4761 replaced with a valid address. No attempt should be made to make such
4762 an address into a valid address and no routine (such as
4763 @code{change_address}) that will do so may be called. Note that
4764 @code{general_operand} will fail when applied to such an address.
4766 @findex reload_in_progress
4767 The global variable @code{reload_in_progress} (which must be explicitly
4768 declared if required) can be used to determine whether such special
4769 handling is required.
4771 The variety of operands that have reloads depends on the rest of the
4772 machine description, but typically on a RISC machine these can only be
4773 pseudo registers that did not get hard registers, while on other
4774 machines explicit memory references will get optional reloads.
4776 If a scratch register is required to move an object to or from memory,
4777 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
4779 If there are cases which need scratch registers during or after reload,
4780 you must provide an appropriate secondary_reload target hook.
4782 @findex can_create_pseudo_p
4783 The macro @code{can_create_pseudo_p} can be used to determine if it
4784 is unsafe to create new pseudo registers. If this variable is nonzero, then
4785 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
4787 The constraints on a @samp{mov@var{m}} must permit moving any hard
4788 register to any other hard register provided that
4789 @code{TARGET_HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
4790 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
4793 It is obligatory to support floating point @samp{mov@var{m}}
4794 instructions into and out of any registers that can hold fixed point
4795 values, because unions and structures (which have modes @code{SImode} or
4796 @code{DImode}) can be in those registers and they may have floating
4799 There may also be a need to support fixed point @samp{mov@var{m}}
4800 instructions in and out of floating point registers. Unfortunately, I
4801 have forgotten why this was so, and I don't know whether it is still
4802 true. If @code{TARGET_HARD_REGNO_MODE_OK} rejects fixed point values in
4803 floating point registers, then the constraints of the fixed point
4804 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
4805 reload into a floating point register.
4807 @cindex @code{reload_in} instruction pattern
4808 @cindex @code{reload_out} instruction pattern
4809 @item @samp{reload_in@var{m}}
4810 @itemx @samp{reload_out@var{m}}
4811 These named patterns have been obsoleted by the target hook
4812 @code{secondary_reload}.
4814 Like @samp{mov@var{m}}, but used when a scratch register is required to
4815 move between operand 0 and operand 1. Operand 2 describes the scratch
4816 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
4817 macro in @pxref{Register Classes}.
4819 There are special restrictions on the form of the @code{match_operand}s
4820 used in these patterns. First, only the predicate for the reload
4821 operand is examined, i.e., @code{reload_in} examines operand 1, but not
4822 the predicates for operand 0 or 2. Second, there may be only one
4823 alternative in the constraints. Third, only a single register class
4824 letter may be used for the constraint; subsequent constraint letters
4825 are ignored. As a special exception, an empty constraint string
4826 matches the @code{ALL_REGS} register class. This may relieve ports
4827 of the burden of defining an @code{ALL_REGS} constraint letter just
4830 @cindex @code{movstrict@var{m}} instruction pattern
4831 @item @samp{movstrict@var{m}}
4832 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
4833 with mode @var{m} of a register whose natural mode is wider,
4834 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
4835 any of the register except the part which belongs to mode @var{m}.
4837 @cindex @code{movmisalign@var{m}} instruction pattern
4838 @item @samp{movmisalign@var{m}}
4839 This variant of a move pattern is designed to load or store a value
4840 from a memory address that is not naturally aligned for its mode.
4841 For a store, the memory will be in operand 0; for a load, the memory
4842 will be in operand 1. The other operand is guaranteed not to be a
4843 memory, so that it's easy to tell whether this is a load or store.
4845 This pattern is used by the autovectorizer, and when expanding a
4846 @code{MISALIGNED_INDIRECT_REF} expression.
4848 @cindex @code{load_multiple} instruction pattern
4849 @item @samp{load_multiple}
4850 Load several consecutive memory locations into consecutive registers.
4851 Operand 0 is the first of the consecutive registers, operand 1
4852 is the first memory location, and operand 2 is a constant: the
4853 number of consecutive registers.
4855 Define this only if the target machine really has such an instruction;
4856 do not define this if the most efficient way of loading consecutive
4857 registers from memory is to do them one at a time.
4859 On some machines, there are restrictions as to which consecutive
4860 registers can be stored into memory, such as particular starting or
4861 ending register numbers or only a range of valid counts. For those
4862 machines, use a @code{define_expand} (@pxref{Expander Definitions})
4863 and make the pattern fail if the restrictions are not met.
4865 Write the generated insn as a @code{parallel} with elements being a
4866 @code{set} of one register from the appropriate memory location (you may
4867 also need @code{use} or @code{clobber} elements). Use a
4868 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
4869 @file{rs6000.md} for examples of the use of this insn pattern.
4871 @cindex @samp{store_multiple} instruction pattern
4872 @item @samp{store_multiple}
4873 Similar to @samp{load_multiple}, but store several consecutive registers
4874 into consecutive memory locations. Operand 0 is the first of the
4875 consecutive memory locations, operand 1 is the first register, and
4876 operand 2 is a constant: the number of consecutive registers.
4878 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
4879 @item @samp{vec_load_lanes@var{m}@var{n}}
4880 Perform an interleaved load of several vectors from memory operand 1
4881 into register operand 0. Both operands have mode @var{m}. The register
4882 operand is viewed as holding consecutive vectors of mode @var{n},
4883 while the memory operand is a flat array that contains the same number
4884 of elements. The operation is equivalent to:
4887 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4888 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4889 for (i = 0; i < c; i++)
4890 operand0[i][j] = operand1[j * c + i];
4893 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
4894 from memory into a register of mode @samp{TI}@. The register
4895 contains two consecutive vectors of mode @samp{V4HI}@.
4897 This pattern can only be used if:
4899 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
4901 is true. GCC assumes that, if a target supports this kind of
4902 instruction for some mode @var{n}, it also supports unaligned
4903 loads for vectors of mode @var{n}.
4905 This pattern is not allowed to @code{FAIL}.
4907 @cindex @code{vec_mask_load_lanes@var{m}@var{n}} instruction pattern
4908 @item @samp{vec_mask_load_lanes@var{m}@var{n}}
4909 Like @samp{vec_load_lanes@var{m}@var{n}}, but takes an additional
4910 mask operand (operand 2) that specifies which elements of the destination
4911 vectors should be loaded. Other elements of the destination
4912 vectors are set to zero. The operation is equivalent to:
4915 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4916 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4918 for (i = 0; i < c; i++)
4919 operand0[i][j] = operand1[j * c + i];
4921 for (i = 0; i < c; i++)
4925 This pattern is not allowed to @code{FAIL}.
4927 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
4928 @item @samp{vec_store_lanes@var{m}@var{n}}
4929 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
4930 and register operands reversed. That is, the instruction is
4934 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4935 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4936 for (i = 0; i < c; i++)
4937 operand0[j * c + i] = operand1[i][j];
4940 for a memory operand 0 and register operand 1.
4942 This pattern is not allowed to @code{FAIL}.
4944 @cindex @code{vec_mask_store_lanes@var{m}@var{n}} instruction pattern
4945 @item @samp{vec_mask_store_lanes@var{m}@var{n}}
4946 Like @samp{vec_store_lanes@var{m}@var{n}}, but takes an additional
4947 mask operand (operand 2) that specifies which elements of the source
4948 vectors should be stored. The operation is equivalent to:
4951 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4952 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4954 for (i = 0; i < c; i++)
4955 operand0[j * c + i] = operand1[i][j];
4958 This pattern is not allowed to @code{FAIL}.
4960 @cindex @code{gather_load@var{m}} instruction pattern
4961 @item @samp{gather_load@var{m}}
4962 Load several separate memory locations into a vector of mode @var{m}.
4963 Operand 1 is a scalar base address and operand 2 is a vector of
4964 offsets from that base. Operand 0 is a destination vector with the
4965 same number of elements as the offset. For each element index @var{i}:
4969 extend the offset element @var{i} to address width, using zero
4970 extension if operand 3 is 1 and sign extension if operand 3 is zero;
4972 multiply the extended offset by operand 4;
4974 add the result to the base; and
4976 load the value at that address into element @var{i} of operand 0.
4979 The value of operand 3 does not matter if the offsets are already
4982 @cindex @code{mask_gather_load@var{m}} instruction pattern
4983 @item @samp{mask_gather_load@var{m}}
4984 Like @samp{gather_load@var{m}}, but takes an extra mask operand as
4985 operand 5. Bit @var{i} of the mask is set if element @var{i}
4986 of the result should be loaded from memory and clear if element @var{i}
4987 of the result should be set to zero.
4989 @cindex @code{scatter_store@var{m}} instruction pattern
4990 @item @samp{scatter_store@var{m}}
4991 Store a vector of mode @var{m} into several distinct memory locations.
4992 Operand 0 is a scalar base address and operand 1 is a vector of offsets
4993 from that base. Operand 4 is the vector of values that should be stored,
4994 which has the same number of elements as the offset. For each element
4999 extend the offset element @var{i} to address width, using zero
5000 extension if operand 2 is 1 and sign extension if operand 2 is zero;
5002 multiply the extended offset by operand 3;
5004 add the result to the base; and
5006 store element @var{i} of operand 4 to that address.
5009 The value of operand 2 does not matter if the offsets are already
5012 @cindex @code{mask_scatter_store@var{m}} instruction pattern
5013 @item @samp{mask_scatter_store@var{m}}
5014 Like @samp{scatter_store@var{m}}, but takes an extra mask operand as
5015 operand 5. Bit @var{i} of the mask is set if element @var{i}
5016 of the result should be stored to memory.
5018 @cindex @code{vec_set@var{m}} instruction pattern
5019 @item @samp{vec_set@var{m}}
5020 Set given field in the vector value. Operand 0 is the vector to modify,
5021 operand 1 is new value of field and operand 2 specify the field index.
5023 @cindex @code{vec_extract@var{m}@var{n}} instruction pattern
5024 @item @samp{vec_extract@var{m}@var{n}}
5025 Extract given field from the vector value. Operand 1 is the vector, operand 2
5026 specify field index and operand 0 place to store value into. The
5027 @var{n} mode is the mode of the field or vector of fields that should be
5028 extracted, should be either element mode of the vector mode @var{m}, or
5029 a vector mode with the same element mode and smaller number of elements.
5030 If @var{n} is a vector mode, the index is counted in units of that mode.
5032 @cindex @code{vec_init@var{m}@var{n}} instruction pattern
5033 @item @samp{vec_init@var{m}@var{n}}
5034 Initialize the vector to given values. Operand 0 is the vector to initialize
5035 and operand 1 is parallel containing values for individual fields. The
5036 @var{n} mode is the mode of the elements, should be either element mode of
5037 the vector mode @var{m}, or a vector mode with the same element mode and
5038 smaller number of elements.
5040 @cindex @code{vec_duplicate@var{m}} instruction pattern
5041 @item @samp{vec_duplicate@var{m}}
5042 Initialize vector output operand 0 so that each element has the value given
5043 by scalar input operand 1. The vector has mode @var{m} and the scalar has
5044 the mode appropriate for one element of @var{m}.
5046 This pattern only handles duplicates of non-constant inputs. Constant
5047 vectors go through the @code{mov@var{m}} pattern instead.
5049 This pattern is not allowed to @code{FAIL}.
5051 @cindex @code{vec_series@var{m}} instruction pattern
5052 @item @samp{vec_series@var{m}}
5053 Initialize vector output operand 0 so that element @var{i} is equal to
5054 operand 1 plus @var{i} times operand 2. In other words, create a linear
5055 series whose base value is operand 1 and whose step is operand 2.
5057 The vector output has mode @var{m} and the scalar inputs have the mode
5058 appropriate for one element of @var{m}. This pattern is not used for
5059 floating-point vectors, in order to avoid having to specify the
5060 rounding behavior for @var{i} > 1.
5062 This pattern is not allowed to @code{FAIL}.
5064 @cindex @code{while_ult@var{m}@var{n}} instruction pattern
5065 @item @code{while_ult@var{m}@var{n}}
5066 Set operand 0 to a mask that is true while incrementing operand 1
5067 gives a value that is less than operand 2. Operand 0 has mode @var{n}
5068 and operands 1 and 2 are scalar integers of mode @var{m}.
5069 The operation is equivalent to:
5072 operand0[0] = operand1 < operand2;
5073 for (i = 1; i < GET_MODE_NUNITS (@var{n}); i++)
5074 operand0[i] = operand0[i - 1] && (operand1 + i < operand2);
5077 @cindex @code{vec_cmp@var{m}@var{n}} instruction pattern
5078 @item @samp{vec_cmp@var{m}@var{n}}
5079 Output a vector comparison. Operand 0 of mode @var{n} is the destination for
5080 predicate in operand 1 which is a signed vector comparison with operands of
5081 mode @var{m} in operands 2 and 3. Predicate is computed by element-wise
5082 evaluation of the vector comparison with a truth value of all-ones and a false
5085 @cindex @code{vec_cmpu@var{m}@var{n}} instruction pattern
5086 @item @samp{vec_cmpu@var{m}@var{n}}
5087 Similar to @code{vec_cmp@var{m}@var{n}} but perform unsigned vector comparison.
5089 @cindex @code{vec_cmpeq@var{m}@var{n}} instruction pattern
5090 @item @samp{vec_cmpeq@var{m}@var{n}}
5091 Similar to @code{vec_cmp@var{m}@var{n}} but perform equality or non-equality
5092 vector comparison only. If @code{vec_cmp@var{m}@var{n}}
5093 or @code{vec_cmpu@var{m}@var{n}} instruction pattern is supported,
5094 it will be preferred over @code{vec_cmpeq@var{m}@var{n}}, so there is
5095 no need to define this instruction pattern if the others are supported.
5097 @cindex @code{vcond@var{m}@var{n}} instruction pattern
5098 @item @samp{vcond@var{m}@var{n}}
5099 Output a conditional vector move. Operand 0 is the destination to
5100 receive a combination of operand 1 and operand 2, which are of mode @var{m},
5101 dependent on the outcome of the predicate in operand 3 which is a signed
5102 vector comparison with operands of mode @var{n} in operands 4 and 5. The
5103 modes @var{m} and @var{n} should have the same size. Operand 0
5104 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
5105 where @var{msk} is computed by element-wise evaluation of the vector
5106 comparison with a truth value of all-ones and a false value of all-zeros.
5108 @cindex @code{vcondu@var{m}@var{n}} instruction pattern
5109 @item @samp{vcondu@var{m}@var{n}}
5110 Similar to @code{vcond@var{m}@var{n}} but performs unsigned vector
5113 @cindex @code{vcondeq@var{m}@var{n}} instruction pattern
5114 @item @samp{vcondeq@var{m}@var{n}}
5115 Similar to @code{vcond@var{m}@var{n}} but performs equality or
5116 non-equality vector comparison only. If @code{vcond@var{m}@var{n}}
5117 or @code{vcondu@var{m}@var{n}} instruction pattern is supported,
5118 it will be preferred over @code{vcondeq@var{m}@var{n}}, so there is
5119 no need to define this instruction pattern if the others are supported.
5121 @cindex @code{vcond_mask_@var{m}@var{n}} instruction pattern
5122 @item @samp{vcond_mask_@var{m}@var{n}}
5123 Similar to @code{vcond@var{m}@var{n}} but operand 3 holds a pre-computed
5124 result of vector comparison.
5126 @cindex @code{maskload@var{m}@var{n}} instruction pattern
5127 @item @samp{maskload@var{m}@var{n}}
5128 Perform a masked load of vector from memory operand 1 of mode @var{m}
5129 into register operand 0. Mask is provided in register operand 2 of
5132 This pattern is not allowed to @code{FAIL}.
5134 @cindex @code{maskstore@var{m}@var{n}} instruction pattern
5135 @item @samp{maskstore@var{m}@var{n}}
5136 Perform a masked store of vector from register operand 1 of mode @var{m}
5137 into memory operand 0. Mask is provided in register operand 2 of
5140 This pattern is not allowed to @code{FAIL}.
5142 @cindex @code{vec_perm@var{m}} instruction pattern
5143 @item @samp{vec_perm@var{m}}
5144 Output a (variable) vector permutation. Operand 0 is the destination
5145 to receive elements from operand 1 and operand 2, which are of mode
5146 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
5147 vector of the same width and number of elements as mode @var{m}.
5149 The input elements are numbered from 0 in operand 1 through
5150 @math{2*@var{N}-1} in operand 2. The elements of the selector must
5151 be computed modulo @math{2*@var{N}}. Note that if
5152 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
5153 with just operand 1 and selector elements modulo @var{N}.
5155 In order to make things easy for a number of targets, if there is no
5156 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
5157 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
5158 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
5161 See also @code{TARGET_VECTORIZER_VEC_PERM_CONST}, which performs
5162 the analogous operation for constant selectors.
5164 @cindex @code{push@var{m}1} instruction pattern
5165 @item @samp{push@var{m}1}
5166 Output a push instruction. Operand 0 is value to push. Used only when
5167 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
5168 missing and in such case an @code{mov} expander is used instead, with a
5169 @code{MEM} expression forming the push operation. The @code{mov} expander
5170 method is deprecated.
5172 @cindex @code{add@var{m}3} instruction pattern
5173 @item @samp{add@var{m}3}
5174 Add operand 2 and operand 1, storing the result in operand 0. All operands
5175 must have mode @var{m}. This can be used even on two-address machines, by
5176 means of constraints requiring operands 1 and 0 to be the same location.
5178 @cindex @code{ssadd@var{m}3} instruction pattern
5179 @cindex @code{usadd@var{m}3} instruction pattern
5180 @cindex @code{sub@var{m}3} instruction pattern
5181 @cindex @code{sssub@var{m}3} instruction pattern
5182 @cindex @code{ussub@var{m}3} instruction pattern
5183 @cindex @code{mul@var{m}3} instruction pattern
5184 @cindex @code{ssmul@var{m}3} instruction pattern
5185 @cindex @code{usmul@var{m}3} instruction pattern
5186 @cindex @code{div@var{m}3} instruction pattern
5187 @cindex @code{ssdiv@var{m}3} instruction pattern
5188 @cindex @code{udiv@var{m}3} instruction pattern
5189 @cindex @code{usdiv@var{m}3} instruction pattern
5190 @cindex @code{mod@var{m}3} instruction pattern
5191 @cindex @code{umod@var{m}3} instruction pattern
5192 @cindex @code{umin@var{m}3} instruction pattern
5193 @cindex @code{umax@var{m}3} instruction pattern
5194 @cindex @code{and@var{m}3} instruction pattern
5195 @cindex @code{ior@var{m}3} instruction pattern
5196 @cindex @code{xor@var{m}3} instruction pattern
5197 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
5198 @itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
5199 @itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
5200 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
5201 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
5202 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
5203 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
5204 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
5205 Similar, for other arithmetic operations.
5207 @cindex @code{addv@var{m}4} instruction pattern
5208 @item @samp{addv@var{m}4}
5209 Like @code{add@var{m}3} but takes a @code{code_label} as operand 3 and
5210 emits code to jump to it if signed overflow occurs during the addition.
5211 This pattern is used to implement the built-in functions performing
5212 signed integer addition with overflow checking.
5214 @cindex @code{subv@var{m}4} instruction pattern
5215 @cindex @code{mulv@var{m}4} instruction pattern
5216 @item @samp{subv@var{m}4}, @samp{mulv@var{m}4}
5217 Similar, for other signed arithmetic operations.
5219 @cindex @code{uaddv@var{m}4} instruction pattern
5220 @item @samp{uaddv@var{m}4}
5221 Like @code{addv@var{m}4} but for unsigned addition. That is to
5222 say, the operation is the same as signed addition but the jump
5223 is taken only on unsigned overflow.
5225 @cindex @code{usubv@var{m}4} instruction pattern
5226 @cindex @code{umulv@var{m}4} instruction pattern
5227 @item @samp{usubv@var{m}4}, @samp{umulv@var{m}4}
5228 Similar, for other unsigned arithmetic operations.
5230 @cindex @code{addptr@var{m}3} instruction pattern
5231 @item @samp{addptr@var{m}3}
5232 Like @code{add@var{m}3} but is guaranteed to only be used for address
5233 calculations. The expanded code is not allowed to clobber the
5234 condition code. It only needs to be defined if @code{add@var{m}3}
5235 sets the condition code. If adds used for address calculations and
5236 normal adds are not compatible it is required to expand a distinct
5237 pattern (e.g. using an unspec). The pattern is used by LRA to emit
5238 address calculations. @code{add@var{m}3} is used if
5239 @code{addptr@var{m}3} is not defined.
5241 @cindex @code{fma@var{m}4} instruction pattern
5242 @item @samp{fma@var{m}4}
5243 Multiply operand 2 and operand 1, then add operand 3, storing the
5244 result in operand 0 without doing an intermediate rounding step. All
5245 operands must have mode @var{m}. This pattern is used to implement
5246 the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from
5247 the ISO C99 standard.
5249 @cindex @code{fms@var{m}4} instruction pattern
5250 @item @samp{fms@var{m}4}
5251 Like @code{fma@var{m}4}, except operand 3 subtracted from the
5252 product instead of added to the product. This is represented
5256 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
5259 @cindex @code{fnma@var{m}4} instruction pattern
5260 @item @samp{fnma@var{m}4}
5261 Like @code{fma@var{m}4} except that the intermediate product
5262 is negated before being added to operand 3. This is represented
5266 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
5269 @cindex @code{fnms@var{m}4} instruction pattern
5270 @item @samp{fnms@var{m}4}
5271 Like @code{fms@var{m}4} except that the intermediate product
5272 is negated before subtracting operand 3. This is represented
5276 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
5279 @cindex @code{min@var{m}3} instruction pattern
5280 @cindex @code{max@var{m}3} instruction pattern
5281 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
5282 Signed minimum and maximum operations. When used with floating point,
5283 if both operands are zeros, or if either operand is @code{NaN}, then
5284 it is unspecified which of the two operands is returned as the result.
5286 @cindex @code{fmin@var{m}3} instruction pattern
5287 @cindex @code{fmax@var{m}3} instruction pattern
5288 @item @samp{fmin@var{m}3}, @samp{fmax@var{m}3}
5289 IEEE-conformant minimum and maximum operations. If one operand is a quiet
5290 @code{NaN}, then the other operand is returned. If both operands are quiet
5291 @code{NaN}, then a quiet @code{NaN} is returned. In the case when gcc supports
5292 signaling @code{NaN} (-fsignaling-nans) an invalid floating point exception is
5293 raised and a quiet @code{NaN} is returned.
5295 All operands have mode @var{m}, which is a scalar or vector
5296 floating-point mode. These patterns are not allowed to @code{FAIL}.
5298 @cindex @code{reduc_smin_scal_@var{m}} instruction pattern
5299 @cindex @code{reduc_smax_scal_@var{m}} instruction pattern
5300 @item @samp{reduc_smin_scal_@var{m}}, @samp{reduc_smax_scal_@var{m}}
5301 Find the signed minimum/maximum of the elements of a vector. The vector is
5302 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
5303 the elements of the input vector.
5305 @cindex @code{reduc_umin_scal_@var{m}} instruction pattern
5306 @cindex @code{reduc_umax_scal_@var{m}} instruction pattern
5307 @item @samp{reduc_umin_scal_@var{m}}, @samp{reduc_umax_scal_@var{m}}
5308 Find the unsigned minimum/maximum of the elements of a vector. The vector is
5309 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
5310 the elements of the input vector.
5312 @cindex @code{reduc_plus_scal_@var{m}} instruction pattern
5313 @item @samp{reduc_plus_scal_@var{m}}
5314 Compute the sum of the elements of a vector. The vector is operand 1, and
5315 operand 0 is the scalar result, with mode equal to the mode of the elements of
5318 @cindex @code{reduc_and_scal_@var{m}} instruction pattern
5319 @item @samp{reduc_and_scal_@var{m}}
5320 @cindex @code{reduc_ior_scal_@var{m}} instruction pattern
5321 @itemx @samp{reduc_ior_scal_@var{m}}
5322 @cindex @code{reduc_xor_scal_@var{m}} instruction pattern
5323 @itemx @samp{reduc_xor_scal_@var{m}}
5324 Compute the bitwise @code{AND}/@code{IOR}/@code{XOR} reduction of the elements
5325 of a vector of mode @var{m}. Operand 1 is the vector input and operand 0
5326 is the scalar result. The mode of the scalar result is the same as one
5329 @cindex @code{extract_last_@var{m}} instruction pattern
5330 @item @code{extract_last_@var{m}}
5331 Find the last set bit in mask operand 1 and extract the associated element
5332 of vector operand 2. Store the result in scalar operand 0. Operand 2
5333 has vector mode @var{m} while operand 0 has the mode appropriate for one
5334 element of @var{m}. Operand 1 has the usual mask mode for vectors of mode
5335 @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}.
5337 @cindex @code{fold_extract_last_@var{m}} instruction pattern
5338 @item @code{fold_extract_last_@var{m}}
5339 If any bits of mask operand 2 are set, find the last set bit, extract
5340 the associated element from vector operand 3, and store the result
5341 in operand 0. Store operand 1 in operand 0 otherwise. Operand 3
5342 has mode @var{m} and operands 0 and 1 have the mode appropriate for
5343 one element of @var{m}. Operand 2 has the usual mask mode for vectors
5344 of mode @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}.
5346 @cindex @code{fold_left_plus_@var{m}} instruction pattern
5347 @item @code{fold_left_plus_@var{m}}
5348 Take scalar operand 1 and successively add each element from vector
5349 operand 2. Store the result in scalar operand 0. The vector has
5350 mode @var{m} and the scalars have the mode appropriate for one
5351 element of @var{m}. The operation is strictly in-order: there is
5354 @cindex @code{sdot_prod@var{m}} instruction pattern
5355 @item @samp{sdot_prod@var{m}}
5356 @cindex @code{udot_prod@var{m}} instruction pattern
5357 @itemx @samp{udot_prod@var{m}}
5358 Compute the sum of the products of two signed/unsigned elements.
5359 Operand 1 and operand 2 are of the same mode. Their product, which is of a
5360 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
5361 wider than the mode of the product. The result is placed in operand 0, which
5362 is of the same mode as operand 3.
5364 @cindex @code{ssad@var{m}} instruction pattern
5365 @item @samp{ssad@var{m}}
5366 @cindex @code{usad@var{m}} instruction pattern
5367 @item @samp{usad@var{m}}
5368 Compute the sum of absolute differences of two signed/unsigned elements.
5369 Operand 1 and operand 2 are of the same mode. Their absolute difference, which
5370 is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
5371 equal or wider than the mode of the absolute difference. The result is placed
5372 in operand 0, which is of the same mode as operand 3.
5374 @cindex @code{widen_ssum@var{m3}} instruction pattern
5375 @item @samp{widen_ssum@var{m3}}
5376 @cindex @code{widen_usum@var{m3}} instruction pattern
5377 @itemx @samp{widen_usum@var{m3}}
5378 Operands 0 and 2 are of the same mode, which is wider than the mode of
5379 operand 1. Add operand 1 to operand 2 and place the widened result in
5380 operand 0. (This is used express accumulation of elements into an accumulator
5383 @cindex @code{vec_shl_insert_@var{m}} instruction pattern
5384 @item @samp{vec_shl_insert_@var{m}}
5385 Shift the elements in vector input operand 1 left one element (i.e.
5386 away from element 0) and fill the vacated element 0 with the scalar
5387 in operand 2. Store the result in vector output operand 0. Operands
5388 0 and 1 have mode @var{m} and operand 2 has the mode appropriate for
5389 one element of @var{m}.
5391 @cindex @code{vec_shr_@var{m}} instruction pattern
5392 @item @samp{vec_shr_@var{m}}
5393 Whole vector right shift in bits, i.e. towards element 0.
5394 Operand 1 is a vector to be shifted.
5395 Operand 2 is an integer shift amount in bits.
5396 Operand 0 is where the resulting shifted vector is stored.
5397 The output and input vectors should have the same modes.
5399 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
5400 @item @samp{vec_pack_trunc_@var{m}}
5401 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
5402 are vectors of the same mode having N integral or floating point elements
5403 of size S@. Operand 0 is the resulting vector in which 2*N elements of
5404 size N/2 are concatenated after narrowing them down using truncation.
5406 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
5407 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
5408 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
5409 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
5410 are vectors of the same mode having N integral elements of size S.
5411 Operand 0 is the resulting vector in which the elements of the two input
5412 vectors are concatenated after narrowing them down using signed/unsigned
5413 saturating arithmetic.
5415 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
5416 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
5417 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
5418 Narrow, convert to signed/unsigned integral type and merge the elements
5419 of two vectors. Operands 1 and 2 are vectors of the same mode having N
5420 floating point elements of size S@. Operand 0 is the resulting vector
5421 in which 2*N elements of size N/2 are concatenated.
5423 @cindex @code{vec_packs_float_@var{m}} instruction pattern
5424 @cindex @code{vec_packu_float_@var{m}} instruction pattern
5425 @item @samp{vec_packs_float_@var{m}}, @samp{vec_packu_float_@var{m}}
5426 Narrow, convert to floating point type and merge the elements
5427 of two vectors. Operands 1 and 2 are vectors of the same mode having N
5428 signed/unsigned integral elements of size S@. Operand 0 is the resulting vector
5429 in which 2*N elements of size N/2 are concatenated.
5431 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
5432 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
5433 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
5434 Extract and widen (promote) the high/low part of a vector of signed
5435 integral or floating point elements. The input vector (operand 1) has N
5436 elements of size S@. Widen (promote) the high/low elements of the vector
5437 using signed or floating point extension and place the resulting N/2
5438 values of size 2*S in the output vector (operand 0).
5440 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
5441 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
5442 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
5443 Extract and widen (promote) the high/low part of a vector of unsigned
5444 integral elements. The input vector (operand 1) has N elements of size S.
5445 Widen (promote) the high/low elements of the vector using zero extension and
5446 place the resulting N/2 values of size 2*S in the output vector (operand 0).
5448 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
5449 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
5450 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
5451 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
5452 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
5453 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
5454 Extract, convert to floating point type and widen the high/low part of a
5455 vector of signed/unsigned integral elements. The input vector (operand 1)
5456 has N elements of size S@. Convert the high/low elements of the vector using
5457 floating point conversion and place the resulting N/2 values of size 2*S in
5458 the output vector (operand 0).
5460 @cindex @code{vec_unpack_sfix_trunc_hi_@var{m}} instruction pattern
5461 @cindex @code{vec_unpack_sfix_trunc_lo_@var{m}} instruction pattern
5462 @cindex @code{vec_unpack_ufix_trunc_hi_@var{m}} instruction pattern
5463 @cindex @code{vec_unpack_ufix_trunc_lo_@var{m}} instruction pattern
5464 @item @samp{vec_unpack_sfix_trunc_hi_@var{m}},
5465 @itemx @samp{vec_unpack_sfix_trunc_lo_@var{m}}
5466 @itemx @samp{vec_unpack_ufix_trunc_hi_@var{m}}
5467 @itemx @samp{vec_unpack_ufix_trunc_lo_@var{m}}
5468 Extract, convert to signed/unsigned integer type and widen the high/low part of a
5469 vector of floating point elements. The input vector (operand 1)
5470 has N elements of size S@. Convert the high/low elements of the vector
5471 to integers and place the resulting N/2 values of size 2*S in
5472 the output vector (operand 0).
5474 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
5475 @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern
5476 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
5477 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
5478 @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern
5479 @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern
5480 @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern
5481 @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern
5482 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
5483 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
5484 @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}}
5485 @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}}
5486 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
5487 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
5488 or even/odd elements of the two vectors, and put the N/2 products of size 2*S
5489 in the output vector (operand 0). A target shouldn't implement even/odd pattern
5490 pair if it is less efficient than lo/hi one.
5492 @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
5493 @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
5494 @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
5495 @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
5496 @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
5497 @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
5498 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
5499 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
5500 the high/low elements of operand 1, and put the N/2 results of size 2*S in the
5501 output vector (operand 0).
5503 @cindex @code{mulhisi3} instruction pattern
5504 @item @samp{mulhisi3}
5505 Multiply operands 1 and 2, which have mode @code{HImode}, and store
5506 a @code{SImode} product in operand 0.
5508 @cindex @code{mulqihi3} instruction pattern
5509 @cindex @code{mulsidi3} instruction pattern
5510 @item @samp{mulqihi3}, @samp{mulsidi3}
5511 Similar widening-multiplication instructions of other widths.
5513 @cindex @code{umulqihi3} instruction pattern
5514 @cindex @code{umulhisi3} instruction pattern
5515 @cindex @code{umulsidi3} instruction pattern
5516 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
5517 Similar widening-multiplication instructions that do unsigned
5520 @cindex @code{usmulqihi3} instruction pattern
5521 @cindex @code{usmulhisi3} instruction pattern
5522 @cindex @code{usmulsidi3} instruction pattern
5523 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
5524 Similar widening-multiplication instructions that interpret the first
5525 operand as unsigned and the second operand as signed, then do a signed
5528 @cindex @code{smul@var{m}3_highpart} instruction pattern
5529 @item @samp{smul@var{m}3_highpart}
5530 Perform a signed multiplication of operands 1 and 2, which have mode
5531 @var{m}, and store the most significant half of the product in operand 0.
5532 The least significant half of the product is discarded.
5534 @cindex @code{umul@var{m}3_highpart} instruction pattern
5535 @item @samp{umul@var{m}3_highpart}
5536 Similar, but the multiplication is unsigned.
5538 @cindex @code{madd@var{m}@var{n}4} instruction pattern
5539 @item @samp{madd@var{m}@var{n}4}
5540 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
5541 operand 3, and store the result in operand 0. Operands 1 and 2
5542 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5543 Both modes must be integer or fixed-point modes and @var{n} must be twice
5544 the size of @var{m}.
5546 In other words, @code{madd@var{m}@var{n}4} is like
5547 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
5549 These instructions are not allowed to @code{FAIL}.
5551 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
5552 @item @samp{umadd@var{m}@var{n}4}
5553 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
5554 operands instead of sign-extending them.
5556 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
5557 @item @samp{ssmadd@var{m}@var{n}4}
5558 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
5561 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
5562 @item @samp{usmadd@var{m}@var{n}4}
5563 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
5564 unsigned-saturating.
5566 @cindex @code{msub@var{m}@var{n}4} instruction pattern
5567 @item @samp{msub@var{m}@var{n}4}
5568 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
5569 result from operand 3, and store the result in operand 0. Operands 1 and 2
5570 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5571 Both modes must be integer or fixed-point modes and @var{n} must be twice
5572 the size of @var{m}.
5574 In other words, @code{msub@var{m}@var{n}4} is like
5575 @code{mul@var{m}@var{n}3} except that it also subtracts the result
5578 These instructions are not allowed to @code{FAIL}.
5580 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
5581 @item @samp{umsub@var{m}@var{n}4}
5582 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
5583 operands instead of sign-extending them.
5585 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
5586 @item @samp{ssmsub@var{m}@var{n}4}
5587 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
5590 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
5591 @item @samp{usmsub@var{m}@var{n}4}
5592 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
5593 unsigned-saturating.
5595 @cindex @code{divmod@var{m}4} instruction pattern
5596 @item @samp{divmod@var{m}4}
5597 Signed division that produces both a quotient and a remainder.
5598 Operand 1 is divided by operand 2 to produce a quotient stored
5599 in operand 0 and a remainder stored in operand 3.
5601 For machines with an instruction that produces both a quotient and a
5602 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
5603 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
5604 allows optimization in the relatively common case when both the quotient
5605 and remainder are computed.
5607 If an instruction that just produces a quotient or just a remainder
5608 exists and is more efficient than the instruction that produces both,
5609 write the output routine of @samp{divmod@var{m}4} to call
5610 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
5611 quotient or remainder and generate the appropriate instruction.
5613 @cindex @code{udivmod@var{m}4} instruction pattern
5614 @item @samp{udivmod@var{m}4}
5615 Similar, but does unsigned division.
5617 @anchor{shift patterns}
5618 @cindex @code{ashl@var{m}3} instruction pattern
5619 @cindex @code{ssashl@var{m}3} instruction pattern
5620 @cindex @code{usashl@var{m}3} instruction pattern
5621 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
5622 Arithmetic-shift operand 1 left by a number of bits specified by operand
5623 2, and store the result in operand 0. Here @var{m} is the mode of
5624 operand 0 and operand 1; operand 2's mode is specified by the
5625 instruction pattern, and the compiler will convert the operand to that
5626 mode before generating the instruction. The shift or rotate expander
5627 or instruction pattern should explicitly specify the mode of the operand 2,
5628 it should never be @code{VOIDmode}. The meaning of out-of-range shift
5629 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
5630 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
5632 @cindex @code{ashr@var{m}3} instruction pattern
5633 @cindex @code{lshr@var{m}3} instruction pattern
5634 @cindex @code{rotl@var{m}3} instruction pattern
5635 @cindex @code{rotr@var{m}3} instruction pattern
5636 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
5637 Other shift and rotate instructions, analogous to the
5638 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
5640 @cindex @code{vashl@var{m}3} instruction pattern
5641 @cindex @code{vashr@var{m}3} instruction pattern
5642 @cindex @code{vlshr@var{m}3} instruction pattern
5643 @cindex @code{vrotl@var{m}3} instruction pattern
5644 @cindex @code{vrotr@var{m}3} instruction pattern
5645 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
5646 Vector shift and rotate instructions that take vectors as operand 2
5647 instead of a scalar type.
5649 @cindex @code{avg@var{m}3_floor} instruction pattern
5650 @cindex @code{uavg@var{m}3_floor} instruction pattern
5651 @item @samp{avg@var{m}3_floor}
5652 @itemx @samp{uavg@var{m}3_floor}
5653 Signed and unsigned average instructions. These instructions add
5654 operands 1 and 2 without truncation, divide the result by 2,
5655 round towards -Inf, and store the result in operand 0. This is
5656 equivalent to the C code:
5658 narrow op0, op1, op2;
5660 op0 = (narrow) (((wide) op1 + (wide) op2) >> 1);
5662 where the sign of @samp{narrow} determines whether this is a signed
5663 or unsigned operation.
5665 @cindex @code{avg@var{m}3_ceil} instruction pattern
5666 @cindex @code{uavg@var{m}3_ceil} instruction pattern
5667 @item @samp{avg@var{m}3_ceil}
5668 @itemx @samp{uavg@var{m}3_ceil}
5669 Like @samp{avg@var{m}3_floor} and @samp{uavg@var{m}3_floor}, but round
5670 towards +Inf. This is equivalent to the C code:
5672 narrow op0, op1, op2;
5674 op0 = (narrow) (((wide) op1 + (wide) op2 + 1) >> 1);
5677 @cindex @code{bswap@var{m}2} instruction pattern
5678 @item @samp{bswap@var{m}2}
5679 Reverse the order of bytes of operand 1 and store the result in operand 0.
5681 @cindex @code{neg@var{m}2} instruction pattern
5682 @cindex @code{ssneg@var{m}2} instruction pattern
5683 @cindex @code{usneg@var{m}2} instruction pattern
5684 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
5685 Negate operand 1 and store the result in operand 0.
5687 @cindex @code{negv@var{m}3} instruction pattern
5688 @item @samp{negv@var{m}3}
5689 Like @code{neg@var{m}2} but takes a @code{code_label} as operand 2 and
5690 emits code to jump to it if signed overflow occurs during the negation.
5692 @cindex @code{abs@var{m}2} instruction pattern
5693 @item @samp{abs@var{m}2}
5694 Store the absolute value of operand 1 into operand 0.
5696 @cindex @code{sqrt@var{m}2} instruction pattern
5697 @item @samp{sqrt@var{m}2}
5698 Store the square root of operand 1 into operand 0. Both operands have
5699 mode @var{m}, which is a scalar or vector floating-point mode.
5701 This pattern is not allowed to @code{FAIL}.
5703 @cindex @code{rsqrt@var{m}2} instruction pattern
5704 @item @samp{rsqrt@var{m}2}
5705 Store the reciprocal of the square root of operand 1 into operand 0.
5706 Both operands have mode @var{m}, which is a scalar or vector
5707 floating-point mode.
5709 On most architectures this pattern is only approximate, so either
5710 its C condition or the @code{TARGET_OPTAB_SUPPORTED_P} hook should
5711 check for the appropriate math flags. (Using the C condition is
5712 more direct, but using @code{TARGET_OPTAB_SUPPORTED_P} can be useful
5713 if a target-specific built-in also uses the @samp{rsqrt@var{m}2}
5716 This pattern is not allowed to @code{FAIL}.
5718 @cindex @code{fmod@var{m}3} instruction pattern
5719 @item @samp{fmod@var{m}3}
5720 Store the remainder of dividing operand 1 by operand 2 into
5721 operand 0, rounded towards zero to an integer. All operands have
5722 mode @var{m}, which is a scalar or vector floating-point mode.
5724 This pattern is not allowed to @code{FAIL}.
5726 @cindex @code{remainder@var{m}3} instruction pattern
5727 @item @samp{remainder@var{m}3}
5728 Store the remainder of dividing operand 1 by operand 2 into
5729 operand 0, rounded to the nearest integer. All operands have
5730 mode @var{m}, which is a scalar or vector floating-point mode.
5732 This pattern is not allowed to @code{FAIL}.
5734 @cindex @code{scalb@var{m}3} instruction pattern
5735 @item @samp{scalb@var{m}3}
5736 Raise @code{FLT_RADIX} to the power of operand 2, multiply it by
5737 operand 1, and store the result in operand 0. All operands have
5738 mode @var{m}, which is a scalar or vector floating-point mode.
5740 This pattern is not allowed to @code{FAIL}.
5742 @cindex @code{ldexp@var{m}3} instruction pattern
5743 @item @samp{ldexp@var{m}3}
5744 Raise 2 to the power of operand 2, multiply it by operand 1, and store
5745 the result in operand 0. Operands 0 and 1 have mode @var{m}, which is
5746 a scalar or vector floating-point mode. Operand 2's mode has
5747 the same number of elements as @var{m} and each element is wide
5748 enough to store an @code{int}. The integers are signed.
5750 This pattern is not allowed to @code{FAIL}.
5752 @cindex @code{cos@var{m}2} instruction pattern
5753 @item @samp{cos@var{m}2}
5754 Store the cosine of operand 1 into operand 0. Both operands have
5755 mode @var{m}, which is a scalar or vector floating-point mode.
5757 This pattern is not allowed to @code{FAIL}.
5759 @cindex @code{sin@var{m}2} instruction pattern
5760 @item @samp{sin@var{m}2}
5761 Store the sine of operand 1 into operand 0. Both operands have
5762 mode @var{m}, which is a scalar or vector floating-point mode.
5764 This pattern is not allowed to @code{FAIL}.
5766 @cindex @code{sincos@var{m}3} instruction pattern
5767 @item @samp{sincos@var{m}3}
5768 Store the cosine of operand 2 into operand 0 and the sine of
5769 operand 2 into operand 1. All operands have mode @var{m},
5770 which is a scalar or vector floating-point mode.
5772 Targets that can calculate the sine and cosine simultaneously can
5773 implement this pattern as opposed to implementing individual
5774 @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin}
5775 and @code{cos} built-in functions will then be expanded to the
5776 @code{sincos@var{m}3} pattern, with one of the output values
5779 @cindex @code{tan@var{m}2} instruction pattern
5780 @item @samp{tan@var{m}2}
5781 Store the tangent of operand 1 into operand 0. Both operands have
5782 mode @var{m}, which is a scalar or vector floating-point mode.
5784 This pattern is not allowed to @code{FAIL}.
5786 @cindex @code{asin@var{m}2} instruction pattern
5787 @item @samp{asin@var{m}2}
5788 Store the arc sine of operand 1 into operand 0. Both operands have
5789 mode @var{m}, which is a scalar or vector floating-point mode.
5791 This pattern is not allowed to @code{FAIL}.
5793 @cindex @code{acos@var{m}2} instruction pattern
5794 @item @samp{acos@var{m}2}
5795 Store the arc cosine of operand 1 into operand 0. Both operands have
5796 mode @var{m}, which is a scalar or vector floating-point mode.
5798 This pattern is not allowed to @code{FAIL}.
5800 @cindex @code{atan@var{m}2} instruction pattern
5801 @item @samp{atan@var{m}2}
5802 Store the arc tangent of operand 1 into operand 0. Both operands have
5803 mode @var{m}, which is a scalar or vector floating-point mode.
5805 This pattern is not allowed to @code{FAIL}.
5807 @cindex @code{exp@var{m}2} instruction pattern
5808 @item @samp{exp@var{m}2}
5809 Raise e (the base of natural logarithms) to the power of operand 1
5810 and store the result in operand 0. Both operands have mode @var{m},
5811 which is a scalar or vector floating-point mode.
5813 This pattern is not allowed to @code{FAIL}.
5815 @cindex @code{expm1@var{m}2} instruction pattern
5816 @item @samp{expm1@var{m}2}
5817 Raise e (the base of natural logarithms) to the power of operand 1,
5818 subtract 1, and store the result in operand 0. Both operands have
5819 mode @var{m}, which is a scalar or vector floating-point mode.
5821 For inputs close to zero, the pattern is expected to be more
5822 accurate than a separate @code{exp@var{m}2} and @code{sub@var{m}3}
5825 This pattern is not allowed to @code{FAIL}.
5827 @cindex @code{exp10@var{m}2} instruction pattern
5828 @item @samp{exp10@var{m}2}
5829 Raise 10 to the power of operand 1 and store the result in operand 0.
5830 Both operands have mode @var{m}, which is a scalar or vector
5831 floating-point mode.
5833 This pattern is not allowed to @code{FAIL}.
5835 @cindex @code{exp2@var{m}2} instruction pattern
5836 @item @samp{exp2@var{m}2}
5837 Raise 2 to the power of operand 1 and store the result in operand 0.
5838 Both operands have mode @var{m}, which is a scalar or vector
5839 floating-point mode.
5841 This pattern is not allowed to @code{FAIL}.
5843 @cindex @code{log@var{m}2} instruction pattern
5844 @item @samp{log@var{m}2}
5845 Store the natural logarithm of operand 1 into operand 0. Both operands
5846 have mode @var{m}, which is a scalar or vector floating-point mode.
5848 This pattern is not allowed to @code{FAIL}.
5850 @cindex @code{log1p@var{m}2} instruction pattern
5851 @item @samp{log1p@var{m}2}
5852 Add 1 to operand 1, compute the natural logarithm, and store
5853 the result in operand 0. Both operands have mode @var{m}, which is
5854 a scalar or vector floating-point mode.
5856 For inputs close to zero, the pattern is expected to be more
5857 accurate than a separate @code{add@var{m}3} and @code{log@var{m}2}
5860 This pattern is not allowed to @code{FAIL}.
5862 @cindex @code{log10@var{m}2} instruction pattern
5863 @item @samp{log10@var{m}2}
5864 Store the base-10 logarithm of operand 1 into operand 0. Both operands
5865 have mode @var{m}, which is a scalar or vector floating-point mode.
5867 This pattern is not allowed to @code{FAIL}.
5869 @cindex @code{log2@var{m}2} instruction pattern
5870 @item @samp{log2@var{m}2}
5871 Store the base-2 logarithm of operand 1 into operand 0. Both operands
5872 have mode @var{m}, which is a scalar or vector floating-point mode.
5874 This pattern is not allowed to @code{FAIL}.
5876 @cindex @code{logb@var{m}2} instruction pattern
5877 @item @samp{logb@var{m}2}
5878 Store the base-@code{FLT_RADIX} logarithm of operand 1 into operand 0.
5879 Both operands have mode @var{m}, which is a scalar or vector
5880 floating-point mode.
5882 This pattern is not allowed to @code{FAIL}.
5884 @cindex @code{significand@var{m}2} instruction pattern
5885 @item @samp{significand@var{m}2}
5886 Store the significand of floating-point operand 1 in operand 0.
5887 Both operands have mode @var{m}, which is a scalar or vector
5888 floating-point mode.
5890 This pattern is not allowed to @code{FAIL}.
5892 @cindex @code{pow@var{m}3} instruction pattern
5893 @item @samp{pow@var{m}3}
5894 Store the value of operand 1 raised to the exponent operand 2
5895 into operand 0. All operands have mode @var{m}, which is a scalar
5896 or vector floating-point mode.
5898 This pattern is not allowed to @code{FAIL}.
5900 @cindex @code{atan2@var{m}3} instruction pattern
5901 @item @samp{atan2@var{m}3}
5902 Store the arc tangent (inverse tangent) of operand 1 divided by
5903 operand 2 into operand 0, using the signs of both arguments to
5904 determine the quadrant of the result. All operands have mode
5905 @var{m}, which is a scalar or vector floating-point mode.
5907 This pattern is not allowed to @code{FAIL}.
5909 @cindex @code{floor@var{m}2} instruction pattern
5910 @item @samp{floor@var{m}2}
5911 Store the largest integral value not greater than operand 1 in operand 0.
5912 Both operands have mode @var{m}, which is a scalar or vector
5913 floating-point mode. If @option{-ffp-int-builtin-inexact} is in
5914 effect, the ``inexact'' exception may be raised for noninteger
5915 operands; otherwise, it may not.
5917 This pattern is not allowed to @code{FAIL}.
5919 @cindex @code{btrunc@var{m}2} instruction pattern
5920 @item @samp{btrunc@var{m}2}
5921 Round operand 1 to an integer, towards zero, and store the result in
5922 operand 0. Both operands have mode @var{m}, which is a scalar or
5923 vector floating-point mode. If @option{-ffp-int-builtin-inexact} is
5924 in effect, the ``inexact'' exception may be raised for noninteger
5925 operands; otherwise, it may not.
5927 This pattern is not allowed to @code{FAIL}.
5929 @cindex @code{round@var{m}2} instruction pattern
5930 @item @samp{round@var{m}2}
5931 Round operand 1 to the nearest integer, rounding away from zero in the
5932 event of a tie, and store the result in operand 0. Both operands have
5933 mode @var{m}, which is a scalar or vector floating-point mode. If
5934 @option{-ffp-int-builtin-inexact} is in effect, the ``inexact''
5935 exception may be raised for noninteger operands; otherwise, it may
5938 This pattern is not allowed to @code{FAIL}.
5940 @cindex @code{ceil@var{m}2} instruction pattern
5941 @item @samp{ceil@var{m}2}
5942 Store the smallest integral value not less than operand 1 in operand 0.
5943 Both operands have mode @var{m}, which is a scalar or vector
5944 floating-point mode. If @option{-ffp-int-builtin-inexact} is in
5945 effect, the ``inexact'' exception may be raised for noninteger
5946 operands; otherwise, it may not.
5948 This pattern is not allowed to @code{FAIL}.
5950 @cindex @code{nearbyint@var{m}2} instruction pattern
5951 @item @samp{nearbyint@var{m}2}
5952 Round operand 1 to an integer, using the current rounding mode, and
5953 store the result in operand 0. Do not raise an inexact condition when
5954 the result is different from the argument. Both operands have mode
5955 @var{m}, which is a scalar or vector floating-point mode.
5957 This pattern is not allowed to @code{FAIL}.
5959 @cindex @code{rint@var{m}2} instruction pattern
5960 @item @samp{rint@var{m}2}
5961 Round operand 1 to an integer, using the current rounding mode, and
5962 store the result in operand 0. Raise an inexact condition when
5963 the result is different from the argument. Both operands have mode
5964 @var{m}, which is a scalar or vector floating-point mode.
5966 This pattern is not allowed to @code{FAIL}.
5968 @cindex @code{lrint@var{m}@var{n}2}
5969 @item @samp{lrint@var{m}@var{n}2}
5970 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5971 point mode @var{n} as a signed number according to the current
5972 rounding mode and store in operand 0 (which has mode @var{n}).
5974 @cindex @code{lround@var{m}@var{n}2}
5975 @item @samp{lround@var{m}@var{n}2}
5976 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5977 point mode @var{n} as a signed number rounding to nearest and away
5978 from zero and store in operand 0 (which has mode @var{n}).
5980 @cindex @code{lfloor@var{m}@var{n}2}
5981 @item @samp{lfloor@var{m}@var{n}2}
5982 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5983 point mode @var{n} as a signed number rounding down and store in
5984 operand 0 (which has mode @var{n}).
5986 @cindex @code{lceil@var{m}@var{n}2}
5987 @item @samp{lceil@var{m}@var{n}2}
5988 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5989 point mode @var{n} as a signed number rounding up and store in
5990 operand 0 (which has mode @var{n}).
5992 @cindex @code{copysign@var{m}3} instruction pattern
5993 @item @samp{copysign@var{m}3}
5994 Store a value with the magnitude of operand 1 and the sign of operand
5995 2 into operand 0. All operands have mode @var{m}, which is a scalar or
5996 vector floating-point mode.
5998 This pattern is not allowed to @code{FAIL}.
6000 @cindex @code{ffs@var{m}2} instruction pattern
6001 @item @samp{ffs@var{m}2}
6002 Store into operand 0 one plus the index of the least significant 1-bit
6003 of operand 1. If operand 1 is zero, store zero.
6005 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6006 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6007 integer mode is suitable for the target. The compiler will insert
6008 conversion instructions as necessary (typically to convert the result
6009 to the same width as @code{int}). When @var{m} is a vector, both
6010 operands must have mode @var{m}.
6012 This pattern is not allowed to @code{FAIL}.
6014 @cindex @code{clrsb@var{m}2} instruction pattern
6015 @item @samp{clrsb@var{m}2}
6016 Count leading redundant sign bits.
6017 Store into operand 0 the number of redundant sign bits in operand 1, starting
6018 at the most significant bit position.
6019 A redundant sign bit is defined as any sign bit after the first. As such,
6020 this count will be one less than the count of leading sign bits.
6022 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6023 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6024 integer mode is suitable for the target. The compiler will insert
6025 conversion instructions as necessary (typically to convert the result
6026 to the same width as @code{int}). When @var{m} is a vector, both
6027 operands must have mode @var{m}.
6029 This pattern is not allowed to @code{FAIL}.
6031 @cindex @code{clz@var{m}2} instruction pattern
6032 @item @samp{clz@var{m}2}
6033 Store into operand 0 the number of leading 0-bits in operand 1, starting
6034 at the most significant bit position. If operand 1 is 0, the
6035 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
6036 the result is undefined or has a useful value.
6038 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6039 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6040 integer mode is suitable for the target. The compiler will insert
6041 conversion instructions as necessary (typically to convert the result
6042 to the same width as @code{int}). When @var{m} is a vector, both
6043 operands must have mode @var{m}.
6045 This pattern is not allowed to @code{FAIL}.
6047 @cindex @code{ctz@var{m}2} instruction pattern
6048 @item @samp{ctz@var{m}2}
6049 Store into operand 0 the number of trailing 0-bits in operand 1, starting
6050 at the least significant bit position. If operand 1 is 0, the
6051 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
6052 the result is undefined or has a useful value.
6054 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6055 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6056 integer mode is suitable for the target. The compiler will insert
6057 conversion instructions as necessary (typically to convert the result
6058 to the same width as @code{int}). When @var{m} is a vector, both
6059 operands must have mode @var{m}.
6061 This pattern is not allowed to @code{FAIL}.
6063 @cindex @code{popcount@var{m}2} instruction pattern
6064 @item @samp{popcount@var{m}2}
6065 Store into operand 0 the number of 1-bits in operand 1.
6067 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6068 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6069 integer mode is suitable for the target. The compiler will insert
6070 conversion instructions as necessary (typically to convert the result
6071 to the same width as @code{int}). When @var{m} is a vector, both
6072 operands must have mode @var{m}.
6074 This pattern is not allowed to @code{FAIL}.
6076 @cindex @code{parity@var{m}2} instruction pattern
6077 @item @samp{parity@var{m}2}
6078 Store into operand 0 the parity of operand 1, i.e.@: the number of 1-bits
6079 in operand 1 modulo 2.
6081 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6082 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6083 integer mode is suitable for the target. The compiler will insert
6084 conversion instructions as necessary (typically to convert the result
6085 to the same width as @code{int}). When @var{m} is a vector, both
6086 operands must have mode @var{m}.
6088 This pattern is not allowed to @code{FAIL}.
6090 @cindex @code{one_cmpl@var{m}2} instruction pattern
6091 @item @samp{one_cmpl@var{m}2}
6092 Store the bitwise-complement of operand 1 into operand 0.
6094 @cindex @code{movmem@var{m}} instruction pattern
6095 @item @samp{movmem@var{m}}
6096 Block move instruction. The destination and source blocks of memory
6097 are the first two operands, and both are @code{mem:BLK}s with an
6098 address in mode @code{Pmode}.
6100 The number of bytes to move is the third operand, in mode @var{m}.
6101 Usually, you specify @code{Pmode} for @var{m}. However, if you can
6102 generate better code knowing the range of valid lengths is smaller than
6103 those representable in a full Pmode pointer, you should provide
6105 mode corresponding to the range of values you can handle efficiently
6106 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
6107 that appear negative) and also a pattern with @code{Pmode}.
6109 The fourth operand is the known shared alignment of the source and
6110 destination, in the form of a @code{const_int} rtx. Thus, if the
6111 compiler knows that both source and destination are word-aligned,
6112 it may provide the value 4 for this operand.
6114 Optional operands 5 and 6 specify expected alignment and size of block
6115 respectively. The expected alignment differs from alignment in operand 4
6116 in a way that the blocks are not required to be aligned according to it in
6117 all cases. This expected alignment is also in bytes, just like operand 4.
6118 Expected size, when unknown, is set to @code{(const_int -1)}.
6120 Descriptions of multiple @code{movmem@var{m}} patterns can only be
6121 beneficial if the patterns for smaller modes have fewer restrictions
6122 on their first, second and fourth operands. Note that the mode @var{m}
6123 in @code{movmem@var{m}} does not impose any restriction on the mode of
6124 individually moved data units in the block.
6126 These patterns need not give special consideration to the possibility
6127 that the source and destination strings might overlap.
6129 @cindex @code{movstr} instruction pattern
6131 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
6132 an output operand in mode @code{Pmode}. The addresses of the
6133 destination and source strings are operands 1 and 2, and both are
6134 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
6135 the expansion of this pattern should store in operand 0 the address in
6136 which the @code{NUL} terminator was stored in the destination string.
6138 This patern has also several optional operands that are same as in
6141 @cindex @code{setmem@var{m}} instruction pattern
6142 @item @samp{setmem@var{m}}
6143 Block set instruction. The destination string is the first operand,
6144 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
6145 number of bytes to set is the second operand, in mode @var{m}. The value to
6146 initialize the memory with is the third operand. Targets that only support the
6147 clearing of memory should reject any value that is not the constant 0. See
6148 @samp{movmem@var{m}} for a discussion of the choice of mode.
6150 The fourth operand is the known alignment of the destination, in the form
6151 of a @code{const_int} rtx. Thus, if the compiler knows that the
6152 destination is word-aligned, it may provide the value 4 for this
6155 Optional operands 5 and 6 specify expected alignment and size of block
6156 respectively. The expected alignment differs from alignment in operand 4
6157 in a way that the blocks are not required to be aligned according to it in
6158 all cases. This expected alignment is also in bytes, just like operand 4.
6159 Expected size, when unknown, is set to @code{(const_int -1)}.
6160 Operand 7 is the minimal size of the block and operand 8 is the
6161 maximal size of the block (NULL if it can not be represented as CONST_INT).
6162 Operand 9 is the probable maximal size (i.e. we can not rely on it for correctness,
6163 but it can be used for choosing proper code sequence for a given size).
6165 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
6167 @cindex @code{cmpstrn@var{m}} instruction pattern
6168 @item @samp{cmpstrn@var{m}}
6169 String compare instruction, with five operands. Operand 0 is the output;
6170 it has mode @var{m}. The remaining four operands are like the operands
6171 of @samp{movmem@var{m}}. The two memory blocks specified are compared
6172 byte by byte in lexicographic order starting at the beginning of each
6173 string. The instruction is not allowed to prefetch more than one byte
6174 at a time since either string may end in the first byte and reading past
6175 that may access an invalid page or segment and cause a fault. The
6176 comparison terminates early if the fetched bytes are different or if
6177 they are equal to zero. The effect of the instruction is to store a
6178 value in operand 0 whose sign indicates the result of the comparison.
6180 @cindex @code{cmpstr@var{m}} instruction pattern
6181 @item @samp{cmpstr@var{m}}
6182 String compare instruction, without known maximum length. Operand 0 is the
6183 output; it has mode @var{m}. The second and third operand are the blocks of
6184 memory to be compared; both are @code{mem:BLK} with an address in mode
6187 The fourth operand is the known shared alignment of the source and
6188 destination, in the form of a @code{const_int} rtx. Thus, if the
6189 compiler knows that both source and destination are word-aligned,
6190 it may provide the value 4 for this operand.
6192 The two memory blocks specified are compared byte by byte in lexicographic
6193 order starting at the beginning of each string. The instruction is not allowed
6194 to prefetch more than one byte at a time since either string may end in the
6195 first byte and reading past that may access an invalid page or segment and
6196 cause a fault. The comparison will terminate when the fetched bytes
6197 are different or if they are equal to zero. The effect of the
6198 instruction is to store a value in operand 0 whose sign indicates the
6199 result of the comparison.
6201 @cindex @code{cmpmem@var{m}} instruction pattern
6202 @item @samp{cmpmem@var{m}}
6203 Block compare instruction, with five operands like the operands
6204 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
6205 byte by byte in lexicographic order starting at the beginning of each
6206 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
6207 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
6208 the comparison will not stop if both bytes are zero. The effect of
6209 the instruction is to store a value in operand 0 whose sign indicates
6210 the result of the comparison.
6212 @cindex @code{strlen@var{m}} instruction pattern
6213 @item @samp{strlen@var{m}}
6214 Compute the length of a string, with three operands.
6215 Operand 0 is the result (of mode @var{m}), operand 1 is
6216 a @code{mem} referring to the first character of the string,
6217 operand 2 is the character to search for (normally zero),
6218 and operand 3 is a constant describing the known alignment
6219 of the beginning of the string.
6221 @cindex @code{float@var{m}@var{n}2} instruction pattern
6222 @item @samp{float@var{m}@var{n}2}
6223 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
6224 floating point mode @var{n} and store in operand 0 (which has mode
6227 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
6228 @item @samp{floatuns@var{m}@var{n}2}
6229 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
6230 to floating point mode @var{n} and store in operand 0 (which has mode
6233 @cindex @code{fix@var{m}@var{n}2} instruction pattern
6234 @item @samp{fix@var{m}@var{n}2}
6235 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6236 point mode @var{n} as a signed number and store in operand 0 (which
6237 has mode @var{n}). This instruction's result is defined only when
6238 the value of operand 1 is an integer.
6240 If the machine description defines this pattern, it also needs to
6241 define the @code{ftrunc} pattern.
6243 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
6244 @item @samp{fixuns@var{m}@var{n}2}
6245 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6246 point mode @var{n} as an unsigned number and store in operand 0 (which
6247 has mode @var{n}). This instruction's result is defined only when the
6248 value of operand 1 is an integer.
6250 @cindex @code{ftrunc@var{m}2} instruction pattern
6251 @item @samp{ftrunc@var{m}2}
6252 Convert operand 1 (valid for floating point mode @var{m}) to an
6253 integer value, still represented in floating point mode @var{m}, and
6254 store it in operand 0 (valid for floating point mode @var{m}).
6256 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
6257 @item @samp{fix_trunc@var{m}@var{n}2}
6258 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
6259 of mode @var{m} by converting the value to an integer.
6261 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
6262 @item @samp{fixuns_trunc@var{m}@var{n}2}
6263 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
6264 value of mode @var{m} by converting the value to an integer.
6266 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
6267 @item @samp{trunc@var{m}@var{n}2}
6268 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
6269 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6270 point or both floating point.
6272 @cindex @code{extend@var{m}@var{n}2} instruction pattern
6273 @item @samp{extend@var{m}@var{n}2}
6274 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
6275 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6276 point or both floating point.
6278 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
6279 @item @samp{zero_extend@var{m}@var{n}2}
6280 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
6281 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6284 @cindex @code{fract@var{m}@var{n}2} instruction pattern
6285 @item @samp{fract@var{m}@var{n}2}
6286 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6287 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6288 could be fixed-point to fixed-point, signed integer to fixed-point,
6289 fixed-point to signed integer, floating-point to fixed-point,
6290 or fixed-point to floating-point.
6291 When overflows or underflows happen, the results are undefined.
6293 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
6294 @item @samp{satfract@var{m}@var{n}2}
6295 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6296 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6297 could be fixed-point to fixed-point, signed integer to fixed-point,
6298 or floating-point to fixed-point.
6299 When overflows or underflows happen, the instruction saturates the
6300 results to the maximum or the minimum.
6302 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
6303 @item @samp{fractuns@var{m}@var{n}2}
6304 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6305 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6306 could be unsigned integer to fixed-point, or
6307 fixed-point to unsigned integer.
6308 When overflows or underflows happen, the results are undefined.
6310 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
6311 @item @samp{satfractuns@var{m}@var{n}2}
6312 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
6313 @var{n} and store in operand 0 (which has mode @var{n}).
6314 When overflows or underflows happen, the instruction saturates the
6315 results to the maximum or the minimum.
6317 @cindex @code{extv@var{m}} instruction pattern
6318 @item @samp{extv@var{m}}
6319 Extract a bit-field from register operand 1, sign-extend it, and store
6320 it in operand 0. Operand 2 specifies the width of the field in bits
6321 and operand 3 the starting bit, which counts from the most significant
6322 bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit
6325 Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a
6326 target-specific mode.
6328 @cindex @code{extvmisalign@var{m}} instruction pattern
6329 @item @samp{extvmisalign@var{m}}
6330 Extract a bit-field from memory operand 1, sign extend it, and store
6331 it in operand 0. Operand 2 specifies the width in bits and operand 3
6332 the starting bit. The starting bit is always somewhere in the first byte of
6333 operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6334 is true and from the least significant bit otherwise.
6336 Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode.
6337 Operands 2 and 3 have a target-specific mode.
6339 The instruction must not read beyond the last byte of the bit-field.
6341 @cindex @code{extzv@var{m}} instruction pattern
6342 @item @samp{extzv@var{m}}
6343 Like @samp{extv@var{m}} except that the bit-field value is zero-extended.
6345 @cindex @code{extzvmisalign@var{m}} instruction pattern
6346 @item @samp{extzvmisalign@var{m}}
6347 Like @samp{extvmisalign@var{m}} except that the bit-field value is
6350 @cindex @code{insv@var{m}} instruction pattern
6351 @item @samp{insv@var{m}}
6352 Insert operand 3 into a bit-field of register operand 0. Operand 1
6353 specifies the width of the field in bits and operand 2 the starting bit,
6354 which counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6355 is true and from the least significant bit otherwise.
6357 Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a
6358 target-specific mode.
6360 @cindex @code{insvmisalign@var{m}} instruction pattern
6361 @item @samp{insvmisalign@var{m}}
6362 Insert operand 3 into a bit-field of memory operand 0. Operand 1
6363 specifies the width of the field in bits and operand 2 the starting bit.
6364 The starting bit is always somewhere in the first byte of operand 0;
6365 it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6366 is true and from the least significant bit otherwise.
6368 Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode.
6369 Operands 1 and 2 have a target-specific mode.
6371 The instruction must not read or write beyond the last byte of the bit-field.
6373 @cindex @code{extv} instruction pattern
6375 Extract a bit-field from operand 1 (a register or memory operand), where
6376 operand 2 specifies the width in bits and operand 3 the starting bit,
6377 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
6378 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
6379 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
6380 be valid for @code{word_mode}.
6382 The RTL generation pass generates this instruction only with constants
6383 for operands 2 and 3 and the constant is never zero for operand 2.
6385 The bit-field value is sign-extended to a full word integer
6386 before it is stored in operand 0.
6388 This pattern is deprecated; please use @samp{extv@var{m}} and
6389 @code{extvmisalign@var{m}} instead.
6391 @cindex @code{extzv} instruction pattern
6393 Like @samp{extv} except that the bit-field value is zero-extended.
6395 This pattern is deprecated; please use @samp{extzv@var{m}} and
6396 @code{extzvmisalign@var{m}} instead.
6398 @cindex @code{insv} instruction pattern
6400 Store operand 3 (which must be valid for @code{word_mode}) into a
6401 bit-field in operand 0, where operand 1 specifies the width in bits and
6402 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
6403 @code{word_mode}; often @code{word_mode} is allowed only for registers.
6404 Operands 1 and 2 must be valid for @code{word_mode}.
6406 The RTL generation pass generates this instruction only with constants
6407 for operands 1 and 2 and the constant is never zero for operand 1.
6409 This pattern is deprecated; please use @samp{insv@var{m}} and
6410 @code{insvmisalign@var{m}} instead.
6412 @cindex @code{mov@var{mode}cc} instruction pattern
6413 @item @samp{mov@var{mode}cc}
6414 Conditionally move operand 2 or operand 3 into operand 0 according to the
6415 comparison in operand 1. If the comparison is true, operand 2 is moved
6416 into operand 0, otherwise operand 3 is moved.
6418 The mode of the operands being compared need not be the same as the operands
6419 being moved. Some machines, sparc64 for example, have instructions that
6420 conditionally move an integer value based on the floating point condition
6421 codes and vice versa.
6423 If the machine does not have conditional move instructions, do not
6424 define these patterns.
6426 @cindex @code{add@var{mode}cc} instruction pattern
6427 @item @samp{add@var{mode}cc}
6428 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
6429 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
6430 comparison in operand 1. If the comparison is false, operand 2 is moved into
6431 operand 0, otherwise (operand 2 + operand 3) is moved.
6433 @cindex @code{cond_add@var{mode}} instruction pattern
6434 @cindex @code{cond_sub@var{mode}} instruction pattern
6435 @cindex @code{cond_mul@var{mode}} instruction pattern
6436 @cindex @code{cond_div@var{mode}} instruction pattern
6437 @cindex @code{cond_udiv@var{mode}} instruction pattern
6438 @cindex @code{cond_mod@var{mode}} instruction pattern
6439 @cindex @code{cond_umod@var{mode}} instruction pattern
6440 @cindex @code{cond_and@var{mode}} instruction pattern
6441 @cindex @code{cond_ior@var{mode}} instruction pattern
6442 @cindex @code{cond_xor@var{mode}} instruction pattern
6443 @cindex @code{cond_smin@var{mode}} instruction pattern
6444 @cindex @code{cond_smax@var{mode}} instruction pattern
6445 @cindex @code{cond_umin@var{mode}} instruction pattern
6446 @cindex @code{cond_umax@var{mode}} instruction pattern
6447 @item @samp{cond_add@var{mode}}
6448 @itemx @samp{cond_sub@var{mode}}
6449 @itemx @samp{cond_mul@var{mode}}
6450 @itemx @samp{cond_div@var{mode}}
6451 @itemx @samp{cond_udiv@var{mode}}
6452 @itemx @samp{cond_mod@var{mode}}
6453 @itemx @samp{cond_umod@var{mode}}
6454 @itemx @samp{cond_and@var{mode}}
6455 @itemx @samp{cond_ior@var{mode}}
6456 @itemx @samp{cond_xor@var{mode}}
6457 @itemx @samp{cond_smin@var{mode}}
6458 @itemx @samp{cond_smax@var{mode}}
6459 @itemx @samp{cond_umin@var{mode}}
6460 @itemx @samp{cond_umax@var{mode}}
6461 When operand 1 is true, perform an operation on operands 2 and 3 and
6462 store the result in operand 0, otherwise store operand 4 in operand 0.
6463 The operation works elementwise if the operands are vectors.
6465 The scalar case is equivalent to:
6468 op0 = op1 ? op2 @var{op} op3 : op4;
6471 while the vector case is equivalent to:
6474 for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
6475 op0[i] = op1[i] ? op2[i] @var{op} op3[i] : op4[i];
6478 where, for example, @var{op} is @code{+} for @samp{cond_add@var{mode}}.
6480 When defined for floating-point modes, the contents of @samp{op3[i]}
6481 are not interpreted if @var{op1[i]} is false, just like they would not
6482 be in a normal C @samp{?:} condition.
6484 Operands 0, 2, 3 and 4 all have mode @var{m}. Operand 1 is a scalar
6485 integer if @var{m} is scalar, otherwise it has the mode returned by
6486 @code{TARGET_VECTORIZE_GET_MASK_MODE}.
6488 @cindex @code{cond_fma@var{mode}} instruction pattern
6489 @cindex @code{cond_fms@var{mode}} instruction pattern
6490 @cindex @code{cond_fnma@var{mode}} instruction pattern
6491 @cindex @code{cond_fnms@var{mode}} instruction pattern
6492 @item @samp{cond_fma@var{mode}}
6493 @itemx @samp{cond_fms@var{mode}}
6494 @itemx @samp{cond_fnma@var{mode}}
6495 @itemx @samp{cond_fnms@var{mode}}
6496 Like @samp{cond_add@var{m}}, except that the conditional operation
6497 takes 3 operands rather than two. For example, the vector form of
6498 @samp{cond_fma@var{mode}} is equivalent to:
6501 for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
6502 op0[i] = op1[i] ? fma (op2[i], op3[i], op4[i]) : op5[i];
6505 @cindex @code{neg@var{mode}cc} instruction pattern
6506 @item @samp{neg@var{mode}cc}
6507 Similar to @samp{mov@var{mode}cc} but for conditional negation. Conditionally
6508 move the negation of operand 2 or the unchanged operand 3 into operand 0
6509 according to the comparison in operand 1. If the comparison is true, the negation
6510 of operand 2 is moved into operand 0, otherwise operand 3 is moved.
6512 @cindex @code{not@var{mode}cc} instruction pattern
6513 @item @samp{not@var{mode}cc}
6514 Similar to @samp{neg@var{mode}cc} but for conditional complement.
6515 Conditionally move the bitwise complement of operand 2 or the unchanged
6516 operand 3 into operand 0 according to the comparison in operand 1.
6517 If the comparison is true, the complement of operand 2 is moved into
6518 operand 0, otherwise operand 3 is moved.
6520 @cindex @code{cstore@var{mode}4} instruction pattern
6521 @item @samp{cstore@var{mode}4}
6522 Store zero or nonzero in operand 0 according to whether a comparison
6523 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
6524 are the first and second operand of the comparison, respectively.
6525 You specify the mode that operand 0 must have when you write the
6526 @code{match_operand} expression. The compiler automatically sees which
6527 mode you have used and supplies an operand of that mode.
6529 The value stored for a true condition must have 1 as its low bit, or
6530 else must be negative. Otherwise the instruction is not suitable and
6531 you should omit it from the machine description. You describe to the
6532 compiler exactly which value is stored by defining the macro
6533 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
6534 found that can be used for all the possible comparison operators, you
6535 should pick one and use a @code{define_expand} to map all results
6536 onto the one you chose.
6538 These operations may @code{FAIL}, but should do so only in relatively
6539 uncommon cases; if they would @code{FAIL} for common cases involving
6540 integer comparisons, it is best to restrict the predicates to not
6541 allow these operands. Likewise if a given comparison operator will
6542 always fail, independent of the operands (for floating-point modes, the
6543 @code{ordered_comparison_operator} predicate is often useful in this case).
6545 If this pattern is omitted, the compiler will generate a conditional
6546 branch---for example, it may copy a constant one to the target and branching
6547 around an assignment of zero to the target---or a libcall. If the predicate
6548 for operand 1 only rejects some operators, it will also try reordering the
6549 operands and/or inverting the result value (e.g.@: by an exclusive OR).
6550 These possibilities could be cheaper or equivalent to the instructions
6551 used for the @samp{cstore@var{mode}4} pattern followed by those required
6552 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
6553 case, you can and should make operand 1's predicate reject some operators
6554 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
6555 from the machine description.
6557 @cindex @code{cbranch@var{mode}4} instruction pattern
6558 @item @samp{cbranch@var{mode}4}
6559 Conditional branch instruction combined with a compare instruction.
6560 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
6561 first and second operands of the comparison, respectively. Operand 3
6562 is the @code{code_label} to jump to.
6564 @cindex @code{jump} instruction pattern
6566 A jump inside a function; an unconditional branch. Operand 0 is the
6567 @code{code_label} to jump to. This pattern name is mandatory on all
6570 @cindex @code{call} instruction pattern
6572 Subroutine call instruction returning no value. Operand 0 is the
6573 function to call; operand 1 is the number of bytes of arguments pushed
6574 as a @code{const_int}; operand 2 is the number of registers used as
6577 On most machines, operand 2 is not actually stored into the RTL
6578 pattern. It is supplied for the sake of some RISC machines which need
6579 to put this information into the assembler code; they can put it in
6580 the RTL instead of operand 1.
6582 Operand 0 should be a @code{mem} RTX whose address is the address of the
6583 function. Note, however, that this address can be a @code{symbol_ref}
6584 expression even if it would not be a legitimate memory address on the
6585 target machine. If it is also not a valid argument for a call
6586 instruction, the pattern for this operation should be a
6587 @code{define_expand} (@pxref{Expander Definitions}) that places the
6588 address into a register and uses that register in the call instruction.
6590 @cindex @code{call_value} instruction pattern
6591 @item @samp{call_value}
6592 Subroutine call instruction returning a value. Operand 0 is the hard
6593 register in which the value is returned. There are three more
6594 operands, the same as the three operands of the @samp{call}
6595 instruction (but with numbers increased by one).
6597 Subroutines that return @code{BLKmode} objects use the @samp{call}
6600 @cindex @code{call_pop} instruction pattern
6601 @cindex @code{call_value_pop} instruction pattern
6602 @item @samp{call_pop}, @samp{call_value_pop}
6603 Similar to @samp{call} and @samp{call_value}, except used if defined and
6604 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
6605 that contains both the function call and a @code{set} to indicate the
6606 adjustment made to the frame pointer.
6608 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
6609 patterns increases the number of functions for which the frame pointer
6610 can be eliminated, if desired.
6612 @cindex @code{untyped_call} instruction pattern
6613 @item @samp{untyped_call}
6614 Subroutine call instruction returning a value of any type. Operand 0 is
6615 the function to call; operand 1 is a memory location where the result of
6616 calling the function is to be stored; operand 2 is a @code{parallel}
6617 expression where each element is a @code{set} expression that indicates
6618 the saving of a function return value into the result block.
6620 This instruction pattern should be defined to support
6621 @code{__builtin_apply} on machines where special instructions are needed
6622 to call a subroutine with arbitrary arguments or to save the value
6623 returned. This instruction pattern is required on machines that have
6624 multiple registers that can hold a return value
6625 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
6627 @cindex @code{return} instruction pattern
6629 Subroutine return instruction. This instruction pattern name should be
6630 defined only if a single instruction can do all the work of returning
6633 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
6634 RTL generation phase. In this case it is to support machines where
6635 multiple instructions are usually needed to return from a function, but
6636 some class of functions only requires one instruction to implement a
6637 return. Normally, the applicable functions are those which do not need
6638 to save any registers or allocate stack space.
6640 It is valid for this pattern to expand to an instruction using
6641 @code{simple_return} if no epilogue is required.
6643 @cindex @code{simple_return} instruction pattern
6644 @item @samp{simple_return}
6645 Subroutine return instruction. This instruction pattern name should be
6646 defined only if a single instruction can do all the work of returning
6647 from a function on a path where no epilogue is required. This pattern
6648 is very similar to the @code{return} instruction pattern, but it is emitted
6649 only by the shrink-wrapping optimization on paths where the function
6650 prologue has not been executed, and a function return should occur without
6651 any of the effects of the epilogue. Additional uses may be introduced on
6652 paths where both the prologue and the epilogue have executed.
6654 @findex reload_completed
6655 @findex leaf_function_p
6656 For such machines, the condition specified in this pattern should only
6657 be true when @code{reload_completed} is nonzero and the function's
6658 epilogue would only be a single instruction. For machines with register
6659 windows, the routine @code{leaf_function_p} may be used to determine if
6660 a register window push is required.
6662 Machines that have conditional return instructions should define patterns
6668 (if_then_else (match_operator
6669 0 "comparison_operator"
6670 [(cc0) (const_int 0)])
6677 where @var{condition} would normally be the same condition specified on the
6678 named @samp{return} pattern.
6680 @cindex @code{untyped_return} instruction pattern
6681 @item @samp{untyped_return}
6682 Untyped subroutine return instruction. This instruction pattern should
6683 be defined to support @code{__builtin_return} on machines where special
6684 instructions are needed to return a value of any type.
6686 Operand 0 is a memory location where the result of calling a function
6687 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
6688 expression where each element is a @code{set} expression that indicates
6689 the restoring of a function return value from the result block.
6691 @cindex @code{nop} instruction pattern
6693 No-op instruction. This instruction pattern name should always be defined
6694 to output a no-op in assembler code. @code{(const_int 0)} will do as an
6697 @cindex @code{indirect_jump} instruction pattern
6698 @item @samp{indirect_jump}
6699 An instruction to jump to an address which is operand zero.
6700 This pattern name is mandatory on all machines.
6702 @cindex @code{casesi} instruction pattern
6704 Instruction to jump through a dispatch table, including bounds checking.
6705 This instruction takes five operands:
6709 The index to dispatch on, which has mode @code{SImode}.
6712 The lower bound for indices in the table, an integer constant.
6715 The total range of indices in the table---the largest index
6716 minus the smallest one (both inclusive).
6719 A label that precedes the table itself.
6722 A label to jump to if the index has a value outside the bounds.
6725 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
6726 @code{jump_table_data}. The number of elements in the table is one plus the
6727 difference between the upper bound and the lower bound.
6729 @cindex @code{tablejump} instruction pattern
6730 @item @samp{tablejump}
6731 Instruction to jump to a variable address. This is a low-level
6732 capability which can be used to implement a dispatch table when there
6733 is no @samp{casesi} pattern.
6735 This pattern requires two operands: the address or offset, and a label
6736 which should immediately precede the jump table. If the macro
6737 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
6738 operand is an offset which counts from the address of the table; otherwise,
6739 it is an absolute address to jump to. In either case, the first operand has
6742 The @samp{tablejump} insn is always the last insn before the jump
6743 table it uses. Its assembler code normally has no need to use the
6744 second operand, but you should incorporate it in the RTL pattern so
6745 that the jump optimizer will not delete the table as unreachable code.
6748 @cindex @code{doloop_end} instruction pattern
6749 @item @samp{doloop_end}
6750 Conditional branch instruction that decrements a register and
6751 jumps if the register is nonzero. Operand 0 is the register to
6752 decrement and test; operand 1 is the label to jump to if the
6753 register is nonzero.
6754 @xref{Looping Patterns}.
6756 This optional instruction pattern should be defined for machines with
6757 low-overhead looping instructions as the loop optimizer will try to
6758 modify suitable loops to utilize it. The target hook
6759 @code{TARGET_CAN_USE_DOLOOP_P} controls the conditions under which
6760 low-overhead loops can be used.
6762 @cindex @code{doloop_begin} instruction pattern
6763 @item @samp{doloop_begin}
6764 Companion instruction to @code{doloop_end} required for machines that
6765 need to perform some initialization, such as loading a special counter
6766 register. Operand 1 is the associated @code{doloop_end} pattern and
6767 operand 0 is the register that it decrements.
6769 If initialization insns do not always need to be emitted, use a
6770 @code{define_expand} (@pxref{Expander Definitions}) and make it fail.
6772 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
6773 @item @samp{canonicalize_funcptr_for_compare}
6774 Canonicalize the function pointer in operand 1 and store the result
6777 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
6778 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
6779 and also has mode @code{Pmode}.
6781 Canonicalization of a function pointer usually involves computing
6782 the address of the function which would be called if the function
6783 pointer were used in an indirect call.
6785 Only define this pattern if function pointers on the target machine
6786 can have different values but still call the same function when
6787 used in an indirect call.
6789 @cindex @code{save_stack_block} instruction pattern
6790 @cindex @code{save_stack_function} instruction pattern
6791 @cindex @code{save_stack_nonlocal} instruction pattern
6792 @cindex @code{restore_stack_block} instruction pattern
6793 @cindex @code{restore_stack_function} instruction pattern
6794 @cindex @code{restore_stack_nonlocal} instruction pattern
6795 @item @samp{save_stack_block}
6796 @itemx @samp{save_stack_function}
6797 @itemx @samp{save_stack_nonlocal}
6798 @itemx @samp{restore_stack_block}
6799 @itemx @samp{restore_stack_function}
6800 @itemx @samp{restore_stack_nonlocal}
6801 Most machines save and restore the stack pointer by copying it to or
6802 from an object of mode @code{Pmode}. Do not define these patterns on
6805 Some machines require special handling for stack pointer saves and
6806 restores. On those machines, define the patterns corresponding to the
6807 non-standard cases by using a @code{define_expand} (@pxref{Expander
6808 Definitions}) that produces the required insns. The three types of
6809 saves and restores are:
6813 @samp{save_stack_block} saves the stack pointer at the start of a block
6814 that allocates a variable-sized object, and @samp{restore_stack_block}
6815 restores the stack pointer when the block is exited.
6818 @samp{save_stack_function} and @samp{restore_stack_function} do a
6819 similar job for the outermost block of a function and are used when the
6820 function allocates variable-sized objects or calls @code{alloca}. Only
6821 the epilogue uses the restored stack pointer, allowing a simpler save or
6822 restore sequence on some machines.
6825 @samp{save_stack_nonlocal} is used in functions that contain labels
6826 branched to by nested functions. It saves the stack pointer in such a
6827 way that the inner function can use @samp{restore_stack_nonlocal} to
6828 restore the stack pointer. The compiler generates code to restore the
6829 frame and argument pointer registers, but some machines require saving
6830 and restoring additional data such as register window information or
6831 stack backchains. Place insns in these patterns to save and restore any
6835 When saving the stack pointer, operand 0 is the save area and operand 1
6836 is the stack pointer. The mode used to allocate the save area defaults
6837 to @code{Pmode} but you can override that choice by defining the
6838 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
6839 specify an integral mode, or @code{VOIDmode} if no save area is needed
6840 for a particular type of save (either because no save is needed or
6841 because a machine-specific save area can be used). Operand 0 is the
6842 stack pointer and operand 1 is the save area for restore operations. If
6843 @samp{save_stack_block} is defined, operand 0 must not be
6844 @code{VOIDmode} since these saves can be arbitrarily nested.
6846 A save area is a @code{mem} that is at a constant offset from
6847 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
6848 nonlocal gotos and a @code{reg} in the other two cases.
6850 @cindex @code{allocate_stack} instruction pattern
6851 @item @samp{allocate_stack}
6852 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
6853 the stack pointer to create space for dynamically allocated data.
6855 Store the resultant pointer to this space into operand 0. If you
6856 are allocating space from the main stack, do this by emitting a
6857 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
6858 If you are allocating the space elsewhere, generate code to copy the
6859 location of the space to operand 0. In the latter case, you must
6860 ensure this space gets freed when the corresponding space on the main
6863 Do not define this pattern if all that must be done is the subtraction.
6864 Some machines require other operations such as stack probes or
6865 maintaining the back chain. Define this pattern to emit those
6866 operations in addition to updating the stack pointer.
6868 @cindex @code{check_stack} instruction pattern
6869 @item @samp{check_stack}
6870 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
6871 probing the stack, define this pattern to perform the needed check and signal
6872 an error if the stack has overflowed. The single operand is the address in
6873 the stack farthest from the current stack pointer that you need to validate.
6874 Normally, on platforms where this pattern is needed, you would obtain the
6875 stack limit from a global or thread-specific variable or register.
6877 @cindex @code{probe_stack_address} instruction pattern
6878 @item @samp{probe_stack_address}
6879 If stack checking (@pxref{Stack Checking}) can be done on your system by
6880 probing the stack but without the need to actually access it, define this
6881 pattern and signal an error if the stack has overflowed. The single operand
6882 is the memory address in the stack that needs to be probed.
6884 @cindex @code{probe_stack} instruction pattern
6885 @item @samp{probe_stack}
6886 If stack checking (@pxref{Stack Checking}) can be done on your system by
6887 probing the stack but doing it with a ``store zero'' instruction is not valid
6888 or optimal, define this pattern to do the probing differently and signal an
6889 error if the stack has overflowed. The single operand is the memory reference
6890 in the stack that needs to be probed.
6892 @cindex @code{nonlocal_goto} instruction pattern
6893 @item @samp{nonlocal_goto}
6894 Emit code to generate a non-local goto, e.g., a jump from one function
6895 to a label in an outer function. This pattern has four arguments,
6896 each representing a value to be used in the jump. The first
6897 argument is to be loaded into the frame pointer, the second is
6898 the address to branch to (code to dispatch to the actual label),
6899 the third is the address of a location where the stack is saved,
6900 and the last is the address of the label, to be placed in the
6901 location for the incoming static chain.
6903 On most machines you need not define this pattern, since GCC will
6904 already generate the correct code, which is to load the frame pointer
6905 and static chain, restore the stack (using the
6906 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
6907 to the dispatcher. You need only define this pattern if this code will
6908 not work on your machine.
6910 @cindex @code{nonlocal_goto_receiver} instruction pattern
6911 @item @samp{nonlocal_goto_receiver}
6912 This pattern, if defined, contains code needed at the target of a
6913 nonlocal goto after the code already generated by GCC@. You will not
6914 normally need to define this pattern. A typical reason why you might
6915 need this pattern is if some value, such as a pointer to a global table,
6916 must be restored when the frame pointer is restored. Note that a nonlocal
6917 goto only occurs within a unit-of-translation, so a global table pointer
6918 that is shared by all functions of a given module need not be restored.
6919 There are no arguments.
6921 @cindex @code{exception_receiver} instruction pattern
6922 @item @samp{exception_receiver}
6923 This pattern, if defined, contains code needed at the site of an
6924 exception handler that isn't needed at the site of a nonlocal goto. You
6925 will not normally need to define this pattern. A typical reason why you
6926 might need this pattern is if some value, such as a pointer to a global
6927 table, must be restored after control flow is branched to the handler of
6928 an exception. There are no arguments.
6930 @cindex @code{builtin_setjmp_setup} instruction pattern
6931 @item @samp{builtin_setjmp_setup}
6932 This pattern, if defined, contains additional code needed to initialize
6933 the @code{jmp_buf}. You will not normally need to define this pattern.
6934 A typical reason why you might need this pattern is if some value, such
6935 as a pointer to a global table, must be restored. Though it is
6936 preferred that the pointer value be recalculated if possible (given the
6937 address of a label for instance). The single argument is a pointer to
6938 the @code{jmp_buf}. Note that the buffer is five words long and that
6939 the first three are normally used by the generic mechanism.
6941 @cindex @code{builtin_setjmp_receiver} instruction pattern
6942 @item @samp{builtin_setjmp_receiver}
6943 This pattern, if defined, contains code needed at the site of a
6944 built-in setjmp that isn't needed at the site of a nonlocal goto. You
6945 will not normally need to define this pattern. A typical reason why you
6946 might need this pattern is if some value, such as a pointer to a global
6947 table, must be restored. It takes one argument, which is the label
6948 to which builtin_longjmp transferred control; this pattern may be emitted
6949 at a small offset from that label.
6951 @cindex @code{builtin_longjmp} instruction pattern
6952 @item @samp{builtin_longjmp}
6953 This pattern, if defined, performs the entire action of the longjmp.
6954 You will not normally need to define this pattern unless you also define
6955 @code{builtin_setjmp_setup}. The single argument is a pointer to the
6958 @cindex @code{eh_return} instruction pattern
6959 @item @samp{eh_return}
6960 This pattern, if defined, affects the way @code{__builtin_eh_return},
6961 and thence the call frame exception handling library routines, are
6962 built. It is intended to handle non-trivial actions needed along
6963 the abnormal return path.
6965 The address of the exception handler to which the function should return
6966 is passed as operand to this pattern. It will normally need to copied by
6967 the pattern to some special register or memory location.
6968 If the pattern needs to determine the location of the target call
6969 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
6970 if defined; it will have already been assigned.
6972 If this pattern is not defined, the default action will be to simply
6973 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
6974 that macro or this pattern needs to be defined if call frame exception
6975 handling is to be used.
6977 @cindex @code{prologue} instruction pattern
6978 @anchor{prologue instruction pattern}
6979 @item @samp{prologue}
6980 This pattern, if defined, emits RTL for entry to a function. The function
6981 entry is responsible for setting up the stack frame, initializing the frame
6982 pointer register, saving callee saved registers, etc.
6984 Using a prologue pattern is generally preferred over defining
6985 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
6987 The @code{prologue} pattern is particularly useful for targets which perform
6988 instruction scheduling.
6990 @cindex @code{window_save} instruction pattern
6991 @anchor{window_save instruction pattern}
6992 @item @samp{window_save}
6993 This pattern, if defined, emits RTL for a register window save. It should
6994 be defined if the target machine has register windows but the window events
6995 are decoupled from calls to subroutines. The canonical example is the SPARC
6998 @cindex @code{epilogue} instruction pattern
6999 @anchor{epilogue instruction pattern}
7000 @item @samp{epilogue}
7001 This pattern emits RTL for exit from a function. The function
7002 exit is responsible for deallocating the stack frame, restoring callee saved
7003 registers and emitting the return instruction.
7005 Using an epilogue pattern is generally preferred over defining
7006 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
7008 The @code{epilogue} pattern is particularly useful for targets which perform
7009 instruction scheduling or which have delay slots for their return instruction.
7011 @cindex @code{sibcall_epilogue} instruction pattern
7012 @item @samp{sibcall_epilogue}
7013 This pattern, if defined, emits RTL for exit from a function without the final
7014 branch back to the calling function. This pattern will be emitted before any
7015 sibling call (aka tail call) sites.
7017 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
7018 parameter passing or any stack slots for arguments passed to the current
7021 @cindex @code{trap} instruction pattern
7023 This pattern, if defined, signals an error, typically by causing some
7024 kind of signal to be raised.
7026 @cindex @code{ctrap@var{MM}4} instruction pattern
7027 @item @samp{ctrap@var{MM}4}
7028 Conditional trap instruction. Operand 0 is a piece of RTL which
7029 performs a comparison, and operands 1 and 2 are the arms of the
7030 comparison. Operand 3 is the trap code, an integer.
7032 A typical @code{ctrap} pattern looks like
7035 (define_insn "ctrapsi4"
7036 [(trap_if (match_operator 0 "trap_operator"
7037 [(match_operand 1 "register_operand")
7038 (match_operand 2 "immediate_operand")])
7039 (match_operand 3 "const_int_operand" "i"))]
7044 @cindex @code{prefetch} instruction pattern
7045 @item @samp{prefetch}
7046 This pattern, if defined, emits code for a non-faulting data prefetch
7047 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
7048 is a constant 1 if the prefetch is preparing for a write to the memory
7049 address, or a constant 0 otherwise. Operand 2 is the expected degree of
7050 temporal locality of the data and is a value between 0 and 3, inclusive; 0
7051 means that the data has no temporal locality, so it need not be left in the
7052 cache after the access; 3 means that the data has a high degree of temporal
7053 locality and should be left in all levels of cache possible; 1 and 2 mean,
7054 respectively, a low or moderate degree of temporal locality.
7056 Targets that do not support write prefetches or locality hints can ignore
7057 the values of operands 1 and 2.
7059 @cindex @code{blockage} instruction pattern
7060 @item @samp{blockage}
7061 This pattern defines a pseudo insn that prevents the instruction
7062 scheduler and other passes from moving instructions and using register
7063 equivalences across the boundary defined by the blockage insn.
7064 This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
7066 @cindex @code{memory_blockage} instruction pattern
7067 @item @samp{memory_blockage}
7068 This pattern, if defined, represents a compiler memory barrier, and will be
7069 placed at points across which RTL passes may not propagate memory accesses.
7070 This instruction needs to read and write volatile BLKmode memory. It does
7071 not need to generate any machine instruction. If this pattern is not defined,
7072 the compiler falls back to emitting an instruction corresponding
7073 to @code{asm volatile ("" ::: "memory")}.
7075 @cindex @code{memory_barrier} instruction pattern
7076 @item @samp{memory_barrier}
7077 If the target memory model is not fully synchronous, then this pattern
7078 should be defined to an instruction that orders both loads and stores
7079 before the instruction with respect to loads and stores after the instruction.
7080 This pattern has no operands.
7082 @cindex @code{speculation_barrier} instruction pattern
7083 @item @samp{speculation_barrier}
7084 If the target can support speculative execution, then this pattern should
7085 be defined to an instruction that will block subsequent execution until
7086 any prior speculation conditions has been resolved. The pattern must also
7087 ensure that the compiler cannot move memory operations past the barrier,
7088 so it needs to be an UNSPEC_VOLATILE pattern. The pattern has no
7091 If this pattern is not defined then the default expansion of
7092 @code{__builtin_speculation_safe_value} will emit a warning. You can
7093 suppress this warning by defining this pattern with a final condition
7094 of @code{0} (zero), which tells the compiler that a speculation
7095 barrier is not needed for this target.
7097 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
7098 @item @samp{sync_compare_and_swap@var{mode}}
7099 This pattern, if defined, emits code for an atomic compare-and-swap
7100 operation. Operand 1 is the memory on which the atomic operation is
7101 performed. Operand 2 is the ``old'' value to be compared against the
7102 current contents of the memory location. Operand 3 is the ``new'' value
7103 to store in the memory if the compare succeeds. Operand 0 is the result
7104 of the operation; it should contain the contents of the memory
7105 before the operation. If the compare succeeds, this should obviously be
7106 a copy of operand 2.
7108 This pattern must show that both operand 0 and operand 1 are modified.
7110 This pattern must issue any memory barrier instructions such that all
7111 memory operations before the atomic operation occur before the atomic
7112 operation and all memory operations after the atomic operation occur
7113 after the atomic operation.
7115 For targets where the success or failure of the compare-and-swap
7116 operation is available via the status flags, it is possible to
7117 avoid a separate compare operation and issue the subsequent
7118 branch or store-flag operation immediately after the compare-and-swap.
7119 To this end, GCC will look for a @code{MODE_CC} set in the
7120 output of @code{sync_compare_and_swap@var{mode}}; if the machine
7121 description includes such a set, the target should also define special
7122 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
7123 be able to take the destination of the @code{MODE_CC} set and pass it
7124 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
7125 operand of the comparison (the second will be @code{(const_int 0)}).
7127 For targets where the operating system may provide support for this
7128 operation via library calls, the @code{sync_compare_and_swap_optab}
7129 may be initialized to a function with the same interface as the
7130 @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire
7131 set of @var{__sync} builtins are supported via library calls, the
7132 target can initialize all of the optabs at once with
7133 @code{init_sync_libfuncs}.
7134 For the purposes of C++11 @code{std::atomic::is_lock_free}, it is
7135 assumed that these library calls do @emph{not} use any kind of
7136 interruptable locking.
7138 @cindex @code{sync_add@var{mode}} instruction pattern
7139 @cindex @code{sync_sub@var{mode}} instruction pattern
7140 @cindex @code{sync_ior@var{mode}} instruction pattern
7141 @cindex @code{sync_and@var{mode}} instruction pattern
7142 @cindex @code{sync_xor@var{mode}} instruction pattern
7143 @cindex @code{sync_nand@var{mode}} instruction pattern
7144 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
7145 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
7146 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
7147 These patterns emit code for an atomic operation on memory.
7148 Operand 0 is the memory on which the atomic operation is performed.
7149 Operand 1 is the second operand to the binary operator.
7151 This pattern must issue any memory barrier instructions such that all
7152 memory operations before the atomic operation occur before the atomic
7153 operation and all memory operations after the atomic operation occur
7154 after the atomic operation.
7156 If these patterns are not defined, the operation will be constructed
7157 from a compare-and-swap operation, if defined.
7159 @cindex @code{sync_old_add@var{mode}} instruction pattern
7160 @cindex @code{sync_old_sub@var{mode}} instruction pattern
7161 @cindex @code{sync_old_ior@var{mode}} instruction pattern
7162 @cindex @code{sync_old_and@var{mode}} instruction pattern
7163 @cindex @code{sync_old_xor@var{mode}} instruction pattern
7164 @cindex @code{sync_old_nand@var{mode}} instruction pattern
7165 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
7166 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
7167 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
7168 These patterns emit code for an atomic operation on memory,
7169 and return the value that the memory contained before the operation.
7170 Operand 0 is the result value, operand 1 is the memory on which the
7171 atomic operation is performed, and operand 2 is the second operand
7172 to the binary operator.
7174 This pattern must issue any memory barrier instructions such that all
7175 memory operations before the atomic operation occur before the atomic
7176 operation and all memory operations after the atomic operation occur
7177 after the atomic operation.
7179 If these patterns are not defined, the operation will be constructed
7180 from a compare-and-swap operation, if defined.
7182 @cindex @code{sync_new_add@var{mode}} instruction pattern
7183 @cindex @code{sync_new_sub@var{mode}} instruction pattern
7184 @cindex @code{sync_new_ior@var{mode}} instruction pattern
7185 @cindex @code{sync_new_and@var{mode}} instruction pattern
7186 @cindex @code{sync_new_xor@var{mode}} instruction pattern
7187 @cindex @code{sync_new_nand@var{mode}} instruction pattern
7188 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
7189 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
7190 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
7191 These patterns are like their @code{sync_old_@var{op}} counterparts,
7192 except that they return the value that exists in the memory location
7193 after the operation, rather than before the operation.
7195 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
7196 @item @samp{sync_lock_test_and_set@var{mode}}
7197 This pattern takes two forms, based on the capabilities of the target.
7198 In either case, operand 0 is the result of the operand, operand 1 is
7199 the memory on which the atomic operation is performed, and operand 2
7200 is the value to set in the lock.
7202 In the ideal case, this operation is an atomic exchange operation, in
7203 which the previous value in memory operand is copied into the result
7204 operand, and the value operand is stored in the memory operand.
7206 For less capable targets, any value operand that is not the constant 1
7207 should be rejected with @code{FAIL}. In this case the target may use
7208 an atomic test-and-set bit operation. The result operand should contain
7209 1 if the bit was previously set and 0 if the bit was previously clear.
7210 The true contents of the memory operand are implementation defined.
7212 This pattern must issue any memory barrier instructions such that the
7213 pattern as a whole acts as an acquire barrier, that is all memory
7214 operations after the pattern do not occur until the lock is acquired.
7216 If this pattern is not defined, the operation will be constructed from
7217 a compare-and-swap operation, if defined.
7219 @cindex @code{sync_lock_release@var{mode}} instruction pattern
7220 @item @samp{sync_lock_release@var{mode}}
7221 This pattern, if defined, releases a lock set by
7222 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
7223 that contains the lock; operand 1 is the value to store in the lock.
7225 If the target doesn't implement full semantics for
7226 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
7227 the constant 0 should be rejected with @code{FAIL}, and the true contents
7228 of the memory operand are implementation defined.
7230 This pattern must issue any memory barrier instructions such that the
7231 pattern as a whole acts as a release barrier, that is the lock is
7232 released only after all previous memory operations have completed.
7234 If this pattern is not defined, then a @code{memory_barrier} pattern
7235 will be emitted, followed by a store of the value to the memory operand.
7237 @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern
7238 @item @samp{atomic_compare_and_swap@var{mode}}
7239 This pattern, if defined, emits code for an atomic compare-and-swap
7240 operation with memory model semantics. Operand 2 is the memory on which
7241 the atomic operation is performed. Operand 0 is an output operand which
7242 is set to true or false based on whether the operation succeeded. Operand
7243 1 is an output operand which is set to the contents of the memory before
7244 the operation was attempted. Operand 3 is the value that is expected to
7245 be in memory. Operand 4 is the value to put in memory if the expected
7246 value is found there. Operand 5 is set to 1 if this compare and swap is to
7247 be treated as a weak operation. Operand 6 is the memory model to be used
7248 if the operation is a success. Operand 7 is the memory model to be used
7249 if the operation fails.
7251 If memory referred to in operand 2 contains the value in operand 3, then
7252 operand 4 is stored in memory pointed to by operand 2 and fencing based on
7253 the memory model in operand 6 is issued.
7255 If memory referred to in operand 2 does not contain the value in operand 3,
7256 then fencing based on the memory model in operand 7 is issued.
7258 If a target does not support weak compare-and-swap operations, or the port
7259 elects not to implement weak operations, the argument in operand 5 can be
7260 ignored. Note a strong implementation must be provided.
7262 If this pattern is not provided, the @code{__atomic_compare_exchange}
7263 built-in functions will utilize the legacy @code{sync_compare_and_swap}
7264 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
7266 @cindex @code{atomic_load@var{mode}} instruction pattern
7267 @item @samp{atomic_load@var{mode}}
7268 This pattern implements an atomic load operation with memory model
7269 semantics. Operand 1 is the memory address being loaded from. Operand 0
7270 is the result of the load. Operand 2 is the memory model to be used for
7273 If not present, the @code{__atomic_load} built-in function will either
7274 resort to a normal load with memory barriers, or a compare-and-swap
7275 operation if a normal load would not be atomic.
7277 @cindex @code{atomic_store@var{mode}} instruction pattern
7278 @item @samp{atomic_store@var{mode}}
7279 This pattern implements an atomic store operation with memory model
7280 semantics. Operand 0 is the memory address being stored to. Operand 1
7281 is the value to be written. Operand 2 is the memory model to be used for
7284 If not present, the @code{__atomic_store} built-in function will attempt to
7285 perform a normal store and surround it with any required memory fences. If
7286 the store would not be atomic, then an @code{__atomic_exchange} is
7287 attempted with the result being ignored.
7289 @cindex @code{atomic_exchange@var{mode}} instruction pattern
7290 @item @samp{atomic_exchange@var{mode}}
7291 This pattern implements an atomic exchange operation with memory model
7292 semantics. Operand 1 is the memory location the operation is performed on.
7293 Operand 0 is an output operand which is set to the original value contained
7294 in the memory pointed to by operand 1. Operand 2 is the value to be
7295 stored. Operand 3 is the memory model to be used.
7297 If this pattern is not present, the built-in function
7298 @code{__atomic_exchange} will attempt to preform the operation with a
7299 compare and swap loop.
7301 @cindex @code{atomic_add@var{mode}} instruction pattern
7302 @cindex @code{atomic_sub@var{mode}} instruction pattern
7303 @cindex @code{atomic_or@var{mode}} instruction pattern
7304 @cindex @code{atomic_and@var{mode}} instruction pattern
7305 @cindex @code{atomic_xor@var{mode}} instruction pattern
7306 @cindex @code{atomic_nand@var{mode}} instruction pattern
7307 @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}}
7308 @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}}
7309 @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}}
7310 These patterns emit code for an atomic operation on memory with memory
7311 model semantics. Operand 0 is the memory on which the atomic operation is
7312 performed. Operand 1 is the second operand to the binary operator.
7313 Operand 2 is the memory model to be used by the operation.
7315 If these patterns are not defined, attempts will be made to use legacy
7316 @code{sync} patterns, or equivalent patterns which return a result. If
7317 none of these are available a compare-and-swap loop will be used.
7319 @cindex @code{atomic_fetch_add@var{mode}} instruction pattern
7320 @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern
7321 @cindex @code{atomic_fetch_or@var{mode}} instruction pattern
7322 @cindex @code{atomic_fetch_and@var{mode}} instruction pattern
7323 @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern
7324 @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern
7325 @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}}
7326 @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}}
7327 @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}}
7328 These patterns emit code for an atomic operation on memory with memory
7329 model semantics, and return the original value. Operand 0 is an output
7330 operand which contains the value of the memory location before the
7331 operation was performed. Operand 1 is the memory on which the atomic
7332 operation is performed. Operand 2 is the second operand to the binary
7333 operator. Operand 3 is the memory model to be used by the operation.
7335 If these patterns are not defined, attempts will be made to use legacy
7336 @code{sync} patterns. If none of these are available a compare-and-swap
7339 @cindex @code{atomic_add_fetch@var{mode}} instruction pattern
7340 @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern
7341 @cindex @code{atomic_or_fetch@var{mode}} instruction pattern
7342 @cindex @code{atomic_and_fetch@var{mode}} instruction pattern
7343 @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern
7344 @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern
7345 @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}}
7346 @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}}
7347 @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}}
7348 These patterns emit code for an atomic operation on memory with memory
7349 model semantics and return the result after the operation is performed.
7350 Operand 0 is an output operand which contains the value after the
7351 operation. Operand 1 is the memory on which the atomic operation is
7352 performed. Operand 2 is the second operand to the binary operator.
7353 Operand 3 is the memory model to be used by the operation.
7355 If these patterns are not defined, attempts will be made to use legacy
7356 @code{sync} patterns, or equivalent patterns which return the result before
7357 the operation followed by the arithmetic operation required to produce the
7358 result. If none of these are available a compare-and-swap loop will be
7361 @cindex @code{atomic_test_and_set} instruction pattern
7362 @item @samp{atomic_test_and_set}
7363 This pattern emits code for @code{__builtin_atomic_test_and_set}.
7364 Operand 0 is an output operand which is set to true if the previous
7365 previous contents of the byte was "set", and false otherwise. Operand 1
7366 is the @code{QImode} memory to be modified. Operand 2 is the memory
7369 The specific value that defines "set" is implementation defined, and
7370 is normally based on what is performed by the native atomic test and set
7373 @cindex @code{atomic_bit_test_and_set@var{mode}} instruction pattern
7374 @cindex @code{atomic_bit_test_and_complement@var{mode}} instruction pattern
7375 @cindex @code{atomic_bit_test_and_reset@var{mode}} instruction pattern
7376 @item @samp{atomic_bit_test_and_set@var{mode}}
7377 @itemx @samp{atomic_bit_test_and_complement@var{mode}}
7378 @itemx @samp{atomic_bit_test_and_reset@var{mode}}
7379 These patterns emit code for an atomic bitwise operation on memory with memory
7380 model semantics, and return the original value of the specified bit.
7381 Operand 0 is an output operand which contains the value of the specified bit
7382 from the memory location before the operation was performed. Operand 1 is the
7383 memory on which the atomic operation is performed. Operand 2 is the bit within
7384 the operand, starting with least significant bit. Operand 3 is the memory model
7385 to be used by the operation. Operand 4 is a flag - it is @code{const1_rtx}
7386 if operand 0 should contain the original value of the specified bit in the
7387 least significant bit of the operand, and @code{const0_rtx} if the bit should
7388 be in its original position in the operand.
7389 @code{atomic_bit_test_and_set@var{mode}} atomically sets the specified bit after
7390 remembering its original value, @code{atomic_bit_test_and_complement@var{mode}}
7391 inverts the specified bit and @code{atomic_bit_test_and_reset@var{mode}} clears
7394 If these patterns are not defined, attempts will be made to use
7395 @code{atomic_fetch_or@var{mode}}, @code{atomic_fetch_xor@var{mode}} or
7396 @code{atomic_fetch_and@var{mode}} instruction patterns, or their @code{sync}
7397 counterparts. If none of these are available a compare-and-swap
7400 @cindex @code{mem_thread_fence} instruction pattern
7401 @item @samp{mem_thread_fence}
7402 This pattern emits code required to implement a thread fence with
7403 memory model semantics. Operand 0 is the memory model to be used.
7405 For the @code{__ATOMIC_RELAXED} model no instructions need to be issued
7406 and this expansion is not invoked.
7408 The compiler always emits a compiler memory barrier regardless of what
7409 expanding this pattern produced.
7411 If this pattern is not defined, the compiler falls back to expanding the
7412 @code{memory_barrier} pattern, then to emitting @code{__sync_synchronize}
7413 library call, and finally to just placing a compiler memory barrier.
7415 @cindex @code{get_thread_pointer@var{mode}} instruction pattern
7416 @cindex @code{set_thread_pointer@var{mode}} instruction pattern
7417 @item @samp{get_thread_pointer@var{mode}}
7418 @itemx @samp{set_thread_pointer@var{mode}}
7419 These patterns emit code that reads/sets the TLS thread pointer. Currently,
7420 these are only needed if the target needs to support the
7421 @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer}
7424 The get/set patterns have a single output/input operand respectively,
7425 with @var{mode} intended to be @code{Pmode}.
7427 @cindex @code{stack_protect_set} instruction pattern
7428 @item @samp{stack_protect_set}
7429 This pattern, if defined, moves a @code{ptr_mode} value from the memory
7430 in operand 1 to the memory in operand 0 without leaving the value in
7431 a register afterward. This is to avoid leaking the value some place
7432 that an attacker might use to rewrite the stack guard slot after
7433 having clobbered it.
7435 If this pattern is not defined, then a plain move pattern is generated.
7437 @cindex @code{stack_protect_test} instruction pattern
7438 @item @samp{stack_protect_test}
7439 This pattern, if defined, compares a @code{ptr_mode} value from the
7440 memory in operand 1 with the memory in operand 0 without leaving the
7441 value in a register afterward and branches to operand 2 if the values
7444 If this pattern is not defined, then a plain compare pattern and
7445 conditional branch pattern is used.
7447 @cindex @code{clear_cache} instruction pattern
7448 @item @samp{clear_cache}
7449 This pattern, if defined, flushes the instruction cache for a region of
7450 memory. The region is bounded to by the Pmode pointers in operand 0
7451 inclusive and operand 1 exclusive.
7453 If this pattern is not defined, a call to the library function
7454 @code{__clear_cache} is used.
7459 @c Each of the following nodes are wrapped in separate
7460 @c "@ifset INTERNALS" to work around memory limits for the default
7461 @c configuration in older tetex distributions. Known to not work:
7462 @c tetex-1.0.7, known to work: tetex-2.0.2.
7464 @node Pattern Ordering
7465 @section When the Order of Patterns Matters
7466 @cindex Pattern Ordering
7467 @cindex Ordering of Patterns
7469 Sometimes an insn can match more than one instruction pattern. Then the
7470 pattern that appears first in the machine description is the one used.
7471 Therefore, more specific patterns (patterns that will match fewer things)
7472 and faster instructions (those that will produce better code when they
7473 do match) should usually go first in the description.
7475 In some cases the effect of ordering the patterns can be used to hide
7476 a pattern when it is not valid. For example, the 68000 has an
7477 instruction for converting a fullword to floating point and another
7478 for converting a byte to floating point. An instruction converting
7479 an integer to floating point could match either one. We put the
7480 pattern to convert the fullword first to make sure that one will
7481 be used rather than the other. (Otherwise a large integer might
7482 be generated as a single-byte immediate quantity, which would not work.)
7483 Instead of using this pattern ordering it would be possible to make the
7484 pattern for convert-a-byte smart enough to deal properly with any
7489 @node Dependent Patterns
7490 @section Interdependence of Patterns
7491 @cindex Dependent Patterns
7492 @cindex Interdependence of Patterns
7494 In some cases machines support instructions identical except for the
7495 machine mode of one or more operands. For example, there may be
7496 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
7500 (set (match_operand:SI 0 @dots{})
7501 (extend:SI (match_operand:HI 1 @dots{})))
7503 (set (match_operand:SI 0 @dots{})
7504 (extend:SI (match_operand:QI 1 @dots{})))
7508 Constant integers do not specify a machine mode, so an instruction to
7509 extend a constant value could match either pattern. The pattern it
7510 actually will match is the one that appears first in the file. For correct
7511 results, this must be the one for the widest possible mode (@code{HImode},
7512 here). If the pattern matches the @code{QImode} instruction, the results
7513 will be incorrect if the constant value does not actually fit that mode.
7515 Such instructions to extend constants are rarely generated because they are
7516 optimized away, but they do occasionally happen in nonoptimized
7519 If a constraint in a pattern allows a constant, the reload pass may
7520 replace a register with a constant permitted by the constraint in some
7521 cases. Similarly for memory references. Because of this substitution,
7522 you should not provide separate patterns for increment and decrement
7523 instructions. Instead, they should be generated from the same pattern
7524 that supports register-register add insns by examining the operands and
7525 generating the appropriate machine instruction.
7530 @section Defining Jump Instruction Patterns
7531 @cindex jump instruction patterns
7532 @cindex defining jump instruction patterns
7534 GCC does not assume anything about how the machine realizes jumps.
7535 The machine description should define a single pattern, usually
7536 a @code{define_expand}, which expands to all the required insns.
7538 Usually, this would be a comparison insn to set the condition code
7539 and a separate branch insn testing the condition code and branching
7540 or not according to its value. For many machines, however,
7541 separating compares and branches is limiting, which is why the
7542 more flexible approach with one @code{define_expand} is used in GCC.
7543 The machine description becomes clearer for architectures that
7544 have compare-and-branch instructions but no condition code. It also
7545 works better when different sets of comparison operators are supported
7546 by different kinds of conditional branches (e.g. integer vs. floating-point),
7547 or by conditional branches with respect to conditional stores.
7549 Two separate insns are always used if the machine description represents
7550 a condition code register using the legacy RTL expression @code{(cc0)},
7551 and on most machines that use a separate condition code register
7552 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
7553 fact, the set and use of the condition code must be separate and
7554 adjacent@footnote{@code{note} insns can separate them, though.}, thus
7555 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
7556 so that the comparison and branch insns could be located from each other
7557 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
7559 Even in this case having a single entry point for conditional branches
7560 is advantageous, because it handles equally well the case where a single
7561 comparison instruction records the results of both signed and unsigned
7562 comparison of the given operands (with the branch insns coming in distinct
7563 signed and unsigned flavors) as in the x86 or SPARC, and the case where
7564 there are distinct signed and unsigned compare instructions and only
7565 one set of conditional branch instructions as in the PowerPC.
7569 @node Looping Patterns
7570 @section Defining Looping Instruction Patterns
7571 @cindex looping instruction patterns
7572 @cindex defining looping instruction patterns
7574 Some machines have special jump instructions that can be utilized to
7575 make loops more efficient. A common example is the 68000 @samp{dbra}
7576 instruction which performs a decrement of a register and a branch if the
7577 result was greater than zero. Other machines, in particular digital
7578 signal processors (DSPs), have special block repeat instructions to
7579 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
7580 DSPs have a block repeat instruction that loads special registers to
7581 mark the top and end of a loop and to count the number of loop
7582 iterations. This avoids the need for fetching and executing a
7583 @samp{dbra}-like instruction and avoids pipeline stalls associated with
7586 GCC has two special named patterns to support low overhead looping.
7587 They are @samp{doloop_begin} and @samp{doloop_end}. These are emitted
7588 by the loop optimizer for certain well-behaved loops with a finite
7589 number of loop iterations using information collected during strength
7592 The @samp{doloop_end} pattern describes the actual looping instruction
7593 (or the implicit looping operation) and the @samp{doloop_begin} pattern
7594 is an optional companion pattern that can be used for initialization
7595 needed for some low-overhead looping instructions.
7597 Note that some machines require the actual looping instruction to be
7598 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
7599 the true RTL for a looping instruction at the top of the loop can cause
7600 problems with flow analysis. So instead, a dummy @code{doloop} insn is
7601 emitted at the end of the loop. The machine dependent reorg pass checks
7602 for the presence of this @code{doloop} insn and then searches back to
7603 the top of the loop, where it inserts the true looping insn (provided
7604 there are no instructions in the loop which would cause problems). Any
7605 additional labels can be emitted at this point. In addition, if the
7606 desired special iteration counter register was not allocated, this
7607 machine dependent reorg pass could emit a traditional compare and jump
7610 For the @samp{doloop_end} pattern, the loop optimizer allocates an
7611 additional pseudo register as an iteration counter. This pseudo
7612 register cannot be used within the loop (i.e., general induction
7613 variables cannot be derived from it), however, in many cases the loop
7614 induction variable may become redundant and removed by the flow pass.
7616 The @samp{doloop_end} pattern must have a specific structure to be
7617 handled correctly by GCC. The example below is taken (slightly
7618 simplified) from the PDP-11 target:
7622 (define_insn "doloop_end"
7625 (ne (match_operand:HI 0 "nonimmediate_operand" "+r,!m")
7627 (label_ref (match_operand 1 "" ""))
7630 (plus:HI (match_dup 0)
7635 if (which_alternative == 0)
7636 return "sob %0,%l1";
7639 output_asm_insn ("dec %0", operands);
7645 The first part of the pattern describes the branch condition. GCC
7646 supports three cases for the way the target machine handles the loop
7649 @item Loop terminates when the loop register decrements to zero. This
7650 is represented by a @code{ne} comparison of the register (its old value)
7651 with constant 1 (as in the example above).
7652 @item Loop terminates when the loop register decrements to @minus{}1.
7653 This is represented by a @code{ne} comparison of the register with
7655 @item Loop terminates when the loop register decrements to a negative
7656 value. This is represented by a @code{ge} comparison of the register
7657 with constant zero. For this case, GCC will attach a @code{REG_NONNEG}
7658 note to the @code{doloop_end} insn if it can determine that the register
7659 will be non-negative.
7662 Since the @code{doloop_end} insn is a jump insn that also has an output,
7663 the reload pass does not handle the output operand. Therefore, the
7664 constraint must allow for that operand to be in memory rather than a
7665 register. In the example shown above, that is handled by using a loop
7666 instruction sequence that can handle memory operands when the memory
7667 alternative appears.
7671 @node Insn Canonicalizations
7672 @section Canonicalization of Instructions
7673 @cindex canonicalization of instructions
7674 @cindex insn canonicalization
7676 There are often cases where multiple RTL expressions could represent an
7677 operation performed by a single machine instruction. This situation is
7678 most commonly encountered with logical, branch, and multiply-accumulate
7679 instructions. In such cases, the compiler attempts to convert these
7680 multiple RTL expressions into a single canonical form to reduce the
7681 number of insn patterns required.
7683 In addition to algebraic simplifications, following canonicalizations
7688 For commutative and comparison operators, a constant is always made the
7689 second operand. If a machine only supports a constant as the second
7690 operand, only patterns that match a constant in the second operand need
7694 For associative operators, a sequence of operators will always chain
7695 to the left; for instance, only the left operand of an integer @code{plus}
7696 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
7697 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
7698 @code{umax} are associative when applied to integers, and sometimes to
7702 @cindex @code{neg}, canonicalization of
7703 @cindex @code{not}, canonicalization of
7704 @cindex @code{mult}, canonicalization of
7705 @cindex @code{plus}, canonicalization of
7706 @cindex @code{minus}, canonicalization of
7707 For these operators, if only one operand is a @code{neg}, @code{not},
7708 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
7712 In combinations of @code{neg}, @code{mult}, @code{plus}, and
7713 @code{minus}, the @code{neg} operations (if any) will be moved inside
7714 the operations as far as possible. For instance,
7715 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
7716 @code{(plus (mult (neg B) C) A)} is canonicalized as
7717 @code{(minus A (mult B C))}.
7719 @cindex @code{compare}, canonicalization of
7721 For the @code{compare} operator, a constant is always the second operand
7722 if the first argument is a condition code register or @code{(cc0)}.
7725 For instructions that inherently set a condition code register, the
7726 @code{compare} operator is always written as the first RTL expression of
7727 the @code{parallel} instruction pattern. For example,
7731 [(set (reg:CCZ FLAGS_REG)
7734 (match_operand:SI 1 "register_operand" "%r")
7735 (match_operand:SI 2 "register_operand" "r"))
7737 (set (match_operand:SI 0 "register_operand" "=r")
7738 (plus:SI (match_dup 1) (match_dup 2)))]
7744 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
7745 @code{minus} is made the first operand under the same conditions as
7749 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
7750 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
7754 @code{(minus @var{x} (const_int @var{n}))} is converted to
7755 @code{(plus @var{x} (const_int @var{-n}))}.
7758 Within address computations (i.e., inside @code{mem}), a left shift is
7759 converted into the appropriate multiplication by a power of two.
7761 @cindex @code{ior}, canonicalization of
7762 @cindex @code{and}, canonicalization of
7763 @cindex De Morgan's law
7765 De Morgan's Law is used to move bitwise negation inside a bitwise
7766 logical-and or logical-or operation. If this results in only one
7767 operand being a @code{not} expression, it will be the first one.
7769 A machine that has an instruction that performs a bitwise logical-and of one
7770 operand with the bitwise negation of the other should specify the pattern
7771 for that instruction as
7775 [(set (match_operand:@var{m} 0 @dots{})
7776 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
7777 (match_operand:@var{m} 2 @dots{})))]
7783 Similarly, a pattern for a ``NAND'' instruction should be written
7787 [(set (match_operand:@var{m} 0 @dots{})
7788 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
7789 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
7794 In both cases, it is not necessary to include patterns for the many
7795 logically equivalent RTL expressions.
7797 @cindex @code{xor}, canonicalization of
7799 The only possible RTL expressions involving both bitwise exclusive-or
7800 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
7801 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
7804 The sum of three items, one of which is a constant, will only appear in
7808 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
7811 @cindex @code{zero_extract}, canonicalization of
7812 @cindex @code{sign_extract}, canonicalization of
7814 Equality comparisons of a group of bits (usually a single bit) with zero
7815 will be written using @code{zero_extract} rather than the equivalent
7816 @code{and} or @code{sign_extract} operations.
7818 @cindex @code{mult}, canonicalization of
7820 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
7821 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
7822 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
7823 for @code{zero_extend}.
7826 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
7827 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
7828 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
7829 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
7830 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
7831 operand of @code{mult} is also a shift, then that is extended also.
7832 This transformation is only applied when it can be proven that the
7833 original operation had sufficient precision to prevent overflow.
7837 Further canonicalization rules are defined in the function
7838 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
7842 @node Expander Definitions
7843 @section Defining RTL Sequences for Code Generation
7844 @cindex expander definitions
7845 @cindex code generation RTL sequences
7846 @cindex defining RTL sequences for code generation
7848 On some target machines, some standard pattern names for RTL generation
7849 cannot be handled with single insn, but a sequence of RTL insns can
7850 represent them. For these target machines, you can write a
7851 @code{define_expand} to specify how to generate the sequence of RTL@.
7853 @findex define_expand
7854 A @code{define_expand} is an RTL expression that looks almost like a
7855 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
7856 only for RTL generation and it can produce more than one RTL insn.
7858 A @code{define_expand} RTX has four operands:
7862 The name. Each @code{define_expand} must have a name, since the only
7863 use for it is to refer to it by name.
7866 The RTL template. This is a vector of RTL expressions representing
7867 a sequence of separate instructions. Unlike @code{define_insn}, there
7868 is no implicit surrounding @code{PARALLEL}.
7871 The condition, a string containing a C expression. This expression is
7872 used to express how the availability of this pattern depends on
7873 subclasses of target machine, selected by command-line options when GCC
7874 is run. This is just like the condition of a @code{define_insn} that
7875 has a standard name. Therefore, the condition (if present) may not
7876 depend on the data in the insn being matched, but only the
7877 target-machine-type flags. The compiler needs to test these conditions
7878 during initialization in order to learn exactly which named instructions
7879 are available in a particular run.
7882 The preparation statements, a string containing zero or more C
7883 statements which are to be executed before RTL code is generated from
7886 Usually these statements prepare temporary registers for use as
7887 internal operands in the RTL template, but they can also generate RTL
7888 insns directly by calling routines such as @code{emit_insn}, etc.
7889 Any such insns precede the ones that come from the RTL template.
7892 Optionally, a vector containing the values of attributes. @xref{Insn
7896 Every RTL insn emitted by a @code{define_expand} must match some
7897 @code{define_insn} in the machine description. Otherwise, the compiler
7898 will crash when trying to generate code for the insn or trying to optimize
7901 The RTL template, in addition to controlling generation of RTL insns,
7902 also describes the operands that need to be specified when this pattern
7903 is used. In particular, it gives a predicate for each operand.
7905 A true operand, which needs to be specified in order to generate RTL from
7906 the pattern, should be described with a @code{match_operand} in its first
7907 occurrence in the RTL template. This enters information on the operand's
7908 predicate into the tables that record such things. GCC uses the
7909 information to preload the operand into a register if that is required for
7910 valid RTL code. If the operand is referred to more than once, subsequent
7911 references should use @code{match_dup}.
7913 The RTL template may also refer to internal ``operands'' which are
7914 temporary registers or labels used only within the sequence made by the
7915 @code{define_expand}. Internal operands are substituted into the RTL
7916 template with @code{match_dup}, never with @code{match_operand}. The
7917 values of the internal operands are not passed in as arguments by the
7918 compiler when it requests use of this pattern. Instead, they are computed
7919 within the pattern, in the preparation statements. These statements
7920 compute the values and store them into the appropriate elements of
7921 @code{operands} so that @code{match_dup} can find them.
7923 There are two special macros defined for use in the preparation statements:
7924 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
7931 Use the @code{DONE} macro to end RTL generation for the pattern. The
7932 only RTL insns resulting from the pattern on this occasion will be
7933 those already emitted by explicit calls to @code{emit_insn} within the
7934 preparation statements; the RTL template will not be generated.
7938 Make the pattern fail on this occasion. When a pattern fails, it means
7939 that the pattern was not truly available. The calling routines in the
7940 compiler will try other strategies for code generation using other patterns.
7942 Failure is currently supported only for binary (addition, multiplication,
7943 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
7947 If the preparation falls through (invokes neither @code{DONE} nor
7948 @code{FAIL}), then the @code{define_expand} acts like a
7949 @code{define_insn} in that the RTL template is used to generate the
7952 The RTL template is not used for matching, only for generating the
7953 initial insn list. If the preparation statement always invokes
7954 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
7955 list of operands, such as this example:
7959 (define_expand "addsi3"
7960 [(match_operand:SI 0 "register_operand" "")
7961 (match_operand:SI 1 "register_operand" "")
7962 (match_operand:SI 2 "register_operand" "")]
7968 handle_add (operands[0], operands[1], operands[2]);
7974 Here is an example, the definition of left-shift for the SPUR chip:
7978 (define_expand "ashlsi3"
7979 [(set (match_operand:SI 0 "register_operand" "")
7983 (match_operand:SI 1 "register_operand" "")
7984 (match_operand:SI 2 "nonmemory_operand" "")))]
7993 if (GET_CODE (operands[2]) != CONST_INT
7994 || (unsigned) INTVAL (operands[2]) > 3)
8001 This example uses @code{define_expand} so that it can generate an RTL insn
8002 for shifting when the shift-count is in the supported range of 0 to 3 but
8003 fail in other cases where machine insns aren't available. When it fails,
8004 the compiler tries another strategy using different patterns (such as, a
8007 If the compiler were able to handle nontrivial condition-strings in
8008 patterns with names, then it would be possible to use a
8009 @code{define_insn} in that case. Here is another case (zero-extension
8010 on the 68000) which makes more use of the power of @code{define_expand}:
8013 (define_expand "zero_extendhisi2"
8014 [(set (match_operand:SI 0 "general_operand" "")
8016 (set (strict_low_part
8020 (match_operand:HI 1 "general_operand" ""))]
8022 "operands[1] = make_safe_from (operands[1], operands[0]);")
8026 @findex make_safe_from
8027 Here two RTL insns are generated, one to clear the entire output operand
8028 and the other to copy the input operand into its low half. This sequence
8029 is incorrect if the input operand refers to [the old value of] the output
8030 operand, so the preparation statement makes sure this isn't so. The
8031 function @code{make_safe_from} copies the @code{operands[1]} into a
8032 temporary register if it refers to @code{operands[0]}. It does this
8033 by emitting another RTL insn.
8035 Finally, a third example shows the use of an internal operand.
8036 Zero-extension on the SPUR chip is done by @code{and}-ing the result
8037 against a halfword mask. But this mask cannot be represented by a
8038 @code{const_int} because the constant value is too large to be legitimate
8039 on this machine. So it must be copied into a register with
8040 @code{force_reg} and then the register used in the @code{and}.
8043 (define_expand "zero_extendhisi2"
8044 [(set (match_operand:SI 0 "register_operand" "")
8046 (match_operand:HI 1 "register_operand" "")
8051 = force_reg (SImode, GEN_INT (65535)); ")
8054 @emph{Note:} If the @code{define_expand} is used to serve a
8055 standard binary or unary arithmetic operation or a bit-field operation,
8056 then the last insn it generates must not be a @code{code_label},
8057 @code{barrier} or @code{note}. It must be an @code{insn},
8058 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
8059 at the end, emit an insn to copy the result of the operation into
8060 itself. Such an insn will generate no code, but it can avoid problems
8065 @node Insn Splitting
8066 @section Defining How to Split Instructions
8067 @cindex insn splitting
8068 @cindex instruction splitting
8069 @cindex splitting instructions
8071 There are two cases where you should specify how to split a pattern
8072 into multiple insns. On machines that have instructions requiring
8073 delay slots (@pxref{Delay Slots}) or that have instructions whose
8074 output is not available for multiple cycles (@pxref{Processor pipeline
8075 description}), the compiler phases that optimize these cases need to
8076 be able to move insns into one-instruction delay slots. However, some
8077 insns may generate more than one machine instruction. These insns
8078 cannot be placed into a delay slot.
8080 Often you can rewrite the single insn as a list of individual insns,
8081 each corresponding to one machine instruction. The disadvantage of
8082 doing so is that it will cause the compilation to be slower and require
8083 more space. If the resulting insns are too complex, it may also
8084 suppress some optimizations. The compiler splits the insn if there is a
8085 reason to believe that it might improve instruction or delay slot
8088 The insn combiner phase also splits putative insns. If three insns are
8089 merged into one insn with a complex expression that cannot be matched by
8090 some @code{define_insn} pattern, the combiner phase attempts to split
8091 the complex pattern into two insns that are recognized. Usually it can
8092 break the complex pattern into two patterns by splitting out some
8093 subexpression. However, in some other cases, such as performing an
8094 addition of a large constant in two insns on a RISC machine, the way to
8095 split the addition into two insns is machine-dependent.
8097 @findex define_split
8098 The @code{define_split} definition tells the compiler how to split a
8099 complex insn into several simpler insns. It looks like this:
8103 [@var{insn-pattern}]
8105 [@var{new-insn-pattern-1}
8106 @var{new-insn-pattern-2}
8108 "@var{preparation-statements}")
8111 @var{insn-pattern} is a pattern that needs to be split and
8112 @var{condition} is the final condition to be tested, as in a
8113 @code{define_insn}. When an insn matching @var{insn-pattern} and
8114 satisfying @var{condition} is found, it is replaced in the insn list
8115 with the insns given by @var{new-insn-pattern-1},
8116 @var{new-insn-pattern-2}, etc.
8118 The @var{preparation-statements} are similar to those statements that
8119 are specified for @code{define_expand} (@pxref{Expander Definitions})
8120 and are executed before the new RTL is generated to prepare for the
8121 generated code or emit some insns whose pattern is not fixed. Unlike
8122 those in @code{define_expand}, however, these statements must not
8123 generate any new pseudo-registers. Once reload has completed, they also
8124 must not allocate any space in the stack frame.
8126 There are two special macros defined for use in the preparation statements:
8127 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
8134 Use the @code{DONE} macro to end RTL generation for the splitter. The
8135 only RTL insns generated as replacement for the matched input insn will
8136 be those already emitted by explicit calls to @code{emit_insn} within
8137 the preparation statements; the replacement pattern is not used.
8141 Make the @code{define_split} fail on this occasion. When a @code{define_split}
8142 fails, it means that the splitter was not truly available for the inputs
8143 it was given, and the input insn will not be split.
8146 If the preparation falls through (invokes neither @code{DONE} nor
8147 @code{FAIL}), then the @code{define_split} uses the replacement
8150 Patterns are matched against @var{insn-pattern} in two different
8151 circumstances. If an insn needs to be split for delay slot scheduling
8152 or insn scheduling, the insn is already known to be valid, which means
8153 that it must have been matched by some @code{define_insn} and, if
8154 @code{reload_completed} is nonzero, is known to satisfy the constraints
8155 of that @code{define_insn}. In that case, the new insn patterns must
8156 also be insns that are matched by some @code{define_insn} and, if
8157 @code{reload_completed} is nonzero, must also satisfy the constraints
8158 of those definitions.
8160 As an example of this usage of @code{define_split}, consider the following
8161 example from @file{a29k.md}, which splits a @code{sign_extend} from
8162 @code{HImode} to @code{SImode} into a pair of shift insns:
8166 [(set (match_operand:SI 0 "gen_reg_operand" "")
8167 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
8170 (ashift:SI (match_dup 1)
8173 (ashiftrt:SI (match_dup 0)
8176 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
8179 When the combiner phase tries to split an insn pattern, it is always the
8180 case that the pattern is @emph{not} matched by any @code{define_insn}.
8181 The combiner pass first tries to split a single @code{set} expression
8182 and then the same @code{set} expression inside a @code{parallel}, but
8183 followed by a @code{clobber} of a pseudo-reg to use as a scratch
8184 register. In these cases, the combiner expects exactly two new insn
8185 patterns to be generated. It will verify that these patterns match some
8186 @code{define_insn} definitions, so you need not do this test in the
8187 @code{define_split} (of course, there is no point in writing a
8188 @code{define_split} that will never produce insns that match).
8190 Here is an example of this use of @code{define_split}, taken from
8195 [(set (match_operand:SI 0 "gen_reg_operand" "")
8196 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
8197 (match_operand:SI 2 "non_add_cint_operand" "")))]
8199 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
8200 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
8203 int low = INTVAL (operands[2]) & 0xffff;
8204 int high = (unsigned) INTVAL (operands[2]) >> 16;
8207 high++, low |= 0xffff0000;
8209 operands[3] = GEN_INT (high << 16);
8210 operands[4] = GEN_INT (low);
8214 Here the predicate @code{non_add_cint_operand} matches any
8215 @code{const_int} that is @emph{not} a valid operand of a single add
8216 insn. The add with the smaller displacement is written so that it
8217 can be substituted into the address of a subsequent operation.
8219 An example that uses a scratch register, from the same file, generates
8220 an equality comparison of a register and a large constant:
8224 [(set (match_operand:CC 0 "cc_reg_operand" "")
8225 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
8226 (match_operand:SI 2 "non_short_cint_operand" "")))
8227 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
8228 "find_single_use (operands[0], insn, 0)
8229 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
8230 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
8231 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
8232 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
8235 /* @r{Get the constant we are comparing against, C, and see what it
8236 looks like sign-extended to 16 bits. Then see what constant
8237 could be XOR'ed with C to get the sign-extended value.} */
8239 int c = INTVAL (operands[2]);
8240 int sextc = (c << 16) >> 16;
8241 int xorv = c ^ sextc;
8243 operands[4] = GEN_INT (xorv);
8244 operands[5] = GEN_INT (sextc);
8248 To avoid confusion, don't write a single @code{define_split} that
8249 accepts some insns that match some @code{define_insn} as well as some
8250 insns that don't. Instead, write two separate @code{define_split}
8251 definitions, one for the insns that are valid and one for the insns that
8254 The splitter is allowed to split jump instructions into sequence of
8255 jumps or create new jumps in while splitting non-jump instructions. As
8256 the control flow graph and branch prediction information needs to be updated,
8257 several restriction apply.
8259 Splitting of jump instruction into sequence that over by another jump
8260 instruction is always valid, as compiler expect identical behavior of new
8261 jump. When new sequence contains multiple jump instructions or new labels,
8262 more assistance is needed. Splitter is required to create only unconditional
8263 jumps, or simple conditional jump instructions. Additionally it must attach a
8264 @code{REG_BR_PROB} note to each conditional jump. A global variable
8265 @code{split_branch_probability} holds the probability of the original branch in case
8266 it was a simple conditional jump, @minus{}1 otherwise. To simplify
8267 recomputing of edge frequencies, the new sequence is required to have only
8268 forward jumps to the newly created labels.
8270 @findex define_insn_and_split
8271 For the common case where the pattern of a define_split exactly matches the
8272 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
8276 (define_insn_and_split
8277 [@var{insn-pattern}]
8279 "@var{output-template}"
8280 "@var{split-condition}"
8281 [@var{new-insn-pattern-1}
8282 @var{new-insn-pattern-2}
8284 "@var{preparation-statements}"
8285 [@var{insn-attributes}])
8289 @var{insn-pattern}, @var{condition}, @var{output-template}, and
8290 @var{insn-attributes} are used as in @code{define_insn}. The
8291 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
8292 in a @code{define_split}. The @var{split-condition} is also used as in
8293 @code{define_split}, with the additional behavior that if the condition starts
8294 with @samp{&&}, the condition used for the split will be the constructed as a
8295 logical ``and'' of the split condition with the insn condition. For example,
8299 (define_insn_and_split "zero_extendhisi2_and"
8300 [(set (match_operand:SI 0 "register_operand" "=r")
8301 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
8302 (clobber (reg:CC 17))]
8303 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
8305 "&& reload_completed"
8306 [(parallel [(set (match_dup 0)
8307 (and:SI (match_dup 0) (const_int 65535)))
8308 (clobber (reg:CC 17))])]
8310 [(set_attr "type" "alu1")])
8314 In this case, the actual split condition will be
8315 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
8317 The @code{define_insn_and_split} construction provides exactly the same
8318 functionality as two separate @code{define_insn} and @code{define_split}
8319 patterns. It exists for compactness, and as a maintenance tool to prevent
8320 having to ensure the two patterns' templates match.
8324 @node Including Patterns
8325 @section Including Patterns in Machine Descriptions.
8326 @cindex insn includes
8329 The @code{include} pattern tells the compiler tools where to
8330 look for patterns that are in files other than in the file
8331 @file{.md}. This is used only at build time and there is no preprocessing allowed.
8345 (include "filestuff")
8349 Where @var{pathname} is a string that specifies the location of the file,
8350 specifies the include file to be in @file{gcc/config/target/filestuff}. The
8351 directory @file{gcc/config/target} is regarded as the default directory.
8354 Machine descriptions may be split up into smaller more manageable subsections
8355 and placed into subdirectories.
8361 (include "BOGUS/filestuff")
8365 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
8367 Specifying an absolute path for the include file such as;
8370 (include "/u2/BOGUS/filestuff")
8373 is permitted but is not encouraged.
8375 @subsection RTL Generation Tool Options for Directory Search
8376 @cindex directory options .md
8377 @cindex options, directory search
8378 @cindex search options
8380 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
8385 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
8390 Add the directory @var{dir} to the head of the list of directories to be
8391 searched for header files. This can be used to override a system machine definition
8392 file, substituting your own version, since these directories are
8393 searched before the default machine description file directories. If you use more than
8394 one @option{-I} option, the directories are scanned in left-to-right
8395 order; the standard default directory come after.
8400 @node Peephole Definitions
8401 @section Machine-Specific Peephole Optimizers
8402 @cindex peephole optimizer definitions
8403 @cindex defining peephole optimizers
8405 In addition to instruction patterns the @file{md} file may contain
8406 definitions of machine-specific peephole optimizations.
8408 The combiner does not notice certain peephole optimizations when the data
8409 flow in the program does not suggest that it should try them. For example,
8410 sometimes two consecutive insns related in purpose can be combined even
8411 though the second one does not appear to use a register computed in the
8412 first one. A machine-specific peephole optimizer can detect such
8415 There are two forms of peephole definitions that may be used. The
8416 original @code{define_peephole} is run at assembly output time to
8417 match insns and substitute assembly text. Use of @code{define_peephole}
8420 A newer @code{define_peephole2} matches insns and substitutes new
8421 insns. The @code{peephole2} pass is run after register allocation
8422 but before scheduling, which may result in much better code for
8423 targets that do scheduling.
8426 * define_peephole:: RTL to Text Peephole Optimizers
8427 * define_peephole2:: RTL to RTL Peephole Optimizers
8432 @node define_peephole
8433 @subsection RTL to Text Peephole Optimizers
8434 @findex define_peephole
8437 A definition looks like this:
8441 [@var{insn-pattern-1}
8442 @var{insn-pattern-2}
8446 "@var{optional-insn-attributes}")
8450 The last string operand may be omitted if you are not using any
8451 machine-specific information in this machine description. If present,
8452 it must obey the same rules as in a @code{define_insn}.
8454 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
8455 consecutive insns. The optimization applies to a sequence of insns when
8456 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
8457 the next, and so on.
8459 Each of the insns matched by a peephole must also match a
8460 @code{define_insn}. Peepholes are checked only at the last stage just
8461 before code generation, and only optionally. Therefore, any insn which
8462 would match a peephole but no @code{define_insn} will cause a crash in code
8463 generation in an unoptimized compilation, or at various optimization
8466 The operands of the insns are matched with @code{match_operands},
8467 @code{match_operator}, and @code{match_dup}, as usual. What is not
8468 usual is that the operand numbers apply to all the insn patterns in the
8469 definition. So, you can check for identical operands in two insns by
8470 using @code{match_operand} in one insn and @code{match_dup} in the
8473 The operand constraints used in @code{match_operand} patterns do not have
8474 any direct effect on the applicability of the peephole, but they will
8475 be validated afterward, so make sure your constraints are general enough
8476 to apply whenever the peephole matches. If the peephole matches
8477 but the constraints are not satisfied, the compiler will crash.
8479 It is safe to omit constraints in all the operands of the peephole; or
8480 you can write constraints which serve as a double-check on the criteria
8483 Once a sequence of insns matches the patterns, the @var{condition} is
8484 checked. This is a C expression which makes the final decision whether to
8485 perform the optimization (we do so if the expression is nonzero). If
8486 @var{condition} is omitted (in other words, the string is empty) then the
8487 optimization is applied to every sequence of insns that matches the
8490 The defined peephole optimizations are applied after register allocation
8491 is complete. Therefore, the peephole definition can check which
8492 operands have ended up in which kinds of registers, just by looking at
8495 @findex prev_active_insn
8496 The way to refer to the operands in @var{condition} is to write
8497 @code{operands[@var{i}]} for operand number @var{i} (as matched by
8498 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
8499 to refer to the last of the insns being matched; use
8500 @code{prev_active_insn} to find the preceding insns.
8502 @findex dead_or_set_p
8503 When optimizing computations with intermediate results, you can use
8504 @var{condition} to match only when the intermediate results are not used
8505 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
8506 @var{op})}, where @var{insn} is the insn in which you expect the value
8507 to be used for the last time (from the value of @code{insn}, together
8508 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
8509 value (from @code{operands[@var{i}]}).
8511 Applying the optimization means replacing the sequence of insns with one
8512 new insn. The @var{template} controls ultimate output of assembler code
8513 for this combined insn. It works exactly like the template of a
8514 @code{define_insn}. Operand numbers in this template are the same ones
8515 used in matching the original sequence of insns.
8517 The result of a defined peephole optimizer does not need to match any of
8518 the insn patterns in the machine description; it does not even have an
8519 opportunity to match them. The peephole optimizer definition itself serves
8520 as the insn pattern to control how the insn is output.
8522 Defined peephole optimizers are run as assembler code is being output,
8523 so the insns they produce are never combined or rearranged in any way.
8525 Here is an example, taken from the 68000 machine description:
8529 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
8530 (set (match_operand:DF 0 "register_operand" "=f")
8531 (match_operand:DF 1 "register_operand" "ad"))]
8532 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
8535 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
8537 output_asm_insn ("move.l %1,(sp)", xoperands);
8538 output_asm_insn ("move.l %1,-(sp)", operands);
8539 return "fmove.d (sp)+,%0";
8541 output_asm_insn ("movel %1,sp@@", xoperands);
8542 output_asm_insn ("movel %1,sp@@-", operands);
8543 return "fmoved sp@@+,%0";
8549 The effect of this optimization is to change
8575 If a peephole matches a sequence including one or more jump insns, you must
8576 take account of the flags such as @code{CC_REVERSED} which specify that the
8577 condition codes are represented in an unusual manner. The compiler
8578 automatically alters any ordinary conditional jumps which occur in such
8579 situations, but the compiler cannot alter jumps which have been replaced by
8580 peephole optimizations. So it is up to you to alter the assembler code
8581 that the peephole produces. Supply C code to write the assembler output,
8582 and in this C code check the condition code status flags and change the
8583 assembler code as appropriate.
8586 @var{insn-pattern-1} and so on look @emph{almost} like the second
8587 operand of @code{define_insn}. There is one important difference: the
8588 second operand of @code{define_insn} consists of one or more RTX's
8589 enclosed in square brackets. Usually, there is only one: then the same
8590 action can be written as an element of a @code{define_peephole}. But
8591 when there are multiple actions in a @code{define_insn}, they are
8592 implicitly enclosed in a @code{parallel}. Then you must explicitly
8593 write the @code{parallel}, and the square brackets within it, in the
8594 @code{define_peephole}. Thus, if an insn pattern looks like this,
8597 (define_insn "divmodsi4"
8598 [(set (match_operand:SI 0 "general_operand" "=d")
8599 (div:SI (match_operand:SI 1 "general_operand" "0")
8600 (match_operand:SI 2 "general_operand" "dmsK")))
8601 (set (match_operand:SI 3 "general_operand" "=d")
8602 (mod:SI (match_dup 1) (match_dup 2)))]
8604 "divsl%.l %2,%3:%0")
8608 then the way to mention this insn in a peephole is as follows:
8614 [(set (match_operand:SI 0 "general_operand" "=d")
8615 (div:SI (match_operand:SI 1 "general_operand" "0")
8616 (match_operand:SI 2 "general_operand" "dmsK")))
8617 (set (match_operand:SI 3 "general_operand" "=d")
8618 (mod:SI (match_dup 1) (match_dup 2)))])
8625 @node define_peephole2
8626 @subsection RTL to RTL Peephole Optimizers
8627 @findex define_peephole2
8629 The @code{define_peephole2} definition tells the compiler how to
8630 substitute one sequence of instructions for another sequence,
8631 what additional scratch registers may be needed and what their
8636 [@var{insn-pattern-1}
8637 @var{insn-pattern-2}
8640 [@var{new-insn-pattern-1}
8641 @var{new-insn-pattern-2}
8643 "@var{preparation-statements}")
8646 The definition is almost identical to @code{define_split}
8647 (@pxref{Insn Splitting}) except that the pattern to match is not a
8648 single instruction, but a sequence of instructions.
8650 It is possible to request additional scratch registers for use in the
8651 output template. If appropriate registers are not free, the pattern
8652 will simply not match.
8654 @findex match_scratch
8656 Scratch registers are requested with a @code{match_scratch} pattern at
8657 the top level of the input pattern. The allocated register (initially) will
8658 be dead at the point requested within the original sequence. If the scratch
8659 is used at more than a single point, a @code{match_dup} pattern at the
8660 top level of the input pattern marks the last position in the input sequence
8661 at which the register must be available.
8663 Here is an example from the IA-32 machine description:
8667 [(match_scratch:SI 2 "r")
8668 (parallel [(set (match_operand:SI 0 "register_operand" "")
8669 (match_operator:SI 3 "arith_or_logical_operator"
8671 (match_operand:SI 1 "memory_operand" "")]))
8672 (clobber (reg:CC 17))])]
8673 "! optimize_size && ! TARGET_READ_MODIFY"
8674 [(set (match_dup 2) (match_dup 1))
8675 (parallel [(set (match_dup 0)
8676 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
8677 (clobber (reg:CC 17))])]
8682 This pattern tries to split a load from its use in the hopes that we'll be
8683 able to schedule around the memory load latency. It allocates a single
8684 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
8685 to be live only at the point just before the arithmetic.
8687 A real example requiring extended scratch lifetimes is harder to come by,
8688 so here's a silly made-up example:
8692 [(match_scratch:SI 4 "r")
8693 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
8694 (set (match_operand:SI 2 "" "") (match_dup 1))
8696 (set (match_operand:SI 3 "" "") (match_dup 1))]
8697 "/* @r{determine 1 does not overlap 0 and 2} */"
8698 [(set (match_dup 4) (match_dup 1))
8699 (set (match_dup 0) (match_dup 4))
8700 (set (match_dup 2) (match_dup 4))
8701 (set (match_dup 3) (match_dup 4))]
8705 There are two special macros defined for use in the preparation statements:
8706 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
8713 Use the @code{DONE} macro to end RTL generation for the peephole. The
8714 only RTL insns generated as replacement for the matched input insn will
8715 be those already emitted by explicit calls to @code{emit_insn} within
8716 the preparation statements; the replacement pattern is not used.
8720 Make the @code{define_peephole2} fail on this occasion. When a @code{define_peephole2}
8721 fails, it means that the replacement was not truly available for the
8722 particular inputs it was given. In that case, GCC may still apply a
8723 later @code{define_peephole2} that also matches the given insn pattern.
8724 (Note that this is different from @code{define_split}, where @code{FAIL}
8725 prevents the input insn from being split at all.)
8728 If the preparation falls through (invokes neither @code{DONE} nor
8729 @code{FAIL}), then the @code{define_peephole2} uses the replacement
8733 If we had not added the @code{(match_dup 4)} in the middle of the input
8734 sequence, it might have been the case that the register we chose at the
8735 beginning of the sequence is killed by the first or second @code{set}.
8739 @node Insn Attributes
8740 @section Instruction Attributes
8741 @cindex insn attributes
8742 @cindex instruction attributes
8744 In addition to describing the instruction supported by the target machine,
8745 the @file{md} file also defines a group of @dfn{attributes} and a set of
8746 values for each. Every generated insn is assigned a value for each attribute.
8747 One possible attribute would be the effect that the insn has on the machine's
8748 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
8749 to track the condition codes.
8752 * Defining Attributes:: Specifying attributes and their values.
8753 * Expressions:: Valid expressions for attribute values.
8754 * Tagging Insns:: Assigning attribute values to insns.
8755 * Attr Example:: An example of assigning attributes.
8756 * Insn Lengths:: Computing the length of insns.
8757 * Constant Attributes:: Defining attributes that are constant.
8758 * Mnemonic Attribute:: Obtain the instruction mnemonic as attribute value.
8759 * Delay Slots:: Defining delay slots required for a machine.
8760 * Processor pipeline description:: Specifying information for insn scheduling.
8765 @node Defining Attributes
8766 @subsection Defining Attributes and their Values
8767 @cindex defining attributes and their values
8768 @cindex attributes, defining
8771 The @code{define_attr} expression is used to define each attribute required
8772 by the target machine. It looks like:
8775 (define_attr @var{name} @var{list-of-values} @var{default})
8778 @var{name} is a string specifying the name of the attribute being
8779 defined. Some attributes are used in a special way by the rest of the
8780 compiler. The @code{enabled} attribute can be used to conditionally
8781 enable or disable insn alternatives (@pxref{Disable Insn
8782 Alternatives}). The @code{predicable} attribute, together with a
8783 suitable @code{define_cond_exec} (@pxref{Conditional Execution}), can
8784 be used to automatically generate conditional variants of instruction
8785 patterns. The @code{mnemonic} attribute can be used to check for the
8786 instruction mnemonic (@pxref{Mnemonic Attribute}). The compiler
8787 internally uses the names @code{ce_enabled} and @code{nonce_enabled},
8788 so they should not be used elsewhere as alternative names.
8790 @var{list-of-values} is either a string that specifies a comma-separated
8791 list of values that can be assigned to the attribute, or a null string to
8792 indicate that the attribute takes numeric values.
8794 @var{default} is an attribute expression that gives the value of this
8795 attribute for insns that match patterns whose definition does not include
8796 an explicit value for this attribute. @xref{Attr Example}, for more
8797 information on the handling of defaults. @xref{Constant Attributes},
8798 for information on attributes that do not depend on any particular insn.
8801 For each defined attribute, a number of definitions are written to the
8802 @file{insn-attr.h} file. For cases where an explicit set of values is
8803 specified for an attribute, the following are defined:
8807 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
8810 An enumerated class is defined for @samp{attr_@var{name}} with
8811 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
8812 the attribute name and value are first converted to uppercase.
8815 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
8816 returns the attribute value for that insn.
8819 For example, if the following is present in the @file{md} file:
8822 (define_attr "type" "branch,fp,load,store,arith" @dots{})
8826 the following lines will be written to the file @file{insn-attr.h}.
8829 #define HAVE_ATTR_type 1
8830 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
8831 TYPE_STORE, TYPE_ARITH@};
8832 extern enum attr_type get_attr_type ();
8835 If the attribute takes numeric values, no @code{enum} type will be
8836 defined and the function to obtain the attribute's value will return
8839 There are attributes which are tied to a specific meaning. These
8840 attributes are not free to use for other purposes:
8844 The @code{length} attribute is used to calculate the length of emitted
8845 code chunks. This is especially important when verifying branch
8846 distances. @xref{Insn Lengths}.
8849 The @code{enabled} attribute can be defined to prevent certain
8850 alternatives of an insn definition from being used during code
8851 generation. @xref{Disable Insn Alternatives}.
8854 The @code{mnemonic} attribute can be defined to implement instruction
8855 specific checks in e.g. the pipeline description.
8856 @xref{Mnemonic Attribute}.
8859 For each of these special attributes, the corresponding
8860 @samp{HAVE_ATTR_@var{name}} @samp{#define} is also written when the
8861 attribute is not defined; in that case, it is defined as @samp{0}.
8863 @findex define_enum_attr
8864 @anchor{define_enum_attr}
8865 Another way of defining an attribute is to use:
8868 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
8871 This works in just the same way as @code{define_attr}, except that
8872 the list of values is taken from a separate enumeration called
8873 @var{enum} (@pxref{define_enum}). This form allows you to use
8874 the same list of values for several attributes without having to
8875 repeat the list each time. For example:
8878 (define_enum "processor" [
8883 (define_enum_attr "arch" "processor"
8884 (const (symbol_ref "target_arch")))
8885 (define_enum_attr "tune" "processor"
8886 (const (symbol_ref "target_tune")))
8889 defines the same attributes as:
8892 (define_attr "arch" "model_a,model_b,@dots{}"
8893 (const (symbol_ref "target_arch")))
8894 (define_attr "tune" "model_a,model_b,@dots{}"
8895 (const (symbol_ref "target_tune")))
8898 but without duplicating the processor list. The second example defines two
8899 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
8900 defines a single C enum (@code{processor}).
8904 @subsection Attribute Expressions
8905 @cindex attribute expressions
8907 RTL expressions used to define attributes use the codes described above
8908 plus a few specific to attribute definitions, to be discussed below.
8909 Attribute value expressions must have one of the following forms:
8912 @cindex @code{const_int} and attributes
8913 @item (const_int @var{i})
8914 The integer @var{i} specifies the value of a numeric attribute. @var{i}
8915 must be non-negative.
8917 The value of a numeric attribute can be specified either with a
8918 @code{const_int}, or as an integer represented as a string in
8919 @code{const_string}, @code{eq_attr} (see below), @code{attr},
8920 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
8921 overrides on specific instructions (@pxref{Tagging Insns}).
8923 @cindex @code{const_string} and attributes
8924 @item (const_string @var{value})
8925 The string @var{value} specifies a constant attribute value.
8926 If @var{value} is specified as @samp{"*"}, it means that the default value of
8927 the attribute is to be used for the insn containing this expression.
8928 @samp{"*"} obviously cannot be used in the @var{default} expression
8929 of a @code{define_attr}.
8931 If the attribute whose value is being specified is numeric, @var{value}
8932 must be a string containing a non-negative integer (normally
8933 @code{const_int} would be used in this case). Otherwise, it must
8934 contain one of the valid values for the attribute.
8936 @cindex @code{if_then_else} and attributes
8937 @item (if_then_else @var{test} @var{true-value} @var{false-value})
8938 @var{test} specifies an attribute test, whose format is defined below.
8939 The value of this expression is @var{true-value} if @var{test} is true,
8940 otherwise it is @var{false-value}.
8942 @cindex @code{cond} and attributes
8943 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
8944 The first operand of this expression is a vector containing an even
8945 number of expressions and consisting of pairs of @var{test} and @var{value}
8946 expressions. The value of the @code{cond} expression is that of the
8947 @var{value} corresponding to the first true @var{test} expression. If
8948 none of the @var{test} expressions are true, the value of the @code{cond}
8949 expression is that of the @var{default} expression.
8952 @var{test} expressions can have one of the following forms:
8955 @cindex @code{const_int} and attribute tests
8956 @item (const_int @var{i})
8957 This test is true if @var{i} is nonzero and false otherwise.
8959 @cindex @code{not} and attributes
8960 @cindex @code{ior} and attributes
8961 @cindex @code{and} and attributes
8962 @item (not @var{test})
8963 @itemx (ior @var{test1} @var{test2})
8964 @itemx (and @var{test1} @var{test2})
8965 These tests are true if the indicated logical function is true.
8967 @cindex @code{match_operand} and attributes
8968 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
8969 This test is true if operand @var{n} of the insn whose attribute value
8970 is being determined has mode @var{m} (this part of the test is ignored
8971 if @var{m} is @code{VOIDmode}) and the function specified by the string
8972 @var{pred} returns a nonzero value when passed operand @var{n} and mode
8973 @var{m} (this part of the test is ignored if @var{pred} is the null
8976 The @var{constraints} operand is ignored and should be the null string.
8978 @cindex @code{match_test} and attributes
8979 @item (match_test @var{c-expr})
8980 The test is true if C expression @var{c-expr} is true. In non-constant
8981 attributes, @var{c-expr} has access to the following variables:
8985 The rtl instruction under test.
8986 @item which_alternative
8987 The @code{define_insn} alternative that @var{insn} matches.
8988 @xref{Output Statement}.
8990 An array of @var{insn}'s rtl operands.
8993 @var{c-expr} behaves like the condition in a C @code{if} statement,
8994 so there is no need to explicitly convert the expression into a boolean
8995 0 or 1 value. For example, the following two tests are equivalent:
8998 (match_test "x & 2")
8999 (match_test "(x & 2) != 0")
9002 @cindex @code{le} and attributes
9003 @cindex @code{leu} and attributes
9004 @cindex @code{lt} and attributes
9005 @cindex @code{gt} and attributes
9006 @cindex @code{gtu} and attributes
9007 @cindex @code{ge} and attributes
9008 @cindex @code{geu} and attributes
9009 @cindex @code{ne} and attributes
9010 @cindex @code{eq} and attributes
9011 @cindex @code{plus} and attributes
9012 @cindex @code{minus} and attributes
9013 @cindex @code{mult} and attributes
9014 @cindex @code{div} and attributes
9015 @cindex @code{mod} and attributes
9016 @cindex @code{abs} and attributes
9017 @cindex @code{neg} and attributes
9018 @cindex @code{ashift} and attributes
9019 @cindex @code{lshiftrt} and attributes
9020 @cindex @code{ashiftrt} and attributes
9021 @item (le @var{arith1} @var{arith2})
9022 @itemx (leu @var{arith1} @var{arith2})
9023 @itemx (lt @var{arith1} @var{arith2})
9024 @itemx (ltu @var{arith1} @var{arith2})
9025 @itemx (gt @var{arith1} @var{arith2})
9026 @itemx (gtu @var{arith1} @var{arith2})
9027 @itemx (ge @var{arith1} @var{arith2})
9028 @itemx (geu @var{arith1} @var{arith2})
9029 @itemx (ne @var{arith1} @var{arith2})
9030 @itemx (eq @var{arith1} @var{arith2})
9031 These tests are true if the indicated comparison of the two arithmetic
9032 expressions is true. Arithmetic expressions are formed with
9033 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
9034 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
9035 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
9038 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
9039 Lengths},for additional forms). @code{symbol_ref} is a string
9040 denoting a C expression that yields an @code{int} when evaluated by the
9041 @samp{get_attr_@dots{}} routine. It should normally be a global
9045 @item (eq_attr @var{name} @var{value})
9046 @var{name} is a string specifying the name of an attribute.
9048 @var{value} is a string that is either a valid value for attribute
9049 @var{name}, a comma-separated list of values, or @samp{!} followed by a
9050 value or list. If @var{value} does not begin with a @samp{!}, this
9051 test is true if the value of the @var{name} attribute of the current
9052 insn is in the list specified by @var{value}. If @var{value} begins
9053 with a @samp{!}, this test is true if the attribute's value is
9054 @emph{not} in the specified list.
9059 (eq_attr "type" "load,store")
9066 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
9069 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
9070 value of the compiler variable @code{which_alternative}
9071 (@pxref{Output Statement}) and the values must be small integers. For
9075 (eq_attr "alternative" "2,3")
9082 (ior (eq (symbol_ref "which_alternative") (const_int 2))
9083 (eq (symbol_ref "which_alternative") (const_int 3)))
9086 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
9087 where the value of the attribute being tested is known for all insns matching
9088 a particular pattern. This is by far the most common case.
9091 @item (attr_flag @var{name})
9092 The value of an @code{attr_flag} expression is true if the flag
9093 specified by @var{name} is true for the @code{insn} currently being
9096 @var{name} is a string specifying one of a fixed set of flags to test.
9097 Test the flags @code{forward} and @code{backward} to determine the
9098 direction of a conditional branch.
9100 This example describes a conditional branch delay slot which
9101 can be nullified for forward branches that are taken (annul-true) or
9102 for backward branches which are not taken (annul-false).
9105 (define_delay (eq_attr "type" "cbranch")
9106 [(eq_attr "in_branch_delay" "true")
9107 (and (eq_attr "in_branch_delay" "true")
9108 (attr_flag "forward"))
9109 (and (eq_attr "in_branch_delay" "true")
9110 (attr_flag "backward"))])
9113 The @code{forward} and @code{backward} flags are false if the current
9114 @code{insn} being scheduled is not a conditional branch.
9116 @code{attr_flag} is only used during delay slot scheduling and has no
9117 meaning to other passes of the compiler.
9120 @item (attr @var{name})
9121 The value of another attribute is returned. This is most useful
9122 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
9123 produce more efficient code for non-numeric attributes.
9129 @subsection Assigning Attribute Values to Insns
9130 @cindex tagging insns
9131 @cindex assigning attribute values to insns
9133 The value assigned to an attribute of an insn is primarily determined by
9134 which pattern is matched by that insn (or which @code{define_peephole}
9135 generated it). Every @code{define_insn} and @code{define_peephole} can
9136 have an optional last argument to specify the values of attributes for
9137 matching insns. The value of any attribute not specified in a particular
9138 insn is set to the default value for that attribute, as specified in its
9139 @code{define_attr}. Extensive use of default values for attributes
9140 permits the specification of the values for only one or two attributes
9141 in the definition of most insn patterns, as seen in the example in the
9144 The optional last argument of @code{define_insn} and
9145 @code{define_peephole} is a vector of expressions, each of which defines
9146 the value for a single attribute. The most general way of assigning an
9147 attribute's value is to use a @code{set} expression whose first operand is an
9148 @code{attr} expression giving the name of the attribute being set. The
9149 second operand of the @code{set} is an attribute expression
9150 (@pxref{Expressions}) giving the value of the attribute.
9152 When the attribute value depends on the @samp{alternative} attribute
9153 (i.e., which is the applicable alternative in the constraint of the
9154 insn), the @code{set_attr_alternative} expression can be used. It
9155 allows the specification of a vector of attribute expressions, one for
9159 When the generality of arbitrary attribute expressions is not required,
9160 the simpler @code{set_attr} expression can be used, which allows
9161 specifying a string giving either a single attribute value or a list
9162 of attribute values, one for each alternative.
9164 The form of each of the above specifications is shown below. In each case,
9165 @var{name} is a string specifying the attribute to be set.
9168 @item (set_attr @var{name} @var{value-string})
9169 @var{value-string} is either a string giving the desired attribute value,
9170 or a string containing a comma-separated list giving the values for
9171 succeeding alternatives. The number of elements must match the number
9172 of alternatives in the constraint of the insn pattern.
9174 Note that it may be useful to specify @samp{*} for some alternative, in
9175 which case the attribute will assume its default value for insns matching
9178 @findex set_attr_alternative
9179 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
9180 Depending on the alternative of the insn, the value will be one of the
9181 specified values. This is a shorthand for using a @code{cond} with
9182 tests on the @samp{alternative} attribute.
9185 @item (set (attr @var{name}) @var{value})
9186 The first operand of this @code{set} must be the special RTL expression
9187 @code{attr}, whose sole operand is a string giving the name of the
9188 attribute being set. @var{value} is the value of the attribute.
9191 The following shows three different ways of representing the same
9192 attribute value specification:
9195 (set_attr "type" "load,store,arith")
9197 (set_attr_alternative "type"
9198 [(const_string "load") (const_string "store")
9199 (const_string "arith")])
9202 (cond [(eq_attr "alternative" "1") (const_string "load")
9203 (eq_attr "alternative" "2") (const_string "store")]
9204 (const_string "arith")))
9208 @findex define_asm_attributes
9209 The @code{define_asm_attributes} expression provides a mechanism to
9210 specify the attributes assigned to insns produced from an @code{asm}
9211 statement. It has the form:
9214 (define_asm_attributes [@var{attr-sets}])
9218 where @var{attr-sets} is specified the same as for both the
9219 @code{define_insn} and the @code{define_peephole} expressions.
9221 These values will typically be the ``worst case'' attribute values. For
9222 example, they might indicate that the condition code will be clobbered.
9224 A specification for a @code{length} attribute is handled specially. The
9225 way to compute the length of an @code{asm} insn is to multiply the
9226 length specified in the expression @code{define_asm_attributes} by the
9227 number of machine instructions specified in the @code{asm} statement,
9228 determined by counting the number of semicolons and newlines in the
9229 string. Therefore, the value of the @code{length} attribute specified
9230 in a @code{define_asm_attributes} should be the maximum possible length
9231 of a single machine instruction.
9236 @subsection Example of Attribute Specifications
9237 @cindex attribute specifications example
9238 @cindex attribute specifications
9240 The judicious use of defaulting is important in the efficient use of
9241 insn attributes. Typically, insns are divided into @dfn{types} and an
9242 attribute, customarily called @code{type}, is used to represent this
9243 value. This attribute is normally used only to define the default value
9244 for other attributes. An example will clarify this usage.
9246 Assume we have a RISC machine with a condition code and in which only
9247 full-word operations are performed in registers. Let us assume that we
9248 can divide all insns into loads, stores, (integer) arithmetic
9249 operations, floating point operations, and branches.
9251 Here we will concern ourselves with determining the effect of an insn on
9252 the condition code and will limit ourselves to the following possible
9253 effects: The condition code can be set unpredictably (clobbered), not
9254 be changed, be set to agree with the results of the operation, or only
9255 changed if the item previously set into the condition code has been
9258 Here is part of a sample @file{md} file for such a machine:
9261 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
9263 (define_attr "cc" "clobber,unchanged,set,change0"
9264 (cond [(eq_attr "type" "load")
9265 (const_string "change0")
9266 (eq_attr "type" "store,branch")
9267 (const_string "unchanged")
9268 (eq_attr "type" "arith")
9269 (if_then_else (match_operand:SI 0 "" "")
9270 (const_string "set")
9271 (const_string "clobber"))]
9272 (const_string "clobber")))
9275 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
9276 (match_operand:SI 1 "general_operand" "r,m,r"))]
9282 [(set_attr "type" "arith,load,store")])
9285 Note that we assume in the above example that arithmetic operations
9286 performed on quantities smaller than a machine word clobber the condition
9287 code since they will set the condition code to a value corresponding to the
9293 @subsection Computing the Length of an Insn
9294 @cindex insn lengths, computing
9295 @cindex computing the length of an insn
9297 For many machines, multiple types of branch instructions are provided, each
9298 for different length branch displacements. In most cases, the assembler
9299 will choose the correct instruction to use. However, when the assembler
9300 cannot do so, GCC can when a special attribute, the @code{length}
9301 attribute, is defined. This attribute must be defined to have numeric
9302 values by specifying a null string in its @code{define_attr}.
9304 In the case of the @code{length} attribute, two additional forms of
9305 arithmetic terms are allowed in test expressions:
9308 @cindex @code{match_dup} and attributes
9309 @item (match_dup @var{n})
9310 This refers to the address of operand @var{n} of the current insn, which
9311 must be a @code{label_ref}.
9313 @cindex @code{pc} and attributes
9315 For non-branch instructions and backward branch instructions, this refers
9316 to the address of the current insn. But for forward branch instructions,
9317 this refers to the address of the next insn, because the length of the
9318 current insn is to be computed.
9321 @cindex @code{addr_vec}, length of
9322 @cindex @code{addr_diff_vec}, length of
9323 For normal insns, the length will be determined by value of the
9324 @code{length} attribute. In the case of @code{addr_vec} and
9325 @code{addr_diff_vec} insn patterns, the length is computed as
9326 the number of vectors multiplied by the size of each vector.
9328 Lengths are measured in addressable storage units (bytes).
9330 Note that it is possible to call functions via the @code{symbol_ref}
9331 mechanism to compute the length of an insn. However, if you use this
9332 mechanism you must provide dummy clauses to express the maximum length
9333 without using the function call. You can an example of this in the
9334 @code{pa} machine description for the @code{call_symref} pattern.
9336 The following macros can be used to refine the length computation:
9339 @findex ADJUST_INSN_LENGTH
9340 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
9341 If defined, modifies the length assigned to instruction @var{insn} as a
9342 function of the context in which it is used. @var{length} is an lvalue
9343 that contains the initially computed length of the insn and should be
9344 updated with the correct length of the insn.
9346 This macro will normally not be required. A case in which it is
9347 required is the ROMP@. On this machine, the size of an @code{addr_vec}
9348 insn must be increased by two to compensate for the fact that alignment
9352 @findex get_attr_length
9353 The routine that returns @code{get_attr_length} (the value of the
9354 @code{length} attribute) can be used by the output routine to
9355 determine the form of the branch instruction to be written, as the
9356 example below illustrates.
9358 As an example of the specification of variable-length branches, consider
9359 the IBM 360. If we adopt the convention that a register will be set to
9360 the starting address of a function, we can jump to labels within 4k of
9361 the start using a four-byte instruction. Otherwise, we need a six-byte
9362 sequence to load the address from memory and then branch to it.
9364 On such a machine, a pattern for a branch instruction might be specified
9370 (label_ref (match_operand 0 "" "")))]
9373 return (get_attr_length (insn) == 4
9374 ? "b %l0" : "l r15,=a(%l0); br r15");
9376 [(set (attr "length")
9377 (if_then_else (lt (match_dup 0) (const_int 4096))
9384 @node Constant Attributes
9385 @subsection Constant Attributes
9386 @cindex constant attributes
9388 A special form of @code{define_attr}, where the expression for the
9389 default value is a @code{const} expression, indicates an attribute that
9390 is constant for a given run of the compiler. Constant attributes may be
9391 used to specify which variety of processor is used. For example,
9394 (define_attr "cpu" "m88100,m88110,m88000"
9396 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
9397 (symbol_ref "TARGET_88110") (const_string "m88110")]
9398 (const_string "m88000"))))
9400 (define_attr "memory" "fast,slow"
9402 (if_then_else (symbol_ref "TARGET_FAST_MEM")
9403 (const_string "fast")
9404 (const_string "slow"))))
9407 The routine generated for constant attributes has no parameters as it
9408 does not depend on any particular insn. RTL expressions used to define
9409 the value of a constant attribute may use the @code{symbol_ref} form,
9410 but may not use either the @code{match_operand} form or @code{eq_attr}
9411 forms involving insn attributes.
9415 @node Mnemonic Attribute
9416 @subsection Mnemonic Attribute
9417 @cindex mnemonic attribute
9419 The @code{mnemonic} attribute is a string type attribute holding the
9420 instruction mnemonic for an insn alternative. The attribute values
9421 will automatically be generated by the machine description parser if
9422 there is an attribute definition in the md file:
9425 (define_attr "mnemonic" "unknown" (const_string "unknown"))
9428 The default value can be freely chosen as long as it does not collide
9429 with any of the instruction mnemonics. This value will be used
9430 whenever the machine description parser is not able to determine the
9431 mnemonic string. This might be the case for output templates
9432 containing more than a single instruction as in
9433 @code{"mvcle\t%0,%1,0\;jo\t.-4"}.
9435 The @code{mnemonic} attribute set is not generated automatically if the
9436 instruction string is generated via C code.
9438 An existing @code{mnemonic} attribute set in an insn definition will not
9439 be overriden by the md file parser. That way it is possible to
9440 manually set the instruction mnemonics for the cases where the md file
9441 parser fails to determine it automatically.
9443 The @code{mnemonic} attribute is useful for dealing with instruction
9444 specific properties in the pipeline description without defining
9445 additional insn attributes.
9448 (define_attr "ooo_expanded" ""
9449 (cond [(eq_attr "mnemonic" "dlr,dsgr,d,dsgf,stam,dsgfr,dlgr")
9457 @subsection Delay Slot Scheduling
9458 @cindex delay slots, defining
9460 The insn attribute mechanism can be used to specify the requirements for
9461 delay slots, if any, on a target machine. An instruction is said to
9462 require a @dfn{delay slot} if some instructions that are physically
9463 after the instruction are executed as if they were located before it.
9464 Classic examples are branch and call instructions, which often execute
9465 the following instruction before the branch or call is performed.
9467 On some machines, conditional branch instructions can optionally
9468 @dfn{annul} instructions in the delay slot. This means that the
9469 instruction will not be executed for certain branch outcomes. Both
9470 instructions that annul if the branch is true and instructions that
9471 annul if the branch is false are supported.
9473 Delay slot scheduling differs from instruction scheduling in that
9474 determining whether an instruction needs a delay slot is dependent only
9475 on the type of instruction being generated, not on data flow between the
9476 instructions. See the next section for a discussion of data-dependent
9477 instruction scheduling.
9479 @findex define_delay
9480 The requirement of an insn needing one or more delay slots is indicated
9481 via the @code{define_delay} expression. It has the following form:
9484 (define_delay @var{test}
9485 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
9486 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
9490 @var{test} is an attribute test that indicates whether this
9491 @code{define_delay} applies to a particular insn. If so, the number of
9492 required delay slots is determined by the length of the vector specified
9493 as the second argument. An insn placed in delay slot @var{n} must
9494 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
9495 attribute test that specifies which insns may be annulled if the branch
9496 is true. Similarly, @var{annul-false-n} specifies which insns in the
9497 delay slot may be annulled if the branch is false. If annulling is not
9498 supported for that delay slot, @code{(nil)} should be coded.
9500 For example, in the common case where branch and call insns require
9501 a single delay slot, which may contain any insn other than a branch or
9502 call, the following would be placed in the @file{md} file:
9505 (define_delay (eq_attr "type" "branch,call")
9506 [(eq_attr "type" "!branch,call") (nil) (nil)])
9509 Multiple @code{define_delay} expressions may be specified. In this
9510 case, each such expression specifies different delay slot requirements
9511 and there must be no insn for which tests in two @code{define_delay}
9512 expressions are both true.
9514 For example, if we have a machine that requires one delay slot for branches
9515 but two for calls, no delay slot can contain a branch or call insn,
9516 and any valid insn in the delay slot for the branch can be annulled if the
9517 branch is true, we might represent this as follows:
9520 (define_delay (eq_attr "type" "branch")
9521 [(eq_attr "type" "!branch,call")
9522 (eq_attr "type" "!branch,call")
9525 (define_delay (eq_attr "type" "call")
9526 [(eq_attr "type" "!branch,call") (nil) (nil)
9527 (eq_attr "type" "!branch,call") (nil) (nil)])
9529 @c the above is *still* too long. --mew 4feb93
9533 @node Processor pipeline description
9534 @subsection Specifying processor pipeline description
9535 @cindex processor pipeline description
9536 @cindex processor functional units
9537 @cindex instruction latency time
9538 @cindex interlock delays
9539 @cindex data dependence delays
9540 @cindex reservation delays
9541 @cindex pipeline hazard recognizer
9542 @cindex automaton based pipeline description
9543 @cindex regular expressions
9544 @cindex deterministic finite state automaton
9545 @cindex automaton based scheduler
9549 To achieve better performance, most modern processors
9550 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
9551 processors) have many @dfn{functional units} on which several
9552 instructions can be executed simultaneously. An instruction starts
9553 execution if its issue conditions are satisfied. If not, the
9554 instruction is stalled until its conditions are satisfied. Such
9555 @dfn{interlock (pipeline) delay} causes interruption of the fetching
9556 of successor instructions (or demands nop instructions, e.g.@: for some
9559 There are two major kinds of interlock delays in modern processors.
9560 The first one is a data dependence delay determining @dfn{instruction
9561 latency time}. The instruction execution is not started until all
9562 source data have been evaluated by prior instructions (there are more
9563 complex cases when the instruction execution starts even when the data
9564 are not available but will be ready in given time after the
9565 instruction execution start). Taking the data dependence delays into
9566 account is simple. The data dependence (true, output, and
9567 anti-dependence) delay between two instructions is given by a
9568 constant. In most cases this approach is adequate. The second kind
9569 of interlock delays is a reservation delay. The reservation delay
9570 means that two instructions under execution will be in need of shared
9571 processors resources, i.e.@: buses, internal registers, and/or
9572 functional units, which are reserved for some time. Taking this kind
9573 of delay into account is complex especially for modern @acronym{RISC}
9576 The task of exploiting more processor parallelism is solved by an
9577 instruction scheduler. For a better solution to this problem, the
9578 instruction scheduler has to have an adequate description of the
9579 processor parallelism (or @dfn{pipeline description}). GCC
9580 machine descriptions describe processor parallelism and functional
9581 unit reservations for groups of instructions with the aid of
9582 @dfn{regular expressions}.
9584 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
9585 figure out the possibility of the instruction issue by the processor
9586 on a given simulated processor cycle. The pipeline hazard recognizer is
9587 automatically generated from the processor pipeline description. The
9588 pipeline hazard recognizer generated from the machine description
9589 is based on a deterministic finite state automaton (@acronym{DFA}):
9590 the instruction issue is possible if there is a transition from one
9591 automaton state to another one. This algorithm is very fast, and
9592 furthermore, its speed is not dependent on processor
9593 complexity@footnote{However, the size of the automaton depends on
9594 processor complexity. To limit this effect, machine descriptions
9595 can split orthogonal parts of the machine description among several
9596 automata: but then, since each of these must be stepped independently,
9597 this does cause a small decrease in the algorithm's performance.}.
9599 @cindex automaton based pipeline description
9600 The rest of this section describes the directives that constitute
9601 an automaton-based processor pipeline description. The order of
9602 these constructions within the machine description file is not
9605 @findex define_automaton
9606 @cindex pipeline hazard recognizer
9607 The following optional construction describes names of automata
9608 generated and used for the pipeline hazards recognition. Sometimes
9609 the generated finite state automaton used by the pipeline hazard
9610 recognizer is large. If we use more than one automaton and bind functional
9611 units to the automata, the total size of the automata is usually
9612 less than the size of the single automaton. If there is no one such
9613 construction, only one finite state automaton is generated.
9616 (define_automaton @var{automata-names})
9619 @var{automata-names} is a string giving names of the automata. The
9620 names are separated by commas. All the automata should have unique names.
9621 The automaton name is used in the constructions @code{define_cpu_unit} and
9622 @code{define_query_cpu_unit}.
9624 @findex define_cpu_unit
9625 @cindex processor functional units
9626 Each processor functional unit used in the description of instruction
9627 reservations should be described by the following construction.
9630 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
9633 @var{unit-names} is a string giving the names of the functional units
9634 separated by commas. Don't use name @samp{nothing}, it is reserved
9637 @var{automaton-name} is a string giving the name of the automaton with
9638 which the unit is bound. The automaton should be described in
9639 construction @code{define_automaton}. You should give
9640 @dfn{automaton-name}, if there is a defined automaton.
9642 The assignment of units to automata are constrained by the uses of the
9643 units in insn reservations. The most important constraint is: if a
9644 unit reservation is present on a particular cycle of an alternative
9645 for an insn reservation, then some unit from the same automaton must
9646 be present on the same cycle for the other alternatives of the insn
9647 reservation. The rest of the constraints are mentioned in the
9648 description of the subsequent constructions.
9650 @findex define_query_cpu_unit
9651 @cindex querying function unit reservations
9652 The following construction describes CPU functional units analogously
9653 to @code{define_cpu_unit}. The reservation of such units can be
9654 queried for an automaton state. The instruction scheduler never
9655 queries reservation of functional units for given automaton state. So
9656 as a rule, you don't need this construction. This construction could
9657 be used for future code generation goals (e.g.@: to generate
9658 @acronym{VLIW} insn templates).
9661 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
9664 @var{unit-names} is a string giving names of the functional units
9665 separated by commas.
9667 @var{automaton-name} is a string giving the name of the automaton with
9668 which the unit is bound.
9670 @findex define_insn_reservation
9671 @cindex instruction latency time
9672 @cindex regular expressions
9674 The following construction is the major one to describe pipeline
9675 characteristics of an instruction.
9678 (define_insn_reservation @var{insn-name} @var{default_latency}
9679 @var{condition} @var{regexp})
9682 @var{default_latency} is a number giving latency time of the
9683 instruction. There is an important difference between the old
9684 description and the automaton based pipeline description. The latency
9685 time is used for all dependencies when we use the old description. In
9686 the automaton based pipeline description, the given latency time is only
9687 used for true dependencies. The cost of anti-dependencies is always
9688 zero and the cost of output dependencies is the difference between
9689 latency times of the producing and consuming insns (if the difference
9690 is negative, the cost is considered to be zero). You can always
9691 change the default costs for any description by using the target hook
9692 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
9694 @var{insn-name} is a string giving the internal name of the insn. The
9695 internal names are used in constructions @code{define_bypass} and in
9696 the automaton description file generated for debugging. The internal
9697 name has nothing in common with the names in @code{define_insn}. It is a
9698 good practice to use insn classes described in the processor manual.
9700 @var{condition} defines what RTL insns are described by this
9701 construction. You should remember that you will be in trouble if
9702 @var{condition} for two or more different
9703 @code{define_insn_reservation} constructions is TRUE for an insn. In
9704 this case what reservation will be used for the insn is not defined.
9705 Such cases are not checked during generation of the pipeline hazards
9706 recognizer because in general recognizing that two conditions may have
9707 the same value is quite difficult (especially if the conditions
9708 contain @code{symbol_ref}). It is also not checked during the
9709 pipeline hazard recognizer work because it would slow down the
9710 recognizer considerably.
9712 @var{regexp} is a string describing the reservation of the cpu's functional
9713 units by the instruction. The reservations are described by a regular
9714 expression according to the following syntax:
9717 regexp = regexp "," oneof
9720 oneof = oneof "|" allof
9723 allof = allof "+" repeat
9726 repeat = element "*" number
9729 element = cpu_function_unit_name
9738 @samp{,} is used for describing the start of the next cycle in
9742 @samp{|} is used for describing a reservation described by the first
9743 regular expression @strong{or} a reservation described by the second
9744 regular expression @strong{or} etc.
9747 @samp{+} is used for describing a reservation described by the first
9748 regular expression @strong{and} a reservation described by the
9749 second regular expression @strong{and} etc.
9752 @samp{*} is used for convenience and simply means a sequence in which
9753 the regular expression are repeated @var{number} times with cycle
9754 advancing (see @samp{,}).
9757 @samp{cpu_function_unit_name} denotes reservation of the named
9761 @samp{reservation_name} --- see description of construction
9762 @samp{define_reservation}.
9765 @samp{nothing} denotes no unit reservations.
9768 @findex define_reservation
9769 Sometimes unit reservations for different insns contain common parts.
9770 In such case, you can simplify the pipeline description by describing
9771 the common part by the following construction
9774 (define_reservation @var{reservation-name} @var{regexp})
9777 @var{reservation-name} is a string giving name of @var{regexp}.
9778 Functional unit names and reservation names are in the same name
9779 space. So the reservation names should be different from the
9780 functional unit names and can not be the reserved name @samp{nothing}.
9782 @findex define_bypass
9783 @cindex instruction latency time
9785 The following construction is used to describe exceptions in the
9786 latency time for given instruction pair. This is so called bypasses.
9789 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
9793 @var{number} defines when the result generated by the instructions
9794 given in string @var{out_insn_names} will be ready for the
9795 instructions given in string @var{in_insn_names}. Each of these
9796 strings is a comma-separated list of filename-style globs and
9797 they refer to the names of @code{define_insn_reservation}s.
9800 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
9802 defines a bypass between instructions that start with
9803 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
9806 @var{guard} is an optional string giving the name of a C function which
9807 defines an additional guard for the bypass. The function will get the
9808 two insns as parameters. If the function returns zero the bypass will
9809 be ignored for this case. The additional guard is necessary to
9810 recognize complicated bypasses, e.g.@: when the consumer is only an address
9811 of insn @samp{store} (not a stored value).
9813 If there are more one bypass with the same output and input insns, the
9814 chosen bypass is the first bypass with a guard in description whose
9815 guard function returns nonzero. If there is no such bypass, then
9816 bypass without the guard function is chosen.
9818 @findex exclusion_set
9819 @findex presence_set
9820 @findex final_presence_set
9822 @findex final_absence_set
9825 The following five constructions are usually used to describe
9826 @acronym{VLIW} processors, or more precisely, to describe a placement
9827 of small instructions into @acronym{VLIW} instruction slots. They
9828 can be used for @acronym{RISC} processors, too.
9831 (exclusion_set @var{unit-names} @var{unit-names})
9832 (presence_set @var{unit-names} @var{patterns})
9833 (final_presence_set @var{unit-names} @var{patterns})
9834 (absence_set @var{unit-names} @var{patterns})
9835 (final_absence_set @var{unit-names} @var{patterns})
9838 @var{unit-names} is a string giving names of functional units
9839 separated by commas.
9841 @var{patterns} is a string giving patterns of functional units
9842 separated by comma. Currently pattern is one unit or units
9843 separated by white-spaces.
9845 The first construction (@samp{exclusion_set}) means that each
9846 functional unit in the first string can not be reserved simultaneously
9847 with a unit whose name is in the second string and vice versa. For
9848 example, the construction is useful for describing processors
9849 (e.g.@: some SPARC processors) with a fully pipelined floating point
9850 functional unit which can execute simultaneously only single floating
9851 point insns or only double floating point insns.
9853 The second construction (@samp{presence_set}) means that each
9854 functional unit in the first string can not be reserved unless at
9855 least one of pattern of units whose names are in the second string is
9856 reserved. This is an asymmetric relation. For example, it is useful
9857 for description that @acronym{VLIW} @samp{slot1} is reserved after
9858 @samp{slot0} reservation. We could describe it by the following
9862 (presence_set "slot1" "slot0")
9865 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
9866 reservation. In this case we could write
9869 (presence_set "slot1" "slot0 b0")
9872 The third construction (@samp{final_presence_set}) is analogous to
9873 @samp{presence_set}. The difference between them is when checking is
9874 done. When an instruction is issued in given automaton state
9875 reflecting all current and planned unit reservations, the automaton
9876 state is changed. The first state is a source state, the second one
9877 is a result state. Checking for @samp{presence_set} is done on the
9878 source state reservation, checking for @samp{final_presence_set} is
9879 done on the result reservation. This construction is useful to
9880 describe a reservation which is actually two subsequent reservations.
9881 For example, if we use
9884 (presence_set "slot1" "slot0")
9887 the following insn will be never issued (because @samp{slot1} requires
9888 @samp{slot0} which is absent in the source state).
9891 (define_reservation "insn_and_nop" "slot0 + slot1")
9894 but it can be issued if we use analogous @samp{final_presence_set}.
9896 The forth construction (@samp{absence_set}) means that each functional
9897 unit in the first string can be reserved only if each pattern of units
9898 whose names are in the second string is not reserved. This is an
9899 asymmetric relation (actually @samp{exclusion_set} is analogous to
9900 this one but it is symmetric). For example it might be useful in a
9901 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
9902 after either @samp{slot1} or @samp{slot2} have been reserved. This
9903 can be described as:
9906 (absence_set "slot0" "slot1, slot2")
9909 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
9910 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
9911 this case we could write
9914 (absence_set "slot2" "slot0 b0, slot1 b1")
9917 All functional units mentioned in a set should belong to the same
9920 The last construction (@samp{final_absence_set}) is analogous to
9921 @samp{absence_set} but checking is done on the result (state)
9922 reservation. See comments for @samp{final_presence_set}.
9924 @findex automata_option
9925 @cindex deterministic finite state automaton
9926 @cindex nondeterministic finite state automaton
9927 @cindex finite state automaton minimization
9928 You can control the generator of the pipeline hazard recognizer with
9929 the following construction.
9932 (automata_option @var{options})
9935 @var{options} is a string giving options which affect the generated
9936 code. Currently there are the following options:
9940 @dfn{no-minimization} makes no minimization of the automaton. This is
9941 only worth to do when we are debugging the description and need to
9942 look more accurately at reservations of states.
9945 @dfn{time} means printing time statistics about the generation of
9949 @dfn{stats} means printing statistics about the generated automata
9950 such as the number of DFA states, NDFA states and arcs.
9953 @dfn{v} means a generation of the file describing the result automata.
9954 The file has suffix @samp{.dfa} and can be used for the description
9955 verification and debugging.
9958 @dfn{w} means a generation of warning instead of error for
9959 non-critical errors.
9962 @dfn{no-comb-vect} prevents the automaton generator from generating
9963 two data structures and comparing them for space efficiency. Using
9964 a comb vector to represent transitions may be better, but it can be
9965 very expensive to construct. This option is useful if the build
9966 process spends an unacceptably long time in genautomata.
9969 @dfn{ndfa} makes nondeterministic finite state automata. This affects
9970 the treatment of operator @samp{|} in the regular expressions. The
9971 usual treatment of the operator is to try the first alternative and,
9972 if the reservation is not possible, the second alternative. The
9973 nondeterministic treatment means trying all alternatives, some of them
9974 may be rejected by reservations in the subsequent insns.
9977 @dfn{collapse-ndfa} modifies the behavior of the generator when
9978 producing an automaton. An additional state transition to collapse a
9979 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
9980 state is generated. It can be triggered by passing @code{const0_rtx} to
9981 state_transition. In such an automaton, cycle advance transitions are
9982 available only for these collapsed states. This option is useful for
9983 ports that want to use the @code{ndfa} option, but also want to use
9984 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
9987 @dfn{progress} means output of a progress bar showing how many states
9988 were generated so far for automaton being processed. This is useful
9989 during debugging a @acronym{DFA} description. If you see too many
9990 generated states, you could interrupt the generator of the pipeline
9991 hazard recognizer and try to figure out a reason for generation of the
9995 As an example, consider a superscalar @acronym{RISC} machine which can
9996 issue three insns (two integer insns and one floating point insn) on
9997 the cycle but can finish only two insns. To describe this, we define
9998 the following functional units.
10001 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
10002 (define_cpu_unit "port0, port1")
10005 All simple integer insns can be executed in any integer pipeline and
10006 their result is ready in two cycles. The simple integer insns are
10007 issued into the first pipeline unless it is reserved, otherwise they
10008 are issued into the second pipeline. Integer division and
10009 multiplication insns can be executed only in the second integer
10010 pipeline and their results are ready correspondingly in 9 and 4
10011 cycles. The integer division is not pipelined, i.e.@: the subsequent
10012 integer division insn can not be issued until the current division
10013 insn finished. Floating point insns are fully pipelined and their
10014 results are ready in 3 cycles. Where the result of a floating point
10015 insn is used by an integer insn, an additional delay of one cycle is
10016 incurred. To describe all of this we could specify
10019 (define_cpu_unit "div")
10021 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
10022 "(i0_pipeline | i1_pipeline), (port0 | port1)")
10024 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
10025 "i1_pipeline, nothing*2, (port0 | port1)")
10027 (define_insn_reservation "div" 9 (eq_attr "type" "div")
10028 "i1_pipeline, div*7, div + (port0 | port1)")
10030 (define_insn_reservation "float" 3 (eq_attr "type" "float")
10031 "f_pipeline, nothing, (port0 | port1))
10033 (define_bypass 4 "float" "simple,mult,div")
10036 To simplify the description we could describe the following reservation
10039 (define_reservation "finish" "port0|port1")
10042 and use it in all @code{define_insn_reservation} as in the following
10046 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
10047 "(i0_pipeline | i1_pipeline), finish")
10053 @node Conditional Execution
10054 @section Conditional Execution
10055 @cindex conditional execution
10056 @cindex predication
10058 A number of architectures provide for some form of conditional
10059 execution, or predication. The hallmark of this feature is the
10060 ability to nullify most of the instructions in the instruction set.
10061 When the instruction set is large and not entirely symmetric, it
10062 can be quite tedious to describe these forms directly in the
10063 @file{.md} file. An alternative is the @code{define_cond_exec} template.
10065 @findex define_cond_exec
10068 [@var{predicate-pattern}]
10070 "@var{output-template}"
10071 "@var{optional-insn-attribues}")
10074 @var{predicate-pattern} is the condition that must be true for the
10075 insn to be executed at runtime and should match a relational operator.
10076 One can use @code{match_operator} to match several relational operators
10077 at once. Any @code{match_operand} operands must have no more than one
10080 @var{condition} is a C expression that must be true for the generated
10083 @findex current_insn_predicate
10084 @var{output-template} is a string similar to the @code{define_insn}
10085 output template (@pxref{Output Template}), except that the @samp{*}
10086 and @samp{@@} special cases do not apply. This is only useful if the
10087 assembly text for the predicate is a simple prefix to the main insn.
10088 In order to handle the general case, there is a global variable
10089 @code{current_insn_predicate} that will contain the entire predicate
10090 if the current insn is predicated, and will otherwise be @code{NULL}.
10092 @var{optional-insn-attributes} is an optional vector of attributes that gets
10093 appended to the insn attributes of the produced cond_exec rtx. It can
10094 be used to add some distinguishing attribute to cond_exec rtxs produced
10095 that way. An example usage would be to use this attribute in conjunction
10096 with attributes on the main pattern to disable particular alternatives under
10097 certain conditions.
10099 When @code{define_cond_exec} is used, an implicit reference to
10100 the @code{predicable} instruction attribute is made.
10101 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
10102 exactly two elements in its @var{list-of-values}), with the possible
10103 values being @code{no} and @code{yes}. The default and all uses in
10104 the insns must be a simple constant, not a complex expressions. It
10105 may, however, depend on the alternative, by using a comma-separated
10106 list of values. If that is the case, the port should also define an
10107 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
10108 should also allow only @code{no} and @code{yes} as its values.
10110 For each @code{define_insn} for which the @code{predicable}
10111 attribute is true, a new @code{define_insn} pattern will be
10112 generated that matches a predicated version of the instruction.
10116 (define_insn "addsi"
10117 [(set (match_operand:SI 0 "register_operand" "r")
10118 (plus:SI (match_operand:SI 1 "register_operand" "r")
10119 (match_operand:SI 2 "register_operand" "r")))]
10124 [(ne (match_operand:CC 0 "register_operand" "c")
10131 generates a new pattern
10136 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
10137 (set (match_operand:SI 0 "register_operand" "r")
10138 (plus:SI (match_operand:SI 1 "register_operand" "r")
10139 (match_operand:SI 2 "register_operand" "r"))))]
10140 "(@var{test2}) && (@var{test1})"
10141 "(%3) add %2,%1,%0")
10147 @section RTL Templates Transformations
10148 @cindex define_subst
10150 For some hardware architectures there are common cases when the RTL
10151 templates for the instructions can be derived from the other RTL
10152 templates using simple transformations. E.g., @file{i386.md} contains
10153 an RTL template for the ordinary @code{sub} instruction---
10154 @code{*subsi_1}, and for the @code{sub} instruction with subsequent
10155 zero-extension---@code{*subsi_1_zext}. Such cases can be easily
10156 implemented by a single meta-template capable of generating a modified
10157 case based on the initial one:
10159 @findex define_subst
10161 (define_subst "@var{name}"
10162 [@var{input-template}]
10164 [@var{output-template}])
10166 @var{input-template} is a pattern describing the source RTL template,
10167 which will be transformed.
10169 @var{condition} is a C expression that is conjunct with the condition
10170 from the input-template to generate a condition to be used in the
10173 @var{output-template} is a pattern that will be used in the resulting
10176 @code{define_subst} mechanism is tightly coupled with the notion of the
10177 subst attribute (@pxref{Subst Iterators}). The use of
10178 @code{define_subst} is triggered by a reference to a subst attribute in
10179 the transforming RTL template. This reference initiates duplication of
10180 the source RTL template and substitution of the attributes with their
10181 values. The source RTL template is left unchanged, while the copy is
10182 transformed by @code{define_subst}. This transformation can fail in the
10183 case when the source RTL template is not matched against the
10184 input-template of the @code{define_subst}. In such case the copy is
10187 @code{define_subst} can be used only in @code{define_insn} and
10188 @code{define_expand}, it cannot be used in other expressions (e.g. in
10189 @code{define_insn_and_split}).
10192 * Define Subst Example:: Example of @code{define_subst} work.
10193 * Define Subst Pattern Matching:: Process of template comparison.
10194 * Define Subst Output Template:: Generation of output template.
10197 @node Define Subst Example
10198 @subsection @code{define_subst} Example
10199 @cindex define_subst
10201 To illustrate how @code{define_subst} works, let us examine a simple
10202 template transformation.
10204 Suppose there are two kinds of instructions: one that touches flags and
10205 the other that does not. The instructions of the second type could be
10206 generated with the following @code{define_subst}:
10209 (define_subst "add_clobber_subst"
10210 [(set (match_operand:SI 0 "" "")
10211 (match_operand:SI 1 "" ""))]
10213 [(set (match_dup 0)
10215 (clobber (reg:CC FLAGS_REG))]
10218 This @code{define_subst} can be applied to any RTL pattern containing
10219 @code{set} of mode SI and generates a copy with clobber when it is
10222 Assume there is an RTL template for a @code{max} instruction to be used
10223 in @code{define_subst} mentioned above:
10226 (define_insn "maxsi"
10227 [(set (match_operand:SI 0 "register_operand" "=r")
10229 (match_operand:SI 1 "register_operand" "r")
10230 (match_operand:SI 2 "register_operand" "r")))]
10232 "max\t@{%2, %1, %0|%0, %1, %2@}"
10236 To mark the RTL template for @code{define_subst} application,
10237 subst-attributes are used. They should be declared in advance:
10240 (define_subst_attr "add_clobber_name" "add_clobber_subst" "_noclobber" "_clobber")
10243 Here @samp{add_clobber_name} is the attribute name,
10244 @samp{add_clobber_subst} is the name of the corresponding
10245 @code{define_subst}, the third argument (@samp{_noclobber}) is the
10246 attribute value that would be substituted into the unchanged version of
10247 the source RTL template, and the last argument (@samp{_clobber}) is the
10248 value that would be substituted into the second, transformed,
10249 version of the RTL template.
10251 Once the subst-attribute has been defined, it should be used in RTL
10252 templates which need to be processed by the @code{define_subst}. So,
10253 the original RTL template should be changed:
10256 (define_insn "maxsi<add_clobber_name>"
10257 [(set (match_operand:SI 0 "register_operand" "=r")
10259 (match_operand:SI 1 "register_operand" "r")
10260 (match_operand:SI 2 "register_operand" "r")))]
10262 "max\t@{%2, %1, %0|%0, %1, %2@}"
10266 The result of the @code{define_subst} usage would look like the following:
10269 (define_insn "maxsi_noclobber"
10270 [(set (match_operand:SI 0 "register_operand" "=r")
10272 (match_operand:SI 1 "register_operand" "r")
10273 (match_operand:SI 2 "register_operand" "r")))]
10275 "max\t@{%2, %1, %0|%0, %1, %2@}"
10277 (define_insn "maxsi_clobber"
10278 [(set (match_operand:SI 0 "register_operand" "=r")
10280 (match_operand:SI 1 "register_operand" "r")
10281 (match_operand:SI 2 "register_operand" "r")))
10282 (clobber (reg:CC FLAGS_REG))]
10284 "max\t@{%2, %1, %0|%0, %1, %2@}"
10288 @node Define Subst Pattern Matching
10289 @subsection Pattern Matching in @code{define_subst}
10290 @cindex define_subst
10292 All expressions, allowed in @code{define_insn} or @code{define_expand},
10293 are allowed in the input-template of @code{define_subst}, except
10294 @code{match_par_dup}, @code{match_scratch}, @code{match_parallel}. The
10295 meanings of expressions in the input-template were changed:
10297 @code{match_operand} matches any expression (possibly, a subtree in
10298 RTL-template), if modes of the @code{match_operand} and this expression
10299 are the same, or mode of the @code{match_operand} is @code{VOIDmode}, or
10300 this expression is @code{match_dup}, @code{match_op_dup}. If the
10301 expression is @code{match_operand} too, and predicate of
10302 @code{match_operand} from the input pattern is not empty, then the
10303 predicates are compared. That can be used for more accurate filtering
10304 of accepted RTL-templates.
10306 @code{match_operator} matches common operators (like @code{plus},
10307 @code{minus}), @code{unspec}, @code{unspec_volatile} operators and
10308 @code{match_operator}s from the original pattern if the modes match and
10309 @code{match_operator} from the input pattern has the same number of
10310 operands as the operator from the original pattern.
10312 @node Define Subst Output Template
10313 @subsection Generation of output template in @code{define_subst}
10314 @cindex define_subst
10316 If all necessary checks for @code{define_subst} application pass, a new
10317 RTL-pattern, based on the output-template, is created to replace the old
10318 template. Like in input-patterns, meanings of some RTL expressions are
10319 changed when they are used in output-patterns of a @code{define_subst}.
10320 Thus, @code{match_dup} is used for copying the whole expression from the
10321 original pattern, which matched corresponding @code{match_operand} from
10324 @code{match_dup N} is used in the output template to be replaced with
10325 the expression from the original pattern, which matched
10326 @code{match_operand N} from the input pattern. As a consequence,
10327 @code{match_dup} cannot be used to point to @code{match_operand}s from
10328 the output pattern, it should always refer to a @code{match_operand}
10329 from the input pattern. If a @code{match_dup N} occurs more than once
10330 in the output template, its first occurrence is replaced with the
10331 expression from the original pattern, and the subsequent expressions
10332 are replaced with @code{match_dup N}, i.e., a reference to the first
10335 In the output template one can refer to the expressions from the
10336 original pattern and create new ones. For instance, some operands could
10337 be added by means of standard @code{match_operand}.
10339 After replacing @code{match_dup} with some RTL-subtree from the original
10340 pattern, it could happen that several @code{match_operand}s in the
10341 output pattern have the same indexes. It is unknown, how many and what
10342 indexes would be used in the expression which would replace
10343 @code{match_dup}, so such conflicts in indexes are inevitable. To
10344 overcome this issue, @code{match_operands} and @code{match_operators},
10345 which were introduced into the output pattern, are renumerated when all
10346 @code{match_dup}s are replaced.
10348 Number of alternatives in @code{match_operand}s introduced into the
10349 output template @code{M} could differ from the number of alternatives in
10350 the original pattern @code{N}, so in the resultant pattern there would
10351 be @code{N*M} alternatives. Thus, constraints from the original pattern
10352 would be duplicated @code{N} times, constraints from the output pattern
10353 would be duplicated @code{M} times, producing all possible combinations.
10357 @node Constant Definitions
10358 @section Constant Definitions
10359 @cindex constant definitions
10360 @findex define_constants
10362 Using literal constants inside instruction patterns reduces legibility and
10363 can be a maintenance problem.
10365 To overcome this problem, you may use the @code{define_constants}
10366 expression. It contains a vector of name-value pairs. From that
10367 point on, wherever any of the names appears in the MD file, it is as
10368 if the corresponding value had been written instead. You may use
10369 @code{define_constants} multiple times; each appearance adds more
10370 constants to the table. It is an error to redefine a constant with
10373 To come back to the a29k load multiple example, instead of
10377 [(match_parallel 0 "load_multiple_operation"
10378 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
10379 (match_operand:SI 2 "memory_operand" "m"))
10381 (clobber (reg:SI 179))])]
10389 (define_constants [
10397 [(match_parallel 0 "load_multiple_operation"
10398 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
10399 (match_operand:SI 2 "memory_operand" "m"))
10400 (use (reg:SI R_CR))
10401 (clobber (reg:SI R_CR))])]
10406 The constants that are defined with a define_constant are also output
10407 in the insn-codes.h header file as #defines.
10409 @cindex enumerations
10410 @findex define_c_enum
10411 You can also use the machine description file to define enumerations.
10412 Like the constants defined by @code{define_constant}, these enumerations
10413 are visible to both the machine description file and the main C code.
10415 The syntax is as follows:
10418 (define_c_enum "@var{name}" [
10426 This definition causes the equivalent of the following C code to appear
10427 in @file{insn-constants.h}:
10434 @var{valuen} = @var{n}
10436 #define NUM_@var{cname}_VALUES (@var{n} + 1)
10439 where @var{cname} is the capitalized form of @var{name}.
10440 It also makes each @var{valuei} available in the machine description
10441 file, just as if it had been declared with:
10444 (define_constants [(@var{valuei} @var{i})])
10447 Each @var{valuei} is usually an upper-case identifier and usually
10448 begins with @var{cname}.
10450 You can split the enumeration definition into as many statements as
10451 you like. The above example is directly equivalent to:
10454 (define_c_enum "@var{name}" [@var{value0}])
10455 (define_c_enum "@var{name}" [@var{value1}])
10457 (define_c_enum "@var{name}" [@var{valuen}])
10460 Splitting the enumeration helps to improve the modularity of each
10461 individual @code{.md} file. For example, if a port defines its
10462 synchronization instructions in a separate @file{sync.md} file,
10463 it is convenient to define all synchronization-specific enumeration
10464 values in @file{sync.md} rather than in the main @file{.md} file.
10466 Some enumeration names have special significance to GCC:
10470 @findex unspec_volatile
10471 If an enumeration called @code{unspecv} is defined, GCC will use it
10472 when printing out @code{unspec_volatile} expressions. For example:
10475 (define_c_enum "unspecv" [
10480 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
10483 (unspec_volatile ... UNSPECV_BLOCKAGE)
10488 If an enumeration called @code{unspec} is defined, GCC will use
10489 it when printing out @code{unspec} expressions. GCC will also use
10490 it when printing out @code{unspec_volatile} expressions unless an
10491 @code{unspecv} enumeration is also defined. You can therefore
10492 decide whether to keep separate enumerations for volatile and
10493 non-volatile expressions or whether to use the same enumeration
10497 @findex define_enum
10498 @anchor{define_enum}
10499 Another way of defining an enumeration is to use @code{define_enum}:
10502 (define_enum "@var{name}" [
10510 This directive implies:
10513 (define_c_enum "@var{name}" [
10514 @var{cname}_@var{cvalue0}
10515 @var{cname}_@var{cvalue1}
10517 @var{cname}_@var{cvaluen}
10521 @findex define_enum_attr
10522 where @var{cvaluei} is the capitalized form of @var{valuei}.
10523 However, unlike @code{define_c_enum}, the enumerations defined
10524 by @code{define_enum} can be used in attribute specifications
10525 (@pxref{define_enum_attr}).
10530 @cindex iterators in @file{.md} files
10532 Ports often need to define similar patterns for more than one machine
10533 mode or for more than one rtx code. GCC provides some simple iterator
10534 facilities to make this process easier.
10537 * Mode Iterators:: Generating variations of patterns for different modes.
10538 * Code Iterators:: Doing the same for codes.
10539 * Int Iterators:: Doing the same for integers.
10540 * Subst Iterators:: Generating variations of patterns for define_subst.
10541 * Parameterized Names:: Specifying iterator values in C++ code.
10544 @node Mode Iterators
10545 @subsection Mode Iterators
10546 @cindex mode iterators in @file{.md} files
10548 Ports often need to define similar patterns for two or more different modes.
10553 If a processor has hardware support for both single and double
10554 floating-point arithmetic, the @code{SFmode} patterns tend to be
10555 very similar to the @code{DFmode} ones.
10558 If a port uses @code{SImode} pointers in one configuration and
10559 @code{DImode} pointers in another, it will usually have very similar
10560 @code{SImode} and @code{DImode} patterns for manipulating pointers.
10563 Mode iterators allow several patterns to be instantiated from one
10564 @file{.md} file template. They can be used with any type of
10565 rtx-based construct, such as a @code{define_insn},
10566 @code{define_split}, or @code{define_peephole2}.
10569 * Defining Mode Iterators:: Defining a new mode iterator.
10570 * Substitutions:: Combining mode iterators with substitutions
10571 * Examples:: Examples
10574 @node Defining Mode Iterators
10575 @subsubsection Defining Mode Iterators
10576 @findex define_mode_iterator
10578 The syntax for defining a mode iterator is:
10581 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
10584 This allows subsequent @file{.md} file constructs to use the mode suffix
10585 @code{:@var{name}}. Every construct that does so will be expanded
10586 @var{n} times, once with every use of @code{:@var{name}} replaced by
10587 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
10588 and so on. In the expansion for a particular @var{modei}, every
10589 C condition will also require that @var{condi} be true.
10594 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
10597 defines a new mode suffix @code{:P}. Every construct that uses
10598 @code{:P} will be expanded twice, once with every @code{:P} replaced
10599 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
10600 The @code{:SI} version will only apply if @code{Pmode == SImode} and
10601 the @code{:DI} version will only apply if @code{Pmode == DImode}.
10603 As with other @file{.md} conditions, an empty string is treated
10604 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
10605 to @code{@var{mode}}. For example:
10608 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
10611 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
10612 but that the @code{:SI} expansion has no such constraint.
10614 Iterators are applied in the order they are defined. This can be
10615 significant if two iterators are used in a construct that requires
10616 substitutions. @xref{Substitutions}.
10618 @node Substitutions
10619 @subsubsection Substitution in Mode Iterators
10620 @findex define_mode_attr
10622 If an @file{.md} file construct uses mode iterators, each version of the
10623 construct will often need slightly different strings or modes. For
10628 When a @code{define_expand} defines several @code{add@var{m}3} patterns
10629 (@pxref{Standard Names}), each expander will need to use the
10630 appropriate mode name for @var{m}.
10633 When a @code{define_insn} defines several instruction patterns,
10634 each instruction will often use a different assembler mnemonic.
10637 When a @code{define_insn} requires operands with different modes,
10638 using an iterator for one of the operand modes usually requires a specific
10639 mode for the other operand(s).
10642 GCC supports such variations through a system of ``mode attributes''.
10643 There are two standard attributes: @code{mode}, which is the name of
10644 the mode in lower case, and @code{MODE}, which is the same thing in
10645 upper case. You can define other attributes using:
10648 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
10651 where @var{name} is the name of the attribute and @var{valuei}
10652 is the value associated with @var{modei}.
10654 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
10655 each string and mode in the pattern for sequences of the form
10656 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
10657 mode attribute. If the attribute is defined for @var{mode}, the whole
10658 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
10661 For example, suppose an @file{.md} file has:
10664 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
10665 (define_mode_attr load [(SI "lw") (DI "ld")])
10668 If one of the patterns that uses @code{:P} contains the string
10669 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
10670 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
10671 @code{"ld\t%0,%1"}.
10673 Here is an example of using an attribute for a mode:
10676 (define_mode_iterator LONG [SI DI])
10677 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
10678 (define_insn @dots{}
10679 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
10682 The @code{@var{iterator}:} prefix may be omitted, in which case the
10683 substitution will be attempted for every iterator expansion.
10686 @subsubsection Mode Iterator Examples
10688 Here is an example from the MIPS port. It defines the following
10689 modes and attributes (among others):
10692 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
10693 (define_mode_attr d [(SI "") (DI "d")])
10696 and uses the following template to define both @code{subsi3}
10700 (define_insn "sub<mode>3"
10701 [(set (match_operand:GPR 0 "register_operand" "=d")
10702 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
10703 (match_operand:GPR 2 "register_operand" "d")))]
10705 "<d>subu\t%0,%1,%2"
10706 [(set_attr "type" "arith")
10707 (set_attr "mode" "<MODE>")])
10710 This is exactly equivalent to:
10713 (define_insn "subsi3"
10714 [(set (match_operand:SI 0 "register_operand" "=d")
10715 (minus:SI (match_operand:SI 1 "register_operand" "d")
10716 (match_operand:SI 2 "register_operand" "d")))]
10719 [(set_attr "type" "arith")
10720 (set_attr "mode" "SI")])
10722 (define_insn "subdi3"
10723 [(set (match_operand:DI 0 "register_operand" "=d")
10724 (minus:DI (match_operand:DI 1 "register_operand" "d")
10725 (match_operand:DI 2 "register_operand" "d")))]
10728 [(set_attr "type" "arith")
10729 (set_attr "mode" "DI")])
10732 @node Code Iterators
10733 @subsection Code Iterators
10734 @cindex code iterators in @file{.md} files
10735 @findex define_code_iterator
10736 @findex define_code_attr
10738 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
10743 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
10746 defines a pseudo rtx code @var{name} that can be instantiated as
10747 @var{codei} if condition @var{condi} is true. Each @var{codei}
10748 must have the same rtx format. @xref{RTL Classes}.
10750 As with mode iterators, each pattern that uses @var{name} will be
10751 expanded @var{n} times, once with all uses of @var{name} replaced by
10752 @var{code1}, once with all uses replaced by @var{code2}, and so on.
10753 @xref{Defining Mode Iterators}.
10755 It is possible to define attributes for codes as well as for modes.
10756 There are two standard code attributes: @code{code}, the name of the
10757 code in lower case, and @code{CODE}, the name of the code in upper case.
10758 Other attributes are defined using:
10761 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
10764 Here's an example of code iterators in action, taken from the MIPS port:
10767 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
10768 eq ne gt ge lt le gtu geu ltu leu])
10770 (define_expand "b<code>"
10772 (if_then_else (any_cond:CC (cc0)
10774 (label_ref (match_operand 0 ""))
10778 gen_conditional_branch (operands, <CODE>);
10783 This is equivalent to:
10786 (define_expand "bunordered"
10788 (if_then_else (unordered:CC (cc0)
10790 (label_ref (match_operand 0 ""))
10794 gen_conditional_branch (operands, UNORDERED);
10798 (define_expand "bordered"
10800 (if_then_else (ordered:CC (cc0)
10802 (label_ref (match_operand 0 ""))
10806 gen_conditional_branch (operands, ORDERED);
10813 @node Int Iterators
10814 @subsection Int Iterators
10815 @cindex int iterators in @file{.md} files
10816 @findex define_int_iterator
10817 @findex define_int_attr
10819 Int iterators operate in a similar way to code iterators. @xref{Code Iterators}.
10824 (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")])
10827 defines a pseudo integer constant @var{name} that can be instantiated as
10828 @var{inti} if condition @var{condi} is true. Each @var{int}
10829 must have the same rtx format. @xref{RTL Classes}. Int iterators can appear
10830 in only those rtx fields that have 'i' as the specifier. This means that
10831 each @var{int} has to be a constant defined using define_constant or
10834 As with mode and code iterators, each pattern that uses @var{name} will be
10835 expanded @var{n} times, once with all uses of @var{name} replaced by
10836 @var{int1}, once with all uses replaced by @var{int2}, and so on.
10837 @xref{Defining Mode Iterators}.
10839 It is possible to define attributes for ints as well as for codes and modes.
10840 Attributes are defined using:
10843 (define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")])
10846 Here's an example of int iterators in action, taken from the ARM port:
10849 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
10851 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
10853 (define_insn "neon_vq<absneg><mode>"
10854 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10855 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10856 (match_operand:SI 2 "immediate_operand" "i")]
10859 "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
10860 [(set_attr "type" "neon_vqneg_vqabs")]
10865 This is equivalent to:
10868 (define_insn "neon_vqabs<mode>"
10869 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10870 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10871 (match_operand:SI 2 "immediate_operand" "i")]
10874 "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
10875 [(set_attr "type" "neon_vqneg_vqabs")]
10878 (define_insn "neon_vqneg<mode>"
10879 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10880 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10881 (match_operand:SI 2 "immediate_operand" "i")]
10884 "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
10885 [(set_attr "type" "neon_vqneg_vqabs")]
10890 @node Subst Iterators
10891 @subsection Subst Iterators
10892 @cindex subst iterators in @file{.md} files
10893 @findex define_subst
10894 @findex define_subst_attr
10896 Subst iterators are special type of iterators with the following
10897 restrictions: they could not be declared explicitly, they always have
10898 only two values, and they do not have explicit dedicated name.
10899 Subst-iterators are triggered only when corresponding subst-attribute is
10900 used in RTL-pattern.
10902 Subst iterators transform templates in the following way: the templates
10903 are duplicated, the subst-attributes in these templates are replaced
10904 with the corresponding values, and a new attribute is implicitly added
10905 to the given @code{define_insn}/@code{define_expand}. The name of the
10906 added attribute matches the name of @code{define_subst}. Such
10907 attributes are declared implicitly, and it is not allowed to have a
10908 @code{define_attr} named as a @code{define_subst}.
10910 Each subst iterator is linked to a @code{define_subst}. It is declared
10911 implicitly by the first appearance of the corresponding
10912 @code{define_subst_attr}, and it is not allowed to define it explicitly.
10914 Declarations of subst-attributes have the following syntax:
10916 @findex define_subst_attr
10918 (define_subst_attr "@var{name}"
10920 "@var{no-subst-value}"
10921 "@var{subst-applied-value}")
10924 @var{name} is a string with which the given subst-attribute could be
10927 @var{subst-name} shows which @code{define_subst} should be applied to an
10928 RTL-template if the given subst-attribute is present in the
10931 @var{no-subst-value} is a value with which subst-attribute would be
10932 replaced in the first copy of the original RTL-template.
10934 @var{subst-applied-value} is a value with which subst-attribute would be
10935 replaced in the second copy of the original RTL-template.
10937 @node Parameterized Names
10938 @subsection Parameterized Names
10939 @cindex @samp{@@} in instruction pattern names
10940 Ports sometimes need to apply iterators using C++ code, in order to
10941 get the code or RTL pattern for a specific instruction. For example,
10942 suppose we have the @samp{neon_vq<absneg><mode>} pattern given above:
10945 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
10947 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
10949 (define_insn "neon_vq<absneg><mode>"
10950 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10951 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10952 (match_operand:SI 2 "immediate_operand" "i")]
10958 A port might need to generate this pattern for a variable
10959 @samp{QABSNEG} value and a variable @samp{VDQIW} mode. There are two
10960 ways of doing this. The first is to build the rtx for the pattern
10961 directly from C++ code; this is a valid technique and avoids any risk
10962 of combinatorial explosion. The second is to prefix the instruction
10963 name with the special character @samp{@@}, which tells GCC to generate
10964 the four additional functions below. In each case, @var{name} is the
10965 name of the instruction without the leading @samp{@@} character,
10966 without the @samp{<@dots{}>} placeholders, and with any underscore
10967 before a @samp{<@dots{}>} placeholder removed if keeping it would
10968 lead to a double or trailing underscore.
10971 @item insn_code maybe_code_for_@var{name} (@var{i1}, @var{i2}, @dots{})
10972 See whether replacing the first @samp{<@dots{}>} placeholder with
10973 iterator value @var{i1}, the second with iterator value @var{i2}, and
10974 so on, gives a valid instruction. Return its code if so, otherwise
10975 return @code{CODE_FOR_nothing}.
10977 @item insn_code code_for_@var{name} (@var{i1}, @var{i2}, @dots{})
10978 Same, but abort the compiler if the requested instruction does not exist.
10980 @item rtx maybe_gen_@var{name} (@var{i1}, @var{i2}, @dots{}, @var{op0}, @var{op1}, @dots{})
10981 Check for a valid instruction in the same way as
10982 @code{maybe_code_for_@var{name}}. If the instruction exists,
10983 generate an instance of it using the operand values given by @var{op0},
10984 @var{op1}, and so on, otherwise return null.
10986 @item rtx gen_@var{name} (@var{i1}, @var{i2}, @dots{}, @var{op0}, @var{op1}, @dots{})
10987 Same, but abort the compiler if the requested instruction does not exist,
10988 or if the instruction generator invoked the @code{FAIL} macro.
10991 For example, changing the pattern above to:
10994 (define_insn "@@neon_vq<absneg><mode>"
10995 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10996 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10997 (match_operand:SI 2 "immediate_operand" "i")]
11003 would define the same patterns as before, but in addition would generate
11004 the four functions below:
11007 insn_code maybe_code_for_neon_vq (int, machine_mode);
11008 insn_code code_for_neon_vq (int, machine_mode);
11009 rtx maybe_gen_neon_vq (int, machine_mode, rtx, rtx, rtx);
11010 rtx gen_neon_vq (int, machine_mode, rtx, rtx, rtx);
11013 Calling @samp{code_for_neon_vq (UNSPEC_VQABS, V8QImode)}
11014 would then give @code{CODE_FOR_neon_vqabsv8qi}.
11016 It is possible to have multiple @samp{@@} patterns with the same
11017 name and same types of iterator. For example:
11020 (define_insn "@@some_arithmetic_op<mode>"
11021 [(set (match_operand:INTEGER_MODES 0 "register_operand") @dots{})]
11025 (define_insn "@@some_arithmetic_op<mode>"
11026 [(set (match_operand:FLOAT_MODES 0 "register_operand") @dots{})]
11031 would produce a single set of functions that handles both
11032 @code{INTEGER_MODES} and @code{FLOAT_MODES}.