| blob | 271e36c508c625e13458e87ad798d42284dde851 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
57 /* Vector mapping INSN_UIDs to luids.
58 The luids are like uids but increase monotonically always.
59 We use them to see whether a jump comes from outside a given loop. */
63 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
64 number the insn is contained in. */
68 /* 1 + largest uid of any insn. */
72 /* 1 + luid of last insn. */
76 /* Number of loops detected in current function. Used as index to the
77 next few tables. */
81 /* Bound on pseudo register number before loop optimization.
82 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
85 /* The value to pass to the next call of reg_scan_update. */
88 #define obstack_chunk_alloc xmalloc
89 #define obstack_chunk_free free
90 \f
91 /* During the analysis of a loop, a chain of `struct movable's
92 is made to record all the movable insns found.
93 Then the entire chain can be scanned to decide which to move. */
95 struct movable
96 {
101 of any registers used within the LIBCALL. */
103 that must be moved with this one. */
106 may be adjusted when matching movables
107 that load the same value are found. */
109 including other movables that force this
110 or match this one. */
114 /* If PARTIAL is 1, GLOBAL means something different:
115 that the reg is live outside the range from where it is set
116 to the following label. */
120 In particular, moving it does not make it
121 invariant. */
123 load SRC, rather than copying INSN. */
125 first insn of a consecutive sets group. */
128 that we should avoid changing when clearing
129 the rest of the reg. */
133 };
135 struct movables
136 {
137 /* Head of movable chain. */
139 /* Last movable in chain. */
141 /* Number of movables in the loop. */
143 };
149 /* Forward declarations. */
168 #if 0
170 #endif
242 {
243 rtx r1;
244 rtx r2;
248 {
249 rtx match;
250 rtx replacement;
251 rtx insn;
254 /* Nonzero iff INSN is between START and END, inclusive. */
255 #define INSN_IN_RANGE_P(INSN, START, END) \
256 (INSN_UID (INSN) < max_uid_for_loop \
257 && INSN_LUID (INSN) >= INSN_LUID (START) \
258 && INSN_LUID (INSN) <= INSN_LUID (END))
260 /* Indirect_jump_in_function is computed once per function. */
268 rtx));
269 \f
270 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
271 copy the value of the strength reduced giv to its original register. */
274 /* Cost of using a register, to normalize the benefits of a giv. */
277 void
279 {
285 }
286 \f
287 /* Compute the mapping from uids to luids.
288 LUIDs are numbers assigned to insns, like uids,
289 except that luids increase monotonically through the code.
290 Start at insn START and stop just before END. Assign LUIDs
291 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
292 static int
296 {
298 rtx insn;
301 {
304 /* Don't assign luids to line-number NOTEs, so that the distance in
305 luids between two insns is not affected by -g. */
309 else
310 /* Give a line number note the same luid as preceding insn. */
312 }
314 }
315 \f
316 /* Entry point of this file. Perform loop optimization
317 on the current function. F is the first insn of the function
318 and DUMPFILE is a stream for output of a trace of actions taken
319 (or 0 if none should be output). */
321 void
323 /* f is the first instruction of a chain of insns for one function */
324 rtx f;
327 {
344 /* Count the number of loops. */
348 {
351 max_loop_num++;
352 }
354 /* Don't waste time if no loops. */
362 /* Get size to use for tables indexed by uids.
363 Leave some space for labels allocated by find_and_verify_loops. */
370 /* Allocate storage for array of loops. */
374 /* Find and process each loop.
375 First, find them, and record them in order of their beginnings. */
378 /* Allocate and initialize auxiliary loop information. */
383 /* Now find all register lifetimes. This must be done after
384 find_and_verify_loops, because it might reorder the insns in the
385 function. */
388 /* This must occur after reg_scan so that registers created by gcse
389 will have entries in the register tables.
391 We could have added a call to reg_scan after gcse_main in toplev.c,
392 but moving this call to init_alias_analysis is more efficient. */
395 /* See if we went too far. Note that get_max_uid already returns
396 one more that the maximum uid of all insn. */
399 /* Now reset it to the actual size we need. See above. */
402 /* find_and_verify_loops has already called compute_luids, but it
403 might have rearranged code afterwards, so we need to recompute
404 the luids now. */
407 /* Don't leave gaps in uid_luid for insns that have been
408 deleted. It is possible that the first or last insn
409 using some register has been deleted by cross-jumping.
410 Make sure that uid_luid for that former insn's uid
411 points to the general area where that insn used to be. */
413 {
417 }
422 /* Determine if the function has indirect jump. On some systems
423 this prevents low overhead loop instructions from being used. */
426 /* Now scan the loops, last ones first, since this means inner ones are done
427 before outer ones. */
429 {
437 }
439 /* If there were lexical blocks inside the loop, they have been
440 replicated. We will now have more than one NOTE_INSN_BLOCK_BEG
441 and NOTE_INSN_BLOCK_END for each such block. We must duplicate
442 the BLOCKs as well. */
448 /* Clean up. */
454 }
455 \f
456 /* Returns the next insn, in execution order, after INSN. START and
457 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
458 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
459 insn-stream; it is used with loops that are entered near the
460 bottom. */
462 static rtx
465 rtx insn;
466 {
470 {
472 /* Go to the top of the loop, and continue there. */
474 else
475 /* We're done. */
477 }
480 /* We're done. */
484 }
486 /* Optimize one loop described by LOOP. */
488 /* ??? Could also move memory writes out of loops if the destination address
489 is invariant, the source is invariant, the memory write is not volatile,
490 and if we can prove that no read inside the loop can read this address
491 before the write occurs. If there is a read of this address after the
492 write, then we can also mark the memory read as invariant. */
494 static void
498 {
504 rtx p;
505 /* 1 if we are scanning insns that could be executed zero times. */
507 /* 1 if we are scanning insns that might never be executed
508 due to a subroutine call which might exit before they are reached. */
510 /* Jump insn that enters the loop, or 0 if control drops in. */
512 /* Number of insns in the loop. */
516 /* The SET from an insn, if it is the only SET in the insn. */
518 /* Chain describing insns movable in current loop. */
520 /* Ratio of extra register life span we can justify
521 for saving an instruction. More if loop doesn't call subroutines
522 since in that case saving an insn makes more difference
523 and more registers are available. */
525 /* Nonzero if we are scanning instructions in a sub-loop. */
535 /* Determine whether this loop starts with a jump down to a test at
536 the end. This will occur for a small number of loops with a test
537 that is too complex to duplicate in front of the loop.
539 We search for the first insn or label in the loop, skipping NOTEs.
540 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
541 (because we might have a loop executed only once that contains a
542 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
543 (in case we have a degenerate loop).
545 Note that if we mistakenly think that a loop is entered at the top
546 when, in fact, it is entered at the exit test, the only effect will be
547 slightly poorer optimization. Making the opposite error can generate
548 incorrect code. Since very few loops now start with a jump to the
549 exit test, the code here to detect that case is very conservative. */
552 p != loop_end
558 ;
562 /* Set up variables describing this loop. */
566 /* If loop has a jump before the first label,
567 the true entry is the target of that jump.
568 Start scan from there.
569 But record in LOOP->TOP the place where the end-test jumps
570 back to so we can scan that after the end of the loop. */
572 {
575 /* Loop entry must be unconditional jump (and not a RETURN) */
578 /* Check to see whether the jump actually
579 jumps out of the loop (meaning it's no loop).
580 This case can happen for things like
581 do {..} while (0). If this label was generated previously
582 by loop, we can't tell anything about it and have to reject
583 the loop. */
585 {
588 }
589 }
591 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
592 as required by loop_reg_used_before_p. So skip such loops. (This
593 test may never be true, but it's best to play it safe.)
595 Also, skip loops where we do not start scanning at a label. This
596 test also rejects loops starting with a JUMP_INSN that failed the
597 test above. */
601 {
606 }
608 /* Count number of times each reg is set during this loop. Set
609 VARRAY_CHAR (regs->may_not_optimize, I) if it is not safe to move
610 out the setting of register I. Set VARRAY_RTX
611 (regs->single_usage, I). */
613 /* Allocate extra space for REGS that might be created by
614 load_mems. We allocate a little extra slop as well, in the hopes
615 that even after the moving of movables creates some new registers
616 we won't have to reallocate these arrays. However, we do grow
617 the arrays, if necessary, in load_mems_recount_loop_regs_set. */
630 {
633 }
635 #ifdef AVOID_CCMODE_COPIES
636 /* Don't try to move insns which set CC registers if we should not
637 create CCmode register copies. */
641 #endif
647 {
653 }
655 /* Scan through the loop finding insns that are safe to move.
656 Set regs->set_in_loop negative for the reg being set, so that
657 this reg will be considered invariant for subsequent insns.
658 We consider whether subsequent insns use the reg
659 in deciding whether it is worth actually moving.
661 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
662 and therefore it is possible that the insns we are scanning
663 would never be executed. At such times, we must make sure
664 that it is safe to execute the insn once instead of zero times.
665 When MAYBE_NEVER is 0, all insns will be executed at least once
666 so that is not a problem. */
671 {
676 {
683 /* Figure out what to use as a source of this insn. If a REG_EQUIV
684 note is given or if a REG_EQUAL note with a constant operand is
685 specified, use it as the source and mark that we should move
686 this insn by calling emit_move_insn rather that duplicating the
687 insn.
689 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
690 is present. */
694 else
695 {
700 {
702 /* A libcall block can use regs that don't appear in
703 the equivalent expression. To move the libcall,
704 we must move those regs too. */
706 }
707 }
709 /* Don't try to optimize a register that was made
710 by loop-optimization for an inner loop.
711 We don't know its life-span, so we can't compute the benefit. */
713 ;
715 than the one where it is set (meaning that
716 something after this point in the loop might
717 depend on its value before the set). */
719 /* And the set is not guaranteed to be executed one
720 the loop starts, or the value before the set is
721 needed before the set occurs...
723 ??? Note we have quadratic behaviour here, mitigated
724 by the fact that the previous test will often fail for
725 large loops. Rather than re-scanning the entire loop
726 each time for register usage, we should build tables
727 of the register usage and use them here instead. */
728 && (maybe_never
730 /* It is unsafe to move the set.
732 This code used to consider it OK to move a set of a variable
733 which was not created by the user and not used in an exit test.
734 That behavior is incorrect and was removed. */
735 ;
741 || (tem1
742 = consec_sets_invariant_p
746 p)))
747 /* If the insn can cause a trap (such as divide by zero),
748 can't move it unless it's guaranteed to be executed
749 once loop is entered. Even a function call might
750 prevent the trap insn from being reached
751 (since it might exit!) */
754 {
758 /* A potential lossage is where we have a case where two insns
759 can be combined as long as they are both in the loop, but
760 we move one of them outside the loop. For large loops,
761 this can lose. The most common case of this is the address
762 of a function being called.
764 Therefore, if this register is marked as being used exactly
765 once if we are in a loop with calls (a "large loop"), see if
766 we can replace the usage of this register with the source
767 of this SET. If we can, delete this insn.
769 Don't do this if P has a REG_RETVAL note or if we have
770 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
781 && (! SMALL_REGISTER_CLASSES
784 /* This test is not redundant; SET_SRC (set) might be
785 a call-clobbered register and the life of REGNO
786 might span a call. */
788 VARRAY_RTX
791 regno))
793 VARRAY_RTX
795 {
796 /* Replace any usage in a REG_EQUAL note. Must copy the
797 new source, so that we don't get rtx sharing between the
798 SET_SOURCE and REG_NOTES of insn p. */
809 }
828 /* Set M->cond if either loop_invariant_p
829 or consec_sets_invariant_p returned 2
830 (only conditionally invariant). */
842 /* Add M to the end of the chain MOVABLES. */
845 else
850 {
851 /* It is possible for the first instruction to have a
852 REG_EQUAL note but a non-invariant SET_SRC, so we must
853 remember the status of the first instruction in case
854 the last instruction doesn't have a REG_EQUAL note. */
857 /* Skip this insn, not checking REG_LIBCALL notes. */
859 /* Skip the consecutive insns, if there are any. */
861 /* Back up to the last insn of the consecutive group. */
864 /* We must now reset m->move_insn, m->is_equiv, and possibly
865 m->set_src to correspond to the effects of all the
866 insns. */
870 else
871 {
875 else
878 }
880 }
881 }
882 /* If this register is always set within a STRICT_LOW_PART
883 or set to zero, then its high bytes are constant.
884 So clear them outside the loop and within the loop
885 just load the low bytes.
886 We must check that the machine has an instruction to do so.
887 Also, if the value loaded into the register
888 depends on the same register, this cannot be done. */
898 {
901 {
915 /* If the insn may not be executed on some cycles,
916 we can't clear the whole reg; clear just high part.
917 Not even if the reg is used only within this loop.
918 Consider this:
919 while (1)
920 while (s != t) {
921 if (foo ()) x = *s;
922 use (x);
923 }
924 Clearing x before the inner loop could clobber a value
925 being saved from the last time around the outer loop.
926 However, if the reg is not used outside this loop
927 and all uses of the register are in the same
928 basic block as the store, there is no problem.
930 If this insn was made by loop, we don't know its
931 INSN_LUID and hence must make a conservative
932 assumption. */
938 || (labels_in_range_p
942 else
951 /* Add M to the end of the chain MOVABLES. */
954 else
957 }
958 }
959 }
960 /* Past a call insn, we get to insns which might not be executed
961 because the call might exit. This matters for insns that trap.
962 Constant and pure call insns always return, so they don't count. */
965 /* Past a label or a jump, we get to insns for which we
966 can't count on whether or how many times they will be
967 executed during each iteration. Therefore, we can
968 only move out sets of trivial variables
969 (those not used after the loop). */
970 /* Similar code appears twice in strength_reduce. */
972 /* If we enter the loop in the middle, and scan around to the
973 beginning, don't set maybe_never for that. This must be an
974 unconditional jump, otherwise the code at the top of the
975 loop might never be executed. Unconditional jumps are
976 followed a by barrier then loop end. */
982 {
983 /* At the virtual top of a converted loop, insns are again known to
984 be executed: logically, the loop begins here even though the exit
985 code has been duplicated. */
989 loop_depth++;
991 loop_depth--;
992 }
993 }
995 /* If one movable subsumes another, ignore that other. */
999 /* For each movable insn, see if the reg that it loads
1000 leads when it dies right into another conditionally movable insn.
1001 If so, record that the second insn "forces" the first one,
1002 since the second can be moved only if the first is. */
1006 /* See if there are multiple movable insns that load the same value.
1007 If there are, make all but the first point at the first one
1008 through the `match' field, and add the priorities of them
1009 all together as the priority of the first. */
1013 /* Now consider each movable insn to decide whether it is worth moving.
1014 Store 0 in regs->set_in_loop for each reg that is moved.
1016 Generally this increases code size, so do not move moveables when
1017 optimizing for code size. */
1022 /* Now candidates that still are negative are those not moved.
1023 Change regs->set_in_loop to indicate that those are not actually
1024 invariant. */
1029 /* Now that we've moved some things out of the loop, we might be able to
1030 hoist even more memory references. */
1037 ;
1044 {
1046 /* Ensure our label doesn't go away. */
1057 }
1063 }
1064 \f
1065 /* Add elements to *OUTPUT to record all the pseudo-regs
1066 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1068 void
1072 {
1080 {
1098 }
1102 {
1106 {
1115 }
1116 }
1117 }
1118 \f
1119 /* Check what regs are referred to in the libcall block ending with INSN,
1120 aside from those mentioned in the equivalent value.
1121 If there are none, return 0.
1122 If there are one or more, return an EXPR_LIST containing all of them. */
1124 rtx
1127 {
1132 /* First, find all the regs used in the libcall block
1133 that are not mentioned as inputs to the result. */
1136 {
1141 }
1144 }
1145 \f
1146 /* Return 1 if all uses of REG
1147 are between INSN and the end of the basic block. */
1149 static int
1152 {
1154 rtx p;
1159 /* Search this basic block for the already recorded last use of the reg. */
1161 {
1163 {
1169 /* Ordinary insn: if this is the last use, we win. */
1175 /* Jump insn: if this is the last use, we win. */
1178 /* Otherwise, it's the end of the basic block, so we lose. */
1183 /* It's the end of the basic block, so we lose. */
1188 }
1189 }
1191 /* The "last use" that was recorded can't be found after the first
1192 use. This can happen when the last use was deleted while
1193 processing an inner loop, this inner loop was then completely
1194 unrolled, and the outer loop is always exited after the inner loop,
1195 so that everything after the first use becomes a single basic block. */
1197 }
1198 \f
1199 /* Compute the benefit of eliminating the insns in the block whose
1200 last insn is LAST. This may be a group of insns used to compute a
1201 value directly or can contain a library call. */
1203 static int
1205 rtx last;
1206 {
1207 rtx insn;
1212 {
1215 routine. */
1219 benefit++;
1220 }
1223 }
1224 \f
1225 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1227 static rtx
1229 rtx insn;
1231 {
1233 {
1234 rtx temp;
1236 /* If first insn of libcall sequence, skip to end. */
1237 /* Do this at start of loop, since INSN is guaranteed to
1238 be an insn here. */
1243 do
1246 }
1249 }
1251 /* Ignore any movable whose insn falls within a libcall
1252 which is part of another movable.
1253 We make use of the fact that the movable for the libcall value
1254 was made later and so appears later on the chain. */
1256 static void
1259 {
1263 {
1264 /* Is this a movable for the value of a libcall? */
1267 {
1268 rtx insn;
1269 /* Check for earlier movables inside that range,
1270 and mark them invalid. We cannot use LUIDs here because
1271 insns created by loop.c for prior loops don't have LUIDs.
1272 Rather than reject all such insns from movables, we just
1273 explicitly check each insn in the libcall (since invariant
1274 libcalls aren't that common). */
1279 }
1280 }
1281 }
1283 /* For each movable insn, see if the reg that it loads
1284 leads when it dies right into another conditionally movable insn.
1285 If so, record that the second insn "forces" the first one,
1286 since the second can be moved only if the first is. */
1288 static void
1291 {
1294 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1296 {
1299 /* ??? Could this be a bug? What if CSE caused the
1300 register of M1 to be used after this insn?
1301 Since CSE does not update regno_last_uid,
1302 this insn M->insn might not be where it dies.
1303 But very likely this doesn't matter; what matters is
1304 that M's reg is computed from M1's reg. */
1309 /* If m->consec, m->set_src isn't valid. */
1313 /* Increase the priority of the moving the first insn
1314 since it permits the second to be moved as well. */
1316 {
1320 }
1321 }
1322 }
1323 \f
1324 /* Find invariant expressions that are equal and can be combined into
1325 one register. */
1327 static void
1331 {
1336 /* Regs that are set more than once are not allowed to match
1337 or be matched. I'm no longer sure why not. */
1338 /* Perhaps testing m->consec_sets would be more appropriate here? */
1343 {
1350 /* We want later insns to match the first one. Don't make the first
1351 one match any later ones. So start this loop at m->next. */
1355 /* A reg used outside the loop mustn't be eliminated. */
1357 /* A reg used for zero-extending mustn't be eliminated. */
1360 ||
1361 (
1362 /* Can combine regs with different modes loaded from the
1363 same constant only if the modes are the same or
1364 if both are integer modes with M wider or the same
1365 width as M1. The check for integer is redundant, but
1366 safe, since the only case of differing destination
1367 modes with equal sources is when both sources are
1368 VOIDmode, i.e., CONST_INT. */
1374 /* See if the source of M1 says it matches M. */
1381 {
1387 }
1388 }
1390 /* Now combine the regs used for zero-extension.
1391 This can be done for those not marked `global'
1392 provided their lives don't overlap. */
1396 {
1399 /* Combine all the registers for extension from mode MODE.
1400 Don't combine any that are used outside this loop. */
1404 {
1410 {
1411 /* First one: don't check for overlap, just record it. */
1414 }
1416 /* Make sure they extend to the same mode.
1417 (Almost always true.) */
1421 /* We already have one: check for overlap with those
1422 already combined together. */
1429 /* No overlap: we can combine this with the others. */
1435 overlap:
1436 ;
1437 }
1438 }
1440 /* Clean up. */
1442 }
1443 \f
1444 /* Return 1 if regs X and Y will become the same if moved. */
1446 static int
1450 {
1467 }
1469 /* Return 1 if X and Y are identical-looking rtx's.
1470 This is the Lisp function EQUAL for rtx arguments.
1472 If two registers are matching movables or a movable register and an
1473 equivalent constant, consider them equal. */
1475 static int
1480 {
1494 /* If we have a register and a constant, they may sometimes be
1495 equal. */
1498 {
1503 }
1507 {
1512 }
1514 /* Otherwise, rtx's of different codes cannot be equal. */
1518 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1519 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1524 /* These three types of rtx's can be compared nonrecursively. */
1533 /* Compare the elements. If any pair of corresponding elements
1534 fail to match, return 0 for the whole things. */
1538 {
1540 {
1552 /* Two vectors must have the same length. */
1556 /* And the corresponding elements must match. */
1575 /* These are just backpointers, so they don't matter. */
1581 /* It is believed that rtx's at this level will never
1582 contain anything but integers and other rtx's,
1583 except for within LABEL_REFs and SYMBOL_REFs. */
1586 }
1587 }
1589 }
1590 \f
1591 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1592 insns in INSNS which use the reference. */
1594 static void
1596 rtx x;
1597 rtx insns;
1598 {
1602 rtx insn;
1605 {
1606 /* This code used to ignore labels that referred to dispatch tables to
1607 avoid flow generating (slighly) worse code.
1609 We no longer ignore such label references (see LABEL_REF handling in
1610 mark_jump_label for additional information). */
1615 }
1619 {
1625 }
1626 }
1627 \f
1628 /* Scan MOVABLES, and move the insns that deserve to be moved.
1629 If two matching movables are combined, replace one reg with the
1630 other throughout. */
1632 static void
1638 {
1646 /* Map of pseudo-register replacements to handle combining
1647 when we move several insns that load the same value
1648 into different pseudo-registers. */
1655 {
1656 /* Describe this movable insn. */
1659 {
1680 }
1682 /* Count movables. Value used in heuristics in strength_reduce. */
1685 /* Ignore the insn if it's already done (it matched something else).
1686 Otherwise, see if it is now safe to move. */
1698 {
1703 /* We have an insn that is safe to move.
1704 Compute its desirability. */
1715 /* An insn MUST be moved if we already moved something else
1716 which is safe only if this one is moved too: that is,
1717 if already_moved[REGNO] is nonzero. */
1719 /* An insn is desirable to move if the new lifetime of the
1720 register is no more than THRESHOLD times the old lifetime.
1721 If it's not desirable, it means the loop is so big
1722 that moving won't speed things up much,
1723 and it is liable to make register usage worse. */
1725 /* It is also desirable to move if it can be moved at no
1726 extra cost because something else was already moved. */
1729 || flag_move_all_movables
1734 {
1739 /* Now move the insns that set the reg. */
1742 {
1745 /* Find the end of this chain of matching regs.
1746 Thus, we load each reg in the chain from that one reg.
1747 And that reg is loaded with 0 directly,
1748 since it has ->match == 0. */
1754 /* Mark the moved, invariant reg as being allowed to
1755 share a hard reg with the other matching invariant. */
1759 regs_may_share
1762 regs_may_share));
1770 }
1771 /* If we are to re-generate the item being moved with a
1772 new move insn, first delete what we have and then emit
1773 the move insn before the loop. */
1775 {
1779 {
1780 /* If this is the first insn of a library call sequence,
1781 skip to the end. */
1786 /* If this is the last insn of a libcall sequence, then
1787 delete every insn in the sequence except the last.
1788 The last insn is handled in the normal manner. */
1791 {
1795 }
1800 /* simplify_giv_expr expects that it can walk the insns
1801 at m->insn forwards and see this old sequence we are
1802 tossing here. delete_insn does preserve the next
1803 pointers, but when we skip over a NOTE we must fix
1804 it up. Otherwise that code walks into the non-deleted
1805 insn stream. */
1808 }
1826 /* The more regs we move, the less we like moving them. */
1828 }
1829 else
1830 {
1832 {
1835 /* If first insn of libcall sequence, skip to end. */
1836 /* Do this at start of loop, since p is guaranteed to
1837 be an insn here. */
1842 /* If last insn of libcall sequence, move all
1843 insns except the last before the loop. The last
1844 insn is handled in the normal manner. */
1847 {
1855 {
1856 rtx body;
1857 rtx n;
1858 rtx next;
1865 /* Find the next insn after TEMP,
1866 not counting USE or NOTE insns. */
1874 /* If that is the call, this may be the insn
1875 that loads the function address.
1877 Extract the function address from the insn
1878 that loads it into a register.
1879 If this insn was cse'd, we get incorrect code.
1881 So emit a new move insn that copies the
1882 function address into the register that the
1883 call insn will use. flow.c will delete any
1884 redundant stores that we have created. */
1889 NULL_RTX)))
1890 {
1896 }
1897 /* We have the call insn.
1898 If it uses the register we suspect it might,
1899 load it with the correct address directly. */
1904 fn_address),
1905 fn_address_insn);
1908 {
1910 /* Because the USAGE information potentially
1911 contains objects other than hard registers
1912 we need to copy it. */
1916 }
1917 else
1925 }
1928 }
1930 {
1931 /* P sets REG to zero; but we should clear only
1932 the bits that are not covered by the mode
1933 m->savemode. */
1935 rtx sequence;
1936 rtx tem;
1939 tem = expand_binop
1952 }
1954 {
1956 /* Because the USAGE information potentially
1957 contains objects other than hard registers
1958 we need to copy it. */
1962 }
1964 {
1965 /* The SET_SRC might not be invariant, so we must
1966 use the REG_EQUAL note. */
1980 }
1981 else
1985 {
1988 /* If there is a REG_EQUAL note present whose value
1989 is not loop invariant, then delete it, since it
1990 may cause problems with later optimization passes.
1991 It is possible for cse to create such notes
1992 like this as a result of record_jump_cond. */
1997 }
2006 /* If library call, now fix the REG_NOTES that contain
2007 insn pointers, namely REG_LIBCALL on FIRST
2008 and REG_RETVAL on I1. */
2010 {
2014 }
2020 /* simplify_giv_expr expects that it can walk the insns
2021 at m->insn forwards and see this old sequence we are
2022 tossing here. delete_insn does preserve the next
2023 pointers, but when we skip over a NOTE we must fix
2024 it up. Otherwise that code walks into the non-deleted
2025 insn stream. */
2028 }
2030 /* The more regs we move, the less we like moving them. */
2032 }
2034 /* Any other movable that loads the same register
2035 MUST be moved. */
2038 /* This reg has been moved out of one loop. */
2041 /* The reg set here is now invariant. */
2047 /* Change the length-of-life info for the register
2048 to say it lives at least the full length of this loop.
2049 This will help guide optimizations in outer loops. */
2052 /* This is the old insn before all the moved insns.
2053 We can't use the moved insn because it is out of range
2054 in uid_luid. Only the old insns have luids. */
2059 /* Combine with this moved insn any other matching movables. */
2064 {
2065 rtx temp;
2067 /* Schedule the reg loaded by M1
2068 for replacement so that shares the reg of M.
2069 If the modes differ (only possible in restricted
2070 circumstances, make a SUBREG.
2072 Note this assumes that the target dependent files
2073 treat REG and SUBREG equally, including within
2074 GO_IF_LEGITIMATE_ADDRESS and in all the
2075 predicates since we never verify that replacing the
2076 original register with a SUBREG results in a
2077 recognizable insn. */
2080 else
2085 /* Get rid of the matching insn
2086 and prevent further processing of it. */
2089 /* if library call, delete all insn except last, which
2090 is deleted below */
2092 NULL_RTX)))
2093 {
2097 }
2100 /* Any other movable that loads the same register
2101 MUST be moved. */
2104 /* The reg merged here is now invariant,
2105 if the reg it matches is invariant. */
2108 }
2109 }
2112 }
2118 }
2123 /* Go through all the instructions in the loop, making
2124 all the register substitutions scheduled in REG_MAP. */
2128 {
2132 }
2134 /* Clean up. */
2137 }
2138 \f
2139 #if 0
2140 /* Scan X and replace the address of any MEM in it with ADDR.
2141 REG is the address that MEM should have before the replacement. */
2143 static void
2146 {
2155 {
2167 /* Short cut for very common case. */
2172 /* Short cut for very common case. */
2177 /* If this MEM uses a reg other than the one we expected,
2178 something is wrong. */
2186 }
2190 {
2194 {
2198 }
2199 }
2200 }
2201 #endif
2202 \f
2203 /* Return the number of memory refs to addresses that vary
2204 in the rtx X. */
2206 static int
2209 rtx x;
2210 {
2221 {
2238 }
2243 {
2247 {
2251 }
2252 }
2254 }
2255 \f
2256 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2257 `has_call', `has_volatile', `has_tablejump',
2258 `unknown_address_altered', `unknown_constant_address_altered', and
2259 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2260 list `store_mems' in LOOP. */
2262 static void
2265 {
2267 rtx insn;
2271 /* The label after END. Jumping here is just like falling off the
2272 end of the loop. We use next_nonnote_insn instead of next_label
2273 as a hedge against the (pathological) case where some actual insn
2274 might end up between the two. */
2293 {
2295 {
2297 {
2299 /* Count number of loops contained in this one. */
2301 }
2303 {
2305 }
2306 }
2308 {
2312 }
2314 {
2334 {
2336 {
2339 }
2340 else
2341 {
2343 }
2345 do
2346 {
2348 {
2350 {
2351 /* Something tricky. */
2354 }
2357 {
2358 /* A jump outside the current loop. */
2361 }
2362 }
2366 }
2368 }
2369 }
2372 }
2374 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2376 anywhere. */
2378 /* We don't want loads for MEMs moved to a location before the
2379 one at which their stack memory becomes allocated. (Note
2380 that this is not a problem for malloc, etc., since those
2381 require actual function calls. */
2382 && ! current_function_calls_alloca
2383 /* There are ways to leave the loop other than falling off the
2384 end. */
2390 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2391 that loop_invariant_p and load_mems can use true_dependence
2392 to determine what is really clobbered. */
2394 {
2397 loop_info->store_mems
2399 }
2401 {
2405 loop_info->store_mems
2407 }
2408 }
2409 \f
2410 /* Scan the function looking for loops. Record the start and end of each loop.
2411 Also mark as invalid loops any loops that contain a setjmp or are branched
2412 to from outside the loop. */
2414 static void
2416 rtx f;
2418 {
2419 rtx insn;
2420 rtx label;
2430 /* If there are jumps to undefined labels,
2431 treat them as jumps out of any/all loops.
2432 This also avoids writing past end of tables when there are no loops. */
2435 /* Find boundaries of loops, mark which loops are contained within
2436 loops, and invalidate loops that have setjmp. */
2441 {
2444 {
2448 num_loops++;
2455 /* In this case, we must invalidate our current loop and any
2456 enclosing loop. */
2458 {
2464 }
2485 }
2487 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2488 enclosing loop, but this doesn't matter. */
2490 }
2492 /* Any loop containing a label used in an initializer must be invalidated,
2493 because it can be jumped into from anywhere. */
2496 {
2500 }
2502 /* Any loop containing a label used for an exception handler must be
2503 invalidated, because it can be jumped into from anywhere. */
2506 {
2510 }
2512 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2513 loop that it is not contained within, that loop is marked invalid.
2514 If any INSN or CALL_INSN uses a label's address, then the loop containing
2515 that label is marked invalid, because it could be jumped into from
2516 anywhere.
2518 Also look for blocks of code ending in an unconditional branch that
2519 exits the loop. If such a block is surrounded by a conditional
2520 branch around the block, move the block elsewhere (see below) and
2521 invert the jump to point to the code block. This may eliminate a
2522 label in our loop and will simplify processing by both us and a
2523 possible second cse pass. */
2527 {
2531 {
2534 {
2538 }
2539 }
2546 /* See if this is an unconditional branch outside the loop. */
2554 {
2555 rtx p;
2561 /* Go backwards until we reach the start of the loop, a label,
2562 or a JUMP_INSN. */
2569 ;
2571 /* Check for the case where we have a jump to an inner nested
2572 loop, and do not perform the optimization in that case. */
2575 {
2578 {
2583 }
2584 }
2586 /* Make sure that the target of P is within the current loop. */
2592 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2593 we have a block of code to try to move.
2595 We look backward and then forward from the target of INSN
2596 to find a BARRIER at the same loop depth as the target.
2597 If we find such a BARRIER, we make a new label for the start
2598 of the block, invert the jump in P and point it to that label,
2599 and move the block of code to the spot we found. */
2604 /* Just ignore jumps to labels that were never emitted.
2605 These always indicate compilation errors. */
2609 /* If it's not safe to move the sequence, then we
2610 mustn't try. */
2613 {
2614 rtx target
2621 /* Don't move things inside a tablejump. */
2634 /* Don't move things inside a tablejump. */
2645 {
2649 /* Ensure our label doesn't go away. */
2652 /* Verify that uid_loop is large enough and that
2653 we can invert P. */
2655 {
2658 /* If no suitable BARRIER was found, create a suitable
2659 one before TARGET. Since TARGET is a fall through
2660 path, we'll need to insert an jump around our block
2661 and a add a BARRIER before TARGET.
2663 This creates an extra unconditional jump outside
2664 the loop. However, the benefits of removing rarely
2665 executed instructions from inside the loop usually
2666 outweighs the cost of the extra unconditional jump
2667 outside the loop. */
2669 {
2670 rtx temp;
2677 }
2679 /* Include the BARRIER after INSN and copy the
2680 block after LOC. */
2682 last_insn_to_move);
2685 /* All those insns are now in TARGET_LOOP. */
2691 /* The label jumped to by INSN is no longer a loop
2692 exit. Unless INSN does not have a label (e.g.,
2693 it is a RETURN insn), search loop->exit_labels
2694 to find its label_ref, and remove it. Also turn
2695 off LABEL_OUTSIDE_LOOP_P bit. */
2697 {
2699 r;
2702 {
2706 else
2709 }
2715 /* If we didn't find it, then something is
2716 wrong. */
2719 }
2721 /* P is now a jump outside the loop, so it must be put
2722 in loop->exit_labels, and marked as such.
2723 The easiest way to do this is to just call
2724 mark_loop_jump again for P. */
2727 /* If INSN now jumps to the insn after it,
2728 delete INSN. */
2733 }
2735 /* Continue the loop after where the conditional
2736 branch used to jump, since the only branch insn
2737 in the block (if it still remains) is an inter-loop
2738 branch and hence needs no processing. */
2744 /* This loop will be continued with NEXT_INSN (insn). */
2746 }
2747 }
2748 }
2749 }
2750 }
2752 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2753 loops it is contained in, mark the target loop invalid.
2755 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2757 static void
2759 rtx x;
2761 {
2767 {
2779 /* There could be a label reference in here. */
2791 /* This may refer to a LABEL_REF or SYMBOL_REF. */
2803 /* Link together all labels that branch outside the loop. This
2804 is used by final_[bg]iv_value and the loop unrolling code. Also
2805 mark this LABEL_REF so we know that this branch should predict
2806 false. */
2808 /* A check to make sure the label is not in an inner nested loop,
2809 since this does not count as a loop exit. */
2811 {
2816 }
2817 else
2821 {
2830 }
2832 /* If this is inside a loop, but not in the current loop or one enclosed
2833 by it, it invalidates at least one loop. */
2838 /* We must invalidate every nested loop containing the target of this
2839 label, except those that also contain the jump insn. */
2842 {
2843 /* Stop when we reach a loop that also contains the jump insn. */
2848 /* If we get here, we know we need to invalidate a loop. */
2855 }
2859 /* If this is not setting pc, ignore. */
2881 /* Strictly speaking this is not a jump into the loop, only a possible
2882 jump out of the loop. However, we have no way to link the destination
2883 of this jump onto the list of exit labels. To be safe we mark this
2884 loop and any containing loops as invalid. */
2886 {
2888 {
2894 }
2895 }
2897 }
2898 }
2899 \f
2900 /* Return nonzero if there is a label in the range from
2901 insn INSN to and including the insn whose luid is END
2902 INSN must have an assigned luid (i.e., it must not have
2903 been previously created by loop.c). */
2905 static int
2907 rtx insn;
2909 {
2911 {
2915 }
2918 }
2920 /* Record that a memory reference X is being set. */
2922 static void
2924 rtx x;
2925 rtx y ATTRIBUTE_UNUSED;
2927 {
2933 /* Count number of memory writes.
2934 This affects heuristics in strength_reduce. */
2937 /* BLKmode MEM means all memory is clobbered. */
2939 {
2942 else
2946 }
2950 }
2952 /* X is a value modified by an INSN that references a biv inside a loop
2953 exit test (ie, X is somehow related to the value of the biv). If X
2954 is a pseudo that is used more than once, then the biv is (effectively)
2955 used more than once. DATA is a pointer to a loop_regs structure. */
2957 static void
2959 rtx x;
2960 rtx y ATTRIBUTE_UNUSED;
2962 {
2977 /* If we do not have usage information, or if we know the register
2978 is used more than once, note that fact for check_dbra_loop. */
2983 }
2984 \f
2985 /* Return nonzero if the rtx X is invariant over the current loop.
2987 The value is 2 if we refer to something only conditionally invariant.
2989 A memory ref is invariant if it is not volatile and does not conflict
2990 with anything stored in `loop_info->store_mems'. */
2992 int
2996 {
3003 rtx mem_list_entry;
3009 {
3017 /* A LABEL_REF is normally invariant, however, if we are unrolling
3018 loops, and this label is inside the loop, then it isn't invariant.
3019 This is because each unrolled copy of the loop body will have
3020 a copy of this label. If this was invariant, then an insn loading
3021 the address of this label into a register might get moved outside
3022 the loop, and then each loop body would end up using the same label.
3024 We don't know the loop bounds here though, so just fail for all
3025 labels. */
3028 else
3037 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3038 since the reg might be set by initialization within the loop. */
3055 /* Volatile memory references must be rejected. Do this before
3056 checking for read-only items, so that volatile read-only items
3057 will be rejected also. */
3061 /* See if there is any dependence between a store and this load. */
3064 {
3070 }
3072 /* It's not invalidated by a store in memory
3073 but we must still verify the address is invariant. */
3077 /* Don't mess with insns declared volatile. */
3084 }
3088 {
3090 {
3096 }
3098 {
3101 {
3107 }
3109 }
3110 }
3113 }
3114 \f
3115 /* Return nonzero if all the insns in the loop that set REG
3116 are INSN and the immediately following insns,
3117 and if each of those insns sets REG in an invariant way
3118 (not counting uses of REG in them).
3120 The value is 2 if some of these insns are only conditionally invariant.
3122 We assume that INSN itself is the first set of REG
3123 and that its source is invariant. */
3125 static int
3130 {
3134 rtx temp;
3135 /* Number of sets we have to insist on finding after INSN. */
3141 /* If N_SETS hit the limit, we can't rely on its value. */
3148 {
3150 rtx set;
3155 /* If library call, skip to end of it. */
3164 {
3169 {
3170 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3171 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3172 notes are OK. */
3178 }
3179 }
3181 count--;
3183 {
3186 }
3187 }
3190 /* If loop_invariant_p ever returned 2, we return 2. */
3192 }
3194 #if 0
3195 /* I don't think this condition is sufficient to allow INSN
3196 to be moved, so we no longer test it. */
3198 /* Return 1 if all insns in the basic block of INSN and following INSN
3199 that set REG are invariant according to TABLE. */
3201 static int
3205 {
3210 {
3219 {
3222 }
3223 }
3224 }
3226 \f
3227 /* Look at all uses (not sets) of registers in X. For each, if it is
3228 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3229 a different insn, set USAGE[REGNO] to const0_rtx. */
3231 static void
3233 rtx insn;
3234 rtx x;
3235 varray_type usage;
3236 {
3248 {
3249 /* Don't count SET_DEST if it is a REG; otherwise count things
3250 in SET_DEST because if a register is partially modified, it won't
3251 show up as a potential movable so we don't care how USAGE is set
3252 for it. */
3256 }
3257 else
3259 {
3265 }
3266 }
3267 \f
3268 /* Count and record any set in X which is contained in INSN. Update
3269 MAY_NOT_MOVE and LAST_SET for any register set in X. */
3271 static void
3275 varray_type may_not_move;
3277 {
3279 /* Don't move a reg that has an explicit clobber.
3280 It's not worth the pain to try to do it correctly. */
3284 {
3292 {
3294 /* If this is the first setting of this reg
3295 in current basic block, and it was set before,
3296 it must be set in two basic blocks, so it cannot
3297 be moved out of the loop. */
3301 /* If this is not first setting in current basic block,
3302 see if reg was used in between previous one and this.
3303 If so, neither one can be moved. */
3310 }
3311 }
3312 }
3314 /* Increment REGS->SET_IN_LOOP at the index of each register
3315 that is modified by an insn between FROM and TO.
3316 If the value of an element of REGS->SET_IN_LOOP becomes 127 or more,
3317 stop incrementing it, to avoid overflow.
3319 Store in SINGLE_USAGE[I] the single insn in which register I is
3320 used, if it is only used once. Otherwise, it is set to 0 (for no
3321 uses) or const0_rtx for more than one use. This parameter may be zero,
3322 in which case this processing is not done.
3324 Store in *COUNT_PTR the number of actual instruction
3325 in the loop. We use this to decide what is worth moving out. */
3327 /* last_set[n] is nonzero iff reg n has been set in the current basic block.
3328 In that case, it is the insn that last set reg n. */
3330 static void
3333 varray_type may_not_move;
3334 varray_type single_usage;
3337 {
3345 {
3347 {
3350 /* Record registers that have exactly one use. */
3353 /* Include uses in REG_EQUAL notes. */
3361 {
3366 }
3367 }
3371 }
3374 /* Clean up. */
3376 }
3377 \f
3378 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3379 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3380 contained in insn INSN is used by any insn that precedes INSN in
3381 cyclic order starting from the loop entry point.
3383 We don't want to use INSN_LUID here because if we restrict INSN to those
3384 that have a valid INSN_LUID, it means we cannot move an invariant out
3385 from an inner loop past two loops. */
3387 static int
3391 {
3393 rtx p;
3395 /* Scan forward checking for register usage. If we hit INSN, we
3396 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3398 {
3404 }
3407 }
3408 \f
3409 /* A "basic induction variable" or biv is a pseudo reg that is set
3410 (within this loop) only by incrementing or decrementing it. */
3411 /* A "general induction variable" or giv is a pseudo reg whose
3412 value is a linear function of a biv. */
3414 /* Bivs are recognized by `basic_induction_var';
3415 Givs by `general_induction_var'. */
3417 /* Communication with routines called via `note_stores'. */
3421 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
3425 /* ??? Unfinished optimizations, and possible future optimizations,
3426 for the strength reduction code. */
3428 /* ??? The interaction of biv elimination, and recognition of 'constant'
3429 bivs, may cause problems. */
3431 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
3432 performance problems.
3434 Perhaps don't eliminate things that can be combined with an addressing
3435 mode. Find all givs that have the same biv, mult_val, and add_val;
3436 then for each giv, check to see if its only use dies in a following
3437 memory address. If so, generate a new memory address and check to see
3438 if it is valid. If it is valid, then store the modified memory address,
3439 otherwise, mark the giv as not done so that it will get its own iv. */
3441 /* ??? Could try to optimize branches when it is known that a biv is always
3442 positive. */
3444 /* ??? When replace a biv in a compare insn, we should replace with closest
3445 giv so that an optimized branch can still be recognized by the combiner,
3446 e.g. the VAX acb insn. */
3448 /* ??? Many of the checks involving uid_luid could be simplified if regscan
3449 was rerun in loop_optimize whenever a register was added or moved.
3450 Also, some of the optimizations could be a little less conservative. */
3451 \f
3452 /* Scan the loop body and call FNCALL for each insn. In the addition to the
3453 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
3454 callback.
3456 NOT_EVERY_ITERATION if current insn is not executed at least once for every
3457 loop iteration except for the last one.
3459 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
3460 loop iteration.
3461 */
3462 void
3465 loop_insn_callback fncall;
3466 {
3467 /* This is 1 if current insn is not executed at least once for every loop
3468 iteration. */
3473 rtx p;
3475 /* If loop_scan_start points to the loop exit test, we have to be wary of
3476 subversive use of gotos inside expression statements. */
3480 /* Scan through loop to find all possible bivs. */
3485 {
3488 /* Past CODE_LABEL, we get to insns that may be executed multiple
3489 times. The only way we can be sure that they can't is if every
3490 jump insn between here and the end of the loop either
3491 returns, exits the loop, is a jump to a location that is still
3492 behind the label, or is a jump to the loop start. */
3495 {
3501 {
3506 {
3509 else
3513 }
3521 {
3524 }
3525 }
3526 }
3528 /* Past a jump, we get to insns for which we can't count
3529 on whether they will be executed during each iteration. */
3530 /* This code appears twice in strength_reduce. There is also similar
3531 code in scan_loop. */
3533 /* If we enter the loop in the middle, and scan around to the
3534 beginning, don't set not_every_iteration for that.
3535 This can be any kind of jump, since we want to know if insns
3536 will be executed if the loop is executed. */
3541 {
3544 /* If this is a jump outside the loop, then it also doesn't
3545 matter. Check to see if the target of this branch is on the
3546 loop->exits_labels list. */
3554 }
3557 {
3558 /* At the virtual top of a converted loop, insns are again known to
3559 be executed each iteration: logically, the loop begins here
3560 even though the exit code has been duplicated.
3562 Insns are also again known to be executed each iteration at
3563 the LOOP_CONT note. */
3569 loop_depth++;
3571 loop_depth--;
3572 }
3574 /* Note if we pass a loop latch. If we do, then we can not clear
3575 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
3576 a loop since a jump before the last CODE_LABEL may have started
3577 a new loop iteration.
3579 Note that LOOP_TOP is only set for rotated loops and we need
3580 this check for all loops, so compare against the CODE_LABEL
3581 which immediately follows LOOP_START. */
3586 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3587 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3588 or not an insn is known to be executed each iteration of the
3589 loop, whether or not any iterations are known to occur.
3591 Therefore, if we have just passed a label and have no more labels
3592 between here and the test insn of the loop, and we have not passed
3593 a jump to the top of the loop, then we know these insns will be
3594 executed each iteration. */
3597 && !past_loop_latch
3602 }
3603 }
3604 \f
3605 /* Perform strength reduction and induction variable elimination.
3607 Pseudo registers created during this function will be beyond the
3608 last valid index in several tables including regs->n_times_set and
3609 regno_last_uid. This does not cause a problem here, because the
3610 added registers cannot be givs outside of their loop, and hence
3611 will never be reconsidered. But scan_loop must check regnos to
3612 make sure they are in bounds. */
3614 static void
3619 {
3623 rtx p;
3624 /* Temporary list pointers for traversing ivs->loop_iv_list. */
3626 /* Ratio of extra register life span we can justify
3627 for saving an instruction. More if loop doesn't call subroutines
3628 since in that case saving an insn makes more difference
3629 and more registers are available. */
3630 /* ??? could set this to last value of threshold in move_movables */
3632 /* Map of pseudo-register replacements. */
3636 rtx test;
3637 rtx end_insert_before;
3651 /* Save insn immediately after the loop_end. Insns inserted after loop_end
3652 must be put before this insn, so that they will appear in the right
3653 order (i.e. loop order).
3655 If loop_end is the end of the current function, then emit a
3656 NOTE_INSN_DELETED after loop_end and set end_insert_before to the
3657 dummy note insn. */
3660 else
3665 /* Scan ivs->loop_iv_list to remove all regs that proved not to be bivs.
3666 Make a sanity check against regs->n_times_set. */
3668 {
3670 /* Above happens if register modified by subreg, etc. */
3671 /* Make sure it is not recognized as a basic induction var: */
3673 /* If never incremented, it is invariant that we decided not to
3674 move. So leave it alone. */
3676 {
3687 }
3688 else
3689 {
3694 }
3695 }
3697 /* Exit if there are no bivs. */
3699 {
3700 /* Can still unroll the loop anyways, but indicate that there is no
3701 strength reduction info available. */
3706 }
3708 /* Find initial value for each biv by searching backwards from loop_start,
3709 halting at first label. Also record any test condition. */
3713 {
3722 /* Record any test of a biv that branches around the loop if no store
3723 between it and the start of loop. We only care about tests with
3724 constants and registers and only certain of those. */
3734 {
3735 /* If an NE test, we have an initial value! */
3737 {
3741 }
3742 else
3744 }
3745 }
3747 /* Look at the each biv and see if we can say anything better about its
3748 initial value from any initializing insns set up above. (This is done
3749 in two passes to avoid missing SETs in a PARALLEL.) */
3751 {
3752 rtx src;
3753 rtx note;
3758 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
3759 is a constant, use the value of that. */
3765 else
3776 {
3780 {
3782 {
3785 }
3786 else
3787 {
3790 }
3791 }
3792 }
3793 /* If we can't make it a giv,
3794 let biv keep initial value of "itself". */
3797 }
3799 /* Search the loop for general induction variables. */
3803 /* Try to calculate and save the number of loop iterations. This is
3804 set to zero if the actual number can not be calculated. This must
3805 be called after all giv's have been identified, since otherwise it may
3806 fail if the iteration variable is a giv. */
3810 /* Now for each giv for which we still don't know whether or not it is
3811 replaceable, check to see if it is replaceable because its final value
3812 can be calculated. This must be done after loop_iterations is called,
3813 so that final_giv_value will work correctly. */
3816 {
3822 }
3824 /* Try to prove that the loop counter variable (if any) is always
3825 nonnegative; if so, record that fact with a REG_NONNEG note
3826 so that "decrement and branch until zero" insn can be used. */
3829 /* Create reg_map to hold substitutions for replaceable giv regs.
3830 Some givs might have been made from biv increments, so look at
3831 ivs->reg_iv_type for a suitable size. */
3835 /* Examine each iv class for feasibility of strength reduction/induction
3836 variable elimination. */
3839 {
3845 /* Test whether it will be possible to eliminate this biv
3846 provided all givs are reduced. This is possible if either
3847 the reg is not used outside the loop, or we can compute
3848 what its final value will be.
3850 For architectures with a decrement_and_branch_until_zero insn,
3851 don't do this if we put a REG_NONNEG note on the endtest for
3852 this biv. */
3854 /* Compare against bl->init_insn rather than loop_start.
3855 We aren't concerned with any uses of the biv between
3856 init_insn and loop_start since these won't be affected
3857 by the value of the biv elsewhere in the function, so
3858 long as init_insn doesn't use the biv itself.
3859 March 14, 1989 -- self@bayes.arc.nasa.gov */
3865 #ifdef HAVE_decrement_and_branch_until_zero
3867 #endif
3870 #ifdef HAVE_decrement_and_branch_until_zero
3872 #endif
3873 ))
3875 insn_count);
3876 else
3877 {
3879 {
3887 }
3888 }
3890 /* Check each extension dependant giv in this class to see if its
3891 root biv is safe from wrapping in the interior mode. */
3894 /* Combine all giv's for this iv_class. */
3897 /* This will be true at the end, if all givs which depend on this
3898 biv have been strength reduced.
3899 We can't (currently) eliminate the biv unless this is so. */
3902 /* Check each giv in this class to see if we will benefit by reducing
3903 it. Skip giv's combined with others. */
3905 {
3917 /* Reduce benefit if not replaceable, since we will insert
3918 a move-insn to replace the insn that calculates this giv.
3919 Don't do this unless the giv is a user variable, since it
3920 will often be marked non-replaceable because of the duplication
3921 of the exit code outside the loop. In such a case, the copies
3922 we insert are dead and will be deleted. So they don't have
3923 a cost. Similar situations exist. */
3924 /* ??? The new final_[bg]iv_value code does a much better job
3925 of finding replaceable giv's, and hence this code may no longer
3926 be necessary. */
3931 /* Decrease the benefit to count the add-insns that we will
3932 insert to increment the reduced reg for the giv.
3933 ??? This can overestimate the run-time cost of the additional
3934 insns, e.g. if there are multiple basic blocks that increment
3935 the biv, but only one of these blocks is executed during each
3936 iteration. There is no good way to detect cases like this with
3937 the current structure of the loop optimizer.
3938 This code is more accurate for determining code size than
3939 run-time benefits. */
3942 /* Decide whether to strength-reduce this giv or to leave the code
3943 unchanged (recompute it from the biv each time it is used).
3944 This decision can be made independently for each giv. */
3946 #ifdef AUTO_INC_DEC
3947 /* Attempt to guess whether autoincrement will handle some of the
3948 new add insns; if so, increase BENEFIT (undo the subtraction of
3949 add_cost that was done above). */
3951 /* Increasing the benefit is risky, since this is only a guess.
3952 Avoid increasing register pressure in cases where there would
3953 be no other benefit from reducing this giv. */
3956 {
3969 }
3970 #endif
3972 /* If an insn is not to be strength reduced, then set its ignore
3973 flag, and clear all_reduced. */
3975 /* A giv that depends on a reversed biv must be reduced if it is
3976 used after the loop exit, otherwise, it would have the wrong
3977 value after the loop exit. To make it simple, just reduce all
3978 of such giv's whether or not we know they are used after the loop
3979 exit. */
3983 {
3991 }
3992 else
3993 {
3994 /* Check that we can increment the reduced giv without a
3995 multiply insn. If not, reject it. */
4000 {
4008 }
4009 }
4010 }
4012 /* Check for givs whose first use is their definition and whose
4013 last use is the definition of another giv. If so, it is likely
4014 dead and should not be used to derive another giv nor to
4015 eliminate a biv. */
4017 {
4024 {
4030 }
4031 }
4033 /* Reduce each giv that we decided to reduce. */
4036 {
4039 {
4042 /* If the code for derived givs immediately below has already
4043 allocated a new_reg, we must keep it. */
4047 #ifdef AUTO_INC_DEC
4048 /* If the target has auto-increment addressing modes, and
4049 this is an address giv, then try to put the increment
4050 immediately after its use, so that flow can create an
4051 auto-increment addressing mode. */
4054 /* We don't handle reversed biv's because bl->biv->insn
4055 does not have a valid INSN_LUID. */
4059 {
4060 /* If other giv's have been combined with this one, then
4061 this will work only if all uses of the other giv's occur
4062 before this giv's insn. This is difficult to check.
4064 We simplify this by looking for the common case where
4065 there is one DEST_REG giv, and this giv's insn is the
4066 last use of the dest_reg of that DEST_REG giv. If the
4067 increment occurs after the address giv, then we can
4068 perform the optimization. (Otherwise, the increment
4069 would have to go before other_giv, and we would not be
4070 able to combine it with the address giv to get an
4071 auto-inc address.) */
4073 {
4078 {
4081 else
4083 }
4090 }
4091 /* Check for case where increment is before the address
4092 giv. Do this test in "loop order". */
4101 else
4104 #ifdef HAVE_cc0
4105 {
4106 rtx prev;
4108 /* We can't put an insn immediately after one setting
4109 cc0, or immediately before one using cc0. */
4116 }
4117 #endif
4121 }
4122 #endif
4124 /* For each place where the biv is incremented, add an insn
4125 to increment the new, reduced reg for the giv. */
4127 {
4128 rtx insert_before;
4134 else
4141 /* A multiply is acceptable here
4142 since this is presumed to be seldom executed. */
4145 }
4147 /* Add code at loop start to initialize giv's reduced reg. */
4151 loop_start);
4152 }
4153 }
4155 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
4156 as not reduced.
4158 For each giv register that can be reduced now: if replaceable,
4159 substitute reduced reg wherever the old giv occurs;
4160 else add new move insn "giv_reg = reduced_reg". */
4163 {
4170 /* Update expression if this was combined, in case other giv was
4171 replaced. */
4176 /* See if this register is known to be a pointer to something. If
4177 so, see if we can find the alignment. First see if there is a
4178 destination register that is a pointer. If so, this shares the
4179 alignment too. Next see if we can deduce anything from the
4180 computational information. If not, and this is a DEST_ADDR
4181 giv, at least we know that it's a pointer, though we don't know
4182 the alignment. */
4190 {
4199 }
4203 {
4211 }
4216 /* Store reduced reg as the address in the memref where we found
4217 this giv. */
4220 {
4223 #if 0
4224 /* I can no longer duplicate the original problem. Perhaps
4225 this is unnecessary now? */
4227 /* Replaceable; it isn't strictly necessary to delete the old
4228 insn and emit a new one, because v->dest_reg is now dead.
4230 However, especially when unrolling loops, the special
4231 handling for (set REG0 REG1) in the second cse pass may
4232 make v->dest_reg live again. To avoid this problem, emit
4233 an insn to set the original giv reg from the reduced giv.
4234 We can not delete the original insn, since it may be part
4235 of a LIBCALL, and the code in flow that eliminates dead
4236 libcalls will fail if it is deleted. */
4239 #endif
4240 }
4241 else
4242 {
4243 /* Not replaceable; emit an insn to set the original giv reg from
4244 the reduced giv, same as above. */
4247 }
4249 /* When a loop is reversed, givs which depend on the reversed
4250 biv, and which are live outside the loop, must be set to their
4251 correct final value. This insn is only needed if the giv is
4252 not replaceable. The correct final value is the same as the
4253 value that the giv starts the reversed loop with. */
4257 end_insert_before);
4259 {
4260 rtx insert_before;
4262 /* If the loop has multiple exits, emit the insn before the
4263 loop to ensure that it will always be executed no matter
4264 how the loop exits. Otherwise, emit the insn after the loop,
4265 since this is slightly more efficient. */
4268 else
4271 insert_before);
4273 #if 0
4274 /* If the insn to set the final value of the giv was emitted
4275 before the loop, then we must delete the insn inside the loop
4276 that sets it. If this is a LIBCALL, then we must delete
4277 every insn in the libcall. Note, however, that
4278 final_giv_value will only succeed when there are multiple
4279 exits if the giv is dead at each exit, hence it does not
4280 matter that the original insn remains because it is dead
4281 anyways. */
4282 /* Delete the insn inside the loop that sets the giv since
4283 the giv is now set before (or after) the loop. */
4285 #endif
4286 }
4289 {
4294 }
4295 }
4297 /* All the givs based on the biv bl have been reduced if they
4298 merit it. */
4300 /* For each giv not marked as maybe dead that has been combined with a
4301 second giv, clear any "maybe dead" mark on that second giv.
4302 v->new_reg will either be or refer to the register of the giv it
4303 combined with.
4305 Doing this clearing avoids problems in biv elimination where a
4306 giv's new_reg is a complex value that can't be put in the insn but
4307 the giv combined with (with a reg as new_reg) is marked maybe_dead.
4308 Since the register will be used in either case, we'd prefer it be
4309 used from the simpler giv. */
4315 /* Try to eliminate the biv, if it is a candidate.
4316 This won't work if ! all_reduced,
4317 since the givs we planned to use might not have been reduced.
4319 We have to be careful that we didn't initially think we could eliminate
4320 this biv because of a giv that we now think may be dead and shouldn't
4321 be used as a biv replacement.
4323 Also, there is the possibility that we may have a giv that looks
4324 like it can be used to eliminate a biv, but the resulting insn
4325 isn't valid. This can happen, for example, on the 88k, where a
4326 JUMP_INSN can compare a register only with zero. Attempts to
4327 replace it with a compare with a constant will fail.
4329 Note that in cases where this call fails, we may have replaced some
4330 of the occurrences of the biv with a giv, but no harm was done in
4331 doing so in the rare cases where it can occur. */
4335 {
4336 /* ?? If we created a new test to bypass the loop entirely,
4337 or otherwise drop straight in, based on this test, then
4338 we might want to rewrite it also. This way some later
4339 pass has more hope of removing the initialization of this
4340 biv entirely. */
4342 /* If final_value != 0, then the biv may be used after loop end
4343 and we must emit an insn to set it just in case.
4345 Reversed bivs already have an insn after the loop setting their
4346 value, so we don't need another one. We can't calculate the
4347 proper final value for such a biv here anyways. */
4349 {
4350 rtx insert_before;
4352 /* If the loop has multiple exits, emit the insn before the
4353 loop to ensure that it will always be executed no matter
4354 how the loop exits. Otherwise, emit the insn after the
4355 loop, since this is slightly more efficient. */
4358 else
4362 end_insert_before);
4363 }
4365 #if 0
4366 /* Delete all of the instructions inside the loop which set
4367 the biv, as they are all dead. If is safe to delete them,
4368 because an insn setting a biv will never be part of a libcall. */
4369 /* However, deleting them will invalidate the regno_last_uid info,
4370 so keeping them around is more convenient. Final_biv_value
4371 will only succeed when there are multiple exits if the biv
4372 is dead at each exit, hence it does not matter that the original
4373 insn remains, because it is dead anyways. */
4376 #endif
4381 }
4382 }
4384 /* Go through all the instructions in the loop, making all the
4385 register substitutions scheduled in REG_MAP. */
4390 {
4394 }
4397 {
4398 /* When we completely unroll a loop we will likely not need the increment
4399 of the loop BIV and we will not need the conditional branch at the
4400 end of the loop. */
4403 #ifdef HAVE_cc0
4404 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
4405 need the comparison before the conditional branch at the end of the
4406 loop. */
4408 #endif
4410 /* We'll need one copy for each loop iteration. */
4413 /* A little slop to account for the ability to remove initialization
4414 code, better CSE, and other secondary benefits of completely
4415 unrolling some loops. */
4418 /* Clamp the value. */
4421 }
4423 /* Unroll loops from within strength reduction so that we can use the
4424 induction variable information that strength_reduce has already
4425 collected. Always unroll loops that would be as small or smaller
4426 unrolled than when rolled. */
4432 #ifdef HAVE_doloop_end
4440 egress:
4444 {
4453 {
4456 }
4458 {
4461 }
4465 }
4466 }
4469 }
4470 \f
4471 /*Record all basic induction variables calculated in the insn. */
4472 static rtx
4475 rtx p;
4478 {
4480 rtx set;
4481 rtx dest_reg;
4482 rtx inc_val;
4483 rtx mult_val;
4489 {
4494 {
4499 {
4500 /* It is a possible basic induction variable.
4501 Create and initialize an induction structure for it. */
4509 }
4512 }
4513 }
4515 }
4516 \f
4517 /* Record all givs calculated in the insn.
4518 A register is a giv if: it is only set once, it is a function of a
4519 biv and a constant (or invariant), and it is not a biv. */
4520 static rtx
4523 rtx p;
4526 {
4529 rtx set;
4530 /* Look for a general induction variable in a register. */
4535 {
4536 rtx src_reg;
4537 rtx dest_reg;
4538 rtx add_val;
4539 rtx mult_val;
4540 rtx ext_val;
4543 rtx last_consec_insn;
4552 /* Equivalent expression is a giv. */
4557 /* Don't try to handle any regs made by loop optimization.
4558 We have nothing on them in regno_first_uid, etc. */
4560 /* Don't recognize a BASIC_INDUCT_VAR here. */
4562 /* This must be the only place where the register is set. */
4564 /* or all sets must be consecutive and make a giv. */
4569 {
4573 /* If this is a library call, increase benefit. */
4577 /* Skip the consecutive insns, if there are any. */
4585 }
4586 }
4588 #ifndef DONT_REDUCE_ADDR
4589 /* Look for givs which are memory addresses. */
4590 /* This resulted in worse code on a VAX 8600. I wonder if it
4591 still does. */
4594 maybe_multiple);
4595 #endif
4597 /* Update the status of whether giv can derive other givs. This can
4598 change when we pass a label or an insn that updates a biv. */
4603 }
4604 \f
4605 /* Return 1 if X is a valid source for an initial value (or as value being
4606 compared against in an initial test).
4608 X must be either a register or constant and must not be clobbered between
4609 the current insn and the start of the loop.
4611 INSN is the insn containing X. */
4613 static int
4615 rtx x;
4616 rtx insn;
4618 rtx loop_start;
4619 {
4623 /* Only consider pseudos we know about initialized in insns whose luids
4624 we know. */
4629 /* Don't use call-clobbered registers across a call which clobbers it. On
4630 some machines, don't use any hard registers at all. */
4632 && (SMALL_REGISTER_CLASSES
4636 /* Don't use registers that have been clobbered before the start of the
4637 loop. */
4642 }
4643 \f
4644 /* Scan X for memory refs and check each memory address
4645 as a possible giv. INSN is the insn whose pattern X comes from.
4646 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
4647 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
4648 more thanonce in each loop iteration. */
4650 static void
4653 rtx x;
4654 rtx insn;
4656 {
4666 {
4682 {
4683 rtx src_reg;
4684 rtx add_val;
4685 rtx mult_val;
4686 rtx ext_val;
4689 /* This code used to disable creating GIVs with mult_val == 1 and
4690 add_val == 0. However, this leads to lost optimizations when
4691 it comes time to combine a set of related DEST_ADDR GIVs, since
4692 this one would not be seen. */
4697 {
4698 /* Found one; record it. */
4707 }
4708 }
4713 }
4715 /* Recursively scan the subexpressions for other mem refs. */
4721 maybe_multiple);
4725 maybe_multiple);
4726 }
4727 \f
4728 /* Fill in the data about one biv update.
4729 V is the `struct induction' in which we record the biv. (It is
4730 allocated by the caller, with alloca.)
4731 INSN is the insn that sets it.
4732 DEST_REG is the biv's reg.
4734 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
4735 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
4736 being set to INC_VAL.
4738 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
4739 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
4740 can be executed more than once per iteration. If MAYBE_MULTIPLE
4741 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
4742 executed exactly once per iteration. */
4744 static void
4749 rtx insn;
4750 rtx dest_reg;
4751 rtx inc_val;
4752 rtx mult_val;
4756 {
4772 /* Add this to the reg's iv_class, creating a class
4773 if this is the first incrementation of the reg. */
4777 {
4778 /* Create and initialize new iv_class. */
4788 /* Set initial value to the reg itself. */
4790 /* We haven't seen the initializing insn yet */
4800 /* Add this class to ivs->loop_iv_list. */
4804 /* Put it in the array of biv register classes. */
4806 }
4808 /* Update IV_CLASS entry for this biv. */
4816 {
4821 {
4825 }
4826 else
4827 {
4831 }
4832 }
4833 }
4834 \f
4835 /* Fill in the data about one giv.
4836 V is the `struct induction' in which we record the giv. (It is
4837 allocated by the caller, with alloca.)
4838 INSN is the insn that sets it.
4839 BENEFIT estimates the savings from deleting this insn.
4840 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
4841 into a register or is used as a memory address.
4843 SRC_REG is the biv reg which the giv is computed from.
4844 DEST_REG is the giv's reg (if the giv is stored in a reg).
4845 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
4846 LOCATION points to the place where this giv's value appears in INSN. */
4848 static void
4853 rtx insn;
4854 rtx src_reg;
4855 rtx dest_reg;
4861 {
4866 rtx temp;
4868 /* Attempt to prove constantness of the values. */
4896 /* The v->always_computable field is used in update_giv_derive, to
4897 determine whether a giv can be used to derive another giv. For a
4898 DEST_REG giv, INSN computes a new value for the giv, so its value
4899 isn't computable if INSN insn't executed every iteration.
4900 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
4901 it does not compute a new value. Hence the value is always computable
4902 regardless of whether INSN is executed each iteration. */
4906 else
4912 {
4915 }
4917 {
4923 /* If the lifetime is zero, it means that this register is
4924 really a dead store. So mark this as a giv that can be
4925 ignored. This will not prevent the biv from being eliminated. */
4931 }
4933 /* Add the giv to the class of givs computed from one biv. */
4937 {
4940 /* Don't count DEST_ADDR. This is supposed to count the number of
4941 insns that calculate givs. */
4945 }
4946 else
4947 /* Fatal error, biv missing for this giv? */
4952 else
4953 {
4954 /* The giv can be replaced outright by the reduced register only if all
4955 of the following conditions are true:
4956 - the insn that sets the giv is always executed on any iteration
4957 on which the giv is used at all
4958 (there are two ways to deduce this:
4959 either the insn is executed on every iteration,
4960 or all uses follow that insn in the same basic block),
4961 - the giv is not used outside the loop
4962 - no assignments to the biv occur during the giv's lifetime. */
4965 /* Previous line always fails if INSN was moved by loop opt. */
4968 && (! not_every_iteration
4970 {
4971 /* Now check that there are no assignments to the biv within the
4972 giv's lifetime. This requires two separate checks. */
4974 /* Check each biv update, and fail if any are between the first
4975 and last use of the giv.
4977 If this loop contains an inner loop that was unrolled, then
4978 the insn modifying the biv may have been emitted by the loop
4979 unrolling code, and hence does not have a valid luid. Just
4980 mark the biv as not replaceable in this case. It is not very
4981 useful as a biv, because it is used in two different loops.
4982 It is very unlikely that we would be able to optimize the giv
4983 using this biv anyways. */
4987 {
4993 {
4997 }
4998 }
5000 /* If there are any backwards branches that go from after the
5001 biv update to before it, then this giv is not replaceable. */
5005 {
5009 }
5010 }
5011 else
5012 {
5013 /* May still be replaceable, we don't have enough info here to
5014 decide. */
5017 }
5018 }
5020 /* Record whether the add_val contains a const_int, for later use by
5021 combine_givs. */
5022 {
5027 ;
5031 {
5033 {
5038 else
5040 }
5043 }
5044 }
5047 {
5051 else
5067 {
5069 {
5081 }
5082 }
5085 {
5088 }
5089 else
5090 {
5093 }
5096 {
5099 }
5100 else
5101 {
5104 }
5105 }
5110 }
5112 /* All this does is determine whether a giv can be made replaceable because
5113 its final value can be calculated. This code can not be part of record_giv
5114 above, because final_giv_value requires that the number of loop iterations
5115 be known, and that can not be accurately calculated until after all givs
5116 have been identified. */
5118 static void
5122 {
5129 /* DEST_ADDR givs will never reach here, because they are always marked
5130 replaceable above in record_giv. */
5132 /* The giv can be replaced outright by the reduced register only if all
5133 of the following conditions are true:
5134 - the insn that sets the giv is always executed on any iteration
5135 on which the giv is used at all
5136 (there are two ways to deduce this:
5137 either the insn is executed on every iteration,
5138 or all uses follow that insn in the same basic block),
5139 - its final value can be calculated (this condition is different
5140 than the one above in record_giv)
5141 - it's not used before the it's set
5142 - no assignments to the biv occur during the giv's lifetime. */
5144 #if 0
5145 /* This is only called now when replaceable is known to be false. */
5146 /* Clear replaceable, so that it won't confuse final_giv_value. */
5148 #endif
5152 {
5155 rtx last_giv_use;
5159 /* When trying to determine whether or not a biv increment occurs
5160 during the lifetime of the giv, we can ignore uses of the variable
5161 outside the loop because final_value is true. Hence we can not
5162 use regno_last_uid and regno_first_uid as above in record_giv. */
5164 /* Search the loop to determine whether any assignments to the
5165 biv occur during the giv's lifetime. Start with the insn
5166 that sets the giv, and search around the loop until we come
5167 back to that insn again.
5169 Also fail if there is a jump within the giv's lifetime that jumps
5170 to somewhere outside the lifetime but still within the loop. This
5171 catches spaghetti code where the execution order is not linear, and
5172 hence the above test fails. Here we assume that the giv lifetime
5173 does not extend from one iteration of the loop to the next, so as
5174 to make the test easier. Since the lifetime isn't known yet,
5175 this requires two loops. See also record_giv above. */
5180 {
5183 {
5186 }
5192 {
5193 /* It is possible for the BIV increment to use the GIV if we
5194 have a cycle. Thus we must be sure to check each insn for
5195 both BIV and GIV uses, and we must check for BIV uses
5196 first. */
5203 {
5205 {
5209 }
5211 }
5212 }
5213 }
5215 /* Now that the lifetime of the giv is known, check for branches
5216 from within the lifetime to outside the lifetime if it is still
5217 replaceable. */
5220 {
5223 {
5236 {
5245 }
5246 }
5247 }
5249 /* If it is replaceable, then save the final value. */
5252 }
5257 }
5258 \f
5259 /* Update the status of whether a giv can derive other givs.
5261 We need to do something special if there is or may be an update to the biv
5262 between the time the giv is defined and the time it is used to derive
5263 another giv.
5265 In addition, a giv that is only conditionally set is not allowed to
5266 derive another giv once a label has been passed.
5268 The cases we look at are when a label or an update to a biv is passed. */
5270 static void
5273 rtx p;
5274 {
5278 rtx tem;
5281 /* Search all IV classes, then all bivs, and finally all givs.
5283 There are three cases we are concerned with. First we have the situation
5284 of a giv that is only updated conditionally. In that case, it may not
5285 derive any givs after a label is passed.
5287 The second case is when a biv update occurs, or may occur, after the
5288 definition of a giv. For certain biv updates (see below) that are
5289 known to occur between the giv definition and use, we can adjust the
5290 giv definition. For others, or when the biv update is conditional,
5291 we must prevent the giv from deriving any other givs. There are two
5292 sub-cases within this case.
5294 If this is a label, we are concerned with any biv update that is done
5295 conditionally, since it may be done after the giv is defined followed by
5296 a branch here (actually, we need to pass both a jump and a label, but
5297 this extra tracking doesn't seem worth it).
5299 If this is a jump, we are concerned about any biv update that may be
5300 executed multiple times. We are actually only concerned about
5301 backward jumps, but it is probably not worth performing the test
5302 on the jump again here.
5304 If this is a biv update, we must adjust the giv status to show that a
5305 subsequent biv update was performed. If this adjustment cannot be done,
5306 the giv cannot derive further givs. */
5312 {
5314 {
5315 /* If cant_derive is already true, there is no point in
5316 checking all of these conditions again. */
5320 /* If this giv is conditionally set and we have passed a label,
5321 it cannot derive anything. */
5325 /* Skip givs that have mult_val == 0, since
5326 they are really invariants. Also skip those that are
5327 replaceable, since we know their lifetime doesn't contain
5328 any biv update. */
5332 /* The only way we can allow this giv to derive another
5333 is if this is a biv increment and we can form the product
5334 of biv->add_val and giv->mult_val. In this case, we will
5335 be able to compute a compensation. */
5337 {
5338 rtx ext_val_dummy;
5349 tem = simplify_giv_expr
5356 else
5358 }
5362 }
5363 }
5364 }
5365 \f
5366 /* Check whether an insn is an increment legitimate for a basic induction var.
5367 X is the source of insn P, or a part of it.
5368 MODE is the mode in which X should be interpreted.
5370 DEST_REG is the putative biv, also the destination of the insn.
5371 We accept patterns of these forms:
5372 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
5373 REG = INVARIANT + REG
5375 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
5376 store the additive term into *INC_VAL, and store the place where
5377 we found the additive term into *LOCATION.
5379 If X is an assignment of an invariant into DEST_REG, we set
5380 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
5382 We also want to detect a BIV when it corresponds to a variable
5383 whose mode was promoted via PROMOTED_MODE. In that case, an increment
5384 of the variable may be a PLUS that adds a SUBREG of that variable to
5385 an invariant and then sign- or zero-extends the result of the PLUS
5386 into the variable.
5388 Most GIVs in such cases will be in the promoted mode, since that is the
5389 probably the natural computation mode (and almost certainly the mode
5390 used for addresses) on the machine. So we view the pseudo-reg containing
5391 the variable as the BIV, as if it were simply incremented.
5393 Note that treating the entire pseudo as a BIV will result in making
5394 simple increments to any GIVs based on it. However, if the variable
5395 overflows in its declared mode but not its promoted mode, the result will
5396 be incorrect. This is acceptable if the variable is signed, since
5397 overflows in such cases are undefined, but not if it is unsigned, since
5398 those overflows are defined. So we only check for SIGN_EXTEND and
5399 not ZERO_EXTEND.
5401 If we cannot find a biv, we return 0. */
5403 static int
5408 rtx dest_reg;
5409 rtx p;
5413 {
5421 {
5427 {
5429 }
5434 {
5436 }
5437 else
5450 /* If this is a SUBREG for a promoted variable, check the inner
5451 value. */
5459 /* If this register is assigned in a previous insn, look at its
5460 source, but don't go outside the loop or past a label. */
5462 /* If this sets a register to itself, we would repeat any previous
5463 biv increment if we applied this strategy blindly. */
5469 {
5470 rtx dest;
5471 do
5472 {
5474 }
5503 }
5504 /* Fall through. */
5506 /* Can accept constant setting of biv only when inside inner most loop.
5507 Otherwise, a biv of an inner loop may be incorrectly recognized
5508 as a biv of the outer loop,
5509 causing code to be moved INTO the inner loop. */
5516 /* convert_modes aborts if we try to convert to or from CCmode, so just
5517 exclude that case. It is very unlikely that a condition code value
5518 would be a useful iterator anyways. */
5522 {
5523 /* Possible bug here? Perhaps we don't know the mode of X. */
5527 }
5528 else
5536 /* Similar, since this can be a sign extension. */
5541 ;
5555 location);
5560 }
5561 }
5562 \f
5563 /* A general induction variable (giv) is any quantity that is a linear
5564 function of a basic induction variable,
5565 i.e. giv = biv * mult_val + add_val.
5566 The coefficients can be any loop invariant quantity.
5567 A giv need not be computed directly from the biv;
5568 it can be computed by way of other givs. */
5570 /* Determine whether X computes a giv.
5571 If it does, return a nonzero value
5572 which is the benefit from eliminating the computation of X;
5573 set *SRC_REG to the register of the biv that it is computed from;
5574 set *ADD_VAL and *MULT_VAL to the coefficients,
5575 such that the value of X is biv * mult + add; */
5577 static int
5581 rtx x;
5589 {
5593 /* If this is an invariant, forget it, it isn't a giv. */
5604 {
5607 /* Since this is now an invariant and wasn't before, it must be a giv
5608 with MULT_VAL == 0. It doesn't matter which BIV we associate this
5609 with. */
5616 /* This is equivalent to a BIV. */
5623 /* Either (plus (biv) (invar)) or
5624 (plus (mult (biv) (invar_1)) (invar_2)). */
5626 {
5629 }
5630 else
5631 {
5634 }
5639 /* ADD_VAL is zero. */
5647 }
5649 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
5650 unless they are CONST_INT). */
5658 else
5661 /* Always return true if this is a giv so it will be detected as such,
5662 even if the benefit is zero or negative. This allows elimination
5663 of bivs that might otherwise not be eliminated. */
5665 }
5666 \f
5667 /* Given an expression, X, try to form it as a linear function of a biv.
5668 We will canonicalize it to be of the form
5669 (plus (mult (BIV) (invar_1))
5670 (invar_2))
5671 with possible degeneracies.
5673 The invariant expressions must each be of a form that can be used as a
5674 machine operand. We surround then with a USE rtx (a hack, but localized
5675 and certainly unambiguous!) if not a CONST_INT for simplicity in this
5676 routine; it is the caller's responsibility to strip them.
5678 If no such canonicalization is possible (i.e., two biv's are used or an
5679 expression that is neither invariant nor a biv or giv), this routine
5680 returns 0.
5682 For a non-zero return, the result will have a code of CONST_INT, USE,
5683 REG (for a BIV), PLUS, or MULT. No other codes will occur.
5685 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
5690 static rtx
5693 rtx x;
5696 {
5701 rtx tem;
5703 /* If this is not an integer mode, or if we cannot do arithmetic in this
5704 mode, this can't be a giv. */
5711 {
5718 /* Put constant last, CONST_INT last if both constant. */
5726 /* Handle addition of zero, then addition of an invariant. */
5731 {
5734 /* Adding two invariants must result in an invariant, so enclose
5735 addition operation inside a USE and return it. */
5745 else
5754 /* biv + invar or mult + invar. Return sum. */
5758 /* (a + invar_1) + invar_2. Associate. */
5759 return
5765 arg1)),
5770 }
5772 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
5773 MULT to reduce cases. */
5779 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
5780 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
5781 Recurse to associate the second PLUS. */
5786 return
5794 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
5810 /* Handle "a - b" as "a + b * (-1)". */
5816 constm1_rtx)),
5825 /* Put constant last, CONST_INT last if both constant. */
5830 /* If second argument is not now constant, not giv. */
5834 /* Handle multiply by 0 or 1. */
5842 {
5844 /* biv * invar. Done. */
5848 /* Product of two constants. */
5852 /* invar * invar is a giv, but attempt to simplify it somehow. */
5858 {
5859 /* (invar_0 * invar_1) * invar_2. Associate. */
5866 arg1)),
5868 }
5869 /* Porpagate the MULT expressions to the intermost nodes. */
5871 {
5872 /* (invar_0 + invar_1) * invar_2. Distribute. */
5878 arg1),
5882 arg1)),
5884 }
5888 /* (a * invar_1) * invar_2. Associate. */
5894 arg1)),
5898 /* (a + invar_1) * invar_2. Distribute. */
5903 arg1),
5906 arg1)),
5911 }
5914 /* Shift by constant is multiply by power of two. */
5918 return
5927 /* "-a" is "a * (-1)" */
5933 /* "~a" is "-a - 1". Silly, but easy. */
5937 const1_rtx),
5941 /* Already in proper form for invariant. */
5947 /* Conditionally recognize extensions of simple IVs. After we've
5948 computed loop traversal counts and verified the range of the
5949 source IV, we'll reevaluate this as a GIV. */
5951 {
5954 {
5957 }
5958 }
5962 /* If this is a new register, we can't deal with it. */
5966 /* Check for biv or giv. */
5968 {
5972 {
5975 /* Form expression from giv and add benefit. Ensure this giv
5976 can derive another and subtract any needed adjustment if so. */
5978 /* Increasing the benefit here is risky. The only case in which it
5979 is arguably correct is if this is the only use of V. In other
5980 cases, this will artificially inflate the benefit of the current
5981 giv, and lead to suboptimal code. Thus, it is disabled, since
5982 potentially not reducing an only marginally beneficial giv is
5983 less harmful than reducing many givs that are not really
5984 beneficial. */
5985 {
5989 }
6002 {
6005 }
6006 else
6007 {
6010 }
6012 }
6015 do_default:
6016 /* If it isn't an induction variable, and it is invariant, we
6017 may be able to simplify things further by looking through
6018 the bits we just moved outside the loop. */
6020 {
6025 {
6026 /* Ok, we found a match. Substitute and simplify. */
6028 /* If we match another movable, we must use that, as
6029 this one is going away. */
6034 /* If consec is non-zero, this is a member of a group of
6035 instructions that were moved together. We handle this
6036 case only to the point of seeking to the last insn and
6037 looking for a REG_EQUAL. Fail if we don't find one. */
6039 {
6042 do
6043 {
6045 }
6051 }
6052 else
6053 {
6057 }
6060 {
6061 /* What we are most interested in is pointer
6062 arithmetic on invariants -- only take
6063 patterns we may be able to do something with. */
6069 {
6071 benefit);
6074 }
6079 {
6084 }
6085 }
6087 }
6088 }
6090 }
6092 /* Fall through to general case. */
6094 /* If invariant, return as USE (unless CONST_INT).
6095 Otherwise, not giv. */
6100 {
6109 }
6110 else
6112 }
6113 }
6115 /* This routine folds invariants such that there is only ever one
6116 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6118 static rtx
6121 {
6127 {
6130 }
6133 {
6136 }
6137 else
6138 {
6141 }
6142 }
6144 static rtx
6148 {
6150 {
6154 else
6157 }
6160 else
6163 }
6164 \f
6165 /* Help detect a giv that is calculated by several consecutive insns;
6166 for example,
6167 giv = biv * M
6168 giv = giv + A
6169 The caller has already identified the first insn P as having a giv as dest;
6170 we check that all other insns that set the same register follow
6171 immediately after P, that they alter nothing else,
6172 and that the result of the last is still a giv.
6174 The value is 0 if the reg set in P is not really a giv.
6175 Otherwise, the value is the amount gained by eliminating
6176 all the consecutive insns that compute the value.
6178 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6179 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6181 The coefficients of the ultimate giv value are stored in
6182 *MULT_VAL and *ADD_VAL. */
6184 static int
6189 rtx p;
6190 rtx src_reg;
6191 rtx dest_reg;
6196 {
6202 rtx temp;
6203 rtx set;
6205 /* Indicate that this is a giv so that we can update the value produced in
6206 each insn of the multi-insn sequence.
6208 This induction structure will be used only by the call to
6209 general_induction_var below, so we can allocate it on our stack.
6210 If this is a giv, our caller will replace the induct var entry with
6211 a new induction structure. */
6232 {
6236 /* If libcall, skip to end of call sequence. */
6247 /* Giv created by equivalent expression. */
6253 {
6257 count--;
6261 }
6263 {
6264 /* Allow insns that set something other than this giv to a
6265 constant. Such insns are needed on machines which cannot
6266 include long constants and should not disqualify a giv. */
6275 }
6276 }
6281 }
6282 \f
6283 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6284 represented by G1. If no such expression can be found, or it is clear that
6285 it cannot possibly be a valid address, 0 is returned.
6287 To perform the computation, we note that
6288 G1 = x * v + a and
6289 G2 = y * v + b
6290 where `v' is the biv.
6292 So G2 = (y/b) * G1 + (b - a*y/x).
6294 Note that MULT = y/x.
6296 Update: A and B are now allowed to be additive expressions such that
6297 B contains all variables in A. That is, computing B-A will not require
6298 subtracting variables. */
6300 static rtx
6303 {
6304 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
6309 /* If MULT is not 1, we cannot handle A with non-constants, since we
6310 would then be required to subtract multiples of the registers in A.
6311 This is theoretically possible, and may even apply to some Fortran
6312 constructs, but it is a lot of work and we do not attempt it here. */
6317 /* In general these structures are sorted top to bottom (down the PLUS
6318 chain), but not left to right across the PLUS. If B is a higher
6319 order giv than A, we can strip one level and recurse. If A is higher
6320 order, we'll eventually bail out, but won't know that until the end.
6321 If they are the same, we'll strip one level around this loop. */
6324 {
6336 /* We matched: remove one reg completely. */
6339 /* An alternate match. */
6342 /* An alternate match. */
6344 else
6345 {
6346 /* Indicates an extra register in B. Strip one level from B and
6347 recurse, hoping B was the higher order expression. */
6352 }
6353 }
6355 /* Here we are at the last level of A, go through the cases hoping to
6356 get rid of everything but a constant. */
6359 {
6372 }
6374 {
6376 }
6378 {
6379 return simplify_gen_binary (MINUS, GET_MODE (b) != VOIDmode ? GET_MODE (b) : GET_MODE (a), const0_rtx, a);
6380 }
6382 {
6387 else
6389 }
6394 }
6396 rtx
6399 {
6402 /* The value that G1 will be multiplied by must be a constant integer. Also,
6403 the only chance we have of getting a valid address is if b*c/a (see above
6404 for notation) is also an integer. */
6407 {
6412 }
6415 else
6416 {
6417 /* ??? Find out if the one is a multiple of the other? */
6419 }
6423 {
6424 /* Failed. If we've got a multiplication factor between G1 and G2,
6425 scale G1's addend and try again. */
6427 {
6431 {
6432 HOST_WIDE_INT m;
6436 }
6437 else
6438 {
6440 mult);
6441 }
6444 }
6445 }
6449 /* Form simplified final result. */
6454 else
6459 else
6460 {
6463 {
6467 }
6470 }
6471 }
6472 \f
6473 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6474 represented by G1. This indicates that G2 should be combined with G1 and
6475 that G2 can use (either directly or via an address expression) a register
6476 used to represent G1. */
6478 static rtx
6481 {
6484 /* With the introduction of ext dependant givs, we must care for modes.
6485 G2 must not use a wider mode than G1. */
6495 /* If these givs are identical, they can be combined. We use the results
6496 of express_from because the addends are not in a canonical form, so
6497 rtx_equal_p is a weaker test. */
6498 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
6499 combination to be the other way round. */
6502 {
6504 }
6506 /* If G2 can be expressed as a function of G1 and that function is valid
6507 as an address and no more expensive than using a register for G2,
6508 the expression of G2 in terms of G1 can be used. */
6512 /* ??? Looses, especially with -fforce-addr, where *g2->location
6513 will always be a register, and so anything more complicated
6514 gets discarded. */
6515 #if 0
6516 #ifdef ADDRESS_COST
6518 #else
6520 #endif
6521 #endif
6522 )
6523 {
6525 }
6528 }
6529 \f
6530 /* Check each extension dependant giv in this class to see if its
6531 root biv is safe from wrapping in the interior mode, which would
6532 make the giv illegal. */
6534 static void
6538 {
6541 HOST_WIDE_INT start_val;
6546 /* Make sure the iteration data is available. We must have
6547 constants in order to be certain of no overflow. */
6548 /* ??? An unknown iteration count with an increment of +-1
6549 combined with friendly exit tests of against an invariant
6550 value is also ameanable to optimization. Not implemented. */
6556 /* Make sure the host can represent the arithmetic. */
6558 {
6560 HOST_WIDE_INT s_end_val;
6572 /* Check for host arithmatic overflow. */
6574 {
6576 HOST_WIDE_INT s_max;
6583 /* Check zero extension of biv ok. */
6585 /* Check for host arithmatic overflow. */
6586 && (neg_incr
6589 /* Check for target arithmetic overflow. */
6590 && (neg_incr
6593 {
6595 }
6597 /* Check sign extension of biv ok. */
6598 /* ??? While it is true that overflow with signed and pointer
6599 arithmetic is undefined, I fear too many programmers don't
6600 keep this fact in mind -- myself included on occasion.
6601 So leave alone with the signed overflow optimizations. */
6603 /* Check for host arithmatic overflow. */
6604 && (neg_incr
6607 /* Check for target arithmetic overflow. */
6608 && (neg_incr
6611 {
6613 }
6614 }
6615 }
6617 /* Invalidate givs that fail the tests. */
6620 {
6625 {
6634 /* We don't know whether this value is being used as either
6635 signed or unsigned, so to safely truncate we must satisfy
6636 both. The initial check here verifies the BIV itself;
6637 once that is successful we may check its range wrt the
6638 derived GIV. */
6640 {
6644 /* We know from the above that both endpoints are nonnegative,
6645 and that there is no wrapping. Verify that both endpoints
6646 are within the (signed) range of the outer mode. */
6649 }
6654 }
6657 {
6659 {
6663 }
6664 }
6665 else
6666 {
6668 {
6673 else
6674 {
6679 else
6681 }
6686 }
6688 }
6689 }
6690 }
6692 /* Generate a version of VALUE in a mode appropriate for initializing V. */
6694 rtx
6697 rtx value;
6698 {
6704 /* Recall that check_ext_dependant_givs verified that the known bounds
6705 of a biv did not overflow or wrap with respect to the extension for
6706 the giv. Therefore, constants need no additional adjustment. */
6710 /* Otherwise, we must adjust the value to compensate for the
6711 differing modes of the biv and the giv. */
6713 }
6714 \f
6715 struct combine_givs_stats
6716 {
6719 };
6721 static int
6725 {
6732 /* Stabilize the sort. */
6736 }
6738 /* Check all pairs of givs for iv_class BL and see if any can be combined with
6739 any other. If so, point SAME to the giv combined with and set NEW_REG to
6740 be an expression (in terms of the other giv's DEST_REG) equivalent to the
6741 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
6743 static void
6747 {
6748 /* Additional benefit to add for being combined multiple times. */
6756 /* Count givs, because bl->giv_count is incorrect here. */
6760 giv_count++;
6762 giv_array
6773 {
6775 rtx single_use;
6780 /* If a DEST_REG GIV is used only once, do not allow it to combine
6781 with anything, for in doing so we will gain nothing that cannot
6782 be had by simply letting the GIV with which we would have combined
6783 to be reduced on its own. The losage shows up in particular with
6784 DEST_ADDR targets on hosts with reg+reg addressing, though it can
6785 be seen elsewhere as well. */
6793 /* Add an additional weight for zero addends. */
6798 {
6799 rtx this_combine;
6804 {
6807 }
6808 }
6810 }
6812 /* Iterate, combining until we can't. */
6813 restart:
6817 {
6820 {
6826 }
6828 }
6831 {
6837 /* If it has already been combined, skip. */
6842 {
6845 /* If it has already been combined, skip. */
6847 {
6857 /* ??? The new final_[bg]iv_value code does a much better job
6858 of finding replaceable giv's, and hence this code may no
6859 longer be necessary. */
6863 /* To help optimize the next set of combinations, remove
6864 this giv from the benefits of other potential mates. */
6866 {
6870 }
6877 }
6878 }
6880 /* To help optimize the next set of combinations, remove
6881 this giv from the benefits of other potential mates. */
6883 {
6885 {
6889 }
6893 /* We've finished with this giv, and everything it touched.
6894 Restart the combination so that proper weights for the
6895 rest of the givs are properly taken into account. */
6896 /* ??? Ideally we would compact the arrays at this point, so
6897 as to not cover old ground. But sanely compacting
6898 can_combine is tricky. */
6900 }
6901 }
6903 /* Clean up. */
6906 }
6907 \f
6908 /* EMIT code before INSERT_BEFORE to set REG = B * M + A. */
6910 void
6916 rtx insert_before;
6917 {
6918 rtx seq;
6919 rtx result;
6921 /* Prevent unexpected sharing of these rtx. */
6925 /* Increase the lifetime of any invariants moved further in code. */
6939 /* It is entirely possible that the expansion created lots of new
6940 registers. Iterate over the sequence we just created and
6941 record them all. */
6944 {
6947 {
6951 }
6952 }
6956 }
6958 /* Similar to emit_iv_add_mult, but compute cost rather than emitting
6959 insns. */
6960 static int
6966 {
6976 {
6981 }
6984 }
6985 \f
6986 /* Test whether A * B can be computed without
6987 an actual multiply insn. Value is 1 if so. */
6989 static int
6991 rtx a;
6992 rtx b;
6993 {
6995 rtx tmp;
6998 /* If only one is constant, make it B. */
7002 /* If first constant, both constant, so don't need multiply. */
7006 /* If second not constant, neither is constant, so would need multiply. */
7010 /* One operand is constant, so might not need multiply insn. Generate the
7011 code for the multiply and see if a call or multiply, or long sequence
7012 of insns is generated. */
7020 {
7025 else
7027 {
7036 {
7039 }
7040 }
7041 }
7051 }
7052 \f
7053 /* Check to see if loop can be terminated by a "decrement and branch until
7054 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7055 Also try reversing an increment loop to a decrement loop
7056 to see if the optimization can be performed.
7057 Value is nonzero if optimization was performed. */
7059 /* This is useful even if the architecture doesn't have such an insn,
7060 because it might change a loops which increments from 0 to n to a loop
7061 which decrements from n to 0. A loop that decrements to zero is usually
7062 faster than one that increments from zero. */
7064 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7065 such as approx_final_value, biv_total_increment, loop_iterations, and
7066 final_[bg]iv_value. */
7068 static int
7072 {
7077 rtx reg;
7078 rtx jump_label;
7079 rtx final_value;
7080 rtx start_value;
7081 rtx new_add_val;
7082 rtx comparison;
7083 rtx before_comparison;
7084 rtx p;
7085 rtx jump;
7086 rtx first_compare;
7091 /* If last insn is a conditional branch, and the insn before tests a
7092 register value, try to optimize it. Otherwise, we can't do anything. */
7101 /* Try to compute whether the compare/branch at the loop end is one or
7102 two instructions. */
7108 else
7111 {
7112 /* If more than one condition is present to control the loop, then
7113 do not proceed, as this function does not know how to rewrite
7114 loop tests with more than one condition.
7116 Look backwards from the first insn in the last comparison
7117 sequence and see if we've got another comparison sequence. */
7119 rtx jump1;
7123 }
7125 /* Check all of the bivs to see if the compare uses one of them.
7126 Skip biv's set more than once because we can't guarantee that
7127 it will be zero on the last iteration. Also skip if the biv is
7128 used between its update and the test insn. */
7131 {
7136 first_compare))
7138 }
7143 /* Look for the case where the basic induction variable is always
7144 nonnegative, and equals zero on the last iteration.
7145 In this case, add a reg_note REG_NONNEG, which allows the
7146 m68k DBRA instruction to be used. */
7154 {
7155 /* Initial value must be greater than 0,
7156 init_val % -dec_value == 0 to ensure that it equals zero on
7157 the last iteration */
7163 {
7164 /* register always nonnegative, add REG_NOTE to branch */
7172 }
7174 /* If the decrement is 1 and the value was tested as >= 0 before
7175 the loop, then we can safely optimize. */
7177 {
7190 {
7198 }
7199 }
7200 }
7203 {
7204 /* Try to change inc to dec, so can apply above optimization. */
7205 /* Can do this if:
7206 all registers modified are induction variables or invariant,
7207 all memory references have non-overlapping addresses
7208 (obviously true if only one write)
7209 allow 2 insns for the compare/jump at the end of the loop. */
7210 /* Also, we must avoid any instructions which use both the reversed
7211 biv and another biv. Such instructions will fail if the loop is
7212 reversed. We meet this condition by requiring that either
7213 no_use_except_counting is true, or else that there is only
7214 one biv. */
7216 /* 1 if the iteration var is used only to count iterations. */
7218 /* 1 if the loop has no memory store, or it has a single memory store
7219 which is reversible. */
7223 {
7226 /* If there are no givs for this biv, and the only exit is the
7227 fall through at the end of the loop, then
7228 see if perhaps there are no uses except to count. */
7232 {
7237 /* An insn that sets the biv is okay. */
7238 ;
7242 {
7243 /* If either of these insns uses the biv and sets a pseudo
7244 that has more than one usage, then the biv has uses
7245 other than counting since it's used to derive a value
7246 that is used more than one time. */
7248 regs);
7250 {
7253 }
7254 }
7256 {
7259 }
7260 }
7261 }
7264 /* No need to worry about MEMs. */
7265 ;
7267 {
7272 /* If the loop has a single store, and the destination address is
7273 invariant, then we can't reverse the loop, because this address
7274 might then have the wrong value at loop exit.
7275 This would work if the source was invariant also, however, in that
7276 case, the insn should have been moved out of the loop. */
7279 {
7282 reversible_mem_store
7289 /* If the store depends on a register that is set after the
7290 store, it depends on the initial value, and is thus not
7291 reversible. */
7293 {
7300 }
7301 }
7302 }
7303 else
7306 /* This code only acts for innermost loops. Also it simplifies
7307 the memory address check by only reversing loops with
7308 zero or one memory access.
7309 Two memory accesses could involve parts of the same array,
7310 and that can't be reversed.
7311 If the biv is used only for counting, than we don't need to worry
7312 about all these things. */
7317 && reversible_mem_store
7322 {
7323 rtx tem;
7325 /* Loop can be reversed. */
7329 /* Now check other conditions:
7331 The increment must be a constant, as must the initial value,
7332 and the comparison code must be LT.
7334 This test can probably be improved since +/- 1 in the constant
7335 can be obtained by changing LT to LE and vice versa; this is
7336 confusing. */
7339 /* for constants, LE gets turned into LT */
7343 {
7354 comparison_const_width
7356 else
7357 comparison_const_width
7361 comparison_sign_mask
7364 /* If the comparison value is not a loop invariant, then we
7365 can not reverse this loop.
7367 ??? If the insns which initialize the comparison value as
7368 a whole compute an invariant result, then we could move
7369 them out of the loop and proceed with loop reversal. */
7377 /* Normalize the initial value if it is an integer and
7378 has no other use except as a counter. This will allow
7379 a few more loops to be reversed. */
7383 {
7385 /* The code below requires comparison_val to be a multiple
7386 of add_val in order to do the loop reversal, so
7387 round up comparison_val to a multiple of add_val.
7388 Since comparison_value is constant, we know that the
7389 current comparison code is LT. */
7391 comparison_val
7393 /* We postpone overflow checks for COMPARISON_VAL here;
7394 even if there is an overflow, we might still be able to
7395 reverse the loop, if converting the loop exit test to
7396 NE is possible. */
7398 }
7400 /* First check if we can do a vanilla loop reversal. */
7402 /* If we have a decrement_and_branch_on_count,
7403 prefer the NE test, since this will allow that
7404 instruction to be generated. Note that we must
7405 use a vanilla loop reversal if the biv is used to
7406 calculate a giv or has a non-counting use. */
7407 #if ! defined (HAVE_decrement_and_branch_until_zero) \
7408 && defined (HAVE_decrement_and_branch_on_count)
7412 #endif
7414 /* Now do postponed overflow checks on COMPARISON_VAL. */
7417 {
7418 /* Register will always be nonnegative, with value
7419 0 on last iteration */
7423 }
7427 {
7430 }
7431 else
7437 /* If the initial value is not zero, or if the comparison
7438 value is not an exact multiple of the increment, then we
7439 can not reverse this loop. */
7442 {
7445 }
7446 else
7447 {
7450 }
7454 /* Reset these in case we normalized the initial value
7455 and comparison value above. */
7458 {
7460 final_value
7462 }
7465 /* Save some info needed to produce the new insns. */
7472 /* Set start_value; if this is not a CONST_INT, we need
7473 to generate a SUB.
7474 Initialize biv to start_value before loop start.
7475 The old initializing insn will be deleted as a
7476 dead store by flow.c. */
7479 {
7482 loop_start);
7483 }
7485 {
7488 enum insn_code icode
7497 start_value
7501 loop_start);
7505 }
7507 {
7509 enum insn_code icode
7517 start_value
7521 loop_start);
7522 }
7523 else
7524 /* We could handle the other cases too, but it'll be
7525 better to have a testcase first. */
7528 /* We may not have a single insn which can increment a reg, so
7529 create a sequence to hold all the insns from expand_inc. */
7538 /* Update biv info to reflect its new status. */
7543 /* Update loop info. */
7552 /* Inc LABEL_NUSES so that delete_insn will
7553 not delete the label. */
7556 /* Emit an insn after the end of the loop to set the biv's
7557 proper exit value if it is used anywhere outside the loop. */
7562 loop_end);
7564 /* Delete compare/branch at end of loop. */
7569 /* Add new compare/branch insn at end of loop. */
7581 ;
7587 {
7589 {
7590 /* Increment of LABEL_NUSES done above. */
7591 /* Register is now always nonnegative,
7592 so add REG_NONNEG note to the branch. */
7595 }
7597 }
7599 /* No insn may reference both the reversed and another biv or it
7600 will fail (see comment near the top of the loop reversal
7601 code).
7602 Earlier on, we have verified that the biv has no use except
7603 counting, or it is the only biv in this function.
7604 However, the code that computes no_use_except_counting does
7605 not verify reg notes. It's possible to have an insn that
7606 references another biv, and has a REG_EQUAL note with an
7607 expression based on the reversed biv. To avoid this case,
7608 remove all REG_EQUAL notes based on the reversed biv
7609 here. */
7612 {
7615 /* If this is a set of a GIV based on the reversed biv, any
7616 REG_EQUAL notes should still be correct. */
7623 {
7628 else
7630 }
7631 }
7633 /* Mark that this biv has been reversed. Each giv which depends
7634 on this biv, and which is also live past the end of the loop
7635 will have to be fixed up. */
7640 {
7644 else
7646 }
7649 }
7650 }
7651 }
7654 }
7655 \f
7656 /* Verify whether the biv BL appears to be eliminable,
7657 based on the insns in the loop that refer to it.
7659 If ELIMINATE_P is non-zero, actually do the elimination.
7661 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
7662 determine whether invariant insns should be placed inside or at the
7663 start of the loop. */
7665 static int
7671 {
7676 rtx p;
7678 /* Scan all insns in the loop, stopping if we find one that uses the
7679 biv in a way that we cannot eliminate. */
7682 {
7686 /* If this is a libcall that sets a giv, skip ahead to its end. */
7688 {
7692 {
7697 {
7704 }
7705 }
7706 }
7711 {
7717 }
7718 }
7721 {
7726 }
7729 }
7730 \f
7731 /* INSN and REFERENCE are instructions in the same insn chain.
7732 Return non-zero if INSN is first. */
7734 int
7737 {
7741 {
7742 /* Start with test for not first so that INSN == REFERENCE yields not
7743 first. */
7749 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
7750 previous insn, hence the <= comparison below does not work if
7751 P is a note. */
7762 }
7763 }
7765 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
7766 the offset that we have to take into account due to auto-increment /
7767 div derivation is zero. */
7768 static int
7771 rtx insn;
7772 {
7773 /* If the giv V had the auto-inc address optimization applied
7774 to it, and INSN occurs between the giv insn and the biv
7775 insn, then we'd have to adjust the value used here.
7776 This is rare, so we don't bother to make this possible. */
7785 }
7787 /* If BL appears in X (part of the pattern of INSN), see if we can
7788 eliminate its use. If so, return 1. If not, return 0.
7790 If BIV does not appear in X, return 1.
7792 If ELIMINATE_P is non-zero, actually do the elimination. WHERE indicates
7793 where extra insns should be added. Depending on how many items have been
7794 moved out of the loop, it will either be before INSN or at the start of
7795 the loop. */
7797 static int
7803 rtx where;
7804 {
7810 #ifdef HAVE_cc0
7812 #endif
7818 {
7820 /* If we haven't already been able to do something with this BIV,
7821 we can't eliminate it. */
7827 /* If this sets the BIV, it is not a problem. */
7831 /* If this is an insn that defines a giv, it is also ok because
7832 it will go away when the giv is reduced. */
7837 #ifdef HAVE_cc0
7839 {
7840 /* Can replace with any giv that was reduced and
7841 that has (MULT_VAL != 0) and (ADD_VAL == 0).
7842 Require a constant for MULT_VAL, so we know it's nonzero.
7843 ??? We disable this optimization to avoid potential
7844 overflows. */
7852 {
7859 /* If the giv has the opposite direction of change,
7860 then reverse the comparison. */
7864 else
7867 /* We can probably test that giv's reduced reg. */
7870 }
7872 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
7873 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
7874 Require a constant for MULT_VAL, so we know it's nonzero.
7875 ??? Do this only if ADD_VAL is a pointer to avoid a potential
7876 overflow problem. */
7888 {
7895 /* If the giv has the opposite direction of change,
7896 then reverse the comparison. */
7900 else
7904 /* Replace biv with the giv's reduced register. */
7909 /* Insn doesn't support that constant or invariant. Copy it
7910 into a register (it will be a loop invariant.) */
7914 where);
7916 /* Substitute the new register for its invariant value in
7917 the compare expression. */
7921 }
7922 }
7923 #endif
7930 /* See if either argument is the biv. */
7935 else
7939 {
7940 /* First try to replace with any giv that has constant positive
7941 mult_val and constant add_val. We might be able to support
7942 negative mult_val, but it seems complex to do it in general. */
7954 {
7961 /* Replace biv with the giv's reduced reg. */
7964 /* If all constants are actually constant integers and
7965 the derived constant can be directly placed in the COMPARE,
7966 do so. */
7970 {
7975 }
7976 else
7977 {
7978 /* Otherwise, load it into a register. */
7982 }
7985 }
7987 /* Look for giv with positive constant mult_val and nonconst add_val.
7988 Insert insns to calculate new compare value.
7989 ??? Turn this off due to possible overflow. */
7997 {
7998 rtx tem;
8008 /* Replace biv with giv's reduced register. */
8012 /* Compute value to compare against. */
8014 /* Use it in this insn. */
8018 }
8019 }
8021 {
8023 {
8024 /* Look for giv with constant positive mult_val and nonconst
8025 add_val. Insert insns to compute new compare value.
8026 ??? Turn this off due to possible overflow. */
8033 {
8034 rtx tem;
8044 /* Replace biv with giv's reduced register. */
8048 /* Compute value to compare against. */
8054 }
8055 }
8057 /* This code has problems. Basically, you can't know when
8058 seeing if we will eliminate BL, whether a particular giv
8059 of ARG will be reduced. If it isn't going to be reduced,
8060 we can't eliminate BL. We can try forcing it to be reduced,
8061 but that can generate poor code.
8063 The problem is that the benefit of reducing TV, below should
8064 be increased if BL can actually be eliminated, but this means
8065 we might have to do a topological sort of the order in which
8066 we try to process biv. It doesn't seem worthwhile to do
8067 this sort of thing now. */
8069 #if 0
8070 /* Otherwise the reg compared with had better be a biv. */
8075 /* Look for a pair of givs, one for each biv,
8076 with identical coefficients. */
8078 {
8089 {
8096 /* Replace biv with its giv's reduced reg. */
8098 /* Replace other operand with the other giv's
8099 reduced reg. */
8102 }
8103 }
8104 #endif
8105 }
8107 /* If we get here, the biv can't be eliminated. */
8111 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8112 biv is used in it, since it will be replaced. */
8120 }
8122 /* See if any subexpression fails elimination. */
8125 {
8127 {
8140 }
8141 }
8144 }
8145 \f
8146 /* Return nonzero if the last use of REG
8147 is in an insn following INSN in the same basic block. */
8149 static int
8151 rtx reg;
8152 rtx insn;
8153 {
8154 rtx n;
8158 {
8161 }
8163 }
8164 \f
8165 /* Called via `note_stores' to record the initial value of a biv. Here we
8166 just record the location of the set and process it later. */
8168 static void
8170 rtx dest;
8171 rtx set;
8173 {
8184 /* If this is the first set found, record it. */
8186 {
8189 }
8190 }
8191 \f
8192 /* If any of the registers in X are "old" and currently have a last use earlier
8193 than INSN, update them to have a last use of INSN. Their actual last use
8194 will be the previous insn but it will not have a valid uid_luid so we can't
8195 use it. */
8197 static void
8199 rtx x;
8200 rtx insn;
8201 {
8202 /* Check for the case where INSN does not have a valid luid. In this case,
8203 there is no need to modify the regno_last_uid, as this can only happen
8204 when code is inserted after the loop_end to set a pseudo's final value,
8205 and hence this insn will never be the last use of x. */
8210 else
8211 {
8215 {
8221 }
8222 }
8223 }
8224 \f
8225 /* Given an insn INSN and condition COND, return the condition in a
8226 canonical form to simplify testing by callers. Specifically:
8228 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
8229 (2) Both operands will be machine operands; (cc0) will have been replaced.
8230 (3) If an operand is a constant, it will be the second operand.
8231 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
8232 for GE, GEU, and LEU.
8234 If the condition cannot be understood, or is an inequality floating-point
8235 comparison which needs to be reversed, 0 will be returned.
8237 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
8239 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8240 insn used in locating the condition was found. If a replacement test
8241 of the condition is desired, it should be placed in front of that
8242 insn and we will be sure that the inputs are still valid.
8244 If WANT_REG is non-zero, we wish the condition to be relative to that
8245 register, if possible. Therefore, do not canonicalize the condition
8246 further. */
8248 rtx
8250 rtx insn;
8251 rtx cond;
8254 rtx want_reg;
8255 {
8258 rtx set;
8259 rtx tem;
8271 {
8274 }
8279 /* If we are comparing a register with zero, see if the register is set
8280 in the previous insn to a COMPARE or a comparison operation. Perform
8281 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
8282 in cse.c */
8287 {
8288 /* Set non-zero when we find something of interest. */
8291 #ifdef HAVE_cc0
8292 /* If comparison with cc0, import actual comparison from compare
8293 insn. */
8295 {
8306 }
8307 #endif
8309 /* If this is a COMPARE, pick up the two things being compared. */
8311 {
8315 }
8319 /* Go back to the previous insn. Stop if it is not an INSN. We also
8320 stop if it isn't a single set or if it has a REG_INC note because
8321 we don't want to bother dealing with it. */
8329 /* If this is setting OP0, get what it sets it to if it looks
8330 relevant. */
8332 {
8335 /* ??? We may not combine comparisons done in a CCmode with
8336 comparisons not done in a CCmode. This is to aid targets
8337 like Alpha that have an IEEE compliant EQ instruction, and
8338 a non-IEEE compliant BEQ instruction. The use of CCmode is
8339 actually artificial, simply to prevent the combination, but
8340 should not affect other platforms.
8342 However, we must allow VOIDmode comparisons to match either
8343 CCmode or non-CCmode comparison, because some ports have
8344 modeless comparisons inside branch patterns.
8346 ??? This mode check should perhaps look more like the mode check
8347 in simplify_comparison in combine. */
8355 && (STORE_FLAG_VALUE
8358 #ifdef FLOAT_STORE_FLAG_VALUE
8361 && (REAL_VALUE_NEGATIVE
8363 #endif
8364 ))
8375 && (STORE_FLAG_VALUE
8378 #ifdef FLOAT_STORE_FLAG_VALUE
8381 && (REAL_VALUE_NEGATIVE
8383 #endif
8384 ))
8390 {
8391 /* We might have reversed a LT to get a GE here. But this wasn't
8392 actually the comparison of data, so we don't flag that we
8393 have had to reverse the condition. */
8397 }
8398 else
8400 }
8403 /* If this sets OP0, but not directly, we have to give up. */
8407 {
8411 {
8417 }
8422 }
8423 }
8425 /* If constant is first, put it last. */
8429 /* If OP0 is the result of a comparison, we weren't able to find what
8430 was really being compared, so fail. */
8434 /* Canonicalize any ordered comparison with integers involving equality
8435 if we can do computations in the relevant mode and we do not
8436 overflow. */
8441 {
8444 unsigned HOST_WIDE_INT max_val
8448 {
8454 /* When cross-compiling, const_val might be sign-extended from
8455 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
8475 }
8476 }
8478 /* If this was floating-point and we reversed anything other than an
8479 EQ or NE or (UN)ORDERED, return zero. */
8481 && did_reverse_condition
8483 && ! flag_fast_math
8487 #ifdef HAVE_cc0
8488 /* Never return CC0; return zero instead. */
8491 #endif
8494 }
8496 /* Given a jump insn JUMP, return the condition that will cause it to branch
8497 to its JUMP_LABEL. If the condition cannot be understood, or is an
8498 inequality floating-point comparison which needs to be reversed, 0 will
8499 be returned.
8501 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8502 insn used in locating the condition was found. If a replacement test
8503 of the condition is desired, it should be placed in front of that
8504 insn and we will be sure that the inputs are still valid. */
8506 rtx
8508 rtx jump;
8510 {
8511 rtx cond;
8513 rtx set;
8515 /* If this is not a standard conditional jump, we can't parse it. */
8523 /* If this branches to JUMP_LABEL when the condition is false, reverse
8524 the condition. */
8525 reverse
8530 }
8532 /* Similar to above routine, except that we also put an invariant last
8533 unless both operands are invariants. */
8535 rtx
8538 rtx x;
8539 {
8549 }
8551 /* Scan the function and determine whether it has indirect (computed) jumps.
8553 This is taken mostly from flow.c; similar code exists elsewhere
8554 in the compiler. It may be useful to put this into rtlanal.c. */
8555 static int
8557 rtx start;
8558 {
8559 rtx insn;
8566 }
8568 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
8569 documentation for LOOP_MEMS for the definition of `appropriate'.
8570 This function is called from prescan_loop via for_each_rtx. */
8572 static int
8576 {
8585 {
8590 /* We're not interested in MEMs that are only clobbered. */
8594 /* We're not interested in the MEM associated with a
8595 CONST_DOUBLE, so there's no need to traverse into this. */
8599 /* We're not interested in any MEMs that only appear in notes. */
8603 /* This is not a MEM. */
8605 }
8607 /* See if we've already seen this MEM. */
8610 {
8612 /* The modes of the two memory accesses are different. If
8613 this happens, something tricky is going on, and we just
8614 don't optimize accesses to this MEM. */
8618 }
8620 /* Resize the array, if necessary. */
8622 {
8625 else
8631 }
8633 /* Actually insert the MEM. */
8635 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
8636 because we can't put it in a register. We still store it in the
8637 table, though, so that if we see the same address later, but in a
8638 non-BLK mode, we'll not think we can optimize it at that point. */
8644 }
8646 /* Like load_mems, but also ensures that REGS->SET_IN_LOOP,
8647 REGS->MAY_NOT_OPTIMIZE, REGS->SINGLE_USAGE, and INSN_COUNT have the correct
8648 values after load_mems. */
8650 static void
8654 {
8660 /* Recalculate regs->set_in_loop and friends since load_mems may have
8661 created new registers. */
8663 {
8671 {
8672 /* Grow all the arrays. */
8677 }
8678 /* Clear the arrays */
8687 {
8690 }
8692 #ifdef AVOID_CCMODE_COPIES
8693 /* Don't try to move insns which set CC registers if we should not
8694 create CCmode register copies. */
8698 #endif
8700 /* Set regs->n_times_set for the new registers. */
8704 }
8705 }
8707 /* Move MEMs into registers for the duration of the loop. */
8709 static void
8712 {
8717 rtx p;
8719 rtx end_label;
8720 /* Nonzero if the next instruction may never be executed. */
8727 /* We cannot use next_label here because it skips over normal insns. */
8732 /* Check to see if it's possible that some instructions in the loop are
8733 never executed. Also check if there is a goto out of the loop other
8734 than right after the end of the loop. */
8738 {
8742 /* If we enter the loop in the middle, and scan
8743 around to the beginning, don't set maybe_never
8744 for that. This must be an unconditional jump,
8745 otherwise the code at the top of the loop might
8746 never be executed. Unconditional jumps are
8747 followed a by barrier then loop end. */
8752 {
8753 /* If this is a jump outside of the loop but not right
8754 after the end of the loop, we would have to emit new fixup
8755 sequences for each such label. */
8763 /* Something complicated. */
8765 else
8766 /* If there are any more instructions in the loop, they
8767 might not be reached. */
8769 }
8772 }
8774 /* Find start of the extended basic block that enters the loop. */
8778 ;
8782 /* Build table of mems that get set to constant values before the
8783 loop. */
8787 /* Actually move the MEMs. */
8789 {
8790 regset_head load_copies;
8791 regset_head store_copies;
8793 rtx reg;
8795 rtx mem_list_entry;
8799 /* There's no telling whether or not MEM is modified. */
8802 /* Go through the MEMs written to in the loop to see if this
8803 one is aliased by one of them. */
8806 {
8811 {
8812 /* MEM is indeed aliased by this store. */
8815 }
8817 }
8823 /* If this MEM is written to, we must be sure that there
8824 are no reads from another MEM that aliases this one. */
8826 {
8830 {
8834 VOIDmode,
8836 rtx_varies_p))
8837 {
8838 /* It's not safe to hoist loop_info->mems[i] out of
8839 the loop because writes to it might not be
8840 seen by reads from loop_info->mems[j]. */
8843 }
8844 }
8845 }
8848 /* We can't access the MEM outside the loop; it might
8849 cause a trap that wouldn't have happened otherwise. */
8853 /* We thought we were going to lift this MEM out of the
8854 loop, but later discovered that we could not. */
8860 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
8861 order to keep scan_loop from moving stores to this MEM
8862 out of the loop just because this REG is neither a
8863 user-variable nor used in the loop test. */
8868 /* Now, replace all references to the MEM with the
8869 corresponding pesudos. */
8874 {
8876 {
8877 rtx set;
8881 /* See if this copies the mem into a register that isn't
8882 modified afterwards. We'll try to do copy propagation
8883 a little further on. */
8885 /* @@@ This test is _way_ too conservative. */
8886 && ! maybe_never
8895 /* See if this copies the mem from a register that isn't
8896 modified afterwards. We'll try to remove the
8897 redundant copy later on by doing a little register
8898 renaming and copy propagation. This will help
8899 to untangle things for the BIV detection code. */
8901 && ! maybe_never
8909 /* Replace the memory reference with the shadow register. */
8912 }
8917 }
8920 /* We couldn't replace all occurrences of the MEM. */
8922 else
8923 {
8924 /* Load the memory immediately before LOOP->START, which is
8925 the NOTE_LOOP_BEG. */
8927 rtx set;
8933 {
8937 {
8941 /* Extending hard register lifetimes cuases crash
8942 on SRC targets. Doing so on non-SRC is
8943 probably also not good idea, since we most
8944 probably have pseudoregister equivalence as
8945 well. */
8948 }
8949 /* Use the constant equivalence if that is cheap enough. */
8955 {
8958 }
8960 /* If best_equiv is nonzero, we know that MEM is set to a
8961 constant or register before the loop. We will use this
8962 knowledge to initialize the shadow register with that
8963 constant or reg rather than by loading from MEM. */
8966 }
8975 {
8977 {
8980 }
8982 /* Store the memory immediately after END, which is
8983 the NOTE_LOOP_END. */
8986 }
8989 {
8994 }
8996 /* Attempt a bit of copy propagation. This helps untangle the
8997 data flow, and enables {basic,general}_induction_var to find
8998 more bivs/givs. */
8999 EXECUTE_IF_SET_IN_REG_SET
9001 {
9003 });
9006 EXECUTE_IF_SET_IN_REG_SET
9008 {
9010 });
9012 }
9013 }
9016 {
9017 /* Now, we need to replace all references to the previous exit
9018 label with the new one. */
9019 rtx_pair rr;
9024 {
9027 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9028 field. This is not handled by for_each_rtx because it doesn't
9029 handle unprinted ('0') fields. We need to update JUMP_LABEL
9030 because the immediately following unroll pass will use it.
9031 replace_label would not work anyways, because that only handles
9032 LABEL_REFs. */
9035 }
9036 }
9039 }
9041 /* For communication between note_reg_stored and its caller. */
9042 struct note_reg_stored_arg
9043 {
9045 rtx reg;
9046 };
9048 /* Called via note_stores, record in SET_SEEN whether X, which is written,
9049 is equal to ARG. */
9050 static void
9054 {
9058 }
9060 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
9061 There must be exactly one insn that sets this pseudo; it will be
9062 deleted if all replacements succeed and we can prove that the register
9063 is not used after the loop. */
9065 static void
9068 rtx replacement;
9070 {
9071 /* This is the reg that we are copying from. */
9074 rtx insn;
9075 /* These help keep track of whether we replaced all uses of the reg. */
9082 {
9083 rtx set;
9085 /* Only substitute within one extended basic block from the initializing
9086 insn. */
9093 /* Is this the initializing insn? */
9098 {
9105 }
9107 /* Only substitute after seeing the initializing insn. */
9109 {
9116 /* Stop replacing when REPLACEMENT is modified. */
9122 }
9123 }
9127 {
9131 {
9137 }
9140 }
9141 }
9143 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
9144 loop LOOP if the order of the sets of these registers can be
9145 swapped. There must be exactly one insn within the loop that sets
9146 this pseudo followed immediately by a move insn that sets
9147 REPLACEMENT with REGNO. */
9148 static void
9151 rtx replacement;
9153 {
9154 rtx insn;
9155 rtx set;
9163 {
9164 /* Search for the insn that copies REGNO to NEW_REGNO? */
9172 }
9175 {
9176 rtx prev_insn;
9177 rtx prev_set;
9179 /* Some DEF-USE info would come in handy here to make this
9180 function more general. For now, just check the previous insn
9181 which is the most likely candidate for setting REGNO. */
9189 {
9190 /* We have:
9191 (set (reg regno) (expr))
9192 (set (reg new_regno) (reg regno))
9194 so try converting this to:
9195 (set (reg new_regno) (expr))
9196 (set (reg regno) (reg new_regno))
9198 The former construct is often generated when a global
9199 variable used for an induction variable is shadowed by a
9200 register (NEW_REGNO). The latter construct improves the
9201 chances of GIV replacement and BIV elimination. */
9211 {
9218 /* Update first use of REGNO. */
9222 /* Now perform copy propagation to hopefully
9223 remove all uses of REGNO within the loop. */
9225 }
9226 }
9227 }
9228 }
9230 /* Replace MEM with its associated pseudo register. This function is
9231 called from load_mems via for_each_rtx. DATA is actually a pointer
9232 to a structure describing the instruction currently being scanned
9233 and the MEM we are currently replacing. */
9235 static int
9239 {
9247 {
9252 /* We're not interested in the MEM associated with a
9253 CONST_DOUBLE, so there's no need to traverse into one. */
9257 /* This is not a MEM. */
9259 }
9262 /* This is not the MEM we are currently replacing. */
9265 /* Actually replace the MEM. */
9269 }
9271 static void
9273 rtx insn;
9274 rtx mem;
9275 rtx reg;
9276 {
9277 loop_replace_args args;
9284 }
9286 /* Replace one register with another. Called through for_each_rtx; PX points
9287 to the rtx being scanned. DATA is actually a pointer to
9288 a structure of arguments. */
9290 static int
9294 {
9305 }
9307 static void
9309 rtx insn;
9310 rtx reg;
9311 rtx replacement;
9312 {
9313 loop_replace_args args;
9320 }
9322 /* Replace occurrences of the old exit label for the loop with the new
9323 one. DATA is an rtx_pair containing the old and new labels,
9324 respectively. */
9326 static int
9330 {
9349 }
9350 \f
9351 #define LOOP_BLOCK_NUM_1(INSN) \
9352 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
9354 /* The notes do not have an assigned block, so look at the next insn. */
9355 #define LOOP_BLOCK_NUM(INSN) \
9356 ((INSN) ? (GET_CODE (INSN) == NOTE \
9357 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
9358 : LOOP_BLOCK_NUM_1 (INSN)) \
9359 : -1)
9361 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
9363 static void
9368 {
9369 rtx label;
9374 /* Print diagnostics to compare our concept of a loop with
9375 what the loop notes say. */
9390 {
9410 {
9413 {
9416 }
9417 }
9420 /* This can happen when a marked loop appears as two nested loops,
9421 say from while (a || b) {}. The inner loop won't match
9422 the loop markers but the outer one will. */
9425 }
9426 }
9428 /* Call this function from the debugger to dump LOOP. */
9430 void
9433 {
9435 }