1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005, 2006 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19 ;; Boston, MA 02110-1301, USA.
21 ;; Return 1 for anything except PARALLEL.
22 (define_predicate "any_operand"
23 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem"))
25 ;; Return 1 for any PARALLEL.
26 (define_predicate "any_parallel_operand"
27 (match_code "parallel"))
29 ;; Return 1 if op is COUNT register.
30 (define_predicate "count_register_operand"
31 (and (match_code "reg")
32 (match_test "REGNO (op) == COUNT_REGISTER_REGNUM
33 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
35 ;; Return 1 if op is an Altivec register.
36 (define_predicate "altivec_register_operand"
37 (and (match_operand 0 "register_operand")
38 (match_test "GET_CODE (op) != REG
39 || ALTIVEC_REGNO_P (REGNO (op))
40 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
42 ;; Return 1 if op is XER register.
43 (define_predicate "xer_operand"
44 (and (match_code "reg")
45 (match_test "XER_REGNO_P (REGNO (op))")))
47 ;; Return 1 if op is a signed 5-bit constant integer.
48 (define_predicate "s5bit_cint_operand"
49 (and (match_code "const_int")
50 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
52 ;; Return 1 if op is a unsigned 5-bit constant integer.
53 (define_predicate "u5bit_cint_operand"
54 (and (match_code "const_int")
55 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
57 ;; Return 1 if op is a signed 8-bit constant integer.
58 ;; Integer multiplication complete more quickly
59 (define_predicate "s8bit_cint_operand"
60 (and (match_code "const_int")
61 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
63 ;; Return 1 if op is a constant integer that can fit in a D field.
64 (define_predicate "short_cint_operand"
65 (and (match_code "const_int")
66 (match_test "satisfies_constraint_I (op)")))
68 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
69 (define_predicate "u_short_cint_operand"
70 (and (match_code "const_int")
71 (match_test "satisfies_constraint_K (op)")))
73 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
74 (define_predicate "non_short_cint_operand"
75 (and (match_code "const_int")
76 (match_test "(unsigned HOST_WIDE_INT)
77 (INTVAL (op) + 0x8000) >= 0x10000")))
79 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
80 (define_predicate "exact_log2_cint_operand"
81 (and (match_code "const_int")
82 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
84 ;; Return 1 if op is a register that is not special.
85 (define_predicate "gpc_reg_operand"
86 (and (match_operand 0 "register_operand")
87 (match_test "(GET_CODE (op) != REG
88 || (REGNO (op) >= ARG_POINTER_REGNUM
89 && !XER_REGNO_P (REGNO (op)))
90 || REGNO (op) < MQ_REGNO)
91 && !((TARGET_E500_DOUBLE || TARGET_SPE)
92 && invalid_e500_subreg (op, mode))")))
94 ;; Return 1 if op is a register that is a condition register field.
95 (define_predicate "cc_reg_operand"
96 (and (match_operand 0 "register_operand")
97 (match_test "GET_CODE (op) != REG
98 || REGNO (op) > LAST_VIRTUAL_REGISTER
99 || CR_REGNO_P (REGNO (op))")))
101 ;; Return 1 if op is a register that is a condition register field not cr0.
102 (define_predicate "cc_reg_not_cr0_operand"
103 (and (match_operand 0 "register_operand")
104 (match_test "GET_CODE (op) != REG
105 || REGNO (op) > LAST_VIRTUAL_REGISTER
106 || CR_REGNO_NOT_CR0_P (REGNO (op))")))
108 ;; Return 1 if op is a constant integer valid for D field
109 ;; or non-special register register.
110 (define_predicate "reg_or_short_operand"
111 (if_then_else (match_code "const_int")
112 (match_operand 0 "short_cint_operand")
113 (match_operand 0 "gpc_reg_operand")))
115 ;; Return 1 if op is a constant integer valid whose negation is valid for
116 ;; D field or non-special register register.
117 ;; Do not allow a constant zero because all patterns that call this
118 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
119 ;; or equal to const, which does not work for zero.
120 (define_predicate "reg_or_neg_short_operand"
121 (if_then_else (match_code "const_int")
122 (match_test "satisfies_constraint_P (op)
123 && INTVAL (op) != 0")
124 (match_operand 0 "gpc_reg_operand")))
126 ;; Return 1 if op is a constant integer valid for DS field
127 ;; or non-special register.
128 (define_predicate "reg_or_aligned_short_operand"
129 (if_then_else (match_code "const_int")
130 (and (match_operand 0 "short_cint_operand")
131 (match_test "!(INTVAL (op) & 3)"))
132 (match_operand 0 "gpc_reg_operand")))
134 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
135 ;; or non-special register.
136 (define_predicate "reg_or_u_short_operand"
137 (if_then_else (match_code "const_int")
138 (match_operand 0 "u_short_cint_operand")
139 (match_operand 0 "gpc_reg_operand")))
141 ;; Return 1 if op is any constant integer
142 ;; or non-special register.
143 (define_predicate "reg_or_cint_operand"
144 (ior (match_code "const_int")
145 (match_operand 0 "gpc_reg_operand")))
147 ;; Return 1 if op is a constant integer valid for addition
148 ;; or non-special register.
149 (define_predicate "reg_or_add_cint_operand"
150 (if_then_else (match_code "const_int")
151 (match_test "(HOST_BITS_PER_WIDE_INT == 32
152 && (mode == SImode || INTVAL (op) < 0x7fff8000))
153 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
154 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
155 (match_operand 0 "gpc_reg_operand")))
157 ;; Return 1 if op is a constant integer valid for subtraction
158 ;; or non-special register.
159 (define_predicate "reg_or_sub_cint_operand"
160 (if_then_else (match_code "const_int")
161 (match_test "(HOST_BITS_PER_WIDE_INT == 32
162 && (mode == SImode || - INTVAL (op) < 0x7fff8000))
163 || ((unsigned HOST_WIDE_INT) (- INTVAL (op)
165 ? 0x80000000 : 0x80008000))
166 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
167 (match_operand 0 "gpc_reg_operand")))
169 ;; Return 1 if op is any 32-bit unsigned constant integer
170 ;; or non-special register.
171 (define_predicate "reg_or_logical_cint_operand"
172 (if_then_else (match_code "const_int")
173 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
175 || ((INTVAL (op) & GET_MODE_MASK (mode)
176 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
177 (if_then_else (match_code "const_double")
178 (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
180 && CONST_DOUBLE_HIGH (op) == 0")
181 (match_operand 0 "gpc_reg_operand"))))
183 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
184 ;; with no more than one instruction per word.
185 (define_predicate "easy_fp_constant"
186 (match_code "const_double")
191 if (GET_MODE (op) != mode
192 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
195 /* Consider all constants with -msoft-float to be easy. */
196 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
200 if (DECIMAL_FLOAT_MODE_P (mode))
203 /* If we are using V.4 style PIC, consider all constants to be hard. */
204 if (flag_pic && DEFAULT_ABI == ABI_V4)
207 #ifdef TARGET_RELOCATABLE
208 /* Similarly if we are using -mrelocatable, consider all constants
210 if (TARGET_RELOCATABLE)
217 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
218 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
220 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
221 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
222 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
223 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
226 /* Force constants to memory before reload to utilize
227 compress_float_constant.
228 Avoid this when flag_unsafe_math_optimizations is enabled
229 because RDIV division to reciprocal optimization is not able
230 to regenerate the division. */
231 if (TARGET_E500_DOUBLE
232 || (!reload_in_progress && !reload_completed
233 && !flag_unsafe_math_optimizations))
236 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
237 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
239 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
240 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
243 /* The constant 0.f is easy. */
244 if (op == CONST0_RTX (SFmode))
247 /* Force constants to memory before reload to utilize
248 compress_float_constant.
249 Avoid this when flag_unsafe_math_optimizations is enabled
250 because RDIV division to reciprocal optimization is not able
251 to regenerate the division. */
252 if (!reload_in_progress && !reload_completed
253 && !flag_unsafe_math_optimizations)
256 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
257 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
259 return num_insns_constant_wide (k[0]) == 1;
262 return ((TARGET_POWERPC64
263 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
264 || (num_insns_constant (op, DImode) <= 2));
274 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
275 ;; vector register without using memory.
276 (define_predicate "easy_vector_constant"
277 (match_code "const_vector")
279 if (ALTIVEC_VECTOR_MODE (mode))
281 if (zero_constant (op, mode))
283 return easy_altivec_constant (op, mode);
286 if (SPE_VECTOR_MODE (mode))
289 if (zero_constant (op, mode))
291 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
294 /* Limit SPE vectors to 15 bits signed. These we can generate with:
299 I don't know how efficient it would be to allow bigger constants,
300 considering we'll have an extra 'ori' for every 'li'. I doubt 5
301 instructions is better than a 64-bit memory load, but I don't
302 have the e500 timing specs. */
303 if (mode == V2SImode)
305 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
306 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
307 return cst >= -0x7fff && cst <= 0x7fff
308 && cst2 >= -0x7fff && cst2 <= 0x7fff;
315 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
316 (define_predicate "easy_vector_constant_add_self"
317 (and (match_code "const_vector")
318 (and (match_test "TARGET_ALTIVEC")
319 (match_test "easy_altivec_constant (op, mode)")))
321 rtx last = CONST_VECTOR_ELT (op, GET_MODE_NUNITS (mode) - 1);
322 HOST_WIDE_INT val = ((INTVAL (last) & 0xff) ^ 0x80) - 0x80;
323 return EASY_VECTOR_15_ADD_SELF (val);
326 ;; Return 1 if operand is constant zero (scalars and vectors).
327 (define_predicate "zero_constant"
328 (and (match_code "const_int,const_double,const_vector")
329 (match_test "op == CONST0_RTX (mode)")))
331 ;; Return 1 if operand is 0.0.
332 ;; or non-special register register field no cr0
333 (define_predicate "zero_fp_constant"
334 (and (match_code "const_double")
335 (match_test "SCALAR_FLOAT_MODE_P (mode)
336 && op == CONST0_RTX (mode)")))
338 ;; Return 1 if the operand is in volatile memory. Note that during the
339 ;; RTL generation phase, memory_operand does not return TRUE for volatile
340 ;; memory references. So this function allows us to recognize volatile
341 ;; references where it's safe.
342 (define_predicate "volatile_mem_operand"
343 (and (and (match_code "mem")
344 (match_test "MEM_VOLATILE_P (op)"))
345 (if_then_else (match_test "reload_completed")
346 (match_operand 0 "memory_operand")
347 (if_then_else (match_test "reload_in_progress")
348 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
349 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
351 ;; Return 1 if the operand is an offsettable memory operand.
352 (define_predicate "offsettable_mem_operand"
353 (and (match_code "mem")
354 (match_test "offsettable_address_p (reload_completed
355 || reload_in_progress,
356 mode, XEXP (op, 0))")))
358 ;; Return 1 if the operand is a memory operand with an address divisible by 4
359 (define_predicate "word_offset_memref_operand"
360 (and (match_operand 0 "memory_operand")
361 (match_test "GET_CODE (XEXP (op, 0)) != PLUS
362 || ! REG_P (XEXP (XEXP (op, 0), 0))
363 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT
364 || INTVAL (XEXP (XEXP (op, 0), 1)) % 4 == 0")))
366 ;; Return 1 if the operand is an indexed or indirect memory operand.
367 (define_predicate "indexed_or_indirect_operand"
372 && ALTIVEC_VECTOR_MODE (mode)
373 && GET_CODE (op) == AND
374 && GET_CODE (XEXP (op, 1)) == CONST_INT
375 && INTVAL (XEXP (op, 1)) == -16)
378 return indexed_or_indirect_address (op, mode);
381 ;; Return 1 if the operand is an indexed or indirect address.
382 (define_special_predicate "indexed_or_indirect_address"
383 (and (match_test "REG_P (op)
384 || (GET_CODE (op) == PLUS
385 /* Omit testing REG_P (XEXP (op, 0)). */
386 && REG_P (XEXP (op, 1)))")
387 (match_operand 0 "address_operand")))
389 ;; Used for the destination of the fix_truncdfsi2 expander.
390 ;; If stfiwx will be used, the result goes to memory; otherwise,
391 ;; we're going to emit a store and a load of a subreg, so the dest is a
393 (define_predicate "fix_trunc_dest_operand"
394 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT")
395 (match_operand 0 "memory_operand")
396 (match_operand 0 "gpc_reg_operand")))
398 ;; Return 1 if the operand is either a non-special register or can be used
399 ;; as the operand of a `mode' add insn.
400 (define_predicate "add_operand"
401 (if_then_else (match_code "const_int")
402 (match_test "satisfies_constraint_I (op)
403 || satisfies_constraint_L (op)")
404 (match_operand 0 "gpc_reg_operand")))
406 ;; Return 1 if OP is a constant but not a valid add_operand.
407 (define_predicate "non_add_cint_operand"
408 (and (match_code "const_int")
409 (match_test "!satisfies_constraint_I (op)
410 && !satisfies_constraint_L (op)")))
412 ;; Return 1 if the operand is a constant that can be used as the operand
414 (define_predicate "logical_const_operand"
415 (match_code "const_int,const_double")
417 HOST_WIDE_INT opl, oph;
419 if (GET_CODE (op) == CONST_INT)
421 opl = INTVAL (op) & GET_MODE_MASK (mode);
423 if (HOST_BITS_PER_WIDE_INT <= 32
424 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
427 else if (GET_CODE (op) == CONST_DOUBLE)
429 gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT);
431 opl = CONST_DOUBLE_LOW (op);
432 oph = CONST_DOUBLE_HIGH (op);
439 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
440 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
443 ;; Return 1 if the operand is a non-special register or a constant that
444 ;; can be used as the operand of an OR or XOR.
445 (define_predicate "logical_operand"
446 (ior (match_operand 0 "gpc_reg_operand")
447 (match_operand 0 "logical_const_operand")))
449 ;; Return 1 if op is a constant that is not a logical operand, but could
450 ;; be split into one.
451 (define_predicate "non_logical_cint_operand"
452 (and (match_code "const_int,const_double")
453 (and (not (match_operand 0 "logical_operand"))
454 (match_operand 0 "reg_or_logical_cint_operand"))))
456 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
457 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1
458 ;; transitions). Reject all ones and all zeros, since these should have
459 ;; been optimized away and confuse the making of MB and ME.
460 (define_predicate "mask_operand"
461 (match_code "const_int")
463 HOST_WIDE_INT c, lsb;
467 if (TARGET_POWERPC64)
469 /* Fail if the mask is not 32-bit. */
470 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
473 /* Fail if the mask wraps around because the upper 32-bits of the
474 mask will all be 1s, contrary to GCC's internal view. */
475 if ((c & 0x80000001) == 0x80000001)
479 /* We don't change the number of transitions by inverting,
480 so make sure we start with the LS bit zero. */
484 /* Reject all zeros or all ones. */
488 /* Find the first transition. */
491 /* Invert to look for a second transition. */
494 /* Erase first transition. */
497 /* Find the second transition (if any). */
500 /* Match if all the bits above are 1's (or c is zero). */
504 ;; Return 1 for the PowerPC64 rlwinm corner case.
505 (define_predicate "mask_operand_wrap"
506 (match_code "const_int")
508 HOST_WIDE_INT c, lsb;
512 if ((c & 0x80000001) != 0x80000001)
526 ;; Return 1 if the operand is a constant that is a PowerPC64 mask
527 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
528 ;; transition). Reject all zeros, since zero should have been
529 ;; optimized away and confuses the making of MB and ME.
530 (define_predicate "mask64_operand"
531 (match_code "const_int")
533 HOST_WIDE_INT c, lsb;
537 /* Reject all zeros. */
541 /* We don't change the number of transitions by inverting,
542 so make sure we start with the LS bit zero. */
546 /* Find the first transition. */
549 /* Match if all the bits above are 1's (or c is zero). */
553 ;; Like mask64_operand, but allow up to three transitions. This
554 ;; predicate is used by insn patterns that generate two rldicl or
555 ;; rldicr machine insns.
556 (define_predicate "mask64_2_operand"
557 (match_code "const_int")
559 HOST_WIDE_INT c, lsb;
563 /* Disallow all zeros. */
567 /* We don't change the number of transitions by inverting,
568 so make sure we start with the LS bit zero. */
572 /* Find the first transition. */
575 /* Invert to look for a second transition. */
578 /* Erase first transition. */
581 /* Find the second transition. */
584 /* Invert to look for a third transition. */
587 /* Erase second transition. */
590 /* Find the third transition (if any). */
593 /* Match if all the bits above are 1's (or c is zero). */
597 ;; Like and_operand, but also match constants that can be implemented
598 ;; with two rldicl or rldicr insns.
599 (define_predicate "and64_2_operand"
600 (ior (match_operand 0 "mask64_2_operand")
601 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
602 (match_operand 0 "gpc_reg_operand")
603 (match_operand 0 "logical_operand"))))
605 ;; Return 1 if the operand is either a non-special register or a
606 ;; constant that can be used as the operand of a logical AND.
607 (define_predicate "and_operand"
608 (ior (match_operand 0 "mask_operand")
609 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode")
610 (match_operand 0 "mask64_operand"))
611 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
612 (match_operand 0 "gpc_reg_operand")
613 (match_operand 0 "logical_operand")))))
615 ;; Return 1 if the operand is either a logical operand or a short cint operand.
616 (define_predicate "scc_eq_operand"
617 (ior (match_operand 0 "logical_operand")
618 (match_operand 0 "short_cint_operand")))
620 ;; Return 1 if the operand is a general non-special register or memory operand.
621 (define_predicate "reg_or_mem_operand"
622 (ior (match_operand 0 "memory_operand")
623 (ior (and (match_code "mem")
624 (match_test "macho_lo_sum_memory_operand (op, mode)"))
625 (ior (match_operand 0 "volatile_mem_operand")
626 (match_operand 0 "gpc_reg_operand")))))
628 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
629 (define_predicate "reg_or_none500mem_operand"
630 (if_then_else (match_code "mem")
631 (and (match_test "!TARGET_E500_DOUBLE")
632 (ior (match_operand 0 "memory_operand")
633 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
634 (match_operand 0 "volatile_mem_operand"))))
635 (match_operand 0 "gpc_reg_operand")))
637 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
638 (define_predicate "zero_reg_mem_operand"
639 (ior (match_operand 0 "zero_fp_constant")
640 (match_operand 0 "reg_or_mem_operand")))
642 ;; Return 1 if the operand is a general register or memory operand without
643 ;; pre_inc or pre_dec, which produces invalid form of PowerPC lwa
645 (define_predicate "lwa_operand"
646 (match_code "reg,subreg,mem")
650 if (reload_completed && GET_CODE (inner) == SUBREG)
651 inner = SUBREG_REG (inner);
653 return gpc_reg_operand (inner, mode)
654 || (memory_operand (inner, mode)
655 && GET_CODE (XEXP (inner, 0)) != PRE_INC
656 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
657 && (GET_CODE (XEXP (inner, 0)) != PLUS
658 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
659 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
662 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
663 (define_predicate "symbol_ref_operand"
664 (and (match_code "symbol_ref")
665 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
666 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
668 ;; Return 1 if op is an operand that can be loaded via the GOT.
669 ;; or non-special register register field no cr0
670 (define_predicate "got_operand"
671 (match_code "symbol_ref,const,label_ref"))
673 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
674 ;; excluding labels involving addition.
675 (define_predicate "got_no_const_operand"
676 (match_code "symbol_ref,label_ref"))
678 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
679 (define_predicate "rs6000_tls_symbol_ref"
680 (and (match_code "symbol_ref")
681 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
683 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
684 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
685 (define_predicate "call_operand"
686 (if_then_else (match_code "reg")
687 (match_test "REGNO (op) == LINK_REGISTER_REGNUM
688 || REGNO (op) == COUNT_REGISTER_REGNUM
689 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
690 (match_code "symbol_ref")))
692 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
694 (define_predicate "current_file_function_operand"
695 (and (match_code "symbol_ref")
696 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
697 && (SYMBOL_REF_LOCAL_P (op)
698 || (op == XEXP (DECL_RTL (current_function_decl),
701 ;; Return 1 if this operand is a valid input for a move insn.
702 (define_predicate "input_operand"
703 (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
704 const_double,const_vector,const_int,plus")
706 /* Memory is always valid. */
707 if (memory_operand (op, mode))
710 /* For floating-point, easy constants are valid. */
711 if (SCALAR_FLOAT_MODE_P (mode)
713 && easy_fp_constant (op, mode))
716 /* Allow any integer constant. */
717 if (GET_MODE_CLASS (mode) == MODE_INT
718 && (GET_CODE (op) == CONST_INT
719 || GET_CODE (op) == CONST_DOUBLE))
722 /* Allow easy vector constants. */
723 if (GET_CODE (op) == CONST_VECTOR
724 && easy_vector_constant (op, mode))
727 /* Do not allow invalid E500 subregs. */
728 if ((TARGET_E500_DOUBLE || TARGET_SPE)
729 && GET_CODE (op) == SUBREG
730 && invalid_e500_subreg (op, mode))
733 /* For floating-point or multi-word mode, the only remaining valid type
735 if (SCALAR_FLOAT_MODE_P (mode)
736 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
737 return register_operand (op, mode);
739 /* The only cases left are integral modes one word or smaller (we
740 do not get called for MODE_CC values). These can be in any
742 if (register_operand (op, mode))
745 /* A SYMBOL_REF referring to the TOC is valid. */
746 if (legitimate_constant_pool_address_p (op))
749 /* A constant pool expression (relative to the TOC) is valid */
750 if (toc_relative_expr_p (op))
753 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
755 if (DEFAULT_ABI == ABI_V4
756 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
757 && small_data_operand (op, Pmode))
763 ;; Return true if OP is an invalid SUBREG operation on the e500.
764 (define_predicate "rs6000_nonimmediate_operand"
765 (match_code "reg,subreg,mem")
767 if ((TARGET_E500_DOUBLE || TARGET_SPE)
768 && GET_CODE (op) == SUBREG
769 && invalid_e500_subreg (op, mode))
772 return nonimmediate_operand (op, mode);
775 ;; Return true if operand is boolean operator.
776 (define_predicate "boolean_operator"
777 (match_code "and,ior,xor"))
779 ;; Return true if operand is OR-form of boolean operator.
780 (define_predicate "boolean_or_operator"
781 (match_code "ior,xor"))
783 ;; Return true if operand is an equality operator.
784 (define_special_predicate "equality_operator"
785 (match_code "eq,ne"))
787 ;; Return true if operand is MIN or MAX operator.
788 (define_predicate "min_max_operator"
789 (match_code "smin,smax,umin,umax"))
791 ;; Return 1 if OP is a comparison operation that is valid for a branch
792 ;; instruction. We check the opcode against the mode of the CC value.
793 ;; validate_condition_mode is an assertion.
794 (define_predicate "branch_comparison_operator"
795 (and (match_operand 0 "comparison_operator")
796 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
797 (match_test "validate_condition_mode (GET_CODE (op),
798 GET_MODE (XEXP (op, 0))),
801 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
802 ;; it must be a positive comparison.
803 (define_predicate "scc_comparison_operator"
804 (and (match_operand 0 "branch_comparison_operator")
805 (match_code "eq,lt,gt,ltu,gtu,unordered")))
807 ;; Return 1 if OP is a comparison operation that is valid for a branch
808 ;; insn, which is true if the corresponding bit in the CC register is set.
809 (define_predicate "branch_positive_comparison_operator"
810 (and (match_operand 0 "branch_comparison_operator")
811 (match_code "eq,lt,gt,ltu,gtu,unordered")))
813 ;; Return 1 is OP is a comparison operation that is valid for a trap insn.
814 (define_predicate "trap_comparison_operator"
815 (and (match_operand 0 "comparison_operator")
816 (match_code "eq,ne,le,lt,ge,gt,leu,ltu,geu,gtu")))
818 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
819 (define_predicate "load_multiple_operation"
820 (match_code "parallel")
822 int count = XVECLEN (op, 0);
823 unsigned int dest_regno;
827 /* Perform a quick check so we don't blow up below. */
829 || GET_CODE (XVECEXP (op, 0, 0)) != SET
830 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
831 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
834 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
835 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
837 for (i = 1; i < count; i++)
839 rtx elt = XVECEXP (op, 0, i);
841 if (GET_CODE (elt) != SET
842 || GET_CODE (SET_DEST (elt)) != REG
843 || GET_MODE (SET_DEST (elt)) != SImode
844 || REGNO (SET_DEST (elt)) != dest_regno + i
845 || GET_CODE (SET_SRC (elt)) != MEM
846 || GET_MODE (SET_SRC (elt)) != SImode
847 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
848 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
849 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
850 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
857 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
858 ;; The second vector element is a CLOBBER.
859 (define_predicate "store_multiple_operation"
860 (match_code "parallel")
862 int count = XVECLEN (op, 0) - 1;
863 unsigned int src_regno;
867 /* Perform a quick check so we don't blow up below. */
869 || GET_CODE (XVECEXP (op, 0, 0)) != SET
870 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
871 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
874 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
875 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
877 for (i = 1; i < count; i++)
879 rtx elt = XVECEXP (op, 0, i + 1);
881 if (GET_CODE (elt) != SET
882 || GET_CODE (SET_SRC (elt)) != REG
883 || GET_MODE (SET_SRC (elt)) != SImode
884 || REGNO (SET_SRC (elt)) != src_regno + i
885 || GET_CODE (SET_DEST (elt)) != MEM
886 || GET_MODE (SET_DEST (elt)) != SImode
887 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
888 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
889 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
890 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
897 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
899 (define_predicate "save_world_operation"
900 (match_code "parallel")
905 int count = XVECLEN (op, 0);
911 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
912 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
915 for (i=1; i <= 18; i++)
917 elt = XVECEXP (op, 0, index++);
918 if (GET_CODE (elt) != SET
919 || GET_CODE (SET_DEST (elt)) != MEM
920 || ! memory_operand (SET_DEST (elt), DFmode)
921 || GET_CODE (SET_SRC (elt)) != REG
922 || GET_MODE (SET_SRC (elt)) != DFmode)
926 for (i=1; i <= 12; i++)
928 elt = XVECEXP (op, 0, index++);
929 if (GET_CODE (elt) != SET
930 || GET_CODE (SET_DEST (elt)) != MEM
931 || GET_CODE (SET_SRC (elt)) != REG
932 || GET_MODE (SET_SRC (elt)) != V4SImode)
936 for (i=1; i <= 19; i++)
938 elt = XVECEXP (op, 0, index++);
939 if (GET_CODE (elt) != SET
940 || GET_CODE (SET_DEST (elt)) != MEM
941 || ! memory_operand (SET_DEST (elt), Pmode)
942 || GET_CODE (SET_SRC (elt)) != REG
943 || GET_MODE (SET_SRC (elt)) != Pmode)
947 elt = XVECEXP (op, 0, index++);
948 if (GET_CODE (elt) != SET
949 || GET_CODE (SET_DEST (elt)) != MEM
950 || ! memory_operand (SET_DEST (elt), Pmode)
951 || GET_CODE (SET_SRC (elt)) != REG
952 || REGNO (SET_SRC (elt)) != CR2_REGNO
953 || GET_MODE (SET_SRC (elt)) != Pmode)
956 if (GET_CODE (XVECEXP (op, 0, index++)) != USE
957 || GET_CODE (XVECEXP (op, 0, index++)) != USE
958 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
963 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
965 (define_predicate "restore_world_operation"
966 (match_code "parallel")
971 int count = XVECLEN (op, 0);
977 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
978 || GET_CODE (XVECEXP (op, 0, index++)) != USE
979 || GET_CODE (XVECEXP (op, 0, index++)) != USE
980 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
983 elt = XVECEXP (op, 0, index++);
984 if (GET_CODE (elt) != SET
985 || GET_CODE (SET_SRC (elt)) != MEM
986 || ! memory_operand (SET_SRC (elt), Pmode)
987 || GET_CODE (SET_DEST (elt)) != REG
988 || REGNO (SET_DEST (elt)) != CR2_REGNO
989 || GET_MODE (SET_DEST (elt)) != Pmode)
992 for (i=1; i <= 19; i++)
994 elt = XVECEXP (op, 0, index++);
995 if (GET_CODE (elt) != SET
996 || GET_CODE (SET_SRC (elt)) != MEM
997 || ! memory_operand (SET_SRC (elt), Pmode)
998 || GET_CODE (SET_DEST (elt)) != REG
999 || GET_MODE (SET_DEST (elt)) != Pmode)
1003 for (i=1; i <= 12; i++)
1005 elt = XVECEXP (op, 0, index++);
1006 if (GET_CODE (elt) != SET
1007 || GET_CODE (SET_SRC (elt)) != MEM
1008 || GET_CODE (SET_DEST (elt)) != REG
1009 || GET_MODE (SET_DEST (elt)) != V4SImode)
1013 for (i=1; i <= 18; i++)
1015 elt = XVECEXP (op, 0, index++);
1016 if (GET_CODE (elt) != SET
1017 || GET_CODE (SET_SRC (elt)) != MEM
1018 || ! memory_operand (SET_SRC (elt), DFmode)
1019 || GET_CODE (SET_DEST (elt)) != REG
1020 || GET_MODE (SET_DEST (elt)) != DFmode)
1024 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1025 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1026 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1027 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1028 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1033 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1034 (define_predicate "vrsave_operation"
1035 (match_code "parallel")
1037 int count = XVECLEN (op, 0);
1038 unsigned int dest_regno, src_regno;
1042 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1043 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1044 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1045 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1048 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1049 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1051 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1054 for (i = 1; i < count; i++)
1056 rtx elt = XVECEXP (op, 0, i);
1058 if (GET_CODE (elt) != CLOBBER
1059 && GET_CODE (elt) != SET)
1066 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1067 (define_predicate "mfcr_operation"
1068 (match_code "parallel")
1070 int count = XVECLEN (op, 0);
1073 /* Perform a quick check so we don't blow up below. */
1075 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1076 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1077 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1080 for (i = 0; i < count; i++)
1082 rtx exp = XVECEXP (op, 0, i);
1087 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1089 if (GET_CODE (src_reg) != REG
1090 || GET_MODE (src_reg) != CCmode
1091 || ! CR_REGNO_P (REGNO (src_reg)))
1094 if (GET_CODE (exp) != SET
1095 || GET_CODE (SET_DEST (exp)) != REG
1096 || GET_MODE (SET_DEST (exp)) != SImode
1097 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1099 unspec = SET_SRC (exp);
1100 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1102 if (GET_CODE (unspec) != UNSPEC
1103 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1104 || XVECLEN (unspec, 0) != 2
1105 || XVECEXP (unspec, 0, 0) != src_reg
1106 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1107 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1113 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1114 (define_predicate "mtcrf_operation"
1115 (match_code "parallel")
1117 int count = XVECLEN (op, 0);
1121 /* Perform a quick check so we don't blow up below. */
1123 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1124 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1125 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1127 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1129 if (GET_CODE (src_reg) != REG
1130 || GET_MODE (src_reg) != SImode
1131 || ! INT_REGNO_P (REGNO (src_reg)))
1134 for (i = 0; i < count; i++)
1136 rtx exp = XVECEXP (op, 0, i);
1140 if (GET_CODE (exp) != SET
1141 || GET_CODE (SET_DEST (exp)) != REG
1142 || GET_MODE (SET_DEST (exp)) != CCmode
1143 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1145 unspec = SET_SRC (exp);
1146 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1148 if (GET_CODE (unspec) != UNSPEC
1149 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1150 || XVECLEN (unspec, 0) != 2
1151 || XVECEXP (unspec, 0, 0) != src_reg
1152 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1153 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1159 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1160 (define_predicate "lmw_operation"
1161 (match_code "parallel")
1163 int count = XVECLEN (op, 0);
1164 unsigned int dest_regno;
1166 unsigned int base_regno;
1167 HOST_WIDE_INT offset;
1170 /* Perform a quick check so we don't blow up below. */
1172 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1173 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1174 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1177 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1178 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1181 || count != 32 - (int) dest_regno)
1184 if (legitimate_indirect_address_p (src_addr, 0))
1187 base_regno = REGNO (src_addr);
1188 if (base_regno == 0)
1191 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
1193 offset = INTVAL (XEXP (src_addr, 1));
1194 base_regno = REGNO (XEXP (src_addr, 0));
1199 for (i = 0; i < count; i++)
1201 rtx elt = XVECEXP (op, 0, i);
1204 HOST_WIDE_INT newoffset;
1206 if (GET_CODE (elt) != SET
1207 || GET_CODE (SET_DEST (elt)) != REG
1208 || GET_MODE (SET_DEST (elt)) != SImode
1209 || REGNO (SET_DEST (elt)) != dest_regno + i
1210 || GET_CODE (SET_SRC (elt)) != MEM
1211 || GET_MODE (SET_SRC (elt)) != SImode)
1213 newaddr = XEXP (SET_SRC (elt), 0);
1214 if (legitimate_indirect_address_p (newaddr, 0))
1219 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1221 addr_reg = XEXP (newaddr, 0);
1222 newoffset = INTVAL (XEXP (newaddr, 1));
1226 if (REGNO (addr_reg) != base_regno
1227 || newoffset != offset + 4 * i)
1234 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1235 (define_predicate "stmw_operation"
1236 (match_code "parallel")
1238 int count = XVECLEN (op, 0);
1239 unsigned int src_regno;
1241 unsigned int base_regno;
1242 HOST_WIDE_INT offset;
1245 /* Perform a quick check so we don't blow up below. */
1247 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1248 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1249 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1252 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1253 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1256 || count != 32 - (int) src_regno)
1259 if (legitimate_indirect_address_p (dest_addr, 0))
1262 base_regno = REGNO (dest_addr);
1263 if (base_regno == 0)
1266 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
1268 offset = INTVAL (XEXP (dest_addr, 1));
1269 base_regno = REGNO (XEXP (dest_addr, 0));
1274 for (i = 0; i < count; i++)
1276 rtx elt = XVECEXP (op, 0, i);
1279 HOST_WIDE_INT newoffset;
1281 if (GET_CODE (elt) != SET
1282 || GET_CODE (SET_SRC (elt)) != REG
1283 || GET_MODE (SET_SRC (elt)) != SImode
1284 || REGNO (SET_SRC (elt)) != src_regno + i
1285 || GET_CODE (SET_DEST (elt)) != MEM
1286 || GET_MODE (SET_DEST (elt)) != SImode)
1288 newaddr = XEXP (SET_DEST (elt), 0);
1289 if (legitimate_indirect_address_p (newaddr, 0))
1294 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1296 addr_reg = XEXP (newaddr, 0);
1297 newoffset = INTVAL (XEXP (newaddr, 1));
1301 if (REGNO (addr_reg) != base_regno
1302 || newoffset != offset + 4 * i)