| blob | 59bb481eba54523862071c27789512778ceac76b |
1 ;; AltiVec patterns.
2 ;; Copyright (C) 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 2, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to the
19 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 ;; MA 02110-1301, USA.
22 (define_constants
23 [(UNSPEC_VCMPBFP 50)
24 (UNSPEC_VCMPEQUB 51)
25 (UNSPEC_VCMPEQUH 52)
26 (UNSPEC_VCMPEQUW 53)
27 (UNSPEC_VCMPEQFP 54)
28 (UNSPEC_VCMPGEFP 55)
29 (UNSPEC_VCMPGTUB 56)
30 (UNSPEC_VCMPGTSB 57)
31 (UNSPEC_VCMPGTUH 58)
32 (UNSPEC_VCMPGTSH 59)
33 (UNSPEC_VCMPGTUW 60)
34 (UNSPEC_VCMPGTSW 61)
35 (UNSPEC_VCMPGTFP 62)
36 (UNSPEC_VMSUMU 65)
37 (UNSPEC_VMSUMM 66)
38 (UNSPEC_VMSUMSHM 68)
39 (UNSPEC_VMSUMUHS 69)
40 (UNSPEC_VMSUMSHS 70)
41 (UNSPEC_VMHADDSHS 71)
42 (UNSPEC_VMHRADDSHS 72)
43 (UNSPEC_VMLADDUHM 73)
44 (UNSPEC_VADDCUW 75)
45 (UNSPEC_VADDU 76)
46 (UNSPEC_VADDS 77)
47 (UNSPEC_VAVGU 80)
48 (UNSPEC_VAVGS 81)
49 (UNSPEC_VMULEUB 83)
50 (UNSPEC_VMULESB 84)
51 (UNSPEC_VMULEUH 85)
52 (UNSPEC_VMULESH 86)
53 (UNSPEC_VMULOUB 87)
54 (UNSPEC_VMULOSB 88)
55 (UNSPEC_VMULOUH 89)
56 (UNSPEC_VMULOSH 90)
57 (UNSPEC_VPKUHUM 93)
58 (UNSPEC_VPKUWUM 94)
59 (UNSPEC_VPKPX 95)
60 (UNSPEC_VPKSHSS 97)
61 (UNSPEC_VPKSWSS 99)
62 (UNSPEC_VPKUHUS 100)
63 (UNSPEC_VPKSHUS 101)
64 (UNSPEC_VPKUWUS 102)
65 (UNSPEC_VPKSWUS 103)
66 (UNSPEC_VRL 104)
67 (UNSPEC_VSL 107)
68 (UNSPEC_VSLV4SI 110)
69 (UNSPEC_VSLO 111)
70 (UNSPEC_VSR 118)
71 (UNSPEC_VSRO 119)
72 (UNSPEC_VSUBCUW 124)
73 (UNSPEC_VSUBU 125)
74 (UNSPEC_VSUBS 126)
75 (UNSPEC_VSUM4UBS 131)
76 (UNSPEC_VSUM4S 132)
77 (UNSPEC_VSUM2SWS 134)
78 (UNSPEC_VSUMSWS 135)
79 (UNSPEC_VPERM 144)
80 (UNSPEC_VRFIP 148)
81 (UNSPEC_VRFIN 149)
82 (UNSPEC_VRFIM 150)
83 (UNSPEC_VCFUX 151)
84 (UNSPEC_VCFSX 152)
85 (UNSPEC_VCTUXS 153)
86 (UNSPEC_VCTSXS 154)
87 (UNSPEC_VLOGEFP 155)
88 (UNSPEC_VEXPTEFP 156)
89 (UNSPEC_VRSQRTEFP 157)
90 (UNSPEC_VREFP 158)
91 (UNSPEC_VSEL4SI 159)
92 (UNSPEC_VSEL4SF 160)
93 (UNSPEC_VSEL8HI 161)
94 (UNSPEC_VSEL16QI 162)
95 (UNSPEC_VLSDOI 163)
96 (UNSPEC_VUPKHSB 167)
97 (UNSPEC_VUPKHPX 168)
98 (UNSPEC_VUPKHSH 169)
99 (UNSPEC_VUPKLSB 170)
100 (UNSPEC_VUPKLPX 171)
101 (UNSPEC_VUPKLSH 172)
102 (UNSPEC_PREDICATE 173)
103 (UNSPEC_DST 190)
104 (UNSPEC_DSTT 191)
105 (UNSPEC_DSTST 192)
106 (UNSPEC_DSTSTT 193)
107 (UNSPEC_LVSL 194)
108 (UNSPEC_LVSR 195)
109 (UNSPEC_LVE 196)
110 (UNSPEC_STVX 201)
111 (UNSPEC_STVXL 202)
112 (UNSPEC_STVE 203)
113 (UNSPEC_SET_VSCR 213)
114 (UNSPEC_GET_VRSAVE 214)
115 (UNSPEC_REALIGN_LOAD 215)
116 (UNSPEC_REDUC_PLUS 217)
117 (UNSPEC_VECSH 219)
118 (UNSPEC_EXTEVEN_V4SI 220)
119 (UNSPEC_EXTEVEN_V8HI 221)
120 (UNSPEC_EXTEVEN_V16QI 222)
121 (UNSPEC_EXTEVEN_V4SF 223)
122 (UNSPEC_EXTODD_V4SI 224)
123 (UNSPEC_EXTODD_V8HI 225)
124 (UNSPEC_EXTODD_V16QI 226)
125 (UNSPEC_EXTODD_V4SF 227)
126 (UNSPEC_INTERHI_V4SI 228)
127 (UNSPEC_INTERHI_V8HI 229)
128 (UNSPEC_INTERHI_V16QI 230)
129 (UNSPEC_INTERHI_V4SF 231)
130 (UNSPEC_INTERLO_V4SI 232)
131 (UNSPEC_INTERLO_V8HI 233)
132 (UNSPEC_INTERLO_V16QI 234)
133 (UNSPEC_INTERLO_V4SF 235)
134 (UNSPEC_VMULWHUB 308)
135 (UNSPEC_VMULWLUB 309)
136 (UNSPEC_VMULWHSB 310)
137 (UNSPEC_VMULWLSB 311)
138 (UNSPEC_VMULWHUH 312)
139 (UNSPEC_VMULWLUH 313)
140 (UNSPEC_VMULWHSH 314)
141 (UNSPEC_VMULWLSH 315)
142 (UNSPEC_VUPKHUB 316)
143 (UNSPEC_VUPKHUH 317)
144 (UNSPEC_VUPKLUB 318)
145 (UNSPEC_VUPKLUH 319)
146 (UNSPEC_VPERMSI 320)
147 (UNSPEC_VPERMHI 321)
148 (UNSPEC_INTERHI 322)
149 (UNSPEC_INTERLO 323)
150 ])
152 (define_constants
153 [(UNSPECV_SET_VRSAVE 30)
154 (UNSPECV_MTVSCR 186)
155 (UNSPECV_MFVSCR 187)
156 (UNSPECV_DSSALL 188)
157 (UNSPECV_DSS 189)
158 ])
160 ;; Vec int modes
161 (define_mode_macro VI [V4SI V8HI V16QI])
162 ;; Short vec in modes
163 (define_mode_macro VIshort [V8HI V16QI])
164 ;; Vec float modes
165 (define_mode_macro VF [V4SF])
166 ;; Vec modes, pity mode macros are not composable
167 (define_mode_macro V [V4SI V8HI V16QI V4SF])
169 (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
171 ;; Generic LVX load instruction.
172 (define_insn "altivec_lvx_<mode>"
173 [(set (match_operand:V 0 "altivec_register_operand" "=v")
174 (match_operand:V 1 "memory_operand" "Z"))]
175 "TARGET_ALTIVEC"
176 "lvx %0,%y1"
177 [(set_attr "type" "vecload")])
179 ;; Generic STVX store instruction.
180 (define_insn "altivec_stvx_<mode>"
181 [(set (match_operand:V 0 "memory_operand" "=Z")
182 (match_operand:V 1 "altivec_register_operand" "v"))]
183 "TARGET_ALTIVEC"
184 "stvx %1,%y0"
185 [(set_attr "type" "vecstore")])
187 ;; Vector move instructions.
188 (define_expand "mov<mode>"
189 [(set (match_operand:V 0 "nonimmediate_operand" "")
190 (match_operand:V 1 "any_operand" ""))]
191 "TARGET_ALTIVEC"
192 {
193 rs6000_emit_move (operands[0], operands[1], <MODE>mode);
194 DONE;
195 })
197 (define_insn "*mov<mode>_internal"
198 [(set (match_operand:V 0 "nonimmediate_operand" "=Z,v,v,o,r,r,v")
199 (match_operand:V 1 "input_operand" "v,Z,v,r,o,r,W"))]
200 "TARGET_ALTIVEC
201 && (register_operand (operands[0], <MODE>mode)
202 || register_operand (operands[1], <MODE>mode))"
203 {
204 switch (which_alternative)
205 {
206 case 0: return "stvx %1,%y0";
207 case 1: return "lvx %0,%y1";
208 case 2: return "vor %0,%1,%1";
209 case 3: return "#";
210 case 4: return "#";
211 case 5: return "#";
212 case 6: return output_vec_const_move (operands);
213 default: gcc_unreachable ();
214 }
215 }
216 [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
218 (define_split
219 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
220 (match_operand:V4SI 1 "input_operand" ""))]
221 "TARGET_ALTIVEC && reload_completed
222 && gpr_or_gpr_p (operands[0], operands[1])"
223 [(pc)]
224 {
225 rs6000_split_multireg_move (operands[0], operands[1]); DONE;
226 })
228 (define_split
229 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
230 (match_operand:V8HI 1 "input_operand" ""))]
231 "TARGET_ALTIVEC && reload_completed
232 && gpr_or_gpr_p (operands[0], operands[1])"
233 [(pc)]
234 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
236 (define_split
237 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
238 (match_operand:V16QI 1 "input_operand" ""))]
239 "TARGET_ALTIVEC && reload_completed
240 && gpr_or_gpr_p (operands[0], operands[1])"
241 [(pc)]
242 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
244 (define_split
245 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
246 (match_operand:V4SF 1 "input_operand" ""))]
247 "TARGET_ALTIVEC && reload_completed
248 && gpr_or_gpr_p (operands[0], operands[1])"
249 [(pc)]
250 {
251 rs6000_split_multireg_move (operands[0], operands[1]); DONE;
252 })
254 (define_split
255 [(set (match_operand:VI 0 "altivec_register_operand" "")
256 (match_operand:VI 1 "easy_vector_constant_add_self" ""))]
257 "TARGET_ALTIVEC && reload_completed"
258 [(set (match_dup 0) (match_dup 3))
259 (set (match_dup 0) (plus:VI (match_dup 0)
260 (match_dup 0)))]
261 {
262 rtx dup = gen_easy_altivec_constant (operands[1]);
263 rtx const_vec;
265 /* Divide the operand of the resulting VEC_DUPLICATE, and use
266 simplify_rtx to make a CONST_VECTOR. */
267 XEXP (dup, 0) = simplify_const_binary_operation (ASHIFTRT, QImode,
268 XEXP (dup, 0), const1_rtx);
269 const_vec = simplify_rtx (dup);
271 if (GET_MODE (const_vec) == <MODE>mode)
272 operands[3] = const_vec;
273 else
274 operands[3] = gen_lowpart (<MODE>mode, const_vec);
275 })
277 (define_insn "get_vrsave_internal"
278 [(set (match_operand:SI 0 "register_operand" "=r")
279 (unspec:SI [(reg:SI 109)] UNSPEC_GET_VRSAVE))]
280 "TARGET_ALTIVEC"
281 {
282 if (TARGET_MACHO)
283 return "mfspr %0,256";
284 else
285 return "mfvrsave %0";
286 }
287 [(set_attr "type" "*")])
289 (define_insn "*set_vrsave_internal"
290 [(match_parallel 0 "vrsave_operation"
291 [(set (reg:SI 109)
292 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
293 (reg:SI 109)] UNSPECV_SET_VRSAVE))])]
294 "TARGET_ALTIVEC"
295 {
296 if (TARGET_MACHO)
297 return "mtspr 256,%1";
298 else
299 return "mtvrsave %1";
300 }
301 [(set_attr "type" "*")])
303 (define_insn "*save_world"
304 [(match_parallel 0 "save_world_operation"
305 [(clobber (reg:SI 65))
306 (use (match_operand:SI 1 "call_operand" "s"))])]
307 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
308 "bl %z1"
309 [(set_attr "type" "branch")
310 (set_attr "length" "4")])
312 (define_insn "*restore_world"
313 [(match_parallel 0 "restore_world_operation"
314 [(return)
315 (use (reg:SI 65))
316 (use (match_operand:SI 1 "call_operand" "s"))
317 (clobber (match_operand:SI 2 "gpc_reg_operand" "=r"))])]
318 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
319 "b %z1")
321 ;; Simple binary operations.
323 ;; add
324 (define_insn "add<mode>3"
325 [(set (match_operand:VI 0 "register_operand" "=v")
326 (plus:VI (match_operand:VI 1 "register_operand" "v")
327 (match_operand:VI 2 "register_operand" "v")))]
328 "TARGET_ALTIVEC"
329 "vaddu<VI_char>m %0,%1,%2"
330 [(set_attr "type" "vecsimple")])
332 (define_insn "addv4sf3"
333 [(set (match_operand:V4SF 0 "register_operand" "=v")
334 (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
335 (match_operand:V4SF 2 "register_operand" "v")))]
336 "TARGET_ALTIVEC"
337 "vaddfp %0,%1,%2"
338 [(set_attr "type" "vecfloat")])
340 (define_insn "altivec_vaddcuw"
341 [(set (match_operand:V4SI 0 "register_operand" "=v")
342 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
343 (match_operand:V4SI 2 "register_operand" "v")]
344 UNSPEC_VADDCUW))]
345 "TARGET_ALTIVEC"
346 "vaddcuw %0,%1,%2"
347 [(set_attr "type" "vecsimple")])
349 (define_insn "altivec_vaddu<VI_char>s"
350 [(set (match_operand:VI 0 "register_operand" "=v")
351 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
352 (match_operand:VI 2 "register_operand" "v")]
353 UNSPEC_VADDU))
354 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
355 "TARGET_ALTIVEC"
356 "vaddu<VI_char>s %0,%1,%2"
357 [(set_attr "type" "vecsimple")])
359 (define_insn "altivec_vadds<VI_char>s"
360 [(set (match_operand:VI 0 "register_operand" "=v")
361 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
362 (match_operand:VI 2 "register_operand" "v")]
363 UNSPEC_VADDS))
364 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
365 "TARGET_ALTIVEC"
366 "vadds<VI_char>s %0,%1,%2"
367 [(set_attr "type" "vecsimple")])
369 ;; sub
370 (define_insn "sub<mode>3"
371 [(set (match_operand:VI 0 "register_operand" "=v")
372 (minus:VI (match_operand:VI 1 "register_operand" "v")
373 (match_operand:VI 2 "register_operand" "v")))]
374 "TARGET_ALTIVEC"
375 "vsubu<VI_char>m %0,%1,%2"
376 [(set_attr "type" "vecsimple")])
378 (define_insn "subv4sf3"
379 [(set (match_operand:V4SF 0 "register_operand" "=v")
380 (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
381 (match_operand:V4SF 2 "register_operand" "v")))]
382 "TARGET_ALTIVEC"
383 "vsubfp %0,%1,%2"
384 [(set_attr "type" "vecfloat")])
386 (define_insn "altivec_vsubcuw"
387 [(set (match_operand:V4SI 0 "register_operand" "=v")
388 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
389 (match_operand:V4SI 2 "register_operand" "v")]
390 UNSPEC_VSUBCUW))]
391 "TARGET_ALTIVEC"
392 "vsubcuw %0,%1,%2"
393 [(set_attr "type" "vecsimple")])
395 (define_insn "altivec_vsubu<VI_char>s"
396 [(set (match_operand:VI 0 "register_operand" "=v")
397 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
398 (match_operand:VI 2 "register_operand" "v")]
399 UNSPEC_VSUBU))
400 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
401 "TARGET_ALTIVEC"
402 "vsubu<VI_char>s %0,%1,%2"
403 [(set_attr "type" "vecsimple")])
405 (define_insn "altivec_vsubs<VI_char>s"
406 [(set (match_operand:VI 0 "register_operand" "=v")
407 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
408 (match_operand:VI 2 "register_operand" "v")]
409 UNSPEC_VSUBS))
410 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
411 "TARGET_ALTIVEC"
412 "vsubs<VI_char>s %0,%1,%2"
413 [(set_attr "type" "vecsimple")])
415 ;;
416 (define_insn "altivec_vavgu<VI_char>"
417 [(set (match_operand:VI 0 "register_operand" "=v")
418 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
419 (match_operand:VI 2 "register_operand" "v")]
420 UNSPEC_VAVGU))]
421 "TARGET_ALTIVEC"
422 "vavgu<VI_char> %0,%1,%2"
423 [(set_attr "type" "vecsimple")])
425 (define_insn "altivec_vavgs<VI_char>"
426 [(set (match_operand:VI 0 "register_operand" "=v")
427 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
428 (match_operand:VI 2 "register_operand" "v")]
429 UNSPEC_VAVGS))]
430 "TARGET_ALTIVEC"
431 "vavgs<VI_char> %0,%1,%2"
432 [(set_attr "type" "vecsimple")])
434 (define_insn "altivec_vcmpbfp"
435 [(set (match_operand:V4SI 0 "register_operand" "=v")
436 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
437 (match_operand:V4SF 2 "register_operand" "v")]
438 UNSPEC_VCMPBFP))]
439 "TARGET_ALTIVEC"
440 "vcmpbfp %0,%1,%2"
441 [(set_attr "type" "veccmp")])
443 (define_insn "altivec_vcmpequb"
444 [(set (match_operand:V16QI 0 "register_operand" "=v")
445 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
446 (match_operand:V16QI 2 "register_operand" "v")]
447 UNSPEC_VCMPEQUB))]
448 "TARGET_ALTIVEC"
449 "vcmpequb %0,%1,%2"
450 [(set_attr "type" "vecsimple")])
452 (define_insn "altivec_vcmpequh"
453 [(set (match_operand:V8HI 0 "register_operand" "=v")
454 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
455 (match_operand:V8HI 2 "register_operand" "v")]
456 UNSPEC_VCMPEQUH))]
457 "TARGET_ALTIVEC"
458 "vcmpequh %0,%1,%2"
459 [(set_attr "type" "vecsimple")])
461 (define_insn "altivec_vcmpequw"
462 [(set (match_operand:V4SI 0 "register_operand" "=v")
463 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
464 (match_operand:V4SI 2 "register_operand" "v")]
465 UNSPEC_VCMPEQUW))]
466 "TARGET_ALTIVEC"
467 "vcmpequw %0,%1,%2"
468 [(set_attr "type" "vecsimple")])
470 (define_insn "altivec_vcmpeqfp"
471 [(set (match_operand:V4SI 0 "register_operand" "=v")
472 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
473 (match_operand:V4SF 2 "register_operand" "v")]
474 UNSPEC_VCMPEQFP))]
475 "TARGET_ALTIVEC"
476 "vcmpeqfp %0,%1,%2"
477 [(set_attr "type" "veccmp")])
479 (define_insn "altivec_vcmpgefp"
480 [(set (match_operand:V4SI 0 "register_operand" "=v")
481 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
482 (match_operand:V4SF 2 "register_operand" "v")]
483 UNSPEC_VCMPGEFP))]
484 "TARGET_ALTIVEC"
485 "vcmpgefp %0,%1,%2"
486 [(set_attr "type" "veccmp")])
488 (define_insn "altivec_vcmpgtub"
489 [(set (match_operand:V16QI 0 "register_operand" "=v")
490 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
491 (match_operand:V16QI 2 "register_operand" "v")]
492 UNSPEC_VCMPGTUB))]
493 "TARGET_ALTIVEC"
494 "vcmpgtub %0,%1,%2"
495 [(set_attr "type" "vecsimple")])
497 (define_insn "altivec_vcmpgtsb"
498 [(set (match_operand:V16QI 0 "register_operand" "=v")
499 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
500 (match_operand:V16QI 2 "register_operand" "v")]
501 UNSPEC_VCMPGTSB))]
502 "TARGET_ALTIVEC"
503 "vcmpgtsb %0,%1,%2"
504 [(set_attr "type" "vecsimple")])
506 (define_insn "altivec_vcmpgtuh"
507 [(set (match_operand:V8HI 0 "register_operand" "=v")
508 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
509 (match_operand:V8HI 2 "register_operand" "v")]
510 UNSPEC_VCMPGTUH))]
511 "TARGET_ALTIVEC"
512 "vcmpgtuh %0,%1,%2"
513 [(set_attr "type" "vecsimple")])
515 (define_insn "altivec_vcmpgtsh"
516 [(set (match_operand:V8HI 0 "register_operand" "=v")
517 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
518 (match_operand:V8HI 2 "register_operand" "v")]
519 UNSPEC_VCMPGTSH))]
520 "TARGET_ALTIVEC"
521 "vcmpgtsh %0,%1,%2"
522 [(set_attr "type" "vecsimple")])
524 (define_insn "altivec_vcmpgtuw"
525 [(set (match_operand:V4SI 0 "register_operand" "=v")
526 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
527 (match_operand:V4SI 2 "register_operand" "v")]
528 UNSPEC_VCMPGTUW))]
529 "TARGET_ALTIVEC"
530 "vcmpgtuw %0,%1,%2"
531 [(set_attr "type" "vecsimple")])
533 (define_insn "altivec_vcmpgtsw"
534 [(set (match_operand:V4SI 0 "register_operand" "=v")
535 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
536 (match_operand:V4SI 2 "register_operand" "v")]
537 UNSPEC_VCMPGTSW))]
538 "TARGET_ALTIVEC"
539 "vcmpgtsw %0,%1,%2"
540 [(set_attr "type" "vecsimple")])
542 (define_insn "altivec_vcmpgtfp"
543 [(set (match_operand:V4SI 0 "register_operand" "=v")
544 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
545 (match_operand:V4SF 2 "register_operand" "v")]
546 UNSPEC_VCMPGTFP))]
547 "TARGET_ALTIVEC"
548 "vcmpgtfp %0,%1,%2"
549 [(set_attr "type" "veccmp")])
551 ;; Fused multiply add
552 (define_insn "altivec_vmaddfp"
553 [(set (match_operand:V4SF 0 "register_operand" "=v")
554 (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
555 (match_operand:V4SF 2 "register_operand" "v"))
556 (match_operand:V4SF 3 "register_operand" "v")))]
557 "TARGET_ALTIVEC"
558 "vmaddfp %0,%1,%2,%3"
559 [(set_attr "type" "vecfloat")])
561 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
563 (define_expand "mulv4sf3"
564 [(use (match_operand:V4SF 0 "register_operand" ""))
565 (use (match_operand:V4SF 1 "register_operand" ""))
566 (use (match_operand:V4SF 2 "register_operand" ""))]
567 "TARGET_ALTIVEC && TARGET_FUSED_MADD"
568 "
569 {
570 rtx neg0;
572 /* Generate [-0.0, -0.0, -0.0, -0.0]. */
573 neg0 = gen_reg_rtx (V4SImode);
574 emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
575 emit_insn (gen_altivec_vslw (neg0, neg0, neg0));
577 /* Use the multiply-add. */
578 emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
579 gen_lowpart (V4SFmode, neg0)));
580 DONE;
581 }")
583 ;; 32-bit integer multiplication
584 ;; A_high = Operand_0 & 0xFFFF0000 >> 16
585 ;; A_low = Operand_0 & 0xFFFF
586 ;; B_high = Operand_1 & 0xFFFF0000 >> 16
587 ;; B_low = Operand_1 & 0xFFFF
588 ;; result = A_low * B_low + (A_high * B_low + B_high * A_low) << 16
590 ;; (define_insn "mulv4si3"
591 ;; [(set (match_operand:V4SI 0 "register_operand" "=v")
592 ;; (mult:V4SI (match_operand:V4SI 1 "register_operand" "v")
593 ;; (match_operand:V4SI 2 "register_operand" "v")))]
594 (define_expand "mulv4si3"
595 [(use (match_operand:V4SI 0 "register_operand" ""))
596 (use (match_operand:V4SI 1 "register_operand" ""))
597 (use (match_operand:V4SI 2 "register_operand" ""))]
598 "TARGET_ALTIVEC"
599 "
600 {
601 rtx zero;
602 rtx swap;
603 rtx small_swap;
604 rtx sixteen;
605 rtx one;
606 rtx two;
607 rtx low_product;
608 rtx high_product;
610 zero = gen_reg_rtx (V4SImode);
611 emit_insn (gen_altivec_vspltisw (zero, const0_rtx));
613 sixteen = gen_reg_rtx (V4SImode);
614 emit_insn (gen_altivec_vspltisw (sixteen, gen_rtx_CONST_INT (V4SImode, -16)));
616 swap = gen_reg_rtx (V4SImode);
617 emit_insn (gen_altivec_vrlw (swap, operands[2], sixteen));
619 one = gen_reg_rtx (V8HImode);
620 convert_move (one, operands[1], 0);
622 two = gen_reg_rtx (V8HImode);
623 convert_move (two, operands[2], 0);
625 small_swap = gen_reg_rtx (V8HImode);
626 convert_move (small_swap, swap, 0);
628 low_product = gen_reg_rtx (V4SImode);
629 emit_insn (gen_altivec_vmulouh (low_product, one, two));
631 high_product = gen_reg_rtx (V4SImode);
632 emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
634 emit_insn (gen_altivec_vslw (high_product, high_product, sixteen));
636 emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
638 DONE;
639 }")
642 ;; Fused multiply subtract
643 (define_insn "altivec_vnmsubfp"
644 [(set (match_operand:V4SF 0 "register_operand" "=v")
645 (neg:V4SF (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
646 (match_operand:V4SF 2 "register_operand" "v"))
647 (match_operand:V4SF 3 "register_operand" "v"))))]
648 "TARGET_ALTIVEC"
649 "vnmsubfp %0,%1,%2,%3"
650 [(set_attr "type" "vecfloat")])
652 (define_insn "altivec_vmsumu<VI_char>m"
653 [(set (match_operand:V4SI 0 "register_operand" "=v")
654 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
655 (match_operand:VIshort 2 "register_operand" "v")
656 (match_operand:V4SI 3 "register_operand" "v")]
657 UNSPEC_VMSUMU))]
658 "TARGET_ALTIVEC"
659 "vmsumu<VI_char>m %0,%1,%2,%3"
660 [(set_attr "type" "veccomplex")])
662 (define_insn "altivec_vmsumm<VI_char>m"
663 [(set (match_operand:V4SI 0 "register_operand" "=v")
664 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
665 (match_operand:VIshort 2 "register_operand" "v")
666 (match_operand:V4SI 3 "register_operand" "v")]
667 UNSPEC_VMSUMM))]
668 "TARGET_ALTIVEC"
669 "vmsumm<VI_char>m %0,%1,%2,%3"
670 [(set_attr "type" "veccomplex")])
672 (define_insn "altivec_vmsumshm"
673 [(set (match_operand:V4SI 0 "register_operand" "=v")
674 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
675 (match_operand:V8HI 2 "register_operand" "v")
676 (match_operand:V4SI 3 "register_operand" "v")]
677 UNSPEC_VMSUMSHM))]
678 "TARGET_ALTIVEC"
679 "vmsumshm %0,%1,%2,%3"
680 [(set_attr "type" "veccomplex")])
682 (define_insn "altivec_vmsumuhs"
683 [(set (match_operand:V4SI 0 "register_operand" "=v")
684 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
685 (match_operand:V8HI 2 "register_operand" "v")
686 (match_operand:V4SI 3 "register_operand" "v")]
687 UNSPEC_VMSUMUHS))
688 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
689 "TARGET_ALTIVEC"
690 "vmsumuhs %0,%1,%2,%3"
691 [(set_attr "type" "veccomplex")])
693 (define_insn "altivec_vmsumshs"
694 [(set (match_operand:V4SI 0 "register_operand" "=v")
695 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
696 (match_operand:V8HI 2 "register_operand" "v")
697 (match_operand:V4SI 3 "register_operand" "v")]
698 UNSPEC_VMSUMSHS))
699 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
700 "TARGET_ALTIVEC"
701 "vmsumshs %0,%1,%2,%3"
702 [(set_attr "type" "veccomplex")])
704 ;; max
706 (define_insn "umax<mode>3"
707 [(set (match_operand:VI 0 "register_operand" "=v")
708 (umax:VI (match_operand:VI 1 "register_operand" "v")
709 (match_operand:VI 2 "register_operand" "v")))]
710 "TARGET_ALTIVEC"
711 "vmaxu<VI_char> %0,%1,%2"
712 [(set_attr "type" "vecsimple")])
714 (define_insn "smax<mode>3"
715 [(set (match_operand:VI 0 "register_operand" "=v")
716 (smax:VI (match_operand:VI 1 "register_operand" "v")
717 (match_operand:VI 2 "register_operand" "v")))]
718 "TARGET_ALTIVEC"
719 "vmaxs<VI_char> %0,%1,%2"
720 [(set_attr "type" "vecsimple")])
722 (define_insn "smaxv4sf3"
723 [(set (match_operand:V4SF 0 "register_operand" "=v")
724 (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
725 (match_operand:V4SF 2 "register_operand" "v")))]
726 "TARGET_ALTIVEC"
727 "vmaxfp %0,%1,%2"
728 [(set_attr "type" "veccmp")])
730 (define_insn "umin<mode>3"
731 [(set (match_operand:VI 0 "register_operand" "=v")
732 (umin:VI (match_operand:VI 1 "register_operand" "v")
733 (match_operand:VI 2 "register_operand" "v")))]
734 "TARGET_ALTIVEC"
735 "vminu<VI_char> %0,%1,%2"
736 [(set_attr "type" "vecsimple")])
738 (define_insn "smin<mode>3"
739 [(set (match_operand:VI 0 "register_operand" "=v")
740 (smin:VI (match_operand:VI 1 "register_operand" "v")
741 (match_operand:VI 2 "register_operand" "v")))]
742 "TARGET_ALTIVEC"
743 "vmins<VI_char> %0,%1,%2"
744 [(set_attr "type" "vecsimple")])
746 (define_insn "sminv4sf3"
747 [(set (match_operand:V4SF 0 "register_operand" "=v")
748 (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
749 (match_operand:V4SF 2 "register_operand" "v")))]
750 "TARGET_ALTIVEC"
751 "vminfp %0,%1,%2"
752 [(set_attr "type" "veccmp")])
754 (define_insn "altivec_vmhaddshs"
755 [(set (match_operand:V8HI 0 "register_operand" "=v")
756 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
757 (match_operand:V8HI 2 "register_operand" "v")
758 (match_operand:V8HI 3 "register_operand" "v")]
759 UNSPEC_VMHADDSHS))
760 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
761 "TARGET_ALTIVEC"
762 "vmhaddshs %0,%1,%2,%3"
763 [(set_attr "type" "veccomplex")])
765 (define_insn "altivec_vmhraddshs"
766 [(set (match_operand:V8HI 0 "register_operand" "=v")
767 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
768 (match_operand:V8HI 2 "register_operand" "v")
769 (match_operand:V8HI 3 "register_operand" "v")]
770 UNSPEC_VMHRADDSHS))
771 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
772 "TARGET_ALTIVEC"
773 "vmhraddshs %0,%1,%2,%3"
774 [(set_attr "type" "veccomplex")])
776 (define_insn "altivec_vmladduhm"
777 [(set (match_operand:V8HI 0 "register_operand" "=v")
778 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
779 (match_operand:V8HI 2 "register_operand" "v")
780 (match_operand:V8HI 3 "register_operand" "v")]
781 UNSPEC_VMLADDUHM))]
782 "TARGET_ALTIVEC"
783 "vmladduhm %0,%1,%2,%3"
784 [(set_attr "type" "veccomplex")])
786 (define_insn "altivec_vmrghb"
787 [(set (match_operand:V16QI 0 "register_operand" "=v")
788 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
789 (parallel [(const_int 0)
790 (const_int 8)
791 (const_int 1)
792 (const_int 9)
793 (const_int 2)
794 (const_int 10)
795 (const_int 3)
796 (const_int 11)
797 (const_int 4)
798 (const_int 12)
799 (const_int 5)
800 (const_int 13)
801 (const_int 6)
802 (const_int 14)
803 (const_int 7)
804 (const_int 15)]))
805 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
806 (parallel [(const_int 8)
807 (const_int 0)
808 (const_int 9)
809 (const_int 1)
810 (const_int 10)
811 (const_int 2)
812 (const_int 11)
813 (const_int 3)
814 (const_int 12)
815 (const_int 4)
816 (const_int 13)
817 (const_int 5)
818 (const_int 14)
819 (const_int 6)
820 (const_int 15)
821 (const_int 7)]))
822 (const_int 21845)))]
823 "TARGET_ALTIVEC"
824 "vmrghb %0,%1,%2"
825 [(set_attr "type" "vecperm")])
827 (define_insn "altivec_vmrghh"
828 [(set (match_operand:V8HI 0 "register_operand" "=v")
829 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
830 (parallel [(const_int 0)
831 (const_int 4)
832 (const_int 1)
833 (const_int 5)
834 (const_int 2)
835 (const_int 6)
836 (const_int 3)
837 (const_int 7)]))
838 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
839 (parallel [(const_int 4)
840 (const_int 0)
841 (const_int 5)
842 (const_int 1)
843 (const_int 6)
844 (const_int 2)
845 (const_int 7)
846 (const_int 3)]))
847 (const_int 85)))]
848 "TARGET_ALTIVEC"
849 "vmrghh %0,%1,%2"
850 [(set_attr "type" "vecperm")])
852 (define_insn "altivec_vmrghw"
853 [(set (match_operand:V4SI 0 "register_operand" "=v")
854 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
855 (parallel [(const_int 0)
856 (const_int 2)
857 (const_int 1)
858 (const_int 3)]))
859 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
860 (parallel [(const_int 2)
861 (const_int 0)
862 (const_int 3)
863 (const_int 1)]))
864 (const_int 5)))]
865 "TARGET_ALTIVEC"
866 "vmrghw %0,%1,%2"
867 [(set_attr "type" "vecperm")])
869 (define_insn "altivec_vmrghsf"
870 [(set (match_operand:V4SF 0 "register_operand" "=v")
871 (vec_merge:V4SF (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "v")
872 (parallel [(const_int 0)
873 (const_int 2)
874 (const_int 1)
875 (const_int 3)]))
876 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "v")
877 (parallel [(const_int 2)
878 (const_int 0)
879 (const_int 3)
880 (const_int 1)]))
881 (const_int 5)))]
882 "TARGET_ALTIVEC"
883 "vmrghw %0,%1,%2"
884 [(set_attr "type" "vecperm")])
886 (define_insn "altivec_vmrglb"
887 [(set (match_operand:V16QI 0 "register_operand" "=v")
888 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
889 (parallel [(const_int 8)
890 (const_int 0)
891 (const_int 9)
892 (const_int 1)
893 (const_int 10)
894 (const_int 2)
895 (const_int 11)
896 (const_int 3)
897 (const_int 12)
898 (const_int 4)
899 (const_int 13)
900 (const_int 5)
901 (const_int 14)
902 (const_int 6)
903 (const_int 15)
904 (const_int 7)]))
905 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
906 (parallel [(const_int 0)
907 (const_int 8)
908 (const_int 1)
909 (const_int 9)
910 (const_int 2)
911 (const_int 10)
912 (const_int 3)
913 (const_int 11)
914 (const_int 4)
915 (const_int 12)
916 (const_int 5)
917 (const_int 13)
918 (const_int 6)
919 (const_int 14)
920 (const_int 7)
921 (const_int 15)]))
922 (const_int 21845)))]
923 "TARGET_ALTIVEC"
924 "vmrglb %0,%1,%2"
925 [(set_attr "type" "vecperm")])
927 (define_insn "altivec_vmrglh"
928 [(set (match_operand:V8HI 0 "register_operand" "=v")
929 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
930 (parallel [(const_int 4)
931 (const_int 0)
932 (const_int 5)
933 (const_int 1)
934 (const_int 6)
935 (const_int 2)
936 (const_int 7)
937 (const_int 3)]))
938 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
939 (parallel [(const_int 0)
940 (const_int 4)
941 (const_int 1)
942 (const_int 5)
943 (const_int 2)
944 (const_int 6)
945 (const_int 3)
946 (const_int 7)]))
947 (const_int 85)))]
948 "TARGET_ALTIVEC"
949 "vmrglh %0,%1,%2"
950 [(set_attr "type" "vecperm")])
952 (define_insn "altivec_vmrglw"
953 [(set (match_operand:V4SI 0 "register_operand" "=v")
954 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
955 (parallel [(const_int 2)
956 (const_int 0)
957 (const_int 3)
958 (const_int 1)]))
959 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
960 (parallel [(const_int 0)
961 (const_int 2)
962 (const_int 1)
963 (const_int 3)]))
964 (const_int 5)))]
965 "TARGET_ALTIVEC"
966 "vmrglw %0,%1,%2"
967 [(set_attr "type" "vecperm")])
969 (define_insn "altivec_vmrglsf"
970 [(set (match_operand:V4SF 0 "register_operand" "=v")
971 (vec_merge:V4SF (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "v")
972 (parallel [(const_int 2)
973 (const_int 0)
974 (const_int 3)
975 (const_int 1)]))
976 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "v")
977 (parallel [(const_int 0)
978 (const_int 2)
979 (const_int 1)
980 (const_int 3)]))
981 (const_int 5)))]
982 "TARGET_ALTIVEC"
983 "vmrglw %0,%1,%2"
984 [(set_attr "type" "vecperm")])
986 (define_insn "altivec_vmuleub"
987 [(set (match_operand:V8HI 0 "register_operand" "=v")
988 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
989 (match_operand:V16QI 2 "register_operand" "v")]
990 UNSPEC_VMULEUB))]
991 "TARGET_ALTIVEC"
992 "vmuleub %0,%1,%2"
993 [(set_attr "type" "veccomplex")])
995 (define_insn "altivec_vmulesb"
996 [(set (match_operand:V8HI 0 "register_operand" "=v")
997 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
998 (match_operand:V16QI 2 "register_operand" "v")]
999 UNSPEC_VMULESB))]
1000 "TARGET_ALTIVEC"
1001 "vmulesb %0,%1,%2"
1002 [(set_attr "type" "veccomplex")])
1004 (define_insn "altivec_vmuleuh"
1005 [(set (match_operand:V4SI 0 "register_operand" "=v")
1006 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1007 (match_operand:V8HI 2 "register_operand" "v")]
1008 UNSPEC_VMULEUH))]
1009 "TARGET_ALTIVEC"
1010 "vmuleuh %0,%1,%2"
1011 [(set_attr "type" "veccomplex")])
1013 (define_insn "altivec_vmulesh"
1014 [(set (match_operand:V4SI 0 "register_operand" "=v")
1015 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1016 (match_operand:V8HI 2 "register_operand" "v")]
1017 UNSPEC_VMULESH))]
1018 "TARGET_ALTIVEC"
1019 "vmulesh %0,%1,%2"
1020 [(set_attr "type" "veccomplex")])
1022 (define_insn "altivec_vmuloub"
1023 [(set (match_operand:V8HI 0 "register_operand" "=v")
1024 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1025 (match_operand:V16QI 2 "register_operand" "v")]
1026 UNSPEC_VMULOUB))]
1027 "TARGET_ALTIVEC"
1028 "vmuloub %0,%1,%2"
1029 [(set_attr "type" "veccomplex")])
1031 (define_insn "altivec_vmulosb"
1032 [(set (match_operand:V8HI 0 "register_operand" "=v")
1033 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1034 (match_operand:V16QI 2 "register_operand" "v")]
1035 UNSPEC_VMULOSB))]
1036 "TARGET_ALTIVEC"
1037 "vmulosb %0,%1,%2"
1038 [(set_attr "type" "veccomplex")])
1040 (define_insn "altivec_vmulouh"
1041 [(set (match_operand:V4SI 0 "register_operand" "=v")
1042 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1043 (match_operand:V8HI 2 "register_operand" "v")]
1044 UNSPEC_VMULOUH))]
1045 "TARGET_ALTIVEC"
1046 "vmulouh %0,%1,%2"
1047 [(set_attr "type" "veccomplex")])
1049 (define_insn "altivec_vmulosh"
1050 [(set (match_operand:V4SI 0 "register_operand" "=v")
1051 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1052 (match_operand:V8HI 2 "register_operand" "v")]
1053 UNSPEC_VMULOSH))]
1054 "TARGET_ALTIVEC"
1055 "vmulosh %0,%1,%2"
1056 [(set_attr "type" "veccomplex")])
1059 ;; logical ops
1061 (define_insn "and<mode>3"
1062 [(set (match_operand:VI 0 "register_operand" "=v")
1063 (and:VI (match_operand:VI 1 "register_operand" "v")
1064 (match_operand:VI 2 "register_operand" "v")))]
1065 "TARGET_ALTIVEC"
1066 "vand %0,%1,%2"
1067 [(set_attr "type" "vecsimple")])
1069 (define_insn "ior<mode>3"
1070 [(set (match_operand:VI 0 "register_operand" "=v")
1071 (ior:VI (match_operand:VI 1 "register_operand" "v")
1072 (match_operand:VI 2 "register_operand" "v")))]
1073 "TARGET_ALTIVEC"
1074 "vor %0,%1,%2"
1075 [(set_attr "type" "vecsimple")])
1077 (define_insn "xor<mode>3"
1078 [(set (match_operand:VI 0 "register_operand" "=v")
1079 (xor:VI (match_operand:VI 1 "register_operand" "v")
1080 (match_operand:VI 2 "register_operand" "v")))]
1081 "TARGET_ALTIVEC"
1082 "vxor %0,%1,%2"
1083 [(set_attr "type" "vecsimple")])
1085 (define_insn "xorv4sf3"
1086 [(set (match_operand:V4SF 0 "register_operand" "=v")
1087 (xor:V4SF (match_operand:V4SF 1 "register_operand" "v")
1088 (match_operand:V4SF 2 "register_operand" "v")))]
1089 "TARGET_ALTIVEC"
1090 "vxor %0,%1,%2"
1091 [(set_attr "type" "vecsimple")])
1093 (define_insn "one_cmpl<mode>2"
1094 [(set (match_operand:VI 0 "register_operand" "=v")
1095 (not:VI (match_operand:VI 1 "register_operand" "v")))]
1096 "TARGET_ALTIVEC"
1097 "vnor %0,%1,%1"
1098 [(set_attr "type" "vecsimple")])
1100 (define_insn "altivec_nor<mode>3"
1101 [(set (match_operand:VI 0 "register_operand" "=v")
1102 (not:VI (ior:VI (match_operand:VI 1 "register_operand" "v")
1103 (match_operand:VI 2 "register_operand" "v"))))]
1104 "TARGET_ALTIVEC"
1105 "vnor %0,%1,%2"
1106 [(set_attr "type" "vecsimple")])
1108 (define_insn "andc<mode>3"
1109 [(set (match_operand:VI 0 "register_operand" "=v")
1110 (and:VI (not:VI (match_operand:VI 2 "register_operand" "v"))
1111 (match_operand:VI 1 "register_operand" "v")))]
1112 "TARGET_ALTIVEC"
1113 "vandc %0,%1,%2"
1114 [(set_attr "type" "vecsimple")])
1116 (define_insn "*andc3_v4sf"
1117 [(set (match_operand:V4SF 0 "register_operand" "=v")
1118 (and:V4SF (not:V4SF (match_operand:V4SF 2 "register_operand" "v"))
1119 (match_operand:V4SF 1 "register_operand" "v")))]
1120 "TARGET_ALTIVEC"
1121 "vandc %0,%1,%2"
1122 [(set_attr "type" "vecsimple")])
1124 (define_insn "altivec_vpkuhum"
1125 [(set (match_operand:V16QI 0 "register_operand" "=v")
1126 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1127 (match_operand:V8HI 2 "register_operand" "v")]
1128 UNSPEC_VPKUHUM))]
1129 "TARGET_ALTIVEC"
1130 "vpkuhum %0,%1,%2"
1131 [(set_attr "type" "vecperm")])
1133 (define_insn "altivec_vpkuwum"
1134 [(set (match_operand:V8HI 0 "register_operand" "=v")
1135 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1136 (match_operand:V4SI 2 "register_operand" "v")]
1137 UNSPEC_VPKUWUM))]
1138 "TARGET_ALTIVEC"
1139 "vpkuwum %0,%1,%2"
1140 [(set_attr "type" "vecperm")])
1142 (define_insn "altivec_vpkpx"
1143 [(set (match_operand:V8HI 0 "register_operand" "=v")
1144 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1145 (match_operand:V4SI 2 "register_operand" "v")]
1146 UNSPEC_VPKPX))]
1147 "TARGET_ALTIVEC"
1148 "vpkpx %0,%1,%2"
1149 [(set_attr "type" "vecperm")])
1151 (define_insn "altivec_vpkshss"
1152 [(set (match_operand:V16QI 0 "register_operand" "=v")
1153 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1154 (match_operand:V8HI 2 "register_operand" "v")]
1155 UNSPEC_VPKSHSS))
1156 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1157 "TARGET_ALTIVEC"
1158 "vpkshss %0,%1,%2"
1159 [(set_attr "type" "vecperm")])
1161 (define_insn "altivec_vpkswss"
1162 [(set (match_operand:V8HI 0 "register_operand" "=v")
1163 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1164 (match_operand:V4SI 2 "register_operand" "v")]
1165 UNSPEC_VPKSWSS))
1166 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1167 "TARGET_ALTIVEC"
1168 "vpkswss %0,%1,%2"
1169 [(set_attr "type" "vecperm")])
1171 (define_insn "altivec_vpkuhus"
1172 [(set (match_operand:V16QI 0 "register_operand" "=v")
1173 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1174 (match_operand:V8HI 2 "register_operand" "v")]
1175 UNSPEC_VPKUHUS))
1176 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1177 "TARGET_ALTIVEC"
1178 "vpkuhus %0,%1,%2"
1179 [(set_attr "type" "vecperm")])
1181 (define_insn "altivec_vpkshus"
1182 [(set (match_operand:V16QI 0 "register_operand" "=v")
1183 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1184 (match_operand:V8HI 2 "register_operand" "v")]
1185 UNSPEC_VPKSHUS))
1186 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1187 "TARGET_ALTIVEC"
1188 "vpkshus %0,%1,%2"
1189 [(set_attr "type" "vecperm")])
1191 (define_insn "altivec_vpkuwus"
1192 [(set (match_operand:V8HI 0 "register_operand" "=v")
1193 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1194 (match_operand:V4SI 2 "register_operand" "v")]
1195 UNSPEC_VPKUWUS))
1196 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1197 "TARGET_ALTIVEC"
1198 "vpkuwus %0,%1,%2"
1199 [(set_attr "type" "vecperm")])
1201 (define_insn "altivec_vpkswus"
1202 [(set (match_operand:V8HI 0 "register_operand" "=v")
1203 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1204 (match_operand:V4SI 2 "register_operand" "v")]
1205 UNSPEC_VPKSWUS))
1206 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1207 "TARGET_ALTIVEC"
1208 "vpkswus %0,%1,%2"
1209 [(set_attr "type" "vecperm")])
1211 (define_insn "altivec_vrl<VI_char>"
1212 [(set (match_operand:VI 0 "register_operand" "=v")
1213 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1214 (match_operand:VI 2 "register_operand" "v")]
1215 UNSPEC_VRL))]
1216 "TARGET_ALTIVEC"
1217 "vrl<VI_char> %0,%1,%2"
1218 [(set_attr "type" "vecsimple")])
1220 (define_insn "altivec_vsl<VI_char>"
1221 [(set (match_operand:VI 0 "register_operand" "=v")
1222 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1223 (match_operand:VI 2 "register_operand" "v")]
1224 UNSPEC_VSL))]
1225 "TARGET_ALTIVEC"
1226 "vsl<VI_char> %0,%1,%2"
1227 [(set_attr "type" "vecsimple")])
1229 (define_insn "altivec_vsl"
1230 [(set (match_operand:V4SI 0 "register_operand" "=v")
1231 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1232 (match_operand:V4SI 2 "register_operand" "v")]
1233 UNSPEC_VSLV4SI))]
1234 "TARGET_ALTIVEC"
1235 "vsl %0,%1,%2"
1236 [(set_attr "type" "vecperm")])
1238 (define_insn "altivec_vslo"
1239 [(set (match_operand:V4SI 0 "register_operand" "=v")
1240 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1241 (match_operand:V4SI 2 "register_operand" "v")]
1242 UNSPEC_VSLO))]
1243 "TARGET_ALTIVEC"
1244 "vslo %0,%1,%2"
1245 [(set_attr "type" "vecperm")])
1247 (define_insn "lshr<mode>3"
1248 [(set (match_operand:VI 0 "register_operand" "=v")
1249 (lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
1250 (match_operand:VI 2 "register_operand" "v") ))]
1251 "TARGET_ALTIVEC"
1252 "vsr<VI_char> %0,%1,%2"
1253 [(set_attr "type" "vecsimple")])
1255 (define_insn "ashr<mode>3"
1256 [(set (match_operand:VI 0 "register_operand" "=v")
1257 (ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
1258 (match_operand:VI 2 "register_operand" "v") ))]
1259 "TARGET_ALTIVEC"
1260 "vsra<VI_char> %0,%1,%2"
1261 [(set_attr "type" "vecsimple")])
1263 (define_insn "altivec_vsr"
1264 [(set (match_operand:V4SI 0 "register_operand" "=v")
1265 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1266 (match_operand:V4SI 2 "register_operand" "v")]
1267 UNSPEC_VSR))]
1268 "TARGET_ALTIVEC"
1269 "vsr %0,%1,%2"
1270 [(set_attr "type" "vecperm")])
1272 (define_insn "altivec_vsro"
1273 [(set (match_operand:V4SI 0 "register_operand" "=v")
1274 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1275 (match_operand:V4SI 2 "register_operand" "v")]
1276 UNSPEC_VSRO))]
1277 "TARGET_ALTIVEC"
1278 "vsro %0,%1,%2"
1279 [(set_attr "type" "vecperm")])
1281 (define_insn "altivec_vsum4ubs"
1282 [(set (match_operand:V4SI 0 "register_operand" "=v")
1283 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1284 (match_operand:V4SI 2 "register_operand" "v")]
1285 UNSPEC_VSUM4UBS))
1286 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1287 "TARGET_ALTIVEC"
1288 "vsum4ubs %0,%1,%2"
1289 [(set_attr "type" "veccomplex")])
1291 (define_insn "altivec_vsum4s<VI_char>s"
1292 [(set (match_operand:V4SI 0 "register_operand" "=v")
1293 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
1294 (match_operand:V4SI 2 "register_operand" "v")]
1295 UNSPEC_VSUM4S))
1296 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1297 "TARGET_ALTIVEC"
1298 "vsum4s<VI_char>s %0,%1,%2"
1299 [(set_attr "type" "veccomplex")])
1301 (define_insn "altivec_vsum2sws"
1302 [(set (match_operand:V4SI 0 "register_operand" "=v")
1303 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1304 (match_operand:V4SI 2 "register_operand" "v")]
1305 UNSPEC_VSUM2SWS))
1306 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1307 "TARGET_ALTIVEC"
1308 "vsum2sws %0,%1,%2"
1309 [(set_attr "type" "veccomplex")])
1311 (define_insn "altivec_vsumsws"
1312 [(set (match_operand:V4SI 0 "register_operand" "=v")
1313 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1314 (match_operand:V4SI 2 "register_operand" "v")]
1315 UNSPEC_VSUMSWS))
1316 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1317 "TARGET_ALTIVEC"
1318 "vsumsws %0,%1,%2"
1319 [(set_attr "type" "veccomplex")])
1321 (define_insn "altivec_vspltb"
1322 [(set (match_operand:V16QI 0 "register_operand" "=v")
1323 (vec_duplicate:V16QI
1324 (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
1325 (parallel
1326 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1327 "TARGET_ALTIVEC"
1328 "vspltb %0,%1,%2"
1329 [(set_attr "type" "vecperm")])
1331 (define_insn "altivec_vsplth"
1332 [(set (match_operand:V8HI 0 "register_operand" "=v")
1333 (vec_duplicate:V8HI
1334 (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
1335 (parallel
1336 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1337 "TARGET_ALTIVEC"
1338 "vsplth %0,%1,%2"
1339 [(set_attr "type" "vecperm")])
1341 (define_insn "altivec_vspltw"
1342 [(set (match_operand:V4SI 0 "register_operand" "=v")
1343 (vec_duplicate:V4SI
1344 (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
1345 (parallel
1346 [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1347 "TARGET_ALTIVEC"
1348 "vspltw %0,%1,%2"
1349 [(set_attr "type" "vecperm")])
1351 (define_insn "*altivec_vspltsf"
1352 [(set (match_operand:V4SF 0 "register_operand" "=v")
1353 (vec_duplicate:V4SF
1354 (vec_select:SF (match_operand:V4SF 1 "register_operand" "v")
1355 (parallel
1356 [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1357 "TARGET_ALTIVEC"
1358 "vspltw %0,%1,%2"
1359 [(set_attr "type" "vecperm")])
1361 (define_insn "altivec_vspltis<VI_char>"
1362 [(set (match_operand:VI 0 "register_operand" "=v")
1363 (vec_duplicate:VI
1364 (match_operand:QI 1 "s5bit_cint_operand" "i")))]
1365 "TARGET_ALTIVEC"
1366 "vspltis<VI_char> %0,%1"
1367 [(set_attr "type" "vecperm")])
1369 (define_insn "ftruncv4sf2"
1370 [(set (match_operand:V4SF 0 "register_operand" "=v")
1371 (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1372 "TARGET_ALTIVEC"
1373 "vrfiz %0,%1"
1374 [(set_attr "type" "vecfloat")])
1376 (define_insn "altivec_vperm_<mode>"
1377 [(set (match_operand:V 0 "register_operand" "=v")
1378 (unspec:V [(match_operand:V 1 "register_operand" "v")
1379 (match_operand:V 2 "register_operand" "v")
1380 (match_operand:V16QI 3 "register_operand" "v")]
1381 UNSPEC_VPERM))]
1382 "TARGET_ALTIVEC"
1383 "vperm %0,%1,%2,%3"
1384 [(set_attr "type" "vecperm")])
1386 (define_insn "altivec_vrfip"
1387 [(set (match_operand:V4SF 0 "register_operand" "=v")
1388 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1389 UNSPEC_VRFIP))]
1390 "TARGET_ALTIVEC"
1391 "vrfip %0,%1"
1392 [(set_attr "type" "vecfloat")])
1394 (define_insn "altivec_vrfin"
1395 [(set (match_operand:V4SF 0 "register_operand" "=v")
1396 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1397 UNSPEC_VRFIN))]
1398 "TARGET_ALTIVEC"
1399 "vrfin %0,%1"
1400 [(set_attr "type" "vecfloat")])
1402 (define_insn "altivec_vrfim"
1403 [(set (match_operand:V4SF 0 "register_operand" "=v")
1404 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1405 UNSPEC_VRFIM))]
1406 "TARGET_ALTIVEC"
1407 "vrfim %0,%1"
1408 [(set_attr "type" "vecfloat")])
1410 (define_insn "altivec_vcfux"
1411 [(set (match_operand:V4SF 0 "register_operand" "=v")
1412 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1413 (match_operand:QI 2 "immediate_operand" "i")]
1414 UNSPEC_VCFUX))]
1415 "TARGET_ALTIVEC"
1416 "vcfux %0,%1,%2"
1417 [(set_attr "type" "vecfloat")])
1419 (define_insn "altivec_vcfsx"
1420 [(set (match_operand:V4SF 0 "register_operand" "=v")
1421 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1422 (match_operand:QI 2 "immediate_operand" "i")]
1423 UNSPEC_VCFSX))]
1424 "TARGET_ALTIVEC"
1425 "vcfsx %0,%1,%2"
1426 [(set_attr "type" "vecfloat")])
1428 (define_insn "altivec_vctuxs"
1429 [(set (match_operand:V4SI 0 "register_operand" "=v")
1430 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1431 (match_operand:QI 2 "immediate_operand" "i")]
1432 UNSPEC_VCTUXS))
1433 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1434 "TARGET_ALTIVEC"
1435 "vctuxs %0,%1,%2"
1436 [(set_attr "type" "vecfloat")])
1438 (define_insn "altivec_vctsxs"
1439 [(set (match_operand:V4SI 0 "register_operand" "=v")
1440 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1441 (match_operand:QI 2 "immediate_operand" "i")]
1442 UNSPEC_VCTSXS))
1443 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1444 "TARGET_ALTIVEC"
1445 "vctsxs %0,%1,%2"
1446 [(set_attr "type" "vecfloat")])
1448 (define_insn "altivec_vlogefp"
1449 [(set (match_operand:V4SF 0 "register_operand" "=v")
1450 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1451 UNSPEC_VLOGEFP))]
1452 "TARGET_ALTIVEC"
1453 "vlogefp %0,%1"
1454 [(set_attr "type" "vecfloat")])
1456 (define_insn "altivec_vexptefp"
1457 [(set (match_operand:V4SF 0 "register_operand" "=v")
1458 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1459 UNSPEC_VEXPTEFP))]
1460 "TARGET_ALTIVEC"
1461 "vexptefp %0,%1"
1462 [(set_attr "type" "vecfloat")])
1464 (define_insn "altivec_vrsqrtefp"
1465 [(set (match_operand:V4SF 0 "register_operand" "=v")
1466 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1467 UNSPEC_VRSQRTEFP))]
1468 "TARGET_ALTIVEC"
1469 "vrsqrtefp %0,%1"
1470 [(set_attr "type" "vecfloat")])
1472 (define_insn "altivec_vrefp"
1473 [(set (match_operand:V4SF 0 "register_operand" "=v")
1474 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1475 UNSPEC_VREFP))]
1476 "TARGET_ALTIVEC"
1477 "vrefp %0,%1"
1478 [(set_attr "type" "vecfloat")])
1480 (define_expand "vcondv4si"
1481 [(set (match_operand:V4SI 0 "register_operand" "=v")
1482 (if_then_else:V4SI
1483 (match_operator 3 "comparison_operator"
1484 [(match_operand:V4SI 4 "register_operand" "v")
1485 (match_operand:V4SI 5 "register_operand" "v")])
1486 (match_operand:V4SI 1 "register_operand" "v")
1487 (match_operand:V4SI 2 "register_operand" "v")))]
1488 "TARGET_ALTIVEC"
1489 "
1490 {
1491 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1492 operands[3], operands[4], operands[5]))
1493 DONE;
1494 else
1495 FAIL;
1496 }
1497 ")
1499 (define_expand "vconduv4si"
1500 [(set (match_operand:V4SI 0 "register_operand" "=v")
1501 (if_then_else:V4SI
1502 (match_operator 3 "comparison_operator"
1503 [(match_operand:V4SI 4 "register_operand" "v")
1504 (match_operand:V4SI 5 "register_operand" "v")])
1505 (match_operand:V4SI 1 "register_operand" "v")
1506 (match_operand:V4SI 2 "register_operand" "v")))]
1507 "TARGET_ALTIVEC"
1508 "
1509 {
1510 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1511 operands[3], operands[4], operands[5]))
1512 DONE;
1513 else
1514 FAIL;
1515 }
1516 ")
1518 (define_expand "vcondv4sf"
1519 [(set (match_operand:V4SF 0 "register_operand" "=v")
1520 (if_then_else:V4SF
1521 (match_operator 3 "comparison_operator"
1522 [(match_operand:V4SF 4 "register_operand" "v")
1523 (match_operand:V4SF 5 "register_operand" "v")])
1524 (match_operand:V4SF 1 "register_operand" "v")
1525 (match_operand:V4SF 2 "register_operand" "v")))]
1526 "TARGET_ALTIVEC"
1527 "
1528 {
1529 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1530 operands[3], operands[4], operands[5]))
1531 DONE;
1532 else
1533 FAIL;
1534 }
1535 ")
1537 (define_expand "vcondv8hi"
1538 [(set (match_operand:V8HI 0 "register_operand" "=v")
1539 (if_then_else:V8HI
1540 (match_operator 3 "comparison_operator"
1541 [(match_operand:V8HI 4 "register_operand" "v")
1542 (match_operand:V8HI 5 "register_operand" "v")])
1543 (match_operand:V8HI 1 "register_operand" "v")
1544 (match_operand:V8HI 2 "register_operand" "v")))]
1545 "TARGET_ALTIVEC"
1546 "
1547 {
1548 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1549 operands[3], operands[4], operands[5]))
1550 DONE;
1551 else
1552 FAIL;
1553 }
1554 ")
1556 (define_expand "vconduv8hi"
1557 [(set (match_operand:V8HI 0 "register_operand" "=v")
1558 (if_then_else:V8HI
1559 (match_operator 3 "comparison_operator"
1560 [(match_operand:V8HI 4 "register_operand" "v")
1561 (match_operand:V8HI 5 "register_operand" "v")])
1562 (match_operand:V8HI 1 "register_operand" "v")
1563 (match_operand:V8HI 2 "register_operand" "v")))]
1564 "TARGET_ALTIVEC"
1565 "
1566 {
1567 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1568 operands[3], operands[4], operands[5]))
1569 DONE;
1570 else
1571 FAIL;
1572 }
1573 ")
1575 (define_expand "vcondv16qi"
1576 [(set (match_operand:V16QI 0 "register_operand" "=v")
1577 (if_then_else:V16QI
1578 (match_operator 3 "comparison_operator"
1579 [(match_operand:V16QI 4 "register_operand" "v")
1580 (match_operand:V16QI 5 "register_operand" "v")])
1581 (match_operand:V16QI 1 "register_operand" "v")
1582 (match_operand:V16QI 2 "register_operand" "v")))]
1583 "TARGET_ALTIVEC"
1584 "
1585 {
1586 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1587 operands[3], operands[4], operands[5]))
1588 DONE;
1589 else
1590 FAIL;
1591 }
1592 ")
1594 (define_expand "vconduv16qi"
1595 [(set (match_operand:V16QI 0 "register_operand" "=v")
1596 (if_then_else:V16QI
1597 (match_operator 3 "comparison_operator"
1598 [(match_operand:V16QI 4 "register_operand" "v")
1599 (match_operand:V16QI 5 "register_operand" "v")])
1600 (match_operand:V16QI 1 "register_operand" "v")
1601 (match_operand:V16QI 2 "register_operand" "v")))]
1602 "TARGET_ALTIVEC"
1603 "
1604 {
1605 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1606 operands[3], operands[4], operands[5]))
1607 DONE;
1608 else
1609 FAIL;
1610 }
1611 ")
1614 (define_insn "altivec_vsel_v4si"
1615 [(set (match_operand:V4SI 0 "register_operand" "=v")
1616 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1617 (match_operand:V4SI 2 "register_operand" "v")
1618 (match_operand:V4SI 3 "register_operand" "v")]
1619 UNSPEC_VSEL4SI))]
1620 "TARGET_ALTIVEC"
1621 "vsel %0,%1,%2,%3"
1622 [(set_attr "type" "vecperm")])
1624 (define_insn "altivec_vsel_v4sf"
1625 [(set (match_operand:V4SF 0 "register_operand" "=v")
1626 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1627 (match_operand:V4SF 2 "register_operand" "v")
1628 (match_operand:V4SI 3 "register_operand" "v")]
1629 UNSPEC_VSEL4SF))]
1630 "TARGET_ALTIVEC"
1631 "vsel %0,%1,%2,%3"
1632 [(set_attr "type" "vecperm")])
1634 (define_insn "altivec_vsel_v8hi"
1635 [(set (match_operand:V8HI 0 "register_operand" "=v")
1636 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1637 (match_operand:V8HI 2 "register_operand" "v")
1638 (match_operand:V8HI 3 "register_operand" "v")]
1639 UNSPEC_VSEL8HI))]
1640 "TARGET_ALTIVEC"
1641 "vsel %0,%1,%2,%3"
1642 [(set_attr "type" "vecperm")])
1644 (define_insn "altivec_vsel_v16qi"
1645 [(set (match_operand:V16QI 0 "register_operand" "=v")
1646 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1647 (match_operand:V16QI 2 "register_operand" "v")
1648 (match_operand:V16QI 3 "register_operand" "v")]
1649 UNSPEC_VSEL16QI))]
1650 "TARGET_ALTIVEC"
1651 "vsel %0,%1,%2,%3"
1652 [(set_attr "type" "vecperm")])
1654 (define_insn "altivec_vsldoi_<mode>"
1655 [(set (match_operand:V 0 "register_operand" "=v")
1656 (unspec:V [(match_operand:V 1 "register_operand" "v")
1657 (match_operand:V 2 "register_operand" "v")
1658 (match_operand:QI 3 "immediate_operand" "i")]
1659 UNSPEC_VLSDOI))]
1660 "TARGET_ALTIVEC"
1661 "vsldoi %0,%1,%2,%3"
1662 [(set_attr "type" "vecperm")])
1664 (define_insn "altivec_vupkhsb"
1665 [(set (match_operand:V8HI 0 "register_operand" "=v")
1666 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1667 UNSPEC_VUPKHSB))]
1668 "TARGET_ALTIVEC"
1669 "vupkhsb %0,%1"
1670 [(set_attr "type" "vecperm")])
1672 (define_insn "altivec_vupkhpx"
1673 [(set (match_operand:V4SI 0 "register_operand" "=v")
1674 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1675 UNSPEC_VUPKHPX))]
1676 "TARGET_ALTIVEC"
1677 "vupkhpx %0,%1"
1678 [(set_attr "type" "vecperm")])
1680 (define_insn "altivec_vupkhsh"
1681 [(set (match_operand:V4SI 0 "register_operand" "=v")
1682 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1683 UNSPEC_VUPKHSH))]
1684 "TARGET_ALTIVEC"
1685 "vupkhsh %0,%1"
1686 [(set_attr "type" "vecperm")])
1688 (define_insn "altivec_vupklsb"
1689 [(set (match_operand:V8HI 0 "register_operand" "=v")
1690 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1691 UNSPEC_VUPKLSB))]
1692 "TARGET_ALTIVEC"
1693 "vupklsb %0,%1"
1694 [(set_attr "type" "vecperm")])
1696 (define_insn "altivec_vupklpx"
1697 [(set (match_operand:V4SI 0 "register_operand" "=v")
1698 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1699 UNSPEC_VUPKLPX))]
1700 "TARGET_ALTIVEC"
1701 "vupklpx %0,%1"
1702 [(set_attr "type" "vecperm")])
1704 (define_insn "altivec_vupklsh"
1705 [(set (match_operand:V4SI 0 "register_operand" "=v")
1706 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1707 UNSPEC_VUPKLSH))]
1708 "TARGET_ALTIVEC"
1709 "vupklsh %0,%1"
1710 [(set_attr "type" "vecperm")])
1712 ;; AltiVec predicates.
1714 (define_expand "cr6_test_for_zero"
1715 [(set (match_operand:SI 0 "register_operand" "=r")
1716 (eq:SI (reg:CC 74)
1717 (const_int 0)))]
1718 "TARGET_ALTIVEC"
1719 "")
1721 (define_expand "cr6_test_for_zero_reverse"
1722 [(set (match_operand:SI 0 "register_operand" "=r")
1723 (eq:SI (reg:CC 74)
1724 (const_int 0)))
1725 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1726 "TARGET_ALTIVEC"
1727 "")
1729 (define_expand "cr6_test_for_lt"
1730 [(set (match_operand:SI 0 "register_operand" "=r")
1731 (lt:SI (reg:CC 74)
1732 (const_int 0)))]
1733 "TARGET_ALTIVEC"
1734 "")
1736 (define_expand "cr6_test_for_lt_reverse"
1737 [(set (match_operand:SI 0 "register_operand" "=r")
1738 (lt:SI (reg:CC 74)
1739 (const_int 0)))
1740 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1741 "TARGET_ALTIVEC"
1742 "")
1744 ;; We can get away with generating the opcode on the fly (%3 below)
1745 ;; because all the predicates have the same scheduling parameters.
1747 (define_insn "altivec_predicate_<mode>"
1748 [(set (reg:CC 74)
1749 (unspec:CC [(match_operand:V 1 "register_operand" "v")
1750 (match_operand:V 2 "register_operand" "v")
1751 (match_operand 3 "any_operand" "")] UNSPEC_PREDICATE))
1752 (clobber (match_scratch:V 0 "=v"))]
1753 "TARGET_ALTIVEC"
1754 "%3 %0,%1,%2"
1755 [(set_attr "type" "veccmp")])
1757 (define_insn "altivec_mtvscr"
1758 [(set (reg:SI 110)
1759 (unspec_volatile:SI
1760 [(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))]
1761 "TARGET_ALTIVEC"
1762 "mtvscr %0"
1763 [(set_attr "type" "vecsimple")])
1765 (define_insn "altivec_mfvscr"
1766 [(set (match_operand:V8HI 0 "register_operand" "=v")
1767 (unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))]
1768 "TARGET_ALTIVEC"
1769 "mfvscr %0"
1770 [(set_attr "type" "vecsimple")])
1772 (define_insn "altivec_dssall"
1773 [(unspec_volatile [(const_int 0)] UNSPECV_DSSALL)]
1774 "TARGET_ALTIVEC"
1775 "dssall"
1776 [(set_attr "type" "vecsimple")])
1778 (define_insn "altivec_dss"
1779 [(unspec_volatile [(match_operand:QI 0 "immediate_operand" "i")]
1780 UNSPECV_DSS)]
1781 "TARGET_ALTIVEC"
1782 "dss %0"
1783 [(set_attr "type" "vecsimple")])
1785 (define_insn "altivec_dst"
1786 [(unspec [(match_operand 0 "register_operand" "b")
1787 (match_operand:SI 1 "register_operand" "r")
1788 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DST)]
1789 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1790 "dst %0,%1,%2"
1791 [(set_attr "type" "vecsimple")])
1793 (define_insn "altivec_dstt"
1794 [(unspec [(match_operand 0 "register_operand" "b")
1795 (match_operand:SI 1 "register_operand" "r")
1796 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTT)]
1797 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1798 "dstt %0,%1,%2"
1799 [(set_attr "type" "vecsimple")])
1801 (define_insn "altivec_dstst"
1802 [(unspec [(match_operand 0 "register_operand" "b")
1803 (match_operand:SI 1 "register_operand" "r")
1804 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTST)]
1805 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1806 "dstst %0,%1,%2"
1807 [(set_attr "type" "vecsimple")])
1809 (define_insn "altivec_dststt"
1810 [(unspec [(match_operand 0 "register_operand" "b")
1811 (match_operand:SI 1 "register_operand" "r")
1812 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTSTT)]
1813 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1814 "dststt %0,%1,%2"
1815 [(set_attr "type" "vecsimple")])
1817 (define_insn "altivec_lvsl"
1818 [(set (match_operand:V16QI 0 "register_operand" "=v")
1819 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSL))]
1820 "TARGET_ALTIVEC"
1821 "lvsl %0,%y1"
1822 [(set_attr "type" "vecload")])
1824 (define_insn "altivec_lvsr"
1825 [(set (match_operand:V16QI 0 "register_operand" "=v")
1826 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSR))]
1827 "TARGET_ALTIVEC"
1828 "lvsr %0,%y1"
1829 [(set_attr "type" "vecload")])
1831 (define_expand "build_vector_mask_for_load"
1832 [(set (match_operand:V16QI 0 "register_operand" "")
1833 (unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
1834 "TARGET_ALTIVEC"
1835 "
1836 {
1837 rtx addr;
1838 rtx temp;
1840 gcc_assert (GET_CODE (operands[1]) == MEM);
1842 addr = XEXP (operands[1], 0);
1843 temp = gen_reg_rtx (GET_MODE (addr));
1844 emit_insn (gen_rtx_SET (VOIDmode, temp,
1845 gen_rtx_NEG (GET_MODE (addr), addr)));
1846 emit_insn (gen_altivec_lvsr (operands[0],
1847 replace_equiv_address (operands[1], temp)));
1848 DONE;
1849 }")
1851 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1852 ;; identical rtl but different instructions-- and gcc gets confused.
1854 (define_insn "altivec_lve<VI_char>x"
1855 [(parallel
1856 [(set (match_operand:VI 0 "register_operand" "=v")
1857 (match_operand:VI 1 "memory_operand" "Z"))
1858 (unspec [(const_int 0)] UNSPEC_LVE)])]
1859 "TARGET_ALTIVEC"
1860 "lve<VI_char>x %0,%y1"
1861 [(set_attr "type" "vecload")])
1863 (define_insn "*altivec_lvesfx"
1864 [(parallel
1865 [(set (match_operand:V4SF 0 "register_operand" "=v")
1866 (match_operand:V4SF 1 "memory_operand" "Z"))
1867 (unspec [(const_int 0)] UNSPEC_LVE)])]
1868 "TARGET_ALTIVEC"
1869 "lvewx %0,%y1"
1870 [(set_attr "type" "vecload")])
1872 (define_insn "altivec_lvxl"
1873 [(parallel
1874 [(set (match_operand:V4SI 0 "register_operand" "=v")
1875 (match_operand:V4SI 1 "memory_operand" "Z"))
1876 (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
1877 "TARGET_ALTIVEC"
1878 "lvxl %0,%y1"
1879 [(set_attr "type" "vecload")])
1881 (define_insn "altivec_lvx"
1882 [(set (match_operand:V4SI 0 "register_operand" "=v")
1883 (match_operand:V4SI 1 "memory_operand" "Z"))]
1884 "TARGET_ALTIVEC"
1885 "lvx %0,%y1"
1886 [(set_attr "type" "vecload")])
1888 (define_insn "altivec_stvx"
1889 [(parallel
1890 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
1891 (match_operand:V4SI 1 "register_operand" "v"))
1892 (unspec [(const_int 0)] UNSPEC_STVX)])]
1893 "TARGET_ALTIVEC"
1894 "stvx %1,%y0"
1895 [(set_attr "type" "vecstore")])
1897 (define_insn "altivec_stvxl"
1898 [(parallel
1899 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
1900 (match_operand:V4SI 1 "register_operand" "v"))
1901 (unspec [(const_int 0)] UNSPEC_STVXL)])]
1902 "TARGET_ALTIVEC"
1903 "stvxl %1,%y0"
1904 [(set_attr "type" "vecstore")])
1906 (define_insn "altivec_stve<VI_char>x"
1907 [(parallel
1908 [(set (match_operand:VI 0 "memory_operand" "=Z")
1909 (match_operand:VI 1 "register_operand" "v"))
1910 (unspec [(const_int 0)] UNSPEC_STVE)])]
1911 "TARGET_ALTIVEC"
1912 "stve<VI_char>x %1,%y0"
1913 [(set_attr "type" "vecstore")])
1915 (define_insn "*altivec_stvesfx"
1916 [(parallel
1917 [(set (match_operand:V4SF 0 "memory_operand" "=Z")
1918 (match_operand:V4SF 1 "register_operand" "v"))
1919 (unspec [(const_int 0)] UNSPEC_STVE)])]
1920 "TARGET_ALTIVEC"
1921 "stvewx %1,%y0"
1922 [(set_attr "type" "vecstore")])
1924 (define_expand "vec_init<mode>"
1925 [(match_operand:V 0 "register_operand" "")
1926 (match_operand 1 "" "")]
1927 "TARGET_ALTIVEC"
1928 {
1929 rs6000_expand_vector_init (operands[0], operands[1]);
1930 DONE;
1931 })
1933 (define_expand "vec_setv4si"
1934 [(match_operand:V4SI 0 "register_operand" "")
1935 (match_operand:SI 1 "register_operand" "")
1936 (match_operand 2 "const_int_operand" "")]
1937 "TARGET_ALTIVEC"
1938 {
1939 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1940 DONE;
1941 })
1943 (define_expand "vec_setv8hi"
1944 [(match_operand:V8HI 0 "register_operand" "")
1945 (match_operand:HI 1 "register_operand" "")
1946 (match_operand 2 "const_int_operand" "")]
1947 "TARGET_ALTIVEC"
1948 {
1949 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1950 DONE;
1951 })
1953 (define_expand "vec_setv16qi"
1954 [(match_operand:V16QI 0 "register_operand" "")
1955 (match_operand:QI 1 "register_operand" "")
1956 (match_operand 2 "const_int_operand" "")]
1957 "TARGET_ALTIVEC"
1958 {
1959 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1960 DONE;
1961 })
1963 (define_expand "vec_setv4sf"
1964 [(match_operand:V4SF 0 "register_operand" "")
1965 (match_operand:SF 1 "register_operand" "")
1966 (match_operand 2 "const_int_operand" "")]
1967 "TARGET_ALTIVEC"
1968 {
1969 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1970 DONE;
1971 })
1973 (define_expand "vec_extractv4si"
1974 [(match_operand:SI 0 "register_operand" "")
1975 (match_operand:V4SI 1 "register_operand" "")
1976 (match_operand 2 "const_int_operand" "")]
1977 "TARGET_ALTIVEC"
1978 {
1979 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
1980 DONE;
1981 })
1983 (define_expand "vec_extractv8hi"
1984 [(match_operand:HI 0 "register_operand" "")
1985 (match_operand:V8HI 1 "register_operand" "")
1986 (match_operand 2 "const_int_operand" "")]
1987 "TARGET_ALTIVEC"
1988 {
1989 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
1990 DONE;
1991 })
1993 (define_expand "vec_extractv16qi"
1994 [(match_operand:QI 0 "register_operand" "")
1995 (match_operand:V16QI 1 "register_operand" "")
1996 (match_operand 2 "const_int_operand" "")]
1997 "TARGET_ALTIVEC"
1998 {
1999 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
2000 DONE;
2001 })
2003 (define_expand "vec_extractv4sf"
2004 [(match_operand:SF 0 "register_operand" "")
2005 (match_operand:V4SF 1 "register_operand" "")
2006 (match_operand 2 "const_int_operand" "")]
2007 "TARGET_ALTIVEC"
2008 {
2009 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
2010 DONE;
2011 })
2013 ;; Generate
2014 ;; vspltis? SCRATCH0,0
2015 ;; vsubu?m SCRATCH2,SCRATCH1,%1
2016 ;; vmaxs? %0,%1,SCRATCH2"
2017 (define_expand "abs<mode>2"
2018 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
2019 (set (match_dup 3)
2020 (minus:VI (match_dup 2)
2021 (match_operand:VI 1 "register_operand" "v")))
2022 (set (match_operand:VI 0 "register_operand" "=v")
2023 (smax:VI (match_dup 1) (match_dup 3)))]
2024 "TARGET_ALTIVEC"
2025 {
2026 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
2027 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
2028 })
2030 ;; Generate
2031 ;; vspltisw SCRATCH1,-1
2032 ;; vslw SCRATCH2,SCRATCH1,SCRATCH1
2033 ;; vandc %0,%1,SCRATCH2
2034 (define_expand "absv4sf2"
2035 [(set (match_dup 2)
2036 (vec_duplicate:V4SI (const_int -1)))
2037 (set (match_dup 3)
2038 (unspec:V4SI [(match_dup 2) (match_dup 2)] UNSPEC_VSL))
2039 (set (match_operand:V4SF 0 "register_operand" "=v")
2040 (and:V4SF (not:V4SF (subreg:V4SF (match_dup 3) 0))
2041 (match_operand:V4SF 1 "register_operand" "v")))]
2042 "TARGET_ALTIVEC"
2043 {
2044 operands[2] = gen_reg_rtx (V4SImode);
2045 operands[3] = gen_reg_rtx (V4SImode);
2046 })
2048 ;; Generate
2049 ;; vspltis? SCRATCH0,0
2050 ;; vsubs?s SCRATCH2,SCRATCH1,%1
2051 ;; vmaxs? %0,%1,SCRATCH2"
2052 (define_expand "altivec_abss_<mode>"
2053 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
2054 (parallel [(set (match_dup 3)
2055 (unspec:VI [(match_dup 2)
2056 (match_operand:VI 1 "register_operand" "v")]
2057 UNSPEC_VSUBS))
2058 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
2059 (set (match_operand:VI 0 "register_operand" "=v")
2060 (smax:VI (match_dup 1) (match_dup 3)))]
2061 "TARGET_ALTIVEC"
2062 {
2063 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
2064 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
2065 })
2067 ;; Vector shift left in bits. Currently supported ony for shift
2068 ;; amounts that can be expressed as byte shifts (divisible by 8).
2069 ;; General shift amounts can be supported using vslo + vsl. We're
2070 ;; not expecting to see these yet (the vectorizer currently
2071 ;; generates only shifts divisible by byte_size).
2072 (define_expand "vec_shl_<mode>"
2073 [(set (match_operand:V 0 "register_operand" "=v")
2074 (unspec:V [(match_operand:V 1 "register_operand" "v")
2075 (match_operand:QI 2 "reg_or_short_operand" "")]
2076 UNSPEC_VECSH))]
2077 "TARGET_ALTIVEC"
2078 "
2079 {
2080 rtx bitshift = operands[2];
2081 rtx byteshift = gen_reg_rtx (QImode);
2082 HOST_WIDE_INT bitshift_val;
2083 HOST_WIDE_INT byteshift_val;
2085 if (! CONSTANT_P (bitshift))
2086 FAIL;
2087 bitshift_val = INTVAL (bitshift);
2088 if (bitshift_val & 0x7)
2089 FAIL;
2090 byteshift_val = bitshift_val >> 3;
2091 byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
2092 emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
2093 byteshift));
2094 DONE;
2095 }")
2097 ;; Vector shift left in bits. Currently supported ony for shift
2098 ;; amounts that can be expressed as byte shifts (divisible by 8).
2099 ;; General shift amounts can be supported using vsro + vsr. We're
2100 ;; not expecting to see these yet (the vectorizer currently
2101 ;; generates only shifts divisible by byte_size).
2102 (define_expand "vec_shr_<mode>"
2103 [(set (match_operand:V 0 "register_operand" "=v")
2104 (unspec:V [(match_operand:V 1 "register_operand" "v")
2105 (match_operand:QI 2 "reg_or_short_operand" "")]
2106 UNSPEC_VECSH))]
2107 "TARGET_ALTIVEC"
2108 "
2109 {
2110 rtx bitshift = operands[2];
2111 rtx byteshift = gen_reg_rtx (QImode);
2112 HOST_WIDE_INT bitshift_val;
2113 HOST_WIDE_INT byteshift_val;
2115 if (! CONSTANT_P (bitshift))
2116 FAIL;
2117 bitshift_val = INTVAL (bitshift);
2118 if (bitshift_val & 0x7)
2119 FAIL;
2120 byteshift_val = 16 - (bitshift_val >> 3);
2121 byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
2122 emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
2123 byteshift));
2124 DONE;
2125 }")
2127 (define_insn "altivec_vsumsws_nomode"
2128 [(set (match_operand 0 "register_operand" "=v")
2129 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
2130 (match_operand:V4SI 2 "register_operand" "v")]
2131 UNSPEC_VSUMSWS))
2132 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
2133 "TARGET_ALTIVEC"
2134 "vsumsws %0,%1,%2"
2135 [(set_attr "type" "veccomplex")])
2137 (define_expand "reduc_splus_<mode>"
2138 [(set (match_operand:VIshort 0 "register_operand" "=v")
2139 (unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")]
2140 UNSPEC_REDUC_PLUS))]
2141 "TARGET_ALTIVEC"
2142 "
2143 {
2144 rtx vzero = gen_reg_rtx (V4SImode);
2145 rtx vtmp1 = gen_reg_rtx (V4SImode);
2147 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2148 emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
2149 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
2150 DONE;
2151 }")
2153 (define_expand "reduc_uplus_v16qi"
2154 [(set (match_operand:V16QI 0 "register_operand" "=v")
2155 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
2156 UNSPEC_REDUC_PLUS))]
2157 "TARGET_ALTIVEC"
2158 "
2159 {
2160 rtx vzero = gen_reg_rtx (V4SImode);
2161 rtx vtmp1 = gen_reg_rtx (V4SImode);
2163 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2164 emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
2165 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
2166 DONE;
2167 }")
2169 (define_insn "vec_realign_load_<mode>"
2170 [(set (match_operand:V 0 "register_operand" "=v")
2171 (unspec:V [(match_operand:V 1 "register_operand" "v")
2172 (match_operand:V 2 "register_operand" "v")
2173 (match_operand:V16QI 3 "register_operand" "v")]
2174 UNSPEC_REALIGN_LOAD))]
2175 "TARGET_ALTIVEC"
2176 "vperm %0,%1,%2,%3"
2177 [(set_attr "type" "vecperm")])
2179 (define_expand "neg<mode>2"
2180 [(use (match_operand:VI 0 "register_operand" ""))
2181 (use (match_operand:VI 1 "register_operand" ""))]
2182 "TARGET_ALTIVEC"
2183 "
2184 {
2185 rtx vzero;
2187 vzero = gen_reg_rtx (GET_MODE (operands[0]));
2188 emit_insn (gen_altivec_vspltis<VI_char> (vzero, const0_rtx));
2189 emit_insn (gen_sub<mode>3 (operands[0], vzero, operands[1]));
2191 DONE;
2192 }")
2194 (define_expand "udot_prod<mode>"
2195 [(set (match_operand:V4SI 0 "register_operand" "=v")
2196 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
2197 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
2198 (match_operand:VIshort 2 "register_operand" "v")]
2199 UNSPEC_VMSUMU)))]
2200 "TARGET_ALTIVEC"
2201 "
2202 {
2203 emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], operands[2], operands[3]));
2204 DONE;
2205 }")
2207 (define_expand "sdot_prodv8hi"
2208 [(set (match_operand:V4SI 0 "register_operand" "=v")
2209 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
2210 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2211 (match_operand:V8HI 2 "register_operand" "v")]
2212 UNSPEC_VMSUMSHM)))]
2213 "TARGET_ALTIVEC"
2214 "
2215 {
2216 emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2], operands[3]));
2217 DONE;
2218 }")
2220 (define_expand "widen_usum<mode>3"
2221 [(set (match_operand:V4SI 0 "register_operand" "=v")
2222 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
2223 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")]
2224 UNSPEC_VMSUMU)))]
2225 "TARGET_ALTIVEC"
2226 "
2227 {
2228 rtx vones = gen_reg_rtx (GET_MODE (operands[1]));
2230 emit_insn (gen_altivec_vspltis<VI_char> (vones, const1_rtx));
2231 emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], vones, operands[2]));
2232 DONE;
2233 }")
2235 (define_expand "widen_ssumv16qi3"
2236 [(set (match_operand:V4SI 0 "register_operand" "=v")
2237 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
2238 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")]
2239 UNSPEC_VMSUMM)))]
2240 "TARGET_ALTIVEC"
2241 "
2242 {
2243 rtx vones = gen_reg_rtx (V16QImode);
2245 emit_insn (gen_altivec_vspltisb (vones, const1_rtx));
2246 emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones, operands[2]));
2247 DONE;
2248 }")
2250 (define_expand "widen_ssumv8hi3"
2251 [(set (match_operand:V4SI 0 "register_operand" "=v")
2252 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
2253 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2254 UNSPEC_VMSUMSHM)))]
2255 "TARGET_ALTIVEC"
2256 "
2257 {
2258 rtx vones = gen_reg_rtx (V8HImode);
2260 emit_insn (gen_altivec_vspltish (vones, const1_rtx));
2261 emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones, operands[2]));
2262 DONE;
2263 }")
2265 (define_expand "vec_unpacks_hi_v16qi"
2266 [(set (match_operand:V8HI 0 "register_operand" "=v")
2267 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2268 UNSPEC_VUPKHSB))]
2269 "TARGET_ALTIVEC"
2270 "
2271 {
2272 emit_insn (gen_altivec_vupkhsb (operands[0], operands[1]));
2273 DONE;
2274 }")
2276 (define_expand "vec_unpacks_hi_v8hi"
2277 [(set (match_operand:V4SI 0 "register_operand" "=v")
2278 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2279 UNSPEC_VUPKHSH))]
2280 "TARGET_ALTIVEC"
2281 "
2282 {
2283 emit_insn (gen_altivec_vupkhsh (operands[0], operands[1]));
2284 DONE;
2285 }")
2287 (define_expand "vec_unpacks_lo_v16qi"
2288 [(set (match_operand:V8HI 0 "register_operand" "=v")
2289 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2290 UNSPEC_VUPKLSB))]
2291 "TARGET_ALTIVEC"
2292 "
2293 {
2294 emit_insn (gen_altivec_vupklsb (operands[0], operands[1]));
2295 DONE;
2296 }")
2298 (define_expand "vec_unpacks_lo_v8hi"
2299 [(set (match_operand:V4SI 0 "register_operand" "=v")
2300 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2301 UNSPEC_VUPKLSH))]
2302 "TARGET_ALTIVEC"
2303 "
2304 {
2305 emit_insn (gen_altivec_vupklsh (operands[0], operands[1]));
2306 DONE;
2307 }")
2309 (define_insn "vperm_v8hiv4si"
2310 [(set (match_operand:V4SI 0 "register_operand" "=v")
2311 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2312 (match_operand:V4SI 2 "register_operand" "v")
2313 (match_operand:V16QI 3 "register_operand" "v")]
2314 UNSPEC_VPERMSI))]
2315 "TARGET_ALTIVEC"
2316 "vperm %0,%1,%2,%3"
2317 [(set_attr "type" "vecperm")])
2319 (define_insn "vperm_v16qiv8hi"
2320 [(set (match_operand:V8HI 0 "register_operand" "=v")
2321 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2322 (match_operand:V8HI 2 "register_operand" "v")
2323 (match_operand:V16QI 3 "register_operand" "v")]
2324 UNSPEC_VPERMHI))]
2325 "TARGET_ALTIVEC"
2326 "vperm %0,%1,%2,%3"
2327 [(set_attr "type" "vecperm")])
2330 (define_expand "vec_unpacku_hi_v16qi"
2331 [(set (match_operand:V8HI 0 "register_operand" "=v")
2332 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2333 UNSPEC_VUPKHUB))]
2334 "TARGET_ALTIVEC"
2335 "
2336 {
2337 rtx vzero = gen_reg_rtx (V8HImode);
2338 rtx mask = gen_reg_rtx (V16QImode);
2339 rtvec v = rtvec_alloc (16);
2341 emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
2343 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2344 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 0);
2345 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
2346 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
2347 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2348 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 2);
2349 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
2350 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
2351 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2352 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 4);
2353 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
2354 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
2355 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2356 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 6);
2357 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
2358 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
2360 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2361 emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
2362 DONE;
2363 }")
2365 (define_expand "vec_unpacku_hi_v8hi"
2366 [(set (match_operand:V4SI 0 "register_operand" "=v")
2367 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2368 UNSPEC_VUPKHUH))]
2369 "TARGET_ALTIVEC"
2370 "
2371 {
2372 rtx vzero = gen_reg_rtx (V4SImode);
2373 rtx mask = gen_reg_rtx (V16QImode);
2374 rtvec v = rtvec_alloc (16);
2376 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2378 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2379 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
2380 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 0);
2381 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
2382 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2383 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
2384 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 2);
2385 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
2386 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2387 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2388 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 4);
2389 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
2390 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2391 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
2392 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 6);
2393 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
2395 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2396 emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
2397 DONE;
2398 }")
2400 (define_expand "vec_unpacku_lo_v16qi"
2401 [(set (match_operand:V8HI 0 "register_operand" "=v")
2402 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2403 UNSPEC_VUPKLUB))]
2404 "TARGET_ALTIVEC"
2405 "
2406 {
2407 rtx vzero = gen_reg_rtx (V8HImode);
2408 rtx mask = gen_reg_rtx (V16QImode);
2409 rtvec v = rtvec_alloc (16);
2411 emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
2413 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2414 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 8);
2415 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
2416 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
2417 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2418 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);
2419 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
2420 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2421 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2422 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 12);
2423 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
2424 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
2425 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2426 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 14);
2427 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
2428 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
2430 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2431 emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
2432 DONE;
2433 }")
2435 (define_expand "vec_unpacku_lo_v8hi"
2436 [(set (match_operand:V4SI 0 "register_operand" "=v")
2437 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2438 UNSPEC_VUPKLUH))]
2439 "TARGET_ALTIVEC"
2440 "
2441 {
2442 rtx vzero = gen_reg_rtx (V4SImode);
2443 rtx mask = gen_reg_rtx (V16QImode);
2444 rtvec v = rtvec_alloc (16);
2446 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2448 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2449 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
2450 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 8);
2451 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
2452 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2453 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
2454 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2455 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2456 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2457 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2458 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 12);
2459 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
2460 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2461 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
2462 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 14);
2463 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
2465 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2466 emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
2467 DONE;
2468 }")
2470 (define_expand "vec_widen_umult_hi_v16qi"
2471 [(set (match_operand:V8HI 0 "register_operand" "=v")
2472 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2473 (match_operand:V16QI 2 "register_operand" "v")]
2474 UNSPEC_VMULWHUB))]
2475 "TARGET_ALTIVEC"
2476 "
2477 {
2478 rtx ve = gen_reg_rtx (V8HImode);
2479 rtx vo = gen_reg_rtx (V8HImode);
2481 emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
2482 emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
2483 emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
2484 DONE;
2485 }")
2487 (define_expand "vec_widen_umult_lo_v16qi"
2488 [(set (match_operand:V8HI 0 "register_operand" "=v")
2489 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2490 (match_operand:V16QI 2 "register_operand" "v")]
2491 UNSPEC_VMULWLUB))]
2492 "TARGET_ALTIVEC"
2493 "
2494 {
2495 rtx ve = gen_reg_rtx (V8HImode);
2496 rtx vo = gen_reg_rtx (V8HImode);
2498 emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
2499 emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
2500 emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
2501 DONE;
2502 }")
2504 (define_expand "vec_widen_smult_hi_v16qi"
2505 [(set (match_operand:V8HI 0 "register_operand" "=v")
2506 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2507 (match_operand:V16QI 2 "register_operand" "v")]
2508 UNSPEC_VMULWHSB))]
2509 "TARGET_ALTIVEC"
2510 "
2511 {
2512 rtx ve = gen_reg_rtx (V8HImode);
2513 rtx vo = gen_reg_rtx (V8HImode);
2515 emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
2516 emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
2517 emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
2518 DONE;
2519 }")
2521 (define_expand "vec_widen_smult_lo_v16qi"
2522 [(set (match_operand:V8HI 0 "register_operand" "=v")
2523 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2524 (match_operand:V16QI 2 "register_operand" "v")]
2525 UNSPEC_VMULWLSB))]
2526 "TARGET_ALTIVEC"
2527 "
2528 {
2529 rtx ve = gen_reg_rtx (V8HImode);
2530 rtx vo = gen_reg_rtx (V8HImode);
2532 emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
2533 emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
2534 emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
2535 DONE;
2536 }")
2538 (define_expand "vec_widen_umult_hi_v8hi"
2539 [(set (match_operand:V4SI 0 "register_operand" "=v")
2540 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2541 (match_operand:V8HI 2 "register_operand" "v")]
2542 UNSPEC_VMULWHUH))]
2543 "TARGET_ALTIVEC"
2544 "
2545 {
2546 rtx ve = gen_reg_rtx (V4SImode);
2547 rtx vo = gen_reg_rtx (V4SImode);
2549 emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
2550 emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
2551 emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
2552 DONE;
2553 }")
2555 (define_expand "vec_widen_umult_lo_v8hi"
2556 [(set (match_operand:V4SI 0 "register_operand" "=v")
2557 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2558 (match_operand:V8HI 2 "register_operand" "v")]
2559 UNSPEC_VMULWLUH))]
2560 "TARGET_ALTIVEC"
2561 "
2562 {
2563 rtx ve = gen_reg_rtx (V4SImode);
2564 rtx vo = gen_reg_rtx (V4SImode);
2566 emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
2567 emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
2568 emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
2569 DONE;
2570 }")
2572 (define_expand "vec_widen_smult_hi_v8hi"
2573 [(set (match_operand:V4SI 0 "register_operand" "=v")
2574 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2575 (match_operand:V8HI 2 "register_operand" "v")]
2576 UNSPEC_VMULWHSH))]
2577 "TARGET_ALTIVEC"
2578 "
2579 {
2580 rtx ve = gen_reg_rtx (V4SImode);
2581 rtx vo = gen_reg_rtx (V4SImode);
2583 emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
2584 emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
2585 emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
2586 DONE;
2587 }")
2589 (define_expand "vec_widen_smult_lo_v8hi"
2590 [(set (match_operand:V4SI 0 "register_operand" "=v")
2591 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2592 (match_operand:V8HI 2 "register_operand" "v")]
2593 UNSPEC_VMULWLSH))]
2594 "TARGET_ALTIVEC"
2595 "
2596 {
2597 rtx ve = gen_reg_rtx (V4SImode);
2598 rtx vo = gen_reg_rtx (V4SImode);
2600 emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
2601 emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
2602 emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
2603 DONE;
2604 }")
2606 (define_expand "vec_pack_trunc_v8hi"
2607 [(set (match_operand:V16QI 0 "register_operand" "=v")
2608 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
2609 (match_operand:V8HI 2 "register_operand" "v")]
2610 UNSPEC_VPKUHUM))]
2611 "TARGET_ALTIVEC"
2612 "
2613 {
2614 emit_insn (gen_altivec_vpkuhum (operands[0], operands[1], operands[2]));
2615 DONE;
2616 }")
2618 (define_expand "vec_pack_trunc_v4si"
2619 [(set (match_operand:V8HI 0 "register_operand" "=v")
2620 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
2621 (match_operand:V4SI 2 "register_operand" "v")]
2622 UNSPEC_VPKUWUM))]
2623 "TARGET_ALTIVEC"
2624 "
2625 {
2626 emit_insn (gen_altivec_vpkuwum (operands[0], operands[1], operands[2]));
2627 DONE;
2628 }")
2630 (define_expand "negv4sf2"
2631 [(use (match_operand:V4SF 0 "register_operand" ""))
2632 (use (match_operand:V4SF 1 "register_operand" ""))]
2633 "TARGET_ALTIVEC"
2634 "
2635 {
2636 rtx neg0;
2638 /* Generate [-0.0, -0.0, -0.0, -0.0]. */
2639 neg0 = gen_reg_rtx (V4SImode);
2640 emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
2641 emit_insn (gen_altivec_vslw (neg0, neg0, neg0));
2643 /* XOR */
2644 emit_insn (gen_xorv4sf3 (operands[0],
2645 gen_lowpart (V4SFmode, neg0), operands[1]));
2647 DONE;
2648 }")
2650 (define_expand "vec_extract_evenv4si"
2651 [(set (match_operand:V4SI 0 "register_operand" "")
2652 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
2653 (match_operand:V4SI 2 "register_operand" "")]
2654 UNSPEC_EXTEVEN_V4SI))]
2655 "TARGET_ALTIVEC"
2656 "
2657 {
2658 rtx mask = gen_reg_rtx (V16QImode);
2659 rtvec v = rtvec_alloc (16);
2661 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2662 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2663 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2);
2664 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3);
2665 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2666 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2667 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2668 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2669 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2670 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2671 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18);
2672 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19);
2673 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2674 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2675 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26);
2676 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27);
2677 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2678 emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask));
2680 DONE;
2681 }")
2683 (define_expand "vec_extract_evenv4sf"
2684 [(set (match_operand:V4SF 0 "register_operand" "")
2685 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
2686 (match_operand:V4SF 2 "register_operand" "")]
2687 UNSPEC_EXTEVEN_V4SF))]
2688 "TARGET_ALTIVEC"
2689 "
2690 {
2691 rtx mask = gen_reg_rtx (V16QImode);
2692 rtvec v = rtvec_alloc (16);
2694 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2695 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2696 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2);
2697 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3);
2698 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2699 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2700 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2701 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2702 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2703 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2704 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18);
2705 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19);
2706 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2707 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2708 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26);
2709 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27);
2710 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2711 emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask));
2713 DONE;
2714 }")
2716 (define_expand "vec_extract_evenv8hi"
2717 [(set (match_operand:V4SI 0 "register_operand" "")
2718 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
2719 (match_operand:V8HI 2 "register_operand" "")]
2720 UNSPEC_EXTEVEN_V8HI))]
2721 "TARGET_ALTIVEC"
2722 "
2723 {
2724 rtx mask = gen_reg_rtx (V16QImode);
2725 rtvec v = rtvec_alloc (16);
2727 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2728 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2729 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4);
2730 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 5);
2731 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2732 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2733 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12);
2734 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 13);
2735 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2736 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2737 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20);
2738 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 21);
2739 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2740 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2741 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28);
2742 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 29);
2743 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2744 emit_insn (gen_altivec_vperm_v8hi (operands[0], operands[1], operands[2], mask));
2746 DONE;
2747 }")
2749 (define_expand "vec_extract_evenv16qi"
2750 [(set (match_operand:V4SI 0 "register_operand" "")
2751 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "")
2752 (match_operand:V16QI 2 "register_operand" "")]
2753 UNSPEC_EXTEVEN_V16QI))]
2754 "TARGET_ALTIVEC"
2755 "
2756 {
2757 rtx mask = gen_reg_rtx (V16QImode);
2758 rtvec v = rtvec_alloc (16);
2760 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2761 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 2);
2762 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4);
2763 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 6);
2764 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2765 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);
2766 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12);
2767 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 14);
2768 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2769 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 18);
2770 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20);
2771 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 22);
2772 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2773 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 26);
2774 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28);
2775 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 30);
2776 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2777 emit_insn (gen_altivec_vperm_v16qi (operands[0], operands[1], operands[2], mask));
2779 DONE;
2780 }")
2782 (define_expand "vec_extract_oddv4si"
2783 [(set (match_operand:V4SI 0 "register_operand" "")
2784 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
2785 (match_operand:V4SI 2 "register_operand" "")]
2786 UNSPEC_EXTODD_V4SI))]
2787 "TARGET_ALTIVEC"
2788 "
2789 {
2790 rtx mask = gen_reg_rtx (V16QImode);
2791 rtvec v = rtvec_alloc (16);
2793 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4);
2794 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5);
2795 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6);
2796 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7);
2797 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12);
2798 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13);
2799 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14);
2800 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15);
2801 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20);
2802 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21);
2803 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22);
2804 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23);
2805 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28);
2806 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29);
2807 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30);
2808 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31);
2809 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2810 emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask));
2812 DONE;
2813 }")
2815 (define_expand "vec_extract_oddv4sf"
2816 [(set (match_operand:V4SF 0 "register_operand" "")
2817 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
2818 (match_operand:V4SF 2 "register_operand" "")]
2819 UNSPEC_EXTODD_V4SF))]
2820 "TARGET_ALTIVEC"
2821 "
2822 {
2823 rtx mask = gen_reg_rtx (V16QImode);
2824 rtvec v = rtvec_alloc (16);
2826 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4);
2827 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5);
2828 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6);
2829 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7);
2830 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12);
2831 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13);
2832 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14);
2833 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15);
2834 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20);
2835 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21);
2836 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22);
2837 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23);
2838 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28);
2839 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29);
2840 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30);
2841 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31);
2842 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2843 emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask));
2845 DONE;
2846 }")
2848 (define_insn "vpkuhum_nomode"
2849 [(set (match_operand:V16QI 0 "register_operand" "=v")
2850 (unspec:V16QI [(match_operand 1 "register_operand" "v")
2851 (match_operand 2 "register_operand" "v")]
2852 UNSPEC_VPKUHUM))]
2853 "TARGET_ALTIVEC"
2854 "vpkuhum %0,%1,%2"
2855 [(set_attr "type" "vecperm")])
2857 (define_insn "vpkuwum_nomode"
2858 [(set (match_operand:V8HI 0 "register_operand" "=v")
2859 (unspec:V8HI [(match_operand 1 "register_operand" "v")
2860 (match_operand 2 "register_operand" "v")]
2861 UNSPEC_VPKUWUM))]
2862 "TARGET_ALTIVEC"
2863 "vpkuwum %0,%1,%2"
2864 [(set_attr "type" "vecperm")])
2866 (define_expand "vec_extract_oddv8hi"
2867 [(set (match_operand:V8HI 0 "register_operand" "")
2868 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
2869 (match_operand:V8HI 2 "register_operand" "")]
2870 UNSPEC_EXTODD_V8HI))]
2871 "TARGET_ALTIVEC"
2872 "
2873 {
2874 emit_insn (gen_vpkuwum_nomode (operands[0], operands[1], operands[2]));
2875 DONE;
2876 }")
2878 (define_expand "vec_extract_oddv16qi"
2879 [(set (match_operand:V16QI 0 "register_operand" "")
2880 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
2881 (match_operand:V16QI 2 "register_operand" "")]
2882 UNSPEC_EXTODD_V16QI))]
2883 "TARGET_ALTIVEC"
2884 "
2885 {
2886 emit_insn (gen_vpkuhum_nomode (operands[0], operands[1], operands[2]));
2887 DONE;
2888 }")
2889 (define_expand "vec_interleave_highv4sf"
2890 [(set (match_operand:V4SF 0 "register_operand" "")
2891 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
2892 (match_operand:V4SF 2 "register_operand" "")]
2893 UNSPEC_INTERHI_V4SF))]
2894 "TARGET_ALTIVEC"
2895 "
2896 {
2897 emit_insn (gen_altivec_vmrghsf (operands[0], operands[1], operands[2]));
2898 DONE;
2899 }")
2901 (define_expand "vec_interleave_lowv4sf"
2902 [(set (match_operand:V4SF 0 "register_operand" "")
2903 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
2904 (match_operand:V4SF 2 "register_operand" "")]
2905 UNSPEC_INTERLO_V4SF))]
2906 "TARGET_ALTIVEC"
2907 "
2908 {
2909 emit_insn (gen_altivec_vmrglsf (operands[0], operands[1], operands[2]));
2910 DONE;
2911 }")
2913 (define_expand "vec_interleave_high<mode>"
2914 [(set (match_operand:VI 0 "register_operand" "")
2915 (unspec:VI [(match_operand:VI 1 "register_operand" "")
2916 (match_operand:VI 2 "register_operand" "")]
2917 UNSPEC_INTERHI))]
2918 "TARGET_ALTIVEC"
2919 "
2920 {
2921 emit_insn (gen_altivec_vmrgh<VI_char> (operands[0], operands[1], operands[2]));
2922 DONE;
2923 }")
2925 (define_expand "vec_interleave_low<mode>"
2926 [(set (match_operand:VI 0 "register_operand" "")
2927 (unspec:VI [(match_operand:VI 1 "register_operand" "")
2928 (match_operand:VI 2 "register_operand" "")]
2929 UNSPEC_INTERLO))]
2930 "TARGET_ALTIVEC"
2931 "
2932 {
2933 emit_insn (gen_altivec_vmrgl<VI_char> (operands[0], operands[1], operands[2]));
2934 DONE;
2935 }")