| blob | 67bab338af190dceafbe834ce075b1d7c28acf28 |
1 ;; IA-64 Machine description template
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by James E. Wilson <wilson@cygnus.com> and
5 ;; David Mosberger <davidm@hpl.hp.com>.
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; any later version.
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 ;; Boston, MA 02110-1301, USA.
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later
27 ;; reload. This will be fixed once scheduling support is turned on.
29 ;; ??? Optimize for post-increment addressing modes.
31 ;; ??? fselect is not supported, because there is no integer register
32 ;; equivalent.
34 ;; ??? fp abs/min/max instructions may also work for integer values.
36 ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy,
37 ;; it assumes the operand is a register and takes REGNO of it without checking.
39 ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy,
40 ;; it assumes the operand is a register and takes REGNO of it without checking.
42 ;; ??? Go through list of documented named patterns and look for more to
43 ;; implement.
45 ;; ??? Go through instruction manual and look for more instructions that
46 ;; can be emitted.
48 ;; ??? Add function unit scheduling info for Itanium (TM) processor.
50 ;; ??? Need a better way to describe alternate fp status registers.
52 (define_constants
53 [; Relocations
54 (UNSPEC_LTOFF_DTPMOD 0)
55 (UNSPEC_LTOFF_DTPREL 1)
56 (UNSPEC_DTPREL 2)
57 (UNSPEC_LTOFF_TPREL 3)
58 (UNSPEC_TPREL 4)
59 (UNSPEC_DTPMOD 5)
61 (UNSPEC_LD_BASE 9)
62 (UNSPEC_GR_SPILL 10)
63 (UNSPEC_GR_RESTORE 11)
64 (UNSPEC_FR_SPILL 12)
65 (UNSPEC_FR_RESTORE 13)
66 (UNSPEC_FR_RECIP_APPROX 14)
67 (UNSPEC_PRED_REL_MUTEX 15)
68 (UNSPEC_GETF_EXP 16)
69 (UNSPEC_PIC_CALL 17)
70 (UNSPEC_MF 18)
71 (UNSPEC_CMPXCHG_ACQ 19)
72 (UNSPEC_FETCHADD_ACQ 20)
73 (UNSPEC_BSP_VALUE 21)
74 (UNSPEC_FLUSHRS 22)
75 (UNSPEC_BUNDLE_SELECTOR 23)
76 (UNSPEC_ADDP4 24)
77 (UNSPEC_PROLOGUE_USE 25)
78 (UNSPEC_RET_ADDR 26)
79 (UNSPEC_SETF_EXP 27)
80 (UNSPEC_FR_SQRT_RECIP_APPROX 28)
81 (UNSPEC_SHRP 29)
82 (UNSPEC_COPYSIGN 30)
83 (UNSPEC_VECT_EXTR 31)
84 (UNSPEC_LDA 40)
85 (UNSPEC_LDS 41)
86 (UNSPEC_LDSA 42)
87 (UNSPEC_LDCCLR 43)
88 (UNSPEC_CHKACLR 45)
89 (UNSPEC_CHKS 47)
90 ])
92 (define_constants
93 [(UNSPECV_ALLOC 0)
94 (UNSPECV_BLOCKAGE 1)
95 (UNSPECV_INSN_GROUP_BARRIER 2)
96 (UNSPECV_BREAK 3)
97 (UNSPECV_SET_BSP 4)
98 (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls
99 (UNSPECV_PSAC_NORMAL 6)
100 (UNSPECV_SETJMP_RECEIVER 7)
101 ])
103 (include "predicates.md")
104 (include "constraints.md")
105 \f
106 ;; ::::::::::::::::::::
107 ;; ::
108 ;; :: Attributes
109 ;; ::
110 ;; ::::::::::::::::::::
112 ;; Processor type. This attribute must exactly match the processor_type
113 ;; enumeration in ia64.h.
114 (define_attr "cpu" "itanium,itanium2" (const (symbol_ref "ia64_tune")))
116 ;; Instruction type. This primarily determines how instructions can be
117 ;; packed in bundles, and secondarily affects scheduling to function units.
119 ;; A alu, can go in I or M syllable of a bundle
120 ;; I integer
121 ;; M memory
122 ;; F floating-point
123 ;; B branch
124 ;; L long immediate, takes two syllables
125 ;; S stop bit
127 ;; ??? Should not have any pattern with type unknown. Perhaps add code to
128 ;; check this in md_reorg? Currently use unknown for patterns which emit
129 ;; multiple instructions, patterns which emit 0 instructions, and patterns
130 ;; which emit instruction that can go in any slot (e.g. nop).
132 (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
133 fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,
134 ld,chk_s_i,chk_s_f,chk_a,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,
135 st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,
136 nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle"
137 (const_string "unknown"))
139 ;; chk_s_i has an I and an M form; use type A for convenience.
140 (define_attr "type" "unknown,A,I,M,F,B,L,X,S"
141 (cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M")
142 (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
143 (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
144 (eq_attr "itanium_class" "lfetch") (const_string "M")
145 (eq_attr "itanium_class" "chk_s_f,chk_a") (const_string "M")
146 (eq_attr "itanium_class" "chk_s_i,ialu,icmp,ilog,mmalua")
147 (const_string "A")
148 (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F")
149 (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F")
150 (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I")
151 (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I")
152 (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I")
153 (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B")
154 (eq_attr "itanium_class" "stop_bit") (const_string "S")
155 (eq_attr "itanium_class" "nop_x") (const_string "X")
156 (eq_attr "itanium_class" "long_i") (const_string "L")]
157 (const_string "unknown")))
159 (define_attr "itanium_requires_unit0" "no,yes"
160 (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes")
161 (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes")
162 (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes")
163 (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes")
164 (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes")
165 (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")]
166 (const_string "no")))
168 ;; Predication. True iff this instruction can be predicated.
170 (define_attr "predicable" "no,yes" (const_string "yes"))
172 ;; Empty. True iff this insn does not generate any code.
174 (define_attr "empty" "no,yes" (const_string "no"))
176 ;; True iff this insn must be the first insn of an instruction group.
177 ;; This is true for the alloc instruction, and will also be true of others
178 ;; when we have full intrinsics support.
180 (define_attr "first_insn" "no,yes" (const_string "no"))
182 (define_attr "data_speculative" "no,yes" (const_string "no"))
184 (define_attr "control_speculative" "no,yes" (const_string "no"))
186 (define_attr "check_load" "no,yes" (const_string "no"))
187 \f
188 ;; DFA descriptions of ia64 processors used for insn scheduling and
189 ;; bundling.
191 (automata_option "ndfa")
193 ;; Uncomment the following line to output automata for debugging.
194 ;; (automata_option "v")
196 (automata_option "w")
198 (include "itanium1.md")
199 (include "itanium2.md")
201 \f
202 ;; ::::::::::::::::::::
203 ;; ::
204 ;; :: Moves
205 ;; ::
206 ;; ::::::::::::::::::::
208 ;; Set of a single predicate register. This is only used to implement
209 ;; pr-to-pr move and complement.
211 (define_insn "*movcci"
212 [(set (match_operand:CCI 0 "register_operand" "=c,c,c")
213 (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))]
214 ""
215 "@
216 cmp.ne %0, p0 = r0, r0
217 cmp.eq %0, p0 = r0, r0
218 (%1) cmp.eq.unc %0, p0 = r0, r0"
219 [(set_attr "itanium_class" "icmp")
220 (set_attr "predicable" "no")])
222 (define_insn "movbi"
223 [(set (match_operand:BI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r")
224 (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))]
225 ""
226 "@
227 cmp.ne %0, %I0 = r0, r0
228 cmp.eq %0, %I0 = r0, r0
229 #
230 #
231 tbit.nz %0, %I0 = %1, 0
232 adds %0 = %1, r0
233 ld1%O1 %0 = %1%P1
234 st1%Q0 %0 = %1%P0
235 mov %0 = %1"
236 [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")])
238 (define_split
239 [(set (match_operand:BI 0 "register_operand" "")
240 (match_operand:BI 1 "register_operand" ""))]
241 "reload_completed
242 && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
243 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
244 [(cond_exec (ne (match_dup 1) (const_int 0))
245 (set (match_dup 0) (const_int 1)))
246 (cond_exec (eq (match_dup 1) (const_int 0))
247 (set (match_dup 0) (const_int 0)))]
248 "")
250 (define_split
251 [(set (match_operand:BI 0 "register_operand" "")
252 (match_operand:BI 1 "register_operand" ""))]
253 "reload_completed
254 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
255 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
256 [(set (match_dup 2) (match_dup 4))
257 (set (match_dup 3) (match_dup 5))
258 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
259 "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
260 operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
261 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
262 operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);")
264 (define_expand "movqi"
265 [(set (match_operand:QI 0 "general_operand" "")
266 (match_operand:QI 1 "general_operand" ""))]
267 ""
268 {
269 rtx op1 = ia64_expand_move (operands[0], operands[1]);
270 if (!op1)
271 DONE;
272 operands[1] = op1;
273 })
275 (define_insn "*movqi_internal"
276 [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
277 (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
278 "ia64_move_ok (operands[0], operands[1])"
279 "@
280 mov %0 = %r1
281 addl %0 = %1, r0
282 ld1%O1 %0 = %1%P1
283 st1%Q0 %0 = %r1%P0
284 getf.sig %0 = %1
285 setf.sig %0 = %r1
286 mov %0 = %1"
287 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
289 (define_expand "movhi"
290 [(set (match_operand:HI 0 "general_operand" "")
291 (match_operand:HI 1 "general_operand" ""))]
292 ""
293 {
294 rtx op1 = ia64_expand_move (operands[0], operands[1]);
295 if (!op1)
296 DONE;
297 operands[1] = op1;
298 })
300 (define_insn "*movhi_internal"
301 [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
302 (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
303 "ia64_move_ok (operands[0], operands[1])"
304 "@
305 mov %0 = %r1
306 addl %0 = %1, r0
307 ld2%O1 %0 = %1%P1
308 st2%Q0 %0 = %r1%P0
309 getf.sig %0 = %1
310 setf.sig %0 = %r1
311 mov %0 = %1"
312 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
314 (define_expand "movsi"
315 [(set (match_operand:SI 0 "general_operand" "")
316 (match_operand:SI 1 "general_operand" ""))]
317 ""
318 {
319 rtx op1 = ia64_expand_move (operands[0], operands[1]);
320 if (!op1)
321 DONE;
322 operands[1] = op1;
323 })
325 (define_insn "*movsi_internal"
326 [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
327 (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))]
328 "ia64_move_ok (operands[0], operands[1])"
329 "@
330 mov %0 = %r1
331 addl %0 = %1, r0
332 movl %0 = %1
333 ld4%O1 %0 = %1%P1
334 st4%Q0 %0 = %r1%P0
335 getf.sig %0 = %1
336 setf.sig %0 = %r1
337 mov %0 = %1
338 mov %0 = %1
339 mov %0 = %r1"
340 ;; frar_m, toar_m ??? why not frar_i and toar_i
341 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
343 (define_expand "movdi"
344 [(set (match_operand:DI 0 "general_operand" "")
345 (match_operand:DI 1 "general_operand" ""))]
346 ""
347 {
348 rtx op1 = ia64_expand_move (operands[0], operands[1]);
349 if (!op1)
350 DONE;
351 operands[1] = op1;
352 })
354 (define_insn "*movdi_internal"
355 [(set (match_operand:DI 0 "destination_operand"
356 "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
357 (match_operand:DI 1 "move_operand"
358 "rO,JT,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
359 "ia64_move_ok (operands[0], operands[1])"
360 {
361 static const char * const alt[] = {
362 "%,mov %0 = %r1",
363 "%,addl %0 = %1, r0",
364 "%,movl %0 = %1",
365 "%,ld8%O1 %0 = %1%P1",
366 "%,st8%Q0 %0 = %r1%P0",
367 "%,getf.sig %0 = %1",
368 "%,setf.sig %0 = %r1",
369 "%,mov %0 = %1",
370 "%,ldf8 %0 = %1%P1",
371 "%,stf8 %0 = %1%P0",
372 "%,mov %0 = %1",
373 "%,mov %0 = %r1",
374 "%,mov %0 = %1",
375 "%,mov %0 = %1",
376 "%,mov %0 = %1",
377 "%,mov %0 = %1",
378 "mov %0 = pr",
379 "mov pr = %1, -1"
380 };
382 gcc_assert (which_alternative != 2 || TARGET_NO_PIC
383 || !symbolic_operand (operands[1], VOIDmode));
385 return alt[which_alternative];
386 }
387 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
389 (define_mode_macro MODE [BI QI HI SI DI SF DF XF TI])
390 (define_mode_macro MODE_FOR_EXTEND [QI HI SI])
392 (define_mode_attr output_a [
393 (BI "ld1.a %0 = %1%P1")
394 (QI "ld1.a %0 = %1%P1")
395 (HI "ld2.a %0 = %1%P1")
396 (SI "ld4.a %0 = %1%P1")
397 (DI
398 "@
399 ld8.a %0 = %1%P1
400 ldf8.a %0 = %1%P1")
401 (SF
402 "@
403 ldfs.a %0 = %1%P1
404 ld4.a %0 = %1%P1")
405 (DF
406 "@
407 ldfd.a %0 = %1%P1
408 ld8.a %0 = %1%P1")
409 (XF "ldfe.a %0 = %1%P1")
410 (TI "ldfp8.a %X0 = %1%P1")])
412 (define_mode_attr output_s [
413 (BI "ld1.s %0 = %1%P1")
414 (QI "ld1.s %0 = %1%P1")
415 (HI "ld2.s %0 = %1%P1")
416 (SI "ld4.s %0 = %1%P1")
417 (DI
418 "@
419 ld8.s %0 = %1%P1
420 ldf8.s %0 = %1%P1")
421 (SF
422 "@
423 ldfs.s %0 = %1%P1
424 ld4.s %0 = %1%P1")
425 (DF
426 "@
427 ldfd.s %0 = %1%P1
428 ld8.s %0 = %1%P1")
429 (XF "ldfe.s %0 = %1%P1")
430 (TI "ldfp8.s %X0 = %1%P1")])
432 (define_mode_attr output_sa [
433 (BI "ld1.sa %0 = %1%P1")
434 (QI "ld1.sa %0 = %1%P1")
435 (HI "ld2.sa %0 = %1%P1")
436 (SI "ld4.sa %0 = %1%P1")
437 (DI
438 "@
439 ld8.sa %0 = %1%P1
440 ldf8.sa %0 = %1%P1")
441 (SF
442 "@
443 ldfs.sa %0 = %1%P1
444 ld4.sa %0 = %1%P1")
445 (DF
446 "@
447 ldfd.sa %0 = %1%P1
448 ld8.sa %0 = %1%P1")
449 (XF "ldfe.sa %0 = %1%P1")
450 (TI "ldfp8.sa %X0 = %1%P1")])
452 (define_mode_attr output_c_clr [
453 (BI "ld1.c.clr%O1 %0 = %1%P1")
454 (QI "ld1.c.clr%O1 %0 = %1%P1")
455 (HI "ld2.c.clr%O1 %0 = %1%P1")
456 (SI "ld4.c.clr%O1 %0 = %1%P1")
457 (DI
458 "@
459 ld8.c.clr%O1 %0 = %1%P1
460 ldf8.c.clr %0 = %1%P1")
461 (SF
462 "@
463 ldfs.c.clr %0 = %1%P1
464 ld4.c.clr%O1 %0 = %1%P1")
465 (DF
466 "@
467 ldfd.c.clr %0 = %1%P1
468 ld8.c.clr%O1 %0 = %1%P1")
469 (XF "ldfe.c.clr %0 = %1%P1")
470 (TI "ldfp8.c.clr %X0 = %1%P1")])
472 (define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")])
473 (define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")])
474 (define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")])
476 (define_mode_attr mem_constr [(BI "*m") (QI "m") (HI "m") (SI "m") (DI "m,Q") (SF "Q,m") (DF "Q,m") (XF "m") (TI "Q")])
478 ;; Define register predicate prefix.
479 ;; We can generate speculative loads only for general and fp registers - this
480 ;; is constrained in ia64.c: ia64_speculate_insn ().
481 (define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")])
483 (define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")])
484 (define_mode_attr chka_class [(BI "chk_a") (QI "chk_a") (HI "chk_a") (SI "chk_a") (DI "chk_a,chk_a") (SF "chk_a,chk_a") (DF "chk_a,chk_a") (XF "chk_a") (TI "chk_a")])
485 (define_mode_attr chks_class [(BI "chk_s_i") (QI "chk_s_i") (HI "chk_s_i") (SI "chk_s_i") (DI "chk_s_i,chk_s_f") (SF "chk_s_f,chk_s_i") (DF "chk_s_f,chk_s_i") (XF "chk_s_f") (TI "chk_s_i")])
487 (define_mode_attr attr_yes [(BI "yes") (QI "yes") (HI "yes") (SI "yes") (DI "yes,yes") (SF "yes,yes") (DF "yes,yes") (XF "yes") (TI "yes")])
489 (define_insn "mov<mode>_advanced"
490 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
491 (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA))]
492 "ia64_move_ok (operands[0], operands[1])"
493 "<output_a>"
494 [(set_attr "itanium_class" "<ld_class>")
495 (set_attr "data_speculative" "<attr_yes>")])
497 (define_insn "zero_extend<mode>di2_advanced"
498 [(set (match_operand:DI 0 "gr_register_operand" "=r")
499 (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA)))]
500 ""
501 "<output_a>"
502 [(set_attr "itanium_class" "<ld_class>")
503 (set_attr "data_speculative" "<attr_yes>")])
505 (define_insn "mov<mode>_speculative"
506 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
507 (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS))]
508 "ia64_move_ok (operands[0], operands[1])"
509 "<output_s>"
510 [(set_attr "itanium_class" "<ld_class>")
511 (set_attr "control_speculative" "<attr_yes>")])
513 (define_insn "zero_extend<mode>di2_speculative"
514 [(set (match_operand:DI 0 "gr_register_operand" "=r")
515 (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS)))]
516 ""
517 "<output_s>"
518 [(set_attr "itanium_class" "<ld_class>")
519 (set_attr "control_speculative" "<attr_yes>")])
521 (define_insn "mov<mode>_speculative_advanced"
522 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
523 (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA))]
524 "ia64_move_ok (operands[0], operands[1])"
525 "<output_sa>"
526 [(set_attr "itanium_class" "<ld_class>")
527 (set_attr "data_speculative" "<attr_yes>")
528 (set_attr "control_speculative" "<attr_yes>")])
530 (define_insn "zero_extend<mode>di2_speculative_advanced"
531 [(set (match_operand:DI 0 "gr_register_operand" "=r")
532 (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))]
533 ""
534 "<output_sa>"
535 [(set_attr "itanium_class" "<ld_class>")
536 (set_attr "data_speculative" "<attr_yes>")
537 (set_attr "control_speculative" "<attr_yes>")])
539 (define_insn "mov<mode>_clr"
540 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>")
541 (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
542 (match_operand:MODE 1 "memory_operand" "<mem_constr>")
543 (match_dup 0)))]
544 "ia64_move_ok (operands[0], operands[1])"
545 "<output_c_clr>"
546 [(set_attr "itanium_class" "<ld_class>")
547 (set_attr "check_load" "<attr_yes>")])
549 (define_insn "zero_extend<mode>di2_clr"
550 [(set (match_operand:DI 0 "gr_register_operand" "+r")
551 (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
552 (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>"))
553 (match_dup 0)))]
554 ""
555 "<output_c_clr>"
556 [(set_attr "itanium_class" "<ld_class>")
557 (set_attr "check_load" "<attr_yes>")])
559 (define_insn "advanced_load_check_clr_<mode>"
560 [(set (pc)
561 (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0))
562 (pc)
563 (label_ref (match_operand 1 "" ""))))]
564 ""
565 "chk.a.clr %0, %l1"
566 [(set_attr "itanium_class" "<chka_class>")])
568 (define_insn "speculation_check_<mode>"
569 [(set (pc)
570 (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0))
571 (pc)
572 (label_ref (match_operand 1 "" ""))))]
573 ""
574 "chk.s %0, %l1"
575 [(set_attr "itanium_class" "<chks_class>")])
577 (define_split
578 [(set (match_operand 0 "register_operand" "")
579 (match_operand 1 "symbolic_operand" ""))]
580 "reload_completed"
581 [(const_int 0)]
582 {
583 if (ia64_expand_load_address (operands[0], operands[1]))
584 DONE;
585 else
586 FAIL;
587 })
589 (define_expand "load_fptr"
590 [(set (match_operand:DI 0 "register_operand" "")
591 (plus:DI (match_dup 2) (match_operand 1 "function_operand" "")))
592 (set (match_dup 0) (match_dup 3))]
593 "reload_completed"
594 {
595 operands[2] = pic_offset_table_rtx;
596 operands[3] = gen_const_mem (DImode, operands[0]);
597 })
599 (define_insn "*load_fptr_internal1"
600 [(set (match_operand:DI 0 "register_operand" "=r")
601 (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))]
602 "reload_completed"
603 "addl %0 = @ltoff(@fptr(%1)), gp"
604 [(set_attr "itanium_class" "ialu")])
606 (define_insn "load_gprel"
607 [(set (match_operand:DI 0 "register_operand" "=r")
608 (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))]
609 "reload_completed"
610 "addl %0 = @gprel(%1), gp"
611 [(set_attr "itanium_class" "ialu")])
613 (define_insn "*gprel64_offset"
614 [(set (match_operand:DI 0 "register_operand" "=r")
615 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))]
616 "reload_completed"
617 "movl %0 = @gprel(%1)"
618 [(set_attr "itanium_class" "long_i")])
620 (define_expand "load_gprel64"
621 [(set (match_operand:DI 0 "register_operand" "")
622 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 2)))
623 (set (match_dup 0)
624 (plus:DI (match_dup 2) (match_dup 0)))]
625 "reload_completed"
626 {
627 operands[2] = pic_offset_table_rtx;
628 })
630 ;; This is used as a placeholder for the return address during early
631 ;; compilation. We won't know where we've placed this until during
632 ;; reload, at which point it can wind up in b0, a general register,
633 ;; or memory. The only safe destination under these conditions is a
634 ;; general register.
636 (define_insn_and_split "*movdi_ret_addr"
637 [(set (match_operand:DI 0 "register_operand" "=r")
638 (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))]
639 ""
640 "#"
641 "reload_completed"
642 [(const_int 0)]
643 {
644 ia64_split_return_addr_rtx (operands[0]);
645 DONE;
646 }
647 [(set_attr "itanium_class" "ialu")])
649 (define_insn "*load_symptr_high"
650 [(set (match_operand:DI 0 "register_operand" "=r")
651 (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s"))
652 (match_operand:DI 2 "register_operand" "a")))]
653 "reload_completed"
654 {
655 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
656 return "%,addl %0 = @ltoffx(%1), %2";
657 else
658 return "%,addl %0 = @ltoff(%1), %2";
659 }
660 [(set_attr "itanium_class" "ialu")])
662 (define_insn "*load_symptr_low"
663 [(set (match_operand:DI 0 "register_operand" "=r")
664 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
665 (match_operand 2 "got_symbolic_operand" "s")))]
666 "reload_completed"
667 {
668 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
669 return "%,ld8.mov %0 = [%1], %2";
670 else
671 return "%,ld8 %0 = [%1]";
672 }
673 [(set_attr "itanium_class" "ld")])
675 (define_insn_and_split "load_dtpmod"
676 [(set (match_operand:DI 0 "register_operand" "=r")
677 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
678 UNSPEC_DTPMOD))]
679 ""
680 "#"
681 "reload_completed"
682 [(set (match_dup 0)
683 (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPMOD)
684 (match_dup 2)))
685 (set (match_dup 0) (match_dup 3))]
686 {
687 operands[2] = pic_offset_table_rtx;
688 operands[3] = gen_const_mem (DImode, operands[0]);
689 })
691 (define_insn "*load_ltoff_dtpmod"
692 [(set (match_operand:DI 0 "register_operand" "=r")
693 (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
694 UNSPEC_LTOFF_DTPMOD)
695 (match_operand:DI 2 "register_operand" "a")))]
696 "reload_completed"
697 "addl %0 = @ltoff(@dtpmod(%1)), %2"
698 [(set_attr "itanium_class" "ialu")])
700 (define_expand "load_dtprel"
701 [(set (match_operand:DI 0 "register_operand" "")
702 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
703 UNSPEC_DTPREL))]
704 ""
705 "")
707 (define_insn "*load_dtprel64"
708 [(set (match_operand:DI 0 "register_operand" "=r")
709 (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
710 UNSPEC_DTPREL))]
711 "TARGET_TLS64"
712 "movl %0 = @dtprel(%1)"
713 [(set_attr "itanium_class" "long_i")])
715 (define_insn "*load_dtprel22"
716 [(set (match_operand:DI 0 "register_operand" "=r")
717 (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
718 UNSPEC_DTPREL))]
719 ""
720 "addl %0 = @dtprel(%1), r0"
721 [(set_attr "itanium_class" "ialu")])
723 (define_insn_and_split "*load_dtprel_gd"
724 [(set (match_operand:DI 0 "register_operand" "=r")
725 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
726 UNSPEC_DTPREL))]
727 ""
728 "#"
729 "reload_completed"
730 [(set (match_dup 0)
731 (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPREL)
732 (match_dup 2)))
733 (set (match_dup 0) (match_dup 3))]
734 {
735 operands[2] = pic_offset_table_rtx;
736 operands[3] = gen_const_mem (DImode, operands[0]);
737 })
739 (define_insn "*load_ltoff_dtprel"
740 [(set (match_operand:DI 0 "register_operand" "=r")
741 (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
742 UNSPEC_LTOFF_DTPREL)
743 (match_operand:DI 2 "register_operand" "a")))]
744 ""
745 "addl %0 = @ltoff(@dtprel(%1)), %2"
746 [(set_attr "itanium_class" "ialu")])
748 (define_expand "add_dtprel"
749 [(set (match_operand:DI 0 "register_operand" "")
750 (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
751 UNSPEC_DTPREL)
752 (match_operand:DI 2 "register_operand" "")))]
753 "!TARGET_TLS64"
754 "")
756 (define_insn "*add_dtprel14"
757 [(set (match_operand:DI 0 "register_operand" "=r")
758 (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
759 UNSPEC_DTPREL)
760 (match_operand:DI 2 "register_operand" "r")))]
761 "TARGET_TLS14"
762 "adds %0 = @dtprel(%1), %2"
763 [(set_attr "itanium_class" "ialu")])
765 (define_insn "*add_dtprel22"
766 [(set (match_operand:DI 0 "register_operand" "=r")
767 (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
768 UNSPEC_DTPREL)
769 (match_operand:DI 2 "register_operand" "a")))]
770 "TARGET_TLS22"
771 "addl %0 = @dtprel(%1), %2"
772 [(set_attr "itanium_class" "ialu")])
774 (define_expand "load_tprel"
775 [(set (match_operand:DI 0 "register_operand" "")
776 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
777 UNSPEC_TPREL))]
778 ""
779 "")
781 (define_insn "*load_tprel64"
782 [(set (match_operand:DI 0 "register_operand" "=r")
783 (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
784 UNSPEC_TPREL))]
785 "TARGET_TLS64"
786 "movl %0 = @tprel(%1)"
787 [(set_attr "itanium_class" "long_i")])
789 (define_insn "*load_tprel22"
790 [(set (match_operand:DI 0 "register_operand" "=r")
791 (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
792 UNSPEC_TPREL))]
793 ""
794 "addl %0 = @tprel(%1), r0"
795 [(set_attr "itanium_class" "ialu")])
797 (define_insn_and_split "*load_tprel_ie"
798 [(set (match_operand:DI 0 "register_operand" "=r")
799 (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")]
800 UNSPEC_TPREL))]
801 ""
802 "#"
803 "reload_completed"
804 [(set (match_dup 0)
805 (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_TPREL)
806 (match_dup 2)))
807 (set (match_dup 0) (match_dup 3))]
808 {
809 operands[2] = pic_offset_table_rtx;
810 operands[3] = gen_const_mem (DImode, operands[0]);
811 })
813 (define_insn "*load_ltoff_tprel"
814 [(set (match_operand:DI 0 "register_operand" "=r")
815 (plus:DI (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")]
816 UNSPEC_LTOFF_TPREL)
817 (match_operand:DI 2 "register_operand" "a")))]
818 ""
819 "addl %0 = @ltoff(@tprel(%1)), %2"
820 [(set_attr "itanium_class" "ialu")])
822 (define_expand "add_tprel"
823 [(set (match_operand:DI 0 "register_operand" "")
824 (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
825 UNSPEC_TPREL)
826 (match_operand:DI 2 "register_operand" "")))]
827 "!TARGET_TLS64"
828 "")
830 (define_insn "*add_tprel14"
831 [(set (match_operand:DI 0 "register_operand" "=r")
832 (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
833 UNSPEC_TPREL)
834 (match_operand:DI 2 "register_operand" "r")))]
835 "TARGET_TLS14"
836 "adds %0 = @tprel(%1), %2"
837 [(set_attr "itanium_class" "ialu")])
839 (define_insn "*add_tprel22"
840 [(set (match_operand:DI 0 "register_operand" "=r")
841 (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
842 UNSPEC_TPREL)
843 (match_operand:DI 2 "register_operand" "a")))]
844 "TARGET_TLS22"
845 "addl %0 = @tprel(%1), %2"
846 [(set_attr "itanium_class" "ialu")])
848 ;; With no offsettable memory references, we've got to have a scratch
849 ;; around to play with the second word. However, in order to avoid a
850 ;; reload nightmare we lie, claim we don't need one, and fix it up
851 ;; in ia64_split_tmode_move.
852 (define_expand "movti"
853 [(set (match_operand:TI 0 "general_operand" "")
854 (match_operand:TI 1 "general_operand" ""))]
855 ""
856 {
857 rtx op1 = ia64_expand_move (operands[0], operands[1]);
858 if (!op1)
859 DONE;
860 operands[1] = op1;
861 })
863 (define_insn_and_split "*movti_internal"
864 [(set (match_operand:TI 0 "destination_operand" "=r, *fm,*x,*f, Q")
865 (match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))]
866 "ia64_move_ok (operands[0], operands[1])"
867 "@
868 #
869 #
870 ldfp8 %X0 = %1%P1
871 #
872 #"
873 "reload_completed && !ia64_load_pair_ok(operands[0], operands[1])"
874 [(const_int 0)]
875 {
876 ia64_split_tmode_move (operands);
877 DONE;
878 }
879 [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")])
881 ;; Floating Point Moves
882 ;;
883 ;; Note - Patterns for SF mode moves are compulsory, but
884 ;; patterns for DF are optional, as GCC can synthesize them.
886 (define_expand "movsf"
887 [(set (match_operand:SF 0 "general_operand" "")
888 (match_operand:SF 1 "general_operand" ""))]
889 ""
890 {
891 rtx op1 = ia64_expand_move (operands[0], operands[1]);
892 if (!op1)
893 DONE;
894 operands[1] = op1;
895 })
897 (define_insn "*movsf_internal"
898 [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
899 (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
900 "ia64_move_ok (operands[0], operands[1])"
901 "@
902 mov %0 = %F1
903 ldfs %0 = %1%P1
904 stfs %0 = %F1%P0
905 getf.s %0 = %F1
906 setf.s %0 = %1
907 mov %0 = %1
908 ld4%O1 %0 = %1%P1
909 st4%Q0 %0 = %1%P0"
910 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
912 (define_expand "movdf"
913 [(set (match_operand:DF 0 "general_operand" "")
914 (match_operand:DF 1 "general_operand" ""))]
915 ""
916 {
917 rtx op1 = ia64_expand_move (operands[0], operands[1]);
918 if (!op1)
919 DONE;
920 operands[1] = op1;
921 })
923 (define_insn "*movdf_internal"
924 [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
925 (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
926 "ia64_move_ok (operands[0], operands[1])"
927 "@
928 mov %0 = %F1
929 ldfd %0 = %1%P1
930 stfd %0 = %F1%P0
931 getf.d %0 = %F1
932 setf.d %0 = %1
933 mov %0 = %1
934 ld8%O1 %0 = %1%P1
935 st8%Q0 %0 = %1%P0"
936 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
938 ;; With no offsettable memory references, we've got to have a scratch
939 ;; around to play with the second word if the variable winds up in GRs.
940 (define_expand "movxf"
941 [(set (match_operand:XF 0 "general_operand" "")
942 (match_operand:XF 1 "general_operand" ""))]
943 ""
944 {
945 if (ia64_expand_movxf_movrf (XFmode, operands))
946 DONE;
947 })
949 ;; ??? There's no easy way to mind volatile acquire/release semantics.
951 (define_insn "*movxf_internal"
952 [(set (match_operand:XF 0 "destination_operand" "=f,f, m")
953 (match_operand:XF 1 "general_operand" "fG,m,fG"))]
954 "ia64_move_ok (operands[0], operands[1])"
955 "@
956 mov %0 = %F1
957 ldfe %0 = %1%P1
958 stfe %0 = %F1%P0"
959 [(set_attr "itanium_class" "fmisc,fld,stf")])
961 ;; Same as for movxf, but for RFmode.
962 (define_expand "movrf"
963 [(set (match_operand:RF 0 "general_operand" "")
964 (match_operand:RF 1 "general_operand" ""))]
965 ""
966 {
967 if (ia64_expand_movxf_movrf (RFmode, operands))
968 DONE;
969 })
971 (define_insn "*movrf_internal"
972 [(set (match_operand:RF 0 "destination_operand" "=f,f, m")
973 (match_operand:RF 1 "general_operand" "fG,m,fG"))]
974 "ia64_move_ok (operands[0], operands[1])"
975 "@
976 mov %0 = %F1
977 ldf.fill %0 = %1%P1
978 stf.spill %0 = %F1%P0"
979 [(set_attr "itanium_class" "fmisc,fld,stf")])
981 ;; Better code generation via insns that deal with TFmode register pairs
982 ;; directly. Same concerns apply as for TImode.
983 (define_expand "movtf"
984 [(set (match_operand:TF 0 "general_operand" "")
985 (match_operand:TF 1 "general_operand" ""))]
986 ""
987 {
988 rtx op1 = ia64_expand_move (operands[0], operands[1]);
989 if (!op1)
990 DONE;
991 operands[1] = op1;
992 })
994 (define_insn_and_split "*movtf_internal"
995 [(set (match_operand:TF 0 "destination_operand" "=r,r,m")
996 (match_operand:TF 1 "general_operand" "ri,m,r"))]
997 "ia64_move_ok (operands[0], operands[1])"
998 "#"
999 "reload_completed"
1000 [(const_int 0)]
1001 {
1002 ia64_split_tmode_move (operands);
1003 DONE;
1004 }
1005 [(set_attr "itanium_class" "unknown")
1006 (set_attr "predicable" "no")])
1008 \f
1009 ;; ::::::::::::::::::::
1010 ;; ::
1011 ;; :: Conversions
1012 ;; ::
1013 ;; ::::::::::::::::::::
1015 ;; Signed conversions from a smaller integer to a larger integer
1017 (define_insn "extendqidi2"
1018 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1019 (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))]
1020 ""
1021 "sxt1 %0 = %1"
1022 [(set_attr "itanium_class" "xtd")])
1024 (define_insn "extendhidi2"
1025 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1026 (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))]
1027 ""
1028 "sxt2 %0 = %1"
1029 [(set_attr "itanium_class" "xtd")])
1031 (define_insn "extendsidi2"
1032 [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f")
1033 (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))]
1034 ""
1035 "@
1036 sxt4 %0 = %1
1037 fsxt.r %0 = %1, %1"
1038 [(set_attr "itanium_class" "xtd,fmisc")])
1040 ;; Unsigned conversions from a smaller integer to a larger integer
1042 (define_insn "zero_extendqidi2"
1043 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
1044 (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))]
1045 ""
1046 "@
1047 zxt1 %0 = %1
1048 ld1%O1 %0 = %1%P1"
1049 [(set_attr "itanium_class" "xtd,ld")])
1051 (define_insn "zero_extendhidi2"
1052 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
1053 (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))]
1054 ""
1055 "@
1056 zxt2 %0 = %1
1057 ld2%O1 %0 = %1%P1"
1058 [(set_attr "itanium_class" "xtd,ld")])
1060 (define_insn "zero_extendsidi2"
1061 [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f")
1062 (zero_extend:DI
1063 (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))]
1064 ""
1065 "@
1066 addp4 %0 = %1, r0
1067 ld4%O1 %0 = %1%P1
1068 fmix.r %0 = f0, %1"
1069 [(set_attr "itanium_class" "ialu,ld,fmisc")])
1071 ;; Convert between floating point types of different sizes.
1073 ;; At first glance, it would appear that emitting fnorm for an extending
1074 ;; conversion is unnecessary. However, the stf and getf instructions work
1075 ;; correctly only if the input is properly rounded for its type. In
1076 ;; particular, we get the wrong result for getf.d/stfd if the input is a
1077 ;; denorm single. Since we don't know what the next instruction will be, we
1078 ;; have to emit an fnorm.
1080 ;; ??? Optimization opportunity here. Get rid of the insn altogether
1081 ;; when we can. Should probably use a scheme like has been proposed
1082 ;; for ia32 in dealing with operands that match unary operators. This
1083 ;; would let combine merge the thing into adjacent insns. See also how the
1084 ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via
1085 ;; se_register_operand.
1087 (define_insn "extendsfdf2"
1088 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1089 (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))]
1090 ""
1091 "fnorm.d %0 = %1"
1092 [(set_attr "itanium_class" "fmac")])
1094 (define_insn "extendsfxf2"
1095 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1096 (float_extend:XF (match_operand:SF 1 "fr_register_operand" "f")))]
1097 ""
1098 "fnorm %0 = %1"
1099 [(set_attr "itanium_class" "fmac")])
1101 (define_insn "extenddfxf2"
1102 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1103 (float_extend:XF (match_operand:DF 1 "fr_register_operand" "f")))]
1104 ""
1105 "fnorm %0 = %1"
1106 [(set_attr "itanium_class" "fmac")])
1108 (define_insn "truncdfsf2"
1109 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1110 (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))]
1111 ""
1112 "fnorm.s %0 = %1"
1113 [(set_attr "itanium_class" "fmac")])
1115 (define_insn "truncxfsf2"
1116 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1117 (float_truncate:SF (match_operand:XF 1 "fr_register_operand" "f")))]
1118 ""
1119 "fnorm.s %0 = %1"
1120 [(set_attr "itanium_class" "fmac")])
1122 (define_insn "truncxfdf2"
1123 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1124 (float_truncate:DF (match_operand:XF 1 "fr_register_operand" "f")))]
1125 ""
1126 "fnorm.d %0 = %1"
1127 [(set_attr "itanium_class" "fmac")])
1129 ;; Convert between signed integer types and floating point.
1131 (define_insn "floatdixf2"
1132 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1133 (float:XF (match_operand:DI 1 "fr_register_operand" "f")))]
1134 ""
1135 "fcvt.xf %0 = %1"
1136 [(set_attr "itanium_class" "fcvtfx")])
1138 (define_insn "fix_truncsfdi2"
1139 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1140 (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
1141 ""
1142 "fcvt.fx.trunc %0 = %1"
1143 [(set_attr "itanium_class" "fcvtfx")])
1145 (define_insn "fix_truncdfdi2"
1146 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1147 (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
1148 ""
1149 "fcvt.fx.trunc %0 = %1"
1150 [(set_attr "itanium_class" "fcvtfx")])
1152 (define_insn "fix_truncxfdi2"
1153 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1154 (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))]
1155 ""
1156 "fcvt.fx.trunc %0 = %1"
1157 [(set_attr "itanium_class" "fcvtfx")])
1159 (define_insn "fix_truncxfdi2_alts"
1160 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1161 (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))
1162 (use (match_operand:SI 2 "const_int_operand" ""))]
1163 ""
1164 "fcvt.fx.trunc.s%2 %0 = %1"
1165 [(set_attr "itanium_class" "fcvtfx")])
1167 ;; Convert between unsigned integer types and floating point.
1169 (define_insn "floatunsdisf2"
1170 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1171 (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))]
1172 ""
1173 "fcvt.xuf.s %0 = %1"
1174 [(set_attr "itanium_class" "fcvtfx")])
1176 (define_insn "floatunsdidf2"
1177 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1178 (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))]
1179 ""
1180 "fcvt.xuf.d %0 = %1"
1181 [(set_attr "itanium_class" "fcvtfx")])
1183 (define_insn "floatunsdixf2"
1184 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1185 (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "f")))]
1186 ""
1187 "fcvt.xuf %0 = %1"
1188 [(set_attr "itanium_class" "fcvtfx")])
1190 (define_insn "fixuns_truncsfdi2"
1191 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1192 (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
1193 ""
1194 "fcvt.fxu.trunc %0 = %1"
1195 [(set_attr "itanium_class" "fcvtfx")])
1197 (define_insn "fixuns_truncdfdi2"
1198 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1199 (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
1200 ""
1201 "fcvt.fxu.trunc %0 = %1"
1202 [(set_attr "itanium_class" "fcvtfx")])
1204 (define_insn "fixuns_truncxfdi2"
1205 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1206 (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))]
1207 ""
1208 "fcvt.fxu.trunc %0 = %1"
1209 [(set_attr "itanium_class" "fcvtfx")])
1211 (define_insn "fixuns_truncxfdi2_alts"
1212 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1213 (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))
1214 (use (match_operand:SI 2 "const_int_operand" ""))]
1215 ""
1216 "fcvt.fxu.trunc.s%2 %0 = %1"
1217 [(set_attr "itanium_class" "fcvtfx")])
1218 \f
1219 ;; ::::::::::::::::::::
1220 ;; ::
1221 ;; :: Bit field extraction
1222 ;; ::
1223 ;; ::::::::::::::::::::
1225 (define_insn "extv"
1226 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1227 (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1228 (match_operand:DI 2 "extr_len_operand" "n")
1229 (match_operand:DI 3 "shift_count_operand" "M")))]
1230 ""
1231 "extr %0 = %1, %3, %2"
1232 [(set_attr "itanium_class" "ishf")])
1234 (define_insn "extzv"
1235 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1236 (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1237 (match_operand:DI 2 "extr_len_operand" "n")
1238 (match_operand:DI 3 "shift_count_operand" "M")))]
1239 ""
1240 "extr.u %0 = %1, %3, %2"
1241 [(set_attr "itanium_class" "ishf")])
1243 ;; Insert a bit field.
1244 ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest.
1245 ;; Source1 can be 0 or -1.
1246 ;; Source2 can be 0.
1248 ;; ??? Actual dep instruction is more powerful than what these insv
1249 ;; patterns support. Unfortunately, combine is unable to create patterns
1250 ;; where source2 != dest.
1252 (define_expand "insv"
1253 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "")
1254 (match_operand:DI 1 "const_int_operand" "")
1255 (match_operand:DI 2 "const_int_operand" ""))
1256 (match_operand:DI 3 "nonmemory_operand" ""))]
1257 ""
1258 {
1259 int width = INTVAL (operands[1]);
1260 int shift = INTVAL (operands[2]);
1262 /* If operand[3] is a constant, and isn't 0 or -1, then load it into a
1263 pseudo. */
1264 if (! register_operand (operands[3], DImode)
1265 && operands[3] != const0_rtx && operands[3] != constm1_rtx)
1266 operands[3] = force_reg (DImode, operands[3]);
1268 /* If this is a single dep instruction, we have nothing to do. */
1269 if (! ((register_operand (operands[3], DImode) && width <= 16)
1270 || operands[3] == const0_rtx || operands[3] == constm1_rtx))
1271 {
1272 /* Check for cases that can be implemented with a mix instruction. */
1273 if (width == 32 && shift == 0)
1274 {
1275 /* Directly generating the mix4left instruction confuses
1276 optimize_bit_field in function.c. Since this is performing
1277 a useful optimization, we defer generation of the complicated
1278 mix4left RTL to the first splitting phase. */
1279 rtx tmp = gen_reg_rtx (DImode);
1280 emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp));
1281 DONE;
1282 }
1283 else if (width == 32 && shift == 32)
1284 {
1285 emit_insn (gen_mix4right (operands[0], operands[3]));
1286 DONE;
1287 }
1289 /* We could handle remaining cases by emitting multiple dep
1290 instructions.
1292 If we need more than two dep instructions then we lose. A 6
1293 insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than
1294 mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles,
1295 the latter is 6 cycles on an Itanium (TM) processor, because there is
1296 only one function unit that can execute dep and shr immed.
1298 If we only need two dep instruction, then we still lose.
1299 mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away
1300 the unnecessary mov, this is still undesirable because it will be
1301 hard to optimize, and it creates unnecessary pressure on the I0
1302 function unit. */
1304 FAIL;
1306 #if 0
1307 /* This code may be useful for other IA-64 processors, so we leave it in
1308 for now. */
1309 while (width > 16)
1310 {
1311 rtx tmp;
1313 emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift),
1314 operands[3]));
1315 shift += 16;
1316 width -= 16;
1317 tmp = gen_reg_rtx (DImode);
1318 emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16)));
1319 operands[3] = tmp;
1320 }
1321 operands[1] = GEN_INT (width);
1322 operands[2] = GEN_INT (shift);
1323 #endif
1324 }
1325 })
1327 (define_insn "*insv_internal"
1328 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1329 (match_operand:DI 1 "const_int_operand" "n")
1330 (match_operand:DI 2 "const_int_operand" "n"))
1331 (match_operand:DI 3 "nonmemory_operand" "rP"))]
1332 "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16)
1333 || operands[3] == const0_rtx || operands[3] == constm1_rtx"
1334 "dep %0 = %3, %0, %2, %1"
1335 [(set_attr "itanium_class" "ishf")])
1337 ;; Combine doesn't like to create bit-field insertions into zero.
1338 (define_insn "*shladdp4_internal"
1339 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1340 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
1341 (match_operand:DI 2 "shladd_log2_operand" "n"))
1342 (match_operand:DI 3 "const_int_operand" "n")))]
1343 "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32"
1344 "shladdp4 %0 = %1, %2, r0"
1345 [(set_attr "itanium_class" "ialu")])
1347 (define_insn "*depz_internal"
1348 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1349 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
1350 (match_operand:DI 2 "const_int_operand" "M"))
1351 (match_operand:DI 3 "const_int_operand" "n")))]
1352 "satisfies_constraint_M (operands[2])
1353 && ia64_depz_field_mask (operands[3], operands[2]) > 0"
1354 {
1355 operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
1356 return "%,dep.z %0 = %1, %2, %3";
1357 }
1358 [(set_attr "itanium_class" "ishf")])
1360 (define_insn "shift_mix4left"
1361 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1362 (const_int 32) (const_int 0))
1363 (match_operand:DI 1 "gr_register_operand" "r"))
1364 (clobber (match_operand:DI 2 "gr_register_operand" "=r"))]
1365 ""
1366 "#"
1367 [(set_attr "itanium_class" "unknown")])
1369 (define_split
1370 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1371 (const_int 32) (const_int 0))
1372 (match_operand:DI 1 "register_operand" ""))
1373 (clobber (match_operand:DI 2 "register_operand" ""))]
1374 ""
1375 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
1376 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1377 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1378 "operands[3] = operands[2];")
1380 (define_insn "*mix4left"
1381 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1382 (const_int 32) (const_int 0))
1383 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r")
1384 (const_int 32)))]
1385 ""
1386 "mix4.l %0 = %0, %r1"
1387 [(set_attr "itanium_class" "mmshf")])
1389 (define_insn "mix4right"
1390 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1391 (const_int 32) (const_int 32))
1392 (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))]
1393 ""
1394 "mix4.r %0 = %r1, %0"
1395 [(set_attr "itanium_class" "mmshf")])
1397 ;; This is used by the rotrsi3 pattern.
1399 (define_insn "*mix4right_3op"
1400 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1401 (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r"))
1402 (ashift:DI (zero_extend:DI
1403 (match_operand:SI 2 "gr_register_operand" "r"))
1404 (const_int 32))))]
1405 ""
1406 "mix4.r %0 = %2, %1"
1407 [(set_attr "itanium_class" "mmshf")])
1409 \f
1410 ;; ::::::::::::::::::::
1411 ;; ::
1412 ;; :: 1-bit Integer arithmetic
1413 ;; ::
1414 ;; ::::::::::::::::::::
1416 (define_insn_and_split "andbi3"
1417 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1418 (and:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1419 (match_operand:BI 2 "register_operand" "c,r,r")))]
1420 ""
1421 "@
1422 #
1423 tbit.nz.and.orcm %0, %I0 = %2, 0
1424 and %0 = %2, %1"
1425 "reload_completed
1426 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1427 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1428 [(cond_exec (eq (match_dup 2) (const_int 0))
1429 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1430 (match_dup 0))))]
1431 ""
1432 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1434 (define_insn_and_split "*andcmbi3"
1435 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1436 (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r"))
1437 (match_operand:BI 2 "register_operand" "0,0,r")))]
1438 ""
1439 "@
1440 #
1441 tbit.z.and.orcm %0, %I0 = %1, 0
1442 andcm %0 = %2, %1"
1443 "reload_completed
1444 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1445 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
1446 [(cond_exec (ne (match_dup 1) (const_int 0))
1447 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1448 (match_dup 0))))]
1449 ""
1450 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1452 (define_insn_and_split "iorbi3"
1453 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1454 (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1455 (match_operand:BI 2 "register_operand" "c,r,r")))]
1456 ""
1457 "@
1458 #
1459 tbit.nz.or.andcm %0, %I0 = %2, 0
1460 or %0 = %2, %1"
1461 "reload_completed
1462 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1463 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1464 [(cond_exec (ne (match_dup 2) (const_int 0))
1465 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1466 (match_dup 0))))]
1467 ""
1468 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1470 (define_insn_and_split "*iorcmbi3"
1471 [(set (match_operand:BI 0 "register_operand" "=c,c")
1472 (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r"))
1473 (match_operand:BI 2 "register_operand" "0,0")))]
1474 ""
1475 "@
1476 #
1477 tbit.z.or.andcm %0, %I0 = %1, 0"
1478 "reload_completed
1479 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1480 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
1481 [(cond_exec (eq (match_dup 1) (const_int 0))
1482 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1483 (match_dup 0))))]
1484 ""
1485 [(set_attr "itanium_class" "unknown,tbit")])
1487 (define_insn "one_cmplbi2"
1488 [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c")
1489 (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c")))
1490 (clobber (match_scratch:BI 2 "=X,X,c,X"))]
1491 ""
1492 "@
1493 tbit.z %0, %I0 = %1, 0
1494 xor %0 = 1, %1
1495 #
1496 #"
1497 [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")])
1499 (define_split
1500 [(set (match_operand:BI 0 "register_operand" "")
1501 (not:BI (match_operand:BI 1 "register_operand" "")))
1502 (clobber (match_scratch:BI 2 ""))]
1503 "reload_completed
1504 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1505 && rtx_equal_p (operands[0], operands[1])"
1506 [(set (match_dup 4) (match_dup 3))
1507 (set (match_dup 0) (const_int 1))
1508 (cond_exec (ne (match_dup 2) (const_int 0))
1509 (set (match_dup 0) (const_int 0)))
1510 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
1511 "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
1512 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
1514 (define_split
1515 [(set (match_operand:BI 0 "register_operand" "")
1516 (not:BI (match_operand:BI 1 "register_operand" "")))
1517 (clobber (match_scratch:BI 2 ""))]
1518 "reload_completed
1519 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1520 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
1521 && ! rtx_equal_p (operands[0], operands[1])"
1522 [(cond_exec (ne (match_dup 1) (const_int 0))
1523 (set (match_dup 0) (const_int 0)))
1524 (cond_exec (eq (match_dup 1) (const_int 0))
1525 (set (match_dup 0) (const_int 1)))
1526 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
1527 "")
1529 (define_insn "*cmpsi_and_0"
1530 [(set (match_operand:BI 0 "register_operand" "=c")
1531 (and:BI (match_operator:BI 4 "predicate_operator"
1532 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1533 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1534 (match_operand:BI 1 "register_operand" "0")))]
1535 ""
1536 "cmp4.%C4.and.orcm %0, %I0 = %3, %r2"
1537 [(set_attr "itanium_class" "icmp")])
1539 (define_insn "*cmpsi_and_1"
1540 [(set (match_operand:BI 0 "register_operand" "=c")
1541 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1542 [(match_operand:SI 2 "gr_register_operand" "r")
1543 (const_int 0)])
1544 (match_operand:BI 1 "register_operand" "0")))]
1545 ""
1546 "cmp4.%C3.and.orcm %0, %I0 = r0, %2"
1547 [(set_attr "itanium_class" "icmp")])
1549 (define_insn "*cmpsi_andnot_0"
1550 [(set (match_operand:BI 0 "register_operand" "=c")
1551 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1552 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1553 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1554 (match_operand:BI 1 "register_operand" "0")))]
1555 ""
1556 "cmp4.%C4.or.andcm %I0, %0 = %3, %r2"
1557 [(set_attr "itanium_class" "icmp")])
1559 (define_insn "*cmpsi_andnot_1"
1560 [(set (match_operand:BI 0 "register_operand" "=c")
1561 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1562 [(match_operand:SI 2 "gr_register_operand" "r")
1563 (const_int 0)]))
1564 (match_operand:BI 1 "register_operand" "0")))]
1565 ""
1566 "cmp4.%C3.or.andcm %I0, %0 = r0, %2"
1567 [(set_attr "itanium_class" "icmp")])
1569 (define_insn "*cmpdi_and_0"
1570 [(set (match_operand:BI 0 "register_operand" "=c")
1571 (and:BI (match_operator:BI 4 "predicate_operator"
1572 [(match_operand:DI 2 "gr_register_operand" "r")
1573 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1574 (match_operand:BI 1 "register_operand" "0")))]
1575 ""
1576 "cmp.%C4.and.orcm %0, %I0 = %3, %2"
1577 [(set_attr "itanium_class" "icmp")])
1579 (define_insn "*cmpdi_and_1"
1580 [(set (match_operand:BI 0 "register_operand" "=c")
1581 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1582 [(match_operand:DI 2 "gr_register_operand" "r")
1583 (const_int 0)])
1584 (match_operand:BI 1 "register_operand" "0")))]
1585 ""
1586 "cmp.%C3.and.orcm %0, %I0 = r0, %2"
1587 [(set_attr "itanium_class" "icmp")])
1589 (define_insn "*cmpdi_andnot_0"
1590 [(set (match_operand:BI 0 "register_operand" "=c")
1591 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1592 [(match_operand:DI 2 "gr_register_operand" "r")
1593 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1594 (match_operand:BI 1 "register_operand" "0")))]
1595 ""
1596 "cmp.%C4.or.andcm %I0, %0 = %3, %2"
1597 [(set_attr "itanium_class" "icmp")])
1599 (define_insn "*cmpdi_andnot_1"
1600 [(set (match_operand:BI 0 "register_operand" "=c")
1601 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1602 [(match_operand:DI 2 "gr_register_operand" "r")
1603 (const_int 0)]))
1604 (match_operand:BI 1 "register_operand" "0")))]
1605 ""
1606 "cmp.%C3.or.andcm %I0, %0 = r0, %2"
1607 [(set_attr "itanium_class" "icmp")])
1609 (define_insn "*tbit_and_0"
1610 [(set (match_operand:BI 0 "register_operand" "=c")
1611 (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1612 (const_int 1))
1613 (const_int 0))
1614 (match_operand:BI 2 "register_operand" "0")))]
1615 ""
1616 "tbit.nz.and.orcm %0, %I0 = %1, 0"
1617 [(set_attr "itanium_class" "tbit")])
1619 (define_insn "*tbit_and_1"
1620 [(set (match_operand:BI 0 "register_operand" "=c")
1621 (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1622 (const_int 1))
1623 (const_int 0))
1624 (match_operand:BI 2 "register_operand" "0")))]
1625 ""
1626 "tbit.z.and.orcm %0, %I0 = %1, 0"
1627 [(set_attr "itanium_class" "tbit")])
1629 (define_insn "*tbit_and_2"
1630 [(set (match_operand:BI 0 "register_operand" "=c")
1631 (and:BI (ne:BI (zero_extract:DI
1632 (match_operand:DI 1 "gr_register_operand" "r")
1633 (const_int 1)
1634 (match_operand:DI 2 "shift_count_operand" "M"))
1635 (const_int 0))
1636 (match_operand:BI 3 "register_operand" "0")))]
1637 ""
1638 "tbit.nz.and.orcm %0, %I0 = %1, %2"
1639 [(set_attr "itanium_class" "tbit")])
1641 (define_insn "*tbit_and_3"
1642 [(set (match_operand:BI 0 "register_operand" "=c")
1643 (and:BI (eq:BI (zero_extract:DI
1644 (match_operand:DI 1 "gr_register_operand" "r")
1645 (const_int 1)
1646 (match_operand:DI 2 "shift_count_operand" "M"))
1647 (const_int 0))
1648 (match_operand:BI 3 "register_operand" "0")))]
1649 ""
1650 "tbit.z.and.orcm %0, %I0 = %1, %2"
1651 [(set_attr "itanium_class" "tbit")])
1653 (define_insn "*cmpsi_or_0"
1654 [(set (match_operand:BI 0 "register_operand" "=c")
1655 (ior:BI (match_operator:BI 4 "predicate_operator"
1656 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1657 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1658 (match_operand:BI 1 "register_operand" "0")))]
1659 ""
1660 "cmp4.%C4.or.andcm %0, %I0 = %3, %r2"
1661 [(set_attr "itanium_class" "icmp")])
1663 (define_insn "*cmpsi_or_1"
1664 [(set (match_operand:BI 0 "register_operand" "=c")
1665 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1666 [(match_operand:SI 2 "gr_register_operand" "r")
1667 (const_int 0)])
1668 (match_operand:BI 1 "register_operand" "0")))]
1669 ""
1670 "cmp4.%C3.or.andcm %0, %I0 = r0, %2"
1671 [(set_attr "itanium_class" "icmp")])
1673 (define_insn "*cmpsi_orcm_0"
1674 [(set (match_operand:BI 0 "register_operand" "=c")
1675 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1676 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1677 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1678 (match_operand:BI 1 "register_operand" "0")))]
1679 ""
1680 "cmp4.%C4.and.orcm %I0, %0 = %3, %r2"
1681 [(set_attr "itanium_class" "icmp")])
1683 (define_insn "*cmpsi_orcm_1"
1684 [(set (match_operand:BI 0 "register_operand" "=c")
1685 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1686 [(match_operand:SI 2 "gr_register_operand" "r")
1687 (const_int 0)]))
1688 (match_operand:BI 1 "register_operand" "0")))]
1689 ""
1690 "cmp4.%C3.and.orcm %I0, %0 = r0, %2"
1691 [(set_attr "itanium_class" "icmp")])
1693 (define_insn "*cmpdi_or_0"
1694 [(set (match_operand:BI 0 "register_operand" "=c")
1695 (ior:BI (match_operator:BI 4 "predicate_operator"
1696 [(match_operand:DI 2 "gr_register_operand" "r")
1697 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1698 (match_operand:BI 1 "register_operand" "0")))]
1699 ""
1700 "cmp.%C4.or.andcm %0, %I0 = %3, %2"
1701 [(set_attr "itanium_class" "icmp")])
1703 (define_insn "*cmpdi_or_1"
1704 [(set (match_operand:BI 0 "register_operand" "=c")
1705 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1706 [(match_operand:DI 2 "gr_register_operand" "r")
1707 (const_int 0)])
1708 (match_operand:BI 1 "register_operand" "0")))]
1709 ""
1710 "cmp.%C3.or.andcm %0, %I0 = r0, %2"
1711 [(set_attr "itanium_class" "icmp")])
1713 (define_insn "*cmpdi_orcm_0"
1714 [(set (match_operand:BI 0 "register_operand" "=c")
1715 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1716 [(match_operand:DI 2 "gr_register_operand" "r")
1717 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1718 (match_operand:BI 1 "register_operand" "0")))]
1719 ""
1720 "cmp.%C4.and.orcm %I0, %0 = %3, %2"
1721 [(set_attr "itanium_class" "icmp")])
1723 (define_insn "*cmpdi_orcm_1"
1724 [(set (match_operand:BI 0 "register_operand" "=c")
1725 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1726 [(match_operand:DI 2 "gr_register_operand" "r")
1727 (const_int 0)]))
1728 (match_operand:BI 1 "register_operand" "0")))]
1729 ""
1730 "cmp.%C3.and.orcm %I0, %0 = r0, %2"
1731 [(set_attr "itanium_class" "icmp")])
1733 (define_insn "*tbit_or_0"
1734 [(set (match_operand:BI 0 "register_operand" "=c")
1735 (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1736 (const_int 1))
1737 (const_int 0))
1738 (match_operand:BI 2 "register_operand" "0")))]
1739 ""
1740 "tbit.nz.or.andcm %0, %I0 = %1, 0"
1741 [(set_attr "itanium_class" "tbit")])
1743 (define_insn "*tbit_or_1"
1744 [(set (match_operand:BI 0 "register_operand" "=c")
1745 (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1746 (const_int 1))
1747 (const_int 0))
1748 (match_operand:BI 2 "register_operand" "0")))]
1749 ""
1750 "tbit.z.or.andcm %0, %I0 = %1, 0"
1751 [(set_attr "itanium_class" "tbit")])
1753 (define_insn "*tbit_or_2"
1754 [(set (match_operand:BI 0 "register_operand" "=c")
1755 (ior:BI (ne:BI (zero_extract:DI
1756 (match_operand:DI 1 "gr_register_operand" "r")
1757 (const_int 1)
1758 (match_operand:DI 2 "shift_count_operand" "M"))
1759 (const_int 0))
1760 (match_operand:BI 3 "register_operand" "0")))]
1761 ""
1762 "tbit.nz.or.andcm %0, %I0 = %1, %2"
1763 [(set_attr "itanium_class" "tbit")])
1765 (define_insn "*tbit_or_3"
1766 [(set (match_operand:BI 0 "register_operand" "=c")
1767 (ior:BI (eq:BI (zero_extract:DI
1768 (match_operand:DI 1 "gr_register_operand" "r")
1769 (const_int 1)
1770 (match_operand:DI 2 "shift_count_operand" "M"))
1771 (const_int 0))
1772 (match_operand:BI 3 "register_operand" "0")))]
1773 ""
1774 "tbit.z.or.andcm %0, %I0 = %1, %2"
1775 [(set_attr "itanium_class" "tbit")])
1777 ;; Transform test of and/or of setcc into parallel comparisons.
1779 (define_split
1780 [(set (match_operand:BI 0 "register_operand" "")
1781 (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1782 (const_int 0))
1783 (match_operand:DI 3 "register_operand" ""))
1784 (const_int 0)))]
1785 ""
1786 [(set (match_dup 0)
1787 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1788 (match_dup 2)))]
1789 "")
1791 (define_split
1792 [(set (match_operand:BI 0 "register_operand" "")
1793 (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1794 (const_int 0))
1795 (match_operand:DI 3 "register_operand" ""))
1796 (const_int 0)))]
1797 ""
1798 [(set (match_dup 0)
1799 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1800 (match_dup 2)))
1801 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1802 (clobber (scratch))])]
1803 "")
1805 (define_split
1806 [(set (match_operand:BI 0 "register_operand" "")
1807 (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1808 (const_int 0))
1809 (match_operand:DI 3 "register_operand" ""))
1810 (const_int 0)))]
1811 ""
1812 [(set (match_dup 0)
1813 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1814 (match_dup 2)))]
1815 "")
1817 (define_split
1818 [(set (match_operand:BI 0 "register_operand" "")
1819 (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1820 (const_int 0))
1821 (match_operand:DI 3 "register_operand" ""))
1822 (const_int 0)))]
1823 ""
1824 [(set (match_dup 0)
1825 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1826 (match_dup 2)))
1827 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1828 (clobber (scratch))])]
1829 "")
1831 ;; ??? Incredibly hackish. Either need four proper patterns with all
1832 ;; the alternatives, or rely on sched1 to split the insn and hope that
1833 ;; nothing bad happens to the comparisons in the meantime.
1834 ;;
1835 ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming
1836 ;; that we're doing height reduction.
1837 ;
1838 ;(define_insn_and_split ""
1839 ; [(set (match_operand:BI 0 "register_operand" "=c")
1840 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1841 ; [(match_operand 2 "" "")
1842 ; (match_operand 3 "" "")])
1843 ; (match_operator:BI 4 "comparison_operator"
1844 ; [(match_operand 5 "" "")
1845 ; (match_operand 6 "" "")]))
1846 ; (match_dup 0)))]
1847 ; "flag_schedule_insns"
1848 ; "#"
1849 ; ""
1850 ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0)))
1851 ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))]
1852 ; "")
1853 ;
1854 ;(define_insn_and_split ""
1855 ; [(set (match_operand:BI 0 "register_operand" "=c")
1856 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1857 ; [(match_operand 2 "" "")
1858 ; (match_operand 3 "" "")])
1859 ; (match_operator:BI 4 "comparison_operator"
1860 ; [(match_operand 5 "" "")
1861 ; (match_operand 6 "" "")]))
1862 ; (match_dup 0)))]
1863 ; "flag_schedule_insns"
1864 ; "#"
1865 ; ""
1866 ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0)))
1867 ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))]
1868 ; "")
1869 ;
1870 ;(define_split
1871 ; [(set (match_operand:BI 0 "register_operand" "")
1872 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1873 ; [(match_operand 2 "" "")
1874 ; (match_operand 3 "" "")])
1875 ; (match_operand:BI 7 "register_operand" ""))
1876 ; (and:BI (match_operator:BI 4 "comparison_operator"
1877 ; [(match_operand 5 "" "")
1878 ; (match_operand 6 "" "")])
1879 ; (match_operand:BI 8 "register_operand" ""))))]
1880 ; ""
1881 ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8)))
1882 ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4))
1883 ; (match_dup 0)))]
1884 ; "")
1885 ;
1886 ;(define_split
1887 ; [(set (match_operand:BI 0 "register_operand" "")
1888 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1889 ; [(match_operand 2 "" "")
1890 ; (match_operand 3 "" "")])
1891 ; (match_operand:BI 7 "register_operand" ""))
1892 ; (ior:BI (match_operator:BI 4 "comparison_operator"
1893 ; [(match_operand 5 "" "")
1894 ; (match_operand 6 "" "")])
1895 ; (match_operand:BI 8 "register_operand" ""))))]
1896 ; ""
1897 ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8)))
1898 ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4))
1899 ; (match_dup 0)))]
1900 ; "")
1902 ;; Try harder to avoid predicate copies by duplicating compares.
1903 ;; Note that we'll have already split the predicate copy, which
1904 ;; is kind of a pain, but oh well.
1906 (define_peephole2
1907 [(set (match_operand:BI 0 "register_operand" "")
1908 (match_operand:BI 1 "comparison_operator" ""))
1909 (set (match_operand:CCI 2 "register_operand" "")
1910 (match_operand:CCI 3 "register_operand" ""))
1911 (set (match_operand:CCI 4 "register_operand" "")
1912 (match_operand:CCI 5 "register_operand" ""))
1913 (set (match_operand:BI 6 "register_operand" "")
1914 (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))]
1915 "REGNO (operands[3]) == REGNO (operands[0])
1916 && REGNO (operands[4]) == REGNO (operands[0]) + 1
1917 && REGNO (operands[4]) == REGNO (operands[2]) + 1
1918 && REGNO (operands[6]) == REGNO (operands[2])"
1919 [(set (match_dup 0) (match_dup 1))
1920 (set (match_dup 6) (match_dup 7))]
1921 "operands[7] = copy_rtx (operands[1]);")
1922 \f
1923 ;; ::::::::::::::::::::
1924 ;; ::
1925 ;; :: 16-bit Integer arithmetic
1926 ;; ::
1927 ;; ::::::::::::::::::::
1929 (define_insn "mulhi3"
1930 [(set (match_operand:HI 0 "gr_register_operand" "=r")
1931 (mult:HI (match_operand:HI 1 "gr_register_operand" "r")
1932 (match_operand:HI 2 "gr_register_operand" "r")))]
1933 ""
1934 "pmpy2.r %0 = %1, %2"
1935 [(set_attr "itanium_class" "mmmul")])
1937 \f
1938 ;; ::::::::::::::::::::
1939 ;; ::
1940 ;; :: 32-bit Integer arithmetic
1941 ;; ::
1942 ;; ::::::::::::::::::::
1944 (define_insn "addsi3"
1945 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
1946 (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a")
1947 (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
1948 ""
1949 "@
1950 add %0 = %1, %2
1951 adds %0 = %2, %1
1952 addl %0 = %2, %1"
1953 [(set_attr "itanium_class" "ialu")])
1955 (define_insn "*addsi3_plus1"
1956 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1957 (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r")
1958 (match_operand:SI 2 "gr_register_operand" "r"))
1959 (const_int 1)))]
1960 ""
1961 "add %0 = %1, %2, 1"
1962 [(set_attr "itanium_class" "ialu")])
1964 (define_insn "*addsi3_plus1_alt"
1965 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1966 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
1967 (const_int 2))
1968 (const_int 1)))]
1969 ""
1970 "add %0 = %1, %1, 1"
1971 [(set_attr "itanium_class" "ialu")])
1973 (define_insn "*addsi3_shladd"
1974 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1975 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
1976 (match_operand:SI 2 "shladd_operand" "n"))
1977 (match_operand:SI 3 "gr_register_operand" "r")))]
1978 ""
1979 "shladd %0 = %1, %S2, %3"
1980 [(set_attr "itanium_class" "ialu")])
1982 (define_insn "subsi3"
1983 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1984 (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK")
1985 (match_operand:SI 2 "gr_register_operand" "r")))]
1986 ""
1987 "sub %0 = %1, %2"
1988 [(set_attr "itanium_class" "ialu")])
1990 (define_insn "*subsi3_minus1"
1991 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1992 (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r"))
1993 (match_operand:SI 2 "gr_register_operand" "r")))]
1994 ""
1995 "sub %0 = %2, %1, 1"
1996 [(set_attr "itanium_class" "ialu")])
1998 ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
2000 (define_insn "mulsi3"
2001 [(set (match_operand:SI 0 "fr_register_operand" "=f")
2002 (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
2003 (match_operand:SI 2 "grfr_register_operand" "f")))]
2004 ""
2005 "xmpy.l %0 = %1, %2"
2006 [(set_attr "itanium_class" "xmpy")])
2008 (define_insn "maddsi4"
2009 [(set (match_operand:SI 0 "fr_register_operand" "=f")
2010 (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
2011 (match_operand:SI 2 "grfr_register_operand" "f"))
2012 (match_operand:SI 3 "grfr_register_operand" "f")))]
2013 ""
2014 "xma.l %0 = %1, %2, %3"
2015 [(set_attr "itanium_class" "xmpy")])
2017 (define_insn "negsi2"
2018 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2019 (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))]
2020 ""
2021 "sub %0 = r0, %1"
2022 [(set_attr "itanium_class" "ialu")])
2024 (define_expand "abssi2"
2025 [(set (match_dup 2)
2026 (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0)))
2027 (set (match_operand:SI 0 "gr_register_operand" "")
2028 (if_then_else:SI (eq (match_dup 2) (const_int 0))
2029 (neg:SI (match_dup 1))
2030 (match_dup 1)))]
2031 ""
2032 { operands[2] = gen_reg_rtx (BImode); })
2034 (define_expand "sminsi3"
2035 [(set (match_dup 3)
2036 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
2037 (match_operand:SI 2 "gr_register_operand" "")))
2038 (set (match_operand:SI 0 "gr_register_operand" "")
2039 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2040 (match_dup 2) (match_dup 1)))]
2041 ""
2042 { operands[3] = gen_reg_rtx (BImode); })
2044 (define_expand "smaxsi3"
2045 [(set (match_dup 3)
2046 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
2047 (match_operand:SI 2 "gr_register_operand" "")))
2048 (set (match_operand:SI 0 "gr_register_operand" "")
2049 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2050 (match_dup 1) (match_dup 2)))]
2051 ""
2052 { operands[3] = gen_reg_rtx (BImode); })
2054 (define_expand "uminsi3"
2055 [(set (match_dup 3)
2056 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
2057 (match_operand:SI 2 "gr_register_operand" "")))
2058 (set (match_operand:SI 0 "gr_register_operand" "")
2059 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2060 (match_dup 2) (match_dup 1)))]
2061 ""
2062 { operands[3] = gen_reg_rtx (BImode); })
2064 (define_expand "umaxsi3"
2065 [(set (match_dup 3)
2066 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
2067 (match_operand:SI 2 "gr_register_operand" "")))
2068 (set (match_operand:SI 0 "gr_register_operand" "")
2069 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2070 (match_dup 1) (match_dup 2)))]
2071 ""
2072 { operands[3] = gen_reg_rtx (BImode); })
2074 (define_expand "divsi3"
2075 [(set (match_operand:SI 0 "register_operand" "")
2076 (div:SI (match_operand:SI 1 "general_operand" "")
2077 (match_operand:SI 2 "general_operand" "")))]
2078 "TARGET_INLINE_INT_DIV"
2079 {
2080 rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp;
2082 op0_xf = gen_reg_rtx (XFmode);
2083 op0_di = gen_reg_rtx (DImode);
2085 if (CONSTANT_P (operands[1]))
2086 operands[1] = force_reg (SImode, operands[1]);
2087 op1_xf = gen_reg_rtx (XFmode);
2088 expand_float (op1_xf, operands[1], 0);
2090 if (CONSTANT_P (operands[2]))
2091 operands[2] = force_reg (SImode, operands[2]);
2092 op2_xf = gen_reg_rtx (XFmode);
2093 expand_float (op2_xf, operands[2], 0);
2095 /* 2^-34 */
2096 twon34_exp = gen_reg_rtx (DImode);
2097 emit_move_insn (twon34_exp, GEN_INT (65501));
2098 twon34 = gen_reg_rtx (XFmode);
2099 emit_insn (gen_setf_exp_xf (twon34, twon34_exp));
2101 emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode),
2102 CONST1_RTX (SImode)));
2104 emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
2106 emit_insn (gen_fix_truncxfdi2_alts (op0_di, op0_xf, const1_rtx));
2107 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
2108 DONE;
2109 })
2111 (define_expand "modsi3"
2112 [(set (match_operand:SI 0 "register_operand" "")
2113 (mod:SI (match_operand:SI 1 "general_operand" "")
2114 (match_operand:SI 2 "general_operand" "")))]
2115 "TARGET_INLINE_INT_DIV"
2116 {
2117 rtx op2_neg, op1_di, div;
2119 div = gen_reg_rtx (SImode);
2120 emit_insn (gen_divsi3 (div, operands[1], operands[2]));
2122 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
2124 /* This is a trick to get us to reuse the value that we're sure to
2125 have already copied to the FP regs. */
2126 op1_di = gen_reg_rtx (DImode);
2127 convert_move (op1_di, operands[1], 0);
2129 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
2130 gen_lowpart (SImode, op1_di)));
2131 DONE;
2132 })
2134 (define_expand "udivsi3"
2135 [(set (match_operand:SI 0 "register_operand" "")
2136 (udiv:SI (match_operand:SI 1 "general_operand" "")
2137 (match_operand:SI 2 "general_operand" "")))]
2138 "TARGET_INLINE_INT_DIV"
2139 {
2140 rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp;
2142 op0_xf = gen_reg_rtx (XFmode);
2143 op0_di = gen_reg_rtx (DImode);
2145 if (CONSTANT_P (operands[1]))
2146 operands[1] = force_reg (SImode, operands[1]);
2147 op1_xf = gen_reg_rtx (XFmode);
2148 expand_float (op1_xf, operands[1], 1);
2150 if (CONSTANT_P (operands[2]))
2151 operands[2] = force_reg (SImode, operands[2]);
2152 op2_xf = gen_reg_rtx (XFmode);
2153 expand_float (op2_xf, operands[2], 1);
2155 /* 2^-34 */
2156 twon34_exp = gen_reg_rtx (DImode);
2157 emit_move_insn (twon34_exp, GEN_INT (65501));
2158 twon34 = gen_reg_rtx (XFmode);
2159 emit_insn (gen_setf_exp_xf (twon34, twon34_exp));
2161 emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode),
2162 CONST1_RTX (SImode)));
2164 emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
2166 emit_insn (gen_fixuns_truncxfdi2_alts (op0_di, op0_xf, const1_rtx));
2167 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
2168 DONE;
2169 })
2171 (define_expand "umodsi3"
2172 [(set (match_operand:SI 0 "register_operand" "")
2173 (umod:SI (match_operand:SI 1 "general_operand" "")
2174 (match_operand:SI 2 "general_operand" "")))]
2175 "TARGET_INLINE_INT_DIV"
2176 {
2177 rtx op2_neg, op1_di, div;
2179 div = gen_reg_rtx (SImode);
2180 emit_insn (gen_udivsi3 (div, operands[1], operands[2]));
2182 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
2184 /* This is a trick to get us to reuse the value that we're sure to
2185 have already copied to the FP regs. */
2186 op1_di = gen_reg_rtx (DImode);
2187 convert_move (op1_di, operands[1], 1);
2189 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
2190 gen_lowpart (SImode, op1_di)));
2191 DONE;
2192 })
2194 (define_insn_and_split "divsi3_internal"
2195 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
2196 (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f")
2197 (match_operand:XF 2 "fr_register_operand" "f"))))
2198 (clobber (match_scratch:XF 4 "=&f"))
2199 (clobber (match_scratch:XF 5 "=&f"))
2200 (clobber (match_scratch:BI 6 "=c"))
2201 (use (match_operand:XF 3 "fr_register_operand" "f"))]
2202 "TARGET_INLINE_INT_DIV"
2203 "#"
2204 "&& reload_completed"
2205 [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
2206 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
2207 UNSPEC_FR_RECIP_APPROX))
2208 (use (const_int 1))])
2209 (cond_exec (ne (match_dup 6) (const_int 0))
2210 (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
2211 (use (const_int 1))]))
2212 (cond_exec (ne (match_dup 6) (const_int 0))
2213 (parallel [(set (match_dup 5)
2214 (minus:XF (match_dup 7)
2215 (mult:XF (match_dup 2) (match_dup 0))))
2216 (use (const_int 1))]))
2217 (cond_exec (ne (match_dup 6) (const_int 0))
2218 (parallel [(set (match_dup 4)
2219 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
2220 (match_dup 4)))
2221 (use (const_int 1))]))
2222 (cond_exec (ne (match_dup 6) (const_int 0))
2223 (parallel [(set (match_dup 5)
2224 (plus:XF (mult:XF (match_dup 5) (match_dup 5))
2225 (match_dup 3)))
2226 (use (const_int 1))]))
2227 (cond_exec (ne (match_dup 6) (const_int 0))
2228 (parallel [(set (match_dup 0)
2229 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
2230 (match_dup 4)))
2231 (use (const_int 1))]))
2232 ]
2233 "operands[7] = CONST1_RTX (XFmode);"
2234 [(set_attr "predicable" "no")])
2235 \f
2236 ;; ::::::::::::::::::::
2237 ;; ::
2238 ;; :: 64-bit Integer arithmetic
2239 ;; ::
2240 ;; ::::::::::::::::::::
2242 (define_insn "adddi3"
2243 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
2244 (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a")
2245 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
2246 ""
2247 "@
2248 add %0 = %1, %2
2249 adds %0 = %2, %1
2250 addl %0 = %2, %1"
2251 [(set_attr "itanium_class" "ialu")])
2253 (define_insn "*adddi3_plus1"
2254 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2255 (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r")
2256 (match_operand:DI 2 "gr_register_operand" "r"))
2257 (const_int 1)))]
2258 ""
2259 "add %0 = %1, %2, 1"
2260 [(set_attr "itanium_class" "ialu")])
2262 ;; This has some of the same problems as shladd. We let the shladd
2263 ;; eliminator hack handle it, which results in the 1 being forced into
2264 ;; a register, but not more ugliness here.
2265 (define_insn "*adddi3_plus1_alt"
2266 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2267 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
2268 (const_int 2))
2269 (const_int 1)))]
2270 ""
2271 "add %0 = %1, %1, 1"
2272 [(set_attr "itanium_class" "ialu")])
2274 (define_insn "subdi3"
2275 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2276 (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK")
2277 (match_operand:DI 2 "gr_register_operand" "r")))]
2278 ""
2279 "sub %0 = %1, %2"
2280 [(set_attr "itanium_class" "ialu")])
2282 (define_insn "*subdi3_minus1"
2283 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2284 (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r"))
2285 (match_operand:DI 2 "gr_register_operand" "r")))]
2286 ""
2287 "sub %0 = %2, %1, 1"
2288 [(set_attr "itanium_class" "ialu")])
2290 ;; ??? Use grfr instead of fr because of virtual register elimination
2291 ;; and silly test cases multiplying by the frame pointer.
2292 (define_insn "muldi3"
2293 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2294 (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2295 (match_operand:DI 2 "grfr_register_operand" "f")))]
2296 ""
2297 "xmpy.l %0 = %1, %2"
2298 [(set_attr "itanium_class" "xmpy")])
2300 ;; ??? If operand 3 is an eliminable reg, then register elimination causes the
2301 ;; same problem that we have with shladd below. Unfortunately, this case is
2302 ;; much harder to fix because the multiply puts the result in an FP register,
2303 ;; but the add needs inputs from a general register. We add a spurious clobber
2304 ;; here so that it will be present just in case register elimination gives us
2305 ;; the funny result.
2307 ;; ??? Maybe validate_changes should try adding match_scratch clobbers?
2309 ;; ??? Maybe we should change how adds are canonicalized.
2311 (define_insn "madddi4"
2312 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2313 (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2314 (match_operand:DI 2 "grfr_register_operand" "f"))
2315 (match_operand:DI 3 "grfr_register_operand" "f")))
2316 (clobber (match_scratch:DI 4 "=X"))]
2317 ""
2318 "xma.l %0 = %1, %2, %3"
2319 [(set_attr "itanium_class" "xmpy")])
2321 ;; This can be created by register elimination if operand3 of shladd is an
2322 ;; eliminable register or has reg_equiv_constant set.
2324 ;; We have to use nonmemory_operand for operand 4, to ensure that the
2325 ;; validate_changes call inside eliminate_regs will always succeed. If it
2326 ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded
2327 ;; incorrectly.
2329 (define_insn "*madddi4_elim"
2330 [(set (match_operand:DI 0 "register_operand" "=&r")
2331 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
2332 (match_operand:DI 2 "register_operand" "f"))
2333 (match_operand:DI 3 "register_operand" "f"))
2334 (match_operand:DI 4 "nonmemory_operand" "rI")))
2335 (clobber (match_scratch:DI 5 "=f"))]
2336 "reload_in_progress"
2337 "#"
2338 [(set_attr "itanium_class" "unknown")])
2340 (define_split
2341 [(set (match_operand:DI 0 "register_operand" "")
2342 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2343 (match_operand:DI 2 "register_operand" ""))
2344 (match_operand:DI 3 "register_operand" ""))
2345 (match_operand:DI 4 "gr_reg_or_14bit_operand" "")))
2346 (clobber (match_scratch:DI 5 ""))]
2347 "reload_completed"
2348 [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
2349 (match_dup 3)))
2350 (clobber (match_dup 0))])
2351 (set (match_dup 0) (match_dup 5))
2352 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
2353 "")
2355 (define_insn "smuldi3_highpart"
2356 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2357 (truncate:DI
2358 (lshiftrt:TI
2359 (mult:TI (sign_extend:TI
2360 (match_operand:DI 1 "fr_register_operand" "f"))
2361 (sign_extend:TI
2362 (match_operand:DI 2 "fr_register_operand" "f")))
2363 (const_int 64))))]
2364 ""
2365 "xmpy.h %0 = %1, %2"
2366 [(set_attr "itanium_class" "xmpy")])
2368 (define_insn "umuldi3_highpart"
2369 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2370 (truncate:DI
2371 (lshiftrt:TI
2372 (mult:TI (zero_extend:TI
2373 (match_operand:DI 1 "fr_register_operand" "f"))
2374 (zero_extend:TI
2375 (match_operand:DI 2 "fr_register_operand" "f")))
2376 (const_int 64))))]
2377 ""
2378 "xmpy.hu %0 = %1, %2"
2379 [(set_attr "itanium_class" "xmpy")])
2381 (define_insn "negdi2"
2382 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2383 (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2384 ""
2385 "sub %0 = r0, %1"
2386 [(set_attr "itanium_class" "ialu")])
2388 (define_expand "absdi2"
2389 [(set (match_dup 2)
2390 (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2391 (set (match_operand:DI 0 "gr_register_operand" "")
2392 (if_then_else:DI (eq (match_dup 2) (const_int 0))
2393 (neg:DI (match_dup 1))
2394 (match_dup 1)))]
2395 ""
2396 { operands[2] = gen_reg_rtx (BImode); })
2398 (define_expand "smindi3"
2399 [(set (match_dup 3)
2400 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2401 (match_operand:DI 2 "gr_register_operand" "")))
2402 (set (match_operand:DI 0 "gr_register_operand" "")
2403 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2404 (match_dup 2) (match_dup 1)))]
2405 ""
2406 { operands[3] = gen_reg_rtx (BImode); })
2408 (define_expand "smaxdi3"
2409 [(set (match_dup 3)
2410 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2411 (match_operand:DI 2 "gr_register_operand" "")))
2412 (set (match_operand:DI 0 "gr_register_operand" "")
2413 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2414 (match_dup 1) (match_dup 2)))]
2415 ""
2416 { operands[3] = gen_reg_rtx (BImode); })
2418 (define_expand "umindi3"
2419 [(set (match_dup 3)
2420 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2421 (match_operand:DI 2 "gr_register_operand" "")))
2422 (set (match_operand:DI 0 "gr_register_operand" "")
2423 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2424 (match_dup 2) (match_dup 1)))]
2425 ""
2426 { operands[3] = gen_reg_rtx (BImode); })
2428 (define_expand "umaxdi3"
2429 [(set (match_dup 3)
2430 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2431 (match_operand:DI 2 "gr_register_operand" "")))
2432 (set (match_operand:DI 0 "gr_register_operand" "")
2433 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2434 (match_dup 1) (match_dup 2)))]
2435 ""
2436 { operands[3] = gen_reg_rtx (BImode); })
2438 (define_expand "ffsdi2"
2439 [(set (match_dup 6)
2440 (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2441 (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
2442 (set (match_dup 5) (const_int 0))
2443 (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
2444 (set (match_dup 4) (popcount:DI (match_dup 3)))
2445 (set (match_operand:DI 0 "gr_register_operand" "")
2446 (if_then_else:DI (ne (match_dup 6) (const_int 0))
2447 (match_dup 5) (match_dup 4)))]
2448 ""
2449 {
2450 operands[2] = gen_reg_rtx (DImode);
2451 operands[3] = gen_reg_rtx (DImode);
2452 operands[4] = gen_reg_rtx (DImode);
2453 operands[5] = gen_reg_rtx (DImode);
2454 operands[6] = gen_reg_rtx (BImode);
2455 })
2457 (define_expand "ctzdi2"
2458 [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "")
2459 (const_int -1)))
2460 (set (match_dup 3) (not:DI (match_dup 1)))
2461 (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3)))
2462 (set (match_operand:DI 0 "gr_register_operand" "")
2463 (popcount:DI (match_dup 4)))]
2464 ""
2465 {
2466 operands[2] = gen_reg_rtx (DImode);
2467 operands[3] = gen_reg_rtx (DImode);
2468 operands[4] = gen_reg_rtx (DImode);
2469 })
2471 ;; Note the computation here is op0 = 63 - (exp - 0xffff).
2472 (define_expand "clzdi2"
2473 [(set (match_dup 2)
2474 (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "")))
2475 (set (match_dup 3)
2476 (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP))
2477 (set (match_dup 4) (const_int 65598))
2478 (set (match_operand:DI 0 "gr_register_operand" "")
2479 (minus:DI (match_dup 4) (match_dup 3)))]
2480 ""
2481 {
2482 operands[2] = gen_reg_rtx (XFmode);
2483 operands[3] = gen_reg_rtx (DImode);
2484 operands[4] = gen_reg_rtx (DImode);
2485 })
2487 (define_insn "popcountdi2"
2488 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2489 (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2490 ""
2491 "popcnt %0 = %1"
2492 [(set_attr "itanium_class" "mmmul")])
2494 (define_insn "bswapdi2"
2495 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2496 (bswap:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2497 ""
2498 "mux1 %0 = %1, @rev"
2499 [(set_attr "itanium_class" "mmshf")])
2501 (define_insn "*getf_exp_xf"
2502 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2503 (unspec:DI [(match_operand:XF 1 "fr_register_operand" "f")]
2504 UNSPEC_GETF_EXP))]
2505 ""
2506 "getf.exp %0 = %1"
2507 [(set_attr "itanium_class" "frfr")])
2509 (define_expand "divdi3"
2510 [(set (match_operand:DI 0 "register_operand" "")
2511 (div:DI (match_operand:DI 1 "general_operand" "")
2512 (match_operand:DI 2 "general_operand" "")))]
2513 "TARGET_INLINE_INT_DIV"
2514 {
2515 rtx op1_xf, op2_xf, op0_xf;
2517 op0_xf = gen_reg_rtx (XFmode);
2519 if (CONSTANT_P (operands[1]))
2520 operands[1] = force_reg (DImode, operands[1]);
2521 op1_xf = gen_reg_rtx (XFmode);
2522 expand_float (op1_xf, operands[1], 0);
2524 if (CONSTANT_P (operands[2]))
2525 operands[2] = force_reg (DImode, operands[2]);
2526 op2_xf = gen_reg_rtx (XFmode);
2527 expand_float (op2_xf, operands[2], 0);
2529 emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode),
2530 CONST1_RTX (DImode)));
2532 if (TARGET_INLINE_INT_DIV == INL_MIN_LAT)
2533 emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf));
2534 else
2535 emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf));
2537 emit_insn (gen_fix_truncxfdi2_alts (operands[0], op0_xf, const1_rtx));
2538 DONE;
2539 })
2541 (define_expand "moddi3"
2542 [(set (match_operand:DI 0 "register_operand" "")
2543 (mod:SI (match_operand:DI 1 "general_operand" "")
2544 (match_operand:DI 2 "general_operand" "")))]
2545 "TARGET_INLINE_INT_DIV"
2546 {
2547 rtx op2_neg, div;
2549 div = gen_reg_rtx (DImode);
2550 emit_insn (gen_divdi3 (div, operands[1], operands[2]));
2552 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2554 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2555 DONE;
2556 })
2558 (define_expand "udivdi3"
2559 [(set (match_operand:DI 0 "register_operand" "")
2560 (udiv:DI (match_operand:DI 1 "general_operand" "")
2561 (match_operand:DI 2 "general_operand" "")))]
2562 "TARGET_INLINE_INT_DIV"
2563 {
2564 rtx op1_xf, op2_xf, op0_xf;
2566 op0_xf = gen_reg_rtx (XFmode);
2568 if (CONSTANT_P (operands[1]))
2569 operands[1] = force_reg (DImode, operands[1]);
2570 op1_xf = gen_reg_rtx (XFmode);
2571 expand_float (op1_xf, operands[1], 1);
2573 if (CONSTANT_P (operands[2]))
2574 operands[2] = force_reg (DImode, operands[2]);
2575 op2_xf = gen_reg_rtx (XFmode);
2576 expand_float (op2_xf, operands[2], 1);
2578 emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode),
2579 CONST1_RTX (DImode)));
2581 if (TARGET_INLINE_INT_DIV == INL_MIN_LAT)
2582 emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf));
2583 else
2584 emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf));
2586 emit_insn (gen_fixuns_truncxfdi2_alts (operands[0], op0_xf, const1_rtx));
2587 DONE;
2588 })
2590 (define_expand "umoddi3"
2591 [(set (match_operand:DI 0 "register_operand" "")
2592 (umod:DI (match_operand:DI 1 "general_operand" "")
2593 (match_operand:DI 2 "general_operand" "")))]
2594 "TARGET_INLINE_INT_DIV"
2595 {
2596 rtx op2_neg, div;
2598 div = gen_reg_rtx (DImode);
2599 emit_insn (gen_udivdi3 (div, operands[1], operands[2]));
2601 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2603 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2604 DONE;
2605 })
2607 (define_insn_and_split "divdi3_internal_lat"
2608 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
2609 (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f")
2610 (match_operand:XF 2 "fr_register_operand" "f"))))
2611 (clobber (match_scratch:XF 3 "=&f"))
2612 (clobber (match_scratch:XF 4 "=&f"))
2613 (clobber (match_scratch:XF 5 "=&f"))
2614 (clobber (match_scratch:BI 6 "=c"))]
2615 "TARGET_INLINE_INT_DIV == INL_MIN_LAT"
2616 "#"
2617 "&& reload_completed"
2618 [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
2619 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
2620 UNSPEC_FR_RECIP_APPROX))
2621 (use (const_int 1))])
2622 (cond_exec (ne (match_dup 6) (const_int 0))
2623 (parallel [(set (match_dup 3)
2624 (minus:XF (match_dup 7)
2625 (mult:XF (match_dup 2) (match_dup 0))))
2626 (use (const_int 1))]))
2627 (cond_exec (ne (match_dup 6) (const_int 0))
2628 (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
2629 (use (const_int 1))]))
2630 (cond_exec (ne (match_dup 6) (const_int 0))
2631 (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3)))
2632 (use (const_int 1))]))
2633 (cond_exec (ne (match_dup 6) (const_int 0))
2634 (parallel [(set (match_dup 4)
2635 (plus:XF (mult:XF (match_dup 3) (match_dup 4))
2636 (match_dup 4)))
2637 (use (const_int 1))]))
2638 (cond_exec (ne (match_dup 6) (const_int 0))
2639 (parallel [(set (match_dup 0)
2640 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
2641 (match_dup 0)))
2642 (use (const_int 1))]))
2643 (cond_exec (ne (match_dup 6) (const_int 0))
2644 (parallel [(set (match_dup 3)
2645 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
2646 (match_dup 4)))
2647 (use (const_int 1))]))
2648 (cond_exec (ne (match_dup 6) (const_int 0))
2649 (parallel [(set (match_dup 0)
2650 (plus:XF (mult:XF (match_dup 5) (match_dup 0))
2651 (match_dup 0)))
2652 (use (const_int 1))]))
2653 (cond_exec (ne (match_dup 6) (const_int 0))
2654 (parallel [(set (match_dup 4)
2655 (minus:XF (match_dup 1)
2656 (mult:XF (match_dup 2) (match_dup 3))))
2657 (use (const_int 1))]))
2658 (cond_exec (ne (match_dup 6) (const_int 0))
2659 (parallel [(set (match_dup 0)
2660 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
2661 (match_dup 3)))
2662 (use (const_int 1))]))
2663 ]
2664 "operands[7] = CONST1_RTX (XFmode);"
2665 [(set_attr "predicable" "no")])
2667 (define_insn_and_split "divdi3_internal_thr"
2668 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
2669 (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f")
2670 (match_operand:XF 2 "fr_register_operand" "f"))))
2671 (clobber (match_scratch:XF 3 "=&f"))
2672 (clobber (match_scratch:XF 4 "=f"))
2673 (clobber (match_scratch:BI 5 "=c"))]
2674 "TARGET_INLINE_INT_DIV == INL_MAX_THR"
2675 "#"
2676 "&& reload_completed"
2677 [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
2678 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
2679 UNSPEC_FR_RECIP_APPROX))
2680 (use (const_int 1))])
2681 (cond_exec (ne (match_dup 5) (const_int 0))
2682 (parallel [(set (match_dup 3)
2683 (minus:XF (match_dup 6)
2684 (mult:XF (match_dup 2) (match_dup 0))))
2685 (use (const_int 1))]))
2686 (cond_exec (ne (match_dup 5) (const_int 0))
2687 (parallel [(set (match_dup 0)
2688 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
2689 (match_dup 0)))
2690 (use (const_int 1))]))
2691 (cond_exec (ne (match_dup 5) (const_int 0))
2692 (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3)))
2693 (use (const_int 1))]))
2694 (cond_exec (ne (match_dup 5) (const_int 0))
2695 (parallel [(set (match_dup 0)
2696 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
2697 (match_dup 0)))
2698 (use (const_int 1))]))
2699 (cond_exec (ne (match_dup 5) (const_int 0))
2700 (parallel [(set (match_dup 3) (mult:XF (match_dup 0) (match_dup 1)))
2701 (use (const_int 1))]))
2702 (cond_exec (ne (match_dup 5) (const_int 0))
2703 (parallel [(set (match_dup 4)
2704 (minus:XF (match_dup 1)
2705 (mult:XF (match_dup 2) (match_dup 3))))
2706 (use (const_int 1))]))
2707 (cond_exec (ne (match_dup 5) (const_int 0))
2708 (parallel [(set (match_dup 0)
2709 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
2710 (match_dup 3)))
2711 (use (const_int 1))]))
2712 ]
2713 "operands[6] = CONST1_RTX (XFmode);"
2714 [(set_attr "predicable" "no")])
2715 \f
2716 ;; ::::::::::::::::::::
2717 ;; ::
2718 ;; :: 128-bit Integer arithmetic
2719 ;; ::
2720 ;; ::::::::::::::::::::
2722 (define_insn "addti3"
2723 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
2724 (plus:TI (match_operand:TI 1 "gr_register_operand" "%r")
2725 (match_operand:TI 2 "gr_reg_or_14bit_operand" "rI")))
2726 (clobber (match_scratch:BI 3 "=&c"))]
2727 ""
2728 "#"
2729 [(set_attr "itanium_class" "unknown")])
2731 (define_split
2732 [(set (match_operand:TI 0 "register_operand" "")
2733 (plus:TI (match_operand:TI 1 "register_operand" "")
2734 (match_operand:TI 2 "register_operand" "")))
2735 (clobber (match_scratch:BI 3 ""))]
2736 "reload_completed"
2737 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
2738 (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1)))
2739 (cond_exec (eq (match_dup 3) (const_int 0))
2740 (set (match_dup 4) (plus:DI (match_dup 5) (match_dup 6))))
2741 (cond_exec (ne (match_dup 3) (const_int 0))
2742 (set (match_dup 4)
2743 (plus:DI (plus:DI (match_dup 5) (match_dup 6))
2744 (const_int 1))))]
2745 {
2746 operands[4] = gen_highpart (DImode, operands[0]);
2747 operands[0] = gen_lowpart (DImode, operands[0]);
2748 operands[5] = gen_highpart (DImode, operands[1]);
2749 operands[1] = gen_lowpart (DImode, operands[1]);
2750 operands[6] = gen_highpart (DImode, operands[2]);
2751 operands[2] = gen_lowpart (DImode, operands[2]);
2752 })
2754 (define_split
2755 [(set (match_operand:TI 0 "register_operand" "")
2756 (plus:TI (match_operand:TI 1 "register_operand" "")
2757 (match_operand:TI 2 "immediate_operand" "")))
2758 (clobber (match_scratch:BI 3 ""))]
2759 "reload_completed"
2760 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
2761 (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1)))
2762 (cond_exec (eq (match_dup 3) (const_int 0))
2763 (set (match_dup 4)
2764 (plus:DI (match_dup 5) (match_dup 6))))
2765 (cond_exec (ne (match_dup 3) (const_int 0))
2766 (set (match_dup 4)
2767 (plus:DI (match_dup 5) (match_dup 7))))]
2768 {
2769 operands[4] = gen_highpart (DImode, operands[0]);
2770 operands[0] = gen_lowpart (DImode, operands[0]);
2771 operands[5] = gen_highpart (DImode, operands[1]);
2772 operands[1] = gen_lowpart (DImode, operands[1]);
2773 operands[6] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2774 operands[7] = INTVAL (operands[2]) < 0 ? const0_rtx : const1_rtx;
2775 })
2777 (define_insn "subti3"
2778 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
2779 (minus:TI (match_operand:TI 1 "gr_reg_or_8bit_operand" "rK")
2780 (match_operand:TI 2 "gr_register_operand" "r")))
2781 (clobber (match_scratch:BI 3 "=&c"))]
2782 ""
2783 "#"
2784 [(set_attr "itanium_class" "unknown")])
2786 (define_split
2787 [(set (match_operand:TI 0 "register_operand" "")
2788 (minus:TI (match_operand:TI 1 "register_operand" "")
2789 (match_operand:TI 2 "register_operand" "")))
2790 (clobber (match_scratch:BI 3 "=&c"))]
2791 "reload_completed"
2792 [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
2793 (set (match_dup 3) (ltu:BI (match_dup 1) (match_dup 0)))
2794 (cond_exec (eq (match_dup 3) (const_int 0))
2795 (set (match_dup 4) (minus:DI (match_dup 5) (match_dup 6))))
2796 (cond_exec (ne (match_dup 3) (const_int 0))
2797 (set (match_dup 4)
2798 (plus:DI (not:DI (match_dup 6)) (match_dup 5))))]
2799 {
2800 operands[4] = gen_highpart (DImode, operands[0]);
2801 operands[0] = gen_lowpart (DImode, operands[0]);
2802 operands[5] = gen_highpart (DImode, operands[1]);
2803 operands[1] = gen_lowpart (DImode, operands[1]);
2804 operands[6] = gen_highpart (DImode, operands[2]);
2805 operands[2] = gen_lowpart (DImode, operands[2]);
2806 })
2808 (define_split
2809 [(set (match_operand:TI 0 "register_operand" "")
2810 (minus:TI (match_operand:TI 1 "immediate_operand" "")
2811 (match_operand:TI 2 "register_operand" "")))
2812 (clobber (match_scratch:BI 3 "=&c"))]
2813 "reload_completed && satisfies_constraint_K (operands[1])"
2814 [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
2815 (set (match_dup 3) (gtu:BI (match_dup 0) (match_dup 1)))
2816 (cond_exec (ne (match_dup 3) (const_int 0))
2817 (set (match_dup 4) (minus:DI (match_dup 6) (match_dup 5))))
2818 (cond_exec (eq (match_dup 3) (const_int 0))
2819 (set (match_dup 4) (minus:DI (match_dup 7) (match_dup 5))))]
2820 {
2821 operands[4] = gen_highpart (DImode, operands[0]);
2822 operands[0] = gen_lowpart (DImode, operands[0]);
2823 operands[5] = gen_highpart (DImode, operands[2]);
2824 operands[2] = gen_lowpart (DImode, operands[2]);
2825 operands[6] = INTVAL (operands[1]) < 0 ? GEN_INT (-2) : constm1_rtx;
2826 operands[7] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
2827 })
2829 (define_expand "mulditi3"
2830 [(set (match_operand:TI 0 "fr_register_operand" "")
2831 (mult:TI (sign_extend:TI
2832 (match_operand:DI 1 "fr_register_operand" ""))
2833 (sign_extend:TI
2834 (match_operand:DI 2 "fr_register_operand" ""))))]
2835 ""
2836 "")
2838 (define_insn_and_split "*mulditi3_internal"
2839 [(set (match_operand:TI 0 "fr_register_operand" "=&f")
2840 (mult:TI (sign_extend:TI
2841 (match_operand:DI 1 "fr_register_operand" "%f"))
2842 (sign_extend:TI
2843 (match_operand:DI 2 "fr_register_operand" "f"))))]
2844 ""
2845 "#"
2846 "reload_completed"
2847 [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2)))
2848 (set (match_dup 3) (truncate:DI
2849 (lshiftrt:TI
2850 (mult:TI (sign_extend:TI (match_dup 1))
2851 (sign_extend:TI (match_dup 2)))
2852 (const_int 64))))]
2853 {
2854 operands[3] = gen_highpart (DImode, operands[0]);
2855 operands[0] = gen_lowpart (DImode, operands[0]);
2856 }
2857 [(set_attr "itanium_class" "unknown")])
2859 (define_expand "umulditi3"
2860 [(set (match_operand:TI 0 "fr_register_operand" "")
2861 (mult:TI (zero_extend:TI
2862 (match_operand:DI 1 "fr_register_operand" ""))
2863 (zero_extend:TI
2864 (match_operand:DI 2 "fr_register_operand" ""))))]
2865 ""
2866 "")
2868 (define_insn_and_split "*umulditi3_internal"
2869 [(set (match_operand:TI 0 "fr_register_operand" "=&f")
2870 (mult:TI (zero_extend:TI
2871 (match_operand:DI 1 "fr_register_operand" "%f"))
2872 (zero_extend:TI
2873 (match_operand:DI 2 "fr_register_operand" "f"))))]
2874 ""
2875 "#"
2876 "reload_completed"
2877 [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2)))
2878 (set (match_dup 3) (truncate:DI
2879 (lshiftrt:TI
2880 (mult:TI (zero_extend:TI (match_dup 1))
2881 (zero_extend:TI (match_dup 2)))
2882 (const_int 64))))]
2883 {
2884 operands[3] = gen_highpart (DImode, operands[0]);
2885 operands[0] = gen_lowpart (DImode, operands[0]);
2886 }
2887 [(set_attr "itanium_class" "unknown")])
2889 (define_insn_and_split "negti2"
2890 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
2891 (neg:TI (match_operand:TI 1 "gr_register_operand" "r")))
2892 (clobber (match_scratch:BI 2 "=&c"))]
2893 ""
2894 "#"
2895 "reload_completed"
2896 [(set (match_dup 2) (eq:BI (match_dup 1) (const_int 0)))
2897 (set (match_dup 0) (minus:DI (const_int 0) (match_dup 1)))
2898 (cond_exec (eq (match_dup 2) (const_int 0))
2899 (set (match_dup 3) (minus:DI (const_int -1) (match_dup 4))))
2900 (cond_exec (ne (match_dup 2) (const_int 0))
2901 (set (match_dup 3) (minus:DI (const_int 0) (match_dup 4))))]
2902 {
2903 operands[3] = gen_highpart (DImode, operands[0]);
2904 operands[0] = gen_lowpart (DImode, operands[0]);
2905 operands[4] = gen_highpart (DImode, operands[1]);
2906 operands[1] = gen_lowpart (DImode, operands[1]);
2907 }
2908 [(set_attr "itanium_class" "unknown")])
2909 \f
2910 ;; ::::::::::::::::::::
2911 ;; ::
2912 ;; :: 32-bit floating point arithmetic
2913 ;; ::
2914 ;; ::::::::::::::::::::
2916 (define_insn "addsf3"
2917 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2918 (plus:SF (match_operand:SF 1 "fr_register_operand" "%f")
2919 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2920 ""
2921 "fadd.s %0 = %1, %F2"
2922 [(set_attr "itanium_class" "fmac")])
2924 (define_insn "subsf3"
2925 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2926 (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2927 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2928 ""
2929 "fsub.s %0 = %F1, %F2"
2930 [(set_attr "itanium_class" "fmac")])
2932 (define_insn "mulsf3"
2933 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2934 (mult:SF (match_operand:SF 1 "fr_register_operand" "%f")
2935 (match_operand:SF 2 "fr_register_operand" "f")))]
2936 ""
2937 "fmpy.s %0 = %1, %2"
2938 [(set_attr "itanium_class" "fmac")])
2940 (define_insn "abssf2"
2941 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2942 (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))]
2943 ""
2944 "fabs %0 = %1"
2945 [(set_attr "itanium_class" "fmisc")])
2947 (define_insn "negsf2"
2948 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2949 (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))]
2950 ""
2951 "fneg %0 = %1"
2952 [(set_attr "itanium_class" "fmisc")])
2954 (define_insn "*nabssf2"
2955 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2956 (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))]
2957 ""
2958 "fnegabs %0 = %1"
2959 [(set_attr "itanium_class" "fmisc")])
2961 (define_insn "copysignsf3"
2962 [(set (match_operand:SF 0 "register_operand" "=f")
2963 (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2964 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")]
2965 UNSPEC_COPYSIGN))]
2966 ""
2967 "fmerge.s %0 = %F2, %F1"
2968 [(set_attr "itanium_class" "fmisc")])
2970 (define_insn "*ncopysignsf3"
2971 [(set (match_operand:SF 0 "register_operand" "=f")
2972 (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2973 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")]
2974 UNSPEC_COPYSIGN)))]
2975 ""
2976 "fmerge.ns %0 = %F2, %F1"
2977 [(set_attr "itanium_class" "fmisc")])
2979 (define_insn "sminsf3"
2980 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2981 (smin:SF (match_operand:SF 1 "fr_register_operand" "f")
2982 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2983 ""
2984 "fmin %0 = %1, %F2"
2985 [(set_attr "itanium_class" "fmisc")])
2987 (define_insn "smaxsf3"
2988 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2989 (smax:SF (match_operand:SF 1 "fr_register_operand" "f")
2990 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2991 ""
2992 "fmax %0 = %1, %F2"
2993 [(set_attr "itanium_class" "fmisc")])
2995 (define_insn "*maddsf4"
2996 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2997 (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2998 (match_operand:SF 2 "fr_register_operand" "f"))
2999 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
3000 ""
3001 "fma.s %0 = %1, %2, %F3"
3002 [(set_attr "itanium_class" "fmac")])
3004 (define_insn "*msubsf4"
3005 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3006 (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
3007 (match_operand:SF 2 "fr_register_operand" "f"))
3008 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
3009 ""
3010 "fms.s %0 = %1, %2, %F3"
3011 [(set_attr "itanium_class" "fmac")])
3013 (define_insn "*nmulsf3"
3014 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3015 (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
3016 (match_operand:SF 2 "fr_register_operand" "f"))))]
3017 ""
3018 "fnmpy.s %0 = %1, %2"
3019 [(set_attr "itanium_class" "fmac")])
3021 (define_insn "*nmaddsf4"
3022 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3023 (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")
3024 (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
3025 (match_operand:SF 2 "fr_register_operand" "f"))))]
3026 ""
3027 "fnma.s %0 = %1, %2, %F3"
3028 [(set_attr "itanium_class" "fmac")])
3030 (define_insn "*nmaddsf4_alts"
3031 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3032 (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")
3033 (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
3034 (match_operand:SF 2 "fr_register_operand" "f"))))
3035 (use (match_operand:SI 4 "const_int_operand" ""))]
3036 ""
3037 "fnma.s.s%4 %0 = %1, %2, %F3"
3038 [(set_attr "itanium_class" "fmac")])
3040 (define_expand "divsf3"
3041 [(set (match_operand:SF 0 "fr_register_operand" "")
3042 (div:SF (match_operand:SF 1 "fr_register_operand" "")
3043 (match_operand:SF 2 "fr_register_operand" "")))]
3044 "TARGET_INLINE_FLOAT_DIV"
3045 {
3046 rtx insn;
3047 if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT)
3048 insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]);
3049 else
3050 insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
3051 emit_insn (insn);
3052 DONE;
3053 })
3055 (define_insn_and_split "divsf3_internal_lat"
3056 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
3057 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
3058 (match_operand:SF 2 "fr_register_operand" "f")))
3059 (clobber (match_scratch:XF 3 "=&f"))
3060 (clobber (match_scratch:XF 4 "=f"))
3061 (clobber (match_scratch:BI 5 "=c"))]
3062 "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT"
3063 "#"
3064 "&& reload_completed"
3065 [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
3066 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
3067 UNSPEC_FR_RECIP_APPROX))
3068 (use (const_int 0))])
3069 (cond_exec (ne (match_dup 5) (const_int 0))
3070 (parallel [(set (match_dup 3) (mult:XF (match_dup 7) (match_dup 6)))
3071 (use (const_int 1))]))
3072 (cond_exec (ne (match_dup 5) (const_int 0))
3073 (parallel [(set (match_dup 4)
3074 (minus:XF (match_dup 10)
3075 (mult:XF (match_dup 8) (match_dup 6))))
3076 (use (const_int 1))]))
3077 (cond_exec (ne (match_dup 5) (const_int 0))
3078 (parallel [(set (match_dup 3)
3079 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3080 (match_dup 3)))
3081 (use (const_int 1))]))
3082 (cond_exec (ne (match_dup 5) (const_int 0))
3083 (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4)))
3084 (use (const_int 1))]))
3085 (cond_exec (ne (match_dup 5) (const_int 0))
3086 (parallel [(set (match_dup 3)
3087 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3088 (match_dup 3)))
3089 (use (const_int 1))]))
3090 (cond_exec (ne (match_dup 5) (const_int 0))
3091 (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4)))
3092 (use (const_int 1))]))
3093 (cond_exec (ne (match_dup 5) (const_int 0))
3094 (parallel [(set (match_dup 9)
3095 (float_truncate:DF
3096 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3097 (match_dup 3))))
3098 (use (const_int 1))]))
3099 (cond_exec (ne (match_dup 5) (const_int 0))
3100 (set (match_dup 0)
3101 (float_truncate:SF (match_dup 6))))
3102 ]
3103 {
3104 operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3105 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3106 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
3107 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0]));
3108 operands[10] = CONST1_RTX (XFmode);
3109 }
3110 [(set_attr "predicable" "no")])
3112 (define_insn_and_split "divsf3_internal_thr"
3113 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
3114 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
3115 (match_operand:SF 2 "fr_register_operand" "f")))
3116 (clobber (match_scratch:XF 3 "=&f"))
3117 (clobber (match_scratch:XF 4 "=f"))
3118 (clobber (match_scratch:BI 5 "=c"))]
3119 "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR"
3120 "#"
3121 "&& reload_completed"
3122 [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
3123 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
3124 UNSPEC_FR_RECIP_APPROX))
3125 (use (const_int 0))])
3126 (cond_exec (ne (match_dup 5) (const_int 0))
3127 (parallel [(set (match_dup 3)
3128 (minus:XF (match_dup 10)
3129 (mult:XF (match_dup 8) (match_dup 6))))
3130 (use (const_int 1))]))
3131 (cond_exec (ne (match_dup 5) (const_int 0))
3132 (parallel [(set (match_dup 3)
3133 (plus:XF (mult:XF (match_dup 3) (match_dup 3))
3134 (match_dup 3)))
3135 (use (const_int 1))]))
3136 (cond_exec (ne (match_dup 5) (const_int 0))
3137 (parallel [(set (match_dup 6)
3138 (plus:XF (mult:XF (match_dup 3) (match_dup 6))
3139 (match_dup 6)))
3140 (use (const_int 1))]))
3141 (cond_exec (ne (match_dup 5) (const_int 0))
3142 (parallel [(set (match_dup 9)
3143 (float_truncate:SF
3144 (mult:XF (match_dup 7) (match_dup 6))))
3145 (use (const_int 1))]))
3146 (cond_exec (ne (match_dup 5) (const_int 0))
3147 (parallel [(set (match_dup 4)
3148 (minus:XF (match_dup 7)
3149 (mult:XF (match_dup 8) (match_dup 3))))
3150 (use (const_int 1))]))
3151 (cond_exec (ne (match_dup 5) (const_int 0))
3152 (set (match_dup 0)
3153 (float_truncate:SF
3154 (plus:XF (mult:XF (match_dup 4) (match_dup 6))
3155 (match_dup 3)))))
3156 ]
3157 {
3158 operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3159 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3160 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
3161 operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
3162 operands[10] = CONST1_RTX (XFmode);
3163 }
3164 [(set_attr "predicable" "no")])
3166 ;; Inline square root.
3168 (define_insn "*sqrt_approx"
3169 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3170 (div:XF (const_int 1)
3171 (sqrt:XF (match_operand:XF 2 "fr_register_operand" "f"))))
3172 (set (match_operand:BI 1 "register_operand" "=c")
3173 (unspec:BI [(match_dup 2)] UNSPEC_FR_SQRT_RECIP_APPROX))
3174 (use (match_operand:SI 3 "const_int_operand" "")) ]
3175 ""
3176 "frsqrta.s%3 %0, %1 = %2"
3177 [(set_attr "itanium_class" "fmisc")
3178 (set_attr "predicable" "no")])
3180 (define_insn "setf_exp_xf"
3181 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3182 (unspec:XF [(match_operand:DI 1 "register_operand" "r")]
3183 UNSPEC_SETF_EXP))]
3184 ""
3185 "setf.exp %0 = %1"
3186 [(set_attr "itanium_class" "frfr")])
3188 (define_expand "sqrtsf2"
3189 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
3190 (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f")))]
3191 "TARGET_INLINE_SQRT"
3192 {
3193 rtx insn;
3194 #if 0
3195 if (TARGET_INLINE_SQRT == INL_MIN_LAT)
3196 insn = gen_sqrtsf2_internal_lat (operands[0], operands[1]);
3197 else
3198 #else
3199 gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT);
3200 #endif
3201 insn = gen_sqrtsf2_internal_thr (operands[0], operands[1]);
3202 emit_insn (insn);
3203 DONE;
3204 })
3206 ;; Latency-optimized square root.
3207 ;; FIXME: Implement.
3209 ;; Throughput-optimized square root.
3211 (define_insn_and_split "sqrtsf2_internal_thr"
3212 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
3213 (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f")))
3214 ;; Register r2 in optimization guide.
3215 (clobber (match_scratch:DI 2 "=r"))
3216 ;; Register f8 in optimization guide
3217 (clobber (match_scratch:XF 3 "=&f"))
3218 ;; Register f9 in optimization guide
3219 (clobber (match_scratch:XF 4 "=&f"))
3220 ;; Register f10 in optimization guide
3221 (clobber (match_scratch:XF 5 "=&f"))
3222 ;; Register p6 in optimization guide.
3223 (clobber (match_scratch:BI 6 "=c"))]
3224 "TARGET_INLINE_SQRT == INL_MAX_THR"
3225 "#"
3226 "&& reload_completed"
3227 [ ;; exponent of +1/2 in r2
3228 (set (match_dup 2) (const_int 65534))
3229 ;; +1/2 in f8
3230 (set (match_dup 3)
3231 (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP))
3232 ;; Step 1
3233 ;; y0 = 1/sqrt(a) in f7
3234 (parallel [(set (match_dup 7)
3235 (div:XF (const_int 1)
3236 (sqrt:XF (match_dup 8))))
3237 (set (match_dup 6)
3238 (unspec:BI [(match_dup 8)]
3239 UNSPEC_FR_SQRT_RECIP_APPROX))
3240 (use (const_int 0))])
3241 ;; Step 2
3242 ;; H0 = 1/2 * y0 in f9
3243 (cond_exec (ne (match_dup 6) (const_int 0))
3244 (parallel [(set (match_dup 4)
3245 (plus:XF (mult:XF (match_dup 3) (match_dup 7))
3246 (match_dup 9)))
3247 (use (const_int 1))]))
3248 ;; Step 3
3249 ;; S0 = a * y0 in f7
3250 (cond_exec (ne (match_dup 6) (const_int 0))
3251 (parallel [(set (match_dup 7)
3252 (plus:XF (mult:XF (match_dup 8) (match_dup 7))
3253 (match_dup 9)))
3254 (use (const_int 1))]))
3255 ;; Step 4
3256 ;; d = 1/2 - S0 * H0 in f10
3257 (cond_exec (ne (match_dup 6) (const_int 0))
3258 (parallel [(set (match_dup 5)
3259 (minus:XF (match_dup 3)
3260 (mult:XF (match_dup 7) (match_dup 4))))
3261 (use (const_int 1))]))
3262 ;; Step 5
3263 ;; d' = d + 1/2 * d in f8
3264 (cond_exec (ne (match_dup 6) (const_int 0))
3265 (parallel [(set (match_dup 3)
3266 (plus:XF (mult:XF (match_dup 3) (match_dup 5))
3267 (match_dup 5)))
3268 (use (const_int 1))]))
3269 ;; Step 6
3270 ;; e = d + d * d' in f8
3271 (cond_exec (ne (match_dup 6) (const_int 0))
3272 (parallel [(set (match_dup 3)
3273 (plus:XF (mult:XF (match_dup 5) (match_dup 3))
3274 (match_dup 5)))
3275 (use (const_int 1))]))
3276 ;; Step 7
3277 ;; S1 = S0 + e * S0 in f7
3278 (cond_exec (ne (match_dup 6) (const_int 0))
3279 (parallel [(set (match_dup 0)
3280 (float_truncate:SF
3281 (plus:XF (mult:XF (match_dup 3) (match_dup 7))
3282 (match_dup 7))))
3283 (use (const_int 1))]))
3284 ;; Step 8
3285 ;; H1 = H0 + e * H0 in f8
3286 (cond_exec (ne (match_dup 6) (const_int 0))
3287 (parallel [(set (match_dup 3)
3288 (plus:XF (mult:XF (match_dup 3) (match_dup 4))
3289 (match_dup 4)))
3290 (use (const_int 1))]))
3291 ;; Step 9
3292 ;; d1 = a - S1 * S1 in f9
3293 (cond_exec (ne (match_dup 6) (const_int 0))
3294 (parallel [(set (match_dup 4)
3295 (minus:XF (match_dup 8)
3296 (mult:XF (match_dup 7) (match_dup 7))))
3297 (use (const_int 1))]))
3298 ;; Step 10
3299 ;; S = S1 + d1 * H1 in f7
3300 (cond_exec (ne (match_dup 6) (const_int 0))
3301 (parallel [(set (match_dup 0)
3302 (float_truncate:SF
3303 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3304 (match_dup 7))))
3305 (use (const_int 0))]))]
3306 {
3307 /* Generate 82-bit versions of the input and output operands. */
3308 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3309 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3310 /* Generate required floating-point constants. */
3311 operands[9] = CONST0_RTX (XFmode);
3312 }
3313 [(set_attr "predicable" "no")])
3314 \f
3315 ;; ::::::::::::::::::::
3316 ;; ::
3317 ;; :: 64-bit floating point arithmetic
3318 ;; ::
3319 ;; ::::::::::::::::::::
3321 (define_insn "adddf3"
3322 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3323 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
3324 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3325 ""
3326 "fadd.d %0 = %1, %F2"
3327 [(set_attr "itanium_class" "fmac")])
3329 (define_insn "*adddf3_trunc"
3330 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3331 (float_truncate:SF
3332 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
3333 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
3334 ""
3335 "fadd.s %0 = %1, %F2"
3336 [(set_attr "itanium_class" "fmac")])
3338 (define_insn "subdf3"
3339 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3340 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
3341 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3342 ""
3343 "fsub.d %0 = %F1, %F2"
3344 [(set_attr "itanium_class" "fmac")])
3346 (define_insn "*subdf3_trunc"
3347 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3348 (float_truncate:SF
3349 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
3350 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
3351 ""
3352 "fsub.s %0 = %F1, %F2"
3353 [(set_attr "itanium_class" "fmac")])
3355 (define_insn "muldf3"
3356 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3357 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3358 (match_operand:DF 2 "fr_register_operand" "f")))]
3359 ""
3360 "fmpy.d %0 = %1, %2"
3361 [(set_attr "itanium_class" "fmac")])
3363 (define_insn "*muldf3_trunc"
3364 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3365 (float_truncate:SF
3366 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3367 (match_operand:DF 2 "fr_register_operand" "f"))))]
3368 ""
3369 "fmpy.s %0 = %1, %2"
3370 [(set_attr "itanium_class" "fmac")])
3372 (define_insn "absdf2"
3373 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3374 (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))]
3375 ""
3376 "fabs %0 = %1"
3377 [(set_attr "itanium_class" "fmisc")])
3379 (define_insn "negdf2"
3380 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3381 (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))]
3382 ""
3383 "fneg %0 = %1"
3384 [(set_attr "itanium_class" "fmisc")])
3386 (define_insn "*nabsdf2"
3387 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3388 (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))]
3389 ""
3390 "fnegabs %0 = %1"
3391 [(set_attr "itanium_class" "fmisc")])
3393 (define_insn "copysigndf3"
3394 [(set (match_operand:DF 0 "register_operand" "=f")
3395 (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
3396 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")]
3397 UNSPEC_COPYSIGN))]
3398 ""
3399 "fmerge.s %0 = %F2, %F1"
3400 [(set_attr "itanium_class" "fmisc")])
3402 (define_insn "*ncopysigndf3"
3403 [(set (match_operand:DF 0 "register_operand" "=f")
3404 (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
3405 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")]
3406 UNSPEC_COPYSIGN)))]
3407 ""
3408 "fmerge.ns %0 = %F2, %F1"
3409 [(set_attr "itanium_class" "fmisc")])
3411 (define_insn "smindf3"
3412 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3413 (smin:DF (match_operand:DF 1 "fr_register_operand" "f")
3414 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3415 ""
3416 "fmin %0 = %1, %F2"
3417 [(set_attr "itanium_class" "fmisc")])
3419 (define_insn "smaxdf3"
3420 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3421 (smax:DF (match_operand:DF 1 "fr_register_operand" "f")
3422 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3423 ""
3424 "fmax %0 = %1, %F2"
3425 [(set_attr "itanium_class" "fmisc")])
3427 (define_insn "*madddf4"
3428 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3429 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3430 (match_operand:DF 2 "fr_register_operand" "f"))
3431 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
3432 ""
3433 "fma.d %0 = %1, %2, %F3"
3434 [(set_attr "itanium_class" "fmac")])
3436 (define_insn "*madddf4_trunc"
3437 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3438 (float_truncate:SF
3439 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3440 (match_operand:DF 2 "fr_register_operand" "f"))
3441 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
3442 ""
3443 "fma.s %0 = %1, %2, %F3"
3444 [(set_attr "itanium_class" "fmac")])
3446 (define_insn "*msubdf4"
3447 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3448 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3449 (match_operand:DF 2 "fr_register_operand" "f"))
3450 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
3451 ""
3452 "fms.d %0 = %1, %2, %F3"
3453 [(set_attr "itanium_class" "fmac")])
3455 (define_insn "*msubdf4_trunc"
3456 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3457 (float_truncate:SF
3458 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3459 (match_operand:DF 2 "fr_register_operand" "f"))
3460 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
3461 ""
3462 "fms.s %0 = %1, %2, %F3"
3463 [(set_attr "itanium_class" "fmac")])
3465 (define_insn "*nmuldf3"
3466 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3467 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3468 (match_operand:DF 2 "fr_register_operand" "f"))))]
3469 ""
3470 "fnmpy.d %0 = %1, %2"
3471 [(set_attr "itanium_class" "fmac")])
3473 (define_insn "*nmuldf3_trunc"
3474 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3475 (float_truncate:SF
3476 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3477 (match_operand:DF 2 "fr_register_operand" "f")))))]
3478 ""
3479 "fnmpy.s %0 = %1, %2"
3480 [(set_attr "itanium_class" "fmac")])
3482 (define_insn "*nmadddf4"
3483 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3484 (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
3485 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3486 (match_operand:DF 2 "fr_register_operand" "f"))))]
3487 ""
3488 "fnma.d %0 = %1, %2, %F3"
3489 [(set_attr "itanium_class" "fmac")])
3491 (define_insn "*nmadddf4_alts"
3492 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3493 (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
3494 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3495 (match_operand:DF 2 "fr_register_operand" "f"))))
3496 (use (match_operand:SI 4 "const_int_operand" ""))]
3497 ""
3498 "fnma.d.s%4 %0 = %1, %2, %F3"
3499 [(set_attr "itanium_class" "fmac")])
3501 (define_insn "*nmadddf4_truncsf"
3502 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3503 (float_truncate:SF
3504 (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
3505 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3506 (match_operand:DF 2 "fr_register_operand" "f")))))]
3507 ""
3508 "fnma.s %0 = %1, %2, %F3"
3509 [(set_attr "itanium_class" "fmac")])
3511 (define_insn "*nmadddf4_truncsf_alts"
3512 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3513 (float_truncate:SF
3514 (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
3515 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3516 (match_operand:DF 2 "fr_register_operand" "f")))))
3517 (use (match_operand:SI 4 "const_int_operand" ""))]
3518 ""
3519 "fnma.s.s%4 %0 = %1, %2, %F3"
3520 [(set_attr "itanium_class" "fmac")])
3522 (define_expand "divdf3"
3523 [(set (match_operand:DF 0 "fr_register_operand" "")
3524 (div:DF (match_operand:DF 1 "fr_register_operand" "")
3525 (match_operand:DF 2 "fr_register_operand" "")))]
3526 "TARGET_INLINE_FLOAT_DIV"
3527 {
3528 rtx insn;
3529 if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT)
3530 insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]);
3531 else
3532 insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
3533 emit_insn (insn);
3534 DONE;
3535 })
3537 (define_insn_and_split "divdf3_internal_lat"
3538 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3539 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
3540 (match_operand:DF 2 "fr_register_operand" "f")))
3541 (clobber (match_scratch:XF 3 "=&f"))
3542 (clobber (match_scratch:XF 4 "=&f"))
3543 (clobber (match_scratch:XF 5 "=&f"))
3544 (clobber (match_scratch:BI 6 "=c"))]
3545 "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT"
3546 "#"
3547 "&& reload_completed"
3548 [(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9)))
3549 (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)]
3550 UNSPEC_FR_RECIP_APPROX))
3551 (use (const_int 0))])
3552 (cond_exec (ne (match_dup 6) (const_int 0))
3553 (parallel [(set (match_dup 3) (mult:XF (match_dup 8) (match_dup 7)))
3554 (use (const_int 1))]))
3555 (cond_exec (ne (match_dup 6) (const_int 0))
3556 (parallel [(set (match_dup 4)
3557 (minus:XF (match_dup 12)
3558 (mult:XF (match_dup 9) (match_dup 7))))
3559 (use (const_int 1))]))
3560 (cond_exec (ne (match_dup 6) (const_int 0))
3561 (parallel [(set (match_dup 3)
3562 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3563 (match_dup 3)))
3564 (use (const_int 1))]))
3565 (cond_exec (ne (match_dup 6) (const_int 0))
3566 (parallel [(set (match_dup 5) (mult:XF (match_dup 4) (match_dup 4)))
3567 (use (const_int 1))]))
3568 (cond_exec (ne (match_dup 6) (const_int 0))
3569 (parallel [(set (match_dup 7)
3570 (plus:XF (mult:XF (match_dup 4) (match_dup 7))
3571 (match_dup 7)))
3572 (use (const_int 1))]))
3573 (cond_exec (ne (match_dup 6) (const_int 0))
3574 (parallel [(set (match_dup 3)
3575 (plus:XF (mult:XF (match_dup 5) (match_dup 3))
3576 (match_dup 3)))
3577 (use (const_int 1))]))
3578 (cond_exec (ne (match_dup 6) (const_int 0))
3579 (parallel [(set (match_dup 4) (mult:XF (match_dup 5) (match_dup 5)))
3580 (use (const_int 1))]))
3581 (cond_exec (ne (match_dup 6) (const_int 0))
3582 (parallel [(set (match_dup 7)
3583 (plus:XF (mult:XF (match_dup 5) (match_dup 7))
3584 (match_dup 7)))
3585 (use (const_int 1))]))
3586 (cond_exec (ne (match_dup 6) (const_int 0))
3587 (parallel [(set (match_dup 10)
3588 (float_truncate:DF
3589 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3590 (match_dup 3))))
3591 (use (const_int 1))]))
3592 (cond_exec (ne (match_dup 6) (const_int 0))
3593 (parallel [(set (match_dup 7)
3594 (plus:XF (mult:XF (match_dup 4) (match_dup 7))
3595 (match_dup 7)))
3596 (use (const_int 1))]))
3597 (cond_exec (ne (match_dup 6) (const_int 0))
3598 (parallel [(set (match_dup 11)
3599 (float_truncate:DF
3600 (minus:XF (match_dup 8)
3601 (mult:XF (match_dup 9) (match_dup 3)))))
3602 (use (const_int 1))]))
3603 (cond_exec (ne (match_dup 6) (const_int 0))
3604 (set (match_dup 0)
3605 (float_truncate:DF (plus:XF (mult:XF (match_dup 5) (match_dup 7))
3606 (match_dup 3)))))
3607 ]
3608 {
3609 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3610 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3611 operands[9] = gen_rtx_REG (XFmode, REGNO (operands[2]));
3612 operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3]));
3613 operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5]));
3614 operands[12] = CONST1_RTX (XFmode);
3615 }
3616 [(set_attr "predicable" "no")])
3618 (define_insn_and_split "divdf3_internal_thr"
3619 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3620 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
3621 (match_operand:DF 2 "fr_register_operand" "f")))
3622 (clobber (match_scratch:XF 3 "=&f"))
3623 (clobber (match_scratch:DF 4 "=f"))
3624 (clobber (match_scratch:BI 5 "=c"))]
3625 "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR"
3626 "#"
3627 "&& reload_completed"
3628 [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
3629 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
3630 UNSPEC_FR_RECIP_APPROX))
3631 (use (const_int 0))])
3632 (cond_exec (ne (match_dup 5) (const_int 0))
3633 (parallel [(set (match_dup 3)
3634 (minus:XF (match_dup 10)
3635 (mult:XF (match_dup 8) (match_dup 6))))
3636 (use (const_int 1))]))
3637 (cond_exec (ne (match_dup 5) (const_int 0))
3638 (parallel [(set (match_dup 6)
3639 (plus:XF (mult:XF (match_dup 3) (match_dup 6))
3640 (match_dup 6)))
3641 (use (const_int 1))]))
3642 (cond_exec (ne (match_dup 5) (const_int 0))
3643 (parallel [(set (match_dup 3)
3644 (mult:XF (match_dup 3) (match_dup 3)))
3645 (use (const_int 1))]))
3646 (cond_exec (ne (match_dup 5) (const_int 0))
3647 (parallel [(set (match_dup 6)
3648 (plus:XF (mult:XF (match_dup 3) (match_dup 6))
3649 (match_dup 6)))
3650 (use (const_int 1))]))
3651 (cond_exec (ne (match_dup 5) (const_int 0))
3652 (parallel [(set (match_dup 3)
3653 (mult:XF (match_dup 3) (match_dup 3)))
3654 (use (const_int 1))]))
3655 (cond_exec (ne (match_dup 5) (const_int 0))
3656 (parallel [(set (match_dup 6)
3657 (plus:XF (mult:XF (match_dup 3) (match_dup 6))
3658 (match_dup 6)))
3659 (use (const_int 1))]))
3660 (cond_exec (ne (match_dup 5) (const_int 0))
3661 (parallel [(set (match_dup 9)
3662 (float_truncate:DF
3663 (mult:XF (match_dup 7) (match_dup 6))))
3664 (use (const_int 1))]))
3665 (cond_exec (ne (match_dup 5) (const_int 0))
3666 (parallel [(set (match_dup 4)
3667 (minus:DF (match_dup 1)
3668 (mult:DF (match_dup 2) (match_dup 9))))
3669 (use (const_int 1))]))
3670 (cond_exec (ne (match_dup 5) (const_int 0))
3671 (set (match_dup 0)
3672 (plus:DF (mult:DF (match_dup 4) (match_dup 0))
3673 (match_dup 9))))
3674 ]
3675 {
3676 operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3677 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3678 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
3679 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
3680 operands[10] = CONST1_RTX (XFmode);
3681 }
3682 [(set_attr "predicable" "no")])
3684 ;; Inline square root.
3686 (define_expand "sqrtdf2"
3687 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3688 (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f")))]
3689 "TARGET_INLINE_SQRT"
3690 {
3691 rtx insn;
3692 #if 0
3693 if (TARGET_INLINE_SQRT == INL_MIN_LAT)
3694 insn = gen_sqrtdf2_internal_lat (operands[0], operands[1]);
3695 else
3696 #else
3697 gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT);
3698 #endif
3699 insn = gen_sqrtdf2_internal_thr (operands[0], operands[1]);
3700 emit_insn (insn);
3701 DONE;
3702 })
3704 ;; Latency-optimized square root.
3705 ;; FIXME: Implement.
3707 ;; Throughput-optimized square root.
3709 (define_insn_and_split "sqrtdf2_internal_thr"
3710 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3711 (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f")))
3712 ;; Register r2 in optimization guide.
3713 (clobber (match_scratch:DI 2 "=r"))
3714 ;; Register f8 in optimization guide
3715 (clobber (match_scratch:XF 3 "=&f"))
3716 ;; Register f9 in optimization guide
3717 (clobber (match_scratch:XF 4 "=&f"))
3718 ;; Register f10 in optimization guide
3719 (clobber (match_scratch:XF 5 "=&f"))
3720 ;; Register p6 in optimization guide.
3721 (clobber (match_scratch:BI 6 "=c"))]
3722 "TARGET_INLINE_SQRT == INL_MAX_THR"
3723 "#"
3724 "&& reload_completed"
3725 [ ;; exponent of +1/2 in r2
3726 (set (match_dup 2) (const_int 65534))
3727 ;; +1/2 in f10
3728 (set (match_dup 5)
3729 (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP))
3730 ;; Step 1
3731 ;; y0 = 1/sqrt(a) in f7
3732 (parallel [(set (match_dup 7)
3733 (div:XF (const_int 1)
3734 (sqrt:XF (match_dup 8))))
3735 (set (match_dup 6)
3736 (unspec:BI [(match_dup 8)]
3737 UNSPEC_FR_SQRT_RECIP_APPROX))
3738 (use (const_int 0))])
3739 ;; Step 2
3740 ;; H0 = 1/2 * y0 in f8
3741 (cond_exec (ne (match_dup 6) (const_int 0))
3742 (parallel [(set (match_dup 3)
3743 (plus:XF (mult:XF (match_dup 5) (match_dup 7))
3744 (match_dup 9)))
3745 (use (const_int 1))]))
3746 ;; Step 3
3747 ;; G0 = a * y0 in f7
3748 (cond_exec (ne (match_dup 6) (const_int 0))
3749 (parallel [(set (match_dup 7)
3750 (plus:XF (mult:XF (match_dup 8) (match_dup 7))
3751 (match_dup 9)))
3752 (use (const_int 1))]))
3753 ;; Step 4
3754 ;; r0 = 1/2 - G0 * H0 in f9
3755 (cond_exec (ne (match_dup 6) (const_int 0))
3756 (parallel [(set (match_dup 4)
3757 (minus:XF (match_dup 5)
3758 (mult:XF (match_dup 7) (match_dup 3))))
3759 (use (const_int 1))]))
3760 ;; Step 5
3761 ;; H1 = H0 + r0 * H0 in f8
3762 (cond_exec (ne (match_dup 6) (const_int 0))
3763 (parallel [(set (match_dup 3)
3764 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3765 (match_dup 3)))
3766 (use (const_int 1))]))
3767 ;; Step 6
3768 ;; G1 = G0 + r0 * G0 in f7
3769 (cond_exec (ne (match_dup 6) (const_int 0))
3770 (parallel [(set (match_dup 7)
3771 (plus:XF (mult:XF (match_dup 4) (match_dup 7))
3772 (match_dup 7)))
3773 (use (const_int 1))]))
3774 ;; Step 7
3775 ;; r1 = 1/2 - G1 * H1 in f9
3776 (cond_exec (ne (match_dup 6) (const_int 0))
3777 (parallel [(set (match_dup 4)
3778 (minus:XF (match_dup 5)
3779 (mult:XF (match_dup 7) (match_dup 3))))
3780 (use (const_int 1))]))
3781 ;; Step 8
3782 ;; H2 = H1 + r1 * H1 in f8
3783 (cond_exec (ne (match_dup 6) (const_int 0))
3784 (parallel [(set (match_dup 3)
3785 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3786 (match_dup 3)))
3787 (use (const_int 1))]))
3788 ;; Step 9
3789 ;; G2 = G1 + r1 * G1 in f7
3790 (cond_exec (ne (match_dup 6) (const_int 0))
3791 (parallel [(set (match_dup 7)
3792 (plus:XF (mult:XF (match_dup 4) (match_dup 7))
3793 (match_dup 7)))
3794 (use (const_int 1))]))
3795 ;; Step 10
3796 ;; d2 = a - G2 * G2 in f9
3797 (cond_exec (ne (match_dup 6) (const_int 0))
3798 (parallel [(set (match_dup 4)
3799 (minus:XF (match_dup 8)
3800 (mult:XF (match_dup 7) (match_dup 7))))
3801 (use (const_int 1))]))
3802 ;; Step 11
3803 ;; G3 = G2 + d2 * H2 in f7
3804 (cond_exec (ne (match_dup 6) (const_int 0))
3805 (parallel [(set (match_dup 7)
3806 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3807 (match_dup 7)))
3808 (use (const_int 1))]))
3809 ;; Step 12
3810 ;; d3 = a - G3 * G3 in f9
3811 (cond_exec (ne (match_dup 6) (const_int 0))
3812 (parallel [(set (match_dup 4)
3813 (minus:XF (match_dup 8)
3814 (mult:XF (match_dup 7) (match_dup 7))))
3815 (use (const_int 1))]))
3816 ;; Step 13
3817 ;; S = G3 + d3 * H2 in f7
3818 (cond_exec (ne (match_dup 6) (const_int 0))
3819 (parallel [(set (match_dup 0)
3820 (float_truncate:DF
3821 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3822 (match_dup 7))))
3823 (use (const_int 0))]))]
3824 {
3825 /* Generate 82-bit versions of the input and output operands. */
3826 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3827 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3828 /* Generate required floating-point constants. */
3829 operands[9] = CONST0_RTX (XFmode);
3830 }
3831 [(set_attr "predicable" "no")])
3832 \f
3833 ;; ::::::::::::::::::::
3834 ;; ::
3835 ;; :: 80-bit floating point arithmetic
3836 ;; ::
3837 ;; ::::::::::::::::::::
3839 (define_insn "addxf3"
3840 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3841 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3842 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3843 ""
3844 "fadd %0 = %F1, %F2"
3845 [(set_attr "itanium_class" "fmac")])
3847 (define_insn "*addxf3_truncsf"
3848 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3849 (float_truncate:SF
3850 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3851 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3852 ""
3853 "fadd.s %0 = %F1, %F2"
3854 [(set_attr "itanium_class" "fmac")])
3856 (define_insn "*addxf3_truncdf"
3857 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3858 (float_truncate:DF
3859 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3860 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3861 ""
3862 "fadd.d %0 = %F1, %F2"
3863 [(set_attr "itanium_class" "fmac")])
3865 (define_insn "subxf3"
3866 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3867 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3868 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3869 ""
3870 "fsub %0 = %F1, %F2"
3871 [(set_attr "itanium_class" "fmac")])
3873 (define_insn "*subxf3_truncsf"
3874 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3875 (float_truncate:SF
3876 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3877 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3878 ""
3879 "fsub.s %0 = %F1, %F2"
3880 [(set_attr "itanium_class" "fmac")])
3882 (define_insn "*subxf3_truncdf"
3883 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3884 (float_truncate:DF
3885 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3886 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3887 ""
3888 "fsub.d %0 = %F1, %F2"
3889 [(set_attr "itanium_class" "fmac")])
3891 (define_insn "mulxf3"
3892 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3893 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3894 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3895 ""
3896 "fmpy %0 = %F1, %F2"
3897 [(set_attr "itanium_class" "fmac")])
3899 (define_insn "*mulxf3_truncsf"
3900 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3901 (float_truncate:SF
3902 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3903 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3904 ""
3905 "fmpy.s %0 = %F1, %F2"
3906 [(set_attr "itanium_class" "fmac")])
3908 (define_insn "*mulxf3_truncdf"
3909 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3910 (float_truncate:DF
3911 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3912 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3913 ""
3914 "fmpy.d %0 = %F1, %F2"
3915 [(set_attr "itanium_class" "fmac")])
3917 (define_insn "*mulxf3_alts"
3918 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3919 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3920 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))
3921 (use (match_operand:SI 3 "const_int_operand" ""))]
3922 ""
3923 "fmpy.s%3 %0 = %F1, %F2"
3924 [(set_attr "itanium_class" "fmac")])
3926 (define_insn "*mulxf3_truncsf_alts"
3927 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3928 (float_truncate:SF
3929 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3930 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))
3931 (use (match_operand:SI 3 "const_int_operand" ""))]
3932 ""
3933 "fmpy.s.s%3 %0 = %F1, %F2"
3934 [(set_attr "itanium_class" "fmac")])
3936 (define_insn "*mulxf3_truncdf_alts"
3937 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3938 (float_truncate:DF
3939 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3940 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))
3941 (use (match_operand:SI 3 "const_int_operand" ""))]
3942 ""
3943 "fmpy.d.s%3 %0 = %F1, %F2"
3944 [(set_attr "itanium_class" "fmac")])
3946 (define_insn "absxf2"
3947 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3948 (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))]
3949 ""
3950 "fabs %0 = %F1"
3951 [(set_attr "itanium_class" "fmisc")])
3953 (define_insn "negxf2"
3954 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3955 (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))]
3956 ""
3957 "fneg %0 = %F1"
3958 [(set_attr "itanium_class" "fmisc")])
3960 (define_insn "*nabsxf2"
3961 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3962 (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))]
3963 ""
3964 "fnegabs %0 = %F1"
3965 [(set_attr "itanium_class" "fmisc")])
3967 (define_insn "copysignxf3"
3968 [(set (match_operand:XF 0 "register_operand" "=f")
3969 (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3970 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")]
3971 UNSPEC_COPYSIGN))]
3972 ""
3973 "fmerge.s %0 = %F2, %F1"
3974 [(set_attr "itanium_class" "fmisc")])
3976 (define_insn "*ncopysignxf3"
3977 [(set (match_operand:XF 0 "register_operand" "=f")
3978 (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3979 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")]
3980 UNSPEC_COPYSIGN)))]
3981 ""
3982 "fmerge.ns %0 = %F2, %F1"
3983 [(set_attr "itanium_class" "fmisc")])
3985 (define_insn "sminxf3"
3986 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3987 (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3988 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3989 ""
3990 "fmin %0 = %F1, %F2"
3991 [(set_attr "itanium_class" "fmisc")])
3993 (define_insn "smaxxf3"
3994 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3995 (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3996 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3997 ""
3998 "fmax %0 = %F1, %F2"
3999 [(set_attr "itanium_class" "fmisc")])
4001 (define_insn "*maddxf4"
4002 [(set (match_operand:XF 0 "fr_register_operand" "=f")
4003 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4004 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
4005 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))]
4006 ""
4007 "fma %0 = %F1, %F2, %F3"
4008 [(set_attr "itanium_class" "fmac")])
4010 (define_insn "*maddxf4_truncsf"
4011 [(set (match_operand:SF 0 "fr_register_operand" "=f")
4012 (float_truncate:SF
4013 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4014 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
4015 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
4016 ""
4017 "fma.s %0 = %F1, %F2, %F3"
4018 [(set_attr "itanium_class" "fmac")])
4020 (define_insn "*maddxf4_truncdf"
4021 [(set (match_operand:DF 0 "fr_register_operand" "=f")
4022 (float_truncate:DF
4023 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4024 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
4025 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
4026 ""
4027 "fma.d %0 = %F1, %F2, %F3"
4028 [(set_attr "itanium_class" "fmac")])
4030 (define_insn "*maddxf4_alts"
4031 [(set (match_operand:XF 0 "fr_register_operand" "=f")
4032 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4033 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
4034 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))
4035 (use (match_operand:SI 4 "const_int_operand" ""))]
4036 ""
4037 "fma.s%4 %0 = %F1, %F2, %F3"
4038 [(set_attr "itanium_class" "fmac")])
4040 (define_insn "*maddxf4_alts_truncsf"
4041 [(set (match_operand:SF 0 "fr_register_operand" "=f")
4042 (float_truncate:SF
4043 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4044 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
4045 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))
4046 (use (match_operand:SI 4 "const_int_operand" ""))]
4047 ""
4048 "fma.s.s%4 %0 = %F1, %F2, %F3"
4049 [(set_attr "itanium_class" "fmac")])
4051 (define_insn "*maddxf4_alts_truncdf"
4052 [(set (match_operand:DF 0 "fr_register_operand" "=f")
4053 (float_truncate:DF
4054 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4055 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
4056 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))
4057 (use (match_operand:SI 4 "const_int_operand" ""))]
4058 ""
4059 "fma.d.s%4 %0 = %F1, %F2, %F3"
4060 [(set_attr "itanium_class" "fmac")])
4062 (define_insn "*msubxf4"
4063 [(set (match_operand:XF 0 "fr_register_operand" "=f")
4064 (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4065 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
4066 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))]
4067 ""
4068 "fms %0 = %F1, %F2, %F3"
4069 [(set_attr "itanium_class" "fmac")])
4071 (define_insn "*msubxf4_truncsf"
4072 [(set (match_operand:SF 0 "fr_register_operand" "=f")
4073 (float_truncate:SF
4074 (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4075 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
4076 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
4077 ""
4078 "fms.s %0 = %F1, %F2, %F3"
4079 [(set_attr "itanium_class" "fmac")])
4081 (define_insn "*msubxf4_truncdf"
4082 [(set (match_operand:DF 0 "fr_register_operand" "=f")
4083 (float_truncate:DF
4084 (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4085 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
4086 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
4087 ""
4088 "fms.d %0 = %F1, %F2, %F3"
4089 [(set_attr "itanium_class" "fmac")])
4091 (define_insn "*nmulxf3"
4092 [(set (match_operand:XF 0 "fr_register_operand" "=f")
4093 (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4094 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
4095 ""
4096 "fnmpy %0 = %F1, %F2"
4097 [(set_attr "itanium_class" "fmac")])
4099 (define_insn "*nmulxf3_truncsf"
4100 [(set (match_operand:SF 0 "fr_register_operand" "=f")
4101 (float_truncate:SF
4102 (neg:XF (mult:XF
4103 (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4104 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))]
4105 ""
4106 "fnmpy.s %0 = %F1, %F2"
4107 [(set_attr "itanium_class" "fmac")])
4109 (define_insn "*nmulxf3_truncdf"
4110 [(set (match_operand:DF 0 "fr_register_operand" "=f")
4111 (float_truncate:DF
4112 (neg:XF (mult:XF
4113 (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4114 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))]
4115 ""
4116 "fnmpy.d %0 = %F1, %F2"
4117 [(set_attr "itanium_class" "fmac")])
4119 (define_insn "*nmaddxf4"
4120 [(set (match_operand:XF 0 "fr_register_operand" "=f")
4121 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
4122 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4123 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
4124 )))]
4125 ""
4126 "fnma %0 = %F1, %F2, %F3"
4127 [(set_attr "itanium_class" "fmac")])
4129 (define_insn "*nmaddxf4_truncsf"
4130 [(set (match_operand:SF 0 "fr_register_operand" "=f")
4131 (float_truncate:SF
4132 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
4133 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4134 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
4135 ))))]
4136 ""
4137 "fnma.s %0 = %F1, %F2, %F3"
4138 [(set_attr "itanium_class" "fmac")])
4140 (define_insn "*nmaddxf4_truncdf"
4141 [(set (match_operand:DF 0 "fr_register_operand" "=f")
4142 (float_truncate:DF
4143 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
4144 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4145 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
4146 ))))]
4147 ""
4148 "fnma.d %0 = %F1, %F2, %F3"
4149 [(set_attr "itanium_class" "fmac")])
4151 (define_insn "*nmaddxf4_alts"
4152 [(set (match_operand:XF 0 "fr_register_operand" "=f")
4153 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
4154 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4155 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
4156 )))
4157 (use (match_operand:SI 4 "const_int_operand" ""))]
4158 ""
4159 "fnma.s%4 %0 = %F1, %F2, %F3"
4160 [(set_attr "itanium_class" "fmac")])
4162 (define_insn "*nmaddxf4_truncsf_alts"
4163 [(set (match_operand:SF 0 "fr_register_operand" "=f")
4164 (float_truncate:SF
4165 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
4166 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4167 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
4168 ))))
4169 (use (match_operand:SI 4 "const_int_operand" ""))]
4170 ""
4171 "fnma.s.s%4 %0 = %F1, %F2, %F3"
4172 [(set_attr "itanium_class" "fmac")])
4174 (define_insn "*nmaddxf4_truncdf_alts"
4175 [(set (match_operand:DF 0 "fr_register_operand" "=f")
4176 (float_truncate:DF
4177 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
4178 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4179 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
4180 ))))
4181 (use (match_operand:SI 4 "const_int_operand" ""))]
4182 ""
4183 "fnma.d.s%4 %0 = %F1, %F2, %F3"
4184 [(set_attr "itanium_class" "fmac")])
4186 (define_expand "divxf3"
4187 [(set (match_operand:XF 0 "fr_register_operand" "")
4188 (div:XF (match_operand:XF 1 "fr_register_operand" "")
4189 (match_operand:XF 2 "fr_register_operand" "")))]
4190 "TARGET_INLINE_FLOAT_DIV"
4191 {
4192 rtx insn;
4193 if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT)
4194 insn = gen_divxf3_internal_lat (operands[0], operands[1], operands[2]);
4195 else
4196 insn = gen_divxf3_internal_thr (operands[0], operands[1], operands[2]);
4197 emit_insn (insn);
4198 DONE;
4199 })
4201 (define_insn_and_split "divxf3_internal_lat"
4202 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
4203 (div:XF (match_operand:XF 1 "fr_register_operand" "f")
4204 (match_operand:XF 2 "fr_register_operand" "f")))
4205 (clobber (match_scratch:XF 3 "=&f"))
4206 (clobber (match_scratch:XF 4 "=&f"))
4207 (clobber (match_scratch:XF 5 "=&f"))
4208 (clobber (match_scratch:XF 6 "=&f"))
4209 (clobber (match_scratch:BI 7 "=c"))]
4210 "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT"
4211 "#"
4212 "&& reload_completed"
4213 [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
4214 (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)]
4215 UNSPEC_FR_RECIP_APPROX))
4216 (use (const_int 0))])
4217 (cond_exec (ne (match_dup 7) (const_int 0))
4218 (parallel [(set (match_dup 3)
4219 (minus:XF (match_dup 8)
4220 (mult:XF (match_dup 2) (match_dup 0))))
4221 (use (const_int 1))]))
4222 (cond_exec (ne (match_dup 7) (const_int 0))
4223 (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
4224 (use (const_int 1))]))
4225 (cond_exec (ne (match_dup 7) (const_int 0))
4226 (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3)))
4227 (use (const_int 1))]))
4228 (cond_exec (ne (match_dup 7) (const_int 0))
4229 (parallel [(set (match_dup 6)
4230 (plus:XF (mult:XF (match_dup 3) (match_dup 3))
4231 (match_dup 3)))
4232 (use (const_int 1))]))
4233 (cond_exec (ne (match_dup 7) (const_int 0))
4234 (parallel [(set (match_dup 3)
4235 (plus:XF (mult:XF (match_dup 5) (match_dup 5))
4236 (match_dup 3)))
4237 (use (const_int 1))]))
4238 (cond_exec (ne (match_dup 7) (const_int 0))
4239 (parallel [(set (match_dup 5)
4240 (plus:XF (mult:XF (match_dup 6) (match_dup 0))
4241 (match_dup 0)))
4242 (use (const_int 1))]))
4243 (cond_exec (ne (match_dup 7) (const_int 0))
4244 (parallel [(set (match_dup 0)
4245 (plus:XF (mult:XF (match_dup 5) (match_dup 3))
4246 (match_dup 0)))
4247 (use (const_int 1))]))
4248 (cond_exec (ne (match_dup 7) (const_int 0))
4249 (parallel [(set (match_dup 4)
4250 (minus:XF (match_dup 1)
4251 (mult:XF (match_dup 2) (match_dup 4))))
4252 (use (const_int 1))]))
4253 (cond_exec (ne (match_dup 7) (const_int 0))
4254 (parallel [(set (match_dup 3)
4255 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
4256 (match_dup 4)))
4257 (use (const_int 1))]))
4258 (cond_exec (ne (match_dup 7) (const_int 0))
4259 (parallel [(set (match_dup 5)
4260 (minus:XF (match_dup 8)
4261 (mult:XF (match_dup 2) (match_dup 0))))
4262 (use (const_int 1))]))
4263 (cond_exec (ne (match_dup 7) (const_int 0))
4264 (parallel [(set (match_dup 0)
4265 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
4266 (match_dup 0)))
4267 (use (const_int 1))]))
4268 (cond_exec (ne (match_dup 7) (const_int 0))
4269 (parallel [(set (match_dup 4)
4270 (minus:XF (match_dup 1)
4271 (mult:XF (match_dup 2) (match_dup 3))))
4272 (use (const_int 1))]))
4273 (cond_exec (ne (match_dup 7) (const_int 0))
4274 (set (match_dup 0)
4275 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
4276 (match_dup 3))))
4277 ]
4278 "operands[8] = CONST1_RTX (XFmode);"
4279 [(set_attr "predicable" "no")])
4281 (define_insn_and_split "divxf3_internal_thr"
4282 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
4283 (div:XF (match_operand:XF 1 "fr_register_operand" "f")
4284 (match_operand:XF 2 "fr_register_operand" "f")))
4285 (clobber (match_scratch:XF 3 "=&f"))
4286 (clobber (match_scratch:XF 4 "=&f"))
4287 (clobber (match_scratch:BI 5 "=c"))]
4288 "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR"
4289 "#"
4290 "&& reload_completed"
4291 [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
4292 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
4293 UNSPEC_FR_RECIP_APPROX))
4294 (use (const_int 0))])
4295 (cond_exec (ne (match_dup 5) (const_int 0))
4296 (parallel [(set (match_dup 3)
4297 (minus:XF (match_dup 6)
4298 (mult:XF (match_dup 2) (match_dup 0))))
4299 (use (const_int 1))]))
4300 (cond_exec (ne (match_dup 5) (const_int 0))
4301 (parallel [(set (match_dup 4)
4302 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
4303 (match_dup 0)))
4304 (use (const_int 1))]))
4305 (cond_exec (ne (match_dup 5) (const_int 0))
4306 (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3)))
4307 (use (const_int 1))]))
4308 (cond_exec (ne (match_dup 5) (const_int 0))
4309 (parallel [(set (match_dup 3)
4310 (plus:XF (mult:XF (match_dup 3) (match_dup 4))
4311 (match_dup 4)))
4312 (use (const_int 1))]))
4313 (cond_exec (ne (match_dup 5) (const_int 0))
4314 (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
4315 (use (const_int 1))]))
4316 (cond_exec (ne (match_dup 5) (const_int 0))
4317 (parallel [(set (match_dup 0)
4318 (minus:XF (match_dup 6)
4319 (mult:XF (match_dup 2) (match_dup 3))))
4320 (use (const_int 1))]))
4321 (cond_exec (ne (match_dup 5) (const_int 0))
4322 (parallel [(set (match_dup 0)
4323 (plus:XF (mult:XF (match_dup 0) (match_dup 3))
4324 (match_dup 3)))
4325 (use (const_int 1))]))
4326 (cond_exec (ne (match_dup 5) (const_int 0))
4327 (parallel [(set (match_dup 3)
4328 (minus:XF (match_dup 1)
4329 (mult:XF (match_dup 2) (match_dup 4))))
4330 (use (const_int 1))]))
4331 (cond_exec (ne (match_dup 5) (const_int 0))
4332 (parallel [(set (match_dup 3)
4333 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
4334 (match_dup 4)))
4335 (use (const_int 1))]))
4336 (cond_exec (ne (match_dup 5) (const_int 0))
4337 (parallel [(set (match_dup 4)
4338 (minus:XF (match_dup 6)
4339 (mult:XF (match_dup 2) (match_dup 0))))
4340 (use (const_int 1))]))
4341 (cond_exec (ne (match_dup 5) (const_int 0))
4342 (parallel [(set (match_dup 0)
4343 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
4344 (match_dup 0)))
4345 (use (const_int 1))]))
4346 (cond_exec (ne (match_dup 5) (const_int 0))
4347 (parallel [(set (match_dup 4)
4348 (minus:XF (match_dup 1)
4349 (mult:XF (match_dup 2) (match_dup 3))))
4350 (use (const_int 1))]))
4351 (cond_exec (ne (match_dup 5) (const_int 0))
4352 (set (match_dup 0)
4353 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
4354 (match_dup 3))))
4355 ]
4356 "operands[6] = CONST1_RTX (XFmode);"
4357 [(set_attr "predicable" "no")])
4359 ;; Inline square root.
4361 (define_expand "sqrtxf2"
4362 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
4363 (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f")))]
4364 "TARGET_INLINE_SQRT"
4365 {
4366 rtx insn;
4367 #if 0
4368 if (TARGET_INLINE_SQRT == INL_MIN_LAT)
4369 insn = gen_sqrtxf2_internal_lat (operands[0], operands[1]);
4370 else
4371 #else
4372 gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT);
4373 #endif
4374 insn = gen_sqrtxf2_internal_thr (operands[0], operands[1]);
4375 emit_insn (insn);
4376 DONE;
4377 })
4379 ;; Latency-optimized square root.
4380 ;; FIXME: Implement.
4382 ;; Throughput-optimized square root.
4384 (define_insn_and_split "sqrtxf2_internal_thr"
4385 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
4386 (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f")))
4387 ;; Register r2 in optimization guide.
4388 (clobber (match_scratch:DI 2 "=r"))
4389 ;; Register f8 in optimization guide
4390 (clobber (match_scratch:XF 3 "=&f"))
4391 ;; Register f9 in optimization guide
4392 (clobber (match_scratch:XF 4 "=&f"))
4393 ;; Register f10 in optimization guide
4394 (clobber (match_scratch:XF 5 "=&f"))
4395 ;; Register f11 in optimization guide
4396 (clobber (match_scratch:XF 6 "=&f"))
4397 ;; Register p6 in optimization guide.
4398 (clobber (match_scratch:BI 7 "=c"))]
4399 "TARGET_INLINE_SQRT == INL_MAX_THR"
4400 "#"
4401 "&& reload_completed"
4402 [ ;; exponent of +1/2 in r2
4403 (set (match_dup 2) (const_int 65534))
4404 ;; +1/2 in f8. The Intel manual mistakenly specifies f10.
4405 (set (match_dup 3)
4406 (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP))
4407 ;; Step 1
4408 ;; y0 = 1/sqrt(a) in f7
4409 (parallel [(set (match_dup 8)
4410 (div:XF (const_int 1)
4411 (sqrt:XF (match_dup 9))))
4412 (set (match_dup 7)
4413 (unspec:BI [(match_dup 9)]
4414 UNSPEC_FR_SQRT_RECIP_APPROX))
4415 (use (const_int 0))])
4416 ;; Step 2
4417 ;; H0 = 1/2 * y0 in f9
4418 (cond_exec (ne (match_dup 7) (const_int 0))
4419 (parallel [(set (match_dup 4)
4420 (plus:XF (mult:XF (match_dup 3) (match_dup 8))
4421 (match_dup 10)))
4422 (use (const_int 1))]))
4423 ;; Step 3
4424 ;; S0 = a * y0 in f7
4425 (cond_exec (ne (match_dup 7) (const_int 0))
4426 (parallel [(set (match_dup 8)
4427 (plus:XF (mult:XF (match_dup 9) (match_dup 8))
4428 (match_dup 10)))
4429 (use (const_int 1))]))
4430 ;; Step 4
4431 ;; d0 = 1/2 - S0 * H0 in f10
4432 (cond_exec (ne (match_dup 7) (const_int 0))
4433 (parallel [(set (match_dup 5)
4434 (minus:XF (match_dup 3)
4435 (mult:XF (match_dup 8) (match_dup 4))))
4436 (use (const_int 1))]))
4437 ;; Step 5
4438 ;; H1 = H0 + d0 * H0 in f9
4439 (cond_exec (ne (match_dup 7) (const_int 0))
4440 (parallel [(set (match_dup 4)
4441 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
4442 (match_dup 4)))
4443 (use (const_int 1))]))
4444 ;; Step 6
4445 ;; S1 = S0 + d0 * S0 in f7
4446 (cond_exec (ne (match_dup 7) (const_int 0))
4447 (parallel [(set (match_dup 8)
4448 (plus:XF (mult:XF (match_dup 5) (match_dup 8))
4449 (match_dup 8)))
4450 (use (const_int 1))]))
4451 ;; Step 7
4452 ;; d1 = 1/2 - S1 * H1 in f10
4453 (cond_exec (ne (match_dup 7) (const_int 0))
4454 (parallel [(set (match_dup 5)
4455 (minus:XF (match_dup 3)
4456 (mult:XF (match_dup 8) (match_dup 4))))
4457 (use (const_int 1))]))
4458 ;; Step 8
4459 ;; H2 = H1 + d1 * H1 in f9
4460 (cond_exec (ne (match_dup 7) (const_int 0))
4461 (parallel [(set (match_dup 4)
4462 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
4463 (match_dup 4)))
4464 (use (const_int 1))]))
4465 ;; Step 9
4466 ;; S2 = S1 + d1 * S1 in f7
4467 (cond_exec (ne (match_dup 7) (const_int 0))
4468 (parallel [(set (match_dup 8)
4469 (plus:XF (mult:XF (match_dup 5) (match_dup 8))
4470 (match_dup 8)))
4471 (use (const_int 1))]))
4472 ;; Step 10
4473 ;; d2 = 1/2 - S2 * H2 in f10
4474 (cond_exec (ne (match_dup 7) (const_int 0))
4475 (parallel [(set (match_dup 5)
4476 (minus:XF (match_dup 3)
4477 (mult:XF (match_dup 8) (match_dup 4))))
4478 (use (const_int 1))]))
4479 ;; Step 11
4480 ;; e2 = a - S2 * S2 in f8
4481 (cond_exec (ne (match_dup 7) (const_int 0))
4482 (parallel [(set (match_dup 3)
4483 (minus:XF (match_dup 9)
4484 (mult:XF (match_dup 8) (match_dup 8))))
4485 (use (const_int 1))]))
4486 ;; Step 12
4487 ;; S3 = S2 + e2 * H2 in f7
4488 (cond_exec (ne (match_dup 7) (const_int 0))
4489 (parallel [(set (match_dup 8)
4490 (plus:XF (mult:XF (match_dup 3) (match_dup 4))
4491 (match_dup 8)))
4492 (use (const_int 1))]))
4493 ;; Step 13
4494 ;; H3 = H2 + d2 * H2 in f9
4495 (cond_exec (ne (match_dup 7) (const_int 0))
4496 (parallel [(set (match_dup 4)
4497 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
4498 (match_dup 4)))
4499 (use (const_int 1))]))
4500 ;; Step 14
4501 ;; e3 = a - S3 * S3 in f8
4502 (cond_exec (ne (match_dup 7) (const_int 0))
4503 (parallel [(set (match_dup 3)
4504 (minus:XF (match_dup 9)
4505 (mult:XF (match_dup 8) (match_dup 8))))
4506 (use (const_int 1))]))
4507 ;; Step 15
4508 ;; S = S3 + e3 * H3 in f7
4509 (cond_exec (ne (match_dup 7) (const_int 0))
4510 (parallel [(set (match_dup 0)
4511 (plus:XF (mult:XF (match_dup 3) (match_dup 4))
4512 (match_dup 8)))
4513 (use (const_int 0))]))]
4514 {
4515 /* Generate 82-bit versions of the input and output operands. */
4516 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[0]));
4517 operands[9] = gen_rtx_REG (XFmode, REGNO (operands[1]));
4518 /* Generate required floating-point constants. */
4519 operands[10] = CONST0_RTX (XFmode);
4520 }
4521 [(set_attr "predicable" "no")])
4523 ;; ??? frcpa works like cmp.foo.unc.
4525 (define_insn "*recip_approx"
4526 [(set (match_operand:XF 0 "fr_register_operand" "=f")
4527 (div:XF (const_int 1)
4528 (match_operand:XF 3 "fr_register_operand" "f")))
4529 (set (match_operand:BI 1 "register_operand" "=c")
4530 (unspec:BI [(match_operand:XF 2 "fr_register_operand" "f")
4531 (match_dup 3)] UNSPEC_FR_RECIP_APPROX))
4532 (use (match_operand:SI 4 "const_int_operand" ""))]
4533 ""
4534 "frcpa.s%4 %0, %1 = %2, %3"
4535 [(set_attr "itanium_class" "fmisc")
4536 (set_attr "predicable" "no")])
4537 \f
4538 ;; ::::::::::::::::::::
4539 ;; ::
4540 ;; :: 32-bit Integer Shifts and Rotates
4541 ;; ::
4542 ;; ::::::::::::::::::::
4544 (define_expand "ashlsi3"
4545 [(set (match_operand:SI 0 "gr_register_operand" "")
4546 (ashift:SI (match_operand:SI 1 "gr_register_operand" "")
4547 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
4548 ""
4549 {
4550 if (GET_CODE (operands[2]) != CONST_INT)
4551 {
4552 /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now
4553 we've got to get rid of stray bits outside the SImode register. */
4554 rtx subshift = gen_reg_rtx (DImode);
4555 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
4556 operands[2] = subshift;
4557 }
4558 })
4560 (define_insn "*ashlsi3_internal"
4561 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
4562 (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r")
4563 (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))]
4564 ""
4565 "@
4566 shladd %0 = %1, %2, r0
4567 dep.z %0 = %1, %2, %E2
4568 shl %0 = %1, %2"
4569 [(set_attr "itanium_class" "ialu,ishf,mmshf")])
4571 (define_expand "ashrsi3"
4572 [(set (match_operand:SI 0 "gr_register_operand" "")
4573 (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
4574 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
4575 ""
4576 {
4577 rtx subtarget = gen_reg_rtx (DImode);
4578 if (GET_CODE (operands[2]) == CONST_INT)
4579 emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
4580 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
4581 else
4582 {
4583 rtx subshift = gen_reg_rtx (DImode);
4584 emit_insn (gen_extendsidi2 (subtarget, operands[1]));
4585 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
4586 emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift));
4587 }
4588 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
4589 DONE;
4590 })
4592 (define_expand "lshrsi3"
4593 [(set (match_operand:SI 0 "gr_register_operand" "")
4594 (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
4595 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
4596 ""
4597 {
4598 rtx subtarget = gen_reg_rtx (DImode);
4599 if (GET_CODE (operands[2]) == CONST_INT)
4600 emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
4601 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
4602 else
4603 {
4604 rtx subshift = gen_reg_rtx (DImode);
4605 emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
4606 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
4607 emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift));
4608 }
4609 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
4610 DONE;
4611 })
4613 ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result
4614 ;; here, instead of 64 like the patterns above. Keep the pattern together
4615 ;; until after combine; otherwise it won't get matched often.
4617 (define_expand "rotrsi3"
4618 [(set (match_operand:SI 0 "gr_register_operand" "")
4619 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "")
4620 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
4621 ""
4622 {
4623 if (GET_MODE (operands[2]) != VOIDmode)
4624 {
4625 rtx tmp = gen_reg_rtx (DImode);
4626 emit_insn (gen_zero_extendsidi2 (tmp, operands[2]));
4627 operands[2] = tmp;
4628 }
4629 })
4631 (define_insn_and_split "*rotrsi3_internal"
4632 [(set (match_operand:SI 0 "gr_register_operand" "=&r")
4633 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r")
4634 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))]
4635 ""
4636 "#"
4637 "reload_completed"
4638 [(set (match_dup 3)
4639 (ior:DI (zero_extend:DI (match_dup 1))
4640 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
4641 (set (match_dup 3)
4642 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
4643 "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));")
4645 (define_expand "rotlsi3"
4646 [(set (match_operand:SI 0 "gr_register_operand" "")
4647 (rotate:SI (match_operand:SI 1 "gr_register_operand" "")
4648 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
4649 ""
4650 {
4651 if (! shift_32bit_count_operand (operands[2], SImode))
4652 {
4653 rtx tmp = gen_reg_rtx (SImode);
4654 emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2]));
4655 emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp));
4656 DONE;
4657 }
4658 })
4660 (define_insn_and_split "*rotlsi3_internal"
4661 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4662 (rotate:SI (match_operand:SI 1 "gr_register_operand" "r")
4663 (match_operand:SI 2 "shift_32bit_count_operand" "n")))]
4664 ""
4665 "mux2 %0 = %1, 0xe1"
4666 "reload_completed && INTVAL (operands[2]) != 16"
4667 [(set (match_dup 3)
4668 (ior:DI (zero_extend:DI (match_dup 1))
4669 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
4670 (set (match_dup 3)
4671 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
4672 {
4673 operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
4674 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
4675 }
4676 [(set_attr "itanium_class" "mmshf")])
4677 \f
4678 ;; ::::::::::::::::::::
4679 ;; ::
4680 ;; :: 64-bit Integer Shifts and Rotates
4681 ;; ::
4682 ;; ::::::::::::::::::::
4684 (define_insn "ashldi3"
4685 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
4686 (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r")
4687 (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))]
4688 ""
4689 "@
4690 shladd %0 = %1, %2, r0
4691 shl %0 = %1, %2
4692 shl %0 = %1, %2"
4693 [(set_attr "itanium_class" "ialu,mmshf,mmshfi")])
4695 ;; ??? Maybe combine this with the multiply and add instruction?
4697 (define_insn "*shladd"
4698 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4699 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
4700 (match_operand:DI 2 "shladd_operand" "n"))
4701 (match_operand:DI 3 "gr_register_operand" "r")))]
4702 ""
4703 "shladd %0 = %1, %S2, %3"
4704 [(set_attr "itanium_class" "ialu")])
4706 ;; This can be created by register elimination if operand3 of shladd is an
4707 ;; eliminable register or has reg_equiv_constant set.
4709 ;; We have to use nonmemory_operand for operand 4, to ensure that the
4710 ;; validate_changes call inside eliminate_regs will always succeed. If it
4711 ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded
4712 ;; incorrectly.
4714 (define_insn_and_split "*shladd_elim"
4715 [(set (match_operand:DI 0 "gr_register_operand" "=&r")
4716 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
4717 (match_operand:DI 2 "shladd_operand" "n"))
4718 (match_operand:DI 3 "nonmemory_operand" "r"))
4719 (match_operand:DI 4 "nonmemory_operand" "rI")))]
4720 "reload_in_progress"
4721 "* gcc_unreachable ();"
4722 "reload_completed"
4723 [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
4724 (match_dup 3)))
4725 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
4726 ""
4727 [(set_attr "itanium_class" "unknown")])
4729 (define_insn "ashrdi3"
4730 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
4731 (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
4732 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
4733 ""
4734 "@
4735 shr %0 = %1, %2
4736 shr %0 = %1, %2"
4737 [(set_attr "itanium_class" "mmshf,mmshfi")])
4739 (define_insn "lshrdi3"
4740 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
4741 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
4742 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
4743 ""
4744 "@
4745 shr.u %0 = %1, %2
4746 shr.u %0 = %1, %2"
4747 [(set_attr "itanium_class" "mmshf,mmshfi")])
4749 ;; Using a predicate that accepts only constants doesn't work, because optabs
4750 ;; will load the operand into a register and call the pattern if the predicate
4751 ;; did not accept it on the first try. So we use nonmemory_operand and then
4752 ;; verify that we have an appropriate constant in the expander.
4754 (define_expand "rotrdi3"
4755 [(set (match_operand:DI 0 "gr_register_operand" "")
4756 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "")
4757 (match_operand:DI 2 "nonmemory_operand" "")))]
4758 ""
4759 {
4760 if (! shift_count_operand (operands[2], DImode))
4761 FAIL;
4762 })
4764 (define_insn "*rotrdi3_internal"
4765 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4766 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r")
4767 (match_operand:DI 2 "shift_count_operand" "M")))]
4768 ""
4769 "shrp %0 = %1, %1, %2"
4770 [(set_attr "itanium_class" "ishf")])
4772 (define_expand "rotldi3"
4773 [(set (match_operand:DI 0 "gr_register_operand" "")
4774 (rotate:DI (match_operand:DI 1 "gr_register_operand" "")
4775 (match_operand:DI 2 "nonmemory_operand" "")))]
4776 ""
4777 {
4778 if (! shift_count_operand (operands[2], DImode))
4779 FAIL;
4780 })
4782 (define_insn "*rotldi3_internal"
4783 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4784 (rotate:DI (match_operand:DI 1 "gr_register_operand" "r")
4785 (match_operand:DI 2 "shift_count_operand" "M")))]
4786 ""
4787 "shrp %0 = %1, %1, %e2"
4788 [(set_attr "itanium_class" "ishf")])
4789 \f
4790 ;; ::::::::::::::::::::
4791 ;; ::
4792 ;; :: 128-bit Integer Shifts and Rotates
4793 ;; ::
4794 ;; ::::::::::::::::::::
4796 (define_expand "ashlti3"
4797 [(set (match_operand:TI 0 "gr_register_operand" "")
4798 (ashift:TI (match_operand:TI 1 "gr_register_operand" "")
4799 (match_operand:DI 2 "nonmemory_operand" "")))]
4800 ""
4801 {
4802 if (!dshift_count_operand (operands[2], DImode))
4803 FAIL;
4804 })
4806 (define_insn_and_split "*ashlti3_internal"
4807 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
4808 (ashift:TI (match_operand:TI 1 "gr_register_operand" "r")
4809 (match_operand:DI 2 "dshift_count_operand" "n")))]
4810 ""
4811 "#"
4812 "reload_completed"
4813 [(const_int 0)]
4814 {
4815 HOST_WIDE_INT shift = INTVAL (operands[2]);
4816 rtx rl = gen_lowpart (DImode, operands[0]);
4817 rtx rh = gen_highpart (DImode, operands[0]);
4818 rtx lo = gen_lowpart (DImode, operands[1]);
4819 rtx shiftlo = GEN_INT (shift & 63);
4821 if (shift & 64)
4822 {
4823 emit_move_insn (rl, const0_rtx);
4824 if (shift & 63)
4825 emit_insn (gen_ashldi3 (rh, lo, shiftlo));
4826 else
4827 emit_move_insn (rh, lo);
4828 }
4829 else
4830 {
4831 rtx hi = gen_highpart (DImode, operands[1]);
4833 emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63)));
4834 emit_insn (gen_ashldi3 (rl, lo, shiftlo));
4835 }
4836 DONE;
4837 })
4839 (define_expand "ashrti3"
4840 [(set (match_operand:TI 0 "gr_register_operand" "")
4841 (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "")
4842 (match_operand:DI 2 "nonmemory_operand" "")))]
4843 ""
4844 {
4845 if (!dshift_count_operand (operands[2], DImode))
4846 FAIL;
4847 })
4849 (define_insn_and_split "*ashrti3_internal"
4850 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
4851 (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
4852 (match_operand:DI 2 "dshift_count_operand" "n")))]
4853 ""
4854 "#"
4855 "reload_completed"
4856 [(const_int 0)]
4857 {
4858 HOST_WIDE_INT shift = INTVAL (operands[2]);
4859 rtx rl = gen_lowpart (DImode, operands[0]);
4860 rtx rh = gen_highpart (DImode, operands[0]);
4861 rtx hi = gen_highpart (DImode, operands[1]);
4862 rtx shiftlo = GEN_INT (shift & 63);
4864 if (shift & 64)
4865 {
4866 if (shift & 63)
4867 emit_insn (gen_ashrdi3 (rl, hi, shiftlo));
4868 else
4869 emit_move_insn (rl, hi);
4870 emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63)));
4871 }
4872 else
4873 {
4874 rtx lo = gen_lowpart (DImode, operands[1]);
4876 emit_insn (gen_shrp (rl, hi, lo, shiftlo));
4877 emit_insn (gen_ashrdi3 (rh, hi, shiftlo));
4878 }
4879 DONE;
4880 })
4882 (define_expand "lshrti3"
4883 [(set (match_operand:TI 0 "gr_register_operand" "")
4884 (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "")
4885 (match_operand:DI 2 "nonmemory_operand" "")))]
4886 ""
4887 {
4888 if (!dshift_count_operand (operands[2], DImode))
4889 FAIL;
4890 })
4892 (define_insn_and_split "*lshrti3_internal"
4893 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
4894 (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
4895 (match_operand:DI 2 "dshift_count_operand" "n")))]
4896 ""
4897 "#"
4898 "reload_completed"
4899 [(const_int 0)]
4900 {
4901 HOST_WIDE_INT shift = INTVAL (operands[2]);
4902 rtx rl = gen_lowpart (DImode, operands[0]);
4903 rtx rh = gen_highpart (DImode, operands[0]);
4904 rtx hi = gen_highpart (DImode, operands[1]);
4905 rtx shiftlo = GEN_INT (shift & 63);
4907 if (shift & 64)
4908 {
4909 if (shift & 63)
4910 emit_insn (gen_lshrdi3 (rl, hi, shiftlo));
4911 else
4912 emit_move_insn (rl, hi);
4913 emit_move_insn (rh, const0_rtx);
4914 }
4915 else
4916 {
4917 rtx lo = gen_lowpart (DImode, operands[1]);
4919 emit_insn (gen_shrp (rl, hi, lo, shiftlo));
4920 emit_insn (gen_lshrdi3 (rh, hi, shiftlo));
4921 }
4922 DONE;
4923 })
4925 (define_expand "rotlti3"
4926 [(set (match_operand:TI 0 "gr_register_operand" "")
4927 (rotate:TI (match_operand:TI 1 "gr_register_operand" "")
4928 (match_operand:DI 2 "nonmemory_operand" "")))]
4929 ""
4930 {
4931 if (! dshift_count_operand (operands[2], DImode))
4932 FAIL;
4933 })
4935 (define_insn_and_split "*rotlti3_internal"
4936 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
4937 (rotate:TI (match_operand:TI 1 "gr_register_operand" "r")
4938 (match_operand:DI 2 "dshift_count_operand" "n")))]
4939 ""
4940 "#"
4941 "reload_completed"
4942 [(const_int 0)]
4943 {
4944 HOST_WIDE_INT count = INTVAL (operands[2]);
4945 rtx rl = gen_lowpart (DImode, operands[0]);
4946 rtx rh = gen_highpart (DImode, operands[0]);
4947 rtx lo = gen_lowpart (DImode, operands[1]);
4948 rtx hi = gen_highpart (DImode, operands[1]);
4949 rtx countlo = GEN_INT (-count & 63);
4951 if (count & 64)
4952 {
4953 if (count & 63)
4954 {
4955 emit_insn (gen_shrp (rl, hi, lo, countlo));
4956 emit_insn (gen_shrp (rh, lo, hi, countlo));
4957 }
4958 else
4959 {
4960 emit_move_insn (rl, hi);
4961 emit_move_insn (rh, lo);
4962 }
4963 }
4964 else
4965 {
4966 emit_insn (gen_shrp (rl, lo, hi, countlo));
4967 emit_insn (gen_shrp (rh, hi, lo, countlo));
4968 }
4969 DONE;
4970 }
4971 [(set_attr "itanium_class" "unknown")])
4973 (define_insn "shrp"
4974 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4975 (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")
4976 (match_operand:DI 2 "gr_register_operand" "r")
4977 (match_operand:DI 3 "shift_count_operand" "M")]
4978 UNSPEC_SHRP))]
4979 ""
4980 "shrp %0 = %1, %2, %3"
4981 [(set_attr "itanium_class" "ishf")])
4982 \f
4983 ;; ::::::::::::::::::::
4984 ;; ::
4985 ;; :: 32-bit Integer Logical operations
4986 ;; ::
4987 ;; ::::::::::::::::::::
4989 ;; We don't seem to need any other 32-bit logical operations, because gcc
4990 ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to
4991 ;; DImode-op;zero-extend, and then we can optimize away the zero-extend.
4992 ;; This doesn't work for unary logical operations, because we don't call
4993 ;; apply_distributive_law for them.
4995 ;; ??? Likewise, this doesn't work for andnot, which isn't handled by
4996 ;; apply_distributive_law. We get inefficient code for
4997 ;; int sub4 (int i, int j) { return i & ~j; }
4998 ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to
4999 ;; (zero_extend (and (not A) B)) in combine.
5000 ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
5001 ;; one_cmplsi2 pattern.
5003 (define_insn "one_cmplsi2"
5004 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5005 (not:SI (match_operand:SI 1 "gr_register_operand" "r")))]
5006 ""
5007 "andcm %0 = -1, %1"
5008 [(set_attr "itanium_class" "ilog")])
5009 \f
5010 ;; ::::::::::::::::::::
5011 ;; ::
5012 ;; :: 64-bit Integer Logical operations
5013 ;; ::
5014 ;; ::::::::::::::::::::
5016 (define_insn "anddi3"
5017 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
5018 (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
5019 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
5020 ""
5021 "@
5022 and %0 = %2, %1
5023 fand %0 = %2, %1"
5024 [(set_attr "itanium_class" "ilog,fmisc")])
5026 (define_insn "*andnot"
5027 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
5028 (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f"))
5029 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
5030 ""
5031 "@
5032 andcm %0 = %2, %1
5033 fandcm %0 = %2, %1"
5034 [(set_attr "itanium_class" "ilog,fmisc")])
5036 (define_insn "iordi3"
5037 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
5038 (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
5039 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
5040 ""
5041 "@
5042 or %0 = %2, %1
5043 for %0 = %2, %1"
5044 [(set_attr "itanium_class" "ilog,fmisc")])
5046 (define_insn "xordi3"
5047 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
5048 (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
5049 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
5050 ""
5051 "@
5052 xor %0 = %2, %1
5053 fxor %0 = %2, %1"
5054 [(set_attr "itanium_class" "ilog,fmisc")])
5056 (define_insn "one_cmpldi2"
5057 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5058 (not:DI (match_operand:DI 1 "gr_register_operand" "r")))]
5059 ""
5060 "andcm %0 = -1, %1"
5061 [(set_attr "itanium_class" "ilog")])
5062 \f
5063 ;; ::::::::::::::::::::
5064 ;; ::
5065 ;; :: Comparisons
5066 ;; ::
5067 ;; ::::::::::::::::::::
5069 (define_expand "cmpbi"
5070 [(set (cc0)
5071 (compare (match_operand:BI 0 "register_operand" "")
5072 (match_operand:BI 1 "const_int_operand" "")))]
5073 ""
5074 {
5075 ia64_compare_op0 = operands[0];
5076 ia64_compare_op1 = operands[1];
5077 DONE;
5078 })
5080 (define_expand "cmpsi"
5081 [(set (cc0)
5082 (compare (match_operand:SI 0 "gr_register_operand" "")
5083 (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
5084 ""
5085 {
5086 ia64_compare_op0 = operands[0];
5087 ia64_compare_op1 = operands[1];
5088 DONE;
5089 })
5091 (define_expand "cmpdi"
5092 [(set (cc0)
5093 (compare (match_operand:DI 0 "gr_register_operand" "")
5094 (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
5095 ""
5096 {
5097 ia64_compare_op0 = operands[0];
5098 ia64_compare_op1 = operands[1];
5099 DONE;
5100 })
5102 (define_expand "cmpsf"
5103 [(set (cc0)
5104 (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "")
5105 (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))]
5106 ""
5107 {
5108 ia64_compare_op0 = operands[0];
5109 ia64_compare_op1 = operands[1];
5110 DONE;
5111 })
5113 (define_expand "cmpdf"
5114 [(set (cc0)
5115 (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "")
5116 (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))]
5117 ""
5118 {
5119 ia64_compare_op0 = operands[0];
5120 ia64_compare_op1 = operands[1];
5121 DONE;
5122 })
5124 (define_expand "cmpxf"
5125 [(set (cc0)
5126 (compare (match_operand:XF 0 "xfreg_or_fp01_operand" "")
5127 (match_operand:XF 1 "xfreg_or_fp01_operand" "")))]
5128 ""
5129 {
5130 ia64_compare_op0 = operands[0];
5131 ia64_compare_op1 = operands[1];
5132 DONE;
5133 })
5135 (define_expand "cmptf"
5136 [(set (cc0)
5137 (compare (match_operand:TF 0 "gr_register_operand" "")
5138 (match_operand:TF 1 "gr_register_operand" "")))]
5139 "TARGET_HPUX"
5140 {
5141 ia64_compare_op0 = operands[0];
5142 ia64_compare_op1 = operands[1];
5143 DONE;
5144 })
5146 (define_insn "*cmpsi_normal"
5147 [(set (match_operand:BI 0 "register_operand" "=c")
5148 (match_operator:BI 1 "normal_comparison_operator"
5149 [(match_operand:SI 2 "gr_register_operand" "r")
5150 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))]
5151 ""
5152 "cmp4.%C1 %0, %I0 = %3, %2"
5153 [(set_attr "itanium_class" "icmp")])
5155 ;; We use %r3 because it is possible for us to match a 0, and two of the
5156 ;; unsigned comparisons don't accept immediate operands of zero.
5158 (define_insn "*cmpsi_adjusted"
5159 [(set (match_operand:BI 0 "register_operand" "=c")
5160 (match_operator:BI 1 "adjusted_comparison_operator"
5161 [(match_operand:SI 2 "gr_register_operand" "r")
5162 (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
5163 ""
5164 "cmp4.%C1 %0, %I0 = %r3, %2"
5165 [(set_attr "itanium_class" "icmp")])
5167 (define_insn "*cmpdi_normal"
5168 [(set (match_operand:BI 0 "register_operand" "=c")
5169 (match_operator:BI 1 "normal_comparison_operator"
5170 [(match_operand:DI 2 "gr_reg_or_0_operand" "rO")
5171 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))]
5172 ""
5173 "cmp.%C1 %0, %I0 = %3, %r2"
5174 [(set_attr "itanium_class" "icmp")])
5176 ;; We use %r3 because it is possible for us to match a 0, and two of the
5177 ;; unsigned comparisons don't accept immediate operands of zero.
5179 (define_insn "*cmpdi_adjusted"
5180 [(set (match_operand:BI 0 "register_operand" "=c")
5181 (match_operator:BI 1 "adjusted_comparison_operator"
5182 [(match_operand:DI 2 "gr_register_operand" "r")
5183 (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
5184 ""
5185 "cmp.%C1 %0, %I0 = %r3, %2"
5186 [(set_attr "itanium_class" "icmp")])
5188 (define_insn "*cmpsf_internal"
5189 [(set (match_operand:BI 0 "register_operand" "=c")
5190 (match_operator:BI 1 "comparison_operator"
5191 [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
5192 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))]
5193 ""
5194 "fcmp.%D1 %0, %I0 = %F2, %F3"
5195 [(set_attr "itanium_class" "fcmp")])
5197 (define_insn "*cmpdf_internal"
5198 [(set (match_operand:BI 0 "register_operand" "=c")
5199 (match_operator:BI 1 "comparison_operator"
5200 [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
5201 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))]
5202 ""
5203 "fcmp.%D1 %0, %I0 = %F2, %F3"
5204 [(set_attr "itanium_class" "fcmp")])
5206 (define_insn "*cmpxf_internal"
5207 [(set (match_operand:BI 0 "register_operand" "=c")
5208 (match_operator:BI 1 "comparison_operator"
5209 [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
5210 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))]
5211 ""
5212 "fcmp.%D1 %0, %I0 = %F2, %F3"
5213 [(set_attr "itanium_class" "fcmp")])
5215 ;; ??? Can this pattern be generated?
5217 (define_insn "*bit_zero"
5218 [(set (match_operand:BI 0 "register_operand" "=c")
5219 (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
5220 (const_int 1)
5221 (match_operand:DI 2 "shift_count_operand" "M"))
5222 (const_int 0)))]
5223 ""
5224 "tbit.z %0, %I0 = %1, %2"
5225 [(set_attr "itanium_class" "tbit")])
5227 (define_insn "*bit_one"
5228 [(set (match_operand:BI 0 "register_operand" "=c")
5229 (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
5230 (const_int 1)
5231 (match_operand:DI 2 "shift_count_operand" "M"))
5232 (const_int 0)))]
5233 ""
5234 "tbit.nz %0, %I0 = %1, %2"
5235 [(set_attr "itanium_class" "tbit")])
5236 \f
5237 ;; ::::::::::::::::::::
5238 ;; ::
5239 ;; :: Branches
5240 ;; ::
5241 ;; ::::::::::::::::::::
5243 (define_expand "beq"
5244 [(set (pc)
5245 (if_then_else (match_dup 1)
5246 (label_ref (match_operand 0 "" ""))
5247 (pc)))]
5248 ""
5249 "operands[1] = ia64_expand_compare (EQ, VOIDmode);")
5251 (define_expand "bne"
5252 [(set (pc)
5253 (if_then_else (match_dup 1)
5254 (label_ref (match_operand 0 "" ""))
5255 (pc)))]
5256 ""
5257 "operands[1] = ia64_expand_compare (NE, VOIDmode);")
5259 (define_expand "blt"
5260 [(set (pc)
5261 (if_then_else (match_dup 1)
5262 (label_ref (match_operand 0 "" ""))
5263 (pc)))]
5264 ""
5265 "operands[1] = ia64_expand_compare (LT, VOIDmode);")
5267 (define_expand "ble"
5268 [(set (pc)
5269 (if_then_else (match_dup 1)
5270 (label_ref (match_operand 0 "" ""))
5271 (pc)))]
5272 ""
5273 "operands[1] = ia64_expand_compare (LE, VOIDmode);")
5275 (define_expand "bgt"
5276 [(set (pc)
5277 (if_then_else (match_dup 1)
5278 (label_ref (match_operand 0 "" ""))
5279 (pc)))]
5280 ""
5281 "operands[1] = ia64_expand_compare (GT, VOIDmode);")
5283 (define_expand "bge"
5284 [(set (pc)
5285 (if_then_else (match_dup 1)
5286 (label_ref (match_operand 0 "" ""))
5287 (pc)))]
5288 ""
5289 "operands[1] = ia64_expand_compare (GE, VOIDmode);")
5291 (define_expand "bltu"
5292 [(set (pc)
5293 (if_then_else (match_dup 1)
5294 (label_ref (match_operand 0 "" ""))
5295 (pc)))]
5296 ""
5297 "operands[1] = ia64_expand_compare (LTU, VOIDmode);")
5299 (define_expand "bleu"
5300 [(set (pc)
5301 (if_then_else (match_dup 1)
5302 (label_ref (match_operand 0 "" ""))
5303 (pc)))]
5304 ""
5305 "operands[1] = ia64_expand_compare (LEU, VOIDmode);")
5307 (define_expand "bgtu"
5308 [(set (pc)
5309 (if_then_else (match_dup 1)
5310 (label_ref (match_operand 0 "" ""))
5311 (pc)))]
5312 ""
5313 "operands[1] = ia64_expand_compare (GTU, VOIDmode);")
5315 (define_expand "bgeu"
5316 [(set (pc)
5317 (if_then_else (match_dup 1)
5318 (label_ref (match_operand 0 "" ""))
5319 (pc)))]
5320 ""
5321 "operands[1] = ia64_expand_compare (GEU, VOIDmode);")
5323 (define_expand "bunordered"
5324 [(set (pc)
5325 (if_then_else (match_dup 1)
5326 (label_ref (match_operand 0 "" ""))
5327 (pc)))]
5328 ""
5329 "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);")
5331 (define_expand "bordered"
5332 [(set (pc)
5333 (if_then_else (match_dup 1)
5334 (label_ref (match_operand 0 "" ""))
5335 (pc)))]
5336 ""
5337 "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);")
5339 (define_insn "*br_true"
5340 [(set (pc)
5341 (if_then_else (match_operator 0 "predicate_operator"
5342 [(match_operand:BI 1 "register_operand" "c")
5343 (const_int 0)])
5344 (label_ref (match_operand 2 "" ""))
5345 (pc)))]
5346 ""
5347 "(%J0) br.cond%+ %l2"
5348 [(set_attr "itanium_class" "br")
5349 (set_attr "predicable" "no")])
5351 (define_insn "*br_false"
5352 [(set (pc)
5353 (if_then_else (match_operator 0 "predicate_operator"
5354 [(match_operand:BI 1 "register_operand" "c")
5355 (const_int 0)])
5356 (pc)
5357 (label_ref (match_operand 2 "" ""))))]
5358 ""
5359 "(%j0) br.cond%+ %l2"
5360 [(set_attr "itanium_class" "br")
5361 (set_attr "predicable" "no")])
5362 \f
5363 ;; ::::::::::::::::::::
5364 ;; ::
5365 ;; :: Counted loop operations
5366 ;; ::
5367 ;; ::::::::::::::::::::
5369 (define_expand "doloop_end"
5370 [(use (match_operand 0 "" "")) ; loop pseudo
5371 (use (match_operand 1 "" "")) ; iterations; zero if unknown
5372 (use (match_operand 2 "" "")) ; max iterations
5373 (use (match_operand 3 "" "")) ; loop level
5374 (use (match_operand 4 "" ""))] ; label
5375 ""
5376 {
5377 /* Only use cloop on innermost loops. */
5378 if (INTVAL (operands[3]) > 1)
5379 FAIL;
5380 emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM),
5381 operands[4]));
5382 DONE;
5383 })
5385 (define_insn "doloop_end_internal"
5386 [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "")
5387 (const_int 0))
5388 (label_ref (match_operand 1 "" ""))
5389 (pc)))
5390 (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0))
5391 (plus:DI (match_dup 0) (const_int -1))
5392 (match_dup 0)))]
5393 ""
5394 "br.cloop.sptk.few %l1"
5395 [(set_attr "itanium_class" "br")
5396 (set_attr "predicable" "no")])
5397 \f
5398 ;; ::::::::::::::::::::
5399 ;; ::
5400 ;; :: Set flag operations
5401 ;; ::
5402 ;; ::::::::::::::::::::
5404 (define_expand "seq"
5405 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5406 ""
5407 "operands[1] = ia64_expand_compare (EQ, DImode);")
5409 (define_expand "sne"
5410 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5411 ""
5412 "operands[1] = ia64_expand_compare (NE, DImode);")
5414 (define_expand "slt"
5415 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5416 ""
5417 "operands[1] = ia64_expand_compare (LT, DImode);")
5419 (define_expand "sle"
5420 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5421 ""
5422 "operands[1] = ia64_expand_compare (LE, DImode);")
5424 (define_expand "sgt"
5425 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5426 ""
5427 "operands[1] = ia64_expand_compare (GT, DImode);")
5429 (define_expand "sge"
5430 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5431 ""
5432 "operands[1] = ia64_expand_compare (GE, DImode);")
5434 (define_expand "sltu"
5435 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5436 ""
5437 "operands[1] = ia64_expand_compare (LTU, DImode);")
5439 (define_expand "sleu"
5440 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5441 ""
5442 "operands[1] = ia64_expand_compare (LEU, DImode);")
5444 (define_expand "sgtu"
5445 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5446 ""
5447 "operands[1] = ia64_expand_compare (GTU, DImode);")
5449 (define_expand "sgeu"
5450 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5451 ""
5452 "operands[1] = ia64_expand_compare (GEU, DImode);")
5454 (define_expand "sunordered"
5455 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5456 ""
5457 "operands[1] = ia64_expand_compare (UNORDERED, DImode);")
5459 (define_expand "sordered"
5460 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5461 ""
5462 "operands[1] = ia64_expand_compare (ORDERED, DImode);")
5464 ;; Don't allow memory as destination here, because cmov/cmov/st is more
5465 ;; efficient than mov/mov/cst/cst.
5467 (define_insn_and_split "*sne_internal"
5468 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5469 (ne:DI (match_operand:BI 1 "register_operand" "c")
5470 (const_int 0)))]
5471 ""
5472 "#"
5473 "reload_completed"
5474 [(cond_exec (ne (match_dup 1) (const_int 0))
5475 (set (match_dup 0) (const_int 1)))
5476 (cond_exec (eq (match_dup 1) (const_int 0))
5477 (set (match_dup 0) (const_int 0)))]
5478 ""
5479 [(set_attr "itanium_class" "unknown")])
5481 (define_insn_and_split "*seq_internal"
5482 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5483 (eq:DI (match_operand:BI 1 "register_operand" "c")
5484 (const_int 0)))]
5485 ""
5486 "#"
5487 "reload_completed"
5488 [(cond_exec (ne (match_dup 1) (const_int 0))
5489 (set (match_dup 0) (const_int 0)))
5490 (cond_exec (eq (match_dup 1) (const_int 0))
5491 (set (match_dup 0) (const_int 1)))]
5492 ""
5493 [(set_attr "itanium_class" "unknown")])
5494 \f
5495 ;; ::::::::::::::::::::
5496 ;; ::
5497 ;; :: Conditional move instructions.
5498 ;; ::
5499 ;; ::::::::::::::::::::
5501 ;; ??? Add movXXcc patterns?
5503 ;;
5504 ;; DImode if_then_else patterns.
5505 ;;
5507 (define_insn "*cmovdi_internal"
5508 [(set (match_operand:DI 0 "destination_operand"
5509 "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e")
5510 (if_then_else:DI
5511 (match_operator 4 "predicate_operator"
5512 [(match_operand:BI 1 "register_operand"
5513 "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
5514 (const_int 0)])
5515 (match_operand:DI 2 "move_operand"
5516 "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK")
5517 (match_operand:DI 3 "move_operand"
5518 "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))]
5519 "ia64_move_ok (operands[0], operands[2])
5520 && ia64_move_ok (operands[0], operands[3])"
5521 { gcc_unreachable (); }
5522 [(set_attr "predicable" "no")])
5524 (define_split
5525 [(set (match_operand 0 "destination_operand" "")
5526 (if_then_else
5527 (match_operator 4 "predicate_operator"
5528 [(match_operand:BI 1 "register_operand" "")
5529 (const_int 0)])
5530 (match_operand 2 "move_operand" "")
5531 (match_operand 3 "move_operand" "")))]
5532 "reload_completed"
5533 [(const_int 0)]
5534 {
5535 bool emitted_something = false;
5536 rtx dest = operands[0];
5537 rtx srct = operands[2];
5538 rtx srcf = operands[3];
5539 rtx cond = operands[4];
5541 if (! rtx_equal_p (dest, srct))
5542 {
5543 ia64_emit_cond_move (dest, srct, cond);
5544 emitted_something = true;
5545 }
5546 if (! rtx_equal_p (dest, srcf))
5547 {
5548 cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE,
5549 VOIDmode, operands[1], const0_rtx);
5550 ia64_emit_cond_move (dest, srcf, cond);
5551 emitted_something = true;
5552 }
5553 if (! emitted_something)
5554 emit_note (NOTE_INSN_DELETED);
5555 DONE;
5556 })
5558 ;; Absolute value pattern.
5560 (define_insn "*absdi2_internal"
5561 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
5562 (if_then_else:DI
5563 (match_operator 4 "predicate_operator"
5564 [(match_operand:BI 1 "register_operand" "c,c")
5565 (const_int 0)])
5566 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI"))
5567 (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))]
5568 ""
5569 "#"
5570 [(set_attr "itanium_class" "ialu,unknown")
5571 (set_attr "predicable" "no")])
5573 (define_split
5574 [(set (match_operand:DI 0 "register_operand" "")
5575 (if_then_else:DI
5576 (match_operator 4 "predicate_operator"
5577 [(match_operand:BI 1 "register_operand" "c,c")
5578 (const_int 0)])
5579 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
5580 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
5581 "reload_completed && rtx_equal_p (operands[0], operands[3])"
5582 [(cond_exec
5583 (match_dup 4)
5584 (set (match_dup 0)
5585 (neg:DI (match_dup 2))))]
5586 "")
5588 (define_split
5589 [(set (match_operand:DI 0 "register_operand" "")
5590 (if_then_else:DI
5591 (match_operator 4 "predicate_operator"
5592 [(match_operand:BI 1 "register_operand" "c,c")
5593 (const_int 0)])
5594 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
5595 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
5596 "reload_completed"
5597 [(cond_exec
5598 (match_dup 4)
5599 (set (match_dup 0) (neg:DI (match_dup 2))))
5600 (cond_exec
5601 (match_dup 5)
5602 (set (match_dup 0) (match_dup 3)))]
5603 {
5604 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
5605 VOIDmode, operands[1], const0_rtx);
5606 })
5608 ;;
5609 ;; SImode if_then_else patterns.
5610 ;;
5612 (define_insn "*cmovsi_internal"
5613 [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f")
5614 (if_then_else:SI
5615 (match_operator 4 "predicate_operator"
5616 [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c")
5617 (const_int 0)])
5618 (match_operand:SI 2 "move_operand"
5619 "0,0,0,rim*f,rO,rO,rim*f,rO,rO")
5620 (match_operand:SI 3 "move_operand"
5621 "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
5622 "ia64_move_ok (operands[0], operands[2])
5623 && ia64_move_ok (operands[0], operands[3])"
5624 { gcc_unreachable (); }
5625 [(set_attr "predicable" "no")])
5627 (define_insn "*abssi2_internal"
5628 [(set (match_operand:SI 0 "gr_register_operand" "=r,r")
5629 (if_then_else:SI
5630 (match_operator 4 "predicate_operator"
5631 [(match_operand:BI 1 "register_operand" "c,c")
5632 (const_int 0)])
5633 (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI"))
5634 (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))]
5635 ""
5636 "#"
5637 [(set_attr "itanium_class" "ialu,unknown")
5638 (set_attr "predicable" "no")])
5640 (define_split
5641 [(set (match_operand:SI 0 "register_operand" "")
5642 (if_then_else:SI
5643 (match_operator 4 "predicate_operator"
5644 [(match_operand:BI 1 "register_operand" "c,c")
5645 (const_int 0)])
5646 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
5647 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
5648 "reload_completed && rtx_equal_p (operands[0], operands[3])"
5649 [(cond_exec
5650 (match_dup 4)
5651 (set (match_dup 0)
5652 (neg:SI (match_dup 2))))]
5653 "")
5655 (define_split
5656 [(set (match_operand:SI 0 "register_operand" "")
5657 (if_then_else:SI
5658 (match_operator 4 "predicate_operator"
5659 [(match_operand:BI 1 "register_operand" "c,c")
5660 (const_int 0)])
5661 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
5662 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
5663 "reload_completed"
5664 [(cond_exec
5665 (match_dup 4)
5666 (set (match_dup 0) (neg:SI (match_dup 2))))
5667 (cond_exec
5668 (match_dup 5)
5669 (set (match_dup 0) (match_dup 3)))]
5670 {
5671 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
5672 VOIDmode, operands[1], const0_rtx);
5673 })
5675 (define_insn_and_split "*cond_opsi2_internal"
5676 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5677 (match_operator:SI 5 "condop_operator"
5678 [(if_then_else:SI
5679 (match_operator 6 "predicate_operator"
5680 [(match_operand:BI 1 "register_operand" "c")
5681 (const_int 0)])
5682 (match_operand:SI 2 "gr_register_operand" "r")
5683 (match_operand:SI 3 "gr_register_operand" "r"))
5684 (match_operand:SI 4 "gr_register_operand" "r")]))]
5685 ""
5686 "#"
5687 "reload_completed"
5688 [(cond_exec
5689 (match_dup 6)
5690 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)])))
5691 (cond_exec
5692 (match_dup 7)
5693 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))]
5694 {
5695 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
5696 VOIDmode, operands[1], const0_rtx);
5697 }
5698 [(set_attr "itanium_class" "ialu")
5699 (set_attr "predicable" "no")])
5702 (define_insn_and_split "*cond_opsi2_internal_b"
5703 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5704 (match_operator:SI 5 "condop_operator"
5705 [(match_operand:SI 4 "gr_register_operand" "r")
5706 (if_then_else:SI
5707 (match_operator 6 "predicate_operator"
5708 [(match_operand:BI 1 "register_operand" "c")
5709 (const_int 0)])
5710 (match_operand:SI 2 "gr_register_operand" "r")
5711 (match_operand:SI 3 "gr_register_operand" "r"))]))]
5712 ""
5713 "#"
5714 "reload_completed"
5715 [(cond_exec
5716 (match_dup 6)
5717 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)])))
5718 (cond_exec
5719 (match_dup 7)
5720 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))]
5721 {
5722 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
5723 VOIDmode, operands[1], const0_rtx);
5724 }
5725 [(set_attr "itanium_class" "ialu")
5726 (set_attr "predicable" "no")])
5728 \f
5729 ;; ::::::::::::::::::::
5730 ;; ::
5731 ;; :: Call and branch instructions
5732 ;; ::
5733 ;; ::::::::::::::::::::
5735 ;; Subroutine call instruction returning no value. Operand 0 is the function
5736 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
5737 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
5738 ;; registers used as operands.
5740 ;; On most machines, operand 2 is not actually stored into the RTL pattern. It
5741 ;; is supplied for the sake of some RISC machines which need to put this
5742 ;; information into the assembler code; they can put it in the RTL instead of
5743 ;; operand 1.
5745 (define_expand "call"
5746 [(use (match_operand:DI 0 "" ""))
5747 (use (match_operand 1 "" ""))
5748 (use (match_operand 2 "" ""))
5749 (use (match_operand 3 "" ""))]
5750 ""
5751 {
5752 ia64_expand_call (NULL_RTX, operands[0], operands[2], false);
5753 DONE;
5754 })
5756 (define_expand "sibcall"
5757 [(use (match_operand:DI 0 "" ""))
5758 (use (match_operand 1 "" ""))
5759 (use (match_operand 2 "" ""))
5760 (use (match_operand 3 "" ""))]
5761 ""
5762 {
5763 ia64_expand_call (NULL_RTX, operands[0], operands[2], true);
5764 DONE;
5765 })
5767 ;; Subroutine call instruction returning a value. Operand 0 is the hard
5768 ;; register in which the value is returned. There are three more operands,
5769 ;; the same as the three operands of the `call' instruction (but with numbers
5770 ;; increased by one).
5771 ;;
5772 ;; Subroutines that return `BLKmode' objects use the `call' insn.
5774 (define_expand "call_value"
5775 [(use (match_operand 0 "" ""))
5776 (use (match_operand:DI 1 "" ""))
5777 (use (match_operand 2 "" ""))
5778 (use (match_operand 3 "" ""))
5779 (use (match_operand 4 "" ""))]
5780 ""
5781 {
5782 ia64_expand_call (operands[0], operands[1], operands[3], false);
5783 DONE;
5784 })
5786 (define_expand "sibcall_value"
5787 [(use (match_operand 0 "" ""))
5788 (use (match_operand:DI 1 "" ""))
5789 (use (match_operand 2 "" ""))
5790 (use (match_operand 3 "" ""))
5791 (use (match_operand 4 "" ""))]
5792 ""
5793 {
5794 ia64_expand_call (operands[0], operands[1], operands[3], true);
5795 DONE;
5796 })
5798 ;; Call subroutine returning any type.
5800 (define_expand "untyped_call"
5801 [(parallel [(call (match_operand 0 "" "")
5802 (const_int 0))
5803 (match_operand 1 "" "")
5804 (match_operand 2 "" "")])]
5805 ""
5806 {
5807 int i;
5809 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
5811 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5812 {
5813 rtx set = XVECEXP (operands[2], 0, i);
5814 emit_move_insn (SET_DEST (set), SET_SRC (set));
5815 }
5817 /* The optimizer does not know that the call sets the function value
5818 registers we stored in the result block. We avoid problems by
5819 claiming that all hard registers are used and clobbered at this
5820 point. */
5821 emit_insn (gen_blockage ());
5823 DONE;
5824 })
5826 (define_insn "call_nogp"
5827 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i"))
5828 (const_int 0))
5829 (clobber (match_operand:DI 1 "register_operand" "=b,b"))]
5830 ""
5831 "br.call%+.many %1 = %0"
5832 [(set_attr "itanium_class" "br,scall")])
5834 (define_insn "call_value_nogp"
5835 [(set (match_operand 0 "" "=X,X")
5836 (call (mem:DI (match_operand:DI 1 "call_operand" "?b,i"))
5837 (const_int 0)))
5838 (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
5839 ""
5840 "br.call%+.many %2 = %1"
5841 [(set_attr "itanium_class" "br,scall")])
5843 (define_insn "sibcall_nogp"
5844 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i"))
5845 (const_int 0))]
5846 ""
5847 "br%+.many %0"
5848 [(set_attr "itanium_class" "br,scall")])
5850 (define_insn "call_gp"
5851 [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i"))
5852 (const_int 1))
5853 (clobber (match_operand:DI 1 "register_operand" "=b,b"))
5854 (clobber (match_scratch:DI 2 "=&r,X"))
5855 (clobber (match_scratch:DI 3 "=b,X"))]
5856 ""
5857 "#"
5858 [(set_attr "itanium_class" "br,scall")])
5860 ;; Irritatingly, we don't have access to INSN within the split body.
5861 ;; See commentary in ia64_split_call as to why these aren't peep2.
5862 (define_split
5863 [(call (mem (match_operand 0 "call_operand" ""))
5864 (const_int 1))
5865 (clobber (match_operand:DI 1 "register_operand" ""))
5866 (clobber (match_scratch:DI 2 ""))
5867 (clobber (match_scratch:DI 3 ""))]
5868 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
5869 [(const_int 0)]
5870 {
5871 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
5872 operands[3], true, false);
5873 DONE;
5874 })
5876 (define_split
5877 [(call (mem (match_operand 0 "call_operand" ""))
5878 (const_int 1))
5879 (clobber (match_operand:DI 1 "register_operand" ""))
5880 (clobber (match_scratch:DI 2 ""))
5881 (clobber (match_scratch:DI 3 ""))]
5882 "reload_completed"
5883 [(const_int 0)]
5884 {
5885 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
5886 operands[3], false, false);
5887 DONE;
5888 })
5890 (define_insn "call_value_gp"
5891 [(set (match_operand 0 "" "=X,X")
5892 (call (mem:DI (match_operand:DI 1 "call_operand" "?r,i"))
5893 (const_int 1)))
5894 (clobber (match_operand:DI 2 "register_operand" "=b,b"))
5895 (clobber (match_scratch:DI 3 "=&r,X"))
5896 (clobber (match_scratch:DI 4 "=b,X"))]
5897 ""
5898 "#"
5899 [(set_attr "itanium_class" "br,scall")])
5901 (define_split
5902 [(set (match_operand 0 "" "")
5903 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
5904 (const_int 1)))
5905 (clobber (match_operand:DI 2 "register_operand" ""))
5906 (clobber (match_scratch:DI 3 ""))
5907 (clobber (match_scratch:DI 4 ""))]
5908 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
5909 [(const_int 0)]
5910 {
5911 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
5912 operands[4], true, false);
5913 DONE;
5914 })
5916 (define_split
5917 [(set (match_operand 0 "" "")
5918 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
5919 (const_int 1)))
5920 (clobber (match_operand:DI 2 "register_operand" ""))
5921 (clobber (match_scratch:DI 3 ""))
5922 (clobber (match_scratch:DI 4 ""))]
5923 "reload_completed"
5924 [(const_int 0)]
5925 {
5926 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
5927 operands[4], false, false);
5928 DONE;
5929 })
5931 (define_insn_and_split "sibcall_gp"
5932 [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i"))
5933 (const_int 1))
5934 (clobber (match_scratch:DI 1 "=&r,X"))
5935 (clobber (match_scratch:DI 2 "=b,X"))]
5936 ""
5937 "#"
5938 "reload_completed"
5939 [(const_int 0)]
5940 {
5941 ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1],
5942 operands[2], true, true);
5943 DONE;
5944 }
5945 [(set_attr "itanium_class" "br")])
5947 (define_insn "return_internal"
5948 [(return)
5949 (use (match_operand:DI 0 "register_operand" "b"))]
5950 ""
5951 "br.ret.sptk.many %0"
5952 [(set_attr "itanium_class" "br")])
5954 (define_insn "return"
5955 [(return)]
5956 "ia64_direct_return ()"
5957 "br.ret.sptk.many rp"
5958 [(set_attr "itanium_class" "br")])
5960 (define_insn "*return_true"
5961 [(set (pc)
5962 (if_then_else (match_operator 0 "predicate_operator"
5963 [(match_operand:BI 1 "register_operand" "c")
5964 (const_int 0)])
5965 (return)
5966 (pc)))]
5967 "ia64_direct_return ()"
5968 "(%J0) br.ret%+.many rp"
5969 [(set_attr "itanium_class" "br")
5970 (set_attr "predicable" "no")])
5972 (define_insn "*return_false"
5973 [(set (pc)
5974 (if_then_else (match_operator 0 "predicate_operator"
5975 [(match_operand:BI 1 "register_operand" "c")
5976 (const_int 0)])
5977 (pc)
5978 (return)))]
5979 "ia64_direct_return ()"
5980 "(%j0) br.ret%+.many rp"
5981 [(set_attr "itanium_class" "br")
5982 (set_attr "predicable" "no")])
5984 (define_insn "jump"
5985 [(set (pc) (label_ref (match_operand 0 "" "")))]
5986 ""
5987 "br %l0"
5988 [(set_attr "itanium_class" "br")])
5990 (define_insn "indirect_jump"
5991 [(set (pc) (match_operand:DI 0 "register_operand" "b"))]
5992 ""
5993 "br %0"
5994 [(set_attr "itanium_class" "br")])
5996 (define_expand "tablejump"
5997 [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" ""))
5998 (use (label_ref (match_operand 1 "" "")))])]
5999 ""
6000 {
6001 rtx op0 = operands[0];
6002 rtx addr;
6004 /* ??? Bother -- do_tablejump is "helpful" and pulls the table
6005 element into a register without bothering to see whether that
6006 is necessary given the operand predicate. Check for MEM just
6007 in case someone fixes this. */
6008 if (GET_CODE (op0) == MEM)
6009 addr = XEXP (op0, 0);
6010 else
6011 {
6012 /* Otherwise, cheat and guess that the previous insn in the
6013 stream was the memory load. Grab the address from that.
6014 Note we have to momentarily pop out of the sequence started
6015 by the insn-emit wrapper in order to grab the last insn. */
6016 rtx last, set;
6018 end_sequence ();
6019 last = get_last_insn ();
6020 start_sequence ();
6021 set = single_set (last);
6023 gcc_assert (rtx_equal_p (SET_DEST (set), op0)
6024 && GET_CODE (SET_SRC (set)) == MEM);
6025 addr = XEXP (SET_SRC (set), 0);
6026 gcc_assert (!rtx_equal_p (addr, op0));
6027 }
6029 /* Jump table elements are stored pc-relative. That is, a displacement
6030 from the entry to the label. Thus to convert to an absolute address
6031 we add the address of the memory from which the value is loaded. */
6032 operands[0] = expand_simple_binop (DImode, PLUS, op0, addr,
6033 NULL_RTX, 1, OPTAB_DIRECT);
6034 })
6036 (define_insn "*tablejump_internal"
6037 [(set (pc) (match_operand:DI 0 "register_operand" "b"))
6038 (use (label_ref (match_operand 1 "" "")))]
6039 ""
6040 "br %0"
6041 [(set_attr "itanium_class" "br")])
6043 \f
6044 ;; ::::::::::::::::::::
6045 ;; ::
6046 ;; :: Prologue and Epilogue instructions
6047 ;; ::
6048 ;; ::::::::::::::::::::
6050 (define_expand "prologue"
6051 [(const_int 1)]
6052 ""
6053 {
6054 ia64_expand_prologue ();
6055 DONE;
6056 })
6058 (define_expand "epilogue"
6059 [(return)]
6060 ""
6061 {
6062 ia64_expand_epilogue (0);
6063 DONE;
6064 })
6066 (define_expand "sibcall_epilogue"
6067 [(return)]
6068 ""
6069 {
6070 ia64_expand_epilogue (1);
6071 DONE;
6072 })
6074 ;; This prevents the scheduler from moving the SP decrement past FP-relative
6075 ;; stack accesses. This is the same as adddi3 plus the extra set.
6077 (define_insn "prologue_allocate_stack"
6078 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6079 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a")
6080 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))
6081 (set (match_operand:DI 3 "register_operand" "+r,r,r")
6082 (match_dup 3))]
6083 ""
6084 "@
6085 add %0 = %1, %2
6086 adds %0 = %2, %1
6087 addl %0 = %2, %1"
6088 [(set_attr "itanium_class" "ialu")])
6090 ;; This prevents the scheduler from moving the SP restore past FP-relative
6091 ;; stack accesses. This is similar to movdi plus the extra set.
6093 (define_insn "epilogue_deallocate_stack"
6094 [(set (match_operand:DI 0 "register_operand" "=r")
6095 (match_operand:DI 1 "register_operand" "+r"))
6096 (set (match_dup 1) (match_dup 1))]
6097 ""
6098 "mov %0 = %1"
6099 [(set_attr "itanium_class" "ialu")])
6101 ;; As USE insns aren't meaningful after reload, this is used instead
6102 ;; to prevent deleting instructions setting registers for EH handling
6103 (define_insn "prologue_use"
6104 [(unspec:DI [(match_operand:DI 0 "register_operand" "")]
6105 UNSPEC_PROLOGUE_USE)]
6106 ""
6107 ""
6108 [(set_attr "itanium_class" "ignore")
6109 (set_attr "predicable" "no")
6110 (set_attr "empty" "yes")])
6112 ;; Allocate a new register frame.
6114 (define_insn "alloc"
6115 [(set (match_operand:DI 0 "register_operand" "=r")
6116 (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC))
6117 (use (match_operand:DI 1 "const_int_operand" "i"))
6118 (use (match_operand:DI 2 "const_int_operand" "i"))
6119 (use (match_operand:DI 3 "const_int_operand" "i"))
6120 (use (match_operand:DI 4 "const_int_operand" "i"))]
6121 ""
6122 "alloc %0 = ar.pfs, %1, %2, %3, %4"
6123 [(set_attr "itanium_class" "syst_m0")
6124 (set_attr "predicable" "no")
6125 (set_attr "first_insn" "yes")])
6127 ;; Modifies ar.unat
6128 (define_expand "gr_spill"
6129 [(parallel [(set (match_operand:DI 0 "memory_operand" "=m")
6130 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6131 (match_operand:DI 2 "const_int_operand" "")]
6132 UNSPEC_GR_SPILL))
6133 (clobber (match_dup 3))])]
6134 ""
6135 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
6137 (define_insn "gr_spill_internal"
6138 [(set (match_operand:DI 0 "destination_operand" "=m")
6139 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6140 (match_operand:DI 2 "const_int_operand" "")]
6141 UNSPEC_GR_SPILL))
6142 (clobber (match_operand:DI 3 "register_operand" ""))]
6143 ""
6144 {
6145 /* Note that we use a C output pattern here to avoid the predicate
6146 being automatically added before the .mem.offset directive. */
6147 return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0";
6148 }
6149 [(set_attr "itanium_class" "st")])
6151 ;; Reads ar.unat
6152 (define_expand "gr_restore"
6153 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
6154 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6155 (match_operand:DI 2 "const_int_operand" "")]
6156 UNSPEC_GR_RESTORE))
6157 (use (match_dup 3))])]
6158 ""
6159 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
6161 (define_insn "gr_restore_internal"
6162 [(set (match_operand:DI 0 "register_operand" "=r")
6163 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6164 (match_operand:DI 2 "const_int_operand" "")]
6165 UNSPEC_GR_RESTORE))
6166 (use (match_operand:DI 3 "register_operand" ""))]
6167 ""
6168 { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; }
6169 [(set_attr "itanium_class" "ld")])
6171 (define_insn "fr_spill"
6172 [(set (match_operand:XF 0 "destination_operand" "=m")
6173 (unspec:XF [(match_operand:XF 1 "register_operand" "f")]
6174 UNSPEC_FR_SPILL))]
6175 ""
6176 "stf.spill %0 = %1%P0"
6177 [(set_attr "itanium_class" "stf")])
6179 (define_insn "fr_restore"
6180 [(set (match_operand:XF 0 "register_operand" "=f")
6181 (unspec:XF [(match_operand:XF 1 "memory_operand" "m")]
6182 UNSPEC_FR_RESTORE))]
6183 ""
6184 "ldf.fill %0 = %1%P1"
6185 [(set_attr "itanium_class" "fld")])
6187 ;; ??? The explicit stop is not ideal. It would be better if
6188 ;; rtx_needs_barrier took care of this, but this is something that can be
6189 ;; fixed later. This avoids an RSE DV.
6191 (define_insn "bsp_value"
6192 [(set (match_operand:DI 0 "register_operand" "=r")
6193 (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))]
6194 ""
6195 "*
6196 {
6197 return \";;\;%,mov %0 = ar.bsp\";
6198 }"
6199 [(set_attr "itanium_class" "frar_i")])
6201 (define_insn "set_bsp"
6202 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
6203 UNSPECV_SET_BSP)]
6204 ""
6205 "flushrs
6206 mov r19=ar.rsc
6207 ;;
6208 and r19=0x1c,r19
6209 ;;
6210 mov ar.rsc=r19
6211 ;;
6212 mov ar.bspstore=%0
6213 ;;
6214 or r19=0x3,r19
6215 ;;
6216 loadrs
6217 invala
6218 ;;
6219 mov ar.rsc=r19"
6220 [(set_attr "itanium_class" "unknown")
6221 (set_attr "predicable" "no")])
6223 ;; ??? The explicit stops are not ideal. It would be better if
6224 ;; rtx_needs_barrier took care of this, but this is something that can be
6225 ;; fixed later. This avoids an RSE DV.
6227 (define_insn "flushrs"
6228 [(unspec [(const_int 0)] UNSPEC_FLUSHRS)]
6229 ""
6230 ";;\;flushrs\;;;"
6231 [(set_attr "itanium_class" "rse_m")
6232 (set_attr "predicable" "no")])
6233 \f
6234 ;; ::::::::::::::::::::
6235 ;; ::
6236 ;; :: Miscellaneous instructions
6237 ;; ::
6238 ;; ::::::::::::::::::::
6240 ;; ??? Emitting a NOP instruction isn't very useful. This should probably
6241 ;; be emitting ";;" to force a break in the instruction packing.
6243 ;; No operation, needed in case the user uses -g but not -O.
6244 (define_insn "nop"
6245 [(const_int 0)]
6246 ""
6247 "nop 0"
6248 [(set_attr "itanium_class" "nop")])
6250 (define_insn "nop_m"
6251 [(const_int 1)]
6252 ""
6253 "nop.m 0"
6254 [(set_attr "itanium_class" "nop_m")])
6256 (define_insn "nop_i"
6257 [(const_int 2)]
6258 ""
6259 "nop.i 0"
6260 [(set_attr "itanium_class" "nop_i")])
6262 (define_insn "nop_f"
6263 [(const_int 3)]
6264 ""
6265 "nop.f 0"
6266 [(set_attr "itanium_class" "nop_f")])
6268 (define_insn "nop_b"
6269 [(const_int 4)]
6270 ""
6271 "nop.b 0"
6272 [(set_attr "itanium_class" "nop_b")])
6274 (define_insn "nop_x"
6275 [(const_int 5)]
6276 ""
6277 ""
6278 [(set_attr "itanium_class" "nop_x")
6279 (set_attr "empty" "yes")])
6281 ;; The following insn will be never generated. It is used only by
6282 ;; insn scheduler to change state before advancing cycle.
6283 (define_insn "pre_cycle"
6284 [(const_int 6)]
6285 ""
6286 ""
6287 [(set_attr "itanium_class" "pre_cycle")])
6289 (define_insn "bundle_selector"
6290 [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)]
6291 ""
6292 { return get_bundle_name (INTVAL (operands[0])); }
6293 [(set_attr "itanium_class" "ignore")
6294 (set_attr "predicable" "no")])
6296 ;; Pseudo instruction that prevents the scheduler from moving code above this
6297 ;; point.
6298 (define_insn "blockage"
6299 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6300 ""
6301 ""
6302 [(set_attr "itanium_class" "ignore")
6303 (set_attr "predicable" "no")])
6305 (define_insn "insn_group_barrier"
6306 [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
6307 UNSPECV_INSN_GROUP_BARRIER)]
6308 ""
6309 ";;"
6310 [(set_attr "itanium_class" "stop_bit")
6311 (set_attr "predicable" "no")
6312 (set_attr "empty" "yes")])
6314 (define_expand "trap"
6315 [(trap_if (const_int 1) (const_int 0))]
6316 ""
6317 "")
6319 ;; ??? We don't have a match-any slot type. Setting the type to unknown
6320 ;; produces worse code that setting the slot type to A.
6322 (define_insn "*trap"
6323 [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))]
6324 ""
6325 "break %0"
6326 [(set_attr "itanium_class" "chk_s_i")])
6328 (define_expand "conditional_trap"
6329 [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))]
6330 ""
6331 {
6332 operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode);
6333 })
6335 (define_insn "*conditional_trap"
6336 [(trap_if (match_operator 0 "predicate_operator"
6337 [(match_operand:BI 1 "register_operand" "c")
6338 (const_int 0)])
6339 (match_operand 2 "const_int_operand" ""))]
6340 ""
6341 "(%J0) break %2"
6342 [(set_attr "itanium_class" "chk_s_i")
6343 (set_attr "predicable" "no")])
6345 (define_insn "break_f"
6346 [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)]
6347 ""
6348 "break.f 0"
6349 [(set_attr "itanium_class" "nop_f")])
6351 (define_insn "prefetch"
6352 [(prefetch (match_operand:DI 0 "address_operand" "p")
6353 (match_operand:DI 1 "const_int_operand" "n")
6354 (match_operand:DI 2 "const_int_operand" "n"))]
6355 ""
6356 {
6357 static const char * const alt[2][4] = {
6358 {
6359 "%,lfetch.nta [%0]",
6360 "%,lfetch.nt1 [%0]",
6361 "%,lfetch.nt2 [%0]",
6362 "%,lfetch [%0]"
6363 },
6364 {
6365 "%,lfetch.excl.nta [%0]",
6366 "%,lfetch.excl.nt1 [%0]",
6367 "%,lfetch.excl.nt2 [%0]",
6368 "%,lfetch.excl [%0]"
6369 }
6370 };
6371 int i = (INTVAL (operands[1]));
6372 int j = (INTVAL (operands[2]));
6374 gcc_assert (i == 0 || i == 1);
6375 gcc_assert (j >= 0 && j <= 3);
6376 return alt[i][j];
6377 }
6378 [(set_attr "itanium_class" "lfetch")])
6379 \f
6380 ;; Non-local goto support.
6382 (define_expand "save_stack_nonlocal"
6383 [(use (match_operand:OI 0 "memory_operand" ""))
6384 (use (match_operand:DI 1 "register_operand" ""))]
6385 ""
6386 {
6387 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
6388 \"__ia64_save_stack_nonlocal\"),
6389 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode,
6390 operands[1], Pmode);
6391 DONE;
6392 })
6394 (define_expand "nonlocal_goto"
6395 [(use (match_operand 0 "general_operand" ""))
6396 (use (match_operand 1 "general_operand" ""))
6397 (use (match_operand 2 "general_operand" ""))
6398 (use (match_operand 3 "general_operand" ""))]
6399 ""
6400 {
6401 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
6402 LCT_NORETURN, VOIDmode, 3,
6403 operands[1], Pmode,
6404 copy_to_reg (XEXP (operands[2], 0)), Pmode,
6405 operands[3], Pmode);
6406 emit_barrier ();
6407 DONE;
6408 })
6410 (define_insn_and_split "builtin_setjmp_receiver"
6411 [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)]
6412 ""
6413 "#"
6414 "reload_completed"
6415 [(const_int 0)]
6416 {
6417 ia64_reload_gp ();
6418 DONE;
6419 })
6421 (define_expand "eh_epilogue"
6422 [(use (match_operand:DI 0 "register_operand" "r"))
6423 (use (match_operand:DI 1 "register_operand" "r"))
6424 (use (match_operand:DI 2 "register_operand" "r"))]
6425 ""
6426 {
6427 rtx bsp = gen_rtx_REG (Pmode, 10);
6428 rtx sp = gen_rtx_REG (Pmode, 9);
6430 if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10)
6431 {
6432 emit_move_insn (bsp, operands[0]);
6433 operands[0] = bsp;
6434 }
6435 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9)
6436 {
6437 emit_move_insn (sp, operands[2]);
6438 operands[2] = sp;
6439 }
6440 emit_insn (gen_rtx_USE (VOIDmode, sp));
6441 emit_insn (gen_rtx_USE (VOIDmode, bsp));
6443 cfun->machine->ia64_eh_epilogue_sp = sp;
6444 cfun->machine->ia64_eh_epilogue_bsp = bsp;
6445 })
6446 \f
6447 ;; Builtin apply support.
6449 (define_expand "restore_stack_nonlocal"
6450 [(use (match_operand:DI 0 "register_operand" ""))
6451 (use (match_operand:OI 1 "memory_operand" ""))]
6452 ""
6453 {
6454 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
6455 "__ia64_restore_stack_nonlocal"),
6456 0, VOIDmode, 1,
6457 copy_to_reg (XEXP (operands[1], 0)), Pmode);
6458 DONE;
6459 })
6461 \f
6462 ;; Predication.
6464 (define_cond_exec
6465 [(match_operator 0 "predicate_operator"
6466 [(match_operand:BI 1 "register_operand" "c")
6467 (const_int 0)])]
6468 ""
6469 "(%J0)")
6471 (define_insn "pred_rel_mutex"
6472 [(set (match_operand:BI 0 "register_operand" "+c")
6473 (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
6474 ""
6475 ".pred.rel.mutex %0, %I0"
6476 [(set_attr "itanium_class" "ignore")
6477 (set_attr "predicable" "no")])
6479 (define_insn "safe_across_calls_all"
6480 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)]
6481 ""
6482 ".pred.safe_across_calls p1-p63"
6483 [(set_attr "itanium_class" "ignore")
6484 (set_attr "predicable" "no")])
6486 (define_insn "safe_across_calls_normal"
6487 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)]
6488 ""
6489 {
6490 emit_safe_across_calls ();
6491 return "";
6492 }
6493 [(set_attr "itanium_class" "ignore")
6494 (set_attr "predicable" "no")])
6496 ;; UNSPEC instruction definition to "swizzle" 32-bit pointer into 64-bit
6497 ;; pointer. This is used by the HP-UX 32 bit mode.
6499 (define_insn "ptr_extend"
6500 [(set (match_operand:DI 0 "gr_register_operand" "=r")
6501 (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")]
6502 UNSPEC_ADDP4))]
6503 ""
6504 "addp4 %0 = 0,%1"
6505 [(set_attr "itanium_class" "ialu")])
6507 ;;
6508 ;; Optimizations for ptr_extend
6510 (define_insn "ptr_extend_plus_imm"
6511 [(set (match_operand:DI 0 "gr_register_operand" "=r")
6512 (unspec:DI
6513 [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
6514 (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
6515 UNSPEC_ADDP4))]
6516 "addp4_optimize_ok (operands[1], operands[2])"
6517 "addp4 %0 = %2, %1"
6518 [(set_attr "itanium_class" "ialu")])
6520 (define_insn "*ptr_extend_plus_2"
6521 [(set (match_operand:DI 0 "gr_register_operand" "=r")
6522 (unspec:DI
6523 [(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
6524 (match_operand:SI 2 "basereg_operand" "r"))]
6525 UNSPEC_ADDP4))]
6526 "addp4_optimize_ok (operands[1], operands[2])"
6527 "addp4 %0 = %1, %2"
6528 [(set_attr "itanium_class" "ialu")])
6530 ;;
6531 ;; Get instruction pointer
6533 (define_insn "ip_value"
6534 [(set (match_operand:DI 0 "register_operand" "=r")
6535 (pc))]
6536 ""
6537 "mov %0 = ip"
6538 [(set_attr "itanium_class" "frbr")])
6540 ;; Vector operations
6541 (include "vect.md")
6542 ;; Atomic operations
6543 (include "sync.md")