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1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
106 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
138 /* Number of attempts to combine instructions in this function. */
142 /* Number of attempts that got as far as substitution in this function. */
146 /* Number of instructions combined with added SETs in this function. */
150 /* Number of instructions combined in this function. */
154 /* Totals over entire compilation. */
158 /* combine_instructions may try to replace the right hand side of the
159 second instruction with the value of an associated REG_EQUAL note
160 before throwing it at try_combine. That is problematic when there
161 is a REG_DEAD note for a register used in the old right hand side
162 and can cause distribute_notes to do wrong things. This is the
163 second instruction if it has been so modified, null otherwise. */
167 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
171 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
174 \f
176 /* Record last point of death of (hard or pseudo) register n. */
179 /* Record last point of modification of (hard or pseudo) register n. */
182 /* The next group of fields allows the recording of the last value assigned
183 to (hard or pseudo) register n. We use this information to see if an
184 operation being processed is redundant given a prior operation performed
185 on the register. For example, an `and' with a constant is redundant if
186 all the zero bits are already known to be turned off.
188 We use an approach similar to that used by cse, but change it in the
189 following ways:
191 (1) We do not want to reinitialize at each label.
192 (2) It is useful, but not critical, to know the actual value assigned
193 to a register. Often just its form is helpful.
195 Therefore, we maintain the following fields:
197 last_set_value the last value assigned
198 last_set_label records the value of label_tick when the
199 register was assigned
200 last_set_table_tick records the value of label_tick when a
201 value using the register is assigned
202 last_set_invalid set to nonzero when it is not valid
203 to use the value of this register in some
204 register's value
206 To understand the usage of these tables, it is important to understand
207 the distinction between the value in last_set_value being valid and
208 the register being validly contained in some other expression in the
209 table.
211 (The next two parameters are out of date).
213 reg_stat[i].last_set_value is valid if it is nonzero, and either
214 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
216 Register I may validly appear in any expression returned for the value
217 of another register if reg_n_sets[i] is 1. It may also appear in the
218 value for register J if reg_stat[j].last_set_invalid is zero, or
219 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
221 If an expression is found in the table containing a register which may
222 not validly appear in an expression, the register is replaced by
223 something that won't match, (clobber (const_int 0)). */
225 /* Record last value assigned to (hard or pseudo) register n. */
227 rtx last_set_value;
229 /* Record the value of label_tick when an expression involving register n
230 is placed in last_set_value. */
234 /* Record the value of label_tick when the value for register n is placed in
235 last_set_value. */
239 /* These fields are maintained in parallel with last_set_value and are
240 used to store the mode in which the register was last set, the bits
241 that were known to be zero when it was last set, and the number of
242 sign bits copies it was known to have when it was last set. */
248 /* Set nonzero if references to register n in expressions should not be
249 used. last_set_invalid is set nonzero when this register is being
250 assigned to and last_set_table_tick == label_tick. */
254 /* Some registers that are set more than once and used in more than one
255 basic block are nevertheless always set in similar ways. For example,
256 a QImode register may be loaded from memory in two places on a machine
257 where byte loads zero extend.
259 We record in the following fields if a register has some leading bits
260 that are always equal to the sign bit, and what we know about the
261 nonzero bits of a register, specifically which bits are known to be
262 zero.
264 If an entry is zero, it means that we don't know anything special. */
270 /* Record the value of the label_tick when the last truncation
271 happened. The field truncated_to_mode is only valid if
272 truncation_label == label_tick. */
276 /* Record the last truncation seen for this register. If truncation
277 is not a nop to this mode we might be able to save an explicit
278 truncation if we know that value already contains a truncated
279 value. */
287 /* One plus the highest pseudo for which we track REG_N_SETS.
288 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
289 but during combine_split_insns new pseudos can be created. As we don't have
290 updated DF information in that case, it is hard to initialize the array
291 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
292 so instead of growing the arrays, just assume all newly created pseudos
293 during combine might be set multiple times. */
297 /* Record the luid of the last insn that invalidated memory
298 (anything that writes memory, and subroutine calls, but not pushes). */
302 /* Record the luid of the last CALL_INSN
303 so we can tell whether a potential combination crosses any calls. */
307 /* When `subst' is called, this is the insn that is being modified
308 (by combining in a previous insn). The PATTERN of this insn
309 is still the old pattern partially modified and it should not be
310 looked at, but this may be used to examine the successors of the insn
311 to judge whether a simplification is valid. */
315 /* This is the lowest LUID that `subst' is currently dealing with.
316 get_last_value will not return a value if the register was set at or
317 after this LUID. If not for this mechanism, we could get confused if
318 I2 or I1 in try_combine were an insn that used the old value of a register
319 to obtain a new value. In that case, we might erroneously get the
320 new value of the register when we wanted the old one. */
324 /* This contains any hard registers that are used in newpat; reg_dead_at_p
325 must consider all these registers to be always live. */
329 /* This is an insn to which a LOG_LINKS entry has been added. If this
330 insn is the earlier than I2 or I3, combine should rescan starting at
331 that location. */
335 /* Basic block in which we are performing combines. */
339 \f
340 /* Length of the currently allocated uid_insn_cost array. */
344 /* The following array records the insn_rtx_cost for every insn
345 in the instruction stream. */
349 /* The following array records the LOG_LINKS for every insn in the
350 instruction stream as struct insn_link pointers. */
356 };
360 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
361 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
363 #define FOR_EACH_LOG_LINK(L, INSN) \
364 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
366 /* Links for LOG_LINKS are allocated from this obstack. */
370 /* Allocate a link. */
374 {
382 }
384 /* Incremented for each basic block. */
388 /* Reset to label_tick for each extended basic block in scanning order. */
392 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
393 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
397 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
398 be safely used. It is zero while computing them and after combine has
399 completed. This former test prevents propagating values based on
400 previously set values, which can be incorrect if a variable is modified
401 in a loop. */
405 \f
406 /* Record one modification to rtl structure
407 to be undone by storing old_contents into *where. */
411 struct undo
412 {
417 };
419 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
420 num_undo says how many are currently recorded.
422 other_insn is nonzero if we have modified some other insn in the process
423 of working on subst_insn. It must be verified too. */
425 struct undobuf
426 {
430 };
434 /* Number of times the pseudo being substituted for
435 was found and replaced. */
440 machine_mode,
444 machine_mode,
516 \f
518 /* It is not safe to use ordinary gen_lowpart in combine.
519 See comments in gen_lowpart_for_combine. */
520 #undef RTL_HOOKS_GEN_LOWPART
521 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
523 /* Our implementation of gen_lowpart never emits a new pseudo. */
524 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
525 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
527 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
528 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
530 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
531 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
533 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
534 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
538 \f
539 /* Convenience wrapper for the canonicalize_comparison target hook.
540 Target hooks cannot use enum rtx_code. */
544 {
548 }
550 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
551 PATTERN can not be split. Otherwise, it returns an insn sequence.
552 This is a wrapper around split_insns which ensures that the
553 reg_stat vector is made larger if the splitter creates a new
554 register. */
558 {
567 }
569 /* This is used by find_single_use to locate an rtx in LOC that
570 contains exactly one use of DEST, which is typically either a REG
571 or CC0. It returns a pointer to the innermost rtx expression
572 containing DEST. Appearances of DEST that are being used to
573 totally replace it are not counted. */
577 {
586 {
590 CASE_CONST_ANY:
595 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
596 of a REG that occupies all of the REG, the insn uses DEST if
597 it is mentioned in the destination or the source. Otherwise, we
598 need just check the source. */
618 }
620 /* If it wasn't one of the common cases above, check each expression and
621 vector of this code. Look for a unique usage of DEST. */
625 {
627 {
632 else
638 /* Duplicate usage. */
640 }
642 {
646 {
652 else
659 }
660 }
661 }
664 }
667 /* See if DEST, produced in INSN, is used only a single time in the
668 sequel. If so, return a pointer to the innermost rtx expression in which
669 it is used.
671 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
673 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
674 care about REG_DEAD notes or LOG_LINKS.
676 Otherwise, we find the single use by finding an insn that has a
677 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
678 only referenced once in that insn, we know that it must be the first
679 and last insn referencing DEST. */
683 {
684 basic_block bb;
689 #ifdef HAVE_cc0
691 {
701 }
702 #endif
712 {
718 {
723 }
724 }
727 }
728 \f
729 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
730 insn. The substitution can be undone by undo_all. If INTO is already
731 set to NEWVAL, do not record this change. Because computing NEWVAL might
732 also call SUBST, we have to compute it before we put anything into
733 the undo table. */
735 static void
737 {
744 /* We'd like to catch as many invalid transformations here as
745 possible. Unfortunately, there are way too many mode changes
746 that are perfectly valid, so we'd waste too much effort for
747 little gain doing the checks here. Focus on catching invalid
748 transformations involving integer constants. */
751 {
752 /* Sanity check that we're replacing oldval with a CONST_INT
753 that is a valid sign-extension for the original mode. */
757 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
758 CONST_INT is not valid, because after the replacement, the
759 original mode would be gone. Unfortunately, we can't tell
760 when do_SUBST is called to replace the operand thereof, so we
761 perform this test on oldval instead, checking whether an
762 invalid replacement took place before we got here. */
767 }
771 else
780 }
782 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
784 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
785 for the value of a HOST_WIDE_INT value (including CONST_INT) is
786 not safe. */
788 static void
790 {
799 else
808 }
810 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
812 /* Similar to SUBST, but just substitute the mode. This is used when
813 changing the mode of a pseudo-register, so that any other
814 references to the entry in the regno_reg_rtx array will change as
815 well. */
817 static void
819 {
828 else
837 }
839 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
841 #ifndef HAVE_cc0
842 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
844 static void
846 {
855 else
864 }
866 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
867 #endif
868 \f
869 /* Subroutine of try_combine. Determine whether the replacement patterns
870 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
871 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
872 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
873 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
874 of all the instructions can be estimated and the replacements are more
875 expensive than the original sequence. */
877 static bool
880 {
885 /* Lookup the original insn_rtx_costs. */
890 {
893 {
897 }
898 else
899 {
903 }
904 }
905 else
906 {
909 }
911 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
912 correct that. */
917 /* Calculate the replacement insn_rtx_costs. */
920 {
924 }
925 else
926 {
929 }
932 {
938 {
941 }
942 else
944 }
946 /* Disallow this combination if both new_cost and old_cost are greater than
947 zero, and new_cost is greater than old cost. */
951 {
970 else
972 }
977 /* Update the uid_insn_cost array with the replacement costs. */
981 {
985 }
988 }
991 /* Delete any insns that copy a register to itself. */
993 static void
995 {
997 basic_block bb;
1000 {
1002 {
1005 {
1010 }
1011 }
1012 }
1013 }
1015 \f
1016 /* Return false if we do not want to (or cannot) combine DEF. */
1017 static bool
1019 {
1020 /* Do not consider if it is pre/post modification in MEM. */
1026 /* Do not combine frame pointer adjustments. */
1029 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1032 #endif
1033 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1035 #endif
1036 )
1040 }
1042 /* Return false if we do not want to (or cannot) combine USE. */
1043 static bool
1045 {
1046 /* Do not consider the usage of the stack pointer by function call. */
1051 }
1053 /* Fill in log links field for all insns. */
1055 static void
1057 {
1058 basic_block bb;
1065 /* Pass through each block from the end, recording the uses of each
1066 register and establishing log links when def is encountered.
1067 Note that we do not clear next_use array in order to save time,
1068 so we have to test whether the use is in the same basic block as def.
1070 There are a few cases below when we do not consider the definition or
1071 usage -- these are taken from original flow.c did. Don't ask me why it is
1072 done this way; I don't know and if it works, I don't want to know. */
1075 {
1077 {
1081 /* Log links are created only once. */
1085 {
1101 /* flow.c claimed:
1103 We don't build a LOG_LINK for hard registers contained
1104 in ASM_OPERANDs. If these registers get replaced,
1105 we might wind up changing the semantics of the insn,
1106 even if reload can make what appear to be valid
1107 assignments later. */
1112 /* Don't add duplicate links between instructions. */
1121 }
1126 }
1127 }
1130 }
1132 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1133 true if we found a LOG_LINK that proves that A feeds B. This only works
1134 if there are no instructions between A and B which could have a link
1135 depending on A, since in that case we would not record a link for B.
1136 We also check the implicit dependency created by a cc0 setter/user
1137 pair. */
1139 static bool
1141 {
1146 #ifdef HAVE_cc0
1149 #endif
1151 }
1152 \f
1153 /* Main entry point for combiner. F is the first insn of the function.
1154 NREGS is the first unused pseudo-reg number.
1156 Return nonzero if the combiner has turned an indirect jump
1157 instruction into a direct jump. */
1158 static int
1160 {
1162 #ifdef HAVE_cc0
1164 #endif
1167 basic_block last_bb;
1187 /* Allocate array for insn info. */
1195 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1196 problems when, for example, we have j <<= 1 in a loop. */
1201 /* Scan all SETs and see if we can deduce anything about what
1202 bits are known to be zero for some registers and how many copies
1203 of the sign bit are known to exist for those registers.
1205 Also set any known values so that we can use it while searching
1206 for what bits are known to be set. */
1209 /* Allow the entry block and the first block to fall into the same EBB.
1210 Conceptually the incoming promotions are assigned to the entry block. */
1215 {
1220 label_tick++;
1228 {
1229 #ifdef AUTO_INC_DEC
1230 rtx links;
1231 #endif
1237 insn);
1240 #ifdef AUTO_INC_DEC
1244 insn);
1245 #endif
1247 /* Record the current insn_rtx_cost of this instruction. */
1250 optimize_this_for_speed_p);
1254 }
1255 }
1259 /* Now scan all the insns in forward order. */
1267 {
1273 label_tick++;
1283 {
1297 /* See if we know about function return values before this
1298 insn based upon SUBREG flags. */
1301 /* See if we can find hardregs and subreg of pseudos in
1302 narrower modes. This could help turning TRUNCATEs
1303 into SUBREGs. */
1306 /* Try this insn with each insn it links back to. */
1312 {
1315 }
1317 /* Try each sequence of three linked insns ending with this one. */
1321 {
1324 /* If the linked insn has been replaced by a note, then there
1325 is no point in pursuing this chain any further. */
1333 {
1336 }
1337 }
1339 #ifdef HAVE_cc0
1340 /* Try to combine a jump insn that uses CC0
1341 with a preceding insn that sets CC0, and maybe with its
1342 logical predecessor as well.
1343 This is how we make decrement-and-branch insns.
1344 We need this special code because data flow connections
1345 via CC0 do not get entered in LOG_LINKS. */
1351 {
1362 }
1364 /* Do the same for an insn that explicitly references CC0. */
1371 {
1382 }
1384 /* Finally, see if any of the insns that this insn links to
1385 explicitly references CC0. If so, try this insn, that insn,
1386 and its predecessor if it sets CC0. */
1398 #endif
1400 /* Try combining an insn with two different insns whose results it
1401 uses. */
1411 {
1414 }
1416 /* Try four-instruction combinations. */
1419 {
1423 /* If the linked insn has been replaced by a note, then there
1424 is no point in pursuing this chain any further. */
1429 {
1433 /* I0 -> I1 -> I2 -> I3. */
1439 {
1442 }
1443 /* I0, I1 -> I2, I2 -> I3. */
1450 {
1453 }
1454 }
1457 {
1461 /* I0 -> I2; I1, I2 -> I3. */
1467 {
1470 }
1471 /* I0 -> I1; I1, I2 -> I3. */
1477 {
1480 }
1481 }
1482 }
1484 /* Try this insn with each REG_EQUAL note it links back to. */
1486 {
1492 /* Avoid using a register that may already been marked
1493 dead by an earlier instruction. */
1498 {
1499 /* Temporarily replace the set's source with the
1500 contents of the REG_EQUAL note. The insn will
1501 be deleted or recognized by try_combine. */
1509 last_combined_insn);
1512 {
1515 }
1517 }
1518 }
1523 retry:
1524 ;
1525 }
1526 }
1533 /* Clean up. */
1539 {
1542 {
1545 }
1547 }
1557 /* Make recognizer allow volatile MEMs again. */
1561 }
1563 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1565 static void
1567 {
1573 }
1574 \f
1575 /* Set up any promoted values for incoming argument registers. */
1577 static void
1579 {
1580 tree arg;
1585 {
1590 /* Only continue if the incoming argument is in a register. */
1594 /* Determine, if possible, whether all call sites of the current
1595 function lie within the current compilation unit. (This does
1596 take into account the exporting of a function via taking its
1597 address, and so forth.) */
1600 /* The mode and signedness of the argument before any promotions happen
1601 (equal to the mode of the pseudo holding it at that stage). */
1605 /* The mode and signedness of the argument after any source language and
1606 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1610 /* The mode and signedness of the argument as it is actually passed,
1611 see assign_parm_setup_reg in function.c. */
1615 /* The mode of the register in which the argument is being passed. */
1618 /* Eliminate sign extensions in the callee when:
1619 (a) A mode promotion has occurred; */
1622 /* (b) The mode of the register is the same as the mode of
1623 the argument as it is passed; */
1626 /* (c) There's no language level extension; */
1628 ;
1629 /* (c.1) All callers are from the current compilation unit. If that's
1630 the case we don't have to rely on an ABI, we only have to know
1631 what we're generating right now, and we know that we will do the
1632 mode1 to mode2 promotion with the given sign. */
1635 /* (c.2) The combination of the two promotions is useful. This is
1636 true when the signs match, or if the first promotion is unsigned.
1637 In the later case, (sign_extend (zero_extend x)) is the same as
1638 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1644 /* Record that the value was promoted from mode1 to mode3,
1645 so that any sign extension at the head of the current
1646 function may be eliminated. */
1650 }
1651 }
1653 /* Called via note_stores. If X is a pseudo that is narrower than
1654 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1656 If we are setting only a portion of X and we can't figure out what
1657 portion, assume all bits will be used since we don't know what will
1658 be happening.
1660 Similarly, set how many bits of X are known to be copies of the sign bit
1661 at all locations in the function. This is the smallest number implied
1662 by any set of X. */
1664 static void
1666 {
1672 /* If this register is undefined at the start of the file, we can't
1673 say what its contents were. */
1674 && ! REGNO_REG_SET_P
1677 {
1681 {
1685 }
1687 /* If this register is being initialized using itself, and the
1688 register is uninitialized in this basic block, and there are
1689 no LOG_LINKS which set the register, then part of the
1690 register is uninitialized. In that case we can't assume
1691 anything about the number of nonzero bits.
1693 ??? We could do better if we checked this in
1694 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1695 could avoid making assumptions about the insn which initially
1696 sets the register, while still using the information in other
1697 insns. We would have to be careful to check every insn
1698 involved in the combination. */
1704 {
1711 {
1715 }
1716 }
1718 /* If this is a complex assignment, see if we can convert it into a
1719 simple assignment. */
1722 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1723 set what we know about X. */
1728 {
1731 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1732 /* If X is narrower than a word and SRC is a non-negative
1733 constant that would appear negative in the mode of X,
1734 sign-extend it for use in reg_stat[].nonzero_bits because some
1735 machines (maybe most) will actually do the sign-extension
1736 and this is the conservative approach.
1738 ??? For 2.5, try to tighten up the MD files in this regard
1739 instead of this kludge. */
1746 #endif
1748 /* Don't call nonzero_bits if it cannot change anything. */
1755 }
1756 else
1757 {
1760 }
1761 }
1762 }
1763 \f
1764 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1765 optionally insns that were previously combined into I3 or that will be
1766 combined into the merger of INSN and I3. The order is PRED, PRED2,
1767 INSN, SUCC, SUCC2, I3.
1769 Return 0 if the combination is not allowed for any reason.
1771 If the combination is allowed, *PDEST will be set to the single
1772 destination of INSN and *PSRC to the single source, and this function
1773 will return 1. */
1775 static int
1779 {
1784 #ifdef AUTO_INC_DEC
1785 rtx link;
1786 #endif
1791 {
1793 {
1798 }
1803 }
1807 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1808 or a PARALLEL consisting of such a SET and CLOBBERs.
1810 If INSN has CLOBBER parallel parts, ignore them for our processing.
1811 By definition, these happen during the execution of the insn. When it
1812 is merged with another insn, all bets are off. If they are, in fact,
1813 needed and aren't also supplied in I3, they may be added by
1814 recog_for_combine. Otherwise, it won't match.
1816 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1817 note.
1819 Get the source and destination of INSN. If more than one, can't
1820 combine. */
1826 {
1828 {
1832 {
1833 /* This is important to combine floating point insns
1834 for the SH4 port. */
1836 /* Combining an isolated USE doesn't make sense.
1837 We depend here on combinable_i3pat to reject them. */
1838 /* The code below this loop only verifies that the inputs of
1839 the SET in INSN do not change. We call reg_set_between_p
1840 to verify that the REG in the USE does not change between
1841 I3 and INSN.
1842 If the USE in INSN was for a pseudo register, the matching
1843 insn pattern will likely match any register; combining this
1844 with any other USE would only be safe if we knew that the
1845 used registers have identical values, or if there was
1846 something to tell them apart, e.g. different modes. For
1847 now, we forgo such complicated tests and simply disallow
1848 combining of USES of pseudo registers with any other USE. */
1851 {
1856 do
1857 {
1867 }
1869 }
1872 /* We can ignore CLOBBERs. */
1877 /* Ignore SETs whose result isn't used but not those that
1878 have side-effects. */
1884 /* If we have already found a SET, this is a second one and
1885 so we cannot combine with this insn. */
1893 /* Anything else means we can't combine. */
1895 }
1896 }
1899 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1900 so don't do anything with it. */
1903 }
1904 else
1910 /* The simplification in expand_field_assignment may call back to
1911 get_last_value, so set safe guard here. */
1917 /* Don't eliminate a store in the stack pointer. */
1919 /* Don't combine with an insn that sets a register to itself if it has
1920 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1922 /* Can't merge an ASM_OPERANDS. */
1924 /* Can't merge a function call. */
1926 /* Don't eliminate a function call argument. */
1932 /* Don't substitute into an incremented register. */
1936 /* Don't substitute into a non-local goto, this confuses CFG. */
1938 /* Make sure that DEST is not used after SUCC but before I3. */
1939 || (!all_adjacent
1940 && ((succ2
1944 /* Make sure that the value that is to be substituted for the register
1945 does not use any registers whose values alter in between. However,
1946 If the insns are adjacent, a use can't cross a set even though we
1947 think it might (this can happen for a sequence of insns each setting
1948 the same destination; last_set of that register might point to
1949 a NOTE). If INSN has a REG_EQUIV note, the register is always
1950 equivalent to the memory so the substitution is valid even if there
1951 are intervening stores. Also, don't move a volatile asm or
1952 UNSPEC_VOLATILE across any other insns. */
1953 || (! all_adjacent
1959 /* Don't combine across a CALL_INSN, because that would possibly
1960 change whether the life span of some REGs crosses calls or not,
1961 and it is a pain to update that information.
1962 Exception: if source is a constant, moving it later can't hurt.
1963 Accept that as a special case. */
1967 /* DEST must either be a REG or CC0. */
1969 {
1970 /* If register alignment is being enforced for multi-word items in all
1971 cases except for parameters, it is possible to have a register copy
1972 insn referencing a hard register that is not allowed to contain the
1973 mode being copied and which would not be valid as an operand of most
1974 insns. Eliminate this problem by not combining with such an insn.
1976 Also, on some machines we don't want to extend the life of a hard
1977 register. */
1982 /* Don't extend the life of a hard register unless it is
1983 user variable (if we have few registers) or it can't
1984 fit into the desired register (meaning something special
1985 is going on).
1986 Also avoid substituting a return register into I3, because
1987 reload can't handle a conflict with constraints of other
1988 inputs. */
1992 }
2000 {
2003 /* If the clobber represents an earlyclobber operand, we must not
2004 substitute an expression containing the clobbered register.
2005 As we do not analyze the constraint strings here, we have to
2006 make the conservative assumption. However, if the register is
2007 a fixed hard reg, the clobber cannot represent any operand;
2008 we leave it up to the machine description to either accept or
2009 reject use-and-clobber patterns. */
2015 }
2017 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2018 or not), reject, unless nothing volatile comes between it and I3 */
2021 {
2022 /* Make sure neither succ nor succ2 contains a volatile reference. */
2027 /* We'll check insns between INSN and I3 below. */
2028 }
2030 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2031 to be an explicit register variable, and was chosen for a reason. */
2037 /* If INSN contains volatile references (specifically volatile MEMs),
2038 we cannot combine across any other volatile references.
2039 Even if INSN doesn't contain volatile references, any intervening
2040 volatile insn might affect machine state. */
2043 ? volatile_refs_p
2050 /* If INSN contains an autoincrement or autodecrement, make sure that
2051 register is not used between there and I3, and not already used in
2052 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2053 Also insist that I3 not be a jump; if it were one
2054 and the incremented register were spilled, we would lose. */
2056 #ifdef AUTO_INC_DEC
2071 #endif
2073 #ifdef HAVE_cc0
2074 /* Don't combine an insn that follows a CC0-setting insn.
2075 An insn that uses CC0 must not be separated from the one that sets it.
2076 We do, however, allow I2 to follow a CC0-setting insn if that insn
2077 is passed as I1; in that case it will be deleted also.
2078 We also allow combining in this case if all the insns are adjacent
2079 because that would leave the two CC0 insns adjacent as well.
2080 It would be more logical to test whether CC0 occurs inside I1 or I2,
2081 but that would be much slower, and this ought to be equivalent. */
2087 #endif
2089 /* If we get here, we have passed all the tests and the combination is
2090 to be allowed. */
2096 }
2097 \f
2098 /* LOC is the location within I3 that contains its pattern or the component
2099 of a PARALLEL of the pattern. We validate that it is valid for combining.
2101 One problem is if I3 modifies its output, as opposed to replacing it
2102 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2103 doing so would produce an insn that is not equivalent to the original insns.
2105 Consider:
2107 (set (reg:DI 101) (reg:DI 100))
2108 (set (subreg:SI (reg:DI 101) 0) <foo>)
2110 This is NOT equivalent to:
2112 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2113 (set (reg:DI 101) (reg:DI 100))])
2115 Not only does this modify 100 (in which case it might still be valid
2116 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2118 We can also run into a problem if I2 sets a register that I1
2119 uses and I1 gets directly substituted into I3 (not via I2). In that
2120 case, we would be getting the wrong value of I2DEST into I3, so we
2121 must reject the combination. This case occurs when I2 and I1 both
2122 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2123 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2124 of a SET must prevent combination from occurring. The same situation
2125 can occur for I0, in which case I0_NOT_IN_SRC is set.
2127 Before doing the above check, we first try to expand a field assignment
2128 into a set of logical operations.
2130 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2131 we place a register that is both set and used within I3. If more than one
2132 such register is detected, we fail.
2134 Return 1 if the combination is valid, zero otherwise. */
2136 static int
2139 {
2143 {
2148 rtx subdest;
2155 /* Check for the case where I3 modifies its output, as discussed
2156 above. We don't want to prevent pseudos from being combined
2157 into the address of a MEM, so only prevent the combination if
2158 i1 or i2 set the same MEM. */
2168 /* This is the same test done in can_combine_p except we can't test
2169 all_adjacent; we don't have to, since this instruction will stay
2170 in place, thus we are not considering increasing the lifetime of
2171 INNER_DEST.
2173 Also, if this insn sets a function argument, combining it with
2174 something that might need a spill could clobber a previous
2175 function argument; the all_adjacent test in can_combine_p also
2176 checks this; here, we do a more specific test for this case. */
2186 /* If DEST is used in I3, it is being killed in this insn, so
2187 record that for later. We have to consider paradoxical
2188 subregs here, since they kill the whole register, but we
2189 ignore partial subregs, STRICT_LOW_PART, etc.
2190 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2191 STACK_POINTER_REGNUM, since these are always considered to be
2192 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2202 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2204 #endif
2205 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2208 #endif
2210 {
2215 }
2216 }
2219 {
2226 }
2229 }
2230 \f
2231 /* Return 1 if X is an arithmetic expression that contains a multiplication
2232 and division. We don't count multiplications by powers of two here. */
2234 static int
2236 {
2238 {
2254 }
2255 }
2256 \f
2257 /* Determine whether INSN can be used in a combination. Return nonzero if
2258 not. This is used in try_combine to detect early some cases where we
2259 can't perform combinations. */
2261 static int
2263 {
2264 rtx set;
2267 /* If this isn't really an insn, we can't do anything.
2268 This can occur when flow deletes an insn that it has merged into an
2269 auto-increment address. */
2273 /* Never combine loads and stores involving hard regs that are likely
2274 to be spilled. The register allocator can usually handle such
2275 reg-reg moves by tying. If we allow the combiner to make
2276 substitutions of likely-spilled regs, reload might die.
2277 As an exception, we allow combinations involving fixed regs; these are
2278 not available to the register allocator so there's no risk involved. */
2299 }
2301 struct likely_spilled_retval_info
2302 {
2305 };
2307 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2308 hard registers that are known to be written to / clobbered in full. */
2309 static void
2311 {
2328 else
2331 }
2333 /* Return nonzero iff part of the return value is live during INSN, and
2334 it is likely spilled. This can happen when more than one insn is needed
2335 to copy the return value, e.g. when we consider to combine into the
2336 second copy insn for a complex value. */
2338 static int
2340 {
2342 rtx reg;
2345 /* We assume here that no machine mode needs more than
2346 32 hard registers when the value overlaps with a register
2347 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2362 /* Disregard parts of the return value that are set later. */
2371 /* Check if any of the (probably) live return value registers is
2372 likely spilled. */
2373 nregs --;
2374 do
2375 {
2381 }
2383 /* Adjust INSN after we made a change to its destination.
2385 Changing the destination can invalidate notes that say something about
2386 the results of the insn and a LOG_LINK pointing to the insn. */
2388 static void
2390 {
2391 /* For notes, be conservative and simply remove them. */
2394 /* The new insn will have a destination that was previously the destination
2395 of an insn just above it. Call distribute_links to make a LOG_LINK from
2396 the next use of that destination. */
2412 }
2414 /* Return TRUE if combine can reuse reg X in mode MODE.
2415 ADDED_SETS is nonzero if the original set is still required. */
2416 static bool
2418 {
2425 /* Allow hard registers if the new mode is legal, and occupies no more
2426 registers than the old mode. */
2432 /* Or a pseudo that is only used once. */
2435 && !added_sets
2437 }
2440 /* Check whether X, the destination of a set, refers to part of
2441 the register specified by REG. */
2443 static bool
2445 {
2446 /* Check that reg is an integer mode register. */
2457 }
2459 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2460 Note that the INSN should be deleted *after* removing dead edges, so
2461 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2462 but not for a (set (pc) (label_ref FOO)). */
2464 static void
2466 {
2474 {
2479 /* Remove barriers from the footer if there are any. */
2482 {
2485 else
2489 }
2492 }
2493 }
2495 #ifndef HAVE_cc0
2496 /* Return whether INSN is a PARALLEL of exactly N register SETs followed
2497 by an arbitrary number of CLOBBERs. */
2498 static bool
2500 {
2520 }
2522 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2523 CLOBBERs), can be split into individual SETs in that order, without
2524 changing semantics. */
2525 static bool
2527 {
2535 {
2544 }
2547 }
2548 #endif
2550 /* Try to combine the insns I0, I1 and I2 into I3.
2551 Here I0, I1 and I2 appear earlier than I3.
2552 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2553 I3.
2555 If we are combining more than two insns and the resulting insn is not
2556 recognized, try splitting it into two insns. If that happens, I2 and I3
2557 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2558 Otherwise, I0, I1 and I2 are pseudo-deleted.
2560 Return 0 if the combination does not work. Then nothing is changed.
2561 If we did the combination, return the insn at which combine should
2562 resume scanning.
2564 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2565 new direct jump instruction.
2567 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2568 been I3 passed to an earlier try_combine within the same basic
2569 block. */
2574 {
2575 /* New patterns for I3 and I2, respectively. */
2579 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2580 dead. */
2582 /* Total number of SETs to put into I3. */
2584 /* Nonzero if I2's or I1's body now appears in I3. */
2586 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2588 /* Contains I3 if the destination of I3 is used in its source, which means
2589 that the old life of I3 is being killed. If that usage is placed into
2590 I2 and not in I3, a REG_DEAD note must be made. */
2592 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2594 /* Copy of SET_SRC of I1 and I0, if needed. */
2596 /* Set if I2DEST was reused as a scratch register. */
2598 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2600 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2605 /* Notes that must be added to REG_NOTES in I3 and I2. */
2607 /* Notes that we substituted I3 into I2 instead of the normal case. */
2609 /* Notes that I1, I2 or I3 is a MULT operation. */
2616 rtx temp_expr;
2619 rtx new_other_notes;
2622 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2623 never be). */
2627 /* Only try four-insn combinations when there's high likelihood of
2628 success. Look for simple insns, such as loads of constants or
2629 binary operations involving a constant. */
2631 {
2641 {
2644 rtx src;
2649 {
2652 }
2654 ngood++;
2657 nshift++;
2658 }
2660 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2661 are likely manipulating its value. Ideally we'll be able to combine
2662 all four insns into a bitfield insertion of some kind.
2664 Note the source in I0 might be inside a sign/zero extension and the
2665 memory modes in I0 and I3 might be different. So extract the address
2666 from the destination of I3 and search for it in the source of I0.
2668 In the event that there's a match but the source/dest do not actually
2669 refer to the same memory, the worst that happens is we try some
2670 combinations that we wouldn't have otherwise. */
2672 /* Ensure the source of SET0 is a MEM, possibly buried inside
2673 an extension. */
2679 /* Ensure the destination of SET3 is a MEM. */
2681 /* Would it be better to extract the base address for the MEM
2682 in SET3 and look for that? I don't have cases where it matters
2683 but I could envision such cases. */
2689 }
2691 /* Exit early if one of the insns involved can't be used for
2692 combinations. */
2703 combine_attempts++;
2706 /* Reset the hard register usage information. */
2710 {
2717 else
2720 }
2722 /* If multiple insns feed into one of I2 or I3, they can be in any
2723 order. To simplify the code below, reorder them in sequence. */
2733 /* First check for one important special case that the code below will
2734 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2735 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2736 we may be able to replace that destination with the destination of I3.
2737 This occurs in the common code where we compute both a quotient and
2738 remainder into a structure, in which case we want to do the computation
2739 directly into the structure to avoid register-register copies.
2741 Note that this case handles both multiple sets in I2 and also cases
2742 where I2 has a number of CLOBBERs inside the PARALLEL.
2744 We make very conservative checks below and only try to handle the
2745 most common cases of this. For example, we only handle the case
2746 where I2 and I3 are adjacent to avoid making difficult register
2747 usage tests. */
2755 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2756 below would need to check what is inside (and reg_overlap_mentioned_p
2757 doesn't support those codes anyway). Don't allow those destinations;
2758 the resulting insn isn't likely to be recognized anyway. */
2764 {
2767 /* Make sure that the destination of I3,
2768 which we are going to substitute into one output of I2,
2769 is not used within another output of I2. We must avoid making this:
2770 (parallel [(set (mem (reg 69)) ...)
2771 (set (reg 69) ...)])
2772 which is not well-defined as to order of actions.
2773 (Besides, reload can't handle output reloads for this.)
2775 The problem can also happen if the dest of I3 is a memory ref,
2776 if another dest in I2 is an indirect memory ref. */
2784 /* Make sure this PARALLEL is not an asm. We do not allow combining
2785 that usually (see can_combine_p), so do not here either. */
2795 {
2796 combine_merges++;
2806 /* Replace the dest in I2 with our dest and make the resulting
2807 insn the new pattern for I3. Then skip to where we validate
2808 the pattern. Everything was set up above. */
2813 }
2814 }
2816 /* If I2 is setting a pseudo to a constant and I3 is setting some
2817 sub-part of it to another constant, merge them by making a new
2818 constant. */
2825 {
2831 {
2834 {
2840 }
2841 }
2842 else
2843 {
2848 }
2851 {
2852 /* If this is the low part, we're done. */
2854 ;
2855 /* Handle the case where inner is twice the size of outer. */
2859 /* Otherwise give up for now. */
2860 else
2862 }
2865 {
2869 wide_int o
2874 combine_merges++;
2881 /* Replace the source in I2 with the new constant and make the
2882 resulting insn the new pattern for I3. Then skip to where we
2883 validate the pattern. Everything was set up above. */
2889 /* The dest of I3 has been replaced with the dest of I2. */
2892 }
2893 }
2895 #ifndef HAVE_cc0
2896 /* If we have no I1 and I2 looks like:
2897 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2898 (set Y OP)])
2899 make up a dummy I1 that is
2900 (set Y OP)
2901 and change I2 to be
2902 (set (reg:CC X) (compare:CC Y (const_int 0)))
2904 (We can ignore any trailing CLOBBERs.)
2906 This undoes a previous combination and allows us to match a branch-and-
2907 decrement insn. */
2919 {
2920 /* We make I1 with the same INSN_UID as I2. This gives it
2921 the same DF_INSN_LUID for value tracking. Our fake I1 will
2922 never appear in the insn stream so giving it the same INSN_UID
2923 as I2 will not cause a problem. */
2936 }
2938 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2939 make those two SETs separate I1 and I2 insns, and make an I0 that is
2940 the original I1. */
2946 {
2947 /* If there is no I1, there is no I0 either. */
2950 /* We make I1 with the same INSN_UID as I2. This gives it
2951 the same DF_INSN_LUID for value tracking. Our fake I1 will
2952 never appear in the insn stream so giving it the same INSN_UID
2953 as I2 will not cause a problem. */
2961 }
2962 #endif
2964 /* Verify that I2 and I1 are valid for combining. */
2970 {
2973 }
2975 /* Record whether I2DEST is used in I2SRC and similarly for the other
2976 cases. Knowing this will help in register status updating below. */
2987 /* For the earlier insns, determine which of the subsequent ones they
2988 feed. */
2995 /* Ensure that I3's pattern can be the destination of combines. */
3001 {
3004 }
3006 /* See if any of the insns is a MULT operation. Unless one is, we will
3007 reject a combination that is, since it must be slower. Be conservative
3008 here. */
3016 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3017 We used to do this EXCEPT in one case: I3 has a post-inc in an
3018 output operand. However, that exception can give rise to insns like
3019 mov r3,(r3)+
3020 which is a famous insn on the PDP-11 where the value of r3 used as the
3021 source was model-dependent. Avoid this sort of thing. */
3023 #if 0
3029 /* It's not the exception. */
3030 #endif
3031 #ifdef AUTO_INC_DEC
3032 {
3033 rtx link;
3039 {
3042 }
3043 }
3044 #endif
3046 /* See if the SETs in I1 or I2 need to be kept around in the merged
3047 instruction: whenever the value set there is still needed past I3.
3048 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3050 For the SET in I1, we have two cases: if I1 and I2 independently feed
3051 into I3, the set in I1 needs to be kept around unless I1DEST dies
3052 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3053 in I1 needs to be kept around unless I1DEST dies or is set in either
3054 I2 or I3. The same considerations apply to I0. */
3061 else
3069 else
3072 /* We are about to copy insns for the case where they need to be kept
3073 around. Check that they can be copied in the merged instruction. */
3079 {
3082 }
3084 /* If the set in I2 needs to be kept around, we must make a copy of
3085 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3086 PATTERN (I2), we are only substituting for the original I1DEST, not into
3087 an already-substituted copy. This also prevents making self-referential
3088 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3089 I2DEST. */
3092 {
3095 else
3097 }
3100 {
3103 else
3105 }
3108 {
3111 else
3113 }
3115 combine_merges++;
3117 /* Substitute in the latest insn for the regs set by the earlier ones. */
3123 #ifndef HAVE_cc0
3124 /* Many machines that don't use CC0 have insns that can both perform an
3125 arithmetic operation and set the condition code. These operations will
3126 be represented as a PARALLEL with the first element of the vector
3127 being a COMPARE of an arithmetic operation with the constant zero.
3128 The second element of the vector will set some pseudo to the result
3129 of the same arithmetic operation. If we simplify the COMPARE, we won't
3130 match such a pattern and so will generate an extra insn. Here we test
3131 for this case, where both the comparison and the operation result are
3132 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3133 I2SRC. Later we will make the PARALLEL that contains I2. */
3139 {
3140 rtx newpat_dest;
3154 {
3159 }
3161 /* Do the rest only if op1 is const0_rtx, which may be the
3162 result of simplification. */
3164 {
3165 /* If a single use of the CC is found, prepare to modify it
3166 when SELECT_CC_MODE returns a new CC-class mode, or when
3167 the above simplify_compare_const() returned a new comparison
3168 operator. undobuf.other_insn is assigned the CC use insn
3169 when modifying it. */
3171 {
3172 #ifdef SELECT_CC_MODE
3173 machine_mode new_mode
3178 {
3183 else
3184 {
3187 }
3188 }
3189 #endif
3190 /* Cases for modifying the CC-using comparison. */
3192 /* ??? Do we need to verify the zero rtx? */
3194 {
3195 /* Replace cc_use_loc with entire new RTX. */
3200 }
3202 {
3203 /* Just replace the CC reg with a new mode. */
3206 }
3207 }
3209 /* Now we modify the current newpat:
3210 First, SET_DEST(newpat) is updated if the CC mode has been
3211 altered. For targets without SELECT_CC_MODE, this should be
3212 optimized away. */
3215 /* This is always done to propagate i2src into newpat. */
3218 /* Create new version of i2pat if needed; the below PARALLEL
3219 creation needs this to work correctly. */
3223 }
3224 }
3225 #endif
3228 {
3229 /* It is possible that the source of I2 or I1 may be performing
3230 an unneeded operation, such as a ZERO_EXTEND of something
3231 that is known to have the high part zero. Handle that case
3232 by letting subst look at the inner insns.
3234 Another way to do this would be to have a function that tries
3235 to simplify a single insn instead of merging two or more
3236 insns. We don't do this because of the potential of infinite
3237 loops and because of the potential extra memory required.
3238 However, doing it the way we are is a bit of a kludge and
3239 doesn't catch all cases.
3241 But only do this if -fexpensive-optimizations since it slows
3242 things down and doesn't usually win.
3244 This is not done in the COMPARE case above because the
3245 unmodified I2PAT is used in the PARALLEL and so a pattern
3246 with a modified I2SRC would not match. */
3249 {
3250 /* Pass pc_rtx so no substitutions are done, just
3251 simplifications. */
3253 {
3256 }
3260 }
3265 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3266 copy of I2SRC each time we substitute it, in order to avoid creating
3267 self-referential RTL when we will be substituting I1SRC for I1DEST
3268 later. Likewise if I0 feeds into I2, either directly or indirectly
3269 through I1, and I0DEST is in I0SRC. */
3276 /* Record whether I2's body now appears within I3's body. */
3278 }
3280 /* If we already got a failure, don't try to do more. Otherwise, try to
3281 substitute I1 if we have it. */
3284 {
3285 /* Check that an autoincrement side-effect on I1 has not been lost.
3286 This happens if I1DEST is mentioned in I2 and dies there, and
3287 has disappeared from the new pattern. */
3289 && i1_feeds_i2_n
3292 /* Before we can do this substitution, we must redo the test done
3293 above (see detailed comments there) that ensures I1DEST isn't
3294 mentioned in any SETs in NEWPAT that are field assignments. */
3297 {
3300 }
3305 /* If the following substitution will modify I1SRC, make a copy of it
3306 for the case where it is substituted for I1DEST in I2PAT later. */
3310 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3311 copy of I1SRC each time we substitute it, in order to avoid creating
3312 self-referential RTL when we will be substituting I0SRC for I0DEST
3313 later. */
3318 /* Record whether I1's body now appears within I3's body. */
3320 }
3322 /* Likewise for I0 if we have it. */
3325 {
3332 {
3335 }
3337 /* If the following substitution will modify I0SRC, make a copy of it
3338 for the case where it is substituted for I0DEST in I1PAT later. */
3341 /* And a copy for I0DEST in I2PAT substitution. */
3350 }
3352 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3353 to count all the ways that I2SRC and I1SRC can be used. */
3364 /* Fail if we tried to make a new register. */
3366 /* Fail if we couldn't do something and have a CLOBBER. */
3368 /* Fail if this new pattern is a MULT and we didn't have one before
3369 at the outer level. */
3372 {
3375 }
3377 /* If the actions of the earlier insns must be kept
3378 in addition to substituting them into the latest one,
3379 we must make a new PARALLEL for the latest insn
3380 to hold additional the SETs. */
3383 {
3385 combine_extras++;
3388 {
3394 }
3395 else
3396 {
3401 }
3407 {
3413 }
3415 {
3424 }
3425 }
3427 validate_replacement:
3429 /* Note which hard regs this insn has as inputs. */
3432 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3433 consider splitting this pattern, we might need these clobbers. */
3436 {
3442 }
3444 /* We have recognized nothing yet. */
3447 /* See if this is a PARALLEL of two SETs where one SET's destination is
3448 a register that is unused and this isn't marked as an instruction that
3449 might trap in an EH region. In that case, we just need the other SET.
3450 We prefer this over the PARALLEL.
3452 This can occur when simplifying a divmod insn. We *must* test for this
3453 case here because the code below that splits two independent SETs doesn't
3454 handle this case correctly when it updates the register status.
3456 It's pointless doing this if we originally had two sets, one from
3457 i3, and one from i2. Combining then splitting the parallel results
3458 in the original i2 again plus an invalid insn (which we delete).
3459 The net effect is only to move instructions around, which makes
3460 debug info less accurate. */
3468 {
3479 {
3482 }
3491 {
3497 }
3501 }
3503 /* Is the result of combination a valid instruction? */
3507 /* If we were combining three insns and the result is a simple SET
3508 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3509 insns. There are two ways to do this. It can be split using a
3510 machine-specific method (like when you have an addition of a large
3511 constant) or by combine in the function find_split_point. */
3515 {
3519 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3520 use I2DEST as a scratch register will help. In the latter case,
3521 convert I2DEST to the mode of the source of NEWPAT if we can. */
3525 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3526 inputs of NEWPAT. */
3528 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3529 possible to try that as a scratch reg. This would require adding
3530 more code to make it work though. */
3533 {
3536 /* First try to split using the original register as a
3537 scratch register. */
3541 i2dest)));
3544 /* If that didn't work, try changing the mode of I2DEST if
3545 we can. */
3550 {
3552 rtx ni2dest;
3556 else
3557 {
3560 }
3562 parallel = (gen_rtx_PARALLEL
3566 ni2dest))));
3571 {
3579 }
3580 }
3583 }
3585 /* If recog_for_combine has discarded clobbers, try to use them
3586 again for the split. */
3588 {
3591 }
3594 {
3599 }
3603 {
3613 /* If I2 or I3 has multiple SETs, we won't know how to track
3614 register status, so don't use these insns. If I2's destination
3615 is used between I2 and I3, we also can't use these insns. */
3625 /* It is possible that both insns now set the destination of I3.
3626 If so, we must show an extra use of it. */
3629 {
3648 }
3649 }
3651 /* If we can split it and use I2DEST, go ahead and see if that
3652 helps things be recognized. Verify that none of the registers
3653 are set between I2 and I3. */
3656 #ifdef HAVE_cc0
3658 #endif
3659 /* We need I2DEST in the proper mode. If it is a hard register
3660 or the only use of a pseudo, we can change its mode.
3661 Make sure we don't change a hard register to have a mode that
3662 isn't valid for it, or change the number of registers. */
3669 /* We can't overwrite I2DEST if its value is still used by
3670 NEWPAT. */
3672 {
3681 /* *SPLIT may be part of I2SRC, so make sure we have the
3682 original expression around for later debug processing.
3683 We should not need I2SRC any more in other cases. */
3686 else
3689 /* Get NEWDEST as a register in the proper mode. We have already
3690 validated that we can do this. */
3692 {
3695 else
3696 {
3699 }
3700 }
3702 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3703 an ASHIFT. This can occur if it was inside a PLUS and hence
3704 appeared to be a memory address. This is a kludge. */
3709 {
3712 /* Update split_code because we may not have a multiply
3713 anymore. */
3715 }
3717 #ifdef INSN_SCHEDULING
3718 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3719 be written as a ZERO_EXTEND. */
3721 {
3722 #ifdef LOAD_EXTEND_OP
3723 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3724 what it really is. */
3729 else
3730 #endif
3733 }
3734 #endif
3736 /* Attempt to split binary operators using arithmetic identities. */
3740 {
3747 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3749 {
3754 }
3755 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3762 {
3768 /* Split both "((X op Y) op X) op Y" and
3769 "((X op Y) op Y) op X" as "T op T" where T is
3770 "X op Y". */
3773 {
3779 }
3780 /* Split "((X op X) op Y) op Y)" as "T op T" where
3781 T is "X op Y". */
3783 {
3789 }
3790 }
3791 }
3794 {
3797 }
3801 /* recog_for_combine might have added CLOBBERs to newi2pat.
3802 Make sure NEWPAT does not depend on the clobbered regs. */
3806 {
3809 {
3812 }
3813 }
3815 /* If the split point was a MULT and we didn't have one before,
3816 don't use one now. */
3819 }
3820 }
3822 /* Check for a case where we loaded from memory in a narrow mode and
3823 then sign extended it, but we need both registers. In that case,
3824 we have a PARALLEL with both loads from the same memory location.
3825 We can split this into a load from memory followed by a register-register
3826 copy. This saves at least one insn, more if register allocation can
3827 eliminate the copy.
3829 We cannot do this if the destination of the first assignment is a
3830 condition code register or cc0. We eliminate this case by making sure
3831 the SET_DEST and SET_SRC have the same mode.
3833 We cannot do this if the destination of the second assignment is
3834 a register that we have already assumed is zero-extended. Similarly
3835 for a SUBREG of such a register. */
3870 {
3871 rtx ni2dest;
3885 }
3887 /* Similarly, check for a case where we have a PARALLEL of two independent
3888 SETs but we started with three insns. In this case, we can do the sets
3889 as two separate insns. This case occurs when some SET allows two
3890 other insns to combine, but the destination of that SET is still live.
3892 Also do this if we started with two insns and (at least) one of the
3893 resulting sets is a noop; this noop will be deleted later. */
3912 {
3916 /* Normally, it doesn't matter which of the two is done first,
3917 but the one that references cc0 can't be the second, and
3918 one which uses any regs/memory set in between i2 and i3 can't
3919 be first. The PARALLEL might also have been pre-existing in i3,
3920 so we need to make sure that we won't wrongly hoist a SET to i2
3921 that would conflict with a death note present in there. */
3928 #ifdef HAVE_cc0
3930 #endif
3931 /* If I3 is a jump, ensure that set0 is a jump so that
3932 we do not create invalid RTL. */
3934 )
3935 {
3938 }
3945 #ifdef HAVE_cc0
3947 #endif
3948 /* If I3 is a jump, ensure that set1 is a jump so that
3949 we do not create invalid RTL. */
3951 )
3952 {
3955 }
3956 else
3957 {
3960 }
3965 {
3966 /* recog_for_combine might have added CLOBBERs to newi2pat.
3967 Make sure NEWPAT does not depend on the clobbered regs. */
3969 {
3972 {
3975 {
3978 }
3979 }
3980 }
3983 }
3984 }
3986 /* If it still isn't recognized, fail and change things back the way they
3987 were. */
3989 /* Is the result a reasonable ASM_OPERANDS? */
3991 {
3994 }
3996 /* If we had to change another insn, make sure it is valid also. */
3998 {
4006 {
4009 }
4010 }
4012 #ifdef HAVE_cc0
4013 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4014 they are adjacent to each other or not. */
4015 {
4019 {
4022 }
4023 }
4024 #endif
4026 /* Only allow this combination if insn_rtx_costs reports that the
4027 replacement instructions are cheaper than the originals. */
4029 {
4032 }
4035 {
4040 {
4045 /* Temporarily revert mode back. */
4049 {
4050 /* If we used i2dest as a scratch register with a
4051 different mode, substitute it for the original
4052 i2src while its original mode is temporarily
4053 restored, and then clear i2scratch so that we don't
4054 do it again later. */
4056 this_basic_block);
4058 /* Put back the new mode. */
4060 }
4061 else
4062 {
4067 {
4070 }
4071 else
4072 {
4079 }
4081 /* We're dealing with a reg that changed mode but not
4082 meaning, so we want to turn it into a subreg for
4083 the new mode. However, because of REG sharing and
4084 because its mode had already changed, we have to do
4085 it in two steps. First, replace any debug uses of
4086 reg, with its original mode temporarily restored,
4087 with this copy we have created; then, replace the
4088 copy with the SUBREG of the original shared reg,
4089 once again changed to the new mode. */
4091 this_basic_block);
4095 this_basic_block);
4096 }
4097 }
4098 }
4100 /* If we will be able to accept this, we have made a
4101 change to the destination of I3. This requires us to
4102 do a few adjustments. */
4105 {
4108 }
4110 /* We now know that we can do this combination. Merge the insns and
4111 update the status of registers and LOG_LINKS. */
4114 {
4119 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4120 ensure that they are still valid. Then add any non-duplicate
4121 notes added by recog_for_combine. */
4123 {
4133 }
4137 NULL_RTX);
4138 }
4141 {
4144 rtx ni2dest;
4146 /* I3 now uses what used to be its destination and which is now
4147 I2's destination. This requires us to do a few adjustments. */
4151 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4152 so we still will.
4154 However, some later insn might be using I2's dest and have
4155 a LOG_LINK pointing at I3. We must remove this link.
4156 The simplest way to remove the link is to point it at I1,
4157 which we know will be a NOTE. */
4159 /* newi2pat is usually a SET here; however, recog_for_combine might
4160 have added some clobbers. */
4163 else
4170 {
4172 {
4178 }
4179 }
4180 }
4182 {
4187 /* Compute which registers we expect to eliminate. newi2pat may be setting
4188 either i3dest or i2dest, so we must check it. */
4191 || !i2dest_killed
4193 /* For i1, we need to compute both local elimination and global
4194 elimination information with respect to newi2pat because i1dest
4195 may be the same as i3dest, in which case newi2pat may be setting
4196 i1dest. Global information is used when distributing REG_DEAD
4197 note for i2 and i3, in which case it does matter if newi2pat sets
4198 i1dest or not.
4200 Local information is used when distributing REG_DEAD note for i1,
4201 in which case it doesn't matter if newi2pat sets i1dest or not.
4202 See PR62151, if we have four insns combination:
4203 i0: r0 <- i0src
4204 i1: r1 <- i1src (using r0)
4205 REG_DEAD (r0)
4206 i2: r0 <- i2src (using r1)
4207 i3: r3 <- i3src (using r0)
4208 ix: using r0
4209 From i1's point of view, r0 is eliminated, no matter if it is set
4210 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4211 should be discarded.
4213 Note local information only affects cases in forms like "I1->I2->I3",
4214 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4215 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4216 i0dest anyway. */
4218 || !i1dest_killed
4223 /* Same case as i1. */
4230 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4231 clear them. */
4239 /* Ensure that we do not have something that should not be shared but
4240 occurs multiple times in the new insns. Check this by first
4241 resetting all the `used' flags and then copying anything is shared. */
4265 {
4272 {
4273 /* I2SRC must still be meaningful at this point. Some splitting
4274 operations can invalidate I2SRC, but those operations do not
4275 apply to calls. */
4278 }
4286 }
4291 /* We had one special case above where I2 had more than one set and
4292 we replaced a destination of one of those sets with the destination
4293 of I3. In that case, we have to update LOG_LINKS of insns later
4294 in this basic block. Note that this (expensive) case is rare.
4296 Also, in this case, we must pretend that all REG_NOTEs for I2
4297 actually came from I3, so that REG_UNUSED notes from I2 will be
4298 properly handled. */
4301 {
4310 temp_insn
4320 {
4325 }
4326 else
4329 }
4337 {
4340 this_basic_block);
4343 }
4344 else
4345 {
4348 this_basic_block);
4350 }
4353 {
4358 this_basic_block);
4360 }
4363 {
4368 this_basic_block);
4370 }
4372 /* Get death notes for everything that is now used in either I3 or
4373 I2 and used to die in a previous insn. If we built two new
4374 patterns, move from I1 to I2 then I2 to I3 so that we get the
4375 proper movement on registers that I2 modifies. */
4381 else
4387 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4404 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4405 know these are REG_UNUSED and want them to go to the desired insn,
4406 so we always pass it as i3. */
4410 NULL_RTX);
4414 NULL_RTX);
4416 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4417 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4418 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4419 in that case, it might delete I2. Similarly for I2 and I1.
4420 Show an additional death due to the REG_DEAD note we make here. If
4421 we discard it in distribute_notes, we will decrement it again. */
4424 {
4429 else
4432 }
4435 {
4440 else
4443 }
4446 {
4451 else
4454 }
4457 {
4462 else
4465 }
4473 {
4478 /* The insn that used to set this register doesn't exist, and
4479 this life of the register may not exist either. See if one of
4480 I3's links points to an insn that sets I2DEST. If it does,
4481 that is now the last known value for I2DEST. If we don't update
4482 this and I2 set the register to a value that depended on its old
4483 contents, we will get confused. If this insn is used, thing
4484 will be set correctly in combine_instructions. */
4492 /* If the reg formerly set in I2 died only once and that was in I3,
4493 zero its use count so it won't make `reload' do any work. */
4496 && ! i2dest_in_i2src
4499 }
4502 {
4515 && ! i1dest_in_i1src
4518 }
4521 {
4534 && ! i0dest_in_i0src
4537 }
4539 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4540 been made to this insn. The order is important, because newi2pat
4541 can affect nonzero_bits of newpat. */
4545 }
4548 {
4550 {
4553 }
4555 }
4558 {
4560 {
4563 }
4565 }
4568 {
4570 {
4573 }
4575 }
4578 {
4580 {
4583 }
4585 }
4588 {
4590 {
4593 }
4595 }
4597 /* Set new_direct_jump_p if a new return or simple jump instruction
4598 has been created. Adjust the CFG accordingly. */
4600 {
4604 }
4609 {
4612 }
4614 /* A noop might also need cleaning up of CFG, if it comes from the
4615 simplification of a jump. */
4620 {
4623 }
4630 {
4633 }
4635 combine_successes++;
4642 else
4644 }
4645 \f
4646 /* Undo all the modifications recorded in undobuf. */
4648 static void
4650 {
4654 {
4657 {
4672 }
4676 }
4679 }
4681 /* We've committed to accepting the changes we made. Move all
4682 of the undos to the free list. */
4684 static void
4686 {
4690 {
4694 }
4696 }
4697 \f
4698 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4699 where we have an arithmetic expression and return that point. LOC will
4700 be inside INSN.
4702 try_combine will call this function to see if an insn can be split into
4703 two insns. */
4707 {
4716 /* First special-case some codes. */
4718 {
4720 #ifdef INSN_SCHEDULING
4721 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4722 point. */
4725 #endif
4729 #ifdef HAVE_lo_sum
4730 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4731 using LO_SUM and HIGH. */
4734 {
4742 }
4743 #endif
4745 /* If we have a PLUS whose second operand is a constant and the
4746 address is not valid, perhaps will can split it up using
4747 the machine-specific way to split large constants. We use
4748 the first pseudo-reg (one of the virtual regs) as a placeholder;
4749 it will not remain in the result. */
4754 {
4758 subst_insn);
4760 /* This should have produced two insns, each of which sets our
4761 placeholder. If the source of the second is a valid address,
4762 we can make put both sources together and make a split point
4763 in the middle. */
4776 && memory_address_addr_space_p
4779 {
4783 /* Replace the placeholder in SRC2 with SRC1. If we can
4784 find where in SRC2 it was placed, that can become our
4785 split point and we can replace this address with SRC2.
4786 Just try two obvious places. */
4797 {
4800 }
4801 }
4803 /* If that didn't work, perhaps the first operand is complex and
4804 needs to be computed separately, so make a split point there.
4805 This will occur on machines that just support REG + CONST
4806 and have a constant moved through some previous computation. */
4812 }
4814 /* If we have a PLUS whose first operand is complex, try computing it
4815 separately by making a split there. */
4826 #ifdef HAVE_cc0
4827 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4828 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4829 we need to put the operand into a register. So split at that
4830 point. */
4839 #endif
4841 /* See if we can split SET_SRC as it stands. */
4846 /* See if we can split SET_DEST as it stands. */
4851 /* See if this is a bitfield assignment with everything constant. If
4852 so, this is an IOR of an AND, so split it into that. */
4862 {
4868 unsigned HOST_WIDE_INT mask
4870 rtx or_mask;
4879 else
4880 {
4886 or_mask));
4887 }
4894 }
4896 /* Otherwise, see if this is an operation that we can split into two.
4897 If so, try to split that. */
4901 {
4903 /* If we are AND'ing with a large constant that is only a single
4904 bit and the result is only being used in a context where we
4905 need to know if it is zero or nonzero, replace it with a bit
4906 extraction. This will avoid the large constant, which might
4907 have taken more than one insn to make. If the constant were
4908 not a valid argument to the AND but took only one insn to make,
4909 this is no worse, but if it took more than one insn, it will
4910 be better. */
4920 {
4925 {
4928 }
4929 }
4933 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4934 is known to be on, this can be converted into a NEG of a shift. */
4940 {
4952 }
4958 /* We can't optimize if either mode is a partial integer
4959 mode as we don't know how many bits are significant
4960 in those modes. */
4974 {
4982 }
4987 }
4991 {
4994 /* For unsigned, we have a choice of a shift followed by an
4995 AND or two shifts. Use two shifts for field sizes where the
4996 constant might be too large. We assume here that we can
4997 always at least get 8-bit constants in an AND insn, which is
4998 true for every current RISC. */
5001 {
5002 unsigned HOST_WIDE_INT mask
5006 gen_rtx_LSHIFTRT
5014 }
5015 else
5016 {
5018 gen_rtx_fmt_ee
5029 }
5030 }
5032 /* See if this is a simple operation with a constant as the second
5033 operand. It might be that this constant is out of range and hence
5034 could be used as a split point. */
5042 /* Finally, see if this is a simple operation with its first operand
5043 not in a register. The operation might require this operand in a
5044 register, so return it as a split point. We can always do this
5045 because if the first operand were another operation, we would have
5046 already found it as a split point. */
5055 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5056 it is better to write this as (not (ior A B)) so we can split it.
5057 Similarly for IOR. */
5059 {
5067 }
5069 /* Many RISC machines have a large set of logical insns. If the
5070 second operand is a NOT, put it first so we will try to split the
5071 other operand first. */
5073 {
5077 }
5082 /* Canonicalization can produce (minus A (mult B C)), where C is a
5083 constant. It may be better to try splitting (plus (mult B -C) A)
5084 instead if this isn't a multiply by a power of two. */
5088 {
5096 mode)),
5099 }
5101 /* Split at a multiply-accumulate instruction. However if this is
5102 the SET_SRC, we likely do not have such an instruction and it's
5103 worthless to try this split. */
5109 }
5111 /* Otherwise, select our actions depending on our rtx class. */
5113 {
5119 /* ... fall through ... */
5127 /* ... fall through ... */
5129 /* Some machines have (and (shift ...) ...) insns. If X is not
5130 an AND, but XEXP (X, 0) is, use it as our split point. */
5140 /* Otherwise, we don't have a split point. */
5142 }
5143 }
5144 \f
5145 /* Throughout X, replace FROM with TO, and return the result.
5146 The result is TO if X is FROM;
5147 otherwise the result is X, but its contents may have been modified.
5148 If they were modified, a record was made in undobuf so that
5149 undo_all will (among other things) return X to its original state.
5151 If the number of changes necessary is too much to record to undo,
5152 the excess changes are not made, so the result is invalid.
5153 The changes already made can still be undone.
5154 undobuf.num_undo is incremented for such changes, so by testing that
5155 the caller can tell whether the result is valid.
5157 `n_occurrences' is incremented each time FROM is replaced.
5159 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5161 IN_COND is nonzero if we are at the top level of a condition.
5163 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5164 by copying if `n_occurrences' is nonzero. */
5166 static rtx
5168 {
5173 rtx new_rtx;
5175 /* Two expressions are equal if they are identical copies of a shared
5176 RTX or if they are both registers with the same register number
5177 and mode. */
5179 #define COMBINE_RTX_EQUAL_P(X,Y) \
5180 ((X) == (Y) \
5181 || (REG_P (X) && REG_P (Y) \
5182 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5184 /* Do not substitute into clobbers of regs -- this will never result in
5185 valid RTL. */
5190 {
5191 n_occurrences++;
5193 }
5195 /* If X and FROM are the same register but different modes, they
5196 will not have been seen as equal above. However, the log links code
5197 will make a LOG_LINKS entry for that case. If we do nothing, we
5198 will try to rerecognize our original insn and, when it succeeds,
5199 we will delete the feeding insn, which is incorrect.
5201 So force this insn not to match in this (rare) case. */
5206 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5207 of which may contain things that can be combined. */
5211 /* It is possible to have a subexpression appear twice in the insn.
5212 Suppose that FROM is a register that appears within TO.
5213 Then, after that subexpression has been scanned once by `subst',
5214 the second time it is scanned, TO may be found. If we were
5215 to scan TO here, we would find FROM within it and create a
5216 self-referent rtl structure which is completely wrong. */
5220 /* Parallel asm_operands need special attention because all of the
5221 inputs are shared across the arms. Furthermore, unsharing the
5222 rtl results in recognition failures. Failure to handle this case
5223 specially can result in circular rtl.
5225 Solve this by doing a normal pass across the first entry of the
5226 parallel, and only processing the SET_DESTs of the subsequent
5227 entries. Ug. */
5232 {
5235 /* If this substitution failed, this whole thing fails. */
5243 {
5249 {
5252 /* If this substitution failed, this whole thing fails. */
5258 }
5259 }
5260 }
5261 else
5262 {
5266 /* We don't need to process a SET_DEST that is a register, CC0,
5267 or PC, so set up to skip this common case. All other cases
5268 where we want to suppress replacing something inside a
5269 SET_SRC are handled via the IN_DEST operand. */
5276 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5277 constant. */
5282 {
5284 {
5287 {
5289 {
5292 n_occurrences++;
5293 }
5294 else
5295 {
5297 unique_copy);
5299 /* If this substitution failed, this whole thing
5300 fails. */
5304 }
5307 }
5308 }
5310 {
5311 /* If this is a register being set, ignore it. */
5318 ;
5321 {
5322 /* In general, don't install a subreg involving two
5323 modes not tieable. It can worsen register
5324 allocation, and can even make invalid reload
5325 insns, since the reg inside may need to be copied
5326 from in the outside mode, and that may be invalid
5327 if it is an fp reg copied in integer mode.
5329 We allow two exceptions to this: It is valid if
5330 it is inside another SUBREG and the mode of that
5331 SUBREG and the mode of the inside of TO is
5332 tieable and it is valid if X is a SET that copies
5333 FROM to CC0. */
5341 #ifdef HAVE_cc0
5343 #endif
5344 )
5356 n_occurrences++;
5357 }
5358 else
5359 /* If we are in a SET_DEST, suppress most cases unless we
5360 have gone inside a MEM, in which case we want to
5361 simplify the address. We assume here that things that
5362 are actually part of the destination have their inner
5363 parts in the first expression. This is true for SUBREG,
5364 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5365 things aside from REG and MEM that should appear in a
5366 SET_DEST. */
5368 (((in_dest
5374 unique_copy);
5376 /* If we found that we will have to reject this combination,
5377 indicate that by returning the CLOBBER ourselves, rather than
5378 an expression containing it. This will speed things up as
5379 well as prevent accidents where two CLOBBERs are considered
5380 to be equal, thus producing an incorrect simplification. */
5386 {
5394 }
5397 {
5401 }
5402 else
5404 }
5405 }
5406 }
5408 /* Check if we are loading something from the constant pool via float
5409 extension; in this case we would undo compress_float_constant
5410 optimization and degenerate constant load to an immediate value. */
5414 {
5418 }
5420 /* Try to simplify X. If the simplification changed the code, it is likely
5421 that further simplification will help, so loop, but limit the number
5422 of repetitions that will be performed. */
5425 {
5426 /* If X is sufficiently simple, don't bother trying to do anything
5427 with it. */
5436 /* We no longer know the original mode of operand 0 since we
5437 have changed the form of X) */
5439 }
5442 }
5443 \f
5444 /* Simplify X, a piece of RTL. We just operate on the expression at the
5445 outer level; call `subst' to simplify recursively. Return the new
5446 expression.
5448 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5449 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5450 of a condition. */
5452 static rtx
5455 {
5458 rtx temp;
5461 /* If this is a commutative operation, put a constant last and a complex
5462 expression first. We don't need to do this for comparisons here. */
5465 {
5469 }
5471 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5472 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5473 things. Check for cases where both arms are testing the same
5474 condition.
5476 Don't do anything if all operands are very simple. */
5489 {
5494 /* If everything is a comparison, what we have is highly unlikely
5495 to be simpler, so don't use it. */
5498 {
5505 /* Simplify the alternative arms; this may collapse the true and
5506 false arms to store-flag values. Be careful to use copy_rtx
5507 here since true_rtx or false_rtx might share RTL with x as a
5508 result of the if_then_else_cond call above. */
5512 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5513 is unlikely to be simpler. */
5516 {
5519 /* Restarting if we generate a store-flag expression will cause
5520 us to loop. Just drop through in this case. */
5522 /* If the result values are STORE_FLAG_VALUE and zero, we can
5523 just make the comparison operation. */
5534 /* Likewise, we can make the negate of a comparison operation
5535 if the result values are - STORE_FLAG_VALUE and zero. */
5543 mode);
5554 mode);
5555 else
5558 mode,
5559 VOIDmode,
5560 cond,
5561 cop1),
5566 }
5567 }
5568 }
5570 /* Try to fold this expression in case we have constants that weren't
5571 present before. */
5574 {
5582 {
5585 {
5589 }
5592 }
5605 }
5608 {
5613 }
5615 /* First see if we can apply the inverse distributive law. */
5618 {
5622 }
5624 /* If CODE is an associative operation not otherwise handled, see if we
5625 can associate some operands. This can win if they are constants or
5626 if they are logically related (i.e. (a & b) & a). */
5632 {
5634 {
5638 rtx inner;
5640 /* Make sure we pass the constant operand if any as the second
5641 one if this is a commutative operation. */
5643 {
5647 }
5653 /* For commutative operations, try the other pair if that one
5654 didn't simplify. */
5656 {
5661 }
5665 }
5666 }
5668 /* A little bit of algebraic simplification here. */
5670 {
5672 /* Ensure that our address has any ASHIFTs converted to MULT in case
5673 address-recognizing predicates are called later. */
5682 /* See if this can be moved to simplify_subreg. */
5685 /* Don't call gen_lowpart if the inner mode
5686 is VOIDmode and we cannot simplify it, as SUBREG without
5687 inner mode is invalid. */
5694 {
5695 rtx temp;
5701 /* If op is known to have all lower bits zero, the result is zero. */
5711 }
5713 /* Don't change the mode of the MEM if that would change the meaning
5714 of the address. */
5721 /* Note that we cannot do any narrowing for non-constants since
5722 we might have been counting on using the fact that some bits were
5723 zero. We now do this in the SET. */
5730 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5731 replaced by (lshiftrt X C). This will convert
5732 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5740 /* If X has only a single bit that might be nonzero, say, bit I, convert
5741 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5742 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5743 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5744 or a SUBREG of one since we'd be making the expression more
5745 complex if it was just a register. */
5751 {
5752 rtx temp1 = simplify_shift_const
5758 /* If all we did was surround TEMP with the two shifts, we
5759 haven't improved anything, so don't use it. Otherwise,
5760 we are better off with TEMP1. */
5765 }
5769 /* We can't handle truncation to a partial integer mode here
5770 because we don't know the real bitsize of the partial
5771 integer mode. */
5780 /* We can truncate a constant value and return it. */
5784 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5785 whose value is a comparison can be replaced with a subreg if
5786 STORE_FLAG_VALUE permits. */
5795 /* (const (const X)) can become (const X). Do it this way rather than
5796 returning the inner CONST since CONST can be shared with a
5797 REG_EQUAL note. */
5802 #ifdef HAVE_lo_sum
5804 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5805 can add in an offset. find_split_point will split this address up
5806 again if it doesn't match. */
5811 #endif
5814 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5815 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5816 bit-field and can be replaced by either a sign_extend or a
5817 sign_extract. The `and' may be a zero_extend and the two
5818 <c>, -<c> constants may be reversed. */
5833 return simplify_shift_const
5840 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5841 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5842 the bitsize of the mode - 1. This allows simplification of
5843 "a = (b & 8) == 0;" */
5855 /* If we are adding two things that have no bits in common, convert
5856 the addition into an IOR. This will often be further simplified,
5857 for example in cases like ((a & 1) + (a & 2)), which can
5858 become a & 3. */
5863 {
5864 /* Try to simplify the expression further. */
5868 /* If we could, great. If not, do not go ahead with the IOR
5869 replacement, since PLUS appears in many special purpose
5870 address arithmetic instructions. */
5878 }
5882 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5883 (and <foo> (const_int pow2-1)) */
5893 /* If we have (mult (plus A B) C), apply the distributive law and then
5894 the inverse distributive law to see if things simplify. This
5895 occurs mostly in addresses, often when unrolling loops. */
5898 {
5902 }
5904 /* Try simplify a*(b/c) as (a*b)/c. */
5907 {
5913 }
5917 /* If this is a divide by a power of two, treat it as a shift if
5918 its first operand is a shift. */
5936 /* If the first operand is a condition code, we can't do anything
5937 with it. */
5941 {
5949 /* Simplify our comparison, if possible. */
5952 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5953 if only the low-order bit is possibly nonzero in X (such as when
5954 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5955 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5956 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5957 (plus X 1).
5959 Remove any ZERO_EXTRACT we made when thinking this was a
5960 comparison. It may now be simpler to use, e.g., an AND. If a
5961 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5962 the call to make_compound_operation in the SET case.
5964 Don't apply these optimizations if the caller would
5965 prefer a comparison rather than a value.
5966 E.g., for the condition in an IF_THEN_ELSE most targets need
5967 an explicit comparison. */
5970 ;
5986 {
5990 mode);
5991 }
5998 {
6002 const1_rtx);
6003 }
6011 {
6014 }
6016 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6017 those above. */
6019 ;
6035 {
6039 mode);
6040 }
6048 {
6052 mode);
6053 }
6055 /* If X is 0/1, (eq X 0) is X-1. */
6061 {
6064 }
6066 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6067 one bit that might be nonzero, we can convert (ne x 0) to
6068 (ashift x c) where C puts the bit in the sign bit. Remove any
6069 AND with STORE_FLAG_VALUE when we are done, since we are only
6070 going to test the sign bit. */
6077 {
6083 else
6085 }
6087 /* If the code changed, return a whole new comparison.
6088 We also need to avoid using SUBST in cases where
6089 simplify_comparison has widened a comparison with a CONST_INT,
6090 since in that case the wider CONST_INT may fail the sanity
6091 checks in do_SUBST. */
6098 /* Otherwise, keep this operation, but maybe change its operands.
6099 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6102 }
6112 /* If we are processing SET_DEST, we are done. */
6130 /* If this is a shift by a constant amount, simplify it. */
6146 }
6149 }
6150 \f
6151 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6153 static rtx
6155 {
6162 rtx temp;
6165 rtx reversed;
6167 /* Simplify storing of the truth value. */
6172 /* Also when the truth value has to be reversed. */
6178 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6179 in it is being compared against certain values. Get the true and false
6180 comparisons and see if that says anything about the value of each arm. */
6186 {
6187 HOST_WIDE_INT nzb;
6193 /* If FALSE_CODE is EQ, swap the codes and arms. */
6196 {
6199 }
6201 /* If we are comparing against zero and the expression being tested has
6202 only a single bit that might be nonzero, that is its value when it is
6203 not equal to zero. Similarly if it is known to be -1 or 0. */
6207 {
6210 }
6214 {
6217 }
6219 /* Now simplify an arm if we know the value of the register in the
6220 branch and it is used in the arm. Be careful due to the potential
6221 of locally-shared RTL. */
6238 }
6240 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6241 reversed, do so to avoid needing two sets of patterns for
6242 subtract-and-branch insns. Similarly if we have a constant in the true
6243 arm, the false arm is the same as the first operand of the comparison, or
6244 the false arm is more complicated than the true arm. */
6257 {
6266 /* It is possible that the conditional has been simplified out. */
6269 }
6271 /* If the two arms are identical, we don't need the comparison. */
6276 /* Convert a == b ? b : a to "a". */
6288 /* Look for cases where we have (abs x) or (neg (abs X)). */
6291 && comparison_p
6298 {
6304 return
6307 mode);
6310 }
6312 /* Look for MIN or MAX. */
6315 && comparison_p
6320 {
6335 }
6337 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6338 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6339 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6340 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6341 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6342 neither 1 or -1, but it isn't worth checking for. */
6345 && comparison_p
6348 {
6364 /* If an identity-zero op is commutative, check whether there
6365 would be a match if we swapped the operands. */
6385 {
6389 }
6401 {
6405 }
6421 {
6425 }
6437 {
6441 }
6444 {
6450 const_true_rtx));
6458 }
6459 }
6461 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6462 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6463 negation of a single bit, we can convert this operation to a shift. We
6464 can actually do this more generally, but it doesn't seem worth it. */
6473 return
6477 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6487 }
6488 \f
6489 /* Simplify X, a SET expression. Return the new expression. */
6491 static rtx
6493 {
6496 machine_mode mode
6501 /* (set (pc) (return)) gets written as (return). */
6505 /* Now that we know for sure which bits of SRC we are using, see if we can
6506 simplify the expression for the object knowing that we only need the
6507 low-order bits. */
6510 {
6513 }
6515 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6516 the comparison result and try to simplify it unless we already have used
6517 undobuf.other_insn. */
6525 {
6534 {
6537 {
6540 }
6541 }
6542 else
6550 {
6554 }
6555 else
6556 {
6561 /* Attempt to simplify CC user. */
6563 {
6567 }
6569 /* Convert X into a no-op move. */
6573 }
6575 /* Simplify our comparison, if possible. */
6578 #ifdef SELECT_CC_MODE
6579 /* If this machine has CC modes other than CCmode, check to see if we
6580 need to use a different CC mode here. */
6589 else
6592 #ifndef HAVE_cc0
6593 /* If the mode changed, we have to change SET_DEST, the mode in the
6594 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6595 a hard register, just build new versions with the proper mode. If it
6596 is a pseudo, we lose unless it is only time we set the pseudo, in
6597 which case we can safely change its mode. */
6599 {
6601 {
6603 rtx new_dest;
6607 else
6608 {
6611 }
6618 }
6619 }
6623 /* If the code changed, we have to build a new comparison in
6624 undobuf.other_insn. */
6626 {
6635 /* If the only change we made was to change an EQ into an NE or
6636 vice versa, OP0 has only one bit that might be nonzero, and OP1
6637 is zero, check if changing the user of the condition code will
6638 produce a valid insn. If it won't, we can keep the original code
6639 in that insn by surrounding our operation with an XOR. */
6646 {
6651 {
6658 }
6659 }
6660 }
6665 /* Otherwise, if we didn't previously have a COMPARE in the
6666 correct mode, we need one. */
6668 {
6671 }
6673 {
6676 }
6677 /* Otherwise, update the COMPARE if needed. */
6679 {
6682 }
6683 }
6684 else
6685 {
6686 /* Get SET_SRC in a form where we have placed back any
6687 compound expressions. Then do the checks below. */
6690 }
6692 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6693 and X being a REG or (subreg (reg)), we may be able to convert this to
6694 (set (subreg:m2 x) (op)).
6696 We can always do this if M1 is narrower than M2 because that means that
6697 we only care about the low bits of the result.
6699 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6700 perform a narrower operation than requested since the high-order bits will
6701 be undefined. On machine where it is defined, this transformation is safe
6702 as long as M1 and M2 have the same number of words. */
6710 #ifndef WORD_REGISTER_OPERATIONS
6713 #endif
6714 #ifdef CANNOT_CHANGE_MODE_CLASS
6719 #endif
6723 {
6726 dest));
6730 }
6732 #ifdef HAVE_cc0
6733 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6734 in SRC. */
6740 {
6744 /* Here we make sure that we don't have a sign bit on. */
6747 {
6750 }
6751 }
6752 #endif
6754 #ifdef LOAD_EXTEND_OP
6755 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6756 would require a paradoxical subreg. Replace the subreg with a
6757 zero_extend to avoid the reload that would otherwise be required. */
6765 {
6771 }
6772 #endif
6774 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6775 are comparing an item known to be 0 or -1 against 0, use a logical
6776 operation instead. Check for one of the arms being an IOR of the other
6777 arm with some value. We compute three terms to be IOR'ed together. In
6778 practice, at most two will be nonzero. Then we do the IOR's. */
6786 #ifdef HAVE_conditional_move
6788 #endif
6793 {
6819 false_rtx);
6825 term3));
6828 }
6830 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6831 whole thing fail. */
6836 else
6837 /* Convert this into a field assignment operation, if possible. */
6839 }
6840 \f
6841 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6842 result. */
6844 static rtx
6846 {
6852 {
6854 /* We can call simplify_and_const_int only if we don't lose
6855 any (sign) bits when converting INTVAL (op1) to
6856 "unsigned HOST_WIDE_INT". */
6860 {
6867 }
6869 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6870 apply the distributive law and then the inverse distributive
6871 law to see if things simplify. */
6873 {
6877 }
6879 {
6883 }
6887 /* If we have (ior (and A B) C), apply the distributive law and then
6888 the inverse distributive law to see if things simplify. */
6891 {
6895 }
6898 {
6902 }
6907 }
6910 }
6911 \f
6912 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6913 operations" because they can be replaced with two more basic operations.
6914 ZERO_EXTEND is also considered "compound" because it can be replaced with
6915 an AND operation, which is simpler, though only one operation.
6917 The function expand_compound_operation is called with an rtx expression
6918 and will convert it to the appropriate shifts and AND operations,
6919 simplifying at each stage.
6921 The function make_compound_operation is called to convert an expression
6922 consisting of shifts and ANDs into the equivalent compound expression.
6923 It is the inverse of this function, loosely speaking. */
6925 static rtx
6927 {
6931 rtx tem;
6934 {
6938 /* We can't necessarily use a const_int for a multiword mode;
6939 it depends on implicitly extending the value.
6940 Since we don't know the right way to extend it,
6941 we can't tell whether the implicit way is right.
6943 Even for a mode that is no wider than a const_int,
6944 we can't win, because we need to sign extend one of its bits through
6945 the rest of it, and we don't know which bit. */
6949 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6950 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6951 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6952 reloaded. If not for that, MEM's would very rarely be safe.
6954 Reject MODEs bigger than a word, because we might not be able
6955 to reference a two-register group starting with an arbitrary register
6956 (and currently gen_lowpart might crash for a SUBREG). */
6961 /* Reject MODEs that aren't scalar integers because turning vector
6962 or complex modes into shifts causes problems. */
6968 /* If the inner object has VOIDmode (the only way this can happen
6969 is if it is an ASM_OPERANDS), we can't do anything since we don't
6970 know how much masking to do. */
6979 /* ... fall through ... */
6982 /* If the operand is a CLOBBER, just return it. */
6991 /* Reject MODEs that aren't scalar integers because turning vector
6992 or complex modes into shifts causes problems. */
7000 /* This should stay within the object being extracted, fail otherwise. */
7011 }
7012 /* Convert sign extension to zero extension, if we know that the high
7013 bit is not set, as this is easier to optimize. It will be converted
7014 back to cheaper alternative in make_extraction. */
7022 {
7026 /* Make sure this is a profitable operation. */
7033 else
7035 }
7037 /* We can optimize some special cases of ZERO_EXTEND. */
7039 {
7040 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7041 know that the last value didn't have any inappropriate bits
7042 set. */
7050 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7059 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7060 is a comparison and STORE_FLAG_VALUE permits. This is like
7061 the first case, but it works even when GET_MODE (x) is larger
7062 than HOST_WIDE_INT. */
7071 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7081 }
7083 /* If we reach here, we want to return a pair of shifts. The inner
7084 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7085 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7086 logical depending on the value of UNSIGNEDP.
7088 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7089 converted into an AND of a shift.
7091 We must check for the case where the left shift would have a negative
7092 count. This can happen in a case like (x >> 31) & 255 on machines
7093 that can't shift by a constant. On those machines, we would first
7094 combine the shift with the AND to produce a variable-position
7095 extraction. Then the constant of 31 would be substituted in
7096 to produce such a position. */
7100 {
7109 }
7116 else
7117 /* Any other cases we can't handle. */
7120 /* If we couldn't do this for some reason, return the original
7121 expression. */
7126 }
7127 \f
7128 /* X is a SET which contains an assignment of one object into
7129 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7130 or certain SUBREGS). If possible, convert it into a series of
7131 logical operations.
7133 We half-heartedly support variable positions, but do not at all
7134 support variable lengths. */
7136 static const_rtx
7138 {
7139 rtx inner;
7143 machine_mode compute_mode;
7145 /* Loop until we find something we can't simplify. */
7147 {
7150 {
7154 }
7157 {
7162 /* A constant position should stay within the width of INNER. */
7168 {
7176 /* If position is ADJUST - X, new position is X. */
7178 else
7179 {
7184 pos);
7185 }
7186 }
7187 }
7189 /* A SUBREG between two modes that occupy the same numbers of words
7190 can be done by moving the SUBREG to the source. */
7192 /* We need SUBREGs to compute nonzero_bits properly. */
7193 && nonzero_sign_valid
7198 {
7200 gen_lowpart
7204 }
7205 else
7213 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7215 {
7216 machine_mode imode;
7218 /* Don't do anything for vector or complex integral types. */
7222 /* Try to find an integral mode to pun with. */
7229 }
7231 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7235 /* Now compute the equivalent expression. Make a copy of INNER
7236 for the SET_DEST in case it is a MEM into which we will substitute;
7237 we don't want shared RTL in that case. */
7239 compute_mode);
7243 compute_mode,
7245 compute_mode),
7246 inner);
7251 mask),
7252 pos);
7257 }
7260 }
7261 \f
7262 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7263 it is an RTX that represents the (variable) starting position; otherwise,
7264 POS is the (constant) starting bit position. Both are counted from the LSB.
7266 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7268 IN_DEST is nonzero if this is a reference in the destination of a SET.
7269 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7270 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7271 be used.
7273 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7274 ZERO_EXTRACT should be built even for bits starting at bit 0.
7276 MODE is the desired mode of the result (if IN_DEST == 0).
7278 The result is an RTX for the extraction or NULL_RTX if the target
7279 can't handle it. */
7281 static rtx
7285 {
7286 /* This mode describes the size of the storage area
7287 to fetch the overall value from. Within that, we
7288 ignore the POS lowest bits, etc. */
7290 machine_mode inner_mode;
7291 machine_mode wanted_inner_mode;
7298 HOST_WIDE_INT orig_pos;
7304 {
7305 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7306 consider just the QI as the memory to extract from.
7307 The subreg adds or removes high bits; its mode is
7308 irrelevant to the meaning of this extraction,
7309 since POS and LEN count from the lsb. */
7313 }
7318 {
7319 /* We're extracting the least significant bits of an rtx
7320 (ashift X (const_int C)), where LEN > C. Extract the
7321 least significant (LEN - C) bits of X, giving an rtx
7322 whose mode is MODE, then shift it left C times. */
7328 }
7334 /* See if this can be done without an extraction. We never can if the
7335 width of the field is not the same as that of some integer mode. For
7336 registers, we can only avoid the extraction if the position is at the
7337 low-order bit and this is either not in the destination or we have the
7338 appropriate STRICT_LOW_PART operation available.
7340 For MEM, we can avoid an extract if the field starts on an appropriate
7341 boundary and we can change the mode of the memory reference. */
7350 && (! in_dest
7354 && (pos
7357 /* We can't do this if we are widening INNER_MODE (it
7358 may not be aligned, for one thing). */
7364 {
7365 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7366 field. If the original and current mode are the same, we need not
7367 adjust the offset. Otherwise, we do if bytes big endian.
7369 If INNER is not a MEM, get a piece consisting of just the field
7370 of interest (in this case POS % BITS_PER_WORD must be 0). */
7373 {
7374 HOST_WIDE_INT offset;
7376 /* POS counts from lsb, but make OFFSET count in memory order. */
7379 else
7383 }
7385 {
7387 {
7388 /* We can't call gen_lowpart in a DEST since we
7389 always want a SUBREG (see below) and it would sometimes
7390 return a new hard register. */
7392 {
7407 /* Avoid creating invalid subregs, for example when
7408 simplifying (x>>32)&255. */
7413 }
7414 else
7416 }
7417 else
7419 }
7420 else
7422 len >= HOST_BITS_PER_WIDE_INT
7427 /* If this extraction is going into the destination of a SET,
7428 make a STRICT_LOW_PART unless we made a MEM. */
7443 /* If we know that no extraneous bits are set, and that the high
7444 bit is not set, convert the extraction to the cheaper of
7445 sign and zero extension, that are equivalent in these cases. */
7451 {
7455 /* Prefer ZERO_EXTENSION, since it gives more information to
7456 backends. */
7461 }
7463 /* Otherwise, sign- or zero-extend unless we already are in the
7464 proper mode. */
7468 }
7470 /* Unless this is a COMPARE or we have a funny memory reference,
7471 don't do anything with zero-extending field extracts starting at
7472 the low-order bit since they are simple AND operations. */
7477 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7478 if the position is not a constant and the length is not 1. In all
7479 other cases, we would only be going outside our object in cases when
7480 an original shift would have been undefined. */
7489 /* If INNER is not from memory, we want it to have the mode of a register
7490 extraction pattern's structure operand, or word_mode if there is no
7491 such pattern. The same applies to extraction_mode and pos_mode
7492 and their respective operands.
7494 For memory, assume that the desired extraction_mode and pos_mode
7495 are the same as for a register operation, since at present we don't
7496 have named patterns for aligned memory structures. */
7500 {
7504 }
7506 /* Never narrow an object, since that might not be safe. */
7514 else
7515 {
7516 /* Be careful not to go beyond the extracted object and maintain the
7517 natural alignment of the memory. */
7521 {
7524 }
7525 }
7530 {
7531 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7532 BITS_BIG_ENDIAN style. If position is constant, compute new
7533 position. Otherwise, build subtraction.
7534 Note that POS is relative to the mode of the original argument.
7535 If it's a MEM we need to recompute POS relative to that.
7536 However, if we're extracting from (or inserting into) a register,
7537 we want to recompute POS relative to wanted_inner_mode. */
7544 else
7545 pos_rtx
7548 pos_rtx);
7549 /* POS may be less than 0 now, but we check for that below.
7550 Note that it can only be less than 0 if !MEM_P (inner). */
7551 }
7553 /* If INNER has a wider mode, and this is a constant extraction, try to
7554 make it smaller and adjust the byte to point to the byte containing
7555 the value. */
7558 && ! pos_rtx
7563 {
7566 /* The computations below will be correct if the machine is big
7567 endian in both bits and bytes or little endian in bits and bytes.
7568 If it is mixed, we must adjust. */
7570 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7571 adjust OFFSET to compensate. */
7576 /* We can now move to the desired byte. */
7587 }
7589 /* If INNER is not memory, get it into the proper mode. If we are changing
7590 its mode, POS must be a constant and smaller than the size of the new
7591 mode. */
7593 {
7594 /* On the LHS, don't create paradoxical subregs implicitely truncating
7595 the register unless TRULY_NOOP_TRUNCATION. */
7598 wanted_inner_mode))
7610 pos_rtx
7616 }
7618 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7619 have to zero extend. Otherwise, we can just use a SUBREG. */
7622 {
7626 /* If we know that no extraneous bits are set, and that the high
7627 bit is not set, convert extraction to cheaper one - either
7628 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7629 cases. */
7637 {
7641 /* Prefer ZERO_EXTENSION, since it gives more information to
7642 backends. */
7646 }
7648 }
7650 /* Make POS_RTX unless we already have it and it is correct. If we don't
7651 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7652 be a CONST_INT. */
7659 /* Make the required operation. See if we can use existing rtx. */
7666 }
7667 \f
7668 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7669 with any other operations in X. Return X without that shift if so. */
7671 static rtx
7673 {
7676 rtx tem;
7679 {
7681 /* This is the shift itself. If it is wide enough, we will return
7682 either the value being shifted if the shift count is equal to
7683 COUNT or a shift for the difference. */
7697 /* If we can safely shift this constant and we find the inner shift,
7698 make a new operation. */
7703 {
7707 }
7712 }
7715 }
7716 \f
7717 /* Look at the expression rooted at X. Look for expressions
7718 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7719 Form these expressions.
7721 Return the new rtx, usually just X.
7723 Also, for machines like the VAX that don't have logical shift insns,
7724 try to convert logical to arithmetic shift operations in cases where
7725 they are equivalent. This undoes the canonicalizations to logical
7726 shifts done elsewhere.
7728 We try, as much as possible, to re-use rtl expressions to save memory.
7730 IN_CODE says what kind of expression we are processing. Normally, it is
7731 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7732 being kludges), it is MEM. When processing the arguments of a comparison
7733 or a COMPARE against zero, it is COMPARE. */
7735 rtx
7737 {
7745 rtx tem;
7748 /* Select the code to be used in recursive calls. Once we are inside an
7749 address, we stay there. If we have a comparison, set to COMPARE,
7750 but once inside, go back to our default of SET. */
7759 /* Process depending on the code of this operation. If NEW is set
7760 nonzero, it will be returned. */
7763 {
7765 /* Convert shifts by constants into multiplications if inside
7766 an address. */
7771 {
7777 {
7780 }
7783 }
7793 {
7797 }
7800 {
7804 mode));
7806 }
7807 else
7808 {
7812 }
7823 {
7827 }
7830 {
7834 mode));
7836 }
7837 else
7838 {
7842 }
7846 /* If the second operand is not a constant, we can't do anything
7847 with it. */
7851 /* If the constant is a power of two minus one and the first operand
7852 is a logical right shift, make an extraction. */
7855 {
7859 }
7861 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7866 {
7868 next_code);
7872 }
7873 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7879 {
7880 /* Apply the distributive law, and then try to make extractions. */
7887 }
7889 /* If we are have (and (rotate X C) M) and C is larger than the number
7890 of bits in M, this is an extraction. */
7896 {
7902 }
7904 /* On machines without logical shifts, if the operand of the AND is
7905 a logical shift and our mask turns off all the propagated sign
7906 bits, we can replace the logical shift with an arithmetic shift. */
7914 {
7921 make_compound_operation
7924 }
7926 /* If the constant is one less than a power of two, this might be
7927 representable by an extraction even if no shift is present.
7928 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7929 we are in a COMPARE. */
7933 next_code),
7936 /* If we are in a comparison and this is an AND with a power of two,
7937 convert this into the appropriate bit extract. */
7942 next_code),
7948 /* If the sign bit is known to be zero, replace this with an
7949 arithmetic shift. */
7954 {
7957 next_code),
7960 }
7962 /* ... fall through ... */
7968 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7969 this is a SIGN_EXTRACT. */
7976 {
7983 }
7985 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7986 If so, try to merge the shifts into a SIGN_EXTEND. We could
7987 also do this for some cases of SIGN_EXTRACT, but it doesn't
7988 seem worth the effort; the case checked for occurs on Alpha. */
8004 /* Call ourselves recursively on the inner expression. If we are
8005 narrowing the object and it has a different RTL code from
8006 what it originally did, do this SUBREG as a force_to_mode. */
8007 {
8011 /* If in_code is COMPARE, it isn't always safe to pass it through
8012 to the recursive make_compound_operation call. */
8016 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8017 is (const_int 0), rather than
8018 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8028 simplified
8036 {
8037 rtx newer
8040 /* If we have something other than a SUBREG, we might have
8041 done an expansion, so rerun ourselves. */
8045 /* force_to_mode can expand compounds. If it just re-expanded the
8046 compound, use gen_lowpart to convert to the desired mode. */
8048 /* Likewise if it re-expanded the compound only partially.
8049 This happens for SUBREG of ZERO_EXTRACT if they extract
8050 the same number of bits. */
8059 }
8063 }
8068 }
8071 {
8074 }
8076 /* Now recursively process each operand of this operation. We need to
8077 handle ZERO_EXTEND specially so that we don't lose track of the
8078 inner mode. */
8080 {
8088 }
8093 {
8096 }
8099 {
8102 }
8104 maybe_swap:
8105 /* If this is a commutative operation, the changes to the operands
8106 may have made it noncanonical. */
8109 {
8113 }
8116 }
8117 \f
8118 /* Given M see if it is a value that would select a field of bits
8119 within an item, but not the entire word. Return -1 if not.
8120 Otherwise, return the starting position of the field, where 0 is the
8121 low-order bit.
8123 *PLEN is set to the length of the field. */
8125 static int
8127 {
8128 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8133 /* Now shift off the low-order zero bits and see if we have a
8134 power of two minus 1. */
8142 }
8143 \f
8144 /* If X refers to a register that equals REG in value, replace these
8145 references with REG. */
8146 static rtx
8148 {
8156 {
8192 {
8196 else
8198 }
8200 /* fall through */
8207 {
8210 {
8212 {
8215 }
8217 }
8218 }
8220 {
8223 {
8226 {
8228 {
8231 }
8233 }
8234 }
8235 }
8238 }
8241 }
8243 /* Return X converted to MODE. If the value is already truncated to
8244 MODE we can just return a subreg even though in the general case we
8245 would need an explicit truncation. */
8247 static rtx
8249 {
8254 {
8255 /* Bit-cast X into an integer mode. */
8260 }
8263 }
8265 /* See if X can be simplified knowing that we will only refer to it in
8266 MODE and will only refer to those bits that are nonzero in MASK.
8267 If other bits are being computed or if masking operations are done
8268 that select a superset of the bits in MASK, they can sometimes be
8269 ignored.
8271 Return a possibly simplified expression, but always convert X to
8272 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8274 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8275 are all off in X. This is used when X will be complemented, by either
8276 NOT, NEG, or XOR. */
8278 static rtx
8281 {
8284 machine_mode op_mode;
8288 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8289 code below will do the wrong thing since the mode of such an
8290 expression is VOIDmode.
8292 Also do nothing if X is a CLOBBER; this can happen if X was
8293 the return value from a call to gen_lowpart. */
8297 /* We want to perform the operation in its present mode unless we know
8298 that the operation is valid in MODE, in which case we do the operation
8299 in MODE. */
8304 /* It is not valid to do a right-shift in a narrower mode
8305 than the one it came in with. */
8310 /* Truncate MASK to fit OP_MODE. */
8314 /* When we have an arithmetic operation, or a shift whose count we
8315 do not know, we need to assume that all bits up to the highest-order
8316 bit in MASK will be needed. This is how we form such a mask. */
8319 else
8323 /* Determine what bits of X are guaranteed to be (non)zero. */
8326 /* If none of the bits in X are needed, return a zero. */
8330 /* If X is a CONST_INT, return a new one. Do this here since the
8331 test below will fail. */
8333 {
8336 else
8337 {
8340 }
8341 }
8343 /* If X is narrower than MODE and we want all the bits in X's mode, just
8344 get X in the proper mode. */
8349 /* We can ignore the effect of a SUBREG if it narrows the mode or
8350 if the constant masks to zero all the bits the mode doesn't have. */
8360 /* The arithmetic simplifications here only work for scalar integer modes. */
8365 {
8367 /* If X is a (clobber (const_int)), return it since we know we are
8368 generating something that won't match. */
8381 /* Similarly for a truncate. */
8385 /* If this is an AND with a constant, convert it into an AND
8386 whose constant is the AND of that constant with MASK. If it
8387 remains an AND of MASK, delete it since it is redundant. */
8390 {
8394 /* If X is still an AND, see if it is an AND with a mask that
8395 is just some low-order bits. If so, and it is MASK, we don't
8396 need it. */
8403 /* If it remains an AND, try making another AND with the bits
8404 in the mode mask that aren't in MASK turned on. If the
8405 constant in the AND is wide enough, this might make a
8406 cheaper constant. */
8411 {
8412 unsigned HOST_WIDE_INT cval
8415 rtx y;
8422 }
8425 }
8430 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8431 low-order bits (as in an alignment operation) and FOO is already
8432 aligned to that boundary, mask C1 to that boundary as well.
8433 This may eliminate that PLUS and, later, the AND. */
8435 {
8439 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8440 number, sign extend it. */
8453 }
8455 /* ... fall through ... */
8458 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8459 most significant bit in MASK since carries from those bits will
8460 affect the bits we are interested in. */
8465 /* If X is (minus C Y) where C's least set bit is larger than any bit
8466 in the mask, then we may replace with (neg Y). */
8469 {
8473 }
8475 /* Similarly, if C contains every bit in the fuller_mask, then we may
8476 replace with (not Y). */
8479 {
8483 }
8490 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8491 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8492 operation which may be a bitfield extraction. Ensure that the
8493 constant we form is not wider than the mode of X. */
8505 {
8514 }
8516 binop:
8517 /* For most binary operations, just propagate into the operation and
8518 change the mode if we have an operation of that mode. */
8523 /* If we ended up truncating both operands, truncate the result of the
8524 operation instead. */
8527 {
8530 }
8540 /* For left shifts, do the same, but just for the first operand.
8541 However, we cannot do anything with shifts where we cannot
8542 guarantee that the counts are smaller than the size of the mode
8543 because such a count will have a different meaning in a
8544 wider mode. */
8554 /* If the shift count is a constant and we can do arithmetic in
8555 the mode of the shift, refine which bits we need. Otherwise, use the
8556 conservative form of the mask. */
8562 else
8574 /* Here we can only do something if the shift count is a constant,
8575 this shift constant is valid for the host, and we can do arithmetic
8576 in OP_MODE. */
8582 {
8586 /* Select the mask of the bits we need for the shift operand. */
8589 /* We can only change the mode of the shift if we can do arithmetic
8590 in the mode of the shift and INNER_MASK is no wider than the
8591 width of X's mode. */
8599 }
8601 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8602 shift and AND produces only copies of the sign bit (C2 is one less
8603 than a power of two), we can do this with just a shift. */
8607 /* The shift puts one of the sign bit copies in the least significant
8608 bit. */
8613 /* Number of bits left after the shift must be more than the mask
8614 needs. */
8617 /* Must be more sign bit copies than the mask needs. */
8627 /* If we are just looking for the sign bit, we don't need this shift at
8628 all, even if it has a variable count. */
8632 /* If this is a shift by a constant, get a mask that contains those bits
8633 that are not copies of the sign bit. We then have two cases: If
8634 MASK only includes those bits, this can be a logical shift, which may
8635 allow simplifications. If MASK is a single-bit field not within
8636 those bits, we are requesting a copy of the sign bit and hence can
8637 shift the sign bit to the appropriate location. */
8641 {
8644 /* If the considered data is wider than HOST_WIDE_INT, we can't
8645 represent a mask for all its bits in a single scalar.
8646 But we only care about the lower bits, so calculate these. */
8649 {
8652 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8653 is the number of bits a full-width mask would have set.
8654 We need only shift if these are fewer than nonzero can
8655 hold. If not, we must keep all bits set in nonzero. */
8660 + HOST_BITS_PER_WIDE_INT
8662 }
8663 else
8664 {
8667 }
8670 {
8675 }
8678 {
8679 x = simplify_shift_const
8685 }
8686 }
8688 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8689 even if the shift count isn't a constant. */
8694 shiftrt:
8696 /* If this is a zero- or sign-extension operation that just affects bits
8697 we don't care about, remove it. Be sure the call above returned
8698 something that is still a shift. */
8708 next_select);
8714 /* If the shift count is constant and we can do computations
8715 in the mode of X, compute where the bits we care about are.
8716 Otherwise, we can't do anything. Don't change the mode of
8717 the shift or propagate MODE into the shift, though. */
8720 {
8730 }
8734 /* If we just want the low-order bit, the NEG isn't needed since it
8735 won't change the low-order bit. */
8739 /* We need any bits less significant than the most significant bit in
8740 MASK since carries from those bits will affect the bits we are
8741 interested in. */
8746 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8747 same as the XOR case above. Ensure that the constant we form is not
8748 wider than the mode of X. */
8756 {
8765 }
8767 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8768 use the full mask inside the NOT. */
8771 unop:
8774 next_select));
8780 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8781 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8782 which is equal to STORE_FLAG_VALUE. */
8794 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8795 written in a narrower mode. We play it safe and do not do so. */
8811 }
8813 /* Ensure we return a value of the proper mode. */
8815 }
8816 \f
8817 /* Return nonzero if X is an expression that has one of two values depending on
8818 whether some other value is zero or nonzero. In that case, we return the
8819 value that is being tested, *PTRUE is set to the value if the rtx being
8820 returned has a nonzero value, and *PFALSE is set to the other alternative.
8822 If we return zero, we set *PTRUE and *PFALSE to X. */
8824 static rtx
8826 {
8832 /* If we are comparing a value against zero, we are done. */
8835 {
8839 }
8841 /* If this is a unary operation whose operand has one of two values, apply
8842 our opcode to compute those values. */
8845 {
8850 }
8852 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8853 make can't possibly match and would suppress other optimizations. */
8855 ;
8857 /* If this is a binary operation, see if either side has only one of two
8858 values. If either one does or if both do and they are conditional on
8859 the same value, compute the new true and false values. */
8861 {
8867 {
8868 /* If if_then_else_cond returned zero, then true/false are the
8869 same rtl. We must copy one of them to prevent invalid rtl
8870 sharing. */
8877 {
8882 }
8883 else
8884 {
8887 }
8890 }
8892 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8893 operands is zero when the other is nonzero, and vice-versa,
8894 and STORE_FLAG_VALUE is 1 or -1. */
8900 {
8917 {
8924 const_true_rtx);
8926 }
8927 }
8929 /* Similarly for MULT, AND and UMIN, except that for these the result
8930 is always zero. */
8934 {
8948 {
8951 }
8952 }
8953 }
8956 {
8957 /* If we have IF_THEN_ELSE already, extract the condition and
8958 canonicalize it if it is NE or EQ. */
8964 {
8967 }
8968 else
8970 }
8972 /* If X is a SUBREG, we can narrow both the true and false values
8973 if the inner expression, if there is a condition. */
8977 {
8983 {
8987 }
8988 }
8990 /* If X is a constant, this isn't special and will cause confusions
8991 if we treat it as such. Likewise if it is equivalent to a constant. */
8994 ;
8996 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8997 will be least confusing to the rest of the compiler. */
8999 {
9002 }
9004 /* If X is known to be either 0 or -1, those are the true and
9005 false values when testing X. */
9009 {
9012 }
9014 /* Likewise for 0 or a single bit. */
9017 {
9020 }
9022 /* Otherwise fail; show no condition with true and false values the same. */
9025 }
9026 \f
9027 /* Return the value of expression X given the fact that condition COND
9028 is known to be true when applied to REG as its first operand and VAL
9029 as its second. X is known to not be shared and so can be modified in
9030 place.
9032 We only handle the simplest cases, and specifically those cases that
9033 arise with IF_THEN_ELSE expressions. */
9035 static rtx
9037 {
9039 rtx temp;
9046 /* If either operand of the condition is a floating point value,
9047 then we have to avoid collapsing an EQ comparison. */
9057 /* If X is (abs REG) and we know something about REG's relationship
9058 with zero, we may be able to simplify this. */
9062 {
9071 }
9073 /* The only other cases we handle are MIN, MAX, and comparisons if the
9074 operands are the same as REG and VAL. */
9077 {
9082 {
9084 {
9092 else
9094 }
9097 {
9100 /* Do not reverse the condition when it is NE or EQ.
9101 This is because we cannot conclude anything about
9102 the value of 'SMAX (x, y)' when x is not equal to y,
9103 but we can when x equals y. */
9109 {
9120 }
9121 }
9122 }
9123 }
9125 {
9130 {
9131 /* We must simplify subreg here, before we lose track of the
9132 original inner_mode. */
9137 else
9139 }
9142 }
9143 /* We don't have to handle SIGN_EXTEND here, because even in the
9144 case of replacing something with a modeless CONST_INT, a
9145 CONST_INT is already (supposed to be) a valid sign extension for
9146 its narrower mode, which implies it's already properly
9147 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9148 story is different. */
9150 {
9155 {
9156 /* We must simplify the zero_extend here, before we lose
9157 track of the original inner_mode. */
9162 else
9164 }
9167 }
9171 {
9178 }
9181 }
9182 \f
9183 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9184 assignment as a field assignment. */
9186 static int
9188 {
9190 {
9195 /* For big endian, adjust the memory offset. */
9200 else
9202 }
9210 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9211 Note that all SUBREGs of MEM are paradoxical; otherwise they
9212 would have been rewritten. */
9225 /* We used to see if get_last_value of X and Y were the same but that's
9226 not correct. In one direction, we'll cause the assignment to have
9227 the wrong destination and in the case, we'll import a register into this
9228 insn that might have already have been dead. So fail if none of the
9229 above cases are true. */
9231 }
9232 \f
9233 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9234 Return that assignment if so.
9236 We only handle the most common cases. */
9238 static rtx
9240 {
9243 rtx assign;
9245 HOST_WIDE_INT c1;
9246 HOST_WIDE_INT pos;
9248 rtx other;
9249 machine_mode mode;
9251 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9252 a clear of a one-bit field. We will have changed it to
9253 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9254 for a SUBREG. */
9260 {
9266 }
9276 {
9283 }
9285 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9286 one-bit field. */
9290 {
9296 }
9298 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9299 SRC is an AND with all bits of that field set, then we can discard
9300 the AND. */
9305 {
9312 else
9315 /* Complete overlap. We can remove the source AND. */
9319 /* Partial overlap. We can reduce the source AND. */
9321 {
9326 }
9327 }
9329 /* The other case we handle is assignments into a constant-position
9330 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9331 a mask that has all one bits except for a group of zero bits and
9332 OTHER is known to have zeros where C1 has ones, this is such an
9333 assignment. Compute the position and length from C1. Shift OTHER
9334 to the appropriate position, force it to the required mode, and
9335 make the extraction. Check for the AND in both operands. */
9337 /* One or more SUBREGs might obscure the constant-position field
9338 assignment. The first one we are likely to encounter is an outer
9339 narrowing SUBREG, which we can just strip for the purposes of
9340 identifying the constant-field assignment. */
9354 /* The second SUBREG that might get in the way is a paradoxical
9355 SUBREG around the first operand of the AND. We want to
9356 pretend the operand is as wide as the destination here. We
9357 do this by adjusting the MEM to wider mode for the sole
9358 purpose of the call to rtx_equal_for_field_assignment_p. Also
9359 note this trick only works for MEMs. */
9371 /* The second SUBREG that might get in the way is a paradoxical
9372 SUBREG around the first operand of the AND. We want to
9373 pretend the operand is as wide as the destination here. We
9374 do this by adjusting the MEM to wider mode for the sole
9375 purpose of the call to rtx_equal_for_field_assignment_p. Also
9376 note this trick only works for MEMs. */
9384 else
9397 /* The mode to use for the source is the mode of the assignment, or of
9398 what is inside a possible STRICT_LOW_PART. */
9402 /* Shift OTHER right POS places and make it the source, restricting it
9403 to the proper length and mode. */
9408 dest);
9415 /* If SRC is masked by an AND that does not make a difference in
9416 the value being stored, strip it. */
9427 }
9428 \f
9429 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9430 if so. */
9432 static rtx
9434 {
9438 rtx tem;
9440 /* Distributivity is not true for floating point as it can change the
9441 value. So we don't do it unless -funsafe-math-optimizations. */
9446 /* The outer operation can only be one of the following: */
9454 /* If either operand is a primitive we can't do anything, so get out
9455 fast. */
9465 /* See if the inner and outer operations distribute. */
9467 {
9472 /* These all distribute except over PLUS. */
9483 /* This is also a multiply, so it distributes over everything. */
9486 /* This used to handle SUBREG, but this turned out to be counter-
9487 productive, since (subreg (op ...)) usually is not handled by
9488 insn patterns, and this "optimization" therefore transformed
9489 recognizable patterns into unrecognizable ones. Therefore the
9490 SUBREG case was removed from here.
9492 It is possible that distributing SUBREG over arithmetic operations
9493 leads to an intermediate result than can then be optimized further,
9494 e.g. by moving the outer SUBREG to the other side of a SET as done
9495 in simplify_set. This seems to have been the original intent of
9496 handling SUBREGs here.
9498 However, with current GCC this does not appear to actually happen,
9499 at least on major platforms. If some case is found where removing
9500 the SUBREG case here prevents follow-on optimizations, distributing
9501 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9505 }
9507 /* Set LHS and RHS to the inner operands (A and B in the example
9508 above) and set OTHER to the common operand (C in the example).
9509 There is only one way to do this unless the inner operation is
9510 commutative. */
9522 else
9525 /* Form the new inner operation, seeing if it simplifies first. */
9528 /* There is one exception to the general way of distributing:
9529 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9531 {
9534 }
9536 /* We may be able to continuing distributing the result, so call
9537 ourselves recursively on the inner operation before forming the
9538 outer operation, which we return. */
9541 }
9543 /* See if X is of the form (* (+ A B) C), and if so convert to
9544 (+ (* A C) (* B C)) and try to simplify.
9546 Most of the time, this results in no change. However, if some of
9547 the operands are the same or inverses of each other, simplifications
9548 will result.
9550 For example, (and (ior A B) (not B)) can occur as the result of
9551 expanding a bit field assignment. When we apply the distributive
9552 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9553 which then simplifies to (and (A (not B))).
9555 Note that no checks happen on the validity of applying the inverse
9556 distributive law. This is pointless since we can do it in the
9557 few places where this routine is called.
9559 N is the index of the term that is decomposed (the arithmetic operation,
9560 i.e. (+ A B) in the first example above). !N is the index of the term that
9561 is distributed, i.e. of C in the first example above. */
9562 static rtx
9564 {
9565 machine_mode mode;
9569 /* Distributivity is not true for floating point as it can change the
9570 value. So we don't do it unless -funsafe-math-optimizations. */
9587 /* Special case (and (xor B C) (not A)), which is equivalent to
9588 (xor (ior A B) (ior A C)) */
9590 {
9593 }
9596 {
9597 /* Distribute the second term. */
9600 }
9601 else
9602 {
9603 /* Distribute the first term. */
9606 }
9616 }
9617 \f
9618 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9619 in MODE. Return an equivalent form, if different from (and VAROP
9620 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9622 static rtx
9625 {
9628 rtx orig_varop;
9636 /* Simplify VAROP knowing that we will be only looking at some of the
9637 bits in it.
9639 Note by passing in CONSTOP, we guarantee that the bits not set in
9640 CONSTOP are not significant and will never be examined. We must
9641 ensure that is the case by explicitly masking out those bits
9642 before returning. */
9645 /* If VAROP is a CLOBBER, we will fail so return it. */
9649 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9650 to VAROP and return the new constant. */
9654 /* See what bits may be nonzero in VAROP. Unlike the general case of
9655 a call to nonzero_bits, here we don't care about bits outside
9656 MODE. */
9660 /* Turn off all bits in the constant that are known to already be zero.
9661 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9662 which is tested below. */
9666 /* If we don't have any bits left, return zero. */
9670 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9671 a power of two, we can replace this with an ASHIFT. */
9676 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9677 or XOR, then try to apply the distributive law. This may eliminate
9678 operations if either branch can be simplified because of the AND.
9679 It may also make some cases more complex, but those cases probably
9680 won't match a pattern either with or without this. */
9683 return
9684 gen_lowpart
9686 apply_distributive_law
9691 constop),
9695 constop))));
9697 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9698 the AND and see if one of the operands simplifies to zero. If so, we
9699 may eliminate it. */
9703 {
9712 }
9714 /* Make a SUBREG if necessary. If we can't make it, fail. */
9719 /* If we are only masking insignificant bits, return VAROP. */
9726 /* Otherwise, return an AND. */
9728 }
9731 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9732 in MODE.
9734 Return an equivalent form, if different from X. Otherwise, return X. If
9735 X is zero, we are to always construct the equivalent form. */
9737 static rtx
9740 {
9751 }
9752 \f
9753 /* Given a REG, X, compute which bits in X can be nonzero.
9754 We don't care about bits outside of those defined in MODE.
9756 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9757 a shift, AND, or zero_extract, we can do better. */
9759 static rtx
9761 const_rtx known_x ATTRIBUTE_UNUSED,
9762 machine_mode known_mode ATTRIBUTE_UNUSED,
9765 {
9766 rtx tem;
9769 /* If X is a register whose nonzero bits value is current, use it.
9770 Otherwise, if X is a register whose value we can find, use that
9771 value. Otherwise, use the previously-computed global nonzero bits
9772 for this register. */
9786 && !REGNO_REG_SET_P
9789 {
9793 /* We don't know anything about the upper bits. */
9798 }
9803 {
9804 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9805 /* If X is narrower than MODE and TEM is a non-negative
9806 constant that would appear negative in the mode of X,
9807 sign-extend it for use in reg_nonzero_bits because some
9808 machines (maybe most) will actually do the sign-extension
9809 and this is the conservative approach.
9811 ??? For 2.5, try to tighten up the MD files in this regard
9812 instead of this kludge. */
9819 #endif
9821 }
9823 {
9827 /* We don't know anything about the upper bits. */
9831 }
9834 }
9836 /* Return the number of bits at the high-order end of X that are known to
9837 be equal to the sign bit. X will be used in mode MODE; if MODE is
9838 VOIDmode, X will be used in its own mode. The returned value will always
9839 be between 1 and the number of bits in MODE. */
9841 static rtx
9843 const_rtx known_x ATTRIBUTE_UNUSED,
9844 machine_mode known_mode
9845 ATTRIBUTE_UNUSED,
9848 {
9849 rtx tem;
9862 && !REGNO_REG_SET_P
9865 {
9868 }
9879 }
9880 \f
9881 /* Return the number of "extended" bits there are in X, when interpreted
9882 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9883 unsigned quantities, this is the number of high-order zero bits.
9884 For signed quantities, this is the number of copies of the sign bit
9885 minus 1. In both case, this function returns the number of "spare"
9886 bits. For example, if two quantities for which this function returns
9887 at least 1 are added, the addition is known not to overflow.
9889 This function will always return 0 unless called during combine, which
9890 implies that it must be called from a define_split. */
9892 unsigned int
9894 {
9904 }
9906 /* This function is called from `simplify_shift_const' to merge two
9907 outer operations. Specifically, we have already found that we need
9908 to perform operation *POP0 with constant *PCONST0 at the outermost
9909 position. We would now like to also perform OP1 with constant CONST1
9910 (with *POP0 being done last).
9912 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9913 the resulting operation. *PCOMP_P is set to 1 if we would need to
9914 complement the innermost operand, otherwise it is unchanged.
9916 MODE is the mode in which the operation will be done. No bits outside
9917 the width of this mode matter. It is assumed that the width of this mode
9918 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9920 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9921 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9922 result is simply *PCONST0.
9924 If the resulting operation cannot be expressed as one operation, we
9925 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9927 static int
9928 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
9929 {
9936 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9940 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9941 if OP0 is SET. */
9950 {
9952 {
9970 }
9971 }
9973 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9977 /* If the two constants aren't the same, we can't do anything. The
9978 remaining six cases can all be done. */
9982 else
9984 {
9987 /* (a & b) | b == b */
9990 /* (a ^ b) | b == a | b */
9991 {;}
9996 /* (a & b) ^ b == (~a) & b */
9999 /* (a | b) ^ b == a & ~b */
10005 /* (a | b) & b == b */
10008 /* (a ^ b) & b) == (~a) & b */
10013 }
10015 /* Check for NO-OP cases. */
10028 /* ??? Slightly redundant with the above mask, but not entirely.
10029 Moving this above means we'd have to sign-extend the mode mask
10030 for the final test. */
10035 }
10036 \f
10037 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10038 the shift in. The original shift operation CODE is performed on OP in
10039 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10040 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10041 result of the shift is subject to operation OUTER_CODE with operand
10042 OUTER_CONST. */
10044 static machine_mode
10048 {
10053 /* In general we can't perform in wider mode for right shift and rotate. */
10055 {
10057 /* We can still widen if the bits brought in from the left are identical
10058 to the sign bit of ORIG_MODE. */
10066 /* Similarly here but with zero bits. */
10071 /* We can also widen if the bits brought in will be masked off. This
10072 operation is performed in ORIG_MODE. */
10074 {
10080 }
10081 /* fall through */
10091 }
10092 }
10094 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10095 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10096 if we cannot simplify it. Otherwise, return a simplified value.
10098 The shift is normally computed in the widest mode we find in VAROP, as
10099 long as it isn't a different number of words than RESULT_MODE. Exceptions
10100 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10102 static rtx
10105 {
10111 unsigned int mode_words
10113 /* We form (outer_op (code varop count) (outer_const)). */
10119 /* Make sure and truncate the "natural" shift on the way in. We don't
10120 want to do this inside the loop as it makes it more difficult to
10121 combine shifts. */
10125 /* If we were given an invalid count, don't do anything except exactly
10126 what was requested. */
10133 /* Unless one of the branches of the `if' in this loop does a `continue',
10134 we will `break' the loop after the `if'. */
10137 {
10138 /* If we have an operand of (clobber (const_int 0)), fail. */
10142 /* Convert ROTATERT to ROTATE. */
10144 {
10149 else
10151 }
10156 /* Handle cases where the count is greater than the size of the mode
10157 minus 1. For ASHIFT, use the size minus one as the count (this can
10158 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10159 take the count modulo the size. For other shifts, the result is
10160 zero.
10162 Since these shifts are being produced by the compiler by combining
10163 multiple operations, each of which are defined, we know what the
10164 result is supposed to be. */
10167 {
10172 else
10173 {
10174 /* We can't simply return zero because there may be an
10175 outer op. */
10179 }
10180 }
10182 /* If we discovered we had to complement VAROP, leave. Making a NOT
10183 here would cause an infinite loop. */
10187 /* An arithmetic right shift of a quantity known to be -1 or 0
10188 is a no-op. */
10192 {
10195 }
10197 /* If we are doing an arithmetic right shift and discarding all but
10198 the sign bit copies, this is equivalent to doing a shift by the
10199 bitsize minus one. Convert it into that shift because it will often
10200 allow other simplifications. */
10207 /* We simplify the tests below and elsewhere by converting
10208 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10209 `make_compound_operation' will convert it to an ASHIFTRT for
10210 those machines (such as VAX) that don't have an LSHIFTRT. */
10227 {
10234 {
10237 }
10241 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10242 minus the width of a smaller mode, we can do this with a
10243 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10250 {
10259 }
10263 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10264 the same number of words as what we've seen so far. Then store
10265 the widest mode in MODE. */
10271 == mode_words
10274 {
10279 }
10283 /* Some machines use MULT instead of ASHIFT because MULT
10284 is cheaper. But it is still better on those machines to
10285 merge two shifts into one. */
10288 {
10289 varop
10295 }
10299 /* Similar, for when divides are cheaper. */
10302 {
10303 varop
10309 }
10313 /* If we are extracting just the sign bit of an arithmetic
10314 right shift, that shift is not needed. However, the sign
10315 bit of a wider mode may be different from what would be
10316 interpreted as the sign bit in a narrower mode, so, if
10317 the result is narrower, don't discard the shift. */
10322 {
10325 }
10327 /* ... fall through ... */
10332 /* Here we have two nested shifts. The result is usually the
10333 AND of a new shift with a mask. We compute the result below. */
10340 {
10344 rtx mask_rtx;
10346 /* We have one common special case. We can't do any merging if
10347 the inner code is an ASHIFTRT of a smaller mode. However, if
10348 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10349 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10350 we can convert it to
10351 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10352 This simplifies certain SIGN_EXTEND operations. */
10356 {
10357 /* C3 has the low-order C1 bits zero. */
10369 }
10371 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10372 than C1 high-order bits equal to the sign bit, we can convert
10373 this to either an ASHIFT or an ASHIFTRT depending on the
10374 two counts.
10376 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10382 {
10386 {
10389 }
10392 }
10394 /* There are some cases we can't do. If CODE is ASHIFTRT,
10395 we can only do this if FIRST_CODE is also ASHIFTRT.
10397 We can't do the case when CODE is ROTATE and FIRST_CODE is
10398 ASHIFTRT.
10400 If the mode of this shift is not the mode of the outer shift,
10401 we can't do this if either shift is a right shift or ROTATE.
10403 Finally, we can't do any of these if the mode is too wide
10404 unless the codes are the same.
10406 Handle the case where the shift codes are the same
10407 first. */
10410 {
10419 }
10430 /* To compute the mask to apply after the shift, shift the
10431 nonzero bits of the inner shift the same way the
10432 outer shift will. */
10435 result_mode);
10437 mask_rtx
10441 /* Give up if we can't compute an outer operation to use. */
10449 /* If the shifts are in the same direction, we add the
10450 counts. Otherwise, we subtract them. */
10454 else
10457 /* If COUNT is positive, the new shift is usually CODE,
10458 except for the two exceptions below, in which case it is
10459 FIRST_CODE. If the count is negative, FIRST_CODE should
10460 always be used */
10470 }
10472 /* If we have (A << B << C) for any shift, we can convert this to
10473 (A << C << B). This wins if A is a constant. Only try this if
10474 B is not a constant. */
10479 {
10486 }
10493 /* Make this fit the case below. */
10500 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10501 with C the size of VAROP - 1 and the shift is logical if
10502 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10503 we have an (le X 0) operation. If we have an arithmetic shift
10504 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10505 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10513 {
10516 const0_rtx);
10522 }
10524 /* If we have (shift (logical)), move the logical to the outside
10525 to allow it to possibly combine with another logical and the
10526 shift to combine with another shift. This also canonicalizes to
10527 what a ZERO_EXTRACT looks like. Also, some machines have
10528 (and (shift)) insns. */
10531 /* We can't do this if we have (ashiftrt (xor)) and the
10532 constant has its sign bit set in shift_mode with shift_mode
10533 wider than result_mode. */
10537 shift_mode))
10545 {
10548 }
10550 /* If we can't do that, try to simplify the shift in each arm of the
10551 logical expression, make a new logical expression, and apply
10552 the inverse distributive law. This also can't be done for
10553 (ashiftrt (xor)) where we've widened the shift and the constant
10554 changes the sign bit. */
10559 shift_mode)))
10560 {
10572 }
10576 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10577 says that the sign bit can be tested, FOO has mode MODE, C is
10578 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10579 that may be nonzero. */
10589 {
10593 }
10597 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10598 than the number of bits in the mode is equivalent to A. */
10602 {
10606 }
10608 /* NEG commutes with ASHIFT since it is multiplication. Move the
10609 NEG outside to allow shifts to combine. */
10613 {
10616 }
10620 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10621 is one less than the number of bits in the mode is
10622 equivalent to (xor A 1). */
10629 {
10633 }
10635 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10636 that might be nonzero in BAR are those being shifted out and those
10637 bits are known zero in FOO, we can replace the PLUS with FOO.
10638 Similarly in the other operand order. This code occurs when
10639 we are computing the size of a variable-size array. */
10646 {
10649 }
10657 result_mode)))
10658 {
10661 }
10663 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10673 {
10676 }
10678 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10679 signbit', and attempt to change the PLUS to an XOR and move it to
10680 the outer operation as is done above in the AND/IOR/XOR case
10681 leg for shift(logical). See details in logical handling above
10682 for reasoning in doing so. */
10693 {
10696 }
10701 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10702 with C the size of VAROP - 1 and the shift is logical if
10703 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10704 we have a (gt X 0) operation. If the shift is arithmetic with
10705 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10706 we have a (neg (gt X 0)) operation. */
10715 {
10718 const0_rtx);
10724 }
10728 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10729 if the truncate does not affect the value. */
10736 {
10739 varop_inner
10742 GEN_INT
10747 }
10752 }
10755 }
10760 /* We have now finished analyzing the shift. The result should be
10761 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10762 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10763 to the result of the shift. OUTER_CONST is the relevant constant,
10764 but we must turn off all bits turned off in the shift. */
10772 /* Make a SUBREG if necessary. If we can't make it, fail. */
10777 /* If we have an outer operation and we just made a shift, it is
10778 possible that we could have simplified the shift were it not
10779 for the outer operation. So try to do the simplification
10780 recursively. */
10784 else
10790 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10791 turn off all the bits that the shift would have turned off. */
10796 /* Do the remainder of the processing in RESULT_MODE. */
10799 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10800 operation. */
10805 {
10813 {
10814 /* This means that we have determined that the result is
10815 equivalent to a constant. This should be rare. */
10818 }
10821 else
10824 }
10827 }
10829 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10830 The result of the shift is RESULT_MODE. If we cannot simplify it,
10831 return X or, if it is NULL, synthesize the expression with
10832 simplify_gen_binary. Otherwise, return a simplified value.
10834 The shift is normally computed in the widest mode we find in VAROP, as
10835 long as it isn't a different number of words than RESULT_MODE. Exceptions
10836 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10838 static rtx
10841 {
10851 }
10853 \f
10854 /* Like recog, but we receive the address of a pointer to a new pattern.
10855 We try to match the rtx that the pointer points to.
10856 If that fails, we may try to modify or replace the pattern,
10857 storing the replacement into the same pointer object.
10859 Modifications include deletion or addition of CLOBBERs.
10861 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10862 the CLOBBERs are placed.
10864 The value is the final insn code from the pattern ultimately matched,
10865 or -1. */
10867 static int
10869 {
10871 rtx pat_without_clobbers;
10879 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10880 we use to indicate that something didn't match. If we find such a
10881 thing, force rejection. */
10895 {
10898 else
10901 }
10903 /* If it isn't, there is the possibility that we previously had an insn
10904 that clobbered some register as a side effect, but the combined
10905 insn doesn't need to do that. So try once more without the clobbers
10906 unless this represents an ASM insn. */
10910 {
10915 {
10918 pos++;
10919 }
10929 {
10932 else
10935 }
10936 }
10943 /* Recognize all noop sets, these will be killed by followup pass. */
10947 /* If we had any clobbers to add, make a new pattern than contains
10948 them. Then check to make sure that all of them are dead. */
10950 {
10960 else
10967 {
10972 {
10976 }
10977 }
10979 }
10983 {
10990 /* Allow targets to reject combined insn. */
10992 {
10995 dump_file);
10997 /* Callers expect recog_for_combine to strip
10998 clobbers from the pattern on failure. */
11003 }
11008 }
11014 }
11015 \f
11016 /* Like gen_lowpart_general but for use by combine. In combine it
11017 is not possible to create any new pseudoregs. However, it is
11018 safe to create invalid memory addresses, because combine will
11019 try to recognize them and all they will do is make the combine
11020 attempt fail.
11022 If for some reason this cannot do its job, an rtx
11023 (clobber (const_int 0)) is returned.
11024 An insn containing that will not be recognized. */
11026 static rtx
11028 {
11032 rtx result;
11037 /* We can only support MODE being wider than a word if X is a
11038 constant integer or has a mode the same size. */
11043 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11044 won't know what to do. So we will strip off the SUBREG here and
11045 process normally. */
11047 {
11050 /* For use in case we fall down into the address adjustments
11051 further below, we need to adjust the known mode and size of
11052 x; imode and isize, since we just adjusted x. */
11059 }
11067 {
11070 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11071 address. */
11076 /* If we want to refer to something bigger than the original memref,
11077 generate a paradoxical subreg instead. That will force a reload
11078 of the original memref X. */
11085 /* Adjust the address so that the address-after-the-data is
11086 unchanged. */
11091 }
11093 /* If X is a comparison operator, rewrite it in a new mode. This
11094 probably won't match, but may allow further simplifications. */
11098 /* If we couldn't simplify X any other way, just enclose it in a
11099 SUBREG. Normally, this SUBREG won't match, but some patterns may
11100 include an explicit SUBREG or we may simplify it further in combine. */
11101 else
11102 {
11104 rtx res;
11108 {
11113 }
11117 }
11119 fail:
11121 }
11122 \f
11123 /* Try to simplify a comparison between OP0 and a constant OP1,
11124 where CODE is the comparison code that will be tested, into a
11125 (CODE OP0 const0_rtx) form.
11127 The result is a possibly different comparison code to use.
11128 *POP1 may be updated. */
11130 static enum rtx_code
11133 {
11137 /* Get the constant we are comparing against and turn off all bits
11138 not on in our mode. */
11142 /* If we are comparing against a constant power of two and the value
11143 being compared can only have that single bit nonzero (e.g., it was
11144 `and'ed with that bit), we can replace this with a comparison
11145 with zero. */
11153 {
11156 }
11158 /* Similarly, if we are comparing a value known to be either -1 or
11159 0 with -1, change it to the opposite comparison against zero. */
11164 {
11167 }
11169 /* Do some canonicalizations based on the comparison code. We prefer
11170 comparisons against zero and then prefer equality comparisons.
11171 If we can reduce the size of a constant, we will do that too. */
11173 {
11175 /* < C is equivalent to <= (C - 1) */
11177 {
11180 /* ... fall through to LE case below. */
11181 }
11182 else
11186 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11188 {
11191 }
11193 /* If we are doing a <= 0 comparison on a value known to have
11194 a zero sign bit, we can replace this with == 0. */
11204 /* >= C is equivalent to > (C - 1). */
11206 {
11209 /* ... fall through to GT below. */
11210 }
11211 else
11215 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11217 {
11220 }
11222 /* If we are doing a > 0 comparison on a value known to have
11223 a zero sign bit, we can replace this with != 0. */
11233 /* < C is equivalent to <= (C - 1). */
11235 {
11238 /* ... fall through ... */
11239 }
11240 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11244 {
11248 }
11249 else
11253 /* unsigned <= 0 is equivalent to == 0 */
11256 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11260 {
11263 }
11267 /* >= C is equivalent to > (C - 1). */
11269 {
11272 /* ... fall through ... */
11273 }
11275 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11279 {
11283 }
11284 else
11288 /* unsigned > 0 is equivalent to != 0 */
11291 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11295 {
11298 }
11303 }
11307 }
11308 \f
11309 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11310 comparison code that will be tested.
11312 The result is a possibly different comparison code to use. *POP0 and
11313 *POP1 may be updated.
11315 It is possible that we might detect that a comparison is either always
11316 true or always false. However, we do not perform general constant
11317 folding in combine, so this knowledge isn't useful. Such tautologies
11318 should have been detected earlier. Hence we ignore all such cases. */
11320 static enum rtx_code
11322 {
11329 /* Try a few ways of applying the same transformation to both operands. */
11331 {
11332 #ifndef WORD_REGISTER_OPERATIONS
11333 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11334 so check specially. */
11349 - (GET_MODE_PRECISION
11351 {
11354 }
11355 #endif
11357 /* If both operands are the same constant shift, see if we can ignore the
11358 shift. We can if the shift is a rotate or if the bits shifted out of
11359 this shift are known to be zero for both inputs and if the type of
11360 comparison is compatible with the shift. */
11373 {
11386 else
11388 }
11390 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11391 SUBREGs are of the same mode, and, in both cases, the AND would
11392 be redundant if the comparison was done in the narrower mode,
11393 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11394 and the operand's possibly nonzero bits are 0xffffff01; in that case
11395 if we only care about QImode, we don't need the AND). This case
11396 occurs if the output mode of an scc insn is not SImode and
11397 STORE_FLAG_VALUE == 1 (e.g., the 386).
11399 Similarly, check for a case where the AND's are ZERO_EXTEND
11400 operations from some narrower mode even though a SUBREG is not
11401 present. */
11406 {
11423 {
11427 /* The resulting comparison is always unsigned since we masked
11428 off the original sign bit. */
11432 }
11439 {
11445 }
11449 }
11451 /* If both operands are NOT, we can strip off the outer operation
11452 and adjust the comparison code for swapped operands; similarly for
11453 NEG, except that this must be an equality comparison. */
11459 else
11461 }
11463 /* If the first operand is a constant, swap the operands and adjust the
11464 comparison code appropriately, but don't do this if the second operand
11465 is already a constant integer. */
11467 {
11470 }
11472 /* We now enter a loop during which we will try to simplify the comparison.
11473 For the most part, we only are concerned with comparisons with zero,
11474 but some things may really be comparisons with zero but not start
11475 out looking that way. */
11478 {
11485 HOST_WIDE_INT const_op;
11487 /* We only want to handle integral modes. This catches VOIDmode,
11488 CCmode, and the floating-point modes. An exception is that we
11489 can handle VOIDmode if OP0 is a COMPARE or a comparison
11490 operation. */
11497 /* Try to simplify the compare to constant, possibly changing the
11498 comparison op, and/or changing op1 to zero. */
11502 /* Compute some predicates to simplify code below. */
11509 /* If this is a sign bit comparison and we can do arithmetic in
11510 MODE, say that we will only be needing the sign bit of OP0. */
11517 /* Now try cases based on the opcode of OP0. If none of the cases
11518 does a "continue", we exit this loop immediately after the
11519 switch. */
11522 {
11524 /* If we are extracting a single bit from a variable position in
11525 a constant that has only a single bit set and are comparing it
11526 with zero, we can convert this into an equality comparison
11527 between the position and the location of the single bit. */
11528 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11529 have already reduced the shift count modulo the word size. */
11535 {
11543 /* Result is nonzero iff shift count is equal to I. */
11546 }
11548 /* ... fall through ... */
11553 {
11556 }
11560 /* If testing for equality, we can take the NOT of the constant. */
11563 {
11567 }
11569 /* If just looking at the sign bit, reverse the sense of the
11570 comparison. */
11572 {
11576 }
11580 /* If testing for equality, we can take the NEG of the constant. */
11583 {
11587 }
11589 /* The remaining cases only apply to comparisons with zero. */
11593 /* When X is ABS or is known positive,
11594 (neg X) is < 0 if and only if X != 0. */
11602 {
11606 }
11608 /* If we have NEG of something whose two high-order bits are the
11609 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11611 {
11615 }
11619 /* If we are testing equality and our count is a constant, we
11620 can perform the inverse operation on our RHS. */
11624 {
11628 }
11630 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11631 a particular bit. Convert it to an AND of a constant of that
11632 bit. This will be converted into a ZERO_EXTRACT. */
11636 {
11643 }
11645 /* Fall through. */
11648 /* ABS is ignorable inside an equality comparison with zero. */
11650 {
11653 }
11657 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11658 (compare FOO CONST) if CONST fits in FOO's mode and we
11659 are either testing inequality or have an unsigned
11660 comparison with ZERO_EXTEND or a signed comparison with
11661 SIGN_EXTEND. But don't do it if we don't have a compare
11662 insn of the given mode, since we'd have to revert it
11663 later on, and then we wouldn't know whether to sign- or
11664 zero-extend. */
11667 && ! unsigned_comparison_p
11671 {
11674 }
11678 /* Check for the case where we are comparing A - C1 with C2, that is
11680 (subreg:MODE (plus (A) (-C1))) op (C2)
11682 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11683 comparison in the wider mode. One of the following two conditions
11684 must be true in order for this to be valid:
11686 1. The mode extension results in the same bit pattern being added
11687 on both sides and the comparison is equality or unsigned. As
11688 C2 has been truncated to fit in MODE, the pattern can only be
11689 all 0s or all 1s.
11691 2. The mode extension results in the sign bit being copied on
11692 each side.
11694 The difficulty here is that we have predicates for A but not for
11695 (A - C1) so we need to check that C1 is within proper bounds so
11696 as to perturbate A as little as possible. */
11703 {
11712 /* (A - C1) zero-extends if it is positive and sign-extends
11713 if it is negative, C2 both zero- and sign-extends. */
11717 /* (A - C1) sign-extends if it is positive and 1-extends
11718 if it is negative, C2 both sign- and 1-extends. */
11725 /* (A - C1) always sign-extends, like C2. */
11729 {
11732 }
11733 }
11735 /* If the inner mode is narrower and we are extracting the low part,
11736 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11740 else
11743 /* ... fall through ... */
11753 {
11756 }
11760 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11761 this for equality comparisons due to pathological cases involving
11762 overflows. */
11766 {
11770 }
11772 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11775 {
11779 }
11783 /* We used to optimize signed comparisons against zero, but that
11784 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11785 arrive here as equality comparisons, or (GEU, LTU) are
11786 optimized away. No need to special-case them. */
11788 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11789 (eq B (minus A C)), whichever simplifies. We can only do
11790 this for equality comparisons due to pathological cases involving
11791 overflows. */
11795 {
11799 }
11804 {
11808 }
11810 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11811 of bits in X minus 1, is one iff X > 0. */
11816 {
11820 }
11824 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11825 if C is zero or B is a constant. */
11829 {
11833 }
11841 /* We can't do anything if OP0 is a condition code value, rather
11842 than an actual data value. */
11848 /* Get the two operands being compared. */
11851 else
11854 /* Check for the cases where we simply want the result of the
11855 earlier test or the opposite of that result. */
11859 {
11863 else
11867 {
11872 }
11873 }
11877 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11878 iff X <= 0. */
11882 {
11886 }
11890 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11891 will be converted to a ZERO_EXTRACT later. */
11895 {
11900 }
11902 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11903 zero and X is a comparison and C1 and C2 describe only bits set
11904 in STORE_FLAG_VALUE, we can compare with X. */
11912 {
11919 {
11922 }
11923 }
11925 /* If we are doing an equality comparison of an AND of a bit equal
11926 to the sign bit, replace this with a LT or GE comparison of
11927 the underlying value. */
11934 {
11938 }
11940 /* If this AND operation is really a ZERO_EXTEND from a narrower
11941 mode, the constant fits within that mode, and this is either an
11942 equality or unsigned comparison, try to do this comparison in
11943 the narrower mode.
11945 Note that in:
11947 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11948 -> (ne:DI (reg:SI 4) (const_int 0))
11950 unless TRULY_NOOP_TRUNCATION allows it or the register is
11951 known to hold a value of the required mode the
11952 transformation is invalid. */
11963 {
11966 }
11968 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11969 fits in both M1 and M2 and the SUBREG is either paradoxical
11970 or represents the low part, permute the SUBREG and the AND
11971 and try again. */
11973 {
11976 /* Require an integral mode, to avoid creating something like
11977 (AND:SF ...). */
11979 /* It is unsafe to commute the AND into the SUBREG if the
11980 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11981 not defined. As originally written the upper bits
11982 have a defined value due to the AND operation.
11983 However, if we commute the AND inside the SUBREG then
11984 they no longer have defined values and the meaning of
11985 the code has been changed. */
11987 #ifdef WORD_REGISTER_OPERATIONS
11990 #endif
12000 {
12006 }
12007 }
12009 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12013 {
12018 }
12020 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12021 (eq (and (lshiftrt X) 1) 0).
12022 Also handle the case where (not X) is expressed using xor. */
12026 {
12038 {
12039 op0
12044 }
12045 }
12049 /* If we have (compare (ashift FOO N) (const_int C)) and
12050 the high order N bits of FOO (N+1 if an inequality comparison)
12051 are known to be zero, we can do this by comparing FOO with C
12052 shifted right N bits so long as the low-order N bits of C are
12053 zero. */
12065 {
12066 /* We must perform a logical shift, not an arithmetic one,
12067 as we want the top N bits of C to be zero. */
12074 }
12076 /* If we are doing a sign bit comparison, it means we are testing
12077 a particular bit. Convert it to the appropriate AND. */
12080 {
12087 }
12089 /* If this an equality comparison with zero and we are shifting
12090 the low bit to the sign bit, we can convert this to an AND of the
12091 low-order bit. */
12095 {
12098 }
12102 /* If this is an equality comparison with zero, we can do this
12103 as a logical shift, which might be much simpler. */
12106 {
12111 }
12113 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12114 do the comparison in a narrower mode. */
12124 {
12127 }
12129 /* Likewise if OP0 is a PLUS of a sign extension with a
12130 constant, which is usually represented with the PLUS
12131 between the shifts. */
12143 {
12151 new_const);
12153 }
12155 /* ... fall through ... */
12157 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12158 the low order N bits of FOO are known to be zero, we can do this
12159 by comparing FOO with C shifted left N bits so long as no
12160 overflow occurs. Even if the low order N bits of FOO aren't known
12161 to be zero, if the comparison is >= or < we can use the same
12162 optimization and for > or <= by setting all the low
12163 order N bits in the comparison constant. */
12174 {
12175 unsigned HOST_WIDE_INT low_bits
12180 {
12181 /* If the shift was logical, then we must make the condition
12182 unsigned. */
12190 const_op
12195 }
12196 }
12198 /* If we are using this shift to extract just the sign bit, we
12199 can replace this with an LT or GE comparison. */
12204 {
12208 }
12213 }
12216 }
12218 /* Now make any compound operations involved in this comparison. Then,
12219 check for an outmost SUBREG on OP0 that is not doing anything or is
12220 paradoxical. The latter transformation must only be performed when
12221 it is known that the "extra" bits will be the same in op0 and op1 or
12222 that they don't matter. There are three cases to consider:
12224 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12225 care bits and we can assume they have any convenient value. So
12226 making the transformation is safe.
12228 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12229 In this case the upper bits of op0 are undefined. We should not make
12230 the simplification in that case as we do not know the contents of
12231 those bits.
12233 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12234 UNKNOWN. In that case we know those bits are zeros or ones. We must
12235 also be sure that they are the same as the upper bits of op1.
12237 We can never remove a SUBREG for a non-equality comparison because
12238 the sign bit is in a different place in the underlying object. */
12247 {
12249 {
12250 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12251 implemented. */
12253 {
12256 }
12257 }
12263 {
12269 }
12270 }
12272 /* We now do the opposite procedure: Some machines don't have compare
12273 insns in all modes. If OP0's mode is an integer mode smaller than a
12274 word and we can't do a compare in that mode, see if there is a larger
12275 mode for which we can do the compare. There are a number of cases in
12276 which we can use the wider mode. */
12286 {
12289 /* If this is a test for negative, we can make an explicit
12290 test of the sign bit. Test this first so we can use
12291 a paradoxical subreg to extend OP0. */
12295 {
12296 unsigned HOST_WIDE_INT sign
12303 }
12305 /* If the only nonzero bits in OP0 and OP1 are those in the
12306 narrower mode and this is an equality or unsigned comparison,
12307 we can use the wider mode. Similarly for sign-extended
12308 values, in which case it is true for all comparisons. */
12325 {
12326 /* If OP0 is an AND and we don't have an AND in MODE either,
12327 make a new AND in the proper mode. */
12335 else
12336 {
12338 {
12341 }
12342 else
12343 {
12346 }
12348 }
12349 }
12350 }
12352 /* We may have changed the comparison operands. Re-canonicalize. */
12354 {
12357 }
12359 /* If this machine only supports a subset of valid comparisons, see if we
12360 can convert an unsupported one into a supported one. */
12367 }
12368 \f
12369 /* Utility function for record_value_for_reg. Count number of
12370 rtxs in X. */
12371 static int
12373 {
12380 {
12400 }
12411 }
12412 \f
12413 /* Utility function for following routine. Called when X is part of a value
12414 being stored into last_set_value. Sets last_set_table_tick
12415 for each register mentioned. Similar to mention_regs in cse.c */
12417 static void
12419 {
12425 {
12431 {
12434 }
12437 }
12441 {
12442 /* Check for identical subexpressions. If x contains
12443 identical subexpression we only have to traverse one of
12444 them. */
12446 {
12447 /* Note that at this point x1 has already been
12448 processed. */
12452 /* If x0 and x1 are identical then there is no need to
12453 process x0. */
12457 /* If x0 is identical to a subexpression of x1 then while
12458 processing x1, x0 has already been processed. Thus we
12459 are done with x. */
12464 /* If x1 is identical to a subexpression of x0 then we
12465 still have to process the rest of x0. */
12468 {
12471 }
12472 }
12475 }
12479 }
12481 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12482 are saying that the register is clobbered and we no longer know its
12483 value. If INSN is zero, don't update reg_stat[].last_set; this is
12484 only permitted with VALUE also zero and is used to invalidate the
12485 register. */
12487 static void
12489 {
12495 /* If VALUE contains REG and we have a previous value for REG, substitute
12496 the previous value. */
12498 {
12499 rtx tem;
12501 /* Set things up so get_last_value is allowed to see anything set up to
12502 our insn. */
12506 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12507 it isn't going to be useful and will take a lot of time to process,
12508 so just use the CLOBBER. */
12511 {
12517 {
12518 /* If there are two or more occurrences of REG in VALUE,
12519 prevent the value from growing too much. */
12522 }
12525 }
12526 }
12528 /* For each register modified, show we don't know its value, that
12529 we don't know about its bitwise content, that its value has been
12530 updated, and that we don't know the location of the death of the
12531 register. */
12533 {
12545 }
12547 /* Mark registers that are being referenced in this value. */
12551 /* Now update the status of each register being set.
12552 If someone is using this register in this block, set this register
12553 to invalid since we will get confused between the two lives in this
12554 basic block. This makes using this register always invalid. In cse, we
12555 scan the table to invalidate all entries using this register, but this
12556 is too much work for us. */
12559 {
12565 else
12567 }
12569 /* The value being assigned might refer to X (like in "x++;"). In that
12570 case, we must replace it with (clobber (const_int 0)) to prevent
12571 infinite loops. */
12574 {
12578 }
12580 /* For the main register being modified, update the value, the mode, the
12581 nonzero bits, and the number of sign bit copies. */
12586 {
12594 rsp->last_set_sign_bit_copies
12596 }
12597 }
12599 /* Called via note_stores from record_dead_and_set_regs to handle one
12600 SET or CLOBBER in an insn. DATA is the instruction in which the
12601 set is occurring. */
12603 static void
12605 {
12612 {
12616 }
12619 {
12620 /* If we are setting the whole register, we know its value. Otherwise
12621 show that we don't know the value. We can handle SUBREG in
12622 some cases. */
12633 else
12635 }
12637 /* Ignore pushes, they clobber nothing. */
12640 }
12642 /* Update the records of when each REG was most recently set or killed
12643 for the things done by INSN. This is the last thing done in processing
12644 INSN in the combiner loop.
12646 We update reg_stat[], in particular fields last_set, last_set_value,
12647 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12648 last_death, and also the similar information mem_last_set (which insn
12649 most recently modified memory) and last_call_luid (which insn was the
12650 most recent subroutine call). */
12652 static void
12654 {
12655 rtx link;
12659 {
12662 {
12667 {
12672 }
12673 }
12676 }
12679 {
12680 hard_reg_set_iterator hrsi;
12682 {
12694 }
12698 /* We can't combine into a call pattern. Remember, though, that
12699 the return value register is set at this LUID. We could
12700 still replace a register with the return value from the
12701 wrong subroutine call! */
12703 }
12704 else
12706 }
12708 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12709 register present in the SUBREG, so for each such SUBREG go back and
12710 adjust nonzero and sign bit information of the registers that are
12711 known to have some zero/sign bits set.
12713 This is needed because when combine blows the SUBREGs away, the
12714 information on zero/sign bits is lost and further combines can be
12715 missed because of that. */
12717 static void
12719 {
12721 rtx set;
12729 {
12738 {
12741 }
12745 {
12748 }
12751 {
12754 }
12755 else
12757 }
12758 }
12760 /* Check if X, a register, is known to contain a value already
12761 truncated to MODE. In this case we can use a subreg to refer to
12762 the truncated value even though in the generic case we would need
12763 an explicit truncation. */
12765 static bool
12767 {
12779 }
12781 /* If X is a hard reg or a subreg record the mode that the register is
12782 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12783 to turn a truncate into a subreg using this information. Return true
12784 if traversing X is complete. */
12786 static bool
12788 {
12789 machine_mode truncated_mode;
12793 {
12804 }
12805 /* ??? For hard-regs we now record everything. We might be able to
12806 optimize this using last_set_mode. */
12809 else
12817 {
12820 }
12823 }
12825 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12826 the modes they are used in. This can help truning TRUNCATEs into
12827 SUBREGs. */
12829 static void
12831 {
12836 }
12838 /* Scan X for promoted SUBREGs. For each one found,
12839 note what it implies to the registers used in it. */
12841 static void
12843 {
12848 else
12849 {
12855 {
12865 }
12866 }
12867 }
12868 \f
12869 /* Verify that all the registers and memory references mentioned in *LOC are
12870 still valid. *LOC was part of a value set in INSN when label_tick was
12871 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12872 the invalid references with (clobber (const_int 0)) and return 1. This
12873 replacement is useful because we often can get useful information about
12874 the form of a value (e.g., if it was produced by a shift that always
12875 produces -1 or 0) even though we don't know exactly what registers it
12876 was produced from. */
12878 static int
12880 {
12887 {
12893 {
12896 /* If this is a pseudo-register that was only set once and not
12897 live at the beginning of the function, it is always valid. */
12901 && (!REGNO_REG_SET_P
12903 regno)))
12905 {
12909 }
12910 }
12913 }
12914 /* If this is a memory reference, make sure that there were no stores after
12915 it that might have clobbered the value. We don't have alias info, so we
12916 assume any store invalidates it. Moreover, we only have local UIDs, so
12917 we also assume that there were stores in the intervening basic blocks. */
12920 {
12924 }
12927 {
12929 {
12930 /* Check for identical subexpressions. If x contains
12931 identical subexpression we only have to traverse one of
12932 them. */
12934 {
12935 /* Note that at this point x0 has already been checked
12936 and found valid. */
12940 /* If x0 and x1 are identical then x is also valid. */
12944 /* If x1 is identical to a subexpression of x0 then
12945 while checking x0, x1 has already been checked. Thus
12946 it is valid and so as x. */
12951 /* If x0 is identical to a subexpression of x1 then x is
12952 valid iff the rest of x1 is valid. */
12955 return
12959 }
12964 }
12970 }
12972 /* If we haven't found a reason for it to be invalid, it is valid. */
12974 }
12976 /* Get the last value assigned to X, if known. Some registers
12977 in the value may be replaced with (clobber (const_int 0)) if their value
12978 is known longer known reliably. */
12980 static rtx
12982 {
12984 rtx value;
12987 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12988 then convert it to the desired mode. If this is a paradoxical SUBREG,
12989 we cannot predict what values the "extra" bits might have. */
13003 /* If we don't have a value, or if it isn't for this basic block and
13004 it's either a hard register, set more than once, or it's a live
13005 at the beginning of the function, return 0.
13007 Because if it's not live at the beginning of the function then the reg
13008 is always set before being used (is never used without being set).
13009 And, if it's set only once, and it's always set before use, then all
13010 uses must have the same last value, even if it's not from this basic
13011 block. */
13018 || REGNO_REG_SET_P
13022 /* If the value was set in a later insn than the ones we are processing,
13023 we can't use it even if the register was only set once. */
13028 /* If the value has all its registers valid, return it. */
13032 /* Otherwise, make a copy and replace any invalid register with
13033 (clobber (const_int 0)). If that fails for some reason, return 0. */
13040 }
13041 \f
13042 /* Return nonzero if expression X refers to a REG or to memory
13043 that is set in an instruction more recent than FROM_LUID. */
13045 static int
13047 {
13053 {
13057 #ifdef PUSH_ROUNDING
13058 /* Don't allow uses of the stack pointer to be moved,
13059 because we don't know whether the move crosses a push insn. */
13062 #endif
13064 {
13070 }
13072 }
13080 {
13082 {
13087 }
13091 }
13093 }
13094 \f
13095 /* Define three variables used for communication between the following
13096 routines. */
13101 /* Function called via note_stores from reg_dead_at_p.
13103 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13104 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13106 static void
13108 {
13118 }
13120 /* Return nonzero if REG is known to be dead at INSN.
13122 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13123 referencing REG, it is dead. If we hit a SET referencing REG, it is
13124 live. Otherwise, see if it is live or dead at the start of the basic
13125 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13126 must be assumed to be always live. */
13128 static int
13130 {
13131 basic_block block;
13134 /* Set variables for reg_dead_at_p_1. */
13140 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13141 we allow the machine description to decide whether use-and-clobber
13142 patterns are OK. */
13144 {
13148 }
13150 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13151 beginning of basic block. */
13154 {
13156 {
13166 }
13172 }
13174 /* Look at live-in sets for the basic block that we were in. */
13180 }
13181 \f
13182 /* Note hard registers in X that are used. */
13184 static void
13186 {
13192 {
13196 CASE_CONST_ANY:
13201 #ifdef HAVE_cc0
13202 /* CC0 must die in the insn after it is set, so we don't need to take
13203 special note of it here. */
13205 #endif
13209 /* If we are clobbering a MEM, mark any hard registers inside the
13210 address as used. */
13217 /* A hard reg in a wide mode may really be multiple registers.
13218 If so, mark all of them just like the first. */
13220 {
13221 /* None of this applies to the stack, frame or arg pointers. */
13223 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
13225 #endif
13226 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
13228 #endif
13233 }
13237 {
13238 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13239 the address. */
13251 }
13256 }
13258 /* Recursively scan the operands of this expression. */
13260 {
13264 {
13268 {
13273 }
13274 }
13275 }
13276 }
13277 \f
13278 /* Remove register number REGNO from the dead registers list of INSN.
13280 Return the note used to record the death, if there was one. */
13282 rtx
13284 {
13291 }
13293 /* For each register (hardware or pseudo) used within expression X, if its
13294 death is in an instruction with luid between FROM_LUID (inclusive) and
13295 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13296 list headed by PNOTES.
13298 That said, don't move registers killed by maybe_kill_insn.
13300 This is done when X is being merged by combination into TO_INSN. These
13301 notes will then be distributed as needed. */
13303 static void
13306 {
13312 {
13316 /* Don't move the register if it gets killed in between from and to. */
13325 {
13328 /* It is possible for the call above to return 0. This can occur
13329 when last_death points to I2 or I1 that we combined with.
13330 In that case make a new note.
13332 We must also check for the case where X is a hard register
13333 and NOTE is a death note for a range of hard registers
13334 including X. In that case, we must put REG_DEAD notes for
13335 the remaining registers in place of NOTE. */
13340 {
13349 }
13351 /* If we didn't find any note, or if we found a REG_DEAD note that
13352 covers only part of the given reg, and we have a multi-reg hard
13353 register, then to be safe we must check for REG_DEAD notes
13354 for each register other than the first. They could have
13355 their own REG_DEAD notes lying around. */
13362 {
13369 else
13375 }
13378 {
13381 }
13382 else
13384 }
13387 }
13390 {
13395 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13396 that accesses one word of a multi-word item, some
13397 piece of everything register in the expression is used by
13398 this insn, so remove any old death. */
13399 /* ??? So why do we test for equality of the sizes? */
13408 {
13411 }
13413 /* If this is some other SUBREG, we know it replaces the entire
13414 value, so use that as the destination. */
13418 /* If this is a MEM, adjust deaths of anything used in the address.
13419 For a REG (the only other possibility), the entire value is
13420 being replaced so the old value is not used in this insn. */
13426 }
13435 {
13437 {
13442 }
13445 }
13446 }
13447 \f
13448 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13449 pattern of an insn. X must be a REG. */
13451 static int
13453 {
13457 {
13459 rtx target;
13466 else
13483 }
13491 }
13492 \f
13493 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13494 as appropriate. I3 and I2 are the insns resulting from the combination
13495 insns including FROM (I2 may be zero).
13497 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13498 not need REG_DEAD notes because they are being substituted for. This
13499 saves searching in the most common cases.
13501 Each note in the list is either ignored or placed on some insns, depending
13502 on the type of note. */
13504 static void
13507 {
13509 rtx tem_note;
13513 {
13518 {
13521 /* Doesn't matter much where we put this, as long as it's somewhere.
13522 It is preferable to keep these notes on branches, which is most
13523 likely to be i3. */
13530 else
13531 {
13534 }
13538 /* These notes must remain with the call or trapping instruction. */
13543 else
13544 {
13550 /* ??? Otherwise assume we've combined things such that we
13551 can now prove that the instructions can't trap. Drop the
13552 note in this case. */
13553 }
13557 /* ??? How to distribute between i3-i1. Assume i3 contains the
13558 entire adjustment. Assert i3 contains at least some adjust. */
13560 {
13562 /* fixup_args_size_notes looks at REG_NORETURN note,
13563 so ensure the note is placed there first. */
13565 {
13569 {
13575 }
13576 }
13578 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13579 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13582 && !ACCUMULATE_OUTGOING_ARGS
13584 }
13591 /* These notes must remain with the call. It should not be
13592 possible for both I2 and I3 to be a call. */
13595 else
13596 {
13599 }
13603 /* Any clobbers for i3 may still exist, and so we must process
13604 REG_UNUSED notes from that insn.
13606 Any clobbers from i2 or i1 can only exist if they were added by
13607 recog_for_combine. In that case, recog_for_combine created the
13608 necessary REG_UNUSED notes. Trying to keep any original
13609 REG_UNUSED notes from these insns can cause incorrect output
13610 if it is for the same register as the original i3 dest.
13611 In that case, we will notice that the register is set in i3,
13612 and then add a REG_UNUSED note for the destination of i3, which
13613 is wrong. However, it is possible to have REG_UNUSED notes from
13614 i2 or i1 for register which were both used and clobbered, so
13615 we keep notes from i2 or i1 if they will turn into REG_DEAD
13616 notes. */
13618 /* If this register is set or clobbered in I3, put the note there
13619 unless there is one already. */
13621 {
13629 }
13630 /* Otherwise, if this register is used by I3, then this register
13631 now dies here, so we must put a REG_DEAD note here unless there
13632 is one already. */
13638 {
13641 }
13647 /* These notes say something about results of an insn. We can
13648 only support them if they used to be on I3 in which case they
13649 remain on I3. Otherwise they are ignored.
13651 If the note refers to an expression that is not a constant, we
13652 must also ignore the note since we cannot tell whether the
13653 equivalence is still true. It might be possible to do
13654 slightly better than this (we only have a problem if I2DEST
13655 or I1DEST is present in the expression), but it doesn't
13656 seem worth the trouble. */
13664 /* These notes say something about how a register is used. They must
13665 be present on any use of the register in I2 or I3. */
13670 {
13673 else
13675 }
13680 /* This can show up in several ways -- either directly in the
13681 pattern, or hidden off in the constant pool with (or without?)
13682 a REG_EQUAL note. */
13683 /* ??? Ignore the without-reg_equal-note problem for now. */
13695 {
13698 else
13700 }
13702 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13703 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13704 there. */
13709 {
13716 }
13722 {
13730 }
13734 /* This note says something about the value of a register prior
13735 to the execution of an insn. It is too much trouble to see
13736 if the note is still correct in all situations. It is better
13737 to simply delete it. */
13741 /* If we replaced the right hand side of FROM_INSN with a
13742 REG_EQUAL note, the original use of the dying register
13743 will not have been combined into I3 and I2. In such cases,
13744 FROM_INSN is guaranteed to be the first of the combined
13745 instructions, so we simply need to search back before
13746 FROM_INSN for the previous use or set of this register,
13747 then alter the notes there appropriately.
13749 If the register is used as an input in I3, it dies there.
13750 Similarly for I2, if it is nonzero and adjacent to I3.
13752 If the register is not used as an input in either I3 or I2
13753 and it is not one of the registers we were supposed to eliminate,
13754 there are two possibilities. We might have a non-adjacent I2
13755 or we might have somehow eliminated an additional register
13756 from a computation. For example, we might have had A & B where
13757 we discover that B will always be zero. In this case we will
13758 eliminate the reference to A.
13760 In both cases, we must search to see if we can find a previous
13761 use of A and put the death note there. */
13767 else
13768 {
13779 && !(i2mod
13781 i2mod_old_rhs)))
13786 /* If the new I2 sets the same register that is marked dead
13787 in the note, the note now should not be put on I2, as the
13788 note refers to a previous incarnation of the reg. */
13791 }
13794 {
13798 {
13800 {
13804 }
13806 /* If the register is being set at TEM_INSN, see if that is all
13807 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13808 into a REG_UNUSED note instead. Don't delete sets to
13809 global register vars. */
13813 {
13816 #ifdef HAVE_cc0
13818 #endif
13826 ;
13828 /* Verify that it was the set, and not a clobber that
13829 modified the register.
13831 CC0 targets must be careful to maintain setter/user
13832 pairs. If we cannot delete the setter due to side
13833 effects, mark the user with an UNUSED note instead
13834 of deleting it. */
13838 #ifdef HAVE_cc0
13842 #endif
13843 )
13844 {
13845 /* Move the notes and links of TEM_INSN elsewhere.
13846 This might delete other dead insns recursively.
13847 First set the pattern to something that won't use
13848 any register. */
13862 #ifdef HAVE_cc0
13863 /* Delete the setter too. */
13865 {
13878 }
13879 #endif
13880 }
13881 else
13882 {
13885 /* If there isn't already a REG_UNUSED note, put one
13886 here. Do not place a REG_DEAD note, even if
13887 the register is also used here; that would not
13888 match the algorithm used in lifetime analysis
13889 and can cause the consistency check in the
13890 scheduler to fail. */
13895 }
13896 }
13900 {
13903 /* If we are doing a 3->2 combination, and we have a
13904 register which formerly died in i3 and was not used
13905 by i2, which now no longer dies in i3 and is used in
13906 i2 but does not die in i2, and place is between i2
13907 and i3, then we may need to move a link from place to
13908 i2. */
13910 && from_insn
13913 {
13917 }
13919 }
13923 }
13925 }
13927 /* If the register is set or already dead at PLACE, we needn't do
13928 anything with this note if it is still a REG_DEAD note.
13929 We check here if it is set at all, not if is it totally replaced,
13930 which is what `dead_or_set_p' checks, so also check for it being
13931 set partially. */
13934 {
13940 {
13941 /* Unless the register previously died in PLACE, clear
13942 last_death. [I no longer understand why this is
13943 being done.] */
13947 }
13948 else
13951 /* If this is a death note for a hard reg that is occupying
13952 multiple registers, ensure that we are still using all
13953 parts of the object. If we find a piece of the object
13954 that is unused, we must arrange for an appropriate REG_DEAD
13955 note to be added for it. However, we can't just emit a USE
13956 and tag the note to it, since the register might actually
13957 be dead; so we recourse, and the recursive call then finds
13958 the previous insn that used this register. */
13962 {
13971 {
13974 }
13977 {
13978 /* Put only REG_DEAD notes for pieces that are
13979 not already dead or set. */
13983 {
13990 {
13992 NULL_RTX);
13996 NULL_RTX);
13997 }
14002 {
14004 {
14008 }
14012 {
14015 }
14016 }
14017 }
14020 }
14021 }
14022 }
14026 /* Any other notes should not be present at this point in the
14027 compilation. */
14029 }
14032 {
14035 }
14039 }
14040 }
14041 \f
14042 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14043 I3, I2, and I1 to new locations. This is also called to add a link
14044 pointing at I3 when I3's destination is changed. */
14046 static void
14048 {
14052 {
14059 /* If the insn that this link points to is a NOTE, ignore it. */
14068 {
14071 {
14087 }
14090 }
14091 else
14101 /* A LOG_LINK is defined as being placed on the first insn that uses
14102 a register and points to the insn that sets the register. Start
14103 searching at the next insn after the target of the link and stop
14104 when we reach a set of the register or the end of the basic block.
14106 Note that this correctly handles the link that used to point from
14107 I3 to I2. Also note that not much searching is typically done here
14108 since most links don't point very far away. */
14117 {
14121 }
14124 {
14127 }
14131 /* If we found a place to put the link, place it there unless there
14132 is already a link to the same insn as LINK at that point. */
14135 {
14143 {
14147 /* Set added_links_insn to the earliest insn we added a
14148 link to. */
14152 }
14153 }
14154 }
14155 }
14156 \f
14157 /* Check for any register or memory mentioned in EQUIV that is not
14158 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14159 of EXPR where some registers may have been replaced by constants. */
14161 static bool
14163 {
14166 {
14171 }
14173 }
14174 \f
14175 DEBUG_FUNCTION void
14177 {
14178 fprintf
14180 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14182 }
14184 void
14186 {
14187 fprintf
14189 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14191 }
14192 \f
14193 /* Try combining insns through substitution. */
14194 static unsigned int
14196 {
14206 rebuild_jump_labels_after_combine
14209 /* Combining insns may have turned an indirect jump into a
14210 direct jump. Rebuild the JUMP_LABEL fields of jumping
14211 instructions. */
14213 {
14218 }
14222 }
14227 {
14237 };
14240 {
14244 {}
14246 /* opt_pass methods: */
14249 {
14251 }
14257 rtl_opt_pass *
14259 {
14261 }