| blob | d7f30f84e0d85e0e4b8eadbfc41046fd0b3d5d14 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; REGNOS
27 ;;
29 (define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
52 ;;
53 ;; UNSPEC usage
54 ;;
56 (define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
63 (UNSPEC_FCTIWZ 10)
64 (UNSPEC_FRIM 11)
65 (UNSPEC_FRIN 12)
66 (UNSPEC_FRIP 13)
67 (UNSPEC_FRIZ 14)
68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
70 (UNSPEC_TLSGD 17)
71 (UNSPEC_TLSLD 18)
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
74 (UNSPEC_TLSDTPREL 21)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
78 (UNSPEC_TLSTPREL 25)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
82 (UNSPEC_TLSTLS 29)
83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
85 (UNSPEC_STFIWX 32)
86 (UNSPEC_POPCNTB 33)
87 (UNSPEC_FRES 34)
88 (UNSPEC_SP_SET 35)
89 (UNSPEC_SP_TEST 36)
90 (UNSPEC_SYNC 37)
91 (UNSPEC_LWSYNC 38)
92 (UNSPEC_ISYNC 39)
93 (UNSPEC_SYNC_OP 40)
94 (UNSPEC_ATOMIC 41)
95 (UNSPEC_CMPXCHG 42)
96 (UNSPEC_XCHG 43)
97 (UNSPEC_AND 44)
98 (UNSPEC_DLMZB 45)
99 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47)
101 (UNSPEC_RSQRT 48)
102 (UNSPEC_TOCREL 49)
103 (UNSPEC_MACHOPIC_OFFSET 50)
104 (UNSPEC_BPERM 51)
105 ])
107 ;;
108 ;; UNSPEC_VOLATILE usage
109 ;;
111 (define_constants
112 [(UNSPECV_BLOCK 0)
113 (UNSPECV_LL 1) ; load-locked
114 (UNSPECV_SC 2) ; store-conditional
115 (UNSPECV_EH_RR 9) ; eh_reg_restore
116 ])
117 \f
118 ;; Define an insn type attribute. This is used in function unit delay
119 ;; computations.
120 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
121 (const_string "integer"))
123 ;; Define floating point instruction sub-types for use with Xfpu.md
124 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
126 ;; Length (in bytes).
127 ; '(pc)' in the following doesn't include the instruction itself; it is
128 ; calculated as if the instruction had zero size.
129 (define_attr "length" ""
130 (if_then_else (eq_attr "type" "branch")
131 (if_then_else (and (ge (minus (match_dup 0) (pc))
132 (const_int -32768))
133 (lt (minus (match_dup 0) (pc))
134 (const_int 32764)))
135 (const_int 4)
136 (const_int 8))
137 (const_int 4)))
139 ;; Processor type -- this attribute must exactly match the processor_type
140 ;; enumeration in rs6000.h.
142 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,power7,cell"
143 (const (symbol_ref "rs6000_cpu_attr")))
146 ;; If this instruction is microcoded on the CELL processor
147 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
148 (define_attr "cell_micro" "not,conditional,always"
149 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
150 (const_string "always")
151 (const_string "not")))
153 (automata_option "ndfa")
155 (include "rios1.md")
156 (include "rios2.md")
157 (include "rs64.md")
158 (include "mpc.md")
159 (include "40x.md")
160 (include "440.md")
161 (include "603.md")
162 (include "6xx.md")
163 (include "7xx.md")
164 (include "7450.md")
165 (include "8540.md")
166 (include "e300c2c3.md")
167 (include "e500mc.md")
168 (include "power4.md")
169 (include "power5.md")
170 (include "power6.md")
171 (include "power7.md")
172 (include "cell.md")
173 (include "xfpu.md")
175 (include "predicates.md")
176 (include "constraints.md")
178 (include "darwin.md")
180 \f
181 ;; Mode iterators
183 ; This mode iterator allows :GPR to be used to indicate the allowable size
184 ; of whole values in GPRs.
185 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
187 ; Any supported integer mode.
188 (define_mode_iterator INT [QI HI SI DI TI])
190 ; Any supported integer mode that fits in one register.
191 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
193 ; extend modes for DImode
194 (define_mode_iterator QHSI [QI HI SI])
196 ; SImode or DImode, even if DImode doesn't fit in GPRs.
197 (define_mode_iterator SDI [SI DI])
199 ; The size of a pointer. Also, the size of the value that a record-condition
200 ; (one with a '.') will compare.
201 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
203 ; Any hardware-supported floating-point mode
204 (define_mode_iterator FP [
205 (SF "TARGET_HARD_FLOAT
206 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
207 (DF "TARGET_HARD_FLOAT
208 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
209 (TF "!TARGET_IEEEQUAD
210 && TARGET_HARD_FLOAT
211 && (TARGET_FPRS || TARGET_E500_DOUBLE)
212 && TARGET_LONG_DOUBLE_128")
213 (DD "TARGET_DFP")
214 (TD "TARGET_DFP")])
216 ; Various instructions that come in SI and DI forms.
217 ; A generic w/d attribute, for things like cmpw/cmpd.
218 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
220 ; DImode bits
221 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
223 ;; ISEL/ISEL64 target selection
224 (define_mode_attr sel [(SI "") (DI "64")])
226 ;; Suffix for reload patterns
227 (define_mode_attr ptrsize [(SI "32bit")
228 (DI "64bit")])
230 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
231 (DI "TARGET_64BIT")])
233 (define_mode_attr mptrsize [(SI "si")
234 (DI "di")])
236 \f
237 ;; Start with fixed-point load and store insns. Here we put only the more
238 ;; complex forms. Basic data transfer is done later.
240 (define_expand "zero_extend<mode>di2"
241 [(set (match_operand:DI 0 "gpc_reg_operand" "")
242 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
243 "TARGET_POWERPC64"
244 "")
246 (define_insn "*zero_extend<mode>di2_internal1"
247 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
248 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
249 "TARGET_POWERPC64"
250 "@
251 l<wd>z%U1%X1 %0,%1
252 rldicl %0,%1,0,<dbits>"
253 [(set_attr "type" "load,*")])
255 (define_insn "*zero_extend<mode>di2_internal2"
256 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
257 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
258 (const_int 0)))
259 (clobber (match_scratch:DI 2 "=r,r"))]
260 "TARGET_64BIT"
261 "@
262 rldicl. %2,%1,0,<dbits>
263 #"
264 [(set_attr "type" "compare")
265 (set_attr "length" "4,8")])
267 (define_split
268 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
269 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
270 (const_int 0)))
271 (clobber (match_scratch:DI 2 ""))]
272 "TARGET_POWERPC64 && reload_completed"
273 [(set (match_dup 2)
274 (zero_extend:DI (match_dup 1)))
275 (set (match_dup 0)
276 (compare:CC (match_dup 2)
277 (const_int 0)))]
278 "")
280 (define_insn "*zero_extend<mode>di2_internal3"
281 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
282 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
283 (const_int 0)))
284 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
285 (zero_extend:DI (match_dup 1)))]
286 "TARGET_64BIT"
287 "@
288 rldicl. %0,%1,0,<dbits>
289 #"
290 [(set_attr "type" "compare")
291 (set_attr "length" "4,8")])
293 (define_split
294 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
295 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
296 (const_int 0)))
297 (set (match_operand:DI 0 "gpc_reg_operand" "")
298 (zero_extend:DI (match_dup 1)))]
299 "TARGET_POWERPC64 && reload_completed"
300 [(set (match_dup 0)
301 (zero_extend:DI (match_dup 1)))
302 (set (match_dup 2)
303 (compare:CC (match_dup 0)
304 (const_int 0)))]
305 "")
307 (define_insn "extendqidi2"
308 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
309 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
310 "TARGET_POWERPC64"
311 "extsb %0,%1"
312 [(set_attr "type" "exts")])
314 (define_insn ""
315 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
316 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
317 (const_int 0)))
318 (clobber (match_scratch:DI 2 "=r,r"))]
319 "TARGET_64BIT"
320 "@
321 extsb. %2,%1
322 #"
323 [(set_attr "type" "compare")
324 (set_attr "length" "4,8")])
326 (define_split
327 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
328 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
329 (const_int 0)))
330 (clobber (match_scratch:DI 2 ""))]
331 "TARGET_POWERPC64 && reload_completed"
332 [(set (match_dup 2)
333 (sign_extend:DI (match_dup 1)))
334 (set (match_dup 0)
335 (compare:CC (match_dup 2)
336 (const_int 0)))]
337 "")
339 (define_insn ""
340 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
341 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
342 (const_int 0)))
343 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
344 (sign_extend:DI (match_dup 1)))]
345 "TARGET_64BIT"
346 "@
347 extsb. %0,%1
348 #"
349 [(set_attr "type" "compare")
350 (set_attr "length" "4,8")])
352 (define_split
353 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
354 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
355 (const_int 0)))
356 (set (match_operand:DI 0 "gpc_reg_operand" "")
357 (sign_extend:DI (match_dup 1)))]
358 "TARGET_POWERPC64 && reload_completed"
359 [(set (match_dup 0)
360 (sign_extend:DI (match_dup 1)))
361 (set (match_dup 2)
362 (compare:CC (match_dup 0)
363 (const_int 0)))]
364 "")
366 (define_expand "extendhidi2"
367 [(set (match_operand:DI 0 "gpc_reg_operand" "")
368 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
369 "TARGET_POWERPC64"
370 "")
372 (define_insn ""
373 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
374 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
375 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
376 "@
377 lha%U1%X1 %0,%1
378 extsh %0,%1"
379 [(set_attr "type" "load_ext,exts")])
381 (define_insn ""
382 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
383 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
384 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
385 "extsh %0,%1"
386 [(set_attr "type" "exts")])
388 (define_insn ""
389 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
390 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
391 (const_int 0)))
392 (clobber (match_scratch:DI 2 "=r,r"))]
393 "TARGET_64BIT"
394 "@
395 extsh. %2,%1
396 #"
397 [(set_attr "type" "compare")
398 (set_attr "length" "4,8")])
400 (define_split
401 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
402 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
403 (const_int 0)))
404 (clobber (match_scratch:DI 2 ""))]
405 "TARGET_POWERPC64 && reload_completed"
406 [(set (match_dup 2)
407 (sign_extend:DI (match_dup 1)))
408 (set (match_dup 0)
409 (compare:CC (match_dup 2)
410 (const_int 0)))]
411 "")
413 (define_insn ""
414 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
415 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
416 (const_int 0)))
417 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
418 (sign_extend:DI (match_dup 1)))]
419 "TARGET_64BIT"
420 "@
421 extsh. %0,%1
422 #"
423 [(set_attr "type" "compare")
424 (set_attr "length" "4,8")])
426 (define_split
427 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
428 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
429 (const_int 0)))
430 (set (match_operand:DI 0 "gpc_reg_operand" "")
431 (sign_extend:DI (match_dup 1)))]
432 "TARGET_POWERPC64 && reload_completed"
433 [(set (match_dup 0)
434 (sign_extend:DI (match_dup 1)))
435 (set (match_dup 2)
436 (compare:CC (match_dup 0)
437 (const_int 0)))]
438 "")
440 (define_expand "extendsidi2"
441 [(set (match_operand:DI 0 "gpc_reg_operand" "")
442 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
443 "TARGET_POWERPC64"
444 "")
446 (define_insn ""
447 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
448 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
449 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
450 "@
451 lwa%U1%X1 %0,%1
452 extsw %0,%1"
453 [(set_attr "type" "load_ext,exts")])
455 (define_insn ""
456 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
457 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
458 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
459 "extsw %0,%1"
460 [(set_attr "type" "exts")])
462 (define_insn ""
463 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
464 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
465 (const_int 0)))
466 (clobber (match_scratch:DI 2 "=r,r"))]
467 "TARGET_64BIT"
468 "@
469 extsw. %2,%1
470 #"
471 [(set_attr "type" "compare")
472 (set_attr "length" "4,8")])
474 (define_split
475 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
476 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
477 (const_int 0)))
478 (clobber (match_scratch:DI 2 ""))]
479 "TARGET_POWERPC64 && reload_completed"
480 [(set (match_dup 2)
481 (sign_extend:DI (match_dup 1)))
482 (set (match_dup 0)
483 (compare:CC (match_dup 2)
484 (const_int 0)))]
485 "")
487 (define_insn ""
488 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
489 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
490 (const_int 0)))
491 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
492 (sign_extend:DI (match_dup 1)))]
493 "TARGET_64BIT"
494 "@
495 extsw. %0,%1
496 #"
497 [(set_attr "type" "compare")
498 (set_attr "length" "4,8")])
500 (define_split
501 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
502 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
503 (const_int 0)))
504 (set (match_operand:DI 0 "gpc_reg_operand" "")
505 (sign_extend:DI (match_dup 1)))]
506 "TARGET_POWERPC64 && reload_completed"
507 [(set (match_dup 0)
508 (sign_extend:DI (match_dup 1)))
509 (set (match_dup 2)
510 (compare:CC (match_dup 0)
511 (const_int 0)))]
512 "")
514 (define_expand "zero_extendqisi2"
515 [(set (match_operand:SI 0 "gpc_reg_operand" "")
516 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
517 ""
518 "")
520 (define_insn ""
521 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
522 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
523 ""
524 "@
525 lbz%U1%X1 %0,%1
526 {rlinm|rlwinm} %0,%1,0,0xff"
527 [(set_attr "type" "load,*")])
529 (define_insn ""
530 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
531 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
532 (const_int 0)))
533 (clobber (match_scratch:SI 2 "=r,r"))]
534 ""
535 "@
536 {andil.|andi.} %2,%1,0xff
537 #"
538 [(set_attr "type" "fast_compare,compare")
539 (set_attr "length" "4,8")])
541 (define_split
542 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
543 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
544 (const_int 0)))
545 (clobber (match_scratch:SI 2 ""))]
546 "reload_completed"
547 [(set (match_dup 2)
548 (zero_extend:SI (match_dup 1)))
549 (set (match_dup 0)
550 (compare:CC (match_dup 2)
551 (const_int 0)))]
552 "")
554 (define_insn ""
555 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
556 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
557 (const_int 0)))
558 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
559 (zero_extend:SI (match_dup 1)))]
560 ""
561 "@
562 {andil.|andi.} %0,%1,0xff
563 #"
564 [(set_attr "type" "fast_compare,compare")
565 (set_attr "length" "4,8")])
567 (define_split
568 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
569 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
570 (const_int 0)))
571 (set (match_operand:SI 0 "gpc_reg_operand" "")
572 (zero_extend:SI (match_dup 1)))]
573 "reload_completed"
574 [(set (match_dup 0)
575 (zero_extend:SI (match_dup 1)))
576 (set (match_dup 2)
577 (compare:CC (match_dup 0)
578 (const_int 0)))]
579 "")
581 (define_expand "extendqisi2"
582 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
583 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
584 ""
585 "
586 {
587 if (TARGET_POWERPC)
588 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
589 else if (TARGET_POWER)
590 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
591 else
592 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
593 DONE;
594 }")
596 (define_insn "extendqisi2_ppc"
597 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
598 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
599 "TARGET_POWERPC"
600 "extsb %0,%1"
601 [(set_attr "type" "exts")])
603 (define_insn ""
604 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
605 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
606 (const_int 0)))
607 (clobber (match_scratch:SI 2 "=r,r"))]
608 "TARGET_POWERPC"
609 "@
610 extsb. %2,%1
611 #"
612 [(set_attr "type" "compare")
613 (set_attr "length" "4,8")])
615 (define_split
616 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
617 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
618 (const_int 0)))
619 (clobber (match_scratch:SI 2 ""))]
620 "TARGET_POWERPC && reload_completed"
621 [(set (match_dup 2)
622 (sign_extend:SI (match_dup 1)))
623 (set (match_dup 0)
624 (compare:CC (match_dup 2)
625 (const_int 0)))]
626 "")
628 (define_insn ""
629 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
630 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
631 (const_int 0)))
632 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
633 (sign_extend:SI (match_dup 1)))]
634 "TARGET_POWERPC"
635 "@
636 extsb. %0,%1
637 #"
638 [(set_attr "type" "compare")
639 (set_attr "length" "4,8")])
641 (define_split
642 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
643 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
644 (const_int 0)))
645 (set (match_operand:SI 0 "gpc_reg_operand" "")
646 (sign_extend:SI (match_dup 1)))]
647 "TARGET_POWERPC && reload_completed"
648 [(set (match_dup 0)
649 (sign_extend:SI (match_dup 1)))
650 (set (match_dup 2)
651 (compare:CC (match_dup 0)
652 (const_int 0)))]
653 "")
655 (define_expand "extendqisi2_power"
656 [(parallel [(set (match_dup 2)
657 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
658 (const_int 24)))
659 (clobber (scratch:SI))])
660 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
661 (ashiftrt:SI (match_dup 2)
662 (const_int 24)))
663 (clobber (scratch:SI))])]
664 "TARGET_POWER"
665 "
666 { operands[1] = gen_lowpart (SImode, operands[1]);
667 operands[2] = gen_reg_rtx (SImode); }")
669 (define_expand "extendqisi2_no_power"
670 [(set (match_dup 2)
671 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
672 (const_int 24)))
673 (set (match_operand:SI 0 "gpc_reg_operand" "")
674 (ashiftrt:SI (match_dup 2)
675 (const_int 24)))]
676 "! TARGET_POWER && ! TARGET_POWERPC"
677 "
678 { operands[1] = gen_lowpart (SImode, operands[1]);
679 operands[2] = gen_reg_rtx (SImode); }")
681 (define_expand "zero_extendqihi2"
682 [(set (match_operand:HI 0 "gpc_reg_operand" "")
683 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
684 ""
685 "")
687 (define_insn ""
688 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
689 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
690 ""
691 "@
692 lbz%U1%X1 %0,%1
693 {rlinm|rlwinm} %0,%1,0,0xff"
694 [(set_attr "type" "load,*")])
696 (define_insn ""
697 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
698 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
699 (const_int 0)))
700 (clobber (match_scratch:HI 2 "=r,r"))]
701 ""
702 "@
703 {andil.|andi.} %2,%1,0xff
704 #"
705 [(set_attr "type" "fast_compare,compare")
706 (set_attr "length" "4,8")])
708 (define_split
709 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
710 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
711 (const_int 0)))
712 (clobber (match_scratch:HI 2 ""))]
713 "reload_completed"
714 [(set (match_dup 2)
715 (zero_extend:HI (match_dup 1)))
716 (set (match_dup 0)
717 (compare:CC (match_dup 2)
718 (const_int 0)))]
719 "")
721 (define_insn ""
722 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
723 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
724 (const_int 0)))
725 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
726 (zero_extend:HI (match_dup 1)))]
727 ""
728 "@
729 {andil.|andi.} %0,%1,0xff
730 #"
731 [(set_attr "type" "fast_compare,compare")
732 (set_attr "length" "4,8")])
734 (define_split
735 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
736 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
737 (const_int 0)))
738 (set (match_operand:HI 0 "gpc_reg_operand" "")
739 (zero_extend:HI (match_dup 1)))]
740 "reload_completed"
741 [(set (match_dup 0)
742 (zero_extend:HI (match_dup 1)))
743 (set (match_dup 2)
744 (compare:CC (match_dup 0)
745 (const_int 0)))]
746 "")
748 (define_expand "extendqihi2"
749 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
750 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
751 ""
752 "
753 {
754 if (TARGET_POWERPC)
755 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
756 else if (TARGET_POWER)
757 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
758 else
759 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
760 DONE;
761 }")
763 (define_insn "extendqihi2_ppc"
764 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
765 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
766 "TARGET_POWERPC"
767 "extsb %0,%1"
768 [(set_attr "type" "exts")])
770 (define_insn ""
771 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
772 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
773 (const_int 0)))
774 (clobber (match_scratch:HI 2 "=r,r"))]
775 "TARGET_POWERPC"
776 "@
777 extsb. %2,%1
778 #"
779 [(set_attr "type" "compare")
780 (set_attr "length" "4,8")])
782 (define_split
783 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
784 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
785 (const_int 0)))
786 (clobber (match_scratch:HI 2 ""))]
787 "TARGET_POWERPC && reload_completed"
788 [(set (match_dup 2)
789 (sign_extend:HI (match_dup 1)))
790 (set (match_dup 0)
791 (compare:CC (match_dup 2)
792 (const_int 0)))]
793 "")
795 (define_insn ""
796 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
797 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
798 (const_int 0)))
799 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
800 (sign_extend:HI (match_dup 1)))]
801 "TARGET_POWERPC"
802 "@
803 extsb. %0,%1
804 #"
805 [(set_attr "type" "compare")
806 (set_attr "length" "4,8")])
808 (define_split
809 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
810 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
811 (const_int 0)))
812 (set (match_operand:HI 0 "gpc_reg_operand" "")
813 (sign_extend:HI (match_dup 1)))]
814 "TARGET_POWERPC && reload_completed"
815 [(set (match_dup 0)
816 (sign_extend:HI (match_dup 1)))
817 (set (match_dup 2)
818 (compare:CC (match_dup 0)
819 (const_int 0)))]
820 "")
822 (define_expand "extendqihi2_power"
823 [(parallel [(set (match_dup 2)
824 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
825 (const_int 24)))
826 (clobber (scratch:SI))])
827 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
828 (ashiftrt:SI (match_dup 2)
829 (const_int 24)))
830 (clobber (scratch:SI))])]
831 "TARGET_POWER"
832 "
833 { operands[0] = gen_lowpart (SImode, operands[0]);
834 operands[1] = gen_lowpart (SImode, operands[1]);
835 operands[2] = gen_reg_rtx (SImode); }")
837 (define_expand "extendqihi2_no_power"
838 [(set (match_dup 2)
839 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
840 (const_int 24)))
841 (set (match_operand:HI 0 "gpc_reg_operand" "")
842 (ashiftrt:SI (match_dup 2)
843 (const_int 24)))]
844 "! TARGET_POWER && ! TARGET_POWERPC"
845 "
846 { operands[0] = gen_lowpart (SImode, operands[0]);
847 operands[1] = gen_lowpart (SImode, operands[1]);
848 operands[2] = gen_reg_rtx (SImode); }")
850 (define_expand "zero_extendhisi2"
851 [(set (match_operand:SI 0 "gpc_reg_operand" "")
852 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
853 ""
854 "")
856 (define_insn ""
857 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
858 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
859 ""
860 "@
861 lhz%U1%X1 %0,%1
862 {rlinm|rlwinm} %0,%1,0,0xffff"
863 [(set_attr "type" "load,*")])
865 (define_insn ""
866 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
867 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
868 (const_int 0)))
869 (clobber (match_scratch:SI 2 "=r,r"))]
870 ""
871 "@
872 {andil.|andi.} %2,%1,0xffff
873 #"
874 [(set_attr "type" "fast_compare,compare")
875 (set_attr "length" "4,8")])
877 (define_split
878 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
879 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
880 (const_int 0)))
881 (clobber (match_scratch:SI 2 ""))]
882 "reload_completed"
883 [(set (match_dup 2)
884 (zero_extend:SI (match_dup 1)))
885 (set (match_dup 0)
886 (compare:CC (match_dup 2)
887 (const_int 0)))]
888 "")
890 (define_insn ""
891 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
892 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
893 (const_int 0)))
894 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
895 (zero_extend:SI (match_dup 1)))]
896 ""
897 "@
898 {andil.|andi.} %0,%1,0xffff
899 #"
900 [(set_attr "type" "fast_compare,compare")
901 (set_attr "length" "4,8")])
903 (define_split
904 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
905 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
906 (const_int 0)))
907 (set (match_operand:SI 0 "gpc_reg_operand" "")
908 (zero_extend:SI (match_dup 1)))]
909 "reload_completed"
910 [(set (match_dup 0)
911 (zero_extend:SI (match_dup 1)))
912 (set (match_dup 2)
913 (compare:CC (match_dup 0)
914 (const_int 0)))]
915 "")
917 (define_expand "extendhisi2"
918 [(set (match_operand:SI 0 "gpc_reg_operand" "")
919 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
920 ""
921 "")
923 (define_insn ""
924 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
925 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
926 "rs6000_gen_cell_microcode"
927 "@
928 lha%U1%X1 %0,%1
929 {exts|extsh} %0,%1"
930 [(set_attr "type" "load_ext,exts")])
932 (define_insn ""
933 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
934 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
935 "!rs6000_gen_cell_microcode"
936 "{exts|extsh} %0,%1"
937 [(set_attr "type" "exts")])
939 (define_insn ""
940 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
941 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
942 (const_int 0)))
943 (clobber (match_scratch:SI 2 "=r,r"))]
944 ""
945 "@
946 {exts.|extsh.} %2,%1
947 #"
948 [(set_attr "type" "compare")
949 (set_attr "length" "4,8")])
951 (define_split
952 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
953 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
954 (const_int 0)))
955 (clobber (match_scratch:SI 2 ""))]
956 "reload_completed"
957 [(set (match_dup 2)
958 (sign_extend:SI (match_dup 1)))
959 (set (match_dup 0)
960 (compare:CC (match_dup 2)
961 (const_int 0)))]
962 "")
964 (define_insn ""
965 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
966 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
967 (const_int 0)))
968 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
969 (sign_extend:SI (match_dup 1)))]
970 ""
971 "@
972 {exts.|extsh.} %0,%1
973 #"
974 [(set_attr "type" "compare")
975 (set_attr "length" "4,8")])
976 \f
977 ;; IBM 405, 440 and 464 half-word multiplication operations.
979 (define_insn "*macchwc"
980 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
981 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
982 (match_operand:SI 2 "gpc_reg_operand" "r")
983 (const_int 16))
984 (sign_extend:SI
985 (match_operand:HI 1 "gpc_reg_operand" "r")))
986 (match_operand:SI 4 "gpc_reg_operand" "0"))
987 (const_int 0)))
988 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
989 (plus:SI (mult:SI (ashiftrt:SI
990 (match_dup 2)
991 (const_int 16))
992 (sign_extend:SI
993 (match_dup 1)))
994 (match_dup 4)))]
995 "TARGET_MULHW"
996 "macchw. %0, %1, %2"
997 [(set_attr "type" "imul3")])
999 (define_insn "*macchw"
1000 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1001 (plus:SI (mult:SI (ashiftrt:SI
1002 (match_operand:SI 2 "gpc_reg_operand" "r")
1003 (const_int 16))
1004 (sign_extend:SI
1005 (match_operand:HI 1 "gpc_reg_operand" "r")))
1006 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1007 "TARGET_MULHW"
1008 "macchw %0, %1, %2"
1009 [(set_attr "type" "imul3")])
1011 (define_insn "*macchwuc"
1012 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1013 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1014 (match_operand:SI 2 "gpc_reg_operand" "r")
1015 (const_int 16))
1016 (zero_extend:SI
1017 (match_operand:HI 1 "gpc_reg_operand" "r")))
1018 (match_operand:SI 4 "gpc_reg_operand" "0"))
1019 (const_int 0)))
1020 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1021 (plus:SI (mult:SI (lshiftrt:SI
1022 (match_dup 2)
1023 (const_int 16))
1024 (zero_extend:SI
1025 (match_dup 1)))
1026 (match_dup 4)))]
1027 "TARGET_MULHW"
1028 "macchwu. %0, %1, %2"
1029 [(set_attr "type" "imul3")])
1031 (define_insn "*macchwu"
1032 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1033 (plus:SI (mult:SI (lshiftrt:SI
1034 (match_operand:SI 2 "gpc_reg_operand" "r")
1035 (const_int 16))
1036 (zero_extend:SI
1037 (match_operand:HI 1 "gpc_reg_operand" "r")))
1038 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1039 "TARGET_MULHW"
1040 "macchwu %0, %1, %2"
1041 [(set_attr "type" "imul3")])
1043 (define_insn "*machhwc"
1044 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1045 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1046 (match_operand:SI 1 "gpc_reg_operand" "%r")
1047 (const_int 16))
1048 (ashiftrt:SI
1049 (match_operand:SI 2 "gpc_reg_operand" "r")
1050 (const_int 16)))
1051 (match_operand:SI 4 "gpc_reg_operand" "0"))
1052 (const_int 0)))
1053 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1054 (plus:SI (mult:SI (ashiftrt:SI
1055 (match_dup 1)
1056 (const_int 16))
1057 (ashiftrt:SI
1058 (match_dup 2)
1059 (const_int 16)))
1060 (match_dup 4)))]
1061 "TARGET_MULHW"
1062 "machhw. %0, %1, %2"
1063 [(set_attr "type" "imul3")])
1065 (define_insn "*machhw"
1066 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1067 (plus:SI (mult:SI (ashiftrt:SI
1068 (match_operand:SI 1 "gpc_reg_operand" "%r")
1069 (const_int 16))
1070 (ashiftrt:SI
1071 (match_operand:SI 2 "gpc_reg_operand" "r")
1072 (const_int 16)))
1073 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1074 "TARGET_MULHW"
1075 "machhw %0, %1, %2"
1076 [(set_attr "type" "imul3")])
1078 (define_insn "*machhwuc"
1079 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1080 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1081 (match_operand:SI 1 "gpc_reg_operand" "%r")
1082 (const_int 16))
1083 (lshiftrt:SI
1084 (match_operand:SI 2 "gpc_reg_operand" "r")
1085 (const_int 16)))
1086 (match_operand:SI 4 "gpc_reg_operand" "0"))
1087 (const_int 0)))
1088 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1089 (plus:SI (mult:SI (lshiftrt:SI
1090 (match_dup 1)
1091 (const_int 16))
1092 (lshiftrt:SI
1093 (match_dup 2)
1094 (const_int 16)))
1095 (match_dup 4)))]
1096 "TARGET_MULHW"
1097 "machhwu. %0, %1, %2"
1098 [(set_attr "type" "imul3")])
1100 (define_insn "*machhwu"
1101 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1102 (plus:SI (mult:SI (lshiftrt:SI
1103 (match_operand:SI 1 "gpc_reg_operand" "%r")
1104 (const_int 16))
1105 (lshiftrt:SI
1106 (match_operand:SI 2 "gpc_reg_operand" "r")
1107 (const_int 16)))
1108 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1109 "TARGET_MULHW"
1110 "machhwu %0, %1, %2"
1111 [(set_attr "type" "imul3")])
1113 (define_insn "*maclhwc"
1114 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1115 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1116 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1117 (sign_extend:SI
1118 (match_operand:HI 2 "gpc_reg_operand" "r")))
1119 (match_operand:SI 4 "gpc_reg_operand" "0"))
1120 (const_int 0)))
1121 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1122 (plus:SI (mult:SI (sign_extend:SI
1123 (match_dup 1))
1124 (sign_extend:SI
1125 (match_dup 2)))
1126 (match_dup 4)))]
1127 "TARGET_MULHW"
1128 "maclhw. %0, %1, %2"
1129 [(set_attr "type" "imul3")])
1131 (define_insn "*maclhw"
1132 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1133 (plus:SI (mult:SI (sign_extend:SI
1134 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1135 (sign_extend:SI
1136 (match_operand:HI 2 "gpc_reg_operand" "r")))
1137 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1138 "TARGET_MULHW"
1139 "maclhw %0, %1, %2"
1140 [(set_attr "type" "imul3")])
1142 (define_insn "*maclhwuc"
1143 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1144 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1145 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1146 (zero_extend:SI
1147 (match_operand:HI 2 "gpc_reg_operand" "r")))
1148 (match_operand:SI 4 "gpc_reg_operand" "0"))
1149 (const_int 0)))
1150 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1151 (plus:SI (mult:SI (zero_extend:SI
1152 (match_dup 1))
1153 (zero_extend:SI
1154 (match_dup 2)))
1155 (match_dup 4)))]
1156 "TARGET_MULHW"
1157 "maclhwu. %0, %1, %2"
1158 [(set_attr "type" "imul3")])
1160 (define_insn "*maclhwu"
1161 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1162 (plus:SI (mult:SI (zero_extend:SI
1163 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1164 (zero_extend:SI
1165 (match_operand:HI 2 "gpc_reg_operand" "r")))
1166 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1167 "TARGET_MULHW"
1168 "maclhwu %0, %1, %2"
1169 [(set_attr "type" "imul3")])
1171 (define_insn "*nmacchwc"
1172 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1173 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1174 (mult:SI (ashiftrt:SI
1175 (match_operand:SI 2 "gpc_reg_operand" "r")
1176 (const_int 16))
1177 (sign_extend:SI
1178 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1179 (const_int 0)))
1180 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1181 (minus:SI (match_dup 4)
1182 (mult:SI (ashiftrt:SI
1183 (match_dup 2)
1184 (const_int 16))
1185 (sign_extend:SI
1186 (match_dup 1)))))]
1187 "TARGET_MULHW"
1188 "nmacchw. %0, %1, %2"
1189 [(set_attr "type" "imul3")])
1191 (define_insn "*nmacchw"
1192 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1193 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1194 (mult:SI (ashiftrt:SI
1195 (match_operand:SI 2 "gpc_reg_operand" "r")
1196 (const_int 16))
1197 (sign_extend:SI
1198 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1199 "TARGET_MULHW"
1200 "nmacchw %0, %1, %2"
1201 [(set_attr "type" "imul3")])
1203 (define_insn "*nmachhwc"
1204 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1205 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1206 (mult:SI (ashiftrt:SI
1207 (match_operand:SI 1 "gpc_reg_operand" "%r")
1208 (const_int 16))
1209 (ashiftrt:SI
1210 (match_operand:SI 2 "gpc_reg_operand" "r")
1211 (const_int 16))))
1212 (const_int 0)))
1213 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1214 (minus:SI (match_dup 4)
1215 (mult:SI (ashiftrt:SI
1216 (match_dup 1)
1217 (const_int 16))
1218 (ashiftrt:SI
1219 (match_dup 2)
1220 (const_int 16)))))]
1221 "TARGET_MULHW"
1222 "nmachhw. %0, %1, %2"
1223 [(set_attr "type" "imul3")])
1225 (define_insn "*nmachhw"
1226 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1227 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1228 (mult:SI (ashiftrt:SI
1229 (match_operand:SI 1 "gpc_reg_operand" "%r")
1230 (const_int 16))
1231 (ashiftrt:SI
1232 (match_operand:SI 2 "gpc_reg_operand" "r")
1233 (const_int 16)))))]
1234 "TARGET_MULHW"
1235 "nmachhw %0, %1, %2"
1236 [(set_attr "type" "imul3")])
1238 (define_insn "*nmaclhwc"
1239 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1240 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1241 (mult:SI (sign_extend:SI
1242 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1243 (sign_extend:SI
1244 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1245 (const_int 0)))
1246 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1247 (minus:SI (match_dup 4)
1248 (mult:SI (sign_extend:SI
1249 (match_dup 1))
1250 (sign_extend:SI
1251 (match_dup 2)))))]
1252 "TARGET_MULHW"
1253 "nmaclhw. %0, %1, %2"
1254 [(set_attr "type" "imul3")])
1256 (define_insn "*nmaclhw"
1257 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1258 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1259 (mult:SI (sign_extend:SI
1260 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1261 (sign_extend:SI
1262 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1263 "TARGET_MULHW"
1264 "nmaclhw %0, %1, %2"
1265 [(set_attr "type" "imul3")])
1267 (define_insn "*mulchwc"
1268 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1269 (compare:CC (mult:SI (ashiftrt:SI
1270 (match_operand:SI 2 "gpc_reg_operand" "r")
1271 (const_int 16))
1272 (sign_extend:SI
1273 (match_operand:HI 1 "gpc_reg_operand" "r")))
1274 (const_int 0)))
1275 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1276 (mult:SI (ashiftrt:SI
1277 (match_dup 2)
1278 (const_int 16))
1279 (sign_extend:SI
1280 (match_dup 1))))]
1281 "TARGET_MULHW"
1282 "mulchw. %0, %1, %2"
1283 [(set_attr "type" "imul3")])
1285 (define_insn "*mulchw"
1286 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1287 (mult:SI (ashiftrt:SI
1288 (match_operand:SI 2 "gpc_reg_operand" "r")
1289 (const_int 16))
1290 (sign_extend:SI
1291 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1292 "TARGET_MULHW"
1293 "mulchw %0, %1, %2"
1294 [(set_attr "type" "imul3")])
1296 (define_insn "*mulchwuc"
1297 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1298 (compare:CC (mult:SI (lshiftrt:SI
1299 (match_operand:SI 2 "gpc_reg_operand" "r")
1300 (const_int 16))
1301 (zero_extend:SI
1302 (match_operand:HI 1 "gpc_reg_operand" "r")))
1303 (const_int 0)))
1304 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1305 (mult:SI (lshiftrt:SI
1306 (match_dup 2)
1307 (const_int 16))
1308 (zero_extend:SI
1309 (match_dup 1))))]
1310 "TARGET_MULHW"
1311 "mulchwu. %0, %1, %2"
1312 [(set_attr "type" "imul3")])
1314 (define_insn "*mulchwu"
1315 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1316 (mult:SI (lshiftrt:SI
1317 (match_operand:SI 2 "gpc_reg_operand" "r")
1318 (const_int 16))
1319 (zero_extend:SI
1320 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1321 "TARGET_MULHW"
1322 "mulchwu %0, %1, %2"
1323 [(set_attr "type" "imul3")])
1325 (define_insn "*mulhhwc"
1326 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1327 (compare:CC (mult:SI (ashiftrt:SI
1328 (match_operand:SI 1 "gpc_reg_operand" "%r")
1329 (const_int 16))
1330 (ashiftrt:SI
1331 (match_operand:SI 2 "gpc_reg_operand" "r")
1332 (const_int 16)))
1333 (const_int 0)))
1334 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1335 (mult:SI (ashiftrt:SI
1336 (match_dup 1)
1337 (const_int 16))
1338 (ashiftrt:SI
1339 (match_dup 2)
1340 (const_int 16))))]
1341 "TARGET_MULHW"
1342 "mulhhw. %0, %1, %2"
1343 [(set_attr "type" "imul3")])
1345 (define_insn "*mulhhw"
1346 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1347 (mult:SI (ashiftrt:SI
1348 (match_operand:SI 1 "gpc_reg_operand" "%r")
1349 (const_int 16))
1350 (ashiftrt:SI
1351 (match_operand:SI 2 "gpc_reg_operand" "r")
1352 (const_int 16))))]
1353 "TARGET_MULHW"
1354 "mulhhw %0, %1, %2"
1355 [(set_attr "type" "imul3")])
1357 (define_insn "*mulhhwuc"
1358 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1359 (compare:CC (mult:SI (lshiftrt:SI
1360 (match_operand:SI 1 "gpc_reg_operand" "%r")
1361 (const_int 16))
1362 (lshiftrt:SI
1363 (match_operand:SI 2 "gpc_reg_operand" "r")
1364 (const_int 16)))
1365 (const_int 0)))
1366 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1367 (mult:SI (lshiftrt:SI
1368 (match_dup 1)
1369 (const_int 16))
1370 (lshiftrt:SI
1371 (match_dup 2)
1372 (const_int 16))))]
1373 "TARGET_MULHW"
1374 "mulhhwu. %0, %1, %2"
1375 [(set_attr "type" "imul3")])
1377 (define_insn "*mulhhwu"
1378 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1379 (mult:SI (lshiftrt:SI
1380 (match_operand:SI 1 "gpc_reg_operand" "%r")
1381 (const_int 16))
1382 (lshiftrt:SI
1383 (match_operand:SI 2 "gpc_reg_operand" "r")
1384 (const_int 16))))]
1385 "TARGET_MULHW"
1386 "mulhhwu %0, %1, %2"
1387 [(set_attr "type" "imul3")])
1389 (define_insn "*mullhwc"
1390 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1391 (compare:CC (mult:SI (sign_extend:SI
1392 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1393 (sign_extend:SI
1394 (match_operand:HI 2 "gpc_reg_operand" "r")))
1395 (const_int 0)))
1396 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1397 (mult:SI (sign_extend:SI
1398 (match_dup 1))
1399 (sign_extend:SI
1400 (match_dup 2))))]
1401 "TARGET_MULHW"
1402 "mullhw. %0, %1, %2"
1403 [(set_attr "type" "imul3")])
1405 (define_insn "*mullhw"
1406 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1407 (mult:SI (sign_extend:SI
1408 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1409 (sign_extend:SI
1410 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1411 "TARGET_MULHW"
1412 "mullhw %0, %1, %2"
1413 [(set_attr "type" "imul3")])
1415 (define_insn "*mullhwuc"
1416 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1417 (compare:CC (mult:SI (zero_extend:SI
1418 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1419 (zero_extend:SI
1420 (match_operand:HI 2 "gpc_reg_operand" "r")))
1421 (const_int 0)))
1422 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1423 (mult:SI (zero_extend:SI
1424 (match_dup 1))
1425 (zero_extend:SI
1426 (match_dup 2))))]
1427 "TARGET_MULHW"
1428 "mullhwu. %0, %1, %2"
1429 [(set_attr "type" "imul3")])
1431 (define_insn "*mullhwu"
1432 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1433 (mult:SI (zero_extend:SI
1434 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1435 (zero_extend:SI
1436 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1437 "TARGET_MULHW"
1438 "mullhwu %0, %1, %2"
1439 [(set_attr "type" "imul3")])
1440 \f
1441 ;; IBM 405, 440 and 464 string-search dlmzb instruction support.
1442 (define_insn "dlmzb"
1443 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1444 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1445 (match_operand:SI 2 "gpc_reg_operand" "r")]
1446 UNSPEC_DLMZB_CR))
1447 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1448 (unspec:SI [(match_dup 1)
1449 (match_dup 2)]
1450 UNSPEC_DLMZB))]
1451 "TARGET_DLMZB"
1452 "dlmzb. %0, %1, %2")
1454 (define_expand "strlensi"
1455 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1456 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1457 (match_operand:QI 2 "const_int_operand" "")
1458 (match_operand 3 "const_int_operand" "")]
1459 UNSPEC_DLMZB_STRLEN))
1460 (clobber (match_scratch:CC 4 "=x"))]
1461 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1462 {
1463 rtx result = operands[0];
1464 rtx src = operands[1];
1465 rtx search_char = operands[2];
1466 rtx align = operands[3];
1467 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1468 rtx loop_label, end_label, mem, cr0, cond;
1469 if (search_char != const0_rtx
1470 || GET_CODE (align) != CONST_INT
1471 || INTVAL (align) < 8)
1472 FAIL;
1473 word1 = gen_reg_rtx (SImode);
1474 word2 = gen_reg_rtx (SImode);
1475 scratch_dlmzb = gen_reg_rtx (SImode);
1476 scratch_string = gen_reg_rtx (Pmode);
1477 loop_label = gen_label_rtx ();
1478 end_label = gen_label_rtx ();
1479 addr = force_reg (Pmode, XEXP (src, 0));
1480 emit_move_insn (scratch_string, addr);
1481 emit_label (loop_label);
1482 mem = change_address (src, SImode, scratch_string);
1483 emit_move_insn (word1, mem);
1484 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1485 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1486 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1487 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1488 emit_jump_insn (gen_rtx_SET (VOIDmode,
1489 pc_rtx,
1490 gen_rtx_IF_THEN_ELSE (VOIDmode,
1491 cond,
1492 gen_rtx_LABEL_REF
1493 (VOIDmode,
1494 end_label),
1495 pc_rtx)));
1496 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1497 emit_jump_insn (gen_rtx_SET (VOIDmode,
1498 pc_rtx,
1499 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1500 emit_barrier ();
1501 emit_label (end_label);
1502 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1503 emit_insn (gen_subsi3 (result, scratch_string, addr));
1504 emit_insn (gen_subsi3 (result, result, const1_rtx));
1505 DONE;
1506 })
1507 \f
1508 (define_split
1509 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1510 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1511 (const_int 0)))
1512 (set (match_operand:SI 0 "gpc_reg_operand" "")
1513 (sign_extend:SI (match_dup 1)))]
1514 "reload_completed"
1515 [(set (match_dup 0)
1516 (sign_extend:SI (match_dup 1)))
1517 (set (match_dup 2)
1518 (compare:CC (match_dup 0)
1519 (const_int 0)))]
1520 "")
1522 ;; Fixed-point arithmetic insns.
1524 (define_expand "add<mode>3"
1525 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1526 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1527 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1528 ""
1529 {
1530 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1531 {
1532 if (non_short_cint_operand (operands[2], DImode))
1533 FAIL;
1534 }
1535 else if (GET_CODE (operands[2]) == CONST_INT
1536 && ! add_operand (operands[2], <MODE>mode))
1537 {
1538 rtx tmp = ((!can_create_pseudo_p ()
1539 || rtx_equal_p (operands[0], operands[1]))
1540 ? operands[0] : gen_reg_rtx (<MODE>mode));
1542 HOST_WIDE_INT val = INTVAL (operands[2]);
1543 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1544 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1546 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1547 FAIL;
1549 /* The ordering here is important for the prolog expander.
1550 When space is allocated from the stack, adding 'low' first may
1551 produce a temporary deallocation (which would be bad). */
1552 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1553 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1554 DONE;
1555 }
1556 })
1558 ;; Discourage ai/addic because of carry but provide it in an alternative
1559 ;; allowing register zero as source.
1560 (define_insn "*add<mode>3_internal1"
1561 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1562 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1563 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1564 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1565 "@
1566 {cax|add} %0,%1,%2
1567 {cal %0,%2(%1)|addi %0,%1,%2}
1568 {ai|addic} %0,%1,%2
1569 {cau|addis} %0,%1,%v2"
1570 [(set_attr "length" "4,4,4,4")])
1572 (define_insn "addsi3_high"
1573 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1574 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1575 (high:SI (match_operand 2 "" ""))))]
1576 "TARGET_MACHO && !TARGET_64BIT"
1577 "{cau|addis} %0,%1,ha16(%2)"
1578 [(set_attr "length" "4")])
1580 (define_insn "*add<mode>3_internal2"
1581 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1582 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1583 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1584 (const_int 0)))
1585 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1586 ""
1587 "@
1588 {cax.|add.} %3,%1,%2
1589 {ai.|addic.} %3,%1,%2
1590 #
1591 #"
1592 [(set_attr "type" "fast_compare,compare,compare,compare")
1593 (set_attr "length" "4,4,8,8")])
1595 (define_split
1596 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1597 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1598 (match_operand:GPR 2 "reg_or_short_operand" ""))
1599 (const_int 0)))
1600 (clobber (match_scratch:GPR 3 ""))]
1601 "reload_completed"
1602 [(set (match_dup 3)
1603 (plus:GPR (match_dup 1)
1604 (match_dup 2)))
1605 (set (match_dup 0)
1606 (compare:CC (match_dup 3)
1607 (const_int 0)))]
1608 "")
1610 (define_insn "*add<mode>3_internal3"
1611 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1612 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1613 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1614 (const_int 0)))
1615 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1616 (plus:P (match_dup 1)
1617 (match_dup 2)))]
1618 ""
1619 "@
1620 {cax.|add.} %0,%1,%2
1621 {ai.|addic.} %0,%1,%2
1622 #
1623 #"
1624 [(set_attr "type" "fast_compare,compare,compare,compare")
1625 (set_attr "length" "4,4,8,8")])
1627 (define_split
1628 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1629 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1630 (match_operand:P 2 "reg_or_short_operand" ""))
1631 (const_int 0)))
1632 (set (match_operand:P 0 "gpc_reg_operand" "")
1633 (plus:P (match_dup 1) (match_dup 2)))]
1634 "reload_completed"
1635 [(set (match_dup 0)
1636 (plus:P (match_dup 1)
1637 (match_dup 2)))
1638 (set (match_dup 3)
1639 (compare:CC (match_dup 0)
1640 (const_int 0)))]
1641 "")
1643 ;; Split an add that we can't do in one insn into two insns, each of which
1644 ;; does one 16-bit part. This is used by combine. Note that the low-order
1645 ;; add should be last in case the result gets used in an address.
1647 (define_split
1648 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1649 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1650 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1651 ""
1652 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1653 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1654 {
1655 HOST_WIDE_INT val = INTVAL (operands[2]);
1656 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1657 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1659 operands[4] = GEN_INT (low);
1660 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1661 operands[3] = GEN_INT (rest);
1662 else if (can_create_pseudo_p ())
1663 {
1664 operands[3] = gen_reg_rtx (DImode);
1665 emit_move_insn (operands[3], operands[2]);
1666 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1667 DONE;
1668 }
1669 else
1670 FAIL;
1671 })
1673 (define_insn "one_cmpl<mode>2"
1674 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1675 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1676 ""
1677 "nor %0,%1,%1")
1679 (define_insn ""
1680 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1681 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1682 (const_int 0)))
1683 (clobber (match_scratch:P 2 "=r,r"))]
1684 ""
1685 "@
1686 nor. %2,%1,%1
1687 #"
1688 [(set_attr "type" "fast_compare,compare")
1689 (set_attr "length" "4,8")])
1691 (define_split
1692 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1693 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1694 (const_int 0)))
1695 (clobber (match_scratch:P 2 ""))]
1696 "reload_completed"
1697 [(set (match_dup 2)
1698 (not:P (match_dup 1)))
1699 (set (match_dup 0)
1700 (compare:CC (match_dup 2)
1701 (const_int 0)))]
1702 "")
1704 (define_insn ""
1705 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1706 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1707 (const_int 0)))
1708 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1709 (not:P (match_dup 1)))]
1710 ""
1711 "@
1712 nor. %0,%1,%1
1713 #"
1714 [(set_attr "type" "fast_compare,compare")
1715 (set_attr "length" "4,8")])
1717 (define_split
1718 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1719 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1720 (const_int 0)))
1721 (set (match_operand:P 0 "gpc_reg_operand" "")
1722 (not:P (match_dup 1)))]
1723 "reload_completed"
1724 [(set (match_dup 0)
1725 (not:P (match_dup 1)))
1726 (set (match_dup 2)
1727 (compare:CC (match_dup 0)
1728 (const_int 0)))]
1729 "")
1731 (define_insn ""
1732 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1733 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1734 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1735 "! TARGET_POWERPC"
1736 "{sf%I1|subf%I1c} %0,%2,%1")
1738 (define_insn ""
1739 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1740 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1741 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1742 "TARGET_POWERPC"
1743 "@
1744 subf %0,%2,%1
1745 subfic %0,%2,%1")
1747 (define_insn ""
1748 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1749 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1750 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1751 (const_int 0)))
1752 (clobber (match_scratch:SI 3 "=r,r"))]
1753 "! TARGET_POWERPC"
1754 "@
1755 {sf.|subfc.} %3,%2,%1
1756 #"
1757 [(set_attr "type" "compare")
1758 (set_attr "length" "4,8")])
1760 (define_insn ""
1761 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1762 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1763 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1764 (const_int 0)))
1765 (clobber (match_scratch:P 3 "=r,r"))]
1766 "TARGET_POWERPC"
1767 "@
1768 subf. %3,%2,%1
1769 #"
1770 [(set_attr "type" "fast_compare")
1771 (set_attr "length" "4,8")])
1773 (define_split
1774 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1775 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1776 (match_operand:P 2 "gpc_reg_operand" ""))
1777 (const_int 0)))
1778 (clobber (match_scratch:P 3 ""))]
1779 "reload_completed"
1780 [(set (match_dup 3)
1781 (minus:P (match_dup 1)
1782 (match_dup 2)))
1783 (set (match_dup 0)
1784 (compare:CC (match_dup 3)
1785 (const_int 0)))]
1786 "")
1788 (define_insn ""
1789 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1790 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1791 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1792 (const_int 0)))
1793 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1794 (minus:SI (match_dup 1) (match_dup 2)))]
1795 "! TARGET_POWERPC"
1796 "@
1797 {sf.|subfc.} %0,%2,%1
1798 #"
1799 [(set_attr "type" "compare")
1800 (set_attr "length" "4,8")])
1802 (define_insn ""
1803 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1804 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1805 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1806 (const_int 0)))
1807 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1808 (minus:P (match_dup 1)
1809 (match_dup 2)))]
1810 "TARGET_POWERPC"
1811 "@
1812 subf. %0,%2,%1
1813 #"
1814 [(set_attr "type" "fast_compare")
1815 (set_attr "length" "4,8")])
1817 (define_split
1818 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1819 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1820 (match_operand:P 2 "gpc_reg_operand" ""))
1821 (const_int 0)))
1822 (set (match_operand:P 0 "gpc_reg_operand" "")
1823 (minus:P (match_dup 1)
1824 (match_dup 2)))]
1825 "reload_completed"
1826 [(set (match_dup 0)
1827 (minus:P (match_dup 1)
1828 (match_dup 2)))
1829 (set (match_dup 3)
1830 (compare:CC (match_dup 0)
1831 (const_int 0)))]
1832 "")
1834 (define_expand "sub<mode>3"
1835 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1836 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1837 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1838 ""
1839 "
1840 {
1841 if (GET_CODE (operands[2]) == CONST_INT)
1842 {
1843 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1844 negate_rtx (<MODE>mode, operands[2])));
1845 DONE;
1846 }
1847 }")
1849 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1850 ;; instruction and some auxiliary computations. Then we just have a single
1851 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1852 ;; combine.
1854 (define_expand "sminsi3"
1855 [(set (match_dup 3)
1856 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1857 (match_operand:SI 2 "reg_or_short_operand" ""))
1858 (const_int 0)
1859 (minus:SI (match_dup 2) (match_dup 1))))
1860 (set (match_operand:SI 0 "gpc_reg_operand" "")
1861 (minus:SI (match_dup 2) (match_dup 3)))]
1862 "TARGET_POWER || TARGET_ISEL"
1863 "
1864 {
1865 if (TARGET_ISEL)
1866 {
1867 operands[2] = force_reg (SImode, operands[2]);
1868 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1869 DONE;
1870 }
1872 operands[3] = gen_reg_rtx (SImode);
1873 }")
1875 (define_split
1876 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1877 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1878 (match_operand:SI 2 "reg_or_short_operand" "")))
1879 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1880 "TARGET_POWER"
1881 [(set (match_dup 3)
1882 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1883 (const_int 0)
1884 (minus:SI (match_dup 2) (match_dup 1))))
1885 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1886 "")
1888 (define_expand "smaxsi3"
1889 [(set (match_dup 3)
1890 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1891 (match_operand:SI 2 "reg_or_short_operand" ""))
1892 (const_int 0)
1893 (minus:SI (match_dup 2) (match_dup 1))))
1894 (set (match_operand:SI 0 "gpc_reg_operand" "")
1895 (plus:SI (match_dup 3) (match_dup 1)))]
1896 "TARGET_POWER || TARGET_ISEL"
1897 "
1898 {
1899 if (TARGET_ISEL)
1900 {
1901 operands[2] = force_reg (SImode, operands[2]);
1902 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1903 DONE;
1904 }
1905 operands[3] = gen_reg_rtx (SImode);
1906 }")
1908 (define_split
1909 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1910 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1911 (match_operand:SI 2 "reg_or_short_operand" "")))
1912 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1913 "TARGET_POWER"
1914 [(set (match_dup 3)
1915 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1916 (const_int 0)
1917 (minus:SI (match_dup 2) (match_dup 1))))
1918 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1919 "")
1921 (define_expand "uminsi3"
1922 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1923 (match_dup 5)))
1924 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1925 (match_dup 5)))
1926 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1927 (const_int 0)
1928 (minus:SI (match_dup 4) (match_dup 3))))
1929 (set (match_operand:SI 0 "gpc_reg_operand" "")
1930 (minus:SI (match_dup 2) (match_dup 3)))]
1931 "TARGET_POWER || TARGET_ISEL"
1932 "
1933 {
1934 if (TARGET_ISEL)
1935 {
1936 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1937 DONE;
1938 }
1939 operands[3] = gen_reg_rtx (SImode);
1940 operands[4] = gen_reg_rtx (SImode);
1941 operands[5] = GEN_INT (-2147483647 - 1);
1942 }")
1944 (define_expand "umaxsi3"
1945 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1946 (match_dup 5)))
1947 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1948 (match_dup 5)))
1949 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1950 (const_int 0)
1951 (minus:SI (match_dup 4) (match_dup 3))))
1952 (set (match_operand:SI 0 "gpc_reg_operand" "")
1953 (plus:SI (match_dup 3) (match_dup 1)))]
1954 "TARGET_POWER || TARGET_ISEL"
1955 "
1956 {
1957 if (TARGET_ISEL)
1958 {
1959 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1960 DONE;
1961 }
1962 operands[3] = gen_reg_rtx (SImode);
1963 operands[4] = gen_reg_rtx (SImode);
1964 operands[5] = GEN_INT (-2147483647 - 1);
1965 }")
1967 (define_insn ""
1968 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1969 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1970 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1971 (const_int 0)
1972 (minus:SI (match_dup 2) (match_dup 1))))]
1973 "TARGET_POWER"
1974 "doz%I2 %0,%1,%2")
1976 (define_insn ""
1977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1978 (compare:CC
1979 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1980 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1981 (const_int 0)
1982 (minus:SI (match_dup 2) (match_dup 1)))
1983 (const_int 0)))
1984 (clobber (match_scratch:SI 3 "=r,r"))]
1985 "TARGET_POWER"
1986 "@
1987 doz%I2. %3,%1,%2
1988 #"
1989 [(set_attr "type" "delayed_compare")
1990 (set_attr "length" "4,8")])
1992 (define_split
1993 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1994 (compare:CC
1995 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1996 (match_operand:SI 2 "reg_or_short_operand" ""))
1997 (const_int 0)
1998 (minus:SI (match_dup 2) (match_dup 1)))
1999 (const_int 0)))
2000 (clobber (match_scratch:SI 3 ""))]
2001 "TARGET_POWER && reload_completed"
2002 [(set (match_dup 3)
2003 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2004 (const_int 0)
2005 (minus:SI (match_dup 2) (match_dup 1))))
2006 (set (match_dup 0)
2007 (compare:CC (match_dup 3)
2008 (const_int 0)))]
2009 "")
2011 (define_insn ""
2012 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2013 (compare:CC
2014 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2015 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2016 (const_int 0)
2017 (minus:SI (match_dup 2) (match_dup 1)))
2018 (const_int 0)))
2019 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2020 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2021 (const_int 0)
2022 (minus:SI (match_dup 2) (match_dup 1))))]
2023 "TARGET_POWER"
2024 "@
2025 doz%I2. %0,%1,%2
2026 #"
2027 [(set_attr "type" "delayed_compare")
2028 (set_attr "length" "4,8")])
2030 (define_split
2031 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2032 (compare:CC
2033 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2034 (match_operand:SI 2 "reg_or_short_operand" ""))
2035 (const_int 0)
2036 (minus:SI (match_dup 2) (match_dup 1)))
2037 (const_int 0)))
2038 (set (match_operand:SI 0 "gpc_reg_operand" "")
2039 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2040 (const_int 0)
2041 (minus:SI (match_dup 2) (match_dup 1))))]
2042 "TARGET_POWER && reload_completed"
2043 [(set (match_dup 0)
2044 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2045 (const_int 0)
2046 (minus:SI (match_dup 2) (match_dup 1))))
2047 (set (match_dup 3)
2048 (compare:CC (match_dup 0)
2049 (const_int 0)))]
2050 "")
2052 ;; We don't need abs with condition code because such comparisons should
2053 ;; never be done.
2054 (define_expand "abssi2"
2055 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2056 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2057 ""
2058 "
2059 {
2060 if (TARGET_ISEL)
2061 {
2062 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2063 DONE;
2064 }
2065 else if (! TARGET_POWER)
2066 {
2067 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2068 DONE;
2069 }
2070 }")
2072 (define_insn "*abssi2_power"
2073 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2074 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2075 "TARGET_POWER"
2076 "abs %0,%1")
2078 (define_insn_and_split "abssi2_isel"
2079 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2080 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2081 (clobber (match_scratch:SI 2 "=&b"))
2082 (clobber (match_scratch:CC 3 "=y"))]
2083 "TARGET_ISEL"
2084 "#"
2085 "&& reload_completed"
2086 [(set (match_dup 2) (neg:SI (match_dup 1)))
2087 (set (match_dup 3)
2088 (compare:CC (match_dup 1)
2089 (const_int 0)))
2090 (set (match_dup 0)
2091 (if_then_else:SI (ge (match_dup 3)
2092 (const_int 0))
2093 (match_dup 1)
2094 (match_dup 2)))]
2095 "")
2097 (define_insn_and_split "abssi2_nopower"
2098 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2099 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2100 (clobber (match_scratch:SI 2 "=&r,&r"))]
2101 "! TARGET_POWER && ! TARGET_ISEL"
2102 "#"
2103 "&& reload_completed"
2104 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2105 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2106 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2107 "")
2109 (define_insn "*nabs_power"
2110 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2111 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2112 "TARGET_POWER"
2113 "nabs %0,%1")
2115 (define_insn_and_split "*nabs_nopower"
2116 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2117 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2118 (clobber (match_scratch:SI 2 "=&r,&r"))]
2119 "! TARGET_POWER"
2120 "#"
2121 "&& reload_completed"
2122 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2123 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2124 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2125 "")
2127 (define_expand "neg<mode>2"
2128 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2129 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2130 ""
2131 "")
2133 (define_insn "*neg<mode>2_internal"
2134 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2135 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2136 ""
2137 "neg %0,%1")
2139 (define_insn ""
2140 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2141 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2142 (const_int 0)))
2143 (clobber (match_scratch:P 2 "=r,r"))]
2144 ""
2145 "@
2146 neg. %2,%1
2147 #"
2148 [(set_attr "type" "fast_compare")
2149 (set_attr "length" "4,8")])
2151 (define_split
2152 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2153 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2154 (const_int 0)))
2155 (clobber (match_scratch:P 2 ""))]
2156 "reload_completed"
2157 [(set (match_dup 2)
2158 (neg:P (match_dup 1)))
2159 (set (match_dup 0)
2160 (compare:CC (match_dup 2)
2161 (const_int 0)))]
2162 "")
2164 (define_insn ""
2165 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2166 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2167 (const_int 0)))
2168 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2169 (neg:P (match_dup 1)))]
2170 ""
2171 "@
2172 neg. %0,%1
2173 #"
2174 [(set_attr "type" "fast_compare")
2175 (set_attr "length" "4,8")])
2177 (define_split
2178 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2179 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2180 (const_int 0)))
2181 (set (match_operand:P 0 "gpc_reg_operand" "")
2182 (neg:P (match_dup 1)))]
2183 "reload_completed"
2184 [(set (match_dup 0)
2185 (neg:P (match_dup 1)))
2186 (set (match_dup 2)
2187 (compare:CC (match_dup 0)
2188 (const_int 0)))]
2189 "")
2191 (define_insn "clz<mode>2"
2192 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2193 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2194 ""
2195 "{cntlz|cntlz<wd>} %0,%1"
2196 [(set_attr "type" "cntlz")])
2198 (define_expand "ctz<mode>2"
2199 [(set (match_dup 2)
2200 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2201 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2202 (match_dup 2)))
2203 (clobber (scratch:CC))])
2204 (set (match_dup 4) (clz:GPR (match_dup 3)))
2205 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2206 (minus:GPR (match_dup 5) (match_dup 4)))]
2207 ""
2208 {
2209 operands[2] = gen_reg_rtx (<MODE>mode);
2210 operands[3] = gen_reg_rtx (<MODE>mode);
2211 operands[4] = gen_reg_rtx (<MODE>mode);
2212 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2213 })
2215 (define_expand "ffs<mode>2"
2216 [(set (match_dup 2)
2217 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2218 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2219 (match_dup 2)))
2220 (clobber (scratch:CC))])
2221 (set (match_dup 4) (clz:GPR (match_dup 3)))
2222 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2223 (minus:GPR (match_dup 5) (match_dup 4)))]
2224 ""
2225 {
2226 operands[2] = gen_reg_rtx (<MODE>mode);
2227 operands[3] = gen_reg_rtx (<MODE>mode);
2228 operands[4] = gen_reg_rtx (<MODE>mode);
2229 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2230 })
2232 (define_insn "popcntb<mode>2"
2233 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2234 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2235 UNSPEC_POPCNTB))]
2236 "TARGET_POPCNTB"
2237 "popcntb %0,%1")
2239 (define_insn "popcntwsi2"
2240 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2241 (popcount:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2242 "TARGET_POPCNTD"
2243 "popcntw %0,%1")
2245 (define_insn "popcntddi2"
2246 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2247 (popcount:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
2248 "TARGET_POPCNTD && TARGET_POWERPC64"
2249 "popcntd %0,%1")
2251 (define_expand "popcount<mode>2"
2252 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2253 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2254 "TARGET_POPCNTB || TARGET_POPCNTD"
2255 {
2256 rs6000_emit_popcount (operands[0], operands[1]);
2257 DONE;
2258 })
2260 (define_expand "parity<mode>2"
2261 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2262 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2263 "TARGET_POPCNTB"
2264 {
2265 rs6000_emit_parity (operands[0], operands[1]);
2266 DONE;
2267 })
2269 ;; Since the hardware zeros the upper part of the register, save generating the
2270 ;; AND immediate if we are converting to unsigned
2271 (define_insn "*bswaphi2_extenddi"
2272 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2273 (zero_extend:DI
2274 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2275 "TARGET_POWERPC64"
2276 "lhbrx %0,%y1"
2277 [(set_attr "length" "4")
2278 (set_attr "type" "load")])
2280 (define_insn "*bswaphi2_extendsi"
2281 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2282 (zero_extend:SI
2283 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2284 "TARGET_POWERPC"
2285 "lhbrx %0,%y1"
2286 [(set_attr "length" "4")
2287 (set_attr "type" "load")])
2289 (define_expand "bswaphi2"
2290 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2291 (bswap:HI
2292 (match_operand:HI 1 "reg_or_mem_operand" "")))
2293 (clobber (match_scratch:SI 2 ""))])]
2294 ""
2295 {
2296 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2297 operands[1] = force_reg (HImode, operands[1]);
2298 })
2300 (define_insn "bswaphi2_internal"
2301 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2302 (bswap:HI
2303 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2304 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2305 "TARGET_POWERPC"
2306 "@
2307 lhbrx %0,%y1
2308 sthbrx %1,%y0
2309 #"
2310 [(set_attr "length" "4,4,12")
2311 (set_attr "type" "load,store,*")])
2313 (define_split
2314 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2315 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2316 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2317 "TARGET_POWERPC && reload_completed"
2318 [(set (match_dup 3)
2319 (zero_extract:SI (match_dup 4)
2320 (const_int 8)
2321 (const_int 16)))
2322 (set (match_dup 2)
2323 (and:SI (ashift:SI (match_dup 4)
2324 (const_int 8))
2325 (const_int 65280))) ;; 0xff00
2326 (set (match_dup 3)
2327 (ior:SI (match_dup 3)
2328 (match_dup 2)))]
2329 "
2330 {
2331 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2332 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2333 }")
2335 (define_insn "*bswapsi2_extenddi"
2336 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2337 (zero_extend:DI
2338 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2339 "TARGET_POWERPC64"
2340 "lwbrx %0,%y1"
2341 [(set_attr "length" "4")
2342 (set_attr "type" "load")])
2344 (define_expand "bswapsi2"
2345 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2346 (bswap:SI
2347 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2348 ""
2349 {
2350 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2351 operands[1] = force_reg (SImode, operands[1]);
2352 })
2354 (define_insn "*bswapsi2_internal"
2355 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2356 (bswap:SI
2357 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2358 ""
2359 "@
2360 {lbrx|lwbrx} %0,%y1
2361 {stbrx|stwbrx} %1,%y0
2362 #"
2363 [(set_attr "length" "4,4,12")
2364 (set_attr "type" "load,store,*")])
2366 (define_split
2367 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2368 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2369 "reload_completed"
2370 [(set (match_dup 0)
2371 (rotate:SI (match_dup 1) (const_int 8)))
2372 (set (zero_extract:SI (match_dup 0)
2373 (const_int 8)
2374 (const_int 0))
2375 (match_dup 1))
2376 (set (zero_extract:SI (match_dup 0)
2377 (const_int 8)
2378 (const_int 16))
2379 (rotate:SI (match_dup 1)
2380 (const_int 16)))]
2381 "")
2383 (define_expand "bswapdi2"
2384 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2385 (bswap:DI
2386 (match_operand:DI 1 "reg_or_mem_operand" "")))
2387 (clobber (match_scratch:DI 2 ""))
2388 (clobber (match_scratch:DI 3 ""))
2389 (clobber (match_scratch:DI 4 ""))])]
2390 ""
2391 {
2392 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2393 operands[1] = force_reg (DImode, operands[1]);
2395 if (TARGET_32BIT)
2396 {
2397 /* 32-bit needs fewer scratch registers. */
2398 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2399 DONE;
2400 }
2401 })
2403 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2404 (define_insn "*bswapdi2_ldbrx"
2405 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2406 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2407 (clobber (match_scratch:DI 2 "=X,X,&r"))
2408 (clobber (match_scratch:DI 3 "=X,X,&r"))
2409 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2410 "TARGET_POWERPC64 && TARGET_LDBRX
2411 && (REG_P (operands[0]) || REG_P (operands[1]))"
2412 "@
2413 ldbrx %0,%y1
2414 stdbrx %1,%y0
2415 #"
2416 [(set_attr "length" "4,4,36")
2417 (set_attr "type" "load,store,*")])
2419 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2420 (define_insn "*bswapdi2_64bit"
2421 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2422 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2423 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2424 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2425 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2426 "TARGET_POWERPC64 && !TARGET_LDBRX
2427 && (REG_P (operands[0]) || REG_P (operands[1]))"
2428 "#"
2429 [(set_attr "length" "16,12,36")])
2431 (define_split
2432 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2433 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2434 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2435 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2436 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2437 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2438 [(const_int 0)]
2439 "
2440 {
2441 rtx dest = operands[0];
2442 rtx src = operands[1];
2443 rtx op2 = operands[2];
2444 rtx op3 = operands[3];
2445 rtx op4 = operands[4];
2446 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2447 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2448 rtx addr1;
2449 rtx addr2;
2450 rtx word_high;
2451 rtx word_low;
2453 addr1 = XEXP (src, 0);
2454 if (GET_CODE (addr1) == PLUS)
2455 {
2456 emit_insn (gen_adddi3 (op2, XEXP (addr1, 0), GEN_INT (4)));
2457 addr2 = gen_rtx_PLUS (DImode, op2, XEXP (addr1, 1));
2458 }
2459 else
2460 {
2461 emit_move_insn (op2, GEN_INT (4));
2462 addr2 = gen_rtx_PLUS (DImode, op2, addr1);
2463 }
2465 if (BYTES_BIG_ENDIAN)
2466 {
2467 word_high = change_address (src, SImode, addr1);
2468 word_low = change_address (src, SImode, addr2);
2469 }
2470 else
2471 {
2472 word_high = change_address (src, SImode, addr2);
2473 word_low = change_address (src, SImode, addr1);
2474 }
2476 emit_insn (gen_bswapsi2 (op3_32, word_low));
2477 emit_insn (gen_bswapsi2 (op4_32, word_high));
2478 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2479 emit_insn (gen_iordi3 (dest, dest, op4));
2480 }")
2482 (define_split
2483 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2484 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2485 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2486 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2487 (clobber (match_operand:DI 4 "" ""))]
2488 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2489 [(const_int 0)]
2490 "
2491 {
2492 rtx dest = operands[0];
2493 rtx src = operands[1];
2494 rtx op2 = operands[2];
2495 rtx op3 = operands[3];
2496 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2497 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2498 rtx addr1;
2499 rtx addr2;
2500 rtx word_high;
2501 rtx word_low;
2503 addr1 = XEXP (dest, 0);
2504 if (GET_CODE (addr1) == PLUS)
2505 {
2506 emit_insn (gen_adddi3 (op2, XEXP (addr1, 0), GEN_INT (4)));
2507 addr2 = gen_rtx_PLUS (DImode, op2, XEXP (addr1, 1));
2508 }
2509 else
2510 {
2511 emit_move_insn (op2, GEN_INT (4));
2512 addr2 = gen_rtx_PLUS (DImode, op2, addr1);
2513 }
2515 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2516 if (BYTES_BIG_ENDIAN)
2517 {
2518 word_high = change_address (dest, SImode, addr1);
2519 word_low = change_address (dest, SImode, addr2);
2520 emit_insn (gen_bswapsi2 (word_high, src_si));
2521 emit_insn (gen_bswapsi2 (word_low, op3_si));
2522 }
2523 else
2524 {
2525 word_high = change_address (dest, SImode, addr2);
2526 word_low = change_address (dest, SImode, addr1);
2527 emit_insn (gen_bswapsi2 (word_low, src_si));
2528 emit_insn (gen_bswapsi2 (word_high, op3_si));
2529 }
2530 }")
2532 (define_split
2533 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2534 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2535 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2536 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2537 (clobber (match_operand:DI 4 "" ""))]
2538 "TARGET_POWERPC64 && reload_completed"
2539 [(const_int 0)]
2540 "
2541 {
2542 rtx dest = operands[0];
2543 rtx src = operands[1];
2544 rtx op2 = operands[2];
2545 rtx op3 = operands[3];
2546 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2547 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2548 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2549 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2551 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2552 emit_insn (gen_bswapsi2 (dest_si, src_si));
2553 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2554 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2555 emit_insn (gen_iordi3 (dest, dest, op3));
2556 }")
2558 (define_insn "bswapdi2_32bit"
2559 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2560 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2561 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2562 "TARGET_32BIT && (REG_P (operands[0]) || REG_P (operands[1]))"
2563 "#"
2564 [(set_attr "length" "16,12,36")])
2566 (define_split
2567 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2568 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2569 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2570 "TARGET_32BIT && reload_completed"
2571 [(const_int 0)]
2572 "
2573 {
2574 rtx dest = operands[0];
2575 rtx src = operands[1];
2576 rtx op2 = operands[2];
2577 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2578 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2579 rtx addr1;
2580 rtx addr2;
2581 rtx word_high;
2582 rtx word_low;
2584 addr1 = XEXP (src, 0);
2585 if (GET_CODE (addr1) == PLUS)
2586 {
2587 emit_insn (gen_addsi3 (op2, XEXP (addr1, 0), GEN_INT (4)));
2588 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2589 }
2590 else
2591 {
2592 emit_move_insn (op2, GEN_INT (4));
2593 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2594 }
2596 if (BYTES_BIG_ENDIAN)
2597 {
2598 word_high = change_address (src, SImode, addr1);
2599 word_low = change_address (src, SImode, addr2);
2600 }
2601 else
2602 {
2603 word_high = change_address (src, SImode, addr2);
2604 word_low = change_address (src, SImode, addr1);
2605 }
2607 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2608 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2609 }")
2611 (define_split
2612 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2613 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2614 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2615 "TARGET_32BIT && reload_completed"
2616 [(const_int 0)]
2617 "
2618 {
2619 rtx dest = operands[0];
2620 rtx src = operands[1];
2621 rtx op2 = operands[2];
2622 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2623 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2624 rtx addr1;
2625 rtx addr2;
2626 rtx word_high;
2627 rtx word_low;
2629 addr1 = XEXP (dest, 0);
2630 if (GET_CODE (addr1) == PLUS)
2631 {
2632 emit_insn (gen_addsi3 (op2, XEXP (addr1, 0), GEN_INT (4)));
2633 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2634 }
2635 else
2636 {
2637 emit_move_insn (op2, GEN_INT (4));
2638 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2639 }
2641 if (BYTES_BIG_ENDIAN)
2642 {
2643 word_high = change_address (dest, SImode, addr1);
2644 word_low = change_address (dest, SImode, addr2);
2645 }
2646 else
2647 {
2648 word_high = change_address (dest, SImode, addr2);
2649 word_low = change_address (dest, SImode, addr1);
2650 }
2652 emit_insn (gen_bswapsi2 (word_high, src_low));
2653 emit_insn (gen_bswapsi2 (word_low, src_high));
2654 }")
2656 (define_split
2657 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2658 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2659 (clobber (match_operand:SI 2 "" ""))]
2660 "TARGET_32BIT && reload_completed"
2661 [(const_int 0)]
2662 "
2663 {
2664 rtx dest = operands[0];
2665 rtx src = operands[1];
2666 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2667 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2668 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2669 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2671 emit_insn (gen_bswapsi2 (dest_high, src_low));
2672 emit_insn (gen_bswapsi2 (dest_low, src_high));
2673 }")
2675 (define_expand "mulsi3"
2676 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2677 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2678 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2679 ""
2680 "
2681 {
2682 if (TARGET_POWER)
2683 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2684 else
2685 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2686 DONE;
2687 }")
2689 (define_insn "mulsi3_mq"
2690 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2691 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2692 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2693 (clobber (match_scratch:SI 3 "=q,q"))]
2694 "TARGET_POWER"
2695 "@
2696 {muls|mullw} %0,%1,%2
2697 {muli|mulli} %0,%1,%2"
2698 [(set (attr "type")
2699 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2700 (const_string "imul3")
2701 (match_operand:SI 2 "short_cint_operand" "")
2702 (const_string "imul2")]
2703 (const_string "imul")))])
2705 (define_insn "mulsi3_no_mq"
2706 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2707 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2708 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2709 "! TARGET_POWER"
2710 "@
2711 {muls|mullw} %0,%1,%2
2712 {muli|mulli} %0,%1,%2"
2713 [(set (attr "type")
2714 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2715 (const_string "imul3")
2716 (match_operand:SI 2 "short_cint_operand" "")
2717 (const_string "imul2")]
2718 (const_string "imul")))])
2720 (define_insn "*mulsi3_mq_internal1"
2721 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2722 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2723 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2724 (const_int 0)))
2725 (clobber (match_scratch:SI 3 "=r,r"))
2726 (clobber (match_scratch:SI 4 "=q,q"))]
2727 "TARGET_POWER"
2728 "@
2729 {muls.|mullw.} %3,%1,%2
2730 #"
2731 [(set_attr "type" "imul_compare")
2732 (set_attr "length" "4,8")])
2734 (define_split
2735 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2736 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2737 (match_operand:SI 2 "gpc_reg_operand" ""))
2738 (const_int 0)))
2739 (clobber (match_scratch:SI 3 ""))
2740 (clobber (match_scratch:SI 4 ""))]
2741 "TARGET_POWER && reload_completed"
2742 [(parallel [(set (match_dup 3)
2743 (mult:SI (match_dup 1) (match_dup 2)))
2744 (clobber (match_dup 4))])
2745 (set (match_dup 0)
2746 (compare:CC (match_dup 3)
2747 (const_int 0)))]
2748 "")
2750 (define_insn "*mulsi3_no_mq_internal1"
2751 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2752 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2753 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2754 (const_int 0)))
2755 (clobber (match_scratch:SI 3 "=r,r"))]
2756 "! TARGET_POWER"
2757 "@
2758 {muls.|mullw.} %3,%1,%2
2759 #"
2760 [(set_attr "type" "imul_compare")
2761 (set_attr "length" "4,8")])
2763 (define_split
2764 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2765 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2766 (match_operand:SI 2 "gpc_reg_operand" ""))
2767 (const_int 0)))
2768 (clobber (match_scratch:SI 3 ""))]
2769 "! TARGET_POWER && reload_completed"
2770 [(set (match_dup 3)
2771 (mult:SI (match_dup 1) (match_dup 2)))
2772 (set (match_dup 0)
2773 (compare:CC (match_dup 3)
2774 (const_int 0)))]
2775 "")
2777 (define_insn "*mulsi3_mq_internal2"
2778 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2779 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2780 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2781 (const_int 0)))
2782 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2783 (mult:SI (match_dup 1) (match_dup 2)))
2784 (clobber (match_scratch:SI 4 "=q,q"))]
2785 "TARGET_POWER"
2786 "@
2787 {muls.|mullw.} %0,%1,%2
2788 #"
2789 [(set_attr "type" "imul_compare")
2790 (set_attr "length" "4,8")])
2792 (define_split
2793 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2794 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2795 (match_operand:SI 2 "gpc_reg_operand" ""))
2796 (const_int 0)))
2797 (set (match_operand:SI 0 "gpc_reg_operand" "")
2798 (mult:SI (match_dup 1) (match_dup 2)))
2799 (clobber (match_scratch:SI 4 ""))]
2800 "TARGET_POWER && reload_completed"
2801 [(parallel [(set (match_dup 0)
2802 (mult:SI (match_dup 1) (match_dup 2)))
2803 (clobber (match_dup 4))])
2804 (set (match_dup 3)
2805 (compare:CC (match_dup 0)
2806 (const_int 0)))]
2807 "")
2809 (define_insn "*mulsi3_no_mq_internal2"
2810 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2811 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2812 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2813 (const_int 0)))
2814 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2815 (mult:SI (match_dup 1) (match_dup 2)))]
2816 "! TARGET_POWER"
2817 "@
2818 {muls.|mullw.} %0,%1,%2
2819 #"
2820 [(set_attr "type" "imul_compare")
2821 (set_attr "length" "4,8")])
2823 (define_split
2824 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2825 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2826 (match_operand:SI 2 "gpc_reg_operand" ""))
2827 (const_int 0)))
2828 (set (match_operand:SI 0 "gpc_reg_operand" "")
2829 (mult:SI (match_dup 1) (match_dup 2)))]
2830 "! TARGET_POWER && reload_completed"
2831 [(set (match_dup 0)
2832 (mult:SI (match_dup 1) (match_dup 2)))
2833 (set (match_dup 3)
2834 (compare:CC (match_dup 0)
2835 (const_int 0)))]
2836 "")
2838 ;; Operand 1 is divided by operand 2; quotient goes to operand
2839 ;; 0 and remainder to operand 3.
2840 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2842 (define_expand "divmodsi4"
2843 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2844 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2845 (match_operand:SI 2 "gpc_reg_operand" "")))
2846 (set (match_operand:SI 3 "register_operand" "")
2847 (mod:SI (match_dup 1) (match_dup 2)))])]
2848 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2849 "
2850 {
2851 if (! TARGET_POWER && ! TARGET_POWERPC)
2852 {
2853 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2854 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2855 emit_insn (gen_divss_call ());
2856 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2857 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2858 DONE;
2859 }
2860 }")
2862 (define_insn "*divmodsi4_internal"
2863 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2864 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2865 (match_operand:SI 2 "gpc_reg_operand" "r")))
2866 (set (match_operand:SI 3 "register_operand" "=q")
2867 (mod:SI (match_dup 1) (match_dup 2)))]
2868 "TARGET_POWER"
2869 "divs %0,%1,%2"
2870 [(set_attr "type" "idiv")])
2872 (define_expand "udiv<mode>3"
2873 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2874 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2875 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2876 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2877 "
2878 {
2879 if (! TARGET_POWER && ! TARGET_POWERPC)
2880 {
2881 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2882 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2883 emit_insn (gen_quous_call ());
2884 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2885 DONE;
2886 }
2887 else if (TARGET_POWER)
2888 {
2889 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2890 DONE;
2891 }
2892 }")
2894 (define_insn "udivsi3_mq"
2895 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2896 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2897 (match_operand:SI 2 "gpc_reg_operand" "r")))
2898 (clobber (match_scratch:SI 3 "=q"))]
2899 "TARGET_POWERPC && TARGET_POWER"
2900 "divwu %0,%1,%2"
2901 [(set_attr "type" "idiv")])
2903 (define_insn "*udivsi3_no_mq"
2904 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2905 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2906 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2907 "TARGET_POWERPC && ! TARGET_POWER"
2908 "div<wd>u %0,%1,%2"
2909 [(set (attr "type")
2910 (cond [(match_operand:SI 0 "" "")
2911 (const_string "idiv")]
2912 (const_string "ldiv")))])
2915 ;; For powers of two we can do srai/aze for divide and then adjust for
2916 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2917 ;; used; for PowerPC, force operands into register and do a normal divide;
2918 ;; for AIX common-mode, use quoss call on register operands.
2919 (define_expand "div<mode>3"
2920 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2921 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2922 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2923 ""
2924 "
2925 {
2926 if (GET_CODE (operands[2]) == CONST_INT
2927 && INTVAL (operands[2]) > 0
2928 && exact_log2 (INTVAL (operands[2])) >= 0)
2929 ;
2930 else if (TARGET_POWERPC)
2931 {
2932 operands[2] = force_reg (<MODE>mode, operands[2]);
2933 if (TARGET_POWER)
2934 {
2935 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2936 DONE;
2937 }
2938 }
2939 else if (TARGET_POWER)
2940 FAIL;
2941 else
2942 {
2943 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2944 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2945 emit_insn (gen_quoss_call ());
2946 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2947 DONE;
2948 }
2949 }")
2951 (define_insn "divsi3_mq"
2952 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2953 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2954 (match_operand:SI 2 "gpc_reg_operand" "r")))
2955 (clobber (match_scratch:SI 3 "=q"))]
2956 "TARGET_POWERPC && TARGET_POWER"
2957 "divw %0,%1,%2"
2958 [(set_attr "type" "idiv")])
2960 (define_insn "*div<mode>3_no_mq"
2961 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2962 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2963 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2964 "TARGET_POWERPC && ! TARGET_POWER"
2965 "div<wd> %0,%1,%2"
2966 [(set (attr "type")
2967 (cond [(match_operand:SI 0 "" "")
2968 (const_string "idiv")]
2969 (const_string "ldiv")))])
2971 (define_expand "mod<mode>3"
2972 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2973 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2974 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2975 ""
2976 "
2977 {
2978 int i;
2979 rtx temp1;
2980 rtx temp2;
2982 if (GET_CODE (operands[2]) != CONST_INT
2983 || INTVAL (operands[2]) <= 0
2984 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2985 FAIL;
2987 temp1 = gen_reg_rtx (<MODE>mode);
2988 temp2 = gen_reg_rtx (<MODE>mode);
2990 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2991 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2992 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2993 DONE;
2994 }")
2996 (define_insn ""
2997 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2998 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2999 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
3000 ""
3001 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
3002 [(set_attr "type" "two")
3003 (set_attr "length" "8")])
3005 (define_insn ""
3006 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3007 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3008 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3009 (const_int 0)))
3010 (clobber (match_scratch:P 3 "=r,r"))]
3011 ""
3012 "@
3013 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
3014 #"
3015 [(set_attr "type" "compare")
3016 (set_attr "length" "8,12")
3017 (set_attr "cell_micro" "not")])
3019 (define_split
3020 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3021 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3022 (match_operand:GPR 2 "exact_log2_cint_operand"
3023 ""))
3024 (const_int 0)))
3025 (clobber (match_scratch:GPR 3 ""))]
3026 "reload_completed"
3027 [(set (match_dup 3)
3028 (div:<MODE> (match_dup 1) (match_dup 2)))
3029 (set (match_dup 0)
3030 (compare:CC (match_dup 3)
3031 (const_int 0)))]
3032 "")
3034 (define_insn ""
3035 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3036 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3037 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3038 (const_int 0)))
3039 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
3040 (div:P (match_dup 1) (match_dup 2)))]
3041 ""
3042 "@
3043 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
3044 #"
3045 [(set_attr "type" "compare")
3046 (set_attr "length" "8,12")
3047 (set_attr "cell_micro" "not")])
3049 (define_split
3050 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3051 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3052 (match_operand:GPR 2 "exact_log2_cint_operand"
3053 ""))
3054 (const_int 0)))
3055 (set (match_operand:GPR 0 "gpc_reg_operand" "")
3056 (div:GPR (match_dup 1) (match_dup 2)))]
3057 "reload_completed"
3058 [(set (match_dup 0)
3059 (div:<MODE> (match_dup 1) (match_dup 2)))
3060 (set (match_dup 3)
3061 (compare:CC (match_dup 0)
3062 (const_int 0)))]
3063 "")
3065 (define_insn ""
3066 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3067 (udiv:SI
3068 (plus:DI (ashift:DI
3069 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3070 (const_int 32))
3071 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
3072 (match_operand:SI 3 "gpc_reg_operand" "r")))
3073 (set (match_operand:SI 2 "register_operand" "=*q")
3074 (umod:SI
3075 (plus:DI (ashift:DI
3076 (zero_extend:DI (match_dup 1)) (const_int 32))
3077 (zero_extend:DI (match_dup 4)))
3078 (match_dup 3)))]
3079 "TARGET_POWER"
3080 "div %0,%1,%3"
3081 [(set_attr "type" "idiv")])
3083 ;; To do unsigned divide we handle the cases of the divisor looking like a
3084 ;; negative number. If it is a constant that is less than 2**31, we don't
3085 ;; have to worry about the branches. So make a few subroutines here.
3086 ;;
3087 ;; First comes the normal case.
3088 (define_expand "udivmodsi4_normal"
3089 [(set (match_dup 4) (const_int 0))
3090 (parallel [(set (match_operand:SI 0 "" "")
3091 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3092 (const_int 32))
3093 (zero_extend:DI (match_operand:SI 1 "" "")))
3094 (match_operand:SI 2 "" "")))
3095 (set (match_operand:SI 3 "" "")
3096 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3097 (const_int 32))
3098 (zero_extend:DI (match_dup 1)))
3099 (match_dup 2)))])]
3100 "TARGET_POWER"
3101 "
3102 { operands[4] = gen_reg_rtx (SImode); }")
3104 ;; This handles the branches.
3105 (define_expand "udivmodsi4_tests"
3106 [(set (match_operand:SI 0 "" "") (const_int 0))
3107 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
3108 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
3109 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
3110 (label_ref (match_operand:SI 4 "" "")) (pc)))
3111 (set (match_dup 0) (const_int 1))
3112 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
3113 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
3114 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
3115 (label_ref (match_dup 4)) (pc)))]
3116 "TARGET_POWER"
3117 "
3118 { operands[5] = gen_reg_rtx (CCUNSmode);
3119 operands[6] = gen_reg_rtx (CCmode);
3120 }")
3122 (define_expand "udivmodsi4"
3123 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3124 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
3125 (match_operand:SI 2 "reg_or_cint_operand" "")))
3126 (set (match_operand:SI 3 "gpc_reg_operand" "")
3127 (umod:SI (match_dup 1) (match_dup 2)))])]
3128 ""
3129 "
3130 {
3131 rtx label = 0;
3133 if (! TARGET_POWER)
3134 {
3135 if (! TARGET_POWERPC)
3136 {
3137 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3138 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3139 emit_insn (gen_divus_call ());
3140 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3141 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
3142 DONE;
3143 }
3144 else
3145 FAIL;
3146 }
3148 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
3149 {
3150 operands[2] = force_reg (SImode, operands[2]);
3151 label = gen_label_rtx ();
3152 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
3153 operands[3], label));
3154 }
3155 else
3156 operands[2] = force_reg (SImode, operands[2]);
3158 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
3159 operands[3]));
3160 if (label)
3161 emit_label (label);
3163 DONE;
3164 }")
3166 ;; AIX architecture-independent common-mode multiply (DImode),
3167 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
3168 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
3169 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
3170 ;; assumed unused if generating common-mode, so ignore.
3171 (define_insn "mulh_call"
3172 [(set (reg:SI 3)
3173 (truncate:SI
3174 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
3175 (sign_extend:DI (reg:SI 4)))
3176 (const_int 32))))
3177 (clobber (reg:SI LR_REGNO))]
3178 "! TARGET_POWER && ! TARGET_POWERPC"
3179 "bla __mulh"
3180 [(set_attr "type" "imul")])
3182 (define_insn "mull_call"
3183 [(set (reg:DI 3)
3184 (mult:DI (sign_extend:DI (reg:SI 3))
3185 (sign_extend:DI (reg:SI 4))))
3186 (clobber (reg:SI LR_REGNO))
3187 (clobber (reg:SI 0))]
3188 "! TARGET_POWER && ! TARGET_POWERPC"
3189 "bla __mull"
3190 [(set_attr "type" "imul")])
3192 (define_insn "divss_call"
3193 [(set (reg:SI 3)
3194 (div:SI (reg:SI 3) (reg:SI 4)))
3195 (set (reg:SI 4)
3196 (mod:SI (reg:SI 3) (reg:SI 4)))
3197 (clobber (reg:SI LR_REGNO))
3198 (clobber (reg:SI 0))]
3199 "! TARGET_POWER && ! TARGET_POWERPC"
3200 "bla __divss"
3201 [(set_attr "type" "idiv")])
3203 (define_insn "divus_call"
3204 [(set (reg:SI 3)
3205 (udiv:SI (reg:SI 3) (reg:SI 4)))
3206 (set (reg:SI 4)
3207 (umod:SI (reg:SI 3) (reg:SI 4)))
3208 (clobber (reg:SI LR_REGNO))
3209 (clobber (reg:SI 0))
3210 (clobber (match_scratch:CC 0 "=x"))
3211 (clobber (reg:CC CR1_REGNO))]
3212 "! TARGET_POWER && ! TARGET_POWERPC"
3213 "bla __divus"
3214 [(set_attr "type" "idiv")])
3216 (define_insn "quoss_call"
3217 [(set (reg:SI 3)
3218 (div:SI (reg:SI 3) (reg:SI 4)))
3219 (clobber (reg:SI LR_REGNO))]
3220 "! TARGET_POWER && ! TARGET_POWERPC"
3221 "bla __quoss"
3222 [(set_attr "type" "idiv")])
3224 (define_insn "quous_call"
3225 [(set (reg:SI 3)
3226 (udiv:SI (reg:SI 3) (reg:SI 4)))
3227 (clobber (reg:SI LR_REGNO))
3228 (clobber (reg:SI 0))
3229 (clobber (match_scratch:CC 0 "=x"))
3230 (clobber (reg:CC CR1_REGNO))]
3231 "! TARGET_POWER && ! TARGET_POWERPC"
3232 "bla __quous"
3233 [(set_attr "type" "idiv")])
3234 \f
3235 ;; Logical instructions
3236 ;; The logical instructions are mostly combined by using match_operator,
3237 ;; but the plain AND insns are somewhat different because there is no
3238 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3239 ;; those rotate-and-mask operations. Thus, the AND insns come first.
3241 (define_expand "andsi3"
3242 [(parallel
3243 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3244 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3245 (match_operand:SI 2 "and_operand" "")))
3246 (clobber (match_scratch:CC 3 ""))])]
3247 ""
3248 "")
3250 (define_insn "andsi3_mc"
3251 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3252 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
3253 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
3254 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
3255 "rs6000_gen_cell_microcode"
3256 "@
3257 and %0,%1,%2
3258 {rlinm|rlwinm} %0,%1,0,%m2,%M2
3259 {andil.|andi.} %0,%1,%b2
3260 {andiu.|andis.} %0,%1,%u2"
3261 [(set_attr "type" "*,*,fast_compare,fast_compare")])
3263 (define_insn "andsi3_nomc"
3264 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3265 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3266 (match_operand:SI 2 "and_operand" "?r,T")))
3267 (clobber (match_scratch:CC 3 "=X,X"))]
3268 "!rs6000_gen_cell_microcode"
3269 "@
3270 and %0,%1,%2
3271 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3273 (define_insn "andsi3_internal0_nomc"
3274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3275 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3276 (match_operand:SI 2 "and_operand" "?r,T")))]
3277 "!rs6000_gen_cell_microcode"
3278 "@
3279 and %0,%1,%2
3280 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3283 ;; Note to set cr's other than cr0 we do the and immediate and then
3284 ;; the test again -- this avoids a mfcr which on the higher end
3285 ;; machines causes an execution serialization
3287 (define_insn "*andsi3_internal2_mc"
3288 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3289 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3290 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3291 (const_int 0)))
3292 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3293 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3294 "TARGET_32BIT && rs6000_gen_cell_microcode"
3295 "@
3296 and. %3,%1,%2
3297 {andil.|andi.} %3,%1,%b2
3298 {andiu.|andis.} %3,%1,%u2
3299 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3300 #
3301 #
3302 #
3303 #"
3304 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3305 compare,compare,compare,compare")
3306 (set_attr "length" "4,4,4,4,8,8,8,8")])
3308 (define_insn "*andsi3_internal3_mc"
3309 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3310 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3311 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3312 (const_int 0)))
3313 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3314 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3315 "TARGET_64BIT && rs6000_gen_cell_microcode"
3316 "@
3317 #
3318 {andil.|andi.} %3,%1,%b2
3319 {andiu.|andis.} %3,%1,%u2
3320 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3321 #
3322 #
3323 #
3324 #"
3325 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3326 compare,compare,compare")
3327 (set_attr "length" "8,4,4,4,8,8,8,8")])
3329 (define_split
3330 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3331 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3332 (match_operand:GPR 2 "and_operand" ""))
3333 (const_int 0)))
3334 (clobber (match_scratch:GPR 3 ""))
3335 (clobber (match_scratch:CC 4 ""))]
3336 "reload_completed"
3337 [(parallel [(set (match_dup 3)
3338 (and:<MODE> (match_dup 1)
3339 (match_dup 2)))
3340 (clobber (match_dup 4))])
3341 (set (match_dup 0)
3342 (compare:CC (match_dup 3)
3343 (const_int 0)))]
3344 "")
3346 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3347 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3349 (define_split
3350 [(set (match_operand:CC 0 "cc_reg_operand" "")
3351 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3352 (match_operand:SI 2 "gpc_reg_operand" ""))
3353 (const_int 0)))
3354 (clobber (match_scratch:SI 3 ""))
3355 (clobber (match_scratch:CC 4 ""))]
3356 "TARGET_POWERPC64 && reload_completed"
3357 [(parallel [(set (match_dup 3)
3358 (and:SI (match_dup 1)
3359 (match_dup 2)))
3360 (clobber (match_dup 4))])
3361 (set (match_dup 0)
3362 (compare:CC (match_dup 3)
3363 (const_int 0)))]
3364 "")
3366 (define_insn "*andsi3_internal4"
3367 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3368 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3369 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3370 (const_int 0)))
3371 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3372 (and:SI (match_dup 1)
3373 (match_dup 2)))
3374 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3375 "TARGET_32BIT && rs6000_gen_cell_microcode"
3376 "@
3377 and. %0,%1,%2
3378 {andil.|andi.} %0,%1,%b2
3379 {andiu.|andis.} %0,%1,%u2
3380 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3381 #
3382 #
3383 #
3384 #"
3385 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3386 compare,compare,compare,compare")
3387 (set_attr "length" "4,4,4,4,8,8,8,8")])
3389 (define_insn "*andsi3_internal5_mc"
3390 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3391 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3392 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3393 (const_int 0)))
3394 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3395 (and:SI (match_dup 1)
3396 (match_dup 2)))
3397 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3398 "TARGET_64BIT && rs6000_gen_cell_microcode"
3399 "@
3400 #
3401 {andil.|andi.} %0,%1,%b2
3402 {andiu.|andis.} %0,%1,%u2
3403 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3404 #
3405 #
3406 #
3407 #"
3408 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3409 compare,compare,compare")
3410 (set_attr "length" "8,4,4,4,8,8,8,8")])
3412 (define_split
3413 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3414 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3415 (match_operand:SI 2 "and_operand" ""))
3416 (const_int 0)))
3417 (set (match_operand:SI 0 "gpc_reg_operand" "")
3418 (and:SI (match_dup 1)
3419 (match_dup 2)))
3420 (clobber (match_scratch:CC 4 ""))]
3421 "reload_completed"
3422 [(parallel [(set (match_dup 0)
3423 (and:SI (match_dup 1)
3424 (match_dup 2)))
3425 (clobber (match_dup 4))])
3426 (set (match_dup 3)
3427 (compare:CC (match_dup 0)
3428 (const_int 0)))]
3429 "")
3431 (define_split
3432 [(set (match_operand:CC 3 "cc_reg_operand" "")
3433 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3434 (match_operand:SI 2 "gpc_reg_operand" ""))
3435 (const_int 0)))
3436 (set (match_operand:SI 0 "gpc_reg_operand" "")
3437 (and:SI (match_dup 1)
3438 (match_dup 2)))
3439 (clobber (match_scratch:CC 4 ""))]
3440 "TARGET_POWERPC64 && reload_completed"
3441 [(parallel [(set (match_dup 0)
3442 (and:SI (match_dup 1)
3443 (match_dup 2)))
3444 (clobber (match_dup 4))])
3445 (set (match_dup 3)
3446 (compare:CC (match_dup 0)
3447 (const_int 0)))]
3448 "")
3450 ;; Handle the PowerPC64 rlwinm corner case
3452 (define_insn_and_split "*andsi3_internal6"
3453 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3454 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3455 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3456 "TARGET_POWERPC64"
3457 "#"
3458 "TARGET_POWERPC64"
3459 [(set (match_dup 0)
3460 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3461 (match_dup 4)))
3462 (set (match_dup 0)
3463 (rotate:SI (match_dup 0) (match_dup 5)))]
3464 "
3465 {
3466 int mb = extract_MB (operands[2]);
3467 int me = extract_ME (operands[2]);
3468 operands[3] = GEN_INT (me + 1);
3469 operands[5] = GEN_INT (32 - (me + 1));
3470 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3471 }"
3472 [(set_attr "length" "8")])
3474 (define_expand "iorsi3"
3475 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3476 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3477 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3478 ""
3479 "
3480 {
3481 if (GET_CODE (operands[2]) == CONST_INT
3482 && ! logical_operand (operands[2], SImode))
3483 {
3484 HOST_WIDE_INT value = INTVAL (operands[2]);
3485 rtx tmp = ((!can_create_pseudo_p ()
3486 || rtx_equal_p (operands[0], operands[1]))
3487 ? operands[0] : gen_reg_rtx (SImode));
3489 emit_insn (gen_iorsi3 (tmp, operands[1],
3490 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3491 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3492 DONE;
3493 }
3494 }")
3496 (define_expand "xorsi3"
3497 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3498 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3499 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3500 ""
3501 "
3502 {
3503 if (GET_CODE (operands[2]) == CONST_INT
3504 && ! logical_operand (operands[2], SImode))
3505 {
3506 HOST_WIDE_INT value = INTVAL (operands[2]);
3507 rtx tmp = ((!can_create_pseudo_p ()
3508 || rtx_equal_p (operands[0], operands[1]))
3509 ? operands[0] : gen_reg_rtx (SImode));
3511 emit_insn (gen_xorsi3 (tmp, operands[1],
3512 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3513 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3514 DONE;
3515 }
3516 }")
3518 (define_insn "*boolsi3_internal1"
3519 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3520 (match_operator:SI 3 "boolean_or_operator"
3521 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3522 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3523 ""
3524 "@
3525 %q3 %0,%1,%2
3526 {%q3il|%q3i} %0,%1,%b2
3527 {%q3iu|%q3is} %0,%1,%u2")
3529 (define_insn "*boolsi3_internal2"
3530 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3531 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3532 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3533 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3534 (const_int 0)))
3535 (clobber (match_scratch:SI 3 "=r,r"))]
3536 "TARGET_32BIT"
3537 "@
3538 %q4. %3,%1,%2
3539 #"
3540 [(set_attr "type" "fast_compare,compare")
3541 (set_attr "length" "4,8")])
3543 (define_split
3544 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3545 (compare:CC (match_operator:SI 4 "boolean_operator"
3546 [(match_operand:SI 1 "gpc_reg_operand" "")
3547 (match_operand:SI 2 "gpc_reg_operand" "")])
3548 (const_int 0)))
3549 (clobber (match_scratch:SI 3 ""))]
3550 "TARGET_32BIT && reload_completed"
3551 [(set (match_dup 3) (match_dup 4))
3552 (set (match_dup 0)
3553 (compare:CC (match_dup 3)
3554 (const_int 0)))]
3555 "")
3557 (define_insn "*boolsi3_internal3"
3558 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3559 (compare:CC (match_operator:SI 4 "boolean_operator"
3560 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3561 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3562 (const_int 0)))
3563 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3564 (match_dup 4))]
3565 "TARGET_32BIT"
3566 "@
3567 %q4. %0,%1,%2
3568 #"
3569 [(set_attr "type" "fast_compare,compare")
3570 (set_attr "length" "4,8")])
3572 (define_split
3573 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3574 (compare:CC (match_operator:SI 4 "boolean_operator"
3575 [(match_operand:SI 1 "gpc_reg_operand" "")
3576 (match_operand:SI 2 "gpc_reg_operand" "")])
3577 (const_int 0)))
3578 (set (match_operand:SI 0 "gpc_reg_operand" "")
3579 (match_dup 4))]
3580 "TARGET_32BIT && reload_completed"
3581 [(set (match_dup 0) (match_dup 4))
3582 (set (match_dup 3)
3583 (compare:CC (match_dup 0)
3584 (const_int 0)))]
3585 "")
3587 ;; Split a logical operation that we can't do in one insn into two insns,
3588 ;; each of which does one 16-bit part. This is used by combine.
3590 (define_split
3591 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3592 (match_operator:SI 3 "boolean_or_operator"
3593 [(match_operand:SI 1 "gpc_reg_operand" "")
3594 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3595 ""
3596 [(set (match_dup 0) (match_dup 4))
3597 (set (match_dup 0) (match_dup 5))]
3598 "
3599 {
3600 rtx i;
3601 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3602 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3603 operands[1], i);
3604 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3605 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3606 operands[0], i);
3607 }")
3609 (define_insn "*boolcsi3_internal1"
3610 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3611 (match_operator:SI 3 "boolean_operator"
3612 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3613 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3614 ""
3615 "%q3 %0,%2,%1")
3617 (define_insn "*boolcsi3_internal2"
3618 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3619 (compare:CC (match_operator:SI 4 "boolean_operator"
3620 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3621 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3622 (const_int 0)))
3623 (clobber (match_scratch:SI 3 "=r,r"))]
3624 "TARGET_32BIT"
3625 "@
3626 %q4. %3,%2,%1
3627 #"
3628 [(set_attr "type" "compare")
3629 (set_attr "length" "4,8")])
3631 (define_split
3632 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3633 (compare:CC (match_operator:SI 4 "boolean_operator"
3634 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3635 (match_operand:SI 2 "gpc_reg_operand" "")])
3636 (const_int 0)))
3637 (clobber (match_scratch:SI 3 ""))]
3638 "TARGET_32BIT && reload_completed"
3639 [(set (match_dup 3) (match_dup 4))
3640 (set (match_dup 0)
3641 (compare:CC (match_dup 3)
3642 (const_int 0)))]
3643 "")
3645 (define_insn "*boolcsi3_internal3"
3646 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3647 (compare:CC (match_operator:SI 4 "boolean_operator"
3648 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3649 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3650 (const_int 0)))
3651 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3652 (match_dup 4))]
3653 "TARGET_32BIT"
3654 "@
3655 %q4. %0,%2,%1
3656 #"
3657 [(set_attr "type" "compare")
3658 (set_attr "length" "4,8")])
3660 (define_split
3661 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3662 (compare:CC (match_operator:SI 4 "boolean_operator"
3663 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3664 (match_operand:SI 2 "gpc_reg_operand" "")])
3665 (const_int 0)))
3666 (set (match_operand:SI 0 "gpc_reg_operand" "")
3667 (match_dup 4))]
3668 "TARGET_32BIT && reload_completed"
3669 [(set (match_dup 0) (match_dup 4))
3670 (set (match_dup 3)
3671 (compare:CC (match_dup 0)
3672 (const_int 0)))]
3673 "")
3675 (define_insn "*boolccsi3_internal1"
3676 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3677 (match_operator:SI 3 "boolean_operator"
3678 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3679 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3680 ""
3681 "%q3 %0,%1,%2")
3683 (define_insn "*boolccsi3_internal2"
3684 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3685 (compare:CC (match_operator:SI 4 "boolean_operator"
3686 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3687 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3688 (const_int 0)))
3689 (clobber (match_scratch:SI 3 "=r,r"))]
3690 "TARGET_32BIT"
3691 "@
3692 %q4. %3,%1,%2
3693 #"
3694 [(set_attr "type" "fast_compare,compare")
3695 (set_attr "length" "4,8")])
3697 (define_split
3698 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3699 (compare:CC (match_operator:SI 4 "boolean_operator"
3700 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3701 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3702 (const_int 0)))
3703 (clobber (match_scratch:SI 3 ""))]
3704 "TARGET_32BIT && reload_completed"
3705 [(set (match_dup 3) (match_dup 4))
3706 (set (match_dup 0)
3707 (compare:CC (match_dup 3)
3708 (const_int 0)))]
3709 "")
3711 (define_insn "*boolccsi3_internal3"
3712 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3713 (compare:CC (match_operator:SI 4 "boolean_operator"
3714 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3715 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3716 (const_int 0)))
3717 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3718 (match_dup 4))]
3719 "TARGET_32BIT"
3720 "@
3721 %q4. %0,%1,%2
3722 #"
3723 [(set_attr "type" "fast_compare,compare")
3724 (set_attr "length" "4,8")])
3726 (define_split
3727 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3728 (compare:CC (match_operator:SI 4 "boolean_operator"
3729 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3730 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3731 (const_int 0)))
3732 (set (match_operand:SI 0 "gpc_reg_operand" "")
3733 (match_dup 4))]
3734 "TARGET_32BIT && reload_completed"
3735 [(set (match_dup 0) (match_dup 4))
3736 (set (match_dup 3)
3737 (compare:CC (match_dup 0)
3738 (const_int 0)))]
3739 "")
3741 ;; maskir insn. We need four forms because things might be in arbitrary
3742 ;; orders. Don't define forms that only set CR fields because these
3743 ;; would modify an input register.
3745 (define_insn "*maskir_internal1"
3746 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3747 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3748 (match_operand:SI 1 "gpc_reg_operand" "0"))
3749 (and:SI (match_dup 2)
3750 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3751 "TARGET_POWER"
3752 "maskir %0,%3,%2")
3754 (define_insn "*maskir_internal2"
3755 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3756 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3757 (match_operand:SI 1 "gpc_reg_operand" "0"))
3758 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3759 (match_dup 2))))]
3760 "TARGET_POWER"
3761 "maskir %0,%3,%2")
3763 (define_insn "*maskir_internal3"
3764 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3765 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3766 (match_operand:SI 3 "gpc_reg_operand" "r"))
3767 (and:SI (not:SI (match_dup 2))
3768 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3769 "TARGET_POWER"
3770 "maskir %0,%3,%2")
3772 (define_insn "*maskir_internal4"
3773 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3774 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3775 (match_operand:SI 2 "gpc_reg_operand" "r"))
3776 (and:SI (not:SI (match_dup 2))
3777 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3778 "TARGET_POWER"
3779 "maskir %0,%3,%2")
3781 (define_insn "*maskir_internal5"
3782 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3783 (compare:CC
3784 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3785 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3786 (and:SI (match_dup 2)
3787 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3788 (const_int 0)))
3789 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3790 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3791 (and:SI (match_dup 2) (match_dup 3))))]
3792 "TARGET_POWER"
3793 "@
3794 maskir. %0,%3,%2
3795 #"
3796 [(set_attr "type" "compare")
3797 (set_attr "length" "4,8")])
3799 (define_split
3800 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3801 (compare:CC
3802 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3803 (match_operand:SI 1 "gpc_reg_operand" ""))
3804 (and:SI (match_dup 2)
3805 (match_operand:SI 3 "gpc_reg_operand" "")))
3806 (const_int 0)))
3807 (set (match_operand:SI 0 "gpc_reg_operand" "")
3808 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3809 (and:SI (match_dup 2) (match_dup 3))))]
3810 "TARGET_POWER && reload_completed"
3811 [(set (match_dup 0)
3812 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3813 (and:SI (match_dup 2) (match_dup 3))))
3814 (set (match_dup 4)
3815 (compare:CC (match_dup 0)
3816 (const_int 0)))]
3817 "")
3819 (define_insn "*maskir_internal6"
3820 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3821 (compare:CC
3822 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3823 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3824 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3825 (match_dup 2)))
3826 (const_int 0)))
3827 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3828 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3829 (and:SI (match_dup 3) (match_dup 2))))]
3830 "TARGET_POWER"
3831 "@
3832 maskir. %0,%3,%2
3833 #"
3834 [(set_attr "type" "compare")
3835 (set_attr "length" "4,8")])
3837 (define_split
3838 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3839 (compare:CC
3840 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3841 (match_operand:SI 1 "gpc_reg_operand" ""))
3842 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3843 (match_dup 2)))
3844 (const_int 0)))
3845 (set (match_operand:SI 0 "gpc_reg_operand" "")
3846 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3847 (and:SI (match_dup 3) (match_dup 2))))]
3848 "TARGET_POWER && reload_completed"
3849 [(set (match_dup 0)
3850 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3851 (and:SI (match_dup 3) (match_dup 2))))
3852 (set (match_dup 4)
3853 (compare:CC (match_dup 0)
3854 (const_int 0)))]
3855 "")
3857 (define_insn "*maskir_internal7"
3858 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3859 (compare:CC
3860 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3861 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3862 (and:SI (not:SI (match_dup 2))
3863 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3864 (const_int 0)))
3865 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3866 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3867 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3868 "TARGET_POWER"
3869 "@
3870 maskir. %0,%3,%2
3871 #"
3872 [(set_attr "type" "compare")
3873 (set_attr "length" "4,8")])
3875 (define_split
3876 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3877 (compare:CC
3878 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3879 (match_operand:SI 3 "gpc_reg_operand" ""))
3880 (and:SI (not:SI (match_dup 2))
3881 (match_operand:SI 1 "gpc_reg_operand" "")))
3882 (const_int 0)))
3883 (set (match_operand:SI 0 "gpc_reg_operand" "")
3884 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3885 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3886 "TARGET_POWER && reload_completed"
3887 [(set (match_dup 0)
3888 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3889 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3890 (set (match_dup 4)
3891 (compare:CC (match_dup 0)
3892 (const_int 0)))]
3893 "")
3895 (define_insn "*maskir_internal8"
3896 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3897 (compare:CC
3898 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3899 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3900 (and:SI (not:SI (match_dup 2))
3901 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3902 (const_int 0)))
3903 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3904 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3905 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3906 "TARGET_POWER"
3907 "@
3908 maskir. %0,%3,%2
3909 #"
3910 [(set_attr "type" "compare")
3911 (set_attr "length" "4,8")])
3913 (define_split
3914 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3915 (compare:CC
3916 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3917 (match_operand:SI 2 "gpc_reg_operand" ""))
3918 (and:SI (not:SI (match_dup 2))
3919 (match_operand:SI 1 "gpc_reg_operand" "")))
3920 (const_int 0)))
3921 (set (match_operand:SI 0 "gpc_reg_operand" "")
3922 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3923 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3924 "TARGET_POWER && reload_completed"
3925 [(set (match_dup 0)
3926 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3927 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3928 (set (match_dup 4)
3929 (compare:CC (match_dup 0)
3930 (const_int 0)))]
3931 "")
3932 \f
3933 ;; Rotate and shift insns, in all their variants. These support shifts,
3934 ;; field inserts and extracts, and various combinations thereof.
3935 (define_expand "insv"
3936 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3937 (match_operand:SI 1 "const_int_operand" "")
3938 (match_operand:SI 2 "const_int_operand" ""))
3939 (match_operand 3 "gpc_reg_operand" ""))]
3940 ""
3941 "
3942 {
3943 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3944 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3945 compiler if the address of the structure is taken later. Likewise, do
3946 not handle invalid E500 subregs. */
3947 if (GET_CODE (operands[0]) == SUBREG
3948 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3949 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3950 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3951 FAIL;
3953 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3954 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3955 else
3956 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3957 DONE;
3958 }")
3960 (define_insn "insvsi"
3961 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3962 (match_operand:SI 1 "const_int_operand" "i")
3963 (match_operand:SI 2 "const_int_operand" "i"))
3964 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3965 ""
3966 "*
3967 {
3968 int start = INTVAL (operands[2]) & 31;
3969 int size = INTVAL (operands[1]) & 31;
3971 operands[4] = GEN_INT (32 - start - size);
3972 operands[1] = GEN_INT (start + size - 1);
3973 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3974 }"
3975 [(set_attr "type" "insert_word")])
3977 (define_insn "*insvsi_internal1"
3978 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3979 (match_operand:SI 1 "const_int_operand" "i")
3980 (match_operand:SI 2 "const_int_operand" "i"))
3981 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3982 (match_operand:SI 4 "const_int_operand" "i")))]
3983 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3984 "*
3985 {
3986 int shift = INTVAL (operands[4]) & 31;
3987 int start = INTVAL (operands[2]) & 31;
3988 int size = INTVAL (operands[1]) & 31;
3990 operands[4] = GEN_INT (shift - start - size);
3991 operands[1] = GEN_INT (start + size - 1);
3992 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3993 }"
3994 [(set_attr "type" "insert_word")])
3996 (define_insn "*insvsi_internal2"
3997 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3998 (match_operand:SI 1 "const_int_operand" "i")
3999 (match_operand:SI 2 "const_int_operand" "i"))
4000 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4001 (match_operand:SI 4 "const_int_operand" "i")))]
4002 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4003 "*
4004 {
4005 int shift = INTVAL (operands[4]) & 31;
4006 int start = INTVAL (operands[2]) & 31;
4007 int size = INTVAL (operands[1]) & 31;
4009 operands[4] = GEN_INT (32 - shift - start - size);
4010 operands[1] = GEN_INT (start + size - 1);
4011 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4012 }"
4013 [(set_attr "type" "insert_word")])
4015 (define_insn "*insvsi_internal3"
4016 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4017 (match_operand:SI 1 "const_int_operand" "i")
4018 (match_operand:SI 2 "const_int_operand" "i"))
4019 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4020 (match_operand:SI 4 "const_int_operand" "i")))]
4021 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4022 "*
4023 {
4024 int shift = INTVAL (operands[4]) & 31;
4025 int start = INTVAL (operands[2]) & 31;
4026 int size = INTVAL (operands[1]) & 31;
4028 operands[4] = GEN_INT (32 - shift - start - size);
4029 operands[1] = GEN_INT (start + size - 1);
4030 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4031 }"
4032 [(set_attr "type" "insert_word")])
4034 (define_insn "*insvsi_internal4"
4035 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4036 (match_operand:SI 1 "const_int_operand" "i")
4037 (match_operand:SI 2 "const_int_operand" "i"))
4038 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4039 (match_operand:SI 4 "const_int_operand" "i")
4040 (match_operand:SI 5 "const_int_operand" "i")))]
4041 "INTVAL (operands[4]) >= INTVAL (operands[1])"
4042 "*
4043 {
4044 int extract_start = INTVAL (operands[5]) & 31;
4045 int extract_size = INTVAL (operands[4]) & 31;
4046 int insert_start = INTVAL (operands[2]) & 31;
4047 int insert_size = INTVAL (operands[1]) & 31;
4049 /* Align extract field with insert field */
4050 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
4051 operands[1] = GEN_INT (insert_start + insert_size - 1);
4052 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
4053 }"
4054 [(set_attr "type" "insert_word")])
4056 ;; combine patterns for rlwimi
4057 (define_insn "*insvsi_internal5"
4058 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4059 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4060 (match_operand:SI 1 "mask_operand" "i"))
4061 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4062 (match_operand:SI 2 "const_int_operand" "i"))
4063 (match_operand:SI 5 "mask_operand" "i"))))]
4064 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4065 "*
4066 {
4067 int me = extract_ME(operands[5]);
4068 int mb = extract_MB(operands[5]);
4069 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4070 operands[2] = GEN_INT(mb);
4071 operands[1] = GEN_INT(me);
4072 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4073 }"
4074 [(set_attr "type" "insert_word")])
4076 (define_insn "*insvsi_internal6"
4077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4078 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4079 (match_operand:SI 2 "const_int_operand" "i"))
4080 (match_operand:SI 5 "mask_operand" "i"))
4081 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4082 (match_operand:SI 1 "mask_operand" "i"))))]
4083 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4084 "*
4085 {
4086 int me = extract_ME(operands[5]);
4087 int mb = extract_MB(operands[5]);
4088 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4089 operands[2] = GEN_INT(mb);
4090 operands[1] = GEN_INT(me);
4091 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4092 }"
4093 [(set_attr "type" "insert_word")])
4095 (define_insn "insvdi"
4096 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4097 (match_operand:SI 1 "const_int_operand" "i")
4098 (match_operand:SI 2 "const_int_operand" "i"))
4099 (match_operand:DI 3 "gpc_reg_operand" "r"))]
4100 "TARGET_POWERPC64"
4101 "*
4102 {
4103 int start = INTVAL (operands[2]) & 63;
4104 int size = INTVAL (operands[1]) & 63;
4106 operands[1] = GEN_INT (64 - start - size);
4107 return \"rldimi %0,%3,%H1,%H2\";
4108 }"
4109 [(set_attr "type" "insert_dword")])
4111 (define_insn "*insvdi_internal2"
4112 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4113 (match_operand:SI 1 "const_int_operand" "i")
4114 (match_operand:SI 2 "const_int_operand" "i"))
4115 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4116 (match_operand:SI 4 "const_int_operand" "i")))]
4117 "TARGET_POWERPC64
4118 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4119 "*
4120 {
4121 int shift = INTVAL (operands[4]) & 63;
4122 int start = (INTVAL (operands[2]) & 63) - 32;
4123 int size = INTVAL (operands[1]) & 63;
4125 operands[4] = GEN_INT (64 - shift - start - size);
4126 operands[2] = GEN_INT (start);
4127 operands[1] = GEN_INT (start + size - 1);
4128 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4129 }")
4131 (define_insn "*insvdi_internal3"
4132 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4133 (match_operand:SI 1 "const_int_operand" "i")
4134 (match_operand:SI 2 "const_int_operand" "i"))
4135 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4136 (match_operand:SI 4 "const_int_operand" "i")))]
4137 "TARGET_POWERPC64
4138 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4139 "*
4140 {
4141 int shift = INTVAL (operands[4]) & 63;
4142 int start = (INTVAL (operands[2]) & 63) - 32;
4143 int size = INTVAL (operands[1]) & 63;
4145 operands[4] = GEN_INT (64 - shift - start - size);
4146 operands[2] = GEN_INT (start);
4147 operands[1] = GEN_INT (start + size - 1);
4148 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4149 }")
4151 (define_expand "extzv"
4152 [(set (match_operand 0 "gpc_reg_operand" "")
4153 (zero_extract (match_operand 1 "gpc_reg_operand" "")
4154 (match_operand:SI 2 "const_int_operand" "")
4155 (match_operand:SI 3 "const_int_operand" "")))]
4156 ""
4157 "
4158 {
4159 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4160 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4161 compiler if the address of the structure is taken later. */
4162 if (GET_CODE (operands[0]) == SUBREG
4163 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
4164 FAIL;
4166 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
4167 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
4168 else
4169 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
4170 DONE;
4171 }")
4173 (define_insn "extzvsi"
4174 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4175 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4176 (match_operand:SI 2 "const_int_operand" "i")
4177 (match_operand:SI 3 "const_int_operand" "i")))]
4178 ""
4179 "*
4180 {
4181 int start = INTVAL (operands[3]) & 31;
4182 int size = INTVAL (operands[2]) & 31;
4184 if (start + size >= 32)
4185 operands[3] = const0_rtx;
4186 else
4187 operands[3] = GEN_INT (start + size);
4188 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
4189 }")
4191 (define_insn "*extzvsi_internal1"
4192 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4193 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4194 (match_operand:SI 2 "const_int_operand" "i,i")
4195 (match_operand:SI 3 "const_int_operand" "i,i"))
4196 (const_int 0)))
4197 (clobber (match_scratch:SI 4 "=r,r"))]
4198 ""
4199 "*
4200 {
4201 int start = INTVAL (operands[3]) & 31;
4202 int size = INTVAL (operands[2]) & 31;
4204 /* Force split for non-cc0 compare. */
4205 if (which_alternative == 1)
4206 return \"#\";
4208 /* If the bit-field being tested fits in the upper or lower half of a
4209 word, it is possible to use andiu. or andil. to test it. This is
4210 useful because the condition register set-use delay is smaller for
4211 andi[ul]. than for rlinm. This doesn't work when the starting bit
4212 position is 0 because the LT and GT bits may be set wrong. */
4214 if ((start > 0 && start + size <= 16) || start >= 16)
4215 {
4216 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
4217 - (1 << (16 - (start & 15) - size))));
4218 if (start < 16)
4219 return \"{andiu.|andis.} %4,%1,%3\";
4220 else
4221 return \"{andil.|andi.} %4,%1,%3\";
4222 }
4224 if (start + size >= 32)
4225 operands[3] = const0_rtx;
4226 else
4227 operands[3] = GEN_INT (start + size);
4228 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
4229 }"
4230 [(set_attr "type" "delayed_compare")
4231 (set_attr "length" "4,8")])
4233 (define_split
4234 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4235 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4236 (match_operand:SI 2 "const_int_operand" "")
4237 (match_operand:SI 3 "const_int_operand" ""))
4238 (const_int 0)))
4239 (clobber (match_scratch:SI 4 ""))]
4240 "reload_completed"
4241 [(set (match_dup 4)
4242 (zero_extract:SI (match_dup 1) (match_dup 2)
4243 (match_dup 3)))
4244 (set (match_dup 0)
4245 (compare:CC (match_dup 4)
4246 (const_int 0)))]
4247 "")
4249 (define_insn "*extzvsi_internal2"
4250 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4251 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4252 (match_operand:SI 2 "const_int_operand" "i,i")
4253 (match_operand:SI 3 "const_int_operand" "i,i"))
4254 (const_int 0)))
4255 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4256 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4257 ""
4258 "*
4259 {
4260 int start = INTVAL (operands[3]) & 31;
4261 int size = INTVAL (operands[2]) & 31;
4263 /* Force split for non-cc0 compare. */
4264 if (which_alternative == 1)
4265 return \"#\";
4267 /* Since we are using the output value, we can't ignore any need for
4268 a shift. The bit-field must end at the LSB. */
4269 if (start >= 16 && start + size == 32)
4270 {
4271 operands[3] = GEN_INT ((1 << size) - 1);
4272 return \"{andil.|andi.} %0,%1,%3\";
4273 }
4275 if (start + size >= 32)
4276 operands[3] = const0_rtx;
4277 else
4278 operands[3] = GEN_INT (start + size);
4279 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
4280 }"
4281 [(set_attr "type" "delayed_compare")
4282 (set_attr "length" "4,8")])
4284 (define_split
4285 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4286 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4287 (match_operand:SI 2 "const_int_operand" "")
4288 (match_operand:SI 3 "const_int_operand" ""))
4289 (const_int 0)))
4290 (set (match_operand:SI 0 "gpc_reg_operand" "")
4291 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4292 "reload_completed"
4293 [(set (match_dup 0)
4294 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
4295 (set (match_dup 4)
4296 (compare:CC (match_dup 0)
4297 (const_int 0)))]
4298 "")
4300 (define_insn "extzvdi"
4301 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4302 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4303 (match_operand:SI 2 "const_int_operand" "i")
4304 (match_operand:SI 3 "const_int_operand" "i")))]
4305 "TARGET_POWERPC64"
4306 "*
4307 {
4308 int start = INTVAL (operands[3]) & 63;
4309 int size = INTVAL (operands[2]) & 63;
4311 if (start + size >= 64)
4312 operands[3] = const0_rtx;
4313 else
4314 operands[3] = GEN_INT (start + size);
4315 operands[2] = GEN_INT (64 - size);
4316 return \"rldicl %0,%1,%3,%2\";
4317 }")
4319 (define_insn "*extzvdi_internal1"
4320 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
4321 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4322 (match_operand:SI 2 "const_int_operand" "i")
4323 (match_operand:SI 3 "const_int_operand" "i"))
4324 (const_int 0)))
4325 (clobber (match_scratch:DI 4 "=r"))]
4326 "TARGET_64BIT && rs6000_gen_cell_microcode"
4327 "*
4328 {
4329 int start = INTVAL (operands[3]) & 63;
4330 int size = INTVAL (operands[2]) & 63;
4332 if (start + size >= 64)
4333 operands[3] = const0_rtx;
4334 else
4335 operands[3] = GEN_INT (start + size);
4336 operands[2] = GEN_INT (64 - size);
4337 return \"rldicl. %4,%1,%3,%2\";
4338 }"
4339 [(set_attr "type" "compare")])
4341 (define_insn "*extzvdi_internal2"
4342 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
4343 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4344 (match_operand:SI 2 "const_int_operand" "i")
4345 (match_operand:SI 3 "const_int_operand" "i"))
4346 (const_int 0)))
4347 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4348 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
4349 "TARGET_64BIT && rs6000_gen_cell_microcode"
4350 "*
4351 {
4352 int start = INTVAL (operands[3]) & 63;
4353 int size = INTVAL (operands[2]) & 63;
4355 if (start + size >= 64)
4356 operands[3] = const0_rtx;
4357 else
4358 operands[3] = GEN_INT (start + size);
4359 operands[2] = GEN_INT (64 - size);
4360 return \"rldicl. %0,%1,%3,%2\";
4361 }"
4362 [(set_attr "type" "compare")])
4364 (define_insn "rotlsi3"
4365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4366 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4367 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4368 ""
4369 "@
4370 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4371 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4372 [(set_attr "type" "var_shift_rotate,integer")])
4374 (define_insn "*rotlsi3_64"
4375 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4376 (zero_extend:DI
4377 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4378 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4379 "TARGET_64BIT"
4380 "@
4381 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4382 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4383 [(set_attr "type" "var_shift_rotate,integer")])
4385 (define_insn "*rotlsi3_internal2"
4386 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4387 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4388 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4389 (const_int 0)))
4390 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4391 ""
4392 "@
4393 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4394 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4395 #
4396 #"
4397 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4398 (set_attr "length" "4,4,8,8")])
4400 (define_split
4401 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4402 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4403 (match_operand:SI 2 "reg_or_cint_operand" ""))
4404 (const_int 0)))
4405 (clobber (match_scratch:SI 3 ""))]
4406 "reload_completed"
4407 [(set (match_dup 3)
4408 (rotate:SI (match_dup 1) (match_dup 2)))
4409 (set (match_dup 0)
4410 (compare:CC (match_dup 3)
4411 (const_int 0)))]
4412 "")
4414 (define_insn "*rotlsi3_internal3"
4415 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4416 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4417 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4418 (const_int 0)))
4419 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4420 (rotate:SI (match_dup 1) (match_dup 2)))]
4421 ""
4422 "@
4423 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4424 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4425 #
4426 #"
4427 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4428 (set_attr "length" "4,4,8,8")])
4430 (define_split
4431 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4432 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4433 (match_operand:SI 2 "reg_or_cint_operand" ""))
4434 (const_int 0)))
4435 (set (match_operand:SI 0 "gpc_reg_operand" "")
4436 (rotate:SI (match_dup 1) (match_dup 2)))]
4437 "reload_completed"
4438 [(set (match_dup 0)
4439 (rotate:SI (match_dup 1) (match_dup 2)))
4440 (set (match_dup 3)
4441 (compare:CC (match_dup 0)
4442 (const_int 0)))]
4443 "")
4445 (define_insn "*rotlsi3_internal4"
4446 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4447 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4448 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4449 (match_operand:SI 3 "mask_operand" "n,n")))]
4450 ""
4451 "@
4452 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4453 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4454 [(set_attr "type" "var_shift_rotate,integer")])
4456 (define_insn "*rotlsi3_internal5"
4457 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4458 (compare:CC (and:SI
4459 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4460 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4461 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4462 (const_int 0)))
4463 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4464 ""
4465 "@
4466 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4467 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4468 #
4469 #"
4470 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4471 (set_attr "length" "4,4,8,8")])
4473 (define_split
4474 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4475 (compare:CC (and:SI
4476 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4477 (match_operand:SI 2 "reg_or_cint_operand" ""))
4478 (match_operand:SI 3 "mask_operand" ""))
4479 (const_int 0)))
4480 (clobber (match_scratch:SI 4 ""))]
4481 "reload_completed"
4482 [(set (match_dup 4)
4483 (and:SI (rotate:SI (match_dup 1)
4484 (match_dup 2))
4485 (match_dup 3)))
4486 (set (match_dup 0)
4487 (compare:CC (match_dup 4)
4488 (const_int 0)))]
4489 "")
4491 (define_insn "*rotlsi3_internal6"
4492 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4493 (compare:CC (and:SI
4494 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4495 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4496 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4497 (const_int 0)))
4498 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4499 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4500 ""
4501 "@
4502 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4503 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4504 #
4505 #"
4506 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4507 (set_attr "length" "4,4,8,8")])
4509 (define_split
4510 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4511 (compare:CC (and:SI
4512 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4513 (match_operand:SI 2 "reg_or_cint_operand" ""))
4514 (match_operand:SI 3 "mask_operand" ""))
4515 (const_int 0)))
4516 (set (match_operand:SI 0 "gpc_reg_operand" "")
4517 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4518 "reload_completed"
4519 [(set (match_dup 0)
4520 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4521 (set (match_dup 4)
4522 (compare:CC (match_dup 0)
4523 (const_int 0)))]
4524 "")
4526 (define_insn "*rotlsi3_internal7"
4527 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4528 (zero_extend:SI
4529 (subreg:QI
4530 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4531 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4532 ""
4533 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4534 [(set (attr "cell_micro")
4535 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4536 (const_string "not")
4537 (const_string "always")))])
4539 (define_insn "*rotlsi3_internal8"
4540 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4541 (compare:CC (zero_extend:SI
4542 (subreg:QI
4543 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4544 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4545 (const_int 0)))
4546 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4547 ""
4548 "@
4549 {rlnm.|rlwnm.} %3,%1,%2,0xff
4550 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4551 #
4552 #"
4553 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4554 (set_attr "length" "4,4,8,8")])
4556 (define_split
4557 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4558 (compare:CC (zero_extend:SI
4559 (subreg:QI
4560 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4561 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4562 (const_int 0)))
4563 (clobber (match_scratch:SI 3 ""))]
4564 "reload_completed"
4565 [(set (match_dup 3)
4566 (zero_extend:SI (subreg:QI
4567 (rotate:SI (match_dup 1)
4568 (match_dup 2)) 0)))
4569 (set (match_dup 0)
4570 (compare:CC (match_dup 3)
4571 (const_int 0)))]
4572 "")
4574 (define_insn "*rotlsi3_internal9"
4575 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4576 (compare:CC (zero_extend:SI
4577 (subreg:QI
4578 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4579 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4580 (const_int 0)))
4581 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4582 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4583 ""
4584 "@
4585 {rlnm.|rlwnm.} %0,%1,%2,0xff
4586 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4587 #
4588 #"
4589 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4590 (set_attr "length" "4,4,8,8")])
4592 (define_split
4593 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4594 (compare:CC (zero_extend:SI
4595 (subreg:QI
4596 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4597 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4598 (const_int 0)))
4599 (set (match_operand:SI 0 "gpc_reg_operand" "")
4600 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4601 "reload_completed"
4602 [(set (match_dup 0)
4603 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4604 (set (match_dup 3)
4605 (compare:CC (match_dup 0)
4606 (const_int 0)))]
4607 "")
4609 (define_insn "*rotlsi3_internal10"
4610 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4611 (zero_extend:SI
4612 (subreg:HI
4613 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4614 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4615 ""
4616 "@
4617 {rlnm|rlwnm} %0,%1,%2,0xffff
4618 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4619 [(set_attr "type" "var_shift_rotate,integer")])
4622 (define_insn "*rotlsi3_internal11"
4623 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4624 (compare:CC (zero_extend:SI
4625 (subreg:HI
4626 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4627 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4628 (const_int 0)))
4629 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4630 ""
4631 "@
4632 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4633 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4634 #
4635 #"
4636 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4637 (set_attr "length" "4,4,8,8")])
4639 (define_split
4640 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4641 (compare:CC (zero_extend:SI
4642 (subreg:HI
4643 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4644 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4645 (const_int 0)))
4646 (clobber (match_scratch:SI 3 ""))]
4647 "reload_completed"
4648 [(set (match_dup 3)
4649 (zero_extend:SI (subreg:HI
4650 (rotate:SI (match_dup 1)
4651 (match_dup 2)) 0)))
4652 (set (match_dup 0)
4653 (compare:CC (match_dup 3)
4654 (const_int 0)))]
4655 "")
4657 (define_insn "*rotlsi3_internal12"
4658 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4659 (compare:CC (zero_extend:SI
4660 (subreg:HI
4661 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4662 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4663 (const_int 0)))
4664 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4665 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4666 ""
4667 "@
4668 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4669 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4670 #
4671 #"
4672 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4673 (set_attr "length" "4,4,8,8")])
4675 (define_split
4676 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4677 (compare:CC (zero_extend:SI
4678 (subreg:HI
4679 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4680 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4681 (const_int 0)))
4682 (set (match_operand:SI 0 "gpc_reg_operand" "")
4683 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4684 "reload_completed"
4685 [(set (match_dup 0)
4686 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4687 (set (match_dup 3)
4688 (compare:CC (match_dup 0)
4689 (const_int 0)))]
4690 "")
4692 ;; Note that we use "sle." instead of "sl." so that we can set
4693 ;; SHIFT_COUNT_TRUNCATED.
4695 (define_expand "ashlsi3"
4696 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4697 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4698 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4699 ""
4700 "
4701 {
4702 if (TARGET_POWER)
4703 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4704 else
4705 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4706 DONE;
4707 }")
4709 (define_insn "ashlsi3_power"
4710 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4711 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4712 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4713 (clobber (match_scratch:SI 3 "=q,X"))]
4714 "TARGET_POWER"
4715 "@
4716 sle %0,%1,%2
4717 {sli|slwi} %0,%1,%h2")
4719 (define_insn "ashlsi3_no_power"
4720 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4721 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4722 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4723 "! TARGET_POWER"
4724 "@
4725 {sl|slw} %0,%1,%2
4726 {sli|slwi} %0,%1,%h2"
4727 [(set_attr "type" "var_shift_rotate,shift")])
4729 (define_insn "*ashlsi3_64"
4730 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4731 (zero_extend:DI
4732 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4733 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4734 "TARGET_POWERPC64"
4735 "@
4736 {sl|slw} %0,%1,%2
4737 {sli|slwi} %0,%1,%h2"
4738 [(set_attr "type" "var_shift_rotate,shift")])
4740 (define_insn ""
4741 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4742 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4743 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4744 (const_int 0)))
4745 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4746 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4747 "TARGET_POWER"
4748 "@
4749 sle. %3,%1,%2
4750 {sli.|slwi.} %3,%1,%h2
4751 #
4752 #"
4753 [(set_attr "type" "delayed_compare")
4754 (set_attr "length" "4,4,8,8")])
4756 (define_split
4757 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4758 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4759 (match_operand:SI 2 "reg_or_cint_operand" ""))
4760 (const_int 0)))
4761 (clobber (match_scratch:SI 3 ""))
4762 (clobber (match_scratch:SI 4 ""))]
4763 "TARGET_POWER && reload_completed"
4764 [(parallel [(set (match_dup 3)
4765 (ashift:SI (match_dup 1) (match_dup 2)))
4766 (clobber (match_dup 4))])
4767 (set (match_dup 0)
4768 (compare:CC (match_dup 3)
4769 (const_int 0)))]
4770 "")
4772 (define_insn ""
4773 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4774 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4775 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4776 (const_int 0)))
4777 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4778 "! TARGET_POWER && TARGET_32BIT"
4779 "@
4780 {sl.|slw.} %3,%1,%2
4781 {sli.|slwi.} %3,%1,%h2
4782 #
4783 #"
4784 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4785 (set_attr "length" "4,4,8,8")])
4787 (define_split
4788 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4789 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4790 (match_operand:SI 2 "reg_or_cint_operand" ""))
4791 (const_int 0)))
4792 (clobber (match_scratch:SI 3 ""))]
4793 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4794 [(set (match_dup 3)
4795 (ashift:SI (match_dup 1) (match_dup 2)))
4796 (set (match_dup 0)
4797 (compare:CC (match_dup 3)
4798 (const_int 0)))]
4799 "")
4801 (define_insn ""
4802 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4803 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4804 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4805 (const_int 0)))
4806 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4807 (ashift:SI (match_dup 1) (match_dup 2)))
4808 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4809 "TARGET_POWER"
4810 "@
4811 sle. %0,%1,%2
4812 {sli.|slwi.} %0,%1,%h2
4813 #
4814 #"
4815 [(set_attr "type" "delayed_compare")
4816 (set_attr "length" "4,4,8,8")])
4818 (define_split
4819 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4820 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4821 (match_operand:SI 2 "reg_or_cint_operand" ""))
4822 (const_int 0)))
4823 (set (match_operand:SI 0 "gpc_reg_operand" "")
4824 (ashift:SI (match_dup 1) (match_dup 2)))
4825 (clobber (match_scratch:SI 4 ""))]
4826 "TARGET_POWER && reload_completed"
4827 [(parallel [(set (match_dup 0)
4828 (ashift:SI (match_dup 1) (match_dup 2)))
4829 (clobber (match_dup 4))])
4830 (set (match_dup 3)
4831 (compare:CC (match_dup 0)
4832 (const_int 0)))]
4833 "")
4835 (define_insn ""
4836 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4837 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4838 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4839 (const_int 0)))
4840 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4841 (ashift:SI (match_dup 1) (match_dup 2)))]
4842 "! TARGET_POWER && TARGET_32BIT"
4843 "@
4844 {sl.|slw.} %0,%1,%2
4845 {sli.|slwi.} %0,%1,%h2
4846 #
4847 #"
4848 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4849 (set_attr "length" "4,4,8,8")])
4851 (define_split
4852 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4853 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4854 (match_operand:SI 2 "reg_or_cint_operand" ""))
4855 (const_int 0)))
4856 (set (match_operand:SI 0 "gpc_reg_operand" "")
4857 (ashift:SI (match_dup 1) (match_dup 2)))]
4858 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4859 [(set (match_dup 0)
4860 (ashift:SI (match_dup 1) (match_dup 2)))
4861 (set (match_dup 3)
4862 (compare:CC (match_dup 0)
4863 (const_int 0)))]
4864 "")
4866 (define_insn "rlwinm"
4867 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4868 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4869 (match_operand:SI 2 "const_int_operand" "i"))
4870 (match_operand:SI 3 "mask_operand" "n")))]
4871 "includes_lshift_p (operands[2], operands[3])"
4872 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4874 (define_insn ""
4875 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4876 (compare:CC
4877 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4878 (match_operand:SI 2 "const_int_operand" "i,i"))
4879 (match_operand:SI 3 "mask_operand" "n,n"))
4880 (const_int 0)))
4881 (clobber (match_scratch:SI 4 "=r,r"))]
4882 "includes_lshift_p (operands[2], operands[3])"
4883 "@
4884 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4885 #"
4886 [(set_attr "type" "delayed_compare")
4887 (set_attr "length" "4,8")])
4889 (define_split
4890 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4891 (compare:CC
4892 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4893 (match_operand:SI 2 "const_int_operand" ""))
4894 (match_operand:SI 3 "mask_operand" ""))
4895 (const_int 0)))
4896 (clobber (match_scratch:SI 4 ""))]
4897 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4898 [(set (match_dup 4)
4899 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4900 (match_dup 3)))
4901 (set (match_dup 0)
4902 (compare:CC (match_dup 4)
4903 (const_int 0)))]
4904 "")
4906 (define_insn ""
4907 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4908 (compare:CC
4909 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4910 (match_operand:SI 2 "const_int_operand" "i,i"))
4911 (match_operand:SI 3 "mask_operand" "n,n"))
4912 (const_int 0)))
4913 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4914 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4915 "includes_lshift_p (operands[2], operands[3])"
4916 "@
4917 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4918 #"
4919 [(set_attr "type" "delayed_compare")
4920 (set_attr "length" "4,8")])
4922 (define_split
4923 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4924 (compare:CC
4925 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4926 (match_operand:SI 2 "const_int_operand" ""))
4927 (match_operand:SI 3 "mask_operand" ""))
4928 (const_int 0)))
4929 (set (match_operand:SI 0 "gpc_reg_operand" "")
4930 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4931 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4932 [(set (match_dup 0)
4933 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4934 (set (match_dup 4)
4935 (compare:CC (match_dup 0)
4936 (const_int 0)))]
4937 "")
4939 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4940 ;; "sli x,x,0".
4941 (define_expand "lshrsi3"
4942 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4943 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4944 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4945 ""
4946 "
4947 {
4948 if (TARGET_POWER)
4949 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4950 else
4951 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4952 DONE;
4953 }")
4955 (define_insn "lshrsi3_power"
4956 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4957 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4958 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4959 (clobber (match_scratch:SI 3 "=q,X,X"))]
4960 "TARGET_POWER"
4961 "@
4962 sre %0,%1,%2
4963 mr %0,%1
4964 {s%A2i|s%A2wi} %0,%1,%h2")
4966 (define_insn "lshrsi3_no_power"
4967 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4968 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4969 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4970 "! TARGET_POWER"
4971 "@
4972 mr %0,%1
4973 {sr|srw} %0,%1,%2
4974 {sri|srwi} %0,%1,%h2"
4975 [(set_attr "type" "integer,var_shift_rotate,shift")])
4977 (define_insn "*lshrsi3_64"
4978 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4979 (zero_extend:DI
4980 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4981 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4982 "TARGET_POWERPC64"
4983 "@
4984 {sr|srw} %0,%1,%2
4985 {sri|srwi} %0,%1,%h2"
4986 [(set_attr "type" "var_shift_rotate,shift")])
4988 (define_insn ""
4989 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4990 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4991 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4992 (const_int 0)))
4993 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4994 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4995 "TARGET_POWER"
4996 "@
4997 sre. %3,%1,%2
4998 mr. %1,%1
4999 {s%A2i.|s%A2wi.} %3,%1,%h2
5000 #
5001 #
5002 #"
5003 [(set_attr "type" "delayed_compare")
5004 (set_attr "length" "4,4,4,8,8,8")])
5006 (define_split
5007 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5008 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5009 (match_operand:SI 2 "reg_or_cint_operand" ""))
5010 (const_int 0)))
5011 (clobber (match_scratch:SI 3 ""))
5012 (clobber (match_scratch:SI 4 ""))]
5013 "TARGET_POWER && reload_completed"
5014 [(parallel [(set (match_dup 3)
5015 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5016 (clobber (match_dup 4))])
5017 (set (match_dup 0)
5018 (compare:CC (match_dup 3)
5019 (const_int 0)))]
5020 "")
5022 (define_insn ""
5023 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5024 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5025 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5026 (const_int 0)))
5027 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
5028 "! TARGET_POWER && TARGET_32BIT"
5029 "@
5030 mr. %1,%1
5031 {sr.|srw.} %3,%1,%2
5032 {sri.|srwi.} %3,%1,%h2
5033 #
5034 #
5035 #"
5036 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5037 (set_attr "length" "4,4,4,8,8,8")])
5039 (define_split
5040 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5041 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5042 (match_operand:SI 2 "reg_or_cint_operand" ""))
5043 (const_int 0)))
5044 (clobber (match_scratch:SI 3 ""))]
5045 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5046 [(set (match_dup 3)
5047 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5048 (set (match_dup 0)
5049 (compare:CC (match_dup 3)
5050 (const_int 0)))]
5051 "")
5053 (define_insn ""
5054 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5055 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5056 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5057 (const_int 0)))
5058 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5059 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5060 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5061 "TARGET_POWER"
5062 "@
5063 sre. %0,%1,%2
5064 mr. %0,%1
5065 {s%A2i.|s%A2wi.} %0,%1,%h2
5066 #
5067 #
5068 #"
5069 [(set_attr "type" "delayed_compare")
5070 (set_attr "length" "4,4,4,8,8,8")])
5072 (define_split
5073 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5074 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5075 (match_operand:SI 2 "reg_or_cint_operand" ""))
5076 (const_int 0)))
5077 (set (match_operand:SI 0 "gpc_reg_operand" "")
5078 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5079 (clobber (match_scratch:SI 4 ""))]
5080 "TARGET_POWER && reload_completed"
5081 [(parallel [(set (match_dup 0)
5082 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5083 (clobber (match_dup 4))])
5084 (set (match_dup 3)
5085 (compare:CC (match_dup 0)
5086 (const_int 0)))]
5087 "")
5089 (define_insn ""
5090 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5091 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5092 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5093 (const_int 0)))
5094 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5095 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5096 "! TARGET_POWER && TARGET_32BIT"
5097 "@
5098 mr. %0,%1
5099 {sr.|srw.} %0,%1,%2
5100 {sri.|srwi.} %0,%1,%h2
5101 #
5102 #
5103 #"
5104 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5105 (set_attr "length" "4,4,4,8,8,8")])
5107 (define_split
5108 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5109 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5110 (match_operand:SI 2 "reg_or_cint_operand" ""))
5111 (const_int 0)))
5112 (set (match_operand:SI 0 "gpc_reg_operand" "")
5113 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5114 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5115 [(set (match_dup 0)
5116 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5117 (set (match_dup 3)
5118 (compare:CC (match_dup 0)
5119 (const_int 0)))]
5120 "")
5122 (define_insn ""
5123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5124 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5125 (match_operand:SI 2 "const_int_operand" "i"))
5126 (match_operand:SI 3 "mask_operand" "n")))]
5127 "includes_rshift_p (operands[2], operands[3])"
5128 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
5130 (define_insn ""
5131 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5132 (compare:CC
5133 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5134 (match_operand:SI 2 "const_int_operand" "i,i"))
5135 (match_operand:SI 3 "mask_operand" "n,n"))
5136 (const_int 0)))
5137 (clobber (match_scratch:SI 4 "=r,r"))]
5138 "includes_rshift_p (operands[2], operands[3])"
5139 "@
5140 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
5141 #"
5142 [(set_attr "type" "delayed_compare")
5143 (set_attr "length" "4,8")])
5145 (define_split
5146 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5147 (compare:CC
5148 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5149 (match_operand:SI 2 "const_int_operand" ""))
5150 (match_operand:SI 3 "mask_operand" ""))
5151 (const_int 0)))
5152 (clobber (match_scratch:SI 4 ""))]
5153 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5154 [(set (match_dup 4)
5155 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
5156 (match_dup 3)))
5157 (set (match_dup 0)
5158 (compare:CC (match_dup 4)
5159 (const_int 0)))]
5160 "")
5162 (define_insn ""
5163 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5164 (compare:CC
5165 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5166 (match_operand:SI 2 "const_int_operand" "i,i"))
5167 (match_operand:SI 3 "mask_operand" "n,n"))
5168 (const_int 0)))
5169 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5170 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5171 "includes_rshift_p (operands[2], operands[3])"
5172 "@
5173 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
5174 #"
5175 [(set_attr "type" "delayed_compare")
5176 (set_attr "length" "4,8")])
5178 (define_split
5179 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5180 (compare:CC
5181 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5182 (match_operand:SI 2 "const_int_operand" ""))
5183 (match_operand:SI 3 "mask_operand" ""))
5184 (const_int 0)))
5185 (set (match_operand:SI 0 "gpc_reg_operand" "")
5186 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5187 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5188 [(set (match_dup 0)
5189 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5190 (set (match_dup 4)
5191 (compare:CC (match_dup 0)
5192 (const_int 0)))]
5193 "")
5195 (define_insn ""
5196 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5197 (zero_extend:SI
5198 (subreg:QI
5199 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5200 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5201 "includes_rshift_p (operands[2], GEN_INT (255))"
5202 "{rlinm|rlwinm} %0,%1,%s2,0xff")
5204 (define_insn ""
5205 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5206 (compare:CC
5207 (zero_extend:SI
5208 (subreg:QI
5209 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5210 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5211 (const_int 0)))
5212 (clobber (match_scratch:SI 3 "=r,r"))]
5213 "includes_rshift_p (operands[2], GEN_INT (255))"
5214 "@
5215 {rlinm.|rlwinm.} %3,%1,%s2,0xff
5216 #"
5217 [(set_attr "type" "delayed_compare")
5218 (set_attr "length" "4,8")])
5220 (define_split
5221 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5222 (compare:CC
5223 (zero_extend:SI
5224 (subreg:QI
5225 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5226 (match_operand:SI 2 "const_int_operand" "")) 0))
5227 (const_int 0)))
5228 (clobber (match_scratch:SI 3 ""))]
5229 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5230 [(set (match_dup 3)
5231 (zero_extend:SI (subreg:QI
5232 (lshiftrt:SI (match_dup 1)
5233 (match_dup 2)) 0)))
5234 (set (match_dup 0)
5235 (compare:CC (match_dup 3)
5236 (const_int 0)))]
5237 "")
5239 (define_insn ""
5240 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5241 (compare:CC
5242 (zero_extend:SI
5243 (subreg:QI
5244 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5245 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5246 (const_int 0)))
5247 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5248 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5249 "includes_rshift_p (operands[2], GEN_INT (255))"
5250 "@
5251 {rlinm.|rlwinm.} %0,%1,%s2,0xff
5252 #"
5253 [(set_attr "type" "delayed_compare")
5254 (set_attr "length" "4,8")])
5256 (define_split
5257 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5258 (compare:CC
5259 (zero_extend:SI
5260 (subreg:QI
5261 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5262 (match_operand:SI 2 "const_int_operand" "")) 0))
5263 (const_int 0)))
5264 (set (match_operand:SI 0 "gpc_reg_operand" "")
5265 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5266 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5267 [(set (match_dup 0)
5268 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5269 (set (match_dup 3)
5270 (compare:CC (match_dup 0)
5271 (const_int 0)))]
5272 "")
5274 (define_insn ""
5275 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5276 (zero_extend:SI
5277 (subreg:HI
5278 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5279 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5280 "includes_rshift_p (operands[2], GEN_INT (65535))"
5281 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
5283 (define_insn ""
5284 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5285 (compare:CC
5286 (zero_extend:SI
5287 (subreg:HI
5288 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5289 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5290 (const_int 0)))
5291 (clobber (match_scratch:SI 3 "=r,r"))]
5292 "includes_rshift_p (operands[2], GEN_INT (65535))"
5293 "@
5294 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
5295 #"
5296 [(set_attr "type" "delayed_compare")
5297 (set_attr "length" "4,8")])
5299 (define_split
5300 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5301 (compare:CC
5302 (zero_extend:SI
5303 (subreg:HI
5304 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5305 (match_operand:SI 2 "const_int_operand" "")) 0))
5306 (const_int 0)))
5307 (clobber (match_scratch:SI 3 ""))]
5308 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5309 [(set (match_dup 3)
5310 (zero_extend:SI (subreg:HI
5311 (lshiftrt:SI (match_dup 1)
5312 (match_dup 2)) 0)))
5313 (set (match_dup 0)
5314 (compare:CC (match_dup 3)
5315 (const_int 0)))]
5316 "")
5318 (define_insn ""
5319 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5320 (compare:CC
5321 (zero_extend:SI
5322 (subreg:HI
5323 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5324 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5325 (const_int 0)))
5326 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5327 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5328 "includes_rshift_p (operands[2], GEN_INT (65535))"
5329 "@
5330 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
5331 #"
5332 [(set_attr "type" "delayed_compare")
5333 (set_attr "length" "4,8")])
5335 (define_split
5336 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5337 (compare:CC
5338 (zero_extend:SI
5339 (subreg:HI
5340 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5341 (match_operand:SI 2 "const_int_operand" "")) 0))
5342 (const_int 0)))
5343 (set (match_operand:SI 0 "gpc_reg_operand" "")
5344 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5345 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5346 [(set (match_dup 0)
5347 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5348 (set (match_dup 3)
5349 (compare:CC (match_dup 0)
5350 (const_int 0)))]
5351 "")
5353 (define_insn ""
5354 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5355 (const_int 1)
5356 (match_operand:SI 1 "gpc_reg_operand" "r"))
5357 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5358 (const_int 31)))]
5359 "TARGET_POWER"
5360 "rrib %0,%1,%2")
5362 (define_insn ""
5363 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5364 (const_int 1)
5365 (match_operand:SI 1 "gpc_reg_operand" "r"))
5366 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5367 (const_int 31)))]
5368 "TARGET_POWER"
5369 "rrib %0,%1,%2")
5371 (define_insn ""
5372 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5373 (const_int 1)
5374 (match_operand:SI 1 "gpc_reg_operand" "r"))
5375 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5376 (const_int 1)
5377 (const_int 0)))]
5378 "TARGET_POWER"
5379 "rrib %0,%1,%2")
5381 (define_expand "ashrsi3"
5382 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5383 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5384 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5385 ""
5386 "
5387 {
5388 if (TARGET_POWER)
5389 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
5390 else
5391 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
5392 DONE;
5393 }")
5395 (define_insn "ashrsi3_power"
5396 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5397 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5398 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
5399 (clobber (match_scratch:SI 3 "=q,X"))]
5400 "TARGET_POWER"
5401 "@
5402 srea %0,%1,%2
5403 {srai|srawi} %0,%1,%h2"
5404 [(set_attr "type" "shift")])
5406 (define_insn "ashrsi3_no_power"
5407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5408 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5409 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
5410 "! TARGET_POWER"
5411 "@
5412 {sra|sraw} %0,%1,%2
5413 {srai|srawi} %0,%1,%h2"
5414 [(set_attr "type" "var_shift_rotate,shift")])
5416 (define_insn "*ashrsi3_64"
5417 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5418 (sign_extend:DI
5419 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5420 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5421 "TARGET_POWERPC64"
5422 "@
5423 {sra|sraw} %0,%1,%2
5424 {srai|srawi} %0,%1,%h2"
5425 [(set_attr "type" "var_shift_rotate,shift")])
5427 (define_insn ""
5428 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5429 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5430 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5431 (const_int 0)))
5432 (clobber (match_scratch:SI 3 "=r,r,r,r"))
5433 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5434 "TARGET_POWER"
5435 "@
5436 srea. %3,%1,%2
5437 {srai.|srawi.} %3,%1,%h2
5438 #
5439 #"
5440 [(set_attr "type" "delayed_compare")
5441 (set_attr "length" "4,4,8,8")])
5443 (define_split
5444 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5445 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5446 (match_operand:SI 2 "reg_or_cint_operand" ""))
5447 (const_int 0)))
5448 (clobber (match_scratch:SI 3 ""))
5449 (clobber (match_scratch:SI 4 ""))]
5450 "TARGET_POWER && reload_completed"
5451 [(parallel [(set (match_dup 3)
5452 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5453 (clobber (match_dup 4))])
5454 (set (match_dup 0)
5455 (compare:CC (match_dup 3)
5456 (const_int 0)))]
5457 "")
5459 (define_insn ""
5460 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5461 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5462 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5463 (const_int 0)))
5464 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5465 "! TARGET_POWER"
5466 "@
5467 {sra.|sraw.} %3,%1,%2
5468 {srai.|srawi.} %3,%1,%h2
5469 #
5470 #"
5471 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5472 (set_attr "length" "4,4,8,8")])
5474 (define_split
5475 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5476 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5477 (match_operand:SI 2 "reg_or_cint_operand" ""))
5478 (const_int 0)))
5479 (clobber (match_scratch:SI 3 ""))]
5480 "! TARGET_POWER && reload_completed"
5481 [(set (match_dup 3)
5482 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5483 (set (match_dup 0)
5484 (compare:CC (match_dup 3)
5485 (const_int 0)))]
5486 "")
5488 (define_insn ""
5489 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5490 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5491 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5492 (const_int 0)))
5493 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5494 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5495 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5496 "TARGET_POWER"
5497 "@
5498 srea. %0,%1,%2
5499 {srai.|srawi.} %0,%1,%h2
5500 #
5501 #"
5502 [(set_attr "type" "delayed_compare")
5503 (set_attr "length" "4,4,8,8")])
5505 (define_split
5506 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5507 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5508 (match_operand:SI 2 "reg_or_cint_operand" ""))
5509 (const_int 0)))
5510 (set (match_operand:SI 0 "gpc_reg_operand" "")
5511 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5512 (clobber (match_scratch:SI 4 ""))]
5513 "TARGET_POWER && reload_completed"
5514 [(parallel [(set (match_dup 0)
5515 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5516 (clobber (match_dup 4))])
5517 (set (match_dup 3)
5518 (compare:CC (match_dup 0)
5519 (const_int 0)))]
5520 "")
5522 (define_insn ""
5523 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5524 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5525 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5526 (const_int 0)))
5527 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5528 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5529 "! TARGET_POWER"
5530 "@
5531 {sra.|sraw.} %0,%1,%2
5532 {srai.|srawi.} %0,%1,%h2
5533 #
5534 #"
5535 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5536 (set_attr "length" "4,4,8,8")])
5537 \f
5538 (define_split
5539 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5540 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5541 (match_operand:SI 2 "reg_or_cint_operand" ""))
5542 (const_int 0)))
5543 (set (match_operand:SI 0 "gpc_reg_operand" "")
5544 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5545 "! TARGET_POWER && reload_completed"
5546 [(set (match_dup 0)
5547 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5548 (set (match_dup 3)
5549 (compare:CC (match_dup 0)
5550 (const_int 0)))]
5551 "")
5553 ;; Floating-point insns, excluding normal data motion.
5554 ;;
5555 ;; PowerPC has a full set of single-precision floating point instructions.
5556 ;;
5557 ;; For the POWER architecture, we pretend that we have both SFmode and
5558 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5559 ;; The only conversions we will do will be when storing to memory. In that
5560 ;; case, we will use the "frsp" instruction before storing.
5561 ;;
5562 ;; Note that when we store into a single-precision memory location, we need to
5563 ;; use the frsp insn first. If the register being stored isn't dead, we
5564 ;; need a scratch register for the frsp. But this is difficult when the store
5565 ;; is done by reload. It is not incorrect to do the frsp on the register in
5566 ;; this case, we just lose precision that we would have otherwise gotten but
5567 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5569 (define_expand "extendsfdf2"
5570 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5571 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5572 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5573 "")
5575 (define_insn_and_split "*extendsfdf2_fpr"
5576 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5577 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5578 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5579 "@
5580 #
5581 fmr %0,%1
5582 lfs%U1%X1 %0,%1"
5583 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5584 [(const_int 0)]
5585 {
5586 emit_note (NOTE_INSN_DELETED);
5587 DONE;
5588 }
5589 [(set_attr "type" "fp,fp,fpload")])
5591 (define_expand "truncdfsf2"
5592 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5593 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5594 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5595 "")
5597 (define_insn "*truncdfsf2_fpr"
5598 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5599 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5600 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5601 "frsp %0,%1"
5602 [(set_attr "type" "fp")])
5604 (define_insn "aux_truncdfsf2"
5605 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5606 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5607 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5608 "frsp %0,%1"
5609 [(set_attr "type" "fp")])
5611 (define_expand "negsf2"
5612 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5613 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5614 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5615 "")
5617 (define_insn "*negsf2"
5618 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5619 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5620 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5621 "fneg %0,%1"
5622 [(set_attr "type" "fp")])
5624 (define_expand "abssf2"
5625 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5626 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5627 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5628 "")
5630 (define_insn "*abssf2"
5631 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5632 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5633 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5634 "fabs %0,%1"
5635 [(set_attr "type" "fp")])
5637 (define_insn ""
5638 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5639 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5640 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5641 "fnabs %0,%1"
5642 [(set_attr "type" "fp")])
5644 (define_expand "addsf3"
5645 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5646 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5647 (match_operand:SF 2 "gpc_reg_operand" "")))]
5648 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5649 "")
5651 (define_insn ""
5652 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5653 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5654 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5655 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5656 "fadds %0,%1,%2"
5657 [(set_attr "type" "fp")
5658 (set_attr "fp_type" "fp_addsub_s")])
5660 (define_insn ""
5661 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5662 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5663 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5664 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5665 "{fa|fadd} %0,%1,%2"
5666 [(set_attr "type" "fp")])
5668 (define_expand "subsf3"
5669 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5670 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5671 (match_operand:SF 2 "gpc_reg_operand" "")))]
5672 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5673 "")
5675 (define_insn ""
5676 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5677 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5678 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5679 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5680 "fsubs %0,%1,%2"
5681 [(set_attr "type" "fp")
5682 (set_attr "fp_type" "fp_addsub_s")])
5684 (define_insn ""
5685 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5686 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5687 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5688 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5689 "{fs|fsub} %0,%1,%2"
5690 [(set_attr "type" "fp")])
5692 (define_expand "mulsf3"
5693 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5694 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5695 (match_operand:SF 2 "gpc_reg_operand" "")))]
5696 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5697 "")
5699 (define_insn ""
5700 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5701 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5702 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5703 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5704 "fmuls %0,%1,%2"
5705 [(set_attr "type" "fp")
5706 (set_attr "fp_type" "fp_mul_s")])
5708 (define_insn ""
5709 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5710 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5711 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5712 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5713 "{fm|fmul} %0,%1,%2"
5714 [(set_attr "type" "dmul")])
5716 (define_expand "divsf3"
5717 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5718 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5719 (match_operand:SF 2 "gpc_reg_operand" "")))]
5720 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5721 "")
5723 (define_insn ""
5724 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5725 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5726 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5727 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5728 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5729 "fdivs %0,%1,%2"
5730 [(set_attr "type" "sdiv")])
5732 (define_insn ""
5733 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5734 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5735 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5736 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5737 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5738 "{fd|fdiv} %0,%1,%2"
5739 [(set_attr "type" "ddiv")])
5741 (define_expand "recipsf3"
5742 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5743 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5744 (match_operand:SF 2 "gpc_reg_operand" "f")]
5745 UNSPEC_FRES))]
5746 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5747 && flag_finite_math_only && !flag_trapping_math"
5748 {
5749 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5750 DONE;
5751 })
5753 (define_insn "fres"
5754 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5755 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5756 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5757 "fres %0,%1"
5758 [(set_attr "type" "fp")])
5760 (define_insn "*fmaddsf4_powerpc"
5761 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5762 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5763 (match_operand:SF 2 "gpc_reg_operand" "f"))
5764 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5765 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5766 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5767 "fmadds %0,%1,%2,%3"
5768 [(set_attr "type" "fp")
5769 (set_attr "fp_type" "fp_maddsub_s")])
5771 (define_insn "*fmaddsf4_power"
5772 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5773 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5774 (match_operand:SF 2 "gpc_reg_operand" "f"))
5775 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5776 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5777 "{fma|fmadd} %0,%1,%2,%3"
5778 [(set_attr "type" "dmul")])
5780 (define_insn "*fmsubsf4_powerpc"
5781 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5782 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5783 (match_operand:SF 2 "gpc_reg_operand" "f"))
5784 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5785 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5786 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5787 "fmsubs %0,%1,%2,%3"
5788 [(set_attr "type" "fp")
5789 (set_attr "fp_type" "fp_maddsub_s")])
5791 (define_insn "*fmsubsf4_power"
5792 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5793 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5794 (match_operand:SF 2 "gpc_reg_operand" "f"))
5795 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5796 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5797 "{fms|fmsub} %0,%1,%2,%3"
5798 [(set_attr "type" "dmul")])
5800 (define_insn "*fnmaddsf4_powerpc_1"
5801 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5802 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5803 (match_operand:SF 2 "gpc_reg_operand" "f"))
5804 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5805 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5806 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5807 "fnmadds %0,%1,%2,%3"
5808 [(set_attr "type" "fp")
5809 (set_attr "fp_type" "fp_maddsub_s")])
5811 (define_insn "*fnmaddsf4_powerpc_2"
5812 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5813 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5814 (match_operand:SF 2 "gpc_reg_operand" "f"))
5815 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5816 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5817 && ! HONOR_SIGNED_ZEROS (SFmode)"
5818 "fnmadds %0,%1,%2,%3"
5819 [(set_attr "type" "fp")
5820 (set_attr "fp_type" "fp_maddsub_s")])
5822 (define_insn "*fnmaddsf4_power_1"
5823 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5824 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5825 (match_operand:SF 2 "gpc_reg_operand" "f"))
5826 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5827 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5828 "{fnma|fnmadd} %0,%1,%2,%3"
5829 [(set_attr "type" "dmul")])
5831 (define_insn "*fnmaddsf4_power_2"
5832 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5833 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5834 (match_operand:SF 2 "gpc_reg_operand" "f"))
5835 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5836 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5837 && ! HONOR_SIGNED_ZEROS (SFmode)"
5838 "{fnma|fnmadd} %0,%1,%2,%3"
5839 [(set_attr "type" "dmul")])
5841 (define_insn "*fnmsubsf4_powerpc_1"
5842 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5843 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5844 (match_operand:SF 2 "gpc_reg_operand" "f"))
5845 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5846 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5847 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5848 "fnmsubs %0,%1,%2,%3"
5849 [(set_attr "type" "fp")
5850 (set_attr "fp_type" "fp_maddsub_s")])
5852 (define_insn "*fnmsubsf4_powerpc_2"
5853 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5854 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5855 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5856 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5857 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5858 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5859 "fnmsubs %0,%1,%2,%3"
5860 [(set_attr "type" "fp")
5861 (set_attr "fp_type" "fp_maddsub_s")])
5863 (define_insn "*fnmsubsf4_power_1"
5864 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5865 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5866 (match_operand:SF 2 "gpc_reg_operand" "f"))
5867 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5868 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5869 "{fnms|fnmsub} %0,%1,%2,%3"
5870 [(set_attr "type" "dmul")])
5872 (define_insn "*fnmsubsf4_power_2"
5873 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5874 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5875 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5876 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5877 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5878 && ! HONOR_SIGNED_ZEROS (SFmode)"
5879 "{fnms|fnmsub} %0,%1,%2,%3"
5880 [(set_attr "type" "dmul")])
5882 (define_expand "sqrtsf2"
5883 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5884 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5885 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5886 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5887 && !TARGET_SIMPLE_FPU"
5888 "")
5890 (define_insn ""
5891 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5892 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5893 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5894 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5895 "fsqrts %0,%1"
5896 [(set_attr "type" "ssqrt")])
5898 (define_insn ""
5899 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5900 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5901 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5902 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5903 "fsqrt %0,%1"
5904 [(set_attr "type" "dsqrt")])
5906 (define_expand "rsqrtsf2"
5907 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5908 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5909 UNSPEC_RSQRT))]
5910 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5911 && flag_finite_math_only && !flag_trapping_math"
5912 {
5913 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5914 DONE;
5915 })
5917 (define_insn "*rsqrt_internal1"
5918 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5919 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5920 UNSPEC_RSQRT))]
5921 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5922 "frsqrte %0,%1"
5923 [(set_attr "type" "fp")])
5925 (define_expand "copysignsf3"
5926 [(set (match_dup 3)
5927 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5928 (set (match_dup 4)
5929 (neg:SF (abs:SF (match_dup 1))))
5930 (set (match_operand:SF 0 "gpc_reg_operand" "")
5931 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5932 (match_dup 5))
5933 (match_dup 3)
5934 (match_dup 4)))]
5935 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5936 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5937 {
5938 operands[3] = gen_reg_rtx (SFmode);
5939 operands[4] = gen_reg_rtx (SFmode);
5940 operands[5] = CONST0_RTX (SFmode);
5941 })
5943 (define_expand "copysigndf3"
5944 [(set (match_dup 3)
5945 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5946 (set (match_dup 4)
5947 (neg:DF (abs:DF (match_dup 1))))
5948 (set (match_operand:DF 0 "gpc_reg_operand" "")
5949 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5950 (match_dup 5))
5951 (match_dup 3)
5952 (match_dup 4)))]
5953 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5954 && ((TARGET_PPC_GFXOPT
5955 && !HONOR_NANS (DFmode)
5956 && !HONOR_SIGNED_ZEROS (DFmode))
5957 || VECTOR_UNIT_VSX_P (DFmode))"
5958 {
5959 if (VECTOR_UNIT_VSX_P (DFmode))
5960 {
5961 emit_insn (gen_vsx_copysigndf3 (operands[0], operands[1],
5962 operands[2], CONST0_RTX (DFmode)));
5963 DONE;
5964 }
5965 operands[3] = gen_reg_rtx (DFmode);
5966 operands[4] = gen_reg_rtx (DFmode);
5967 operands[5] = CONST0_RTX (DFmode);
5968 })
5970 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5971 ;; fsel instruction and some auxiliary computations. Then we just have a
5972 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5973 ;; combine.
5974 (define_expand "smaxsf3"
5975 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5976 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5977 (match_operand:SF 2 "gpc_reg_operand" ""))
5978 (match_dup 1)
5979 (match_dup 2)))]
5980 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5981 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5982 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5984 (define_expand "sminsf3"
5985 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5986 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5987 (match_operand:SF 2 "gpc_reg_operand" ""))
5988 (match_dup 2)
5989 (match_dup 1)))]
5990 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5991 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5992 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5994 (define_split
5995 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5996 (match_operator:SF 3 "min_max_operator"
5997 [(match_operand:SF 1 "gpc_reg_operand" "")
5998 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5999 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6000 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6001 [(const_int 0)]
6002 "
6003 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6004 operands[1], operands[2]);
6005 DONE;
6006 }")
6008 (define_expand "mov<mode>cc"
6009 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
6010 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6011 (match_operand:GPR 2 "gpc_reg_operand" "")
6012 (match_operand:GPR 3 "gpc_reg_operand" "")))]
6013 "TARGET_ISEL<sel>"
6014 "
6015 {
6016 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6017 DONE;
6018 else
6019 FAIL;
6020 }")
6022 ;; We use the BASE_REGS for the isel input operands because, if rA is
6023 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
6024 ;; because we may switch the operands and rB may end up being rA.
6025 ;;
6026 ;; We need 2 patterns: an unsigned and a signed pattern. We could
6027 ;; leave out the mode in operand 4 and use one pattern, but reload can
6028 ;; change the mode underneath our feet and then gets confused trying
6029 ;; to reload the value.
6030 (define_insn "isel_signed_<mode>"
6031 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6032 (if_then_else:GPR
6033 (match_operator 1 "comparison_operator"
6034 [(match_operand:CC 4 "cc_reg_operand" "y")
6035 (const_int 0)])
6036 (match_operand:GPR 2 "gpc_reg_operand" "b")
6037 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6038 "TARGET_ISEL<sel>"
6039 "*
6040 { return output_isel (operands); }"
6041 [(set_attr "length" "4")])
6043 (define_insn "isel_unsigned_<mode>"
6044 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6045 (if_then_else:GPR
6046 (match_operator 1 "comparison_operator"
6047 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
6048 (const_int 0)])
6049 (match_operand:GPR 2 "gpc_reg_operand" "b")
6050 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6051 "TARGET_ISEL<sel>"
6052 "*
6053 { return output_isel (operands); }"
6054 [(set_attr "length" "4")])
6056 (define_expand "movsfcc"
6057 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6058 (if_then_else:SF (match_operand 1 "comparison_operator" "")
6059 (match_operand:SF 2 "gpc_reg_operand" "")
6060 (match_operand:SF 3 "gpc_reg_operand" "")))]
6061 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6062 "
6063 {
6064 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6065 DONE;
6066 else
6067 FAIL;
6068 }")
6070 (define_insn "*fselsfsf4"
6071 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6072 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6073 (match_operand:SF 4 "zero_fp_constant" "F"))
6074 (match_operand:SF 2 "gpc_reg_operand" "f")
6075 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6076 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6077 "fsel %0,%1,%2,%3"
6078 [(set_attr "type" "fp")])
6080 (define_insn "*fseldfsf4"
6081 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6082 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6083 (match_operand:DF 4 "zero_fp_constant" "F"))
6084 (match_operand:SF 2 "gpc_reg_operand" "f")
6085 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6086 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6087 "fsel %0,%1,%2,%3"
6088 [(set_attr "type" "fp")])
6090 (define_expand "negdf2"
6091 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6092 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6093 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6094 "")
6096 (define_insn "*negdf2_fpr"
6097 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6098 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6099 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6100 && !VECTOR_UNIT_VSX_P (DFmode)"
6101 "fneg %0,%1"
6102 [(set_attr "type" "fp")])
6104 (define_expand "absdf2"
6105 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6106 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6107 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6108 "")
6110 (define_insn "*absdf2_fpr"
6111 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6112 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6113 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6114 && !VECTOR_UNIT_VSX_P (DFmode)"
6115 "fabs %0,%1"
6116 [(set_attr "type" "fp")])
6118 (define_insn "*nabsdf2_fpr"
6119 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6120 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6121 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6122 && !VECTOR_UNIT_VSX_P (DFmode)"
6123 "fnabs %0,%1"
6124 [(set_attr "type" "fp")])
6126 (define_expand "adddf3"
6127 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6128 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6129 (match_operand:DF 2 "gpc_reg_operand" "")))]
6130 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6131 "")
6133 (define_insn "*adddf3_fpr"
6134 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6135 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6136 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6137 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6138 && !VECTOR_UNIT_VSX_P (DFmode)"
6139 "{fa|fadd} %0,%1,%2"
6140 [(set_attr "type" "fp")
6141 (set_attr "fp_type" "fp_addsub_d")])
6143 (define_expand "subdf3"
6144 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6145 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6146 (match_operand:DF 2 "gpc_reg_operand" "")))]
6147 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6148 "")
6150 (define_insn "*subdf3_fpr"
6151 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6152 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6153 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6154 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6155 && !VECTOR_UNIT_VSX_P (DFmode)"
6156 "{fs|fsub} %0,%1,%2"
6157 [(set_attr "type" "fp")
6158 (set_attr "fp_type" "fp_addsub_d")])
6160 (define_expand "muldf3"
6161 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6162 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
6163 (match_operand:DF 2 "gpc_reg_operand" "")))]
6164 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6165 "")
6167 (define_insn "*muldf3_fpr"
6168 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6169 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6170 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6171 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6172 && !VECTOR_UNIT_VSX_P (DFmode)"
6173 "{fm|fmul} %0,%1,%2"
6174 [(set_attr "type" "dmul")
6175 (set_attr "fp_type" "fp_mul_d")])
6177 (define_expand "divdf3"
6178 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6179 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
6180 (match_operand:DF 2 "gpc_reg_operand" "")))]
6181 "TARGET_HARD_FLOAT
6182 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
6183 && !TARGET_SIMPLE_FPU"
6184 "")
6186 (define_insn "*divdf3_fpr"
6187 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6188 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6189 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6190 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
6191 && !VECTOR_UNIT_VSX_P (DFmode)"
6192 "{fd|fdiv} %0,%1,%2"
6193 [(set_attr "type" "ddiv")])
6195 (define_expand "recipdf3"
6196 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6197 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")
6198 (match_operand:DF 2 "gpc_reg_operand" "d")]
6199 UNSPEC_FRES))]
6200 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
6201 && flag_finite_math_only && !flag_trapping_math"
6202 {
6203 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
6204 DONE;
6205 })
6207 (define_expand "fred"
6208 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6209 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRES))]
6210 "(TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)) && flag_finite_math_only"
6211 "")
6213 (define_insn "*fred_fpr"
6214 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6215 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
6216 "TARGET_POPCNTB && flag_finite_math_only && !VECTOR_UNIT_VSX_P (DFmode)"
6217 "fre %0,%1"
6218 [(set_attr "type" "fp")])
6220 (define_insn "*fmadddf4_fpr"
6221 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6222 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6223 (match_operand:DF 2 "gpc_reg_operand" "d"))
6224 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6225 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6226 && VECTOR_UNIT_NONE_P (DFmode)"
6227 "{fma|fmadd} %0,%1,%2,%3"
6228 [(set_attr "type" "dmul")
6229 (set_attr "fp_type" "fp_maddsub_d")])
6231 (define_insn "*fmsubdf4_fpr"
6232 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6233 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6234 (match_operand:DF 2 "gpc_reg_operand" "d"))
6235 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6236 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6237 && VECTOR_UNIT_NONE_P (DFmode)"
6238 "{fms|fmsub} %0,%1,%2,%3"
6239 [(set_attr "type" "dmul")
6240 (set_attr "fp_type" "fp_maddsub_d")])
6242 (define_insn "*fnmadddf4_fpr_1"
6243 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6244 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6245 (match_operand:DF 2 "gpc_reg_operand" "d"))
6246 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6247 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6248 && HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6249 "{fnma|fnmadd} %0,%1,%2,%3"
6250 [(set_attr "type" "dmul")
6251 (set_attr "fp_type" "fp_maddsub_d")])
6253 (define_insn "*fnmadddf4_fpr_2"
6254 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6255 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d"))
6256 (match_operand:DF 2 "gpc_reg_operand" "d"))
6257 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6258 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6259 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6260 "{fnma|fnmadd} %0,%1,%2,%3"
6261 [(set_attr "type" "dmul")
6262 (set_attr "fp_type" "fp_maddsub_d")])
6264 (define_insn "*fnmsubdf4_fpr_1"
6265 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6266 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6267 (match_operand:DF 2 "gpc_reg_operand" "d"))
6268 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6269 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6270 && HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6271 "{fnms|fnmsub} %0,%1,%2,%3"
6272 [(set_attr "type" "dmul")
6273 (set_attr "fp_type" "fp_maddsub_d")])
6275 (define_insn "*fnmsubdf4_fpr_2"
6276 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6277 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "d")
6278 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6279 (match_operand:DF 2 "gpc_reg_operand" "d"))))]
6280 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6281 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6282 "{fnms|fnmsub} %0,%1,%2,%3"
6283 [(set_attr "type" "dmul")
6284 (set_attr "fp_type" "fp_maddsub_d")])
6286 (define_insn "sqrtdf2"
6287 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6288 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6289 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6290 && TARGET_DOUBLE_FLOAT
6291 && !VECTOR_UNIT_VSX_P (DFmode)"
6292 "fsqrt %0,%1"
6293 [(set_attr "type" "dsqrt")])
6295 ;; The conditional move instructions allow us to perform max and min
6296 ;; operations even when
6298 (define_expand "smaxdf3"
6299 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6300 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6301 (match_operand:DF 2 "gpc_reg_operand" ""))
6302 (match_dup 1)
6303 (match_dup 2)))]
6304 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6305 && !flag_trapping_math"
6306 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6308 (define_expand "smindf3"
6309 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6310 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6311 (match_operand:DF 2 "gpc_reg_operand" ""))
6312 (match_dup 2)
6313 (match_dup 1)))]
6314 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6315 && !flag_trapping_math"
6316 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6318 (define_split
6319 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6320 (match_operator:DF 3 "min_max_operator"
6321 [(match_operand:DF 1 "gpc_reg_operand" "")
6322 (match_operand:DF 2 "gpc_reg_operand" "")]))]
6323 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6324 && !flag_trapping_math"
6325 [(const_int 0)]
6326 "
6327 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6328 operands[1], operands[2]);
6329 DONE;
6330 }")
6332 (define_expand "movdfcc"
6333 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6334 (if_then_else:DF (match_operand 1 "comparison_operator" "")
6335 (match_operand:DF 2 "gpc_reg_operand" "")
6336 (match_operand:DF 3 "gpc_reg_operand" "")))]
6337 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6338 "
6339 {
6340 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6341 DONE;
6342 else
6343 FAIL;
6344 }")
6346 (define_insn "*fseldfdf4"
6347 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6348 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6349 (match_operand:DF 4 "zero_fp_constant" "F"))
6350 (match_operand:DF 2 "gpc_reg_operand" "d")
6351 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6352 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6353 "fsel %0,%1,%2,%3"
6354 [(set_attr "type" "fp")])
6356 (define_insn "*fselsfdf4"
6357 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6358 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6359 (match_operand:SF 4 "zero_fp_constant" "F"))
6360 (match_operand:DF 2 "gpc_reg_operand" "d")
6361 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6362 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6363 "fsel %0,%1,%2,%3"
6364 [(set_attr "type" "fp")])
6365 \f
6366 ;; Conversions to and from floating-point.
6368 (define_expand "fixuns_truncsfsi2"
6369 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6370 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6371 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6372 "")
6374 (define_expand "fix_truncsfsi2"
6375 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6376 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6377 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6378 "")
6380 (define_expand "fixuns_truncdfsi2"
6381 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6382 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
6383 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
6384 "")
6386 (define_expand "fixuns_truncdfdi2"
6387 [(set (match_operand:DI 0 "register_operand" "")
6388 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
6389 "TARGET_HARD_FLOAT && TARGET_VSX"
6390 "")
6392 ; For each of these conversions, there is a define_expand, a define_insn
6393 ; with a '#' template, and a define_split (with C code). The idea is
6394 ; to allow constant folding with the template of the define_insn,
6395 ; then to have the insns split later (between sched1 and final).
6397 (define_expand "floatsidf2"
6398 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6399 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6400 (use (match_dup 2))
6401 (use (match_dup 3))
6402 (clobber (match_dup 4))
6403 (clobber (match_dup 5))
6404 (clobber (match_dup 6))])]
6405 "TARGET_HARD_FLOAT
6406 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6407 "
6408 {
6409 if (TARGET_E500_DOUBLE)
6410 {
6411 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
6412 DONE;
6413 }
6414 if (TARGET_POWERPC64)
6415 {
6416 rtx x = convert_to_mode (DImode, operands[1], 0);
6417 emit_insn (gen_floatdidf2 (operands[0], x));
6418 DONE;
6419 }
6421 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6422 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
6423 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6424 operands[5] = gen_reg_rtx (DFmode);
6425 operands[6] = gen_reg_rtx (SImode);
6426 }")
6428 (define_insn_and_split "*floatsidf2_internal"
6429 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6430 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6431 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6432 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6433 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6434 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
6435 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
6436 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6437 "#"
6438 ""
6439 [(pc)]
6440 "
6441 {
6442 rtx lowword, highword;
6443 gcc_assert (MEM_P (operands[4]));
6444 highword = adjust_address (operands[4], SImode, 0);
6445 lowword = adjust_address (operands[4], SImode, 4);
6446 if (! WORDS_BIG_ENDIAN)
6447 {
6448 rtx tmp;
6449 tmp = highword; highword = lowword; lowword = tmp;
6450 }
6452 emit_insn (gen_xorsi3 (operands[6], operands[1],
6453 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
6454 emit_move_insn (lowword, operands[6]);
6455 emit_move_insn (highword, operands[2]);
6456 emit_move_insn (operands[5], operands[4]);
6457 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6458 DONE;
6459 }"
6460 [(set_attr "length" "24")])
6462 (define_expand "floatunssisf2"
6463 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6464 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6465 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6466 "")
6468 (define_expand "floatunssidf2"
6469 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6470 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6471 (use (match_dup 2))
6472 (use (match_dup 3))
6473 (clobber (match_dup 4))
6474 (clobber (match_dup 5))])]
6475 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6476 "
6477 {
6478 if (TARGET_E500_DOUBLE)
6479 {
6480 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6481 DONE;
6482 }
6483 if (TARGET_POWERPC64)
6484 {
6485 rtx x = convert_to_mode (DImode, operands[1], 1);
6486 emit_insn (gen_floatdidf2 (operands[0], x));
6487 DONE;
6488 }
6490 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6491 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6492 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6493 operands[5] = gen_reg_rtx (DFmode);
6494 }")
6496 (define_insn_and_split "*floatunssidf2_internal"
6497 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6498 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6499 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6500 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6501 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6502 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6503 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6504 "#"
6505 ""
6506 [(pc)]
6507 "
6508 {
6509 rtx lowword, highword;
6510 gcc_assert (MEM_P (operands[4]));
6511 highword = adjust_address (operands[4], SImode, 0);
6512 lowword = adjust_address (operands[4], SImode, 4);
6513 if (! WORDS_BIG_ENDIAN)
6514 {
6515 rtx tmp;
6516 tmp = highword; highword = lowword; lowword = tmp;
6517 }
6519 emit_move_insn (lowword, operands[1]);
6520 emit_move_insn (highword, operands[2]);
6521 emit_move_insn (operands[5], operands[4]);
6522 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6523 DONE;
6524 }"
6525 [(set_attr "length" "20")])
6527 (define_expand "fix_truncdfsi2"
6528 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
6529 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
6530 (clobber (match_dup 2))
6531 (clobber (match_dup 3))])]
6532 "(TARGET_POWER2 || TARGET_POWERPC)
6533 && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6534 "
6535 {
6536 if (TARGET_E500_DOUBLE)
6537 {
6538 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
6539 DONE;
6540 }
6541 operands[2] = gen_reg_rtx (DImode);
6542 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6543 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
6544 {
6545 operands[3] = gen_reg_rtx (DImode);
6546 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
6547 operands[2], operands[3]));
6548 DONE;
6549 }
6550 if (TARGET_PPC_GFXOPT)
6551 {
6552 rtx orig_dest = operands[0];
6553 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
6554 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
6555 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
6556 operands[2]));
6557 if (operands[0] != orig_dest)
6558 emit_move_insn (orig_dest, operands[0]);
6559 DONE;
6560 }
6561 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
6562 }")
6564 (define_insn_and_split "*fix_truncdfsi2_internal"
6565 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6566 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6567 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6568 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6569 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6570 && TARGET_DOUBLE_FLOAT"
6571 "#"
6572 ""
6573 [(pc)]
6574 "
6575 {
6576 rtx lowword;
6577 gcc_assert (MEM_P (operands[3]));
6578 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6580 emit_insn (gen_fctiwz (operands[2], operands[1]));
6581 emit_move_insn (operands[3], operands[2]);
6582 emit_move_insn (operands[0], lowword);
6583 DONE;
6584 }"
6585 [(set_attr "length" "16")])
6587 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6588 [(set (match_operand:SI 0 "memory_operand" "=Z")
6589 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6590 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))]
6591 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6592 && TARGET_DOUBLE_FLOAT
6593 && TARGET_PPC_GFXOPT"
6594 "#"
6595 "&& 1"
6596 [(pc)]
6597 "
6598 {
6599 emit_insn (gen_fctiwz (operands[2], operands[1]));
6600 emit_insn (gen_stfiwx (operands[0], operands[2]));
6601 DONE;
6602 }"
6603 [(set_attr "length" "16")])
6605 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6606 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6607 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6608 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6609 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6610 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6611 && TARGET_DOUBLE_FLOAT"
6612 "#"
6613 "&& 1"
6614 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6615 (set (match_dup 3) (match_dup 2))
6616 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6617 ""
6618 [(set_attr "length" "12")])
6620 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6621 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6622 ; because the first makes it clear that operand 0 is not live
6623 ; before the instruction.
6624 (define_insn "fctiwz"
6625 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6626 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))]
6627 UNSPEC_FCTIWZ))]
6628 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6629 && TARGET_DOUBLE_FLOAT"
6630 "{fcirz|fctiwz} %0,%1"
6631 [(set_attr "type" "fp")])
6633 (define_expand "btruncdf2"
6634 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6635 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIZ))]
6636 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6637 "")
6639 (define_insn "*btruncdf2_fpr"
6640 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6641 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6642 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6643 && !VECTOR_UNIT_VSX_P (DFmode)"
6644 "friz %0,%1"
6645 [(set_attr "type" "fp")])
6647 (define_insn "btruncsf2"
6648 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6649 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6650 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6651 "friz %0,%1"
6652 [(set_attr "type" "fp")])
6654 (define_expand "ceildf2"
6655 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6656 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIP))]
6657 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6658 "")
6660 (define_insn "*ceildf2_fpr"
6661 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6662 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIP))]
6663 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6664 && !VECTOR_UNIT_VSX_P (DFmode)"
6665 "frip %0,%1"
6666 [(set_attr "type" "fp")])
6668 (define_insn "ceilsf2"
6669 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6670 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6671 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6672 "frip %0,%1"
6673 [(set_attr "type" "fp")])
6675 (define_expand "floordf2"
6676 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6677 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIM))]
6678 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6679 "")
6681 (define_insn "*floordf2_fpr"
6682 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6683 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIM))]
6684 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6685 && !VECTOR_UNIT_VSX_P (DFmode)"
6686 "frim %0,%1"
6687 [(set_attr "type" "fp")])
6689 (define_insn "floorsf2"
6690 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6691 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6692 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6693 "frim %0,%1"
6694 [(set_attr "type" "fp")])
6696 ;; No VSX equivalent to frin
6697 (define_insn "rounddf2"
6698 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6699 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIN))]
6700 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6701 "frin %0,%1"
6702 [(set_attr "type" "fp")])
6704 (define_insn "roundsf2"
6705 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6706 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6707 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6708 "frin %0,%1"
6709 [(set_attr "type" "fp")])
6711 (define_expand "ftruncdf2"
6712 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6713 (fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6714 "VECTOR_UNIT_VSX_P (DFmode)"
6715 "")
6717 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6718 (define_insn "stfiwx"
6719 [(set (match_operand:SI 0 "memory_operand" "=Z")
6720 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6721 UNSPEC_STFIWX))]
6722 "TARGET_PPC_GFXOPT"
6723 "stfiwx %1,%y0"
6724 [(set_attr "type" "fpstore")])
6726 (define_expand "floatsisf2"
6727 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6728 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6729 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6730 "")
6732 (define_expand "floatdidf2"
6733 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6734 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6735 "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6736 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6737 "")
6739 (define_insn "*floatdidf2_fpr"
6740 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6741 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))]
6742 "(TARGET_POWERPC64 || TARGET_XILINX_FPU)
6743 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6744 && !VECTOR_UNIT_VSX_P (DFmode)"
6745 "fcfid %0,%1"
6746 [(set_attr "type" "fp")])
6748 (define_expand "floatunsdidf2"
6749 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6750 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6751 "TARGET_VSX"
6752 "")
6754 (define_expand "fix_truncdfdi2"
6755 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6756 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "")))]
6757 "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6758 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6759 "")
6761 (define_insn "*fix_truncdfdi2_fpr"
6762 [(set (match_operand:DI 0 "gpc_reg_operand" "=!d#r")
6763 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d")))]
6764 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
6765 && TARGET_DOUBLE_FLOAT && TARGET_FPRS && !VECTOR_UNIT_VSX_P (DFmode)"
6766 "fctidz %0,%1"
6767 [(set_attr "type" "fp")])
6769 (define_expand "floatdisf2"
6770 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6771 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6772 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6773 "
6774 {
6775 rtx val = operands[1];
6776 if (!flag_unsafe_math_optimizations)
6777 {
6778 rtx label = gen_label_rtx ();
6779 val = gen_reg_rtx (DImode);
6780 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6781 emit_label (label);
6782 }
6783 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6784 DONE;
6785 }")
6787 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6788 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6789 ;; from double rounding.
6790 (define_insn_and_split "floatdisf2_internal1"
6791 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6792 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))
6793 (clobber (match_scratch:DF 2 "=d"))]
6794 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6795 "#"
6796 "&& reload_completed"
6797 [(set (match_dup 2)
6798 (float:DF (match_dup 1)))
6799 (set (match_dup 0)
6800 (float_truncate:SF (match_dup 2)))]
6801 "")
6803 ;; Twiddles bits to avoid double rounding.
6804 ;; Bits that might be truncated when converting to DFmode are replaced
6805 ;; by a bit that won't be lost at that stage, but is below the SFmode
6806 ;; rounding position.
6807 (define_expand "floatdisf2_internal2"
6808 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6809 (const_int 53)))
6810 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6811 (const_int 2047)))
6812 (clobber (scratch:CC))])
6813 (set (match_dup 3) (plus:DI (match_dup 3)
6814 (const_int 1)))
6815 (set (match_dup 0) (plus:DI (match_dup 0)
6816 (const_int 2047)))
6817 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6818 (const_int 2)))
6819 (set (match_dup 0) (ior:DI (match_dup 0)
6820 (match_dup 1)))
6821 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6822 (const_int -2048)))
6823 (clobber (scratch:CC))])
6824 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6825 (label_ref (match_operand:DI 2 "" ""))
6826 (pc)))
6827 (set (match_dup 0) (match_dup 1))]
6828 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6829 "
6830 {
6831 operands[3] = gen_reg_rtx (DImode);
6832 operands[4] = gen_reg_rtx (CCUNSmode);
6833 }")
6834 \f
6835 ;; Define the DImode operations that can be done in a small number
6836 ;; of instructions. The & constraints are to prevent the register
6837 ;; allocator from allocating registers that overlap with the inputs
6838 ;; (for example, having an input in 7,8 and an output in 6,7). We
6839 ;; also allow for the output being the same as one of the inputs.
6841 (define_insn "*adddi3_noppc64"
6842 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6843 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6844 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6845 "! TARGET_POWERPC64"
6846 "*
6847 {
6848 if (WORDS_BIG_ENDIAN)
6849 return (GET_CODE (operands[2])) != CONST_INT
6850 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6851 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6852 else
6853 return (GET_CODE (operands[2])) != CONST_INT
6854 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6855 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6856 }"
6857 [(set_attr "type" "two")
6858 (set_attr "length" "8")])
6860 (define_insn "*subdi3_noppc64"
6861 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6862 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6863 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6864 "! TARGET_POWERPC64"
6865 "*
6866 {
6867 if (WORDS_BIG_ENDIAN)
6868 return (GET_CODE (operands[1]) != CONST_INT)
6869 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6870 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6871 else
6872 return (GET_CODE (operands[1]) != CONST_INT)
6873 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6874 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6875 }"
6876 [(set_attr "type" "two")
6877 (set_attr "length" "8")])
6879 (define_insn "*negdi2_noppc64"
6880 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6881 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6882 "! TARGET_POWERPC64"
6883 "*
6884 {
6885 return (WORDS_BIG_ENDIAN)
6886 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6887 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6888 }"
6889 [(set_attr "type" "two")
6890 (set_attr "length" "8")])
6892 (define_expand "mulsidi3"
6893 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6894 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6895 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6896 "! TARGET_POWERPC64"
6897 "
6898 {
6899 if (! TARGET_POWER && ! TARGET_POWERPC)
6900 {
6901 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6902 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6903 emit_insn (gen_mull_call ());
6904 if (WORDS_BIG_ENDIAN)
6905 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6906 else
6907 {
6908 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6909 gen_rtx_REG (SImode, 3));
6910 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6911 gen_rtx_REG (SImode, 4));
6912 }
6913 DONE;
6914 }
6915 else if (TARGET_POWER)
6916 {
6917 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6918 DONE;
6919 }
6920 }")
6922 (define_insn "mulsidi3_mq"
6923 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6924 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6925 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6926 (clobber (match_scratch:SI 3 "=q"))]
6927 "TARGET_POWER"
6928 "mul %0,%1,%2\;mfmq %L0"
6929 [(set_attr "type" "imul")
6930 (set_attr "length" "8")])
6932 (define_insn "*mulsidi3_no_mq"
6933 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6934 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6935 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6936 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6937 "*
6938 {
6939 return (WORDS_BIG_ENDIAN)
6940 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6941 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6942 }"
6943 [(set_attr "type" "imul")
6944 (set_attr "length" "8")])
6946 (define_split
6947 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6948 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6949 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6950 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6951 [(set (match_dup 3)
6952 (truncate:SI
6953 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6954 (sign_extend:DI (match_dup 2)))
6955 (const_int 32))))
6956 (set (match_dup 4)
6957 (mult:SI (match_dup 1)
6958 (match_dup 2)))]
6959 "
6960 {
6961 int endian = (WORDS_BIG_ENDIAN == 0);
6962 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6963 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6964 }")
6966 (define_expand "umulsidi3"
6967 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6968 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6969 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6970 "TARGET_POWERPC && ! TARGET_POWERPC64"
6971 "
6972 {
6973 if (TARGET_POWER)
6974 {
6975 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6976 DONE;
6977 }
6978 }")
6980 (define_insn "umulsidi3_mq"
6981 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6982 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6983 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6984 (clobber (match_scratch:SI 3 "=q"))]
6985 "TARGET_POWERPC && TARGET_POWER"
6986 "*
6987 {
6988 return (WORDS_BIG_ENDIAN)
6989 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6990 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6991 }"
6992 [(set_attr "type" "imul")
6993 (set_attr "length" "8")])
6995 (define_insn "*umulsidi3_no_mq"
6996 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6997 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6998 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6999 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7000 "*
7001 {
7002 return (WORDS_BIG_ENDIAN)
7003 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7004 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7005 }"
7006 [(set_attr "type" "imul")
7007 (set_attr "length" "8")])
7009 (define_split
7010 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7011 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7012 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7013 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7014 [(set (match_dup 3)
7015 (truncate:SI
7016 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
7017 (zero_extend:DI (match_dup 2)))
7018 (const_int 32))))
7019 (set (match_dup 4)
7020 (mult:SI (match_dup 1)
7021 (match_dup 2)))]
7022 "
7023 {
7024 int endian = (WORDS_BIG_ENDIAN == 0);
7025 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7026 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7027 }")
7029 (define_expand "smulsi3_highpart"
7030 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7031 (truncate:SI
7032 (lshiftrt:DI (mult:DI (sign_extend:DI
7033 (match_operand:SI 1 "gpc_reg_operand" ""))
7034 (sign_extend:DI
7035 (match_operand:SI 2 "gpc_reg_operand" "")))
7036 (const_int 32))))]
7037 ""
7038 "
7039 {
7040 if (! TARGET_POWER && ! TARGET_POWERPC)
7041 {
7042 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7043 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7044 emit_insn (gen_mulh_call ());
7045 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
7046 DONE;
7047 }
7048 else if (TARGET_POWER)
7049 {
7050 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7051 DONE;
7052 }
7053 }")
7055 (define_insn "smulsi3_highpart_mq"
7056 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7057 (truncate:SI
7058 (lshiftrt:DI (mult:DI (sign_extend:DI
7059 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7060 (sign_extend:DI
7061 (match_operand:SI 2 "gpc_reg_operand" "r")))
7062 (const_int 32))))
7063 (clobber (match_scratch:SI 3 "=q"))]
7064 "TARGET_POWER"
7065 "mul %0,%1,%2"
7066 [(set_attr "type" "imul")])
7068 (define_insn "*smulsi3_highpart_no_mq"
7069 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7070 (truncate:SI
7071 (lshiftrt:DI (mult:DI (sign_extend:DI
7072 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7073 (sign_extend:DI
7074 (match_operand:SI 2 "gpc_reg_operand" "r")))
7075 (const_int 32))))]
7076 "TARGET_POWERPC && ! TARGET_POWER"
7077 "mulhw %0,%1,%2"
7078 [(set_attr "type" "imul")])
7080 (define_expand "umulsi3_highpart"
7081 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7082 (truncate:SI
7083 (lshiftrt:DI (mult:DI (zero_extend:DI
7084 (match_operand:SI 1 "gpc_reg_operand" ""))
7085 (zero_extend:DI
7086 (match_operand:SI 2 "gpc_reg_operand" "")))
7087 (const_int 32))))]
7088 "TARGET_POWERPC"
7089 "
7090 {
7091 if (TARGET_POWER)
7092 {
7093 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7094 DONE;
7095 }
7096 }")
7098 (define_insn "umulsi3_highpart_mq"
7099 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7100 (truncate:SI
7101 (lshiftrt:DI (mult:DI (zero_extend:DI
7102 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7103 (zero_extend:DI
7104 (match_operand:SI 2 "gpc_reg_operand" "r")))
7105 (const_int 32))))
7106 (clobber (match_scratch:SI 3 "=q"))]
7107 "TARGET_POWERPC && TARGET_POWER"
7108 "mulhwu %0,%1,%2"
7109 [(set_attr "type" "imul")])
7111 (define_insn "*umulsi3_highpart_no_mq"
7112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7113 (truncate:SI
7114 (lshiftrt:DI (mult:DI (zero_extend:DI
7115 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7116 (zero_extend:DI
7117 (match_operand:SI 2 "gpc_reg_operand" "r")))
7118 (const_int 32))))]
7119 "TARGET_POWERPC && ! TARGET_POWER"
7120 "mulhwu %0,%1,%2"
7121 [(set_attr "type" "imul")])
7123 ;; If operands 0 and 2 are in the same register, we have a problem. But
7124 ;; operands 0 and 1 (the usual case) can be in the same register. That's
7125 ;; why we have the strange constraints below.
7126 (define_insn "ashldi3_power"
7127 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7128 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7129 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7130 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7131 "TARGET_POWER"
7132 "@
7133 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
7134 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7135 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7136 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
7137 [(set_attr "length" "8")])
7139 (define_insn "lshrdi3_power"
7140 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7141 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7142 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7143 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7144 "TARGET_POWER"
7145 "@
7146 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
7147 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7148 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7149 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
7150 [(set_attr "length" "8")])
7152 ;; Shift by a variable amount is too complex to be worth open-coding. We
7153 ;; just handle shifts by constants.
7154 (define_insn "ashrdi3_power"
7155 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7156 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7157 (match_operand:SI 2 "const_int_operand" "M,i")))
7158 (clobber (match_scratch:SI 3 "=X,q"))]
7159 "TARGET_POWER"
7160 "@
7161 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7162 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
7163 [(set_attr "type" "shift")
7164 (set_attr "length" "8")])
7166 (define_insn "ashrdi3_no_power"
7167 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
7168 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7169 (match_operand:SI 2 "const_int_operand" "M,i")))]
7170 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
7171 "@
7172 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7173 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
7174 [(set_attr "type" "two,three")
7175 (set_attr "length" "8,12")])
7177 (define_insn "*ashrdisi3_noppc64"
7178 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7179 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7180 (const_int 32)) 4))]
7181 "TARGET_32BIT && !TARGET_POWERPC64"
7182 "*
7183 {
7184 if (REGNO (operands[0]) == REGNO (operands[1]))
7185 return \"\";
7186 else
7187 return \"mr %0,%1\";
7188 }"
7189 [(set_attr "length" "4")])
7191 \f
7192 ;; PowerPC64 DImode operations.
7194 (define_insn_and_split "absdi2"
7195 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7196 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
7197 (clobber (match_scratch:DI 2 "=&r,&r"))]
7198 "TARGET_POWERPC64"
7199 "#"
7200 "&& reload_completed"
7201 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7202 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7203 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
7204 "")
7206 (define_insn_and_split "*nabsdi2"
7207 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7208 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
7209 (clobber (match_scratch:DI 2 "=&r,&r"))]
7210 "TARGET_POWERPC64"
7211 "#"
7212 "&& reload_completed"
7213 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7214 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7215 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
7216 "")
7218 (define_insn "muldi3"
7219 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7220 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7221 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
7222 "TARGET_POWERPC64"
7223 "@
7224 mulld %0,%1,%2
7225 mulli %0,%1,%2"
7226 [(set (attr "type")
7227 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
7228 (const_string "imul3")
7229 (match_operand:SI 2 "short_cint_operand" "")
7230 (const_string "imul2")]
7231 (const_string "lmul")))])
7233 (define_insn "*muldi3_internal1"
7234 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7235 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7236 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7237 (const_int 0)))
7238 (clobber (match_scratch:DI 3 "=r,r"))]
7239 "TARGET_POWERPC64"
7240 "@
7241 mulld. %3,%1,%2
7242 #"
7243 [(set_attr "type" "lmul_compare")
7244 (set_attr "length" "4,8")])
7246 (define_split
7247 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7248 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7249 (match_operand:DI 2 "gpc_reg_operand" ""))
7250 (const_int 0)))
7251 (clobber (match_scratch:DI 3 ""))]
7252 "TARGET_POWERPC64 && reload_completed"
7253 [(set (match_dup 3)
7254 (mult:DI (match_dup 1) (match_dup 2)))
7255 (set (match_dup 0)
7256 (compare:CC (match_dup 3)
7257 (const_int 0)))]
7258 "")
7260 (define_insn "*muldi3_internal2"
7261 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7262 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7263 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7264 (const_int 0)))
7265 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7266 (mult:DI (match_dup 1) (match_dup 2)))]
7267 "TARGET_POWERPC64"
7268 "@
7269 mulld. %0,%1,%2
7270 #"
7271 [(set_attr "type" "lmul_compare")
7272 (set_attr "length" "4,8")])
7274 (define_split
7275 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7276 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7277 (match_operand:DI 2 "gpc_reg_operand" ""))
7278 (const_int 0)))
7279 (set (match_operand:DI 0 "gpc_reg_operand" "")
7280 (mult:DI (match_dup 1) (match_dup 2)))]
7281 "TARGET_POWERPC64 && reload_completed"
7282 [(set (match_dup 0)
7283 (mult:DI (match_dup 1) (match_dup 2)))
7284 (set (match_dup 3)
7285 (compare:CC (match_dup 0)
7286 (const_int 0)))]
7287 "")
7289 (define_insn "smuldi3_highpart"
7290 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7291 (truncate:DI
7292 (lshiftrt:TI (mult:TI (sign_extend:TI
7293 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7294 (sign_extend:TI
7295 (match_operand:DI 2 "gpc_reg_operand" "r")))
7296 (const_int 64))))]
7297 "TARGET_POWERPC64"
7298 "mulhd %0,%1,%2"
7299 [(set_attr "type" "lmul")])
7301 (define_insn "umuldi3_highpart"
7302 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7303 (truncate:DI
7304 (lshiftrt:TI (mult:TI (zero_extend:TI
7305 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7306 (zero_extend:TI
7307 (match_operand:DI 2 "gpc_reg_operand" "r")))
7308 (const_int 64))))]
7309 "TARGET_POWERPC64"
7310 "mulhdu %0,%1,%2"
7311 [(set_attr "type" "lmul")])
7313 (define_insn "rotldi3"
7314 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7315 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7316 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
7317 "TARGET_POWERPC64"
7318 "@
7319 rldcl %0,%1,%2,0
7320 rldicl %0,%1,%H2,0"
7321 [(set_attr "type" "var_shift_rotate,integer")])
7323 (define_insn "*rotldi3_internal2"
7324 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7325 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7326 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7327 (const_int 0)))
7328 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7329 "TARGET_64BIT"
7330 "@
7331 rldcl. %3,%1,%2,0
7332 rldicl. %3,%1,%H2,0
7333 #
7334 #"
7335 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7336 (set_attr "length" "4,4,8,8")])
7338 (define_split
7339 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7340 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7341 (match_operand:DI 2 "reg_or_cint_operand" ""))
7342 (const_int 0)))
7343 (clobber (match_scratch:DI 3 ""))]
7344 "TARGET_POWERPC64 && reload_completed"
7345 [(set (match_dup 3)
7346 (rotate:DI (match_dup 1) (match_dup 2)))
7347 (set (match_dup 0)
7348 (compare:CC (match_dup 3)
7349 (const_int 0)))]
7350 "")
7352 (define_insn "*rotldi3_internal3"
7353 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7354 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7355 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7356 (const_int 0)))
7357 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7358 (rotate:DI (match_dup 1) (match_dup 2)))]
7359 "TARGET_64BIT"
7360 "@
7361 rldcl. %0,%1,%2,0
7362 rldicl. %0,%1,%H2,0
7363 #
7364 #"
7365 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7366 (set_attr "length" "4,4,8,8")])
7368 (define_split
7369 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7370 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7371 (match_operand:DI 2 "reg_or_cint_operand" ""))
7372 (const_int 0)))
7373 (set (match_operand:DI 0 "gpc_reg_operand" "")
7374 (rotate:DI (match_dup 1) (match_dup 2)))]
7375 "TARGET_POWERPC64 && reload_completed"
7376 [(set (match_dup 0)
7377 (rotate:DI (match_dup 1) (match_dup 2)))
7378 (set (match_dup 3)
7379 (compare:CC (match_dup 0)
7380 (const_int 0)))]
7381 "")
7383 (define_insn "*rotldi3_internal4"
7384 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7385 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7386 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
7387 (match_operand:DI 3 "mask64_operand" "n,n")))]
7388 "TARGET_POWERPC64"
7389 "@
7390 rldc%B3 %0,%1,%2,%S3
7391 rldic%B3 %0,%1,%H2,%S3"
7392 [(set_attr "type" "var_shift_rotate,integer")])
7394 (define_insn "*rotldi3_internal5"
7395 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7396 (compare:CC (and:DI
7397 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7398 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7399 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7400 (const_int 0)))
7401 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
7402 "TARGET_64BIT"
7403 "@
7404 rldc%B3. %4,%1,%2,%S3
7405 rldic%B3. %4,%1,%H2,%S3
7406 #
7407 #"
7408 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7409 (set_attr "length" "4,4,8,8")])
7411 (define_split
7412 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7413 (compare:CC (and:DI
7414 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7415 (match_operand:DI 2 "reg_or_cint_operand" ""))
7416 (match_operand:DI 3 "mask64_operand" ""))
7417 (const_int 0)))
7418 (clobber (match_scratch:DI 4 ""))]
7419 "TARGET_POWERPC64 && reload_completed"
7420 [(set (match_dup 4)
7421 (and:DI (rotate:DI (match_dup 1)
7422 (match_dup 2))
7423 (match_dup 3)))
7424 (set (match_dup 0)
7425 (compare:CC (match_dup 4)
7426 (const_int 0)))]
7427 "")
7429 (define_insn "*rotldi3_internal6"
7430 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
7431 (compare:CC (and:DI
7432 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7433 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7434 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7435 (const_int 0)))
7436 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7437 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7438 "TARGET_64BIT"
7439 "@
7440 rldc%B3. %0,%1,%2,%S3
7441 rldic%B3. %0,%1,%H2,%S3
7442 #
7443 #"
7444 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7445 (set_attr "length" "4,4,8,8")])
7447 (define_split
7448 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7449 (compare:CC (and:DI
7450 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7451 (match_operand:DI 2 "reg_or_cint_operand" ""))
7452 (match_operand:DI 3 "mask64_operand" ""))
7453 (const_int 0)))
7454 (set (match_operand:DI 0 "gpc_reg_operand" "")
7455 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7456 "TARGET_POWERPC64 && reload_completed"
7457 [(set (match_dup 0)
7458 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7459 (set (match_dup 4)
7460 (compare:CC (match_dup 0)
7461 (const_int 0)))]
7462 "")
7464 (define_insn "*rotldi3_internal7"
7465 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7466 (zero_extend:DI
7467 (subreg:QI
7468 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7469 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7470 "TARGET_POWERPC64"
7471 "@
7472 rldcl %0,%1,%2,56
7473 rldicl %0,%1,%H2,56"
7474 [(set_attr "type" "var_shift_rotate,integer")])
7476 (define_insn "*rotldi3_internal8"
7477 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7478 (compare:CC (zero_extend:DI
7479 (subreg:QI
7480 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7481 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7482 (const_int 0)))
7483 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7484 "TARGET_64BIT"
7485 "@
7486 rldcl. %3,%1,%2,56
7487 rldicl. %3,%1,%H2,56
7488 #
7489 #"
7490 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7491 (set_attr "length" "4,4,8,8")])
7493 (define_split
7494 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7495 (compare:CC (zero_extend:DI
7496 (subreg:QI
7497 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7498 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7499 (const_int 0)))
7500 (clobber (match_scratch:DI 3 ""))]
7501 "TARGET_POWERPC64 && reload_completed"
7502 [(set (match_dup 3)
7503 (zero_extend:DI (subreg:QI
7504 (rotate:DI (match_dup 1)
7505 (match_dup 2)) 0)))
7506 (set (match_dup 0)
7507 (compare:CC (match_dup 3)
7508 (const_int 0)))]
7509 "")
7511 (define_insn "*rotldi3_internal9"
7512 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7513 (compare:CC (zero_extend:DI
7514 (subreg:QI
7515 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7516 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7517 (const_int 0)))
7518 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7519 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7520 "TARGET_64BIT"
7521 "@
7522 rldcl. %0,%1,%2,56
7523 rldicl. %0,%1,%H2,56
7524 #
7525 #"
7526 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7527 (set_attr "length" "4,4,8,8")])
7529 (define_split
7530 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7531 (compare:CC (zero_extend:DI
7532 (subreg:QI
7533 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7534 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7535 (const_int 0)))
7536 (set (match_operand:DI 0 "gpc_reg_operand" "")
7537 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7538 "TARGET_POWERPC64 && reload_completed"
7539 [(set (match_dup 0)
7540 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7541 (set (match_dup 3)
7542 (compare:CC (match_dup 0)
7543 (const_int 0)))]
7544 "")
7546 (define_insn "*rotldi3_internal10"
7547 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7548 (zero_extend:DI
7549 (subreg:HI
7550 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7551 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7552 "TARGET_POWERPC64"
7553 "@
7554 rldcl %0,%1,%2,48
7555 rldicl %0,%1,%H2,48"
7556 [(set_attr "type" "var_shift_rotate,integer")])
7558 (define_insn "*rotldi3_internal11"
7559 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7560 (compare:CC (zero_extend:DI
7561 (subreg:HI
7562 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7563 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7564 (const_int 0)))
7565 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7566 "TARGET_64BIT"
7567 "@
7568 rldcl. %3,%1,%2,48
7569 rldicl. %3,%1,%H2,48
7570 #
7571 #"
7572 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7573 (set_attr "length" "4,4,8,8")])
7575 (define_split
7576 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7577 (compare:CC (zero_extend:DI
7578 (subreg:HI
7579 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7580 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7581 (const_int 0)))
7582 (clobber (match_scratch:DI 3 ""))]
7583 "TARGET_POWERPC64 && reload_completed"
7584 [(set (match_dup 3)
7585 (zero_extend:DI (subreg:HI
7586 (rotate:DI (match_dup 1)
7587 (match_dup 2)) 0)))
7588 (set (match_dup 0)
7589 (compare:CC (match_dup 3)
7590 (const_int 0)))]
7591 "")
7593 (define_insn "*rotldi3_internal12"
7594 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7595 (compare:CC (zero_extend:DI
7596 (subreg:HI
7597 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7598 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7599 (const_int 0)))
7600 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7601 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7602 "TARGET_64BIT"
7603 "@
7604 rldcl. %0,%1,%2,48
7605 rldicl. %0,%1,%H2,48
7606 #
7607 #"
7608 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7609 (set_attr "length" "4,4,8,8")])
7611 (define_split
7612 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7613 (compare:CC (zero_extend:DI
7614 (subreg:HI
7615 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7616 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7617 (const_int 0)))
7618 (set (match_operand:DI 0 "gpc_reg_operand" "")
7619 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7620 "TARGET_POWERPC64 && reload_completed"
7621 [(set (match_dup 0)
7622 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7623 (set (match_dup 3)
7624 (compare:CC (match_dup 0)
7625 (const_int 0)))]
7626 "")
7628 (define_insn "*rotldi3_internal13"
7629 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7630 (zero_extend:DI
7631 (subreg:SI
7632 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7633 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7634 "TARGET_POWERPC64"
7635 "@
7636 rldcl %0,%1,%2,32
7637 rldicl %0,%1,%H2,32"
7638 [(set_attr "type" "var_shift_rotate,integer")])
7640 (define_insn "*rotldi3_internal14"
7641 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7642 (compare:CC (zero_extend:DI
7643 (subreg:SI
7644 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7645 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7646 (const_int 0)))
7647 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7648 "TARGET_64BIT"
7649 "@
7650 rldcl. %3,%1,%2,32
7651 rldicl. %3,%1,%H2,32
7652 #
7653 #"
7654 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7655 (set_attr "length" "4,4,8,8")])
7657 (define_split
7658 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7659 (compare:CC (zero_extend:DI
7660 (subreg:SI
7661 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7662 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7663 (const_int 0)))
7664 (clobber (match_scratch:DI 3 ""))]
7665 "TARGET_POWERPC64 && reload_completed"
7666 [(set (match_dup 3)
7667 (zero_extend:DI (subreg:SI
7668 (rotate:DI (match_dup 1)
7669 (match_dup 2)) 0)))
7670 (set (match_dup 0)
7671 (compare:CC (match_dup 3)
7672 (const_int 0)))]
7673 "")
7675 (define_insn "*rotldi3_internal15"
7676 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7677 (compare:CC (zero_extend:DI
7678 (subreg:SI
7679 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7680 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7681 (const_int 0)))
7682 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7683 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7684 "TARGET_64BIT"
7685 "@
7686 rldcl. %0,%1,%2,32
7687 rldicl. %0,%1,%H2,32
7688 #
7689 #"
7690 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7691 (set_attr "length" "4,4,8,8")])
7693 (define_split
7694 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7695 (compare:CC (zero_extend:DI
7696 (subreg:SI
7697 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7698 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7699 (const_int 0)))
7700 (set (match_operand:DI 0 "gpc_reg_operand" "")
7701 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7702 "TARGET_POWERPC64 && reload_completed"
7703 [(set (match_dup 0)
7704 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7705 (set (match_dup 3)
7706 (compare:CC (match_dup 0)
7707 (const_int 0)))]
7708 "")
7710 (define_expand "ashldi3"
7711 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7712 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7713 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7714 "TARGET_POWERPC64 || TARGET_POWER"
7715 "
7716 {
7717 if (TARGET_POWERPC64)
7718 ;
7719 else if (TARGET_POWER)
7720 {
7721 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7722 DONE;
7723 }
7724 else
7725 FAIL;
7726 }")
7728 (define_insn "*ashldi3_internal1"
7729 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7730 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7731 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7732 "TARGET_POWERPC64"
7733 "@
7734 sld %0,%1,%2
7735 sldi %0,%1,%H2"
7736 [(set_attr "type" "var_shift_rotate,shift")])
7738 (define_insn "*ashldi3_internal2"
7739 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7740 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7741 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7742 (const_int 0)))
7743 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7744 "TARGET_64BIT"
7745 "@
7746 sld. %3,%1,%2
7747 sldi. %3,%1,%H2
7748 #
7749 #"
7750 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7751 (set_attr "length" "4,4,8,8")])
7753 (define_split
7754 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7755 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7756 (match_operand:SI 2 "reg_or_cint_operand" ""))
7757 (const_int 0)))
7758 (clobber (match_scratch:DI 3 ""))]
7759 "TARGET_POWERPC64 && reload_completed"
7760 [(set (match_dup 3)
7761 (ashift:DI (match_dup 1) (match_dup 2)))
7762 (set (match_dup 0)
7763 (compare:CC (match_dup 3)
7764 (const_int 0)))]
7765 "")
7767 (define_insn "*ashldi3_internal3"
7768 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7769 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7770 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7771 (const_int 0)))
7772 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7773 (ashift:DI (match_dup 1) (match_dup 2)))]
7774 "TARGET_64BIT"
7775 "@
7776 sld. %0,%1,%2
7777 sldi. %0,%1,%H2
7778 #
7779 #"
7780 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7781 (set_attr "length" "4,4,8,8")])
7783 (define_split
7784 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7785 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7786 (match_operand:SI 2 "reg_or_cint_operand" ""))
7787 (const_int 0)))
7788 (set (match_operand:DI 0 "gpc_reg_operand" "")
7789 (ashift:DI (match_dup 1) (match_dup 2)))]
7790 "TARGET_POWERPC64 && reload_completed"
7791 [(set (match_dup 0)
7792 (ashift:DI (match_dup 1) (match_dup 2)))
7793 (set (match_dup 3)
7794 (compare:CC (match_dup 0)
7795 (const_int 0)))]
7796 "")
7798 (define_insn "*ashldi3_internal4"
7799 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7800 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7801 (match_operand:SI 2 "const_int_operand" "i"))
7802 (match_operand:DI 3 "const_int_operand" "n")))]
7803 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7804 "rldic %0,%1,%H2,%W3")
7806 (define_insn "ashldi3_internal5"
7807 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7808 (compare:CC
7809 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7810 (match_operand:SI 2 "const_int_operand" "i,i"))
7811 (match_operand:DI 3 "const_int_operand" "n,n"))
7812 (const_int 0)))
7813 (clobber (match_scratch:DI 4 "=r,r"))]
7814 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7815 "@
7816 rldic. %4,%1,%H2,%W3
7817 #"
7818 [(set_attr "type" "compare")
7819 (set_attr "length" "4,8")])
7821 (define_split
7822 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7823 (compare:CC
7824 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7825 (match_operand:SI 2 "const_int_operand" ""))
7826 (match_operand:DI 3 "const_int_operand" ""))
7827 (const_int 0)))
7828 (clobber (match_scratch:DI 4 ""))]
7829 "TARGET_POWERPC64 && reload_completed
7830 && includes_rldic_lshift_p (operands[2], operands[3])"
7831 [(set (match_dup 4)
7832 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7833 (match_dup 3)))
7834 (set (match_dup 0)
7835 (compare:CC (match_dup 4)
7836 (const_int 0)))]
7837 "")
7839 (define_insn "*ashldi3_internal6"
7840 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7841 (compare:CC
7842 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7843 (match_operand:SI 2 "const_int_operand" "i,i"))
7844 (match_operand:DI 3 "const_int_operand" "n,n"))
7845 (const_int 0)))
7846 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7847 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7848 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7849 "@
7850 rldic. %0,%1,%H2,%W3
7851 #"
7852 [(set_attr "type" "compare")
7853 (set_attr "length" "4,8")])
7855 (define_split
7856 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7857 (compare:CC
7858 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7859 (match_operand:SI 2 "const_int_operand" ""))
7860 (match_operand:DI 3 "const_int_operand" ""))
7861 (const_int 0)))
7862 (set (match_operand:DI 0 "gpc_reg_operand" "")
7863 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7864 "TARGET_POWERPC64 && reload_completed
7865 && includes_rldic_lshift_p (operands[2], operands[3])"
7866 [(set (match_dup 0)
7867 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7868 (match_dup 3)))
7869 (set (match_dup 4)
7870 (compare:CC (match_dup 0)
7871 (const_int 0)))]
7872 "")
7874 (define_insn "*ashldi3_internal7"
7875 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7876 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7877 (match_operand:SI 2 "const_int_operand" "i"))
7878 (match_operand:DI 3 "mask64_operand" "n")))]
7879 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7880 "rldicr %0,%1,%H2,%S3")
7882 (define_insn "ashldi3_internal8"
7883 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7884 (compare:CC
7885 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7886 (match_operand:SI 2 "const_int_operand" "i,i"))
7887 (match_operand:DI 3 "mask64_operand" "n,n"))
7888 (const_int 0)))
7889 (clobber (match_scratch:DI 4 "=r,r"))]
7890 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7891 "@
7892 rldicr. %4,%1,%H2,%S3
7893 #"
7894 [(set_attr "type" "compare")
7895 (set_attr "length" "4,8")])
7897 (define_split
7898 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7899 (compare:CC
7900 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7901 (match_operand:SI 2 "const_int_operand" ""))
7902 (match_operand:DI 3 "mask64_operand" ""))
7903 (const_int 0)))
7904 (clobber (match_scratch:DI 4 ""))]
7905 "TARGET_POWERPC64 && reload_completed
7906 && includes_rldicr_lshift_p (operands[2], operands[3])"
7907 [(set (match_dup 4)
7908 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7909 (match_dup 3)))
7910 (set (match_dup 0)
7911 (compare:CC (match_dup 4)
7912 (const_int 0)))]
7913 "")
7915 (define_insn "*ashldi3_internal9"
7916 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7917 (compare:CC
7918 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7919 (match_operand:SI 2 "const_int_operand" "i,i"))
7920 (match_operand:DI 3 "mask64_operand" "n,n"))
7921 (const_int 0)))
7922 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7923 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7924 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7925 "@
7926 rldicr. %0,%1,%H2,%S3
7927 #"
7928 [(set_attr "type" "compare")
7929 (set_attr "length" "4,8")])
7931 (define_split
7932 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7933 (compare:CC
7934 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7935 (match_operand:SI 2 "const_int_operand" ""))
7936 (match_operand:DI 3 "mask64_operand" ""))
7937 (const_int 0)))
7938 (set (match_operand:DI 0 "gpc_reg_operand" "")
7939 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7940 "TARGET_POWERPC64 && reload_completed
7941 && includes_rldicr_lshift_p (operands[2], operands[3])"
7942 [(set (match_dup 0)
7943 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7944 (match_dup 3)))
7945 (set (match_dup 4)
7946 (compare:CC (match_dup 0)
7947 (const_int 0)))]
7948 "")
7950 (define_expand "lshrdi3"
7951 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7952 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7953 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7954 "TARGET_POWERPC64 || TARGET_POWER"
7955 "
7956 {
7957 if (TARGET_POWERPC64)
7958 ;
7959 else if (TARGET_POWER)
7960 {
7961 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7962 DONE;
7963 }
7964 else
7965 FAIL;
7966 }")
7968 (define_insn "*lshrdi3_internal1"
7969 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7970 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7971 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7972 "TARGET_POWERPC64"
7973 "@
7974 srd %0,%1,%2
7975 srdi %0,%1,%H2"
7976 [(set_attr "type" "var_shift_rotate,shift")])
7978 (define_insn "*lshrdi3_internal2"
7979 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7980 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7981 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7982 (const_int 0)))
7983 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7984 "TARGET_64BIT "
7985 "@
7986 srd. %3,%1,%2
7987 srdi. %3,%1,%H2
7988 #
7989 #"
7990 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7991 (set_attr "length" "4,4,8,8")])
7993 (define_split
7994 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7995 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7996 (match_operand:SI 2 "reg_or_cint_operand" ""))
7997 (const_int 0)))
7998 (clobber (match_scratch:DI 3 ""))]
7999 "TARGET_POWERPC64 && reload_completed"
8000 [(set (match_dup 3)
8001 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8002 (set (match_dup 0)
8003 (compare:CC (match_dup 3)
8004 (const_int 0)))]
8005 "")
8007 (define_insn "*lshrdi3_internal3"
8008 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8009 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8010 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8011 (const_int 0)))
8012 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8013 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8014 "TARGET_64BIT"
8015 "@
8016 srd. %0,%1,%2
8017 srdi. %0,%1,%H2
8018 #
8019 #"
8020 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8021 (set_attr "length" "4,4,8,8")])
8023 (define_split
8024 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8025 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8026 (match_operand:SI 2 "reg_or_cint_operand" ""))
8027 (const_int 0)))
8028 (set (match_operand:DI 0 "gpc_reg_operand" "")
8029 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8030 "TARGET_POWERPC64 && reload_completed"
8031 [(set (match_dup 0)
8032 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8033 (set (match_dup 3)
8034 (compare:CC (match_dup 0)
8035 (const_int 0)))]
8036 "")
8038 (define_expand "ashrdi3"
8039 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8040 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8041 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8042 "WORDS_BIG_ENDIAN"
8043 "
8044 {
8045 if (TARGET_POWERPC64)
8046 ;
8047 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
8048 {
8049 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
8050 DONE;
8051 }
8052 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
8053 && WORDS_BIG_ENDIAN)
8054 {
8055 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
8056 DONE;
8057 }
8058 else
8059 FAIL;
8060 }")
8062 (define_insn "*ashrdi3_internal1"
8063 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8064 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8065 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8066 "TARGET_POWERPC64"
8067 "@
8068 srad %0,%1,%2
8069 sradi %0,%1,%H2"
8070 [(set_attr "type" "var_shift_rotate,shift")])
8072 (define_insn "*ashrdi3_internal2"
8073 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8074 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8075 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8076 (const_int 0)))
8077 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8078 "TARGET_64BIT"
8079 "@
8080 srad. %3,%1,%2
8081 sradi. %3,%1,%H2
8082 #
8083 #"
8084 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8085 (set_attr "length" "4,4,8,8")])
8087 (define_split
8088 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8089 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8090 (match_operand:SI 2 "reg_or_cint_operand" ""))
8091 (const_int 0)))
8092 (clobber (match_scratch:DI 3 ""))]
8093 "TARGET_POWERPC64 && reload_completed"
8094 [(set (match_dup 3)
8095 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8096 (set (match_dup 0)
8097 (compare:CC (match_dup 3)
8098 (const_int 0)))]
8099 "")
8101 (define_insn "*ashrdi3_internal3"
8102 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8103 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8104 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8105 (const_int 0)))
8106 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8107 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8108 "TARGET_64BIT"
8109 "@
8110 srad. %0,%1,%2
8111 sradi. %0,%1,%H2
8112 #
8113 #"
8114 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8115 (set_attr "length" "4,4,8,8")])
8117 (define_split
8118 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8119 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8120 (match_operand:SI 2 "reg_or_cint_operand" ""))
8121 (const_int 0)))
8122 (set (match_operand:DI 0 "gpc_reg_operand" "")
8123 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8124 "TARGET_POWERPC64 && reload_completed"
8125 [(set (match_dup 0)
8126 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8127 (set (match_dup 3)
8128 (compare:CC (match_dup 0)
8129 (const_int 0)))]
8130 "")
8132 (define_expand "anddi3"
8133 [(parallel
8134 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8135 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8136 (match_operand:DI 2 "and64_2_operand" "")))
8137 (clobber (match_scratch:CC 3 ""))])]
8138 "TARGET_POWERPC64"
8139 "")
8141 (define_insn "anddi3_mc"
8142 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
8143 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
8144 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
8145 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
8146 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
8147 "@
8148 and %0,%1,%2
8149 rldic%B2 %0,%1,0,%S2
8150 rlwinm %0,%1,0,%m2,%M2
8151 andi. %0,%1,%b2
8152 andis. %0,%1,%u2
8153 #"
8154 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
8155 (set_attr "length" "4,4,4,4,4,8")])
8157 (define_insn "anddi3_nomc"
8158 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8159 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
8160 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
8161 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
8162 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
8163 "@
8164 and %0,%1,%2
8165 rldic%B2 %0,%1,0,%S2
8166 rlwinm %0,%1,0,%m2,%M2
8167 #"
8168 [(set_attr "length" "4,4,4,8")])
8170 (define_split
8171 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8172 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8173 (match_operand:DI 2 "mask64_2_operand" "")))
8174 (clobber (match_scratch:CC 3 ""))]
8175 "TARGET_POWERPC64
8176 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8177 && !mask_operand (operands[2], DImode)
8178 && !mask64_operand (operands[2], DImode)"
8179 [(set (match_dup 0)
8180 (and:DI (rotate:DI (match_dup 1)
8181 (match_dup 4))
8182 (match_dup 5)))
8183 (set (match_dup 0)
8184 (and:DI (rotate:DI (match_dup 0)
8185 (match_dup 6))
8186 (match_dup 7)))]
8187 {
8188 build_mask64_2_operands (operands[2], &operands[4]);
8189 })
8191 (define_insn "*anddi3_internal2_mc"
8192 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8193 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8194 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8195 (const_int 0)))
8196 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
8197 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8198 "TARGET_64BIT && rs6000_gen_cell_microcode"
8199 "@
8200 and. %3,%1,%2
8201 rldic%B2. %3,%1,0,%S2
8202 rlwinm. %3,%1,0,%m2,%M2
8203 andi. %3,%1,%b2
8204 andis. %3,%1,%u2
8205 #
8206 #
8207 #
8208 #
8209 #
8210 #
8211 #"
8212 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8213 fast_compare,compare,compare,compare,compare,compare,\
8214 compare,compare")
8215 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8217 (define_split
8218 [(set (match_operand:CC 0 "cc_reg_operand" "")
8219 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8220 (match_operand:DI 2 "mask64_2_operand" ""))
8221 (const_int 0)))
8222 (clobber (match_scratch:DI 3 ""))
8223 (clobber (match_scratch:CC 4 ""))]
8224 "TARGET_64BIT && reload_completed
8225 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8226 && !mask_operand (operands[2], DImode)
8227 && !mask64_operand (operands[2], DImode)"
8228 [(set (match_dup 3)
8229 (and:DI (rotate:DI (match_dup 1)
8230 (match_dup 5))
8231 (match_dup 6)))
8232 (parallel [(set (match_dup 0)
8233 (compare:CC (and:DI (rotate:DI (match_dup 3)
8234 (match_dup 7))
8235 (match_dup 8))
8236 (const_int 0)))
8237 (clobber (match_dup 3))])]
8238 "
8239 {
8240 build_mask64_2_operands (operands[2], &operands[5]);
8241 }")
8243 (define_insn "*anddi3_internal3_mc"
8244 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8245 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8246 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8247 (const_int 0)))
8248 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8249 (and:DI (match_dup 1) (match_dup 2)))
8250 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8251 "TARGET_64BIT && rs6000_gen_cell_microcode"
8252 "@
8253 and. %0,%1,%2
8254 rldic%B2. %0,%1,0,%S2
8255 rlwinm. %0,%1,0,%m2,%M2
8256 andi. %0,%1,%b2
8257 andis. %0,%1,%u2
8258 #
8259 #
8260 #
8261 #
8262 #
8263 #
8264 #"
8265 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8266 fast_compare,compare,compare,compare,compare,compare,\
8267 compare,compare")
8268 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8270 (define_split
8271 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8272 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8273 (match_operand:DI 2 "and64_2_operand" ""))
8274 (const_int 0)))
8275 (set (match_operand:DI 0 "gpc_reg_operand" "")
8276 (and:DI (match_dup 1) (match_dup 2)))
8277 (clobber (match_scratch:CC 4 ""))]
8278 "TARGET_64BIT && reload_completed"
8279 [(parallel [(set (match_dup 0)
8280 (and:DI (match_dup 1) (match_dup 2)))
8281 (clobber (match_dup 4))])
8282 (set (match_dup 3)
8283 (compare:CC (match_dup 0)
8284 (const_int 0)))]
8285 "")
8287 (define_split
8288 [(set (match_operand:CC 3 "cc_reg_operand" "")
8289 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8290 (match_operand:DI 2 "mask64_2_operand" ""))
8291 (const_int 0)))
8292 (set (match_operand:DI 0 "gpc_reg_operand" "")
8293 (and:DI (match_dup 1) (match_dup 2)))
8294 (clobber (match_scratch:CC 4 ""))]
8295 "TARGET_64BIT && reload_completed
8296 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8297 && !mask_operand (operands[2], DImode)
8298 && !mask64_operand (operands[2], DImode)"
8299 [(set (match_dup 0)
8300 (and:DI (rotate:DI (match_dup 1)
8301 (match_dup 5))
8302 (match_dup 6)))
8303 (parallel [(set (match_dup 3)
8304 (compare:CC (and:DI (rotate:DI (match_dup 0)
8305 (match_dup 7))
8306 (match_dup 8))
8307 (const_int 0)))
8308 (set (match_dup 0)
8309 (and:DI (rotate:DI (match_dup 0)
8310 (match_dup 7))
8311 (match_dup 8)))])]
8312 "
8313 {
8314 build_mask64_2_operands (operands[2], &operands[5]);
8315 }")
8317 (define_expand "iordi3"
8318 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8319 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8320 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8321 "TARGET_POWERPC64"
8322 "
8323 {
8324 if (non_logical_cint_operand (operands[2], DImode))
8325 {
8326 HOST_WIDE_INT value;
8327 rtx tmp = ((!can_create_pseudo_p ()
8328 || rtx_equal_p (operands[0], operands[1]))
8329 ? operands[0] : gen_reg_rtx (DImode));
8331 if (GET_CODE (operands[2]) == CONST_INT)
8332 {
8333 value = INTVAL (operands[2]);
8334 emit_insn (gen_iordi3 (tmp, operands[1],
8335 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8336 }
8337 else
8338 {
8339 value = CONST_DOUBLE_LOW (operands[2]);
8340 emit_insn (gen_iordi3 (tmp, operands[1],
8341 immed_double_const (value
8342 & (~ (HOST_WIDE_INT) 0xffff),
8343 0, DImode)));
8344 }
8346 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8347 DONE;
8348 }
8349 }")
8351 (define_expand "xordi3"
8352 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8353 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8354 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8355 "TARGET_POWERPC64"
8356 "
8357 {
8358 if (non_logical_cint_operand (operands[2], DImode))
8359 {
8360 HOST_WIDE_INT value;
8361 rtx tmp = ((!can_create_pseudo_p ()
8362 || rtx_equal_p (operands[0], operands[1]))
8363 ? operands[0] : gen_reg_rtx (DImode));
8365 if (GET_CODE (operands[2]) == CONST_INT)
8366 {
8367 value = INTVAL (operands[2]);
8368 emit_insn (gen_xordi3 (tmp, operands[1],
8369 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8370 }
8371 else
8372 {
8373 value = CONST_DOUBLE_LOW (operands[2]);
8374 emit_insn (gen_xordi3 (tmp, operands[1],
8375 immed_double_const (value
8376 & (~ (HOST_WIDE_INT) 0xffff),
8377 0, DImode)));
8378 }
8380 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8381 DONE;
8382 }
8383 }")
8385 (define_insn "*booldi3_internal1"
8386 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8387 (match_operator:DI 3 "boolean_or_operator"
8388 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8389 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8390 "TARGET_POWERPC64"
8391 "@
8392 %q3 %0,%1,%2
8393 %q3i %0,%1,%b2
8394 %q3is %0,%1,%u2")
8396 (define_insn "*booldi3_internal2"
8397 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8398 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8399 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8400 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8401 (const_int 0)))
8402 (clobber (match_scratch:DI 3 "=r,r"))]
8403 "TARGET_64BIT"
8404 "@
8405 %q4. %3,%1,%2
8406 #"
8407 [(set_attr "type" "fast_compare,compare")
8408 (set_attr "length" "4,8")])
8410 (define_split
8411 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8412 (compare:CC (match_operator:DI 4 "boolean_operator"
8413 [(match_operand:DI 1 "gpc_reg_operand" "")
8414 (match_operand:DI 2 "gpc_reg_operand" "")])
8415 (const_int 0)))
8416 (clobber (match_scratch:DI 3 ""))]
8417 "TARGET_POWERPC64 && reload_completed"
8418 [(set (match_dup 3) (match_dup 4))
8419 (set (match_dup 0)
8420 (compare:CC (match_dup 3)
8421 (const_int 0)))]
8422 "")
8424 (define_insn "*booldi3_internal3"
8425 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8426 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8427 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8428 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8429 (const_int 0)))
8430 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8431 (match_dup 4))]
8432 "TARGET_64BIT"
8433 "@
8434 %q4. %0,%1,%2
8435 #"
8436 [(set_attr "type" "fast_compare,compare")
8437 (set_attr "length" "4,8")])
8439 (define_split
8440 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8441 (compare:CC (match_operator:DI 4 "boolean_operator"
8442 [(match_operand:DI 1 "gpc_reg_operand" "")
8443 (match_operand:DI 2 "gpc_reg_operand" "")])
8444 (const_int 0)))
8445 (set (match_operand:DI 0 "gpc_reg_operand" "")
8446 (match_dup 4))]
8447 "TARGET_POWERPC64 && reload_completed"
8448 [(set (match_dup 0) (match_dup 4))
8449 (set (match_dup 3)
8450 (compare:CC (match_dup 0)
8451 (const_int 0)))]
8452 "")
8454 ;; Split a logical operation that we can't do in one insn into two insns,
8455 ;; each of which does one 16-bit part. This is used by combine.
8457 (define_split
8458 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8459 (match_operator:DI 3 "boolean_or_operator"
8460 [(match_operand:DI 1 "gpc_reg_operand" "")
8461 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8462 "TARGET_POWERPC64"
8463 [(set (match_dup 0) (match_dup 4))
8464 (set (match_dup 0) (match_dup 5))]
8465 "
8466 {
8467 rtx i3,i4;
8469 if (GET_CODE (operands[2]) == CONST_DOUBLE)
8470 {
8471 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
8472 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
8473 0, DImode);
8474 i4 = GEN_INT (value & 0xffff);
8475 }
8476 else
8477 {
8478 i3 = GEN_INT (INTVAL (operands[2])
8479 & (~ (HOST_WIDE_INT) 0xffff));
8480 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8481 }
8482 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8483 operands[1], i3);
8484 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8485 operands[0], i4);
8486 }")
8488 (define_insn "*boolcdi3_internal1"
8489 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8490 (match_operator:DI 3 "boolean_operator"
8491 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8492 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8493 "TARGET_POWERPC64"
8494 "%q3 %0,%2,%1")
8496 (define_insn "*boolcdi3_internal2"
8497 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8498 (compare:CC (match_operator:DI 4 "boolean_operator"
8499 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8500 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8501 (const_int 0)))
8502 (clobber (match_scratch:DI 3 "=r,r"))]
8503 "TARGET_64BIT"
8504 "@
8505 %q4. %3,%2,%1
8506 #"
8507 [(set_attr "type" "fast_compare,compare")
8508 (set_attr "length" "4,8")])
8510 (define_split
8511 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8512 (compare:CC (match_operator:DI 4 "boolean_operator"
8513 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8514 (match_operand:DI 2 "gpc_reg_operand" "")])
8515 (const_int 0)))
8516 (clobber (match_scratch:DI 3 ""))]
8517 "TARGET_POWERPC64 && reload_completed"
8518 [(set (match_dup 3) (match_dup 4))
8519 (set (match_dup 0)
8520 (compare:CC (match_dup 3)
8521 (const_int 0)))]
8522 "")
8524 (define_insn "*boolcdi3_internal3"
8525 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8526 (compare:CC (match_operator:DI 4 "boolean_operator"
8527 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8528 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8529 (const_int 0)))
8530 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8531 (match_dup 4))]
8532 "TARGET_64BIT"
8533 "@
8534 %q4. %0,%2,%1
8535 #"
8536 [(set_attr "type" "fast_compare,compare")
8537 (set_attr "length" "4,8")])
8539 (define_split
8540 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8541 (compare:CC (match_operator:DI 4 "boolean_operator"
8542 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8543 (match_operand:DI 2 "gpc_reg_operand" "")])
8544 (const_int 0)))
8545 (set (match_operand:DI 0 "gpc_reg_operand" "")
8546 (match_dup 4))]
8547 "TARGET_POWERPC64 && reload_completed"
8548 [(set (match_dup 0) (match_dup 4))
8549 (set (match_dup 3)
8550 (compare:CC (match_dup 0)
8551 (const_int 0)))]
8552 "")
8554 (define_insn "*boolccdi3_internal1"
8555 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8556 (match_operator:DI 3 "boolean_operator"
8557 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8558 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8559 "TARGET_POWERPC64"
8560 "%q3 %0,%1,%2")
8562 (define_insn "*boolccdi3_internal2"
8563 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8564 (compare:CC (match_operator:DI 4 "boolean_operator"
8565 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8566 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8567 (const_int 0)))
8568 (clobber (match_scratch:DI 3 "=r,r"))]
8569 "TARGET_64BIT"
8570 "@
8571 %q4. %3,%1,%2
8572 #"
8573 [(set_attr "type" "fast_compare,compare")
8574 (set_attr "length" "4,8")])
8576 (define_split
8577 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8578 (compare:CC (match_operator:DI 4 "boolean_operator"
8579 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8580 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8581 (const_int 0)))
8582 (clobber (match_scratch:DI 3 ""))]
8583 "TARGET_POWERPC64 && reload_completed"
8584 [(set (match_dup 3) (match_dup 4))
8585 (set (match_dup 0)
8586 (compare:CC (match_dup 3)
8587 (const_int 0)))]
8588 "")
8590 (define_insn "*boolccdi3_internal3"
8591 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8592 (compare:CC (match_operator:DI 4 "boolean_operator"
8593 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8594 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8595 (const_int 0)))
8596 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8597 (match_dup 4))]
8598 "TARGET_64BIT"
8599 "@
8600 %q4. %0,%1,%2
8601 #"
8602 [(set_attr "type" "fast_compare,compare")
8603 (set_attr "length" "4,8")])
8605 (define_split
8606 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8607 (compare:CC (match_operator:DI 4 "boolean_operator"
8608 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8609 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8610 (const_int 0)))
8611 (set (match_operand:DI 0 "gpc_reg_operand" "")
8612 (match_dup 4))]
8613 "TARGET_POWERPC64 && reload_completed"
8614 [(set (match_dup 0) (match_dup 4))
8615 (set (match_dup 3)
8616 (compare:CC (match_dup 0)
8617 (const_int 0)))]
8618 "")
8620 (define_expand "smindi3"
8621 [(match_operand:DI 0 "gpc_reg_operand" "")
8622 (match_operand:DI 1 "gpc_reg_operand" "")
8623 (match_operand:DI 2 "gpc_reg_operand" "")]
8624 "TARGET_ISEL64"
8625 "
8626 {
8627 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
8628 DONE;
8629 }")
8631 (define_expand "smaxdi3"
8632 [(match_operand:DI 0 "gpc_reg_operand" "")
8633 (match_operand:DI 1 "gpc_reg_operand" "")
8634 (match_operand:DI 2 "gpc_reg_operand" "")]
8635 "TARGET_ISEL64"
8636 "
8637 {
8638 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
8639 DONE;
8640 }")
8642 (define_expand "umindi3"
8643 [(match_operand:DI 0 "gpc_reg_operand" "")
8644 (match_operand:DI 1 "gpc_reg_operand" "")
8645 (match_operand:DI 2 "gpc_reg_operand" "")]
8646 "TARGET_ISEL64"
8647 "
8648 {
8649 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
8650 DONE;
8651 }")
8653 (define_expand "umaxdi3"
8654 [(match_operand:DI 0 "gpc_reg_operand" "")
8655 (match_operand:DI 1 "gpc_reg_operand" "")
8656 (match_operand:DI 2 "gpc_reg_operand" "")]
8657 "TARGET_ISEL64"
8658 "
8659 {
8660 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
8661 DONE;
8662 }")
8664 \f
8665 ;; Now define ways of moving data around.
8667 ;; Set up a register with a value from the GOT table
8669 (define_expand "movsi_got"
8670 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8671 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8672 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8673 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8674 "
8675 {
8676 if (GET_CODE (operands[1]) == CONST)
8677 {
8678 rtx offset = const0_rtx;
8679 HOST_WIDE_INT value;
8681 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8682 value = INTVAL (offset);
8683 if (value != 0)
8684 {
8685 rtx tmp = (!can_create_pseudo_p ()
8686 ? operands[0]
8687 : gen_reg_rtx (Pmode));
8688 emit_insn (gen_movsi_got (tmp, operands[1]));
8689 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8690 DONE;
8691 }
8692 }
8694 operands[2] = rs6000_got_register (operands[1]);
8695 }")
8697 (define_insn "*movsi_got_internal"
8698 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8699 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8700 (match_operand:SI 2 "gpc_reg_operand" "b")]
8701 UNSPEC_MOVSI_GOT))]
8702 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8703 "{l|lwz} %0,%a1@got(%2)"
8704 [(set_attr "type" "load")])
8706 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8707 ;; didn't get allocated to a hard register.
8708 (define_split
8709 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8710 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8711 (match_operand:SI 2 "memory_operand" "")]
8712 UNSPEC_MOVSI_GOT))]
8713 "DEFAULT_ABI == ABI_V4
8714 && flag_pic == 1
8715 && (reload_in_progress || reload_completed)"
8716 [(set (match_dup 0) (match_dup 2))
8717 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8718 UNSPEC_MOVSI_GOT))]
8719 "")
8721 ;; For SI, we special-case integers that can't be loaded in one insn. We
8722 ;; do the load 16-bits at a time. We could do this by loading from memory,
8723 ;; and this is even supposed to be faster, but it is simpler not to get
8724 ;; integers in the TOC.
8725 (define_insn "movsi_low"
8726 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8727 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8728 (match_operand 2 "" ""))))]
8729 "TARGET_MACHO && ! TARGET_64BIT"
8730 "{l|lwz} %0,lo16(%2)(%1)"
8731 [(set_attr "type" "load")
8732 (set_attr "length" "4")])
8734 (define_insn "*movsi_internal1"
8735 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8736 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8737 "!TARGET_SINGLE_FPU &&
8738 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8739 "@
8740 mr %0,%1
8741 {cal|la} %0,%a1
8742 {l%U1%X1|lwz%U1%X1} %0,%1
8743 {st%U0%X0|stw%U0%X0} %1,%0
8744 {lil|li} %0,%1
8745 {liu|lis} %0,%v1
8746 #
8747 {cal|la} %0,%a1
8748 mf%1 %0
8749 mt%0 %1
8750 mt%0 %1
8751 mt%0 %1
8752 {cror 0,0,0|nop}"
8753 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8754 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8756 (define_insn "*movsi_internal1_single"
8757 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
8758 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
8759 "TARGET_SINGLE_FPU &&
8760 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8761 "@
8762 mr %0,%1
8763 {cal|la} %0,%a1
8764 {l%U1%X1|lwz%U1%X1} %0,%1
8765 {st%U0%X0|stw%U0%X0} %1,%0
8766 {lil|li} %0,%1
8767 {liu|lis} %0,%v1
8768 #
8769 {cal|la} %0,%a1
8770 mf%1 %0
8771 mt%0 %1
8772 mt%0 %1
8773 mt%0 %1
8774 {cror 0,0,0|nop}
8775 stfs%U0%X0 %1, %0
8776 lfs%U1%X1 %0, %1"
8777 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
8778 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
8780 ;; Split a load of a large constant into the appropriate two-insn
8781 ;; sequence.
8783 (define_split
8784 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8785 (match_operand:SI 1 "const_int_operand" ""))]
8786 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8787 && (INTVAL (operands[1]) & 0xffff) != 0"
8788 [(set (match_dup 0)
8789 (match_dup 2))
8790 (set (match_dup 0)
8791 (ior:SI (match_dup 0)
8792 (match_dup 3)))]
8793 "
8794 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8796 if (tem == operands[0])
8797 DONE;
8798 else
8799 FAIL;
8800 }")
8802 (define_insn "*mov<mode>_internal2"
8803 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8804 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8805 (const_int 0)))
8806 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8807 ""
8808 "@
8809 {cmpi|cmp<wd>i} %2,%0,0
8810 mr. %0,%1
8811 #"
8812 [(set_attr "type" "cmp,compare,cmp")
8813 (set_attr "length" "4,4,8")])
8815 (define_split
8816 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8817 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8818 (const_int 0)))
8819 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8820 "reload_completed"
8821 [(set (match_dup 0) (match_dup 1))
8822 (set (match_dup 2)
8823 (compare:CC (match_dup 0)
8824 (const_int 0)))]
8825 "")
8826 \f
8827 (define_insn "*movhi_internal"
8828 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8829 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8830 "gpc_reg_operand (operands[0], HImode)
8831 || gpc_reg_operand (operands[1], HImode)"
8832 "@
8833 mr %0,%1
8834 lhz%U1%X1 %0,%1
8835 sth%U0%X0 %1,%0
8836 {lil|li} %0,%w1
8837 mf%1 %0
8838 mt%0 %1
8839 mt%0 %1
8840 {cror 0,0,0|nop}"
8841 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8843 (define_expand "mov<mode>"
8844 [(set (match_operand:INT 0 "general_operand" "")
8845 (match_operand:INT 1 "any_operand" ""))]
8846 ""
8847 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8849 (define_insn "*movqi_internal"
8850 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8851 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8852 "gpc_reg_operand (operands[0], QImode)
8853 || gpc_reg_operand (operands[1], QImode)"
8854 "@
8855 mr %0,%1
8856 lbz%U1%X1 %0,%1
8857 stb%U0%X0 %1,%0
8858 {lil|li} %0,%1
8859 mf%1 %0
8860 mt%0 %1
8861 mt%0 %1
8862 {cror 0,0,0|nop}"
8863 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8864 \f
8865 ;; Here is how to move condition codes around. When we store CC data in
8866 ;; an integer register or memory, we store just the high-order 4 bits.
8867 ;; This lets us not shift in the most common case of CR0.
8868 (define_expand "movcc"
8869 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8870 (match_operand:CC 1 "nonimmediate_operand" ""))]
8871 ""
8872 "")
8874 (define_insn "*movcc_internal1"
8875 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8876 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8877 "register_operand (operands[0], CCmode)
8878 || register_operand (operands[1], CCmode)"
8879 "@
8880 mcrf %0,%1
8881 mtcrf 128,%1
8882 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8883 crxor %0,%0,%0
8884 mfcr %0%Q1
8885 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8886 mr %0,%1
8887 {lil|li} %0,%1
8888 mf%1 %0
8889 mt%0 %1
8890 mt%0 %1
8891 {l%U1%X1|lwz%U1%X1} %0,%1
8892 {st%U0%U1|stw%U0%U1} %1,%0"
8893 [(set (attr "type")
8894 (cond [(eq_attr "alternative" "0,3")
8895 (const_string "cr_logical")
8896 (eq_attr "alternative" "1,2")
8897 (const_string "mtcr")
8898 (eq_attr "alternative" "6,7,9")
8899 (const_string "integer")
8900 (eq_attr "alternative" "8")
8901 (const_string "mfjmpr")
8902 (eq_attr "alternative" "10")
8903 (const_string "mtjmpr")
8904 (eq_attr "alternative" "11")
8905 (const_string "load")
8906 (eq_attr "alternative" "12")
8907 (const_string "store")
8908 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8909 (const_string "mfcrf")
8910 ]
8911 (const_string "mfcr")))
8912 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8913 \f
8914 ;; For floating-point, we normally deal with the floating-point registers
8915 ;; unless -msoft-float is used. The sole exception is that parameter passing
8916 ;; can produce floating-point values in fixed-point registers. Unless the
8917 ;; value is a simple constant or already in memory, we deal with this by
8918 ;; allocating memory and copying the value explicitly via that memory location.
8919 (define_expand "movsf"
8920 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8921 (match_operand:SF 1 "any_operand" ""))]
8922 ""
8923 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8925 (define_split
8926 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8927 (match_operand:SF 1 "const_double_operand" ""))]
8928 "reload_completed
8929 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8930 || (GET_CODE (operands[0]) == SUBREG
8931 && GET_CODE (SUBREG_REG (operands[0])) == REG
8932 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8933 [(set (match_dup 2) (match_dup 3))]
8934 "
8935 {
8936 long l;
8937 REAL_VALUE_TYPE rv;
8939 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8940 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8942 if (! TARGET_POWERPC64)
8943 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8944 else
8945 operands[2] = gen_lowpart (SImode, operands[0]);
8947 operands[3] = gen_int_mode (l, SImode);
8948 }")
8950 (define_insn "*movsf_hardfloat"
8951 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8952 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8953 "(gpc_reg_operand (operands[0], SFmode)
8954 || gpc_reg_operand (operands[1], SFmode))
8955 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8956 "@
8957 mr %0,%1
8958 {l%U1%X1|lwz%U1%X1} %0,%1
8959 {st%U0%X0|stw%U0%X0} %1,%0
8960 fmr %0,%1
8961 lfs%U1%X1 %0,%1
8962 stfs%U0%X0 %1,%0
8963 mt%0 %1
8964 mt%0 %1
8965 mf%1 %0
8966 {cror 0,0,0|nop}
8967 #
8968 #"
8969 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8970 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8972 (define_insn "*movsf_softfloat"
8973 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8974 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8975 "(gpc_reg_operand (operands[0], SFmode)
8976 || gpc_reg_operand (operands[1], SFmode))
8977 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8978 "@
8979 mr %0,%1
8980 mt%0 %1
8981 mt%0 %1
8982 mf%1 %0
8983 {l%U1%X1|lwz%U1%X1} %0,%1
8984 {st%U0%X0|stw%U0%X0} %1,%0
8985 {lil|li} %0,%1
8986 {liu|lis} %0,%v1
8987 {cal|la} %0,%a1
8988 #
8989 #
8990 {cror 0,0,0|nop}"
8991 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8992 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8994 \f
8995 (define_expand "movdf"
8996 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8997 (match_operand:DF 1 "any_operand" ""))]
8998 ""
8999 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
9001 (define_split
9002 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9003 (match_operand:DF 1 "const_int_operand" ""))]
9004 "! TARGET_POWERPC64 && reload_completed
9005 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9006 || (GET_CODE (operands[0]) == SUBREG
9007 && GET_CODE (SUBREG_REG (operands[0])) == REG
9008 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9009 [(set (match_dup 2) (match_dup 4))
9010 (set (match_dup 3) (match_dup 1))]
9011 "
9012 {
9013 int endian = (WORDS_BIG_ENDIAN == 0);
9014 HOST_WIDE_INT value = INTVAL (operands[1]);
9016 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9017 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9018 #if HOST_BITS_PER_WIDE_INT == 32
9019 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9020 #else
9021 operands[4] = GEN_INT (value >> 32);
9022 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9023 #endif
9024 }")
9026 (define_split
9027 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9028 (match_operand:DF 1 "const_double_operand" ""))]
9029 "! TARGET_POWERPC64 && reload_completed
9030 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9031 || (GET_CODE (operands[0]) == SUBREG
9032 && GET_CODE (SUBREG_REG (operands[0])) == REG
9033 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9034 [(set (match_dup 2) (match_dup 4))
9035 (set (match_dup 3) (match_dup 5))]
9036 "
9037 {
9038 int endian = (WORDS_BIG_ENDIAN == 0);
9039 long l[2];
9040 REAL_VALUE_TYPE rv;
9042 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9043 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9045 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9046 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9047 operands[4] = gen_int_mode (l[endian], SImode);
9048 operands[5] = gen_int_mode (l[1 - endian], SImode);
9049 }")
9051 (define_split
9052 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9053 (match_operand:DF 1 "const_double_operand" ""))]
9054 "TARGET_POWERPC64 && reload_completed
9055 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9056 || (GET_CODE (operands[0]) == SUBREG
9057 && GET_CODE (SUBREG_REG (operands[0])) == REG
9058 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9059 [(set (match_dup 2) (match_dup 3))]
9060 "
9061 {
9062 int endian = (WORDS_BIG_ENDIAN == 0);
9063 long l[2];
9064 REAL_VALUE_TYPE rv;
9065 #if HOST_BITS_PER_WIDE_INT >= 64
9066 HOST_WIDE_INT val;
9067 #endif
9069 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9070 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9072 operands[2] = gen_lowpart (DImode, operands[0]);
9073 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9074 #if HOST_BITS_PER_WIDE_INT >= 64
9075 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9076 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9078 operands[3] = gen_int_mode (val, DImode);
9079 #else
9080 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
9081 #endif
9082 }")
9084 ;; Don't have reload use general registers to load a constant. First,
9085 ;; it might not work if the output operand is the equivalent of
9086 ;; a non-offsettable memref, but also it is less efficient than loading
9087 ;; the constant into an FP register, since it will probably be used there.
9088 ;; The "??" is a kludge until we can figure out a more reasonable way
9089 ;; of handling these non-offsettable values.
9090 (define_insn "*movdf_hardfloat32"
9091 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,!r,!r,!r")
9092 (match_operand:DF 1 "input_operand" "r,m,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
9093 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9094 && (gpc_reg_operand (operands[0], DFmode)
9095 || gpc_reg_operand (operands[1], DFmode))"
9096 "*
9097 {
9098 switch (which_alternative)
9099 {
9100 default:
9101 gcc_unreachable ();
9102 case 0:
9103 /* We normally copy the low-numbered register first. However, if
9104 the first register operand 0 is the same as the second register
9105 of operand 1, we must copy in the opposite order. */
9106 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9107 return \"mr %L0,%L1\;mr %0,%1\";
9108 else
9109 return \"mr %0,%1\;mr %L0,%L1\";
9110 case 1:
9111 if (rs6000_offsettable_memref_p (operands[1])
9112 || (GET_CODE (operands[1]) == MEM
9113 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
9114 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
9115 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
9116 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
9117 {
9118 /* If the low-address word is used in the address, we must load
9119 it last. Otherwise, load it first. Note that we cannot have
9120 auto-increment in that case since the address register is
9121 known to be dead. */
9122 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
9123 operands[1], 0))
9124 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
9125 else
9126 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
9127 }
9128 else
9129 {
9130 rtx addreg;
9132 addreg = find_addr_reg (XEXP (operands[1], 0));
9133 if (refers_to_regno_p (REGNO (operands[0]),
9134 REGNO (operands[0]) + 1,
9135 operands[1], 0))
9136 {
9137 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
9138 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
9139 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
9140 return \"{l%X1|lwz%X1} %0,%1\";
9141 }
9142 else
9143 {
9144 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
9145 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
9146 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
9147 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
9148 return \"\";
9149 }
9150 }
9151 case 2:
9152 if (rs6000_offsettable_memref_p (operands[0])
9153 || (GET_CODE (operands[0]) == MEM
9154 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
9155 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
9156 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
9157 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
9158 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
9159 else
9160 {
9161 rtx addreg;
9163 addreg = find_addr_reg (XEXP (operands[0], 0));
9164 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
9165 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
9166 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
9167 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
9168 return \"\";
9169 }
9170 case 3:
9171 case 4:
9172 return \"xxlor %x0,%x1,%x1\";
9173 case 5:
9174 case 6:
9175 return \"lxsd%U1x %x0,%y1\";
9176 case 7:
9177 case 8:
9178 return \"stxsd%U0x %x1,%y0\";
9179 case 9:
9180 return \"fmr %0,%1\";
9181 case 10:
9182 return \"lfd%U1%X1 %0,%1\";
9183 case 11:
9184 return \"stfd%U0%X0 %1,%0\";
9185 case 12:
9186 return \"xxlxor %x0,%x0,%x0\";
9187 case 13:
9188 case 14:
9189 case 15:
9190 return \"#\";
9191 }
9192 }"
9193 [(set_attr "type" "two,load,store,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,*,*,*")
9194 (set_attr "length" "8,16,16,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9196 (define_insn "*movdf_softfloat32"
9197 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
9198 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
9199 "! TARGET_POWERPC64
9200 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9201 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9202 && (gpc_reg_operand (operands[0], DFmode)
9203 || gpc_reg_operand (operands[1], DFmode))"
9204 "*
9205 {
9206 switch (which_alternative)
9207 {
9208 default:
9209 gcc_unreachable ();
9210 case 0:
9211 /* We normally copy the low-numbered register first. However, if
9212 the first register operand 0 is the same as the second register of
9213 operand 1, we must copy in the opposite order. */
9214 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9215 return \"mr %L0,%L1\;mr %0,%1\";
9216 else
9217 return \"mr %0,%1\;mr %L0,%L1\";
9218 case 1:
9219 /* If the low-address word is used in the address, we must load
9220 it last. Otherwise, load it first. Note that we cannot have
9221 auto-increment in that case since the address register is
9222 known to be dead. */
9223 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
9224 operands[1], 0))
9225 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
9226 else
9227 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
9228 case 2:
9229 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
9230 case 3:
9231 case 4:
9232 case 5:
9233 return \"#\";
9234 }
9235 }"
9236 [(set_attr "type" "two,load,store,*,*,*")
9237 (set_attr "length" "8,8,8,8,12,16")])
9239 ; ld/std require word-aligned displacements -> 'Y' constraint.
9240 ; List Y->r and r->Y before r->r for reload.
9241 (define_insn "*movdf_hardfloat64_mfpgpr"
9242 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r,r,d")
9243 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
9244 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9245 && TARGET_DOUBLE_FLOAT
9246 && (gpc_reg_operand (operands[0], DFmode)
9247 || gpc_reg_operand (operands[1], DFmode))"
9248 "@
9249 std%U0%X0 %1,%0
9250 ld%U1%X1 %0,%1
9251 mr %0,%1
9252 xxlor %x0,%x1,%x1
9253 xxlor %x0,%x1,%x1
9254 lxsd%U1x %x0,%y1
9255 lxsd%U1x %x0,%y1
9256 stxsd%U0x %x1,%y0
9257 stxsd%U0x %x1,%y0
9258 fmr %0,%1
9259 lfd%U1%X1 %0,%1
9260 stfd%U0%X0 %1,%0
9261 xxlxor %x0,%x0,%x0
9262 mt%0 %1
9263 mf%1 %0
9264 {cror 0,0,0|nop}
9265 #
9266 #
9267 #
9268 mftgpr %0,%1
9269 mffgpr %0,%1"
9270 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
9271 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9273 ; ld/std require word-aligned displacements -> 'Y' constraint.
9274 ; List Y->r and r->Y before r->r for reload.
9275 (define_insn "*movdf_hardfloat64"
9276 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r")
9277 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
9278 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9279 && TARGET_DOUBLE_FLOAT
9280 && (gpc_reg_operand (operands[0], DFmode)
9281 || gpc_reg_operand (operands[1], DFmode))"
9282 "@
9283 std%U0%X0 %1,%0
9284 ld%U1%X1 %0,%1
9285 mr %0,%1
9286 xxlor %x0,%x1,%x1
9287 xxlor %x0,%x1,%x1
9288 lxsd%U1x %x0,%y1
9289 lxsd%U1x %x0,%y1
9290 stxsd%U0x %x1,%y0
9291 stxsd%U0x %x1,%y0
9292 fmr %0,%1
9293 lfd%U1%X1 %0,%1
9294 stfd%U0%X0 %1,%0
9295 xxlxor %x0,%x0,%x0
9296 mt%0 %1
9297 mf%1 %0
9298 {cror 0,0,0|nop}
9299 #
9300 #
9301 #"
9302 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
9303 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9305 (define_insn "*movdf_softfloat64"
9306 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
9307 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
9308 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9309 && (gpc_reg_operand (operands[0], DFmode)
9310 || gpc_reg_operand (operands[1], DFmode))"
9311 "@
9312 ld%U1%X1 %0,%1
9313 std%U0%X0 %1,%0
9314 mr %0,%1
9315 mt%0 %1
9316 mf%1 %0
9317 #
9318 #
9319 #
9320 {cror 0,0,0|nop}"
9321 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
9322 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9323 \f
9324 (define_expand "movtf"
9325 [(set (match_operand:TF 0 "general_operand" "")
9326 (match_operand:TF 1 "any_operand" ""))]
9327 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
9328 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
9330 ; It's important to list the o->f and f->o moves before f->f because
9331 ; otherwise reload, given m->f, will try to pick f->f and reload it,
9332 ; which doesn't make progress. Likewise r->Y must be before r->r.
9333 (define_insn_and_split "*movtf_internal"
9334 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
9335 (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
9336 "!TARGET_IEEEQUAD
9337 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
9338 && (gpc_reg_operand (operands[0], TFmode)
9339 || gpc_reg_operand (operands[1], TFmode))"
9340 "#"
9341 "&& reload_completed"
9342 [(pc)]
9343 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9344 [(set_attr "length" "8,8,8,20,20,16")])
9346 (define_insn_and_split "*movtf_softfloat"
9347 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
9348 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
9349 "!TARGET_IEEEQUAD
9350 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
9351 && (gpc_reg_operand (operands[0], TFmode)
9352 || gpc_reg_operand (operands[1], TFmode))"
9353 "#"
9354 "&& reload_completed"
9355 [(pc)]
9356 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9357 [(set_attr "length" "20,20,16")])
9359 (define_expand "extenddftf2"
9360 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9361 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9362 "!TARGET_IEEEQUAD
9363 && TARGET_HARD_FLOAT
9364 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9365 && TARGET_LONG_DOUBLE_128"
9366 {
9367 if (TARGET_E500_DOUBLE)
9368 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9369 else
9370 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9371 DONE;
9372 })
9374 (define_expand "extenddftf2_fprs"
9375 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9376 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9377 (use (match_dup 2))])]
9378 "!TARGET_IEEEQUAD
9379 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9380 && TARGET_LONG_DOUBLE_128"
9381 {
9382 operands[2] = CONST0_RTX (DFmode);
9383 /* Generate GOT reference early for SVR4 PIC. */
9384 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9385 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9386 })
9388 (define_insn_and_split "*extenddftf2_internal"
9389 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
9390 (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
9391 (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
9392 "!TARGET_IEEEQUAD
9393 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9394 && TARGET_LONG_DOUBLE_128"
9395 "#"
9396 "&& reload_completed"
9397 [(pc)]
9398 {
9399 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9400 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9401 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9402 operands[1]);
9403 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9404 operands[2]);
9405 DONE;
9406 })
9408 (define_expand "extendsftf2"
9409 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9410 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9411 "!TARGET_IEEEQUAD
9412 && TARGET_HARD_FLOAT
9413 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9414 && TARGET_LONG_DOUBLE_128"
9415 {
9416 rtx tmp = gen_reg_rtx (DFmode);
9417 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9418 emit_insn (gen_extenddftf2 (operands[0], tmp));
9419 DONE;
9420 })
9422 (define_expand "trunctfdf2"
9423 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9424 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9425 "!TARGET_IEEEQUAD
9426 && TARGET_HARD_FLOAT
9427 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9428 && TARGET_LONG_DOUBLE_128"
9429 "")
9431 (define_insn_and_split "trunctfdf2_internal1"
9432 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9433 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9434 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9435 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9436 "@
9437 #
9438 fmr %0,%1"
9439 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9440 [(const_int 0)]
9441 {
9442 emit_note (NOTE_INSN_DELETED);
9443 DONE;
9444 }
9445 [(set_attr "type" "fp")])
9447 (define_insn "trunctfdf2_internal2"
9448 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9449 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9450 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9451 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9452 && TARGET_LONG_DOUBLE_128"
9453 "fadd %0,%1,%L1"
9454 [(set_attr "type" "fp")
9455 (set_attr "fp_type" "fp_addsub_d")])
9457 (define_expand "trunctfsf2"
9458 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9459 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9460 "!TARGET_IEEEQUAD
9461 && TARGET_HARD_FLOAT
9462 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9463 && TARGET_LONG_DOUBLE_128"
9464 {
9465 if (TARGET_E500_DOUBLE)
9466 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9467 else
9468 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9469 DONE;
9470 })
9472 (define_insn_and_split "trunctfsf2_fprs"
9473 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9474 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9475 (clobber (match_scratch:DF 2 "=d"))]
9476 "!TARGET_IEEEQUAD
9477 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9478 && TARGET_LONG_DOUBLE_128"
9479 "#"
9480 "&& reload_completed"
9481 [(set (match_dup 2)
9482 (float_truncate:DF (match_dup 1)))
9483 (set (match_dup 0)
9484 (float_truncate:SF (match_dup 2)))]
9485 "")
9487 (define_expand "floatsitf2"
9488 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9489 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9490 "!TARGET_IEEEQUAD
9491 && TARGET_HARD_FLOAT
9492 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9493 && TARGET_LONG_DOUBLE_128"
9494 {
9495 rtx tmp = gen_reg_rtx (DFmode);
9496 expand_float (tmp, operands[1], false);
9497 emit_insn (gen_extenddftf2 (operands[0], tmp));
9498 DONE;
9499 })
9501 ; fadd, but rounding towards zero.
9502 ; This is probably not the optimal code sequence.
9503 (define_insn "fix_trunc_helper"
9504 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9505 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9506 UNSPEC_FIX_TRUNC_TF))
9507 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9508 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9509 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9510 [(set_attr "type" "fp")
9511 (set_attr "length" "20")])
9513 (define_expand "fix_trunctfsi2"
9514 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9515 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9516 "!TARGET_IEEEQUAD
9517 && (TARGET_POWER2 || TARGET_POWERPC)
9518 && TARGET_HARD_FLOAT
9519 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9520 && TARGET_LONG_DOUBLE_128"
9521 {
9522 if (TARGET_E500_DOUBLE)
9523 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9524 else
9525 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9526 DONE;
9527 })
9529 (define_expand "fix_trunctfsi2_fprs"
9530 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9531 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9532 (clobber (match_dup 2))
9533 (clobber (match_dup 3))
9534 (clobber (match_dup 4))
9535 (clobber (match_dup 5))])]
9536 "!TARGET_IEEEQUAD
9537 && (TARGET_POWER2 || TARGET_POWERPC)
9538 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9539 {
9540 operands[2] = gen_reg_rtx (DFmode);
9541 operands[3] = gen_reg_rtx (DFmode);
9542 operands[4] = gen_reg_rtx (DImode);
9543 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
9544 })
9546 (define_insn_and_split "*fix_trunctfsi2_internal"
9547 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9548 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9549 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9550 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9551 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9552 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9553 "!TARGET_IEEEQUAD
9554 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9555 "#"
9556 ""
9557 [(pc)]
9558 {
9559 rtx lowword;
9560 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9562 gcc_assert (MEM_P (operands[5]));
9563 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9565 emit_insn (gen_fctiwz (operands[4], operands[2]));
9566 emit_move_insn (operands[5], operands[4]);
9567 emit_move_insn (operands[0], lowword);
9568 DONE;
9569 })
9571 (define_expand "negtf2"
9572 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9573 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9574 "!TARGET_IEEEQUAD
9575 && TARGET_HARD_FLOAT
9576 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9577 && TARGET_LONG_DOUBLE_128"
9578 "")
9580 (define_insn "negtf2_internal"
9581 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9582 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9583 "!TARGET_IEEEQUAD
9584 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9585 "*
9586 {
9587 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9588 return \"fneg %L0,%L1\;fneg %0,%1\";
9589 else
9590 return \"fneg %0,%1\;fneg %L0,%L1\";
9591 }"
9592 [(set_attr "type" "fp")
9593 (set_attr "length" "8")])
9595 (define_expand "abstf2"
9596 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9597 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9598 "!TARGET_IEEEQUAD
9599 && TARGET_HARD_FLOAT
9600 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9601 && TARGET_LONG_DOUBLE_128"
9602 "
9603 {
9604 rtx label = gen_label_rtx ();
9605 if (TARGET_E500_DOUBLE)
9606 {
9607 if (flag_finite_math_only && !flag_trapping_math)
9608 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9609 else
9610 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9611 }
9612 else
9613 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9614 emit_label (label);
9615 DONE;
9616 }")
9618 (define_expand "abstf2_internal"
9619 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9620 (match_operand:TF 1 "gpc_reg_operand" ""))
9621 (set (match_dup 3) (match_dup 5))
9622 (set (match_dup 5) (abs:DF (match_dup 5)))
9623 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9624 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9625 (label_ref (match_operand 2 "" ""))
9626 (pc)))
9627 (set (match_dup 6) (neg:DF (match_dup 6)))]
9628 "!TARGET_IEEEQUAD
9629 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9630 && TARGET_LONG_DOUBLE_128"
9631 "
9632 {
9633 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9634 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9635 operands[3] = gen_reg_rtx (DFmode);
9636 operands[4] = gen_reg_rtx (CCFPmode);
9637 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9638 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9639 }")
9640 \f
9641 ;; Next come the multi-word integer load and store and the load and store
9642 ;; multiple insns.
9644 ; List r->r after r->"o<>", otherwise reload will try to reload a
9645 ; non-offsettable address by using r->r which won't make progress.
9646 (define_insn "*movdi_internal32"
9647 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r")
9648 (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF"))]
9649 "! TARGET_POWERPC64
9650 && (gpc_reg_operand (operands[0], DImode)
9651 || gpc_reg_operand (operands[1], DImode))"
9652 "@
9653 #
9654 #
9655 #
9656 fmr %0,%1
9657 lfd%U1%X1 %0,%1
9658 stfd%U0%X0 %1,%0
9659 #"
9660 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
9662 (define_split
9663 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9664 (match_operand:DI 1 "const_int_operand" ""))]
9665 "! TARGET_POWERPC64 && reload_completed"
9666 [(set (match_dup 2) (match_dup 4))
9667 (set (match_dup 3) (match_dup 1))]
9668 "
9669 {
9670 HOST_WIDE_INT value = INTVAL (operands[1]);
9671 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9672 DImode);
9673 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9674 DImode);
9675 #if HOST_BITS_PER_WIDE_INT == 32
9676 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9677 #else
9678 operands[4] = GEN_INT (value >> 32);
9679 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9680 #endif
9681 }")
9683 (define_split
9684 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
9685 (match_operand:DI 1 "input_operand" ""))]
9686 "reload_completed && !TARGET_POWERPC64
9687 && gpr_or_gpr_p (operands[0], operands[1])"
9688 [(pc)]
9689 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9691 (define_insn "*movdi_mfpgpr"
9692 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
9693 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
9694 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9695 && (gpc_reg_operand (operands[0], DImode)
9696 || gpc_reg_operand (operands[1], DImode))"
9697 "@
9698 mr %0,%1
9699 ld%U1%X1 %0,%1
9700 std%U0%X0 %1,%0
9701 li %0,%1
9702 lis %0,%v1
9703 #
9704 {cal|la} %0,%a1
9705 fmr %0,%1
9706 lfd%U1%X1 %0,%1
9707 stfd%U0%X0 %1,%0
9708 mf%1 %0
9709 mt%0 %1
9710 {cror 0,0,0|nop}
9711 mftgpr %0,%1
9712 mffgpr %0,%1"
9713 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
9714 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
9716 (define_insn "*movdi_internal64"
9717 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h")
9718 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0"))]
9719 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9720 && (gpc_reg_operand (operands[0], DImode)
9721 || gpc_reg_operand (operands[1], DImode))"
9722 "@
9723 mr %0,%1
9724 ld%U1%X1 %0,%1
9725 std%U0%X0 %1,%0
9726 li %0,%1
9727 lis %0,%v1
9728 #
9729 {cal|la} %0,%a1
9730 fmr %0,%1
9731 lfd%U1%X1 %0,%1
9732 stfd%U0%X0 %1,%0
9733 mf%1 %0
9734 mt%0 %1
9735 {cror 0,0,0|nop}"
9736 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9737 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9739 ;; immediate value valid for a single instruction hiding in a const_double
9740 (define_insn ""
9741 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9742 (match_operand:DI 1 "const_double_operand" "F"))]
9743 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9744 && GET_CODE (operands[1]) == CONST_DOUBLE
9745 && num_insns_constant (operands[1], DImode) == 1"
9746 "*
9747 {
9748 return ((unsigned HOST_WIDE_INT)
9749 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9750 ? \"li %0,%1\" : \"lis %0,%v1\";
9751 }")
9753 ;; Generate all one-bits and clear left or right.
9754 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9755 (define_split
9756 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9757 (match_operand:DI 1 "mask64_operand" ""))]
9758 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9759 [(set (match_dup 0) (const_int -1))
9760 (set (match_dup 0)
9761 (and:DI (rotate:DI (match_dup 0)
9762 (const_int 0))
9763 (match_dup 1)))]
9764 "")
9766 ;; Split a load of a large constant into the appropriate five-instruction
9767 ;; sequence. Handle anything in a constant number of insns.
9768 ;; When non-easy constants can go in the TOC, this should use
9769 ;; easy_fp_constant predicate.
9770 (define_split
9771 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9772 (match_operand:DI 1 "const_int_operand" ""))]
9773 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9774 [(set (match_dup 0) (match_dup 2))
9775 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9776 "
9777 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9779 if (tem == operands[0])
9780 DONE;
9781 else
9782 FAIL;
9783 }")
9785 (define_split
9786 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9787 (match_operand:DI 1 "const_double_operand" ""))]
9788 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9789 [(set (match_dup 0) (match_dup 2))
9790 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9791 "
9792 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9794 if (tem == operands[0])
9795 DONE;
9796 else
9797 FAIL;
9798 }")
9799 \f
9800 ;; TImode is similar, except that we usually want to compute the address into
9801 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9802 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9804 ;; We say that MQ is clobbered in the last alternative because the first
9805 ;; alternative would never get used otherwise since it would need a reload
9806 ;; while the 2nd alternative would not. We put memory cases first so they
9807 ;; are preferred. Otherwise, we'd try to reload the output instead of
9808 ;; giving the SCRATCH mq.
9810 (define_insn "*movti_power"
9811 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9812 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9813 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9814 "TARGET_POWER && ! TARGET_POWERPC64
9815 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9816 "*
9817 {
9818 switch (which_alternative)
9819 {
9820 default:
9821 gcc_unreachable ();
9823 case 0:
9824 if (TARGET_STRING)
9825 return \"{stsi|stswi} %1,%P0,16\";
9826 case 1:
9827 case 2:
9828 return \"#\";
9829 case 3:
9830 /* If the address is not used in the output, we can use lsi. Otherwise,
9831 fall through to generating four loads. */
9832 if (TARGET_STRING
9833 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9834 return \"{lsi|lswi} %0,%P1,16\";
9835 /* ... fall through ... */
9836 case 4:
9837 case 5:
9838 return \"#\";
9839 }
9840 }"
9841 [(set_attr "type" "store,store,*,load,load,*")])
9843 (define_insn "*movti_string"
9844 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9845 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9846 "! TARGET_POWER && ! TARGET_POWERPC64
9847 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9848 "*
9849 {
9850 switch (which_alternative)
9851 {
9852 default:
9853 gcc_unreachable ();
9854 case 0:
9855 if (TARGET_STRING)
9856 return \"{stsi|stswi} %1,%P0,16\";
9857 case 1:
9858 case 2:
9859 return \"#\";
9860 case 3:
9861 /* If the address is not used in the output, we can use lsi. Otherwise,
9862 fall through to generating four loads. */
9863 if (TARGET_STRING
9864 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9865 return \"{lsi|lswi} %0,%P1,16\";
9866 /* ... fall through ... */
9867 case 4:
9868 case 5:
9869 return \"#\";
9870 }
9871 }"
9872 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
9873 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
9874 (const_string "always")
9875 (const_string "conditional")))])
9877 (define_insn "*movti_ppc64"
9878 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9879 (match_operand:TI 1 "input_operand" "r,r,m"))]
9880 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9881 || gpc_reg_operand (operands[1], TImode)))
9882 && VECTOR_MEM_NONE_P (TImode)"
9883 "#"
9884 [(set_attr "type" "*,store,load")])
9886 (define_split
9887 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9888 (match_operand:TI 1 "const_double_operand" ""))]
9889 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
9890 [(set (match_dup 2) (match_dup 4))
9891 (set (match_dup 3) (match_dup 5))]
9892 "
9893 {
9894 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9895 TImode);
9896 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9897 TImode);
9898 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9899 {
9900 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9901 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9902 }
9903 else if (GET_CODE (operands[1]) == CONST_INT)
9904 {
9905 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9906 operands[5] = operands[1];
9907 }
9908 else
9909 FAIL;
9910 }")
9912 (define_split
9913 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9914 (match_operand:TI 1 "input_operand" ""))]
9915 "reload_completed && VECTOR_MEM_NONE_P (TImode)
9916 && gpr_or_gpr_p (operands[0], operands[1])"
9917 [(pc)]
9918 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9919 \f
9920 (define_expand "load_multiple"
9921 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9922 (match_operand:SI 1 "" ""))
9923 (use (match_operand:SI 2 "" ""))])]
9924 "TARGET_STRING && !TARGET_POWERPC64"
9925 "
9926 {
9927 int regno;
9928 int count;
9929 rtx op1;
9930 int i;
9932 /* Support only loading a constant number of fixed-point registers from
9933 memory and only bother with this if more than two; the machine
9934 doesn't support more than eight. */
9935 if (GET_CODE (operands[2]) != CONST_INT
9936 || INTVAL (operands[2]) <= 2
9937 || INTVAL (operands[2]) > 8
9938 || GET_CODE (operands[1]) != MEM
9939 || GET_CODE (operands[0]) != REG
9940 || REGNO (operands[0]) >= 32)
9941 FAIL;
9943 count = INTVAL (operands[2]);
9944 regno = REGNO (operands[0]);
9946 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9947 op1 = replace_equiv_address (operands[1],
9948 force_reg (SImode, XEXP (operands[1], 0)));
9950 for (i = 0; i < count; i++)
9951 XVECEXP (operands[3], 0, i)
9952 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9953 adjust_address_nv (op1, SImode, i * 4));
9954 }")
9956 (define_insn "*ldmsi8"
9957 [(match_parallel 0 "load_multiple_operation"
9958 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9959 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9960 (set (match_operand:SI 3 "gpc_reg_operand" "")
9961 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9962 (set (match_operand:SI 4 "gpc_reg_operand" "")
9963 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9964 (set (match_operand:SI 5 "gpc_reg_operand" "")
9965 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9966 (set (match_operand:SI 6 "gpc_reg_operand" "")
9967 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9968 (set (match_operand:SI 7 "gpc_reg_operand" "")
9969 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9970 (set (match_operand:SI 8 "gpc_reg_operand" "")
9971 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9972 (set (match_operand:SI 9 "gpc_reg_operand" "")
9973 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9974 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9975 "*
9976 { return rs6000_output_load_multiple (operands); }"
9977 [(set_attr "type" "load_ux")
9978 (set_attr "length" "32")])
9980 (define_insn "*ldmsi7"
9981 [(match_parallel 0 "load_multiple_operation"
9982 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9983 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9984 (set (match_operand:SI 3 "gpc_reg_operand" "")
9985 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9986 (set (match_operand:SI 4 "gpc_reg_operand" "")
9987 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9988 (set (match_operand:SI 5 "gpc_reg_operand" "")
9989 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9990 (set (match_operand:SI 6 "gpc_reg_operand" "")
9991 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9992 (set (match_operand:SI 7 "gpc_reg_operand" "")
9993 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9994 (set (match_operand:SI 8 "gpc_reg_operand" "")
9995 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9996 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9997 "*
9998 { return rs6000_output_load_multiple (operands); }"
9999 [(set_attr "type" "load_ux")
10000 (set_attr "length" "32")])
10002 (define_insn "*ldmsi6"
10003 [(match_parallel 0 "load_multiple_operation"
10004 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10005 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10006 (set (match_operand:SI 3 "gpc_reg_operand" "")
10007 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10008 (set (match_operand:SI 4 "gpc_reg_operand" "")
10009 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10010 (set (match_operand:SI 5 "gpc_reg_operand" "")
10011 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10012 (set (match_operand:SI 6 "gpc_reg_operand" "")
10013 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10014 (set (match_operand:SI 7 "gpc_reg_operand" "")
10015 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
10016 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10017 "*
10018 { return rs6000_output_load_multiple (operands); }"
10019 [(set_attr "type" "load_ux")
10020 (set_attr "length" "32")])
10022 (define_insn "*ldmsi5"
10023 [(match_parallel 0 "load_multiple_operation"
10024 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10025 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10026 (set (match_operand:SI 3 "gpc_reg_operand" "")
10027 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10028 (set (match_operand:SI 4 "gpc_reg_operand" "")
10029 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10030 (set (match_operand:SI 5 "gpc_reg_operand" "")
10031 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10032 (set (match_operand:SI 6 "gpc_reg_operand" "")
10033 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10034 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10035 "*
10036 { return rs6000_output_load_multiple (operands); }"
10037 [(set_attr "type" "load_ux")
10038 (set_attr "length" "32")])
10040 (define_insn "*ldmsi4"
10041 [(match_parallel 0 "load_multiple_operation"
10042 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10043 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10044 (set (match_operand:SI 3 "gpc_reg_operand" "")
10045 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10046 (set (match_operand:SI 4 "gpc_reg_operand" "")
10047 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10048 (set (match_operand:SI 5 "gpc_reg_operand" "")
10049 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10050 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10051 "*
10052 { return rs6000_output_load_multiple (operands); }"
10053 [(set_attr "type" "load_ux")
10054 (set_attr "length" "32")])
10056 (define_insn "*ldmsi3"
10057 [(match_parallel 0 "load_multiple_operation"
10058 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10059 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10060 (set (match_operand:SI 3 "gpc_reg_operand" "")
10061 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10062 (set (match_operand:SI 4 "gpc_reg_operand" "")
10063 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10064 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10065 "*
10066 { return rs6000_output_load_multiple (operands); }"
10067 [(set_attr "type" "load_ux")
10068 (set_attr "length" "32")])
10070 (define_expand "store_multiple"
10071 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10072 (match_operand:SI 1 "" ""))
10073 (clobber (scratch:SI))
10074 (use (match_operand:SI 2 "" ""))])]
10075 "TARGET_STRING && !TARGET_POWERPC64"
10076 "
10077 {
10078 int regno;
10079 int count;
10080 rtx to;
10081 rtx op0;
10082 int i;
10084 /* Support only storing a constant number of fixed-point registers to
10085 memory and only bother with this if more than two; the machine
10086 doesn't support more than eight. */
10087 if (GET_CODE (operands[2]) != CONST_INT
10088 || INTVAL (operands[2]) <= 2
10089 || INTVAL (operands[2]) > 8
10090 || GET_CODE (operands[0]) != MEM
10091 || GET_CODE (operands[1]) != REG
10092 || REGNO (operands[1]) >= 32)
10093 FAIL;
10095 count = INTVAL (operands[2]);
10096 regno = REGNO (operands[1]);
10098 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10099 to = force_reg (SImode, XEXP (operands[0], 0));
10100 op0 = replace_equiv_address (operands[0], to);
10102 XVECEXP (operands[3], 0, 0)
10103 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10104 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10105 gen_rtx_SCRATCH (SImode));
10107 for (i = 1; i < count; i++)
10108 XVECEXP (operands[3], 0, i + 1)
10109 = gen_rtx_SET (VOIDmode,
10110 adjust_address_nv (op0, SImode, i * 4),
10111 gen_rtx_REG (SImode, regno + i));
10112 }")
10114 (define_insn "*stmsi8"
10115 [(match_parallel 0 "store_multiple_operation"
10116 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10117 (match_operand:SI 2 "gpc_reg_operand" "r"))
10118 (clobber (match_scratch:SI 3 "=X"))
10119 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10120 (match_operand:SI 4 "gpc_reg_operand" "r"))
10121 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10122 (match_operand:SI 5 "gpc_reg_operand" "r"))
10123 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10124 (match_operand:SI 6 "gpc_reg_operand" "r"))
10125 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10126 (match_operand:SI 7 "gpc_reg_operand" "r"))
10127 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10128 (match_operand:SI 8 "gpc_reg_operand" "r"))
10129 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10130 (match_operand:SI 9 "gpc_reg_operand" "r"))
10131 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10132 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10133 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10134 "{stsi|stswi} %2,%1,%O0"
10135 [(set_attr "type" "store_ux")
10136 (set_attr "cell_micro" "always")])
10138 (define_insn "*stmsi7"
10139 [(match_parallel 0 "store_multiple_operation"
10140 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10141 (match_operand:SI 2 "gpc_reg_operand" "r"))
10142 (clobber (match_scratch:SI 3 "=X"))
10143 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10144 (match_operand:SI 4 "gpc_reg_operand" "r"))
10145 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10146 (match_operand:SI 5 "gpc_reg_operand" "r"))
10147 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10148 (match_operand:SI 6 "gpc_reg_operand" "r"))
10149 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10150 (match_operand:SI 7 "gpc_reg_operand" "r"))
10151 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10152 (match_operand:SI 8 "gpc_reg_operand" "r"))
10153 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10154 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10155 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10156 "{stsi|stswi} %2,%1,%O0"
10157 [(set_attr "type" "store_ux")
10158 (set_attr "cell_micro" "always")])
10160 (define_insn "*stmsi6"
10161 [(match_parallel 0 "store_multiple_operation"
10162 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10163 (match_operand:SI 2 "gpc_reg_operand" "r"))
10164 (clobber (match_scratch:SI 3 "=X"))
10165 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10166 (match_operand:SI 4 "gpc_reg_operand" "r"))
10167 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10168 (match_operand:SI 5 "gpc_reg_operand" "r"))
10169 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10170 (match_operand:SI 6 "gpc_reg_operand" "r"))
10171 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10172 (match_operand:SI 7 "gpc_reg_operand" "r"))
10173 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10174 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10175 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10176 "{stsi|stswi} %2,%1,%O0"
10177 [(set_attr "type" "store_ux")
10178 (set_attr "cell_micro" "always")])
10180 (define_insn "*stmsi5"
10181 [(match_parallel 0 "store_multiple_operation"
10182 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10183 (match_operand:SI 2 "gpc_reg_operand" "r"))
10184 (clobber (match_scratch:SI 3 "=X"))
10185 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10186 (match_operand:SI 4 "gpc_reg_operand" "r"))
10187 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10188 (match_operand:SI 5 "gpc_reg_operand" "r"))
10189 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10190 (match_operand:SI 6 "gpc_reg_operand" "r"))
10191 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10192 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10193 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10194 "{stsi|stswi} %2,%1,%O0"
10195 [(set_attr "type" "store_ux")
10196 (set_attr "cell_micro" "always")])
10198 (define_insn "*stmsi4"
10199 [(match_parallel 0 "store_multiple_operation"
10200 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10201 (match_operand:SI 2 "gpc_reg_operand" "r"))
10202 (clobber (match_scratch:SI 3 "=X"))
10203 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10204 (match_operand:SI 4 "gpc_reg_operand" "r"))
10205 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10206 (match_operand:SI 5 "gpc_reg_operand" "r"))
10207 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10208 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10209 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10210 "{stsi|stswi} %2,%1,%O0"
10211 [(set_attr "type" "store_ux")
10212 (set_attr "cell_micro" "always")])
10214 (define_insn "*stmsi3"
10215 [(match_parallel 0 "store_multiple_operation"
10216 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10217 (match_operand:SI 2 "gpc_reg_operand" "r"))
10218 (clobber (match_scratch:SI 3 "=X"))
10219 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10220 (match_operand:SI 4 "gpc_reg_operand" "r"))
10221 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10222 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10223 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10224 "{stsi|stswi} %2,%1,%O0"
10225 [(set_attr "type" "store_ux")
10226 (set_attr "cell_micro" "always")])
10228 (define_insn "*stmsi8_power"
10229 [(match_parallel 0 "store_multiple_operation"
10230 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10231 (match_operand:SI 2 "gpc_reg_operand" "r"))
10232 (clobber (match_scratch:SI 3 "=q"))
10233 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10234 (match_operand:SI 4 "gpc_reg_operand" "r"))
10235 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10236 (match_operand:SI 5 "gpc_reg_operand" "r"))
10237 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10238 (match_operand:SI 6 "gpc_reg_operand" "r"))
10239 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10240 (match_operand:SI 7 "gpc_reg_operand" "r"))
10241 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10242 (match_operand:SI 8 "gpc_reg_operand" "r"))
10243 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10244 (match_operand:SI 9 "gpc_reg_operand" "r"))
10245 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10246 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10247 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10248 "{stsi|stswi} %2,%1,%O0"
10249 [(set_attr "type" "store_ux")
10250 (set_attr "cell_micro" "always")])
10252 (define_insn "*stmsi7_power"
10253 [(match_parallel 0 "store_multiple_operation"
10254 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10255 (match_operand:SI 2 "gpc_reg_operand" "r"))
10256 (clobber (match_scratch:SI 3 "=q"))
10257 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10258 (match_operand:SI 4 "gpc_reg_operand" "r"))
10259 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10260 (match_operand:SI 5 "gpc_reg_operand" "r"))
10261 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10262 (match_operand:SI 6 "gpc_reg_operand" "r"))
10263 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10264 (match_operand:SI 7 "gpc_reg_operand" "r"))
10265 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10266 (match_operand:SI 8 "gpc_reg_operand" "r"))
10267 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10268 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10269 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10270 "{stsi|stswi} %2,%1,%O0"
10271 [(set_attr "type" "store_ux")
10272 (set_attr "cell_micro" "always")])
10274 (define_insn "*stmsi6_power"
10275 [(match_parallel 0 "store_multiple_operation"
10276 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10277 (match_operand:SI 2 "gpc_reg_operand" "r"))
10278 (clobber (match_scratch:SI 3 "=q"))
10279 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10280 (match_operand:SI 4 "gpc_reg_operand" "r"))
10281 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10282 (match_operand:SI 5 "gpc_reg_operand" "r"))
10283 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10284 (match_operand:SI 6 "gpc_reg_operand" "r"))
10285 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10286 (match_operand:SI 7 "gpc_reg_operand" "r"))
10287 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10288 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10289 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10290 "{stsi|stswi} %2,%1,%O0"
10291 [(set_attr "type" "store_ux")
10292 (set_attr "cell_micro" "always")])
10294 (define_insn "*stmsi5_power"
10295 [(match_parallel 0 "store_multiple_operation"
10296 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10297 (match_operand:SI 2 "gpc_reg_operand" "r"))
10298 (clobber (match_scratch:SI 3 "=q"))
10299 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10300 (match_operand:SI 4 "gpc_reg_operand" "r"))
10301 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10302 (match_operand:SI 5 "gpc_reg_operand" "r"))
10303 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10304 (match_operand:SI 6 "gpc_reg_operand" "r"))
10305 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10306 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10307 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10308 "{stsi|stswi} %2,%1,%O0"
10309 [(set_attr "type" "store_ux")
10310 (set_attr "cell_micro" "always")])
10312 (define_insn "*stmsi4_power"
10313 [(match_parallel 0 "store_multiple_operation"
10314 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10315 (match_operand:SI 2 "gpc_reg_operand" "r"))
10316 (clobber (match_scratch:SI 3 "=q"))
10317 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10318 (match_operand:SI 4 "gpc_reg_operand" "r"))
10319 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10320 (match_operand:SI 5 "gpc_reg_operand" "r"))
10321 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10322 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10323 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10324 "{stsi|stswi} %2,%1,%O0"
10325 [(set_attr "type" "store_ux")
10326 (set_attr "cell_micro" "always")])
10328 (define_insn "*stmsi3_power"
10329 [(match_parallel 0 "store_multiple_operation"
10330 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10331 (match_operand:SI 2 "gpc_reg_operand" "r"))
10332 (clobber (match_scratch:SI 3 "=q"))
10333 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10334 (match_operand:SI 4 "gpc_reg_operand" "r"))
10335 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10336 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10337 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10338 "{stsi|stswi} %2,%1,%O0"
10339 [(set_attr "type" "store_ux")
10340 (set_attr "cell_micro" "always")])
10341 \f
10342 (define_expand "setmemsi"
10343 [(parallel [(set (match_operand:BLK 0 "" "")
10344 (match_operand 2 "const_int_operand" ""))
10345 (use (match_operand:SI 1 "" ""))
10346 (use (match_operand:SI 3 "" ""))])]
10347 ""
10348 "
10349 {
10350 /* If value to set is not zero, use the library routine. */
10351 if (operands[2] != const0_rtx)
10352 FAIL;
10354 if (expand_block_clear (operands))
10355 DONE;
10356 else
10357 FAIL;
10358 }")
10360 ;; String/block move insn.
10361 ;; Argument 0 is the destination
10362 ;; Argument 1 is the source
10363 ;; Argument 2 is the length
10364 ;; Argument 3 is the alignment
10366 (define_expand "movmemsi"
10367 [(parallel [(set (match_operand:BLK 0 "" "")
10368 (match_operand:BLK 1 "" ""))
10369 (use (match_operand:SI 2 "" ""))
10370 (use (match_operand:SI 3 "" ""))])]
10371 ""
10372 "
10373 {
10374 if (expand_block_move (operands))
10375 DONE;
10376 else
10377 FAIL;
10378 }")
10380 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10381 ;; register allocator doesn't have a clue about allocating 8 word registers.
10382 ;; rD/rS = r5 is preferred, efficient form.
10383 (define_expand "movmemsi_8reg"
10384 [(parallel [(set (match_operand 0 "" "")
10385 (match_operand 1 "" ""))
10386 (use (match_operand 2 "" ""))
10387 (use (match_operand 3 "" ""))
10388 (clobber (reg:SI 5))
10389 (clobber (reg:SI 6))
10390 (clobber (reg:SI 7))
10391 (clobber (reg:SI 8))
10392 (clobber (reg:SI 9))
10393 (clobber (reg:SI 10))
10394 (clobber (reg:SI 11))
10395 (clobber (reg:SI 12))
10396 (clobber (match_scratch:SI 4 ""))])]
10397 "TARGET_STRING"
10398 "")
10400 (define_insn ""
10401 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10402 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10403 (use (match_operand:SI 2 "immediate_operand" "i"))
10404 (use (match_operand:SI 3 "immediate_operand" "i"))
10405 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10406 (clobber (reg:SI 6))
10407 (clobber (reg:SI 7))
10408 (clobber (reg:SI 8))
10409 (clobber (reg:SI 9))
10410 (clobber (reg:SI 10))
10411 (clobber (reg:SI 11))
10412 (clobber (reg:SI 12))
10413 (clobber (match_scratch:SI 5 "=q"))]
10414 "TARGET_STRING && TARGET_POWER
10415 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10416 || INTVAL (operands[2]) == 0)
10417 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10418 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10419 && REGNO (operands[4]) == 5"
10420 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10421 [(set_attr "type" "store_ux")
10422 (set_attr "cell_micro" "always")
10423 (set_attr "length" "8")])
10425 (define_insn ""
10426 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10427 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10428 (use (match_operand:SI 2 "immediate_operand" "i"))
10429 (use (match_operand:SI 3 "immediate_operand" "i"))
10430 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10431 (clobber (reg:SI 6))
10432 (clobber (reg:SI 7))
10433 (clobber (reg:SI 8))
10434 (clobber (reg:SI 9))
10435 (clobber (reg:SI 10))
10436 (clobber (reg:SI 11))
10437 (clobber (reg:SI 12))
10438 (clobber (match_scratch:SI 5 "=X"))]
10439 "TARGET_STRING && ! TARGET_POWER
10440 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10441 || INTVAL (operands[2]) == 0)
10442 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10443 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10444 && REGNO (operands[4]) == 5"
10445 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10446 [(set_attr "type" "store_ux")
10447 (set_attr "cell_micro" "always")
10448 (set_attr "length" "8")])
10450 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10451 ;; register allocator doesn't have a clue about allocating 6 word registers.
10452 ;; rD/rS = r5 is preferred, efficient form.
10453 (define_expand "movmemsi_6reg"
10454 [(parallel [(set (match_operand 0 "" "")
10455 (match_operand 1 "" ""))
10456 (use (match_operand 2 "" ""))
10457 (use (match_operand 3 "" ""))
10458 (clobber (reg:SI 5))
10459 (clobber (reg:SI 6))
10460 (clobber (reg:SI 7))
10461 (clobber (reg:SI 8))
10462 (clobber (reg:SI 9))
10463 (clobber (reg:SI 10))
10464 (clobber (match_scratch:SI 4 ""))])]
10465 "TARGET_STRING"
10466 "")
10468 (define_insn ""
10469 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10470 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10471 (use (match_operand:SI 2 "immediate_operand" "i"))
10472 (use (match_operand:SI 3 "immediate_operand" "i"))
10473 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10474 (clobber (reg:SI 6))
10475 (clobber (reg:SI 7))
10476 (clobber (reg:SI 8))
10477 (clobber (reg:SI 9))
10478 (clobber (reg:SI 10))
10479 (clobber (match_scratch:SI 5 "=q"))]
10480 "TARGET_STRING && TARGET_POWER
10481 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
10482 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10483 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10484 && REGNO (operands[4]) == 5"
10485 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10486 [(set_attr "type" "store_ux")
10487 (set_attr "cell_micro" "always")
10488 (set_attr "length" "8")])
10490 (define_insn ""
10491 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10492 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10493 (use (match_operand:SI 2 "immediate_operand" "i"))
10494 (use (match_operand:SI 3 "immediate_operand" "i"))
10495 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10496 (clobber (reg:SI 6))
10497 (clobber (reg:SI 7))
10498 (clobber (reg:SI 8))
10499 (clobber (reg:SI 9))
10500 (clobber (reg:SI 10))
10501 (clobber (match_scratch:SI 5 "=X"))]
10502 "TARGET_STRING && ! TARGET_POWER
10503 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10504 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10505 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10506 && REGNO (operands[4]) == 5"
10507 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10508 [(set_attr "type" "store_ux")
10509 (set_attr "cell_micro" "always")
10510 (set_attr "length" "8")])
10512 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10513 ;; problems with TImode.
10514 ;; rD/rS = r5 is preferred, efficient form.
10515 (define_expand "movmemsi_4reg"
10516 [(parallel [(set (match_operand 0 "" "")
10517 (match_operand 1 "" ""))
10518 (use (match_operand 2 "" ""))
10519 (use (match_operand 3 "" ""))
10520 (clobber (reg:SI 5))
10521 (clobber (reg:SI 6))
10522 (clobber (reg:SI 7))
10523 (clobber (reg:SI 8))
10524 (clobber (match_scratch:SI 4 ""))])]
10525 "TARGET_STRING"
10526 "")
10528 (define_insn ""
10529 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10530 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10531 (use (match_operand:SI 2 "immediate_operand" "i"))
10532 (use (match_operand:SI 3 "immediate_operand" "i"))
10533 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10534 (clobber (reg:SI 6))
10535 (clobber (reg:SI 7))
10536 (clobber (reg:SI 8))
10537 (clobber (match_scratch:SI 5 "=q"))]
10538 "TARGET_STRING && TARGET_POWER
10539 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10540 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10541 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10542 && REGNO (operands[4]) == 5"
10543 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10544 [(set_attr "type" "store_ux")
10545 (set_attr "cell_micro" "always")
10546 (set_attr "length" "8")])
10548 (define_insn ""
10549 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10550 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10551 (use (match_operand:SI 2 "immediate_operand" "i"))
10552 (use (match_operand:SI 3 "immediate_operand" "i"))
10553 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10554 (clobber (reg:SI 6))
10555 (clobber (reg:SI 7))
10556 (clobber (reg:SI 8))
10557 (clobber (match_scratch:SI 5 "=X"))]
10558 "TARGET_STRING && ! TARGET_POWER
10559 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10560 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10561 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10562 && REGNO (operands[4]) == 5"
10563 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10564 [(set_attr "type" "store_ux")
10565 (set_attr "cell_micro" "always")
10566 (set_attr "length" "8")])
10568 ;; Move up to 8 bytes at a time.
10569 (define_expand "movmemsi_2reg"
10570 [(parallel [(set (match_operand 0 "" "")
10571 (match_operand 1 "" ""))
10572 (use (match_operand 2 "" ""))
10573 (use (match_operand 3 "" ""))
10574 (clobber (match_scratch:DI 4 ""))
10575 (clobber (match_scratch:SI 5 ""))])]
10576 "TARGET_STRING && ! TARGET_POWERPC64"
10577 "")
10579 (define_insn ""
10580 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10581 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10582 (use (match_operand:SI 2 "immediate_operand" "i"))
10583 (use (match_operand:SI 3 "immediate_operand" "i"))
10584 (clobber (match_scratch:DI 4 "=&r"))
10585 (clobber (match_scratch:SI 5 "=q"))]
10586 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
10587 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10588 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10589 [(set_attr "type" "store_ux")
10590 (set_attr "cell_micro" "always")
10591 (set_attr "length" "8")])
10593 (define_insn ""
10594 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10595 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10596 (use (match_operand:SI 2 "immediate_operand" "i"))
10597 (use (match_operand:SI 3 "immediate_operand" "i"))
10598 (clobber (match_scratch:DI 4 "=&r"))
10599 (clobber (match_scratch:SI 5 "=X"))]
10600 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
10601 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10602 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10603 [(set_attr "type" "store_ux")
10604 (set_attr "cell_micro" "always")
10605 (set_attr "length" "8")])
10607 ;; Move up to 4 bytes at a time.
10608 (define_expand "movmemsi_1reg"
10609 [(parallel [(set (match_operand 0 "" "")
10610 (match_operand 1 "" ""))
10611 (use (match_operand 2 "" ""))
10612 (use (match_operand 3 "" ""))
10613 (clobber (match_scratch:SI 4 ""))
10614 (clobber (match_scratch:SI 5 ""))])]
10615 "TARGET_STRING"
10616 "")
10618 (define_insn ""
10619 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10620 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10621 (use (match_operand:SI 2 "immediate_operand" "i"))
10622 (use (match_operand:SI 3 "immediate_operand" "i"))
10623 (clobber (match_scratch:SI 4 "=&r"))
10624 (clobber (match_scratch:SI 5 "=q"))]
10625 "TARGET_STRING && TARGET_POWER
10626 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10627 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10628 [(set_attr "type" "store_ux")
10629 (set_attr "cell_micro" "always")
10630 (set_attr "length" "8")])
10632 (define_insn ""
10633 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10634 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10635 (use (match_operand:SI 2 "immediate_operand" "i"))
10636 (use (match_operand:SI 3 "immediate_operand" "i"))
10637 (clobber (match_scratch:SI 4 "=&r"))
10638 (clobber (match_scratch:SI 5 "=X"))]
10639 "TARGET_STRING && ! TARGET_POWER
10640 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10641 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10642 [(set_attr "type" "store_ux")
10643 (set_attr "cell_micro" "always")
10644 (set_attr "length" "8")])
10645 \f
10646 ;; Define insns that do load or store with update. Some of these we can
10647 ;; get by using pre-decrement or pre-increment, but the hardware can also
10648 ;; do cases where the increment is not the size of the object.
10649 ;;
10650 ;; In all these cases, we use operands 0 and 1 for the register being
10651 ;; incremented because those are the operands that local-alloc will
10652 ;; tie and these are the pair most likely to be tieable (and the ones
10653 ;; that will benefit the most).
10655 (define_insn "*movdi_update1"
10656 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10657 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10658 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10659 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10660 (plus:DI (match_dup 1) (match_dup 2)))]
10661 "TARGET_POWERPC64 && TARGET_UPDATE
10662 && (!avoiding_indexed_address_p (DImode)
10663 || !gpc_reg_operand (operands[2], DImode))"
10664 "@
10665 ldux %3,%0,%2
10666 ldu %3,%2(%0)"
10667 [(set_attr "type" "load_ux,load_u")])
10669 (define_insn "movdi_<mode>_update"
10670 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10671 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10672 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10673 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10674 (plus:P (match_dup 1) (match_dup 2)))]
10675 "TARGET_POWERPC64 && TARGET_UPDATE
10676 && (!avoiding_indexed_address_p (Pmode)
10677 || !gpc_reg_operand (operands[2], Pmode)
10678 || (REG_P (operands[0])
10679 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10680 "@
10681 stdux %3,%0,%2
10682 stdu %3,%2(%0)"
10683 [(set_attr "type" "store_ux,store_u")])
10685 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10686 ;; needed for stack allocation, even if the user passes -mno-update.
10687 (define_insn "movdi_<mode>_update_stack"
10688 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10689 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10690 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10691 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10692 (plus:P (match_dup 1) (match_dup 2)))]
10693 "TARGET_POWERPC64"
10694 "@
10695 stdux %3,%0,%2
10696 stdu %3,%2(%0)"
10697 [(set_attr "type" "store_ux,store_u")])
10699 (define_insn "*movsi_update1"
10700 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10701 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10702 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10703 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10704 (plus:SI (match_dup 1) (match_dup 2)))]
10705 "TARGET_UPDATE
10706 && (!avoiding_indexed_address_p (SImode)
10707 || !gpc_reg_operand (operands[2], SImode))"
10708 "@
10709 {lux|lwzux} %3,%0,%2
10710 {lu|lwzu} %3,%2(%0)"
10711 [(set_attr "type" "load_ux,load_u")])
10713 (define_insn "*movsi_update2"
10714 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10715 (sign_extend:DI
10716 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10717 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10718 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10719 (plus:DI (match_dup 1) (match_dup 2)))]
10720 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10721 && !avoiding_indexed_address_p (DImode)"
10722 "lwaux %3,%0,%2"
10723 [(set_attr "type" "load_ext_ux")])
10725 (define_insn "movsi_update"
10726 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10727 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10728 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10729 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10730 (plus:SI (match_dup 1) (match_dup 2)))]
10731 "TARGET_UPDATE
10732 && (!avoiding_indexed_address_p (SImode)
10733 || !gpc_reg_operand (operands[2], SImode)
10734 || (REG_P (operands[0])
10735 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10736 "@
10737 {stux|stwux} %3,%0,%2
10738 {stu|stwu} %3,%2(%0)"
10739 [(set_attr "type" "store_ux,store_u")])
10741 ;; This is an unconditional pattern; needed for stack allocation, even
10742 ;; if the user passes -mno-update.
10743 (define_insn "movsi_update_stack"
10744 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10745 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10746 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10747 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10748 (plus:SI (match_dup 1) (match_dup 2)))]
10749 ""
10750 "@
10751 {stux|stwux} %3,%0,%2
10752 {stu|stwu} %3,%2(%0)"
10753 [(set_attr "type" "store_ux,store_u")])
10755 (define_insn "*movhi_update1"
10756 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10757 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10758 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10759 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10760 (plus:SI (match_dup 1) (match_dup 2)))]
10761 "TARGET_UPDATE
10762 && (!avoiding_indexed_address_p (SImode)
10763 || !gpc_reg_operand (operands[2], SImode))"
10764 "@
10765 lhzux %3,%0,%2
10766 lhzu %3,%2(%0)"
10767 [(set_attr "type" "load_ux,load_u")])
10769 (define_insn "*movhi_update2"
10770 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10771 (zero_extend:SI
10772 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10773 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10774 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10775 (plus:SI (match_dup 1) (match_dup 2)))]
10776 "TARGET_UPDATE
10777 && (!avoiding_indexed_address_p (SImode)
10778 || !gpc_reg_operand (operands[2], SImode))"
10779 "@
10780 lhzux %3,%0,%2
10781 lhzu %3,%2(%0)"
10782 [(set_attr "type" "load_ux,load_u")])
10784 (define_insn "*movhi_update3"
10785 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10786 (sign_extend:SI
10787 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10788 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10789 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10790 (plus:SI (match_dup 1) (match_dup 2)))]
10791 "TARGET_UPDATE && rs6000_gen_cell_microcode
10792 && (!avoiding_indexed_address_p (SImode)
10793 || !gpc_reg_operand (operands[2], SImode))"
10794 "@
10795 lhaux %3,%0,%2
10796 lhau %3,%2(%0)"
10797 [(set_attr "type" "load_ext_ux,load_ext_u")])
10799 (define_insn "*movhi_update4"
10800 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10801 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10802 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10803 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10804 (plus:SI (match_dup 1) (match_dup 2)))]
10805 "TARGET_UPDATE
10806 && (!avoiding_indexed_address_p (SImode)
10807 || !gpc_reg_operand (operands[2], SImode))"
10808 "@
10809 sthux %3,%0,%2
10810 sthu %3,%2(%0)"
10811 [(set_attr "type" "store_ux,store_u")])
10813 (define_insn "*movqi_update1"
10814 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10815 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10816 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10817 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10818 (plus:SI (match_dup 1) (match_dup 2)))]
10819 "TARGET_UPDATE
10820 && (!avoiding_indexed_address_p (SImode)
10821 || !gpc_reg_operand (operands[2], SImode))"
10822 "@
10823 lbzux %3,%0,%2
10824 lbzu %3,%2(%0)"
10825 [(set_attr "type" "load_ux,load_u")])
10827 (define_insn "*movqi_update2"
10828 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10829 (zero_extend:SI
10830 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10831 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10832 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10833 (plus:SI (match_dup 1) (match_dup 2)))]
10834 "TARGET_UPDATE
10835 && (!avoiding_indexed_address_p (SImode)
10836 || !gpc_reg_operand (operands[2], SImode))"
10837 "@
10838 lbzux %3,%0,%2
10839 lbzu %3,%2(%0)"
10840 [(set_attr "type" "load_ux,load_u")])
10842 (define_insn "*movqi_update3"
10843 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10844 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10845 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10846 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10847 (plus:SI (match_dup 1) (match_dup 2)))]
10848 "TARGET_UPDATE
10849 && (!avoiding_indexed_address_p (SImode)
10850 || !gpc_reg_operand (operands[2], SImode))"
10851 "@
10852 stbux %3,%0,%2
10853 stbu %3,%2(%0)"
10854 [(set_attr "type" "store_ux,store_u")])
10856 (define_insn "*movsf_update1"
10857 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10858 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10859 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10860 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10861 (plus:SI (match_dup 1) (match_dup 2)))]
10862 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10863 && (!avoiding_indexed_address_p (SImode)
10864 || !gpc_reg_operand (operands[2], SImode))"
10865 "@
10866 lfsux %3,%0,%2
10867 lfsu %3,%2(%0)"
10868 [(set_attr "type" "fpload_ux,fpload_u")])
10870 (define_insn "*movsf_update2"
10871 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10872 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10873 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10874 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10875 (plus:SI (match_dup 1) (match_dup 2)))]
10876 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10877 && (!avoiding_indexed_address_p (SImode)
10878 || !gpc_reg_operand (operands[2], SImode))"
10879 "@
10880 stfsux %3,%0,%2
10881 stfsu %3,%2(%0)"
10882 [(set_attr "type" "fpstore_ux,fpstore_u")])
10884 (define_insn "*movsf_update3"
10885 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10886 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10887 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10888 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10889 (plus:SI (match_dup 1) (match_dup 2)))]
10890 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10891 && (!avoiding_indexed_address_p (SImode)
10892 || !gpc_reg_operand (operands[2], SImode))"
10893 "@
10894 {lux|lwzux} %3,%0,%2
10895 {lu|lwzu} %3,%2(%0)"
10896 [(set_attr "type" "load_ux,load_u")])
10898 (define_insn "*movsf_update4"
10899 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10900 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10901 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10902 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10903 (plus:SI (match_dup 1) (match_dup 2)))]
10904 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10905 && (!avoiding_indexed_address_p (SImode)
10906 || !gpc_reg_operand (operands[2], SImode))"
10907 "@
10908 {stux|stwux} %3,%0,%2
10909 {stu|stwu} %3,%2(%0)"
10910 [(set_attr "type" "store_ux,store_u")])
10912 (define_insn "*movdf_update1"
10913 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10914 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10915 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10916 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10917 (plus:SI (match_dup 1) (match_dup 2)))]
10918 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10919 && (!avoiding_indexed_address_p (SImode)
10920 || !gpc_reg_operand (operands[2], SImode))"
10921 "@
10922 lfdux %3,%0,%2
10923 lfdu %3,%2(%0)"
10924 [(set_attr "type" "fpload_ux,fpload_u")])
10926 (define_insn "*movdf_update2"
10927 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10928 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10929 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10930 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10931 (plus:SI (match_dup 1) (match_dup 2)))]
10932 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10933 && (!avoiding_indexed_address_p (SImode)
10934 || !gpc_reg_operand (operands[2], SImode))"
10935 "@
10936 stfdux %3,%0,%2
10937 stfdu %3,%2(%0)"
10938 [(set_attr "type" "fpstore_ux,fpstore_u")])
10940 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10942 (define_insn "*lfq_power2"
10943 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10944 (match_operand:V2DF 1 "memory_operand" ""))]
10945 "TARGET_POWER2
10946 && TARGET_HARD_FLOAT && TARGET_FPRS"
10947 "lfq%U1%X1 %0,%1")
10949 (define_peephole2
10950 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10951 (match_operand:DF 1 "memory_operand" ""))
10952 (set (match_operand:DF 2 "gpc_reg_operand" "")
10953 (match_operand:DF 3 "memory_operand" ""))]
10954 "TARGET_POWER2
10955 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10956 && registers_ok_for_quad_peep (operands[0], operands[2])
10957 && mems_ok_for_quad_peep (operands[1], operands[3])"
10958 [(set (match_dup 0)
10959 (match_dup 1))]
10960 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10961 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10963 (define_insn "*stfq_power2"
10964 [(set (match_operand:V2DF 0 "memory_operand" "")
10965 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10966 "TARGET_POWER2
10967 && TARGET_HARD_FLOAT && TARGET_FPRS"
10968 "stfq%U0%X0 %1,%0")
10971 (define_peephole2
10972 [(set (match_operand:DF 0 "memory_operand" "")
10973 (match_operand:DF 1 "gpc_reg_operand" ""))
10974 (set (match_operand:DF 2 "memory_operand" "")
10975 (match_operand:DF 3 "gpc_reg_operand" ""))]
10976 "TARGET_POWER2
10977 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10978 && registers_ok_for_quad_peep (operands[1], operands[3])
10979 && mems_ok_for_quad_peep (operands[0], operands[2])"
10980 [(set (match_dup 0)
10981 (match_dup 1))]
10982 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10983 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10985 ;; After inserting conditional returns we can sometimes have
10986 ;; unnecessary register moves. Unfortunately we cannot have a
10987 ;; modeless peephole here, because some single SImode sets have early
10988 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10989 ;; sequences, using get_attr_length here will smash the operands
10990 ;; array. Neither is there an early_cobbler_p predicate.
10991 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10992 (define_peephole2
10993 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10994 (match_operand:DF 1 "any_operand" ""))
10995 (set (match_operand:DF 2 "gpc_reg_operand" "")
10996 (match_dup 0))]
10997 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10998 && peep2_reg_dead_p (2, operands[0])"
10999 [(set (match_dup 2) (match_dup 1))])
11001 (define_peephole2
11002 [(set (match_operand:SF 0 "gpc_reg_operand" "")
11003 (match_operand:SF 1 "any_operand" ""))
11004 (set (match_operand:SF 2 "gpc_reg_operand" "")
11005 (match_dup 0))]
11006 "peep2_reg_dead_p (2, operands[0])"
11007 [(set (match_dup 2) (match_dup 1))])
11009 \f
11010 ;; TLS support.
11012 ;; Mode attributes for different ABIs.
11013 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
11014 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
11015 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
11016 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
11018 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
11019 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11020 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11021 (match_operand 4 "" "g")))
11022 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11023 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11024 UNSPEC_TLSGD)
11025 (clobber (reg:SI LR_REGNO))]
11026 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11027 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
11028 "&& TARGET_TLS_MARKERS"
11029 [(set (match_dup 0)
11030 (unspec:TLSmode [(match_dup 1)
11031 (match_dup 2)]
11032 UNSPEC_TLSGD))
11033 (parallel [(set (match_dup 0)
11034 (call (mem:TLSmode (match_dup 3))
11035 (match_dup 4)))
11036 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11037 (clobber (reg:SI LR_REGNO))])]
11038 ""
11039 [(set_attr "type" "two")
11040 (set_attr "length" "12")])
11042 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
11043 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11044 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11045 (match_operand 4 "" "g")))
11046 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11047 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11048 UNSPEC_TLSGD)
11049 (clobber (reg:SI LR_REGNO))]
11050 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11051 {
11052 if (flag_pic)
11053 {
11054 if (TARGET_SECURE_PLT && flag_pic == 2)
11055 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11056 else
11057 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11058 }
11059 else
11060 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11061 }
11062 "&& TARGET_TLS_MARKERS"
11063 [(set (match_dup 0)
11064 (unspec:TLSmode [(match_dup 1)
11065 (match_dup 2)]
11066 UNSPEC_TLSGD))
11067 (parallel [(set (match_dup 0)
11068 (call (mem:TLSmode (match_dup 3))
11069 (match_dup 4)))
11070 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11071 (clobber (reg:SI LR_REGNO))])]
11072 ""
11073 [(set_attr "type" "two")
11074 (set_attr "length" "8")])
11076 (define_insn "*tls_gd<TLSmode:tls_abi_suffix>"
11077 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11078 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11079 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11080 UNSPEC_TLSGD))]
11081 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11082 "addi %0,%1,%2@got@tlsgd"
11083 [(set_attr "length" "4")])
11085 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11086 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11087 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11088 (match_operand 2 "" "g")))
11089 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11090 UNSPEC_TLSGD)
11091 (clobber (reg:SI LR_REGNO))]
11092 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11093 "bl %z1(%3@tlsgd)\;%."
11094 [(set_attr "type" "branch")
11095 (set_attr "length" "8")])
11097 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11098 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11099 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11100 (match_operand 2 "" "g")))
11101 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11102 UNSPEC_TLSGD)
11103 (clobber (reg:SI LR_REGNO))]
11104 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11105 {
11106 if (flag_pic)
11107 {
11108 if (TARGET_SECURE_PLT && flag_pic == 2)
11109 return "bl %z1+32768(%3@tlsgd)@plt";
11110 return "bl %z1(%3@tlsgd)@plt";
11111 }
11112 return "bl %z1(%3@tlsgd)";
11113 }
11114 [(set_attr "type" "branch")
11115 (set_attr "length" "4")])
11117 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11118 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11119 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11120 (match_operand 3 "" "g")))
11121 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11122 UNSPEC_TLSLD)
11123 (clobber (reg:SI LR_REGNO))]
11124 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11125 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
11126 "&& TARGET_TLS_MARKERS"
11127 [(set (match_dup 0)
11128 (unspec:TLSmode [(match_dup 1)]
11129 UNSPEC_TLSLD))
11130 (parallel [(set (match_dup 0)
11131 (call (mem:TLSmode (match_dup 2))
11132 (match_dup 3)))
11133 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11134 (clobber (reg:SI LR_REGNO))])]
11135 ""
11136 [(set_attr "length" "12")])
11138 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11139 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11140 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11141 (match_operand 3 "" "g")))
11142 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11143 UNSPEC_TLSLD)
11144 (clobber (reg:SI LR_REGNO))]
11145 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11146 {
11147 if (flag_pic)
11148 {
11149 if (TARGET_SECURE_PLT && flag_pic == 2)
11150 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11151 else
11152 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11153 }
11154 else
11155 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11156 }
11157 "&& TARGET_TLS_MARKERS"
11158 [(set (match_dup 0)
11159 (unspec:TLSmode [(match_dup 1)]
11160 UNSPEC_TLSLD))
11161 (parallel [(set (match_dup 0)
11162 (call (mem:TLSmode (match_dup 2))
11163 (match_dup 3)))
11164 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11165 (clobber (reg:SI LR_REGNO))])]
11166 ""
11167 [(set_attr "length" "8")])
11169 (define_insn "*tls_ld<TLSmode:tls_abi_suffix>"
11170 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11171 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11172 UNSPEC_TLSLD))]
11173 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11174 "addi %0,%1,%&@got@tlsld"
11175 [(set_attr "length" "4")])
11177 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11178 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11179 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11180 (match_operand 2 "" "g")))
11181 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11182 (clobber (reg:SI LR_REGNO))]
11183 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11184 "bl %z1(%&@tlsld)\;%."
11185 [(set_attr "type" "branch")
11186 (set_attr "length" "8")])
11188 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11189 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11190 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11191 (match_operand 2 "" "g")))
11192 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11193 (clobber (reg:SI LR_REGNO))]
11194 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11195 {
11196 if (flag_pic)
11197 {
11198 if (TARGET_SECURE_PLT && flag_pic == 2)
11199 return "bl %z1+32768(%&@tlsld)@plt";
11200 return "bl %z1(%&@tlsld)@plt";
11201 }
11202 return "bl %z1(%&@tlsld)";
11203 }
11204 [(set_attr "type" "branch")
11205 (set_attr "length" "4")])
11207 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11208 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11209 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11210 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11211 UNSPEC_TLSDTPREL))]
11212 "HAVE_AS_TLS"
11213 "addi %0,%1,%2@dtprel")
11215 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11216 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11217 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11218 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11219 UNSPEC_TLSDTPRELHA))]
11220 "HAVE_AS_TLS"
11221 "addis %0,%1,%2@dtprel@ha")
11223 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11224 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11225 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11226 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11227 UNSPEC_TLSDTPRELLO))]
11228 "HAVE_AS_TLS"
11229 "addi %0,%1,%2@dtprel@l")
11231 (define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11232 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11233 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11234 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11235 UNSPEC_TLSGOTDTPREL))]
11236 "HAVE_AS_TLS"
11237 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
11239 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11240 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11241 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11242 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11243 UNSPEC_TLSTPREL))]
11244 "HAVE_AS_TLS"
11245 "addi %0,%1,%2@tprel")
11247 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11248 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11249 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11250 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11251 UNSPEC_TLSTPRELHA))]
11252 "HAVE_AS_TLS"
11253 "addis %0,%1,%2@tprel@ha")
11255 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11256 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11257 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11258 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11259 UNSPEC_TLSTPRELLO))]
11260 "HAVE_AS_TLS"
11261 "addi %0,%1,%2@tprel@l")
11263 ;; "b" output constraint here and on tls_tls input to support linker tls
11264 ;; optimization. The linker may edit the instructions emitted by a
11265 ;; tls_got_tprel/tls_tls pair to addis,addi.
11266 (define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11267 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11268 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11269 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11270 UNSPEC_TLSGOTTPREL))]
11271 "HAVE_AS_TLS"
11272 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
11274 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11275 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11276 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11277 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11278 UNSPEC_TLSTLS))]
11279 "HAVE_AS_TLS"
11280 "add %0,%1,%2@tls")
11282 \f
11283 ;; Next come insns related to the calling sequence.
11284 ;;
11285 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11286 ;; We move the back-chain and decrement the stack pointer.
11288 (define_expand "allocate_stack"
11289 [(set (match_operand 0 "gpc_reg_operand" "")
11290 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11291 (set (reg 1)
11292 (minus (reg 1) (match_dup 1)))]
11293 ""
11294 "
11295 { rtx chain = gen_reg_rtx (Pmode);
11296 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11297 rtx neg_op0;
11298 rtx insn, par, set, mem;
11300 emit_move_insn (chain, stack_bot);
11302 /* Check stack bounds if necessary. */
11303 if (crtl->limit_stack)
11304 {
11305 rtx available;
11306 available = expand_binop (Pmode, sub_optab,
11307 stack_pointer_rtx, stack_limit_rtx,
11308 NULL_RTX, 1, OPTAB_WIDEN);
11309 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11310 }
11312 if (GET_CODE (operands[1]) != CONST_INT
11313 || INTVAL (operands[1]) < -32767
11314 || INTVAL (operands[1]) > 32768)
11315 {
11316 neg_op0 = gen_reg_rtx (Pmode);
11317 if (TARGET_32BIT)
11318 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11319 else
11320 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11321 }
11322 else
11323 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11325 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11326 : gen_movdi_di_update_stack))
11327 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11328 chain));
11329 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11330 it now and set the alias set/attributes. The above gen_*_update
11331 calls will generate a PARALLEL with the MEM set being the first
11332 operation. */
11333 par = PATTERN (insn);
11334 gcc_assert (GET_CODE (par) == PARALLEL);
11335 set = XVECEXP (par, 0, 0);
11336 gcc_assert (GET_CODE (set) == SET);
11337 mem = SET_DEST (set);
11338 gcc_assert (MEM_P (mem));
11339 MEM_NOTRAP_P (mem) = 1;
11340 set_mem_alias_set (mem, get_frame_alias_set ());
11342 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11343 DONE;
11344 }")
11346 ;; These patterns say how to save and restore the stack pointer. We need not
11347 ;; save the stack pointer at function level since we are careful to
11348 ;; preserve the backchain. At block level, we have to restore the backchain
11349 ;; when we restore the stack pointer.
11350 ;;
11351 ;; For nonlocal gotos, we must save both the stack pointer and its
11352 ;; backchain and restore both. Note that in the nonlocal case, the
11353 ;; save area is a memory location.
11355 (define_expand "save_stack_function"
11356 [(match_operand 0 "any_operand" "")
11357 (match_operand 1 "any_operand" "")]
11358 ""
11359 "DONE;")
11361 (define_expand "restore_stack_function"
11362 [(match_operand 0 "any_operand" "")
11363 (match_operand 1 "any_operand" "")]
11364 ""
11365 "DONE;")
11367 ;; Adjust stack pointer (op0) to a new value (op1).
11368 ;; First copy old stack backchain to new location, and ensure that the
11369 ;; scheduler won't reorder the sp assignment before the backchain write.
11370 (define_expand "restore_stack_block"
11371 [(set (match_dup 2) (match_dup 3))
11372 (set (match_dup 4) (match_dup 2))
11373 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
11374 (set (match_operand 0 "register_operand" "")
11375 (match_operand 1 "register_operand" ""))]
11376 ""
11377 "
11378 {
11379 operands[1] = force_reg (Pmode, operands[1]);
11380 operands[2] = gen_reg_rtx (Pmode);
11381 operands[3] = gen_frame_mem (Pmode, operands[0]);
11382 operands[4] = gen_frame_mem (Pmode, operands[1]);
11383 operands[5] = gen_frame_mem (BLKmode, operands[0]);
11384 }")
11386 (define_expand "save_stack_nonlocal"
11387 [(set (match_dup 3) (match_dup 4))
11388 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11389 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11390 ""
11391 "
11392 {
11393 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11395 /* Copy the backchain to the first word, sp to the second. */
11396 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11397 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11398 operands[3] = gen_reg_rtx (Pmode);
11399 operands[4] = gen_frame_mem (Pmode, operands[1]);
11400 }")
11402 (define_expand "restore_stack_nonlocal"
11403 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11404 (set (match_dup 3) (match_dup 4))
11405 (set (match_dup 5) (match_dup 2))
11406 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
11407 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11408 ""
11409 "
11410 {
11411 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11413 /* Restore the backchain from the first word, sp from the second. */
11414 operands[2] = gen_reg_rtx (Pmode);
11415 operands[3] = gen_reg_rtx (Pmode);
11416 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11417 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11418 operands[5] = gen_frame_mem (Pmode, operands[3]);
11419 operands[6] = gen_frame_mem (BLKmode, operands[0]);
11420 }")
11421 \f
11422 ;; TOC register handling.
11424 ;; Code to initialize the TOC register...
11426 (define_insn "load_toc_aix_si"
11427 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11428 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11429 (use (reg:SI 2))])]
11430 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
11431 "*
11432 {
11433 char buf[30];
11434 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11435 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11436 operands[2] = gen_rtx_REG (Pmode, 2);
11437 return \"{l|lwz} %0,%1(%2)\";
11438 }"
11439 [(set_attr "type" "load")])
11441 (define_insn "load_toc_aix_di"
11442 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11443 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11444 (use (reg:DI 2))])]
11445 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
11446 "*
11447 {
11448 char buf[30];
11449 #ifdef TARGET_RELOCATABLE
11450 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11451 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11452 #else
11453 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11454 #endif
11455 if (TARGET_ELF)
11456 strcat (buf, \"@toc\");
11457 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11458 operands[2] = gen_rtx_REG (Pmode, 2);
11459 return \"ld %0,%1(%2)\";
11460 }"
11461 [(set_attr "type" "load")])
11463 (define_insn "load_toc_v4_pic_si"
11464 [(set (reg:SI LR_REGNO)
11465 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11466 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11467 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11468 [(set_attr "type" "branch")
11469 (set_attr "length" "4")])
11471 (define_insn "load_toc_v4_PIC_1"
11472 [(set (reg:SI LR_REGNO)
11473 (match_operand:SI 0 "immediate_operand" "s"))
11474 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11475 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
11476 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11477 "bcl 20,31,%0\\n%0:"
11478 [(set_attr "type" "branch")
11479 (set_attr "length" "4")])
11481 (define_insn "load_toc_v4_PIC_1b"
11482 [(set (reg:SI LR_REGNO)
11483 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
11484 UNSPEC_TOCPTR))]
11485 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11486 "bcl 20,31,$+8\\n\\t.long %0-$"
11487 [(set_attr "type" "branch")
11488 (set_attr "length" "8")])
11490 (define_insn "load_toc_v4_PIC_2"
11491 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11492 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11493 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11494 (match_operand:SI 3 "immediate_operand" "s")))))]
11495 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11496 "{l|lwz} %0,%2-%3(%1)"
11497 [(set_attr "type" "load")])
11499 (define_insn "load_toc_v4_PIC_3b"
11500 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
11501 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11502 (high:SI
11503 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11504 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11505 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11506 "{cau|addis} %0,%1,%2-%3@ha")
11508 (define_insn "load_toc_v4_PIC_3c"
11509 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11510 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11511 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11512 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11513 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11514 "{cal|addi} %0,%1,%2-%3@l")
11516 ;; If the TOC is shared over a translation unit, as happens with all
11517 ;; the kinds of PIC that we support, we need to restore the TOC
11518 ;; pointer only when jumping over units of translation.
11519 ;; On Darwin, we need to reload the picbase.
11521 (define_expand "builtin_setjmp_receiver"
11522 [(use (label_ref (match_operand 0 "" "")))]
11523 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11524 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11525 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11526 "
11527 {
11528 #if TARGET_MACHO
11529 if (DEFAULT_ABI == ABI_DARWIN)
11530 {
11531 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11532 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11533 rtx tmplabrtx;
11534 char tmplab[20];
11536 crtl->uses_pic_offset_table = 1;
11537 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11538 CODE_LABEL_NUMBER (operands[0]));
11539 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11541 emit_insn (gen_load_macho_picbase (tmplabrtx));
11542 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11543 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11544 }
11545 else
11546 #endif
11547 rs6000_emit_load_toc_table (FALSE);
11548 DONE;
11549 }")
11551 ;; Elf specific ways of loading addresses for non-PIC code.
11552 ;; The output of this could be r0, but we make a very strong
11553 ;; preference for a base register because it will usually
11554 ;; be needed there.
11555 (define_insn "elf_high"
11556 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11557 (high:SI (match_operand 1 "" "")))]
11558 "TARGET_ELF && ! TARGET_64BIT"
11559 "{liu|lis} %0,%1@ha")
11561 (define_insn "elf_low"
11562 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11563 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11564 (match_operand 2 "" "")))]
11565 "TARGET_ELF && ! TARGET_64BIT"
11566 "@
11567 {cal|la} %0,%2@l(%1)
11568 {ai|addic} %0,%1,%K2")
11569 \f
11570 ;; A function pointer under AIX is a pointer to a data area whose first word
11571 ;; contains the actual address of the function, whose second word contains a
11572 ;; pointer to its TOC, and whose third word contains a value to place in the
11573 ;; static chain register (r11). Note that if we load the static chain, our
11574 ;; "trampoline" need not have any executable code.
11576 (define_expand "call_indirect_aix32"
11577 [(set (match_dup 2)
11578 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
11579 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11580 (reg:SI 2))
11581 (set (reg:SI 11)
11582 (mem:SI (plus:SI (match_dup 0)
11583 (const_int 8))))
11584 (parallel [(call (mem:SI (match_dup 2))
11585 (match_operand 1 "" ""))
11586 (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
11587 (use (reg:SI 11))
11588 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11589 (clobber (reg:SI LR_REGNO))])]
11590 "TARGET_32BIT"
11591 "
11592 { operands[2] = gen_reg_rtx (SImode); }")
11594 (define_expand "call_indirect_aix64"
11595 [(set (match_dup 2)
11596 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
11597 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11598 (reg:DI 2))
11599 (set (reg:DI 11)
11600 (mem:DI (plus:DI (match_dup 0)
11601 (const_int 16))))
11602 (parallel [(call (mem:SI (match_dup 2))
11603 (match_operand 1 "" ""))
11604 (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
11605 (use (reg:DI 11))
11606 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11607 (clobber (reg:SI LR_REGNO))])]
11608 "TARGET_64BIT"
11609 "
11610 { operands[2] = gen_reg_rtx (DImode); }")
11612 (define_expand "call_value_indirect_aix32"
11613 [(set (match_dup 3)
11614 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11615 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11616 (reg:SI 2))
11617 (set (reg:SI 11)
11618 (mem:SI (plus:SI (match_dup 1)
11619 (const_int 8))))
11620 (parallel [(set (match_operand 0 "" "")
11621 (call (mem:SI (match_dup 3))
11622 (match_operand 2 "" "")))
11623 (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
11624 (use (reg:SI 11))
11625 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11626 (clobber (reg:SI LR_REGNO))])]
11627 "TARGET_32BIT"
11628 "
11629 { operands[3] = gen_reg_rtx (SImode); }")
11631 (define_expand "call_value_indirect_aix64"
11632 [(set (match_dup 3)
11633 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11634 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11635 (reg:DI 2))
11636 (set (reg:DI 11)
11637 (mem:DI (plus:DI (match_dup 1)
11638 (const_int 16))))
11639 (parallel [(set (match_operand 0 "" "")
11640 (call (mem:SI (match_dup 3))
11641 (match_operand 2 "" "")))
11642 (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
11643 (use (reg:DI 11))
11644 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11645 (clobber (reg:SI LR_REGNO))])]
11646 "TARGET_64BIT"
11647 "
11648 { operands[3] = gen_reg_rtx (DImode); }")
11650 ;; Now the definitions for the call and call_value insns
11651 (define_expand "call"
11652 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11653 (match_operand 1 "" ""))
11654 (use (match_operand 2 "" ""))
11655 (clobber (reg:SI LR_REGNO))])]
11656 ""
11657 "
11658 {
11659 #if TARGET_MACHO
11660 if (MACHOPIC_INDIRECT)
11661 operands[0] = machopic_indirect_call_target (operands[0]);
11662 #endif
11664 gcc_assert (GET_CODE (operands[0]) == MEM);
11665 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11667 operands[0] = XEXP (operands[0], 0);
11669 if (GET_CODE (operands[0]) != SYMBOL_REF
11670 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
11671 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11672 {
11673 if (INTVAL (operands[2]) & CALL_LONG)
11674 operands[0] = rs6000_longcall_ref (operands[0]);
11676 switch (DEFAULT_ABI)
11677 {
11678 case ABI_V4:
11679 case ABI_DARWIN:
11680 operands[0] = force_reg (Pmode, operands[0]);
11681 break;
11683 case ABI_AIX:
11684 /* AIX function pointers are really pointers to a three word
11685 area. */
11686 emit_call_insn (TARGET_32BIT
11687 ? gen_call_indirect_aix32 (force_reg (SImode,
11688 operands[0]),
11689 operands[1])
11690 : gen_call_indirect_aix64 (force_reg (DImode,
11691 operands[0]),
11692 operands[1]));
11693 DONE;
11695 default:
11696 gcc_unreachable ();
11697 }
11698 }
11699 }")
11701 (define_expand "call_value"
11702 [(parallel [(set (match_operand 0 "" "")
11703 (call (mem:SI (match_operand 1 "address_operand" ""))
11704 (match_operand 2 "" "")))
11705 (use (match_operand 3 "" ""))
11706 (clobber (reg:SI LR_REGNO))])]
11707 ""
11708 "
11709 {
11710 #if TARGET_MACHO
11711 if (MACHOPIC_INDIRECT)
11712 operands[1] = machopic_indirect_call_target (operands[1]);
11713 #endif
11715 gcc_assert (GET_CODE (operands[1]) == MEM);
11716 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11718 operands[1] = XEXP (operands[1], 0);
11720 if (GET_CODE (operands[1]) != SYMBOL_REF
11721 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
11722 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11723 {
11724 if (INTVAL (operands[3]) & CALL_LONG)
11725 operands[1] = rs6000_longcall_ref (operands[1]);
11727 switch (DEFAULT_ABI)
11728 {
11729 case ABI_V4:
11730 case ABI_DARWIN:
11731 operands[1] = force_reg (Pmode, operands[1]);
11732 break;
11734 case ABI_AIX:
11735 /* AIX function pointers are really pointers to a three word
11736 area. */
11737 emit_call_insn (TARGET_32BIT
11738 ? gen_call_value_indirect_aix32 (operands[0],
11739 force_reg (SImode,
11740 operands[1]),
11741 operands[2])
11742 : gen_call_value_indirect_aix64 (operands[0],
11743 force_reg (DImode,
11744 operands[1]),
11745 operands[2]));
11746 DONE;
11748 default:
11749 gcc_unreachable ();
11750 }
11751 }
11752 }")
11754 ;; Call to function in current module. No TOC pointer reload needed.
11755 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11756 ;; either the function was not prototyped, or it was prototyped as a
11757 ;; variable argument function. It is > 0 if FP registers were passed
11758 ;; and < 0 if they were not.
11760 (define_insn "*call_local32"
11761 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11762 (match_operand 1 "" "g,g"))
11763 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11764 (clobber (reg:SI LR_REGNO))]
11765 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11766 "*
11767 {
11768 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11769 output_asm_insn (\"crxor 6,6,6\", operands);
11771 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11772 output_asm_insn (\"creqv 6,6,6\", operands);
11774 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11775 }"
11776 [(set_attr "type" "branch")
11777 (set_attr "length" "4,8")])
11779 (define_insn "*call_local64"
11780 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11781 (match_operand 1 "" "g,g"))
11782 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11783 (clobber (reg:SI LR_REGNO))]
11784 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11785 "*
11786 {
11787 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11788 output_asm_insn (\"crxor 6,6,6\", operands);
11790 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11791 output_asm_insn (\"creqv 6,6,6\", operands);
11793 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11794 }"
11795 [(set_attr "type" "branch")
11796 (set_attr "length" "4,8")])
11798 (define_insn "*call_value_local32"
11799 [(set (match_operand 0 "" "")
11800 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11801 (match_operand 2 "" "g,g")))
11802 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11803 (clobber (reg:SI LR_REGNO))]
11804 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11805 "*
11806 {
11807 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11808 output_asm_insn (\"crxor 6,6,6\", operands);
11810 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11811 output_asm_insn (\"creqv 6,6,6\", operands);
11813 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11814 }"
11815 [(set_attr "type" "branch")
11816 (set_attr "length" "4,8")])
11819 (define_insn "*call_value_local64"
11820 [(set (match_operand 0 "" "")
11821 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11822 (match_operand 2 "" "g,g")))
11823 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11824 (clobber (reg:SI LR_REGNO))]
11825 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11826 "*
11827 {
11828 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11829 output_asm_insn (\"crxor 6,6,6\", operands);
11831 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11832 output_asm_insn (\"creqv 6,6,6\", operands);
11834 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11835 }"
11836 [(set_attr "type" "branch")
11837 (set_attr "length" "4,8")])
11839 ;; Call to function which may be in another module. Restore the TOC
11840 ;; pointer (r2) after the call unless this is System V.
11841 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11842 ;; either the function was not prototyped, or it was prototyped as a
11843 ;; variable argument function. It is > 0 if FP registers were passed
11844 ;; and < 0 if they were not.
11846 (define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
11847 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11848 (match_operand 1 "" "g,g"))
11849 (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
11850 (use (reg:SI 11))
11851 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11852 (clobber (reg:SI LR_REGNO))]
11853 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11854 "#"
11855 "&& reload_completed"
11856 [(set (reg:SI 2)
11857 (mem:SI (plus:SI (match_dup 2) (const_int 4))))
11858 (parallel [(call (mem:SI (match_dup 0))
11859 (match_dup 1))
11860 (use (reg:SI 2))
11861 (use (reg:SI 11))
11862 (set (reg:SI 2)
11863 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11864 (clobber (reg:SI LR_REGNO))])]
11865 ""
11866 [(set_attr "type" "jmpreg")
11867 (set_attr "length" "12")])
11869 (define_insn "*call_indirect_nonlocal_aix32"
11870 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11871 (match_operand 1 "" "g,g"))
11872 (use (reg:SI 2))
11873 (use (reg:SI 11))
11874 (set (reg:SI 2)
11875 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11876 (clobber (reg:SI LR_REGNO))]
11877 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11878 "b%T0l\;{l|lwz} 2,20(1)"
11879 [(set_attr "type" "jmpreg")
11880 (set_attr "length" "8")])
11882 (define_insn "*call_nonlocal_aix32"
11883 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11884 (match_operand 1 "" "g"))
11885 (use (match_operand:SI 2 "immediate_operand" "O"))
11886 (clobber (reg:SI LR_REGNO))]
11887 "TARGET_32BIT
11888 && DEFAULT_ABI == ABI_AIX
11889 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11890 "bl %z0\;%."
11891 [(set_attr "type" "branch")
11892 (set_attr "length" "8")])
11894 (define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
11895 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11896 (match_operand 1 "" "g,g"))
11897 (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
11898 (const_int 8))))
11899 (use (reg:DI 11))
11900 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11901 (clobber (reg:SI LR_REGNO))]
11902 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11903 "#"
11904 "&& reload_completed"
11905 [(set (reg:DI 2)
11906 (mem:DI (plus:DI (match_dup 2) (const_int 8))))
11907 (parallel [(call (mem:SI (match_dup 0))
11908 (match_dup 1))
11909 (use (reg:DI 2))
11910 (use (reg:DI 11))
11911 (set (reg:DI 2)
11912 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11913 (clobber (reg:SI LR_REGNO))])]
11914 ""
11915 [(set_attr "type" "jmpreg")
11916 (set_attr "length" "12")])
11918 (define_insn "*call_indirect_nonlocal_aix64"
11919 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11920 (match_operand 1 "" "g,g"))
11921 (use (reg:DI 2))
11922 (use (reg:DI 11))
11923 (set (reg:DI 2)
11924 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11925 (clobber (reg:SI LR_REGNO))]
11926 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11927 "b%T0l\;ld 2,40(1)"
11928 [(set_attr "type" "jmpreg")
11929 (set_attr "length" "8")])
11931 (define_insn "*call_nonlocal_aix64"
11932 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11933 (match_operand 1 "" "g"))
11934 (use (match_operand:SI 2 "immediate_operand" "O"))
11935 (clobber (reg:SI LR_REGNO))]
11936 "TARGET_64BIT
11937 && DEFAULT_ABI == ABI_AIX
11938 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11939 "bl %z0\;%."
11940 [(set_attr "type" "branch")
11941 (set_attr "length" "8")])
11943 (define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
11944 [(set (match_operand 0 "" "")
11945 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11946 (match_operand 2 "" "g,g")))
11947 (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
11948 (const_int 4))))
11949 (use (reg:SI 11))
11950 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11951 (clobber (reg:SI LR_REGNO))]
11952 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11953 "#"
11954 "&& reload_completed"
11955 [(set (reg:SI 2)
11956 (mem:SI (plus:SI (match_dup 3) (const_int 4))))
11957 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11958 (match_dup 2)))
11959 (use (reg:SI 2))
11960 (use (reg:SI 11))
11961 (set (reg:SI 2)
11962 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11963 (clobber (reg:SI LR_REGNO))])]
11964 ""
11965 [(set_attr "type" "jmpreg")
11966 (set_attr "length" "12")])
11968 (define_insn "*call_value_indirect_nonlocal_aix32"
11969 [(set (match_operand 0 "" "")
11970 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11971 (match_operand 2 "" "g,g")))
11972 (use (reg:SI 2))
11973 (use (reg:SI 11))
11974 (set (reg:SI 2)
11975 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11976 (clobber (reg:SI LR_REGNO))]
11977 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11978 "b%T1l\;{l|lwz} 2,20(1)"
11979 [(set_attr "type" "jmpreg")
11980 (set_attr "length" "8")])
11982 (define_insn "*call_value_nonlocal_aix32"
11983 [(set (match_operand 0 "" "")
11984 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11985 (match_operand 2 "" "g")))
11986 (use (match_operand:SI 3 "immediate_operand" "O"))
11987 (clobber (reg:SI LR_REGNO))]
11988 "TARGET_32BIT
11989 && DEFAULT_ABI == ABI_AIX
11990 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11991 "bl %z1\;%."
11992 [(set_attr "type" "branch")
11993 (set_attr "length" "8")])
11995 (define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
11996 [(set (match_operand 0 "" "")
11997 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11998 (match_operand 2 "" "g,g")))
11999 (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
12000 (const_int 8))))
12001 (use (reg:DI 11))
12002 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12003 (clobber (reg:SI LR_REGNO))]
12004 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
12005 "#"
12006 "&& reload_completed"
12007 [(set (reg:DI 2)
12008 (mem:DI (plus:DI (match_dup 3) (const_int 8))))
12009 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
12010 (match_dup 2)))
12011 (use (reg:DI 2))
12012 (use (reg:DI 11))
12013 (set (reg:DI 2)
12014 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12015 (clobber (reg:SI LR_REGNO))])]
12016 ""
12017 [(set_attr "type" "jmpreg")
12018 (set_attr "length" "12")])
12020 (define_insn "*call_value_indirect_nonlocal_aix64"
12021 [(set (match_operand 0 "" "")
12022 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
12023 (match_operand 2 "" "g,g")))
12024 (use (reg:DI 2))
12025 (use (reg:DI 11))
12026 (set (reg:DI 2)
12027 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12028 (clobber (reg:SI LR_REGNO))]
12029 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12030 "b%T1l\;ld 2,40(1)"
12031 [(set_attr "type" "jmpreg")
12032 (set_attr "length" "8")])
12034 (define_insn "*call_value_nonlocal_aix64"
12035 [(set (match_operand 0 "" "")
12036 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12037 (match_operand 2 "" "g")))
12038 (use (match_operand:SI 3 "immediate_operand" "O"))
12039 (clobber (reg:SI LR_REGNO))]
12040 "TARGET_64BIT
12041 && DEFAULT_ABI == ABI_AIX
12042 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12043 "bl %z1\;%."
12044 [(set_attr "type" "branch")
12045 (set_attr "length" "8")])
12047 ;; A function pointer under System V is just a normal pointer
12048 ;; operands[0] is the function pointer
12049 ;; operands[1] is the stack size to clean up
12050 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12051 ;; which indicates how to set cr1
12053 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12054 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12055 (match_operand 1 "" "g,g,g,g"))
12056 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12057 (clobber (reg:SI LR_REGNO))]
12058 "DEFAULT_ABI == ABI_V4
12059 || DEFAULT_ABI == ABI_DARWIN"
12060 {
12061 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12062 output_asm_insn ("crxor 6,6,6", operands);
12064 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12065 output_asm_insn ("creqv 6,6,6", operands);
12067 return "b%T0l";
12068 }
12069 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12070 (set_attr "length" "4,4,8,8")])
12072 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12073 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12074 (match_operand 1 "" "g,g"))
12075 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12076 (clobber (reg:SI LR_REGNO))]
12077 "(DEFAULT_ABI == ABI_DARWIN
12078 || (DEFAULT_ABI == ABI_V4
12079 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12080 {
12081 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12082 output_asm_insn ("crxor 6,6,6", operands);
12084 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12085 output_asm_insn ("creqv 6,6,6", operands);
12087 #if TARGET_MACHO
12088 return output_call(insn, operands, 0, 2);
12089 #else
12090 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12091 {
12092 gcc_assert (!TARGET_SECURE_PLT);
12093 return "bl %z0@plt";
12094 }
12095 else
12096 return "bl %z0";
12097 #endif
12098 }
12099 "DEFAULT_ABI == ABI_V4
12100 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12101 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12102 [(parallel [(call (mem:SI (match_dup 0))
12103 (match_dup 1))
12104 (use (match_dup 2))
12105 (use (match_dup 3))
12106 (clobber (reg:SI LR_REGNO))])]
12107 {
12108 operands[3] = pic_offset_table_rtx;
12109 }
12110 [(set_attr "type" "branch,branch")
12111 (set_attr "length" "4,8")])
12113 (define_insn "*call_nonlocal_sysv_secure<mode>"
12114 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12115 (match_operand 1 "" "g,g"))
12116 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12117 (use (match_operand:SI 3 "register_operand" "r,r"))
12118 (clobber (reg:SI LR_REGNO))]
12119 "(DEFAULT_ABI == ABI_V4
12120 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12121 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12122 {
12123 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12124 output_asm_insn ("crxor 6,6,6", operands);
12126 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12127 output_asm_insn ("creqv 6,6,6", operands);
12129 if (flag_pic == 2)
12130 /* The magic 32768 offset here and in the other sysv call insns
12131 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12132 See sysv4.h:toc_section. */
12133 return "bl %z0+32768@plt";
12134 else
12135 return "bl %z0@plt";
12136 }
12137 [(set_attr "type" "branch,branch")
12138 (set_attr "length" "4,8")])
12140 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12141 [(set (match_operand 0 "" "")
12142 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12143 (match_operand 2 "" "g,g,g,g")))
12144 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12145 (clobber (reg:SI LR_REGNO))]
12146 "DEFAULT_ABI == ABI_V4
12147 || DEFAULT_ABI == ABI_DARWIN"
12148 {
12149 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12150 output_asm_insn ("crxor 6,6,6", operands);
12152 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12153 output_asm_insn ("creqv 6,6,6", operands);
12155 return "b%T1l";
12156 }
12157 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12158 (set_attr "length" "4,4,8,8")])
12160 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12161 [(set (match_operand 0 "" "")
12162 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12163 (match_operand 2 "" "g,g")))
12164 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12165 (clobber (reg:SI LR_REGNO))]
12166 "(DEFAULT_ABI == ABI_DARWIN
12167 || (DEFAULT_ABI == ABI_V4
12168 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12169 {
12170 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12171 output_asm_insn ("crxor 6,6,6", operands);
12173 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12174 output_asm_insn ("creqv 6,6,6", operands);
12176 #if TARGET_MACHO
12177 return output_call(insn, operands, 1, 3);
12178 #else
12179 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12180 {
12181 gcc_assert (!TARGET_SECURE_PLT);
12182 return "bl %z1@plt";
12183 }
12184 else
12185 return "bl %z1";
12186 #endif
12187 }
12188 "DEFAULT_ABI == ABI_V4
12189 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12190 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12191 [(parallel [(set (match_dup 0)
12192 (call (mem:SI (match_dup 1))
12193 (match_dup 2)))
12194 (use (match_dup 3))
12195 (use (match_dup 4))
12196 (clobber (reg:SI LR_REGNO))])]
12197 {
12198 operands[4] = pic_offset_table_rtx;
12199 }
12200 [(set_attr "type" "branch,branch")
12201 (set_attr "length" "4,8")])
12203 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12204 [(set (match_operand 0 "" "")
12205 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12206 (match_operand 2 "" "g,g")))
12207 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12208 (use (match_operand:SI 4 "register_operand" "r,r"))
12209 (clobber (reg:SI LR_REGNO))]
12210 "(DEFAULT_ABI == ABI_V4
12211 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12212 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12213 {
12214 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12215 output_asm_insn ("crxor 6,6,6", operands);
12217 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12218 output_asm_insn ("creqv 6,6,6", operands);
12220 if (flag_pic == 2)
12221 return "bl %z1+32768@plt";
12222 else
12223 return "bl %z1@plt";
12224 }
12225 [(set_attr "type" "branch,branch")
12226 (set_attr "length" "4,8")])
12228 ;; Call subroutine returning any type.
12229 (define_expand "untyped_call"
12230 [(parallel [(call (match_operand 0 "" "")
12231 (const_int 0))
12232 (match_operand 1 "" "")
12233 (match_operand 2 "" "")])]
12234 ""
12235 "
12236 {
12237 int i;
12239 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12241 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12242 {
12243 rtx set = XVECEXP (operands[2], 0, i);
12244 emit_move_insn (SET_DEST (set), SET_SRC (set));
12245 }
12247 /* The optimizer does not know that the call sets the function value
12248 registers we stored in the result block. We avoid problems by
12249 claiming that all hard registers are used and clobbered at this
12250 point. */
12251 emit_insn (gen_blockage ());
12253 DONE;
12254 }")
12256 ;; sibling call patterns
12257 (define_expand "sibcall"
12258 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12259 (match_operand 1 "" ""))
12260 (use (match_operand 2 "" ""))
12261 (use (reg:SI LR_REGNO))
12262 (return)])]
12263 ""
12264 "
12265 {
12266 #if TARGET_MACHO
12267 if (MACHOPIC_INDIRECT)
12268 operands[0] = machopic_indirect_call_target (operands[0]);
12269 #endif
12271 gcc_assert (GET_CODE (operands[0]) == MEM);
12272 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12274 operands[0] = XEXP (operands[0], 0);
12275 }")
12277 ;; this and similar patterns must be marked as using LR, otherwise
12278 ;; dataflow will try to delete the store into it. This is true
12279 ;; even when the actual reg to jump to is in CTR, when LR was
12280 ;; saved and restored around the PIC-setting BCL.
12281 (define_insn "*sibcall_local32"
12282 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12283 (match_operand 1 "" "g,g"))
12284 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12285 (use (reg:SI LR_REGNO))
12286 (return)]
12287 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12288 "*
12289 {
12290 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12291 output_asm_insn (\"crxor 6,6,6\", operands);
12293 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12294 output_asm_insn (\"creqv 6,6,6\", operands);
12296 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12297 }"
12298 [(set_attr "type" "branch")
12299 (set_attr "length" "4,8")])
12301 (define_insn "*sibcall_local64"
12302 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12303 (match_operand 1 "" "g,g"))
12304 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12305 (use (reg:SI LR_REGNO))
12306 (return)]
12307 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12308 "*
12309 {
12310 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12311 output_asm_insn (\"crxor 6,6,6\", operands);
12313 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12314 output_asm_insn (\"creqv 6,6,6\", operands);
12316 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12317 }"
12318 [(set_attr "type" "branch")
12319 (set_attr "length" "4,8")])
12321 (define_insn "*sibcall_value_local32"
12322 [(set (match_operand 0 "" "")
12323 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12324 (match_operand 2 "" "g,g")))
12325 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12326 (use (reg:SI LR_REGNO))
12327 (return)]
12328 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12329 "*
12330 {
12331 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12332 output_asm_insn (\"crxor 6,6,6\", operands);
12334 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12335 output_asm_insn (\"creqv 6,6,6\", operands);
12337 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12338 }"
12339 [(set_attr "type" "branch")
12340 (set_attr "length" "4,8")])
12343 (define_insn "*sibcall_value_local64"
12344 [(set (match_operand 0 "" "")
12345 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12346 (match_operand 2 "" "g,g")))
12347 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12348 (use (reg:SI LR_REGNO))
12349 (return)]
12350 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12351 "*
12352 {
12353 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12354 output_asm_insn (\"crxor 6,6,6\", operands);
12356 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12357 output_asm_insn (\"creqv 6,6,6\", operands);
12359 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12360 }"
12361 [(set_attr "type" "branch")
12362 (set_attr "length" "4,8")])
12364 (define_insn "*sibcall_nonlocal_aix32"
12365 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12366 (match_operand 1 "" "g"))
12367 (use (match_operand:SI 2 "immediate_operand" "O"))
12368 (use (reg:SI LR_REGNO))
12369 (return)]
12370 "TARGET_32BIT
12371 && DEFAULT_ABI == ABI_AIX
12372 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12373 "b %z0"
12374 [(set_attr "type" "branch")
12375 (set_attr "length" "4")])
12377 (define_insn "*sibcall_nonlocal_aix64"
12378 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12379 (match_operand 1 "" "g"))
12380 (use (match_operand:SI 2 "immediate_operand" "O"))
12381 (use (reg:SI LR_REGNO))
12382 (return)]
12383 "TARGET_64BIT
12384 && DEFAULT_ABI == ABI_AIX
12385 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12386 "b %z0"
12387 [(set_attr "type" "branch")
12388 (set_attr "length" "4")])
12390 (define_insn "*sibcall_value_nonlocal_aix32"
12391 [(set (match_operand 0 "" "")
12392 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12393 (match_operand 2 "" "g")))
12394 (use (match_operand:SI 3 "immediate_operand" "O"))
12395 (use (reg:SI LR_REGNO))
12396 (return)]
12397 "TARGET_32BIT
12398 && DEFAULT_ABI == ABI_AIX
12399 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12400 "b %z1"
12401 [(set_attr "type" "branch")
12402 (set_attr "length" "4")])
12404 (define_insn "*sibcall_value_nonlocal_aix64"
12405 [(set (match_operand 0 "" "")
12406 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12407 (match_operand 2 "" "g")))
12408 (use (match_operand:SI 3 "immediate_operand" "O"))
12409 (use (reg:SI LR_REGNO))
12410 (return)]
12411 "TARGET_64BIT
12412 && DEFAULT_ABI == ABI_AIX
12413 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12414 "b %z1"
12415 [(set_attr "type" "branch")
12416 (set_attr "length" "4")])
12418 (define_insn "*sibcall_nonlocal_sysv<mode>"
12419 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12420 (match_operand 1 "" ""))
12421 (use (match_operand 2 "immediate_operand" "O,n"))
12422 (use (reg:SI LR_REGNO))
12423 (return)]
12424 "(DEFAULT_ABI == ABI_DARWIN
12425 || DEFAULT_ABI == ABI_V4)
12426 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12427 "*
12428 {
12429 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12430 output_asm_insn (\"crxor 6,6,6\", operands);
12432 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12433 output_asm_insn (\"creqv 6,6,6\", operands);
12435 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12436 {
12437 gcc_assert (!TARGET_SECURE_PLT);
12438 return \"b %z0@plt\";
12439 }
12440 else
12441 return \"b %z0\";
12442 }"
12443 [(set_attr "type" "branch,branch")
12444 (set_attr "length" "4,8")])
12446 (define_expand "sibcall_value"
12447 [(parallel [(set (match_operand 0 "register_operand" "")
12448 (call (mem:SI (match_operand 1 "address_operand" ""))
12449 (match_operand 2 "" "")))
12450 (use (match_operand 3 "" ""))
12451 (use (reg:SI LR_REGNO))
12452 (return)])]
12453 ""
12454 "
12455 {
12456 #if TARGET_MACHO
12457 if (MACHOPIC_INDIRECT)
12458 operands[1] = machopic_indirect_call_target (operands[1]);
12459 #endif
12461 gcc_assert (GET_CODE (operands[1]) == MEM);
12462 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12464 operands[1] = XEXP (operands[1], 0);
12465 }")
12467 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12468 [(set (match_operand 0 "" "")
12469 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12470 (match_operand 2 "" "")))
12471 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12472 (use (reg:SI LR_REGNO))
12473 (return)]
12474 "(DEFAULT_ABI == ABI_DARWIN
12475 || DEFAULT_ABI == ABI_V4)
12476 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12477 "*
12478 {
12479 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12480 output_asm_insn (\"crxor 6,6,6\", operands);
12482 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12483 output_asm_insn (\"creqv 6,6,6\", operands);
12485 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12486 {
12487 gcc_assert (!TARGET_SECURE_PLT);
12488 return \"b %z1@plt\";
12489 }
12490 else
12491 return \"b %z1\";
12492 }"
12493 [(set_attr "type" "branch,branch")
12494 (set_attr "length" "4,8")])
12496 (define_expand "sibcall_epilogue"
12497 [(use (const_int 0))]
12498 "TARGET_SCHED_PROLOG"
12499 "
12500 {
12501 rs6000_emit_epilogue (TRUE);
12502 DONE;
12503 }")
12505 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12506 ;; all of memory. This blocks insns from being moved across this point.
12508 (define_insn "blockage"
12509 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12510 ""
12511 "")
12512 \f
12513 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
12514 ;; signed & unsigned, and one type of branch.
12515 ;;
12516 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12517 ;; insns, and branches.
12519 (define_expand "cbranch<mode>4"
12520 [(use (match_operator 0 "rs6000_cbranch_operator"
12521 [(match_operand:GPR 1 "gpc_reg_operand" "")
12522 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12523 (use (match_operand 3 ""))]
12524 ""
12525 "
12526 {
12527 /* Take care of the possibility that operands[2] might be negative but
12528 this might be a logical operation. That insn doesn't exist. */
12529 if (GET_CODE (operands[2]) == CONST_INT
12530 && INTVAL (operands[2]) < 0)
12531 {
12532 operands[2] = force_reg (<MODE>mode, operands[2]);
12533 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12534 GET_MODE (operands[0]),
12535 operands[1], operands[2]);
12536 }
12538 rs6000_emit_cbranch (<MODE>mode, operands);
12539 DONE;
12540 }")
12542 (define_expand "cbranch<mode>4"
12543 [(use (match_operator 0 "rs6000_cbranch_operator"
12544 [(match_operand:FP 1 "gpc_reg_operand" "")
12545 (match_operand:FP 2 "gpc_reg_operand" "")]))
12546 (use (match_operand 3 ""))]
12547 ""
12548 "
12549 {
12550 rs6000_emit_cbranch (<MODE>mode, operands);
12551 DONE;
12552 }")
12554 (define_expand "cstore<mode>4"
12555 [(use (match_operator 1 "rs6000_cbranch_operator"
12556 [(match_operand:GPR 2 "gpc_reg_operand" "")
12557 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12558 (clobber (match_operand:SI 0 "register_operand"))]
12559 ""
12560 "
12561 {
12562 /* Take care of the possibility that operands[3] might be negative but
12563 this might be a logical operation. That insn doesn't exist. */
12564 if (GET_CODE (operands[3]) == CONST_INT
12565 && INTVAL (operands[3]) < 0)
12566 {
12567 operands[3] = force_reg (<MODE>mode, operands[3]);
12568 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12569 GET_MODE (operands[1]),
12570 operands[2], operands[3]);
12571 }
12573 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12574 For SEQ, likewise, except that comparisons with zero should be done
12575 with an scc insns. However, due to the order that combine see the
12576 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12577 the cases we don't want to handle or are best handled by portable
12578 code. */
12579 if (GET_CODE (operands[1]) == NE)
12580 FAIL;
12581 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12582 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12583 && operands[3] == const0_rtx)
12584 FAIL;
12585 rs6000_emit_sCOND (<MODE>mode, operands);
12586 DONE;
12587 }")
12589 (define_expand "cstore<mode>4"
12590 [(use (match_operator 1 "rs6000_cbranch_operator"
12591 [(match_operand:FP 2 "gpc_reg_operand" "")
12592 (match_operand:FP 3 "gpc_reg_operand" "")]))
12593 (clobber (match_operand:SI 0 "register_operand"))]
12594 ""
12595 "
12596 {
12597 rs6000_emit_sCOND (<MODE>mode, operands);
12598 DONE;
12599 }")
12602 (define_expand "stack_protect_set"
12603 [(match_operand 0 "memory_operand" "")
12604 (match_operand 1 "memory_operand" "")]
12605 ""
12606 {
12607 #ifdef TARGET_THREAD_SSP_OFFSET
12608 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12609 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12610 operands[1] = gen_rtx_MEM (Pmode, addr);
12611 #endif
12612 if (TARGET_64BIT)
12613 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12614 else
12615 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12616 DONE;
12617 })
12619 (define_insn "stack_protect_setsi"
12620 [(set (match_operand:SI 0 "memory_operand" "=m")
12621 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12622 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12623 "TARGET_32BIT"
12624 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
12625 [(set_attr "type" "three")
12626 (set_attr "length" "12")])
12628 (define_insn "stack_protect_setdi"
12629 [(set (match_operand:DI 0 "memory_operand" "=m")
12630 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12631 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12632 "TARGET_64BIT"
12633 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
12634 [(set_attr "type" "three")
12635 (set_attr "length" "12")])
12637 (define_expand "stack_protect_test"
12638 [(match_operand 0 "memory_operand" "")
12639 (match_operand 1 "memory_operand" "")
12640 (match_operand 2 "" "")]
12641 ""
12642 {
12643 rtx test, op0, op1;
12644 #ifdef TARGET_THREAD_SSP_OFFSET
12645 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12646 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12647 operands[1] = gen_rtx_MEM (Pmode, addr);
12648 #endif
12649 op0 = operands[0];
12650 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12651 test = gen_rtx_EQ (VOIDmode, op0, op1);
12652 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12653 DONE;
12654 })
12656 (define_insn "stack_protect_testsi"
12657 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12658 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12659 (match_operand:SI 2 "memory_operand" "m,m")]
12660 UNSPEC_SP_TEST))
12661 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12662 (clobber (match_scratch:SI 3 "=&r,&r"))]
12663 "TARGET_32BIT"
12664 "@
12665 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12666 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12667 [(set_attr "length" "16,20")])
12669 (define_insn "stack_protect_testdi"
12670 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12671 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
12672 (match_operand:DI 2 "memory_operand" "m,m")]
12673 UNSPEC_SP_TEST))
12674 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12675 (clobber (match_scratch:DI 3 "=&r,&r"))]
12676 "TARGET_64BIT"
12677 "@
12678 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12679 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12680 [(set_attr "length" "16,20")])
12682 \f
12683 ;; Here are the actual compare insns.
12684 (define_insn "*cmp<mode>_internal1"
12685 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12686 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12687 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12688 ""
12689 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
12690 [(set_attr "type" "cmp")])
12692 ;; If we are comparing a register for equality with a large constant,
12693 ;; we can do this with an XOR followed by a compare. But this is profitable
12694 ;; only if the large constant is only used for the comparison (and in this
12695 ;; case we already have a register to reuse as scratch).
12696 ;;
12697 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12698 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12700 (define_peephole2
12701 [(set (match_operand:SI 0 "register_operand")
12702 (match_operand:SI 1 "logical_const_operand" ""))
12703 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12704 [(match_dup 0)
12705 (match_operand:SI 2 "logical_const_operand" "")]))
12706 (set (match_operand:CC 4 "cc_reg_operand" "")
12707 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12708 (match_dup 0)))
12709 (set (pc)
12710 (if_then_else (match_operator 6 "equality_operator"
12711 [(match_dup 4) (const_int 0)])
12712 (match_operand 7 "" "")
12713 (match_operand 8 "" "")))]
12714 "peep2_reg_dead_p (3, operands[0])
12715 && peep2_reg_dead_p (4, operands[4])"
12716 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12717 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12718 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12720 {
12721 /* Get the constant we are comparing against, and see what it looks like
12722 when sign-extended from 16 to 32 bits. Then see what constant we could
12723 XOR with SEXTC to get the sign-extended value. */
12724 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12725 SImode,
12726 operands[1], operands[2]);
12727 HOST_WIDE_INT c = INTVAL (cnst);
12728 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12729 HOST_WIDE_INT xorv = c ^ sextc;
12731 operands[9] = GEN_INT (xorv);
12732 operands[10] = GEN_INT (sextc);
12733 })
12735 (define_insn "*cmpsi_internal2"
12736 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12737 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12738 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12739 ""
12740 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
12741 [(set_attr "type" "cmp")])
12743 (define_insn "*cmpdi_internal2"
12744 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12745 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12746 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12747 ""
12748 "cmpld%I2 %0,%1,%b2"
12749 [(set_attr "type" "cmp")])
12751 ;; The following two insns don't exist as single insns, but if we provide
12752 ;; them, we can swap an add and compare, which will enable us to overlap more
12753 ;; of the required delay between a compare and branch. We generate code for
12754 ;; them by splitting.
12756 (define_insn ""
12757 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12758 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12759 (match_operand:SI 2 "short_cint_operand" "i")))
12760 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12761 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12762 ""
12763 "#"
12764 [(set_attr "length" "8")])
12766 (define_insn ""
12767 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12768 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12769 (match_operand:SI 2 "u_short_cint_operand" "i")))
12770 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12771 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12772 ""
12773 "#"
12774 [(set_attr "length" "8")])
12776 (define_split
12777 [(set (match_operand:CC 3 "cc_reg_operand" "")
12778 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12779 (match_operand:SI 2 "short_cint_operand" "")))
12780 (set (match_operand:SI 0 "gpc_reg_operand" "")
12781 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12782 ""
12783 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12784 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12786 (define_split
12787 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12788 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12789 (match_operand:SI 2 "u_short_cint_operand" "")))
12790 (set (match_operand:SI 0 "gpc_reg_operand" "")
12791 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12792 ""
12793 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12794 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12796 (define_insn "*cmpsf_internal1"
12797 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12798 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12799 (match_operand:SF 2 "gpc_reg_operand" "f")))]
12800 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
12801 "fcmpu %0,%1,%2"
12802 [(set_attr "type" "fpcompare")])
12804 (define_insn "*cmpdf_internal1"
12805 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12806 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
12807 (match_operand:DF 2 "gpc_reg_operand" "d")))]
12808 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
12809 && !VECTOR_UNIT_VSX_P (DFmode)"
12810 "fcmpu %0,%1,%2"
12811 [(set_attr "type" "fpcompare")])
12813 ;; Only need to compare second words if first words equal
12814 (define_insn "*cmptf_internal1"
12815 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12816 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12817 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12818 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12819 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12820 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12821 [(set_attr "type" "fpcompare")
12822 (set_attr "length" "12")])
12824 (define_insn_and_split "*cmptf_internal2"
12825 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12826 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12827 (match_operand:TF 2 "gpc_reg_operand" "d")))
12828 (clobber (match_scratch:DF 3 "=d"))
12829 (clobber (match_scratch:DF 4 "=d"))
12830 (clobber (match_scratch:DF 5 "=d"))
12831 (clobber (match_scratch:DF 6 "=d"))
12832 (clobber (match_scratch:DF 7 "=d"))
12833 (clobber (match_scratch:DF 8 "=d"))
12834 (clobber (match_scratch:DF 9 "=d"))
12835 (clobber (match_scratch:DF 10 "=d"))]
12836 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12837 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12838 "#"
12839 "&& reload_completed"
12840 [(set (match_dup 3) (match_dup 13))
12841 (set (match_dup 4) (match_dup 14))
12842 (set (match_dup 9) (abs:DF (match_dup 5)))
12843 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12844 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12845 (label_ref (match_dup 11))
12846 (pc)))
12847 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12848 (set (pc) (label_ref (match_dup 12)))
12849 (match_dup 11)
12850 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12851 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12852 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12853 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
12854 (match_dup 12)]
12855 {
12856 REAL_VALUE_TYPE rv;
12857 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12858 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12860 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12861 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12862 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12863 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12864 operands[11] = gen_label_rtx ();
12865 operands[12] = gen_label_rtx ();
12866 real_inf (&rv);
12867 operands[13] = force_const_mem (DFmode,
12868 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12869 operands[14] = force_const_mem (DFmode,
12870 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12871 DFmode));
12872 if (TARGET_TOC)
12873 {
12874 operands[13] = gen_const_mem (DFmode,
12875 create_TOC_reference (XEXP (operands[13], 0)));
12876 operands[14] = gen_const_mem (DFmode,
12877 create_TOC_reference (XEXP (operands[14], 0)));
12878 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12879 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12880 }
12881 })
12882 \f
12883 ;; Now we have the scc insns. We can do some combinations because of the
12884 ;; way the machine works.
12885 ;;
12886 ;; Note that this is probably faster if we can put an insn between the
12887 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12888 ;; cases the insns below which don't use an intermediate CR field will
12889 ;; be used instead.
12890 (define_insn ""
12891 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12892 (match_operator:SI 1 "scc_comparison_operator"
12893 [(match_operand 2 "cc_reg_operand" "y")
12894 (const_int 0)]))]
12895 ""
12896 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12897 [(set (attr "type")
12898 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12899 (const_string "mfcrf")
12900 ]
12901 (const_string "mfcr")))
12902 (set_attr "length" "8")])
12904 ;; Same as above, but get the GT bit.
12905 (define_insn "move_from_CR_gt_bit"
12906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12907 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12908 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12909 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12910 [(set_attr "type" "mfcr")
12911 (set_attr "length" "8")])
12913 ;; Same as above, but get the OV/ORDERED bit.
12914 (define_insn "move_from_CR_ov_bit"
12915 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12916 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12917 "TARGET_ISEL"
12918 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12919 [(set_attr "type" "mfcr")
12920 (set_attr "length" "8")])
12922 (define_insn ""
12923 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12924 (match_operator:DI 1 "scc_comparison_operator"
12925 [(match_operand 2 "cc_reg_operand" "y")
12926 (const_int 0)]))]
12927 "TARGET_POWERPC64"
12928 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12929 [(set (attr "type")
12930 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12931 (const_string "mfcrf")
12932 ]
12933 (const_string "mfcr")))
12934 (set_attr "length" "8")])
12936 (define_insn ""
12937 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12938 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12939 [(match_operand 2 "cc_reg_operand" "y,y")
12940 (const_int 0)])
12941 (const_int 0)))
12942 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12943 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12944 "TARGET_32BIT"
12945 "@
12946 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12947 #"
12948 [(set_attr "type" "delayed_compare")
12949 (set_attr "length" "8,16")])
12951 (define_split
12952 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12953 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12954 [(match_operand 2 "cc_reg_operand" "")
12955 (const_int 0)])
12956 (const_int 0)))
12957 (set (match_operand:SI 3 "gpc_reg_operand" "")
12958 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12959 "TARGET_32BIT && reload_completed"
12960 [(set (match_dup 3)
12961 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12962 (set (match_dup 0)
12963 (compare:CC (match_dup 3)
12964 (const_int 0)))]
12965 "")
12967 (define_insn ""
12968 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12969 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12970 [(match_operand 2 "cc_reg_operand" "y")
12971 (const_int 0)])
12972 (match_operand:SI 3 "const_int_operand" "n")))]
12973 ""
12974 "*
12975 {
12976 int is_bit = ccr_bit (operands[1], 1);
12977 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12978 int count;
12980 if (is_bit >= put_bit)
12981 count = is_bit - put_bit;
12982 else
12983 count = 32 - (put_bit - is_bit);
12985 operands[4] = GEN_INT (count);
12986 operands[5] = GEN_INT (put_bit);
12988 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12989 }"
12990 [(set (attr "type")
12991 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12992 (const_string "mfcrf")
12993 ]
12994 (const_string "mfcr")))
12995 (set_attr "length" "8")])
12997 (define_insn ""
12998 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12999 (compare:CC
13000 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13001 [(match_operand 2 "cc_reg_operand" "y,y")
13002 (const_int 0)])
13003 (match_operand:SI 3 "const_int_operand" "n,n"))
13004 (const_int 0)))
13005 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
13006 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13007 (match_dup 3)))]
13008 ""
13009 "*
13010 {
13011 int is_bit = ccr_bit (operands[1], 1);
13012 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13013 int count;
13015 /* Force split for non-cc0 compare. */
13016 if (which_alternative == 1)
13017 return \"#\";
13019 if (is_bit >= put_bit)
13020 count = is_bit - put_bit;
13021 else
13022 count = 32 - (put_bit - is_bit);
13024 operands[5] = GEN_INT (count);
13025 operands[6] = GEN_INT (put_bit);
13027 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
13028 }"
13029 [(set_attr "type" "delayed_compare")
13030 (set_attr "length" "8,16")])
13032 (define_split
13033 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13034 (compare:CC
13035 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13036 [(match_operand 2 "cc_reg_operand" "")
13037 (const_int 0)])
13038 (match_operand:SI 3 "const_int_operand" ""))
13039 (const_int 0)))
13040 (set (match_operand:SI 4 "gpc_reg_operand" "")
13041 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13042 (match_dup 3)))]
13043 "reload_completed"
13044 [(set (match_dup 4)
13045 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13046 (match_dup 3)))
13047 (set (match_dup 0)
13048 (compare:CC (match_dup 4)
13049 (const_int 0)))]
13050 "")
13052 ;; There is a 3 cycle delay between consecutive mfcr instructions
13053 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13055 (define_peephole
13056 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13057 (match_operator:SI 1 "scc_comparison_operator"
13058 [(match_operand 2 "cc_reg_operand" "y")
13059 (const_int 0)]))
13060 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13061 (match_operator:SI 4 "scc_comparison_operator"
13062 [(match_operand 5 "cc_reg_operand" "y")
13063 (const_int 0)]))]
13064 "REGNO (operands[2]) != REGNO (operands[5])"
13065 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13066 [(set_attr "type" "mfcr")
13067 (set_attr "length" "12")])
13069 (define_peephole
13070 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13071 (match_operator:DI 1 "scc_comparison_operator"
13072 [(match_operand 2 "cc_reg_operand" "y")
13073 (const_int 0)]))
13074 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13075 (match_operator:DI 4 "scc_comparison_operator"
13076 [(match_operand 5 "cc_reg_operand" "y")
13077 (const_int 0)]))]
13078 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13079 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13080 [(set_attr "type" "mfcr")
13081 (set_attr "length" "12")])
13083 ;; There are some scc insns that can be done directly, without a compare.
13084 ;; These are faster because they don't involve the communications between
13085 ;; the FXU and branch units. In fact, we will be replacing all of the
13086 ;; integer scc insns here or in the portable methods in emit_store_flag.
13087 ;;
13088 ;; Also support (neg (scc ..)) since that construct is used to replace
13089 ;; branches, (plus (scc ..) ..) since that construct is common and
13090 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13091 ;; cases where it is no more expensive than (neg (scc ..)).
13093 ;; Have reload force a constant into a register for the simple insns that
13094 ;; otherwise won't accept constants. We do this because it is faster than
13095 ;; the cmp/mfcr sequence we would otherwise generate.
13097 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13098 (DI "rKJI")])
13100 (define_insn_and_split "*eq<mode>"
13101 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13102 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13103 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13104 "!TARGET_POWER"
13105 "#"
13106 "!TARGET_POWER"
13107 [(set (match_dup 0)
13108 (clz:GPR (match_dup 3)))
13109 (set (match_dup 0)
13110 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13111 {
13112 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13113 {
13114 /* Use output operand as intermediate. */
13115 operands[3] = operands[0];
13117 if (logical_operand (operands[2], <MODE>mode))
13118 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13119 gen_rtx_XOR (<MODE>mode,
13120 operands[1], operands[2])));
13121 else
13122 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13123 gen_rtx_PLUS (<MODE>mode, operands[1],
13124 negate_rtx (<MODE>mode,
13125 operands[2]))));
13126 }
13127 else
13128 operands[3] = operands[1];
13130 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13131 })
13133 (define_insn_and_split "*eq<mode>_compare"
13134 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13135 (compare:CC
13136 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13137 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13138 (const_int 0)))
13139 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13140 (eq:P (match_dup 1) (match_dup 2)))]
13141 "!TARGET_POWER && optimize_size"
13142 "#"
13143 "!TARGET_POWER && optimize_size"
13144 [(set (match_dup 0)
13145 (clz:P (match_dup 4)))
13146 (parallel [(set (match_dup 3)
13147 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13148 (const_int 0)))
13149 (set (match_dup 0)
13150 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13151 {
13152 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13153 {
13154 /* Use output operand as intermediate. */
13155 operands[4] = operands[0];
13157 if (logical_operand (operands[2], <MODE>mode))
13158 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13159 gen_rtx_XOR (<MODE>mode,
13160 operands[1], operands[2])));
13161 else
13162 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13163 gen_rtx_PLUS (<MODE>mode, operands[1],
13164 negate_rtx (<MODE>mode,
13165 operands[2]))));
13166 }
13167 else
13168 operands[4] = operands[1];
13170 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13171 })
13173 (define_insn "*eqsi_power"
13174 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
13175 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13176 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
13177 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
13178 "TARGET_POWER"
13179 "@
13180 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13181 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
13182 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13183 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13184 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
13185 [(set_attr "type" "three,two,three,three,three")
13186 (set_attr "length" "12,8,12,12,12")])
13188 ;; We have insns of the form shown by the first define_insn below. If
13189 ;; there is something inside the comparison operation, we must split it.
13190 (define_split
13191 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13192 (plus:SI (match_operator 1 "comparison_operator"
13193 [(match_operand:SI 2 "" "")
13194 (match_operand:SI 3
13195 "reg_or_cint_operand" "")])
13196 (match_operand:SI 4 "gpc_reg_operand" "")))
13197 (clobber (match_operand:SI 5 "register_operand" ""))]
13198 "! gpc_reg_operand (operands[2], SImode)"
13199 [(set (match_dup 5) (match_dup 2))
13200 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
13201 (match_dup 4)))])
13203 (define_insn "*plus_eqsi"
13204 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13205 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13206 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13207 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13208 "TARGET_32BIT"
13209 "@
13210 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13211 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
13212 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13213 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13214 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13215 [(set_attr "type" "three,two,three,three,three")
13216 (set_attr "length" "12,8,12,12,12")])
13218 (define_insn "*compare_plus_eqsi"
13219 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13220 (compare:CC
13221 (plus:SI
13222 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13223 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13224 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13225 (const_int 0)))
13226 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13227 "TARGET_32BIT && optimize_size"
13228 "@
13229 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13230 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
13231 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13232 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13233 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13234 #
13235 #
13236 #
13237 #
13238 #"
13239 [(set_attr "type" "compare")
13240 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13242 (define_split
13243 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13244 (compare:CC
13245 (plus:SI
13246 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13247 (match_operand:SI 2 "scc_eq_operand" ""))
13248 (match_operand:SI 3 "gpc_reg_operand" ""))
13249 (const_int 0)))
13250 (clobber (match_scratch:SI 4 ""))]
13251 "TARGET_32BIT && optimize_size && reload_completed"
13252 [(set (match_dup 4)
13253 (plus:SI (eq:SI (match_dup 1)
13254 (match_dup 2))
13255 (match_dup 3)))
13256 (set (match_dup 0)
13257 (compare:CC (match_dup 4)
13258 (const_int 0)))]
13259 "")
13261 (define_insn "*plus_eqsi_compare"
13262 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13263 (compare:CC
13264 (plus:SI
13265 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13266 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13267 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13268 (const_int 0)))
13269 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13270 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13271 "TARGET_32BIT && optimize_size"
13272 "@
13273 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13274 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
13275 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13276 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13277 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13278 #
13279 #
13280 #
13281 #
13282 #"
13283 [(set_attr "type" "compare")
13284 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13286 (define_split
13287 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13288 (compare:CC
13289 (plus:SI
13290 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13291 (match_operand:SI 2 "scc_eq_operand" ""))
13292 (match_operand:SI 3 "gpc_reg_operand" ""))
13293 (const_int 0)))
13294 (set (match_operand:SI 0 "gpc_reg_operand" "")
13295 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13296 "TARGET_32BIT && optimize_size && reload_completed"
13297 [(set (match_dup 0)
13298 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13299 (set (match_dup 4)
13300 (compare:CC (match_dup 0)
13301 (const_int 0)))]
13302 "")
13304 (define_insn "*neg_eq0<mode>"
13305 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13306 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13307 (const_int 0))))]
13308 ""
13309 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
13310 [(set_attr "type" "two")
13311 (set_attr "length" "8")])
13313 (define_insn_and_split "*neg_eq<mode>"
13314 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13315 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13316 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13317 ""
13318 "#"
13319 ""
13320 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13321 {
13322 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13323 {
13324 /* Use output operand as intermediate. */
13325 operands[3] = operands[0];
13327 if (logical_operand (operands[2], <MODE>mode))
13328 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13329 gen_rtx_XOR (<MODE>mode,
13330 operands[1], operands[2])));
13331 else
13332 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13333 gen_rtx_PLUS (<MODE>mode, operands[1],
13334 negate_rtx (<MODE>mode,
13335 operands[2]))));
13336 }
13337 else
13338 operands[3] = operands[1];
13339 })
13341 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
13342 ;; since it nabs/sr is just as fast.
13343 (define_insn "*ne0si"
13344 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13345 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13346 (const_int 31)))
13347 (clobber (match_scratch:SI 2 "=&r"))]
13348 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
13349 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
13350 [(set_attr "type" "two")
13351 (set_attr "length" "8")])
13353 (define_insn "*ne0di"
13354 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13355 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13356 (const_int 63)))
13357 (clobber (match_scratch:DI 2 "=&r"))]
13358 "TARGET_64BIT"
13359 "addic %2,%1,-1\;subfe %0,%2,%1"
13360 [(set_attr "type" "two")
13361 (set_attr "length" "8")])
13363 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
13364 (define_insn "*plus_ne0si"
13365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13366 (plus:SI (lshiftrt:SI
13367 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13368 (const_int 31))
13369 (match_operand:SI 2 "gpc_reg_operand" "r")))
13370 (clobber (match_scratch:SI 3 "=&r"))]
13371 "TARGET_32BIT"
13372 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
13373 [(set_attr "type" "two")
13374 (set_attr "length" "8")])
13376 (define_insn "*plus_ne0di"
13377 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13378 (plus:DI (lshiftrt:DI
13379 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13380 (const_int 63))
13381 (match_operand:DI 2 "gpc_reg_operand" "r")))
13382 (clobber (match_scratch:DI 3 "=&r"))]
13383 "TARGET_64BIT"
13384 "addic %3,%1,-1\;addze %0,%2"
13385 [(set_attr "type" "two")
13386 (set_attr "length" "8")])
13388 (define_insn "*compare_plus_ne0si"
13389 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13390 (compare:CC
13391 (plus:SI (lshiftrt:SI
13392 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13393 (const_int 31))
13394 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13395 (const_int 0)))
13396 (clobber (match_scratch:SI 3 "=&r,&r"))
13397 (clobber (match_scratch:SI 4 "=X,&r"))]
13398 "TARGET_32BIT"
13399 "@
13400 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
13401 #"
13402 [(set_attr "type" "compare")
13403 (set_attr "length" "8,12")])
13405 (define_split
13406 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13407 (compare:CC
13408 (plus:SI (lshiftrt:SI
13409 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13410 (const_int 31))
13411 (match_operand:SI 2 "gpc_reg_operand" ""))
13412 (const_int 0)))
13413 (clobber (match_scratch:SI 3 ""))
13414 (clobber (match_scratch:SI 4 ""))]
13415 "TARGET_32BIT && reload_completed"
13416 [(parallel [(set (match_dup 3)
13417 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
13418 (const_int 31))
13419 (match_dup 2)))
13420 (clobber (match_dup 4))])
13421 (set (match_dup 0)
13422 (compare:CC (match_dup 3)
13423 (const_int 0)))]
13424 "")
13426 (define_insn "*compare_plus_ne0di"
13427 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13428 (compare:CC
13429 (plus:DI (lshiftrt:DI
13430 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13431 (const_int 63))
13432 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13433 (const_int 0)))
13434 (clobber (match_scratch:DI 3 "=&r,&r"))]
13435 "TARGET_64BIT"
13436 "@
13437 addic %3,%1,-1\;addze. %3,%2
13438 #"
13439 [(set_attr "type" "compare")
13440 (set_attr "length" "8,12")])
13442 (define_split
13443 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13444 (compare:CC
13445 (plus:DI (lshiftrt:DI
13446 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13447 (const_int 63))
13448 (match_operand:DI 2 "gpc_reg_operand" ""))
13449 (const_int 0)))
13450 (clobber (match_scratch:DI 3 ""))]
13451 "TARGET_64BIT && reload_completed"
13452 [(set (match_dup 3)
13453 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
13454 (const_int 63))
13455 (match_dup 2)))
13456 (set (match_dup 0)
13457 (compare:CC (match_dup 3)
13458 (const_int 0)))]
13459 "")
13461 (define_insn "*plus_ne0si_compare"
13462 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13463 (compare:CC
13464 (plus:SI (lshiftrt:SI
13465 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13466 (const_int 31))
13467 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13468 (const_int 0)))
13469 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13470 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13471 (match_dup 2)))
13472 (clobber (match_scratch:SI 3 "=&r,&r"))]
13473 "TARGET_32BIT"
13474 "@
13475 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
13476 #"
13477 [(set_attr "type" "compare")
13478 (set_attr "length" "8,12")])
13480 (define_split
13481 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13482 (compare:CC
13483 (plus:SI (lshiftrt:SI
13484 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13485 (const_int 31))
13486 (match_operand:SI 2 "gpc_reg_operand" ""))
13487 (const_int 0)))
13488 (set (match_operand:SI 0 "gpc_reg_operand" "")
13489 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13490 (match_dup 2)))
13491 (clobber (match_scratch:SI 3 ""))]
13492 "TARGET_32BIT && reload_completed"
13493 [(parallel [(set (match_dup 0)
13494 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13495 (match_dup 2)))
13496 (clobber (match_dup 3))])
13497 (set (match_dup 4)
13498 (compare:CC (match_dup 0)
13499 (const_int 0)))]
13500 "")
13502 (define_insn "*plus_ne0di_compare"
13503 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13504 (compare:CC
13505 (plus:DI (lshiftrt:DI
13506 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13507 (const_int 63))
13508 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13509 (const_int 0)))
13510 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13511 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13512 (match_dup 2)))
13513 (clobber (match_scratch:DI 3 "=&r,&r"))]
13514 "TARGET_64BIT"
13515 "@
13516 addic %3,%1,-1\;addze. %0,%2
13517 #"
13518 [(set_attr "type" "compare")
13519 (set_attr "length" "8,12")])
13521 (define_split
13522 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13523 (compare:CC
13524 (plus:DI (lshiftrt:DI
13525 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13526 (const_int 63))
13527 (match_operand:DI 2 "gpc_reg_operand" ""))
13528 (const_int 0)))
13529 (set (match_operand:DI 0 "gpc_reg_operand" "")
13530 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13531 (match_dup 2)))
13532 (clobber (match_scratch:DI 3 ""))]
13533 "TARGET_64BIT && reload_completed"
13534 [(parallel [(set (match_dup 0)
13535 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13536 (match_dup 2)))
13537 (clobber (match_dup 3))])
13538 (set (match_dup 4)
13539 (compare:CC (match_dup 0)
13540 (const_int 0)))]
13541 "")
13543 (define_insn ""
13544 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13545 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13546 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
13547 (clobber (match_scratch:SI 3 "=r,X"))]
13548 "TARGET_POWER"
13549 "@
13550 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
13551 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
13552 [(set_attr "length" "12")])
13554 (define_insn ""
13555 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13556 (compare:CC
13557 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13558 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13559 (const_int 0)))
13560 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
13561 (le:SI (match_dup 1) (match_dup 2)))
13562 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
13563 "TARGET_POWER"
13564 "@
13565 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13566 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
13567 #
13568 #"
13569 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
13570 (set_attr "length" "12,12,16,16")])
13572 (define_split
13573 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13574 (compare:CC
13575 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13576 (match_operand:SI 2 "reg_or_short_operand" ""))
13577 (const_int 0)))
13578 (set (match_operand:SI 0 "gpc_reg_operand" "")
13579 (le:SI (match_dup 1) (match_dup 2)))
13580 (clobber (match_scratch:SI 3 ""))]
13581 "TARGET_POWER && reload_completed"
13582 [(parallel [(set (match_dup 0)
13583 (le:SI (match_dup 1) (match_dup 2)))
13584 (clobber (match_dup 3))])
13585 (set (match_dup 4)
13586 (compare:CC (match_dup 0)
13587 (const_int 0)))]
13588 "")
13590 (define_insn ""
13591 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13592 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13593 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
13594 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13595 "TARGET_POWER"
13596 "@
13597 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13598 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
13599 [(set_attr "length" "12")])
13601 (define_insn ""
13602 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13603 (compare:CC
13604 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13605 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13606 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13607 (const_int 0)))
13608 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13609 "TARGET_POWER"
13610 "@
13611 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13612 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
13613 #
13614 #"
13615 [(set_attr "type" "compare")
13616 (set_attr "length" "12,12,16,16")])
13618 (define_split
13619 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13620 (compare:CC
13621 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13622 (match_operand:SI 2 "reg_or_short_operand" ""))
13623 (match_operand:SI 3 "gpc_reg_operand" ""))
13624 (const_int 0)))
13625 (clobber (match_scratch:SI 4 ""))]
13626 "TARGET_POWER && reload_completed"
13627 [(set (match_dup 4)
13628 (plus:SI (le:SI (match_dup 1) (match_dup 2))
13629 (match_dup 3)))
13630 (set (match_dup 0)
13631 (compare:CC (match_dup 4)
13632 (const_int 0)))]
13633 "")
13635 (define_insn ""
13636 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13637 (compare:CC
13638 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13639 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13640 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13641 (const_int 0)))
13642 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13643 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13644 "TARGET_POWER"
13645 "@
13646 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13647 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
13648 #
13649 #"
13650 [(set_attr "type" "compare")
13651 (set_attr "length" "12,12,16,16")])
13653 (define_split
13654 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13655 (compare:CC
13656 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13657 (match_operand:SI 2 "reg_or_short_operand" ""))
13658 (match_operand:SI 3 "gpc_reg_operand" ""))
13659 (const_int 0)))
13660 (set (match_operand:SI 0 "gpc_reg_operand" "")
13661 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13662 "TARGET_POWER && reload_completed"
13663 [(set (match_dup 0)
13664 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13665 (set (match_dup 4)
13666 (compare:CC (match_dup 0)
13667 (const_int 0)))]
13668 "")
13670 (define_insn ""
13671 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13672 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13673 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
13674 "TARGET_POWER"
13675 "@
13676 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
13677 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
13678 [(set_attr "length" "12")])
13680 (define_insn "*leu<mode>"
13681 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13682 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13683 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13684 ""
13685 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13686 [(set_attr "type" "three")
13687 (set_attr "length" "12")])
13689 (define_insn "*leu<mode>_compare"
13690 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13691 (compare:CC
13692 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13693 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13694 (const_int 0)))
13695 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13696 (leu:P (match_dup 1) (match_dup 2)))]
13697 ""
13698 "@
13699 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13700 #"
13701 [(set_attr "type" "compare")
13702 (set_attr "length" "12,16")])
13704 (define_split
13705 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13706 (compare:CC
13707 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13708 (match_operand:P 2 "reg_or_short_operand" ""))
13709 (const_int 0)))
13710 (set (match_operand:P 0 "gpc_reg_operand" "")
13711 (leu:P (match_dup 1) (match_dup 2)))]
13712 "reload_completed"
13713 [(set (match_dup 0)
13714 (leu:P (match_dup 1) (match_dup 2)))
13715 (set (match_dup 3)
13716 (compare:CC (match_dup 0)
13717 (const_int 0)))]
13718 "")
13720 (define_insn "*plus_leu<mode>"
13721 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13722 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13723 (match_operand:P 2 "reg_or_short_operand" "rI"))
13724 (match_operand:P 3 "gpc_reg_operand" "r")))]
13725 ""
13726 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
13727 [(set_attr "type" "two")
13728 (set_attr "length" "8")])
13730 (define_insn ""
13731 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13732 (compare:CC
13733 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13734 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13735 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13736 (const_int 0)))
13737 (clobber (match_scratch:SI 4 "=&r,&r"))]
13738 "TARGET_32BIT"
13739 "@
13740 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
13741 #"
13742 [(set_attr "type" "compare")
13743 (set_attr "length" "8,12")])
13745 (define_split
13746 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13747 (compare:CC
13748 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13749 (match_operand:SI 2 "reg_or_short_operand" ""))
13750 (match_operand:SI 3 "gpc_reg_operand" ""))
13751 (const_int 0)))
13752 (clobber (match_scratch:SI 4 ""))]
13753 "TARGET_32BIT && reload_completed"
13754 [(set (match_dup 4)
13755 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13756 (match_dup 3)))
13757 (set (match_dup 0)
13758 (compare:CC (match_dup 4)
13759 (const_int 0)))]
13760 "")
13762 (define_insn ""
13763 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13764 (compare:CC
13765 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13766 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13767 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13768 (const_int 0)))
13769 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13770 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13771 "TARGET_32BIT"
13772 "@
13773 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
13774 #"
13775 [(set_attr "type" "compare")
13776 (set_attr "length" "8,12")])
13778 (define_split
13779 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13780 (compare:CC
13781 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13782 (match_operand:SI 2 "reg_or_short_operand" ""))
13783 (match_operand:SI 3 "gpc_reg_operand" ""))
13784 (const_int 0)))
13785 (set (match_operand:SI 0 "gpc_reg_operand" "")
13786 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13787 "TARGET_32BIT && reload_completed"
13788 [(set (match_dup 0)
13789 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13790 (set (match_dup 4)
13791 (compare:CC (match_dup 0)
13792 (const_int 0)))]
13793 "")
13795 (define_insn "*neg_leu<mode>"
13796 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13797 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13798 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13799 ""
13800 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
13801 [(set_attr "type" "three")
13802 (set_attr "length" "12")])
13804 (define_insn "*and_neg_leu<mode>"
13805 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13806 (and:P (neg:P
13807 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13808 (match_operand:P 2 "reg_or_short_operand" "rI")))
13809 (match_operand:P 3 "gpc_reg_operand" "r")))]
13810 ""
13811 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13812 [(set_attr "type" "three")
13813 (set_attr "length" "12")])
13815 (define_insn ""
13816 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13817 (compare:CC
13818 (and:SI (neg:SI
13819 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13820 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13821 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13822 (const_int 0)))
13823 (clobber (match_scratch:SI 4 "=&r,&r"))]
13824 "TARGET_32BIT"
13825 "@
13826 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13827 #"
13828 [(set_attr "type" "compare")
13829 (set_attr "length" "12,16")])
13831 (define_split
13832 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13833 (compare:CC
13834 (and:SI (neg:SI
13835 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13836 (match_operand:SI 2 "reg_or_short_operand" "")))
13837 (match_operand:SI 3 "gpc_reg_operand" ""))
13838 (const_int 0)))
13839 (clobber (match_scratch:SI 4 ""))]
13840 "TARGET_32BIT && reload_completed"
13841 [(set (match_dup 4)
13842 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13843 (match_dup 3)))
13844 (set (match_dup 0)
13845 (compare:CC (match_dup 4)
13846 (const_int 0)))]
13847 "")
13849 (define_insn ""
13850 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13851 (compare:CC
13852 (and:SI (neg:SI
13853 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13854 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13855 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13856 (const_int 0)))
13857 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13858 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13859 "TARGET_32BIT"
13860 "@
13861 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13862 #"
13863 [(set_attr "type" "compare")
13864 (set_attr "length" "12,16")])
13866 (define_split
13867 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13868 (compare:CC
13869 (and:SI (neg:SI
13870 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13871 (match_operand:SI 2 "reg_or_short_operand" "")))
13872 (match_operand:SI 3 "gpc_reg_operand" ""))
13873 (const_int 0)))
13874 (set (match_operand:SI 0 "gpc_reg_operand" "")
13875 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13876 "TARGET_32BIT && reload_completed"
13877 [(set (match_dup 0)
13878 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13879 (match_dup 3)))
13880 (set (match_dup 4)
13881 (compare:CC (match_dup 0)
13882 (const_int 0)))]
13883 "")
13885 (define_insn ""
13886 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13887 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13888 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13889 "TARGET_POWER"
13890 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13891 [(set_attr "length" "12")])
13893 (define_insn ""
13894 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13895 (compare:CC
13896 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13897 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13898 (const_int 0)))
13899 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13900 (lt:SI (match_dup 1) (match_dup 2)))]
13901 "TARGET_POWER"
13902 "@
13903 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13904 #"
13905 [(set_attr "type" "delayed_compare")
13906 (set_attr "length" "12,16")])
13908 (define_split
13909 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13910 (compare:CC
13911 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13912 (match_operand:SI 2 "reg_or_short_operand" ""))
13913 (const_int 0)))
13914 (set (match_operand:SI 0 "gpc_reg_operand" "")
13915 (lt:SI (match_dup 1) (match_dup 2)))]
13916 "TARGET_POWER && reload_completed"
13917 [(set (match_dup 0)
13918 (lt:SI (match_dup 1) (match_dup 2)))
13919 (set (match_dup 3)
13920 (compare:CC (match_dup 0)
13921 (const_int 0)))]
13922 "")
13924 (define_insn ""
13925 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13926 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13927 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13928 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13929 "TARGET_POWER"
13930 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13931 [(set_attr "length" "12")])
13933 (define_insn ""
13934 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13935 (compare:CC
13936 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13937 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13938 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13939 (const_int 0)))
13940 (clobber (match_scratch:SI 4 "=&r,&r"))]
13941 "TARGET_POWER"
13942 "@
13943 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13944 #"
13945 [(set_attr "type" "compare")
13946 (set_attr "length" "12,16")])
13948 (define_split
13949 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13950 (compare:CC
13951 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13952 (match_operand:SI 2 "reg_or_short_operand" ""))
13953 (match_operand:SI 3 "gpc_reg_operand" ""))
13954 (const_int 0)))
13955 (clobber (match_scratch:SI 4 ""))]
13956 "TARGET_POWER && reload_completed"
13957 [(set (match_dup 4)
13958 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13959 (match_dup 3)))
13960 (set (match_dup 0)
13961 (compare:CC (match_dup 4)
13962 (const_int 0)))]
13963 "")
13965 (define_insn ""
13966 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13967 (compare:CC
13968 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13969 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13970 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13971 (const_int 0)))
13972 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13973 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13974 "TARGET_POWER"
13975 "@
13976 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13977 #"
13978 [(set_attr "type" "compare")
13979 (set_attr "length" "12,16")])
13981 (define_split
13982 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13983 (compare:CC
13984 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13985 (match_operand:SI 2 "reg_or_short_operand" ""))
13986 (match_operand:SI 3 "gpc_reg_operand" ""))
13987 (const_int 0)))
13988 (set (match_operand:SI 0 "gpc_reg_operand" "")
13989 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13990 "TARGET_POWER && reload_completed"
13991 [(set (match_dup 0)
13992 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13993 (set (match_dup 4)
13994 (compare:CC (match_dup 0)
13995 (const_int 0)))]
13996 "")
13998 (define_insn ""
13999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14000 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14001 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14002 "TARGET_POWER"
14003 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14004 [(set_attr "length" "12")])
14006 (define_insn_and_split "*ltu<mode>"
14007 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14008 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14009 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14010 ""
14011 "#"
14012 ""
14013 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14014 (set (match_dup 0) (neg:P (match_dup 0)))]
14015 "")
14017 (define_insn_and_split "*ltu<mode>_compare"
14018 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14019 (compare:CC
14020 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14021 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14022 (const_int 0)))
14023 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14024 (ltu:P (match_dup 1) (match_dup 2)))]
14025 ""
14026 "#"
14027 ""
14028 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14029 (parallel [(set (match_dup 3)
14030 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14031 (set (match_dup 0) (neg:P (match_dup 0)))])]
14032 "")
14034 (define_insn_and_split "*plus_ltu<mode>"
14035 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
14036 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14037 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14038 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
14039 ""
14040 "#"
14041 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14042 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14043 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14044 "")
14046 (define_insn_and_split "*plus_ltu<mode>_compare"
14047 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14048 (compare:CC
14049 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14050 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14051 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14052 (const_int 0)))
14053 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14054 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14055 ""
14056 "#"
14057 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14058 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14059 (parallel [(set (match_dup 4)
14060 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14061 (const_int 0)))
14062 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14063 "")
14065 (define_insn "*neg_ltu<mode>"
14066 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14067 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14068 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14069 ""
14070 "@
14071 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
14072 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
14073 [(set_attr "type" "two")
14074 (set_attr "length" "8")])
14076 (define_insn ""
14077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14078 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14079 (match_operand:SI 2 "reg_or_short_operand" "rI")))
14080 (clobber (match_scratch:SI 3 "=r"))]
14081 "TARGET_POWER"
14082 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
14083 [(set_attr "length" "12")])
14085 (define_insn ""
14086 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14087 (compare:CC
14088 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14089 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14090 (const_int 0)))
14091 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14092 (ge:SI (match_dup 1) (match_dup 2)))
14093 (clobber (match_scratch:SI 3 "=r,r"))]
14094 "TARGET_POWER"
14095 "@
14096 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14097 #"
14098 [(set_attr "type" "compare")
14099 (set_attr "length" "12,16")])
14101 (define_split
14102 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14103 (compare:CC
14104 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14105 (match_operand:SI 2 "reg_or_short_operand" ""))
14106 (const_int 0)))
14107 (set (match_operand:SI 0 "gpc_reg_operand" "")
14108 (ge:SI (match_dup 1) (match_dup 2)))
14109 (clobber (match_scratch:SI 3 ""))]
14110 "TARGET_POWER && reload_completed"
14111 [(parallel [(set (match_dup 0)
14112 (ge:SI (match_dup 1) (match_dup 2)))
14113 (clobber (match_dup 3))])
14114 (set (match_dup 4)
14115 (compare:CC (match_dup 0)
14116 (const_int 0)))]
14117 "")
14119 (define_insn ""
14120 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14121 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14122 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14123 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14124 "TARGET_POWER"
14125 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
14126 [(set_attr "length" "12")])
14128 (define_insn ""
14129 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14130 (compare:CC
14131 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14132 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14133 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14134 (const_int 0)))
14135 (clobber (match_scratch:SI 4 "=&r,&r"))]
14136 "TARGET_POWER"
14137 "@
14138 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14139 #"
14140 [(set_attr "type" "compare")
14141 (set_attr "length" "12,16")])
14143 (define_split
14144 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14145 (compare:CC
14146 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14147 (match_operand:SI 2 "reg_or_short_operand" ""))
14148 (match_operand:SI 3 "gpc_reg_operand" ""))
14149 (const_int 0)))
14150 (clobber (match_scratch:SI 4 ""))]
14151 "TARGET_POWER && reload_completed"
14152 [(set (match_dup 4)
14153 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
14154 (match_dup 3)))
14155 (set (match_dup 0)
14156 (compare:CC (match_dup 4)
14157 (const_int 0)))]
14158 "")
14160 (define_insn ""
14161 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14162 (compare:CC
14163 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14164 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14165 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14166 (const_int 0)))
14167 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14168 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14169 "TARGET_POWER"
14170 "@
14171 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14172 #"
14173 [(set_attr "type" "compare")
14174 (set_attr "length" "12,16")])
14176 (define_split
14177 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14178 (compare:CC
14179 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14180 (match_operand:SI 2 "reg_or_short_operand" ""))
14181 (match_operand:SI 3 "gpc_reg_operand" ""))
14182 (const_int 0)))
14183 (set (match_operand:SI 0 "gpc_reg_operand" "")
14184 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14185 "TARGET_POWER && reload_completed"
14186 [(set (match_dup 0)
14187 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14188 (set (match_dup 4)
14189 (compare:CC (match_dup 0)
14190 (const_int 0)))]
14191 "")
14193 (define_insn ""
14194 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14195 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14196 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14197 "TARGET_POWER"
14198 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
14199 [(set_attr "length" "12")])
14201 (define_insn "*geu<mode>"
14202 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14203 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14204 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14205 ""
14206 "@
14207 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
14208 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14209 [(set_attr "type" "three")
14210 (set_attr "length" "12")])
14212 (define_insn "*geu<mode>_compare"
14213 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14214 (compare:CC
14215 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14216 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14217 (const_int 0)))
14218 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14219 (geu:P (match_dup 1) (match_dup 2)))]
14220 ""
14221 "@
14222 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14223 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14224 #
14225 #"
14226 [(set_attr "type" "compare")
14227 (set_attr "length" "12,12,16,16")])
14229 (define_split
14230 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14231 (compare:CC
14232 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14233 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14234 (const_int 0)))
14235 (set (match_operand:P 0 "gpc_reg_operand" "")
14236 (geu:P (match_dup 1) (match_dup 2)))]
14237 "reload_completed"
14238 [(set (match_dup 0)
14239 (geu:P (match_dup 1) (match_dup 2)))
14240 (set (match_dup 3)
14241 (compare:CC (match_dup 0)
14242 (const_int 0)))]
14243 "")
14245 (define_insn "*plus_geu<mode>"
14246 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14247 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14248 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14249 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14250 ""
14251 "@
14252 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
14253 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
14254 [(set_attr "type" "two")
14255 (set_attr "length" "8")])
14257 (define_insn ""
14258 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14259 (compare:CC
14260 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14261 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14262 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14263 (const_int 0)))
14264 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14265 "TARGET_32BIT"
14266 "@
14267 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
14268 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
14269 #
14270 #"
14271 [(set_attr "type" "compare")
14272 (set_attr "length" "8,8,12,12")])
14274 (define_split
14275 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14276 (compare:CC
14277 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14278 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14279 (match_operand:SI 3 "gpc_reg_operand" ""))
14280 (const_int 0)))
14281 (clobber (match_scratch:SI 4 ""))]
14282 "TARGET_32BIT && reload_completed"
14283 [(set (match_dup 4)
14284 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14285 (match_dup 3)))
14286 (set (match_dup 0)
14287 (compare:CC (match_dup 4)
14288 (const_int 0)))]
14289 "")
14291 (define_insn ""
14292 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14293 (compare:CC
14294 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14295 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14296 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14297 (const_int 0)))
14298 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14299 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14300 "TARGET_32BIT"
14301 "@
14302 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
14303 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
14304 #
14305 #"
14306 [(set_attr "type" "compare")
14307 (set_attr "length" "8,8,12,12")])
14309 (define_split
14310 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14311 (compare:CC
14312 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14313 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14314 (match_operand:SI 3 "gpc_reg_operand" ""))
14315 (const_int 0)))
14316 (set (match_operand:SI 0 "gpc_reg_operand" "")
14317 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14318 "TARGET_32BIT && reload_completed"
14319 [(set (match_dup 0)
14320 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14321 (set (match_dup 4)
14322 (compare:CC (match_dup 0)
14323 (const_int 0)))]
14324 "")
14326 (define_insn "*neg_geu<mode>"
14327 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14328 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14329 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14330 ""
14331 "@
14332 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
14333 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
14334 [(set_attr "type" "three")
14335 (set_attr "length" "12")])
14337 (define_insn "*and_neg_geu<mode>"
14338 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14339 (and:P (neg:P
14340 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14341 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14342 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14343 ""
14344 "@
14345 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
14346 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14347 [(set_attr "type" "three")
14348 (set_attr "length" "12")])
14350 (define_insn ""
14351 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14352 (compare:CC
14353 (and:SI (neg:SI
14354 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14355 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14356 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14357 (const_int 0)))
14358 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14359 "TARGET_32BIT"
14360 "@
14361 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14362 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14363 #
14364 #"
14365 [(set_attr "type" "compare")
14366 (set_attr "length" "12,12,16,16")])
14368 (define_split
14369 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14370 (compare:CC
14371 (and:SI (neg:SI
14372 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14373 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14374 (match_operand:SI 3 "gpc_reg_operand" ""))
14375 (const_int 0)))
14376 (clobber (match_scratch:SI 4 ""))]
14377 "TARGET_32BIT && reload_completed"
14378 [(set (match_dup 4)
14379 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14380 (match_dup 3)))
14381 (set (match_dup 0)
14382 (compare:CC (match_dup 4)
14383 (const_int 0)))]
14384 "")
14386 (define_insn ""
14387 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14388 (compare:CC
14389 (and:SI (neg:SI
14390 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14391 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14392 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14393 (const_int 0)))
14394 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14395 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14396 "TARGET_32BIT"
14397 "@
14398 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14399 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14400 #
14401 #"
14402 [(set_attr "type" "compare")
14403 (set_attr "length" "12,12,16,16")])
14405 (define_split
14406 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14407 (compare:CC
14408 (and:SI (neg:SI
14409 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14410 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14411 (match_operand:SI 3 "gpc_reg_operand" ""))
14412 (const_int 0)))
14413 (set (match_operand:SI 0 "gpc_reg_operand" "")
14414 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14415 "TARGET_32BIT && reload_completed"
14416 [(set (match_dup 0)
14417 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
14418 (set (match_dup 4)
14419 (compare:CC (match_dup 0)
14420 (const_int 0)))]
14421 "")
14423 (define_insn ""
14424 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14425 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14426 (match_operand:SI 2 "reg_or_short_operand" "r")))]
14427 "TARGET_POWER"
14428 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14429 [(set_attr "length" "12")])
14431 (define_insn ""
14432 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14433 (compare:CC
14434 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14435 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14436 (const_int 0)))
14437 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14438 (gt:SI (match_dup 1) (match_dup 2)))]
14439 "TARGET_POWER"
14440 "@
14441 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14442 #"
14443 [(set_attr "type" "delayed_compare")
14444 (set_attr "length" "12,16")])
14446 (define_split
14447 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14448 (compare:CC
14449 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14450 (match_operand:SI 2 "reg_or_short_operand" ""))
14451 (const_int 0)))
14452 (set (match_operand:SI 0 "gpc_reg_operand" "")
14453 (gt:SI (match_dup 1) (match_dup 2)))]
14454 "TARGET_POWER && reload_completed"
14455 [(set (match_dup 0)
14456 (gt:SI (match_dup 1) (match_dup 2)))
14457 (set (match_dup 3)
14458 (compare:CC (match_dup 0)
14459 (const_int 0)))]
14460 "")
14462 (define_insn "*plus_gt0<mode>"
14463 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14464 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
14465 (const_int 0))
14466 (match_operand:P 2 "gpc_reg_operand" "r")))]
14467 ""
14468 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
14469 [(set_attr "type" "three")
14470 (set_attr "length" "12")])
14472 (define_insn ""
14473 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14474 (compare:CC
14475 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14476 (const_int 0))
14477 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14478 (const_int 0)))
14479 (clobber (match_scratch:SI 3 "=&r,&r"))]
14480 "TARGET_32BIT"
14481 "@
14482 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
14483 #"
14484 [(set_attr "type" "compare")
14485 (set_attr "length" "12,16")])
14487 (define_split
14488 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14489 (compare:CC
14490 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14491 (const_int 0))
14492 (match_operand:SI 2 "gpc_reg_operand" ""))
14493 (const_int 0)))
14494 (clobber (match_scratch:SI 3 ""))]
14495 "TARGET_32BIT && reload_completed"
14496 [(set (match_dup 3)
14497 (plus:SI (gt:SI (match_dup 1) (const_int 0))
14498 (match_dup 2)))
14499 (set (match_dup 0)
14500 (compare:CC (match_dup 3)
14501 (const_int 0)))]
14502 "")
14504 (define_insn ""
14505 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14506 (compare:CC
14507 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14508 (const_int 0))
14509 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14510 (const_int 0)))
14511 (clobber (match_scratch:DI 3 "=&r,&r"))]
14512 "TARGET_64BIT"
14513 "@
14514 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14515 #"
14516 [(set_attr "type" "compare")
14517 (set_attr "length" "12,16")])
14519 (define_split
14520 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14521 (compare:CC
14522 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14523 (const_int 0))
14524 (match_operand:DI 2 "gpc_reg_operand" ""))
14525 (const_int 0)))
14526 (clobber (match_scratch:DI 3 ""))]
14527 "TARGET_64BIT && reload_completed"
14528 [(set (match_dup 3)
14529 (plus:DI (gt:DI (match_dup 1) (const_int 0))
14530 (match_dup 2)))
14531 (set (match_dup 0)
14532 (compare:CC (match_dup 3)
14533 (const_int 0)))]
14534 "")
14536 (define_insn ""
14537 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14538 (compare:CC
14539 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14540 (const_int 0))
14541 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14542 (const_int 0)))
14543 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14544 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14545 "TARGET_32BIT"
14546 "@
14547 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
14548 #"
14549 [(set_attr "type" "compare")
14550 (set_attr "length" "12,16")])
14552 (define_split
14553 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14554 (compare:CC
14555 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14556 (const_int 0))
14557 (match_operand:SI 2 "gpc_reg_operand" ""))
14558 (const_int 0)))
14559 (set (match_operand:SI 0 "gpc_reg_operand" "")
14560 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14561 "TARGET_32BIT && reload_completed"
14562 [(set (match_dup 0)
14563 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14564 (set (match_dup 3)
14565 (compare:CC (match_dup 0)
14566 (const_int 0)))]
14567 "")
14569 (define_insn ""
14570 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14571 (compare:CC
14572 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14573 (const_int 0))
14574 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14575 (const_int 0)))
14576 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14577 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14578 "TARGET_64BIT"
14579 "@
14580 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14581 #"
14582 [(set_attr "type" "compare")
14583 (set_attr "length" "12,16")])
14585 (define_split
14586 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14587 (compare:CC
14588 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14589 (const_int 0))
14590 (match_operand:DI 2 "gpc_reg_operand" ""))
14591 (const_int 0)))
14592 (set (match_operand:DI 0 "gpc_reg_operand" "")
14593 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14594 "TARGET_64BIT && reload_completed"
14595 [(set (match_dup 0)
14596 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14597 (set (match_dup 3)
14598 (compare:CC (match_dup 0)
14599 (const_int 0)))]
14600 "")
14602 (define_insn ""
14603 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14604 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14605 (match_operand:SI 2 "reg_or_short_operand" "r"))
14606 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14607 "TARGET_POWER"
14608 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14609 [(set_attr "length" "12")])
14611 (define_insn ""
14612 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14613 (compare:CC
14614 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14615 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14616 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14617 (const_int 0)))
14618 (clobber (match_scratch:SI 4 "=&r,&r"))]
14619 "TARGET_POWER"
14620 "@
14621 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14622 #"
14623 [(set_attr "type" "compare")
14624 (set_attr "length" "12,16")])
14626 (define_split
14627 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14628 (compare:CC
14629 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14630 (match_operand:SI 2 "reg_or_short_operand" ""))
14631 (match_operand:SI 3 "gpc_reg_operand" ""))
14632 (const_int 0)))
14633 (clobber (match_scratch:SI 4 ""))]
14634 "TARGET_POWER && reload_completed"
14635 [(set (match_dup 4)
14636 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14637 (set (match_dup 0)
14638 (compare:CC (match_dup 4)
14639 (const_int 0)))]
14640 "")
14642 (define_insn ""
14643 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14644 (compare:CC
14645 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14646 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14647 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14648 (const_int 0)))
14649 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14650 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14651 "TARGET_POWER"
14652 "@
14653 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14654 #"
14655 [(set_attr "type" "compare")
14656 (set_attr "length" "12,16")])
14658 (define_split
14659 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14660 (compare:CC
14661 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14662 (match_operand:SI 2 "reg_or_short_operand" ""))
14663 (match_operand:SI 3 "gpc_reg_operand" ""))
14664 (const_int 0)))
14665 (set (match_operand:SI 0 "gpc_reg_operand" "")
14666 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14667 "TARGET_POWER && reload_completed"
14668 [(set (match_dup 0)
14669 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14670 (set (match_dup 4)
14671 (compare:CC (match_dup 0)
14672 (const_int 0)))]
14673 "")
14675 (define_insn ""
14676 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14677 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14678 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
14679 "TARGET_POWER"
14680 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14681 [(set_attr "length" "12")])
14683 (define_insn_and_split "*gtu<mode>"
14684 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14685 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14686 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14687 ""
14688 "#"
14689 ""
14690 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14691 (set (match_dup 0) (neg:P (match_dup 0)))]
14692 "")
14694 (define_insn_and_split "*gtu<mode>_compare"
14695 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14696 (compare:CC
14697 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14698 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14699 (const_int 0)))
14700 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14701 (gtu:P (match_dup 1) (match_dup 2)))]
14702 ""
14703 "#"
14704 ""
14705 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14706 (parallel [(set (match_dup 3)
14707 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14708 (set (match_dup 0) (neg:P (match_dup 0)))])]
14709 "")
14711 (define_insn_and_split "*plus_gtu<mode>"
14712 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14713 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14714 (match_operand:P 2 "reg_or_short_operand" "rI"))
14715 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14716 ""
14717 "#"
14718 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14719 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14720 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14721 "")
14723 (define_insn_and_split "*plus_gtu<mode>_compare"
14724 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14725 (compare:CC
14726 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14727 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14728 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14729 (const_int 0)))
14730 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14731 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14732 ""
14733 "#"
14734 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14735 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14736 (parallel [(set (match_dup 4)
14737 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14738 (const_int 0)))
14739 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14740 "")
14742 (define_insn "*neg_gtu<mode>"
14743 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14744 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14745 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14746 ""
14747 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
14748 [(set_attr "type" "two")
14749 (set_attr "length" "8")])
14751 \f
14752 ;; Define both directions of branch and return. If we need a reload
14753 ;; register, we'd rather use CR0 since it is much easier to copy a
14754 ;; register CC value to there.
14756 (define_insn ""
14757 [(set (pc)
14758 (if_then_else (match_operator 1 "branch_comparison_operator"
14759 [(match_operand 2
14760 "cc_reg_operand" "y")
14761 (const_int 0)])
14762 (label_ref (match_operand 0 "" ""))
14763 (pc)))]
14764 ""
14765 "*
14766 {
14767 return output_cbranch (operands[1], \"%l0\", 0, insn);
14768 }"
14769 [(set_attr "type" "branch")])
14771 (define_insn ""
14772 [(set (pc)
14773 (if_then_else (match_operator 0 "branch_comparison_operator"
14774 [(match_operand 1
14775 "cc_reg_operand" "y")
14776 (const_int 0)])
14777 (return)
14778 (pc)))]
14779 "direct_return ()"
14780 "*
14781 {
14782 return output_cbranch (operands[0], NULL, 0, insn);
14783 }"
14784 [(set_attr "type" "jmpreg")
14785 (set_attr "length" "4")])
14787 (define_insn ""
14788 [(set (pc)
14789 (if_then_else (match_operator 1 "branch_comparison_operator"
14790 [(match_operand 2
14791 "cc_reg_operand" "y")
14792 (const_int 0)])
14793 (pc)
14794 (label_ref (match_operand 0 "" ""))))]
14795 ""
14796 "*
14797 {
14798 return output_cbranch (operands[1], \"%l0\", 1, insn);
14799 }"
14800 [(set_attr "type" "branch")])
14802 (define_insn ""
14803 [(set (pc)
14804 (if_then_else (match_operator 0 "branch_comparison_operator"
14805 [(match_operand 1
14806 "cc_reg_operand" "y")
14807 (const_int 0)])
14808 (pc)
14809 (return)))]
14810 "direct_return ()"
14811 "*
14812 {
14813 return output_cbranch (operands[0], NULL, 1, insn);
14814 }"
14815 [(set_attr "type" "jmpreg")
14816 (set_attr "length" "4")])
14818 ;; Logic on condition register values.
14820 ; This pattern matches things like
14821 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14822 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14823 ; (const_int 1)))
14824 ; which are generated by the branch logic.
14825 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14827 (define_insn "*cceq_ior_compare"
14828 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14829 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14830 [(match_operator:SI 2
14831 "branch_positive_comparison_operator"
14832 [(match_operand 3
14833 "cc_reg_operand" "y,y")
14834 (const_int 0)])
14835 (match_operator:SI 4
14836 "branch_positive_comparison_operator"
14837 [(match_operand 5
14838 "cc_reg_operand" "0,y")
14839 (const_int 0)])])
14840 (const_int 1)))]
14841 ""
14842 "cr%q1 %E0,%j2,%j4"
14843 [(set_attr "type" "cr_logical,delayed_cr")])
14845 ; Why is the constant -1 here, but 1 in the previous pattern?
14846 ; Because ~1 has all but the low bit set.
14847 (define_insn ""
14848 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14849 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14850 [(not:SI (match_operator:SI 2
14851 "branch_positive_comparison_operator"
14852 [(match_operand 3
14853 "cc_reg_operand" "y,y")
14854 (const_int 0)]))
14855 (match_operator:SI 4
14856 "branch_positive_comparison_operator"
14857 [(match_operand 5
14858 "cc_reg_operand" "0,y")
14859 (const_int 0)])])
14860 (const_int -1)))]
14861 ""
14862 "cr%q1 %E0,%j2,%j4"
14863 [(set_attr "type" "cr_logical,delayed_cr")])
14865 (define_insn "*cceq_rev_compare"
14866 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14867 (compare:CCEQ (match_operator:SI 1
14868 "branch_positive_comparison_operator"
14869 [(match_operand 2
14870 "cc_reg_operand" "0,y")
14871 (const_int 0)])
14872 (const_int 0)))]
14873 ""
14874 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14875 [(set_attr "type" "cr_logical,delayed_cr")])
14877 ;; If we are comparing the result of two comparisons, this can be done
14878 ;; using creqv or crxor.
14880 (define_insn_and_split ""
14881 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14882 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14883 [(match_operand 2 "cc_reg_operand" "y")
14884 (const_int 0)])
14885 (match_operator 3 "branch_comparison_operator"
14886 [(match_operand 4 "cc_reg_operand" "y")
14887 (const_int 0)])))]
14888 ""
14889 "#"
14890 ""
14891 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14892 (match_dup 5)))]
14893 "
14894 {
14895 int positive_1, positive_2;
14897 positive_1 = branch_positive_comparison_operator (operands[1],
14898 GET_MODE (operands[1]));
14899 positive_2 = branch_positive_comparison_operator (operands[3],
14900 GET_MODE (operands[3]));
14902 if (! positive_1)
14903 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14904 GET_CODE (operands[1])),
14905 SImode,
14906 operands[2], const0_rtx);
14907 else if (GET_MODE (operands[1]) != SImode)
14908 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14909 operands[2], const0_rtx);
14911 if (! positive_2)
14912 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14913 GET_CODE (operands[3])),
14914 SImode,
14915 operands[4], const0_rtx);
14916 else if (GET_MODE (operands[3]) != SImode)
14917 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14918 operands[4], const0_rtx);
14920 if (positive_1 == positive_2)
14921 {
14922 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14923 operands[5] = constm1_rtx;
14924 }
14925 else
14926 {
14927 operands[5] = const1_rtx;
14928 }
14929 }")
14931 ;; Unconditional branch and return.
14933 (define_insn "jump"
14934 [(set (pc)
14935 (label_ref (match_operand 0 "" "")))]
14936 ""
14937 "b %l0"
14938 [(set_attr "type" "branch")])
14940 (define_insn "return"
14941 [(return)]
14942 "direct_return ()"
14943 "{br|blr}"
14944 [(set_attr "type" "jmpreg")])
14946 (define_expand "indirect_jump"
14947 [(set (pc) (match_operand 0 "register_operand" ""))])
14949 (define_insn "*indirect_jump<mode>"
14950 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14951 ""
14952 "@
14953 bctr
14954 {br|blr}"
14955 [(set_attr "type" "jmpreg")])
14957 ;; Table jump for switch statements:
14958 (define_expand "tablejump"
14959 [(use (match_operand 0 "" ""))
14960 (use (label_ref (match_operand 1 "" "")))]
14961 ""
14962 "
14963 {
14964 if (TARGET_32BIT)
14965 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14966 else
14967 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14968 DONE;
14969 }")
14971 (define_expand "tablejumpsi"
14972 [(set (match_dup 3)
14973 (plus:SI (match_operand:SI 0 "" "")
14974 (match_dup 2)))
14975 (parallel [(set (pc) (match_dup 3))
14976 (use (label_ref (match_operand 1 "" "")))])]
14977 "TARGET_32BIT"
14978 "
14979 { operands[0] = force_reg (SImode, operands[0]);
14980 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14981 operands[3] = gen_reg_rtx (SImode);
14982 }")
14984 (define_expand "tablejumpdi"
14985 [(set (match_dup 4)
14986 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14987 (set (match_dup 3)
14988 (plus:DI (match_dup 4)
14989 (match_dup 2)))
14990 (parallel [(set (pc) (match_dup 3))
14991 (use (label_ref (match_operand 1 "" "")))])]
14992 "TARGET_64BIT"
14993 "
14994 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14995 operands[3] = gen_reg_rtx (DImode);
14996 operands[4] = gen_reg_rtx (DImode);
14997 }")
14999 (define_insn "*tablejump<mode>_internal1"
15000 [(set (pc)
15001 (match_operand:P 0 "register_operand" "c,*l"))
15002 (use (label_ref (match_operand 1 "" "")))]
15003 ""
15004 "@
15005 bctr
15006 {br|blr}"
15007 [(set_attr "type" "jmpreg")])
15009 (define_insn "nop"
15010 [(const_int 0)]
15011 ""
15012 "{cror 0,0,0|nop}")
15013 \f
15014 ;; Define the subtract-one-and-jump insns, starting with the template
15015 ;; so loop.c knows what to generate.
15017 (define_expand "doloop_end"
15018 [(use (match_operand 0 "" "")) ; loop pseudo
15019 (use (match_operand 1 "" "")) ; iterations; zero if unknown
15020 (use (match_operand 2 "" "")) ; max iterations
15021 (use (match_operand 3 "" "")) ; loop level
15022 (use (match_operand 4 "" ""))] ; label
15023 ""
15024 "
15025 {
15026 /* Only use this on innermost loops. */
15027 if (INTVAL (operands[3]) > 1)
15028 FAIL;
15029 if (TARGET_64BIT)
15030 {
15031 if (GET_MODE (operands[0]) != DImode)
15032 FAIL;
15033 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
15034 }
15035 else
15036 {
15037 if (GET_MODE (operands[0]) != SImode)
15038 FAIL;
15039 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
15040 }
15041 DONE;
15042 }")
15044 (define_expand "ctr<mode>"
15045 [(parallel [(set (pc)
15046 (if_then_else (ne (match_operand:P 0 "register_operand" "")
15047 (const_int 1))
15048 (label_ref (match_operand 1 "" ""))
15049 (pc)))
15050 (set (match_dup 0)
15051 (plus:P (match_dup 0)
15052 (const_int -1)))
15053 (clobber (match_scratch:CC 2 ""))
15054 (clobber (match_scratch:P 3 ""))])]
15055 ""
15056 "")
15058 ;; We need to be able to do this for any operand, including MEM, or we
15059 ;; will cause reload to blow up since we don't allow output reloads on
15060 ;; JUMP_INSNs.
15061 ;; For the length attribute to be calculated correctly, the
15062 ;; label MUST be operand 0.
15064 (define_insn "*ctr<mode>_internal1"
15065 [(set (pc)
15066 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15067 (const_int 1))
15068 (label_ref (match_operand 0 "" ""))
15069 (pc)))
15070 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15071 (plus:P (match_dup 1)
15072 (const_int -1)))
15073 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15074 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15075 ""
15076 "*
15077 {
15078 if (which_alternative != 0)
15079 return \"#\";
15080 else if (get_attr_length (insn) == 4)
15081 return \"{bdn|bdnz} %l0\";
15082 else
15083 return \"bdz $+8\;b %l0\";
15084 }"
15085 [(set_attr "type" "branch")
15086 (set_attr "length" "*,12,16,16")])
15088 (define_insn "*ctr<mode>_internal2"
15089 [(set (pc)
15090 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15091 (const_int 1))
15092 (pc)
15093 (label_ref (match_operand 0 "" ""))))
15094 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15095 (plus:P (match_dup 1)
15096 (const_int -1)))
15097 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15098 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15099 ""
15100 "*
15101 {
15102 if (which_alternative != 0)
15103 return \"#\";
15104 else if (get_attr_length (insn) == 4)
15105 return \"bdz %l0\";
15106 else
15107 return \"{bdn|bdnz} $+8\;b %l0\";
15108 }"
15109 [(set_attr "type" "branch")
15110 (set_attr "length" "*,12,16,16")])
15112 ;; Similar but use EQ
15114 (define_insn "*ctr<mode>_internal5"
15115 [(set (pc)
15116 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15117 (const_int 1))
15118 (label_ref (match_operand 0 "" ""))
15119 (pc)))
15120 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15121 (plus:P (match_dup 1)
15122 (const_int -1)))
15123 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15124 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15125 ""
15126 "*
15127 {
15128 if (which_alternative != 0)
15129 return \"#\";
15130 else if (get_attr_length (insn) == 4)
15131 return \"bdz %l0\";
15132 else
15133 return \"{bdn|bdnz} $+8\;b %l0\";
15134 }"
15135 [(set_attr "type" "branch")
15136 (set_attr "length" "*,12,16,16")])
15138 (define_insn "*ctr<mode>_internal6"
15139 [(set (pc)
15140 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15141 (const_int 1))
15142 (pc)
15143 (label_ref (match_operand 0 "" ""))))
15144 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15145 (plus:P (match_dup 1)
15146 (const_int -1)))
15147 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15148 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15149 ""
15150 "*
15151 {
15152 if (which_alternative != 0)
15153 return \"#\";
15154 else if (get_attr_length (insn) == 4)
15155 return \"{bdn|bdnz} %l0\";
15156 else
15157 return \"bdz $+8\;b %l0\";
15158 }"
15159 [(set_attr "type" "branch")
15160 (set_attr "length" "*,12,16,16")])
15162 ;; Now the splitters if we could not allocate the CTR register
15164 (define_split
15165 [(set (pc)
15166 (if_then_else (match_operator 2 "comparison_operator"
15167 [(match_operand:P 1 "gpc_reg_operand" "")
15168 (const_int 1)])
15169 (match_operand 5 "" "")
15170 (match_operand 6 "" "")))
15171 (set (match_operand:P 0 "gpc_reg_operand" "")
15172 (plus:P (match_dup 1) (const_int -1)))
15173 (clobber (match_scratch:CC 3 ""))
15174 (clobber (match_scratch:P 4 ""))]
15175 "reload_completed"
15176 [(parallel [(set (match_dup 3)
15177 (compare:CC (plus:P (match_dup 1)
15178 (const_int -1))
15179 (const_int 0)))
15180 (set (match_dup 0)
15181 (plus:P (match_dup 1)
15182 (const_int -1)))])
15183 (set (pc) (if_then_else (match_dup 7)
15184 (match_dup 5)
15185 (match_dup 6)))]
15186 "
15187 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15188 operands[3], const0_rtx); }")
15190 (define_split
15191 [(set (pc)
15192 (if_then_else (match_operator 2 "comparison_operator"
15193 [(match_operand:P 1 "gpc_reg_operand" "")
15194 (const_int 1)])
15195 (match_operand 5 "" "")
15196 (match_operand 6 "" "")))
15197 (set (match_operand:P 0 "nonimmediate_operand" "")
15198 (plus:P (match_dup 1) (const_int -1)))
15199 (clobber (match_scratch:CC 3 ""))
15200 (clobber (match_scratch:P 4 ""))]
15201 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
15202 [(parallel [(set (match_dup 3)
15203 (compare:CC (plus:P (match_dup 1)
15204 (const_int -1))
15205 (const_int 0)))
15206 (set (match_dup 4)
15207 (plus:P (match_dup 1)
15208 (const_int -1)))])
15209 (set (match_dup 0)
15210 (match_dup 4))
15211 (set (pc) (if_then_else (match_dup 7)
15212 (match_dup 5)
15213 (match_dup 6)))]
15214 "
15215 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15216 operands[3], const0_rtx); }")
15217 \f
15218 (define_insn "trap"
15219 [(trap_if (const_int 1) (const_int 0))]
15220 ""
15221 "{t 31,0,0|trap}"
15222 [(set_attr "type" "trap")])
15224 (define_expand "ctrap<mode>4"
15225 [(trap_if (match_operator 0 "ordered_comparison_operator"
15226 [(match_operand:GPR 1 "register_operand")
15227 (match_operand:GPR 2 "reg_or_short_operand")])
15228 (match_operand 3 "zero_constant" ""))]
15229 ""
15230 "")
15232 (define_insn ""
15233 [(trap_if (match_operator 0 "ordered_comparison_operator"
15234 [(match_operand:GPR 1 "register_operand" "r")
15235 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
15236 (const_int 0))]
15237 ""
15238 "{t|t<wd>}%V0%I2 %1,%2"
15239 [(set_attr "type" "trap")])
15240 \f
15241 ;; Insns related to generating the function prologue and epilogue.
15243 (define_expand "prologue"
15244 [(use (const_int 0))]
15245 "TARGET_SCHED_PROLOG"
15246 "
15247 {
15248 rs6000_emit_prologue ();
15249 DONE;
15250 }")
15252 (define_insn "*movesi_from_cr_one"
15253 [(match_parallel 0 "mfcr_operation"
15254 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15255 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
15256 (match_operand 3 "immediate_operand" "n")]
15257 UNSPEC_MOVESI_FROM_CR))])]
15258 "TARGET_MFCRF"
15259 "*
15260 {
15261 int mask = 0;
15262 int i;
15263 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15264 {
15265 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15266 operands[4] = GEN_INT (mask);
15267 output_asm_insn (\"mfcr %1,%4\", operands);
15268 }
15269 return \"\";
15270 }"
15271 [(set_attr "type" "mfcrf")])
15273 (define_insn "movesi_from_cr"
15274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15275 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15276 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15277 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15278 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15279 UNSPEC_MOVESI_FROM_CR))]
15280 ""
15281 "mfcr %0"
15282 [(set_attr "type" "mfcr")])
15284 (define_insn "*stmw"
15285 [(match_parallel 0 "stmw_operation"
15286 [(set (match_operand:SI 1 "memory_operand" "=m")
15287 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15288 "TARGET_MULTIPLE"
15289 "{stm|stmw} %2,%1"
15290 [(set_attr "type" "store_ux")])
15292 (define_insn "*save_gpregs_<mode>"
15293 [(match_parallel 0 "any_parallel_operand"
15294 [(clobber (reg:P 65))
15295 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15296 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15297 (set (match_operand:P 3 "memory_operand" "=m")
15298 (match_operand:P 4 "gpc_reg_operand" "r"))])]
15299 ""
15300 "bl %z1"
15301 [(set_attr "type" "branch")
15302 (set_attr "length" "4")])
15304 (define_insn "*save_fpregs_<mode>"
15305 [(match_parallel 0 "any_parallel_operand"
15306 [(clobber (reg:P 65))
15307 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15308 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15309 (set (match_operand:DF 3 "memory_operand" "=m")
15310 (match_operand:DF 4 "gpc_reg_operand" "d"))])]
15311 ""
15312 "bl %z1"
15313 [(set_attr "type" "branch")
15314 (set_attr "length" "4")])
15316 ; These are to explain that changes to the stack pointer should
15317 ; not be moved over stores to stack memory.
15318 (define_insn "stack_tie"
15319 [(set (match_operand:BLK 0 "memory_operand" "+m")
15320 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
15321 ""
15322 ""
15323 [(set_attr "length" "0")])
15326 (define_expand "epilogue"
15327 [(use (const_int 0))]
15328 "TARGET_SCHED_PROLOG"
15329 "
15330 {
15331 rs6000_emit_epilogue (FALSE);
15332 DONE;
15333 }")
15335 ; On some processors, doing the mtcrf one CC register at a time is
15336 ; faster (like on the 604e). On others, doing them all at once is
15337 ; faster; for instance, on the 601 and 750.
15339 (define_expand "movsi_to_cr_one"
15340 [(set (match_operand:CC 0 "cc_reg_operand" "")
15341 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15342 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15343 ""
15344 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15346 (define_insn "*movsi_to_cr"
15347 [(match_parallel 0 "mtcrf_operation"
15348 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15349 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15350 (match_operand 3 "immediate_operand" "n")]
15351 UNSPEC_MOVESI_TO_CR))])]
15352 ""
15353 "*
15354 {
15355 int mask = 0;
15356 int i;
15357 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15358 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15359 operands[4] = GEN_INT (mask);
15360 return \"mtcrf %4,%2\";
15361 }"
15362 [(set_attr "type" "mtcr")])
15364 (define_insn "*mtcrfsi"
15365 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15366 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15367 (match_operand 2 "immediate_operand" "n")]
15368 UNSPEC_MOVESI_TO_CR))]
15369 "GET_CODE (operands[0]) == REG
15370 && CR_REGNO_P (REGNO (operands[0]))
15371 && GET_CODE (operands[2]) == CONST_INT
15372 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15373 "mtcrf %R0,%1"
15374 [(set_attr "type" "mtcr")])
15376 ; The load-multiple instructions have similar properties.
15377 ; Note that "load_multiple" is a name known to the machine-independent
15378 ; code that actually corresponds to the PowerPC load-string.
15380 (define_insn "*lmw"
15381 [(match_parallel 0 "lmw_operation"
15382 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15383 (match_operand:SI 2 "memory_operand" "m"))])]
15384 "TARGET_MULTIPLE"
15385 "{lm|lmw} %1,%2"
15386 [(set_attr "type" "load_ux")
15387 (set_attr "cell_micro" "always")])
15389 (define_insn "*return_internal_<mode>"
15390 [(return)
15391 (use (match_operand:P 0 "register_operand" "lc"))]
15392 ""
15393 "b%T0"
15394 [(set_attr "type" "jmpreg")])
15396 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
15397 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
15399 (define_insn "*restore_gpregs_<mode>"
15400 [(match_parallel 0 "any_parallel_operand"
15401 [(clobber (match_operand:P 1 "register_operand" "=l"))
15402 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15403 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15404 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15405 (match_operand:P 5 "memory_operand" "m"))])]
15406 ""
15407 "bl %z2"
15408 [(set_attr "type" "branch")
15409 (set_attr "length" "4")])
15411 (define_insn "*return_and_restore_gpregs_<mode>"
15412 [(match_parallel 0 "any_parallel_operand"
15413 [(return)
15414 (clobber (match_operand:P 1 "register_operand" "=l"))
15415 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15416 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15417 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15418 (match_operand:P 5 "memory_operand" "m"))])]
15419 ""
15420 "b %z2"
15421 [(set_attr "type" "branch")
15422 (set_attr "length" "4")])
15424 (define_insn "*return_and_restore_fpregs_<mode>"
15425 [(match_parallel 0 "any_parallel_operand"
15426 [(return)
15427 (clobber (match_operand:P 1 "register_operand" "=l"))
15428 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15429 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15430 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
15431 (match_operand:DF 5 "memory_operand" "m"))])]
15432 ""
15433 "b %z2"
15434 [(set_attr "type" "branch")
15435 (set_attr "length" "4")])
15437 ; This is used in compiling the unwind routines.
15438 (define_expand "eh_return"
15439 [(use (match_operand 0 "general_operand" ""))]
15440 ""
15441 "
15442 {
15443 if (TARGET_32BIT)
15444 emit_insn (gen_eh_set_lr_si (operands[0]));
15445 else
15446 emit_insn (gen_eh_set_lr_di (operands[0]));
15447 DONE;
15448 }")
15450 ; We can't expand this before we know where the link register is stored.
15451 (define_insn "eh_set_lr_<mode>"
15452 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
15453 UNSPECV_EH_RR)
15454 (clobber (match_scratch:P 1 "=&b"))]
15455 ""
15456 "#")
15458 (define_split
15459 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
15460 (clobber (match_scratch 1 ""))]
15461 "reload_completed"
15462 [(const_int 0)]
15463 "
15464 {
15465 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
15466 DONE;
15467 }")
15469 (define_insn "prefetch"
15470 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
15471 (match_operand:SI 1 "const_int_operand" "n")
15472 (match_operand:SI 2 "const_int_operand" "n"))]
15473 "TARGET_POWERPC"
15474 "*
15475 {
15476 if (GET_CODE (operands[0]) == REG)
15477 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
15478 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
15479 }"
15480 [(set_attr "type" "load")])
15481 \f
15482 (define_insn "bpermd_<mode>"
15483 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15484 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
15485 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
15486 "TARGET_POPCNTD"
15487 "bpermd %0,%1,%2"
15488 [(set_attr "type" "integer")])
15490 \f
15492 (include "sync.md")
15493 (include "vector.md")
15494 (include "vsx.md")
15495 (include "altivec.md")
15496 (include "spe.md")
15497 (include "dfp.md")
15498 (include "paired.md")