1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2018 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
118 #include "memmodel.h"
126 #include "addresses.h"
129 #include "rtl-error.h"
133 #include "print-rtl.h"
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
138 static int bb_reload_num
;
140 /* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143 static rtx_insn
*curr_insn
;
144 static rtx curr_insn_set
;
145 static basic_block curr_bb
;
146 static lra_insn_recog_data_t curr_id
;
147 static struct lra_static_insn_data
*curr_static_id
;
148 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
156 /* Start numbers for new registers and insns at the current constraints
158 static int new_regno_start
;
159 static int new_insn_uid_start
;
161 /* If LOC is nonnull, strip any outer subreg from it. */
163 strip_subreg (rtx
*loc
)
165 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
171 get_try_hard_regno (int regno
)
174 enum reg_class rclass
;
176 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
177 hard_regno
= lra_get_regno_hard_regno (regno
);
180 rclass
= lra_get_allocno_class (regno
);
181 if (rclass
== NO_REGS
)
183 return ira_class_hard_regs
[rclass
][0];
186 /* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
191 get_hard_regno (rtx x
, bool final_p
)
198 reg
= SUBREG_REG (x
);
201 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
202 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
206 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
208 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
209 SUBREG_BYTE (x
), GET_MODE (x
));
213 /* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217 static enum reg_class
218 get_reg_class (int regno
)
222 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
223 hard_regno
= lra_get_regno_hard_regno (regno
);
226 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
227 return REGNO_REG_CLASS (hard_regno
);
229 if (regno
>= new_regno_start
)
230 return lra_get_allocno_class (regno
);
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
243 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
245 enum reg_class rclass
, common_class
;
246 machine_mode reg_mode
;
247 int class_size
, hard_regno
, nregs
, i
, j
;
248 int regno
= REGNO (reg
);
250 if (new_class
!= NULL
)
251 *new_class
= NO_REGS
;
252 if (regno
< FIRST_PSEUDO_REGISTER
)
255 rtx
*final_loc
= &final_reg
;
257 lra_eliminate_reg_if_possible (final_loc
);
258 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
260 reg_mode
= GET_MODE (reg
);
261 rclass
= get_reg_class (regno
);
262 if (regno
< new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn
) >= new_insn_uid_start
269 && curr_insn_set
!= NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set
))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
272 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
278 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
279 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
280 lra_no_alloc_regs
)));
283 common_class
= ira_reg_class_subset
[rclass
][cl
];
284 if (new_class
!= NULL
)
285 *new_class
= common_class
;
286 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
289 /* Check that there are enough allocatable regs. */
290 class_size
= ira_class_hard_regs_num
[common_class
];
291 for (i
= 0; i
< class_size
; i
++)
293 hard_regno
= ira_class_hard_regs
[common_class
][i
];
294 nregs
= hard_regno_nregs (hard_regno
, reg_mode
);
297 for (j
= 0; j
< nregs
; j
++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
299 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
309 /* Return true if REGNO satisfies a memory constraint. */
313 return get_reg_class (regno
) == NO_REGS
;
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
321 rtx addr
, addr_space_t as
)
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as
));
325 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
331 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
336 /* Temporarily eliminates registers in an address (for the lifetime of
338 class address_eliminator
{
340 address_eliminator (struct address_info
*ad
);
341 ~address_eliminator ();
344 struct address_info
*m_ad
;
352 address_eliminator::address_eliminator (struct address_info
*ad
)
354 m_base_loc (strip_subreg (ad
->base_term
)),
355 m_base_reg (NULL_RTX
),
356 m_index_loc (strip_subreg (ad
->index_term
)),
357 m_index_reg (NULL_RTX
)
359 if (m_base_loc
!= NULL
)
361 m_base_reg
= *m_base_loc
;
362 lra_eliminate_reg_if_possible (m_base_loc
);
363 if (m_ad
->base_term2
!= NULL
)
364 *m_ad
->base_term2
= *m_ad
->base_term
;
366 if (m_index_loc
!= NULL
)
368 m_index_reg
= *m_index_loc
;
369 lra_eliminate_reg_if_possible (m_index_loc
);
373 address_eliminator::~address_eliminator ()
375 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
377 *m_base_loc
= m_base_reg
;
378 if (m_ad
->base_term2
!= NULL
)
379 *m_ad
->base_term2
= *m_ad
->base_term
;
381 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
382 *m_index_loc
= m_index_reg
;
385 /* Return true if the eliminated form of AD is a legitimate target address. */
387 valid_address_p (struct address_info
*ad
)
389 address_eliminator
eliminator (ad
);
390 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
393 /* Return true if the eliminated form of memory reference OP satisfies
394 extra (special) memory constraint CONSTRAINT. */
396 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
398 struct address_info ad
;
400 decompose_mem_address (&ad
, op
);
401 address_eliminator
eliminator (&ad
);
402 return constraint_satisfied_p (op
, constraint
);
405 /* Return true if the eliminated form of address AD satisfies extra
406 address constraint CONSTRAINT. */
408 satisfies_address_constraint_p (struct address_info
*ad
,
409 enum constraint_num constraint
)
411 address_eliminator
eliminator (ad
);
412 return constraint_satisfied_p (*ad
->outer
, constraint
);
415 /* Return true if the eliminated form of address OP satisfies extra
416 address constraint CONSTRAINT. */
418 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
420 struct address_info ad
;
422 decompose_lea_address (&ad
, &op
);
423 return satisfies_address_constraint_p (&ad
, constraint
);
426 /* Initiate equivalences for LRA. As we keep original equivalences
427 before any elimination, we need to make copies otherwise any change
428 in insns might change the equivalences. */
430 lra_init_equiv (void)
432 ira_expand_reg_equiv ();
433 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
437 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
438 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
439 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
440 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
444 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
446 /* Update equivalence for REGNO. We need to this as the equivalence
447 might contain other pseudos which are changed by their
450 update_equiv (int regno
)
454 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
455 ira_reg_equiv
[regno
].memory
456 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
458 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
459 ira_reg_equiv
[regno
].invariant
460 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
464 /* If we have decided to substitute X with another value, return that
465 value, otherwise return X. */
472 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
473 || ! ira_reg_equiv
[regno
].defined_p
474 || ! ira_reg_equiv
[regno
].profitable_p
475 || lra_get_regno_hard_regno (regno
) >= 0)
477 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
479 if (targetm
.cannot_substitute_mem_equiv_p (res
))
483 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
485 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
494 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
496 rtx res
= get_equiv (x
);
498 if (x
== res
|| CONSTANT_P (res
))
500 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
501 false, false, 0, true);
504 /* Set up curr_operand_mode. */
506 init_curr_operand_mode (void)
508 int nop
= curr_static_id
->n_operands
;
509 for (int i
= 0; i
< nop
; i
++)
511 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
512 if (mode
== VOIDmode
)
514 /* The .md mode for address operands is the mode of the
515 addressed value rather than the mode of the address itself. */
516 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
519 mode
= curr_static_id
->operand
[i
].mode
;
521 curr_operand_mode
[i
] = mode
;
527 /* The page contains code to reuse input reloads. */
529 /* Structure describes input reload of the current insns. */
532 /* True for input reload of matched operands. */
534 /* Reloaded value. */
536 /* Reload pseudo used. */
540 /* The number of elements in the following array. */
541 static int curr_insn_input_reloads_num
;
542 /* Array containing info about input reloads. It is used to find the
543 same input reload and reuse the reload pseudo in this case. */
544 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
546 /* Initiate data concerning reuse of input reloads for the current
549 init_curr_insn_input_reloads (void)
551 curr_insn_input_reloads_num
= 0;
554 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
555 created input reload pseudo (only if TYPE is not OP_OUT). Don't
556 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
557 wrapped up in SUBREG. The result pseudo is returned through
558 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
559 reused the already created input reload pseudo. Use TITLE to
560 describe new registers for debug purposes. */
562 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
563 enum reg_class rclass
, bool in_subreg_p
,
564 const char *title
, rtx
*result_reg
)
567 enum reg_class new_class
;
568 bool unique_p
= false;
573 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
576 /* Prevent reuse value of expression with side effects,
577 e.g. volatile memory. */
578 if (! side_effects_p (original
))
579 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
581 if (! curr_insn_input_reloads
[i
].match_p
582 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
583 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
585 rtx reg
= curr_insn_input_reloads
[i
].reg
;
587 /* If input is equal to original and both are VOIDmode,
588 GET_MODE (reg) might be still different from mode.
589 Ensure we don't return *result_reg with wrong mode. */
590 if (GET_MODE (reg
) != mode
)
594 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg
)),
595 GET_MODE_SIZE (mode
)))
597 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
598 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
602 if (lra_dump_file
!= NULL
)
604 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
605 dump_value_slim (lra_dump_file
, original
, 1);
607 if (new_class
!= lra_get_allocno_class (regno
))
608 lra_change_class (regno
, new_class
, ", change to", false);
609 if (lra_dump_file
!= NULL
)
610 fprintf (lra_dump_file
, "\n");
613 /* If we have an input reload with a different mode, make sure it
614 will get a different hard reg. */
615 else if (REG_P (original
)
616 && REG_P (curr_insn_input_reloads
[i
].input
)
617 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
618 && (GET_MODE (original
)
619 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
622 *result_reg
= (unique_p
623 ? lra_create_new_reg_with_unique_value
624 : lra_create_new_reg
) (mode
, original
, rclass
, title
);
625 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
626 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
627 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
628 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
634 /* The page contains code to extract memory address parts. */
636 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
638 ok_for_index_p_nonstrict (rtx reg
)
640 unsigned regno
= REGNO (reg
);
642 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
645 /* A version of regno_ok_for_base_p for use here, when all pseudos
646 should count as OK. Arguments as for regno_ok_for_base_p. */
648 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
649 enum rtx_code outer_code
, enum rtx_code index_code
)
651 unsigned regno
= REGNO (reg
);
653 if (regno
>= FIRST_PSEUDO_REGISTER
)
655 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
660 /* The page contains major code to choose the current insn alternative
661 and generate reloads for it. */
663 /* Return the offset from REGNO of the least significant register
666 This function is used to tell whether two registers satisfy
667 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
669 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
670 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
672 lra_constraint_offset (int regno
, machine_mode mode
)
674 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
676 scalar_int_mode int_mode
;
678 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
679 && GET_MODE_SIZE (int_mode
) > UNITS_PER_WORD
)
680 return hard_regno_nregs (regno
, mode
) - 1;
684 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
685 if they are the same hard reg, and has special hacks for
686 auto-increment and auto-decrement. This is specifically intended for
687 process_alt_operands to use in determining whether two operands
688 match. X is the operand whose number is the lower of the two.
690 It is supposed that X is the output operand and Y is the input
691 operand. Y_HARD_REGNO is the final hard regno of register Y or
692 register in subreg Y as we know it now. Otherwise, it is a
695 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
698 RTX_CODE code
= GET_CODE (x
);
703 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
704 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
708 i
= get_hard_regno (x
, false);
712 if ((j
= y_hard_regno
) < 0)
715 i
+= lra_constraint_offset (i
, GET_MODE (x
));
716 j
+= lra_constraint_offset (j
, GET_MODE (y
));
721 /* If two operands must match, because they are really a single
722 operand of an assembler insn, then two post-increments are invalid
723 because the assembler insn would increment only once. On the
724 other hand, a post-increment matches ordinary indexing if the
725 post-increment is the output operand. */
726 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
727 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
729 /* Two pre-increments are invalid because the assembler insn would
730 increment only once. On the other hand, a pre-increment matches
731 ordinary indexing if the pre-increment is the input operand. */
732 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
733 || GET_CODE (y
) == PRE_MODIFY
)
734 return operands_match_p (x
, XEXP (y
, 0), -1);
738 if (code
== REG
&& REG_P (y
))
739 return REGNO (x
) == REGNO (y
);
741 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
742 && x
== SUBREG_REG (y
))
744 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
745 && SUBREG_REG (x
) == y
)
748 /* Now we have disposed of all the cases in which different rtx
750 if (code
!= GET_CODE (y
))
753 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
754 if (GET_MODE (x
) != GET_MODE (y
))
763 return label_ref_label (x
) == label_ref_label (y
);
765 return XSTR (x
, 0) == XSTR (y
, 0);
771 /* Compare the elements. If any pair of corresponding elements fail
772 to match, return false for the whole things. */
774 fmt
= GET_RTX_FORMAT (code
);
775 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
781 if (XWINT (x
, i
) != XWINT (y
, i
))
786 if (XINT (x
, i
) != XINT (y
, i
))
791 if (maybe_ne (SUBREG_BYTE (x
), SUBREG_BYTE (y
)))
796 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
805 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
807 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
809 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
815 /* It is believed that rtx's at this level will never
816 contain anything but integers and other rtx's, except for
817 within LABEL_REFs and SYMBOL_REFs. */
825 /* True if X is a constant that can be forced into the constant pool.
826 MODE is the mode of the operand, or VOIDmode if not known. */
827 #define CONST_POOL_OK_P(MODE, X) \
828 ((MODE) != VOIDmode \
830 && GET_CODE (X) != HIGH \
831 && GET_MODE_SIZE (MODE).is_constant () \
832 && !targetm.cannot_force_const_mem (MODE, X))
834 /* True if C is a non-empty register class that has too few registers
835 to be safely used as a reload target class. */
836 #define SMALL_REGISTER_CLASS_P(C) \
837 (ira_class_hard_regs_num [(C)] == 1 \
838 || (ira_class_hard_regs_num [(C)] >= 1 \
839 && targetm.class_likely_spilled_p (C)))
841 /* If REG is a reload pseudo, try to make its class satisfying CL. */
843 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
845 enum reg_class rclass
;
847 /* Do not make more accurate class from reloads generated. They are
848 mostly moves with a lot of constraints. Making more accurate
849 class may results in very narrow class and impossibility of find
850 registers for several reloads of one insn. */
851 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
853 if (GET_CODE (reg
) == SUBREG
)
854 reg
= SUBREG_REG (reg
);
855 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
857 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
858 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
861 /* Searches X for any reference to a reg with the same value as REGNO,
862 returning the rtx of the reference found if any. Otherwise,
865 regno_val_use_in (unsigned int regno
, rtx x
)
871 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
874 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
875 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
879 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
882 else if (fmt
[i
] == 'E')
883 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
884 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
891 /* Return true if all current insn non-output operands except INS (it
892 has a negaitve end marker) do not use pseudos with the same value
895 check_conflict_input_operands (int regno
, signed char *ins
)
898 int n_operands
= curr_static_id
->n_operands
;
900 for (int nop
= 0; nop
< n_operands
; nop
++)
901 if (! curr_static_id
->operand
[nop
].is_operator
902 && curr_static_id
->operand
[nop
].type
!= OP_OUT
)
904 for (int i
= 0; (in
= ins
[i
]) >= 0; i
++)
908 && regno_val_use_in (regno
, *curr_id
->operand_loc
[nop
]) != NULL_RTX
)
914 /* Generate reloads for matching OUT and INS (array of input operand
915 numbers with end marker -1) with reg class GOAL_CLASS, considering
916 output operands OUTS (similar array to INS) needing to be in different
917 registers. Add input and output reloads correspondingly to the lists
918 *BEFORE and *AFTER. OUT might be negative. In this case we generate
919 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
920 that the output operand is early clobbered for chosen alternative. */
922 match_reload (signed char out
, signed char *ins
, signed char *outs
,
923 enum reg_class goal_class
, rtx_insn
**before
,
924 rtx_insn
**after
, bool early_clobber_p
)
928 rtx new_in_reg
, new_out_reg
, reg
;
929 machine_mode inmode
, outmode
;
930 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
931 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
933 inmode
= curr_operand_mode
[ins
[0]];
934 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
935 push_to_sequence (*before
);
936 if (inmode
!= outmode
)
938 /* process_alt_operands has already checked that the mode sizes
940 if (partial_subreg_p (outmode
, inmode
))
943 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
945 if (SCALAR_INT_MODE_P (inmode
))
946 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
949 poly_uint64 offset
= subreg_lowpart_offset (outmode
, inmode
);
950 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, offset
);
952 LRA_SUBREG_P (new_out_reg
) = 1;
953 /* If the input reg is dying here, we can use the same hard
954 register for REG and IN_RTX. We do it only for original
955 pseudos as reload pseudos can die although original
956 pseudos still live where reload pseudos dies. */
957 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
958 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
960 || check_conflict_input_operands(REGNO (in_rtx
), ins
)))
961 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
966 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
968 if (SCALAR_INT_MODE_P (outmode
))
969 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
972 poly_uint64 offset
= subreg_lowpart_offset (inmode
, outmode
);
973 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, offset
);
975 /* NEW_IN_REG is non-paradoxical subreg. We don't want
976 NEW_OUT_REG living above. We add clobber clause for
977 this. This is just a temporary clobber. We can remove
978 it at the end of LRA work. */
979 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
980 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
981 LRA_SUBREG_P (new_in_reg
) = 1;
982 if (GET_CODE (in_rtx
) == SUBREG
)
984 rtx subreg_reg
= SUBREG_REG (in_rtx
);
986 /* If SUBREG_REG is dying here and sub-registers IN_RTX
987 and NEW_IN_REG are similar, we can use the same hard
988 register for REG and SUBREG_REG. */
989 if (REG_P (subreg_reg
)
990 && (int) REGNO (subreg_reg
) < lra_new_regno_start
991 && GET_MODE (subreg_reg
) == outmode
992 && known_eq (SUBREG_BYTE (in_rtx
), SUBREG_BYTE (new_in_reg
))
993 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
))
994 && (! early_clobber_p
995 || check_conflict_input_operands (REGNO (subreg_reg
),
997 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
1003 /* Pseudos have values -- see comments for lra_reg_info.
1004 Different pseudos with the same value do not conflict even if
1005 they live in the same place. When we create a pseudo we
1006 assign value of original pseudo (if any) from which we
1007 created the new pseudo. If we create the pseudo from the
1008 input pseudo, the new pseudo will have no conflict with the
1009 input pseudo which is wrong when the input pseudo lives after
1010 the insn and as the new pseudo value is changed by the insn
1011 output. Therefore we create the new pseudo from the output
1012 except the case when we have single matched dying input
1015 We cannot reuse the current output register because we might
1016 have a situation like "a <- a op b", where the constraints
1017 force the second input operand ("b") to match the output
1018 operand ("a"). "b" must then be copied into a new register
1019 so that it doesn't clobber the current value of "a".
1021 We can not use the same value if the output pseudo is
1022 early clobbered or the input pseudo is mentioned in the
1023 output, e.g. as an address part in memory, because
1024 output reload will actually extend the pseudo liveness.
1025 We don't care about eliminable hard regs here as we are
1026 interesting only in pseudos. */
1028 /* Matching input's register value is the same as one of the other
1029 output operand. Output operands in a parallel insn must be in
1030 different registers. */
1031 out_conflict
= false;
1034 for (i
= 0; outs
[i
] >= 0; i
++)
1036 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
1037 if (REG_P (other_out_rtx
)
1038 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1041 out_conflict
= true;
1047 new_in_reg
= new_out_reg
1048 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1049 && (int) REGNO (in_rtx
) < lra_new_regno_start
1050 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1051 && (! early_clobber_p
1052 || check_conflict_input_operands (REGNO (in_rtx
), ins
))
1054 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1056 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
, "")
1057 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1060 /* In operand can be got from transformations before processing insn
1061 constraints. One example of such transformations is subreg
1062 reloading (see function simplify_operand_subreg). The new
1063 pseudos created by the transformations might have inaccurate
1064 class (ALL_REGS) and we should make their classes more
1066 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1067 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1068 *before
= get_insns ();
1070 /* Add the new pseudo to consider values of subsequent input reload
1072 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1073 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1074 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1075 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1076 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1079 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1080 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1081 *curr_id
->operand_loc
[in
] = new_in_reg
;
1083 lra_update_dups (curr_id
, ins
);
1086 /* See a comment for the input operand above. */
1087 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1088 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1091 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1093 *after
= get_insns ();
1096 *curr_id
->operand_loc
[out
] = new_out_reg
;
1097 lra_update_dup (curr_id
, out
);
1100 /* Return register class which is union of all reg classes in insn
1101 constraint alternative string starting with P. */
1102 static enum reg_class
1103 reg_class_from_constraints (const char *p
)
1106 enum reg_class op_class
= NO_REGS
;
1109 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1116 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1120 enum constraint_num cn
= lookup_constraint (p
);
1121 enum reg_class cl
= reg_class_for_constraint (cn
);
1124 if (insn_extra_address_constraint (cn
))
1126 = (reg_class_subunion
1127 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1128 ADDRESS
, SCRATCH
)]);
1132 op_class
= reg_class_subunion
[op_class
][cl
];
1135 while ((p
+= len
), c
);
1139 /* If OP is a register, return the class of the register as per
1140 get_reg_class, otherwise return NO_REGS. */
1141 static inline enum reg_class
1142 get_op_class (rtx op
)
1144 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1147 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1148 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1149 SUBREG for VAL to make them equal. */
1151 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1153 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1155 /* Usually size of mem_pseudo is greater than val size but in
1156 rare cases it can be less as it can be defined by target
1157 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1160 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1161 GET_CODE (val
) == SUBREG
1162 ? SUBREG_REG (val
) : val
);
1163 LRA_SUBREG_P (val
) = 1;
1167 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1168 LRA_SUBREG_P (mem_pseudo
) = 1;
1171 return to_p
? gen_move_insn (mem_pseudo
, val
)
1172 : gen_move_insn (val
, mem_pseudo
);
1175 /* Process a special case insn (register move), return true if we
1176 don't need to process it anymore. INSN should be a single set
1177 insn. Set up that RTL was changed through CHANGE_P and that hook
1178 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1181 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1184 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1186 enum reg_class dclass
, sclass
, secondary_class
;
1187 secondary_reload_info sri
;
1189 lra_assert (curr_insn_set
!= NULL_RTX
);
1190 dreg
= dest
= SET_DEST (curr_insn_set
);
1191 sreg
= src
= SET_SRC (curr_insn_set
);
1192 if (GET_CODE (dest
) == SUBREG
)
1193 dreg
= SUBREG_REG (dest
);
1194 if (GET_CODE (src
) == SUBREG
)
1195 sreg
= SUBREG_REG (src
);
1196 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1198 sclass
= dclass
= NO_REGS
;
1200 dclass
= get_reg_class (REGNO (dreg
));
1201 gcc_assert (dclass
< LIM_REG_CLASSES
);
1202 if (dclass
== ALL_REGS
)
1203 /* ALL_REGS is used for new pseudos created by transformations
1204 like reload of SUBREG_REG (see function
1205 simplify_operand_subreg). We don't know their class yet. We
1206 should figure out the class from processing the insn
1207 constraints not in this fast path function. Even if ALL_REGS
1208 were a right class for the pseudo, secondary_... hooks usually
1209 are not define for ALL_REGS. */
1212 sclass
= get_reg_class (REGNO (sreg
));
1213 gcc_assert (sclass
< LIM_REG_CLASSES
);
1214 if (sclass
== ALL_REGS
)
1215 /* See comments above. */
1217 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1219 if (targetm
.secondary_memory_needed (GET_MODE (src
), sclass
, dclass
)
1220 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1222 != targetm
.secondary_memory_needed_mode (GET_MODE (src
)))))
1227 if (! REG_P (dreg
) || ! REG_P (sreg
))
1229 sri
.prev_sri
= NULL
;
1230 sri
.icode
= CODE_FOR_nothing
;
1232 secondary_class
= NO_REGS
;
1233 /* Set up hard register for a reload pseudo for hook
1234 secondary_reload because some targets just ignore unassigned
1235 pseudos in the hook. */
1236 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1238 dregno
= REGNO (dreg
);
1239 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1243 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1245 sregno
= REGNO (sreg
);
1246 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1250 if (sclass
!= NO_REGS
)
1252 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1253 (reg_class_t
) sclass
,
1254 GET_MODE (src
), &sri
);
1255 if (sclass
== NO_REGS
1256 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1257 && dclass
!= NO_REGS
))
1259 enum reg_class old_sclass
= secondary_class
;
1260 secondary_reload_info old_sri
= sri
;
1262 sri
.prev_sri
= NULL
;
1263 sri
.icode
= CODE_FOR_nothing
;
1266 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1267 (reg_class_t
) dclass
,
1268 GET_MODE (src
), &sri
);
1269 /* Check the target hook consistency. */
1271 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1272 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1273 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1276 reg_renumber
[sregno
] = -1;
1278 reg_renumber
[dregno
] = -1;
1279 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1283 if (secondary_class
!= NO_REGS
)
1284 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1288 if (sri
.icode
== CODE_FOR_nothing
)
1289 lra_emit_move (new_reg
, src
);
1292 enum reg_class scratch_class
;
1294 scratch_class
= (reg_class_from_constraints
1295 (insn_data
[sri
.icode
].operand
[2].constraint
));
1296 scratch_reg
= (lra_create_new_reg_with_unique_value
1297 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1298 scratch_class
, "scratch"));
1299 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1302 before
= get_insns ();
1304 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1305 if (new_reg
!= NULL_RTX
)
1306 SET_SRC (curr_insn_set
) = new_reg
;
1309 if (lra_dump_file
!= NULL
)
1311 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1312 dump_insn_slim (lra_dump_file
, curr_insn
);
1314 lra_set_insn_deleted (curr_insn
);
1320 /* The following data describe the result of process_alt_operands.
1321 The data are used in curr_insn_transform to generate reloads. */
1323 /* The chosen reg classes which should be used for the corresponding
1325 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1326 /* True if the operand should be the same as another operand and that
1327 other operand does not need a reload. */
1328 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1329 /* True if the operand does not need a reload. */
1330 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1331 /* True if the operand can be offsetable memory. */
1332 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1333 /* The number of an operand to which given operand can be matched to. */
1334 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1335 /* The number of elements in the following array. */
1336 static int goal_alt_dont_inherit_ops_num
;
1337 /* Numbers of operands whose reload pseudos should not be inherited. */
1338 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1339 /* True if the insn commutative operands should be swapped. */
1340 static bool goal_alt_swapped
;
1341 /* The chosen insn alternative. */
1342 static int goal_alt_number
;
1344 /* True if the corresponding operand is the result of an equivalence
1346 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1348 /* The following five variables are used to choose the best insn
1349 alternative. They reflect final characteristics of the best
1352 /* Number of necessary reloads and overall cost reflecting the
1353 previous value and other unpleasantness of the best alternative. */
1354 static int best_losers
, best_overall
;
1355 /* Overall number hard registers used for reloads. For example, on
1356 some targets we need 2 general registers to reload DFmode and only
1357 one floating point register. */
1358 static int best_reload_nregs
;
1359 /* Overall number reflecting distances of previous reloading the same
1360 value. The distances are counted from the current BB start. It is
1361 used to improve inheritance chances. */
1362 static int best_reload_sum
;
1364 /* True if the current insn should have no correspondingly input or
1366 static bool no_input_reloads_p
, no_output_reloads_p
;
1368 /* True if we swapped the commutative operands in the current
1370 static int curr_swapped
;
1372 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1373 register of class CL. Add any input reloads to list BEFORE. AFTER
1374 is nonnull if *LOC is an automodified value; handle that case by
1375 adding the required output reloads to list AFTER. Return true if
1376 the RTL was changed.
1378 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1379 register. Return false if the address register is correct. */
1381 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1385 enum reg_class rclass
, new_class
;
1389 bool subreg_p
, before_p
= false;
1391 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1394 reg
= SUBREG_REG (*loc
);
1395 mode
= GET_MODE (reg
);
1397 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1398 between two registers with different classes, but there normally will
1399 be "mov" which transfers element of vector register into the general
1400 register, and this normally will be a subreg which should be reloaded
1401 as a whole. This is particularly likely to be triggered when
1402 -fno-split-wide-types specified. */
1404 || in_class_p (reg
, cl
, &new_class
)
1405 || known_le (GET_MODE_SIZE (mode
), GET_MODE_SIZE (ptr_mode
)))
1406 loc
= &SUBREG_REG (*loc
);
1410 mode
= GET_MODE (reg
);
1415 /* Always reload memory in an address even if the target supports
1417 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1422 regno
= REGNO (reg
);
1423 rclass
= get_reg_class (regno
);
1425 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1427 if (lra_dump_file
!= NULL
)
1429 fprintf (lra_dump_file
,
1430 "Changing pseudo %d in address of insn %u on equiv ",
1431 REGNO (reg
), INSN_UID (curr_insn
));
1432 dump_value_slim (lra_dump_file
, *loc
, 1);
1433 fprintf (lra_dump_file
, "\n");
1435 *loc
= copy_rtx (*loc
);
1437 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1442 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1443 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1446 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1450 lra_change_class (regno
, new_class
, " Change to", true);
1458 push_to_sequence (*before
);
1459 lra_emit_move (new_reg
, reg
);
1460 *before
= get_insns ();
1467 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1469 *after
= get_insns ();
1475 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1476 the insn to be inserted before curr insn. AFTER returns the
1477 the insn to be inserted after curr insn. ORIGREG and NEWREG
1478 are the original reg and new reg for reload. */
1480 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1485 push_to_sequence (*before
);
1486 lra_emit_move (newreg
, origreg
);
1487 *before
= get_insns ();
1493 lra_emit_move (origreg
, newreg
);
1495 *after
= get_insns ();
1500 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1501 static bool process_address (int, bool, rtx_insn
**, rtx_insn
**);
1503 /* Make reloads for subreg in operand NOP with internal subreg mode
1504 REG_MODE, add new reloads for further processing. Return true if
1505 any change was done. */
1507 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1510 rtx_insn
*before
, *after
;
1511 machine_mode mode
, innermode
;
1513 rtx operand
= *curr_id
->operand_loc
[nop
];
1514 enum reg_class regclass
;
1517 before
= after
= NULL
;
1519 if (GET_CODE (operand
) != SUBREG
)
1522 mode
= GET_MODE (operand
);
1523 reg
= SUBREG_REG (operand
);
1524 innermode
= GET_MODE (reg
);
1525 type
= curr_static_id
->operand
[nop
].type
;
1528 const bool addr_was_valid
1529 = valid_address_p (innermode
, XEXP (reg
, 0), MEM_ADDR_SPACE (reg
));
1530 alter_subreg (curr_id
->operand_loc
[nop
], false);
1531 rtx subst
= *curr_id
->operand_loc
[nop
];
1532 lra_assert (MEM_P (subst
));
1535 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1536 MEM_ADDR_SPACE (subst
))
1537 || ((get_constraint_type (lookup_constraint
1538 (curr_static_id
->operand
[nop
].constraint
))
1539 != CT_SPECIAL_MEMORY
)
1540 /* We still can reload address and if the address is
1541 valid, we can remove subreg without reloading its
1543 && valid_address_p (GET_MODE (subst
),
1545 [ira_class_hard_regs
1546 [base_reg_class (GET_MODE (subst
),
1547 MEM_ADDR_SPACE (subst
),
1548 ADDRESS
, SCRATCH
)][0]],
1549 MEM_ADDR_SPACE (subst
))))
1551 /* If we change the address for a paradoxical subreg of memory, the
1552 new address might violate the necessary alignment or the access
1553 might be slow; take this into consideration. We need not worry
1554 about accesses beyond allocated memory for paradoxical memory
1555 subregs as we don't substitute such equiv memory (see processing
1556 equivalences in function lra_constraints) and because for spilled
1557 pseudos we allocate stack memory enough for the biggest
1558 corresponding paradoxical subreg.
1560 However, do not blindly simplify a (subreg (mem ...)) for
1561 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1562 data into a register when the inner is narrower than outer or
1563 missing important data from memory when the inner is wider than
1564 outer. This rule only applies to modes that are no wider than
1566 if (!(maybe_ne (GET_MODE_PRECISION (mode
),
1567 GET_MODE_PRECISION (innermode
))
1568 && known_le (GET_MODE_SIZE (mode
), UNITS_PER_WORD
)
1569 && known_le (GET_MODE_SIZE (innermode
), UNITS_PER_WORD
)
1570 && WORD_REGISTER_OPERATIONS
)
1571 && (!(MEM_ALIGN (subst
) < GET_MODE_ALIGNMENT (mode
)
1572 && targetm
.slow_unaligned_access (mode
, MEM_ALIGN (subst
)))
1573 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1574 && targetm
.slow_unaligned_access (innermode
,
1578 *curr_id
->operand_loc
[nop
] = operand
;
1580 /* But if the address was not valid, we cannot reload the MEM without
1581 reloading the address first. */
1582 if (!addr_was_valid
)
1583 process_address (nop
, false, &before
, &after
);
1585 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1586 enum reg_class rclass
1587 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1588 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
,
1589 reg
, rclass
, TRUE
, "slow mem", &new_reg
))
1591 bool insert_before
, insert_after
;
1592 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1594 insert_before
= (type
!= OP_OUT
1595 || partial_subreg_p (mode
, innermode
));
1596 insert_after
= type
!= OP_IN
;
1597 insert_move_for_subreg (insert_before
? &before
: NULL
,
1598 insert_after
? &after
: NULL
,
1601 SUBREG_REG (operand
) = new_reg
;
1603 /* Convert to MODE. */
1606 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1607 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1608 rclass
, TRUE
, "slow mem", &new_reg
))
1610 bool insert_before
, insert_after
;
1611 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1613 insert_before
= type
!= OP_OUT
;
1614 insert_after
= type
!= OP_IN
;
1615 insert_move_for_subreg (insert_before
? &before
: NULL
,
1616 insert_after
? &after
: NULL
,
1619 *curr_id
->operand_loc
[nop
] = new_reg
;
1620 lra_process_new_insns (curr_insn
, before
, after
,
1621 "Inserting slow mem reload");
1625 /* If the address was valid and became invalid, prefer to reload
1626 the memory. Typical case is when the index scale should
1627 correspond the memory. */
1628 *curr_id
->operand_loc
[nop
] = operand
;
1629 /* Do not return false here as the MEM_P (reg) will be processed
1630 later in this function. */
1632 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1634 alter_subreg (curr_id
->operand_loc
[nop
], false);
1637 else if (CONSTANT_P (reg
))
1639 /* Try to simplify subreg of constant. It is usually result of
1640 equivalence substitution. */
1641 if (innermode
== VOIDmode
1642 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1643 innermode
= curr_static_id
->operand
[nop
].mode
;
1644 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1645 SUBREG_BYTE (operand
))) != NULL_RTX
)
1647 *curr_id
->operand_loc
[nop
] = new_reg
;
1651 /* Put constant into memory when we have mixed modes. It generates
1652 a better code in most cases as it does not need a secondary
1653 reload memory. It also prevents LRA looping when LRA is using
1654 secondary reload memory again and again. */
1655 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1656 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1658 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1659 alter_subreg (curr_id
->operand_loc
[nop
], false);
1662 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1663 if there may be a problem accessing OPERAND in the outer
1666 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1667 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1668 /* Don't reload paradoxical subregs because we could be looping
1669 having repeatedly final regno out of hard regs range. */
1670 && (hard_regno_nregs (hard_regno
, innermode
)
1671 >= hard_regno_nregs (hard_regno
, mode
))
1672 && simplify_subreg_regno (hard_regno
, innermode
,
1673 SUBREG_BYTE (operand
), mode
) < 0
1674 /* Don't reload subreg for matching reload. It is actually
1675 valid subreg in LRA. */
1676 && ! LRA_SUBREG_P (operand
))
1677 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1679 enum reg_class rclass
;
1682 /* There is a big probability that we will get the same class
1683 for the new pseudo and we will get the same insn which
1684 means infinite looping. So spill the new pseudo. */
1687 /* The class will be defined later in curr_insn_transform. */
1689 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1691 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1692 rclass
, TRUE
, "subreg reg", &new_reg
))
1694 bool insert_before
, insert_after
;
1695 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1697 insert_before
= (type
!= OP_OUT
1698 || read_modify_subreg_p (operand
));
1699 insert_after
= (type
!= OP_IN
);
1700 insert_move_for_subreg (insert_before
? &before
: NULL
,
1701 insert_after
? &after
: NULL
,
1704 SUBREG_REG (operand
) = new_reg
;
1705 lra_process_new_insns (curr_insn
, before
, after
,
1706 "Inserting subreg reload");
1709 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1710 IRA allocates hardreg to the inner pseudo reg according to its mode
1711 instead of the outermode, so the size of the hardreg may not be enough
1712 to contain the outermode operand, in that case we may need to insert
1713 reload for the reg. For the following two types of paradoxical subreg,
1714 we need to insert reload:
1715 1. If the op_type is OP_IN, and the hardreg could not be paired with
1716 other hardreg to contain the outermode operand
1717 (checked by in_hard_reg_set_p), we need to insert the reload.
1718 2. If the op_type is OP_OUT or OP_INOUT.
1720 Here is a paradoxical subreg example showing how the reload is generated:
1722 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1723 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1725 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1726 here, if reg107 is assigned to hardreg R15, because R15 is the last
1727 hardreg, compiler cannot find another hardreg to pair with R15 to
1728 contain TImode data. So we insert a TImode reload reg180 for it.
1729 After reload is inserted:
1731 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1732 (reg:DI 107 [ __comp ])) -1
1733 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1734 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1736 Two reload hard registers will be allocated to reg180 to save TImode data
1738 else if (REG_P (reg
)
1739 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1740 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1741 && (hard_regno_nregs (hard_regno
, innermode
)
1742 < hard_regno_nregs (hard_regno
, mode
))
1743 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1745 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1748 /* The class will be defined later in curr_insn_transform. */
1749 enum reg_class rclass
1750 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1752 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1753 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1756 bool insert_before
, insert_after
;
1758 PUT_MODE (new_reg
, mode
);
1759 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1760 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1762 insert_before
= (type
!= OP_OUT
);
1763 insert_after
= (type
!= OP_IN
);
1764 insert_move_for_subreg (insert_before
? &before
: NULL
,
1765 insert_after
? &after
: NULL
,
1768 SUBREG_REG (operand
) = new_reg
;
1769 lra_process_new_insns (curr_insn
, before
, after
,
1770 "Inserting paradoxical subreg reload");
1776 /* Return TRUE if X refers for a hard register from SET. */
1778 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1780 int i
, j
, x_hard_regno
;
1787 code
= GET_CODE (x
);
1788 mode
= GET_MODE (x
);
1791 mode
= wider_subreg_mode (x
);
1793 code
= GET_CODE (x
);
1798 x_hard_regno
= get_hard_regno (x
, true);
1799 return (x_hard_regno
>= 0
1800 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1804 struct address_info ad
;
1806 decompose_mem_address (&ad
, x
);
1807 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1809 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1812 fmt
= GET_RTX_FORMAT (code
);
1813 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1817 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1820 else if (fmt
[i
] == 'E')
1822 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1823 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1830 /* Return true if OP is a spilled pseudo. */
1832 spilled_pseudo_p (rtx op
)
1835 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1838 /* Return true if X is a general constant. */
1840 general_constant_p (rtx x
)
1842 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1846 reg_in_class_p (rtx reg
, enum reg_class cl
)
1849 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1850 return in_class_p (reg
, cl
, NULL
);
1853 /* Return true if SET of RCLASS contains no hard regs which can be
1856 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1862 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1863 COPY_HARD_REG_SET (temp
, set
);
1864 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
1865 return (hard_reg_set_subset_p
1866 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1870 /* Used to check validity info about small class input operands. It
1871 should be incremented at start of processing an insn
1873 static unsigned int curr_small_class_check
= 0;
1875 /* Update number of used inputs of class OP_CLASS for operand NOP.
1876 Return true if we have more such class operands than the number of
1879 update_and_check_small_class_inputs (int nop
, enum reg_class op_class
)
1881 static unsigned int small_class_check
[LIM_REG_CLASSES
];
1882 static int small_class_input_nums
[LIM_REG_CLASSES
];
1884 if (SMALL_REGISTER_CLASS_P (op_class
)
1885 /* We are interesting in classes became small because of fixing
1886 some hard regs, e.g. by an user through GCC options. */
1887 && hard_reg_set_intersect_p (reg_class_contents
[op_class
],
1889 && (curr_static_id
->operand
[nop
].type
!= OP_OUT
1890 || curr_static_id
->operand
[nop
].early_clobber
))
1892 if (small_class_check
[op_class
] == curr_small_class_check
)
1893 small_class_input_nums
[op_class
]++;
1896 small_class_check
[op_class
] = curr_small_class_check
;
1897 small_class_input_nums
[op_class
] = 1;
1899 if (small_class_input_nums
[op_class
] > ira_class_hard_regs_num
[op_class
])
1905 /* Major function to choose the current insn alternative and what
1906 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1907 negative we should consider only this alternative. Return false if
1908 we can not choose the alternative or find how to reload the
1911 process_alt_operands (int only_alternative
)
1914 int nop
, overall
, nalt
;
1915 int n_alternatives
= curr_static_id
->n_alternatives
;
1916 int n_operands
= curr_static_id
->n_operands
;
1917 /* LOSERS counts the operands that don't fit this alternative and
1918 would require loading. */
1921 /* REJECT is a count of how undesirable this alternative says it is
1922 if any reloading is required. If the alternative matches exactly
1923 then REJECT is ignored, but otherwise it gets this much counted
1924 against it in addition to the reloading needed. */
1926 /* This is defined by '!' or '?' alternative constraint and added to
1927 reject. But in some cases it can be ignored. */
1930 /* The number of elements in the following array. */
1931 int early_clobbered_regs_num
;
1932 /* Numbers of operands which are early clobber registers. */
1933 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1934 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1935 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1936 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1937 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1938 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1939 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1940 /* The number of elements in the following array. */
1941 int curr_alt_dont_inherit_ops_num
;
1942 /* Numbers of operands whose reload pseudos should not be inherited. */
1943 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1945 /* The register when the operand is a subreg of register, otherwise the
1947 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1948 /* The register if the operand is a register or subreg of register,
1950 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1951 int hard_regno
[MAX_RECOG_OPERANDS
];
1952 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1953 int reload_nregs
, reload_sum
;
1957 /* Calculate some data common for all alternatives to speed up the
1959 for (nop
= 0; nop
< n_operands
; nop
++)
1963 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1964 /* The real hard regno of the operand after the allocation. */
1965 hard_regno
[nop
] = get_hard_regno (op
, true);
1967 operand_reg
[nop
] = reg
= op
;
1968 biggest_mode
[nop
] = GET_MODE (op
);
1969 if (GET_CODE (op
) == SUBREG
)
1971 biggest_mode
[nop
] = wider_subreg_mode (op
);
1972 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1975 operand_reg
[nop
] = NULL_RTX
;
1976 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1977 || ((int) REGNO (reg
)
1978 == lra_get_elimination_hard_regno (REGNO (reg
))))
1979 no_subreg_reg_operand
[nop
] = reg
;
1981 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1982 /* Just use natural mode for elimination result. It should
1983 be enough for extra constraints hooks. */
1984 = regno_reg_rtx
[hard_regno
[nop
]];
1987 /* The constraints are made of several alternatives. Each operand's
1988 constraint looks like foo,bar,... with commas separating the
1989 alternatives. The first alternatives for all operands go
1990 together, the second alternatives go together, etc.
1992 First loop over alternatives. */
1993 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1994 if (only_alternative
>= 0)
1995 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1997 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1999 /* Loop over operands for one constraint alternative. */
2000 if (!TEST_BIT (preferred
, nalt
))
2003 curr_small_class_check
++;
2004 overall
= losers
= addr_losers
= 0;
2005 static_reject
= reject
= reload_nregs
= reload_sum
= 0;
2006 for (nop
= 0; nop
< n_operands
; nop
++)
2008 int inc
= (curr_static_id
2009 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
2010 if (lra_dump_file
!= NULL
&& inc
!= 0)
2011 fprintf (lra_dump_file
,
2012 " Staticly defined alt reject+=%d\n", inc
);
2013 static_reject
+= inc
;
2015 reject
+= static_reject
;
2016 early_clobbered_regs_num
= 0;
2018 for (nop
= 0; nop
< n_operands
; nop
++)
2022 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
2023 bool win
, did_match
, offmemok
, early_clobber_p
;
2024 /* false => this operand can be reloaded somehow for this
2027 /* true => this operand can be reloaded if the alternative
2030 /* True if a constant forced into memory would be OK for
2033 enum reg_class this_alternative
, this_costly_alternative
;
2034 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
2035 bool this_alternative_match_win
, this_alternative_win
;
2036 bool this_alternative_offmemok
;
2039 enum constraint_num cn
;
2041 opalt_num
= nalt
* n_operands
+ nop
;
2042 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
2044 /* Fast track for no constraints at all. */
2045 curr_alt
[nop
] = NO_REGS
;
2046 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
2047 curr_alt_win
[nop
] = true;
2048 curr_alt_match_win
[nop
] = false;
2049 curr_alt_offmemok
[nop
] = false;
2050 curr_alt_matches
[nop
] = -1;
2054 op
= no_subreg_reg_operand
[nop
];
2055 mode
= curr_operand_mode
[nop
];
2057 win
= did_match
= winreg
= offmemok
= constmemok
= false;
2060 early_clobber_p
= false;
2061 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
2063 this_costly_alternative
= this_alternative
= NO_REGS
;
2064 /* We update set of possible hard regs besides its class
2065 because reg class might be inaccurate. For example,
2066 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2067 is translated in HI_REGS because classes are merged by
2068 pairs and there is no accurate intermediate class. */
2069 CLEAR_HARD_REG_SET (this_alternative_set
);
2070 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
2071 this_alternative_win
= false;
2072 this_alternative_match_win
= false;
2073 this_alternative_offmemok
= false;
2074 this_alternative_matches
= -1;
2076 /* An empty constraint should be excluded by the fast
2078 lra_assert (*p
!= 0 && *p
!= ',');
2081 /* Scan this alternative's specs for this operand; set WIN
2082 if the operand fits any letter in this alternative.
2083 Otherwise, clear BADOP if this operand could fit some
2084 letter after reloads, or set WINREG if this operand could
2085 fit after reloads provided the constraint allows some
2090 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
2100 early_clobber_p
= true;
2104 op_reject
+= LRA_MAX_REJECT
;
2107 op_reject
+= LRA_LOSER_COST_FACTOR
;
2111 /* Ignore rest of this alternative. */
2115 case '0': case '1': case '2': case '3': case '4':
2116 case '5': case '6': case '7': case '8': case '9':
2121 m
= strtoul (p
, &end
, 10);
2124 lra_assert (nop
> m
);
2126 /* Reject matches if we don't know which operand is
2127 bigger. This situation would arguably be a bug in
2128 an .md pattern, but could also occur in a user asm. */
2129 if (!ordered_p (GET_MODE_SIZE (biggest_mode
[m
]),
2130 GET_MODE_SIZE (biggest_mode
[nop
])))
2133 this_alternative_matches
= m
;
2134 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
], false);
2135 /* We are supposed to match a previous operand.
2136 If we do, we win if that one did. If we do
2137 not, count both of the operands as losers.
2138 (This is too conservative, since most of the
2139 time only a single reload insn will be needed
2140 to make the two operands win. As a result,
2141 this alternative may be rejected when it is
2142 actually desirable.) */
2144 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2145 *curr_id
->operand_loc
[m
], m_hregno
))
2147 /* We should reject matching of an early
2148 clobber operand if the matching operand is
2149 not dying in the insn. */
2150 if (! curr_static_id
->operand
[m
].early_clobber
2151 || operand_reg
[nop
] == NULL_RTX
2152 || (find_regno_note (curr_insn
, REG_DEAD
,
2154 || REGNO (op
) == REGNO (operand_reg
[m
])))
2159 /* If we are matching a non-offsettable
2160 address where an offsettable address was
2161 expected, then we must reject this
2162 combination, because we can't reload
2164 if (curr_alt_offmemok
[m
]
2165 && MEM_P (*curr_id
->operand_loc
[m
])
2166 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2171 /* Operands don't match. Both operands must
2172 allow a reload register, otherwise we
2173 cannot make them match. */
2174 if (curr_alt
[m
] == NO_REGS
)
2176 /* Retroactively mark the operand we had to
2177 match as a loser, if it wasn't already and
2178 it wasn't matched to a register constraint
2179 (e.g it might be matched by memory). */
2181 && (operand_reg
[m
] == NULL_RTX
2182 || hard_regno
[m
] < 0))
2186 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2187 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2190 /* Prefer matching earlyclobber alternative as
2191 it results in less hard regs required for
2192 the insn than a non-matching earlyclobber
2194 if (curr_static_id
->operand
[m
].early_clobber
)
2196 if (lra_dump_file
!= NULL
)
2199 " %d Matching earlyclobber alt:"
2204 /* Otherwise we prefer no matching
2205 alternatives because it gives more freedom
2207 else if (operand_reg
[nop
] == NULL_RTX
2208 || (find_regno_note (curr_insn
, REG_DEAD
,
2209 REGNO (operand_reg
[nop
]))
2212 if (lra_dump_file
!= NULL
)
2215 " %d Matching alt: reject+=2\n",
2220 /* If we have to reload this operand and some
2221 previous operand also had to match the same
2222 thing as this operand, we don't know how to do
2224 if (!match_p
|| !curr_alt_win
[m
])
2226 for (i
= 0; i
< nop
; i
++)
2227 if (curr_alt_matches
[i
] == m
)
2235 /* This can be fixed with reloads if the operand
2236 we are supposed to match can be fixed with
2239 this_alternative
= curr_alt
[m
];
2240 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
2241 winreg
= this_alternative
!= NO_REGS
;
2247 || general_constant_p (op
)
2248 || spilled_pseudo_p (op
))
2254 cn
= lookup_constraint (p
);
2255 switch (get_constraint_type (cn
))
2258 cl
= reg_class_for_constraint (cn
);
2264 if (CONST_INT_P (op
)
2265 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2271 && satisfies_memory_constraint_p (op
, cn
))
2273 else if (spilled_pseudo_p (op
))
2276 /* If we didn't already win, we can reload constants
2277 via force_const_mem or put the pseudo value into
2278 memory, or make other memory by reloading the
2279 address like for 'o'. */
2280 if (CONST_POOL_OK_P (mode
, op
)
2281 || MEM_P (op
) || REG_P (op
)
2282 /* We can restore the equiv insn by a
2284 || equiv_substition_p
[nop
])
2291 /* If we didn't already win, we can reload the address
2292 into a base register. */
2293 if (satisfies_address_constraint_p (op
, cn
))
2295 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2301 if (constraint_satisfied_p (op
, cn
))
2305 case CT_SPECIAL_MEMORY
:
2307 && satisfies_memory_constraint_p (op
, cn
))
2309 else if (spilled_pseudo_p (op
))
2316 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2317 IOR_HARD_REG_SET (this_alternative_set
,
2318 reg_class_contents
[cl
]);
2321 this_costly_alternative
2322 = reg_class_subunion
[this_costly_alternative
][cl
];
2323 IOR_HARD_REG_SET (this_costly_alternative_set
,
2324 reg_class_contents
[cl
]);
2326 if (mode
== BLKmode
)
2331 if (hard_regno
[nop
] >= 0
2332 && in_hard_reg_set_p (this_alternative_set
,
2333 mode
, hard_regno
[nop
]))
2335 else if (hard_regno
[nop
] < 0
2336 && in_class_p (op
, this_alternative
, NULL
))
2341 if (c
!= ' ' && c
!= '\t')
2342 costly_p
= c
== '*';
2344 while ((p
+= len
), c
);
2346 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2347 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2348 /* Record which operands fit this alternative. */
2351 this_alternative_win
= true;
2352 if (operand_reg
[nop
] != NULL_RTX
)
2354 if (hard_regno
[nop
] >= 0)
2356 if (in_hard_reg_set_p (this_costly_alternative_set
,
2357 mode
, hard_regno
[nop
]))
2359 if (lra_dump_file
!= NULL
)
2360 fprintf (lra_dump_file
,
2361 " %d Costly set: reject++\n",
2368 /* Prefer won reg to spilled pseudo under other
2369 equal conditions for possibe inheritance. */
2372 if (lra_dump_file
!= NULL
)
2375 " %d Non pseudo reload: reject++\n",
2379 if (in_class_p (operand_reg
[nop
],
2380 this_costly_alternative
, NULL
))
2382 if (lra_dump_file
!= NULL
)
2385 " %d Non pseudo costly reload:"
2391 /* We simulate the behavior of old reload here.
2392 Although scratches need hard registers and it
2393 might result in spilling other pseudos, no reload
2394 insns are generated for the scratches. So it
2395 might cost something but probably less than old
2396 reload pass believes. */
2399 if (lra_dump_file
!= NULL
)
2400 fprintf (lra_dump_file
,
2401 " %d Scratch win: reject+=2\n",
2408 this_alternative_match_win
= true;
2411 int const_to_mem
= 0;
2414 reject
+= op_reject
;
2415 /* Never do output reload of stack pointer. It makes
2416 impossible to do elimination when SP is changed in
2418 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2419 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2422 /* If this alternative asks for a specific reg class, see if there
2423 is at least one allocatable register in that class. */
2425 = (this_alternative
== NO_REGS
2426 || (hard_reg_set_subset_p
2427 (reg_class_contents
[this_alternative
],
2428 lra_no_alloc_regs
)));
2430 /* For asms, verify that the class for this alternative is possible
2431 for the mode that is specified. */
2432 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2435 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2436 if (targetm
.hard_regno_mode_ok (i
, mode
)
2437 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2440 if (i
== FIRST_PSEUDO_REGISTER
)
2444 /* If this operand accepts a register, and if the
2445 register class has at least one allocatable register,
2446 then this operand can be reloaded. */
2447 if (winreg
&& !no_regs_p
)
2452 if (lra_dump_file
!= NULL
)
2453 fprintf (lra_dump_file
,
2454 " alt=%d: Bad operand -- refuse\n",
2459 if (this_alternative
!= NO_REGS
)
2461 HARD_REG_SET available_regs
;
2463 COPY_HARD_REG_SET (available_regs
,
2464 reg_class_contents
[this_alternative
]);
2465 AND_COMPL_HARD_REG_SET
2467 ira_prohibited_class_mode_regs
[this_alternative
][mode
]);
2468 AND_COMPL_HARD_REG_SET (available_regs
, lra_no_alloc_regs
);
2469 if (hard_reg_set_empty_p (available_regs
))
2471 /* There are no hard regs holding a value of given
2475 this_alternative
= NO_REGS
;
2476 if (lra_dump_file
!= NULL
)
2477 fprintf (lra_dump_file
,
2478 " %d Using memory because of"
2479 " a bad mode: reject+=2\n",
2485 if (lra_dump_file
!= NULL
)
2486 fprintf (lra_dump_file
,
2487 " alt=%d: Wrong mode -- refuse\n",
2494 /* If not assigned pseudo has a class which a subset of
2495 required reg class, it is a less costly alternative
2496 as the pseudo still can get a hard reg of necessary
2498 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2499 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2500 && ira_class_subset_p
[this_alternative
][cl
])
2502 if (lra_dump_file
!= NULL
)
2505 " %d Super set class reg: reject-=3\n", nop
);
2509 this_alternative_offmemok
= offmemok
;
2510 if (this_costly_alternative
!= NO_REGS
)
2512 if (lra_dump_file
!= NULL
)
2513 fprintf (lra_dump_file
,
2514 " %d Costly loser: reject++\n", nop
);
2517 /* If the operand is dying, has a matching constraint,
2518 and satisfies constraints of the matched operand
2519 which failed to satisfy the own constraints, most probably
2520 the reload for this operand will be gone. */
2521 if (this_alternative_matches
>= 0
2522 && !curr_alt_win
[this_alternative_matches
]
2524 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2525 && (hard_regno
[nop
] >= 0
2526 ? in_hard_reg_set_p (this_alternative_set
,
2527 mode
, hard_regno
[nop
])
2528 : in_class_p (op
, this_alternative
, NULL
)))
2530 if (lra_dump_file
!= NULL
)
2533 " %d Dying matched operand reload: reject++\n",
2539 /* Strict_low_part requires to reload the register
2540 not the sub-register. In this case we should
2541 check that a final reload hard reg can hold the
2543 if (curr_static_id
->operand
[nop
].strict_low
2545 && hard_regno
[nop
] < 0
2546 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2547 && ira_class_hard_regs_num
[this_alternative
] > 0
2548 && (!targetm
.hard_regno_mode_ok
2549 (ira_class_hard_regs
[this_alternative
][0],
2550 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2552 if (lra_dump_file
!= NULL
)
2555 " alt=%d: Strict low subreg reload -- refuse\n",
2561 if (operand_reg
[nop
] != NULL_RTX
2562 /* Output operands and matched input operands are
2563 not inherited. The following conditions do not
2564 exactly describe the previous statement but they
2565 are pretty close. */
2566 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2567 && (this_alternative_matches
< 0
2568 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2570 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2574 /* The value of reload_sum has sense only if we
2575 process insns in their order. It happens only on
2576 the first constraints sub-pass when we do most of
2578 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2579 reload_sum
+= last_reload
- bb_reload_num
;
2581 /* If this is a constant that is reloaded into the
2582 desired class by copying it to memory first, count
2583 that as another reload. This is consistent with
2584 other code and is required to avoid choosing another
2585 alternative when the constant is moved into memory.
2586 Note that the test here is precisely the same as in
2587 the code below that calls force_const_mem. */
2588 if (CONST_POOL_OK_P (mode
, op
)
2589 && ((targetm
.preferred_reload_class
2590 (op
, this_alternative
) == NO_REGS
)
2591 || no_input_reloads_p
))
2598 /* Alternative loses if it requires a type of reload not
2599 permitted for this insn. We can always reload
2600 objects with a REG_UNUSED note. */
2601 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2602 && no_output_reloads_p
2603 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2604 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2605 && no_input_reloads_p
&& ! const_to_mem
)
2606 || (this_alternative_matches
>= 0
2607 && (no_input_reloads_p
2608 || (no_output_reloads_p
2609 && (curr_static_id
->operand
2610 [this_alternative_matches
].type
!= OP_IN
)
2611 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2612 no_subreg_reg_operand
2613 [this_alternative_matches
])))))
2615 if (lra_dump_file
!= NULL
)
2618 " alt=%d: No input/otput reload -- refuse\n",
2623 /* Alternative loses if it required class pseudo can not
2624 hold value of required mode. Such insns can be
2625 described by insn definitions with mode iterators. */
2626 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2627 && ! hard_reg_set_empty_p (this_alternative_set
)
2628 /* It is common practice for constraints to use a
2629 class which does not have actually enough regs to
2630 hold the value (e.g. x86 AREG for mode requiring
2631 more one general reg). Therefore we have 2
2632 conditions to check that the reload pseudo can
2633 not hold the mode value. */
2634 && (!targetm
.hard_regno_mode_ok
2635 (ira_class_hard_regs
[this_alternative
][0],
2636 GET_MODE (*curr_id
->operand_loc
[nop
])))
2637 /* The above condition is not enough as the first
2638 reg in ira_class_hard_regs can be not aligned for
2639 multi-words mode values. */
2640 && (prohibited_class_reg_set_mode_p
2641 (this_alternative
, this_alternative_set
,
2642 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2644 if (lra_dump_file
!= NULL
)
2645 fprintf (lra_dump_file
,
2646 " alt=%d: reload pseudo for op %d "
2647 " can not hold the mode value -- refuse\n",
2652 /* Check strong discouragement of reload of non-constant
2653 into class THIS_ALTERNATIVE. */
2654 if (! CONSTANT_P (op
) && ! no_regs_p
2655 && (targetm
.preferred_reload_class
2656 (op
, this_alternative
) == NO_REGS
2657 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2658 && (targetm
.preferred_output_reload_class
2659 (op
, this_alternative
) == NO_REGS
))))
2661 if (lra_dump_file
!= NULL
)
2662 fprintf (lra_dump_file
,
2663 " %d Non-prefered reload: reject+=%d\n",
2664 nop
, LRA_MAX_REJECT
);
2665 reject
+= LRA_MAX_REJECT
;
2668 if (! (MEM_P (op
) && offmemok
)
2669 && ! (const_to_mem
&& constmemok
))
2671 /* We prefer to reload pseudos over reloading other
2672 things, since such reloads may be able to be
2673 eliminated later. So bump REJECT in other cases.
2674 Don't do this in the case where we are forcing a
2675 constant into memory and it will then win since
2676 we don't want to have a different alternative
2678 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2680 if (lra_dump_file
!= NULL
)
2683 " %d Non-pseudo reload: reject+=2\n",
2690 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2692 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2694 if (lra_dump_file
!= NULL
)
2697 " %d Small class reload: reject+=%d\n",
2698 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2699 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2703 /* We are trying to spill pseudo into memory. It is
2704 usually more costly than moving to a hard register
2705 although it might takes the same number of
2708 Non-pseudo spill may happen also. Suppose a target allows both
2709 register and memory in the operand constraint alternatives,
2710 then it's typical that an eliminable register has a substition
2711 of "base + offset" which can either be reloaded by a simple
2712 "new_reg <= base + offset" which will match the register
2713 constraint, or a similar reg addition followed by further spill
2714 to and reload from memory which will match the memory
2715 constraint, but this memory spill will be much more costly
2718 Code below increases the reject for both pseudo and non-pseudo
2721 && !(MEM_P (op
) && offmemok
)
2722 && !(REG_P (op
) && hard_regno
[nop
] < 0))
2724 if (lra_dump_file
!= NULL
)
2727 " %d Spill %spseudo into memory: reject+=3\n",
2728 nop
, REG_P (op
) ? "" : "Non-");
2730 if (VECTOR_MODE_P (mode
))
2732 /* Spilling vectors into memory is usually more
2733 costly as they contain big values. */
2734 if (lra_dump_file
!= NULL
)
2737 " %d Spill vector pseudo: reject+=2\n",
2743 /* When we use an operand requiring memory in given
2744 alternative, the insn should write *and* read the
2745 value to/from memory it is costly in comparison with
2746 an insn alternative which does not use memory
2747 (e.g. register or immediate operand). We exclude
2748 memory operand for such case as we can satisfy the
2749 memory constraints by reloading address. */
2750 if (no_regs_p
&& offmemok
&& !MEM_P (op
))
2752 if (lra_dump_file
!= NULL
)
2755 " Using memory insn operand %d: reject+=3\n",
2760 /* If reload requires moving value through secondary
2761 memory, it will need one more insn at least. */
2762 if (this_alternative
!= NO_REGS
2763 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2764 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2765 && targetm
.secondary_memory_needed (GET_MODE (op
), cl
,
2767 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2768 && (targetm
.secondary_memory_needed
2769 (GET_MODE (op
), this_alternative
, cl
)))))
2772 /* Input reloads can be inherited more often than output
2773 reloads can be removed, so penalize output
2775 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2777 if (lra_dump_file
!= NULL
)
2780 " %d Non input pseudo reload: reject++\n",
2785 if (MEM_P (op
) && offmemok
)
2787 else if (curr_static_id
->operand
[nop
].type
== OP_INOUT
)
2789 if (lra_dump_file
!= NULL
)
2792 " %d Input/Output reload: reject+=%d\n",
2793 nop
, LRA_LOSER_COST_FACTOR
);
2794 reject
+= LRA_LOSER_COST_FACTOR
;
2798 if (early_clobber_p
&& ! scratch_p
)
2800 if (lra_dump_file
!= NULL
)
2801 fprintf (lra_dump_file
,
2802 " %d Early clobber: reject++\n", nop
);
2805 /* ??? We check early clobbers after processing all operands
2806 (see loop below) and there we update the costs more.
2807 Should we update the cost (may be approximately) here
2808 because of early clobber register reloads or it is a rare
2809 or non-important thing to be worth to do it. */
2810 overall
= (losers
* LRA_LOSER_COST_FACTOR
+ reject
2811 - (addr_losers
== losers
? static_reject
: 0));
2812 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2814 if (lra_dump_file
!= NULL
)
2815 fprintf (lra_dump_file
,
2816 " alt=%d,overall=%d,losers=%d -- refuse\n",
2817 nalt
, overall
, losers
);
2821 if (update_and_check_small_class_inputs (nop
, this_alternative
))
2823 if (lra_dump_file
!= NULL
)
2824 fprintf (lra_dump_file
,
2825 " alt=%d, not enough small class regs -- refuse\n",
2829 curr_alt
[nop
] = this_alternative
;
2830 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2831 curr_alt_win
[nop
] = this_alternative_win
;
2832 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2833 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2834 curr_alt_matches
[nop
] = this_alternative_matches
;
2836 if (this_alternative_matches
>= 0
2837 && !did_match
&& !this_alternative_win
)
2838 curr_alt_win
[this_alternative_matches
] = false;
2840 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2841 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2844 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2845 /* Prevent processing non-move insns. */
2846 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2847 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2848 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2849 && REG_P (no_subreg_reg_operand
[0])
2850 && REG_P (no_subreg_reg_operand
[1])
2851 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2852 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2853 || (! curr_alt_win
[0] && curr_alt_win
[1]
2854 && REG_P (no_subreg_reg_operand
[1])
2855 /* Check that we reload memory not the memory
2857 && ! (curr_alt_offmemok
[0]
2858 && MEM_P (no_subreg_reg_operand
[0]))
2859 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2860 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2861 && REG_P (no_subreg_reg_operand
[0])
2862 /* Check that we reload memory not the memory
2864 && ! (curr_alt_offmemok
[1]
2865 && MEM_P (no_subreg_reg_operand
[1]))
2866 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2867 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2868 no_subreg_reg_operand
[1])
2869 || (targetm
.preferred_reload_class
2870 (no_subreg_reg_operand
[1],
2871 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2872 /* If it is a result of recent elimination in move
2873 insn we can transform it into an add still by
2874 using this alternative. */
2875 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
2876 /* Likewise if the source has been replaced with an
2877 equivalent value. This only happens once -- the reload
2878 will use the equivalent value instead of the register it
2879 replaces -- so there should be no danger of cycling. */
2880 && !equiv_substition_p
[1])))
2882 /* We have a move insn and a new reload insn will be similar
2883 to the current insn. We should avoid such situation as
2884 it results in LRA cycling. */
2885 if (lra_dump_file
!= NULL
)
2886 fprintf (lra_dump_file
,
2887 " Cycle danger: overall += LRA_MAX_REJECT\n");
2888 overall
+= LRA_MAX_REJECT
;
2891 curr_alt_dont_inherit_ops_num
= 0;
2892 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2894 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2895 HARD_REG_SET temp_set
;
2897 i
= early_clobbered_nops
[nop
];
2898 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2899 || hard_regno
[i
] < 0)
2901 lra_assert (operand_reg
[i
] != NULL_RTX
);
2902 clobbered_hard_regno
= hard_regno
[i
];
2903 CLEAR_HARD_REG_SET (temp_set
);
2904 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2905 first_conflict_j
= last_conflict_j
= -1;
2906 for (j
= 0; j
< n_operands
; j
++)
2908 /* We don't want process insides of match_operator and
2909 match_parallel because otherwise we would process
2910 their operands once again generating a wrong
2912 || curr_static_id
->operand
[j
].is_operator
)
2914 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2915 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2917 /* If we don't reload j-th operand, check conflicts. */
2918 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2919 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2921 if (first_conflict_j
< 0)
2922 first_conflict_j
= j
;
2923 last_conflict_j
= j
;
2925 if (last_conflict_j
< 0)
2927 /* If earlyclobber operand conflicts with another
2928 non-matching operand which is actually the same register
2929 as the earlyclobber operand, it is better to reload the
2930 another operand as an operand matching the earlyclobber
2931 operand can be also the same. */
2932 if (first_conflict_j
== last_conflict_j
2933 && operand_reg
[last_conflict_j
] != NULL_RTX
2934 && ! curr_alt_match_win
[last_conflict_j
]
2935 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2937 curr_alt_win
[last_conflict_j
] = false;
2938 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2941 /* Early clobber was already reflected in REJECT. */
2942 lra_assert (reject
> 0);
2943 if (lra_dump_file
!= NULL
)
2946 " %d Conflict early clobber reload: reject--\n",
2949 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2953 /* We need to reload early clobbered register and the
2954 matched registers. */
2955 for (j
= 0; j
< n_operands
; j
++)
2956 if (curr_alt_matches
[j
] == i
)
2958 curr_alt_match_win
[j
] = false;
2960 overall
+= LRA_LOSER_COST_FACTOR
;
2962 if (! curr_alt_match_win
[i
])
2963 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2966 /* Remember pseudos used for match reloads are never
2968 lra_assert (curr_alt_matches
[i
] >= 0);
2969 curr_alt_win
[curr_alt_matches
[i
]] = false;
2971 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2973 /* Early clobber was already reflected in REJECT. */
2974 lra_assert (reject
> 0);
2975 if (lra_dump_file
!= NULL
)
2978 " %d Matched conflict early clobber reloads: "
2982 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2985 if (lra_dump_file
!= NULL
)
2986 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2987 nalt
, overall
, losers
, reload_nregs
);
2989 /* If this alternative can be made to work by reloading, and it
2990 needs less reloading than the others checked so far, record
2991 it as the chosen goal for reloading. */
2992 if ((best_losers
!= 0 && losers
== 0)
2993 || (((best_losers
== 0 && losers
== 0)
2994 || (best_losers
!= 0 && losers
!= 0))
2995 && (best_overall
> overall
2996 || (best_overall
== overall
2997 /* If the cost of the reloads is the same,
2998 prefer alternative which requires minimal
2999 number of reload regs. */
3000 && (reload_nregs
< best_reload_nregs
3001 || (reload_nregs
== best_reload_nregs
3002 && (best_reload_sum
< reload_sum
3003 || (best_reload_sum
== reload_sum
3004 && nalt
< goal_alt_number
))))))))
3006 for (nop
= 0; nop
< n_operands
; nop
++)
3008 goal_alt_win
[nop
] = curr_alt_win
[nop
];
3009 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
3010 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
3011 goal_alt
[nop
] = curr_alt
[nop
];
3012 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
3014 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
3015 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
3016 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
3017 goal_alt_swapped
= curr_swapped
;
3018 best_overall
= overall
;
3019 best_losers
= losers
;
3020 best_reload_nregs
= reload_nregs
;
3021 best_reload_sum
= reload_sum
;
3022 goal_alt_number
= nalt
;
3025 /* Everything is satisfied. Do not process alternatives
3034 /* Make reload base reg from address AD. */
3036 base_to_reg (struct address_info
*ad
)
3040 rtx new_inner
= NULL_RTX
;
3041 rtx new_reg
= NULL_RTX
;
3043 rtx_insn
*last_insn
= get_last_insn();
3045 lra_assert (ad
->disp
== ad
->disp_term
);
3046 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3047 get_index_code (ad
));
3048 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base
), NULL_RTX
,
3050 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
3051 ad
->disp_term
== NULL
3054 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
3056 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base
));
3057 code
= recog_memoized (insn
);
3060 delete_insns_since (last_insn
);
3067 /* Make reload base reg + DISP from address AD. Return the new pseudo. */
3069 base_plus_disp_to_reg (struct address_info
*ad
, rtx disp
)
3074 lra_assert (ad
->base
== ad
->base_term
);
3075 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3076 get_index_code (ad
));
3077 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
3079 lra_emit_add (new_reg
, *ad
->base_term
, disp
);
3083 /* Make reload of index part of address AD. Return the new
3086 index_part_to_reg (struct address_info
*ad
)
3090 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
3091 INDEX_REG_CLASS
, "index term");
3092 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
3093 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
3097 /* Return true if we can add a displacement to address AD, even if that
3098 makes the address invalid. The fix-up code requires any new address
3099 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3101 can_add_disp_p (struct address_info
*ad
)
3103 return (!ad
->autoinc_p
3104 && ad
->segment
== NULL
3105 && ad
->base
== ad
->base_term
3106 && ad
->disp
== ad
->disp_term
);
3109 /* Make equiv substitution in address AD. Return true if a substitution
3112 equiv_address_substitution (struct address_info
*ad
)
3114 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
3116 HOST_WIDE_INT scale
;
3119 base_term
= strip_subreg (ad
->base_term
);
3120 if (base_term
== NULL
)
3121 base_reg
= new_base_reg
= NULL_RTX
;
3124 base_reg
= *base_term
;
3125 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
3127 index_term
= strip_subreg (ad
->index_term
);
3128 if (index_term
== NULL
)
3129 index_reg
= new_index_reg
= NULL_RTX
;
3132 index_reg
= *index_term
;
3133 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
3135 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
3139 if (lra_dump_file
!= NULL
)
3141 fprintf (lra_dump_file
, "Changing address in insn %d ",
3142 INSN_UID (curr_insn
));
3143 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3145 if (base_reg
!= new_base_reg
)
3148 if (REG_P (new_base_reg
))
3150 *base_term
= new_base_reg
;
3153 else if (GET_CODE (new_base_reg
) == PLUS
3154 && REG_P (XEXP (new_base_reg
, 0))
3155 && poly_int_rtx_p (XEXP (new_base_reg
, 1), &offset
)
3156 && can_add_disp_p (ad
))
3159 *base_term
= XEXP (new_base_reg
, 0);
3162 if (ad
->base_term2
!= NULL
)
3163 *ad
->base_term2
= *ad
->base_term
;
3165 if (index_reg
!= new_index_reg
)
3168 if (REG_P (new_index_reg
))
3170 *index_term
= new_index_reg
;
3173 else if (GET_CODE (new_index_reg
) == PLUS
3174 && REG_P (XEXP (new_index_reg
, 0))
3175 && poly_int_rtx_p (XEXP (new_index_reg
, 1), &offset
)
3176 && can_add_disp_p (ad
)
3177 && (scale
= get_index_scale (ad
)))
3179 disp
+= offset
* scale
;
3180 *index_term
= XEXP (new_index_reg
, 0);
3184 if (maybe_ne (disp
, 0))
3186 if (ad
->disp
!= NULL
)
3187 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3190 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3191 update_address (ad
);
3195 if (lra_dump_file
!= NULL
)
3198 fprintf (lra_dump_file
, " -- no change\n");
3201 fprintf (lra_dump_file
, " on equiv ");
3202 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3203 fprintf (lra_dump_file
, "\n");
3209 /* Major function to make reloads for an address in operand NOP or
3210 check its correctness (If CHECK_ONLY_P is true). The supported
3213 1) an address that existed before LRA started, at which point it
3214 must have been valid. These addresses are subject to elimination
3215 and may have become invalid due to the elimination offset being out
3218 2) an address created by forcing a constant to memory
3219 (force_const_to_mem). The initial form of these addresses might
3220 not be valid, and it is this function's job to make them valid.
3222 3) a frame address formed from a register and a (possibly zero)
3223 constant offset. As above, these addresses might not be valid and
3224 this function must make them so.
3226 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3227 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3228 address. Return true for any RTL change.
3230 The function is a helper function which does not produce all
3231 transformations (when CHECK_ONLY_P is false) which can be
3232 necessary. It does just basic steps. To do all necessary
3233 transformations use function process_address. */
3235 process_address_1 (int nop
, bool check_only_p
,
3236 rtx_insn
**before
, rtx_insn
**after
)
3238 struct address_info ad
;
3240 HOST_WIDE_INT scale
;
3241 rtx op
= *curr_id
->operand_loc
[nop
];
3242 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
3243 enum constraint_num cn
= lookup_constraint (constraint
);
3244 bool change_p
= false;
3247 && GET_MODE (op
) == BLKmode
3248 && GET_CODE (XEXP (op
, 0)) == SCRATCH
)
3251 if (insn_extra_address_constraint (cn
))
3252 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3253 /* Do not attempt to decompose arbitrary addresses generated by combine
3254 for asm operands with loose constraints, e.g 'X'. */
3256 && !(INSN_CODE (curr_insn
) < 0
3257 && get_constraint_type (cn
) == CT_FIXED_FORM
3258 && constraint_satisfied_p (op
, cn
)))
3259 decompose_mem_address (&ad
, op
);
3260 else if (GET_CODE (op
) == SUBREG
3261 && MEM_P (SUBREG_REG (op
)))
3262 decompose_mem_address (&ad
, SUBREG_REG (op
));
3265 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3266 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3267 when INDEX_REG_CLASS is a single register class. */
3268 if (ad
.base_term
!= NULL
3269 && ad
.index_term
!= NULL
3270 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
3271 && REG_P (*ad
.base_term
)
3272 && REG_P (*ad
.index_term
)
3273 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
3274 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
3276 std::swap (ad
.base
, ad
.index
);
3277 std::swap (ad
.base_term
, ad
.index_term
);
3280 change_p
= equiv_address_substitution (&ad
);
3281 if (ad
.base_term
!= NULL
3282 && (process_addr_reg
3283 (ad
.base_term
, check_only_p
, before
,
3285 && !(REG_P (*ad
.base_term
)
3286 && find_regno_note (curr_insn
, REG_DEAD
,
3287 REGNO (*ad
.base_term
)) != NULL_RTX
)
3289 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3290 get_index_code (&ad
)))))
3293 if (ad
.base_term2
!= NULL
)
3294 *ad
.base_term2
= *ad
.base_term
;
3296 if (ad
.index_term
!= NULL
3297 && process_addr_reg (ad
.index_term
, check_only_p
,
3298 before
, NULL
, INDEX_REG_CLASS
))
3301 /* Target hooks sometimes don't treat extra-constraint addresses as
3302 legitimate address_operands, so handle them specially. */
3303 if (insn_extra_address_constraint (cn
)
3304 && satisfies_address_constraint_p (&ad
, cn
))
3310 /* There are three cases where the shape of *AD.INNER may now be invalid:
3312 1) the original address was valid, but either elimination or
3313 equiv_address_substitution was applied and that made
3314 the address invalid.
3316 2) the address is an invalid symbolic address created by
3319 3) the address is a frame address with an invalid offset.
3321 4) the address is a frame address with an invalid base.
3323 All these cases involve a non-autoinc address, so there is no
3324 point revalidating other types. */
3325 if (ad
.autoinc_p
|| valid_address_p (&ad
))
3328 /* Any index existed before LRA started, so we can assume that the
3329 presence and shape of the index is valid. */
3330 push_to_sequence (*before
);
3331 lra_assert (ad
.disp
== ad
.disp_term
);
3332 if (ad
.base
== NULL
)
3334 if (ad
.index
== NULL
)
3337 rtx_insn
*last
= get_last_insn ();
3339 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3341 rtx addr
= *ad
.inner
;
3343 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3346 /* addr => lo_sum (new_base, addr), case (2) above. */
3347 insn
= emit_insn (gen_rtx_SET
3349 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3350 code
= recog_memoized (insn
);
3353 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3354 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3356 /* Try to put lo_sum into register. */
3357 insn
= emit_insn (gen_rtx_SET
3359 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3360 code
= recog_memoized (insn
);
3363 *ad
.inner
= new_reg
;
3364 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3374 delete_insns_since (last
);
3379 /* addr => new_base, case (2) above. */
3380 lra_emit_move (new_reg
, addr
);
3382 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3384 insn
= NEXT_INSN (insn
))
3385 if (recog_memoized (insn
) < 0)
3387 if (insn
!= NULL_RTX
)
3389 /* Do nothing if we cannot generate right insns.
3390 This is analogous to reload pass behavior. */
3391 delete_insns_since (last
);
3395 *ad
.inner
= new_reg
;
3400 /* index * scale + disp => new base + index * scale,
3402 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3403 GET_CODE (*ad
.index
));
3405 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3406 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
3407 lra_emit_move (new_reg
, *ad
.disp
);
3408 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3409 new_reg
, *ad
.index
);
3412 else if (ad
.index
== NULL
)
3417 rtx_insn
*insns
, *last_insn
;
3418 /* Try to reload base into register only if the base is invalid
3419 for the address but with valid offset, case (4) above. */
3421 new_reg
= base_to_reg (&ad
);
3423 /* base + disp => new base, cases (1) and (3) above. */
3424 /* Another option would be to reload the displacement into an
3425 index register. However, postreload has code to optimize
3426 address reloads that have the same base and different
3427 displacements, so reloading into an index register would
3428 not necessarily be a win. */
3429 if (new_reg
== NULL_RTX
)
3431 /* See if the target can split the displacement into a
3432 legitimate new displacement from a local anchor. */
3433 gcc_assert (ad
.disp
== ad
.disp_term
);
3434 poly_int64 orig_offset
;
3435 rtx offset1
, offset2
;
3436 if (poly_int_rtx_p (*ad
.disp
, &orig_offset
)
3437 && targetm
.legitimize_address_displacement (&offset1
, &offset2
,
3441 new_reg
= base_plus_disp_to_reg (&ad
, offset1
);
3442 new_reg
= gen_rtx_PLUS (GET_MODE (new_reg
), new_reg
, offset2
);
3445 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3447 insns
= get_insns ();
3448 last_insn
= get_last_insn ();
3449 /* If we generated at least two insns, try last insn source as
3450 an address. If we succeed, we generate one less insn. */
3452 && last_insn
!= insns
3453 && (set
= single_set (last_insn
)) != NULL_RTX
3454 && GET_CODE (SET_SRC (set
)) == PLUS
3455 && REG_P (XEXP (SET_SRC (set
), 0))
3456 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3458 *ad
.inner
= SET_SRC (set
);
3459 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3461 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3462 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3463 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3464 get_index_code (&ad
));
3465 regno
= REGNO (*ad
.base_term
);
3466 if (regno
>= FIRST_PSEUDO_REGISTER
3467 && cl
!= lra_get_allocno_class (regno
))
3468 lra_change_class (regno
, cl
, " Change to", true);
3469 new_reg
= SET_SRC (set
);
3470 delete_insns_since (PREV_INSN (last_insn
));
3475 *ad
.inner
= new_reg
;
3477 else if (ad
.disp_term
!= NULL
)
3479 /* base + scale * index + disp => new base + scale * index,
3481 gcc_assert (ad
.disp
== ad
.disp_term
);
3482 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3483 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3484 new_reg
, *ad
.index
);
3486 else if ((scale
= get_index_scale (&ad
)) == 1)
3488 /* The last transformation to one reg will be made in
3489 curr_insn_transform function. */
3493 else if (scale
!= 0)
3495 /* base + scale * index => base + new_reg,
3497 Index part of address may become invalid. For example, we
3498 changed pseudo on the equivalent memory and a subreg of the
3499 pseudo onto the memory of different mode for which the scale is
3501 new_reg
= index_part_to_reg (&ad
);
3502 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3503 *ad
.base_term
, new_reg
);
3507 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3509 rtx addr
= *ad
.inner
;
3511 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3512 /* addr => new_base. */
3513 lra_emit_move (new_reg
, addr
);
3514 *ad
.inner
= new_reg
;
3516 *before
= get_insns ();
3521 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3522 Use process_address_1 as a helper function. Return true for any
3525 If CHECK_ONLY_P is true, just check address correctness. Return
3526 false if the address correct. */
3528 process_address (int nop
, bool check_only_p
,
3529 rtx_insn
**before
, rtx_insn
**after
)
3533 while (process_address_1 (nop
, check_only_p
, before
, after
))
3542 /* Emit insns to reload VALUE into a new register. VALUE is an
3543 auto-increment or auto-decrement RTX whose operand is a register or
3544 memory location; so reloading involves incrementing that location.
3545 IN is either identical to VALUE, or some cheaper place to reload
3546 value being incremented/decremented from.
3548 INC_AMOUNT is the number to increment or decrement by (always
3549 positive and ignored for POST_MODIFY/PRE_MODIFY).
3551 Return pseudo containing the result. */
3553 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, poly_int64 inc_amount
)
3555 /* REG or MEM to be copied and incremented. */
3556 rtx incloc
= XEXP (value
, 0);
3557 /* Nonzero if increment after copying. */
3558 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3559 || GET_CODE (value
) == POST_MODIFY
);
3564 rtx real_in
= in
== value
? incloc
: in
;
3568 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3570 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3571 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3572 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3573 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3574 inc
= XEXP (XEXP (value
, 1), 1);
3578 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3579 inc_amount
= -inc_amount
;
3581 inc
= gen_int_mode (inc_amount
, GET_MODE (value
));
3584 if (! post
&& REG_P (incloc
))
3587 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3590 if (real_in
!= result
)
3592 /* First copy the location to the result register. */
3593 lra_assert (REG_P (result
));
3594 emit_insn (gen_move_insn (result
, real_in
));
3597 /* We suppose that there are insns to add/sub with the constant
3598 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3599 old reload worked with this assumption. If the assumption
3600 becomes wrong, we should use approach in function
3601 base_plus_disp_to_reg. */
3604 /* See if we can directly increment INCLOC. */
3605 last
= get_last_insn ();
3606 add_insn
= emit_insn (plus_p
3607 ? gen_add2_insn (incloc
, inc
)
3608 : gen_sub2_insn (incloc
, inc
));
3610 code
= recog_memoized (add_insn
);
3613 if (! post
&& result
!= incloc
)
3614 emit_insn (gen_move_insn (result
, incloc
));
3617 delete_insns_since (last
);
3620 /* If couldn't do the increment directly, must increment in RESULT.
3621 The way we do this depends on whether this is pre- or
3622 post-increment. For pre-increment, copy INCLOC to the reload
3623 register, increment it there, then save back. */
3626 if (real_in
!= result
)
3627 emit_insn (gen_move_insn (result
, real_in
));
3629 emit_insn (gen_add2_insn (result
, inc
));
3631 emit_insn (gen_sub2_insn (result
, inc
));
3632 if (result
!= incloc
)
3633 emit_insn (gen_move_insn (incloc
, result
));
3639 Because this might be a jump insn or a compare, and because
3640 RESULT may not be available after the insn in an input
3641 reload, we must do the incrementing before the insn being
3644 We have already copied IN to RESULT. Increment the copy in
3645 RESULT, save that back, then decrement RESULT so it has
3646 the original value. */
3648 emit_insn (gen_add2_insn (result
, inc
));
3650 emit_insn (gen_sub2_insn (result
, inc
));
3651 emit_insn (gen_move_insn (incloc
, result
));
3652 /* Restore non-modified value for the result. We prefer this
3653 way because it does not require an additional hard
3658 if (poly_int_rtx_p (inc
, &offset
))
3659 emit_insn (gen_add2_insn (result
,
3660 gen_int_mode (-offset
,
3661 GET_MODE (result
))));
3663 emit_insn (gen_sub2_insn (result
, inc
));
3666 emit_insn (gen_add2_insn (result
, inc
));
3671 /* Return true if the current move insn does not need processing as we
3672 already know that it satisfies its constraints. */
3674 simple_move_p (void)
3677 enum reg_class dclass
, sclass
;
3679 lra_assert (curr_insn_set
!= NULL_RTX
);
3680 dest
= SET_DEST (curr_insn_set
);
3681 src
= SET_SRC (curr_insn_set
);
3683 /* If the instruction has multiple sets we need to process it even if it
3684 is single_set. This can happen if one or more of the SETs are dead.
3686 if (multiple_sets (curr_insn
))
3689 return ((dclass
= get_op_class (dest
)) != NO_REGS
3690 && (sclass
= get_op_class (src
)) != NO_REGS
3691 /* The backend guarantees that register moves of cost 2
3692 never need reloads. */
3693 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3696 /* Swap operands NOP and NOP + 1. */
3698 swap_operands (int nop
)
3700 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3701 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3702 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3703 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
3704 /* Swap the duplicates too. */
3705 lra_update_dup (curr_id
, nop
);
3706 lra_update_dup (curr_id
, nop
+ 1);
3709 /* Main entry point of the constraint code: search the body of the
3710 current insn to choose the best alternative. It is mimicking insn
3711 alternative cost calculation model of former reload pass. That is
3712 because machine descriptions were written to use this model. This
3713 model can be changed in future. Make commutative operand exchange
3716 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3717 constraints. Return true if any change happened during function
3720 If CHECK_ONLY_P is true then don't do any transformation. Just
3721 check that the insn satisfies all constraints. If the insn does
3722 not satisfy any constraint, return true. */
3724 curr_insn_transform (bool check_only_p
)
3731 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3732 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3733 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
3734 rtx_insn
*before
, *after
;
3736 /* Flag that the insn has been changed through a transformation. */
3740 int max_regno_before
;
3741 int reused_alternative_num
;
3743 curr_insn_set
= single_set (curr_insn
);
3744 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3747 no_input_reloads_p
= no_output_reloads_p
= false;
3748 goal_alt_number
= -1;
3749 change_p
= sec_mem_p
= false;
3750 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3751 reloads; neither are insns that SET cc0. Insns that use CC0 are
3752 not allowed to have any input reloads. */
3753 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3754 no_output_reloads_p
= true;
3756 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3757 no_input_reloads_p
= true;
3758 if (HAVE_cc0
&& reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3759 no_output_reloads_p
= true;
3761 n_operands
= curr_static_id
->n_operands
;
3762 n_alternatives
= curr_static_id
->n_alternatives
;
3764 /* Just return "no reloads" if insn has no operands with
3766 if (n_operands
== 0 || n_alternatives
== 0)
3769 max_regno_before
= max_reg_num ();
3771 for (i
= 0; i
< n_operands
; i
++)
3773 goal_alt_matched
[i
][0] = -1;
3774 goal_alt_matches
[i
] = -1;
3777 commutative
= curr_static_id
->commutative
;
3779 /* Now see what we need for pseudos that didn't get hard regs or got
3780 the wrong kind of hard reg. For this, we must consider all the
3781 operands together against the register constraints. */
3783 best_losers
= best_overall
= INT_MAX
;
3784 best_reload_sum
= 0;
3786 curr_swapped
= false;
3787 goal_alt_swapped
= false;
3790 /* Make equivalence substitution and memory subreg elimination
3791 before address processing because an address legitimacy can
3792 depend on memory mode. */
3793 for (i
= 0; i
< n_operands
; i
++)
3796 bool op_change_p
= false;
3798 if (curr_static_id
->operand
[i
].is_operator
)
3801 old
= op
= *curr_id
->operand_loc
[i
];
3802 if (GET_CODE (old
) == SUBREG
)
3803 old
= SUBREG_REG (old
);
3804 subst
= get_equiv_with_elimination (old
, curr_insn
);
3805 original_subreg_reg_mode
[i
] = VOIDmode
;
3806 equiv_substition_p
[i
] = false;
3809 equiv_substition_p
[i
] = true;
3810 subst
= copy_rtx (subst
);
3811 lra_assert (REG_P (old
));
3812 if (GET_CODE (op
) != SUBREG
)
3813 *curr_id
->operand_loc
[i
] = subst
;
3816 SUBREG_REG (op
) = subst
;
3817 if (GET_MODE (subst
) == VOIDmode
)
3818 original_subreg_reg_mode
[i
] = GET_MODE (old
);
3820 if (lra_dump_file
!= NULL
)
3822 fprintf (lra_dump_file
,
3823 "Changing pseudo %d in operand %i of insn %u on equiv ",
3824 REGNO (old
), i
, INSN_UID (curr_insn
));
3825 dump_value_slim (lra_dump_file
, subst
, 1);
3826 fprintf (lra_dump_file
, "\n");
3828 op_change_p
= change_p
= true;
3830 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3833 lra_update_dup (curr_id
, i
);
3837 /* Reload address registers and displacements. We do it before
3838 finding an alternative because of memory constraints. */
3839 before
= after
= NULL
;
3840 for (i
= 0; i
< n_operands
; i
++)
3841 if (! curr_static_id
->operand
[i
].is_operator
3842 && process_address (i
, check_only_p
, &before
, &after
))
3847 lra_update_dup (curr_id
, i
);
3851 /* If we've changed the instruction then any alternative that
3852 we chose previously may no longer be valid. */
3853 lra_set_used_insn_alternative (curr_insn
, -1);
3855 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3856 && check_and_process_move (&change_p
, &sec_mem_p
))
3861 reused_alternative_num
= check_only_p
? -1 : curr_id
->used_insn_alternative
;
3862 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3863 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3864 reused_alternative_num
, INSN_UID (curr_insn
));
3866 if (process_alt_operands (reused_alternative_num
))
3870 return ! alt_p
|| best_losers
!= 0;
3872 /* If insn is commutative (it's safe to exchange a certain pair of
3873 operands) then we need to try each alternative twice, the second
3874 time matching those two operands as if we had exchanged them. To
3875 do this, really exchange them in operands.
3877 If we have just tried the alternatives the second time, return
3878 operands to normal and drop through. */
3880 if (reused_alternative_num
< 0 && commutative
>= 0)
3882 curr_swapped
= !curr_swapped
;
3885 swap_operands (commutative
);
3889 swap_operands (commutative
);
3892 if (! alt_p
&& ! sec_mem_p
)
3894 /* No alternative works with reloads?? */
3895 if (INSN_CODE (curr_insn
) >= 0)
3896 fatal_insn ("unable to generate reloads for:", curr_insn
);
3897 error_for_asm (curr_insn
,
3898 "inconsistent operand constraints in an %<asm%>");
3899 /* Avoid further trouble with this insn. Don't generate use
3900 pattern here as we could use the insn SP offset. */
3901 lra_set_insn_deleted (curr_insn
);
3905 /* If the best alternative is with operands 1 and 2 swapped, swap
3906 them. Update the operand numbers of any reloads already
3909 if (goal_alt_swapped
)
3911 if (lra_dump_file
!= NULL
)
3912 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3913 INSN_UID (curr_insn
));
3915 /* Swap the duplicates too. */
3916 swap_operands (commutative
);
3920 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3921 too conservatively. So we use the secondary memory only if there
3922 is no any alternative without reloads. */
3923 use_sec_mem_p
= false;
3925 use_sec_mem_p
= true;
3928 for (i
= 0; i
< n_operands
; i
++)
3929 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3931 use_sec_mem_p
= i
< n_operands
;
3936 int in
= -1, out
= -1;
3937 rtx new_reg
, src
, dest
, rld
;
3938 machine_mode sec_mode
, rld_mode
;
3940 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
3941 dest
= SET_DEST (curr_insn_set
);
3942 src
= SET_SRC (curr_insn_set
);
3943 for (i
= 0; i
< n_operands
; i
++)
3944 if (*curr_id
->operand_loc
[i
] == dest
)
3946 else if (*curr_id
->operand_loc
[i
] == src
)
3948 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
3949 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
3950 out
= curr_static_id
->dup_num
[i
];
3951 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
3952 in
= curr_static_id
->dup_num
[i
];
3953 lra_assert (out
>= 0 && in
>= 0
3954 && curr_static_id
->operand
[out
].type
== OP_OUT
3955 && curr_static_id
->operand
[in
].type
== OP_IN
);
3956 rld
= partial_subreg_p (GET_MODE (src
), GET_MODE (dest
)) ? src
: dest
;
3957 rld_mode
= GET_MODE (rld
);
3958 sec_mode
= targetm
.secondary_memory_needed_mode (rld_mode
);
3959 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3960 NO_REGS
, "secondary");
3961 /* If the mode is changed, it should be wider. */
3962 lra_assert (!partial_subreg_p (sec_mode
, rld_mode
));
3963 if (sec_mode
!= rld_mode
)
3965 /* If the target says specifically to use another mode for
3966 secondary memory moves we can not reuse the original
3968 after
= emit_spill_move (false, new_reg
, dest
);
3969 lra_process_new_insns (curr_insn
, NULL
, after
,
3970 "Inserting the sec. move");
3971 /* We may have non null BEFORE here (e.g. after address
3973 push_to_sequence (before
);
3974 before
= emit_spill_move (true, new_reg
, src
);
3976 before
= get_insns ();
3978 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3979 lra_set_insn_deleted (curr_insn
);
3981 else if (dest
== rld
)
3983 *curr_id
->operand_loc
[out
] = new_reg
;
3984 lra_update_dup (curr_id
, out
);
3985 after
= emit_spill_move (false, new_reg
, dest
);
3986 lra_process_new_insns (curr_insn
, NULL
, after
,
3987 "Inserting the sec. move");
3991 *curr_id
->operand_loc
[in
] = new_reg
;
3992 lra_update_dup (curr_id
, in
);
3993 /* See comments above. */
3994 push_to_sequence (before
);
3995 before
= emit_spill_move (true, new_reg
, src
);
3997 before
= get_insns ();
3999 lra_process_new_insns (curr_insn
, before
, NULL
,
4000 "Inserting the sec. move");
4002 lra_update_insn_regno_info (curr_insn
);
4006 lra_assert (goal_alt_number
>= 0);
4007 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
4009 if (lra_dump_file
!= NULL
)
4013 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
4014 goal_alt_number
, INSN_UID (curr_insn
));
4015 for (i
= 0; i
< n_operands
; i
++)
4017 p
= (curr_static_id
->operand_alternative
4018 [goal_alt_number
* n_operands
+ i
].constraint
);
4021 fprintf (lra_dump_file
, " (%d) ", i
);
4022 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
4023 fputc (*p
, lra_dump_file
);
4025 if (INSN_CODE (curr_insn
) >= 0
4026 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
4027 fprintf (lra_dump_file
, " {%s}", p
);
4028 if (maybe_ne (curr_id
->sp_offset
, 0))
4030 fprintf (lra_dump_file
, " (sp_off=");
4031 print_dec (curr_id
->sp_offset
, lra_dump_file
);
4032 fprintf (lra_dump_file
, ")");
4034 fprintf (lra_dump_file
, "\n");
4037 /* Right now, for any pair of operands I and J that are required to
4038 match, with J < I, goal_alt_matches[I] is J. Add I to
4039 goal_alt_matched[J]. */
4041 for (i
= 0; i
< n_operands
; i
++)
4042 if ((j
= goal_alt_matches
[i
]) >= 0)
4044 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
4046 /* We allow matching one output operand and several input
4049 || (curr_static_id
->operand
[j
].type
== OP_OUT
4050 && curr_static_id
->operand
[i
].type
== OP_IN
4051 && (curr_static_id
->operand
4052 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
4053 goal_alt_matched
[j
][k
] = i
;
4054 goal_alt_matched
[j
][k
+ 1] = -1;
4057 for (i
= 0; i
< n_operands
; i
++)
4058 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
4060 /* Any constants that aren't allowed and can't be reloaded into
4061 registers are here changed into memory references. */
4062 for (i
= 0; i
< n_operands
; i
++)
4063 if (goal_alt_win
[i
])
4066 enum reg_class new_class
;
4067 rtx reg
= *curr_id
->operand_loc
[i
];
4069 if (GET_CODE (reg
) == SUBREG
)
4070 reg
= SUBREG_REG (reg
);
4072 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
4074 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
4076 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
4079 lra_change_class (regno
, new_class
, " Change to", true);
4085 const char *constraint
;
4087 rtx op
= *curr_id
->operand_loc
[i
];
4088 rtx subreg
= NULL_RTX
;
4089 machine_mode mode
= curr_operand_mode
[i
];
4091 if (GET_CODE (op
) == SUBREG
)
4094 op
= SUBREG_REG (op
);
4095 mode
= GET_MODE (op
);
4098 if (CONST_POOL_OK_P (mode
, op
)
4099 && ((targetm
.preferred_reload_class
4100 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
4101 || no_input_reloads_p
))
4103 rtx tem
= force_const_mem (mode
, op
);
4106 if (subreg
!= NULL_RTX
)
4107 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
4109 *curr_id
->operand_loc
[i
] = tem
;
4110 lra_update_dup (curr_id
, i
);
4111 process_address (i
, false, &before
, &after
);
4113 /* If the alternative accepts constant pool refs directly
4114 there will be no reload needed at all. */
4115 if (subreg
!= NULL_RTX
)
4117 /* Skip alternatives before the one requested. */
4118 constraint
= (curr_static_id
->operand_alternative
4119 [goal_alt_number
* n_operands
+ i
].constraint
);
4121 (c
= *constraint
) && c
!= ',' && c
!= '#';
4122 constraint
+= CONSTRAINT_LEN (c
, constraint
))
4124 enum constraint_num cn
= lookup_constraint (constraint
);
4125 if ((insn_extra_memory_constraint (cn
)
4126 || insn_extra_special_memory_constraint (cn
))
4127 && satisfies_memory_constraint_p (tem
, cn
))
4130 if (c
== '\0' || c
== ',' || c
== '#')
4133 goal_alt_win
[i
] = true;
4139 for (i
= 0; i
< n_operands
; i
++)
4142 bool optional_p
= false;
4144 rtx op
= *curr_id
->operand_loc
[i
];
4146 if (goal_alt_win
[i
])
4148 if (goal_alt
[i
] == NO_REGS
4150 /* When we assign NO_REGS it means that we will not
4151 assign a hard register to the scratch pseudo by
4152 assigment pass and the scratch pseudo will be
4153 spilled. Spilled scratch pseudos are transformed
4154 back to scratches at the LRA end. */
4155 && lra_former_scratch_operand_p (curr_insn
, i
)
4156 && lra_former_scratch_p (REGNO (op
)))
4158 int regno
= REGNO (op
);
4159 lra_change_class (regno
, NO_REGS
, " Change to", true);
4160 if (lra_get_regno_hard_regno (regno
) >= 0)
4161 /* We don't have to mark all insn affected by the
4162 spilled pseudo as there is only one such insn, the
4164 reg_renumber
[regno
] = -1;
4165 lra_assert (bitmap_single_bit_set_p
4166 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4168 /* We can do an optional reload. If the pseudo got a hard
4169 reg, we might improve the code through inheritance. If
4170 it does not get a hard register we coalesce memory/memory
4171 moves later. Ignore move insns to avoid cycling. */
4173 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4174 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4175 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4176 && regno
< new_regno_start
4177 && ! lra_former_scratch_p (regno
)
4178 && reg_renumber
[regno
] < 0
4179 /* Check that the optional reload pseudo will be able to
4180 hold given mode value. */
4181 && ! (prohibited_class_reg_set_mode_p
4182 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4183 PSEUDO_REGNO_MODE (regno
)))
4184 && (curr_insn_set
== NULL_RTX
4185 || !((REG_P (SET_SRC (curr_insn_set
))
4186 || MEM_P (SET_SRC (curr_insn_set
))
4187 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4188 && (REG_P (SET_DEST (curr_insn_set
))
4189 || MEM_P (SET_DEST (curr_insn_set
))
4190 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4196 /* Operands that match previous ones have already been handled. */
4197 if (goal_alt_matches
[i
] >= 0)
4200 /* We should not have an operand with a non-offsettable address
4201 appearing where an offsettable address will do. It also may
4202 be a case when the address should be special in other words
4203 not a general one (e.g. it needs no index reg). */
4204 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4206 enum reg_class rclass
;
4207 rtx
*loc
= &XEXP (op
, 0);
4208 enum rtx_code code
= GET_CODE (*loc
);
4210 push_to_sequence (before
);
4211 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4213 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4214 new_reg
= emit_inc (rclass
, *loc
, *loc
,
4215 /* This value does not matter for MODIFY. */
4216 GET_MODE_SIZE (GET_MODE (op
)));
4217 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
4218 "offsetable address", &new_reg
))
4221 enum rtx_code code
= GET_CODE (addr
);
4223 if (code
== AND
&& CONST_INT_P (XEXP (addr
, 1)))
4224 /* (and ... (const_int -X)) is used to align to X bytes. */
4225 addr
= XEXP (*loc
, 0);
4226 lra_emit_move (new_reg
, addr
);
4228 emit_move_insn (new_reg
, gen_rtx_AND (GET_MODE (new_reg
), new_reg
, XEXP (*loc
, 1)));
4230 before
= get_insns ();
4233 lra_update_dup (curr_id
, i
);
4235 else if (goal_alt_matched
[i
][0] == -1)
4240 enum op_type type
= curr_static_id
->operand
[i
].type
;
4242 loc
= curr_id
->operand_loc
[i
];
4243 mode
= curr_operand_mode
[i
];
4244 if (GET_CODE (*loc
) == SUBREG
)
4246 reg
= SUBREG_REG (*loc
);
4247 poly_int64 byte
= SUBREG_BYTE (*loc
);
4249 /* Strict_low_part requires reloading the register and not
4250 just the subreg. Likewise for a strict subreg no wider
4251 than a word for WORD_REGISTER_OPERATIONS targets. */
4252 && (curr_static_id
->operand
[i
].strict_low
4253 || (!paradoxical_subreg_p (mode
, GET_MODE (reg
))
4255 = get_try_hard_regno (REGNO (reg
))) >= 0
4256 && (simplify_subreg_regno
4258 GET_MODE (reg
), byte
, mode
) < 0)
4259 && (goal_alt
[i
] == NO_REGS
4260 || (simplify_subreg_regno
4261 (ira_class_hard_regs
[goal_alt
[i
]][0],
4262 GET_MODE (reg
), byte
, mode
) >= 0)))
4263 || (partial_subreg_p (mode
, GET_MODE (reg
))
4264 && known_le (GET_MODE_SIZE (GET_MODE (reg
)),
4266 && WORD_REGISTER_OPERATIONS
)))
4268 /* An OP_INOUT is required when reloading a subreg of a
4269 mode wider than a word to ensure that data beyond the
4270 word being reloaded is preserved. Also automatically
4271 ensure that strict_low_part reloads are made into
4272 OP_INOUT which should already be true from the backend
4275 && (curr_static_id
->operand
[i
].strict_low
4276 || read_modify_subreg_p (*loc
)))
4278 loc
= &SUBREG_REG (*loc
);
4279 mode
= GET_MODE (*loc
);
4283 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4284 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4287 push_to_sequence (before
);
4288 lra_emit_move (new_reg
, old
);
4289 before
= get_insns ();
4294 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4297 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4299 after
= get_insns ();
4303 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4304 if (goal_alt_dont_inherit_ops
[j
] == i
)
4306 lra_set_regno_unique_value (REGNO (new_reg
));
4309 lra_update_dup (curr_id
, i
);
4311 else if (curr_static_id
->operand
[i
].type
== OP_IN
4312 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4314 || (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4316 && (operands_match_p
4317 (*curr_id
->operand_loc
[i
],
4318 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4321 /* generate reloads for input and matched outputs. */
4322 match_inputs
[0] = i
;
4323 match_inputs
[1] = -1;
4324 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4325 goal_alt
[i
], &before
, &after
,
4326 curr_static_id
->operand_alternative
4327 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4330 else if ((curr_static_id
->operand
[i
].type
== OP_OUT
4331 || (curr_static_id
->operand
[i
].type
== OP_INOUT
4332 && (operands_match_p
4333 (*curr_id
->operand_loc
[i
],
4334 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4336 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4338 /* Generate reloads for output and matched inputs. */
4339 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
], &before
,
4340 &after
, curr_static_id
->operand_alternative
4341 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4342 else if (curr_static_id
->operand
[i
].type
== OP_IN
4343 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4346 /* Generate reloads for matched inputs. */
4347 match_inputs
[0] = i
;
4348 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4349 match_inputs
[j
+ 1] = k
;
4350 match_inputs
[j
+ 1] = -1;
4351 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
], &before
,
4355 /* We must generate code in any case when function
4356 process_alt_operands decides that it is possible. */
4359 /* Memorise processed outputs so that output remaining to be processed
4360 can avoid using the same register value (see match_reload). */
4361 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4363 outputs
[n_outputs
++] = i
;
4364 outputs
[n_outputs
] = -1;
4371 lra_assert (REG_P (reg
));
4372 regno
= REGNO (reg
);
4373 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4374 if (GET_CODE (op
) == SUBREG
)
4375 op
= SUBREG_REG (op
);
4376 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4377 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4378 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4379 if (lra_dump_file
!= NULL
)
4380 fprintf (lra_dump_file
,
4381 " Making reload reg %d for reg %d optional\n",
4385 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4386 || max_regno_before
!= max_reg_num ())
4390 lra_update_operator_dups (curr_id
);
4391 /* Something changes -- process the insn. */
4392 lra_update_insn_regno_info (curr_insn
);
4394 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4398 /* Return true if INSN satisfies all constraints. In other words, no
4399 reload insns are needed. */
4401 lra_constrain_insn (rtx_insn
*insn
)
4403 int saved_new_regno_start
= new_regno_start
;
4404 int saved_new_insn_uid_start
= new_insn_uid_start
;
4408 curr_id
= lra_get_insn_recog_data (curr_insn
);
4409 curr_static_id
= curr_id
->insn_static_data
;
4410 new_insn_uid_start
= get_max_uid ();
4411 new_regno_start
= max_reg_num ();
4412 change_p
= curr_insn_transform (true);
4413 new_regno_start
= saved_new_regno_start
;
4414 new_insn_uid_start
= saved_new_insn_uid_start
;
4418 /* Return true if X is in LIST. */
4420 in_list_p (rtx x
, rtx list
)
4422 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4423 if (XEXP (list
, 0) == x
)
4428 /* Return true if X contains an allocatable hard register (if
4429 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4431 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4437 code
= GET_CODE (x
);
4440 int regno
= REGNO (x
);
4441 HARD_REG_SET alloc_regs
;
4445 if (regno
>= FIRST_PSEUDO_REGISTER
)
4446 regno
= lra_get_regno_hard_regno (regno
);
4449 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
4450 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4454 if (regno
< FIRST_PSEUDO_REGISTER
)
4458 return lra_get_regno_hard_regno (regno
) < 0;
4461 fmt
= GET_RTX_FORMAT (code
);
4462 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4466 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4469 else if (fmt
[i
] == 'E')
4471 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4472 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4479 /* Process all regs in location *LOC and change them on equivalent
4480 substitution. Return true if any change was done. */
4482 loc_equivalence_change_p (rtx
*loc
)
4484 rtx subst
, reg
, x
= *loc
;
4485 bool result
= false;
4486 enum rtx_code code
= GET_CODE (x
);
4492 reg
= SUBREG_REG (x
);
4493 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4494 && GET_MODE (subst
) == VOIDmode
)
4496 /* We cannot reload debug location. Simplify subreg here
4497 while we know the inner mode. */
4498 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4499 GET_MODE (reg
), SUBREG_BYTE (x
));
4503 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4509 /* Scan all the operand sub-expressions. */
4510 fmt
= GET_RTX_FORMAT (code
);
4511 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4514 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4515 else if (fmt
[i
] == 'E')
4516 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4518 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4523 /* Similar to loc_equivalence_change_p, but for use as
4524 simplify_replace_fn_rtx callback. DATA is insn for which the
4525 elimination is done. If it null we don't do the elimination. */
4527 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4532 rtx subst
= (data
== NULL
4533 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4540 /* Maximum number of generated reload insns per an insn. It is for
4541 preventing this pass cycling in a bug case. */
4542 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4544 /* The current iteration number of this LRA pass. */
4545 int lra_constraint_iter
;
4547 /* True if we substituted equiv which needs checking register
4548 allocation correctness because the equivalent value contains
4549 allocatable hard registers or when we restore multi-register
4551 bool lra_risky_transformations_p
;
4553 /* Return true if REGNO is referenced in more than one block. */
4555 multi_block_pseudo_p (int regno
)
4557 basic_block bb
= NULL
;
4561 if (regno
< FIRST_PSEUDO_REGISTER
)
4564 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4566 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4567 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4572 /* Return true if LIST contains a deleted insn. */
4574 contains_deleted_insn_p (rtx_insn_list
*list
)
4576 for (; list
!= NULL_RTX
; list
= list
->next ())
4577 if (NOTE_P (list
->insn ())
4578 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4583 /* Return true if X contains a pseudo dying in INSN. */
4585 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4592 return (insn
!= NULL_RTX
4593 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4594 code
= GET_CODE (x
);
4595 fmt
= GET_RTX_FORMAT (code
);
4596 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4600 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4603 else if (fmt
[i
] == 'E')
4605 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4606 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4613 /* Return true if INSN contains a dying pseudo in INSN right hand
4616 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4618 rtx set
= single_set (insn
);
4620 gcc_assert (set
!= NULL
);
4621 return dead_pseudo_p (SET_SRC (set
), insn
);
4624 /* Return true if any init insn of REGNO contains a dying pseudo in
4625 insn right hand side. */
4627 init_insn_rhs_dead_pseudo_p (int regno
)
4629 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4633 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4634 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4639 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4640 reverse only if we have one init insn with given REGNO as a
4643 reverse_equiv_p (int regno
)
4645 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4650 if (! INSN_P (insns
->insn ())
4651 || insns
->next () != NULL
)
4653 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4655 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4658 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4659 call this function only for non-reverse equivalence. */
4661 contains_reloaded_insn_p (int regno
)
4664 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4666 for (; list
!= NULL
; list
= list
->next ())
4667 if ((set
= single_set (list
->insn ())) == NULL_RTX
4668 || ! REG_P (SET_DEST (set
))
4669 || (int) REGNO (SET_DEST (set
)) != regno
)
4674 /* Entry function of LRA constraint pass. Return true if the
4675 constraint pass did change the code. */
4677 lra_constraints (bool first_p
)
4680 int i
, hard_regno
, new_insns_num
;
4681 unsigned int min_len
, new_min_len
, uid
;
4682 rtx set
, x
, reg
, dest_reg
;
4683 basic_block last_bb
;
4686 lra_constraint_iter
++;
4687 if (lra_dump_file
!= NULL
)
4688 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4689 lra_constraint_iter
);
4691 if (pic_offset_table_rtx
4692 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4693 lra_risky_transformations_p
= true;
4695 /* On the first iteration we should check IRA assignment
4696 correctness. In rare cases, the assignments can be wrong as
4697 early clobbers operands are ignored in IRA. */
4698 lra_risky_transformations_p
= first_p
;
4699 new_insn_uid_start
= get_max_uid ();
4700 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4701 /* Mark used hard regs for target stack size calulations. */
4702 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4703 if (lra_reg_info
[i
].nrefs
!= 0
4704 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4708 nregs
= hard_regno_nregs (hard_regno
, lra_reg_info
[i
].biggest_mode
);
4709 for (j
= 0; j
< nregs
; j
++)
4710 df_set_regs_ever_live (hard_regno
+ j
, true);
4712 /* Do elimination before the equivalence processing as we can spill
4713 some pseudos during elimination. */
4714 lra_eliminate (false, first_p
);
4715 auto_bitmap
equiv_insn_bitmap (®_obstack
);
4716 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4717 if (lra_reg_info
[i
].nrefs
!= 0)
4719 ira_reg_equiv
[i
].profitable_p
= true;
4720 reg
= regno_reg_rtx
[i
];
4721 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4723 bool pseudo_p
= contains_reg_p (x
, false, false);
4725 /* After RTL transformation, we can not guarantee that
4726 pseudo in the substitution was not reloaded which might
4727 make equivalence invalid. For example, in reverse
4734 the memory address register was reloaded before the 2nd
4736 if ((! first_p
&& pseudo_p
)
4737 /* We don't use DF for compilation speed sake. So it
4738 is problematic to update live info when we use an
4739 equivalence containing pseudos in more than one
4741 || (pseudo_p
&& multi_block_pseudo_p (i
))
4742 /* If an init insn was deleted for some reason, cancel
4743 the equiv. We could update the equiv insns after
4744 transformations including an equiv insn deletion
4745 but it is not worthy as such cases are extremely
4747 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4748 /* If it is not a reverse equivalence, we check that a
4749 pseudo in rhs of the init insn is not dying in the
4750 insn. Otherwise, the live info at the beginning of
4751 the corresponding BB might be wrong after we
4752 removed the insn. When the equiv can be a
4753 constant, the right hand side of the init insn can
4755 || (! reverse_equiv_p (i
)
4756 && (init_insn_rhs_dead_pseudo_p (i
)
4757 /* If we reloaded the pseudo in an equivalence
4758 init insn, we can not remove the equiv init
4759 insns and the init insns might write into
4760 const memory in this case. */
4761 || contains_reloaded_insn_p (i
)))
4762 /* Prevent access beyond equivalent memory for
4763 paradoxical subregs. */
4765 && maybe_gt (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
),
4766 GET_MODE_SIZE (GET_MODE (x
))))
4767 || (pic_offset_table_rtx
4768 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4769 && (targetm
.preferred_reload_class
4770 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4771 || contains_symbol_ref_p (x
))))
4772 ira_reg_equiv
[i
].defined_p
= false;
4773 if (contains_reg_p (x
, false, true))
4774 ira_reg_equiv
[i
].profitable_p
= false;
4775 if (get_equiv (reg
) != reg
)
4776 bitmap_ior_into (equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4779 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4781 /* We should add all insns containing pseudos which should be
4782 substituted by their equivalences. */
4783 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap
, 0, uid
, bi
)
4784 lra_push_insn_by_uid (uid
);
4785 min_len
= lra_insn_stack_length ();
4789 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4791 curr_insn
= lra_pop_insn ();
4793 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4794 if (curr_bb
!= last_bb
)
4797 bb_reload_num
= lra_curr_reload_num
;
4799 if (min_len
> new_min_len
)
4801 min_len
= new_min_len
;
4804 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4806 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4807 MAX_RELOAD_INSNS_NUMBER
);
4809 if (DEBUG_INSN_P (curr_insn
))
4811 /* We need to check equivalence in debug insn and change
4812 pseudo to the equivalent value if necessary. */
4813 curr_id
= lra_get_insn_recog_data (curr_insn
);
4814 if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4816 rtx old
= *curr_id
->operand_loc
[0];
4817 *curr_id
->operand_loc
[0]
4818 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4819 loc_equivalence_callback
, curr_insn
);
4820 if (old
!= *curr_id
->operand_loc
[0])
4822 lra_update_insn_regno_info (curr_insn
);
4827 else if (INSN_P (curr_insn
))
4829 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4831 dest_reg
= SET_DEST (set
);
4832 /* The equivalence pseudo could be set up as SUBREG in a
4833 case when it is a call restore insn in a mode
4834 different from the pseudo mode. */
4835 if (GET_CODE (dest_reg
) == SUBREG
)
4836 dest_reg
= SUBREG_REG (dest_reg
);
4837 if ((REG_P (dest_reg
)
4838 && (x
= get_equiv (dest_reg
)) != dest_reg
4839 /* Remove insns which set up a pseudo whose value
4840 can not be changed. Such insns might be not in
4841 init_insns because we don't update equiv data
4842 during insn transformations.
4844 As an example, let suppose that a pseudo got
4845 hard register and on the 1st pass was not
4846 changed to equivalent constant. We generate an
4847 additional insn setting up the pseudo because of
4848 secondary memory movement. Then the pseudo is
4849 spilled and we use the equiv constant. In this
4850 case we should remove the additional insn and
4851 this insn is not init_insns list. */
4852 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4853 /* Check that this is actually an insn setting
4854 up the equivalence. */
4855 || in_list_p (curr_insn
,
4857 [REGNO (dest_reg
)].init_insns
)))
4858 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4859 && in_list_p (curr_insn
,
4861 [REGNO (SET_SRC (set
))].init_insns
)))
4863 /* This is equiv init insn of pseudo which did not get a
4864 hard register -- remove the insn. */
4865 if (lra_dump_file
!= NULL
)
4867 fprintf (lra_dump_file
,
4868 " Removing equiv init insn %i (freq=%d)\n",
4869 INSN_UID (curr_insn
),
4870 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4871 dump_insn_slim (lra_dump_file
, curr_insn
);
4873 if (contains_reg_p (x
, true, false))
4874 lra_risky_transformations_p
= true;
4875 lra_set_insn_deleted (curr_insn
);
4879 curr_id
= lra_get_insn_recog_data (curr_insn
);
4880 curr_static_id
= curr_id
->insn_static_data
;
4881 init_curr_insn_input_reloads ();
4882 init_curr_operand_mode ();
4883 if (curr_insn_transform (false))
4885 /* Check non-transformed insns too for equiv change as USE
4886 or CLOBBER don't need reloads but can contain pseudos
4887 being changed on their equivalences. */
4888 else if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
))
4889 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4891 lra_update_insn_regno_info (curr_insn
);
4897 /* If we used a new hard regno, changed_p should be true because the
4898 hard reg is assigned to a new pseudo. */
4899 if (flag_checking
&& !changed_p
)
4901 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4902 if (lra_reg_info
[i
].nrefs
!= 0
4903 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4905 int j
, nregs
= hard_regno_nregs (hard_regno
,
4906 PSEUDO_REGNO_MODE (i
));
4908 for (j
= 0; j
< nregs
; j
++)
4909 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4915 static void initiate_invariants (void);
4916 static void finish_invariants (void);
4918 /* Initiate the LRA constraint pass. It is done once per
4921 lra_constraints_init (void)
4923 initiate_invariants ();
4926 /* Finalize the LRA constraint pass. It is done once per
4929 lra_constraints_finish (void)
4931 finish_invariants ();
4936 /* Structure describes invariants for ineheritance. */
4937 struct lra_invariant
4939 /* The order number of the invariant. */
4941 /* The invariant RTX. */
4943 /* The origin insn of the invariant. */
4947 typedef lra_invariant invariant_t
;
4948 typedef invariant_t
*invariant_ptr_t
;
4949 typedef const invariant_t
*const_invariant_ptr_t
;
4951 /* Pointer to the inheritance invariants. */
4952 static vec
<invariant_ptr_t
> invariants
;
4954 /* Allocation pool for the invariants. */
4955 static object_allocator
<lra_invariant
> *invariants_pool
;
4957 /* Hash table for the invariants. */
4958 static htab_t invariant_table
;
4960 /* Hash function for INVARIANT. */
4962 invariant_hash (const void *invariant
)
4964 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
4965 return lra_rtx_hash (inv
);
4968 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
4970 invariant_eq_p (const void *invariant1
, const void *invariant2
)
4972 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
4973 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
4975 return rtx_equal_p (inv1
, inv2
);
4978 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
4979 invariant which is in the table. */
4980 static invariant_ptr_t
4981 insert_invariant (rtx invariant_rtx
)
4984 invariant_t invariant
;
4985 invariant_ptr_t invariant_ptr
;
4987 invariant
.invariant_rtx
= invariant_rtx
;
4988 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
4989 if (*entry_ptr
== NULL
)
4991 invariant_ptr
= invariants_pool
->allocate ();
4992 invariant_ptr
->invariant_rtx
= invariant_rtx
;
4993 invariant_ptr
->insn
= NULL
;
4994 invariants
.safe_push (invariant_ptr
);
4995 *entry_ptr
= (void *) invariant_ptr
;
4997 return (invariant_ptr_t
) *entry_ptr
;
5000 /* Initiate the invariant table. */
5002 initiate_invariants (void)
5004 invariants
.create (100);
5006 = new object_allocator
<lra_invariant
> ("Inheritance invariants");
5007 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
5010 /* Finish the invariant table. */
5012 finish_invariants (void)
5014 htab_delete (invariant_table
);
5015 delete invariants_pool
;
5016 invariants
.release ();
5019 /* Make the invariant table empty. */
5021 clear_invariants (void)
5023 htab_empty (invariant_table
);
5024 invariants_pool
->release ();
5025 invariants
.truncate (0);
5030 /* This page contains code to do inheritance/split
5033 /* Number of reloads passed so far in current EBB. */
5034 static int reloads_num
;
5036 /* Number of calls passed so far in current EBB. */
5037 static int calls_num
;
5039 /* Current reload pseudo check for validity of elements in
5041 static int curr_usage_insns_check
;
5043 /* Info about last usage of registers in EBB to do inheritance/split
5044 transformation. Inheritance transformation is done from a spilled
5045 pseudo and split transformations from a hard register or a pseudo
5046 assigned to a hard register. */
5049 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5050 value INSNS is valid. The insns is chain of optional debug insns
5051 and a finishing non-debug insn using the corresponding reg. The
5052 value is also used to mark the registers which are set up in the
5053 current insn. The negated insn uid is used for this. */
5055 /* Value of global reloads_num at the last insn in INSNS. */
5057 /* Value of global reloads_nums at the last insn in INSNS. */
5059 /* It can be true only for splitting. And it means that the restore
5060 insn should be put after insn given by the following member. */
5062 /* Next insns in the current EBB which use the original reg and the
5063 original reg value is not changed between the current insn and
5064 the next insns. In order words, e.g. for inheritance, if we need
5065 to use the original reg value again in the next insns we can try
5066 to use the value in a hard register from a reload insn of the
5071 /* Map: regno -> corresponding pseudo usage insns. */
5072 static struct usage_insns
*usage_insns
;
5075 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
5077 usage_insns
[regno
].check
= curr_usage_insns_check
;
5078 usage_insns
[regno
].insns
= insn
;
5079 usage_insns
[regno
].reloads_num
= reloads_num
;
5080 usage_insns
[regno
].calls_num
= calls_num
;
5081 usage_insns
[regno
].after_p
= after_p
;
5084 /* The function is used to form list REGNO usages which consists of
5085 optional debug insns finished by a non-debug insn using REGNO.
5086 RELOADS_NUM is current number of reload insns processed so far. */
5088 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
5090 rtx next_usage_insns
;
5092 if (usage_insns
[regno
].check
== curr_usage_insns_check
5093 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
5094 && DEBUG_INSN_P (insn
))
5096 /* Check that we did not add the debug insn yet. */
5097 if (next_usage_insns
!= insn
5098 && (GET_CODE (next_usage_insns
) != INSN_LIST
5099 || XEXP (next_usage_insns
, 0) != insn
))
5100 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
5103 else if (NONDEBUG_INSN_P (insn
))
5104 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
5106 usage_insns
[regno
].check
= 0;
5109 /* Return first non-debug insn in list USAGE_INSNS. */
5111 skip_usage_debug_insns (rtx usage_insns
)
5115 /* Skip debug insns. */
5116 for (insn
= usage_insns
;
5117 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
5118 insn
= XEXP (insn
, 1))
5120 return safe_as_a
<rtx_insn
*> (insn
);
5123 /* Return true if we need secondary memory moves for insn in
5124 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5127 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
5128 rtx usage_insns ATTRIBUTE_UNUSED
)
5134 if (inher_cl
== ALL_REGS
5135 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
5137 lra_assert (INSN_P (insn
));
5138 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
5140 dest
= SET_DEST (set
);
5143 lra_assert (inher_cl
!= NO_REGS
);
5144 cl
= get_reg_class (REGNO (dest
));
5145 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
5146 && targetm
.secondary_memory_needed (GET_MODE (dest
), inher_cl
, cl
));
5149 /* Registers involved in inheritance/split in the current EBB
5150 (inheritance/split pseudos and original registers). */
5151 static bitmap_head check_only_regs
;
5153 /* Reload pseudos can not be involded in invariant inheritance in the
5155 static bitmap_head invalid_invariant_regs
;
5157 /* Do inheritance transformations for insn INSN, which defines (if
5158 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5159 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5160 form as the "insns" field of usage_insns. Return true if we
5161 succeed in such transformation.
5163 The transformations look like:
5166 ... p <- i (new insn)
5168 <- ... p ... <- ... i ...
5170 ... i <- p (new insn)
5171 <- ... p ... <- ... i ...
5173 <- ... p ... <- ... i ...
5174 where p is a spilled original pseudo and i is a new inheritance pseudo.
5177 The inheritance pseudo has the smallest class of two classes CL and
5178 class of ORIGINAL REGNO. */
5180 inherit_reload_reg (bool def_p
, int original_regno
,
5181 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
5183 if (optimize_function_for_size_p (cfun
))
5186 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
5187 rtx original_reg
= regno_reg_rtx
[original_regno
];
5188 rtx new_reg
, usage_insn
;
5189 rtx_insn
*new_insns
;
5191 lra_assert (! usage_insns
[original_regno
].after_p
);
5192 if (lra_dump_file
!= NULL
)
5193 fprintf (lra_dump_file
,
5194 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5195 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5197 if (lra_dump_file
!= NULL
)
5199 fprintf (lra_dump_file
,
5200 " Rejecting inheritance for %d "
5201 "because of disjoint classes %s and %s\n",
5202 original_regno
, reg_class_names
[cl
],
5203 reg_class_names
[rclass
]);
5204 fprintf (lra_dump_file
,
5205 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5209 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5210 /* We don't use a subset of two classes because it can be
5211 NO_REGS. This transformation is still profitable in most
5212 cases even if the classes are not intersected as register
5213 move is probably cheaper than a memory load. */
5214 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5216 if (lra_dump_file
!= NULL
)
5217 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5218 reg_class_names
[cl
], reg_class_names
[rclass
]);
5222 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5224 /* Reject inheritance resulting in secondary memory moves.
5225 Otherwise, there is a danger in LRA cycling. Also such
5226 transformation will be unprofitable. */
5227 if (lra_dump_file
!= NULL
)
5229 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5230 rtx set
= single_set (insn
);
5232 lra_assert (set
!= NULL_RTX
);
5234 rtx dest
= SET_DEST (set
);
5236 lra_assert (REG_P (dest
));
5237 fprintf (lra_dump_file
,
5238 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5239 "as secondary mem is needed\n",
5240 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5241 original_regno
, reg_class_names
[rclass
]);
5242 fprintf (lra_dump_file
,
5243 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5247 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5248 rclass
, "inheritance");
5251 lra_emit_move (original_reg
, new_reg
);
5253 lra_emit_move (new_reg
, original_reg
);
5254 new_insns
= get_insns ();
5256 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5258 if (lra_dump_file
!= NULL
)
5260 fprintf (lra_dump_file
,
5261 " Rejecting inheritance %d->%d "
5262 "as it results in 2 or more insns:\n",
5263 original_regno
, REGNO (new_reg
));
5264 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5265 fprintf (lra_dump_file
,
5266 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5270 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5271 lra_update_insn_regno_info (insn
);
5273 /* We now have a new usage insn for original regno. */
5274 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5275 if (lra_dump_file
!= NULL
)
5276 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5277 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5278 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5279 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5280 bitmap_set_bit (&check_only_regs
, original_regno
);
5281 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5283 lra_process_new_insns (insn
, NULL
, new_insns
,
5284 "Add original<-inheritance");
5286 lra_process_new_insns (insn
, new_insns
, NULL
,
5287 "Add inheritance<-original");
5288 while (next_usage_insns
!= NULL_RTX
)
5290 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5292 usage_insn
= next_usage_insns
;
5293 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5294 next_usage_insns
= NULL
;
5298 usage_insn
= XEXP (next_usage_insns
, 0);
5299 lra_assert (DEBUG_INSN_P (usage_insn
));
5300 next_usage_insns
= XEXP (next_usage_insns
, 1);
5302 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5303 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5304 if (lra_dump_file
!= NULL
)
5306 basic_block bb
= BLOCK_FOR_INSN (usage_insn
);
5307 fprintf (lra_dump_file
,
5308 " Inheritance reuse change %d->%d (bb%d):\n",
5309 original_regno
, REGNO (new_reg
),
5310 bb
? bb
->index
: -1);
5311 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5314 if (lra_dump_file
!= NULL
)
5315 fprintf (lra_dump_file
,
5316 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5320 /* Return true if we need a caller save/restore for pseudo REGNO which
5321 was assigned to a hard register. */
5323 need_for_call_save_p (int regno
)
5325 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5326 return (usage_insns
[regno
].calls_num
< calls_num
5327 && (overlaps_hard_reg_set_p
5329 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
5330 ? lra_reg_info
[regno
].actual_call_used_reg_set
5331 : call_used_reg_set
,
5332 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
5333 || (targetm
.hard_regno_call_part_clobbered
5334 (reg_renumber
[regno
], PSEUDO_REGNO_MODE (regno
)))));
5337 /* Global registers occurring in the current EBB. */
5338 static bitmap_head ebb_global_regs
;
5340 /* Return true if we need a split for hard register REGNO or pseudo
5341 REGNO which was assigned to a hard register.
5342 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5343 used for reloads since the EBB end. It is an approximation of the
5344 used hard registers in the split range. The exact value would
5345 require expensive calculations. If we were aggressive with
5346 splitting because of the approximation, the split pseudo will save
5347 the same hard register assignment and will be removed in the undo
5348 pass. We still need the approximation because too aggressive
5349 splitting would result in too inaccurate cost calculation in the
5350 assignment pass because of too many generated moves which will be
5351 probably removed in the undo pass. */
5353 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5355 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5357 lra_assert (hard_regno
>= 0);
5358 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5359 /* Don't split eliminable hard registers, otherwise we can
5360 split hard registers like hard frame pointer, which
5361 lives on BB start/end according to DF-infrastructure,
5362 when there is a pseudo assigned to the register and
5363 living in the same BB. */
5364 && (regno
>= FIRST_PSEUDO_REGISTER
5365 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5366 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5367 /* Don't split call clobbered hard regs living through
5368 calls, otherwise we might have a check problem in the
5369 assign sub-pass as in the most cases (exception is a
5370 situation when lra_risky_transformations_p value is
5371 true) the assign pass assumes that all pseudos living
5372 through calls are assigned to call saved hard regs. */
5373 && (regno
>= FIRST_PSEUDO_REGISTER
5374 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
5375 || usage_insns
[regno
].calls_num
== calls_num
)
5376 /* We need at least 2 reloads to make pseudo splitting
5377 profitable. We should provide hard regno splitting in
5378 any case to solve 1st insn scheduling problem when
5379 moving hard register definition up might result in
5380 impossibility to find hard register for reload pseudo of
5381 small register class. */
5382 && (usage_insns
[regno
].reloads_num
5383 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
5384 && (regno
< FIRST_PSEUDO_REGISTER
5385 /* For short living pseudos, spilling + inheritance can
5386 be considered a substitution for splitting.
5387 Therefore we do not splitting for local pseudos. It
5388 decreases also aggressiveness of splitting. The
5389 minimal number of references is chosen taking into
5390 account that for 2 references splitting has no sense
5391 as we can just spill the pseudo. */
5392 || (regno
>= FIRST_PSEUDO_REGISTER
5393 && lra_reg_info
[regno
].nrefs
> 3
5394 && bitmap_bit_p (&ebb_global_regs
, regno
))))
5395 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
5398 /* Return class for the split pseudo created from original pseudo with
5399 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5400 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5401 results in no secondary memory movements. */
5402 static enum reg_class
5403 choose_split_class (enum reg_class allocno_class
,
5404 int hard_regno ATTRIBUTE_UNUSED
,
5405 machine_mode mode ATTRIBUTE_UNUSED
)
5408 enum reg_class cl
, best_cl
= NO_REGS
;
5409 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5410 = REGNO_REG_CLASS (hard_regno
);
5412 if (! targetm
.secondary_memory_needed (mode
, allocno_class
, allocno_class
)
5413 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
5414 return allocno_class
;
5416 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
5418 if (! targetm
.secondary_memory_needed (mode
, cl
, hard_reg_class
)
5419 && ! targetm
.secondary_memory_needed (mode
, hard_reg_class
, cl
)
5420 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
5421 && (best_cl
== NO_REGS
5422 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
5427 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5428 It only makes sense to call this function if NEW_REGNO is always
5429 equal to ORIGINAL_REGNO. */
5432 lra_copy_reg_equiv (unsigned int new_regno
, unsigned int original_regno
)
5434 if (!ira_reg_equiv
[original_regno
].defined_p
)
5437 ira_expand_reg_equiv ();
5438 ira_reg_equiv
[new_regno
].defined_p
= true;
5439 if (ira_reg_equiv
[original_regno
].memory
)
5440 ira_reg_equiv
[new_regno
].memory
5441 = copy_rtx (ira_reg_equiv
[original_regno
].memory
);
5442 if (ira_reg_equiv
[original_regno
].constant
)
5443 ira_reg_equiv
[new_regno
].constant
5444 = copy_rtx (ira_reg_equiv
[original_regno
].constant
);
5445 if (ira_reg_equiv
[original_regno
].invariant
)
5446 ira_reg_equiv
[new_regno
].invariant
5447 = copy_rtx (ira_reg_equiv
[original_regno
].invariant
);
5450 /* Do split transformations for insn INSN, which defines or uses
5451 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5452 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5453 "insns" field of usage_insns.
5455 The transformations look like:
5458 ... s <- p (new insn -- save)
5460 ... p <- s (new insn -- restore)
5461 <- ... p ... <- ... p ...
5463 <- ... p ... <- ... p ...
5464 ... s <- p (new insn -- save)
5466 ... p <- s (new insn -- restore)
5467 <- ... p ... <- ... p ...
5469 where p is an original pseudo got a hard register or a hard
5470 register and s is a new split pseudo. The save is put before INSN
5471 if BEFORE_P is true. Return true if we succeed in such
5474 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
5475 rtx next_usage_insns
)
5477 enum reg_class rclass
;
5479 int hard_regno
, nregs
;
5480 rtx new_reg
, usage_insn
;
5481 rtx_insn
*restore
, *save
;
5486 if (original_regno
< FIRST_PSEUDO_REGISTER
)
5488 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
5489 hard_regno
= original_regno
;
5490 call_save_p
= false;
5492 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
5493 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
5494 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5495 as part of a multi-word register. In that case, or if the biggest
5496 mode was larger than a register, just use the reg_rtx. Otherwise,
5497 limit the size to that of the biggest access in the function. */
5498 if (mode
== VOIDmode
5499 || paradoxical_subreg_p (mode
, reg_rtx_mode
))
5501 original_reg
= regno_reg_rtx
[hard_regno
];
5502 mode
= reg_rtx_mode
;
5505 original_reg
= gen_rtx_REG (mode
, hard_regno
);
5509 mode
= PSEUDO_REGNO_MODE (original_regno
);
5510 hard_regno
= reg_renumber
[original_regno
];
5511 nregs
= hard_regno_nregs (hard_regno
, mode
);
5512 rclass
= lra_get_allocno_class (original_regno
);
5513 original_reg
= regno_reg_rtx
[original_regno
];
5514 call_save_p
= need_for_call_save_p (original_regno
);
5516 lra_assert (hard_regno
>= 0);
5517 if (lra_dump_file
!= NULL
)
5518 fprintf (lra_dump_file
,
5519 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5523 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
5524 hard_regno_nregs (hard_regno
, mode
),
5526 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
5530 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
5531 if (rclass
== NO_REGS
)
5533 if (lra_dump_file
!= NULL
)
5535 fprintf (lra_dump_file
,
5536 " Rejecting split of %d(%s): "
5537 "no good reg class for %d(%s)\n",
5539 reg_class_names
[lra_get_allocno_class (original_regno
)],
5541 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
5544 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5548 /* Split_if_necessary can split hard registers used as part of a
5549 multi-register mode but splits each register individually. The
5550 mode used for each independent register may not be supported
5551 so reject the split. Splitting the wider mode should theoretically
5552 be possible but is not implemented. */
5553 if (!targetm
.hard_regno_mode_ok (hard_regno
, mode
))
5555 if (lra_dump_file
!= NULL
)
5557 fprintf (lra_dump_file
,
5558 " Rejecting split of %d(%s): unsuitable mode %s\n",
5560 reg_class_names
[lra_get_allocno_class (original_regno
)],
5561 GET_MODE_NAME (mode
));
5564 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5568 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, "split");
5569 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
5571 int new_regno
= REGNO (new_reg
);
5572 save
= emit_spill_move (true, new_reg
, original_reg
);
5573 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
5575 if (lra_dump_file
!= NULL
)
5579 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5580 original_regno
, new_regno
);
5581 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
5582 fprintf (lra_dump_file
,
5583 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5587 restore
= emit_spill_move (false, new_reg
, original_reg
);
5588 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
5590 if (lra_dump_file
!= NULL
)
5592 fprintf (lra_dump_file
,
5593 " Rejecting split %d->%d "
5594 "resulting in > 2 restore insns:\n",
5595 original_regno
, new_regno
);
5596 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
5597 fprintf (lra_dump_file
,
5598 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5602 /* Transfer equivalence information to the spill register, so that
5603 if we fail to allocate the spill register, we have the option of
5604 rematerializing the original value instead of spilling to the stack. */
5605 if (!HARD_REGISTER_NUM_P (original_regno
)
5606 && mode
== PSEUDO_REGNO_MODE (original_regno
))
5607 lra_copy_reg_equiv (new_regno
, original_regno
);
5608 after_p
= usage_insns
[original_regno
].after_p
;
5609 lra_reg_info
[new_regno
].restore_rtx
= regno_reg_rtx
[original_regno
];
5610 bitmap_set_bit (&check_only_regs
, new_regno
);
5611 bitmap_set_bit (&check_only_regs
, original_regno
);
5612 bitmap_set_bit (&lra_split_regs
, new_regno
);
5615 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5617 usage_insn
= next_usage_insns
;
5620 usage_insn
= XEXP (next_usage_insns
, 0);
5621 lra_assert (DEBUG_INSN_P (usage_insn
));
5622 next_usage_insns
= XEXP (next_usage_insns
, 1);
5623 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5624 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5625 if (lra_dump_file
!= NULL
)
5627 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5628 original_regno
, new_regno
);
5629 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5632 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5633 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5634 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5635 after_p
? NULL
: restore
,
5636 after_p
? restore
: NULL
,
5638 ? "Add reg<-save" : "Add reg<-split");
5639 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5640 before_p
? NULL
: save
,
5642 ? "Add save<-reg" : "Add split<-reg");
5644 /* If we are trying to split multi-register. We should check
5645 conflicts on the next assignment sub-pass. IRA can allocate on
5646 sub-register levels, LRA do this on pseudos level right now and
5647 this discrepancy may create allocation conflicts after
5649 lra_risky_transformations_p
= true;
5650 if (lra_dump_file
!= NULL
)
5651 fprintf (lra_dump_file
,
5652 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5656 /* Recognize that we need a split transformation for insn INSN, which
5657 defines or uses REGNO in its insn biggest MODE (we use it only if
5658 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5659 hard registers which might be used for reloads since the EBB end.
5660 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5661 uid before starting INSN processing. Return true if we succeed in
5662 such transformation. */
5664 split_if_necessary (int regno
, machine_mode mode
,
5665 HARD_REG_SET potential_reload_hard_regs
,
5666 bool before_p
, rtx_insn
*insn
, int max_uid
)
5670 rtx next_usage_insns
;
5672 if (regno
< FIRST_PSEUDO_REGISTER
)
5673 nregs
= hard_regno_nregs (regno
, mode
);
5674 for (i
= 0; i
< nregs
; i
++)
5675 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5676 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5677 /* To avoid processing the register twice or more. */
5678 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5679 && INSN_UID (next_usage_insns
) < max_uid
)
5680 || (GET_CODE (next_usage_insns
) == INSN_LIST
5681 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5682 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5683 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
5688 /* Return TRUE if rtx X is considered as an invariant for
5691 invariant_p (const_rtx x
)
5698 code
= GET_CODE (x
);
5699 mode
= GET_MODE (x
);
5703 code
= GET_CODE (x
);
5704 mode
= wider_subreg_mode (mode
, GET_MODE (x
));
5712 int i
, nregs
, regno
= REGNO (x
);
5714 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
5715 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
5716 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
5718 nregs
= hard_regno_nregs (regno
, mode
);
5719 for (i
= 0; i
< nregs
; i
++)
5720 if (! fixed_regs
[regno
+ i
]
5721 /* A hard register may be clobbered in the current insn
5722 but we can ignore this case because if the hard
5723 register is used it should be set somewhere after the
5725 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
5728 fmt
= GET_RTX_FORMAT (code
);
5729 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5733 if (! invariant_p (XEXP (x
, i
)))
5736 else if (fmt
[i
] == 'E')
5738 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5739 if (! invariant_p (XVECEXP (x
, i
, j
)))
5746 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
5747 inheritance transformation (using dest_reg instead invariant in a
5748 subsequent insn). */
5750 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
5752 invariant_ptr_t invariant_ptr
;
5753 rtx_insn
*insn
, *new_insns
;
5754 rtx insn_set
, insn_reg
, new_reg
;
5756 bool succ_p
= false;
5757 int dst_regno
= REGNO (dst_reg
);
5758 machine_mode dst_mode
= GET_MODE (dst_reg
);
5759 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
5761 invariant_ptr
= insert_invariant (invariant_rtx
);
5762 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
5764 /* We have a subsequent insn using the invariant. */
5765 insn_set
= single_set (insn
);
5766 lra_assert (insn_set
!= NULL
);
5767 insn_reg
= SET_DEST (insn_set
);
5768 lra_assert (REG_P (insn_reg
));
5769 insn_regno
= REGNO (insn_reg
);
5770 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
5772 if (dst_mode
== GET_MODE (insn_reg
)
5773 /* We should consider only result move reg insns which are
5775 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
5776 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
5778 if (lra_dump_file
!= NULL
)
5779 fprintf (lra_dump_file
,
5780 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
5781 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
,
5782 cl
, "invariant inheritance");
5783 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5784 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5785 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
5787 lra_emit_move (new_reg
, dst_reg
);
5788 new_insns
= get_insns ();
5790 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
5791 "Add invariant inheritance<-original");
5793 lra_emit_move (SET_DEST (insn_set
), new_reg
);
5794 new_insns
= get_insns ();
5796 lra_process_new_insns (insn
, NULL
, new_insns
,
5797 "Changing reload<-inheritance");
5798 lra_set_insn_deleted (insn
);
5800 if (lra_dump_file
!= NULL
)
5802 fprintf (lra_dump_file
,
5803 " Invariant inheritance reuse change %d (bb%d):\n",
5804 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5805 dump_insn_slim (lra_dump_file
, insn
);
5806 fprintf (lra_dump_file
,
5807 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
5811 invariant_ptr
->insn
= curr_insn
;
5815 /* Check only registers living at the current program point in the
5817 static bitmap_head live_regs
;
5819 /* Update live info in EBB given by its HEAD and TAIL insns after
5820 inheritance/split transformation. The function removes dead moves
5823 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5828 rtx_insn
*prev_insn
;
5831 basic_block last_bb
, prev_bb
, curr_bb
;
5833 struct lra_insn_reg
*reg
;
5837 last_bb
= BLOCK_FOR_INSN (tail
);
5839 for (curr_insn
= tail
;
5840 curr_insn
!= PREV_INSN (head
);
5841 curr_insn
= prev_insn
)
5843 prev_insn
= PREV_INSN (curr_insn
);
5844 /* We need to process empty blocks too. They contain
5845 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5846 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5848 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5849 if (curr_bb
!= prev_bb
)
5851 if (prev_bb
!= NULL
)
5853 /* Update df_get_live_in (prev_bb): */
5854 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5855 if (bitmap_bit_p (&live_regs
, j
))
5856 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5858 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5860 if (curr_bb
!= last_bb
)
5862 /* Update df_get_live_out (curr_bb): */
5863 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5865 live_p
= bitmap_bit_p (&live_regs
, j
);
5867 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5868 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5874 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5876 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5880 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5882 if (! NONDEBUG_INSN_P (curr_insn
))
5884 curr_id
= lra_get_insn_recog_data (curr_insn
);
5885 curr_static_id
= curr_id
->insn_static_data
;
5887 if ((set
= single_set (curr_insn
)) != NULL_RTX
5888 && REG_P (SET_DEST (set
))
5889 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5890 && SET_DEST (set
) != pic_offset_table_rtx
5891 && bitmap_bit_p (&check_only_regs
, regno
)
5892 && ! bitmap_bit_p (&live_regs
, regno
))
5894 /* See which defined values die here. */
5895 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5896 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5897 bitmap_clear_bit (&live_regs
, reg
->regno
);
5898 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5899 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5900 bitmap_clear_bit (&live_regs
, reg
->regno
);
5901 if (curr_id
->arg_hard_regs
!= NULL
)
5902 /* Make clobbered argument hard registers die. */
5903 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5904 if (regno
>= FIRST_PSEUDO_REGISTER
)
5905 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
5906 /* Mark each used value as live. */
5907 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5908 if (reg
->type
!= OP_OUT
5909 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5910 bitmap_set_bit (&live_regs
, reg
->regno
);
5911 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5912 if (reg
->type
!= OP_OUT
5913 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5914 bitmap_set_bit (&live_regs
, reg
->regno
);
5915 if (curr_id
->arg_hard_regs
!= NULL
)
5916 /* Make used argument hard registers live. */
5917 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5918 if (regno
< FIRST_PSEUDO_REGISTER
5919 && bitmap_bit_p (&check_only_regs
, regno
))
5920 bitmap_set_bit (&live_regs
, regno
);
5921 /* It is quite important to remove dead move insns because it
5922 means removing dead store. We don't need to process them for
5926 if (lra_dump_file
!= NULL
)
5928 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5929 dump_insn_slim (lra_dump_file
, curr_insn
);
5931 lra_set_insn_deleted (curr_insn
);
5936 /* The structure describes info to do an inheritance for the current
5937 insn. We need to collect such info first before doing the
5938 transformations because the transformations change the insn
5939 internal representation. */
5942 /* Original regno. */
5944 /* Subsequent insns which can inherit original reg value. */
5948 /* Array containing all info for doing inheritance from the current
5950 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5952 /* Number elements in the previous array. */
5953 static int to_inherit_num
;
5955 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5956 structure to_inherit. */
5958 add_to_inherit (int regno
, rtx insns
)
5962 for (i
= 0; i
< to_inherit_num
; i
++)
5963 if (to_inherit
[i
].regno
== regno
)
5965 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5966 to_inherit
[to_inherit_num
].regno
= regno
;
5967 to_inherit
[to_inherit_num
++].insns
= insns
;
5970 /* Return the last non-debug insn in basic block BB, or the block begin
5973 get_last_insertion_point (basic_block bb
)
5977 FOR_BB_INSNS_REVERSE (bb
, insn
)
5978 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5983 /* Set up RES by registers living on edges FROM except the edge (FROM,
5984 TO) or by registers set up in a jump insn in BB FROM. */
5986 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5989 struct lra_insn_reg
*reg
;
5993 lra_assert (to
!= NULL
);
5995 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5997 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5998 last
= get_last_insertion_point (from
);
5999 if (! JUMP_P (last
))
6001 curr_id
= lra_get_insn_recog_data (last
);
6002 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6003 if (reg
->type
!= OP_IN
)
6004 bitmap_set_bit (res
, reg
->regno
);
6007 /* Used as a temporary results of some bitmap calculations. */
6008 static bitmap_head temp_bitmap
;
6010 /* We split for reloads of small class of hard regs. The following
6011 defines how many hard regs the class should have to be qualified as
6012 small. The code is mostly oriented to x86/x86-64 architecture
6013 where some insns need to use only specific register or pair of
6014 registers and these register can live in RTL explicitly, e.g. for
6015 parameter passing. */
6016 static const int max_small_class_regs_num
= 2;
6018 /* Do inheritance/split transformations in EBB starting with HEAD and
6019 finishing on TAIL. We process EBB insns in the reverse order.
6020 Return true if we did any inheritance/split transformation in the
6023 We should avoid excessive splitting which results in worse code
6024 because of inaccurate cost calculations for spilling new split
6025 pseudos in such case. To achieve this we do splitting only if
6026 register pressure is high in given basic block and there are reload
6027 pseudos requiring hard registers. We could do more register
6028 pressure calculations at any given program point to avoid necessary
6029 splitting even more but it is to expensive and the current approach
6030 works well enough. */
6032 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
6034 int i
, src_regno
, dst_regno
, nregs
;
6035 bool change_p
, succ_p
, update_reloads_num_p
;
6036 rtx_insn
*prev_insn
, *last_insn
;
6037 rtx next_usage_insns
, curr_set
;
6039 struct lra_insn_reg
*reg
;
6040 basic_block last_processed_bb
, curr_bb
= NULL
;
6041 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
6045 bool head_p
, after_p
;
6048 curr_usage_insns_check
++;
6049 clear_invariants ();
6050 reloads_num
= calls_num
= 0;
6051 bitmap_clear (&check_only_regs
);
6052 bitmap_clear (&invalid_invariant_regs
);
6053 last_processed_bb
= NULL
;
6054 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6055 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
6056 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
6057 /* We don't process new insns generated in the loop. */
6058 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
6060 prev_insn
= PREV_INSN (curr_insn
);
6061 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
6062 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6063 if (last_processed_bb
!= curr_bb
)
6065 /* We are at the end of BB. Add qualified living
6066 pseudos for potential splitting. */
6067 to_process
= df_get_live_out (curr_bb
);
6068 if (last_processed_bb
!= NULL
)
6070 /* We are somewhere in the middle of EBB. */
6071 get_live_on_other_edges (curr_bb
, last_processed_bb
,
6073 to_process
= &temp_bitmap
;
6075 last_processed_bb
= curr_bb
;
6076 last_insn
= get_last_insertion_point (curr_bb
);
6077 after_p
= (! JUMP_P (last_insn
)
6078 && (! CALL_P (last_insn
)
6079 || (find_reg_note (last_insn
,
6080 REG_NORETURN
, NULL_RTX
) == NULL_RTX
6081 && ! SIBLING_CALL_P (last_insn
))));
6082 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6083 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6085 if ((int) j
>= lra_constraint_new_regno_start
)
6087 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6089 if (j
< FIRST_PSEUDO_REGISTER
)
6090 SET_HARD_REG_BIT (live_hard_regs
, j
);
6092 add_to_hard_reg_set (&live_hard_regs
,
6093 PSEUDO_REGNO_MODE (j
),
6095 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
6099 src_regno
= dst_regno
= -1;
6100 curr_set
= single_set (curr_insn
);
6101 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
6102 dst_regno
= REGNO (SET_DEST (curr_set
));
6103 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
6104 src_regno
= REGNO (SET_SRC (curr_set
));
6105 update_reloads_num_p
= true;
6106 if (src_regno
< lra_constraint_new_regno_start
6107 && src_regno
>= FIRST_PSEUDO_REGISTER
6108 && reg_renumber
[src_regno
] < 0
6109 && dst_regno
>= lra_constraint_new_regno_start
6110 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
6112 /* 'reload_pseudo <- original_pseudo'. */
6113 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6115 update_reloads_num_p
= false;
6117 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6118 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
6119 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
6120 curr_insn
, next_usage_insns
);
6124 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6125 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6126 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6127 reg_class_contents
[cl
]);
6129 else if (src_regno
< 0
6130 && dst_regno
>= lra_constraint_new_regno_start
6131 && invariant_p (SET_SRC (curr_set
))
6132 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
6133 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
6134 && ! bitmap_bit_p (&invalid_invariant_regs
,
6135 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
6137 /* 'reload_pseudo <- invariant'. */
6138 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6140 update_reloads_num_p
= false;
6141 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
6143 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6144 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6145 reg_class_contents
[cl
]);
6147 else if (src_regno
>= lra_constraint_new_regno_start
6148 && dst_regno
< lra_constraint_new_regno_start
6149 && dst_regno
>= FIRST_PSEUDO_REGISTER
6150 && reg_renumber
[dst_regno
] < 0
6151 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
6152 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6153 && (next_usage_insns
6154 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6156 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6158 update_reloads_num_p
= false;
6159 /* 'original_pseudo <- reload_pseudo'. */
6160 if (! JUMP_P (curr_insn
)
6161 && inherit_reload_reg (true, dst_regno
, cl
,
6162 curr_insn
, next_usage_insns
))
6165 usage_insns
[dst_regno
].check
= 0;
6166 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6167 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6168 reg_class_contents
[cl
]);
6170 else if (INSN_P (curr_insn
))
6173 int max_uid
= get_max_uid ();
6175 curr_id
= lra_get_insn_recog_data (curr_insn
);
6176 curr_static_id
= curr_id
->insn_static_data
;
6178 /* Process insn definitions. */
6179 for (iter
= 0; iter
< 2; iter
++)
6180 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6183 if (reg
->type
!= OP_IN
6184 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6186 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
6187 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
6188 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6189 && (next_usage_insns
6190 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6192 struct lra_insn_reg
*r
;
6194 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
6195 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
6197 /* Don't do inheritance if the pseudo is also
6198 used in the insn. */
6200 /* We can not do inheritance right now
6201 because the current insn reg info (chain
6202 regs) can change after that. */
6203 add_to_inherit (dst_regno
, next_usage_insns
);
6205 /* We can not process one reg twice here because of
6206 usage_insns invalidation. */
6207 if ((dst_regno
< FIRST_PSEUDO_REGISTER
6208 || reg_renumber
[dst_regno
] >= 0)
6209 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
6213 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
6214 potential_reload_hard_regs
,
6215 false, curr_insn
, max_uid
))
6217 CLEAR_HARD_REG_SET (s
);
6218 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
6219 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
6221 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
6222 reg_renumber
[dst_regno
]);
6223 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
6225 /* We should invalidate potential inheritance or
6226 splitting for the current insn usages to the next
6227 usage insns (see code below) as the output pseudo
6229 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
6230 && reg_renumber
[dst_regno
] < 0)
6231 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
6232 && (dst_regno
< FIRST_PSEUDO_REGISTER
6233 || reg_renumber
[dst_regno
] >= 0)))
6235 /* Invalidate and mark definitions. */
6236 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6237 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6240 nregs
= hard_regno_nregs (dst_regno
,
6242 for (i
= 0; i
< nregs
; i
++)
6243 usage_insns
[dst_regno
+ i
].check
6244 = -(int) INSN_UID (curr_insn
);
6248 /* Process clobbered call regs. */
6249 if (curr_id
->arg_hard_regs
!= NULL
)
6250 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6251 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6252 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6253 = -(int) INSN_UID (curr_insn
);
6254 if (! JUMP_P (curr_insn
))
6255 for (i
= 0; i
< to_inherit_num
; i
++)
6256 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6257 ALL_REGS
, curr_insn
,
6258 to_inherit
[i
].insns
))
6260 if (CALL_P (curr_insn
))
6262 rtx cheap
, pat
, dest
;
6264 int regno
, hard_regno
;
6267 if ((cheap
= find_reg_note (curr_insn
,
6268 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6269 && ((cheap
= XEXP (cheap
, 0)), true)
6270 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6271 && (hard_regno
= reg_renumber
[regno
]) >= 0
6272 && usage_insns
[regno
].check
== curr_usage_insns_check
6273 /* If there are pending saves/restores, the
6274 optimization is not worth. */
6275 && usage_insns
[regno
].calls_num
== calls_num
- 1
6276 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
6278 /* Restore the pseudo from the call result as
6279 REG_RETURNED note says that the pseudo value is
6280 in the call result and the pseudo is an argument
6282 pat
= PATTERN (curr_insn
);
6283 if (GET_CODE (pat
) == PARALLEL
)
6284 pat
= XVECEXP (pat
, 0, 0);
6285 dest
= SET_DEST (pat
);
6286 /* For multiple return values dest is PARALLEL.
6287 Currently we handle only single return value case. */
6291 emit_move_insn (cheap
, copy_rtx (dest
));
6292 restore
= get_insns ();
6294 lra_process_new_insns (curr_insn
, NULL
, restore
,
6295 "Inserting call parameter restore");
6296 /* We don't need to save/restore of the pseudo from
6298 usage_insns
[regno
].calls_num
= calls_num
;
6299 bitmap_set_bit (&check_only_regs
, regno
);
6304 /* Process insn usages. */
6305 for (iter
= 0; iter
< 2; iter
++)
6306 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6309 if ((reg
->type
!= OP_OUT
6310 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
6311 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6313 if (src_regno
>= FIRST_PSEUDO_REGISTER
6314 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
6316 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6317 && (next_usage_insns
6318 = usage_insns
[src_regno
].insns
) != NULL_RTX
6319 && NONDEBUG_INSN_P (curr_insn
))
6320 add_to_inherit (src_regno
, next_usage_insns
);
6321 else if (usage_insns
[src_regno
].check
6322 != -(int) INSN_UID (curr_insn
))
6323 /* Add usages but only if the reg is not set up
6324 in the same insn. */
6325 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6327 else if (src_regno
< FIRST_PSEUDO_REGISTER
6328 || reg_renumber
[src_regno
] >= 0)
6331 rtx_insn
*use_insn
= curr_insn
;
6333 before_p
= (JUMP_P (curr_insn
)
6334 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
6335 if (NONDEBUG_INSN_P (curr_insn
)
6336 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
6337 && split_if_necessary (src_regno
, reg
->biggest_mode
,
6338 potential_reload_hard_regs
,
6339 before_p
, curr_insn
, max_uid
))
6342 lra_risky_transformations_p
= true;
6345 usage_insns
[src_regno
].check
= 0;
6347 use_insn
= PREV_INSN (curr_insn
);
6349 if (NONDEBUG_INSN_P (curr_insn
))
6351 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6352 add_to_hard_reg_set (&live_hard_regs
,
6353 reg
->biggest_mode
, src_regno
);
6355 add_to_hard_reg_set (&live_hard_regs
,
6356 PSEUDO_REGNO_MODE (src_regno
),
6357 reg_renumber
[src_regno
]);
6359 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
6362 /* Process used call regs. */
6363 if (curr_id
->arg_hard_regs
!= NULL
)
6364 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6365 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6367 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
6368 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6370 for (i
= 0; i
< to_inherit_num
; i
++)
6372 src_regno
= to_inherit
[i
].regno
;
6373 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
6374 curr_insn
, to_inherit
[i
].insns
))
6377 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6380 if (update_reloads_num_p
6381 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
6384 if ((REG_P (SET_DEST (curr_set
))
6385 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
6386 && reg_renumber
[regno
] < 0
6387 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
6388 || (REG_P (SET_SRC (curr_set
))
6389 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
6390 && reg_renumber
[regno
] < 0
6391 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
6393 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6395 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6396 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6397 reg_class_contents
[cl
]);
6400 if (NONDEBUG_INSN_P (curr_insn
))
6404 /* Invalidate invariants with changed regs. */
6405 curr_id
= lra_get_insn_recog_data (curr_insn
);
6406 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6407 if (reg
->type
!= OP_IN
)
6409 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6410 bitmap_set_bit (&invalid_invariant_regs
,
6411 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
6413 curr_static_id
= curr_id
->insn_static_data
;
6414 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6415 if (reg
->type
!= OP_IN
)
6416 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6417 if (curr_id
->arg_hard_regs
!= NULL
)
6418 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6419 if (regno
>= FIRST_PSEUDO_REGISTER
)
6420 bitmap_set_bit (&invalid_invariant_regs
,
6421 regno
- FIRST_PSEUDO_REGISTER
);
6423 /* We reached the start of the current basic block. */
6424 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
6425 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
6427 /* We reached the beginning of the current block -- do
6428 rest of spliting in the current BB. */
6429 to_process
= df_get_live_in (curr_bb
);
6430 if (BLOCK_FOR_INSN (head
) != curr_bb
)
6432 /* We are somewhere in the middle of EBB. */
6433 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
6434 curr_bb
, &temp_bitmap
);
6435 to_process
= &temp_bitmap
;
6438 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6440 if ((int) j
>= lra_constraint_new_regno_start
)
6442 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6443 && usage_insns
[j
].check
== curr_usage_insns_check
6444 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
6446 if (need_for_split_p (potential_reload_hard_regs
, j
))
6448 if (lra_dump_file
!= NULL
&& head_p
)
6450 fprintf (lra_dump_file
,
6451 " ----------------------------------\n");
6454 if (split_reg (false, j
, bb_note (curr_bb
),
6458 usage_insns
[j
].check
= 0;
6466 /* This value affects EBB forming. If probability of edge from EBB to
6467 a BB is not greater than the following value, we don't add the BB
6469 #define EBB_PROBABILITY_CUTOFF \
6470 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
6472 /* Current number of inheritance/split iteration. */
6473 int lra_inheritance_iter
;
6475 /* Entry function for inheritance/split pass. */
6477 lra_inheritance (void)
6480 basic_block bb
, start_bb
;
6483 lra_inheritance_iter
++;
6484 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6486 timevar_push (TV_LRA_INHERITANCE
);
6487 if (lra_dump_file
!= NULL
)
6488 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
6489 lra_inheritance_iter
);
6490 curr_usage_insns_check
= 0;
6491 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
6492 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
6493 usage_insns
[i
].check
= 0;
6494 bitmap_initialize (&check_only_regs
, ®_obstack
);
6495 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
6496 bitmap_initialize (&live_regs
, ®_obstack
);
6497 bitmap_initialize (&temp_bitmap
, ®_obstack
);
6498 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
6499 FOR_EACH_BB_FN (bb
, cfun
)
6502 if (lra_dump_file
!= NULL
)
6503 fprintf (lra_dump_file
, "EBB");
6504 /* Form a EBB starting with BB. */
6505 bitmap_clear (&ebb_global_regs
);
6506 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
6509 if (lra_dump_file
!= NULL
)
6510 fprintf (lra_dump_file
, " %d", bb
->index
);
6511 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
6512 || LABEL_P (BB_HEAD (bb
->next_bb
)))
6514 e
= find_fallthru_edge (bb
->succs
);
6517 if (e
->probability
.initialized_p ()
6518 && e
->probability
.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF
)
6522 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
6523 if (lra_dump_file
!= NULL
)
6524 fprintf (lra_dump_file
, "\n");
6525 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
6526 /* Remember that the EBB head and tail can change in
6528 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
6530 bitmap_clear (&ebb_global_regs
);
6531 bitmap_clear (&temp_bitmap
);
6532 bitmap_clear (&live_regs
);
6533 bitmap_clear (&invalid_invariant_regs
);
6534 bitmap_clear (&check_only_regs
);
6537 timevar_pop (TV_LRA_INHERITANCE
);
6542 /* This page contains code to undo failed inheritance/split
6545 /* Current number of iteration undoing inheritance/split. */
6546 int lra_undo_inheritance_iter
;
6548 /* Fix BB live info LIVE after removing pseudos created on pass doing
6549 inheritance/split which are REMOVED_PSEUDOS. */
6551 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
6556 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
6557 if (bitmap_clear_bit (live
, regno
)
6558 && REG_P (lra_reg_info
[regno
].restore_rtx
))
6559 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
6562 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6567 if (GET_CODE (reg
) == SUBREG
)
6568 reg
= SUBREG_REG (reg
);
6574 /* Delete a move INSN with destination reg DREGNO and a previous
6575 clobber insn with the same regno. The inheritance/split code can
6576 generate moves with preceding clobber and when we delete such moves
6577 we should delete the clobber insn too to keep the correct life
6580 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
6582 rtx_insn
*prev_insn
= PREV_INSN (insn
);
6584 lra_set_insn_deleted (insn
);
6585 lra_assert (dregno
>= 0);
6586 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
6587 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
6588 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
6589 lra_set_insn_deleted (prev_insn
);
6592 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6593 return true if we did any change. The undo transformations for
6594 inheritance looks like
6598 p <- i, i <- p, and i <- i3
6599 where p is original pseudo from which inheritance pseudo i was
6600 created, i and i3 are removed inheritance pseudos, i2 is another
6601 not removed inheritance pseudo. All split pseudos or other
6602 occurrences of removed inheritance pseudos are changed on the
6603 corresponding original pseudos.
6605 The function also schedules insns changed and created during
6606 inheritance/split pass for processing by the subsequent constraint
6609 remove_inheritance_pseudos (bitmap remove_pseudos
)
6612 int regno
, sregno
, prev_sregno
, dregno
;
6615 rtx_insn
*prev_insn
;
6616 bool change_p
, done_p
;
6618 change_p
= ! bitmap_empty_p (remove_pseudos
);
6619 /* We can not finish the function right away if CHANGE_P is true
6620 because we need to marks insns affected by previous
6621 inheritance/split pass for processing by the subsequent
6623 FOR_EACH_BB_FN (bb
, cfun
)
6625 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
6626 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
6627 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
6629 if (! INSN_P (curr_insn
))
6632 sregno
= dregno
= -1;
6633 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
6634 && (set
= single_set (curr_insn
)) != NULL_RTX
)
6636 dregno
= get_regno (SET_DEST (set
));
6637 sregno
= get_regno (SET_SRC (set
));
6640 if (sregno
>= 0 && dregno
>= 0)
6642 if (bitmap_bit_p (remove_pseudos
, dregno
)
6643 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
6645 /* invariant inheritance pseudo <- original pseudo */
6646 if (lra_dump_file
!= NULL
)
6648 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
6649 dump_insn_slim (lra_dump_file
, curr_insn
);
6650 fprintf (lra_dump_file
, "\n");
6652 delete_move_and_clobber (curr_insn
, dregno
);
6655 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6656 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
6658 /* reload pseudo <- invariant inheritance pseudo */
6660 /* We can not just change the source. It might be
6661 an insn different from the move. */
6662 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
6663 rtx_insn
*new_insns
= get_insns ();
6665 lra_assert (single_set (new_insns
) != NULL
6666 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
6667 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6668 "Changing reload<-invariant inheritance");
6669 delete_move_and_clobber (curr_insn
, dregno
);
6672 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
6673 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
6674 || (bitmap_bit_p (remove_pseudos
, dregno
)
6675 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6676 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6677 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
6678 || (bitmap_bit_p (remove_pseudos
, dregno
)
6679 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
6680 /* One of the following cases:
6681 original <- removed inheritance pseudo
6682 removed inherit pseudo <- another removed inherit pseudo
6683 removed inherit pseudo <- original pseudo
6685 removed_split_pseudo <- original_reg
6686 original_reg <- removed_split_pseudo */
6688 if (lra_dump_file
!= NULL
)
6690 fprintf (lra_dump_file
, " Removing %s:\n",
6691 bitmap_bit_p (&lra_split_regs
, sregno
)
6692 || bitmap_bit_p (&lra_split_regs
, dregno
)
6693 ? "split" : "inheritance");
6694 dump_insn_slim (lra_dump_file
, curr_insn
);
6696 delete_move_and_clobber (curr_insn
, dregno
);
6699 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6700 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
6702 /* Search the following pattern:
6703 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6704 original_pseudo <- inherit_or_split_pseudo1
6705 where the 2nd insn is the current insn and
6706 inherit_or_split_pseudo2 is not removed. If it is found,
6707 change the current insn onto:
6708 original_pseudo <- inherit_or_split_pseudo2. */
6709 for (prev_insn
= PREV_INSN (curr_insn
);
6710 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
6711 prev_insn
= PREV_INSN (prev_insn
))
6713 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
6714 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
6715 /* There should be no subregs in insn we are
6716 searching because only the original reg might
6717 be in subreg when we changed the mode of
6718 load/store for splitting. */
6719 && REG_P (SET_DEST (prev_set
))
6720 && REG_P (SET_SRC (prev_set
))
6721 && (int) REGNO (SET_DEST (prev_set
)) == sregno
6722 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
6723 >= FIRST_PSEUDO_REGISTER
)
6724 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
6726 /* As we consider chain of inheritance or
6727 splitting described in above comment we should
6728 check that sregno and prev_sregno were
6729 inheritance/split pseudos created from the
6730 same original regno. */
6731 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6732 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6733 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
6734 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
6736 lra_assert (GET_MODE (SET_SRC (prev_set
))
6737 == GET_MODE (regno_reg_rtx
[sregno
]));
6738 /* Although we have a single set, the insn can
6739 contain more one sregno register occurrence
6740 as a source. Change all occurrences. */
6741 lra_substitute_pseudo_within_insn (curr_insn
, sregno
,
6744 /* As we are finishing with processing the insn
6745 here, check the destination too as it might
6746 inheritance pseudo for another pseudo. */
6747 if (bitmap_bit_p (remove_pseudos
, dregno
)
6748 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
6750 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
6752 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
6753 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
6755 SET_DEST (set
) = restore_rtx
;
6757 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6758 lra_set_used_insn_alternative_by_uid
6759 (INSN_UID (curr_insn
), -1);
6761 if (lra_dump_file
!= NULL
)
6763 fprintf (lra_dump_file
, " Change reload insn:\n");
6764 dump_insn_slim (lra_dump_file
, curr_insn
);
6771 struct lra_insn_reg
*reg
;
6772 bool restored_regs_p
= false;
6773 bool kept_regs_p
= false;
6775 curr_id
= lra_get_insn_recog_data (curr_insn
);
6776 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6779 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
6780 if (restore_rtx
!= NULL_RTX
)
6782 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
6784 lra_substitute_pseudo_within_insn
6785 (curr_insn
, regno
, restore_rtx
, false);
6786 restored_regs_p
= true;
6792 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
6794 /* The instruction has changed since the previous
6795 constraints pass. */
6796 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6797 lra_set_used_insn_alternative_by_uid
6798 (INSN_UID (curr_insn
), -1);
6800 else if (restored_regs_p
)
6801 /* The instruction has been restored to the form that
6802 it had during the previous constraints pass. */
6803 lra_update_insn_regno_info (curr_insn
);
6804 if (restored_regs_p
&& lra_dump_file
!= NULL
)
6806 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
6807 dump_insn_slim (lra_dump_file
, curr_insn
);
6815 /* If optional reload pseudos failed to get a hard register or was not
6816 inherited, it is better to remove optional reloads. We do this
6817 transformation after undoing inheritance to figure out necessity to
6818 remove optional reloads easier. Return true if we do any
6821 undo_optional_reloads (void)
6823 bool change_p
, keep_p
;
6824 unsigned int regno
, uid
;
6825 bitmap_iterator bi
, bi2
;
6828 auto_bitmap
removed_optional_reload_pseudos (®_obstack
);
6830 bitmap_copy (removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
6831 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6834 /* Keep optional reloads from previous subpasses. */
6835 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
6836 /* If the original pseudo changed its allocation, just
6837 removing the optional pseudo is dangerous as the original
6838 pseudo will have longer live range. */
6839 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
6841 else if (reg_renumber
[regno
] >= 0)
6842 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
6844 insn
= lra_insn_recog_data
[uid
]->insn
;
6845 if ((set
= single_set (insn
)) == NULL_RTX
)
6847 src
= SET_SRC (set
);
6848 dest
= SET_DEST (set
);
6849 if (! REG_P (src
) || ! REG_P (dest
))
6851 if (REGNO (dest
) == regno
6852 /* Ignore insn for optional reloads itself. */
6853 && REGNO (lra_reg_info
[regno
].restore_rtx
) != REGNO (src
)
6854 /* Check only inheritance on last inheritance pass. */
6855 && (int) REGNO (src
) >= new_regno_start
6856 /* Check that the optional reload was inherited. */
6857 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
6865 bitmap_clear_bit (removed_optional_reload_pseudos
, regno
);
6866 if (lra_dump_file
!= NULL
)
6867 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
6870 change_p
= ! bitmap_empty_p (removed_optional_reload_pseudos
);
6871 auto_bitmap
insn_bitmap (®_obstack
);
6872 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos
, 0, regno
, bi
)
6874 if (lra_dump_file
!= NULL
)
6875 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
6876 bitmap_copy (insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
6877 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap
, 0, uid
, bi2
)
6879 insn
= lra_insn_recog_data
[uid
]->insn
;
6880 if ((set
= single_set (insn
)) != NULL_RTX
)
6882 src
= SET_SRC (set
);
6883 dest
= SET_DEST (set
);
6884 if (REG_P (src
) && REG_P (dest
)
6885 && ((REGNO (src
) == regno
6886 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6888 || (REGNO (dest
) == regno
6889 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6892 if (lra_dump_file
!= NULL
)
6894 fprintf (lra_dump_file
, " Deleting move %u\n",
6896 dump_insn_slim (lra_dump_file
, insn
);
6898 delete_move_and_clobber (insn
, REGNO (dest
));
6901 /* We should not worry about generation memory-memory
6902 moves here as if the corresponding inheritance did
6903 not work (inheritance pseudo did not get a hard reg),
6904 we remove the inheritance pseudo and the optional
6907 lra_substitute_pseudo_within_insn
6908 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
6909 lra_update_insn_regno_info (insn
);
6910 if (lra_dump_file
!= NULL
)
6912 fprintf (lra_dump_file
,
6913 " Restoring original insn:\n");
6914 dump_insn_slim (lra_dump_file
, insn
);
6918 /* Clear restore_regnos. */
6919 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6920 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6924 /* Entry function for undoing inheritance/split transformation. Return true
6925 if we did any RTL change in this pass. */
6927 lra_undo_inheritance (void)
6931 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
6936 lra_undo_inheritance_iter
++;
6937 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6939 if (lra_dump_file
!= NULL
)
6940 fprintf (lra_dump_file
,
6941 "\n********** Undoing inheritance #%d: **********\n\n",
6942 lra_undo_inheritance_iter
);
6943 auto_bitmap
remove_pseudos (®_obstack
);
6944 n_inherit
= n_all_inherit
= 0;
6945 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6946 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
6949 if (reg_renumber
[regno
] < 0
6950 /* If the original pseudo changed its allocation, just
6951 removing inheritance is dangerous as for changing
6952 allocation we used shorter live-ranges. */
6953 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
6954 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
6955 bitmap_set_bit (remove_pseudos
, regno
);
6959 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
6960 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
6961 n_inherit
, n_all_inherit
,
6962 (double) n_inherit
/ n_all_inherit
* 100);
6963 n_split
= n_all_split
= 0;
6964 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6965 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
6967 int restore_regno
= REGNO (restore_rtx
);
6970 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6971 ? reg_renumber
[restore_regno
] : restore_regno
);
6972 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6973 bitmap_set_bit (remove_pseudos
, regno
);
6977 if (lra_dump_file
!= NULL
)
6978 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6979 regno
, restore_regno
);
6982 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6983 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6984 n_split
, n_all_split
,
6985 (double) n_split
/ n_all_split
* 100);
6986 change_p
= remove_inheritance_pseudos (remove_pseudos
);
6987 /* Clear restore_regnos. */
6988 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6989 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6990 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6991 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6992 change_p
= undo_optional_reloads () || change_p
;