PR target/84064
[official-gcc.git] / gcc / combine.c
blob6adc0a7d6f8510ff501a949def3560b3115830eb
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2018 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with modified_between_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
78 #include "config.h"
79 #include "system.h"
80 #include "coretypes.h"
81 #include "backend.h"
82 #include "target.h"
83 #include "rtl.h"
84 #include "tree.h"
85 #include "cfghooks.h"
86 #include "predict.h"
87 #include "df.h"
88 #include "memmodel.h"
89 #include "tm_p.h"
90 #include "optabs.h"
91 #include "regs.h"
92 #include "emit-rtl.h"
93 #include "recog.h"
94 #include "cgraph.h"
95 #include "stor-layout.h"
96 #include "cfgrtl.h"
97 #include "cfgcleanup.h"
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
99 #include "explow.h"
100 #include "insn-attr.h"
101 #include "rtlhooks-def.h"
102 #include "params.h"
103 #include "tree-pass.h"
104 #include "valtrack.h"
105 #include "rtl-iter.h"
106 #include "print-rtl.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras;
120 /* Number of instructions combined in this function. */
122 static int combine_successes;
124 /* Totals over entire compilation. */
126 static int total_attempts, total_merges, total_extras, total_successes;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
135 static rtx_insn *i2mod;
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs;
145 struct reg_stat_type {
146 /* Record last point of death of (hard or pseudo) register n. */
147 rtx_insn *last_death;
149 /* Record last point of modification of (hard or pseudo) register n. */
150 rtx_insn *last_set;
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick;
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
207 int last_set_label;
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits;
215 char last_set_sign_bit_copies;
216 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies;
238 unsigned HOST_WIDE_INT nonzero_bits;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
251 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 static vec<reg_stat_type> reg_stat;
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
265 static unsigned int reg_n_sets_max;
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
270 static int mem_last_set;
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
275 static int last_call_luid;
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
283 static rtx_insn *subst_insn;
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
292 static int subst_low_luid;
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
297 static HARD_REG_SET newpat_used_regs;
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
301 that location. */
303 static rtx_insn *added_links_insn;
305 /* And similarly, for notes. */
307 static rtx_insn *added_notes_insn;
309 /* Basic block in which we are performing combines. */
310 static basic_block this_basic_block;
311 static bool optimize_this_for_speed_p;
314 /* Length of the currently allocated uid_insn_cost array. */
316 static int max_uid_known;
318 /* The following array records the insn_cost for every insn
319 in the instruction stream. */
321 static int *uid_insn_cost;
323 /* The following array records the LOG_LINKS for every insn in the
324 instruction stream as struct insn_link pointers. */
326 struct insn_link {
327 rtx_insn *insn;
328 unsigned int regno;
329 struct insn_link *next;
332 static struct insn_link **uid_log_links;
334 static inline int
335 insn_uid_check (const_rtx insn)
337 int uid = INSN_UID (insn);
338 gcc_checking_assert (uid <= max_uid_known);
339 return uid;
342 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
343 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
345 #define FOR_EACH_LOG_LINK(L, INSN) \
346 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
348 /* Links for LOG_LINKS are allocated from this obstack. */
350 static struct obstack insn_link_obstack;
352 /* Allocate a link. */
354 static inline struct insn_link *
355 alloc_insn_link (rtx_insn *insn, unsigned int regno, struct insn_link *next)
357 struct insn_link *l
358 = (struct insn_link *) obstack_alloc (&insn_link_obstack,
359 sizeof (struct insn_link));
360 l->insn = insn;
361 l->regno = regno;
362 l->next = next;
363 return l;
366 /* Incremented for each basic block. */
368 static int label_tick;
370 /* Reset to label_tick for each extended basic block in scanning order. */
372 static int label_tick_ebb_start;
374 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
375 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
377 static scalar_int_mode nonzero_bits_mode;
379 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
380 be safely used. It is zero while computing them and after combine has
381 completed. This former test prevents propagating values based on
382 previously set values, which can be incorrect if a variable is modified
383 in a loop. */
385 static int nonzero_sign_valid;
388 /* Record one modification to rtl structure
389 to be undone by storing old_contents into *where. */
391 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
393 struct undo
395 struct undo *next;
396 enum undo_kind kind;
397 union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents;
398 union { rtx *r; int *i; struct insn_link **l; } where;
401 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
402 num_undo says how many are currently recorded.
404 other_insn is nonzero if we have modified some other insn in the process
405 of working on subst_insn. It must be verified too. */
407 struct undobuf
409 struct undo *undos;
410 struct undo *frees;
411 rtx_insn *other_insn;
414 static struct undobuf undobuf;
416 /* Number of times the pseudo being substituted for
417 was found and replaced. */
419 static int n_occurrences;
421 static rtx reg_nonzero_bits_for_combine (const_rtx, scalar_int_mode,
422 scalar_int_mode,
423 unsigned HOST_WIDE_INT *);
424 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, scalar_int_mode,
425 scalar_int_mode,
426 unsigned int *);
427 static void do_SUBST (rtx *, rtx);
428 static void do_SUBST_INT (int *, int);
429 static void init_reg_last (void);
430 static void setup_incoming_promotions (rtx_insn *);
431 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
432 static int cant_combine_insn_p (rtx_insn *);
433 static int can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
434 rtx_insn *, rtx_insn *, rtx *, rtx *);
435 static int combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx, int, int, rtx *);
436 static int contains_muldiv (rtx);
437 static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
438 int *, rtx_insn *);
439 static void undo_all (void);
440 static void undo_commit (void);
441 static rtx *find_split_point (rtx *, rtx_insn *, bool);
442 static rtx subst (rtx, rtx, rtx, int, int, int);
443 static rtx combine_simplify_rtx (rtx, machine_mode, int, int);
444 static rtx simplify_if_then_else (rtx);
445 static rtx simplify_set (rtx);
446 static rtx simplify_logical (rtx);
447 static rtx expand_compound_operation (rtx);
448 static const_rtx expand_field_assignment (const_rtx);
449 static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INT,
450 rtx, unsigned HOST_WIDE_INT, int, int, int);
451 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
452 unsigned HOST_WIDE_INT *);
453 static rtx canon_reg_for_combine (rtx, rtx);
454 static rtx force_int_to_mode (rtx, scalar_int_mode, scalar_int_mode,
455 scalar_int_mode, unsigned HOST_WIDE_INT, int);
456 static rtx force_to_mode (rtx, machine_mode,
457 unsigned HOST_WIDE_INT, int);
458 static rtx if_then_else_cond (rtx, rtx *, rtx *);
459 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
460 static int rtx_equal_for_field_assignment_p (rtx, rtx, bool = false);
461 static rtx make_field_assignment (rtx);
462 static rtx apply_distributive_law (rtx);
463 static rtx distribute_and_simplify_rtx (rtx, int);
464 static rtx simplify_and_const_int_1 (scalar_int_mode, rtx,
465 unsigned HOST_WIDE_INT);
466 static rtx simplify_and_const_int (rtx, scalar_int_mode, rtx,
467 unsigned HOST_WIDE_INT);
468 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
469 HOST_WIDE_INT, machine_mode, int *);
470 static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int);
471 static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx,
472 int);
473 static int recog_for_combine (rtx *, rtx_insn *, rtx *);
474 static rtx gen_lowpart_for_combine (machine_mode, rtx);
475 static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode,
476 rtx, rtx *);
477 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
478 static void update_table_tick (rtx);
479 static void record_value_for_reg (rtx, rtx_insn *, rtx);
480 static void check_promoted_subreg (rtx_insn *, rtx);
481 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
482 static void record_dead_and_set_regs (rtx_insn *);
483 static int get_last_value_validate (rtx *, rtx_insn *, int, int);
484 static rtx get_last_value (const_rtx);
485 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
486 static int reg_dead_at_p (rtx, rtx_insn *);
487 static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *);
488 static int reg_bitfield_target_p (rtx, rtx);
489 static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *, rtx, rtx, rtx);
490 static void distribute_links (struct insn_link *);
491 static void mark_used_regs_combine (rtx);
492 static void record_promoted_value (rtx_insn *, rtx);
493 static bool unmentioned_reg_p (rtx, rtx);
494 static void record_truncated_values (rtx *, void *);
495 static bool reg_truncated_to_mode (machine_mode, const_rtx);
496 static rtx gen_lowpart_or_truncate (machine_mode, rtx);
499 /* It is not safe to use ordinary gen_lowpart in combine.
500 See comments in gen_lowpart_for_combine. */
501 #undef RTL_HOOKS_GEN_LOWPART
502 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
504 /* Our implementation of gen_lowpart never emits a new pseudo. */
505 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
506 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
508 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
509 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
511 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
512 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
514 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
515 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
517 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
520 /* Convenience wrapper for the canonicalize_comparison target hook.
521 Target hooks cannot use enum rtx_code. */
522 static inline void
523 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
524 bool op0_preserve_value)
526 int code_int = (int)*code;
527 targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
528 *code = (enum rtx_code)code_int;
531 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
532 PATTERN can not be split. Otherwise, it returns an insn sequence.
533 This is a wrapper around split_insns which ensures that the
534 reg_stat vector is made larger if the splitter creates a new
535 register. */
537 static rtx_insn *
538 combine_split_insns (rtx pattern, rtx_insn *insn)
540 rtx_insn *ret;
541 unsigned int nregs;
543 ret = split_insns (pattern, insn);
544 nregs = max_reg_num ();
545 if (nregs > reg_stat.length ())
546 reg_stat.safe_grow_cleared (nregs);
547 return ret;
550 /* This is used by find_single_use to locate an rtx in LOC that
551 contains exactly one use of DEST, which is typically either a REG
552 or CC0. It returns a pointer to the innermost rtx expression
553 containing DEST. Appearances of DEST that are being used to
554 totally replace it are not counted. */
556 static rtx *
557 find_single_use_1 (rtx dest, rtx *loc)
559 rtx x = *loc;
560 enum rtx_code code = GET_CODE (x);
561 rtx *result = NULL;
562 rtx *this_result;
563 int i;
564 const char *fmt;
566 switch (code)
568 case CONST:
569 case LABEL_REF:
570 case SYMBOL_REF:
571 CASE_CONST_ANY:
572 case CLOBBER:
573 return 0;
575 case SET:
576 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
577 of a REG that occupies all of the REG, the insn uses DEST if
578 it is mentioned in the destination or the source. Otherwise, we
579 need just check the source. */
580 if (GET_CODE (SET_DEST (x)) != CC0
581 && GET_CODE (SET_DEST (x)) != PC
582 && !REG_P (SET_DEST (x))
583 && ! (GET_CODE (SET_DEST (x)) == SUBREG
584 && REG_P (SUBREG_REG (SET_DEST (x)))
585 && !read_modify_subreg_p (SET_DEST (x))))
586 break;
588 return find_single_use_1 (dest, &SET_SRC (x));
590 case MEM:
591 case SUBREG:
592 return find_single_use_1 (dest, &XEXP (x, 0));
594 default:
595 break;
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
601 fmt = GET_RTX_FORMAT (code);
602 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
604 if (fmt[i] == 'e')
606 if (dest == XEXP (x, i)
607 || (REG_P (dest) && REG_P (XEXP (x, i))
608 && REGNO (dest) == REGNO (XEXP (x, i))))
609 this_result = loc;
610 else
611 this_result = find_single_use_1 (dest, &XEXP (x, i));
613 if (result == NULL)
614 result = this_result;
615 else if (this_result)
616 /* Duplicate usage. */
617 return NULL;
619 else if (fmt[i] == 'E')
621 int j;
623 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
625 if (XVECEXP (x, i, j) == dest
626 || (REG_P (dest)
627 && REG_P (XVECEXP (x, i, j))
628 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
629 this_result = loc;
630 else
631 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
633 if (result == NULL)
634 result = this_result;
635 else if (this_result)
636 return NULL;
641 return result;
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
647 it is used.
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
659 static rtx *
660 find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc)
662 basic_block bb;
663 rtx_insn *next;
664 rtx *result;
665 struct insn_link *link;
667 if (dest == cc0_rtx)
669 next = NEXT_INSN (insn);
670 if (next == 0
671 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
672 return 0;
674 result = find_single_use_1 (dest, &PATTERN (next));
675 if (result && ploc)
676 *ploc = next;
677 return result;
680 if (!REG_P (dest))
681 return 0;
683 bb = BLOCK_FOR_INSN (insn);
684 for (next = NEXT_INSN (insn);
685 next && BLOCK_FOR_INSN (next) == bb;
686 next = NEXT_INSN (next))
687 if (NONDEBUG_INSN_P (next) && dead_or_set_p (next, dest))
689 FOR_EACH_LOG_LINK (link, next)
690 if (link->insn == insn && link->regno == REGNO (dest))
691 break;
693 if (link)
695 result = find_single_use_1 (dest, &PATTERN (next));
696 if (ploc)
697 *ploc = next;
698 return result;
702 return 0;
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
709 the undo table. */
711 static void
712 do_SUBST (rtx *into, rtx newval)
714 struct undo *buf;
715 rtx oldval = *into;
717 if (oldval == newval)
718 return;
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
725 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
726 && CONST_INT_P (newval))
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
730 gcc_assert (INTVAL (newval)
731 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
739 gcc_assert (!(GET_CODE (oldval) == SUBREG
740 && CONST_INT_P (SUBREG_REG (oldval))));
741 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
742 && CONST_INT_P (XEXP (oldval, 0))));
745 if (undobuf.frees)
746 buf = undobuf.frees, undobuf.frees = buf->next;
747 else
748 buf = XNEW (struct undo);
750 buf->kind = UNDO_RTX;
751 buf->where.r = into;
752 buf->old_contents.r = oldval;
753 *into = newval;
755 buf->next = undobuf.undos, undobuf.undos = buf;
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
762 not safe. */
764 static void
765 do_SUBST_INT (int *into, int newval)
767 struct undo *buf;
768 int oldval = *into;
770 if (oldval == newval)
771 return;
773 if (undobuf.frees)
774 buf = undobuf.frees, undobuf.frees = buf->next;
775 else
776 buf = XNEW (struct undo);
778 buf->kind = UNDO_INT;
779 buf->where.i = into;
780 buf->old_contents.i = oldval;
781 *into = newval;
783 buf->next = undobuf.undos, undobuf.undos = buf;
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
791 well. */
793 static void
794 do_SUBST_MODE (rtx *into, machine_mode newval)
796 struct undo *buf;
797 machine_mode oldval = GET_MODE (*into);
799 if (oldval == newval)
800 return;
802 if (undobuf.frees)
803 buf = undobuf.frees, undobuf.frees = buf->next;
804 else
805 buf = XNEW (struct undo);
807 buf->kind = UNDO_MODE;
808 buf->where.r = into;
809 buf->old_contents.m = oldval;
810 adjust_reg_mode (*into, newval);
812 buf->next = undobuf.undos, undobuf.undos = buf;
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
819 static void
820 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
822 struct undo *buf;
823 struct insn_link * oldval = *into;
825 if (oldval == newval)
826 return;
828 if (undobuf.frees)
829 buf = undobuf.frees, undobuf.frees = buf->next;
830 else
831 buf = XNEW (struct undo);
833 buf->kind = UNDO_LINKS;
834 buf->where.l = into;
835 buf->old_contents.l = oldval;
836 *into = newval;
838 buf->next = undobuf.undos, undobuf.undos = buf;
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
851 static bool
852 combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3,
853 rtx newpat, rtx newi2pat, rtx newotherpat)
855 int i0_cost, i1_cost, i2_cost, i3_cost;
856 int new_i2_cost, new_i3_cost;
857 int old_cost, new_cost;
859 /* Lookup the original insn_costs. */
860 i2_cost = INSN_COST (i2);
861 i3_cost = INSN_COST (i3);
863 if (i1)
865 i1_cost = INSN_COST (i1);
866 if (i0)
868 i0_cost = INSN_COST (i0);
869 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
870 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
872 else
874 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
875 ? i1_cost + i2_cost + i3_cost : 0);
876 i0_cost = 0;
879 else
881 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
882 i1_cost = i0_cost = 0;
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
886 correct that. */
887 if (old_cost && i1 && INSN_UID (i1) == INSN_UID (i2))
888 old_cost -= i1_cost;
891 /* Calculate the replacement insn_costs. */
892 rtx tmp = PATTERN (i3);
893 PATTERN (i3) = newpat;
894 int tmpi = INSN_CODE (i3);
895 INSN_CODE (i3) = -1;
896 new_i3_cost = insn_cost (i3, optimize_this_for_speed_p);
897 PATTERN (i3) = tmp;
898 INSN_CODE (i3) = tmpi;
899 if (newi2pat)
901 tmp = PATTERN (i2);
902 PATTERN (i2) = newi2pat;
903 tmpi = INSN_CODE (i2);
904 INSN_CODE (i2) = -1;
905 new_i2_cost = insn_cost (i2, optimize_this_for_speed_p);
906 PATTERN (i2) = tmp;
907 INSN_CODE (i2) = tmpi;
908 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
909 ? new_i2_cost + new_i3_cost : 0;
911 else
913 new_cost = new_i3_cost;
914 new_i2_cost = 0;
917 if (undobuf.other_insn)
919 int old_other_cost, new_other_cost;
921 old_other_cost = INSN_COST (undobuf.other_insn);
922 tmp = PATTERN (undobuf.other_insn);
923 PATTERN (undobuf.other_insn) = newotherpat;
924 tmpi = INSN_CODE (undobuf.other_insn);
925 INSN_CODE (undobuf.other_insn) = -1;
926 new_other_cost = insn_cost (undobuf.other_insn,
927 optimize_this_for_speed_p);
928 PATTERN (undobuf.other_insn) = tmp;
929 INSN_CODE (undobuf.other_insn) = tmpi;
930 if (old_other_cost > 0 && new_other_cost > 0)
932 old_cost += old_other_cost;
933 new_cost += new_other_cost;
935 else
936 old_cost = 0;
939 /* Disallow this combination if both new_cost and old_cost are greater than
940 zero, and new_cost is greater than old cost. */
941 int reject = old_cost > 0 && new_cost > old_cost;
943 if (dump_file)
945 fprintf (dump_file, "%s combination of insns ",
946 reject ? "rejecting" : "allowing");
947 if (i0)
948 fprintf (dump_file, "%d, ", INSN_UID (i0));
949 if (i1 && INSN_UID (i1) != INSN_UID (i2))
950 fprintf (dump_file, "%d, ", INSN_UID (i1));
951 fprintf (dump_file, "%d and %d\n", INSN_UID (i2), INSN_UID (i3));
953 fprintf (dump_file, "original costs ");
954 if (i0)
955 fprintf (dump_file, "%d + ", i0_cost);
956 if (i1 && INSN_UID (i1) != INSN_UID (i2))
957 fprintf (dump_file, "%d + ", i1_cost);
958 fprintf (dump_file, "%d + %d = %d\n", i2_cost, i3_cost, old_cost);
960 if (newi2pat)
961 fprintf (dump_file, "replacement costs %d + %d = %d\n",
962 new_i2_cost, new_i3_cost, new_cost);
963 else
964 fprintf (dump_file, "replacement cost %d\n", new_cost);
967 if (reject)
968 return false;
970 /* Update the uid_insn_cost array with the replacement costs. */
971 INSN_COST (i2) = new_i2_cost;
972 INSN_COST (i3) = new_i3_cost;
973 if (i1)
975 INSN_COST (i1) = 0;
976 if (i0)
977 INSN_COST (i0) = 0;
980 return true;
984 /* Delete any insns that copy a register to itself. */
986 static void
987 delete_noop_moves (void)
989 rtx_insn *insn, *next;
990 basic_block bb;
992 FOR_EACH_BB_FN (bb, cfun)
994 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
996 next = NEXT_INSN (insn);
997 if (INSN_P (insn) && noop_move_p (insn))
999 if (dump_file)
1000 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
1002 delete_insn_and_edges (insn);
1009 /* Return false if we do not want to (or cannot) combine DEF. */
1010 static bool
1011 can_combine_def_p (df_ref def)
1013 /* Do not consider if it is pre/post modification in MEM. */
1014 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1015 return false;
1017 unsigned int regno = DF_REF_REGNO (def);
1019 /* Do not combine frame pointer adjustments. */
1020 if ((regno == FRAME_POINTER_REGNUM
1021 && (!reload_completed || frame_pointer_needed))
1022 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1023 && regno == HARD_FRAME_POINTER_REGNUM
1024 && (!reload_completed || frame_pointer_needed))
1025 || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1026 && regno == ARG_POINTER_REGNUM && fixed_regs[regno]))
1027 return false;
1029 return true;
1032 /* Return false if we do not want to (or cannot) combine USE. */
1033 static bool
1034 can_combine_use_p (df_ref use)
1036 /* Do not consider the usage of the stack pointer by function call. */
1037 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1038 return false;
1040 return true;
1043 /* Fill in log links field for all insns. */
1045 static void
1046 create_log_links (void)
1048 basic_block bb;
1049 rtx_insn **next_use;
1050 rtx_insn *insn;
1051 df_ref def, use;
1053 next_use = XCNEWVEC (rtx_insn *, max_reg_num ());
1055 /* Pass through each block from the end, recording the uses of each
1056 register and establishing log links when def is encountered.
1057 Note that we do not clear next_use array in order to save time,
1058 so we have to test whether the use is in the same basic block as def.
1060 There are a few cases below when we do not consider the definition or
1061 usage -- these are taken from original flow.c did. Don't ask me why it is
1062 done this way; I don't know and if it works, I don't want to know. */
1064 FOR_EACH_BB_FN (bb, cfun)
1066 FOR_BB_INSNS_REVERSE (bb, insn)
1068 if (!NONDEBUG_INSN_P (insn))
1069 continue;
1071 /* Log links are created only once. */
1072 gcc_assert (!LOG_LINKS (insn));
1074 FOR_EACH_INSN_DEF (def, insn)
1076 unsigned int regno = DF_REF_REGNO (def);
1077 rtx_insn *use_insn;
1079 if (!next_use[regno])
1080 continue;
1082 if (!can_combine_def_p (def))
1083 continue;
1085 use_insn = next_use[regno];
1086 next_use[regno] = NULL;
1088 if (BLOCK_FOR_INSN (use_insn) != bb)
1089 continue;
1091 /* flow.c claimed:
1093 We don't build a LOG_LINK for hard registers contained
1094 in ASM_OPERANDs. If these registers get replaced,
1095 we might wind up changing the semantics of the insn,
1096 even if reload can make what appear to be valid
1097 assignments later. */
1098 if (regno < FIRST_PSEUDO_REGISTER
1099 && asm_noperands (PATTERN (use_insn)) >= 0)
1100 continue;
1102 /* Don't add duplicate links between instructions. */
1103 struct insn_link *links;
1104 FOR_EACH_LOG_LINK (links, use_insn)
1105 if (insn == links->insn && regno == links->regno)
1106 break;
1108 if (!links)
1109 LOG_LINKS (use_insn)
1110 = alloc_insn_link (insn, regno, LOG_LINKS (use_insn));
1113 FOR_EACH_INSN_USE (use, insn)
1114 if (can_combine_use_p (use))
1115 next_use[DF_REF_REGNO (use)] = insn;
1119 free (next_use);
1122 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1123 true if we found a LOG_LINK that proves that A feeds B. This only works
1124 if there are no instructions between A and B which could have a link
1125 depending on A, since in that case we would not record a link for B.
1126 We also check the implicit dependency created by a cc0 setter/user
1127 pair. */
1129 static bool
1130 insn_a_feeds_b (rtx_insn *a, rtx_insn *b)
1132 struct insn_link *links;
1133 FOR_EACH_LOG_LINK (links, b)
1134 if (links->insn == a)
1135 return true;
1136 if (HAVE_cc0 && sets_cc0_p (a))
1137 return true;
1138 return false;
1141 /* Main entry point for combiner. F is the first insn of the function.
1142 NREGS is the first unused pseudo-reg number.
1144 Return nonzero if the combiner has turned an indirect jump
1145 instruction into a direct jump. */
1146 static int
1147 combine_instructions (rtx_insn *f, unsigned int nregs)
1149 rtx_insn *insn, *next;
1150 rtx_insn *prev;
1151 struct insn_link *links, *nextlinks;
1152 rtx_insn *first;
1153 basic_block last_bb;
1155 int new_direct_jump_p = 0;
1157 for (first = f; first && !NONDEBUG_INSN_P (first); )
1158 first = NEXT_INSN (first);
1159 if (!first)
1160 return 0;
1162 combine_attempts = 0;
1163 combine_merges = 0;
1164 combine_extras = 0;
1165 combine_successes = 0;
1167 rtl_hooks = combine_rtl_hooks;
1169 reg_stat.safe_grow_cleared (nregs);
1171 init_recog_no_volatile ();
1173 /* Allocate array for insn info. */
1174 max_uid_known = get_max_uid ();
1175 uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1176 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1177 gcc_obstack_init (&insn_link_obstack);
1179 nonzero_bits_mode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, 0).require ();
1181 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1182 problems when, for example, we have j <<= 1 in a loop. */
1184 nonzero_sign_valid = 0;
1185 label_tick = label_tick_ebb_start = 1;
1187 /* Scan all SETs and see if we can deduce anything about what
1188 bits are known to be zero for some registers and how many copies
1189 of the sign bit are known to exist for those registers.
1191 Also set any known values so that we can use it while searching
1192 for what bits are known to be set. */
1194 setup_incoming_promotions (first);
1195 /* Allow the entry block and the first block to fall into the same EBB.
1196 Conceptually the incoming promotions are assigned to the entry block. */
1197 last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1199 create_log_links ();
1200 FOR_EACH_BB_FN (this_basic_block, cfun)
1202 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1203 last_call_luid = 0;
1204 mem_last_set = -1;
1206 label_tick++;
1207 if (!single_pred_p (this_basic_block)
1208 || single_pred (this_basic_block) != last_bb)
1209 label_tick_ebb_start = label_tick;
1210 last_bb = this_basic_block;
1212 FOR_BB_INSNS (this_basic_block, insn)
1213 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1215 rtx links;
1217 subst_low_luid = DF_INSN_LUID (insn);
1218 subst_insn = insn;
1220 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1221 insn);
1222 record_dead_and_set_regs (insn);
1224 if (AUTO_INC_DEC)
1225 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1226 if (REG_NOTE_KIND (links) == REG_INC)
1227 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1228 insn);
1230 /* Record the current insn_cost of this instruction. */
1231 if (NONJUMP_INSN_P (insn))
1232 INSN_COST (insn) = insn_cost (insn, optimize_this_for_speed_p);
1233 if (dump_file)
1235 fprintf (dump_file, "insn_cost %d for ", INSN_COST (insn));
1236 dump_insn_slim (dump_file, insn);
1241 nonzero_sign_valid = 1;
1243 /* Now scan all the insns in forward order. */
1244 label_tick = label_tick_ebb_start = 1;
1245 init_reg_last ();
1246 setup_incoming_promotions (first);
1247 last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1248 int max_combine = PARAM_VALUE (PARAM_MAX_COMBINE_INSNS);
1250 FOR_EACH_BB_FN (this_basic_block, cfun)
1252 rtx_insn *last_combined_insn = NULL;
1254 /* Ignore instruction combination in basic blocks that are going to
1255 be removed as unreachable anyway. See PR82386. */
1256 if (EDGE_COUNT (this_basic_block->preds) == 0)
1257 continue;
1259 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1260 last_call_luid = 0;
1261 mem_last_set = -1;
1263 label_tick++;
1264 if (!single_pred_p (this_basic_block)
1265 || single_pred (this_basic_block) != last_bb)
1266 label_tick_ebb_start = label_tick;
1267 last_bb = this_basic_block;
1269 rtl_profile_for_bb (this_basic_block);
1270 for (insn = BB_HEAD (this_basic_block);
1271 insn != NEXT_INSN (BB_END (this_basic_block));
1272 insn = next ? next : NEXT_INSN (insn))
1274 next = 0;
1275 if (!NONDEBUG_INSN_P (insn))
1276 continue;
1278 while (last_combined_insn
1279 && (!NONDEBUG_INSN_P (last_combined_insn)
1280 || last_combined_insn->deleted ()))
1281 last_combined_insn = PREV_INSN (last_combined_insn);
1282 if (last_combined_insn == NULL_RTX
1283 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1284 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1285 last_combined_insn = insn;
1287 /* See if we know about function return values before this
1288 insn based upon SUBREG flags. */
1289 check_promoted_subreg (insn, PATTERN (insn));
1291 /* See if we can find hardregs and subreg of pseudos in
1292 narrower modes. This could help turning TRUNCATEs
1293 into SUBREGs. */
1294 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1296 /* Try this insn with each insn it links back to. */
1298 FOR_EACH_LOG_LINK (links, insn)
1299 if ((next = try_combine (insn, links->insn, NULL,
1300 NULL, &new_direct_jump_p,
1301 last_combined_insn)) != 0)
1303 statistics_counter_event (cfun, "two-insn combine", 1);
1304 goto retry;
1307 /* Try each sequence of three linked insns ending with this one. */
1309 if (max_combine >= 3)
1310 FOR_EACH_LOG_LINK (links, insn)
1312 rtx_insn *link = links->insn;
1314 /* If the linked insn has been replaced by a note, then there
1315 is no point in pursuing this chain any further. */
1316 if (NOTE_P (link))
1317 continue;
1319 FOR_EACH_LOG_LINK (nextlinks, link)
1320 if ((next = try_combine (insn, link, nextlinks->insn,
1321 NULL, &new_direct_jump_p,
1322 last_combined_insn)) != 0)
1324 statistics_counter_event (cfun, "three-insn combine", 1);
1325 goto retry;
1329 /* Try to combine a jump insn that uses CC0
1330 with a preceding insn that sets CC0, and maybe with its
1331 logical predecessor as well.
1332 This is how we make decrement-and-branch insns.
1333 We need this special code because data flow connections
1334 via CC0 do not get entered in LOG_LINKS. */
1336 if (HAVE_cc0
1337 && JUMP_P (insn)
1338 && (prev = prev_nonnote_insn (insn)) != 0
1339 && NONJUMP_INSN_P (prev)
1340 && sets_cc0_p (PATTERN (prev)))
1342 if ((next = try_combine (insn, prev, NULL, NULL,
1343 &new_direct_jump_p,
1344 last_combined_insn)) != 0)
1345 goto retry;
1347 FOR_EACH_LOG_LINK (nextlinks, prev)
1348 if ((next = try_combine (insn, prev, nextlinks->insn,
1349 NULL, &new_direct_jump_p,
1350 last_combined_insn)) != 0)
1351 goto retry;
1354 /* Do the same for an insn that explicitly references CC0. */
1355 if (HAVE_cc0 && NONJUMP_INSN_P (insn)
1356 && (prev = prev_nonnote_insn (insn)) != 0
1357 && NONJUMP_INSN_P (prev)
1358 && sets_cc0_p (PATTERN (prev))
1359 && GET_CODE (PATTERN (insn)) == SET
1360 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1362 if ((next = try_combine (insn, prev, NULL, NULL,
1363 &new_direct_jump_p,
1364 last_combined_insn)) != 0)
1365 goto retry;
1367 FOR_EACH_LOG_LINK (nextlinks, prev)
1368 if ((next = try_combine (insn, prev, nextlinks->insn,
1369 NULL, &new_direct_jump_p,
1370 last_combined_insn)) != 0)
1371 goto retry;
1374 /* Finally, see if any of the insns that this insn links to
1375 explicitly references CC0. If so, try this insn, that insn,
1376 and its predecessor if it sets CC0. */
1377 if (HAVE_cc0)
1379 FOR_EACH_LOG_LINK (links, insn)
1380 if (NONJUMP_INSN_P (links->insn)
1381 && GET_CODE (PATTERN (links->insn)) == SET
1382 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1383 && (prev = prev_nonnote_insn (links->insn)) != 0
1384 && NONJUMP_INSN_P (prev)
1385 && sets_cc0_p (PATTERN (prev))
1386 && (next = try_combine (insn, links->insn,
1387 prev, NULL, &new_direct_jump_p,
1388 last_combined_insn)) != 0)
1389 goto retry;
1392 /* Try combining an insn with two different insns whose results it
1393 uses. */
1394 if (max_combine >= 3)
1395 FOR_EACH_LOG_LINK (links, insn)
1396 for (nextlinks = links->next; nextlinks;
1397 nextlinks = nextlinks->next)
1398 if ((next = try_combine (insn, links->insn,
1399 nextlinks->insn, NULL,
1400 &new_direct_jump_p,
1401 last_combined_insn)) != 0)
1404 statistics_counter_event (cfun, "three-insn combine", 1);
1405 goto retry;
1408 /* Try four-instruction combinations. */
1409 if (max_combine >= 4)
1410 FOR_EACH_LOG_LINK (links, insn)
1412 struct insn_link *next1;
1413 rtx_insn *link = links->insn;
1415 /* If the linked insn has been replaced by a note, then there
1416 is no point in pursuing this chain any further. */
1417 if (NOTE_P (link))
1418 continue;
1420 FOR_EACH_LOG_LINK (next1, link)
1422 rtx_insn *link1 = next1->insn;
1423 if (NOTE_P (link1))
1424 continue;
1425 /* I0 -> I1 -> I2 -> I3. */
1426 FOR_EACH_LOG_LINK (nextlinks, link1)
1427 if ((next = try_combine (insn, link, link1,
1428 nextlinks->insn,
1429 &new_direct_jump_p,
1430 last_combined_insn)) != 0)
1432 statistics_counter_event (cfun, "four-insn combine", 1);
1433 goto retry;
1435 /* I0, I1 -> I2, I2 -> I3. */
1436 for (nextlinks = next1->next; nextlinks;
1437 nextlinks = nextlinks->next)
1438 if ((next = try_combine (insn, link, link1,
1439 nextlinks->insn,
1440 &new_direct_jump_p,
1441 last_combined_insn)) != 0)
1443 statistics_counter_event (cfun, "four-insn combine", 1);
1444 goto retry;
1448 for (next1 = links->next; next1; next1 = next1->next)
1450 rtx_insn *link1 = next1->insn;
1451 if (NOTE_P (link1))
1452 continue;
1453 /* I0 -> I2; I1, I2 -> I3. */
1454 FOR_EACH_LOG_LINK (nextlinks, link)
1455 if ((next = try_combine (insn, link, link1,
1456 nextlinks->insn,
1457 &new_direct_jump_p,
1458 last_combined_insn)) != 0)
1460 statistics_counter_event (cfun, "four-insn combine", 1);
1461 goto retry;
1463 /* I0 -> I1; I1, I2 -> I3. */
1464 FOR_EACH_LOG_LINK (nextlinks, link1)
1465 if ((next = try_combine (insn, link, link1,
1466 nextlinks->insn,
1467 &new_direct_jump_p,
1468 last_combined_insn)) != 0)
1470 statistics_counter_event (cfun, "four-insn combine", 1);
1471 goto retry;
1476 /* Try this insn with each REG_EQUAL note it links back to. */
1477 FOR_EACH_LOG_LINK (links, insn)
1479 rtx set, note;
1480 rtx_insn *temp = links->insn;
1481 if ((set = single_set (temp)) != 0
1482 && (note = find_reg_equal_equiv_note (temp)) != 0
1483 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1484 /* Avoid using a register that may already been marked
1485 dead by an earlier instruction. */
1486 && ! unmentioned_reg_p (note, SET_SRC (set))
1487 && (GET_MODE (note) == VOIDmode
1488 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1489 : (GET_MODE (SET_DEST (set)) == GET_MODE (note)
1490 && (GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
1491 || (GET_MODE (XEXP (SET_DEST (set), 0))
1492 == GET_MODE (note))))))
1494 /* Temporarily replace the set's source with the
1495 contents of the REG_EQUAL note. The insn will
1496 be deleted or recognized by try_combine. */
1497 rtx orig_src = SET_SRC (set);
1498 rtx orig_dest = SET_DEST (set);
1499 if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT)
1500 SET_DEST (set) = XEXP (SET_DEST (set), 0);
1501 SET_SRC (set) = note;
1502 i2mod = temp;
1503 i2mod_old_rhs = copy_rtx (orig_src);
1504 i2mod_new_rhs = copy_rtx (note);
1505 next = try_combine (insn, i2mod, NULL, NULL,
1506 &new_direct_jump_p,
1507 last_combined_insn);
1508 i2mod = NULL;
1509 if (next)
1511 statistics_counter_event (cfun, "insn-with-note combine", 1);
1512 goto retry;
1514 SET_SRC (set) = orig_src;
1515 SET_DEST (set) = orig_dest;
1519 if (!NOTE_P (insn))
1520 record_dead_and_set_regs (insn);
1522 retry:
1527 default_rtl_profile ();
1528 clear_bb_flags ();
1529 new_direct_jump_p |= purge_all_dead_edges ();
1530 delete_noop_moves ();
1532 /* Clean up. */
1533 obstack_free (&insn_link_obstack, NULL);
1534 free (uid_log_links);
1535 free (uid_insn_cost);
1536 reg_stat.release ();
1539 struct undo *undo, *next;
1540 for (undo = undobuf.frees; undo; undo = next)
1542 next = undo->next;
1543 free (undo);
1545 undobuf.frees = 0;
1548 total_attempts += combine_attempts;
1549 total_merges += combine_merges;
1550 total_extras += combine_extras;
1551 total_successes += combine_successes;
1553 nonzero_sign_valid = 0;
1554 rtl_hooks = general_rtl_hooks;
1556 /* Make recognizer allow volatile MEMs again. */
1557 init_recog ();
1559 return new_direct_jump_p;
1562 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1564 static void
1565 init_reg_last (void)
1567 unsigned int i;
1568 reg_stat_type *p;
1570 FOR_EACH_VEC_ELT (reg_stat, i, p)
1571 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1574 /* Set up any promoted values for incoming argument registers. */
1576 static void
1577 setup_incoming_promotions (rtx_insn *first)
1579 tree arg;
1580 bool strictly_local = false;
1582 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1583 arg = DECL_CHAIN (arg))
1585 rtx x, reg = DECL_INCOMING_RTL (arg);
1586 int uns1, uns3;
1587 machine_mode mode1, mode2, mode3, mode4;
1589 /* Only continue if the incoming argument is in a register. */
1590 if (!REG_P (reg))
1591 continue;
1593 /* Determine, if possible, whether all call sites of the current
1594 function lie within the current compilation unit. (This does
1595 take into account the exporting of a function via taking its
1596 address, and so forth.) */
1597 strictly_local = cgraph_node::local_info (current_function_decl)->local;
1599 /* The mode and signedness of the argument before any promotions happen
1600 (equal to the mode of the pseudo holding it at that stage). */
1601 mode1 = TYPE_MODE (TREE_TYPE (arg));
1602 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1604 /* The mode and signedness of the argument after any source language and
1605 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1606 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1607 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1609 /* The mode and signedness of the argument as it is actually passed,
1610 see assign_parm_setup_reg in function.c. */
1611 mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3,
1612 TREE_TYPE (cfun->decl), 0);
1614 /* The mode of the register in which the argument is being passed. */
1615 mode4 = GET_MODE (reg);
1617 /* Eliminate sign extensions in the callee when:
1618 (a) A mode promotion has occurred; */
1619 if (mode1 == mode3)
1620 continue;
1621 /* (b) The mode of the register is the same as the mode of
1622 the argument as it is passed; */
1623 if (mode3 != mode4)
1624 continue;
1625 /* (c) There's no language level extension; */
1626 if (mode1 == mode2)
1628 /* (c.1) All callers are from the current compilation unit. If that's
1629 the case we don't have to rely on an ABI, we only have to know
1630 what we're generating right now, and we know that we will do the
1631 mode1 to mode2 promotion with the given sign. */
1632 else if (!strictly_local)
1633 continue;
1634 /* (c.2) The combination of the two promotions is useful. This is
1635 true when the signs match, or if the first promotion is unsigned.
1636 In the later case, (sign_extend (zero_extend x)) is the same as
1637 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1638 else if (uns1)
1639 uns3 = true;
1640 else if (uns3)
1641 continue;
1643 /* Record that the value was promoted from mode1 to mode3,
1644 so that any sign extension at the head of the current
1645 function may be eliminated. */
1646 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1647 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1648 record_value_for_reg (reg, first, x);
1652 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1653 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1654 because some machines (maybe most) will actually do the sign-extension and
1655 this is the conservative approach.
1657 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1658 kludge. */
1660 static rtx
1661 sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec)
1663 scalar_int_mode int_mode;
1664 if (CONST_INT_P (src)
1665 && is_a <scalar_int_mode> (mode, &int_mode)
1666 && GET_MODE_PRECISION (int_mode) < prec
1667 && INTVAL (src) > 0
1668 && val_signbit_known_set_p (int_mode, INTVAL (src)))
1669 src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (int_mode));
1671 return src;
1674 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1675 and SET. */
1677 static void
1678 update_rsp_from_reg_equal (reg_stat_type *rsp, rtx_insn *insn, const_rtx set,
1679 rtx x)
1681 rtx reg_equal_note = insn ? find_reg_equal_equiv_note (insn) : NULL_RTX;
1682 unsigned HOST_WIDE_INT bits = 0;
1683 rtx reg_equal = NULL, src = SET_SRC (set);
1684 unsigned int num = 0;
1686 if (reg_equal_note)
1687 reg_equal = XEXP (reg_equal_note, 0);
1689 if (SHORT_IMMEDIATES_SIGN_EXTEND)
1691 src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD);
1692 if (reg_equal)
1693 reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x), BITS_PER_WORD);
1696 /* Don't call nonzero_bits if it cannot change anything. */
1697 if (rsp->nonzero_bits != HOST_WIDE_INT_M1U)
1699 bits = nonzero_bits (src, nonzero_bits_mode);
1700 if (reg_equal && bits)
1701 bits &= nonzero_bits (reg_equal, nonzero_bits_mode);
1702 rsp->nonzero_bits |= bits;
1705 /* Don't call num_sign_bit_copies if it cannot change anything. */
1706 if (rsp->sign_bit_copies != 1)
1708 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1709 if (reg_equal && maybe_ne (num, GET_MODE_PRECISION (GET_MODE (x))))
1711 unsigned int numeq = num_sign_bit_copies (reg_equal, GET_MODE (x));
1712 if (num == 0 || numeq > num)
1713 num = numeq;
1715 if (rsp->sign_bit_copies == 0 || num < rsp->sign_bit_copies)
1716 rsp->sign_bit_copies = num;
1720 /* Called via note_stores. If X is a pseudo that is narrower than
1721 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1723 If we are setting only a portion of X and we can't figure out what
1724 portion, assume all bits will be used since we don't know what will
1725 be happening.
1727 Similarly, set how many bits of X are known to be copies of the sign bit
1728 at all locations in the function. This is the smallest number implied
1729 by any set of X. */
1731 static void
1732 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1734 rtx_insn *insn = (rtx_insn *) data;
1735 scalar_int_mode mode;
1737 if (REG_P (x)
1738 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1739 /* If this register is undefined at the start of the file, we can't
1740 say what its contents were. */
1741 && ! REGNO_REG_SET_P
1742 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))
1743 && is_a <scalar_int_mode> (GET_MODE (x), &mode)
1744 && HWI_COMPUTABLE_MODE_P (mode))
1746 reg_stat_type *rsp = &reg_stat[REGNO (x)];
1748 if (set == 0 || GET_CODE (set) == CLOBBER)
1750 rsp->nonzero_bits = GET_MODE_MASK (mode);
1751 rsp->sign_bit_copies = 1;
1752 return;
1755 /* If this register is being initialized using itself, and the
1756 register is uninitialized in this basic block, and there are
1757 no LOG_LINKS which set the register, then part of the
1758 register is uninitialized. In that case we can't assume
1759 anything about the number of nonzero bits.
1761 ??? We could do better if we checked this in
1762 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1763 could avoid making assumptions about the insn which initially
1764 sets the register, while still using the information in other
1765 insns. We would have to be careful to check every insn
1766 involved in the combination. */
1768 if (insn
1769 && reg_referenced_p (x, PATTERN (insn))
1770 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1771 REGNO (x)))
1773 struct insn_link *link;
1775 FOR_EACH_LOG_LINK (link, insn)
1776 if (dead_or_set_p (link->insn, x))
1777 break;
1778 if (!link)
1780 rsp->nonzero_bits = GET_MODE_MASK (mode);
1781 rsp->sign_bit_copies = 1;
1782 return;
1786 /* If this is a complex assignment, see if we can convert it into a
1787 simple assignment. */
1788 set = expand_field_assignment (set);
1790 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1791 set what we know about X. */
1793 if (SET_DEST (set) == x
1794 || (paradoxical_subreg_p (SET_DEST (set))
1795 && SUBREG_REG (SET_DEST (set)) == x))
1796 update_rsp_from_reg_equal (rsp, insn, set, x);
1797 else
1799 rsp->nonzero_bits = GET_MODE_MASK (mode);
1800 rsp->sign_bit_copies = 1;
1805 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1806 optionally insns that were previously combined into I3 or that will be
1807 combined into the merger of INSN and I3. The order is PRED, PRED2,
1808 INSN, SUCC, SUCC2, I3.
1810 Return 0 if the combination is not allowed for any reason.
1812 If the combination is allowed, *PDEST will be set to the single
1813 destination of INSN and *PSRC to the single source, and this function
1814 will return 1. */
1816 static int
1817 can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
1818 rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2,
1819 rtx *pdest, rtx *psrc)
1821 int i;
1822 const_rtx set = 0;
1823 rtx src, dest;
1824 rtx_insn *p;
1825 rtx link;
1826 bool all_adjacent = true;
1827 int (*is_volatile_p) (const_rtx);
1829 if (succ)
1831 if (succ2)
1833 if (next_active_insn (succ2) != i3)
1834 all_adjacent = false;
1835 if (next_active_insn (succ) != succ2)
1836 all_adjacent = false;
1838 else if (next_active_insn (succ) != i3)
1839 all_adjacent = false;
1840 if (next_active_insn (insn) != succ)
1841 all_adjacent = false;
1843 else if (next_active_insn (insn) != i3)
1844 all_adjacent = false;
1846 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1847 or a PARALLEL consisting of such a SET and CLOBBERs.
1849 If INSN has CLOBBER parallel parts, ignore them for our processing.
1850 By definition, these happen during the execution of the insn. When it
1851 is merged with another insn, all bets are off. If they are, in fact,
1852 needed and aren't also supplied in I3, they may be added by
1853 recog_for_combine. Otherwise, it won't match.
1855 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1856 note.
1858 Get the source and destination of INSN. If more than one, can't
1859 combine. */
1861 if (GET_CODE (PATTERN (insn)) == SET)
1862 set = PATTERN (insn);
1863 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1864 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1866 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1868 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1870 switch (GET_CODE (elt))
1872 /* This is important to combine floating point insns
1873 for the SH4 port. */
1874 case USE:
1875 /* Combining an isolated USE doesn't make sense.
1876 We depend here on combinable_i3pat to reject them. */
1877 /* The code below this loop only verifies that the inputs of
1878 the SET in INSN do not change. We call reg_set_between_p
1879 to verify that the REG in the USE does not change between
1880 I3 and INSN.
1881 If the USE in INSN was for a pseudo register, the matching
1882 insn pattern will likely match any register; combining this
1883 with any other USE would only be safe if we knew that the
1884 used registers have identical values, or if there was
1885 something to tell them apart, e.g. different modes. For
1886 now, we forgo such complicated tests and simply disallow
1887 combining of USES of pseudo registers with any other USE. */
1888 if (REG_P (XEXP (elt, 0))
1889 && GET_CODE (PATTERN (i3)) == PARALLEL)
1891 rtx i3pat = PATTERN (i3);
1892 int i = XVECLEN (i3pat, 0) - 1;
1893 unsigned int regno = REGNO (XEXP (elt, 0));
1897 rtx i3elt = XVECEXP (i3pat, 0, i);
1899 if (GET_CODE (i3elt) == USE
1900 && REG_P (XEXP (i3elt, 0))
1901 && (REGNO (XEXP (i3elt, 0)) == regno
1902 ? reg_set_between_p (XEXP (elt, 0),
1903 PREV_INSN (insn), i3)
1904 : regno >= FIRST_PSEUDO_REGISTER))
1905 return 0;
1907 while (--i >= 0);
1909 break;
1911 /* We can ignore CLOBBERs. */
1912 case CLOBBER:
1913 break;
1915 case SET:
1916 /* Ignore SETs whose result isn't used but not those that
1917 have side-effects. */
1918 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1919 && insn_nothrow_p (insn)
1920 && !side_effects_p (elt))
1921 break;
1923 /* If we have already found a SET, this is a second one and
1924 so we cannot combine with this insn. */
1925 if (set)
1926 return 0;
1928 set = elt;
1929 break;
1931 default:
1932 /* Anything else means we can't combine. */
1933 return 0;
1937 if (set == 0
1938 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1939 so don't do anything with it. */
1940 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1941 return 0;
1943 else
1944 return 0;
1946 if (set == 0)
1947 return 0;
1949 /* The simplification in expand_field_assignment may call back to
1950 get_last_value, so set safe guard here. */
1951 subst_low_luid = DF_INSN_LUID (insn);
1953 set = expand_field_assignment (set);
1954 src = SET_SRC (set), dest = SET_DEST (set);
1956 /* Do not eliminate user-specified register if it is in an
1957 asm input because we may break the register asm usage defined
1958 in GCC manual if allow to do so.
1959 Be aware that this may cover more cases than we expect but this
1960 should be harmless. */
1961 if (REG_P (dest) && REG_USERVAR_P (dest) && HARD_REGISTER_P (dest)
1962 && extract_asm_operands (PATTERN (i3)))
1963 return 0;
1965 /* Don't eliminate a store in the stack pointer. */
1966 if (dest == stack_pointer_rtx
1967 /* Don't combine with an insn that sets a register to itself if it has
1968 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1969 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1970 /* Can't merge an ASM_OPERANDS. */
1971 || GET_CODE (src) == ASM_OPERANDS
1972 /* Can't merge a function call. */
1973 || GET_CODE (src) == CALL
1974 /* Don't eliminate a function call argument. */
1975 || (CALL_P (i3)
1976 && (find_reg_fusage (i3, USE, dest)
1977 || (REG_P (dest)
1978 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1979 && global_regs[REGNO (dest)])))
1980 /* Don't substitute into an incremented register. */
1981 || FIND_REG_INC_NOTE (i3, dest)
1982 || (succ && FIND_REG_INC_NOTE (succ, dest))
1983 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1984 /* Don't substitute into a non-local goto, this confuses CFG. */
1985 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1986 /* Make sure that DEST is not used after INSN but before SUCC, or
1987 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1988 || (!all_adjacent
1989 && ((succ2
1990 && (reg_used_between_p (dest, succ2, i3)
1991 || reg_used_between_p (dest, succ, succ2)))
1992 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))
1993 || (succ
1994 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1995 that case SUCC is not in the insn stream, so use SUCC2
1996 instead for this test. */
1997 && reg_used_between_p (dest, insn,
1998 succ2
1999 && INSN_UID (succ) == INSN_UID (succ2)
2000 ? succ2 : succ))))
2001 /* Make sure that the value that is to be substituted for the register
2002 does not use any registers whose values alter in between. However,
2003 If the insns are adjacent, a use can't cross a set even though we
2004 think it might (this can happen for a sequence of insns each setting
2005 the same destination; last_set of that register might point to
2006 a NOTE). If INSN has a REG_EQUIV note, the register is always
2007 equivalent to the memory so the substitution is valid even if there
2008 are intervening stores. Also, don't move a volatile asm or
2009 UNSPEC_VOLATILE across any other insns. */
2010 || (! all_adjacent
2011 && (((!MEM_P (src)
2012 || ! find_reg_note (insn, REG_EQUIV, src))
2013 && modified_between_p (src, insn, i3))
2014 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
2015 || GET_CODE (src) == UNSPEC_VOLATILE))
2016 /* Don't combine across a CALL_INSN, because that would possibly
2017 change whether the life span of some REGs crosses calls or not,
2018 and it is a pain to update that information.
2019 Exception: if source is a constant, moving it later can't hurt.
2020 Accept that as a special case. */
2021 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
2022 return 0;
2024 /* DEST must either be a REG or CC0. */
2025 if (REG_P (dest))
2027 /* If register alignment is being enforced for multi-word items in all
2028 cases except for parameters, it is possible to have a register copy
2029 insn referencing a hard register that is not allowed to contain the
2030 mode being copied and which would not be valid as an operand of most
2031 insns. Eliminate this problem by not combining with such an insn.
2033 Also, on some machines we don't want to extend the life of a hard
2034 register. */
2036 if (REG_P (src)
2037 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
2038 && !targetm.hard_regno_mode_ok (REGNO (dest), GET_MODE (dest)))
2039 /* Don't extend the life of a hard register unless it is
2040 user variable (if we have few registers) or it can't
2041 fit into the desired register (meaning something special
2042 is going on).
2043 Also avoid substituting a return register into I3, because
2044 reload can't handle a conflict with constraints of other
2045 inputs. */
2046 || (REGNO (src) < FIRST_PSEUDO_REGISTER
2047 && !targetm.hard_regno_mode_ok (REGNO (src),
2048 GET_MODE (src)))))
2049 return 0;
2051 else if (GET_CODE (dest) != CC0)
2052 return 0;
2055 if (GET_CODE (PATTERN (i3)) == PARALLEL)
2056 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
2057 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
2059 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
2061 /* If the clobber represents an earlyclobber operand, we must not
2062 substitute an expression containing the clobbered register.
2063 As we do not analyze the constraint strings here, we have to
2064 make the conservative assumption. However, if the register is
2065 a fixed hard reg, the clobber cannot represent any operand;
2066 we leave it up to the machine description to either accept or
2067 reject use-and-clobber patterns. */
2068 if (!REG_P (reg)
2069 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
2070 || !fixed_regs[REGNO (reg)])
2071 if (reg_overlap_mentioned_p (reg, src))
2072 return 0;
2075 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2076 or not), reject, unless nothing volatile comes between it and I3 */
2078 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
2080 /* Make sure neither succ nor succ2 contains a volatile reference. */
2081 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
2082 return 0;
2083 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
2084 return 0;
2085 /* We'll check insns between INSN and I3 below. */
2088 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2089 to be an explicit register variable, and was chosen for a reason. */
2091 if (GET_CODE (src) == ASM_OPERANDS
2092 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
2093 return 0;
2095 /* If INSN contains volatile references (specifically volatile MEMs),
2096 we cannot combine across any other volatile references.
2097 Even if INSN doesn't contain volatile references, any intervening
2098 volatile insn might affect machine state. */
2100 is_volatile_p = volatile_refs_p (PATTERN (insn))
2101 ? volatile_refs_p
2102 : volatile_insn_p;
2104 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
2105 if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
2106 return 0;
2108 /* If INSN contains an autoincrement or autodecrement, make sure that
2109 register is not used between there and I3, and not already used in
2110 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2111 Also insist that I3 not be a jump; if it were one
2112 and the incremented register were spilled, we would lose. */
2114 if (AUTO_INC_DEC)
2115 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2116 if (REG_NOTE_KIND (link) == REG_INC
2117 && (JUMP_P (i3)
2118 || reg_used_between_p (XEXP (link, 0), insn, i3)
2119 || (pred != NULL_RTX
2120 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
2121 || (pred2 != NULL_RTX
2122 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
2123 || (succ != NULL_RTX
2124 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
2125 || (succ2 != NULL_RTX
2126 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
2127 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
2128 return 0;
2130 /* Don't combine an insn that follows a CC0-setting insn.
2131 An insn that uses CC0 must not be separated from the one that sets it.
2132 We do, however, allow I2 to follow a CC0-setting insn if that insn
2133 is passed as I1; in that case it will be deleted also.
2134 We also allow combining in this case if all the insns are adjacent
2135 because that would leave the two CC0 insns adjacent as well.
2136 It would be more logical to test whether CC0 occurs inside I1 or I2,
2137 but that would be much slower, and this ought to be equivalent. */
2139 if (HAVE_cc0)
2141 p = prev_nonnote_insn (insn);
2142 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2143 && ! all_adjacent)
2144 return 0;
2147 /* If we get here, we have passed all the tests and the combination is
2148 to be allowed. */
2150 *pdest = dest;
2151 *psrc = src;
2153 return 1;
2156 /* LOC is the location within I3 that contains its pattern or the component
2157 of a PARALLEL of the pattern. We validate that it is valid for combining.
2159 One problem is if I3 modifies its output, as opposed to replacing it
2160 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2161 doing so would produce an insn that is not equivalent to the original insns.
2163 Consider:
2165 (set (reg:DI 101) (reg:DI 100))
2166 (set (subreg:SI (reg:DI 101) 0) <foo>)
2168 This is NOT equivalent to:
2170 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2171 (set (reg:DI 101) (reg:DI 100))])
2173 Not only does this modify 100 (in which case it might still be valid
2174 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2176 We can also run into a problem if I2 sets a register that I1
2177 uses and I1 gets directly substituted into I3 (not via I2). In that
2178 case, we would be getting the wrong value of I2DEST into I3, so we
2179 must reject the combination. This case occurs when I2 and I1 both
2180 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2181 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2182 of a SET must prevent combination from occurring. The same situation
2183 can occur for I0, in which case I0_NOT_IN_SRC is set.
2185 Before doing the above check, we first try to expand a field assignment
2186 into a set of logical operations.
2188 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2189 we place a register that is both set and used within I3. If more than one
2190 such register is detected, we fail.
2192 Return 1 if the combination is valid, zero otherwise. */
2194 static int
2195 combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2196 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2198 rtx x = *loc;
2200 if (GET_CODE (x) == SET)
2202 rtx set = x ;
2203 rtx dest = SET_DEST (set);
2204 rtx src = SET_SRC (set);
2205 rtx inner_dest = dest;
2206 rtx subdest;
2208 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2209 || GET_CODE (inner_dest) == SUBREG
2210 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2211 inner_dest = XEXP (inner_dest, 0);
2213 /* Check for the case where I3 modifies its output, as discussed
2214 above. We don't want to prevent pseudos from being combined
2215 into the address of a MEM, so only prevent the combination if
2216 i1 or i2 set the same MEM. */
2217 if ((inner_dest != dest &&
2218 (!MEM_P (inner_dest)
2219 || rtx_equal_p (i2dest, inner_dest)
2220 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2221 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2222 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2223 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2224 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2226 /* This is the same test done in can_combine_p except we can't test
2227 all_adjacent; we don't have to, since this instruction will stay
2228 in place, thus we are not considering increasing the lifetime of
2229 INNER_DEST.
2231 Also, if this insn sets a function argument, combining it with
2232 something that might need a spill could clobber a previous
2233 function argument; the all_adjacent test in can_combine_p also
2234 checks this; here, we do a more specific test for this case. */
2236 || (REG_P (inner_dest)
2237 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2238 && !targetm.hard_regno_mode_ok (REGNO (inner_dest),
2239 GET_MODE (inner_dest)))
2240 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2241 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2242 return 0;
2244 /* If DEST is used in I3, it is being killed in this insn, so
2245 record that for later. We have to consider paradoxical
2246 subregs here, since they kill the whole register, but we
2247 ignore partial subregs, STRICT_LOW_PART, etc.
2248 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2249 STACK_POINTER_REGNUM, since these are always considered to be
2250 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2251 subdest = dest;
2252 if (GET_CODE (subdest) == SUBREG && !partial_subreg_p (subdest))
2253 subdest = SUBREG_REG (subdest);
2254 if (pi3dest_killed
2255 && REG_P (subdest)
2256 && reg_referenced_p (subdest, PATTERN (i3))
2257 && REGNO (subdest) != FRAME_POINTER_REGNUM
2258 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2259 || REGNO (subdest) != HARD_FRAME_POINTER_REGNUM)
2260 && (FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM
2261 || (REGNO (subdest) != ARG_POINTER_REGNUM
2262 || ! fixed_regs [REGNO (subdest)]))
2263 && REGNO (subdest) != STACK_POINTER_REGNUM)
2265 if (*pi3dest_killed)
2266 return 0;
2268 *pi3dest_killed = subdest;
2272 else if (GET_CODE (x) == PARALLEL)
2274 int i;
2276 for (i = 0; i < XVECLEN (x, 0); i++)
2277 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2278 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2279 return 0;
2282 return 1;
2285 /* Return 1 if X is an arithmetic expression that contains a multiplication
2286 and division. We don't count multiplications by powers of two here. */
2288 static int
2289 contains_muldiv (rtx x)
2291 switch (GET_CODE (x))
2293 case MOD: case DIV: case UMOD: case UDIV:
2294 return 1;
2296 case MULT:
2297 return ! (CONST_INT_P (XEXP (x, 1))
2298 && pow2p_hwi (UINTVAL (XEXP (x, 1))));
2299 default:
2300 if (BINARY_P (x))
2301 return contains_muldiv (XEXP (x, 0))
2302 || contains_muldiv (XEXP (x, 1));
2304 if (UNARY_P (x))
2305 return contains_muldiv (XEXP (x, 0));
2307 return 0;
2311 /* Determine whether INSN can be used in a combination. Return nonzero if
2312 not. This is used in try_combine to detect early some cases where we
2313 can't perform combinations. */
2315 static int
2316 cant_combine_insn_p (rtx_insn *insn)
2318 rtx set;
2319 rtx src, dest;
2321 /* If this isn't really an insn, we can't do anything.
2322 This can occur when flow deletes an insn that it has merged into an
2323 auto-increment address. */
2324 if (!NONDEBUG_INSN_P (insn))
2325 return 1;
2327 /* Never combine loads and stores involving hard regs that are likely
2328 to be spilled. The register allocator can usually handle such
2329 reg-reg moves by tying. If we allow the combiner to make
2330 substitutions of likely-spilled regs, reload might die.
2331 As an exception, we allow combinations involving fixed regs; these are
2332 not available to the register allocator so there's no risk involved. */
2334 set = single_set (insn);
2335 if (! set)
2336 return 0;
2337 src = SET_SRC (set);
2338 dest = SET_DEST (set);
2339 if (GET_CODE (src) == SUBREG)
2340 src = SUBREG_REG (src);
2341 if (GET_CODE (dest) == SUBREG)
2342 dest = SUBREG_REG (dest);
2343 if (REG_P (src) && REG_P (dest)
2344 && ((HARD_REGISTER_P (src)
2345 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2346 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2347 || (HARD_REGISTER_P (dest)
2348 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2349 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2350 return 1;
2352 return 0;
2355 struct likely_spilled_retval_info
2357 unsigned regno, nregs;
2358 unsigned mask;
2361 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2362 hard registers that are known to be written to / clobbered in full. */
2363 static void
2364 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2366 struct likely_spilled_retval_info *const info =
2367 (struct likely_spilled_retval_info *) data;
2368 unsigned regno, nregs;
2369 unsigned new_mask;
2371 if (!REG_P (XEXP (set, 0)))
2372 return;
2373 regno = REGNO (x);
2374 if (regno >= info->regno + info->nregs)
2375 return;
2376 nregs = REG_NREGS (x);
2377 if (regno + nregs <= info->regno)
2378 return;
2379 new_mask = (2U << (nregs - 1)) - 1;
2380 if (regno < info->regno)
2381 new_mask >>= info->regno - regno;
2382 else
2383 new_mask <<= regno - info->regno;
2384 info->mask &= ~new_mask;
2387 /* Return nonzero iff part of the return value is live during INSN, and
2388 it is likely spilled. This can happen when more than one insn is needed
2389 to copy the return value, e.g. when we consider to combine into the
2390 second copy insn for a complex value. */
2392 static int
2393 likely_spilled_retval_p (rtx_insn *insn)
2395 rtx_insn *use = BB_END (this_basic_block);
2396 rtx reg;
2397 rtx_insn *p;
2398 unsigned regno, nregs;
2399 /* We assume here that no machine mode needs more than
2400 32 hard registers when the value overlaps with a register
2401 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2402 unsigned mask;
2403 struct likely_spilled_retval_info info;
2405 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2406 return 0;
2407 reg = XEXP (PATTERN (use), 0);
2408 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2409 return 0;
2410 regno = REGNO (reg);
2411 nregs = REG_NREGS (reg);
2412 if (nregs == 1)
2413 return 0;
2414 mask = (2U << (nregs - 1)) - 1;
2416 /* Disregard parts of the return value that are set later. */
2417 info.regno = regno;
2418 info.nregs = nregs;
2419 info.mask = mask;
2420 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2421 if (INSN_P (p))
2422 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2423 mask = info.mask;
2425 /* Check if any of the (probably) live return value registers is
2426 likely spilled. */
2427 nregs --;
2430 if ((mask & 1 << nregs)
2431 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2432 return 1;
2433 } while (nregs--);
2434 return 0;
2437 /* Adjust INSN after we made a change to its destination.
2439 Changing the destination can invalidate notes that say something about
2440 the results of the insn and a LOG_LINK pointing to the insn. */
2442 static void
2443 adjust_for_new_dest (rtx_insn *insn)
2445 /* For notes, be conservative and simply remove them. */
2446 remove_reg_equal_equiv_notes (insn);
2448 /* The new insn will have a destination that was previously the destination
2449 of an insn just above it. Call distribute_links to make a LOG_LINK from
2450 the next use of that destination. */
2452 rtx set = single_set (insn);
2453 gcc_assert (set);
2455 rtx reg = SET_DEST (set);
2457 while (GET_CODE (reg) == ZERO_EXTRACT
2458 || GET_CODE (reg) == STRICT_LOW_PART
2459 || GET_CODE (reg) == SUBREG)
2460 reg = XEXP (reg, 0);
2461 gcc_assert (REG_P (reg));
2463 distribute_links (alloc_insn_link (insn, REGNO (reg), NULL));
2465 df_insn_rescan (insn);
2468 /* Return TRUE if combine can reuse reg X in mode MODE.
2469 ADDED_SETS is nonzero if the original set is still required. */
2470 static bool
2471 can_change_dest_mode (rtx x, int added_sets, machine_mode mode)
2473 unsigned int regno;
2475 if (!REG_P (x))
2476 return false;
2478 /* Don't change between modes with different underlying register sizes,
2479 since this could lead to invalid subregs. */
2480 if (maybe_ne (REGMODE_NATURAL_SIZE (mode),
2481 REGMODE_NATURAL_SIZE (GET_MODE (x))))
2482 return false;
2484 regno = REGNO (x);
2485 /* Allow hard registers if the new mode is legal, and occupies no more
2486 registers than the old mode. */
2487 if (regno < FIRST_PSEUDO_REGISTER)
2488 return (targetm.hard_regno_mode_ok (regno, mode)
2489 && REG_NREGS (x) >= hard_regno_nregs (regno, mode));
2491 /* Or a pseudo that is only used once. */
2492 return (regno < reg_n_sets_max
2493 && REG_N_SETS (regno) == 1
2494 && !added_sets
2495 && !REG_USERVAR_P (x));
2499 /* Check whether X, the destination of a set, refers to part of
2500 the register specified by REG. */
2502 static bool
2503 reg_subword_p (rtx x, rtx reg)
2505 /* Check that reg is an integer mode register. */
2506 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2507 return false;
2509 if (GET_CODE (x) == STRICT_LOW_PART
2510 || GET_CODE (x) == ZERO_EXTRACT)
2511 x = XEXP (x, 0);
2513 return GET_CODE (x) == SUBREG
2514 && SUBREG_REG (x) == reg
2515 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2518 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2519 Note that the INSN should be deleted *after* removing dead edges, so
2520 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2521 but not for a (set (pc) (label_ref FOO)). */
2523 static void
2524 update_cfg_for_uncondjump (rtx_insn *insn)
2526 basic_block bb = BLOCK_FOR_INSN (insn);
2527 gcc_assert (BB_END (bb) == insn);
2529 purge_dead_edges (bb);
2531 delete_insn (insn);
2532 if (EDGE_COUNT (bb->succs) == 1)
2534 rtx_insn *insn;
2536 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2538 /* Remove barriers from the footer if there are any. */
2539 for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn))
2540 if (BARRIER_P (insn))
2542 if (PREV_INSN (insn))
2543 SET_NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2544 else
2545 BB_FOOTER (bb) = NEXT_INSN (insn);
2546 if (NEXT_INSN (insn))
2547 SET_PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2549 else if (LABEL_P (insn))
2550 break;
2554 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2555 by an arbitrary number of CLOBBERs. */
2556 static bool
2557 is_parallel_of_n_reg_sets (rtx pat, int n)
2559 if (GET_CODE (pat) != PARALLEL)
2560 return false;
2562 int len = XVECLEN (pat, 0);
2563 if (len < n)
2564 return false;
2566 int i;
2567 for (i = 0; i < n; i++)
2568 if (GET_CODE (XVECEXP (pat, 0, i)) != SET
2569 || !REG_P (SET_DEST (XVECEXP (pat, 0, i))))
2570 return false;
2571 for ( ; i < len; i++)
2572 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER
2573 || XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
2574 return false;
2576 return true;
2579 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2580 CLOBBERs), can be split into individual SETs in that order, without
2581 changing semantics. */
2582 static bool
2583 can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n)
2585 if (!insn_nothrow_p (insn))
2586 return false;
2588 rtx pat = PATTERN (insn);
2590 int i, j;
2591 for (i = 0; i < n; i++)
2593 if (side_effects_p (SET_SRC (XVECEXP (pat, 0, i))))
2594 return false;
2596 rtx reg = SET_DEST (XVECEXP (pat, 0, i));
2598 for (j = i + 1; j < n; j++)
2599 if (reg_referenced_p (reg, XVECEXP (pat, 0, j)))
2600 return false;
2603 return true;
2606 /* Try to combine the insns I0, I1 and I2 into I3.
2607 Here I0, I1 and I2 appear earlier than I3.
2608 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2611 If we are combining more than two insns and the resulting insn is not
2612 recognized, try splitting it into two insns. If that happens, I2 and I3
2613 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2614 Otherwise, I0, I1 and I2 are pseudo-deleted.
2616 Return 0 if the combination does not work. Then nothing is changed.
2617 If we did the combination, return the insn at which combine should
2618 resume scanning.
2620 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2621 new direct jump instruction.
2623 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2624 been I3 passed to an earlier try_combine within the same basic
2625 block. */
2627 static rtx_insn *
2628 try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
2629 int *new_direct_jump_p, rtx_insn *last_combined_insn)
2631 /* New patterns for I3 and I2, respectively. */
2632 rtx newpat, newi2pat = 0;
2633 rtvec newpat_vec_with_clobbers = 0;
2634 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2635 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2636 dead. */
2637 int added_sets_0, added_sets_1, added_sets_2;
2638 /* Total number of SETs to put into I3. */
2639 int total_sets;
2640 /* Nonzero if I2's or I1's body now appears in I3. */
2641 int i2_is_used = 0, i1_is_used = 0;
2642 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2643 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2644 /* Contains I3 if the destination of I3 is used in its source, which means
2645 that the old life of I3 is being killed. If that usage is placed into
2646 I2 and not in I3, a REG_DEAD note must be made. */
2647 rtx i3dest_killed = 0;
2648 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2649 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2650 /* Copy of SET_SRC of I1 and I0, if needed. */
2651 rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2652 /* Set if I2DEST was reused as a scratch register. */
2653 bool i2scratch = false;
2654 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2655 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2656 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2657 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2658 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2659 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2660 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2661 /* Notes that must be added to REG_NOTES in I3 and I2. */
2662 rtx new_i3_notes, new_i2_notes;
2663 /* Notes that we substituted I3 into I2 instead of the normal case. */
2664 int i3_subst_into_i2 = 0;
2665 /* Notes that I1, I2 or I3 is a MULT operation. */
2666 int have_mult = 0;
2667 int swap_i2i3 = 0;
2668 int changed_i3_dest = 0;
2670 int maxreg;
2671 rtx_insn *temp_insn;
2672 rtx temp_expr;
2673 struct insn_link *link;
2674 rtx other_pat = 0;
2675 rtx new_other_notes;
2676 int i;
2677 scalar_int_mode dest_mode, temp_mode;
2679 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2680 never be). */
2681 if (i1 == i2 || i0 == i2 || (i0 && i0 == i1))
2682 return 0;
2684 /* Only try four-insn combinations when there's high likelihood of
2685 success. Look for simple insns, such as loads of constants or
2686 binary operations involving a constant. */
2687 if (i0)
2689 int i;
2690 int ngood = 0;
2691 int nshift = 0;
2692 rtx set0, set3;
2694 if (!flag_expensive_optimizations)
2695 return 0;
2697 for (i = 0; i < 4; i++)
2699 rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2700 rtx set = single_set (insn);
2701 rtx src;
2702 if (!set)
2703 continue;
2704 src = SET_SRC (set);
2705 if (CONSTANT_P (src))
2707 ngood += 2;
2708 break;
2710 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2711 ngood++;
2712 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2713 || GET_CODE (src) == LSHIFTRT)
2714 nshift++;
2717 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2718 are likely manipulating its value. Ideally we'll be able to combine
2719 all four insns into a bitfield insertion of some kind.
2721 Note the source in I0 might be inside a sign/zero extension and the
2722 memory modes in I0 and I3 might be different. So extract the address
2723 from the destination of I3 and search for it in the source of I0.
2725 In the event that there's a match but the source/dest do not actually
2726 refer to the same memory, the worst that happens is we try some
2727 combinations that we wouldn't have otherwise. */
2728 if ((set0 = single_set (i0))
2729 /* Ensure the source of SET0 is a MEM, possibly buried inside
2730 an extension. */
2731 && (GET_CODE (SET_SRC (set0)) == MEM
2732 || ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND
2733 || GET_CODE (SET_SRC (set0)) == SIGN_EXTEND)
2734 && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM))
2735 && (set3 = single_set (i3))
2736 /* Ensure the destination of SET3 is a MEM. */
2737 && GET_CODE (SET_DEST (set3)) == MEM
2738 /* Would it be better to extract the base address for the MEM
2739 in SET3 and look for that? I don't have cases where it matters
2740 but I could envision such cases. */
2741 && rtx_referenced_p (XEXP (SET_DEST (set3), 0), SET_SRC (set0)))
2742 ngood += 2;
2744 if (ngood < 2 && nshift < 2)
2745 return 0;
2748 /* Exit early if one of the insns involved can't be used for
2749 combinations. */
2750 if (CALL_P (i2)
2751 || (i1 && CALL_P (i1))
2752 || (i0 && CALL_P (i0))
2753 || cant_combine_insn_p (i3)
2754 || cant_combine_insn_p (i2)
2755 || (i1 && cant_combine_insn_p (i1))
2756 || (i0 && cant_combine_insn_p (i0))
2757 || likely_spilled_retval_p (i3))
2758 return 0;
2760 combine_attempts++;
2761 undobuf.other_insn = 0;
2763 /* Reset the hard register usage information. */
2764 CLEAR_HARD_REG_SET (newpat_used_regs);
2766 if (dump_file && (dump_flags & TDF_DETAILS))
2768 if (i0)
2769 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2770 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2771 else if (i1)
2772 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2773 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2774 else
2775 fprintf (dump_file, "\nTrying %d -> %d:\n",
2776 INSN_UID (i2), INSN_UID (i3));
2778 if (i0)
2779 dump_insn_slim (dump_file, i0);
2780 if (i1)
2781 dump_insn_slim (dump_file, i1);
2782 dump_insn_slim (dump_file, i2);
2783 dump_insn_slim (dump_file, i3);
2786 /* If multiple insns feed into one of I2 or I3, they can be in any
2787 order. To simplify the code below, reorder them in sequence. */
2788 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2789 std::swap (i0, i2);
2790 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2791 std::swap (i0, i1);
2792 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2793 std::swap (i1, i2);
2795 added_links_insn = 0;
2796 added_notes_insn = 0;
2798 /* First check for one important special case that the code below will
2799 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2800 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2801 we may be able to replace that destination with the destination of I3.
2802 This occurs in the common code where we compute both a quotient and
2803 remainder into a structure, in which case we want to do the computation
2804 directly into the structure to avoid register-register copies.
2806 Note that this case handles both multiple sets in I2 and also cases
2807 where I2 has a number of CLOBBERs inside the PARALLEL.
2809 We make very conservative checks below and only try to handle the
2810 most common cases of this. For example, we only handle the case
2811 where I2 and I3 are adjacent to avoid making difficult register
2812 usage tests. */
2814 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2815 && REG_P (SET_SRC (PATTERN (i3)))
2816 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2817 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2818 && GET_CODE (PATTERN (i2)) == PARALLEL
2819 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2820 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2821 below would need to check what is inside (and reg_overlap_mentioned_p
2822 doesn't support those codes anyway). Don't allow those destinations;
2823 the resulting insn isn't likely to be recognized anyway. */
2824 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2825 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2826 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2827 SET_DEST (PATTERN (i3)))
2828 && next_active_insn (i2) == i3)
2830 rtx p2 = PATTERN (i2);
2832 /* Make sure that the destination of I3,
2833 which we are going to substitute into one output of I2,
2834 is not used within another output of I2. We must avoid making this:
2835 (parallel [(set (mem (reg 69)) ...)
2836 (set (reg 69) ...)])
2837 which is not well-defined as to order of actions.
2838 (Besides, reload can't handle output reloads for this.)
2840 The problem can also happen if the dest of I3 is a memory ref,
2841 if another dest in I2 is an indirect memory ref.
2843 Neither can this PARALLEL be an asm. We do not allow combining
2844 that usually (see can_combine_p), so do not here either. */
2845 bool ok = true;
2846 for (i = 0; ok && i < XVECLEN (p2, 0); i++)
2848 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2849 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2850 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2851 SET_DEST (XVECEXP (p2, 0, i))))
2852 ok = false;
2853 else if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2854 && GET_CODE (SET_SRC (XVECEXP (p2, 0, i))) == ASM_OPERANDS)
2855 ok = false;
2858 if (ok)
2859 for (i = 0; i < XVECLEN (p2, 0); i++)
2860 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2861 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2863 combine_merges++;
2865 subst_insn = i3;
2866 subst_low_luid = DF_INSN_LUID (i2);
2868 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2869 i2src = SET_SRC (XVECEXP (p2, 0, i));
2870 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2871 i2dest_killed = dead_or_set_p (i2, i2dest);
2873 /* Replace the dest in I2 with our dest and make the resulting
2874 insn the new pattern for I3. Then skip to where we validate
2875 the pattern. Everything was set up above. */
2876 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2877 newpat = p2;
2878 i3_subst_into_i2 = 1;
2879 goto validate_replacement;
2883 /* If I2 is setting a pseudo to a constant and I3 is setting some
2884 sub-part of it to another constant, merge them by making a new
2885 constant. */
2886 if (i1 == 0
2887 && (temp_expr = single_set (i2)) != 0
2888 && is_a <scalar_int_mode> (GET_MODE (SET_DEST (temp_expr)), &temp_mode)
2889 && CONST_SCALAR_INT_P (SET_SRC (temp_expr))
2890 && GET_CODE (PATTERN (i3)) == SET
2891 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2892 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr)))
2894 rtx dest = SET_DEST (PATTERN (i3));
2895 rtx temp_dest = SET_DEST (temp_expr);
2896 int offset = -1;
2897 int width = 0;
2899 if (GET_CODE (dest) == ZERO_EXTRACT)
2901 if (CONST_INT_P (XEXP (dest, 1))
2902 && CONST_INT_P (XEXP (dest, 2))
2903 && is_a <scalar_int_mode> (GET_MODE (XEXP (dest, 0)),
2904 &dest_mode))
2906 width = INTVAL (XEXP (dest, 1));
2907 offset = INTVAL (XEXP (dest, 2));
2908 dest = XEXP (dest, 0);
2909 if (BITS_BIG_ENDIAN)
2910 offset = GET_MODE_PRECISION (dest_mode) - width - offset;
2913 else
2915 if (GET_CODE (dest) == STRICT_LOW_PART)
2916 dest = XEXP (dest, 0);
2917 if (is_a <scalar_int_mode> (GET_MODE (dest), &dest_mode))
2919 width = GET_MODE_PRECISION (dest_mode);
2920 offset = 0;
2924 if (offset >= 0)
2926 /* If this is the low part, we're done. */
2927 if (subreg_lowpart_p (dest))
2929 /* Handle the case where inner is twice the size of outer. */
2930 else if (GET_MODE_PRECISION (temp_mode)
2931 == 2 * GET_MODE_PRECISION (dest_mode))
2932 offset += GET_MODE_PRECISION (dest_mode);
2933 /* Otherwise give up for now. */
2934 else
2935 offset = -1;
2938 if (offset >= 0)
2940 rtx inner = SET_SRC (PATTERN (i3));
2941 rtx outer = SET_SRC (temp_expr);
2943 wide_int o = wi::insert (rtx_mode_t (outer, temp_mode),
2944 rtx_mode_t (inner, dest_mode),
2945 offset, width);
2947 combine_merges++;
2948 subst_insn = i3;
2949 subst_low_luid = DF_INSN_LUID (i2);
2950 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2951 i2dest = temp_dest;
2952 i2dest_killed = dead_or_set_p (i2, i2dest);
2954 /* Replace the source in I2 with the new constant and make the
2955 resulting insn the new pattern for I3. Then skip to where we
2956 validate the pattern. Everything was set up above. */
2957 SUBST (SET_SRC (temp_expr),
2958 immed_wide_int_const (o, temp_mode));
2960 newpat = PATTERN (i2);
2962 /* The dest of I3 has been replaced with the dest of I2. */
2963 changed_i3_dest = 1;
2964 goto validate_replacement;
2968 /* If we have no I1 and I2 looks like:
2969 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2970 (set Y OP)])
2971 make up a dummy I1 that is
2972 (set Y OP)
2973 and change I2 to be
2974 (set (reg:CC X) (compare:CC Y (const_int 0)))
2976 (We can ignore any trailing CLOBBERs.)
2978 This undoes a previous combination and allows us to match a branch-and-
2979 decrement insn. */
2981 if (!HAVE_cc0 && i1 == 0
2982 && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
2983 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2984 == MODE_CC)
2985 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2986 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2987 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2988 SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))
2989 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2990 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2992 /* We make I1 with the same INSN_UID as I2. This gives it
2993 the same DF_INSN_LUID for value tracking. Our fake I1 will
2994 never appear in the insn stream so giving it the same INSN_UID
2995 as I2 will not cause a problem. */
2997 i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2998 XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2),
2999 -1, NULL_RTX);
3000 INSN_UID (i1) = INSN_UID (i2);
3002 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
3003 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
3004 SET_DEST (PATTERN (i1)));
3005 unsigned int regno = REGNO (SET_DEST (PATTERN (i1)));
3006 SUBST_LINK (LOG_LINKS (i2),
3007 alloc_insn_link (i1, regno, LOG_LINKS (i2)));
3010 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3011 make those two SETs separate I1 and I2 insns, and make an I0 that is
3012 the original I1. */
3013 if (!HAVE_cc0 && i0 == 0
3014 && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
3015 && can_split_parallel_of_n_reg_sets (i2, 2)
3016 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
3017 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3)
3018 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
3019 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
3021 /* If there is no I1, there is no I0 either. */
3022 i0 = i1;
3024 /* We make I1 with the same INSN_UID as I2. This gives it
3025 the same DF_INSN_LUID for value tracking. Our fake I1 will
3026 never appear in the insn stream so giving it the same INSN_UID
3027 as I2 will not cause a problem. */
3029 i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
3030 XVECEXP (PATTERN (i2), 0, 0), INSN_LOCATION (i2),
3031 -1, NULL_RTX);
3032 INSN_UID (i1) = INSN_UID (i2);
3034 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 1));
3037 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
3038 if (!can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src))
3040 if (dump_file)
3041 fprintf (dump_file, "Can't combine i2 into i3\n");
3042 undo_all ();
3043 return 0;
3045 if (i1 && !can_combine_p (i1, i3, i0, NULL, i2, NULL, &i1dest, &i1src))
3047 if (dump_file)
3048 fprintf (dump_file, "Can't combine i1 into i3\n");
3049 undo_all ();
3050 return 0;
3052 if (i0 && !can_combine_p (i0, i3, NULL, NULL, i1, i2, &i0dest, &i0src))
3054 if (dump_file)
3055 fprintf (dump_file, "Can't combine i0 into i3\n");
3056 undo_all ();
3057 return 0;
3060 /* Record whether I2DEST is used in I2SRC and similarly for the other
3061 cases. Knowing this will help in register status updating below. */
3062 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
3063 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
3064 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
3065 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
3066 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
3067 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
3068 i2dest_killed = dead_or_set_p (i2, i2dest);
3069 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
3070 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
3072 /* For the earlier insns, determine which of the subsequent ones they
3073 feed. */
3074 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
3075 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
3076 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
3077 : (!reg_overlap_mentioned_p (i1dest, i0dest)
3078 && reg_overlap_mentioned_p (i0dest, i2src))));
3080 /* Ensure that I3's pattern can be the destination of combines. */
3081 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
3082 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
3083 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
3084 || (i1dest_in_i0src && !i0_feeds_i1_n)),
3085 &i3dest_killed))
3087 undo_all ();
3088 return 0;
3091 /* See if any of the insns is a MULT operation. Unless one is, we will
3092 reject a combination that is, since it must be slower. Be conservative
3093 here. */
3094 if (GET_CODE (i2src) == MULT
3095 || (i1 != 0 && GET_CODE (i1src) == MULT)
3096 || (i0 != 0 && GET_CODE (i0src) == MULT)
3097 || (GET_CODE (PATTERN (i3)) == SET
3098 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
3099 have_mult = 1;
3101 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3102 We used to do this EXCEPT in one case: I3 has a post-inc in an
3103 output operand. However, that exception can give rise to insns like
3104 mov r3,(r3)+
3105 which is a famous insn on the PDP-11 where the value of r3 used as the
3106 source was model-dependent. Avoid this sort of thing. */
3108 #if 0
3109 if (!(GET_CODE (PATTERN (i3)) == SET
3110 && REG_P (SET_SRC (PATTERN (i3)))
3111 && MEM_P (SET_DEST (PATTERN (i3)))
3112 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
3113 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
3114 /* It's not the exception. */
3115 #endif
3116 if (AUTO_INC_DEC)
3118 rtx link;
3119 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
3120 if (REG_NOTE_KIND (link) == REG_INC
3121 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
3122 || (i1 != 0
3123 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
3125 undo_all ();
3126 return 0;
3130 /* See if the SETs in I1 or I2 need to be kept around in the merged
3131 instruction: whenever the value set there is still needed past I3.
3132 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3134 For the SET in I1, we have two cases: if I1 and I2 independently feed
3135 into I3, the set in I1 needs to be kept around unless I1DEST dies
3136 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3137 in I1 needs to be kept around unless I1DEST dies or is set in either
3138 I2 or I3. The same considerations apply to I0. */
3140 added_sets_2 = !dead_or_set_p (i3, i2dest);
3142 if (i1)
3143 added_sets_1 = !(dead_or_set_p (i3, i1dest)
3144 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
3145 else
3146 added_sets_1 = 0;
3148 if (i0)
3149 added_sets_0 = !(dead_or_set_p (i3, i0dest)
3150 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
3151 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3152 && dead_or_set_p (i2, i0dest)));
3153 else
3154 added_sets_0 = 0;
3156 /* We are about to copy insns for the case where they need to be kept
3157 around. Check that they can be copied in the merged instruction. */
3159 if (targetm.cannot_copy_insn_p
3160 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3161 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3162 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3164 undo_all ();
3165 return 0;
3168 /* If the set in I2 needs to be kept around, we must make a copy of
3169 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3170 PATTERN (I2), we are only substituting for the original I1DEST, not into
3171 an already-substituted copy. This also prevents making self-referential
3172 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3173 I2DEST. */
3175 if (added_sets_2)
3177 if (GET_CODE (PATTERN (i2)) == PARALLEL)
3178 i2pat = gen_rtx_SET (i2dest, copy_rtx (i2src));
3179 else
3180 i2pat = copy_rtx (PATTERN (i2));
3183 if (added_sets_1)
3185 if (GET_CODE (PATTERN (i1)) == PARALLEL)
3186 i1pat = gen_rtx_SET (i1dest, copy_rtx (i1src));
3187 else
3188 i1pat = copy_rtx (PATTERN (i1));
3191 if (added_sets_0)
3193 if (GET_CODE (PATTERN (i0)) == PARALLEL)
3194 i0pat = gen_rtx_SET (i0dest, copy_rtx (i0src));
3195 else
3196 i0pat = copy_rtx (PATTERN (i0));
3199 combine_merges++;
3201 /* Substitute in the latest insn for the regs set by the earlier ones. */
3203 maxreg = max_reg_num ();
3205 subst_insn = i3;
3207 /* Many machines that don't use CC0 have insns that can both perform an
3208 arithmetic operation and set the condition code. These operations will
3209 be represented as a PARALLEL with the first element of the vector
3210 being a COMPARE of an arithmetic operation with the constant zero.
3211 The second element of the vector will set some pseudo to the result
3212 of the same arithmetic operation. If we simplify the COMPARE, we won't
3213 match such a pattern and so will generate an extra insn. Here we test
3214 for this case, where both the comparison and the operation result are
3215 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3216 I2SRC. Later we will make the PARALLEL that contains I2. */
3218 if (!HAVE_cc0 && i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3219 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3220 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3221 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3223 rtx newpat_dest;
3224 rtx *cc_use_loc = NULL;
3225 rtx_insn *cc_use_insn = NULL;
3226 rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3227 machine_mode compare_mode, orig_compare_mode;
3228 enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3229 scalar_int_mode mode;
3231 newpat = PATTERN (i3);
3232 newpat_dest = SET_DEST (newpat);
3233 compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3235 if (undobuf.other_insn == 0
3236 && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
3237 &cc_use_insn)))
3239 compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3240 if (is_a <scalar_int_mode> (GET_MODE (i2dest), &mode))
3241 compare_code = simplify_compare_const (compare_code, mode,
3242 op0, &op1);
3243 target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
3246 /* Do the rest only if op1 is const0_rtx, which may be the
3247 result of simplification. */
3248 if (op1 == const0_rtx)
3250 /* If a single use of the CC is found, prepare to modify it
3251 when SELECT_CC_MODE returns a new CC-class mode, or when
3252 the above simplify_compare_const() returned a new comparison
3253 operator. undobuf.other_insn is assigned the CC use insn
3254 when modifying it. */
3255 if (cc_use_loc)
3257 #ifdef SELECT_CC_MODE
3258 machine_mode new_mode
3259 = SELECT_CC_MODE (compare_code, op0, op1);
3260 if (new_mode != orig_compare_mode
3261 && can_change_dest_mode (SET_DEST (newpat),
3262 added_sets_2, new_mode))
3264 unsigned int regno = REGNO (newpat_dest);
3265 compare_mode = new_mode;
3266 if (regno < FIRST_PSEUDO_REGISTER)
3267 newpat_dest = gen_rtx_REG (compare_mode, regno);
3268 else
3270 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3271 newpat_dest = regno_reg_rtx[regno];
3274 #endif
3275 /* Cases for modifying the CC-using comparison. */
3276 if (compare_code != orig_compare_code
3277 /* ??? Do we need to verify the zero rtx? */
3278 && XEXP (*cc_use_loc, 1) == const0_rtx)
3280 /* Replace cc_use_loc with entire new RTX. */
3281 SUBST (*cc_use_loc,
3282 gen_rtx_fmt_ee (compare_code, compare_mode,
3283 newpat_dest, const0_rtx));
3284 undobuf.other_insn = cc_use_insn;
3286 else if (compare_mode != orig_compare_mode)
3288 /* Just replace the CC reg with a new mode. */
3289 SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3290 undobuf.other_insn = cc_use_insn;
3294 /* Now we modify the current newpat:
3295 First, SET_DEST(newpat) is updated if the CC mode has been
3296 altered. For targets without SELECT_CC_MODE, this should be
3297 optimized away. */
3298 if (compare_mode != orig_compare_mode)
3299 SUBST (SET_DEST (newpat), newpat_dest);
3300 /* This is always done to propagate i2src into newpat. */
3301 SUBST (SET_SRC (newpat),
3302 gen_rtx_COMPARE (compare_mode, op0, op1));
3303 /* Create new version of i2pat if needed; the below PARALLEL
3304 creation needs this to work correctly. */
3305 if (! rtx_equal_p (i2src, op0))
3306 i2pat = gen_rtx_SET (i2dest, op0);
3307 i2_is_used = 1;
3311 if (i2_is_used == 0)
3313 /* It is possible that the source of I2 or I1 may be performing
3314 an unneeded operation, such as a ZERO_EXTEND of something
3315 that is known to have the high part zero. Handle that case
3316 by letting subst look at the inner insns.
3318 Another way to do this would be to have a function that tries
3319 to simplify a single insn instead of merging two or more
3320 insns. We don't do this because of the potential of infinite
3321 loops and because of the potential extra memory required.
3322 However, doing it the way we are is a bit of a kludge and
3323 doesn't catch all cases.
3325 But only do this if -fexpensive-optimizations since it slows
3326 things down and doesn't usually win.
3328 This is not done in the COMPARE case above because the
3329 unmodified I2PAT is used in the PARALLEL and so a pattern
3330 with a modified I2SRC would not match. */
3332 if (flag_expensive_optimizations)
3334 /* Pass pc_rtx so no substitutions are done, just
3335 simplifications. */
3336 if (i1)
3338 subst_low_luid = DF_INSN_LUID (i1);
3339 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3342 subst_low_luid = DF_INSN_LUID (i2);
3343 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3346 n_occurrences = 0; /* `subst' counts here */
3347 subst_low_luid = DF_INSN_LUID (i2);
3349 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3350 copy of I2SRC each time we substitute it, in order to avoid creating
3351 self-referential RTL when we will be substituting I1SRC for I1DEST
3352 later. Likewise if I0 feeds into I2, either directly or indirectly
3353 through I1, and I0DEST is in I0SRC. */
3354 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3355 (i1_feeds_i2_n && i1dest_in_i1src)
3356 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3357 && i0dest_in_i0src));
3358 substed_i2 = 1;
3360 /* Record whether I2's body now appears within I3's body. */
3361 i2_is_used = n_occurrences;
3364 /* If we already got a failure, don't try to do more. Otherwise, try to
3365 substitute I1 if we have it. */
3367 if (i1 && GET_CODE (newpat) != CLOBBER)
3369 /* Check that an autoincrement side-effect on I1 has not been lost.
3370 This happens if I1DEST is mentioned in I2 and dies there, and
3371 has disappeared from the new pattern. */
3372 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3373 && i1_feeds_i2_n
3374 && dead_or_set_p (i2, i1dest)
3375 && !reg_overlap_mentioned_p (i1dest, newpat))
3376 /* Before we can do this substitution, we must redo the test done
3377 above (see detailed comments there) that ensures I1DEST isn't
3378 mentioned in any SETs in NEWPAT that are field assignments. */
3379 || !combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX,
3380 0, 0, 0))
3382 undo_all ();
3383 return 0;
3386 n_occurrences = 0;
3387 subst_low_luid = DF_INSN_LUID (i1);
3389 /* If the following substitution will modify I1SRC, make a copy of it
3390 for the case where it is substituted for I1DEST in I2PAT later. */
3391 if (added_sets_2 && i1_feeds_i2_n)
3392 i1src_copy = copy_rtx (i1src);
3394 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3395 copy of I1SRC each time we substitute it, in order to avoid creating
3396 self-referential RTL when we will be substituting I0SRC for I0DEST
3397 later. */
3398 newpat = subst (newpat, i1dest, i1src, 0, 0,
3399 i0_feeds_i1_n && i0dest_in_i0src);
3400 substed_i1 = 1;
3402 /* Record whether I1's body now appears within I3's body. */
3403 i1_is_used = n_occurrences;
3406 /* Likewise for I0 if we have it. */
3408 if (i0 && GET_CODE (newpat) != CLOBBER)
3410 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3411 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3412 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3413 && !reg_overlap_mentioned_p (i0dest, newpat))
3414 || !combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX,
3415 0, 0, 0))
3417 undo_all ();
3418 return 0;
3421 /* If the following substitution will modify I0SRC, make a copy of it
3422 for the case where it is substituted for I0DEST in I1PAT later. */
3423 if (added_sets_1 && i0_feeds_i1_n)
3424 i0src_copy = copy_rtx (i0src);
3425 /* And a copy for I0DEST in I2PAT substitution. */
3426 if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3427 || (i0_feeds_i2_n)))
3428 i0src_copy2 = copy_rtx (i0src);
3430 n_occurrences = 0;
3431 subst_low_luid = DF_INSN_LUID (i0);
3432 newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3433 substed_i0 = 1;
3436 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3437 to count all the ways that I2SRC and I1SRC can be used. */
3438 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3439 && i2_is_used + added_sets_2 > 1)
3440 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3441 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3442 > 1))
3443 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3444 && (n_occurrences + added_sets_0
3445 + (added_sets_1 && i0_feeds_i1_n)
3446 + (added_sets_2 && i0_feeds_i2_n)
3447 > 1))
3448 /* Fail if we tried to make a new register. */
3449 || max_reg_num () != maxreg
3450 /* Fail if we couldn't do something and have a CLOBBER. */
3451 || GET_CODE (newpat) == CLOBBER
3452 /* Fail if this new pattern is a MULT and we didn't have one before
3453 at the outer level. */
3454 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3455 && ! have_mult))
3457 undo_all ();
3458 return 0;
3461 /* If the actions of the earlier insns must be kept
3462 in addition to substituting them into the latest one,
3463 we must make a new PARALLEL for the latest insn
3464 to hold additional the SETs. */
3466 if (added_sets_0 || added_sets_1 || added_sets_2)
3468 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3469 combine_extras++;
3471 if (GET_CODE (newpat) == PARALLEL)
3473 rtvec old = XVEC (newpat, 0);
3474 total_sets = XVECLEN (newpat, 0) + extra_sets;
3475 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3476 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3477 sizeof (old->elem[0]) * old->num_elem);
3479 else
3481 rtx old = newpat;
3482 total_sets = 1 + extra_sets;
3483 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3484 XVECEXP (newpat, 0, 0) = old;
3487 if (added_sets_0)
3488 XVECEXP (newpat, 0, --total_sets) = i0pat;
3490 if (added_sets_1)
3492 rtx t = i1pat;
3493 if (i0_feeds_i1_n)
3494 t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3496 XVECEXP (newpat, 0, --total_sets) = t;
3498 if (added_sets_2)
3500 rtx t = i2pat;
3501 if (i1_feeds_i2_n)
3502 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3503 i0_feeds_i1_n && i0dest_in_i0src);
3504 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3505 t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3507 XVECEXP (newpat, 0, --total_sets) = t;
3511 validate_replacement:
3513 /* Note which hard regs this insn has as inputs. */
3514 mark_used_regs_combine (newpat);
3516 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3517 consider splitting this pattern, we might need these clobbers. */
3518 if (i1 && GET_CODE (newpat) == PARALLEL
3519 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3521 int len = XVECLEN (newpat, 0);
3523 newpat_vec_with_clobbers = rtvec_alloc (len);
3524 for (i = 0; i < len; i++)
3525 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3528 /* We have recognized nothing yet. */
3529 insn_code_number = -1;
3531 /* See if this is a PARALLEL of two SETs where one SET's destination is
3532 a register that is unused and this isn't marked as an instruction that
3533 might trap in an EH region. In that case, we just need the other SET.
3534 We prefer this over the PARALLEL.
3536 This can occur when simplifying a divmod insn. We *must* test for this
3537 case here because the code below that splits two independent SETs doesn't
3538 handle this case correctly when it updates the register status.
3540 It's pointless doing this if we originally had two sets, one from
3541 i3, and one from i2. Combining then splitting the parallel results
3542 in the original i2 again plus an invalid insn (which we delete).
3543 The net effect is only to move instructions around, which makes
3544 debug info less accurate.
3546 If the remaining SET came from I2 its destination should not be used
3547 between I2 and I3. See PR82024. */
3549 if (!(added_sets_2 && i1 == 0)
3550 && is_parallel_of_n_reg_sets (newpat, 2)
3551 && asm_noperands (newpat) < 0)
3553 rtx set0 = XVECEXP (newpat, 0, 0);
3554 rtx set1 = XVECEXP (newpat, 0, 1);
3555 rtx oldpat = newpat;
3557 if (((REG_P (SET_DEST (set1))
3558 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3559 || (GET_CODE (SET_DEST (set1)) == SUBREG
3560 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3561 && insn_nothrow_p (i3)
3562 && !side_effects_p (SET_SRC (set1)))
3564 newpat = set0;
3565 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3568 else if (((REG_P (SET_DEST (set0))
3569 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3570 || (GET_CODE (SET_DEST (set0)) == SUBREG
3571 && find_reg_note (i3, REG_UNUSED,
3572 SUBREG_REG (SET_DEST (set0)))))
3573 && insn_nothrow_p (i3)
3574 && !side_effects_p (SET_SRC (set0)))
3576 rtx dest = SET_DEST (set1);
3577 if (GET_CODE (dest) == SUBREG)
3578 dest = SUBREG_REG (dest);
3579 if (!reg_used_between_p (dest, i2, i3))
3581 newpat = set1;
3582 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3584 if (insn_code_number >= 0)
3585 changed_i3_dest = 1;
3589 if (insn_code_number < 0)
3590 newpat = oldpat;
3593 /* Is the result of combination a valid instruction? */
3594 if (insn_code_number < 0)
3595 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3597 /* If we were combining three insns and the result is a simple SET
3598 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3599 insns. There are two ways to do this. It can be split using a
3600 machine-specific method (like when you have an addition of a large
3601 constant) or by combine in the function find_split_point. */
3603 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3604 && asm_noperands (newpat) < 0)
3606 rtx parallel, *split;
3607 rtx_insn *m_split_insn;
3609 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3610 use I2DEST as a scratch register will help. In the latter case,
3611 convert I2DEST to the mode of the source of NEWPAT if we can. */
3613 m_split_insn = combine_split_insns (newpat, i3);
3615 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3616 inputs of NEWPAT. */
3618 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3619 possible to try that as a scratch reg. This would require adding
3620 more code to make it work though. */
3622 if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3624 machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3626 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3627 (temporarily, until we are committed to this instruction
3628 combination) does not work: for example, any call to nonzero_bits
3629 on the register (from a splitter in the MD file, for example)
3630 will get the old information, which is invalid.
3632 Since nowadays we can create registers during combine just fine,
3633 we should just create a new one here, not reuse i2dest. */
3635 /* First try to split using the original register as a
3636 scratch register. */
3637 parallel = gen_rtx_PARALLEL (VOIDmode,
3638 gen_rtvec (2, newpat,
3639 gen_rtx_CLOBBER (VOIDmode,
3640 i2dest)));
3641 m_split_insn = combine_split_insns (parallel, i3);
3643 /* If that didn't work, try changing the mode of I2DEST if
3644 we can. */
3645 if (m_split_insn == 0
3646 && new_mode != GET_MODE (i2dest)
3647 && new_mode != VOIDmode
3648 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3650 machine_mode old_mode = GET_MODE (i2dest);
3651 rtx ni2dest;
3653 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3654 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3655 else
3657 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3658 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3661 parallel = (gen_rtx_PARALLEL
3662 (VOIDmode,
3663 gen_rtvec (2, newpat,
3664 gen_rtx_CLOBBER (VOIDmode,
3665 ni2dest))));
3666 m_split_insn = combine_split_insns (parallel, i3);
3668 if (m_split_insn == 0
3669 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3671 struct undo *buf;
3673 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3674 buf = undobuf.undos;
3675 undobuf.undos = buf->next;
3676 buf->next = undobuf.frees;
3677 undobuf.frees = buf;
3681 i2scratch = m_split_insn != 0;
3684 /* If recog_for_combine has discarded clobbers, try to use them
3685 again for the split. */
3686 if (m_split_insn == 0 && newpat_vec_with_clobbers)
3688 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3689 m_split_insn = combine_split_insns (parallel, i3);
3692 if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX)
3694 rtx m_split_pat = PATTERN (m_split_insn);
3695 insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes);
3696 if (insn_code_number >= 0)
3697 newpat = m_split_pat;
3699 else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX
3700 && (next_nonnote_nondebug_insn (i2) == i3
3701 || !modified_between_p (PATTERN (m_split_insn), i2, i3)))
3703 rtx i2set, i3set;
3704 rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn));
3705 newi2pat = PATTERN (m_split_insn);
3707 i3set = single_set (NEXT_INSN (m_split_insn));
3708 i2set = single_set (m_split_insn);
3710 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3712 /* If I2 or I3 has multiple SETs, we won't know how to track
3713 register status, so don't use these insns. If I2's destination
3714 is used between I2 and I3, we also can't use these insns. */
3716 if (i2_code_number >= 0 && i2set && i3set
3717 && (next_nonnote_nondebug_insn (i2) == i3
3718 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3719 insn_code_number = recog_for_combine (&newi3pat, i3,
3720 &new_i3_notes);
3721 if (insn_code_number >= 0)
3722 newpat = newi3pat;
3724 /* It is possible that both insns now set the destination of I3.
3725 If so, we must show an extra use of it. */
3727 if (insn_code_number >= 0)
3729 rtx new_i3_dest = SET_DEST (i3set);
3730 rtx new_i2_dest = SET_DEST (i2set);
3732 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3733 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3734 || GET_CODE (new_i3_dest) == SUBREG)
3735 new_i3_dest = XEXP (new_i3_dest, 0);
3737 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3738 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3739 || GET_CODE (new_i2_dest) == SUBREG)
3740 new_i2_dest = XEXP (new_i2_dest, 0);
3742 if (REG_P (new_i3_dest)
3743 && REG_P (new_i2_dest)
3744 && REGNO (new_i3_dest) == REGNO (new_i2_dest)
3745 && REGNO (new_i2_dest) < reg_n_sets_max)
3746 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3750 /* If we can split it and use I2DEST, go ahead and see if that
3751 helps things be recognized. Verify that none of the registers
3752 are set between I2 and I3. */
3753 if (insn_code_number < 0
3754 && (split = find_split_point (&newpat, i3, false)) != 0
3755 && (!HAVE_cc0 || REG_P (i2dest))
3756 /* We need I2DEST in the proper mode. If it is a hard register
3757 or the only use of a pseudo, we can change its mode.
3758 Make sure we don't change a hard register to have a mode that
3759 isn't valid for it, or change the number of registers. */
3760 && (GET_MODE (*split) == GET_MODE (i2dest)
3761 || GET_MODE (*split) == VOIDmode
3762 || can_change_dest_mode (i2dest, added_sets_2,
3763 GET_MODE (*split)))
3764 && (next_nonnote_nondebug_insn (i2) == i3
3765 || !modified_between_p (*split, i2, i3))
3766 /* We can't overwrite I2DEST if its value is still used by
3767 NEWPAT. */
3768 && ! reg_referenced_p (i2dest, newpat))
3770 rtx newdest = i2dest;
3771 enum rtx_code split_code = GET_CODE (*split);
3772 machine_mode split_mode = GET_MODE (*split);
3773 bool subst_done = false;
3774 newi2pat = NULL_RTX;
3776 i2scratch = true;
3778 /* *SPLIT may be part of I2SRC, so make sure we have the
3779 original expression around for later debug processing.
3780 We should not need I2SRC any more in other cases. */
3781 if (MAY_HAVE_DEBUG_BIND_INSNS)
3782 i2src = copy_rtx (i2src);
3783 else
3784 i2src = NULL;
3786 /* Get NEWDEST as a register in the proper mode. We have already
3787 validated that we can do this. */
3788 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3790 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3791 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3792 else
3794 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3795 newdest = regno_reg_rtx[REGNO (i2dest)];
3799 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3800 an ASHIFT. This can occur if it was inside a PLUS and hence
3801 appeared to be a memory address. This is a kludge. */
3802 if (split_code == MULT
3803 && CONST_INT_P (XEXP (*split, 1))
3804 && INTVAL (XEXP (*split, 1)) > 0
3805 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3807 rtx i_rtx = gen_int_shift_amount (split_mode, i);
3808 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3809 XEXP (*split, 0), i_rtx));
3810 /* Update split_code because we may not have a multiply
3811 anymore. */
3812 split_code = GET_CODE (*split);
3815 /* Similarly for (plus (mult FOO (const_int pow2))). */
3816 if (split_code == PLUS
3817 && GET_CODE (XEXP (*split, 0)) == MULT
3818 && CONST_INT_P (XEXP (XEXP (*split, 0), 1))
3819 && INTVAL (XEXP (XEXP (*split, 0), 1)) > 0
3820 && (i = exact_log2 (UINTVAL (XEXP (XEXP (*split, 0), 1)))) >= 0)
3822 rtx nsplit = XEXP (*split, 0);
3823 rtx i_rtx = gen_int_shift_amount (GET_MODE (nsplit), i);
3824 SUBST (XEXP (*split, 0), gen_rtx_ASHIFT (GET_MODE (nsplit),
3825 XEXP (nsplit, 0),
3826 i_rtx));
3827 /* Update split_code because we may not have a multiply
3828 anymore. */
3829 split_code = GET_CODE (*split);
3832 #ifdef INSN_SCHEDULING
3833 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3834 be written as a ZERO_EXTEND. */
3835 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3837 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3838 what it really is. */
3839 if (load_extend_op (GET_MODE (SUBREG_REG (*split)))
3840 == SIGN_EXTEND)
3841 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3842 SUBREG_REG (*split)));
3843 else
3844 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3845 SUBREG_REG (*split)));
3847 #endif
3849 /* Attempt to split binary operators using arithmetic identities. */
3850 if (BINARY_P (SET_SRC (newpat))
3851 && split_mode == GET_MODE (SET_SRC (newpat))
3852 && ! side_effects_p (SET_SRC (newpat)))
3854 rtx setsrc = SET_SRC (newpat);
3855 machine_mode mode = GET_MODE (setsrc);
3856 enum rtx_code code = GET_CODE (setsrc);
3857 rtx src_op0 = XEXP (setsrc, 0);
3858 rtx src_op1 = XEXP (setsrc, 1);
3860 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3861 if (rtx_equal_p (src_op0, src_op1))
3863 newi2pat = gen_rtx_SET (newdest, src_op0);
3864 SUBST (XEXP (setsrc, 0), newdest);
3865 SUBST (XEXP (setsrc, 1), newdest);
3866 subst_done = true;
3868 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3869 else if ((code == PLUS || code == MULT)
3870 && GET_CODE (src_op0) == code
3871 && GET_CODE (XEXP (src_op0, 0)) == code
3872 && (INTEGRAL_MODE_P (mode)
3873 || (FLOAT_MODE_P (mode)
3874 && flag_unsafe_math_optimizations)))
3876 rtx p = XEXP (XEXP (src_op0, 0), 0);
3877 rtx q = XEXP (XEXP (src_op0, 0), 1);
3878 rtx r = XEXP (src_op0, 1);
3879 rtx s = src_op1;
3881 /* Split both "((X op Y) op X) op Y" and
3882 "((X op Y) op Y) op X" as "T op T" where T is
3883 "X op Y". */
3884 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3885 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3887 newi2pat = gen_rtx_SET (newdest, XEXP (src_op0, 0));
3888 SUBST (XEXP (setsrc, 0), newdest);
3889 SUBST (XEXP (setsrc, 1), newdest);
3890 subst_done = true;
3892 /* Split "((X op X) op Y) op Y)" as "T op T" where
3893 T is "X op Y". */
3894 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3896 rtx tmp = simplify_gen_binary (code, mode, p, r);
3897 newi2pat = gen_rtx_SET (newdest, tmp);
3898 SUBST (XEXP (setsrc, 0), newdest);
3899 SUBST (XEXP (setsrc, 1), newdest);
3900 subst_done = true;
3905 if (!subst_done)
3907 newi2pat = gen_rtx_SET (newdest, *split);
3908 SUBST (*split, newdest);
3911 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3913 /* recog_for_combine might have added CLOBBERs to newi2pat.
3914 Make sure NEWPAT does not depend on the clobbered regs. */
3915 if (GET_CODE (newi2pat) == PARALLEL)
3916 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3917 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3919 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3920 if (reg_overlap_mentioned_p (reg, newpat))
3922 undo_all ();
3923 return 0;
3927 /* If the split point was a MULT and we didn't have one before,
3928 don't use one now. */
3929 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3930 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3934 /* Check for a case where we loaded from memory in a narrow mode and
3935 then sign extended it, but we need both registers. In that case,
3936 we have a PARALLEL with both loads from the same memory location.
3937 We can split this into a load from memory followed by a register-register
3938 copy. This saves at least one insn, more if register allocation can
3939 eliminate the copy.
3941 We cannot do this if the destination of the first assignment is a
3942 condition code register or cc0. We eliminate this case by making sure
3943 the SET_DEST and SET_SRC have the same mode.
3945 We cannot do this if the destination of the second assignment is
3946 a register that we have already assumed is zero-extended. Similarly
3947 for a SUBREG of such a register. */
3949 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3950 && GET_CODE (newpat) == PARALLEL
3951 && XVECLEN (newpat, 0) == 2
3952 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3953 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3954 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3955 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3956 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3957 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3958 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3959 && !modified_between_p (SET_SRC (XVECEXP (newpat, 0, 1)), i2, i3)
3960 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3961 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3962 && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)),
3963 (REG_P (temp_expr)
3964 && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3965 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3966 BITS_PER_WORD)
3967 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3968 HOST_BITS_PER_INT)
3969 && (reg_stat[REGNO (temp_expr)].nonzero_bits
3970 != GET_MODE_MASK (word_mode))))
3971 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3972 && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3973 (REG_P (temp_expr)
3974 && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3975 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3976 BITS_PER_WORD)
3977 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3978 HOST_BITS_PER_INT)
3979 && (reg_stat[REGNO (temp_expr)].nonzero_bits
3980 != GET_MODE_MASK (word_mode)))))
3981 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3982 SET_SRC (XVECEXP (newpat, 0, 1)))
3983 && ! find_reg_note (i3, REG_UNUSED,
3984 SET_DEST (XVECEXP (newpat, 0, 0))))
3986 rtx ni2dest;
3988 newi2pat = XVECEXP (newpat, 0, 0);
3989 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3990 newpat = XVECEXP (newpat, 0, 1);
3991 SUBST (SET_SRC (newpat),
3992 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3993 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3995 if (i2_code_number >= 0)
3996 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3998 if (insn_code_number >= 0)
3999 swap_i2i3 = 1;
4002 /* Similarly, check for a case where we have a PARALLEL of two independent
4003 SETs but we started with three insns. In this case, we can do the sets
4004 as two separate insns. This case occurs when some SET allows two
4005 other insns to combine, but the destination of that SET is still live.
4007 Also do this if we started with two insns and (at least) one of the
4008 resulting sets is a noop; this noop will be deleted later. */
4010 else if (insn_code_number < 0 && asm_noperands (newpat) < 0
4011 && GET_CODE (newpat) == PARALLEL
4012 && XVECLEN (newpat, 0) == 2
4013 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
4014 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
4015 && (i1 || set_noop_p (XVECEXP (newpat, 0, 0))
4016 || set_noop_p (XVECEXP (newpat, 0, 1)))
4017 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
4018 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
4019 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
4020 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
4021 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
4022 XVECEXP (newpat, 0, 0))
4023 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
4024 XVECEXP (newpat, 0, 1))
4025 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
4026 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
4028 rtx set0 = XVECEXP (newpat, 0, 0);
4029 rtx set1 = XVECEXP (newpat, 0, 1);
4031 /* Normally, it doesn't matter which of the two is done first,
4032 but the one that references cc0 can't be the second, and
4033 one which uses any regs/memory set in between i2 and i3 can't
4034 be first. The PARALLEL might also have been pre-existing in i3,
4035 so we need to make sure that we won't wrongly hoist a SET to i2
4036 that would conflict with a death note present in there. */
4037 if (!modified_between_p (SET_SRC (set1), i2, i3)
4038 && !(REG_P (SET_DEST (set1))
4039 && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
4040 && !(GET_CODE (SET_DEST (set1)) == SUBREG
4041 && find_reg_note (i2, REG_DEAD,
4042 SUBREG_REG (SET_DEST (set1))))
4043 && (!HAVE_cc0 || !reg_referenced_p (cc0_rtx, set0))
4044 /* If I3 is a jump, ensure that set0 is a jump so that
4045 we do not create invalid RTL. */
4046 && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx)
4049 newi2pat = set1;
4050 newpat = set0;
4052 else if (!modified_between_p (SET_SRC (set0), i2, i3)
4053 && !(REG_P (SET_DEST (set0))
4054 && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
4055 && !(GET_CODE (SET_DEST (set0)) == SUBREG
4056 && find_reg_note (i2, REG_DEAD,
4057 SUBREG_REG (SET_DEST (set0))))
4058 && (!HAVE_cc0 || !reg_referenced_p (cc0_rtx, set1))
4059 /* If I3 is a jump, ensure that set1 is a jump so that
4060 we do not create invalid RTL. */
4061 && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx)
4064 newi2pat = set0;
4065 newpat = set1;
4067 else
4069 undo_all ();
4070 return 0;
4073 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
4075 if (i2_code_number >= 0)
4077 /* recog_for_combine might have added CLOBBERs to newi2pat.
4078 Make sure NEWPAT does not depend on the clobbered regs. */
4079 if (GET_CODE (newi2pat) == PARALLEL)
4081 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
4082 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
4084 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
4085 if (reg_overlap_mentioned_p (reg, newpat))
4087 undo_all ();
4088 return 0;
4093 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
4097 /* If it still isn't recognized, fail and change things back the way they
4098 were. */
4099 if ((insn_code_number < 0
4100 /* Is the result a reasonable ASM_OPERANDS? */
4101 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
4103 undo_all ();
4104 return 0;
4107 /* If we had to change another insn, make sure it is valid also. */
4108 if (undobuf.other_insn)
4110 CLEAR_HARD_REG_SET (newpat_used_regs);
4112 other_pat = PATTERN (undobuf.other_insn);
4113 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
4114 &new_other_notes);
4116 if (other_code_number < 0 && ! check_asm_operands (other_pat))
4118 undo_all ();
4119 return 0;
4123 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4124 they are adjacent to each other or not. */
4125 if (HAVE_cc0)
4127 rtx_insn *p = prev_nonnote_insn (i3);
4128 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
4129 && sets_cc0_p (newi2pat))
4131 undo_all ();
4132 return 0;
4136 /* Only allow this combination if insn_cost reports that the
4137 replacement instructions are cheaper than the originals. */
4138 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
4140 undo_all ();
4141 return 0;
4144 if (MAY_HAVE_DEBUG_BIND_INSNS)
4146 struct undo *undo;
4148 for (undo = undobuf.undos; undo; undo = undo->next)
4149 if (undo->kind == UNDO_MODE)
4151 rtx reg = *undo->where.r;
4152 machine_mode new_mode = GET_MODE (reg);
4153 machine_mode old_mode = undo->old_contents.m;
4155 /* Temporarily revert mode back. */
4156 adjust_reg_mode (reg, old_mode);
4158 if (reg == i2dest && i2scratch)
4160 /* If we used i2dest as a scratch register with a
4161 different mode, substitute it for the original
4162 i2src while its original mode is temporarily
4163 restored, and then clear i2scratch so that we don't
4164 do it again later. */
4165 propagate_for_debug (i2, last_combined_insn, reg, i2src,
4166 this_basic_block);
4167 i2scratch = false;
4168 /* Put back the new mode. */
4169 adjust_reg_mode (reg, new_mode);
4171 else
4173 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
4174 rtx_insn *first, *last;
4176 if (reg == i2dest)
4178 first = i2;
4179 last = last_combined_insn;
4181 else
4183 first = i3;
4184 last = undobuf.other_insn;
4185 gcc_assert (last);
4186 if (DF_INSN_LUID (last)
4187 < DF_INSN_LUID (last_combined_insn))
4188 last = last_combined_insn;
4191 /* We're dealing with a reg that changed mode but not
4192 meaning, so we want to turn it into a subreg for
4193 the new mode. However, because of REG sharing and
4194 because its mode had already changed, we have to do
4195 it in two steps. First, replace any debug uses of
4196 reg, with its original mode temporarily restored,
4197 with this copy we have created; then, replace the
4198 copy with the SUBREG of the original shared reg,
4199 once again changed to the new mode. */
4200 propagate_for_debug (first, last, reg, tempreg,
4201 this_basic_block);
4202 adjust_reg_mode (reg, new_mode);
4203 propagate_for_debug (first, last, tempreg,
4204 lowpart_subreg (old_mode, reg, new_mode),
4205 this_basic_block);
4210 /* If we will be able to accept this, we have made a
4211 change to the destination of I3. This requires us to
4212 do a few adjustments. */
4214 if (changed_i3_dest)
4216 PATTERN (i3) = newpat;
4217 adjust_for_new_dest (i3);
4220 /* We now know that we can do this combination. Merge the insns and
4221 update the status of registers and LOG_LINKS. */
4223 if (undobuf.other_insn)
4225 rtx note, next;
4227 PATTERN (undobuf.other_insn) = other_pat;
4229 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4230 ensure that they are still valid. Then add any non-duplicate
4231 notes added by recog_for_combine. */
4232 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
4234 next = XEXP (note, 1);
4236 if ((REG_NOTE_KIND (note) == REG_DEAD
4237 && !reg_referenced_p (XEXP (note, 0),
4238 PATTERN (undobuf.other_insn)))
4239 ||(REG_NOTE_KIND (note) == REG_UNUSED
4240 && !reg_set_p (XEXP (note, 0),
4241 PATTERN (undobuf.other_insn)))
4242 /* Simply drop equal note since it may be no longer valid
4243 for other_insn. It may be possible to record that CC
4244 register is changed and only discard those notes, but
4245 in practice it's unnecessary complication and doesn't
4246 give any meaningful improvement.
4248 See PR78559. */
4249 || REG_NOTE_KIND (note) == REG_EQUAL
4250 || REG_NOTE_KIND (note) == REG_EQUIV)
4251 remove_note (undobuf.other_insn, note);
4254 distribute_notes (new_other_notes, undobuf.other_insn,
4255 undobuf.other_insn, NULL, NULL_RTX, NULL_RTX,
4256 NULL_RTX);
4259 if (swap_i2i3)
4261 rtx_insn *insn;
4262 struct insn_link *link;
4263 rtx ni2dest;
4265 /* I3 now uses what used to be its destination and which is now
4266 I2's destination. This requires us to do a few adjustments. */
4267 PATTERN (i3) = newpat;
4268 adjust_for_new_dest (i3);
4270 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4271 so we still will.
4273 However, some later insn might be using I2's dest and have
4274 a LOG_LINK pointing at I3. We must remove this link.
4275 The simplest way to remove the link is to point it at I1,
4276 which we know will be a NOTE. */
4278 /* newi2pat is usually a SET here; however, recog_for_combine might
4279 have added some clobbers. */
4280 if (GET_CODE (newi2pat) == PARALLEL)
4281 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
4282 else
4283 ni2dest = SET_DEST (newi2pat);
4285 for (insn = NEXT_INSN (i3);
4286 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4287 || insn != BB_HEAD (this_basic_block->next_bb));
4288 insn = NEXT_INSN (insn))
4290 if (NONDEBUG_INSN_P (insn)
4291 && reg_referenced_p (ni2dest, PATTERN (insn)))
4293 FOR_EACH_LOG_LINK (link, insn)
4294 if (link->insn == i3)
4295 link->insn = i1;
4297 break;
4303 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4304 struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4305 rtx midnotes = 0;
4306 int from_luid;
4307 /* Compute which registers we expect to eliminate. newi2pat may be setting
4308 either i3dest or i2dest, so we must check it. */
4309 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4310 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4311 || !i2dest_killed
4312 ? 0 : i2dest);
4313 /* For i1, we need to compute both local elimination and global
4314 elimination information with respect to newi2pat because i1dest
4315 may be the same as i3dest, in which case newi2pat may be setting
4316 i1dest. Global information is used when distributing REG_DEAD
4317 note for i2 and i3, in which case it does matter if newi2pat sets
4318 i1dest or not.
4320 Local information is used when distributing REG_DEAD note for i1,
4321 in which case it doesn't matter if newi2pat sets i1dest or not.
4322 See PR62151, if we have four insns combination:
4323 i0: r0 <- i0src
4324 i1: r1 <- i1src (using r0)
4325 REG_DEAD (r0)
4326 i2: r0 <- i2src (using r1)
4327 i3: r3 <- i3src (using r0)
4328 ix: using r0
4329 From i1's point of view, r0 is eliminated, no matter if it is set
4330 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4331 should be discarded.
4333 Note local information only affects cases in forms like "I1->I2->I3",
4334 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4335 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4336 i0dest anyway. */
4337 rtx local_elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4338 || !i1dest_killed
4339 ? 0 : i1dest);
4340 rtx elim_i1 = (local_elim_i1 == 0
4341 || (newi2pat && reg_set_p (i1dest, newi2pat))
4342 ? 0 : i1dest);
4343 /* Same case as i1. */
4344 rtx local_elim_i0 = (i0 == 0 || i0dest_in_i0src || !i0dest_killed
4345 ? 0 : i0dest);
4346 rtx elim_i0 = (local_elim_i0 == 0
4347 || (newi2pat && reg_set_p (i0dest, newi2pat))
4348 ? 0 : i0dest);
4350 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4351 clear them. */
4352 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4353 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4354 if (i1)
4355 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4356 if (i0)
4357 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4359 /* Ensure that we do not have something that should not be shared but
4360 occurs multiple times in the new insns. Check this by first
4361 resetting all the `used' flags and then copying anything is shared. */
4363 reset_used_flags (i3notes);
4364 reset_used_flags (i2notes);
4365 reset_used_flags (i1notes);
4366 reset_used_flags (i0notes);
4367 reset_used_flags (newpat);
4368 reset_used_flags (newi2pat);
4369 if (undobuf.other_insn)
4370 reset_used_flags (PATTERN (undobuf.other_insn));
4372 i3notes = copy_rtx_if_shared (i3notes);
4373 i2notes = copy_rtx_if_shared (i2notes);
4374 i1notes = copy_rtx_if_shared (i1notes);
4375 i0notes = copy_rtx_if_shared (i0notes);
4376 newpat = copy_rtx_if_shared (newpat);
4377 newi2pat = copy_rtx_if_shared (newi2pat);
4378 if (undobuf.other_insn)
4379 reset_used_flags (PATTERN (undobuf.other_insn));
4381 INSN_CODE (i3) = insn_code_number;
4382 PATTERN (i3) = newpat;
4384 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4386 for (rtx link = CALL_INSN_FUNCTION_USAGE (i3); link;
4387 link = XEXP (link, 1))
4389 if (substed_i2)
4391 /* I2SRC must still be meaningful at this point. Some
4392 splitting operations can invalidate I2SRC, but those
4393 operations do not apply to calls. */
4394 gcc_assert (i2src);
4395 XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4396 i2dest, i2src);
4398 if (substed_i1)
4399 XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4400 i1dest, i1src);
4401 if (substed_i0)
4402 XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4403 i0dest, i0src);
4407 if (undobuf.other_insn)
4408 INSN_CODE (undobuf.other_insn) = other_code_number;
4410 /* We had one special case above where I2 had more than one set and
4411 we replaced a destination of one of those sets with the destination
4412 of I3. In that case, we have to update LOG_LINKS of insns later
4413 in this basic block. Note that this (expensive) case is rare.
4415 Also, in this case, we must pretend that all REG_NOTEs for I2
4416 actually came from I3, so that REG_UNUSED notes from I2 will be
4417 properly handled. */
4419 if (i3_subst_into_i2)
4421 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4422 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4423 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4424 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4425 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4426 && ! find_reg_note (i2, REG_UNUSED,
4427 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4428 for (temp_insn = NEXT_INSN (i2);
4429 temp_insn
4430 && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4431 || BB_HEAD (this_basic_block) != temp_insn);
4432 temp_insn = NEXT_INSN (temp_insn))
4433 if (temp_insn != i3 && NONDEBUG_INSN_P (temp_insn))
4434 FOR_EACH_LOG_LINK (link, temp_insn)
4435 if (link->insn == i2)
4436 link->insn = i3;
4438 if (i3notes)
4440 rtx link = i3notes;
4441 while (XEXP (link, 1))
4442 link = XEXP (link, 1);
4443 XEXP (link, 1) = i2notes;
4445 else
4446 i3notes = i2notes;
4447 i2notes = 0;
4450 LOG_LINKS (i3) = NULL;
4451 REG_NOTES (i3) = 0;
4452 LOG_LINKS (i2) = NULL;
4453 REG_NOTES (i2) = 0;
4455 if (newi2pat)
4457 if (MAY_HAVE_DEBUG_BIND_INSNS && i2scratch)
4458 propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4459 this_basic_block);
4460 INSN_CODE (i2) = i2_code_number;
4461 PATTERN (i2) = newi2pat;
4463 else
4465 if (MAY_HAVE_DEBUG_BIND_INSNS && i2src)
4466 propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4467 this_basic_block);
4468 SET_INSN_DELETED (i2);
4471 if (i1)
4473 LOG_LINKS (i1) = NULL;
4474 REG_NOTES (i1) = 0;
4475 if (MAY_HAVE_DEBUG_BIND_INSNS)
4476 propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4477 this_basic_block);
4478 SET_INSN_DELETED (i1);
4481 if (i0)
4483 LOG_LINKS (i0) = NULL;
4484 REG_NOTES (i0) = 0;
4485 if (MAY_HAVE_DEBUG_BIND_INSNS)
4486 propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4487 this_basic_block);
4488 SET_INSN_DELETED (i0);
4491 /* Get death notes for everything that is now used in either I3 or
4492 I2 and used to die in a previous insn. If we built two new
4493 patterns, move from I1 to I2 then I2 to I3 so that we get the
4494 proper movement on registers that I2 modifies. */
4496 if (i0)
4497 from_luid = DF_INSN_LUID (i0);
4498 else if (i1)
4499 from_luid = DF_INSN_LUID (i1);
4500 else
4501 from_luid = DF_INSN_LUID (i2);
4502 if (newi2pat)
4503 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4504 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4506 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4507 if (i3notes)
4508 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL,
4509 elim_i2, elim_i1, elim_i0);
4510 if (i2notes)
4511 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL,
4512 elim_i2, elim_i1, elim_i0);
4513 if (i1notes)
4514 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL,
4515 elim_i2, local_elim_i1, local_elim_i0);
4516 if (i0notes)
4517 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL,
4518 elim_i2, elim_i1, local_elim_i0);
4519 if (midnotes)
4520 distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL,
4521 elim_i2, elim_i1, elim_i0);
4523 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4524 know these are REG_UNUSED and want them to go to the desired insn,
4525 so we always pass it as i3. */
4527 if (newi2pat && new_i2_notes)
4528 distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX,
4529 NULL_RTX);
4531 if (new_i3_notes)
4532 distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX,
4533 NULL_RTX);
4535 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4536 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4537 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4538 in that case, it might delete I2. Similarly for I2 and I1.
4539 Show an additional death due to the REG_DEAD note we make here. If
4540 we discard it in distribute_notes, we will decrement it again. */
4542 if (i3dest_killed)
4544 rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4545 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4546 distribute_notes (new_note, NULL, i2, NULL, elim_i2,
4547 elim_i1, elim_i0);
4548 else
4549 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4550 elim_i2, elim_i1, elim_i0);
4553 if (i2dest_in_i2src)
4555 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4556 if (newi2pat && reg_set_p (i2dest, newi2pat))
4557 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4558 NULL_RTX, NULL_RTX);
4559 else
4560 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4561 NULL_RTX, NULL_RTX, NULL_RTX);
4564 if (i1dest_in_i1src)
4566 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4567 if (newi2pat && reg_set_p (i1dest, newi2pat))
4568 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4569 NULL_RTX, NULL_RTX);
4570 else
4571 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4572 NULL_RTX, NULL_RTX, NULL_RTX);
4575 if (i0dest_in_i0src)
4577 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4578 if (newi2pat && reg_set_p (i0dest, newi2pat))
4579 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4580 NULL_RTX, NULL_RTX);
4581 else
4582 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4583 NULL_RTX, NULL_RTX, NULL_RTX);
4586 distribute_links (i3links);
4587 distribute_links (i2links);
4588 distribute_links (i1links);
4589 distribute_links (i0links);
4591 if (REG_P (i2dest))
4593 struct insn_link *link;
4594 rtx_insn *i2_insn = 0;
4595 rtx i2_val = 0, set;
4597 /* The insn that used to set this register doesn't exist, and
4598 this life of the register may not exist either. See if one of
4599 I3's links points to an insn that sets I2DEST. If it does,
4600 that is now the last known value for I2DEST. If we don't update
4601 this and I2 set the register to a value that depended on its old
4602 contents, we will get confused. If this insn is used, thing
4603 will be set correctly in combine_instructions. */
4604 FOR_EACH_LOG_LINK (link, i3)
4605 if ((set = single_set (link->insn)) != 0
4606 && rtx_equal_p (i2dest, SET_DEST (set)))
4607 i2_insn = link->insn, i2_val = SET_SRC (set);
4609 record_value_for_reg (i2dest, i2_insn, i2_val);
4611 /* If the reg formerly set in I2 died only once and that was in I3,
4612 zero its use count so it won't make `reload' do any work. */
4613 if (! added_sets_2
4614 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4615 && ! i2dest_in_i2src
4616 && REGNO (i2dest) < reg_n_sets_max)
4617 INC_REG_N_SETS (REGNO (i2dest), -1);
4620 if (i1 && REG_P (i1dest))
4622 struct insn_link *link;
4623 rtx_insn *i1_insn = 0;
4624 rtx i1_val = 0, set;
4626 FOR_EACH_LOG_LINK (link, i3)
4627 if ((set = single_set (link->insn)) != 0
4628 && rtx_equal_p (i1dest, SET_DEST (set)))
4629 i1_insn = link->insn, i1_val = SET_SRC (set);
4631 record_value_for_reg (i1dest, i1_insn, i1_val);
4633 if (! added_sets_1
4634 && ! i1dest_in_i1src
4635 && REGNO (i1dest) < reg_n_sets_max)
4636 INC_REG_N_SETS (REGNO (i1dest), -1);
4639 if (i0 && REG_P (i0dest))
4641 struct insn_link *link;
4642 rtx_insn *i0_insn = 0;
4643 rtx i0_val = 0, set;
4645 FOR_EACH_LOG_LINK (link, i3)
4646 if ((set = single_set (link->insn)) != 0
4647 && rtx_equal_p (i0dest, SET_DEST (set)))
4648 i0_insn = link->insn, i0_val = SET_SRC (set);
4650 record_value_for_reg (i0dest, i0_insn, i0_val);
4652 if (! added_sets_0
4653 && ! i0dest_in_i0src
4654 && REGNO (i0dest) < reg_n_sets_max)
4655 INC_REG_N_SETS (REGNO (i0dest), -1);
4658 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4659 been made to this insn. The order is important, because newi2pat
4660 can affect nonzero_bits of newpat. */
4661 if (newi2pat)
4662 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4663 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4666 if (undobuf.other_insn != NULL_RTX)
4668 if (dump_file)
4670 fprintf (dump_file, "modifying other_insn ");
4671 dump_insn_slim (dump_file, undobuf.other_insn);
4673 df_insn_rescan (undobuf.other_insn);
4676 if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4678 if (dump_file)
4680 fprintf (dump_file, "modifying insn i0 ");
4681 dump_insn_slim (dump_file, i0);
4683 df_insn_rescan (i0);
4686 if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4688 if (dump_file)
4690 fprintf (dump_file, "modifying insn i1 ");
4691 dump_insn_slim (dump_file, i1);
4693 df_insn_rescan (i1);
4696 if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4698 if (dump_file)
4700 fprintf (dump_file, "modifying insn i2 ");
4701 dump_insn_slim (dump_file, i2);
4703 df_insn_rescan (i2);
4706 if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4708 if (dump_file)
4710 fprintf (dump_file, "modifying insn i3 ");
4711 dump_insn_slim (dump_file, i3);
4713 df_insn_rescan (i3);
4716 /* Set new_direct_jump_p if a new return or simple jump instruction
4717 has been created. Adjust the CFG accordingly. */
4718 if (returnjump_p (i3) || any_uncondjump_p (i3))
4720 *new_direct_jump_p = 1;
4721 mark_jump_label (PATTERN (i3), i3, 0);
4722 update_cfg_for_uncondjump (i3);
4725 if (undobuf.other_insn != NULL_RTX
4726 && (returnjump_p (undobuf.other_insn)
4727 || any_uncondjump_p (undobuf.other_insn)))
4729 *new_direct_jump_p = 1;
4730 update_cfg_for_uncondjump (undobuf.other_insn);
4733 if (GET_CODE (PATTERN (i3)) == TRAP_IF
4734 && XEXP (PATTERN (i3), 0) == const1_rtx)
4736 basic_block bb = BLOCK_FOR_INSN (i3);
4737 gcc_assert (bb);
4738 remove_edge (split_block (bb, i3));
4739 emit_barrier_after_bb (bb);
4740 *new_direct_jump_p = 1;
4743 if (undobuf.other_insn
4744 && GET_CODE (PATTERN (undobuf.other_insn)) == TRAP_IF
4745 && XEXP (PATTERN (undobuf.other_insn), 0) == const1_rtx)
4747 basic_block bb = BLOCK_FOR_INSN (undobuf.other_insn);
4748 gcc_assert (bb);
4749 remove_edge (split_block (bb, undobuf.other_insn));
4750 emit_barrier_after_bb (bb);
4751 *new_direct_jump_p = 1;
4754 /* A noop might also need cleaning up of CFG, if it comes from the
4755 simplification of a jump. */
4756 if (JUMP_P (i3)
4757 && GET_CODE (newpat) == SET
4758 && SET_SRC (newpat) == pc_rtx
4759 && SET_DEST (newpat) == pc_rtx)
4761 *new_direct_jump_p = 1;
4762 update_cfg_for_uncondjump (i3);
4765 if (undobuf.other_insn != NULL_RTX
4766 && JUMP_P (undobuf.other_insn)
4767 && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4768 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4769 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4771 *new_direct_jump_p = 1;
4772 update_cfg_for_uncondjump (undobuf.other_insn);
4775 combine_successes++;
4776 undo_commit ();
4778 rtx_insn *ret = newi2pat ? i2 : i3;
4779 if (added_links_insn && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (ret))
4780 ret = added_links_insn;
4781 if (added_notes_insn && DF_INSN_LUID (added_notes_insn) < DF_INSN_LUID (ret))
4782 ret = added_notes_insn;
4784 return ret;
4787 /* Get a marker for undoing to the current state. */
4789 static void *
4790 get_undo_marker (void)
4792 return undobuf.undos;
4795 /* Undo the modifications up to the marker. */
4797 static void
4798 undo_to_marker (void *marker)
4800 struct undo *undo, *next;
4802 for (undo = undobuf.undos; undo != marker; undo = next)
4804 gcc_assert (undo);
4806 next = undo->next;
4807 switch (undo->kind)
4809 case UNDO_RTX:
4810 *undo->where.r = undo->old_contents.r;
4811 break;
4812 case UNDO_INT:
4813 *undo->where.i = undo->old_contents.i;
4814 break;
4815 case UNDO_MODE:
4816 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4817 break;
4818 case UNDO_LINKS:
4819 *undo->where.l = undo->old_contents.l;
4820 break;
4821 default:
4822 gcc_unreachable ();
4825 undo->next = undobuf.frees;
4826 undobuf.frees = undo;
4829 undobuf.undos = (struct undo *) marker;
4832 /* Undo all the modifications recorded in undobuf. */
4834 static void
4835 undo_all (void)
4837 undo_to_marker (0);
4840 /* We've committed to accepting the changes we made. Move all
4841 of the undos to the free list. */
4843 static void
4844 undo_commit (void)
4846 struct undo *undo, *next;
4848 for (undo = undobuf.undos; undo; undo = next)
4850 next = undo->next;
4851 undo->next = undobuf.frees;
4852 undobuf.frees = undo;
4854 undobuf.undos = 0;
4857 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4858 where we have an arithmetic expression and return that point. LOC will
4859 be inside INSN.
4861 try_combine will call this function to see if an insn can be split into
4862 two insns. */
4864 static rtx *
4865 find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
4867 rtx x = *loc;
4868 enum rtx_code code = GET_CODE (x);
4869 rtx *split;
4870 unsigned HOST_WIDE_INT len = 0;
4871 HOST_WIDE_INT pos = 0;
4872 int unsignedp = 0;
4873 rtx inner = NULL_RTX;
4874 scalar_int_mode mode, inner_mode;
4876 /* First special-case some codes. */
4877 switch (code)
4879 case SUBREG:
4880 #ifdef INSN_SCHEDULING
4881 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4882 point. */
4883 if (MEM_P (SUBREG_REG (x)))
4884 return loc;
4885 #endif
4886 return find_split_point (&SUBREG_REG (x), insn, false);
4888 case MEM:
4889 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4890 using LO_SUM and HIGH. */
4891 if (HAVE_lo_sum && (GET_CODE (XEXP (x, 0)) == CONST
4892 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF))
4894 machine_mode address_mode = get_address_mode (x);
4896 SUBST (XEXP (x, 0),
4897 gen_rtx_LO_SUM (address_mode,
4898 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4899 XEXP (x, 0)));
4900 return &XEXP (XEXP (x, 0), 0);
4903 /* If we have a PLUS whose second operand is a constant and the
4904 address is not valid, perhaps will can split it up using
4905 the machine-specific way to split large constants. We use
4906 the first pseudo-reg (one of the virtual regs) as a placeholder;
4907 it will not remain in the result. */
4908 if (GET_CODE (XEXP (x, 0)) == PLUS
4909 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4910 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4911 MEM_ADDR_SPACE (x)))
4913 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4914 rtx_insn *seq = combine_split_insns (gen_rtx_SET (reg, XEXP (x, 0)),
4915 subst_insn);
4917 /* This should have produced two insns, each of which sets our
4918 placeholder. If the source of the second is a valid address,
4919 we can make put both sources together and make a split point
4920 in the middle. */
4922 if (seq
4923 && NEXT_INSN (seq) != NULL_RTX
4924 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4925 && NONJUMP_INSN_P (seq)
4926 && GET_CODE (PATTERN (seq)) == SET
4927 && SET_DEST (PATTERN (seq)) == reg
4928 && ! reg_mentioned_p (reg,
4929 SET_SRC (PATTERN (seq)))
4930 && NONJUMP_INSN_P (NEXT_INSN (seq))
4931 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4932 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4933 && memory_address_addr_space_p
4934 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4935 MEM_ADDR_SPACE (x)))
4937 rtx src1 = SET_SRC (PATTERN (seq));
4938 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4940 /* Replace the placeholder in SRC2 with SRC1. If we can
4941 find where in SRC2 it was placed, that can become our
4942 split point and we can replace this address with SRC2.
4943 Just try two obvious places. */
4945 src2 = replace_rtx (src2, reg, src1);
4946 split = 0;
4947 if (XEXP (src2, 0) == src1)
4948 split = &XEXP (src2, 0);
4949 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4950 && XEXP (XEXP (src2, 0), 0) == src1)
4951 split = &XEXP (XEXP (src2, 0), 0);
4953 if (split)
4955 SUBST (XEXP (x, 0), src2);
4956 return split;
4960 /* If that didn't work, perhaps the first operand is complex and
4961 needs to be computed separately, so make a split point there.
4962 This will occur on machines that just support REG + CONST
4963 and have a constant moved through some previous computation. */
4965 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4966 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4967 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4968 return &XEXP (XEXP (x, 0), 0);
4971 /* If we have a PLUS whose first operand is complex, try computing it
4972 separately by making a split there. */
4973 if (GET_CODE (XEXP (x, 0)) == PLUS
4974 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4975 MEM_ADDR_SPACE (x))
4976 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4977 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4978 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4979 return &XEXP (XEXP (x, 0), 0);
4980 break;
4982 case SET:
4983 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4984 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4985 we need to put the operand into a register. So split at that
4986 point. */
4988 if (SET_DEST (x) == cc0_rtx
4989 && GET_CODE (SET_SRC (x)) != COMPARE
4990 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4991 && !OBJECT_P (SET_SRC (x))
4992 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4993 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4994 return &SET_SRC (x);
4996 /* See if we can split SET_SRC as it stands. */
4997 split = find_split_point (&SET_SRC (x), insn, true);
4998 if (split && split != &SET_SRC (x))
4999 return split;
5001 /* See if we can split SET_DEST as it stands. */
5002 split = find_split_point (&SET_DEST (x), insn, false);
5003 if (split && split != &SET_DEST (x))
5004 return split;
5006 /* See if this is a bitfield assignment with everything constant. If
5007 so, this is an IOR of an AND, so split it into that. */
5008 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5009 && is_a <scalar_int_mode> (GET_MODE (XEXP (SET_DEST (x), 0)),
5010 &inner_mode)
5011 && HWI_COMPUTABLE_MODE_P (inner_mode)
5012 && CONST_INT_P (XEXP (SET_DEST (x), 1))
5013 && CONST_INT_P (XEXP (SET_DEST (x), 2))
5014 && CONST_INT_P (SET_SRC (x))
5015 && ((INTVAL (XEXP (SET_DEST (x), 1))
5016 + INTVAL (XEXP (SET_DEST (x), 2)))
5017 <= GET_MODE_PRECISION (inner_mode))
5018 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
5020 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
5021 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
5022 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
5023 rtx dest = XEXP (SET_DEST (x), 0);
5024 unsigned HOST_WIDE_INT mask
5025 = (HOST_WIDE_INT_1U << len) - 1;
5026 rtx or_mask;
5028 if (BITS_BIG_ENDIAN)
5029 pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5031 or_mask = gen_int_mode (src << pos, inner_mode);
5032 if (src == mask)
5033 SUBST (SET_SRC (x),
5034 simplify_gen_binary (IOR, inner_mode, dest, or_mask));
5035 else
5037 rtx negmask = gen_int_mode (~(mask << pos), inner_mode);
5038 SUBST (SET_SRC (x),
5039 simplify_gen_binary (IOR, inner_mode,
5040 simplify_gen_binary (AND, inner_mode,
5041 dest, negmask),
5042 or_mask));
5045 SUBST (SET_DEST (x), dest);
5047 split = find_split_point (&SET_SRC (x), insn, true);
5048 if (split && split != &SET_SRC (x))
5049 return split;
5052 /* Otherwise, see if this is an operation that we can split into two.
5053 If so, try to split that. */
5054 code = GET_CODE (SET_SRC (x));
5056 switch (code)
5058 case AND:
5059 /* If we are AND'ing with a large constant that is only a single
5060 bit and the result is only being used in a context where we
5061 need to know if it is zero or nonzero, replace it with a bit
5062 extraction. This will avoid the large constant, which might
5063 have taken more than one insn to make. If the constant were
5064 not a valid argument to the AND but took only one insn to make,
5065 this is no worse, but if it took more than one insn, it will
5066 be better. */
5068 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
5069 && REG_P (XEXP (SET_SRC (x), 0))
5070 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
5071 && REG_P (SET_DEST (x))
5072 && (split = find_single_use (SET_DEST (x), insn, NULL)) != 0
5073 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
5074 && XEXP (*split, 0) == SET_DEST (x)
5075 && XEXP (*split, 1) == const0_rtx)
5077 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
5078 XEXP (SET_SRC (x), 0),
5079 pos, NULL_RTX, 1, 1, 0, 0);
5080 if (extraction != 0)
5082 SUBST (SET_SRC (x), extraction);
5083 return find_split_point (loc, insn, false);
5086 break;
5088 case NE:
5089 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5090 is known to be on, this can be converted into a NEG of a shift. */
5091 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
5092 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
5093 && ((pos = exact_log2 (nonzero_bits (XEXP (SET_SRC (x), 0),
5094 GET_MODE (XEXP (SET_SRC (x),
5095 0))))) >= 1))
5097 machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
5098 rtx pos_rtx = gen_int_shift_amount (mode, pos);
5099 SUBST (SET_SRC (x),
5100 gen_rtx_NEG (mode,
5101 gen_rtx_LSHIFTRT (mode,
5102 XEXP (SET_SRC (x), 0),
5103 pos_rtx)));
5105 split = find_split_point (&SET_SRC (x), insn, true);
5106 if (split && split != &SET_SRC (x))
5107 return split;
5109 break;
5111 case SIGN_EXTEND:
5112 inner = XEXP (SET_SRC (x), 0);
5114 /* We can't optimize if either mode is a partial integer
5115 mode as we don't know how many bits are significant
5116 in those modes. */
5117 if (!is_int_mode (GET_MODE (inner), &inner_mode)
5118 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
5119 break;
5121 pos = 0;
5122 len = GET_MODE_PRECISION (inner_mode);
5123 unsignedp = 0;
5124 break;
5126 case SIGN_EXTRACT:
5127 case ZERO_EXTRACT:
5128 if (is_a <scalar_int_mode> (GET_MODE (XEXP (SET_SRC (x), 0)),
5129 &inner_mode)
5130 && CONST_INT_P (XEXP (SET_SRC (x), 1))
5131 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
5133 inner = XEXP (SET_SRC (x), 0);
5134 len = INTVAL (XEXP (SET_SRC (x), 1));
5135 pos = INTVAL (XEXP (SET_SRC (x), 2));
5137 if (BITS_BIG_ENDIAN)
5138 pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5139 unsignedp = (code == ZERO_EXTRACT);
5141 break;
5143 default:
5144 break;
5147 if (len
5148 && known_subrange_p (pos, len,
5149 0, GET_MODE_PRECISION (GET_MODE (inner)))
5150 && is_a <scalar_int_mode> (GET_MODE (SET_SRC (x)), &mode))
5152 /* For unsigned, we have a choice of a shift followed by an
5153 AND or two shifts. Use two shifts for field sizes where the
5154 constant might be too large. We assume here that we can
5155 always at least get 8-bit constants in an AND insn, which is
5156 true for every current RISC. */
5158 if (unsignedp && len <= 8)
5160 unsigned HOST_WIDE_INT mask
5161 = (HOST_WIDE_INT_1U << len) - 1;
5162 rtx pos_rtx = gen_int_shift_amount (mode, pos);
5163 SUBST (SET_SRC (x),
5164 gen_rtx_AND (mode,
5165 gen_rtx_LSHIFTRT
5166 (mode, gen_lowpart (mode, inner), pos_rtx),
5167 gen_int_mode (mask, mode)));
5169 split = find_split_point (&SET_SRC (x), insn, true);
5170 if (split && split != &SET_SRC (x))
5171 return split;
5173 else
5175 int left_bits = GET_MODE_PRECISION (mode) - len - pos;
5176 int right_bits = GET_MODE_PRECISION (mode) - len;
5177 SUBST (SET_SRC (x),
5178 gen_rtx_fmt_ee
5179 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
5180 gen_rtx_ASHIFT (mode,
5181 gen_lowpart (mode, inner),
5182 gen_int_shift_amount (mode, left_bits)),
5183 gen_int_shift_amount (mode, right_bits)));
5185 split = find_split_point (&SET_SRC (x), insn, true);
5186 if (split && split != &SET_SRC (x))
5187 return split;
5191 /* See if this is a simple operation with a constant as the second
5192 operand. It might be that this constant is out of range and hence
5193 could be used as a split point. */
5194 if (BINARY_P (SET_SRC (x))
5195 && CONSTANT_P (XEXP (SET_SRC (x), 1))
5196 && (OBJECT_P (XEXP (SET_SRC (x), 0))
5197 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
5198 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
5199 return &XEXP (SET_SRC (x), 1);
5201 /* Finally, see if this is a simple operation with its first operand
5202 not in a register. The operation might require this operand in a
5203 register, so return it as a split point. We can always do this
5204 because if the first operand were another operation, we would have
5205 already found it as a split point. */
5206 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
5207 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
5208 return &XEXP (SET_SRC (x), 0);
5210 return 0;
5212 case AND:
5213 case IOR:
5214 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5215 it is better to write this as (not (ior A B)) so we can split it.
5216 Similarly for IOR. */
5217 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
5219 SUBST (*loc,
5220 gen_rtx_NOT (GET_MODE (x),
5221 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
5222 GET_MODE (x),
5223 XEXP (XEXP (x, 0), 0),
5224 XEXP (XEXP (x, 1), 0))));
5225 return find_split_point (loc, insn, set_src);
5228 /* Many RISC machines have a large set of logical insns. If the
5229 second operand is a NOT, put it first so we will try to split the
5230 other operand first. */
5231 if (GET_CODE (XEXP (x, 1)) == NOT)
5233 rtx tem = XEXP (x, 0);
5234 SUBST (XEXP (x, 0), XEXP (x, 1));
5235 SUBST (XEXP (x, 1), tem);
5237 break;
5239 case PLUS:
5240 case MINUS:
5241 /* Canonicalization can produce (minus A (mult B C)), where C is a
5242 constant. It may be better to try splitting (plus (mult B -C) A)
5243 instead if this isn't a multiply by a power of two. */
5244 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
5245 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
5246 && !pow2p_hwi (INTVAL (XEXP (XEXP (x, 1), 1))))
5248 machine_mode mode = GET_MODE (x);
5249 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
5250 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
5251 SUBST (*loc, gen_rtx_PLUS (mode,
5252 gen_rtx_MULT (mode,
5253 XEXP (XEXP (x, 1), 0),
5254 gen_int_mode (other_int,
5255 mode)),
5256 XEXP (x, 0)));
5257 return find_split_point (loc, insn, set_src);
5260 /* Split at a multiply-accumulate instruction. However if this is
5261 the SET_SRC, we likely do not have such an instruction and it's
5262 worthless to try this split. */
5263 if (!set_src
5264 && (GET_CODE (XEXP (x, 0)) == MULT
5265 || (GET_CODE (XEXP (x, 0)) == ASHIFT
5266 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
5267 return loc;
5269 default:
5270 break;
5273 /* Otherwise, select our actions depending on our rtx class. */
5274 switch (GET_RTX_CLASS (code))
5276 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5277 case RTX_TERNARY:
5278 split = find_split_point (&XEXP (x, 2), insn, false);
5279 if (split)
5280 return split;
5281 /* fall through */
5282 case RTX_BIN_ARITH:
5283 case RTX_COMM_ARITH:
5284 case RTX_COMPARE:
5285 case RTX_COMM_COMPARE:
5286 split = find_split_point (&XEXP (x, 1), insn, false);
5287 if (split)
5288 return split;
5289 /* fall through */
5290 case RTX_UNARY:
5291 /* Some machines have (and (shift ...) ...) insns. If X is not
5292 an AND, but XEXP (X, 0) is, use it as our split point. */
5293 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
5294 return &XEXP (x, 0);
5296 split = find_split_point (&XEXP (x, 0), insn, false);
5297 if (split)
5298 return split;
5299 return loc;
5301 default:
5302 /* Otherwise, we don't have a split point. */
5303 return 0;
5307 /* Throughout X, replace FROM with TO, and return the result.
5308 The result is TO if X is FROM;
5309 otherwise the result is X, but its contents may have been modified.
5310 If they were modified, a record was made in undobuf so that
5311 undo_all will (among other things) return X to its original state.
5313 If the number of changes necessary is too much to record to undo,
5314 the excess changes are not made, so the result is invalid.
5315 The changes already made can still be undone.
5316 undobuf.num_undo is incremented for such changes, so by testing that
5317 the caller can tell whether the result is valid.
5319 `n_occurrences' is incremented each time FROM is replaced.
5321 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5323 IN_COND is nonzero if we are at the top level of a condition.
5325 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5326 by copying if `n_occurrences' is nonzero. */
5328 static rtx
5329 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
5331 enum rtx_code code = GET_CODE (x);
5332 machine_mode op0_mode = VOIDmode;
5333 const char *fmt;
5334 int len, i;
5335 rtx new_rtx;
5337 /* Two expressions are equal if they are identical copies of a shared
5338 RTX or if they are both registers with the same register number
5339 and mode. */
5341 #define COMBINE_RTX_EQUAL_P(X,Y) \
5342 ((X) == (Y) \
5343 || (REG_P (X) && REG_P (Y) \
5344 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5346 /* Do not substitute into clobbers of regs -- this will never result in
5347 valid RTL. */
5348 if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0)))
5349 return x;
5351 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5353 n_occurrences++;
5354 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5357 /* If X and FROM are the same register but different modes, they
5358 will not have been seen as equal above. However, the log links code
5359 will make a LOG_LINKS entry for that case. If we do nothing, we
5360 will try to rerecognize our original insn and, when it succeeds,
5361 we will delete the feeding insn, which is incorrect.
5363 So force this insn not to match in this (rare) case. */
5364 if (! in_dest && code == REG && REG_P (from)
5365 && reg_overlap_mentioned_p (x, from))
5366 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5368 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5369 of which may contain things that can be combined. */
5370 if (code != MEM && code != LO_SUM && OBJECT_P (x))
5371 return x;
5373 /* It is possible to have a subexpression appear twice in the insn.
5374 Suppose that FROM is a register that appears within TO.
5375 Then, after that subexpression has been scanned once by `subst',
5376 the second time it is scanned, TO may be found. If we were
5377 to scan TO here, we would find FROM within it and create a
5378 self-referent rtl structure which is completely wrong. */
5379 if (COMBINE_RTX_EQUAL_P (x, to))
5380 return to;
5382 /* Parallel asm_operands need special attention because all of the
5383 inputs are shared across the arms. Furthermore, unsharing the
5384 rtl results in recognition failures. Failure to handle this case
5385 specially can result in circular rtl.
5387 Solve this by doing a normal pass across the first entry of the
5388 parallel, and only processing the SET_DESTs of the subsequent
5389 entries. Ug. */
5391 if (code == PARALLEL
5392 && GET_CODE (XVECEXP (x, 0, 0)) == SET
5393 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5395 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
5397 /* If this substitution failed, this whole thing fails. */
5398 if (GET_CODE (new_rtx) == CLOBBER
5399 && XEXP (new_rtx, 0) == const0_rtx)
5400 return new_rtx;
5402 SUBST (XVECEXP (x, 0, 0), new_rtx);
5404 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5406 rtx dest = SET_DEST (XVECEXP (x, 0, i));
5408 if (!REG_P (dest)
5409 && GET_CODE (dest) != CC0
5410 && GET_CODE (dest) != PC)
5412 new_rtx = subst (dest, from, to, 0, 0, unique_copy);
5414 /* If this substitution failed, this whole thing fails. */
5415 if (GET_CODE (new_rtx) == CLOBBER
5416 && XEXP (new_rtx, 0) == const0_rtx)
5417 return new_rtx;
5419 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5423 else
5425 len = GET_RTX_LENGTH (code);
5426 fmt = GET_RTX_FORMAT (code);
5428 /* We don't need to process a SET_DEST that is a register, CC0,
5429 or PC, so set up to skip this common case. All other cases
5430 where we want to suppress replacing something inside a
5431 SET_SRC are handled via the IN_DEST operand. */
5432 if (code == SET
5433 && (REG_P (SET_DEST (x))
5434 || GET_CODE (SET_DEST (x)) == CC0
5435 || GET_CODE (SET_DEST (x)) == PC))
5436 fmt = "ie";
5438 /* Trying to simplify the operands of a widening MULT is not likely
5439 to create RTL matching a machine insn. */
5440 if (code == MULT
5441 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5442 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
5443 && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
5444 || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
5445 && REG_P (XEXP (XEXP (x, 0), 0))
5446 && REG_P (XEXP (XEXP (x, 1), 0))
5447 && from == to)
5448 return x;
5451 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5452 constant. */
5453 if (fmt[0] == 'e')
5454 op0_mode = GET_MODE (XEXP (x, 0));
5456 for (i = 0; i < len; i++)
5458 if (fmt[i] == 'E')
5460 int j;
5461 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5463 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5465 new_rtx = (unique_copy && n_occurrences
5466 ? copy_rtx (to) : to);
5467 n_occurrences++;
5469 else
5471 new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5472 unique_copy);
5474 /* If this substitution failed, this whole thing
5475 fails. */
5476 if (GET_CODE (new_rtx) == CLOBBER
5477 && XEXP (new_rtx, 0) == const0_rtx)
5478 return new_rtx;
5481 SUBST (XVECEXP (x, i, j), new_rtx);
5484 else if (fmt[i] == 'e')
5486 /* If this is a register being set, ignore it. */
5487 new_rtx = XEXP (x, i);
5488 if (in_dest
5489 && i == 0
5490 && (((code == SUBREG || code == ZERO_EXTRACT)
5491 && REG_P (new_rtx))
5492 || code == STRICT_LOW_PART))
5495 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5497 /* In general, don't install a subreg involving two
5498 modes not tieable. It can worsen register
5499 allocation, and can even make invalid reload
5500 insns, since the reg inside may need to be copied
5501 from in the outside mode, and that may be invalid
5502 if it is an fp reg copied in integer mode.
5504 We allow two exceptions to this: It is valid if
5505 it is inside another SUBREG and the mode of that
5506 SUBREG and the mode of the inside of TO is
5507 tieable and it is valid if X is a SET that copies
5508 FROM to CC0. */
5510 if (GET_CODE (to) == SUBREG
5511 && !targetm.modes_tieable_p (GET_MODE (to),
5512 GET_MODE (SUBREG_REG (to)))
5513 && ! (code == SUBREG
5514 && (targetm.modes_tieable_p
5515 (GET_MODE (x), GET_MODE (SUBREG_REG (to)))))
5516 && (!HAVE_cc0
5517 || (! (code == SET
5518 && i == 1
5519 && XEXP (x, 0) == cc0_rtx))))
5520 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5522 if (code == SUBREG
5523 && REG_P (to)
5524 && REGNO (to) < FIRST_PSEUDO_REGISTER
5525 && simplify_subreg_regno (REGNO (to), GET_MODE (to),
5526 SUBREG_BYTE (x),
5527 GET_MODE (x)) < 0)
5528 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5530 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5531 n_occurrences++;
5533 else
5534 /* If we are in a SET_DEST, suppress most cases unless we
5535 have gone inside a MEM, in which case we want to
5536 simplify the address. We assume here that things that
5537 are actually part of the destination have their inner
5538 parts in the first expression. This is true for SUBREG,
5539 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5540 things aside from REG and MEM that should appear in a
5541 SET_DEST. */
5542 new_rtx = subst (XEXP (x, i), from, to,
5543 (((in_dest
5544 && (code == SUBREG || code == STRICT_LOW_PART
5545 || code == ZERO_EXTRACT))
5546 || code == SET)
5547 && i == 0),
5548 code == IF_THEN_ELSE && i == 0,
5549 unique_copy);
5551 /* If we found that we will have to reject this combination,
5552 indicate that by returning the CLOBBER ourselves, rather than
5553 an expression containing it. This will speed things up as
5554 well as prevent accidents where two CLOBBERs are considered
5555 to be equal, thus producing an incorrect simplification. */
5557 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5558 return new_rtx;
5560 if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5562 machine_mode mode = GET_MODE (x);
5564 x = simplify_subreg (GET_MODE (x), new_rtx,
5565 GET_MODE (SUBREG_REG (x)),
5566 SUBREG_BYTE (x));
5567 if (! x)
5568 x = gen_rtx_CLOBBER (mode, const0_rtx);
5570 else if (CONST_SCALAR_INT_P (new_rtx)
5571 && GET_CODE (x) == ZERO_EXTEND)
5573 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5574 new_rtx, GET_MODE (XEXP (x, 0)));
5575 gcc_assert (x);
5577 else
5578 SUBST (XEXP (x, i), new_rtx);
5583 /* Check if we are loading something from the constant pool via float
5584 extension; in this case we would undo compress_float_constant
5585 optimization and degenerate constant load to an immediate value. */
5586 if (GET_CODE (x) == FLOAT_EXTEND
5587 && MEM_P (XEXP (x, 0))
5588 && MEM_READONLY_P (XEXP (x, 0)))
5590 rtx tmp = avoid_constant_pool_reference (x);
5591 if (x != tmp)
5592 return x;
5595 /* Try to simplify X. If the simplification changed the code, it is likely
5596 that further simplification will help, so loop, but limit the number
5597 of repetitions that will be performed. */
5599 for (i = 0; i < 4; i++)
5601 /* If X is sufficiently simple, don't bother trying to do anything
5602 with it. */
5603 if (code != CONST_INT && code != REG && code != CLOBBER)
5604 x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5606 if (GET_CODE (x) == code)
5607 break;
5609 code = GET_CODE (x);
5611 /* We no longer know the original mode of operand 0 since we
5612 have changed the form of X) */
5613 op0_mode = VOIDmode;
5616 return x;
5619 /* If X is a commutative operation whose operands are not in the canonical
5620 order, use substitutions to swap them. */
5622 static void
5623 maybe_swap_commutative_operands (rtx x)
5625 if (COMMUTATIVE_ARITH_P (x)
5626 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5628 rtx temp = XEXP (x, 0);
5629 SUBST (XEXP (x, 0), XEXP (x, 1));
5630 SUBST (XEXP (x, 1), temp);
5634 /* Simplify X, a piece of RTL. We just operate on the expression at the
5635 outer level; call `subst' to simplify recursively. Return the new
5636 expression.
5638 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5639 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5640 of a condition. */
5642 static rtx
5643 combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
5644 int in_cond)
5646 enum rtx_code code = GET_CODE (x);
5647 machine_mode mode = GET_MODE (x);
5648 scalar_int_mode int_mode;
5649 rtx temp;
5650 int i;
5652 /* If this is a commutative operation, put a constant last and a complex
5653 expression first. We don't need to do this for comparisons here. */
5654 maybe_swap_commutative_operands (x);
5656 /* Try to fold this expression in case we have constants that weren't
5657 present before. */
5658 temp = 0;
5659 switch (GET_RTX_CLASS (code))
5661 case RTX_UNARY:
5662 if (op0_mode == VOIDmode)
5663 op0_mode = GET_MODE (XEXP (x, 0));
5664 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5665 break;
5666 case RTX_COMPARE:
5667 case RTX_COMM_COMPARE:
5669 machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5670 if (cmp_mode == VOIDmode)
5672 cmp_mode = GET_MODE (XEXP (x, 1));
5673 if (cmp_mode == VOIDmode)
5674 cmp_mode = op0_mode;
5676 temp = simplify_relational_operation (code, mode, cmp_mode,
5677 XEXP (x, 0), XEXP (x, 1));
5679 break;
5680 case RTX_COMM_ARITH:
5681 case RTX_BIN_ARITH:
5682 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5683 break;
5684 case RTX_BITFIELD_OPS:
5685 case RTX_TERNARY:
5686 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5687 XEXP (x, 1), XEXP (x, 2));
5688 break;
5689 default:
5690 break;
5693 if (temp)
5695 x = temp;
5696 code = GET_CODE (temp);
5697 op0_mode = VOIDmode;
5698 mode = GET_MODE (temp);
5701 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5702 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5703 things. Check for cases where both arms are testing the same
5704 condition.
5706 Don't do anything if all operands are very simple. */
5708 if ((BINARY_P (x)
5709 && ((!OBJECT_P (XEXP (x, 0))
5710 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5711 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5712 || (!OBJECT_P (XEXP (x, 1))
5713 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5714 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5715 || (UNARY_P (x)
5716 && (!OBJECT_P (XEXP (x, 0))
5717 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5718 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5720 rtx cond, true_rtx, false_rtx;
5722 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5723 if (cond != 0
5724 /* If everything is a comparison, what we have is highly unlikely
5725 to be simpler, so don't use it. */
5726 && ! (COMPARISON_P (x)
5727 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5729 rtx cop1 = const0_rtx;
5730 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5732 if (cond_code == NE && COMPARISON_P (cond))
5733 return x;
5735 /* Simplify the alternative arms; this may collapse the true and
5736 false arms to store-flag values. Be careful to use copy_rtx
5737 here since true_rtx or false_rtx might share RTL with x as a
5738 result of the if_then_else_cond call above. */
5739 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5740 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5742 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5743 is unlikely to be simpler. */
5744 if (general_operand (true_rtx, VOIDmode)
5745 && general_operand (false_rtx, VOIDmode))
5747 enum rtx_code reversed;
5749 /* Restarting if we generate a store-flag expression will cause
5750 us to loop. Just drop through in this case. */
5752 /* If the result values are STORE_FLAG_VALUE and zero, we can
5753 just make the comparison operation. */
5754 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5755 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5756 cond, cop1);
5757 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5758 && ((reversed = reversed_comparison_code_parts
5759 (cond_code, cond, cop1, NULL))
5760 != UNKNOWN))
5761 x = simplify_gen_relational (reversed, mode, VOIDmode,
5762 cond, cop1);
5764 /* Likewise, we can make the negate of a comparison operation
5765 if the result values are - STORE_FLAG_VALUE and zero. */
5766 else if (CONST_INT_P (true_rtx)
5767 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5768 && false_rtx == const0_rtx)
5769 x = simplify_gen_unary (NEG, mode,
5770 simplify_gen_relational (cond_code,
5771 mode, VOIDmode,
5772 cond, cop1),
5773 mode);
5774 else if (CONST_INT_P (false_rtx)
5775 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5776 && true_rtx == const0_rtx
5777 && ((reversed = reversed_comparison_code_parts
5778 (cond_code, cond, cop1, NULL))
5779 != UNKNOWN))
5780 x = simplify_gen_unary (NEG, mode,
5781 simplify_gen_relational (reversed,
5782 mode, VOIDmode,
5783 cond, cop1),
5784 mode);
5785 else
5786 return gen_rtx_IF_THEN_ELSE (mode,
5787 simplify_gen_relational (cond_code,
5788 mode,
5789 VOIDmode,
5790 cond,
5791 cop1),
5792 true_rtx, false_rtx);
5794 code = GET_CODE (x);
5795 op0_mode = VOIDmode;
5800 /* First see if we can apply the inverse distributive law. */
5801 if (code == PLUS || code == MINUS
5802 || code == AND || code == IOR || code == XOR)
5804 x = apply_distributive_law (x);
5805 code = GET_CODE (x);
5806 op0_mode = VOIDmode;
5809 /* If CODE is an associative operation not otherwise handled, see if we
5810 can associate some operands. This can win if they are constants or
5811 if they are logically related (i.e. (a & b) & a). */
5812 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5813 || code == AND || code == IOR || code == XOR
5814 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5815 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5816 || (flag_associative_math && FLOAT_MODE_P (mode))))
5818 if (GET_CODE (XEXP (x, 0)) == code)
5820 rtx other = XEXP (XEXP (x, 0), 0);
5821 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5822 rtx inner_op1 = XEXP (x, 1);
5823 rtx inner;
5825 /* Make sure we pass the constant operand if any as the second
5826 one if this is a commutative operation. */
5827 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5828 std::swap (inner_op0, inner_op1);
5829 inner = simplify_binary_operation (code == MINUS ? PLUS
5830 : code == DIV ? MULT
5831 : code,
5832 mode, inner_op0, inner_op1);
5834 /* For commutative operations, try the other pair if that one
5835 didn't simplify. */
5836 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5838 other = XEXP (XEXP (x, 0), 1);
5839 inner = simplify_binary_operation (code, mode,
5840 XEXP (XEXP (x, 0), 0),
5841 XEXP (x, 1));
5844 if (inner)
5845 return simplify_gen_binary (code, mode, other, inner);
5849 /* A little bit of algebraic simplification here. */
5850 switch (code)
5852 case MEM:
5853 /* Ensure that our address has any ASHIFTs converted to MULT in case
5854 address-recognizing predicates are called later. */
5855 temp = make_compound_operation (XEXP (x, 0), MEM);
5856 SUBST (XEXP (x, 0), temp);
5857 break;
5859 case SUBREG:
5860 if (op0_mode == VOIDmode)
5861 op0_mode = GET_MODE (SUBREG_REG (x));
5863 /* See if this can be moved to simplify_subreg. */
5864 if (CONSTANT_P (SUBREG_REG (x))
5865 && known_eq (subreg_lowpart_offset (mode, op0_mode), SUBREG_BYTE (x))
5866 /* Don't call gen_lowpart if the inner mode
5867 is VOIDmode and we cannot simplify it, as SUBREG without
5868 inner mode is invalid. */
5869 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5870 || gen_lowpart_common (mode, SUBREG_REG (x))))
5871 return gen_lowpart (mode, SUBREG_REG (x));
5873 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5874 break;
5876 rtx temp;
5877 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5878 SUBREG_BYTE (x));
5879 if (temp)
5880 return temp;
5882 /* If op is known to have all lower bits zero, the result is zero. */
5883 scalar_int_mode int_mode, int_op0_mode;
5884 if (!in_dest
5885 && is_a <scalar_int_mode> (mode, &int_mode)
5886 && is_a <scalar_int_mode> (op0_mode, &int_op0_mode)
5887 && (GET_MODE_PRECISION (int_mode)
5888 < GET_MODE_PRECISION (int_op0_mode))
5889 && known_eq (subreg_lowpart_offset (int_mode, int_op0_mode),
5890 SUBREG_BYTE (x))
5891 && HWI_COMPUTABLE_MODE_P (int_op0_mode)
5892 && (nonzero_bits (SUBREG_REG (x), int_op0_mode)
5893 & GET_MODE_MASK (int_mode)) == 0)
5894 return CONST0_RTX (int_mode);
5897 /* Don't change the mode of the MEM if that would change the meaning
5898 of the address. */
5899 if (MEM_P (SUBREG_REG (x))
5900 && (MEM_VOLATILE_P (SUBREG_REG (x))
5901 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5902 MEM_ADDR_SPACE (SUBREG_REG (x)))))
5903 return gen_rtx_CLOBBER (mode, const0_rtx);
5905 /* Note that we cannot do any narrowing for non-constants since
5906 we might have been counting on using the fact that some bits were
5907 zero. We now do this in the SET. */
5909 break;
5911 case NEG:
5912 temp = expand_compound_operation (XEXP (x, 0));
5914 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5915 replaced by (lshiftrt X C). This will convert
5916 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5918 if (GET_CODE (temp) == ASHIFTRT
5919 && CONST_INT_P (XEXP (temp, 1))
5920 && INTVAL (XEXP (temp, 1)) == GET_MODE_UNIT_PRECISION (mode) - 1)
5921 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5922 INTVAL (XEXP (temp, 1)));
5924 /* If X has only a single bit that might be nonzero, say, bit I, convert
5925 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5926 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5927 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5928 or a SUBREG of one since we'd be making the expression more
5929 complex if it was just a register. */
5931 if (!REG_P (temp)
5932 && ! (GET_CODE (temp) == SUBREG
5933 && REG_P (SUBREG_REG (temp)))
5934 && is_a <scalar_int_mode> (mode, &int_mode)
5935 && (i = exact_log2 (nonzero_bits (temp, int_mode))) >= 0)
5937 rtx temp1 = simplify_shift_const
5938 (NULL_RTX, ASHIFTRT, int_mode,
5939 simplify_shift_const (NULL_RTX, ASHIFT, int_mode, temp,
5940 GET_MODE_PRECISION (int_mode) - 1 - i),
5941 GET_MODE_PRECISION (int_mode) - 1 - i);
5943 /* If all we did was surround TEMP with the two shifts, we
5944 haven't improved anything, so don't use it. Otherwise,
5945 we are better off with TEMP1. */
5946 if (GET_CODE (temp1) != ASHIFTRT
5947 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5948 || XEXP (XEXP (temp1, 0), 0) != temp)
5949 return temp1;
5951 break;
5953 case TRUNCATE:
5954 /* We can't handle truncation to a partial integer mode here
5955 because we don't know the real bitsize of the partial
5956 integer mode. */
5957 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5958 break;
5960 if (HWI_COMPUTABLE_MODE_P (mode))
5961 SUBST (XEXP (x, 0),
5962 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5963 GET_MODE_MASK (mode), 0));
5965 /* We can truncate a constant value and return it. */
5966 if (CONST_INT_P (XEXP (x, 0)))
5967 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5969 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5970 whose value is a comparison can be replaced with a subreg if
5971 STORE_FLAG_VALUE permits. */
5972 if (HWI_COMPUTABLE_MODE_P (mode)
5973 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5974 && (temp = get_last_value (XEXP (x, 0)))
5975 && COMPARISON_P (temp))
5976 return gen_lowpart (mode, XEXP (x, 0));
5977 break;
5979 case CONST:
5980 /* (const (const X)) can become (const X). Do it this way rather than
5981 returning the inner CONST since CONST can be shared with a
5982 REG_EQUAL note. */
5983 if (GET_CODE (XEXP (x, 0)) == CONST)
5984 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5985 break;
5987 case LO_SUM:
5988 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5989 can add in an offset. find_split_point will split this address up
5990 again if it doesn't match. */
5991 if (HAVE_lo_sum && GET_CODE (XEXP (x, 0)) == HIGH
5992 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5993 return XEXP (x, 1);
5994 break;
5996 case PLUS:
5997 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5998 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5999 bit-field and can be replaced by either a sign_extend or a
6000 sign_extract. The `and' may be a zero_extend and the two
6001 <c>, -<c> constants may be reversed. */
6002 if (GET_CODE (XEXP (x, 0)) == XOR
6003 && is_a <scalar_int_mode> (mode, &int_mode)
6004 && CONST_INT_P (XEXP (x, 1))
6005 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
6006 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
6007 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
6008 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
6009 && HWI_COMPUTABLE_MODE_P (int_mode)
6010 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
6011 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
6012 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
6013 == (HOST_WIDE_INT_1U << (i + 1)) - 1))
6014 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
6015 && known_eq ((GET_MODE_PRECISION
6016 (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))),
6017 (unsigned int) i + 1))))
6018 return simplify_shift_const
6019 (NULL_RTX, ASHIFTRT, int_mode,
6020 simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6021 XEXP (XEXP (XEXP (x, 0), 0), 0),
6022 GET_MODE_PRECISION (int_mode) - (i + 1)),
6023 GET_MODE_PRECISION (int_mode) - (i + 1));
6025 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6026 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6027 the bitsize of the mode - 1. This allows simplification of
6028 "a = (b & 8) == 0;" */
6029 if (XEXP (x, 1) == constm1_rtx
6030 && !REG_P (XEXP (x, 0))
6031 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
6032 && REG_P (SUBREG_REG (XEXP (x, 0))))
6033 && is_a <scalar_int_mode> (mode, &int_mode)
6034 && nonzero_bits (XEXP (x, 0), int_mode) == 1)
6035 return simplify_shift_const
6036 (NULL_RTX, ASHIFTRT, int_mode,
6037 simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6038 gen_rtx_XOR (int_mode, XEXP (x, 0),
6039 const1_rtx),
6040 GET_MODE_PRECISION (int_mode) - 1),
6041 GET_MODE_PRECISION (int_mode) - 1);
6043 /* If we are adding two things that have no bits in common, convert
6044 the addition into an IOR. This will often be further simplified,
6045 for example in cases like ((a & 1) + (a & 2)), which can
6046 become a & 3. */
6048 if (HWI_COMPUTABLE_MODE_P (mode)
6049 && (nonzero_bits (XEXP (x, 0), mode)
6050 & nonzero_bits (XEXP (x, 1), mode)) == 0)
6052 /* Try to simplify the expression further. */
6053 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
6054 temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
6056 /* If we could, great. If not, do not go ahead with the IOR
6057 replacement, since PLUS appears in many special purpose
6058 address arithmetic instructions. */
6059 if (GET_CODE (temp) != CLOBBER
6060 && (GET_CODE (temp) != IOR
6061 || ((XEXP (temp, 0) != XEXP (x, 0)
6062 || XEXP (temp, 1) != XEXP (x, 1))
6063 && (XEXP (temp, 0) != XEXP (x, 1)
6064 || XEXP (temp, 1) != XEXP (x, 0)))))
6065 return temp;
6068 /* Canonicalize x + x into x << 1. */
6069 if (GET_MODE_CLASS (mode) == MODE_INT
6070 && rtx_equal_p (XEXP (x, 0), XEXP (x, 1))
6071 && !side_effects_p (XEXP (x, 0)))
6072 return simplify_gen_binary (ASHIFT, mode, XEXP (x, 0), const1_rtx);
6074 break;
6076 case MINUS:
6077 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6078 (and <foo> (const_int pow2-1)) */
6079 if (is_a <scalar_int_mode> (mode, &int_mode)
6080 && GET_CODE (XEXP (x, 1)) == AND
6081 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
6082 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x, 1), 1)))
6083 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6084 return simplify_and_const_int (NULL_RTX, int_mode, XEXP (x, 0),
6085 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
6086 break;
6088 case MULT:
6089 /* If we have (mult (plus A B) C), apply the distributive law and then
6090 the inverse distributive law to see if things simplify. This
6091 occurs mostly in addresses, often when unrolling loops. */
6093 if (GET_CODE (XEXP (x, 0)) == PLUS)
6095 rtx result = distribute_and_simplify_rtx (x, 0);
6096 if (result)
6097 return result;
6100 /* Try simplify a*(b/c) as (a*b)/c. */
6101 if (FLOAT_MODE_P (mode) && flag_associative_math
6102 && GET_CODE (XEXP (x, 0)) == DIV)
6104 rtx tem = simplify_binary_operation (MULT, mode,
6105 XEXP (XEXP (x, 0), 0),
6106 XEXP (x, 1));
6107 if (tem)
6108 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
6110 break;
6112 case UDIV:
6113 /* If this is a divide by a power of two, treat it as a shift if
6114 its first operand is a shift. */
6115 if (is_a <scalar_int_mode> (mode, &int_mode)
6116 && CONST_INT_P (XEXP (x, 1))
6117 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
6118 && (GET_CODE (XEXP (x, 0)) == ASHIFT
6119 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
6120 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
6121 || GET_CODE (XEXP (x, 0)) == ROTATE
6122 || GET_CODE (XEXP (x, 0)) == ROTATERT))
6123 return simplify_shift_const (NULL_RTX, LSHIFTRT, int_mode,
6124 XEXP (x, 0), i);
6125 break;
6127 case EQ: case NE:
6128 case GT: case GTU: case GE: case GEU:
6129 case LT: case LTU: case LE: case LEU:
6130 case UNEQ: case LTGT:
6131 case UNGT: case UNGE:
6132 case UNLT: case UNLE:
6133 case UNORDERED: case ORDERED:
6134 /* If the first operand is a condition code, we can't do anything
6135 with it. */
6136 if (GET_CODE (XEXP (x, 0)) == COMPARE
6137 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
6138 && ! CC0_P (XEXP (x, 0))))
6140 rtx op0 = XEXP (x, 0);
6141 rtx op1 = XEXP (x, 1);
6142 enum rtx_code new_code;
6144 if (GET_CODE (op0) == COMPARE)
6145 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
6147 /* Simplify our comparison, if possible. */
6148 new_code = simplify_comparison (code, &op0, &op1);
6150 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6151 if only the low-order bit is possibly nonzero in X (such as when
6152 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6153 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6154 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6155 (plus X 1).
6157 Remove any ZERO_EXTRACT we made when thinking this was a
6158 comparison. It may now be simpler to use, e.g., an AND. If a
6159 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6160 the call to make_compound_operation in the SET case.
6162 Don't apply these optimizations if the caller would
6163 prefer a comparison rather than a value.
6164 E.g., for the condition in an IF_THEN_ELSE most targets need
6165 an explicit comparison. */
6167 if (in_cond)
6170 else if (STORE_FLAG_VALUE == 1
6171 && new_code == NE
6172 && is_int_mode (mode, &int_mode)
6173 && op1 == const0_rtx
6174 && int_mode == GET_MODE (op0)
6175 && nonzero_bits (op0, int_mode) == 1)
6176 return gen_lowpart (int_mode,
6177 expand_compound_operation (op0));
6179 else if (STORE_FLAG_VALUE == 1
6180 && new_code == NE
6181 && is_int_mode (mode, &int_mode)
6182 && op1 == const0_rtx
6183 && int_mode == GET_MODE (op0)
6184 && (num_sign_bit_copies (op0, int_mode)
6185 == GET_MODE_PRECISION (int_mode)))
6187 op0 = expand_compound_operation (op0);
6188 return simplify_gen_unary (NEG, int_mode,
6189 gen_lowpart (int_mode, op0),
6190 int_mode);
6193 else if (STORE_FLAG_VALUE == 1
6194 && new_code == EQ
6195 && is_int_mode (mode, &int_mode)
6196 && op1 == const0_rtx
6197 && int_mode == GET_MODE (op0)
6198 && nonzero_bits (op0, int_mode) == 1)
6200 op0 = expand_compound_operation (op0);
6201 return simplify_gen_binary (XOR, int_mode,
6202 gen_lowpart (int_mode, op0),
6203 const1_rtx);
6206 else if (STORE_FLAG_VALUE == 1
6207 && new_code == EQ
6208 && is_int_mode (mode, &int_mode)
6209 && op1 == const0_rtx
6210 && int_mode == GET_MODE (op0)
6211 && (num_sign_bit_copies (op0, int_mode)
6212 == GET_MODE_PRECISION (int_mode)))
6214 op0 = expand_compound_operation (op0);
6215 return plus_constant (int_mode, gen_lowpart (int_mode, op0), 1);
6218 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6219 those above. */
6220 if (in_cond)
6223 else if (STORE_FLAG_VALUE == -1
6224 && new_code == NE
6225 && is_int_mode (mode, &int_mode)
6226 && op1 == const0_rtx
6227 && int_mode == GET_MODE (op0)
6228 && (num_sign_bit_copies (op0, int_mode)
6229 == GET_MODE_PRECISION (int_mode)))
6230 return gen_lowpart (int_mode, expand_compound_operation (op0));
6232 else if (STORE_FLAG_VALUE == -1
6233 && new_code == NE
6234 && is_int_mode (mode, &int_mode)
6235 && op1 == const0_rtx
6236 && int_mode == GET_MODE (op0)
6237 && nonzero_bits (op0, int_mode) == 1)
6239 op0 = expand_compound_operation (op0);
6240 return simplify_gen_unary (NEG, int_mode,
6241 gen_lowpart (int_mode, op0),
6242 int_mode);
6245 else if (STORE_FLAG_VALUE == -1
6246 && new_code == EQ
6247 && is_int_mode (mode, &int_mode)
6248 && op1 == const0_rtx
6249 && int_mode == GET_MODE (op0)
6250 && (num_sign_bit_copies (op0, int_mode)
6251 == GET_MODE_PRECISION (int_mode)))
6253 op0 = expand_compound_operation (op0);
6254 return simplify_gen_unary (NOT, int_mode,
6255 gen_lowpart (int_mode, op0),
6256 int_mode);
6259 /* If X is 0/1, (eq X 0) is X-1. */
6260 else if (STORE_FLAG_VALUE == -1
6261 && new_code == EQ
6262 && is_int_mode (mode, &int_mode)
6263 && op1 == const0_rtx
6264 && int_mode == GET_MODE (op0)
6265 && nonzero_bits (op0, int_mode) == 1)
6267 op0 = expand_compound_operation (op0);
6268 return plus_constant (int_mode, gen_lowpart (int_mode, op0), -1);
6271 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6272 one bit that might be nonzero, we can convert (ne x 0) to
6273 (ashift x c) where C puts the bit in the sign bit. Remove any
6274 AND with STORE_FLAG_VALUE when we are done, since we are only
6275 going to test the sign bit. */
6276 if (new_code == NE
6277 && is_int_mode (mode, &int_mode)
6278 && HWI_COMPUTABLE_MODE_P (int_mode)
6279 && val_signbit_p (int_mode, STORE_FLAG_VALUE)
6280 && op1 == const0_rtx
6281 && int_mode == GET_MODE (op0)
6282 && (i = exact_log2 (nonzero_bits (op0, int_mode))) >= 0)
6284 x = simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6285 expand_compound_operation (op0),
6286 GET_MODE_PRECISION (int_mode) - 1 - i);
6287 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
6288 return XEXP (x, 0);
6289 else
6290 return x;
6293 /* If the code changed, return a whole new comparison.
6294 We also need to avoid using SUBST in cases where
6295 simplify_comparison has widened a comparison with a CONST_INT,
6296 since in that case the wider CONST_INT may fail the sanity
6297 checks in do_SUBST. */
6298 if (new_code != code
6299 || (CONST_INT_P (op1)
6300 && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
6301 && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
6302 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
6304 /* Otherwise, keep this operation, but maybe change its operands.
6305 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6306 SUBST (XEXP (x, 0), op0);
6307 SUBST (XEXP (x, 1), op1);
6309 break;
6311 case IF_THEN_ELSE:
6312 return simplify_if_then_else (x);
6314 case ZERO_EXTRACT:
6315 case SIGN_EXTRACT:
6316 case ZERO_EXTEND:
6317 case SIGN_EXTEND:
6318 /* If we are processing SET_DEST, we are done. */
6319 if (in_dest)
6320 return x;
6322 return expand_compound_operation (x);
6324 case SET:
6325 return simplify_set (x);
6327 case AND:
6328 case IOR:
6329 return simplify_logical (x);
6331 case ASHIFT:
6332 case LSHIFTRT:
6333 case ASHIFTRT:
6334 case ROTATE:
6335 case ROTATERT:
6336 /* If this is a shift by a constant amount, simplify it. */
6337 if (CONST_INT_P (XEXP (x, 1)))
6338 return simplify_shift_const (x, code, mode, XEXP (x, 0),
6339 INTVAL (XEXP (x, 1)));
6341 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
6342 SUBST (XEXP (x, 1),
6343 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
6344 (HOST_WIDE_INT_1U
6345 << exact_log2 (GET_MODE_UNIT_BITSIZE
6346 (GET_MODE (x))))
6347 - 1,
6348 0));
6349 break;
6351 default:
6352 break;
6355 return x;
6358 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6360 static rtx
6361 simplify_if_then_else (rtx x)
6363 machine_mode mode = GET_MODE (x);
6364 rtx cond = XEXP (x, 0);
6365 rtx true_rtx = XEXP (x, 1);
6366 rtx false_rtx = XEXP (x, 2);
6367 enum rtx_code true_code = GET_CODE (cond);
6368 int comparison_p = COMPARISON_P (cond);
6369 rtx temp;
6370 int i;
6371 enum rtx_code false_code;
6372 rtx reversed;
6373 scalar_int_mode int_mode, inner_mode;
6375 /* Simplify storing of the truth value. */
6376 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
6377 return simplify_gen_relational (true_code, mode, VOIDmode,
6378 XEXP (cond, 0), XEXP (cond, 1));
6380 /* Also when the truth value has to be reversed. */
6381 if (comparison_p
6382 && true_rtx == const0_rtx && false_rtx == const_true_rtx
6383 && (reversed = reversed_comparison (cond, mode)))
6384 return reversed;
6386 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6387 in it is being compared against certain values. Get the true and false
6388 comparisons and see if that says anything about the value of each arm. */
6390 if (comparison_p
6391 && ((false_code = reversed_comparison_code (cond, NULL))
6392 != UNKNOWN)
6393 && REG_P (XEXP (cond, 0)))
6395 HOST_WIDE_INT nzb;
6396 rtx from = XEXP (cond, 0);
6397 rtx true_val = XEXP (cond, 1);
6398 rtx false_val = true_val;
6399 int swapped = 0;
6401 /* If FALSE_CODE is EQ, swap the codes and arms. */
6403 if (false_code == EQ)
6405 swapped = 1, true_code = EQ, false_code = NE;
6406 std::swap (true_rtx, false_rtx);
6409 scalar_int_mode from_mode;
6410 if (is_a <scalar_int_mode> (GET_MODE (from), &from_mode))
6412 /* If we are comparing against zero and the expression being
6413 tested has only a single bit that might be nonzero, that is
6414 its value when it is not equal to zero. Similarly if it is
6415 known to be -1 or 0. */
6416 if (true_code == EQ
6417 && true_val == const0_rtx
6418 && pow2p_hwi (nzb = nonzero_bits (from, from_mode)))
6420 false_code = EQ;
6421 false_val = gen_int_mode (nzb, from_mode);
6423 else if (true_code == EQ
6424 && true_val == const0_rtx
6425 && (num_sign_bit_copies (from, from_mode)
6426 == GET_MODE_PRECISION (from_mode)))
6428 false_code = EQ;
6429 false_val = constm1_rtx;
6433 /* Now simplify an arm if we know the value of the register in the
6434 branch and it is used in the arm. Be careful due to the potential
6435 of locally-shared RTL. */
6437 if (reg_mentioned_p (from, true_rtx))
6438 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6439 from, true_val),
6440 pc_rtx, pc_rtx, 0, 0, 0);
6441 if (reg_mentioned_p (from, false_rtx))
6442 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6443 from, false_val),
6444 pc_rtx, pc_rtx, 0, 0, 0);
6446 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6447 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6449 true_rtx = XEXP (x, 1);
6450 false_rtx = XEXP (x, 2);
6451 true_code = GET_CODE (cond);
6454 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6455 reversed, do so to avoid needing two sets of patterns for
6456 subtract-and-branch insns. Similarly if we have a constant in the true
6457 arm, the false arm is the same as the first operand of the comparison, or
6458 the false arm is more complicated than the true arm. */
6460 if (comparison_p
6461 && reversed_comparison_code (cond, NULL) != UNKNOWN
6462 && (true_rtx == pc_rtx
6463 || (CONSTANT_P (true_rtx)
6464 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6465 || true_rtx == const0_rtx
6466 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6467 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6468 && !OBJECT_P (false_rtx))
6469 || reg_mentioned_p (true_rtx, false_rtx)
6470 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6472 true_code = reversed_comparison_code (cond, NULL);
6473 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6474 SUBST (XEXP (x, 1), false_rtx);
6475 SUBST (XEXP (x, 2), true_rtx);
6477 std::swap (true_rtx, false_rtx);
6478 cond = XEXP (x, 0);
6480 /* It is possible that the conditional has been simplified out. */
6481 true_code = GET_CODE (cond);
6482 comparison_p = COMPARISON_P (cond);
6485 /* If the two arms are identical, we don't need the comparison. */
6487 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6488 return true_rtx;
6490 /* Convert a == b ? b : a to "a". */
6491 if (true_code == EQ && ! side_effects_p (cond)
6492 && !HONOR_NANS (mode)
6493 && rtx_equal_p (XEXP (cond, 0), false_rtx)
6494 && rtx_equal_p (XEXP (cond, 1), true_rtx))
6495 return false_rtx;
6496 else if (true_code == NE && ! side_effects_p (cond)
6497 && !HONOR_NANS (mode)
6498 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6499 && rtx_equal_p (XEXP (cond, 1), false_rtx))
6500 return true_rtx;
6502 /* Look for cases where we have (abs x) or (neg (abs X)). */
6504 if (GET_MODE_CLASS (mode) == MODE_INT
6505 && comparison_p
6506 && XEXP (cond, 1) == const0_rtx
6507 && GET_CODE (false_rtx) == NEG
6508 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6509 && rtx_equal_p (true_rtx, XEXP (cond, 0))
6510 && ! side_effects_p (true_rtx))
6511 switch (true_code)
6513 case GT:
6514 case GE:
6515 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6516 case LT:
6517 case LE:
6518 return
6519 simplify_gen_unary (NEG, mode,
6520 simplify_gen_unary (ABS, mode, true_rtx, mode),
6521 mode);
6522 default:
6523 break;
6526 /* Look for MIN or MAX. */
6528 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6529 && comparison_p
6530 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6531 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6532 && ! side_effects_p (cond))
6533 switch (true_code)
6535 case GE:
6536 case GT:
6537 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6538 case LE:
6539 case LT:
6540 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6541 case GEU:
6542 case GTU:
6543 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6544 case LEU:
6545 case LTU:
6546 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6547 default:
6548 break;
6551 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6552 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6553 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6554 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6555 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6556 neither 1 or -1, but it isn't worth checking for. */
6558 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6559 && comparison_p
6560 && is_int_mode (mode, &int_mode)
6561 && ! side_effects_p (x))
6563 rtx t = make_compound_operation (true_rtx, SET);
6564 rtx f = make_compound_operation (false_rtx, SET);
6565 rtx cond_op0 = XEXP (cond, 0);
6566 rtx cond_op1 = XEXP (cond, 1);
6567 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6568 scalar_int_mode m = int_mode;
6569 rtx z = 0, c1 = NULL_RTX;
6571 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6572 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6573 || GET_CODE (t) == ASHIFT
6574 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6575 && rtx_equal_p (XEXP (t, 0), f))
6576 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6578 /* If an identity-zero op is commutative, check whether there
6579 would be a match if we swapped the operands. */
6580 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6581 || GET_CODE (t) == XOR)
6582 && rtx_equal_p (XEXP (t, 1), f))
6583 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6584 else if (GET_CODE (t) == SIGN_EXTEND
6585 && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6586 && (GET_CODE (XEXP (t, 0)) == PLUS
6587 || GET_CODE (XEXP (t, 0)) == MINUS
6588 || GET_CODE (XEXP (t, 0)) == IOR
6589 || GET_CODE (XEXP (t, 0)) == XOR
6590 || GET_CODE (XEXP (t, 0)) == ASHIFT
6591 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6592 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6593 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6594 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6595 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6596 && (num_sign_bit_copies (f, GET_MODE (f))
6597 > (unsigned int)
6598 (GET_MODE_PRECISION (int_mode)
6599 - GET_MODE_PRECISION (inner_mode))))
6601 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6602 extend_op = SIGN_EXTEND;
6603 m = inner_mode;
6605 else if (GET_CODE (t) == SIGN_EXTEND
6606 && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6607 && (GET_CODE (XEXP (t, 0)) == PLUS
6608 || GET_CODE (XEXP (t, 0)) == IOR
6609 || GET_CODE (XEXP (t, 0)) == XOR)
6610 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6611 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6612 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6613 && (num_sign_bit_copies (f, GET_MODE (f))
6614 > (unsigned int)
6615 (GET_MODE_PRECISION (int_mode)
6616 - GET_MODE_PRECISION (inner_mode))))
6618 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6619 extend_op = SIGN_EXTEND;
6620 m = inner_mode;
6622 else if (GET_CODE (t) == ZERO_EXTEND
6623 && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6624 && (GET_CODE (XEXP (t, 0)) == PLUS
6625 || GET_CODE (XEXP (t, 0)) == MINUS
6626 || GET_CODE (XEXP (t, 0)) == IOR
6627 || GET_CODE (XEXP (t, 0)) == XOR
6628 || GET_CODE (XEXP (t, 0)) == ASHIFT
6629 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6630 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6631 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6632 && HWI_COMPUTABLE_MODE_P (int_mode)
6633 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6634 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6635 && ((nonzero_bits (f, GET_MODE (f))
6636 & ~GET_MODE_MASK (inner_mode))
6637 == 0))
6639 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6640 extend_op = ZERO_EXTEND;
6641 m = inner_mode;
6643 else if (GET_CODE (t) == ZERO_EXTEND
6644 && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6645 && (GET_CODE (XEXP (t, 0)) == PLUS
6646 || GET_CODE (XEXP (t, 0)) == IOR
6647 || GET_CODE (XEXP (t, 0)) == XOR)
6648 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6649 && HWI_COMPUTABLE_MODE_P (int_mode)
6650 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6651 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6652 && ((nonzero_bits (f, GET_MODE (f))
6653 & ~GET_MODE_MASK (inner_mode))
6654 == 0))
6656 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6657 extend_op = ZERO_EXTEND;
6658 m = inner_mode;
6661 if (z)
6663 machine_mode cm = m;
6664 if ((op == ASHIFT || op == LSHIFTRT || op == ASHIFTRT)
6665 && GET_MODE (c1) != VOIDmode)
6666 cm = GET_MODE (c1);
6667 temp = subst (simplify_gen_relational (true_code, cm, VOIDmode,
6668 cond_op0, cond_op1),
6669 pc_rtx, pc_rtx, 0, 0, 0);
6670 temp = simplify_gen_binary (MULT, cm, temp,
6671 simplify_gen_binary (MULT, cm, c1,
6672 const_true_rtx));
6673 temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6674 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6676 if (extend_op != UNKNOWN)
6677 temp = simplify_gen_unary (extend_op, int_mode, temp, m);
6679 return temp;
6683 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6684 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6685 negation of a single bit, we can convert this operation to a shift. We
6686 can actually do this more generally, but it doesn't seem worth it. */
6688 if (true_code == NE
6689 && is_a <scalar_int_mode> (mode, &int_mode)
6690 && XEXP (cond, 1) == const0_rtx
6691 && false_rtx == const0_rtx
6692 && CONST_INT_P (true_rtx)
6693 && ((nonzero_bits (XEXP (cond, 0), int_mode) == 1
6694 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6695 || ((num_sign_bit_copies (XEXP (cond, 0), int_mode)
6696 == GET_MODE_PRECISION (int_mode))
6697 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6698 return
6699 simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6700 gen_lowpart (int_mode, XEXP (cond, 0)), i);
6702 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6703 non-zero bit in A is C1. */
6704 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6705 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6706 && is_a <scalar_int_mode> (mode, &int_mode)
6707 && is_a <scalar_int_mode> (GET_MODE (XEXP (cond, 0)), &inner_mode)
6708 && (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))
6709 == nonzero_bits (XEXP (cond, 0), inner_mode)
6710 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))) >= 0)
6712 rtx val = XEXP (cond, 0);
6713 if (inner_mode == int_mode)
6714 return val;
6715 else if (GET_MODE_PRECISION (inner_mode) < GET_MODE_PRECISION (int_mode))
6716 return simplify_gen_unary (ZERO_EXTEND, int_mode, val, inner_mode);
6719 return x;
6722 /* Simplify X, a SET expression. Return the new expression. */
6724 static rtx
6725 simplify_set (rtx x)
6727 rtx src = SET_SRC (x);
6728 rtx dest = SET_DEST (x);
6729 machine_mode mode
6730 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6731 rtx_insn *other_insn;
6732 rtx *cc_use;
6733 scalar_int_mode int_mode;
6735 /* (set (pc) (return)) gets written as (return). */
6736 if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6737 return src;
6739 /* Now that we know for sure which bits of SRC we are using, see if we can
6740 simplify the expression for the object knowing that we only need the
6741 low-order bits. */
6743 if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6745 src = force_to_mode (src, mode, HOST_WIDE_INT_M1U, 0);
6746 SUBST (SET_SRC (x), src);
6749 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6750 the comparison result and try to simplify it unless we already have used
6751 undobuf.other_insn. */
6752 if ((GET_MODE_CLASS (mode) == MODE_CC
6753 || GET_CODE (src) == COMPARE
6754 || CC0_P (dest))
6755 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6756 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6757 && COMPARISON_P (*cc_use)
6758 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6760 enum rtx_code old_code = GET_CODE (*cc_use);
6761 enum rtx_code new_code;
6762 rtx op0, op1, tmp;
6763 int other_changed = 0;
6764 rtx inner_compare = NULL_RTX;
6765 machine_mode compare_mode = GET_MODE (dest);
6767 if (GET_CODE (src) == COMPARE)
6769 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6770 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6772 inner_compare = op0;
6773 op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6776 else
6777 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6779 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6780 op0, op1);
6781 if (!tmp)
6782 new_code = old_code;
6783 else if (!CONSTANT_P (tmp))
6785 new_code = GET_CODE (tmp);
6786 op0 = XEXP (tmp, 0);
6787 op1 = XEXP (tmp, 1);
6789 else
6791 rtx pat = PATTERN (other_insn);
6792 undobuf.other_insn = other_insn;
6793 SUBST (*cc_use, tmp);
6795 /* Attempt to simplify CC user. */
6796 if (GET_CODE (pat) == SET)
6798 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6799 if (new_rtx != NULL_RTX)
6800 SUBST (SET_SRC (pat), new_rtx);
6803 /* Convert X into a no-op move. */
6804 SUBST (SET_DEST (x), pc_rtx);
6805 SUBST (SET_SRC (x), pc_rtx);
6806 return x;
6809 /* Simplify our comparison, if possible. */
6810 new_code = simplify_comparison (new_code, &op0, &op1);
6812 #ifdef SELECT_CC_MODE
6813 /* If this machine has CC modes other than CCmode, check to see if we
6814 need to use a different CC mode here. */
6815 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6816 compare_mode = GET_MODE (op0);
6817 else if (inner_compare
6818 && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6819 && new_code == old_code
6820 && op0 == XEXP (inner_compare, 0)
6821 && op1 == XEXP (inner_compare, 1))
6822 compare_mode = GET_MODE (inner_compare);
6823 else
6824 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6826 /* If the mode changed, we have to change SET_DEST, the mode in the
6827 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6828 a hard register, just build new versions with the proper mode. If it
6829 is a pseudo, we lose unless it is only time we set the pseudo, in
6830 which case we can safely change its mode. */
6831 if (!HAVE_cc0 && compare_mode != GET_MODE (dest))
6833 if (can_change_dest_mode (dest, 0, compare_mode))
6835 unsigned int regno = REGNO (dest);
6836 rtx new_dest;
6838 if (regno < FIRST_PSEUDO_REGISTER)
6839 new_dest = gen_rtx_REG (compare_mode, regno);
6840 else
6842 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6843 new_dest = regno_reg_rtx[regno];
6846 SUBST (SET_DEST (x), new_dest);
6847 SUBST (XEXP (*cc_use, 0), new_dest);
6848 other_changed = 1;
6850 dest = new_dest;
6853 #endif /* SELECT_CC_MODE */
6855 /* If the code changed, we have to build a new comparison in
6856 undobuf.other_insn. */
6857 if (new_code != old_code)
6859 int other_changed_previously = other_changed;
6860 unsigned HOST_WIDE_INT mask;
6861 rtx old_cc_use = *cc_use;
6863 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6864 dest, const0_rtx));
6865 other_changed = 1;
6867 /* If the only change we made was to change an EQ into an NE or
6868 vice versa, OP0 has only one bit that might be nonzero, and OP1
6869 is zero, check if changing the user of the condition code will
6870 produce a valid insn. If it won't, we can keep the original code
6871 in that insn by surrounding our operation with an XOR. */
6873 if (((old_code == NE && new_code == EQ)
6874 || (old_code == EQ && new_code == NE))
6875 && ! other_changed_previously && op1 == const0_rtx
6876 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6877 && pow2p_hwi (mask = nonzero_bits (op0, GET_MODE (op0))))
6879 rtx pat = PATTERN (other_insn), note = 0;
6881 if ((recog_for_combine (&pat, other_insn, &note) < 0
6882 && ! check_asm_operands (pat)))
6884 *cc_use = old_cc_use;
6885 other_changed = 0;
6887 op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
6888 gen_int_mode (mask,
6889 GET_MODE (op0)));
6894 if (other_changed)
6895 undobuf.other_insn = other_insn;
6897 /* Don't generate a compare of a CC with 0, just use that CC. */
6898 if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6900 SUBST (SET_SRC (x), op0);
6901 src = SET_SRC (x);
6903 /* Otherwise, if we didn't previously have the same COMPARE we
6904 want, create it from scratch. */
6905 else if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode
6906 || XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6908 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6909 src = SET_SRC (x);
6912 else
6914 /* Get SET_SRC in a form where we have placed back any
6915 compound expressions. Then do the checks below. */
6916 src = make_compound_operation (src, SET);
6917 SUBST (SET_SRC (x), src);
6920 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6921 and X being a REG or (subreg (reg)), we may be able to convert this to
6922 (set (subreg:m2 x) (op)).
6924 We can always do this if M1 is narrower than M2 because that means that
6925 we only care about the low bits of the result.
6927 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6928 perform a narrower operation than requested since the high-order bits will
6929 be undefined. On machine where it is defined, this transformation is safe
6930 as long as M1 and M2 have the same number of words. */
6932 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6933 && !OBJECT_P (SUBREG_REG (src))
6934 && (known_equal_after_align_up
6935 (GET_MODE_SIZE (GET_MODE (src)),
6936 GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))),
6937 UNITS_PER_WORD))
6938 && (WORD_REGISTER_OPERATIONS || !paradoxical_subreg_p (src))
6939 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6940 && !REG_CAN_CHANGE_MODE_P (REGNO (dest),
6941 GET_MODE (SUBREG_REG (src)),
6942 GET_MODE (src)))
6943 && (REG_P (dest)
6944 || (GET_CODE (dest) == SUBREG
6945 && REG_P (SUBREG_REG (dest)))))
6947 SUBST (SET_DEST (x),
6948 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6949 dest));
6950 SUBST (SET_SRC (x), SUBREG_REG (src));
6952 src = SET_SRC (x), dest = SET_DEST (x);
6955 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6956 in SRC. */
6957 if (dest == cc0_rtx
6958 && partial_subreg_p (src)
6959 && subreg_lowpart_p (src))
6961 rtx inner = SUBREG_REG (src);
6962 machine_mode inner_mode = GET_MODE (inner);
6964 /* Here we make sure that we don't have a sign bit on. */
6965 if (val_signbit_known_clear_p (GET_MODE (src),
6966 nonzero_bits (inner, inner_mode)))
6968 SUBST (SET_SRC (x), inner);
6969 src = SET_SRC (x);
6973 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6974 would require a paradoxical subreg. Replace the subreg with a
6975 zero_extend to avoid the reload that would otherwise be required.
6976 Don't do this unless we have a scalar integer mode, otherwise the
6977 transformation is incorrect. */
6979 enum rtx_code extend_op;
6980 if (paradoxical_subreg_p (src)
6981 && MEM_P (SUBREG_REG (src))
6982 && SCALAR_INT_MODE_P (GET_MODE (src))
6983 && (extend_op = load_extend_op (GET_MODE (SUBREG_REG (src)))) != UNKNOWN)
6985 SUBST (SET_SRC (x),
6986 gen_rtx_fmt_e (extend_op, GET_MODE (src), SUBREG_REG (src)));
6988 src = SET_SRC (x);
6991 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6992 are comparing an item known to be 0 or -1 against 0, use a logical
6993 operation instead. Check for one of the arms being an IOR of the other
6994 arm with some value. We compute three terms to be IOR'ed together. In
6995 practice, at most two will be nonzero. Then we do the IOR's. */
6997 if (GET_CODE (dest) != PC
6998 && GET_CODE (src) == IF_THEN_ELSE
6999 && is_int_mode (GET_MODE (src), &int_mode)
7000 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
7001 && XEXP (XEXP (src, 0), 1) == const0_rtx
7002 && int_mode == GET_MODE (XEXP (XEXP (src, 0), 0))
7003 && (!HAVE_conditional_move
7004 || ! can_conditionally_move_p (int_mode))
7005 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), int_mode)
7006 == GET_MODE_PRECISION (int_mode))
7007 && ! side_effects_p (src))
7009 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
7010 ? XEXP (src, 1) : XEXP (src, 2));
7011 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
7012 ? XEXP (src, 2) : XEXP (src, 1));
7013 rtx term1 = const0_rtx, term2, term3;
7015 if (GET_CODE (true_rtx) == IOR
7016 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
7017 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
7018 else if (GET_CODE (true_rtx) == IOR
7019 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
7020 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
7021 else if (GET_CODE (false_rtx) == IOR
7022 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
7023 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
7024 else if (GET_CODE (false_rtx) == IOR
7025 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
7026 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
7028 term2 = simplify_gen_binary (AND, int_mode,
7029 XEXP (XEXP (src, 0), 0), true_rtx);
7030 term3 = simplify_gen_binary (AND, int_mode,
7031 simplify_gen_unary (NOT, int_mode,
7032 XEXP (XEXP (src, 0), 0),
7033 int_mode),
7034 false_rtx);
7036 SUBST (SET_SRC (x),
7037 simplify_gen_binary (IOR, int_mode,
7038 simplify_gen_binary (IOR, int_mode,
7039 term1, term2),
7040 term3));
7042 src = SET_SRC (x);
7045 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7046 whole thing fail. */
7047 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
7048 return src;
7049 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
7050 return dest;
7051 else
7052 /* Convert this into a field assignment operation, if possible. */
7053 return make_field_assignment (x);
7056 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7057 result. */
7059 static rtx
7060 simplify_logical (rtx x)
7062 rtx op0 = XEXP (x, 0);
7063 rtx op1 = XEXP (x, 1);
7064 scalar_int_mode mode;
7066 switch (GET_CODE (x))
7068 case AND:
7069 /* We can call simplify_and_const_int only if we don't lose
7070 any (sign) bits when converting INTVAL (op1) to
7071 "unsigned HOST_WIDE_INT". */
7072 if (is_a <scalar_int_mode> (GET_MODE (x), &mode)
7073 && CONST_INT_P (op1)
7074 && (HWI_COMPUTABLE_MODE_P (mode)
7075 || INTVAL (op1) > 0))
7077 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
7078 if (GET_CODE (x) != AND)
7079 return x;
7081 op0 = XEXP (x, 0);
7082 op1 = XEXP (x, 1);
7085 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7086 apply the distributive law and then the inverse distributive
7087 law to see if things simplify. */
7088 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
7090 rtx result = distribute_and_simplify_rtx (x, 0);
7091 if (result)
7092 return result;
7094 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
7096 rtx result = distribute_and_simplify_rtx (x, 1);
7097 if (result)
7098 return result;
7100 break;
7102 case IOR:
7103 /* If we have (ior (and A B) C), apply the distributive law and then
7104 the inverse distributive law to see if things simplify. */
7106 if (GET_CODE (op0) == AND)
7108 rtx result = distribute_and_simplify_rtx (x, 0);
7109 if (result)
7110 return result;
7113 if (GET_CODE (op1) == AND)
7115 rtx result = distribute_and_simplify_rtx (x, 1);
7116 if (result)
7117 return result;
7119 break;
7121 default:
7122 gcc_unreachable ();
7125 return x;
7128 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7129 operations" because they can be replaced with two more basic operations.
7130 ZERO_EXTEND is also considered "compound" because it can be replaced with
7131 an AND operation, which is simpler, though only one operation.
7133 The function expand_compound_operation is called with an rtx expression
7134 and will convert it to the appropriate shifts and AND operations,
7135 simplifying at each stage.
7137 The function make_compound_operation is called to convert an expression
7138 consisting of shifts and ANDs into the equivalent compound expression.
7139 It is the inverse of this function, loosely speaking. */
7141 static rtx
7142 expand_compound_operation (rtx x)
7144 unsigned HOST_WIDE_INT pos = 0, len;
7145 int unsignedp = 0;
7146 unsigned int modewidth;
7147 rtx tem;
7148 scalar_int_mode inner_mode;
7150 switch (GET_CODE (x))
7152 case ZERO_EXTEND:
7153 unsignedp = 1;
7154 /* FALLTHRU */
7155 case SIGN_EXTEND:
7156 /* We can't necessarily use a const_int for a multiword mode;
7157 it depends on implicitly extending the value.
7158 Since we don't know the right way to extend it,
7159 we can't tell whether the implicit way is right.
7161 Even for a mode that is no wider than a const_int,
7162 we can't win, because we need to sign extend one of its bits through
7163 the rest of it, and we don't know which bit. */
7164 if (CONST_INT_P (XEXP (x, 0)))
7165 return x;
7167 /* Reject modes that aren't scalar integers because turning vector
7168 or complex modes into shifts causes problems. */
7169 if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode))
7170 return x;
7172 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7173 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7174 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7175 reloaded. If not for that, MEM's would very rarely be safe.
7177 Reject modes bigger than a word, because we might not be able
7178 to reference a two-register group starting with an arbitrary register
7179 (and currently gen_lowpart might crash for a SUBREG). */
7181 if (GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7182 return x;
7184 len = GET_MODE_PRECISION (inner_mode);
7185 /* If the inner object has VOIDmode (the only way this can happen
7186 is if it is an ASM_OPERANDS), we can't do anything since we don't
7187 know how much masking to do. */
7188 if (len == 0)
7189 return x;
7191 break;
7193 case ZERO_EXTRACT:
7194 unsignedp = 1;
7196 /* fall through */
7198 case SIGN_EXTRACT:
7199 /* If the operand is a CLOBBER, just return it. */
7200 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
7201 return XEXP (x, 0);
7203 if (!CONST_INT_P (XEXP (x, 1))
7204 || !CONST_INT_P (XEXP (x, 2)))
7205 return x;
7207 /* Reject modes that aren't scalar integers because turning vector
7208 or complex modes into shifts causes problems. */
7209 if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode))
7210 return x;
7212 len = INTVAL (XEXP (x, 1));
7213 pos = INTVAL (XEXP (x, 2));
7215 /* This should stay within the object being extracted, fail otherwise. */
7216 if (len + pos > GET_MODE_PRECISION (inner_mode))
7217 return x;
7219 if (BITS_BIG_ENDIAN)
7220 pos = GET_MODE_PRECISION (inner_mode) - len - pos;
7222 break;
7224 default:
7225 return x;
7228 /* We've rejected non-scalar operations by now. */
7229 scalar_int_mode mode = as_a <scalar_int_mode> (GET_MODE (x));
7231 /* Convert sign extension to zero extension, if we know that the high
7232 bit is not set, as this is easier to optimize. It will be converted
7233 back to cheaper alternative in make_extraction. */
7234 if (GET_CODE (x) == SIGN_EXTEND
7235 && HWI_COMPUTABLE_MODE_P (mode)
7236 && ((nonzero_bits (XEXP (x, 0), inner_mode)
7237 & ~(((unsigned HOST_WIDE_INT) GET_MODE_MASK (inner_mode)) >> 1))
7238 == 0))
7240 rtx temp = gen_rtx_ZERO_EXTEND (mode, XEXP (x, 0));
7241 rtx temp2 = expand_compound_operation (temp);
7243 /* Make sure this is a profitable operation. */
7244 if (set_src_cost (x, mode, optimize_this_for_speed_p)
7245 > set_src_cost (temp2, mode, optimize_this_for_speed_p))
7246 return temp2;
7247 else if (set_src_cost (x, mode, optimize_this_for_speed_p)
7248 > set_src_cost (temp, mode, optimize_this_for_speed_p))
7249 return temp;
7250 else
7251 return x;
7254 /* We can optimize some special cases of ZERO_EXTEND. */
7255 if (GET_CODE (x) == ZERO_EXTEND)
7257 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7258 know that the last value didn't have any inappropriate bits
7259 set. */
7260 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7261 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7262 && HWI_COMPUTABLE_MODE_P (mode)
7263 && (nonzero_bits (XEXP (XEXP (x, 0), 0), mode)
7264 & ~GET_MODE_MASK (inner_mode)) == 0)
7265 return XEXP (XEXP (x, 0), 0);
7267 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7268 if (GET_CODE (XEXP (x, 0)) == SUBREG
7269 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7270 && subreg_lowpart_p (XEXP (x, 0))
7271 && HWI_COMPUTABLE_MODE_P (mode)
7272 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), mode)
7273 & ~GET_MODE_MASK (inner_mode)) == 0)
7274 return SUBREG_REG (XEXP (x, 0));
7276 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7277 is a comparison and STORE_FLAG_VALUE permits. This is like
7278 the first case, but it works even when MODE is larger
7279 than HOST_WIDE_INT. */
7280 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7281 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7282 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
7283 && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
7284 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7285 return XEXP (XEXP (x, 0), 0);
7287 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7288 if (GET_CODE (XEXP (x, 0)) == SUBREG
7289 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7290 && subreg_lowpart_p (XEXP (x, 0))
7291 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
7292 && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
7293 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7294 return SUBREG_REG (XEXP (x, 0));
7298 /* If we reach here, we want to return a pair of shifts. The inner
7299 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7300 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7301 logical depending on the value of UNSIGNEDP.
7303 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7304 converted into an AND of a shift.
7306 We must check for the case where the left shift would have a negative
7307 count. This can happen in a case like (x >> 31) & 255 on machines
7308 that can't shift by a constant. On those machines, we would first
7309 combine the shift with the AND to produce a variable-position
7310 extraction. Then the constant of 31 would be substituted in
7311 to produce such a position. */
7313 modewidth = GET_MODE_PRECISION (mode);
7314 if (modewidth >= pos + len)
7316 tem = gen_lowpart (mode, XEXP (x, 0));
7317 if (!tem || GET_CODE (tem) == CLOBBER)
7318 return x;
7319 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
7320 tem, modewidth - pos - len);
7321 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
7322 mode, tem, modewidth - len);
7324 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
7325 tem = simplify_and_const_int (NULL_RTX, mode,
7326 simplify_shift_const (NULL_RTX, LSHIFTRT,
7327 mode, XEXP (x, 0),
7328 pos),
7329 (HOST_WIDE_INT_1U << len) - 1);
7330 else
7331 /* Any other cases we can't handle. */
7332 return x;
7334 /* If we couldn't do this for some reason, return the original
7335 expression. */
7336 if (GET_CODE (tem) == CLOBBER)
7337 return x;
7339 return tem;
7342 /* X is a SET which contains an assignment of one object into
7343 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7344 or certain SUBREGS). If possible, convert it into a series of
7345 logical operations.
7347 We half-heartedly support variable positions, but do not at all
7348 support variable lengths. */
7350 static const_rtx
7351 expand_field_assignment (const_rtx x)
7353 rtx inner;
7354 rtx pos; /* Always counts from low bit. */
7355 int len, inner_len;
7356 rtx mask, cleared, masked;
7357 scalar_int_mode compute_mode;
7359 /* Loop until we find something we can't simplify. */
7360 while (1)
7362 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
7363 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
7365 rtx x0 = XEXP (SET_DEST (x), 0);
7366 if (!GET_MODE_PRECISION (GET_MODE (x0)).is_constant (&len))
7367 break;
7368 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
7369 pos = gen_int_mode (subreg_lsb (XEXP (SET_DEST (x), 0)),
7370 MAX_MODE_INT);
7372 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
7373 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
7375 inner = XEXP (SET_DEST (x), 0);
7376 if (!GET_MODE_PRECISION (GET_MODE (inner)).is_constant (&inner_len))
7377 break;
7379 len = INTVAL (XEXP (SET_DEST (x), 1));
7380 pos = XEXP (SET_DEST (x), 2);
7382 /* A constant position should stay within the width of INNER. */
7383 if (CONST_INT_P (pos) && INTVAL (pos) + len > inner_len)
7384 break;
7386 if (BITS_BIG_ENDIAN)
7388 if (CONST_INT_P (pos))
7389 pos = GEN_INT (inner_len - len - INTVAL (pos));
7390 else if (GET_CODE (pos) == MINUS
7391 && CONST_INT_P (XEXP (pos, 1))
7392 && INTVAL (XEXP (pos, 1)) == inner_len - len)
7393 /* If position is ADJUST - X, new position is X. */
7394 pos = XEXP (pos, 0);
7395 else
7396 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
7397 gen_int_mode (inner_len - len,
7398 GET_MODE (pos)),
7399 pos);
7403 /* If the destination is a subreg that overwrites the whole of the inner
7404 register, we can move the subreg to the source. */
7405 else if (GET_CODE (SET_DEST (x)) == SUBREG
7406 /* We need SUBREGs to compute nonzero_bits properly. */
7407 && nonzero_sign_valid
7408 && !read_modify_subreg_p (SET_DEST (x)))
7410 x = gen_rtx_SET (SUBREG_REG (SET_DEST (x)),
7411 gen_lowpart
7412 (GET_MODE (SUBREG_REG (SET_DEST (x))),
7413 SET_SRC (x)));
7414 continue;
7416 else
7417 break;
7419 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7420 inner = SUBREG_REG (inner);
7422 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7423 if (!is_a <scalar_int_mode> (GET_MODE (inner), &compute_mode))
7425 /* Don't do anything for vector or complex integral types. */
7426 if (! FLOAT_MODE_P (GET_MODE (inner)))
7427 break;
7429 /* Try to find an integral mode to pun with. */
7430 if (!int_mode_for_size (GET_MODE_BITSIZE (GET_MODE (inner)), 0)
7431 .exists (&compute_mode))
7432 break;
7434 inner = gen_lowpart (compute_mode, inner);
7437 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7438 if (len >= HOST_BITS_PER_WIDE_INT)
7439 break;
7441 /* Don't try to compute in too wide unsupported modes. */
7442 if (!targetm.scalar_mode_supported_p (compute_mode))
7443 break;
7445 /* Now compute the equivalent expression. Make a copy of INNER
7446 for the SET_DEST in case it is a MEM into which we will substitute;
7447 we don't want shared RTL in that case. */
7448 mask = gen_int_mode ((HOST_WIDE_INT_1U << len) - 1,
7449 compute_mode);
7450 cleared = simplify_gen_binary (AND, compute_mode,
7451 simplify_gen_unary (NOT, compute_mode,
7452 simplify_gen_binary (ASHIFT,
7453 compute_mode,
7454 mask, pos),
7455 compute_mode),
7456 inner);
7457 masked = simplify_gen_binary (ASHIFT, compute_mode,
7458 simplify_gen_binary (
7459 AND, compute_mode,
7460 gen_lowpart (compute_mode, SET_SRC (x)),
7461 mask),
7462 pos);
7464 x = gen_rtx_SET (copy_rtx (inner),
7465 simplify_gen_binary (IOR, compute_mode,
7466 cleared, masked));
7469 return x;
7472 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7473 it is an RTX that represents the (variable) starting position; otherwise,
7474 POS is the (constant) starting bit position. Both are counted from the LSB.
7476 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7478 IN_DEST is nonzero if this is a reference in the destination of a SET.
7479 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7480 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7481 be used.
7483 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7484 ZERO_EXTRACT should be built even for bits starting at bit 0.
7486 MODE is the desired mode of the result (if IN_DEST == 0).
7488 The result is an RTX for the extraction or NULL_RTX if the target
7489 can't handle it. */
7491 static rtx
7492 make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7493 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7494 int in_dest, int in_compare)
7496 /* This mode describes the size of the storage area
7497 to fetch the overall value from. Within that, we
7498 ignore the POS lowest bits, etc. */
7499 machine_mode is_mode = GET_MODE (inner);
7500 machine_mode inner_mode;
7501 scalar_int_mode wanted_inner_mode;
7502 scalar_int_mode wanted_inner_reg_mode = word_mode;
7503 scalar_int_mode pos_mode = word_mode;
7504 machine_mode extraction_mode = word_mode;
7505 rtx new_rtx = 0;
7506 rtx orig_pos_rtx = pos_rtx;
7507 HOST_WIDE_INT orig_pos;
7509 if (pos_rtx && CONST_INT_P (pos_rtx))
7510 pos = INTVAL (pos_rtx), pos_rtx = 0;
7512 if (GET_CODE (inner) == SUBREG
7513 && subreg_lowpart_p (inner)
7514 && (paradoxical_subreg_p (inner)
7515 /* If trying or potentionally trying to extract
7516 bits outside of is_mode, don't look through
7517 non-paradoxical SUBREGs. See PR82192. */
7518 || (pos_rtx == NULL_RTX
7519 && known_le (pos + len, GET_MODE_PRECISION (is_mode)))))
7521 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7522 consider just the QI as the memory to extract from.
7523 The subreg adds or removes high bits; its mode is
7524 irrelevant to the meaning of this extraction,
7525 since POS and LEN count from the lsb. */
7526 if (MEM_P (SUBREG_REG (inner)))
7527 is_mode = GET_MODE (SUBREG_REG (inner));
7528 inner = SUBREG_REG (inner);
7530 else if (GET_CODE (inner) == ASHIFT
7531 && CONST_INT_P (XEXP (inner, 1))
7532 && pos_rtx == 0 && pos == 0
7533 && len > UINTVAL (XEXP (inner, 1)))
7535 /* We're extracting the least significant bits of an rtx
7536 (ashift X (const_int C)), where LEN > C. Extract the
7537 least significant (LEN - C) bits of X, giving an rtx
7538 whose mode is MODE, then shift it left C times. */
7539 new_rtx = make_extraction (mode, XEXP (inner, 0),
7540 0, 0, len - INTVAL (XEXP (inner, 1)),
7541 unsignedp, in_dest, in_compare);
7542 if (new_rtx != 0)
7543 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7545 else if (GET_CODE (inner) == TRUNCATE
7546 /* If trying or potentionally trying to extract
7547 bits outside of is_mode, don't look through
7548 TRUNCATE. See PR82192. */
7549 && pos_rtx == NULL_RTX
7550 && known_le (pos + len, GET_MODE_PRECISION (is_mode)))
7551 inner = XEXP (inner, 0);
7553 inner_mode = GET_MODE (inner);
7555 /* See if this can be done without an extraction. We never can if the
7556 width of the field is not the same as that of some integer mode. For
7557 registers, we can only avoid the extraction if the position is at the
7558 low-order bit and this is either not in the destination or we have the
7559 appropriate STRICT_LOW_PART operation available.
7561 For MEM, we can avoid an extract if the field starts on an appropriate
7562 boundary and we can change the mode of the memory reference. */
7564 scalar_int_mode tmode;
7565 if (int_mode_for_size (len, 1).exists (&tmode)
7566 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7567 && !MEM_P (inner)
7568 && (pos == 0 || REG_P (inner))
7569 && (inner_mode == tmode
7570 || !REG_P (inner)
7571 || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7572 || reg_truncated_to_mode (tmode, inner))
7573 && (! in_dest
7574 || (REG_P (inner)
7575 && have_insn_for (STRICT_LOW_PART, tmode))))
7576 || (MEM_P (inner) && pos_rtx == 0
7577 && (pos
7578 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7579 : BITS_PER_UNIT)) == 0
7580 /* We can't do this if we are widening INNER_MODE (it
7581 may not be aligned, for one thing). */
7582 && !paradoxical_subreg_p (tmode, inner_mode)
7583 && (inner_mode == tmode
7584 || (! mode_dependent_address_p (XEXP (inner, 0),
7585 MEM_ADDR_SPACE (inner))
7586 && ! MEM_VOLATILE_P (inner))))))
7588 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7589 field. If the original and current mode are the same, we need not
7590 adjust the offset. Otherwise, we do if bytes big endian.
7592 If INNER is not a MEM, get a piece consisting of just the field
7593 of interest (in this case POS % BITS_PER_WORD must be 0). */
7595 if (MEM_P (inner))
7597 poly_int64 offset;
7599 /* POS counts from lsb, but make OFFSET count in memory order. */
7600 if (BYTES_BIG_ENDIAN)
7601 offset = bits_to_bytes_round_down (GET_MODE_PRECISION (is_mode)
7602 - len - pos);
7603 else
7604 offset = pos / BITS_PER_UNIT;
7606 new_rtx = adjust_address_nv (inner, tmode, offset);
7608 else if (REG_P (inner))
7610 if (tmode != inner_mode)
7612 /* We can't call gen_lowpart in a DEST since we
7613 always want a SUBREG (see below) and it would sometimes
7614 return a new hard register. */
7615 if (pos || in_dest)
7617 poly_uint64 offset
7618 = subreg_offset_from_lsb (tmode, inner_mode, pos);
7620 /* Avoid creating invalid subregs, for example when
7621 simplifying (x>>32)&255. */
7622 if (!validate_subreg (tmode, inner_mode, inner, offset))
7623 return NULL_RTX;
7625 new_rtx = gen_rtx_SUBREG (tmode, inner, offset);
7627 else
7628 new_rtx = gen_lowpart (tmode, inner);
7630 else
7631 new_rtx = inner;
7633 else
7634 new_rtx = force_to_mode (inner, tmode,
7635 len >= HOST_BITS_PER_WIDE_INT
7636 ? HOST_WIDE_INT_M1U
7637 : (HOST_WIDE_INT_1U << len) - 1, 0);
7639 /* If this extraction is going into the destination of a SET,
7640 make a STRICT_LOW_PART unless we made a MEM. */
7642 if (in_dest)
7643 return (MEM_P (new_rtx) ? new_rtx
7644 : (GET_CODE (new_rtx) != SUBREG
7645 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7646 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7648 if (mode == tmode)
7649 return new_rtx;
7651 if (CONST_SCALAR_INT_P (new_rtx))
7652 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7653 mode, new_rtx, tmode);
7655 /* If we know that no extraneous bits are set, and that the high
7656 bit is not set, convert the extraction to the cheaper of
7657 sign and zero extension, that are equivalent in these cases. */
7658 if (flag_expensive_optimizations
7659 && (HWI_COMPUTABLE_MODE_P (tmode)
7660 && ((nonzero_bits (new_rtx, tmode)
7661 & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7662 == 0)))
7664 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7665 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7667 /* Prefer ZERO_EXTENSION, since it gives more information to
7668 backends. */
7669 if (set_src_cost (temp, mode, optimize_this_for_speed_p)
7670 <= set_src_cost (temp1, mode, optimize_this_for_speed_p))
7671 return temp;
7672 return temp1;
7675 /* Otherwise, sign- or zero-extend unless we already are in the
7676 proper mode. */
7678 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7679 mode, new_rtx));
7682 /* Unless this is a COMPARE or we have a funny memory reference,
7683 don't do anything with zero-extending field extracts starting at
7684 the low-order bit since they are simple AND operations. */
7685 if (pos_rtx == 0 && pos == 0 && ! in_dest
7686 && ! in_compare && unsignedp)
7687 return 0;
7689 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7690 if the position is not a constant and the length is not 1. In all
7691 other cases, we would only be going outside our object in cases when
7692 an original shift would have been undefined. */
7693 if (MEM_P (inner)
7694 && ((pos_rtx == 0 && maybe_gt (pos + len, GET_MODE_PRECISION (is_mode)))
7695 || (pos_rtx != 0 && len != 1)))
7696 return 0;
7698 enum extraction_pattern pattern = (in_dest ? EP_insv
7699 : unsignedp ? EP_extzv : EP_extv);
7701 /* If INNER is not from memory, we want it to have the mode of a register
7702 extraction pattern's structure operand, or word_mode if there is no
7703 such pattern. The same applies to extraction_mode and pos_mode
7704 and their respective operands.
7706 For memory, assume that the desired extraction_mode and pos_mode
7707 are the same as for a register operation, since at present we don't
7708 have named patterns for aligned memory structures. */
7709 struct extraction_insn insn;
7710 unsigned int inner_size;
7711 if (GET_MODE_BITSIZE (inner_mode).is_constant (&inner_size)
7712 && get_best_reg_extraction_insn (&insn, pattern, inner_size, mode))
7714 wanted_inner_reg_mode = insn.struct_mode.require ();
7715 pos_mode = insn.pos_mode;
7716 extraction_mode = insn.field_mode;
7719 /* Never narrow an object, since that might not be safe. */
7721 if (mode != VOIDmode
7722 && partial_subreg_p (extraction_mode, mode))
7723 extraction_mode = mode;
7725 if (!MEM_P (inner))
7726 wanted_inner_mode = wanted_inner_reg_mode;
7727 else
7729 /* Be careful not to go beyond the extracted object and maintain the
7730 natural alignment of the memory. */
7731 wanted_inner_mode = smallest_int_mode_for_size (len);
7732 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7733 > GET_MODE_BITSIZE (wanted_inner_mode))
7734 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode).require ();
7737 orig_pos = pos;
7739 if (BITS_BIG_ENDIAN)
7741 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7742 BITS_BIG_ENDIAN style. If position is constant, compute new
7743 position. Otherwise, build subtraction.
7744 Note that POS is relative to the mode of the original argument.
7745 If it's a MEM we need to recompute POS relative to that.
7746 However, if we're extracting from (or inserting into) a register,
7747 we want to recompute POS relative to wanted_inner_mode. */
7748 int width;
7749 if (!MEM_P (inner))
7750 width = GET_MODE_BITSIZE (wanted_inner_mode);
7751 else if (!GET_MODE_BITSIZE (is_mode).is_constant (&width))
7752 return NULL_RTX;
7754 if (pos_rtx == 0)
7755 pos = width - len - pos;
7756 else
7757 pos_rtx
7758 = gen_rtx_MINUS (GET_MODE (pos_rtx),
7759 gen_int_mode (width - len, GET_MODE (pos_rtx)),
7760 pos_rtx);
7761 /* POS may be less than 0 now, but we check for that below.
7762 Note that it can only be less than 0 if !MEM_P (inner). */
7765 /* If INNER has a wider mode, and this is a constant extraction, try to
7766 make it smaller and adjust the byte to point to the byte containing
7767 the value. */
7768 if (wanted_inner_mode != VOIDmode
7769 && inner_mode != wanted_inner_mode
7770 && ! pos_rtx
7771 && partial_subreg_p (wanted_inner_mode, is_mode)
7772 && MEM_P (inner)
7773 && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7774 && ! MEM_VOLATILE_P (inner))
7776 poly_int64 offset = 0;
7778 /* The computations below will be correct if the machine is big
7779 endian in both bits and bytes or little endian in bits and bytes.
7780 If it is mixed, we must adjust. */
7782 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7783 adjust OFFSET to compensate. */
7784 if (BYTES_BIG_ENDIAN
7785 && paradoxical_subreg_p (is_mode, inner_mode))
7786 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7788 /* We can now move to the desired byte. */
7789 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7790 * GET_MODE_SIZE (wanted_inner_mode);
7791 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7793 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7794 && is_mode != wanted_inner_mode)
7795 offset = (GET_MODE_SIZE (is_mode)
7796 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7798 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7801 /* If INNER is not memory, get it into the proper mode. If we are changing
7802 its mode, POS must be a constant and smaller than the size of the new
7803 mode. */
7804 else if (!MEM_P (inner))
7806 /* On the LHS, don't create paradoxical subregs implicitely truncating
7807 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7808 if (in_dest
7809 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7810 wanted_inner_mode))
7811 return NULL_RTX;
7813 if (GET_MODE (inner) != wanted_inner_mode
7814 && (pos_rtx != 0
7815 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7816 return NULL_RTX;
7818 if (orig_pos < 0)
7819 return NULL_RTX;
7821 inner = force_to_mode (inner, wanted_inner_mode,
7822 pos_rtx
7823 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7824 ? HOST_WIDE_INT_M1U
7825 : (((HOST_WIDE_INT_1U << len) - 1)
7826 << orig_pos),
7830 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7831 have to zero extend. Otherwise, we can just use a SUBREG.
7833 We dealt with constant rtxes earlier, so pos_rtx cannot
7834 have VOIDmode at this point. */
7835 if (pos_rtx != 0
7836 && (GET_MODE_SIZE (pos_mode)
7837 > GET_MODE_SIZE (as_a <scalar_int_mode> (GET_MODE (pos_rtx)))))
7839 rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7840 GET_MODE (pos_rtx));
7842 /* If we know that no extraneous bits are set, and that the high
7843 bit is not set, convert extraction to cheaper one - either
7844 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7845 cases. */
7846 if (flag_expensive_optimizations
7847 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7848 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7849 & ~(((unsigned HOST_WIDE_INT)
7850 GET_MODE_MASK (GET_MODE (pos_rtx)))
7851 >> 1))
7852 == 0)))
7854 rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7855 GET_MODE (pos_rtx));
7857 /* Prefer ZERO_EXTENSION, since it gives more information to
7858 backends. */
7859 if (set_src_cost (temp1, pos_mode, optimize_this_for_speed_p)
7860 < set_src_cost (temp, pos_mode, optimize_this_for_speed_p))
7861 temp = temp1;
7863 pos_rtx = temp;
7866 /* Make POS_RTX unless we already have it and it is correct. If we don't
7867 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7868 be a CONST_INT. */
7869 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7870 pos_rtx = orig_pos_rtx;
7872 else if (pos_rtx == 0)
7873 pos_rtx = GEN_INT (pos);
7875 /* Make the required operation. See if we can use existing rtx. */
7876 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7877 extraction_mode, inner, GEN_INT (len), pos_rtx);
7878 if (! in_dest)
7879 new_rtx = gen_lowpart (mode, new_rtx);
7881 return new_rtx;
7884 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7885 can be commuted with any other operations in X. Return X without
7886 that shift if so. */
7888 static rtx
7889 extract_left_shift (scalar_int_mode mode, rtx x, int count)
7891 enum rtx_code code = GET_CODE (x);
7892 rtx tem;
7894 switch (code)
7896 case ASHIFT:
7897 /* This is the shift itself. If it is wide enough, we will return
7898 either the value being shifted if the shift count is equal to
7899 COUNT or a shift for the difference. */
7900 if (CONST_INT_P (XEXP (x, 1))
7901 && INTVAL (XEXP (x, 1)) >= count)
7902 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7903 INTVAL (XEXP (x, 1)) - count);
7904 break;
7906 case NEG: case NOT:
7907 if ((tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
7908 return simplify_gen_unary (code, mode, tem, mode);
7910 break;
7912 case PLUS: case IOR: case XOR: case AND:
7913 /* If we can safely shift this constant and we find the inner shift,
7914 make a new operation. */
7915 if (CONST_INT_P (XEXP (x, 1))
7916 && (UINTVAL (XEXP (x, 1))
7917 & (((HOST_WIDE_INT_1U << count)) - 1)) == 0
7918 && (tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
7920 HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
7921 return simplify_gen_binary (code, mode, tem,
7922 gen_int_mode (val, mode));
7924 break;
7926 default:
7927 break;
7930 return 0;
7933 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7934 level of the expression and MODE is its mode. IN_CODE is as for
7935 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7936 that should be used when recursing on operands of *X_PTR.
7938 There are two possible actions:
7940 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7941 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7943 - Return a new rtx, which the caller returns directly. */
7945 static rtx
7946 make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
7947 enum rtx_code in_code,
7948 enum rtx_code *next_code_ptr)
7950 rtx x = *x_ptr;
7951 enum rtx_code next_code = *next_code_ptr;
7952 enum rtx_code code = GET_CODE (x);
7953 int mode_width = GET_MODE_PRECISION (mode);
7954 rtx rhs, lhs;
7955 rtx new_rtx = 0;
7956 int i;
7957 rtx tem;
7958 scalar_int_mode inner_mode;
7959 bool equality_comparison = false;
7961 if (in_code == EQ)
7963 equality_comparison = true;
7964 in_code = COMPARE;
7967 /* Process depending on the code of this operation. If NEW is set
7968 nonzero, it will be returned. */
7970 switch (code)
7972 case ASHIFT:
7973 /* Convert shifts by constants into multiplications if inside
7974 an address. */
7975 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7976 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7977 && INTVAL (XEXP (x, 1)) >= 0)
7979 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7980 HOST_WIDE_INT multval = HOST_WIDE_INT_1 << count;
7982 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7983 if (GET_CODE (new_rtx) == NEG)
7985 new_rtx = XEXP (new_rtx, 0);
7986 multval = -multval;
7988 multval = trunc_int_for_mode (multval, mode);
7989 new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
7991 break;
7993 case PLUS:
7994 lhs = XEXP (x, 0);
7995 rhs = XEXP (x, 1);
7996 lhs = make_compound_operation (lhs, next_code);
7997 rhs = make_compound_operation (rhs, next_code);
7998 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG)
8000 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
8001 XEXP (lhs, 1));
8002 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
8004 else if (GET_CODE (lhs) == MULT
8005 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
8007 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
8008 simplify_gen_unary (NEG, mode,
8009 XEXP (lhs, 1),
8010 mode));
8011 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
8013 else
8015 SUBST (XEXP (x, 0), lhs);
8016 SUBST (XEXP (x, 1), rhs);
8018 maybe_swap_commutative_operands (x);
8019 return x;
8021 case MINUS:
8022 lhs = XEXP (x, 0);
8023 rhs = XEXP (x, 1);
8024 lhs = make_compound_operation (lhs, next_code);
8025 rhs = make_compound_operation (rhs, next_code);
8026 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG)
8028 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
8029 XEXP (rhs, 1));
8030 return simplify_gen_binary (PLUS, mode, tem, lhs);
8032 else if (GET_CODE (rhs) == MULT
8033 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
8035 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
8036 simplify_gen_unary (NEG, mode,
8037 XEXP (rhs, 1),
8038 mode));
8039 return simplify_gen_binary (PLUS, mode, tem, lhs);
8041 else
8043 SUBST (XEXP (x, 0), lhs);
8044 SUBST (XEXP (x, 1), rhs);
8045 return x;
8048 case AND:
8049 /* If the second operand is not a constant, we can't do anything
8050 with it. */
8051 if (!CONST_INT_P (XEXP (x, 1)))
8052 break;
8054 /* If the constant is a power of two minus one and the first operand
8055 is a logical right shift, make an extraction. */
8056 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8057 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8059 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8060 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1),
8061 i, 1, 0, in_code == COMPARE);
8064 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8065 else if (GET_CODE (XEXP (x, 0)) == SUBREG
8066 && subreg_lowpart_p (XEXP (x, 0))
8067 && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (XEXP (x, 0))),
8068 &inner_mode)
8069 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
8070 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8072 rtx inner_x0 = SUBREG_REG (XEXP (x, 0));
8073 new_rtx = make_compound_operation (XEXP (inner_x0, 0), next_code);
8074 new_rtx = make_extraction (inner_mode, new_rtx, 0,
8075 XEXP (inner_x0, 1),
8076 i, 1, 0, in_code == COMPARE);
8078 /* If we narrowed the mode when dropping the subreg, then we lose. */
8079 if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode))
8080 new_rtx = NULL;
8082 /* If that didn't give anything, see if the AND simplifies on
8083 its own. */
8084 if (!new_rtx && i >= 0)
8086 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8087 new_rtx = make_extraction (mode, new_rtx, 0, NULL_RTX, i, 1,
8088 0, in_code == COMPARE);
8091 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8092 else if ((GET_CODE (XEXP (x, 0)) == XOR
8093 || GET_CODE (XEXP (x, 0)) == IOR)
8094 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
8095 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
8096 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8098 /* Apply the distributive law, and then try to make extractions. */
8099 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
8100 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
8101 XEXP (x, 1)),
8102 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
8103 XEXP (x, 1)));
8104 new_rtx = make_compound_operation (new_rtx, in_code);
8107 /* If we are have (and (rotate X C) M) and C is larger than the number
8108 of bits in M, this is an extraction. */
8110 else if (GET_CODE (XEXP (x, 0)) == ROTATE
8111 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8112 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
8113 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
8115 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8116 new_rtx = make_extraction (mode, new_rtx,
8117 (GET_MODE_PRECISION (mode)
8118 - INTVAL (XEXP (XEXP (x, 0), 1))),
8119 NULL_RTX, i, 1, 0, in_code == COMPARE);
8122 /* On machines without logical shifts, if the operand of the AND is
8123 a logical shift and our mask turns off all the propagated sign
8124 bits, we can replace the logical shift with an arithmetic shift. */
8125 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8126 && !have_insn_for (LSHIFTRT, mode)
8127 && have_insn_for (ASHIFTRT, mode)
8128 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8129 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8130 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8131 && mode_width <= HOST_BITS_PER_WIDE_INT)
8133 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8135 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
8136 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
8137 SUBST (XEXP (x, 0),
8138 gen_rtx_ASHIFTRT (mode,
8139 make_compound_operation (XEXP (XEXP (x,
8142 next_code),
8143 XEXP (XEXP (x, 0), 1)));
8146 /* If the constant is one less than a power of two, this might be
8147 representable by an extraction even if no shift is present.
8148 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8149 we are in a COMPARE. */
8150 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8151 new_rtx = make_extraction (mode,
8152 make_compound_operation (XEXP (x, 0),
8153 next_code),
8154 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
8156 /* If we are in a comparison and this is an AND with a power of two,
8157 convert this into the appropriate bit extract. */
8158 else if (in_code == COMPARE
8159 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
8160 && (equality_comparison || i < GET_MODE_PRECISION (mode) - 1))
8161 new_rtx = make_extraction (mode,
8162 make_compound_operation (XEXP (x, 0),
8163 next_code),
8164 i, NULL_RTX, 1, 1, 0, 1);
8166 /* If the one operand is a paradoxical subreg of a register or memory and
8167 the constant (limited to the smaller mode) has only zero bits where
8168 the sub expression has known zero bits, this can be expressed as
8169 a zero_extend. */
8170 else if (GET_CODE (XEXP (x, 0)) == SUBREG)
8172 rtx sub;
8174 sub = XEXP (XEXP (x, 0), 0);
8175 machine_mode sub_mode = GET_MODE (sub);
8176 int sub_width;
8177 if ((REG_P (sub) || MEM_P (sub))
8178 && GET_MODE_PRECISION (sub_mode).is_constant (&sub_width)
8179 && sub_width < mode_width)
8181 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (sub_mode);
8182 unsigned HOST_WIDE_INT mask;
8184 /* original AND constant with all the known zero bits set */
8185 mask = UINTVAL (XEXP (x, 1)) | (~nonzero_bits (sub, sub_mode));
8186 if ((mask & mode_mask) == mode_mask)
8188 new_rtx = make_compound_operation (sub, next_code);
8189 new_rtx = make_extraction (mode, new_rtx, 0, 0, sub_width,
8190 1, 0, in_code == COMPARE);
8195 break;
8197 case LSHIFTRT:
8198 /* If the sign bit is known to be zero, replace this with an
8199 arithmetic shift. */
8200 if (have_insn_for (ASHIFTRT, mode)
8201 && ! have_insn_for (LSHIFTRT, mode)
8202 && mode_width <= HOST_BITS_PER_WIDE_INT
8203 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
8205 new_rtx = gen_rtx_ASHIFTRT (mode,
8206 make_compound_operation (XEXP (x, 0),
8207 next_code),
8208 XEXP (x, 1));
8209 break;
8212 /* fall through */
8214 case ASHIFTRT:
8215 lhs = XEXP (x, 0);
8216 rhs = XEXP (x, 1);
8218 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8219 this is a SIGN_EXTRACT. */
8220 if (CONST_INT_P (rhs)
8221 && GET_CODE (lhs) == ASHIFT
8222 && CONST_INT_P (XEXP (lhs, 1))
8223 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
8224 && INTVAL (XEXP (lhs, 1)) >= 0
8225 && INTVAL (rhs) < mode_width)
8227 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
8228 new_rtx = make_extraction (mode, new_rtx,
8229 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
8230 NULL_RTX, mode_width - INTVAL (rhs),
8231 code == LSHIFTRT, 0, in_code == COMPARE);
8232 break;
8235 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8236 If so, try to merge the shifts into a SIGN_EXTEND. We could
8237 also do this for some cases of SIGN_EXTRACT, but it doesn't
8238 seem worth the effort; the case checked for occurs on Alpha. */
8240 if (!OBJECT_P (lhs)
8241 && ! (GET_CODE (lhs) == SUBREG
8242 && (OBJECT_P (SUBREG_REG (lhs))))
8243 && CONST_INT_P (rhs)
8244 && INTVAL (rhs) >= 0
8245 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
8246 && INTVAL (rhs) < mode_width
8247 && (new_rtx = extract_left_shift (mode, lhs, INTVAL (rhs))) != 0)
8248 new_rtx = make_extraction (mode, make_compound_operation (new_rtx,
8249 next_code),
8250 0, NULL_RTX, mode_width - INTVAL (rhs),
8251 code == LSHIFTRT, 0, in_code == COMPARE);
8253 break;
8255 case SUBREG:
8256 /* Call ourselves recursively on the inner expression. If we are
8257 narrowing the object and it has a different RTL code from
8258 what it originally did, do this SUBREG as a force_to_mode. */
8260 rtx inner = SUBREG_REG (x), simplified;
8261 enum rtx_code subreg_code = in_code;
8263 /* If the SUBREG is masking of a logical right shift,
8264 make an extraction. */
8265 if (GET_CODE (inner) == LSHIFTRT
8266 && is_a <scalar_int_mode> (GET_MODE (inner), &inner_mode)
8267 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (inner_mode)
8268 && CONST_INT_P (XEXP (inner, 1))
8269 && UINTVAL (XEXP (inner, 1)) < GET_MODE_PRECISION (inner_mode)
8270 && subreg_lowpart_p (x))
8272 new_rtx = make_compound_operation (XEXP (inner, 0), next_code);
8273 int width = GET_MODE_PRECISION (inner_mode)
8274 - INTVAL (XEXP (inner, 1));
8275 if (width > mode_width)
8276 width = mode_width;
8277 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (inner, 1),
8278 width, 1, 0, in_code == COMPARE);
8279 break;
8282 /* If in_code is COMPARE, it isn't always safe to pass it through
8283 to the recursive make_compound_operation call. */
8284 if (subreg_code == COMPARE
8285 && (!subreg_lowpart_p (x)
8286 || GET_CODE (inner) == SUBREG
8287 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8288 is (const_int 0), rather than
8289 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8290 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8291 for non-equality comparisons against 0 is not equivalent
8292 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8293 || (GET_CODE (inner) == AND
8294 && CONST_INT_P (XEXP (inner, 1))
8295 && partial_subreg_p (x)
8296 && exact_log2 (UINTVAL (XEXP (inner, 1)))
8297 >= GET_MODE_BITSIZE (mode) - 1)))
8298 subreg_code = SET;
8300 tem = make_compound_operation (inner, subreg_code);
8302 simplified
8303 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
8304 if (simplified)
8305 tem = simplified;
8307 if (GET_CODE (tem) != GET_CODE (inner)
8308 && partial_subreg_p (x)
8309 && subreg_lowpart_p (x))
8311 rtx newer
8312 = force_to_mode (tem, mode, HOST_WIDE_INT_M1U, 0);
8314 /* If we have something other than a SUBREG, we might have
8315 done an expansion, so rerun ourselves. */
8316 if (GET_CODE (newer) != SUBREG)
8317 newer = make_compound_operation (newer, in_code);
8319 /* force_to_mode can expand compounds. If it just re-expanded
8320 the compound, use gen_lowpart to convert to the desired
8321 mode. */
8322 if (rtx_equal_p (newer, x)
8323 /* Likewise if it re-expanded the compound only partially.
8324 This happens for SUBREG of ZERO_EXTRACT if they extract
8325 the same number of bits. */
8326 || (GET_CODE (newer) == SUBREG
8327 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
8328 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
8329 && GET_CODE (inner) == AND
8330 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
8331 return gen_lowpart (GET_MODE (x), tem);
8333 return newer;
8336 if (simplified)
8337 return tem;
8339 break;
8341 default:
8342 break;
8345 if (new_rtx)
8346 *x_ptr = gen_lowpart (mode, new_rtx);
8347 *next_code_ptr = next_code;
8348 return NULL_RTX;
8351 /* Look at the expression rooted at X. Look for expressions
8352 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8353 Form these expressions.
8355 Return the new rtx, usually just X.
8357 Also, for machines like the VAX that don't have logical shift insns,
8358 try to convert logical to arithmetic shift operations in cases where
8359 they are equivalent. This undoes the canonicalizations to logical
8360 shifts done elsewhere.
8362 We try, as much as possible, to re-use rtl expressions to save memory.
8364 IN_CODE says what kind of expression we are processing. Normally, it is
8365 SET. In a memory address it is MEM. When processing the arguments of
8366 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8367 precisely it is an equality comparison against zero. */
8370 make_compound_operation (rtx x, enum rtx_code in_code)
8372 enum rtx_code code = GET_CODE (x);
8373 const char *fmt;
8374 int i, j;
8375 enum rtx_code next_code;
8376 rtx new_rtx, tem;
8378 /* Select the code to be used in recursive calls. Once we are inside an
8379 address, we stay there. If we have a comparison, set to COMPARE,
8380 but once inside, go back to our default of SET. */
8382 next_code = (code == MEM ? MEM
8383 : ((code == COMPARE || COMPARISON_P (x))
8384 && XEXP (x, 1) == const0_rtx) ? COMPARE
8385 : in_code == COMPARE || in_code == EQ ? SET : in_code);
8387 scalar_int_mode mode;
8388 if (is_a <scalar_int_mode> (GET_MODE (x), &mode))
8390 rtx new_rtx = make_compound_operation_int (mode, &x, in_code,
8391 &next_code);
8392 if (new_rtx)
8393 return new_rtx;
8394 code = GET_CODE (x);
8397 /* Now recursively process each operand of this operation. We need to
8398 handle ZERO_EXTEND specially so that we don't lose track of the
8399 inner mode. */
8400 if (code == ZERO_EXTEND)
8402 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8403 tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
8404 new_rtx, GET_MODE (XEXP (x, 0)));
8405 if (tem)
8406 return tem;
8407 SUBST (XEXP (x, 0), new_rtx);
8408 return x;
8411 fmt = GET_RTX_FORMAT (code);
8412 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8413 if (fmt[i] == 'e')
8415 new_rtx = make_compound_operation (XEXP (x, i), next_code);
8416 SUBST (XEXP (x, i), new_rtx);
8418 else if (fmt[i] == 'E')
8419 for (j = 0; j < XVECLEN (x, i); j++)
8421 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
8422 SUBST (XVECEXP (x, i, j), new_rtx);
8425 maybe_swap_commutative_operands (x);
8426 return x;
8429 /* Given M see if it is a value that would select a field of bits
8430 within an item, but not the entire word. Return -1 if not.
8431 Otherwise, return the starting position of the field, where 0 is the
8432 low-order bit.
8434 *PLEN is set to the length of the field. */
8436 static int
8437 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
8439 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8440 int pos = m ? ctz_hwi (m) : -1;
8441 int len = 0;
8443 if (pos >= 0)
8444 /* Now shift off the low-order zero bits and see if we have a
8445 power of two minus 1. */
8446 len = exact_log2 ((m >> pos) + 1);
8448 if (len <= 0)
8449 pos = -1;
8451 *plen = len;
8452 return pos;
8455 /* If X refers to a register that equals REG in value, replace these
8456 references with REG. */
8457 static rtx
8458 canon_reg_for_combine (rtx x, rtx reg)
8460 rtx op0, op1, op2;
8461 const char *fmt;
8462 int i;
8463 bool copied;
8465 enum rtx_code code = GET_CODE (x);
8466 switch (GET_RTX_CLASS (code))
8468 case RTX_UNARY:
8469 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8470 if (op0 != XEXP (x, 0))
8471 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
8472 GET_MODE (reg));
8473 break;
8475 case RTX_BIN_ARITH:
8476 case RTX_COMM_ARITH:
8477 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8478 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8479 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8480 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
8481 break;
8483 case RTX_COMPARE:
8484 case RTX_COMM_COMPARE:
8485 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8486 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8487 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8488 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
8489 GET_MODE (op0), op0, op1);
8490 break;
8492 case RTX_TERNARY:
8493 case RTX_BITFIELD_OPS:
8494 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8495 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8496 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
8497 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
8498 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
8499 GET_MODE (op0), op0, op1, op2);
8500 /* FALLTHRU */
8502 case RTX_OBJ:
8503 if (REG_P (x))
8505 if (rtx_equal_p (get_last_value (reg), x)
8506 || rtx_equal_p (reg, get_last_value (x)))
8507 return reg;
8508 else
8509 break;
8512 /* fall through */
8514 default:
8515 fmt = GET_RTX_FORMAT (code);
8516 copied = false;
8517 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8518 if (fmt[i] == 'e')
8520 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8521 if (op != XEXP (x, i))
8523 if (!copied)
8525 copied = true;
8526 x = copy_rtx (x);
8528 XEXP (x, i) = op;
8531 else if (fmt[i] == 'E')
8533 int j;
8534 for (j = 0; j < XVECLEN (x, i); j++)
8536 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8537 if (op != XVECEXP (x, i, j))
8539 if (!copied)
8541 copied = true;
8542 x = copy_rtx (x);
8544 XVECEXP (x, i, j) = op;
8549 break;
8552 return x;
8555 /* Return X converted to MODE. If the value is already truncated to
8556 MODE we can just return a subreg even though in the general case we
8557 would need an explicit truncation. */
8559 static rtx
8560 gen_lowpart_or_truncate (machine_mode mode, rtx x)
8562 if (!CONST_INT_P (x)
8563 && partial_subreg_p (mode, GET_MODE (x))
8564 && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8565 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8567 /* Bit-cast X into an integer mode. */
8568 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8569 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)).require (), x);
8570 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode).require (),
8571 x, GET_MODE (x));
8574 return gen_lowpart (mode, x);
8577 /* See if X can be simplified knowing that we will only refer to it in
8578 MODE and will only refer to those bits that are nonzero in MASK.
8579 If other bits are being computed or if masking operations are done
8580 that select a superset of the bits in MASK, they can sometimes be
8581 ignored.
8583 Return a possibly simplified expression, but always convert X to
8584 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8586 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8587 are all off in X. This is used when X will be complemented, by either
8588 NOT, NEG, or XOR. */
8590 static rtx
8591 force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
8592 int just_select)
8594 enum rtx_code code = GET_CODE (x);
8595 int next_select = just_select || code == XOR || code == NOT || code == NEG;
8596 machine_mode op_mode;
8597 unsigned HOST_WIDE_INT nonzero;
8599 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8600 code below will do the wrong thing since the mode of such an
8601 expression is VOIDmode.
8603 Also do nothing if X is a CLOBBER; this can happen if X was
8604 the return value from a call to gen_lowpart. */
8605 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8606 return x;
8608 /* We want to perform the operation in its present mode unless we know
8609 that the operation is valid in MODE, in which case we do the operation
8610 in MODE. */
8611 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8612 && have_insn_for (code, mode))
8613 ? mode : GET_MODE (x));
8615 /* It is not valid to do a right-shift in a narrower mode
8616 than the one it came in with. */
8617 if ((code == LSHIFTRT || code == ASHIFTRT)
8618 && partial_subreg_p (mode, GET_MODE (x)))
8619 op_mode = GET_MODE (x);
8621 /* Truncate MASK to fit OP_MODE. */
8622 if (op_mode)
8623 mask &= GET_MODE_MASK (op_mode);
8625 /* Determine what bits of X are guaranteed to be (non)zero. */
8626 nonzero = nonzero_bits (x, mode);
8628 /* If none of the bits in X are needed, return a zero. */
8629 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8630 x = const0_rtx;
8632 /* If X is a CONST_INT, return a new one. Do this here since the
8633 test below will fail. */
8634 if (CONST_INT_P (x))
8636 if (SCALAR_INT_MODE_P (mode))
8637 return gen_int_mode (INTVAL (x) & mask, mode);
8638 else
8640 x = GEN_INT (INTVAL (x) & mask);
8641 return gen_lowpart_common (mode, x);
8645 /* If X is narrower than MODE and we want all the bits in X's mode, just
8646 get X in the proper mode. */
8647 if (paradoxical_subreg_p (mode, GET_MODE (x))
8648 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8649 return gen_lowpart (mode, x);
8651 /* We can ignore the effect of a SUBREG if it narrows the mode or
8652 if the constant masks to zero all the bits the mode doesn't have. */
8653 if (GET_CODE (x) == SUBREG
8654 && subreg_lowpart_p (x)
8655 && (partial_subreg_p (x)
8656 || (mask
8657 & GET_MODE_MASK (GET_MODE (x))
8658 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0))
8659 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8661 scalar_int_mode int_mode, xmode;
8662 if (is_a <scalar_int_mode> (mode, &int_mode)
8663 && is_a <scalar_int_mode> (GET_MODE (x), &xmode))
8664 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8665 integer too. */
8666 return force_int_to_mode (x, int_mode, xmode,
8667 as_a <scalar_int_mode> (op_mode),
8668 mask, just_select);
8670 return gen_lowpart_or_truncate (mode, x);
8673 /* Subroutine of force_to_mode that handles cases in which both X and
8674 the result are scalar integers. MODE is the mode of the result,
8675 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8676 is preferred for simplified versions of X. The other arguments
8677 are as for force_to_mode. */
8679 static rtx
8680 force_int_to_mode (rtx x, scalar_int_mode mode, scalar_int_mode xmode,
8681 scalar_int_mode op_mode, unsigned HOST_WIDE_INT mask,
8682 int just_select)
8684 enum rtx_code code = GET_CODE (x);
8685 int next_select = just_select || code == XOR || code == NOT || code == NEG;
8686 unsigned HOST_WIDE_INT fuller_mask;
8687 rtx op0, op1, temp;
8689 /* When we have an arithmetic operation, or a shift whose count we
8690 do not know, we need to assume that all bits up to the highest-order
8691 bit in MASK will be needed. This is how we form such a mask. */
8692 if (mask & (HOST_WIDE_INT_1U << (HOST_BITS_PER_WIDE_INT - 1)))
8693 fuller_mask = HOST_WIDE_INT_M1U;
8694 else
8695 fuller_mask = ((HOST_WIDE_INT_1U << (floor_log2 (mask) + 1))
8696 - 1);
8698 switch (code)
8700 case CLOBBER:
8701 /* If X is a (clobber (const_int)), return it since we know we are
8702 generating something that won't match. */
8703 return x;
8705 case SIGN_EXTEND:
8706 case ZERO_EXTEND:
8707 case ZERO_EXTRACT:
8708 case SIGN_EXTRACT:
8709 x = expand_compound_operation (x);
8710 if (GET_CODE (x) != code)
8711 return force_to_mode (x, mode, mask, next_select);
8712 break;
8714 case TRUNCATE:
8715 /* Similarly for a truncate. */
8716 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8718 case AND:
8719 /* If this is an AND with a constant, convert it into an AND
8720 whose constant is the AND of that constant with MASK. If it
8721 remains an AND of MASK, delete it since it is redundant. */
8723 if (CONST_INT_P (XEXP (x, 1)))
8725 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8726 mask & INTVAL (XEXP (x, 1)));
8727 xmode = op_mode;
8729 /* If X is still an AND, see if it is an AND with a mask that
8730 is just some low-order bits. If so, and it is MASK, we don't
8731 need it. */
8733 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8734 && (INTVAL (XEXP (x, 1)) & GET_MODE_MASK (xmode)) == mask)
8735 x = XEXP (x, 0);
8737 /* If it remains an AND, try making another AND with the bits
8738 in the mode mask that aren't in MASK turned on. If the
8739 constant in the AND is wide enough, this might make a
8740 cheaper constant. */
8742 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8743 && GET_MODE_MASK (xmode) != mask
8744 && HWI_COMPUTABLE_MODE_P (xmode))
8746 unsigned HOST_WIDE_INT cval
8747 = UINTVAL (XEXP (x, 1)) | (GET_MODE_MASK (xmode) & ~mask);
8748 rtx y;
8750 y = simplify_gen_binary (AND, xmode, XEXP (x, 0),
8751 gen_int_mode (cval, xmode));
8752 if (set_src_cost (y, xmode, optimize_this_for_speed_p)
8753 < set_src_cost (x, xmode, optimize_this_for_speed_p))
8754 x = y;
8757 break;
8760 goto binop;
8762 case PLUS:
8763 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8764 low-order bits (as in an alignment operation) and FOO is already
8765 aligned to that boundary, mask C1 to that boundary as well.
8766 This may eliminate that PLUS and, later, the AND. */
8769 unsigned int width = GET_MODE_PRECISION (mode);
8770 unsigned HOST_WIDE_INT smask = mask;
8772 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8773 number, sign extend it. */
8775 if (width < HOST_BITS_PER_WIDE_INT
8776 && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8777 smask |= HOST_WIDE_INT_M1U << width;
8779 if (CONST_INT_P (XEXP (x, 1))
8780 && pow2p_hwi (- smask)
8781 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8782 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8783 return force_to_mode (plus_constant (xmode, XEXP (x, 0),
8784 (INTVAL (XEXP (x, 1)) & smask)),
8785 mode, smask, next_select);
8788 /* fall through */
8790 case MULT:
8791 /* Substituting into the operands of a widening MULT is not likely to
8792 create RTL matching a machine insn. */
8793 if (code == MULT
8794 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
8795 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
8796 && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
8797 || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
8798 && REG_P (XEXP (XEXP (x, 0), 0))
8799 && REG_P (XEXP (XEXP (x, 1), 0)))
8800 return gen_lowpart_or_truncate (mode, x);
8802 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8803 most significant bit in MASK since carries from those bits will
8804 affect the bits we are interested in. */
8805 mask = fuller_mask;
8806 goto binop;
8808 case MINUS:
8809 /* If X is (minus C Y) where C's least set bit is larger than any bit
8810 in the mask, then we may replace with (neg Y). */
8811 if (CONST_INT_P (XEXP (x, 0))
8812 && least_bit_hwi (UINTVAL (XEXP (x, 0))) > mask)
8814 x = simplify_gen_unary (NEG, xmode, XEXP (x, 1), xmode);
8815 return force_to_mode (x, mode, mask, next_select);
8818 /* Similarly, if C contains every bit in the fuller_mask, then we may
8819 replace with (not Y). */
8820 if (CONST_INT_P (XEXP (x, 0))
8821 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8823 x = simplify_gen_unary (NOT, xmode, XEXP (x, 1), xmode);
8824 return force_to_mode (x, mode, mask, next_select);
8827 mask = fuller_mask;
8828 goto binop;
8830 case IOR:
8831 case XOR:
8832 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8833 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8834 operation which may be a bitfield extraction. Ensure that the
8835 constant we form is not wider than the mode of X. */
8837 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8838 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8839 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8840 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8841 && CONST_INT_P (XEXP (x, 1))
8842 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8843 + floor_log2 (INTVAL (XEXP (x, 1))))
8844 < GET_MODE_PRECISION (xmode))
8845 && (UINTVAL (XEXP (x, 1))
8846 & ~nonzero_bits (XEXP (x, 0), xmode)) == 0)
8848 temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8849 << INTVAL (XEXP (XEXP (x, 0), 1)),
8850 xmode);
8851 temp = simplify_gen_binary (GET_CODE (x), xmode,
8852 XEXP (XEXP (x, 0), 0), temp);
8853 x = simplify_gen_binary (LSHIFTRT, xmode, temp,
8854 XEXP (XEXP (x, 0), 1));
8855 return force_to_mode (x, mode, mask, next_select);
8858 binop:
8859 /* For most binary operations, just propagate into the operation and
8860 change the mode if we have an operation of that mode. */
8862 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8863 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8865 /* If we ended up truncating both operands, truncate the result of the
8866 operation instead. */
8867 if (GET_CODE (op0) == TRUNCATE
8868 && GET_CODE (op1) == TRUNCATE)
8870 op0 = XEXP (op0, 0);
8871 op1 = XEXP (op1, 0);
8874 op0 = gen_lowpart_or_truncate (op_mode, op0);
8875 op1 = gen_lowpart_or_truncate (op_mode, op1);
8877 if (op_mode != xmode || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8879 x = simplify_gen_binary (code, op_mode, op0, op1);
8880 xmode = op_mode;
8882 break;
8884 case ASHIFT:
8885 /* For left shifts, do the same, but just for the first operand.
8886 However, we cannot do anything with shifts where we cannot
8887 guarantee that the counts are smaller than the size of the mode
8888 because such a count will have a different meaning in a
8889 wider mode. */
8891 if (! (CONST_INT_P (XEXP (x, 1))
8892 && INTVAL (XEXP (x, 1)) >= 0
8893 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8894 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8895 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8896 < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8897 break;
8899 /* If the shift count is a constant and we can do arithmetic in
8900 the mode of the shift, refine which bits we need. Otherwise, use the
8901 conservative form of the mask. */
8902 if (CONST_INT_P (XEXP (x, 1))
8903 && INTVAL (XEXP (x, 1)) >= 0
8904 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8905 && HWI_COMPUTABLE_MODE_P (op_mode))
8906 mask >>= INTVAL (XEXP (x, 1));
8907 else
8908 mask = fuller_mask;
8910 op0 = gen_lowpart_or_truncate (op_mode,
8911 force_to_mode (XEXP (x, 0), mode,
8912 mask, next_select));
8914 if (op_mode != xmode || op0 != XEXP (x, 0))
8916 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8917 xmode = op_mode;
8919 break;
8921 case LSHIFTRT:
8922 /* Here we can only do something if the shift count is a constant,
8923 this shift constant is valid for the host, and we can do arithmetic
8924 in OP_MODE. */
8926 if (CONST_INT_P (XEXP (x, 1))
8927 && INTVAL (XEXP (x, 1)) >= 0
8928 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8929 && HWI_COMPUTABLE_MODE_P (op_mode))
8931 rtx inner = XEXP (x, 0);
8932 unsigned HOST_WIDE_INT inner_mask;
8934 /* Select the mask of the bits we need for the shift operand. */
8935 inner_mask = mask << INTVAL (XEXP (x, 1));
8937 /* We can only change the mode of the shift if we can do arithmetic
8938 in the mode of the shift and INNER_MASK is no wider than the
8939 width of X's mode. */
8940 if ((inner_mask & ~GET_MODE_MASK (xmode)) != 0)
8941 op_mode = xmode;
8943 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8945 if (xmode != op_mode || inner != XEXP (x, 0))
8947 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8948 xmode = op_mode;
8952 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8953 shift and AND produces only copies of the sign bit (C2 is one less
8954 than a power of two), we can do this with just a shift. */
8956 if (GET_CODE (x) == LSHIFTRT
8957 && CONST_INT_P (XEXP (x, 1))
8958 /* The shift puts one of the sign bit copies in the least significant
8959 bit. */
8960 && ((INTVAL (XEXP (x, 1))
8961 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8962 >= GET_MODE_PRECISION (xmode))
8963 && pow2p_hwi (mask + 1)
8964 /* Number of bits left after the shift must be more than the mask
8965 needs. */
8966 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8967 <= GET_MODE_PRECISION (xmode))
8968 /* Must be more sign bit copies than the mask needs. */
8969 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8970 >= exact_log2 (mask + 1)))
8972 int nbits = GET_MODE_PRECISION (xmode) - exact_log2 (mask + 1);
8973 x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0),
8974 gen_int_shift_amount (xmode, nbits));
8976 goto shiftrt;
8978 case ASHIFTRT:
8979 /* If we are just looking for the sign bit, we don't need this shift at
8980 all, even if it has a variable count. */
8981 if (val_signbit_p (xmode, mask))
8982 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8984 /* If this is a shift by a constant, get a mask that contains those bits
8985 that are not copies of the sign bit. We then have two cases: If
8986 MASK only includes those bits, this can be a logical shift, which may
8987 allow simplifications. If MASK is a single-bit field not within
8988 those bits, we are requesting a copy of the sign bit and hence can
8989 shift the sign bit to the appropriate location. */
8991 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8992 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8994 unsigned HOST_WIDE_INT nonzero;
8995 int i;
8997 /* If the considered data is wider than HOST_WIDE_INT, we can't
8998 represent a mask for all its bits in a single scalar.
8999 But we only care about the lower bits, so calculate these. */
9001 if (GET_MODE_PRECISION (xmode) > HOST_BITS_PER_WIDE_INT)
9003 nonzero = HOST_WIDE_INT_M1U;
9005 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9006 is the number of bits a full-width mask would have set.
9007 We need only shift if these are fewer than nonzero can
9008 hold. If not, we must keep all bits set in nonzero. */
9010 if (GET_MODE_PRECISION (xmode) - INTVAL (XEXP (x, 1))
9011 < HOST_BITS_PER_WIDE_INT)
9012 nonzero >>= INTVAL (XEXP (x, 1))
9013 + HOST_BITS_PER_WIDE_INT
9014 - GET_MODE_PRECISION (xmode);
9016 else
9018 nonzero = GET_MODE_MASK (xmode);
9019 nonzero >>= INTVAL (XEXP (x, 1));
9022 if ((mask & ~nonzero) == 0)
9024 x = simplify_shift_const (NULL_RTX, LSHIFTRT, xmode,
9025 XEXP (x, 0), INTVAL (XEXP (x, 1)));
9026 if (GET_CODE (x) != ASHIFTRT)
9027 return force_to_mode (x, mode, mask, next_select);
9030 else if ((i = exact_log2 (mask)) >= 0)
9032 x = simplify_shift_const
9033 (NULL_RTX, LSHIFTRT, xmode, XEXP (x, 0),
9034 GET_MODE_PRECISION (xmode) - 1 - i);
9036 if (GET_CODE (x) != ASHIFTRT)
9037 return force_to_mode (x, mode, mask, next_select);
9041 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9042 even if the shift count isn't a constant. */
9043 if (mask == 1)
9044 x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0), XEXP (x, 1));
9046 shiftrt:
9048 /* If this is a zero- or sign-extension operation that just affects bits
9049 we don't care about, remove it. Be sure the call above returned
9050 something that is still a shift. */
9052 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
9053 && CONST_INT_P (XEXP (x, 1))
9054 && INTVAL (XEXP (x, 1)) >= 0
9055 && (INTVAL (XEXP (x, 1))
9056 <= GET_MODE_PRECISION (xmode) - (floor_log2 (mask) + 1))
9057 && GET_CODE (XEXP (x, 0)) == ASHIFT
9058 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
9059 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
9060 next_select);
9062 break;
9064 case ROTATE:
9065 case ROTATERT:
9066 /* If the shift count is constant and we can do computations
9067 in the mode of X, compute where the bits we care about are.
9068 Otherwise, we can't do anything. Don't change the mode of
9069 the shift or propagate MODE into the shift, though. */
9070 if (CONST_INT_P (XEXP (x, 1))
9071 && INTVAL (XEXP (x, 1)) >= 0)
9073 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
9074 xmode, gen_int_mode (mask, xmode),
9075 XEXP (x, 1));
9076 if (temp && CONST_INT_P (temp))
9077 x = simplify_gen_binary (code, xmode,
9078 force_to_mode (XEXP (x, 0), xmode,
9079 INTVAL (temp), next_select),
9080 XEXP (x, 1));
9082 break;
9084 case NEG:
9085 /* If we just want the low-order bit, the NEG isn't needed since it
9086 won't change the low-order bit. */
9087 if (mask == 1)
9088 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
9090 /* We need any bits less significant than the most significant bit in
9091 MASK since carries from those bits will affect the bits we are
9092 interested in. */
9093 mask = fuller_mask;
9094 goto unop;
9096 case NOT:
9097 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9098 same as the XOR case above. Ensure that the constant we form is not
9099 wider than the mode of X. */
9101 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
9102 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
9103 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
9104 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
9105 < GET_MODE_PRECISION (xmode))
9106 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9108 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), xmode);
9109 temp = simplify_gen_binary (XOR, xmode, XEXP (XEXP (x, 0), 0), temp);
9110 x = simplify_gen_binary (LSHIFTRT, xmode,
9111 temp, XEXP (XEXP (x, 0), 1));
9113 return force_to_mode (x, mode, mask, next_select);
9116 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9117 use the full mask inside the NOT. */
9118 mask = fuller_mask;
9120 unop:
9121 op0 = gen_lowpart_or_truncate (op_mode,
9122 force_to_mode (XEXP (x, 0), mode, mask,
9123 next_select));
9124 if (op_mode != xmode || op0 != XEXP (x, 0))
9126 x = simplify_gen_unary (code, op_mode, op0, op_mode);
9127 xmode = op_mode;
9129 break;
9131 case NE:
9132 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9133 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9134 which is equal to STORE_FLAG_VALUE. */
9135 if ((mask & ~STORE_FLAG_VALUE) == 0
9136 && XEXP (x, 1) == const0_rtx
9137 && GET_MODE (XEXP (x, 0)) == mode
9138 && pow2p_hwi (nonzero_bits (XEXP (x, 0), mode))
9139 && (nonzero_bits (XEXP (x, 0), mode)
9140 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
9141 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
9143 break;
9145 case IF_THEN_ELSE:
9146 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9147 written in a narrower mode. We play it safe and do not do so. */
9149 op0 = gen_lowpart_or_truncate (xmode,
9150 force_to_mode (XEXP (x, 1), mode,
9151 mask, next_select));
9152 op1 = gen_lowpart_or_truncate (xmode,
9153 force_to_mode (XEXP (x, 2), mode,
9154 mask, next_select));
9155 if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))
9156 x = simplify_gen_ternary (IF_THEN_ELSE, xmode,
9157 GET_MODE (XEXP (x, 0)), XEXP (x, 0),
9158 op0, op1);
9159 break;
9161 default:
9162 break;
9165 /* Ensure we return a value of the proper mode. */
9166 return gen_lowpart_or_truncate (mode, x);
9169 /* Return nonzero if X is an expression that has one of two values depending on
9170 whether some other value is zero or nonzero. In that case, we return the
9171 value that is being tested, *PTRUE is set to the value if the rtx being
9172 returned has a nonzero value, and *PFALSE is set to the other alternative.
9174 If we return zero, we set *PTRUE and *PFALSE to X. */
9176 static rtx
9177 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
9179 machine_mode mode = GET_MODE (x);
9180 enum rtx_code code = GET_CODE (x);
9181 rtx cond0, cond1, true0, true1, false0, false1;
9182 unsigned HOST_WIDE_INT nz;
9183 scalar_int_mode int_mode;
9185 /* If we are comparing a value against zero, we are done. */
9186 if ((code == NE || code == EQ)
9187 && XEXP (x, 1) == const0_rtx)
9189 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
9190 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
9191 return XEXP (x, 0);
9194 /* If this is a unary operation whose operand has one of two values, apply
9195 our opcode to compute those values. */
9196 else if (UNARY_P (x)
9197 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
9199 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
9200 *pfalse = simplify_gen_unary (code, mode, false0,
9201 GET_MODE (XEXP (x, 0)));
9202 return cond0;
9205 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9206 make can't possibly match and would suppress other optimizations. */
9207 else if (code == COMPARE)
9210 /* If this is a binary operation, see if either side has only one of two
9211 values. If either one does or if both do and they are conditional on
9212 the same value, compute the new true and false values. */
9213 else if (BINARY_P (x))
9215 rtx op0 = XEXP (x, 0);
9216 rtx op1 = XEXP (x, 1);
9217 cond0 = if_then_else_cond (op0, &true0, &false0);
9218 cond1 = if_then_else_cond (op1, &true1, &false1);
9220 if ((cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1))
9221 && (REG_P (op0) || REG_P (op1)))
9223 /* Try to enable a simplification by undoing work done by
9224 if_then_else_cond if it converted a REG into something more
9225 complex. */
9226 if (REG_P (op0))
9228 cond0 = 0;
9229 true0 = false0 = op0;
9231 else
9233 cond1 = 0;
9234 true1 = false1 = op1;
9238 if ((cond0 != 0 || cond1 != 0)
9239 && ! (cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1)))
9241 /* If if_then_else_cond returned zero, then true/false are the
9242 same rtl. We must copy one of them to prevent invalid rtl
9243 sharing. */
9244 if (cond0 == 0)
9245 true0 = copy_rtx (true0);
9246 else if (cond1 == 0)
9247 true1 = copy_rtx (true1);
9249 if (COMPARISON_P (x))
9251 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
9252 true0, true1);
9253 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
9254 false0, false1);
9256 else
9258 *ptrue = simplify_gen_binary (code, mode, true0, true1);
9259 *pfalse = simplify_gen_binary (code, mode, false0, false1);
9262 return cond0 ? cond0 : cond1;
9265 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9266 operands is zero when the other is nonzero, and vice-versa,
9267 and STORE_FLAG_VALUE is 1 or -1. */
9269 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9270 && (code == PLUS || code == IOR || code == XOR || code == MINUS
9271 || code == UMAX)
9272 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9274 rtx op0 = XEXP (XEXP (x, 0), 1);
9275 rtx op1 = XEXP (XEXP (x, 1), 1);
9277 cond0 = XEXP (XEXP (x, 0), 0);
9278 cond1 = XEXP (XEXP (x, 1), 0);
9280 if (COMPARISON_P (cond0)
9281 && COMPARISON_P (cond1)
9282 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9283 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9284 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9285 || ((swap_condition (GET_CODE (cond0))
9286 == reversed_comparison_code (cond1, NULL))
9287 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9288 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9289 && ! side_effects_p (x))
9291 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
9292 *pfalse = simplify_gen_binary (MULT, mode,
9293 (code == MINUS
9294 ? simplify_gen_unary (NEG, mode,
9295 op1, mode)
9296 : op1),
9297 const_true_rtx);
9298 return cond0;
9302 /* Similarly for MULT, AND and UMIN, except that for these the result
9303 is always zero. */
9304 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9305 && (code == MULT || code == AND || code == UMIN)
9306 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9308 cond0 = XEXP (XEXP (x, 0), 0);
9309 cond1 = XEXP (XEXP (x, 1), 0);
9311 if (COMPARISON_P (cond0)
9312 && COMPARISON_P (cond1)
9313 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9314 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9315 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9316 || ((swap_condition (GET_CODE (cond0))
9317 == reversed_comparison_code (cond1, NULL))
9318 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9319 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9320 && ! side_effects_p (x))
9322 *ptrue = *pfalse = const0_rtx;
9323 return cond0;
9328 else if (code == IF_THEN_ELSE)
9330 /* If we have IF_THEN_ELSE already, extract the condition and
9331 canonicalize it if it is NE or EQ. */
9332 cond0 = XEXP (x, 0);
9333 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
9334 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
9335 return XEXP (cond0, 0);
9336 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
9338 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
9339 return XEXP (cond0, 0);
9341 else
9342 return cond0;
9345 /* If X is a SUBREG, we can narrow both the true and false values
9346 if the inner expression, if there is a condition. */
9347 else if (code == SUBREG
9348 && (cond0 = if_then_else_cond (SUBREG_REG (x), &true0,
9349 &false0)) != 0)
9351 true0 = simplify_gen_subreg (mode, true0,
9352 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9353 false0 = simplify_gen_subreg (mode, false0,
9354 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9355 if (true0 && false0)
9357 *ptrue = true0;
9358 *pfalse = false0;
9359 return cond0;
9363 /* If X is a constant, this isn't special and will cause confusions
9364 if we treat it as such. Likewise if it is equivalent to a constant. */
9365 else if (CONSTANT_P (x)
9366 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
9369 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9370 will be least confusing to the rest of the compiler. */
9371 else if (mode == BImode)
9373 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
9374 return x;
9377 /* If X is known to be either 0 or -1, those are the true and
9378 false values when testing X. */
9379 else if (x == constm1_rtx || x == const0_rtx
9380 || (is_a <scalar_int_mode> (mode, &int_mode)
9381 && (num_sign_bit_copies (x, int_mode)
9382 == GET_MODE_PRECISION (int_mode))))
9384 *ptrue = constm1_rtx, *pfalse = const0_rtx;
9385 return x;
9388 /* Likewise for 0 or a single bit. */
9389 else if (HWI_COMPUTABLE_MODE_P (mode)
9390 && pow2p_hwi (nz = nonzero_bits (x, mode)))
9392 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
9393 return x;
9396 /* Otherwise fail; show no condition with true and false values the same. */
9397 *ptrue = *pfalse = x;
9398 return 0;
9401 /* Return the value of expression X given the fact that condition COND
9402 is known to be true when applied to REG as its first operand and VAL
9403 as its second. X is known to not be shared and so can be modified in
9404 place.
9406 We only handle the simplest cases, and specifically those cases that
9407 arise with IF_THEN_ELSE expressions. */
9409 static rtx
9410 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
9412 enum rtx_code code = GET_CODE (x);
9413 const char *fmt;
9414 int i, j;
9416 if (side_effects_p (x))
9417 return x;
9419 /* If either operand of the condition is a floating point value,
9420 then we have to avoid collapsing an EQ comparison. */
9421 if (cond == EQ
9422 && rtx_equal_p (x, reg)
9423 && ! FLOAT_MODE_P (GET_MODE (x))
9424 && ! FLOAT_MODE_P (GET_MODE (val)))
9425 return val;
9427 if (cond == UNEQ && rtx_equal_p (x, reg))
9428 return val;
9430 /* If X is (abs REG) and we know something about REG's relationship
9431 with zero, we may be able to simplify this. */
9433 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
9434 switch (cond)
9436 case GE: case GT: case EQ:
9437 return XEXP (x, 0);
9438 case LT: case LE:
9439 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
9440 XEXP (x, 0),
9441 GET_MODE (XEXP (x, 0)));
9442 default:
9443 break;
9446 /* The only other cases we handle are MIN, MAX, and comparisons if the
9447 operands are the same as REG and VAL. */
9449 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
9451 if (rtx_equal_p (XEXP (x, 0), val))
9453 std::swap (val, reg);
9454 cond = swap_condition (cond);
9457 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
9459 if (COMPARISON_P (x))
9461 if (comparison_dominates_p (cond, code))
9462 return const_true_rtx;
9464 code = reversed_comparison_code (x, NULL);
9465 if (code != UNKNOWN
9466 && comparison_dominates_p (cond, code))
9467 return const0_rtx;
9468 else
9469 return x;
9471 else if (code == SMAX || code == SMIN
9472 || code == UMIN || code == UMAX)
9474 int unsignedp = (code == UMIN || code == UMAX);
9476 /* Do not reverse the condition when it is NE or EQ.
9477 This is because we cannot conclude anything about
9478 the value of 'SMAX (x, y)' when x is not equal to y,
9479 but we can when x equals y. */
9480 if ((code == SMAX || code == UMAX)
9481 && ! (cond == EQ || cond == NE))
9482 cond = reverse_condition (cond);
9484 switch (cond)
9486 case GE: case GT:
9487 return unsignedp ? x : XEXP (x, 1);
9488 case LE: case LT:
9489 return unsignedp ? x : XEXP (x, 0);
9490 case GEU: case GTU:
9491 return unsignedp ? XEXP (x, 1) : x;
9492 case LEU: case LTU:
9493 return unsignedp ? XEXP (x, 0) : x;
9494 default:
9495 break;
9500 else if (code == SUBREG)
9502 machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
9503 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
9505 if (SUBREG_REG (x) != r)
9507 /* We must simplify subreg here, before we lose track of the
9508 original inner_mode. */
9509 new_rtx = simplify_subreg (GET_MODE (x), r,
9510 inner_mode, SUBREG_BYTE (x));
9511 if (new_rtx)
9512 return new_rtx;
9513 else
9514 SUBST (SUBREG_REG (x), r);
9517 return x;
9519 /* We don't have to handle SIGN_EXTEND here, because even in the
9520 case of replacing something with a modeless CONST_INT, a
9521 CONST_INT is already (supposed to be) a valid sign extension for
9522 its narrower mode, which implies it's already properly
9523 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9524 story is different. */
9525 else if (code == ZERO_EXTEND)
9527 machine_mode inner_mode = GET_MODE (XEXP (x, 0));
9528 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
9530 if (XEXP (x, 0) != r)
9532 /* We must simplify the zero_extend here, before we lose
9533 track of the original inner_mode. */
9534 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
9535 r, inner_mode);
9536 if (new_rtx)
9537 return new_rtx;
9538 else
9539 SUBST (XEXP (x, 0), r);
9542 return x;
9545 fmt = GET_RTX_FORMAT (code);
9546 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9548 if (fmt[i] == 'e')
9549 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
9550 else if (fmt[i] == 'E')
9551 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9552 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
9553 cond, reg, val));
9556 return x;
9559 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9560 assignment as a field assignment. */
9562 static int
9563 rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x)
9565 if (widen_x && GET_MODE (x) != GET_MODE (y))
9567 if (paradoxical_subreg_p (GET_MODE (x), GET_MODE (y)))
9568 return 0;
9569 if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN)
9570 return 0;
9571 x = adjust_address_nv (x, GET_MODE (y),
9572 byte_lowpart_offset (GET_MODE (y),
9573 GET_MODE (x)));
9576 if (x == y || rtx_equal_p (x, y))
9577 return 1;
9579 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
9580 return 0;
9582 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9583 Note that all SUBREGs of MEM are paradoxical; otherwise they
9584 would have been rewritten. */
9585 if (MEM_P (x) && GET_CODE (y) == SUBREG
9586 && MEM_P (SUBREG_REG (y))
9587 && rtx_equal_p (SUBREG_REG (y),
9588 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
9589 return 1;
9591 if (MEM_P (y) && GET_CODE (x) == SUBREG
9592 && MEM_P (SUBREG_REG (x))
9593 && rtx_equal_p (SUBREG_REG (x),
9594 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
9595 return 1;
9597 /* We used to see if get_last_value of X and Y were the same but that's
9598 not correct. In one direction, we'll cause the assignment to have
9599 the wrong destination and in the case, we'll import a register into this
9600 insn that might have already have been dead. So fail if none of the
9601 above cases are true. */
9602 return 0;
9605 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9606 Return that assignment if so.
9608 We only handle the most common cases. */
9610 static rtx
9611 make_field_assignment (rtx x)
9613 rtx dest = SET_DEST (x);
9614 rtx src = SET_SRC (x);
9615 rtx assign;
9616 rtx rhs, lhs;
9617 HOST_WIDE_INT c1;
9618 HOST_WIDE_INT pos;
9619 unsigned HOST_WIDE_INT len;
9620 rtx other;
9622 /* All the rules in this function are specific to scalar integers. */
9623 scalar_int_mode mode;
9624 if (!is_a <scalar_int_mode> (GET_MODE (dest), &mode))
9625 return x;
9627 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9628 a clear of a one-bit field. We will have changed it to
9629 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9630 for a SUBREG. */
9632 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9633 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9634 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9635 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9637 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9638 1, 1, 1, 0);
9639 if (assign != 0)
9640 return gen_rtx_SET (assign, const0_rtx);
9641 return x;
9644 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9645 && subreg_lowpart_p (XEXP (src, 0))
9646 && partial_subreg_p (XEXP (src, 0))
9647 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9648 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9649 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9650 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9652 assign = make_extraction (VOIDmode, dest, 0,
9653 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9654 1, 1, 1, 0);
9655 if (assign != 0)
9656 return gen_rtx_SET (assign, const0_rtx);
9657 return x;
9660 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9661 one-bit field. */
9662 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9663 && XEXP (XEXP (src, 0), 0) == const1_rtx
9664 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9666 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9667 1, 1, 1, 0);
9668 if (assign != 0)
9669 return gen_rtx_SET (assign, const1_rtx);
9670 return x;
9673 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9674 SRC is an AND with all bits of that field set, then we can discard
9675 the AND. */
9676 if (GET_CODE (dest) == ZERO_EXTRACT
9677 && CONST_INT_P (XEXP (dest, 1))
9678 && GET_CODE (src) == AND
9679 && CONST_INT_P (XEXP (src, 1)))
9681 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9682 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9683 unsigned HOST_WIDE_INT ze_mask;
9685 if (width >= HOST_BITS_PER_WIDE_INT)
9686 ze_mask = -1;
9687 else
9688 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9690 /* Complete overlap. We can remove the source AND. */
9691 if ((and_mask & ze_mask) == ze_mask)
9692 return gen_rtx_SET (dest, XEXP (src, 0));
9694 /* Partial overlap. We can reduce the source AND. */
9695 if ((and_mask & ze_mask) != and_mask)
9697 src = gen_rtx_AND (mode, XEXP (src, 0),
9698 gen_int_mode (and_mask & ze_mask, mode));
9699 return gen_rtx_SET (dest, src);
9703 /* The other case we handle is assignments into a constant-position
9704 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9705 a mask that has all one bits except for a group of zero bits and
9706 OTHER is known to have zeros where C1 has ones, this is such an
9707 assignment. Compute the position and length from C1. Shift OTHER
9708 to the appropriate position, force it to the required mode, and
9709 make the extraction. Check for the AND in both operands. */
9711 /* One or more SUBREGs might obscure the constant-position field
9712 assignment. The first one we are likely to encounter is an outer
9713 narrowing SUBREG, which we can just strip for the purposes of
9714 identifying the constant-field assignment. */
9715 scalar_int_mode src_mode = mode;
9716 if (GET_CODE (src) == SUBREG
9717 && subreg_lowpart_p (src)
9718 && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (src)), &src_mode))
9719 src = SUBREG_REG (src);
9721 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9722 return x;
9724 rhs = expand_compound_operation (XEXP (src, 0));
9725 lhs = expand_compound_operation (XEXP (src, 1));
9727 if (GET_CODE (rhs) == AND
9728 && CONST_INT_P (XEXP (rhs, 1))
9729 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9730 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9731 /* The second SUBREG that might get in the way is a paradoxical
9732 SUBREG around the first operand of the AND. We want to
9733 pretend the operand is as wide as the destination here. We
9734 do this by adjusting the MEM to wider mode for the sole
9735 purpose of the call to rtx_equal_for_field_assignment_p. Also
9736 note this trick only works for MEMs. */
9737 else if (GET_CODE (rhs) == AND
9738 && paradoxical_subreg_p (XEXP (rhs, 0))
9739 && MEM_P (SUBREG_REG (XEXP (rhs, 0)))
9740 && CONST_INT_P (XEXP (rhs, 1))
9741 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs, 0)),
9742 dest, true))
9743 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9744 else if (GET_CODE (lhs) == AND
9745 && CONST_INT_P (XEXP (lhs, 1))
9746 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9747 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9748 /* The second SUBREG that might get in the way is a paradoxical
9749 SUBREG around the first operand of the AND. We want to
9750 pretend the operand is as wide as the destination here. We
9751 do this by adjusting the MEM to wider mode for the sole
9752 purpose of the call to rtx_equal_for_field_assignment_p. Also
9753 note this trick only works for MEMs. */
9754 else if (GET_CODE (lhs) == AND
9755 && paradoxical_subreg_p (XEXP (lhs, 0))
9756 && MEM_P (SUBREG_REG (XEXP (lhs, 0)))
9757 && CONST_INT_P (XEXP (lhs, 1))
9758 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs, 0)),
9759 dest, true))
9760 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9761 else
9762 return x;
9764 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (mode), &len);
9765 if (pos < 0
9766 || pos + len > GET_MODE_PRECISION (mode)
9767 || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
9768 || (c1 & nonzero_bits (other, mode)) != 0)
9769 return x;
9771 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9772 if (assign == 0)
9773 return x;
9775 /* The mode to use for the source is the mode of the assignment, or of
9776 what is inside a possible STRICT_LOW_PART. */
9777 machine_mode new_mode = (GET_CODE (assign) == STRICT_LOW_PART
9778 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9780 /* Shift OTHER right POS places and make it the source, restricting it
9781 to the proper length and mode. */
9783 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9784 src_mode, other, pos),
9785 dest);
9786 src = force_to_mode (src, new_mode,
9787 len >= HOST_BITS_PER_WIDE_INT
9788 ? HOST_WIDE_INT_M1U
9789 : (HOST_WIDE_INT_1U << len) - 1,
9792 /* If SRC is masked by an AND that does not make a difference in
9793 the value being stored, strip it. */
9794 if (GET_CODE (assign) == ZERO_EXTRACT
9795 && CONST_INT_P (XEXP (assign, 1))
9796 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9797 && GET_CODE (src) == AND
9798 && CONST_INT_P (XEXP (src, 1))
9799 && UINTVAL (XEXP (src, 1))
9800 == (HOST_WIDE_INT_1U << INTVAL (XEXP (assign, 1))) - 1)
9801 src = XEXP (src, 0);
9803 return gen_rtx_SET (assign, src);
9806 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9807 if so. */
9809 static rtx
9810 apply_distributive_law (rtx x)
9812 enum rtx_code code = GET_CODE (x);
9813 enum rtx_code inner_code;
9814 rtx lhs, rhs, other;
9815 rtx tem;
9817 /* Distributivity is not true for floating point as it can change the
9818 value. So we don't do it unless -funsafe-math-optimizations. */
9819 if (FLOAT_MODE_P (GET_MODE (x))
9820 && ! flag_unsafe_math_optimizations)
9821 return x;
9823 /* The outer operation can only be one of the following: */
9824 if (code != IOR && code != AND && code != XOR
9825 && code != PLUS && code != MINUS)
9826 return x;
9828 lhs = XEXP (x, 0);
9829 rhs = XEXP (x, 1);
9831 /* If either operand is a primitive we can't do anything, so get out
9832 fast. */
9833 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9834 return x;
9836 lhs = expand_compound_operation (lhs);
9837 rhs = expand_compound_operation (rhs);
9838 inner_code = GET_CODE (lhs);
9839 if (inner_code != GET_CODE (rhs))
9840 return x;
9842 /* See if the inner and outer operations distribute. */
9843 switch (inner_code)
9845 case LSHIFTRT:
9846 case ASHIFTRT:
9847 case AND:
9848 case IOR:
9849 /* These all distribute except over PLUS. */
9850 if (code == PLUS || code == MINUS)
9851 return x;
9852 break;
9854 case MULT:
9855 if (code != PLUS && code != MINUS)
9856 return x;
9857 break;
9859 case ASHIFT:
9860 /* This is also a multiply, so it distributes over everything. */
9861 break;
9863 /* This used to handle SUBREG, but this turned out to be counter-
9864 productive, since (subreg (op ...)) usually is not handled by
9865 insn patterns, and this "optimization" therefore transformed
9866 recognizable patterns into unrecognizable ones. Therefore the
9867 SUBREG case was removed from here.
9869 It is possible that distributing SUBREG over arithmetic operations
9870 leads to an intermediate result than can then be optimized further,
9871 e.g. by moving the outer SUBREG to the other side of a SET as done
9872 in simplify_set. This seems to have been the original intent of
9873 handling SUBREGs here.
9875 However, with current GCC this does not appear to actually happen,
9876 at least on major platforms. If some case is found where removing
9877 the SUBREG case here prevents follow-on optimizations, distributing
9878 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9880 default:
9881 return x;
9884 /* Set LHS and RHS to the inner operands (A and B in the example
9885 above) and set OTHER to the common operand (C in the example).
9886 There is only one way to do this unless the inner operation is
9887 commutative. */
9888 if (COMMUTATIVE_ARITH_P (lhs)
9889 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9890 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9891 else if (COMMUTATIVE_ARITH_P (lhs)
9892 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9893 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9894 else if (COMMUTATIVE_ARITH_P (lhs)
9895 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9896 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9897 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9898 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9899 else
9900 return x;
9902 /* Form the new inner operation, seeing if it simplifies first. */
9903 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9905 /* There is one exception to the general way of distributing:
9906 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9907 if (code == XOR && inner_code == IOR)
9909 inner_code = AND;
9910 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9913 /* We may be able to continuing distributing the result, so call
9914 ourselves recursively on the inner operation before forming the
9915 outer operation, which we return. */
9916 return simplify_gen_binary (inner_code, GET_MODE (x),
9917 apply_distributive_law (tem), other);
9920 /* See if X is of the form (* (+ A B) C), and if so convert to
9921 (+ (* A C) (* B C)) and try to simplify.
9923 Most of the time, this results in no change. However, if some of
9924 the operands are the same or inverses of each other, simplifications
9925 will result.
9927 For example, (and (ior A B) (not B)) can occur as the result of
9928 expanding a bit field assignment. When we apply the distributive
9929 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9930 which then simplifies to (and (A (not B))).
9932 Note that no checks happen on the validity of applying the inverse
9933 distributive law. This is pointless since we can do it in the
9934 few places where this routine is called.
9936 N is the index of the term that is decomposed (the arithmetic operation,
9937 i.e. (+ A B) in the first example above). !N is the index of the term that
9938 is distributed, i.e. of C in the first example above. */
9939 static rtx
9940 distribute_and_simplify_rtx (rtx x, int n)
9942 machine_mode mode;
9943 enum rtx_code outer_code, inner_code;
9944 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9946 /* Distributivity is not true for floating point as it can change the
9947 value. So we don't do it unless -funsafe-math-optimizations. */
9948 if (FLOAT_MODE_P (GET_MODE (x))
9949 && ! flag_unsafe_math_optimizations)
9950 return NULL_RTX;
9952 decomposed = XEXP (x, n);
9953 if (!ARITHMETIC_P (decomposed))
9954 return NULL_RTX;
9956 mode = GET_MODE (x);
9957 outer_code = GET_CODE (x);
9958 distributed = XEXP (x, !n);
9960 inner_code = GET_CODE (decomposed);
9961 inner_op0 = XEXP (decomposed, 0);
9962 inner_op1 = XEXP (decomposed, 1);
9964 /* Special case (and (xor B C) (not A)), which is equivalent to
9965 (xor (ior A B) (ior A C)) */
9966 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9968 distributed = XEXP (distributed, 0);
9969 outer_code = IOR;
9972 if (n == 0)
9974 /* Distribute the second term. */
9975 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9976 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9978 else
9980 /* Distribute the first term. */
9981 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9982 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9985 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9986 new_op0, new_op1));
9987 if (GET_CODE (tmp) != outer_code
9988 && (set_src_cost (tmp, mode, optimize_this_for_speed_p)
9989 < set_src_cost (x, mode, optimize_this_for_speed_p)))
9990 return tmp;
9992 return NULL_RTX;
9995 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9996 in MODE. Return an equivalent form, if different from (and VAROP
9997 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9999 static rtx
10000 simplify_and_const_int_1 (scalar_int_mode mode, rtx varop,
10001 unsigned HOST_WIDE_INT constop)
10003 unsigned HOST_WIDE_INT nonzero;
10004 unsigned HOST_WIDE_INT orig_constop;
10005 rtx orig_varop;
10006 int i;
10008 orig_varop = varop;
10009 orig_constop = constop;
10010 if (GET_CODE (varop) == CLOBBER)
10011 return NULL_RTX;
10013 /* Simplify VAROP knowing that we will be only looking at some of the
10014 bits in it.
10016 Note by passing in CONSTOP, we guarantee that the bits not set in
10017 CONSTOP are not significant and will never be examined. We must
10018 ensure that is the case by explicitly masking out those bits
10019 before returning. */
10020 varop = force_to_mode (varop, mode, constop, 0);
10022 /* If VAROP is a CLOBBER, we will fail so return it. */
10023 if (GET_CODE (varop) == CLOBBER)
10024 return varop;
10026 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10027 to VAROP and return the new constant. */
10028 if (CONST_INT_P (varop))
10029 return gen_int_mode (INTVAL (varop) & constop, mode);
10031 /* See what bits may be nonzero in VAROP. Unlike the general case of
10032 a call to nonzero_bits, here we don't care about bits outside
10033 MODE. */
10035 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
10037 /* Turn off all bits in the constant that are known to already be zero.
10038 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10039 which is tested below. */
10041 constop &= nonzero;
10043 /* If we don't have any bits left, return zero. */
10044 if (constop == 0)
10045 return const0_rtx;
10047 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10048 a power of two, we can replace this with an ASHIFT. */
10049 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
10050 && (i = exact_log2 (constop)) >= 0)
10051 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
10053 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10054 or XOR, then try to apply the distributive law. This may eliminate
10055 operations if either branch can be simplified because of the AND.
10056 It may also make some cases more complex, but those cases probably
10057 won't match a pattern either with or without this. */
10059 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
10061 scalar_int_mode varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10062 return
10063 gen_lowpart
10064 (mode,
10065 apply_distributive_law
10066 (simplify_gen_binary (GET_CODE (varop), varop_mode,
10067 simplify_and_const_int (NULL_RTX, varop_mode,
10068 XEXP (varop, 0),
10069 constop),
10070 simplify_and_const_int (NULL_RTX, varop_mode,
10071 XEXP (varop, 1),
10072 constop))));
10075 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10076 the AND and see if one of the operands simplifies to zero. If so, we
10077 may eliminate it. */
10079 if (GET_CODE (varop) == PLUS
10080 && pow2p_hwi (constop + 1))
10082 rtx o0, o1;
10084 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
10085 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
10086 if (o0 == const0_rtx)
10087 return o1;
10088 if (o1 == const0_rtx)
10089 return o0;
10092 /* Make a SUBREG if necessary. If we can't make it, fail. */
10093 varop = gen_lowpart (mode, varop);
10094 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10095 return NULL_RTX;
10097 /* If we are only masking insignificant bits, return VAROP. */
10098 if (constop == nonzero)
10099 return varop;
10101 if (varop == orig_varop && constop == orig_constop)
10102 return NULL_RTX;
10104 /* Otherwise, return an AND. */
10105 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
10109 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10110 in MODE.
10112 Return an equivalent form, if different from X. Otherwise, return X. If
10113 X is zero, we are to always construct the equivalent form. */
10115 static rtx
10116 simplify_and_const_int (rtx x, scalar_int_mode mode, rtx varop,
10117 unsigned HOST_WIDE_INT constop)
10119 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
10120 if (tem)
10121 return tem;
10123 if (!x)
10124 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
10125 gen_int_mode (constop, mode));
10126 if (GET_MODE (x) != mode)
10127 x = gen_lowpart (mode, x);
10128 return x;
10131 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10132 We don't care about bits outside of those defined in MODE.
10134 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10135 a shift, AND, or zero_extract, we can do better. */
10137 static rtx
10138 reg_nonzero_bits_for_combine (const_rtx x, scalar_int_mode xmode,
10139 scalar_int_mode mode,
10140 unsigned HOST_WIDE_INT *nonzero)
10142 rtx tem;
10143 reg_stat_type *rsp;
10145 /* If X is a register whose nonzero bits value is current, use it.
10146 Otherwise, if X is a register whose value we can find, use that
10147 value. Otherwise, use the previously-computed global nonzero bits
10148 for this register. */
10150 rsp = &reg_stat[REGNO (x)];
10151 if (rsp->last_set_value != 0
10152 && (rsp->last_set_mode == mode
10153 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
10154 && GET_MODE_CLASS (mode) == MODE_INT))
10155 && ((rsp->last_set_label >= label_tick_ebb_start
10156 && rsp->last_set_label < label_tick)
10157 || (rsp->last_set_label == label_tick
10158 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10159 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10160 && REGNO (x) < reg_n_sets_max
10161 && REG_N_SETS (REGNO (x)) == 1
10162 && !REGNO_REG_SET_P
10163 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10164 REGNO (x)))))
10166 /* Note that, even if the precision of last_set_mode is lower than that
10167 of mode, record_value_for_reg invoked nonzero_bits on the register
10168 with nonzero_bits_mode (because last_set_mode is necessarily integral
10169 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10170 are all valid, hence in mode too since nonzero_bits_mode is defined
10171 to the largest HWI_COMPUTABLE_MODE_P mode. */
10172 *nonzero &= rsp->last_set_nonzero_bits;
10173 return NULL;
10176 tem = get_last_value (x);
10177 if (tem)
10179 if (SHORT_IMMEDIATES_SIGN_EXTEND)
10180 tem = sign_extend_short_imm (tem, xmode, GET_MODE_PRECISION (mode));
10182 return tem;
10185 if (nonzero_sign_valid && rsp->nonzero_bits)
10187 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
10189 if (GET_MODE_PRECISION (xmode) < GET_MODE_PRECISION (mode))
10190 /* We don't know anything about the upper bits. */
10191 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (xmode);
10193 *nonzero &= mask;
10196 return NULL;
10199 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10200 end of X that are known to be equal to the sign bit. X will be used
10201 in mode MODE; the returned value will always be between 1 and the
10202 number of bits in MODE. */
10204 static rtx
10205 reg_num_sign_bit_copies_for_combine (const_rtx x, scalar_int_mode xmode,
10206 scalar_int_mode mode,
10207 unsigned int *result)
10209 rtx tem;
10210 reg_stat_type *rsp;
10212 rsp = &reg_stat[REGNO (x)];
10213 if (rsp->last_set_value != 0
10214 && rsp->last_set_mode == mode
10215 && ((rsp->last_set_label >= label_tick_ebb_start
10216 && rsp->last_set_label < label_tick)
10217 || (rsp->last_set_label == label_tick
10218 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10219 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10220 && REGNO (x) < reg_n_sets_max
10221 && REG_N_SETS (REGNO (x)) == 1
10222 && !REGNO_REG_SET_P
10223 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10224 REGNO (x)))))
10226 *result = rsp->last_set_sign_bit_copies;
10227 return NULL;
10230 tem = get_last_value (x);
10231 if (tem != 0)
10232 return tem;
10234 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
10235 && GET_MODE_PRECISION (xmode) == GET_MODE_PRECISION (mode))
10236 *result = rsp->sign_bit_copies;
10238 return NULL;
10241 /* Return the number of "extended" bits there are in X, when interpreted
10242 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10243 unsigned quantities, this is the number of high-order zero bits.
10244 For signed quantities, this is the number of copies of the sign bit
10245 minus 1. In both case, this function returns the number of "spare"
10246 bits. For example, if two quantities for which this function returns
10247 at least 1 are added, the addition is known not to overflow.
10249 This function will always return 0 unless called during combine, which
10250 implies that it must be called from a define_split. */
10252 unsigned int
10253 extended_count (const_rtx x, machine_mode mode, int unsignedp)
10255 if (nonzero_sign_valid == 0)
10256 return 0;
10258 scalar_int_mode int_mode;
10259 return (unsignedp
10260 ? (is_a <scalar_int_mode> (mode, &int_mode)
10261 && HWI_COMPUTABLE_MODE_P (int_mode)
10262 ? (unsigned int) (GET_MODE_PRECISION (int_mode) - 1
10263 - floor_log2 (nonzero_bits (x, int_mode)))
10264 : 0)
10265 : num_sign_bit_copies (x, mode) - 1);
10268 /* This function is called from `simplify_shift_const' to merge two
10269 outer operations. Specifically, we have already found that we need
10270 to perform operation *POP0 with constant *PCONST0 at the outermost
10271 position. We would now like to also perform OP1 with constant CONST1
10272 (with *POP0 being done last).
10274 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10275 the resulting operation. *PCOMP_P is set to 1 if we would need to
10276 complement the innermost operand, otherwise it is unchanged.
10278 MODE is the mode in which the operation will be done. No bits outside
10279 the width of this mode matter. It is assumed that the width of this mode
10280 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10282 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10283 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10284 result is simply *PCONST0.
10286 If the resulting operation cannot be expressed as one operation, we
10287 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10289 static int
10290 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10292 enum rtx_code op0 = *pop0;
10293 HOST_WIDE_INT const0 = *pconst0;
10295 const0 &= GET_MODE_MASK (mode);
10296 const1 &= GET_MODE_MASK (mode);
10298 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10299 if (op0 == AND)
10300 const1 &= const0;
10302 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10303 if OP0 is SET. */
10305 if (op1 == UNKNOWN || op0 == SET)
10306 return 1;
10308 else if (op0 == UNKNOWN)
10309 op0 = op1, const0 = const1;
10311 else if (op0 == op1)
10313 switch (op0)
10315 case AND:
10316 const0 &= const1;
10317 break;
10318 case IOR:
10319 const0 |= const1;
10320 break;
10321 case XOR:
10322 const0 ^= const1;
10323 break;
10324 case PLUS:
10325 const0 += const1;
10326 break;
10327 case NEG:
10328 op0 = UNKNOWN;
10329 break;
10330 default:
10331 break;
10335 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10336 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
10337 return 0;
10339 /* If the two constants aren't the same, we can't do anything. The
10340 remaining six cases can all be done. */
10341 else if (const0 != const1)
10342 return 0;
10344 else
10345 switch (op0)
10347 case IOR:
10348 if (op1 == AND)
10349 /* (a & b) | b == b */
10350 op0 = SET;
10351 else /* op1 == XOR */
10352 /* (a ^ b) | b == a | b */
10354 break;
10356 case XOR:
10357 if (op1 == AND)
10358 /* (a & b) ^ b == (~a) & b */
10359 op0 = AND, *pcomp_p = 1;
10360 else /* op1 == IOR */
10361 /* (a | b) ^ b == a & ~b */
10362 op0 = AND, const0 = ~const0;
10363 break;
10365 case AND:
10366 if (op1 == IOR)
10367 /* (a | b) & b == b */
10368 op0 = SET;
10369 else /* op1 == XOR */
10370 /* (a ^ b) & b) == (~a) & b */
10371 *pcomp_p = 1;
10372 break;
10373 default:
10374 break;
10377 /* Check for NO-OP cases. */
10378 const0 &= GET_MODE_MASK (mode);
10379 if (const0 == 0
10380 && (op0 == IOR || op0 == XOR || op0 == PLUS))
10381 op0 = UNKNOWN;
10382 else if (const0 == 0 && op0 == AND)
10383 op0 = SET;
10384 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
10385 && op0 == AND)
10386 op0 = UNKNOWN;
10388 *pop0 = op0;
10390 /* ??? Slightly redundant with the above mask, but not entirely.
10391 Moving this above means we'd have to sign-extend the mode mask
10392 for the final test. */
10393 if (op0 != UNKNOWN && op0 != NEG)
10394 *pconst0 = trunc_int_for_mode (const0, mode);
10396 return 1;
10399 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10400 the shift in. The original shift operation CODE is performed on OP in
10401 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10402 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10403 result of the shift is subject to operation OUTER_CODE with operand
10404 OUTER_CONST. */
10406 static scalar_int_mode
10407 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
10408 scalar_int_mode orig_mode, scalar_int_mode mode,
10409 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
10411 gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
10413 /* In general we can't perform in wider mode for right shift and rotate. */
10414 switch (code)
10416 case ASHIFTRT:
10417 /* We can still widen if the bits brought in from the left are identical
10418 to the sign bit of ORIG_MODE. */
10419 if (num_sign_bit_copies (op, mode)
10420 > (unsigned) (GET_MODE_PRECISION (mode)
10421 - GET_MODE_PRECISION (orig_mode)))
10422 return mode;
10423 return orig_mode;
10425 case LSHIFTRT:
10426 /* Similarly here but with zero bits. */
10427 if (HWI_COMPUTABLE_MODE_P (mode)
10428 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
10429 return mode;
10431 /* We can also widen if the bits brought in will be masked off. This
10432 operation is performed in ORIG_MODE. */
10433 if (outer_code == AND)
10435 int care_bits = low_bitmask_len (orig_mode, outer_const);
10437 if (care_bits >= 0
10438 && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
10439 return mode;
10441 /* fall through */
10443 case ROTATE:
10444 return orig_mode;
10446 case ROTATERT:
10447 gcc_unreachable ();
10449 default:
10450 return mode;
10454 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10455 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10456 if we cannot simplify it. Otherwise, return a simplified value.
10458 The shift is normally computed in the widest mode we find in VAROP, as
10459 long as it isn't a different number of words than RESULT_MODE. Exceptions
10460 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10462 static rtx
10463 simplify_shift_const_1 (enum rtx_code code, machine_mode result_mode,
10464 rtx varop, int orig_count)
10466 enum rtx_code orig_code = code;
10467 rtx orig_varop = varop;
10468 int count, log2;
10469 machine_mode mode = result_mode;
10470 machine_mode shift_mode;
10471 scalar_int_mode tmode, inner_mode, int_mode, int_varop_mode, int_result_mode;
10472 /* We form (outer_op (code varop count) (outer_const)). */
10473 enum rtx_code outer_op = UNKNOWN;
10474 HOST_WIDE_INT outer_const = 0;
10475 int complement_p = 0;
10476 rtx new_rtx, x;
10478 /* Make sure and truncate the "natural" shift on the way in. We don't
10479 want to do this inside the loop as it makes it more difficult to
10480 combine shifts. */
10481 if (SHIFT_COUNT_TRUNCATED)
10482 orig_count &= GET_MODE_UNIT_BITSIZE (mode) - 1;
10484 /* If we were given an invalid count, don't do anything except exactly
10485 what was requested. */
10487 if (orig_count < 0 || orig_count >= (int) GET_MODE_UNIT_PRECISION (mode))
10488 return NULL_RTX;
10490 count = orig_count;
10492 /* Unless one of the branches of the `if' in this loop does a `continue',
10493 we will `break' the loop after the `if'. */
10495 while (count != 0)
10497 /* If we have an operand of (clobber (const_int 0)), fail. */
10498 if (GET_CODE (varop) == CLOBBER)
10499 return NULL_RTX;
10501 /* Convert ROTATERT to ROTATE. */
10502 if (code == ROTATERT)
10504 unsigned int bitsize = GET_MODE_UNIT_PRECISION (result_mode);
10505 code = ROTATE;
10506 count = bitsize - count;
10509 shift_mode = result_mode;
10510 if (shift_mode != mode)
10512 /* We only change the modes of scalar shifts. */
10513 int_mode = as_a <scalar_int_mode> (mode);
10514 int_result_mode = as_a <scalar_int_mode> (result_mode);
10515 shift_mode = try_widen_shift_mode (code, varop, count,
10516 int_result_mode, int_mode,
10517 outer_op, outer_const);
10520 scalar_int_mode shift_unit_mode
10521 = as_a <scalar_int_mode> (GET_MODE_INNER (shift_mode));
10523 /* Handle cases where the count is greater than the size of the mode
10524 minus 1. For ASHIFT, use the size minus one as the count (this can
10525 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10526 take the count modulo the size. For other shifts, the result is
10527 zero.
10529 Since these shifts are being produced by the compiler by combining
10530 multiple operations, each of which are defined, we know what the
10531 result is supposed to be. */
10533 if (count > (GET_MODE_PRECISION (shift_unit_mode) - 1))
10535 if (code == ASHIFTRT)
10536 count = GET_MODE_PRECISION (shift_unit_mode) - 1;
10537 else if (code == ROTATE || code == ROTATERT)
10538 count %= GET_MODE_PRECISION (shift_unit_mode);
10539 else
10541 /* We can't simply return zero because there may be an
10542 outer op. */
10543 varop = const0_rtx;
10544 count = 0;
10545 break;
10549 /* If we discovered we had to complement VAROP, leave. Making a NOT
10550 here would cause an infinite loop. */
10551 if (complement_p)
10552 break;
10554 if (shift_mode == shift_unit_mode)
10556 /* An arithmetic right shift of a quantity known to be -1 or 0
10557 is a no-op. */
10558 if (code == ASHIFTRT
10559 && (num_sign_bit_copies (varop, shift_unit_mode)
10560 == GET_MODE_PRECISION (shift_unit_mode)))
10562 count = 0;
10563 break;
10566 /* If we are doing an arithmetic right shift and discarding all but
10567 the sign bit copies, this is equivalent to doing a shift by the
10568 bitsize minus one. Convert it into that shift because it will
10569 often allow other simplifications. */
10571 if (code == ASHIFTRT
10572 && (count + num_sign_bit_copies (varop, shift_unit_mode)
10573 >= GET_MODE_PRECISION (shift_unit_mode)))
10574 count = GET_MODE_PRECISION (shift_unit_mode) - 1;
10576 /* We simplify the tests below and elsewhere by converting
10577 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10578 `make_compound_operation' will convert it to an ASHIFTRT for
10579 those machines (such as VAX) that don't have an LSHIFTRT. */
10580 if (code == ASHIFTRT
10581 && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10582 && val_signbit_known_clear_p (shift_unit_mode,
10583 nonzero_bits (varop,
10584 shift_unit_mode)))
10585 code = LSHIFTRT;
10587 if (((code == LSHIFTRT
10588 && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10589 && !(nonzero_bits (varop, shift_unit_mode) >> count))
10590 || (code == ASHIFT
10591 && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10592 && !((nonzero_bits (varop, shift_unit_mode) << count)
10593 & GET_MODE_MASK (shift_unit_mode))))
10594 && !side_effects_p (varop))
10595 varop = const0_rtx;
10598 switch (GET_CODE (varop))
10600 case SIGN_EXTEND:
10601 case ZERO_EXTEND:
10602 case SIGN_EXTRACT:
10603 case ZERO_EXTRACT:
10604 new_rtx = expand_compound_operation (varop);
10605 if (new_rtx != varop)
10607 varop = new_rtx;
10608 continue;
10610 break;
10612 case MEM:
10613 /* The following rules apply only to scalars. */
10614 if (shift_mode != shift_unit_mode)
10615 break;
10616 int_mode = as_a <scalar_int_mode> (mode);
10618 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10619 minus the width of a smaller mode, we can do this with a
10620 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10621 if ((code == ASHIFTRT || code == LSHIFTRT)
10622 && ! mode_dependent_address_p (XEXP (varop, 0),
10623 MEM_ADDR_SPACE (varop))
10624 && ! MEM_VOLATILE_P (varop)
10625 && (int_mode_for_size (GET_MODE_BITSIZE (int_mode) - count, 1)
10626 .exists (&tmode)))
10628 new_rtx = adjust_address_nv (varop, tmode,
10629 BYTES_BIG_ENDIAN ? 0
10630 : count / BITS_PER_UNIT);
10632 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
10633 : ZERO_EXTEND, int_mode, new_rtx);
10634 count = 0;
10635 continue;
10637 break;
10639 case SUBREG:
10640 /* The following rules apply only to scalars. */
10641 if (shift_mode != shift_unit_mode)
10642 break;
10643 int_mode = as_a <scalar_int_mode> (mode);
10644 int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10646 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10647 the same number of words as what we've seen so far. Then store
10648 the widest mode in MODE. */
10649 if (subreg_lowpart_p (varop)
10650 && is_int_mode (GET_MODE (SUBREG_REG (varop)), &inner_mode)
10651 && GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_varop_mode)
10652 && (CEIL (GET_MODE_SIZE (inner_mode), UNITS_PER_WORD)
10653 == CEIL (GET_MODE_SIZE (int_mode), UNITS_PER_WORD))
10654 && GET_MODE_CLASS (int_varop_mode) == MODE_INT)
10656 varop = SUBREG_REG (varop);
10657 if (GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_mode))
10658 mode = inner_mode;
10659 continue;
10661 break;
10663 case MULT:
10664 /* Some machines use MULT instead of ASHIFT because MULT
10665 is cheaper. But it is still better on those machines to
10666 merge two shifts into one. */
10667 if (CONST_INT_P (XEXP (varop, 1))
10668 && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10670 rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10671 varop = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10672 XEXP (varop, 0), log2_rtx);
10673 continue;
10675 break;
10677 case UDIV:
10678 /* Similar, for when divides are cheaper. */
10679 if (CONST_INT_P (XEXP (varop, 1))
10680 && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10682 rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10683 varop = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10684 XEXP (varop, 0), log2_rtx);
10685 continue;
10687 break;
10689 case ASHIFTRT:
10690 /* If we are extracting just the sign bit of an arithmetic
10691 right shift, that shift is not needed. However, the sign
10692 bit of a wider mode may be different from what would be
10693 interpreted as the sign bit in a narrower mode, so, if
10694 the result is narrower, don't discard the shift. */
10695 if (code == LSHIFTRT
10696 && count == (GET_MODE_UNIT_BITSIZE (result_mode) - 1)
10697 && (GET_MODE_UNIT_BITSIZE (result_mode)
10698 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop))))
10700 varop = XEXP (varop, 0);
10701 continue;
10704 /* fall through */
10706 case LSHIFTRT:
10707 case ASHIFT:
10708 case ROTATE:
10709 /* The following rules apply only to scalars. */
10710 if (shift_mode != shift_unit_mode)
10711 break;
10712 int_mode = as_a <scalar_int_mode> (mode);
10713 int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10714 int_result_mode = as_a <scalar_int_mode> (result_mode);
10716 /* Here we have two nested shifts. The result is usually the
10717 AND of a new shift with a mask. We compute the result below. */
10718 if (CONST_INT_P (XEXP (varop, 1))
10719 && INTVAL (XEXP (varop, 1)) >= 0
10720 && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (int_varop_mode)
10721 && HWI_COMPUTABLE_MODE_P (int_result_mode)
10722 && HWI_COMPUTABLE_MODE_P (int_mode))
10724 enum rtx_code first_code = GET_CODE (varop);
10725 unsigned int first_count = INTVAL (XEXP (varop, 1));
10726 unsigned HOST_WIDE_INT mask;
10727 rtx mask_rtx;
10729 /* We have one common special case. We can't do any merging if
10730 the inner code is an ASHIFTRT of a smaller mode. However, if
10731 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10732 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10733 we can convert it to
10734 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10735 This simplifies certain SIGN_EXTEND operations. */
10736 if (code == ASHIFT && first_code == ASHIFTRT
10737 && count == (GET_MODE_PRECISION (int_result_mode)
10738 - GET_MODE_PRECISION (int_varop_mode)))
10740 /* C3 has the low-order C1 bits zero. */
10742 mask = GET_MODE_MASK (int_mode)
10743 & ~((HOST_WIDE_INT_1U << first_count) - 1);
10745 varop = simplify_and_const_int (NULL_RTX, int_result_mode,
10746 XEXP (varop, 0), mask);
10747 varop = simplify_shift_const (NULL_RTX, ASHIFT,
10748 int_result_mode, varop, count);
10749 count = first_count;
10750 code = ASHIFTRT;
10751 continue;
10754 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10755 than C1 high-order bits equal to the sign bit, we can convert
10756 this to either an ASHIFT or an ASHIFTRT depending on the
10757 two counts.
10759 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10761 if (code == ASHIFTRT && first_code == ASHIFT
10762 && int_varop_mode == shift_unit_mode
10763 && (num_sign_bit_copies (XEXP (varop, 0), shift_unit_mode)
10764 > first_count))
10766 varop = XEXP (varop, 0);
10767 count -= first_count;
10768 if (count < 0)
10770 count = -count;
10771 code = ASHIFT;
10774 continue;
10777 /* There are some cases we can't do. If CODE is ASHIFTRT,
10778 we can only do this if FIRST_CODE is also ASHIFTRT.
10780 We can't do the case when CODE is ROTATE and FIRST_CODE is
10781 ASHIFTRT.
10783 If the mode of this shift is not the mode of the outer shift,
10784 we can't do this if either shift is a right shift or ROTATE.
10786 Finally, we can't do any of these if the mode is too wide
10787 unless the codes are the same.
10789 Handle the case where the shift codes are the same
10790 first. */
10792 if (code == first_code)
10794 if (int_varop_mode != int_result_mode
10795 && (code == ASHIFTRT || code == LSHIFTRT
10796 || code == ROTATE))
10797 break;
10799 count += first_count;
10800 varop = XEXP (varop, 0);
10801 continue;
10804 if (code == ASHIFTRT
10805 || (code == ROTATE && first_code == ASHIFTRT)
10806 || GET_MODE_PRECISION (int_mode) > HOST_BITS_PER_WIDE_INT
10807 || (int_varop_mode != int_result_mode
10808 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10809 || first_code == ROTATE
10810 || code == ROTATE)))
10811 break;
10813 /* To compute the mask to apply after the shift, shift the
10814 nonzero bits of the inner shift the same way the
10815 outer shift will. */
10817 mask_rtx = gen_int_mode (nonzero_bits (varop, int_varop_mode),
10818 int_result_mode);
10819 rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
10820 mask_rtx
10821 = simplify_const_binary_operation (code, int_result_mode,
10822 mask_rtx, count_rtx);
10824 /* Give up if we can't compute an outer operation to use. */
10825 if (mask_rtx == 0
10826 || !CONST_INT_P (mask_rtx)
10827 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10828 INTVAL (mask_rtx),
10829 int_result_mode, &complement_p))
10830 break;
10832 /* If the shifts are in the same direction, we add the
10833 counts. Otherwise, we subtract them. */
10834 if ((code == ASHIFTRT || code == LSHIFTRT)
10835 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10836 count += first_count;
10837 else
10838 count -= first_count;
10840 /* If COUNT is positive, the new shift is usually CODE,
10841 except for the two exceptions below, in which case it is
10842 FIRST_CODE. If the count is negative, FIRST_CODE should
10843 always be used */
10844 if (count > 0
10845 && ((first_code == ROTATE && code == ASHIFT)
10846 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10847 code = first_code;
10848 else if (count < 0)
10849 code = first_code, count = -count;
10851 varop = XEXP (varop, 0);
10852 continue;
10855 /* If we have (A << B << C) for any shift, we can convert this to
10856 (A << C << B). This wins if A is a constant. Only try this if
10857 B is not a constant. */
10859 else if (GET_CODE (varop) == code
10860 && CONST_INT_P (XEXP (varop, 0))
10861 && !CONST_INT_P (XEXP (varop, 1)))
10863 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10864 sure the result will be masked. See PR70222. */
10865 if (code == LSHIFTRT
10866 && int_mode != int_result_mode
10867 && !merge_outer_ops (&outer_op, &outer_const, AND,
10868 GET_MODE_MASK (int_result_mode)
10869 >> orig_count, int_result_mode,
10870 &complement_p))
10871 break;
10872 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10873 up outer sign extension (often left and right shift) is
10874 hardly more efficient than the original. See PR70429. */
10875 if (code == ASHIFTRT && int_mode != int_result_mode)
10876 break;
10878 rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
10879 rtx new_rtx = simplify_const_binary_operation (code, int_mode,
10880 XEXP (varop, 0),
10881 count_rtx);
10882 varop = gen_rtx_fmt_ee (code, int_mode, new_rtx, XEXP (varop, 1));
10883 count = 0;
10884 continue;
10886 break;
10888 case NOT:
10889 /* The following rules apply only to scalars. */
10890 if (shift_mode != shift_unit_mode)
10891 break;
10893 /* Make this fit the case below. */
10894 varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10895 continue;
10897 case IOR:
10898 case AND:
10899 case XOR:
10900 /* The following rules apply only to scalars. */
10901 if (shift_mode != shift_unit_mode)
10902 break;
10903 int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10904 int_result_mode = as_a <scalar_int_mode> (result_mode);
10906 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10907 with C the size of VAROP - 1 and the shift is logical if
10908 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10909 we have an (le X 0) operation. If we have an arithmetic shift
10910 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10911 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10913 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10914 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10915 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10916 && (code == LSHIFTRT || code == ASHIFTRT)
10917 && count == (GET_MODE_PRECISION (int_varop_mode) - 1)
10918 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10920 count = 0;
10921 varop = gen_rtx_LE (int_varop_mode, XEXP (varop, 1),
10922 const0_rtx);
10924 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10925 varop = gen_rtx_NEG (int_varop_mode, varop);
10927 continue;
10930 /* If we have (shift (logical)), move the logical to the outside
10931 to allow it to possibly combine with another logical and the
10932 shift to combine with another shift. This also canonicalizes to
10933 what a ZERO_EXTRACT looks like. Also, some machines have
10934 (and (shift)) insns. */
10936 if (CONST_INT_P (XEXP (varop, 1))
10937 /* We can't do this if we have (ashiftrt (xor)) and the
10938 constant has its sign bit set in shift_unit_mode with
10939 shift_unit_mode wider than result_mode. */
10940 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10941 && int_result_mode != shift_unit_mode
10942 && trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10943 shift_unit_mode) < 0)
10944 && (new_rtx = simplify_const_binary_operation
10945 (code, int_result_mode,
10946 gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
10947 gen_int_shift_amount (int_result_mode, count))) != 0
10948 && CONST_INT_P (new_rtx)
10949 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10950 INTVAL (new_rtx), int_result_mode,
10951 &complement_p))
10953 varop = XEXP (varop, 0);
10954 continue;
10957 /* If we can't do that, try to simplify the shift in each arm of the
10958 logical expression, make a new logical expression, and apply
10959 the inverse distributive law. This also can't be done for
10960 (ashiftrt (xor)) where we've widened the shift and the constant
10961 changes the sign bit. */
10962 if (CONST_INT_P (XEXP (varop, 1))
10963 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10964 && int_result_mode != shift_unit_mode
10965 && trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10966 shift_unit_mode) < 0))
10968 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
10969 XEXP (varop, 0), count);
10970 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
10971 XEXP (varop, 1), count);
10973 varop = simplify_gen_binary (GET_CODE (varop), shift_unit_mode,
10974 lhs, rhs);
10975 varop = apply_distributive_law (varop);
10977 count = 0;
10978 continue;
10980 break;
10982 case EQ:
10983 /* The following rules apply only to scalars. */
10984 if (shift_mode != shift_unit_mode)
10985 break;
10986 int_result_mode = as_a <scalar_int_mode> (result_mode);
10988 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10989 says that the sign bit can be tested, FOO has mode MODE, C is
10990 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10991 that may be nonzero. */
10992 if (code == LSHIFTRT
10993 && XEXP (varop, 1) == const0_rtx
10994 && GET_MODE (XEXP (varop, 0)) == int_result_mode
10995 && count == (GET_MODE_PRECISION (int_result_mode) - 1)
10996 && HWI_COMPUTABLE_MODE_P (int_result_mode)
10997 && STORE_FLAG_VALUE == -1
10998 && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
10999 && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
11000 int_result_mode, &complement_p))
11002 varop = XEXP (varop, 0);
11003 count = 0;
11004 continue;
11006 break;
11008 case NEG:
11009 /* The following rules apply only to scalars. */
11010 if (shift_mode != shift_unit_mode)
11011 break;
11012 int_result_mode = as_a <scalar_int_mode> (result_mode);
11014 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11015 than the number of bits in the mode is equivalent to A. */
11016 if (code == LSHIFTRT
11017 && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11018 && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1)
11020 varop = XEXP (varop, 0);
11021 count = 0;
11022 continue;
11025 /* NEG commutes with ASHIFT since it is multiplication. Move the
11026 NEG outside to allow shifts to combine. */
11027 if (code == ASHIFT
11028 && merge_outer_ops (&outer_op, &outer_const, NEG, 0,
11029 int_result_mode, &complement_p))
11031 varop = XEXP (varop, 0);
11032 continue;
11034 break;
11036 case PLUS:
11037 /* The following rules apply only to scalars. */
11038 if (shift_mode != shift_unit_mode)
11039 break;
11040 int_result_mode = as_a <scalar_int_mode> (result_mode);
11042 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11043 is one less than the number of bits in the mode is
11044 equivalent to (xor A 1). */
11045 if (code == LSHIFTRT
11046 && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11047 && XEXP (varop, 1) == constm1_rtx
11048 && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
11049 && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
11050 int_result_mode, &complement_p))
11052 count = 0;
11053 varop = XEXP (varop, 0);
11054 continue;
11057 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11058 that might be nonzero in BAR are those being shifted out and those
11059 bits are known zero in FOO, we can replace the PLUS with FOO.
11060 Similarly in the other operand order. This code occurs when
11061 we are computing the size of a variable-size array. */
11063 if ((code == ASHIFTRT || code == LSHIFTRT)
11064 && count < HOST_BITS_PER_WIDE_INT
11065 && nonzero_bits (XEXP (varop, 1), int_result_mode) >> count == 0
11066 && (nonzero_bits (XEXP (varop, 1), int_result_mode)
11067 & nonzero_bits (XEXP (varop, 0), int_result_mode)) == 0)
11069 varop = XEXP (varop, 0);
11070 continue;
11072 else if ((code == ASHIFTRT || code == LSHIFTRT)
11073 && count < HOST_BITS_PER_WIDE_INT
11074 && HWI_COMPUTABLE_MODE_P (int_result_mode)
11075 && (nonzero_bits (XEXP (varop, 0), int_result_mode)
11076 >> count) == 0
11077 && (nonzero_bits (XEXP (varop, 0), int_result_mode)
11078 & nonzero_bits (XEXP (varop, 1), int_result_mode)) == 0)
11080 varop = XEXP (varop, 1);
11081 continue;
11084 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11085 if (code == ASHIFT
11086 && CONST_INT_P (XEXP (varop, 1))
11087 && (new_rtx = simplify_const_binary_operation
11088 (ASHIFT, int_result_mode,
11089 gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11090 gen_int_shift_amount (int_result_mode, count))) != 0
11091 && CONST_INT_P (new_rtx)
11092 && merge_outer_ops (&outer_op, &outer_const, PLUS,
11093 INTVAL (new_rtx), int_result_mode,
11094 &complement_p))
11096 varop = XEXP (varop, 0);
11097 continue;
11100 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11101 signbit', and attempt to change the PLUS to an XOR and move it to
11102 the outer operation as is done above in the AND/IOR/XOR case
11103 leg for shift(logical). See details in logical handling above
11104 for reasoning in doing so. */
11105 if (code == LSHIFTRT
11106 && CONST_INT_P (XEXP (varop, 1))
11107 && mode_signbit_p (int_result_mode, XEXP (varop, 1))
11108 && (new_rtx = simplify_const_binary_operation
11109 (code, int_result_mode,
11110 gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11111 gen_int_shift_amount (int_result_mode, count))) != 0
11112 && CONST_INT_P (new_rtx)
11113 && merge_outer_ops (&outer_op, &outer_const, XOR,
11114 INTVAL (new_rtx), int_result_mode,
11115 &complement_p))
11117 varop = XEXP (varop, 0);
11118 continue;
11121 break;
11123 case MINUS:
11124 /* The following rules apply only to scalars. */
11125 if (shift_mode != shift_unit_mode)
11126 break;
11127 int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
11129 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11130 with C the size of VAROP - 1 and the shift is logical if
11131 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11132 we have a (gt X 0) operation. If the shift is arithmetic with
11133 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11134 we have a (neg (gt X 0)) operation. */
11136 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
11137 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
11138 && count == (GET_MODE_PRECISION (int_varop_mode) - 1)
11139 && (code == LSHIFTRT || code == ASHIFTRT)
11140 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11141 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
11142 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
11144 count = 0;
11145 varop = gen_rtx_GT (int_varop_mode, XEXP (varop, 1),
11146 const0_rtx);
11148 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
11149 varop = gen_rtx_NEG (int_varop_mode, varop);
11151 continue;
11153 break;
11155 case TRUNCATE:
11156 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11157 if the truncate does not affect the value. */
11158 if (code == LSHIFTRT
11159 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
11160 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11161 && (INTVAL (XEXP (XEXP (varop, 0), 1))
11162 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop, 0)))
11163 - GET_MODE_UNIT_PRECISION (GET_MODE (varop)))))
11165 rtx varop_inner = XEXP (varop, 0);
11166 int new_count = count + INTVAL (XEXP (varop_inner, 1));
11167 rtx new_count_rtx = gen_int_shift_amount (GET_MODE (varop_inner),
11168 new_count);
11169 varop_inner = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
11170 XEXP (varop_inner, 0),
11171 new_count_rtx);
11172 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
11173 count = 0;
11174 continue;
11176 break;
11178 default:
11179 break;
11182 break;
11185 shift_mode = result_mode;
11186 if (shift_mode != mode)
11188 /* We only change the modes of scalar shifts. */
11189 int_mode = as_a <scalar_int_mode> (mode);
11190 int_result_mode = as_a <scalar_int_mode> (result_mode);
11191 shift_mode = try_widen_shift_mode (code, varop, count, int_result_mode,
11192 int_mode, outer_op, outer_const);
11195 /* We have now finished analyzing the shift. The result should be
11196 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11197 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11198 to the result of the shift. OUTER_CONST is the relevant constant,
11199 but we must turn off all bits turned off in the shift. */
11201 if (outer_op == UNKNOWN
11202 && orig_code == code && orig_count == count
11203 && varop == orig_varop
11204 && shift_mode == GET_MODE (varop))
11205 return NULL_RTX;
11207 /* Make a SUBREG if necessary. If we can't make it, fail. */
11208 varop = gen_lowpart (shift_mode, varop);
11209 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
11210 return NULL_RTX;
11212 /* If we have an outer operation and we just made a shift, it is
11213 possible that we could have simplified the shift were it not
11214 for the outer operation. So try to do the simplification
11215 recursively. */
11217 if (outer_op != UNKNOWN)
11218 x = simplify_shift_const_1 (code, shift_mode, varop, count);
11219 else
11220 x = NULL_RTX;
11222 if (x == NULL_RTX)
11223 x = simplify_gen_binary (code, shift_mode, varop,
11224 gen_int_shift_amount (shift_mode, count));
11226 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11227 turn off all the bits that the shift would have turned off. */
11228 if (orig_code == LSHIFTRT && result_mode != shift_mode)
11229 /* We only change the modes of scalar shifts. */
11230 x = simplify_and_const_int (NULL_RTX, as_a <scalar_int_mode> (shift_mode),
11231 x, GET_MODE_MASK (result_mode) >> orig_count);
11233 /* Do the remainder of the processing in RESULT_MODE. */
11234 x = gen_lowpart_or_truncate (result_mode, x);
11236 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11237 operation. */
11238 if (complement_p)
11239 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
11241 if (outer_op != UNKNOWN)
11243 int_result_mode = as_a <scalar_int_mode> (result_mode);
11245 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
11246 && GET_MODE_PRECISION (int_result_mode) < HOST_BITS_PER_WIDE_INT)
11247 outer_const = trunc_int_for_mode (outer_const, int_result_mode);
11249 if (outer_op == AND)
11250 x = simplify_and_const_int (NULL_RTX, int_result_mode, x, outer_const);
11251 else if (outer_op == SET)
11253 /* This means that we have determined that the result is
11254 equivalent to a constant. This should be rare. */
11255 if (!side_effects_p (x))
11256 x = GEN_INT (outer_const);
11258 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
11259 x = simplify_gen_unary (outer_op, int_result_mode, x, int_result_mode);
11260 else
11261 x = simplify_gen_binary (outer_op, int_result_mode, x,
11262 GEN_INT (outer_const));
11265 return x;
11268 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11269 The result of the shift is RESULT_MODE. If we cannot simplify it,
11270 return X or, if it is NULL, synthesize the expression with
11271 simplify_gen_binary. Otherwise, return a simplified value.
11273 The shift is normally computed in the widest mode we find in VAROP, as
11274 long as it isn't a different number of words than RESULT_MODE. Exceptions
11275 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11277 static rtx
11278 simplify_shift_const (rtx x, enum rtx_code code, machine_mode result_mode,
11279 rtx varop, int count)
11281 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
11282 if (tem)
11283 return tem;
11285 if (!x)
11286 x = simplify_gen_binary (code, GET_MODE (varop), varop,
11287 gen_int_shift_amount (GET_MODE (varop), count));
11288 if (GET_MODE (x) != result_mode)
11289 x = gen_lowpart (result_mode, x);
11290 return x;
11294 /* A subroutine of recog_for_combine. See there for arguments and
11295 return value. */
11297 static int
11298 recog_for_combine_1 (rtx *pnewpat, rtx_insn *insn, rtx *pnotes)
11300 rtx pat = *pnewpat;
11301 rtx pat_without_clobbers;
11302 int insn_code_number;
11303 int num_clobbers_to_add = 0;
11304 int i;
11305 rtx notes = NULL_RTX;
11306 rtx old_notes, old_pat;
11307 int old_icode;
11309 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11310 we use to indicate that something didn't match. If we find such a
11311 thing, force rejection. */
11312 if (GET_CODE (pat) == PARALLEL)
11313 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
11314 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
11315 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
11316 return -1;
11318 old_pat = PATTERN (insn);
11319 old_notes = REG_NOTES (insn);
11320 PATTERN (insn) = pat;
11321 REG_NOTES (insn) = NULL_RTX;
11323 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11324 if (dump_file && (dump_flags & TDF_DETAILS))
11326 if (insn_code_number < 0)
11327 fputs ("Failed to match this instruction:\n", dump_file);
11328 else
11329 fputs ("Successfully matched this instruction:\n", dump_file);
11330 print_rtl_single (dump_file, pat);
11333 /* If it isn't, there is the possibility that we previously had an insn
11334 that clobbered some register as a side effect, but the combined
11335 insn doesn't need to do that. So try once more without the clobbers
11336 unless this represents an ASM insn. */
11338 if (insn_code_number < 0 && ! check_asm_operands (pat)
11339 && GET_CODE (pat) == PARALLEL)
11341 int pos;
11343 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
11344 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
11346 if (i != pos)
11347 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
11348 pos++;
11351 SUBST_INT (XVECLEN (pat, 0), pos);
11353 if (pos == 1)
11354 pat = XVECEXP (pat, 0, 0);
11356 PATTERN (insn) = pat;
11357 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11358 if (dump_file && (dump_flags & TDF_DETAILS))
11360 if (insn_code_number < 0)
11361 fputs ("Failed to match this instruction:\n", dump_file);
11362 else
11363 fputs ("Successfully matched this instruction:\n", dump_file);
11364 print_rtl_single (dump_file, pat);
11368 pat_without_clobbers = pat;
11370 PATTERN (insn) = old_pat;
11371 REG_NOTES (insn) = old_notes;
11373 /* Recognize all noop sets, these will be killed by followup pass. */
11374 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
11375 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
11377 /* If we had any clobbers to add, make a new pattern than contains
11378 them. Then check to make sure that all of them are dead. */
11379 if (num_clobbers_to_add)
11381 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
11382 rtvec_alloc (GET_CODE (pat) == PARALLEL
11383 ? (XVECLEN (pat, 0)
11384 + num_clobbers_to_add)
11385 : num_clobbers_to_add + 1));
11387 if (GET_CODE (pat) == PARALLEL)
11388 for (i = 0; i < XVECLEN (pat, 0); i++)
11389 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
11390 else
11391 XVECEXP (newpat, 0, 0) = pat;
11393 add_clobbers (newpat, insn_code_number);
11395 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
11396 i < XVECLEN (newpat, 0); i++)
11398 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
11399 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
11400 return -1;
11401 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
11403 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
11404 notes = alloc_reg_note (REG_UNUSED,
11405 XEXP (XVECEXP (newpat, 0, i), 0), notes);
11408 pat = newpat;
11411 if (insn_code_number >= 0
11412 && insn_code_number != NOOP_MOVE_INSN_CODE)
11414 old_pat = PATTERN (insn);
11415 old_notes = REG_NOTES (insn);
11416 old_icode = INSN_CODE (insn);
11417 PATTERN (insn) = pat;
11418 REG_NOTES (insn) = notes;
11419 INSN_CODE (insn) = insn_code_number;
11421 /* Allow targets to reject combined insn. */
11422 if (!targetm.legitimate_combined_insn (insn))
11424 if (dump_file && (dump_flags & TDF_DETAILS))
11425 fputs ("Instruction not appropriate for target.",
11426 dump_file);
11428 /* Callers expect recog_for_combine to strip
11429 clobbers from the pattern on failure. */
11430 pat = pat_without_clobbers;
11431 notes = NULL_RTX;
11433 insn_code_number = -1;
11436 PATTERN (insn) = old_pat;
11437 REG_NOTES (insn) = old_notes;
11438 INSN_CODE (insn) = old_icode;
11441 *pnewpat = pat;
11442 *pnotes = notes;
11444 return insn_code_number;
11447 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11448 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11449 Return whether anything was so changed. */
11451 static bool
11452 change_zero_ext (rtx pat)
11454 bool changed = false;
11455 rtx *src = &SET_SRC (pat);
11457 subrtx_ptr_iterator::array_type array;
11458 FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11460 rtx x = **iter;
11461 scalar_int_mode mode, inner_mode;
11462 if (!is_a <scalar_int_mode> (GET_MODE (x), &mode))
11463 continue;
11464 int size;
11466 if (GET_CODE (x) == ZERO_EXTRACT
11467 && CONST_INT_P (XEXP (x, 1))
11468 && CONST_INT_P (XEXP (x, 2))
11469 && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode)
11470 && GET_MODE_PRECISION (inner_mode) <= GET_MODE_PRECISION (mode))
11472 size = INTVAL (XEXP (x, 1));
11474 int start = INTVAL (XEXP (x, 2));
11475 if (BITS_BIG_ENDIAN)
11476 start = GET_MODE_PRECISION (inner_mode) - size - start;
11478 if (start != 0)
11479 x = gen_rtx_LSHIFTRT (inner_mode, XEXP (x, 0),
11480 gen_int_shift_amount (inner_mode, start));
11481 else
11482 x = XEXP (x, 0);
11483 if (mode != inner_mode)
11484 x = gen_lowpart_SUBREG (mode, x);
11486 else if (GET_CODE (x) == ZERO_EXTEND
11487 && GET_CODE (XEXP (x, 0)) == SUBREG
11488 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x, 0))))
11489 && !paradoxical_subreg_p (XEXP (x, 0))
11490 && subreg_lowpart_p (XEXP (x, 0)))
11492 inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11493 size = GET_MODE_PRECISION (inner_mode);
11494 x = SUBREG_REG (XEXP (x, 0));
11495 if (GET_MODE (x) != mode)
11496 x = gen_lowpart_SUBREG (mode, x);
11498 else if (GET_CODE (x) == ZERO_EXTEND
11499 && REG_P (XEXP (x, 0))
11500 && HARD_REGISTER_P (XEXP (x, 0))
11501 && can_change_dest_mode (XEXP (x, 0), 0, mode))
11503 inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11504 size = GET_MODE_PRECISION (inner_mode);
11505 x = gen_rtx_REG (mode, REGNO (XEXP (x, 0)));
11507 else
11508 continue;
11510 if (!(GET_CODE (x) == LSHIFTRT
11511 && CONST_INT_P (XEXP (x, 1))
11512 && size + INTVAL (XEXP (x, 1)) == GET_MODE_PRECISION (mode)))
11514 wide_int mask = wi::mask (size, false, GET_MODE_PRECISION (mode));
11515 x = gen_rtx_AND (mode, x, immed_wide_int_const (mask, mode));
11518 SUBST (**iter, x);
11519 changed = true;
11522 if (changed)
11523 FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11524 maybe_swap_commutative_operands (**iter);
11526 rtx *dst = &SET_DEST (pat);
11527 scalar_int_mode mode;
11528 if (GET_CODE (*dst) == ZERO_EXTRACT
11529 && REG_P (XEXP (*dst, 0))
11530 && is_a <scalar_int_mode> (GET_MODE (XEXP (*dst, 0)), &mode)
11531 && CONST_INT_P (XEXP (*dst, 1))
11532 && CONST_INT_P (XEXP (*dst, 2)))
11534 rtx reg = XEXP (*dst, 0);
11535 int width = INTVAL (XEXP (*dst, 1));
11536 int offset = INTVAL (XEXP (*dst, 2));
11537 int reg_width = GET_MODE_PRECISION (mode);
11538 if (BITS_BIG_ENDIAN)
11539 offset = reg_width - width - offset;
11541 rtx x, y, z, w;
11542 wide_int mask = wi::shifted_mask (offset, width, true, reg_width);
11543 wide_int mask2 = wi::shifted_mask (offset, width, false, reg_width);
11544 x = gen_rtx_AND (mode, reg, immed_wide_int_const (mask, mode));
11545 if (offset)
11546 y = gen_rtx_ASHIFT (mode, SET_SRC (pat), GEN_INT (offset));
11547 else
11548 y = SET_SRC (pat);
11549 z = gen_rtx_AND (mode, y, immed_wide_int_const (mask2, mode));
11550 w = gen_rtx_IOR (mode, x, z);
11551 SUBST (SET_DEST (pat), reg);
11552 SUBST (SET_SRC (pat), w);
11554 changed = true;
11557 return changed;
11560 /* Like recog, but we receive the address of a pointer to a new pattern.
11561 We try to match the rtx that the pointer points to.
11562 If that fails, we may try to modify or replace the pattern,
11563 storing the replacement into the same pointer object.
11565 Modifications include deletion or addition of CLOBBERs. If the
11566 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11567 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11568 (and undo if that fails).
11570 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11571 the CLOBBERs are placed.
11573 The value is the final insn code from the pattern ultimately matched,
11574 or -1. */
11576 static int
11577 recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes)
11579 rtx pat = *pnewpat;
11580 int insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes);
11581 if (insn_code_number >= 0 || check_asm_operands (pat))
11582 return insn_code_number;
11584 void *marker = get_undo_marker ();
11585 bool changed = false;
11587 if (GET_CODE (pat) == SET)
11588 changed = change_zero_ext (pat);
11589 else if (GET_CODE (pat) == PARALLEL)
11591 int i;
11592 for (i = 0; i < XVECLEN (pat, 0); i++)
11594 rtx set = XVECEXP (pat, 0, i);
11595 if (GET_CODE (set) == SET)
11596 changed |= change_zero_ext (set);
11600 if (changed)
11602 insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes);
11604 if (insn_code_number < 0)
11605 undo_to_marker (marker);
11608 return insn_code_number;
11611 /* Like gen_lowpart_general but for use by combine. In combine it
11612 is not possible to create any new pseudoregs. However, it is
11613 safe to create invalid memory addresses, because combine will
11614 try to recognize them and all they will do is make the combine
11615 attempt fail.
11617 If for some reason this cannot do its job, an rtx
11618 (clobber (const_int 0)) is returned.
11619 An insn containing that will not be recognized. */
11621 static rtx
11622 gen_lowpart_for_combine (machine_mode omode, rtx x)
11624 machine_mode imode = GET_MODE (x);
11625 rtx result;
11627 if (omode == imode)
11628 return x;
11630 /* We can only support MODE being wider than a word if X is a
11631 constant integer or has a mode the same size. */
11632 if (maybe_gt (GET_MODE_SIZE (omode), UNITS_PER_WORD)
11633 && ! (CONST_SCALAR_INT_P (x)
11634 || known_eq (GET_MODE_SIZE (imode), GET_MODE_SIZE (omode))))
11635 goto fail;
11637 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11638 won't know what to do. So we will strip off the SUBREG here and
11639 process normally. */
11640 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
11642 x = SUBREG_REG (x);
11644 /* For use in case we fall down into the address adjustments
11645 further below, we need to adjust the known mode and size of
11646 x; imode and isize, since we just adjusted x. */
11647 imode = GET_MODE (x);
11649 if (imode == omode)
11650 return x;
11653 result = gen_lowpart_common (omode, x);
11655 if (result)
11656 return result;
11658 if (MEM_P (x))
11660 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11661 address. */
11662 if (MEM_VOLATILE_P (x)
11663 || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
11664 goto fail;
11666 /* If we want to refer to something bigger than the original memref,
11667 generate a paradoxical subreg instead. That will force a reload
11668 of the original memref X. */
11669 if (paradoxical_subreg_p (omode, imode))
11670 return gen_rtx_SUBREG (omode, x, 0);
11672 poly_int64 offset = byte_lowpart_offset (omode, imode);
11673 return adjust_address_nv (x, omode, offset);
11676 /* If X is a comparison operator, rewrite it in a new mode. This
11677 probably won't match, but may allow further simplifications. */
11678 else if (COMPARISON_P (x))
11679 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
11681 /* If we couldn't simplify X any other way, just enclose it in a
11682 SUBREG. Normally, this SUBREG won't match, but some patterns may
11683 include an explicit SUBREG or we may simplify it further in combine. */
11684 else
11686 rtx res;
11688 if (imode == VOIDmode)
11690 imode = int_mode_for_mode (omode).require ();
11691 x = gen_lowpart_common (imode, x);
11692 if (x == NULL)
11693 goto fail;
11695 res = lowpart_subreg (omode, x, imode);
11696 if (res)
11697 return res;
11700 fail:
11701 return gen_rtx_CLOBBER (omode, const0_rtx);
11704 /* Try to simplify a comparison between OP0 and a constant OP1,
11705 where CODE is the comparison code that will be tested, into a
11706 (CODE OP0 const0_rtx) form.
11708 The result is a possibly different comparison code to use.
11709 *POP1 may be updated. */
11711 static enum rtx_code
11712 simplify_compare_const (enum rtx_code code, machine_mode mode,
11713 rtx op0, rtx *pop1)
11715 scalar_int_mode int_mode;
11716 HOST_WIDE_INT const_op = INTVAL (*pop1);
11718 /* Get the constant we are comparing against and turn off all bits
11719 not on in our mode. */
11720 if (mode != VOIDmode)
11721 const_op = trunc_int_for_mode (const_op, mode);
11723 /* If we are comparing against a constant power of two and the value
11724 being compared can only have that single bit nonzero (e.g., it was
11725 `and'ed with that bit), we can replace this with a comparison
11726 with zero. */
11727 if (const_op
11728 && (code == EQ || code == NE || code == GE || code == GEU
11729 || code == LT || code == LTU)
11730 && is_a <scalar_int_mode> (mode, &int_mode)
11731 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11732 && pow2p_hwi (const_op & GET_MODE_MASK (int_mode))
11733 && (nonzero_bits (op0, int_mode)
11734 == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (int_mode))))
11736 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
11737 const_op = 0;
11740 /* Similarly, if we are comparing a value known to be either -1 or
11741 0 with -1, change it to the opposite comparison against zero. */
11742 if (const_op == -1
11743 && (code == EQ || code == NE || code == GT || code == LE
11744 || code == GEU || code == LTU)
11745 && is_a <scalar_int_mode> (mode, &int_mode)
11746 && num_sign_bit_copies (op0, int_mode) == GET_MODE_PRECISION (int_mode))
11748 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
11749 const_op = 0;
11752 /* Do some canonicalizations based on the comparison code. We prefer
11753 comparisons against zero and then prefer equality comparisons.
11754 If we can reduce the size of a constant, we will do that too. */
11755 switch (code)
11757 case LT:
11758 /* < C is equivalent to <= (C - 1) */
11759 if (const_op > 0)
11761 const_op -= 1;
11762 code = LE;
11763 /* ... fall through to LE case below. */
11764 gcc_fallthrough ();
11766 else
11767 break;
11769 case LE:
11770 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11771 if (const_op < 0)
11773 const_op += 1;
11774 code = LT;
11777 /* If we are doing a <= 0 comparison on a value known to have
11778 a zero sign bit, we can replace this with == 0. */
11779 else if (const_op == 0
11780 && is_a <scalar_int_mode> (mode, &int_mode)
11781 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11782 && (nonzero_bits (op0, int_mode)
11783 & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
11784 == 0)
11785 code = EQ;
11786 break;
11788 case GE:
11789 /* >= C is equivalent to > (C - 1). */
11790 if (const_op > 0)
11792 const_op -= 1;
11793 code = GT;
11794 /* ... fall through to GT below. */
11795 gcc_fallthrough ();
11797 else
11798 break;
11800 case GT:
11801 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11802 if (const_op < 0)
11804 const_op += 1;
11805 code = GE;
11808 /* If we are doing a > 0 comparison on a value known to have
11809 a zero sign bit, we can replace this with != 0. */
11810 else if (const_op == 0
11811 && is_a <scalar_int_mode> (mode, &int_mode)
11812 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11813 && (nonzero_bits (op0, int_mode)
11814 & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
11815 == 0)
11816 code = NE;
11817 break;
11819 case LTU:
11820 /* < C is equivalent to <= (C - 1). */
11821 if (const_op > 0)
11823 const_op -= 1;
11824 code = LEU;
11825 /* ... fall through ... */
11826 gcc_fallthrough ();
11828 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11829 else if (is_a <scalar_int_mode> (mode, &int_mode)
11830 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11831 && ((unsigned HOST_WIDE_INT) const_op
11832 == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
11834 const_op = 0;
11835 code = GE;
11836 break;
11838 else
11839 break;
11841 case LEU:
11842 /* unsigned <= 0 is equivalent to == 0 */
11843 if (const_op == 0)
11844 code = EQ;
11845 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11846 else if (is_a <scalar_int_mode> (mode, &int_mode)
11847 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11848 && ((unsigned HOST_WIDE_INT) const_op
11849 == ((HOST_WIDE_INT_1U
11850 << (GET_MODE_PRECISION (int_mode) - 1)) - 1)))
11852 const_op = 0;
11853 code = GE;
11855 break;
11857 case GEU:
11858 /* >= C is equivalent to > (C - 1). */
11859 if (const_op > 1)
11861 const_op -= 1;
11862 code = GTU;
11863 /* ... fall through ... */
11864 gcc_fallthrough ();
11867 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11868 else if (is_a <scalar_int_mode> (mode, &int_mode)
11869 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11870 && ((unsigned HOST_WIDE_INT) const_op
11871 == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
11873 const_op = 0;
11874 code = LT;
11875 break;
11877 else
11878 break;
11880 case GTU:
11881 /* unsigned > 0 is equivalent to != 0 */
11882 if (const_op == 0)
11883 code = NE;
11884 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11885 else if (is_a <scalar_int_mode> (mode, &int_mode)
11886 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11887 && ((unsigned HOST_WIDE_INT) const_op
11888 == (HOST_WIDE_INT_1U
11889 << (GET_MODE_PRECISION (int_mode) - 1)) - 1))
11891 const_op = 0;
11892 code = LT;
11894 break;
11896 default:
11897 break;
11900 *pop1 = GEN_INT (const_op);
11901 return code;
11904 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11905 comparison code that will be tested.
11907 The result is a possibly different comparison code to use. *POP0 and
11908 *POP1 may be updated.
11910 It is possible that we might detect that a comparison is either always
11911 true or always false. However, we do not perform general constant
11912 folding in combine, so this knowledge isn't useful. Such tautologies
11913 should have been detected earlier. Hence we ignore all such cases. */
11915 static enum rtx_code
11916 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
11918 rtx op0 = *pop0;
11919 rtx op1 = *pop1;
11920 rtx tem, tem1;
11921 int i;
11922 scalar_int_mode mode, inner_mode, tmode;
11923 opt_scalar_int_mode tmode_iter;
11925 /* Try a few ways of applying the same transformation to both operands. */
11926 while (1)
11928 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11929 so check specially. */
11930 if (!WORD_REGISTER_OPERATIONS
11931 && code != GTU && code != GEU && code != LTU && code != LEU
11932 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
11933 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11934 && GET_CODE (XEXP (op1, 0)) == ASHIFT
11935 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
11936 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
11937 && is_a <scalar_int_mode> (GET_MODE (op0), &mode)
11938 && (is_a <scalar_int_mode>
11939 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))), &inner_mode))
11940 && inner_mode == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))
11941 && CONST_INT_P (XEXP (op0, 1))
11942 && XEXP (op0, 1) == XEXP (op1, 1)
11943 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11944 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11945 && (INTVAL (XEXP (op0, 1))
11946 == (GET_MODE_PRECISION (mode)
11947 - GET_MODE_PRECISION (inner_mode))))
11949 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11950 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11953 /* If both operands are the same constant shift, see if we can ignore the
11954 shift. We can if the shift is a rotate or if the bits shifted out of
11955 this shift are known to be zero for both inputs and if the type of
11956 comparison is compatible with the shift. */
11957 if (GET_CODE (op0) == GET_CODE (op1)
11958 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
11959 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11960 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11961 && (code != GT && code != LT && code != GE && code != LE))
11962 || (GET_CODE (op0) == ASHIFTRT
11963 && (code != GTU && code != LTU
11964 && code != GEU && code != LEU)))
11965 && CONST_INT_P (XEXP (op0, 1))
11966 && INTVAL (XEXP (op0, 1)) >= 0
11967 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11968 && XEXP (op0, 1) == XEXP (op1, 1))
11970 machine_mode mode = GET_MODE (op0);
11971 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11972 int shift_count = INTVAL (XEXP (op0, 1));
11974 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11975 mask &= (mask >> shift_count) << shift_count;
11976 else if (GET_CODE (op0) == ASHIFT)
11977 mask = (mask & (mask << shift_count)) >> shift_count;
11979 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11980 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11981 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11982 else
11983 break;
11986 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11987 SUBREGs are of the same mode, and, in both cases, the AND would
11988 be redundant if the comparison was done in the narrower mode,
11989 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11990 and the operand's possibly nonzero bits are 0xffffff01; in that case
11991 if we only care about QImode, we don't need the AND). This case
11992 occurs if the output mode of an scc insn is not SImode and
11993 STORE_FLAG_VALUE == 1 (e.g., the 386).
11995 Similarly, check for a case where the AND's are ZERO_EXTEND
11996 operations from some narrower mode even though a SUBREG is not
11997 present. */
11999 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
12000 && CONST_INT_P (XEXP (op0, 1))
12001 && CONST_INT_P (XEXP (op1, 1)))
12003 rtx inner_op0 = XEXP (op0, 0);
12004 rtx inner_op1 = XEXP (op1, 0);
12005 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
12006 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
12007 int changed = 0;
12009 if (paradoxical_subreg_p (inner_op0)
12010 && GET_CODE (inner_op1) == SUBREG
12011 && HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0)))
12012 && (GET_MODE (SUBREG_REG (inner_op0))
12013 == GET_MODE (SUBREG_REG (inner_op1)))
12014 && ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
12015 GET_MODE (SUBREG_REG (inner_op0)))) == 0
12016 && ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
12017 GET_MODE (SUBREG_REG (inner_op1)))) == 0)
12019 op0 = SUBREG_REG (inner_op0);
12020 op1 = SUBREG_REG (inner_op1);
12022 /* The resulting comparison is always unsigned since we masked
12023 off the original sign bit. */
12024 code = unsigned_condition (code);
12026 changed = 1;
12029 else if (c0 == c1)
12030 FOR_EACH_MODE_UNTIL (tmode,
12031 as_a <scalar_int_mode> (GET_MODE (op0)))
12032 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
12034 op0 = gen_lowpart_or_truncate (tmode, inner_op0);
12035 op1 = gen_lowpart_or_truncate (tmode, inner_op1);
12036 code = unsigned_condition (code);
12037 changed = 1;
12038 break;
12041 if (! changed)
12042 break;
12045 /* If both operands are NOT, we can strip off the outer operation
12046 and adjust the comparison code for swapped operands; similarly for
12047 NEG, except that this must be an equality comparison. */
12048 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
12049 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
12050 && (code == EQ || code == NE)))
12051 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
12053 else
12054 break;
12057 /* If the first operand is a constant, swap the operands and adjust the
12058 comparison code appropriately, but don't do this if the second operand
12059 is already a constant integer. */
12060 if (swap_commutative_operands_p (op0, op1))
12062 std::swap (op0, op1);
12063 code = swap_condition (code);
12066 /* We now enter a loop during which we will try to simplify the comparison.
12067 For the most part, we only are concerned with comparisons with zero,
12068 but some things may really be comparisons with zero but not start
12069 out looking that way. */
12071 while (CONST_INT_P (op1))
12073 machine_mode raw_mode = GET_MODE (op0);
12074 scalar_int_mode int_mode;
12075 int equality_comparison_p;
12076 int sign_bit_comparison_p;
12077 int unsigned_comparison_p;
12078 HOST_WIDE_INT const_op;
12080 /* We only want to handle integral modes. This catches VOIDmode,
12081 CCmode, and the floating-point modes. An exception is that we
12082 can handle VOIDmode if OP0 is a COMPARE or a comparison
12083 operation. */
12085 if (GET_MODE_CLASS (raw_mode) != MODE_INT
12086 && ! (raw_mode == VOIDmode
12087 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
12088 break;
12090 /* Try to simplify the compare to constant, possibly changing the
12091 comparison op, and/or changing op1 to zero. */
12092 code = simplify_compare_const (code, raw_mode, op0, &op1);
12093 const_op = INTVAL (op1);
12095 /* Compute some predicates to simplify code below. */
12097 equality_comparison_p = (code == EQ || code == NE);
12098 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
12099 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
12100 || code == GEU);
12102 /* If this is a sign bit comparison and we can do arithmetic in
12103 MODE, say that we will only be needing the sign bit of OP0. */
12104 if (sign_bit_comparison_p
12105 && is_a <scalar_int_mode> (raw_mode, &int_mode)
12106 && HWI_COMPUTABLE_MODE_P (int_mode))
12107 op0 = force_to_mode (op0, int_mode,
12108 HOST_WIDE_INT_1U
12109 << (GET_MODE_PRECISION (int_mode) - 1),
12112 if (COMPARISON_P (op0))
12114 /* We can't do anything if OP0 is a condition code value, rather
12115 than an actual data value. */
12116 if (const_op != 0
12117 || CC0_P (XEXP (op0, 0))
12118 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
12119 break;
12121 /* Get the two operands being compared. */
12122 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
12123 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
12124 else
12125 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
12127 /* Check for the cases where we simply want the result of the
12128 earlier test or the opposite of that result. */
12129 if (code == NE || code == EQ
12130 || (val_signbit_known_set_p (raw_mode, STORE_FLAG_VALUE)
12131 && (code == LT || code == GE)))
12133 enum rtx_code new_code;
12134 if (code == LT || code == NE)
12135 new_code = GET_CODE (op0);
12136 else
12137 new_code = reversed_comparison_code (op0, NULL);
12139 if (new_code != UNKNOWN)
12141 code = new_code;
12142 op0 = tem;
12143 op1 = tem1;
12144 continue;
12147 break;
12150 if (raw_mode == VOIDmode)
12151 break;
12152 scalar_int_mode mode = as_a <scalar_int_mode> (raw_mode);
12154 /* Now try cases based on the opcode of OP0. If none of the cases
12155 does a "continue", we exit this loop immediately after the
12156 switch. */
12158 unsigned int mode_width = GET_MODE_PRECISION (mode);
12159 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
12160 switch (GET_CODE (op0))
12162 case ZERO_EXTRACT:
12163 /* If we are extracting a single bit from a variable position in
12164 a constant that has only a single bit set and are comparing it
12165 with zero, we can convert this into an equality comparison
12166 between the position and the location of the single bit. */
12167 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12168 have already reduced the shift count modulo the word size. */
12169 if (!SHIFT_COUNT_TRUNCATED
12170 && CONST_INT_P (XEXP (op0, 0))
12171 && XEXP (op0, 1) == const1_rtx
12172 && equality_comparison_p && const_op == 0
12173 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
12175 if (BITS_BIG_ENDIAN)
12176 i = BITS_PER_WORD - 1 - i;
12178 op0 = XEXP (op0, 2);
12179 op1 = GEN_INT (i);
12180 const_op = i;
12182 /* Result is nonzero iff shift count is equal to I. */
12183 code = reverse_condition (code);
12184 continue;
12187 /* fall through */
12189 case SIGN_EXTRACT:
12190 tem = expand_compound_operation (op0);
12191 if (tem != op0)
12193 op0 = tem;
12194 continue;
12196 break;
12198 case NOT:
12199 /* If testing for equality, we can take the NOT of the constant. */
12200 if (equality_comparison_p
12201 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
12203 op0 = XEXP (op0, 0);
12204 op1 = tem;
12205 continue;
12208 /* If just looking at the sign bit, reverse the sense of the
12209 comparison. */
12210 if (sign_bit_comparison_p)
12212 op0 = XEXP (op0, 0);
12213 code = (code == GE ? LT : GE);
12214 continue;
12216 break;
12218 case NEG:
12219 /* If testing for equality, we can take the NEG of the constant. */
12220 if (equality_comparison_p
12221 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
12223 op0 = XEXP (op0, 0);
12224 op1 = tem;
12225 continue;
12228 /* The remaining cases only apply to comparisons with zero. */
12229 if (const_op != 0)
12230 break;
12232 /* When X is ABS or is known positive,
12233 (neg X) is < 0 if and only if X != 0. */
12235 if (sign_bit_comparison_p
12236 && (GET_CODE (XEXP (op0, 0)) == ABS
12237 || (mode_width <= HOST_BITS_PER_WIDE_INT
12238 && (nonzero_bits (XEXP (op0, 0), mode)
12239 & (HOST_WIDE_INT_1U << (mode_width - 1)))
12240 == 0)))
12242 op0 = XEXP (op0, 0);
12243 code = (code == LT ? NE : EQ);
12244 continue;
12247 /* If we have NEG of something whose two high-order bits are the
12248 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12249 if (num_sign_bit_copies (op0, mode) >= 2)
12251 op0 = XEXP (op0, 0);
12252 code = swap_condition (code);
12253 continue;
12255 break;
12257 case ROTATE:
12258 /* If we are testing equality and our count is a constant, we
12259 can perform the inverse operation on our RHS. */
12260 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
12261 && (tem = simplify_binary_operation (ROTATERT, mode,
12262 op1, XEXP (op0, 1))) != 0)
12264 op0 = XEXP (op0, 0);
12265 op1 = tem;
12266 continue;
12269 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12270 a particular bit. Convert it to an AND of a constant of that
12271 bit. This will be converted into a ZERO_EXTRACT. */
12272 if (const_op == 0 && sign_bit_comparison_p
12273 && CONST_INT_P (XEXP (op0, 1))
12274 && mode_width <= HOST_BITS_PER_WIDE_INT)
12276 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12277 (HOST_WIDE_INT_1U
12278 << (mode_width - 1
12279 - INTVAL (XEXP (op0, 1)))));
12280 code = (code == LT ? NE : EQ);
12281 continue;
12284 /* Fall through. */
12286 case ABS:
12287 /* ABS is ignorable inside an equality comparison with zero. */
12288 if (const_op == 0 && equality_comparison_p)
12290 op0 = XEXP (op0, 0);
12291 continue;
12293 break;
12295 case SIGN_EXTEND:
12296 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12297 (compare FOO CONST) if CONST fits in FOO's mode and we
12298 are either testing inequality or have an unsigned
12299 comparison with ZERO_EXTEND or a signed comparison with
12300 SIGN_EXTEND. But don't do it if we don't have a compare
12301 insn of the given mode, since we'd have to revert it
12302 later on, and then we wouldn't know whether to sign- or
12303 zero-extend. */
12304 if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode)
12305 && ! unsigned_comparison_p
12306 && HWI_COMPUTABLE_MODE_P (mode)
12307 && trunc_int_for_mode (const_op, mode) == const_op
12308 && have_insn_for (COMPARE, mode))
12310 op0 = XEXP (op0, 0);
12311 continue;
12313 break;
12315 case SUBREG:
12316 /* Check for the case where we are comparing A - C1 with C2, that is
12318 (subreg:MODE (plus (A) (-C1))) op (C2)
12320 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12321 comparison in the wider mode. One of the following two conditions
12322 must be true in order for this to be valid:
12324 1. The mode extension results in the same bit pattern being added
12325 on both sides and the comparison is equality or unsigned. As
12326 C2 has been truncated to fit in MODE, the pattern can only be
12327 all 0s or all 1s.
12329 2. The mode extension results in the sign bit being copied on
12330 each side.
12332 The difficulty here is that we have predicates for A but not for
12333 (A - C1) so we need to check that C1 is within proper bounds so
12334 as to perturbate A as little as possible. */
12336 if (mode_width <= HOST_BITS_PER_WIDE_INT
12337 && subreg_lowpart_p (op0)
12338 && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op0)),
12339 &inner_mode)
12340 && GET_MODE_PRECISION (inner_mode) > mode_width
12341 && GET_CODE (SUBREG_REG (op0)) == PLUS
12342 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
12344 rtx a = XEXP (SUBREG_REG (op0), 0);
12345 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
12347 if ((c1 > 0
12348 && (unsigned HOST_WIDE_INT) c1
12349 < HOST_WIDE_INT_1U << (mode_width - 1)
12350 && (equality_comparison_p || unsigned_comparison_p)
12351 /* (A - C1) zero-extends if it is positive and sign-extends
12352 if it is negative, C2 both zero- and sign-extends. */
12353 && (((nonzero_bits (a, inner_mode)
12354 & ~GET_MODE_MASK (mode)) == 0
12355 && const_op >= 0)
12356 /* (A - C1) sign-extends if it is positive and 1-extends
12357 if it is negative, C2 both sign- and 1-extends. */
12358 || (num_sign_bit_copies (a, inner_mode)
12359 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
12360 - mode_width)
12361 && const_op < 0)))
12362 || ((unsigned HOST_WIDE_INT) c1
12363 < HOST_WIDE_INT_1U << (mode_width - 2)
12364 /* (A - C1) always sign-extends, like C2. */
12365 && num_sign_bit_copies (a, inner_mode)
12366 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
12367 - (mode_width - 1))))
12369 op0 = SUBREG_REG (op0);
12370 continue;
12374 /* If the inner mode is narrower and we are extracting the low part,
12375 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12376 if (paradoxical_subreg_p (op0))
12378 else if (subreg_lowpart_p (op0)
12379 && GET_MODE_CLASS (mode) == MODE_INT
12380 && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
12381 && (code == NE || code == EQ)
12382 && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
12383 && !paradoxical_subreg_p (op0)
12384 && (nonzero_bits (SUBREG_REG (op0), inner_mode)
12385 & ~GET_MODE_MASK (mode)) == 0)
12387 /* Remove outer subregs that don't do anything. */
12388 tem = gen_lowpart (inner_mode, op1);
12390 if ((nonzero_bits (tem, inner_mode)
12391 & ~GET_MODE_MASK (mode)) == 0)
12393 op0 = SUBREG_REG (op0);
12394 op1 = tem;
12395 continue;
12397 break;
12399 else
12400 break;
12402 /* FALLTHROUGH */
12404 case ZERO_EXTEND:
12405 if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode)
12406 && (unsigned_comparison_p || equality_comparison_p)
12407 && HWI_COMPUTABLE_MODE_P (mode)
12408 && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
12409 && const_op >= 0
12410 && have_insn_for (COMPARE, mode))
12412 op0 = XEXP (op0, 0);
12413 continue;
12415 break;
12417 case PLUS:
12418 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12419 this for equality comparisons due to pathological cases involving
12420 overflows. */
12421 if (equality_comparison_p
12422 && (tem = simplify_binary_operation (MINUS, mode,
12423 op1, XEXP (op0, 1))) != 0)
12425 op0 = XEXP (op0, 0);
12426 op1 = tem;
12427 continue;
12430 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12431 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
12432 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
12434 op0 = XEXP (XEXP (op0, 0), 0);
12435 code = (code == LT ? EQ : NE);
12436 continue;
12438 break;
12440 case MINUS:
12441 /* We used to optimize signed comparisons against zero, but that
12442 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12443 arrive here as equality comparisons, or (GEU, LTU) are
12444 optimized away. No need to special-case them. */
12446 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12447 (eq B (minus A C)), whichever simplifies. We can only do
12448 this for equality comparisons due to pathological cases involving
12449 overflows. */
12450 if (equality_comparison_p
12451 && (tem = simplify_binary_operation (PLUS, mode,
12452 XEXP (op0, 1), op1)) != 0)
12454 op0 = XEXP (op0, 0);
12455 op1 = tem;
12456 continue;
12459 if (equality_comparison_p
12460 && (tem = simplify_binary_operation (MINUS, mode,
12461 XEXP (op0, 0), op1)) != 0)
12463 op0 = XEXP (op0, 1);
12464 op1 = tem;
12465 continue;
12468 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12469 of bits in X minus 1, is one iff X > 0. */
12470 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
12471 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12472 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
12473 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12475 op0 = XEXP (op0, 1);
12476 code = (code == GE ? LE : GT);
12477 continue;
12479 break;
12481 case XOR:
12482 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12483 if C is zero or B is a constant. */
12484 if (equality_comparison_p
12485 && (tem = simplify_binary_operation (XOR, mode,
12486 XEXP (op0, 1), op1)) != 0)
12488 op0 = XEXP (op0, 0);
12489 op1 = tem;
12490 continue;
12492 break;
12495 case IOR:
12496 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12497 iff X <= 0. */
12498 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
12499 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
12500 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12502 op0 = XEXP (op0, 1);
12503 code = (code == GE ? GT : LE);
12504 continue;
12506 break;
12508 case AND:
12509 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12510 will be converted to a ZERO_EXTRACT later. */
12511 if (const_op == 0 && equality_comparison_p
12512 && GET_CODE (XEXP (op0, 0)) == ASHIFT
12513 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
12515 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
12516 XEXP (XEXP (op0, 0), 1));
12517 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12518 continue;
12521 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12522 zero and X is a comparison and C1 and C2 describe only bits set
12523 in STORE_FLAG_VALUE, we can compare with X. */
12524 if (const_op == 0 && equality_comparison_p
12525 && mode_width <= HOST_BITS_PER_WIDE_INT
12526 && CONST_INT_P (XEXP (op0, 1))
12527 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
12528 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12529 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
12530 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
12532 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12533 << INTVAL (XEXP (XEXP (op0, 0), 1)));
12534 if ((~STORE_FLAG_VALUE & mask) == 0
12535 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
12536 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
12537 && COMPARISON_P (tem))))
12539 op0 = XEXP (XEXP (op0, 0), 0);
12540 continue;
12544 /* If we are doing an equality comparison of an AND of a bit equal
12545 to the sign bit, replace this with a LT or GE comparison of
12546 the underlying value. */
12547 if (equality_comparison_p
12548 && const_op == 0
12549 && CONST_INT_P (XEXP (op0, 1))
12550 && mode_width <= HOST_BITS_PER_WIDE_INT
12551 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12552 == HOST_WIDE_INT_1U << (mode_width - 1)))
12554 op0 = XEXP (op0, 0);
12555 code = (code == EQ ? GE : LT);
12556 continue;
12559 /* If this AND operation is really a ZERO_EXTEND from a narrower
12560 mode, the constant fits within that mode, and this is either an
12561 equality or unsigned comparison, try to do this comparison in
12562 the narrower mode.
12564 Note that in:
12566 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12567 -> (ne:DI (reg:SI 4) (const_int 0))
12569 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12570 known to hold a value of the required mode the
12571 transformation is invalid. */
12572 if ((equality_comparison_p || unsigned_comparison_p)
12573 && CONST_INT_P (XEXP (op0, 1))
12574 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
12575 & GET_MODE_MASK (mode))
12576 + 1)) >= 0
12577 && const_op >> i == 0
12578 && int_mode_for_size (i, 1).exists (&tmode))
12580 op0 = gen_lowpart_or_truncate (tmode, XEXP (op0, 0));
12581 continue;
12584 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12585 fits in both M1 and M2 and the SUBREG is either paradoxical
12586 or represents the low part, permute the SUBREG and the AND
12587 and try again. */
12588 if (GET_CODE (XEXP (op0, 0)) == SUBREG
12589 && CONST_INT_P (XEXP (op0, 1)))
12591 unsigned HOST_WIDE_INT c1 = INTVAL (XEXP (op0, 1));
12592 /* Require an integral mode, to avoid creating something like
12593 (AND:SF ...). */
12594 if ((is_a <scalar_int_mode>
12595 (GET_MODE (SUBREG_REG (XEXP (op0, 0))), &tmode))
12596 /* It is unsafe to commute the AND into the SUBREG if the
12597 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12598 not defined. As originally written the upper bits
12599 have a defined value due to the AND operation.
12600 However, if we commute the AND inside the SUBREG then
12601 they no longer have defined values and the meaning of
12602 the code has been changed.
12603 Also C1 should not change value in the smaller mode,
12604 see PR67028 (a positive C1 can become negative in the
12605 smaller mode, so that the AND does no longer mask the
12606 upper bits). */
12607 && ((WORD_REGISTER_OPERATIONS
12608 && mode_width > GET_MODE_PRECISION (tmode)
12609 && mode_width <= BITS_PER_WORD
12610 && trunc_int_for_mode (c1, tmode) == (HOST_WIDE_INT) c1)
12611 || (mode_width <= GET_MODE_PRECISION (tmode)
12612 && subreg_lowpart_p (XEXP (op0, 0))))
12613 && mode_width <= HOST_BITS_PER_WIDE_INT
12614 && HWI_COMPUTABLE_MODE_P (tmode)
12615 && (c1 & ~mask) == 0
12616 && (c1 & ~GET_MODE_MASK (tmode)) == 0
12617 && c1 != mask
12618 && c1 != GET_MODE_MASK (tmode))
12620 op0 = simplify_gen_binary (AND, tmode,
12621 SUBREG_REG (XEXP (op0, 0)),
12622 gen_int_mode (c1, tmode));
12623 op0 = gen_lowpart (mode, op0);
12624 continue;
12628 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12629 if (const_op == 0 && equality_comparison_p
12630 && XEXP (op0, 1) == const1_rtx
12631 && GET_CODE (XEXP (op0, 0)) == NOT)
12633 op0 = simplify_and_const_int (NULL_RTX, mode,
12634 XEXP (XEXP (op0, 0), 0), 1);
12635 code = (code == NE ? EQ : NE);
12636 continue;
12639 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12640 (eq (and (lshiftrt X) 1) 0).
12641 Also handle the case where (not X) is expressed using xor. */
12642 if (const_op == 0 && equality_comparison_p
12643 && XEXP (op0, 1) == const1_rtx
12644 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
12646 rtx shift_op = XEXP (XEXP (op0, 0), 0);
12647 rtx shift_count = XEXP (XEXP (op0, 0), 1);
12649 if (GET_CODE (shift_op) == NOT
12650 || (GET_CODE (shift_op) == XOR
12651 && CONST_INT_P (XEXP (shift_op, 1))
12652 && CONST_INT_P (shift_count)
12653 && HWI_COMPUTABLE_MODE_P (mode)
12654 && (UINTVAL (XEXP (shift_op, 1))
12655 == HOST_WIDE_INT_1U
12656 << INTVAL (shift_count))))
12659 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
12660 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12661 code = (code == NE ? EQ : NE);
12662 continue;
12665 break;
12667 case ASHIFT:
12668 /* If we have (compare (ashift FOO N) (const_int C)) and
12669 the high order N bits of FOO (N+1 if an inequality comparison)
12670 are known to be zero, we can do this by comparing FOO with C
12671 shifted right N bits so long as the low-order N bits of C are
12672 zero. */
12673 if (CONST_INT_P (XEXP (op0, 1))
12674 && INTVAL (XEXP (op0, 1)) >= 0
12675 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
12676 < HOST_BITS_PER_WIDE_INT)
12677 && (((unsigned HOST_WIDE_INT) const_op
12678 & ((HOST_WIDE_INT_1U << INTVAL (XEXP (op0, 1)))
12679 - 1)) == 0)
12680 && mode_width <= HOST_BITS_PER_WIDE_INT
12681 && (nonzero_bits (XEXP (op0, 0), mode)
12682 & ~(mask >> (INTVAL (XEXP (op0, 1))
12683 + ! equality_comparison_p))) == 0)
12685 /* We must perform a logical shift, not an arithmetic one,
12686 as we want the top N bits of C to be zero. */
12687 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
12689 temp >>= INTVAL (XEXP (op0, 1));
12690 op1 = gen_int_mode (temp, mode);
12691 op0 = XEXP (op0, 0);
12692 continue;
12695 /* If we are doing a sign bit comparison, it means we are testing
12696 a particular bit. Convert it to the appropriate AND. */
12697 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
12698 && mode_width <= HOST_BITS_PER_WIDE_INT)
12700 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12701 (HOST_WIDE_INT_1U
12702 << (mode_width - 1
12703 - INTVAL (XEXP (op0, 1)))));
12704 code = (code == LT ? NE : EQ);
12705 continue;
12708 /* If this an equality comparison with zero and we are shifting
12709 the low bit to the sign bit, we can convert this to an AND of the
12710 low-order bit. */
12711 if (const_op == 0 && equality_comparison_p
12712 && CONST_INT_P (XEXP (op0, 1))
12713 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
12715 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
12716 continue;
12718 break;
12720 case ASHIFTRT:
12721 /* If this is an equality comparison with zero, we can do this
12722 as a logical shift, which might be much simpler. */
12723 if (equality_comparison_p && const_op == 0
12724 && CONST_INT_P (XEXP (op0, 1)))
12726 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
12727 XEXP (op0, 0),
12728 INTVAL (XEXP (op0, 1)));
12729 continue;
12732 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12733 do the comparison in a narrower mode. */
12734 if (! unsigned_comparison_p
12735 && CONST_INT_P (XEXP (op0, 1))
12736 && GET_CODE (XEXP (op0, 0)) == ASHIFT
12737 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
12738 && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1)
12739 .exists (&tmode))
12740 && (((unsigned HOST_WIDE_INT) const_op
12741 + (GET_MODE_MASK (tmode) >> 1) + 1)
12742 <= GET_MODE_MASK (tmode)))
12744 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
12745 continue;
12748 /* Likewise if OP0 is a PLUS of a sign extension with a
12749 constant, which is usually represented with the PLUS
12750 between the shifts. */
12751 if (! unsigned_comparison_p
12752 && CONST_INT_P (XEXP (op0, 1))
12753 && GET_CODE (XEXP (op0, 0)) == PLUS
12754 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12755 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
12756 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
12757 && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1)
12758 .exists (&tmode))
12759 && (((unsigned HOST_WIDE_INT) const_op
12760 + (GET_MODE_MASK (tmode) >> 1) + 1)
12761 <= GET_MODE_MASK (tmode)))
12763 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
12764 rtx add_const = XEXP (XEXP (op0, 0), 1);
12765 rtx new_const = simplify_gen_binary (ASHIFTRT, mode,
12766 add_const, XEXP (op0, 1));
12768 op0 = simplify_gen_binary (PLUS, tmode,
12769 gen_lowpart (tmode, inner),
12770 new_const);
12771 continue;
12774 /* FALLTHROUGH */
12775 case LSHIFTRT:
12776 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12777 the low order N bits of FOO are known to be zero, we can do this
12778 by comparing FOO with C shifted left N bits so long as no
12779 overflow occurs. Even if the low order N bits of FOO aren't known
12780 to be zero, if the comparison is >= or < we can use the same
12781 optimization and for > or <= by setting all the low
12782 order N bits in the comparison constant. */
12783 if (CONST_INT_P (XEXP (op0, 1))
12784 && INTVAL (XEXP (op0, 1)) > 0
12785 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
12786 && mode_width <= HOST_BITS_PER_WIDE_INT
12787 && (((unsigned HOST_WIDE_INT) const_op
12788 + (GET_CODE (op0) != LSHIFTRT
12789 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
12790 + 1)
12791 : 0))
12792 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
12794 unsigned HOST_WIDE_INT low_bits
12795 = (nonzero_bits (XEXP (op0, 0), mode)
12796 & ((HOST_WIDE_INT_1U
12797 << INTVAL (XEXP (op0, 1))) - 1));
12798 if (low_bits == 0 || !equality_comparison_p)
12800 /* If the shift was logical, then we must make the condition
12801 unsigned. */
12802 if (GET_CODE (op0) == LSHIFTRT)
12803 code = unsigned_condition (code);
12805 const_op = (unsigned HOST_WIDE_INT) const_op
12806 << INTVAL (XEXP (op0, 1));
12807 if (low_bits != 0
12808 && (code == GT || code == GTU
12809 || code == LE || code == LEU))
12810 const_op
12811 |= ((HOST_WIDE_INT_1 << INTVAL (XEXP (op0, 1))) - 1);
12812 op1 = GEN_INT (const_op);
12813 op0 = XEXP (op0, 0);
12814 continue;
12818 /* If we are using this shift to extract just the sign bit, we
12819 can replace this with an LT or GE comparison. */
12820 if (const_op == 0
12821 && (equality_comparison_p || sign_bit_comparison_p)
12822 && CONST_INT_P (XEXP (op0, 1))
12823 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
12825 op0 = XEXP (op0, 0);
12826 code = (code == NE || code == GT ? LT : GE);
12827 continue;
12829 break;
12831 default:
12832 break;
12835 break;
12838 /* Now make any compound operations involved in this comparison. Then,
12839 check for an outmost SUBREG on OP0 that is not doing anything or is
12840 paradoxical. The latter transformation must only be performed when
12841 it is known that the "extra" bits will be the same in op0 and op1 or
12842 that they don't matter. There are three cases to consider:
12844 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12845 care bits and we can assume they have any convenient value. So
12846 making the transformation is safe.
12848 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12849 In this case the upper bits of op0 are undefined. We should not make
12850 the simplification in that case as we do not know the contents of
12851 those bits.
12853 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12854 In that case we know those bits are zeros or ones. We must also be
12855 sure that they are the same as the upper bits of op1.
12857 We can never remove a SUBREG for a non-equality comparison because
12858 the sign bit is in a different place in the underlying object. */
12860 rtx_code op0_mco_code = SET;
12861 if (op1 == const0_rtx)
12862 op0_mco_code = code == NE || code == EQ ? EQ : COMPARE;
12864 op0 = make_compound_operation (op0, op0_mco_code);
12865 op1 = make_compound_operation (op1, SET);
12867 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
12868 && is_int_mode (GET_MODE (op0), &mode)
12869 && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
12870 && (code == NE || code == EQ))
12872 if (paradoxical_subreg_p (op0))
12874 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12875 implemented. */
12876 if (REG_P (SUBREG_REG (op0)))
12878 op0 = SUBREG_REG (op0);
12879 op1 = gen_lowpart (inner_mode, op1);
12882 else if (GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
12883 && (nonzero_bits (SUBREG_REG (op0), inner_mode)
12884 & ~GET_MODE_MASK (mode)) == 0)
12886 tem = gen_lowpart (inner_mode, op1);
12888 if ((nonzero_bits (tem, inner_mode) & ~GET_MODE_MASK (mode)) == 0)
12889 op0 = SUBREG_REG (op0), op1 = tem;
12893 /* We now do the opposite procedure: Some machines don't have compare
12894 insns in all modes. If OP0's mode is an integer mode smaller than a
12895 word and we can't do a compare in that mode, see if there is a larger
12896 mode for which we can do the compare. There are a number of cases in
12897 which we can use the wider mode. */
12899 if (is_int_mode (GET_MODE (op0), &mode)
12900 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
12901 && ! have_insn_for (COMPARE, mode))
12902 FOR_EACH_WIDER_MODE (tmode_iter, mode)
12904 tmode = tmode_iter.require ();
12905 if (!HWI_COMPUTABLE_MODE_P (tmode))
12906 break;
12907 if (have_insn_for (COMPARE, tmode))
12909 int zero_extended;
12911 /* If this is a test for negative, we can make an explicit
12912 test of the sign bit. Test this first so we can use
12913 a paradoxical subreg to extend OP0. */
12915 if (op1 == const0_rtx && (code == LT || code == GE)
12916 && HWI_COMPUTABLE_MODE_P (mode))
12918 unsigned HOST_WIDE_INT sign
12919 = HOST_WIDE_INT_1U << (GET_MODE_BITSIZE (mode) - 1);
12920 op0 = simplify_gen_binary (AND, tmode,
12921 gen_lowpart (tmode, op0),
12922 gen_int_mode (sign, tmode));
12923 code = (code == LT) ? NE : EQ;
12924 break;
12927 /* If the only nonzero bits in OP0 and OP1 are those in the
12928 narrower mode and this is an equality or unsigned comparison,
12929 we can use the wider mode. Similarly for sign-extended
12930 values, in which case it is true for all comparisons. */
12931 zero_extended = ((code == EQ || code == NE
12932 || code == GEU || code == GTU
12933 || code == LEU || code == LTU)
12934 && (nonzero_bits (op0, tmode)
12935 & ~GET_MODE_MASK (mode)) == 0
12936 && ((CONST_INT_P (op1)
12937 || (nonzero_bits (op1, tmode)
12938 & ~GET_MODE_MASK (mode)) == 0)));
12940 if (zero_extended
12941 || ((num_sign_bit_copies (op0, tmode)
12942 > (unsigned int) (GET_MODE_PRECISION (tmode)
12943 - GET_MODE_PRECISION (mode)))
12944 && (num_sign_bit_copies (op1, tmode)
12945 > (unsigned int) (GET_MODE_PRECISION (tmode)
12946 - GET_MODE_PRECISION (mode)))))
12948 /* If OP0 is an AND and we don't have an AND in MODE either,
12949 make a new AND in the proper mode. */
12950 if (GET_CODE (op0) == AND
12951 && !have_insn_for (AND, mode))
12952 op0 = simplify_gen_binary (AND, tmode,
12953 gen_lowpart (tmode,
12954 XEXP (op0, 0)),
12955 gen_lowpart (tmode,
12956 XEXP (op0, 1)));
12957 else
12959 if (zero_extended)
12961 op0 = simplify_gen_unary (ZERO_EXTEND, tmode,
12962 op0, mode);
12963 op1 = simplify_gen_unary (ZERO_EXTEND, tmode,
12964 op1, mode);
12966 else
12968 op0 = simplify_gen_unary (SIGN_EXTEND, tmode,
12969 op0, mode);
12970 op1 = simplify_gen_unary (SIGN_EXTEND, tmode,
12971 op1, mode);
12973 break;
12979 /* We may have changed the comparison operands. Re-canonicalize. */
12980 if (swap_commutative_operands_p (op0, op1))
12982 std::swap (op0, op1);
12983 code = swap_condition (code);
12986 /* If this machine only supports a subset of valid comparisons, see if we
12987 can convert an unsupported one into a supported one. */
12988 target_canonicalize_comparison (&code, &op0, &op1, 0);
12990 *pop0 = op0;
12991 *pop1 = op1;
12993 return code;
12996 /* Utility function for record_value_for_reg. Count number of
12997 rtxs in X. */
12998 static int
12999 count_rtxs (rtx x)
13001 enum rtx_code code = GET_CODE (x);
13002 const char *fmt;
13003 int i, j, ret = 1;
13005 if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
13006 || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
13008 rtx x0 = XEXP (x, 0);
13009 rtx x1 = XEXP (x, 1);
13011 if (x0 == x1)
13012 return 1 + 2 * count_rtxs (x0);
13014 if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
13015 || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
13016 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13017 return 2 + 2 * count_rtxs (x0)
13018 + count_rtxs (x == XEXP (x1, 0)
13019 ? XEXP (x1, 1) : XEXP (x1, 0));
13021 if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
13022 || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
13023 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13024 return 2 + 2 * count_rtxs (x1)
13025 + count_rtxs (x == XEXP (x0, 0)
13026 ? XEXP (x0, 1) : XEXP (x0, 0));
13029 fmt = GET_RTX_FORMAT (code);
13030 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13031 if (fmt[i] == 'e')
13032 ret += count_rtxs (XEXP (x, i));
13033 else if (fmt[i] == 'E')
13034 for (j = 0; j < XVECLEN (x, i); j++)
13035 ret += count_rtxs (XVECEXP (x, i, j));
13037 return ret;
13040 /* Utility function for following routine. Called when X is part of a value
13041 being stored into last_set_value. Sets last_set_table_tick
13042 for each register mentioned. Similar to mention_regs in cse.c */
13044 static void
13045 update_table_tick (rtx x)
13047 enum rtx_code code = GET_CODE (x);
13048 const char *fmt = GET_RTX_FORMAT (code);
13049 int i, j;
13051 if (code == REG)
13053 unsigned int regno = REGNO (x);
13054 unsigned int endregno = END_REGNO (x);
13055 unsigned int r;
13057 for (r = regno; r < endregno; r++)
13059 reg_stat_type *rsp = &reg_stat[r];
13060 rsp->last_set_table_tick = label_tick;
13063 return;
13066 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13067 if (fmt[i] == 'e')
13069 /* Check for identical subexpressions. If x contains
13070 identical subexpression we only have to traverse one of
13071 them. */
13072 if (i == 0 && ARITHMETIC_P (x))
13074 /* Note that at this point x1 has already been
13075 processed. */
13076 rtx x0 = XEXP (x, 0);
13077 rtx x1 = XEXP (x, 1);
13079 /* If x0 and x1 are identical then there is no need to
13080 process x0. */
13081 if (x0 == x1)
13082 break;
13084 /* If x0 is identical to a subexpression of x1 then while
13085 processing x1, x0 has already been processed. Thus we
13086 are done with x. */
13087 if (ARITHMETIC_P (x1)
13088 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13089 break;
13091 /* If x1 is identical to a subexpression of x0 then we
13092 still have to process the rest of x0. */
13093 if (ARITHMETIC_P (x0)
13094 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13096 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
13097 break;
13101 update_table_tick (XEXP (x, i));
13103 else if (fmt[i] == 'E')
13104 for (j = 0; j < XVECLEN (x, i); j++)
13105 update_table_tick (XVECEXP (x, i, j));
13108 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13109 are saying that the register is clobbered and we no longer know its
13110 value. If INSN is zero, don't update reg_stat[].last_set; this is
13111 only permitted with VALUE also zero and is used to invalidate the
13112 register. */
13114 static void
13115 record_value_for_reg (rtx reg, rtx_insn *insn, rtx value)
13117 unsigned int regno = REGNO (reg);
13118 unsigned int endregno = END_REGNO (reg);
13119 unsigned int i;
13120 reg_stat_type *rsp;
13122 /* If VALUE contains REG and we have a previous value for REG, substitute
13123 the previous value. */
13124 if (value && insn && reg_overlap_mentioned_p (reg, value))
13126 rtx tem;
13128 /* Set things up so get_last_value is allowed to see anything set up to
13129 our insn. */
13130 subst_low_luid = DF_INSN_LUID (insn);
13131 tem = get_last_value (reg);
13133 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13134 it isn't going to be useful and will take a lot of time to process,
13135 so just use the CLOBBER. */
13137 if (tem)
13139 if (ARITHMETIC_P (tem)
13140 && GET_CODE (XEXP (tem, 0)) == CLOBBER
13141 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
13142 tem = XEXP (tem, 0);
13143 else if (count_occurrences (value, reg, 1) >= 2)
13145 /* If there are two or more occurrences of REG in VALUE,
13146 prevent the value from growing too much. */
13147 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
13148 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
13151 value = replace_rtx (copy_rtx (value), reg, tem);
13155 /* For each register modified, show we don't know its value, that
13156 we don't know about its bitwise content, that its value has been
13157 updated, and that we don't know the location of the death of the
13158 register. */
13159 for (i = regno; i < endregno; i++)
13161 rsp = &reg_stat[i];
13163 if (insn)
13164 rsp->last_set = insn;
13166 rsp->last_set_value = 0;
13167 rsp->last_set_mode = VOIDmode;
13168 rsp->last_set_nonzero_bits = 0;
13169 rsp->last_set_sign_bit_copies = 0;
13170 rsp->last_death = 0;
13171 rsp->truncated_to_mode = VOIDmode;
13174 /* Mark registers that are being referenced in this value. */
13175 if (value)
13176 update_table_tick (value);
13178 /* Now update the status of each register being set.
13179 If someone is using this register in this block, set this register
13180 to invalid since we will get confused between the two lives in this
13181 basic block. This makes using this register always invalid. In cse, we
13182 scan the table to invalidate all entries using this register, but this
13183 is too much work for us. */
13185 for (i = regno; i < endregno; i++)
13187 rsp = &reg_stat[i];
13188 rsp->last_set_label = label_tick;
13189 if (!insn
13190 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
13191 rsp->last_set_invalid = 1;
13192 else
13193 rsp->last_set_invalid = 0;
13196 /* The value being assigned might refer to X (like in "x++;"). In that
13197 case, we must replace it with (clobber (const_int 0)) to prevent
13198 infinite loops. */
13199 rsp = &reg_stat[regno];
13200 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
13202 value = copy_rtx (value);
13203 if (!get_last_value_validate (&value, insn, label_tick, 1))
13204 value = 0;
13207 /* For the main register being modified, update the value, the mode, the
13208 nonzero bits, and the number of sign bit copies. */
13210 rsp->last_set_value = value;
13212 if (value)
13214 machine_mode mode = GET_MODE (reg);
13215 subst_low_luid = DF_INSN_LUID (insn);
13216 rsp->last_set_mode = mode;
13217 if (GET_MODE_CLASS (mode) == MODE_INT
13218 && HWI_COMPUTABLE_MODE_P (mode))
13219 mode = nonzero_bits_mode;
13220 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
13221 rsp->last_set_sign_bit_copies
13222 = num_sign_bit_copies (value, GET_MODE (reg));
13226 /* Called via note_stores from record_dead_and_set_regs to handle one
13227 SET or CLOBBER in an insn. DATA is the instruction in which the
13228 set is occurring. */
13230 static void
13231 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
13233 rtx_insn *record_dead_insn = (rtx_insn *) data;
13235 if (GET_CODE (dest) == SUBREG)
13236 dest = SUBREG_REG (dest);
13238 if (!record_dead_insn)
13240 if (REG_P (dest))
13241 record_value_for_reg (dest, NULL, NULL_RTX);
13242 return;
13245 if (REG_P (dest))
13247 /* If we are setting the whole register, we know its value. Otherwise
13248 show that we don't know the value. We can handle SUBREG in
13249 some cases. */
13250 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
13251 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
13252 else if (GET_CODE (setter) == SET
13253 && GET_CODE (SET_DEST (setter)) == SUBREG
13254 && SUBREG_REG (SET_DEST (setter)) == dest
13255 && known_le (GET_MODE_PRECISION (GET_MODE (dest)), BITS_PER_WORD)
13256 && subreg_lowpart_p (SET_DEST (setter)))
13257 record_value_for_reg (dest, record_dead_insn,
13258 gen_lowpart (GET_MODE (dest),
13259 SET_SRC (setter)));
13260 else
13261 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
13263 else if (MEM_P (dest)
13264 /* Ignore pushes, they clobber nothing. */
13265 && ! push_operand (dest, GET_MODE (dest)))
13266 mem_last_set = DF_INSN_LUID (record_dead_insn);
13269 /* Update the records of when each REG was most recently set or killed
13270 for the things done by INSN. This is the last thing done in processing
13271 INSN in the combiner loop.
13273 We update reg_stat[], in particular fields last_set, last_set_value,
13274 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13275 last_death, and also the similar information mem_last_set (which insn
13276 most recently modified memory) and last_call_luid (which insn was the
13277 most recent subroutine call). */
13279 static void
13280 record_dead_and_set_regs (rtx_insn *insn)
13282 rtx link;
13283 unsigned int i;
13285 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
13287 if (REG_NOTE_KIND (link) == REG_DEAD
13288 && REG_P (XEXP (link, 0)))
13290 unsigned int regno = REGNO (XEXP (link, 0));
13291 unsigned int endregno = END_REGNO (XEXP (link, 0));
13293 for (i = regno; i < endregno; i++)
13295 reg_stat_type *rsp;
13297 rsp = &reg_stat[i];
13298 rsp->last_death = insn;
13301 else if (REG_NOTE_KIND (link) == REG_INC)
13302 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
13305 if (CALL_P (insn))
13307 hard_reg_set_iterator hrsi;
13308 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi)
13310 reg_stat_type *rsp;
13312 rsp = &reg_stat[i];
13313 rsp->last_set_invalid = 1;
13314 rsp->last_set = insn;
13315 rsp->last_set_value = 0;
13316 rsp->last_set_mode = VOIDmode;
13317 rsp->last_set_nonzero_bits = 0;
13318 rsp->last_set_sign_bit_copies = 0;
13319 rsp->last_death = 0;
13320 rsp->truncated_to_mode = VOIDmode;
13323 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
13325 /* We can't combine into a call pattern. Remember, though, that
13326 the return value register is set at this LUID. We could
13327 still replace a register with the return value from the
13328 wrong subroutine call! */
13329 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
13331 else
13332 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
13335 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13336 register present in the SUBREG, so for each such SUBREG go back and
13337 adjust nonzero and sign bit information of the registers that are
13338 known to have some zero/sign bits set.
13340 This is needed because when combine blows the SUBREGs away, the
13341 information on zero/sign bits is lost and further combines can be
13342 missed because of that. */
13344 static void
13345 record_promoted_value (rtx_insn *insn, rtx subreg)
13347 struct insn_link *links;
13348 rtx set;
13349 unsigned int regno = REGNO (SUBREG_REG (subreg));
13350 machine_mode mode = GET_MODE (subreg);
13352 if (!HWI_COMPUTABLE_MODE_P (mode))
13353 return;
13355 for (links = LOG_LINKS (insn); links;)
13357 reg_stat_type *rsp;
13359 insn = links->insn;
13360 set = single_set (insn);
13362 if (! set || !REG_P (SET_DEST (set))
13363 || REGNO (SET_DEST (set)) != regno
13364 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
13366 links = links->next;
13367 continue;
13370 rsp = &reg_stat[regno];
13371 if (rsp->last_set == insn)
13373 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
13374 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
13377 if (REG_P (SET_SRC (set)))
13379 regno = REGNO (SET_SRC (set));
13380 links = LOG_LINKS (insn);
13382 else
13383 break;
13387 /* Check if X, a register, is known to contain a value already
13388 truncated to MODE. In this case we can use a subreg to refer to
13389 the truncated value even though in the generic case we would need
13390 an explicit truncation. */
13392 static bool
13393 reg_truncated_to_mode (machine_mode mode, const_rtx x)
13395 reg_stat_type *rsp = &reg_stat[REGNO (x)];
13396 machine_mode truncated = rsp->truncated_to_mode;
13398 if (truncated == 0
13399 || rsp->truncation_label < label_tick_ebb_start)
13400 return false;
13401 if (!partial_subreg_p (mode, truncated))
13402 return true;
13403 if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
13404 return true;
13405 return false;
13408 /* If X is a hard reg or a subreg record the mode that the register is
13409 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13410 able to turn a truncate into a subreg using this information. Return true
13411 if traversing X is complete. */
13413 static bool
13414 record_truncated_value (rtx x)
13416 machine_mode truncated_mode;
13417 reg_stat_type *rsp;
13419 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
13421 machine_mode original_mode = GET_MODE (SUBREG_REG (x));
13422 truncated_mode = GET_MODE (x);
13424 if (!partial_subreg_p (truncated_mode, original_mode))
13425 return true;
13427 truncated_mode = GET_MODE (x);
13428 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
13429 return true;
13431 x = SUBREG_REG (x);
13433 /* ??? For hard-regs we now record everything. We might be able to
13434 optimize this using last_set_mode. */
13435 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
13436 truncated_mode = GET_MODE (x);
13437 else
13438 return false;
13440 rsp = &reg_stat[REGNO (x)];
13441 if (rsp->truncated_to_mode == 0
13442 || rsp->truncation_label < label_tick_ebb_start
13443 || partial_subreg_p (truncated_mode, rsp->truncated_to_mode))
13445 rsp->truncated_to_mode = truncated_mode;
13446 rsp->truncation_label = label_tick;
13449 return true;
13452 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13453 the modes they are used in. This can help truning TRUNCATEs into
13454 SUBREGs. */
13456 static void
13457 record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED)
13459 subrtx_var_iterator::array_type array;
13460 FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
13461 if (record_truncated_value (*iter))
13462 iter.skip_subrtxes ();
13465 /* Scan X for promoted SUBREGs. For each one found,
13466 note what it implies to the registers used in it. */
13468 static void
13469 check_promoted_subreg (rtx_insn *insn, rtx x)
13471 if (GET_CODE (x) == SUBREG
13472 && SUBREG_PROMOTED_VAR_P (x)
13473 && REG_P (SUBREG_REG (x)))
13474 record_promoted_value (insn, x);
13475 else
13477 const char *format = GET_RTX_FORMAT (GET_CODE (x));
13478 int i, j;
13480 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
13481 switch (format[i])
13483 case 'e':
13484 check_promoted_subreg (insn, XEXP (x, i));
13485 break;
13486 case 'V':
13487 case 'E':
13488 if (XVEC (x, i) != 0)
13489 for (j = 0; j < XVECLEN (x, i); j++)
13490 check_promoted_subreg (insn, XVECEXP (x, i, j));
13491 break;
13496 /* Verify that all the registers and memory references mentioned in *LOC are
13497 still valid. *LOC was part of a value set in INSN when label_tick was
13498 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13499 the invalid references with (clobber (const_int 0)) and return 1. This
13500 replacement is useful because we often can get useful information about
13501 the form of a value (e.g., if it was produced by a shift that always
13502 produces -1 or 0) even though we don't know exactly what registers it
13503 was produced from. */
13505 static int
13506 get_last_value_validate (rtx *loc, rtx_insn *insn, int tick, int replace)
13508 rtx x = *loc;
13509 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
13510 int len = GET_RTX_LENGTH (GET_CODE (x));
13511 int i, j;
13513 if (REG_P (x))
13515 unsigned int regno = REGNO (x);
13516 unsigned int endregno = END_REGNO (x);
13517 unsigned int j;
13519 for (j = regno; j < endregno; j++)
13521 reg_stat_type *rsp = &reg_stat[j];
13522 if (rsp->last_set_invalid
13523 /* If this is a pseudo-register that was only set once and not
13524 live at the beginning of the function, it is always valid. */
13525 || (! (regno >= FIRST_PSEUDO_REGISTER
13526 && regno < reg_n_sets_max
13527 && REG_N_SETS (regno) == 1
13528 && (!REGNO_REG_SET_P
13529 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
13530 regno)))
13531 && rsp->last_set_label > tick))
13533 if (replace)
13534 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13535 return replace;
13539 return 1;
13541 /* If this is a memory reference, make sure that there were no stores after
13542 it that might have clobbered the value. We don't have alias info, so we
13543 assume any store invalidates it. Moreover, we only have local UIDs, so
13544 we also assume that there were stores in the intervening basic blocks. */
13545 else if (MEM_P (x) && !MEM_READONLY_P (x)
13546 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
13548 if (replace)
13549 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13550 return replace;
13553 for (i = 0; i < len; i++)
13555 if (fmt[i] == 'e')
13557 /* Check for identical subexpressions. If x contains
13558 identical subexpression we only have to traverse one of
13559 them. */
13560 if (i == 1 && ARITHMETIC_P (x))
13562 /* Note that at this point x0 has already been checked
13563 and found valid. */
13564 rtx x0 = XEXP (x, 0);
13565 rtx x1 = XEXP (x, 1);
13567 /* If x0 and x1 are identical then x is also valid. */
13568 if (x0 == x1)
13569 return 1;
13571 /* If x1 is identical to a subexpression of x0 then
13572 while checking x0, x1 has already been checked. Thus
13573 it is valid and so as x. */
13574 if (ARITHMETIC_P (x0)
13575 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13576 return 1;
13578 /* If x0 is identical to a subexpression of x1 then x is
13579 valid iff the rest of x1 is valid. */
13580 if (ARITHMETIC_P (x1)
13581 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13582 return
13583 get_last_value_validate (&XEXP (x1,
13584 x0 == XEXP (x1, 0) ? 1 : 0),
13585 insn, tick, replace);
13588 if (get_last_value_validate (&XEXP (x, i), insn, tick,
13589 replace) == 0)
13590 return 0;
13592 else if (fmt[i] == 'E')
13593 for (j = 0; j < XVECLEN (x, i); j++)
13594 if (get_last_value_validate (&XVECEXP (x, i, j),
13595 insn, tick, replace) == 0)
13596 return 0;
13599 /* If we haven't found a reason for it to be invalid, it is valid. */
13600 return 1;
13603 /* Get the last value assigned to X, if known. Some registers
13604 in the value may be replaced with (clobber (const_int 0)) if their value
13605 is known longer known reliably. */
13607 static rtx
13608 get_last_value (const_rtx x)
13610 unsigned int regno;
13611 rtx value;
13612 reg_stat_type *rsp;
13614 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13615 then convert it to the desired mode. If this is a paradoxical SUBREG,
13616 we cannot predict what values the "extra" bits might have. */
13617 if (GET_CODE (x) == SUBREG
13618 && subreg_lowpart_p (x)
13619 && !paradoxical_subreg_p (x)
13620 && (value = get_last_value (SUBREG_REG (x))) != 0)
13621 return gen_lowpart (GET_MODE (x), value);
13623 if (!REG_P (x))
13624 return 0;
13626 regno = REGNO (x);
13627 rsp = &reg_stat[regno];
13628 value = rsp->last_set_value;
13630 /* If we don't have a value, or if it isn't for this basic block and
13631 it's either a hard register, set more than once, or it's a live
13632 at the beginning of the function, return 0.
13634 Because if it's not live at the beginning of the function then the reg
13635 is always set before being used (is never used without being set).
13636 And, if it's set only once, and it's always set before use, then all
13637 uses must have the same last value, even if it's not from this basic
13638 block. */
13640 if (value == 0
13641 || (rsp->last_set_label < label_tick_ebb_start
13642 && (regno < FIRST_PSEUDO_REGISTER
13643 || regno >= reg_n_sets_max
13644 || REG_N_SETS (regno) != 1
13645 || REGNO_REG_SET_P
13646 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno))))
13647 return 0;
13649 /* If the value was set in a later insn than the ones we are processing,
13650 we can't use it even if the register was only set once. */
13651 if (rsp->last_set_label == label_tick
13652 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
13653 return 0;
13655 /* If fewer bits were set than what we are asked for now, we cannot use
13656 the value. */
13657 if (maybe_lt (GET_MODE_PRECISION (rsp->last_set_mode),
13658 GET_MODE_PRECISION (GET_MODE (x))))
13659 return 0;
13661 /* If the value has all its registers valid, return it. */
13662 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
13663 return value;
13665 /* Otherwise, make a copy and replace any invalid register with
13666 (clobber (const_int 0)). If that fails for some reason, return 0. */
13668 value = copy_rtx (value);
13669 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
13670 return value;
13672 return 0;
13675 /* Define three variables used for communication between the following
13676 routines. */
13678 static unsigned int reg_dead_regno, reg_dead_endregno;
13679 static int reg_dead_flag;
13681 /* Function called via note_stores from reg_dead_at_p.
13683 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13684 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13686 static void
13687 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
13689 unsigned int regno, endregno;
13691 if (!REG_P (dest))
13692 return;
13694 regno = REGNO (dest);
13695 endregno = END_REGNO (dest);
13696 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
13697 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
13700 /* Return nonzero if REG is known to be dead at INSN.
13702 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13703 referencing REG, it is dead. If we hit a SET referencing REG, it is
13704 live. Otherwise, see if it is live or dead at the start of the basic
13705 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13706 must be assumed to be always live. */
13708 static int
13709 reg_dead_at_p (rtx reg, rtx_insn *insn)
13711 basic_block block;
13712 unsigned int i;
13714 /* Set variables for reg_dead_at_p_1. */
13715 reg_dead_regno = REGNO (reg);
13716 reg_dead_endregno = END_REGNO (reg);
13718 reg_dead_flag = 0;
13720 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13721 we allow the machine description to decide whether use-and-clobber
13722 patterns are OK. */
13723 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
13725 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
13726 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
13727 return 0;
13730 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13731 beginning of basic block. */
13732 block = BLOCK_FOR_INSN (insn);
13733 for (;;)
13735 if (INSN_P (insn))
13737 if (find_regno_note (insn, REG_UNUSED, reg_dead_regno))
13738 return 1;
13740 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
13741 if (reg_dead_flag)
13742 return reg_dead_flag == 1 ? 1 : 0;
13744 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
13745 return 1;
13748 if (insn == BB_HEAD (block))
13749 break;
13751 insn = PREV_INSN (insn);
13754 /* Look at live-in sets for the basic block that we were in. */
13755 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
13756 if (REGNO_REG_SET_P (df_get_live_in (block), i))
13757 return 0;
13759 return 1;
13762 /* Note hard registers in X that are used. */
13764 static void
13765 mark_used_regs_combine (rtx x)
13767 RTX_CODE code = GET_CODE (x);
13768 unsigned int regno;
13769 int i;
13771 switch (code)
13773 case LABEL_REF:
13774 case SYMBOL_REF:
13775 case CONST:
13776 CASE_CONST_ANY:
13777 case PC:
13778 case ADDR_VEC:
13779 case ADDR_DIFF_VEC:
13780 case ASM_INPUT:
13781 /* CC0 must die in the insn after it is set, so we don't need to take
13782 special note of it here. */
13783 case CC0:
13784 return;
13786 case CLOBBER:
13787 /* If we are clobbering a MEM, mark any hard registers inside the
13788 address as used. */
13789 if (MEM_P (XEXP (x, 0)))
13790 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
13791 return;
13793 case REG:
13794 regno = REGNO (x);
13795 /* A hard reg in a wide mode may really be multiple registers.
13796 If so, mark all of them just like the first. */
13797 if (regno < FIRST_PSEUDO_REGISTER)
13799 /* None of this applies to the stack, frame or arg pointers. */
13800 if (regno == STACK_POINTER_REGNUM
13801 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13802 && regno == HARD_FRAME_POINTER_REGNUM)
13803 || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
13804 && regno == ARG_POINTER_REGNUM && fixed_regs[regno])
13805 || regno == FRAME_POINTER_REGNUM)
13806 return;
13808 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
13810 return;
13812 case SET:
13814 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13815 the address. */
13816 rtx testreg = SET_DEST (x);
13818 while (GET_CODE (testreg) == SUBREG
13819 || GET_CODE (testreg) == ZERO_EXTRACT
13820 || GET_CODE (testreg) == STRICT_LOW_PART)
13821 testreg = XEXP (testreg, 0);
13823 if (MEM_P (testreg))
13824 mark_used_regs_combine (XEXP (testreg, 0));
13826 mark_used_regs_combine (SET_SRC (x));
13828 return;
13830 default:
13831 break;
13834 /* Recursively scan the operands of this expression. */
13837 const char *fmt = GET_RTX_FORMAT (code);
13839 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13841 if (fmt[i] == 'e')
13842 mark_used_regs_combine (XEXP (x, i));
13843 else if (fmt[i] == 'E')
13845 int j;
13847 for (j = 0; j < XVECLEN (x, i); j++)
13848 mark_used_regs_combine (XVECEXP (x, i, j));
13854 /* Remove register number REGNO from the dead registers list of INSN.
13856 Return the note used to record the death, if there was one. */
13859 remove_death (unsigned int regno, rtx_insn *insn)
13861 rtx note = find_regno_note (insn, REG_DEAD, regno);
13863 if (note)
13864 remove_note (insn, note);
13866 return note;
13869 /* For each register (hardware or pseudo) used within expression X, if its
13870 death is in an instruction with luid between FROM_LUID (inclusive) and
13871 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13872 list headed by PNOTES.
13874 That said, don't move registers killed by maybe_kill_insn.
13876 This is done when X is being merged by combination into TO_INSN. These
13877 notes will then be distributed as needed. */
13879 static void
13880 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
13881 rtx *pnotes)
13883 const char *fmt;
13884 int len, i;
13885 enum rtx_code code = GET_CODE (x);
13887 if (code == REG)
13889 unsigned int regno = REGNO (x);
13890 rtx_insn *where_dead = reg_stat[regno].last_death;
13892 /* If we do not know where the register died, it may still die between
13893 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
13894 if (!where_dead || DF_INSN_LUID (where_dead) >= DF_INSN_LUID (to_insn))
13896 rtx_insn *insn = prev_real_insn (to_insn);
13897 while (insn
13898 && BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (to_insn)
13899 && DF_INSN_LUID (insn) >= from_luid)
13901 if (dead_or_set_regno_p (insn, regno))
13903 if (find_regno_note (insn, REG_DEAD, regno))
13904 where_dead = insn;
13905 break;
13908 insn = prev_real_insn (insn);
13912 /* Don't move the register if it gets killed in between from and to. */
13913 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
13914 && ! reg_referenced_p (x, maybe_kill_insn))
13915 return;
13917 if (where_dead
13918 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
13919 && DF_INSN_LUID (where_dead) >= from_luid
13920 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13922 rtx note = remove_death (regno, where_dead);
13924 /* It is possible for the call above to return 0. This can occur
13925 when last_death points to I2 or I1 that we combined with.
13926 In that case make a new note.
13928 We must also check for the case where X is a hard register
13929 and NOTE is a death note for a range of hard registers
13930 including X. In that case, we must put REG_DEAD notes for
13931 the remaining registers in place of NOTE. */
13933 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13934 && partial_subreg_p (GET_MODE (x), GET_MODE (XEXP (note, 0))))
13936 unsigned int deadregno = REGNO (XEXP (note, 0));
13937 unsigned int deadend = END_REGNO (XEXP (note, 0));
13938 unsigned int ourend = END_REGNO (x);
13939 unsigned int i;
13941 for (i = deadregno; i < deadend; i++)
13942 if (i < regno || i >= ourend)
13943 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13946 /* If we didn't find any note, or if we found a REG_DEAD note that
13947 covers only part of the given reg, and we have a multi-reg hard
13948 register, then to be safe we must check for REG_DEAD notes
13949 for each register other than the first. They could have
13950 their own REG_DEAD notes lying around. */
13951 else if ((note == 0
13952 || (note != 0
13953 && partial_subreg_p (GET_MODE (XEXP (note, 0)),
13954 GET_MODE (x))))
13955 && regno < FIRST_PSEUDO_REGISTER
13956 && REG_NREGS (x) > 1)
13958 unsigned int ourend = END_REGNO (x);
13959 unsigned int i, offset;
13960 rtx oldnotes = 0;
13962 if (note)
13963 offset = hard_regno_nregs (regno, GET_MODE (XEXP (note, 0)));
13964 else
13965 offset = 1;
13967 for (i = regno + offset; i < ourend; i++)
13968 move_deaths (regno_reg_rtx[i],
13969 maybe_kill_insn, from_luid, to_insn, &oldnotes);
13972 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13974 XEXP (note, 1) = *pnotes;
13975 *pnotes = note;
13977 else
13978 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13981 return;
13984 else if (GET_CODE (x) == SET)
13986 rtx dest = SET_DEST (x);
13988 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13990 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13991 that accesses one word of a multi-word item, some
13992 piece of everything register in the expression is used by
13993 this insn, so remove any old death. */
13994 /* ??? So why do we test for equality of the sizes? */
13996 if (GET_CODE (dest) == ZERO_EXTRACT
13997 || GET_CODE (dest) == STRICT_LOW_PART
13998 || (GET_CODE (dest) == SUBREG
13999 && !read_modify_subreg_p (dest)))
14001 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
14002 return;
14005 /* If this is some other SUBREG, we know it replaces the entire
14006 value, so use that as the destination. */
14007 if (GET_CODE (dest) == SUBREG)
14008 dest = SUBREG_REG (dest);
14010 /* If this is a MEM, adjust deaths of anything used in the address.
14011 For a REG (the only other possibility), the entire value is
14012 being replaced so the old value is not used in this insn. */
14014 if (MEM_P (dest))
14015 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
14016 to_insn, pnotes);
14017 return;
14020 else if (GET_CODE (x) == CLOBBER)
14021 return;
14023 len = GET_RTX_LENGTH (code);
14024 fmt = GET_RTX_FORMAT (code);
14026 for (i = 0; i < len; i++)
14028 if (fmt[i] == 'E')
14030 int j;
14031 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
14032 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
14033 to_insn, pnotes);
14035 else if (fmt[i] == 'e')
14036 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
14040 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14041 pattern of an insn. X must be a REG. */
14043 static int
14044 reg_bitfield_target_p (rtx x, rtx body)
14046 int i;
14048 if (GET_CODE (body) == SET)
14050 rtx dest = SET_DEST (body);
14051 rtx target;
14052 unsigned int regno, tregno, endregno, endtregno;
14054 if (GET_CODE (dest) == ZERO_EXTRACT)
14055 target = XEXP (dest, 0);
14056 else if (GET_CODE (dest) == STRICT_LOW_PART)
14057 target = SUBREG_REG (XEXP (dest, 0));
14058 else
14059 return 0;
14061 if (GET_CODE (target) == SUBREG)
14062 target = SUBREG_REG (target);
14064 if (!REG_P (target))
14065 return 0;
14067 tregno = REGNO (target), regno = REGNO (x);
14068 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
14069 return target == x;
14071 endtregno = end_hard_regno (GET_MODE (target), tregno);
14072 endregno = end_hard_regno (GET_MODE (x), regno);
14074 return endregno > tregno && regno < endtregno;
14077 else if (GET_CODE (body) == PARALLEL)
14078 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
14079 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
14080 return 1;
14082 return 0;
14085 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14086 as appropriate. I3 and I2 are the insns resulting from the combination
14087 insns including FROM (I2 may be zero).
14089 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14090 not need REG_DEAD notes because they are being substituted for. This
14091 saves searching in the most common cases.
14093 Each note in the list is either ignored or placed on some insns, depending
14094 on the type of note. */
14096 static void
14097 distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
14098 rtx elim_i2, rtx elim_i1, rtx elim_i0)
14100 rtx note, next_note;
14101 rtx tem_note;
14102 rtx_insn *tem_insn;
14104 for (note = notes; note; note = next_note)
14106 rtx_insn *place = 0, *place2 = 0;
14108 next_note = XEXP (note, 1);
14109 switch (REG_NOTE_KIND (note))
14111 case REG_BR_PROB:
14112 case REG_BR_PRED:
14113 /* Doesn't matter much where we put this, as long as it's somewhere.
14114 It is preferable to keep these notes on branches, which is most
14115 likely to be i3. */
14116 place = i3;
14117 break;
14119 case REG_NON_LOCAL_GOTO:
14120 if (JUMP_P (i3))
14121 place = i3;
14122 else
14124 gcc_assert (i2 && JUMP_P (i2));
14125 place = i2;
14127 break;
14129 case REG_EH_REGION:
14130 /* These notes must remain with the call or trapping instruction. */
14131 if (CALL_P (i3))
14132 place = i3;
14133 else if (i2 && CALL_P (i2))
14134 place = i2;
14135 else
14137 gcc_assert (cfun->can_throw_non_call_exceptions);
14138 if (may_trap_p (i3))
14139 place = i3;
14140 else if (i2 && may_trap_p (i2))
14141 place = i2;
14142 /* ??? Otherwise assume we've combined things such that we
14143 can now prove that the instructions can't trap. Drop the
14144 note in this case. */
14146 break;
14148 case REG_ARGS_SIZE:
14149 /* ??? How to distribute between i3-i1. Assume i3 contains the
14150 entire adjustment. Assert i3 contains at least some adjust. */
14151 if (!noop_move_p (i3))
14153 poly_int64 old_size, args_size = get_args_size (note);
14154 /* fixup_args_size_notes looks at REG_NORETURN note,
14155 so ensure the note is placed there first. */
14156 if (CALL_P (i3))
14158 rtx *np;
14159 for (np = &next_note; *np; np = &XEXP (*np, 1))
14160 if (REG_NOTE_KIND (*np) == REG_NORETURN)
14162 rtx n = *np;
14163 *np = XEXP (n, 1);
14164 XEXP (n, 1) = REG_NOTES (i3);
14165 REG_NOTES (i3) = n;
14166 break;
14169 old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
14170 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14171 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14172 gcc_assert (maybe_ne (old_size, args_size)
14173 || (CALL_P (i3)
14174 && !ACCUMULATE_OUTGOING_ARGS
14175 && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
14177 break;
14179 case REG_NORETURN:
14180 case REG_SETJMP:
14181 case REG_TM:
14182 case REG_CALL_DECL:
14183 case REG_CALL_NOCF_CHECK:
14184 /* These notes must remain with the call. It should not be
14185 possible for both I2 and I3 to be a call. */
14186 if (CALL_P (i3))
14187 place = i3;
14188 else
14190 gcc_assert (i2 && CALL_P (i2));
14191 place = i2;
14193 break;
14195 case REG_UNUSED:
14196 /* Any clobbers for i3 may still exist, and so we must process
14197 REG_UNUSED notes from that insn.
14199 Any clobbers from i2 or i1 can only exist if they were added by
14200 recog_for_combine. In that case, recog_for_combine created the
14201 necessary REG_UNUSED notes. Trying to keep any original
14202 REG_UNUSED notes from these insns can cause incorrect output
14203 if it is for the same register as the original i3 dest.
14204 In that case, we will notice that the register is set in i3,
14205 and then add a REG_UNUSED note for the destination of i3, which
14206 is wrong. However, it is possible to have REG_UNUSED notes from
14207 i2 or i1 for register which were both used and clobbered, so
14208 we keep notes from i2 or i1 if they will turn into REG_DEAD
14209 notes. */
14211 /* If this register is set or clobbered in I3, put the note there
14212 unless there is one already. */
14213 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
14215 if (from_insn != i3)
14216 break;
14218 if (! (REG_P (XEXP (note, 0))
14219 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
14220 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
14221 place = i3;
14223 /* Otherwise, if this register is used by I3, then this register
14224 now dies here, so we must put a REG_DEAD note here unless there
14225 is one already. */
14226 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
14227 && ! (REG_P (XEXP (note, 0))
14228 ? find_regno_note (i3, REG_DEAD,
14229 REGNO (XEXP (note, 0)))
14230 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
14232 PUT_REG_NOTE_KIND (note, REG_DEAD);
14233 place = i3;
14236 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14237 but we can't tell which at this point. We must reset any
14238 expectations we had about the value that was previously
14239 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14240 and, if appropriate, restore its previous value, but we
14241 don't have enough information for that at this point. */
14242 else
14244 record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14246 /* Otherwise, if this register is now referenced in i2
14247 then the register used to be modified in one of the
14248 original insns. If it was i3 (say, in an unused
14249 parallel), it's now completely gone, so the note can
14250 be discarded. But if it was modified in i2, i1 or i0
14251 and we still reference it in i2, then we're
14252 referencing the previous value, and since the
14253 register was modified and REG_UNUSED, we know that
14254 the previous value is now dead. So, if we only
14255 reference the register in i2, we change the note to
14256 REG_DEAD, to reflect the previous value. However, if
14257 we're also setting or clobbering the register as
14258 scratch, we know (because the register was not
14259 referenced in i3) that it's unused, just as it was
14260 unused before, and we place the note in i2. */
14261 if (from_insn != i3 && i2 && INSN_P (i2)
14262 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14264 if (!reg_set_p (XEXP (note, 0), PATTERN (i2)))
14265 PUT_REG_NOTE_KIND (note, REG_DEAD);
14266 if (! (REG_P (XEXP (note, 0))
14267 ? find_regno_note (i2, REG_NOTE_KIND (note),
14268 REGNO (XEXP (note, 0)))
14269 : find_reg_note (i2, REG_NOTE_KIND (note),
14270 XEXP (note, 0))))
14271 place = i2;
14275 break;
14277 case REG_EQUAL:
14278 case REG_EQUIV:
14279 case REG_NOALIAS:
14280 /* These notes say something about results of an insn. We can
14281 only support them if they used to be on I3 in which case they
14282 remain on I3. Otherwise they are ignored.
14284 If the note refers to an expression that is not a constant, we
14285 must also ignore the note since we cannot tell whether the
14286 equivalence is still true. It might be possible to do
14287 slightly better than this (we only have a problem if I2DEST
14288 or I1DEST is present in the expression), but it doesn't
14289 seem worth the trouble. */
14291 if (from_insn == i3
14292 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
14293 place = i3;
14294 break;
14296 case REG_INC:
14297 /* These notes say something about how a register is used. They must
14298 be present on any use of the register in I2 or I3. */
14299 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
14300 place = i3;
14302 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
14304 if (place)
14305 place2 = i2;
14306 else
14307 place = i2;
14309 break;
14311 case REG_LABEL_TARGET:
14312 case REG_LABEL_OPERAND:
14313 /* This can show up in several ways -- either directly in the
14314 pattern, or hidden off in the constant pool with (or without?)
14315 a REG_EQUAL note. */
14316 /* ??? Ignore the without-reg_equal-note problem for now. */
14317 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
14318 || ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX))
14319 && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14320 && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0)))
14321 place = i3;
14323 if (i2
14324 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
14325 || ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX))
14326 && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14327 && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0))))
14329 if (place)
14330 place2 = i2;
14331 else
14332 place = i2;
14335 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14336 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14337 there. */
14338 if (place && JUMP_P (place)
14339 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
14340 && (JUMP_LABEL (place) == NULL
14341 || JUMP_LABEL (place) == XEXP (note, 0)))
14343 rtx label = JUMP_LABEL (place);
14345 if (!label)
14346 JUMP_LABEL (place) = XEXP (note, 0);
14347 else if (LABEL_P (label))
14348 LABEL_NUSES (label)--;
14351 if (place2 && JUMP_P (place2)
14352 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
14353 && (JUMP_LABEL (place2) == NULL
14354 || JUMP_LABEL (place2) == XEXP (note, 0)))
14356 rtx label = JUMP_LABEL (place2);
14358 if (!label)
14359 JUMP_LABEL (place2) = XEXP (note, 0);
14360 else if (LABEL_P (label))
14361 LABEL_NUSES (label)--;
14362 place2 = 0;
14364 break;
14366 case REG_NONNEG:
14367 /* This note says something about the value of a register prior
14368 to the execution of an insn. It is too much trouble to see
14369 if the note is still correct in all situations. It is better
14370 to simply delete it. */
14371 break;
14373 case REG_DEAD:
14374 /* If we replaced the right hand side of FROM_INSN with a
14375 REG_EQUAL note, the original use of the dying register
14376 will not have been combined into I3 and I2. In such cases,
14377 FROM_INSN is guaranteed to be the first of the combined
14378 instructions, so we simply need to search back before
14379 FROM_INSN for the previous use or set of this register,
14380 then alter the notes there appropriately.
14382 If the register is used as an input in I3, it dies there.
14383 Similarly for I2, if it is nonzero and adjacent to I3.
14385 If the register is not used as an input in either I3 or I2
14386 and it is not one of the registers we were supposed to eliminate,
14387 there are two possibilities. We might have a non-adjacent I2
14388 or we might have somehow eliminated an additional register
14389 from a computation. For example, we might have had A & B where
14390 we discover that B will always be zero. In this case we will
14391 eliminate the reference to A.
14393 In both cases, we must search to see if we can find a previous
14394 use of A and put the death note there. */
14396 if (from_insn
14397 && from_insn == i2mod
14398 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
14399 tem_insn = from_insn;
14400 else
14402 if (from_insn
14403 && CALL_P (from_insn)
14404 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
14405 place = from_insn;
14406 else if (i2 && reg_set_p (XEXP (note, 0), PATTERN (i2)))
14408 /* If the new I2 sets the same register that is marked
14409 dead in the note, we do not in general know where to
14410 put the note. One important case we _can_ handle is
14411 when the note comes from I3. */
14412 if (from_insn == i3)
14413 place = i3;
14414 else
14415 break;
14417 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
14418 place = i3;
14419 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
14420 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14421 place = i2;
14422 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
14423 && !(i2mod
14424 && reg_overlap_mentioned_p (XEXP (note, 0),
14425 i2mod_old_rhs)))
14426 || rtx_equal_p (XEXP (note, 0), elim_i1)
14427 || rtx_equal_p (XEXP (note, 0), elim_i0))
14428 break;
14429 tem_insn = i3;
14432 if (place == 0)
14434 basic_block bb = this_basic_block;
14436 for (tem_insn = PREV_INSN (tem_insn); place == 0; tem_insn = PREV_INSN (tem_insn))
14438 if (!NONDEBUG_INSN_P (tem_insn))
14440 if (tem_insn == BB_HEAD (bb))
14441 break;
14442 continue;
14445 /* If the register is being set at TEM_INSN, see if that is all
14446 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14447 into a REG_UNUSED note instead. Don't delete sets to
14448 global register vars. */
14449 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
14450 || !global_regs[REGNO (XEXP (note, 0))])
14451 && reg_set_p (XEXP (note, 0), PATTERN (tem_insn)))
14453 rtx set = single_set (tem_insn);
14454 rtx inner_dest = 0;
14455 rtx_insn *cc0_setter = NULL;
14457 if (set != 0)
14458 for (inner_dest = SET_DEST (set);
14459 (GET_CODE (inner_dest) == STRICT_LOW_PART
14460 || GET_CODE (inner_dest) == SUBREG
14461 || GET_CODE (inner_dest) == ZERO_EXTRACT);
14462 inner_dest = XEXP (inner_dest, 0))
14465 /* Verify that it was the set, and not a clobber that
14466 modified the register.
14468 CC0 targets must be careful to maintain setter/user
14469 pairs. If we cannot delete the setter due to side
14470 effects, mark the user with an UNUSED note instead
14471 of deleting it. */
14473 if (set != 0 && ! side_effects_p (SET_SRC (set))
14474 && rtx_equal_p (XEXP (note, 0), inner_dest)
14475 && (!HAVE_cc0
14476 || (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
14477 || ((cc0_setter = prev_cc0_setter (tem_insn)) != NULL
14478 && sets_cc0_p (PATTERN (cc0_setter)) > 0))))
14480 /* Move the notes and links of TEM_INSN elsewhere.
14481 This might delete other dead insns recursively.
14482 First set the pattern to something that won't use
14483 any register. */
14484 rtx old_notes = REG_NOTES (tem_insn);
14486 PATTERN (tem_insn) = pc_rtx;
14487 REG_NOTES (tem_insn) = NULL;
14489 distribute_notes (old_notes, tem_insn, tem_insn, NULL,
14490 NULL_RTX, NULL_RTX, NULL_RTX);
14491 distribute_links (LOG_LINKS (tem_insn));
14493 unsigned int regno = REGNO (XEXP (note, 0));
14494 reg_stat_type *rsp = &reg_stat[regno];
14495 if (rsp->last_set == tem_insn)
14496 record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14498 SET_INSN_DELETED (tem_insn);
14499 if (tem_insn == i2)
14500 i2 = NULL;
14502 /* Delete the setter too. */
14503 if (cc0_setter)
14505 PATTERN (cc0_setter) = pc_rtx;
14506 old_notes = REG_NOTES (cc0_setter);
14507 REG_NOTES (cc0_setter) = NULL;
14509 distribute_notes (old_notes, cc0_setter,
14510 cc0_setter, NULL,
14511 NULL_RTX, NULL_RTX, NULL_RTX);
14512 distribute_links (LOG_LINKS (cc0_setter));
14514 SET_INSN_DELETED (cc0_setter);
14515 if (cc0_setter == i2)
14516 i2 = NULL;
14519 else
14521 PUT_REG_NOTE_KIND (note, REG_UNUSED);
14523 /* If there isn't already a REG_UNUSED note, put one
14524 here. Do not place a REG_DEAD note, even if
14525 the register is also used here; that would not
14526 match the algorithm used in lifetime analysis
14527 and can cause the consistency check in the
14528 scheduler to fail. */
14529 if (! find_regno_note (tem_insn, REG_UNUSED,
14530 REGNO (XEXP (note, 0))))
14531 place = tem_insn;
14532 break;
14535 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem_insn))
14536 || (CALL_P (tem_insn)
14537 && find_reg_fusage (tem_insn, USE, XEXP (note, 0))))
14539 place = tem_insn;
14541 /* If we are doing a 3->2 combination, and we have a
14542 register which formerly died in i3 and was not used
14543 by i2, which now no longer dies in i3 and is used in
14544 i2 but does not die in i2, and place is between i2
14545 and i3, then we may need to move a link from place to
14546 i2. */
14547 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
14548 && from_insn
14549 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
14550 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14552 struct insn_link *links = LOG_LINKS (place);
14553 LOG_LINKS (place) = NULL;
14554 distribute_links (links);
14556 break;
14559 if (tem_insn == BB_HEAD (bb))
14560 break;
14565 /* If the register is set or already dead at PLACE, we needn't do
14566 anything with this note if it is still a REG_DEAD note.
14567 We check here if it is set at all, not if is it totally replaced,
14568 which is what `dead_or_set_p' checks, so also check for it being
14569 set partially. */
14571 if (place && REG_NOTE_KIND (note) == REG_DEAD)
14573 unsigned int regno = REGNO (XEXP (note, 0));
14574 reg_stat_type *rsp = &reg_stat[regno];
14576 if (dead_or_set_p (place, XEXP (note, 0))
14577 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
14579 /* Unless the register previously died in PLACE, clear
14580 last_death. [I no longer understand why this is
14581 being done.] */
14582 if (rsp->last_death != place)
14583 rsp->last_death = 0;
14584 place = 0;
14586 else
14587 rsp->last_death = place;
14589 /* If this is a death note for a hard reg that is occupying
14590 multiple registers, ensure that we are still using all
14591 parts of the object. If we find a piece of the object
14592 that is unused, we must arrange for an appropriate REG_DEAD
14593 note to be added for it. However, we can't just emit a USE
14594 and tag the note to it, since the register might actually
14595 be dead; so we recourse, and the recursive call then finds
14596 the previous insn that used this register. */
14598 if (place && REG_NREGS (XEXP (note, 0)) > 1)
14600 unsigned int endregno = END_REGNO (XEXP (note, 0));
14601 bool all_used = true;
14602 unsigned int i;
14604 for (i = regno; i < endregno; i++)
14605 if ((! refers_to_regno_p (i, PATTERN (place))
14606 && ! find_regno_fusage (place, USE, i))
14607 || dead_or_set_regno_p (place, i))
14609 all_used = false;
14610 break;
14613 if (! all_used)
14615 /* Put only REG_DEAD notes for pieces that are
14616 not already dead or set. */
14618 for (i = regno; i < endregno;
14619 i += hard_regno_nregs (i, reg_raw_mode[i]))
14621 rtx piece = regno_reg_rtx[i];
14622 basic_block bb = this_basic_block;
14624 if (! dead_or_set_p (place, piece)
14625 && ! reg_bitfield_target_p (piece,
14626 PATTERN (place)))
14628 rtx new_note = alloc_reg_note (REG_DEAD, piece,
14629 NULL_RTX);
14631 distribute_notes (new_note, place, place,
14632 NULL, NULL_RTX, NULL_RTX,
14633 NULL_RTX);
14635 else if (! refers_to_regno_p (i, PATTERN (place))
14636 && ! find_regno_fusage (place, USE, i))
14637 for (tem_insn = PREV_INSN (place); ;
14638 tem_insn = PREV_INSN (tem_insn))
14640 if (!NONDEBUG_INSN_P (tem_insn))
14642 if (tem_insn == BB_HEAD (bb))
14643 break;
14644 continue;
14646 if (dead_or_set_p (tem_insn, piece)
14647 || reg_bitfield_target_p (piece,
14648 PATTERN (tem_insn)))
14650 add_reg_note (tem_insn, REG_UNUSED, piece);
14651 break;
14656 place = 0;
14660 break;
14662 default:
14663 /* Any other notes should not be present at this point in the
14664 compilation. */
14665 gcc_unreachable ();
14668 if (place)
14670 XEXP (note, 1) = REG_NOTES (place);
14671 REG_NOTES (place) = note;
14673 /* Set added_notes_insn to the earliest insn we added a note to. */
14674 if (added_notes_insn == 0
14675 || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place))
14676 added_notes_insn = place;
14679 if (place2)
14681 add_shallow_copy_of_reg_note (place2, note);
14683 /* Set added_notes_insn to the earliest insn we added a note to. */
14684 if (added_notes_insn == 0
14685 || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place2))
14686 added_notes_insn = place2;
14691 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14692 I3, I2, and I1 to new locations. This is also called to add a link
14693 pointing at I3 when I3's destination is changed. */
14695 static void
14696 distribute_links (struct insn_link *links)
14698 struct insn_link *link, *next_link;
14700 for (link = links; link; link = next_link)
14702 rtx_insn *place = 0;
14703 rtx_insn *insn;
14704 rtx set, reg;
14706 next_link = link->next;
14708 /* If the insn that this link points to is a NOTE, ignore it. */
14709 if (NOTE_P (link->insn))
14710 continue;
14712 set = 0;
14713 rtx pat = PATTERN (link->insn);
14714 if (GET_CODE (pat) == SET)
14715 set = pat;
14716 else if (GET_CODE (pat) == PARALLEL)
14718 int i;
14719 for (i = 0; i < XVECLEN (pat, 0); i++)
14721 set = XVECEXP (pat, 0, i);
14722 if (GET_CODE (set) != SET)
14723 continue;
14725 reg = SET_DEST (set);
14726 while (GET_CODE (reg) == ZERO_EXTRACT
14727 || GET_CODE (reg) == STRICT_LOW_PART
14728 || GET_CODE (reg) == SUBREG)
14729 reg = XEXP (reg, 0);
14731 if (!REG_P (reg))
14732 continue;
14734 if (REGNO (reg) == link->regno)
14735 break;
14737 if (i == XVECLEN (pat, 0))
14738 continue;
14740 else
14741 continue;
14743 reg = SET_DEST (set);
14745 while (GET_CODE (reg) == ZERO_EXTRACT
14746 || GET_CODE (reg) == STRICT_LOW_PART
14747 || GET_CODE (reg) == SUBREG)
14748 reg = XEXP (reg, 0);
14750 /* A LOG_LINK is defined as being placed on the first insn that uses
14751 a register and points to the insn that sets the register. Start
14752 searching at the next insn after the target of the link and stop
14753 when we reach a set of the register or the end of the basic block.
14755 Note that this correctly handles the link that used to point from
14756 I3 to I2. Also note that not much searching is typically done here
14757 since most links don't point very far away. */
14759 for (insn = NEXT_INSN (link->insn);
14760 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
14761 || BB_HEAD (this_basic_block->next_bb) != insn));
14762 insn = NEXT_INSN (insn))
14763 if (DEBUG_INSN_P (insn))
14764 continue;
14765 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
14767 if (reg_referenced_p (reg, PATTERN (insn)))
14768 place = insn;
14769 break;
14771 else if (CALL_P (insn)
14772 && find_reg_fusage (insn, USE, reg))
14774 place = insn;
14775 break;
14777 else if (INSN_P (insn) && reg_set_p (reg, insn))
14778 break;
14780 /* If we found a place to put the link, place it there unless there
14781 is already a link to the same insn as LINK at that point. */
14783 if (place)
14785 struct insn_link *link2;
14787 FOR_EACH_LOG_LINK (link2, place)
14788 if (link2->insn == link->insn && link2->regno == link->regno)
14789 break;
14791 if (link2 == NULL)
14793 link->next = LOG_LINKS (place);
14794 LOG_LINKS (place) = link;
14796 /* Set added_links_insn to the earliest insn we added a
14797 link to. */
14798 if (added_links_insn == 0
14799 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
14800 added_links_insn = place;
14806 /* Check for any register or memory mentioned in EQUIV that is not
14807 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14808 of EXPR where some registers may have been replaced by constants. */
14810 static bool
14811 unmentioned_reg_p (rtx equiv, rtx expr)
14813 subrtx_iterator::array_type array;
14814 FOR_EACH_SUBRTX (iter, array, equiv, NONCONST)
14816 const_rtx x = *iter;
14817 if ((REG_P (x) || MEM_P (x))
14818 && !reg_mentioned_p (x, expr))
14819 return true;
14821 return false;
14824 DEBUG_FUNCTION void
14825 dump_combine_stats (FILE *file)
14827 fprintf
14828 (file,
14829 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14830 combine_attempts, combine_merges, combine_extras, combine_successes);
14833 void
14834 dump_combine_total_stats (FILE *file)
14836 fprintf
14837 (file,
14838 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14839 total_attempts, total_merges, total_extras, total_successes);
14842 /* Try combining insns through substitution. */
14843 static unsigned int
14844 rest_of_handle_combine (void)
14846 int rebuild_jump_labels_after_combine;
14848 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
14849 df_note_add_problem ();
14850 df_analyze ();
14852 regstat_init_n_sets_and_refs ();
14853 reg_n_sets_max = max_reg_num ();
14855 rebuild_jump_labels_after_combine
14856 = combine_instructions (get_insns (), max_reg_num ());
14858 /* Combining insns may have turned an indirect jump into a
14859 direct jump. Rebuild the JUMP_LABEL fields of jumping
14860 instructions. */
14861 if (rebuild_jump_labels_after_combine)
14863 if (dom_info_available_p (CDI_DOMINATORS))
14864 free_dominance_info (CDI_DOMINATORS);
14865 timevar_push (TV_JUMP);
14866 rebuild_jump_labels (get_insns ());
14867 cleanup_cfg (0);
14868 timevar_pop (TV_JUMP);
14871 regstat_free_n_sets_and_refs ();
14872 return 0;
14875 namespace {
14877 const pass_data pass_data_combine =
14879 RTL_PASS, /* type */
14880 "combine", /* name */
14881 OPTGROUP_NONE, /* optinfo_flags */
14882 TV_COMBINE, /* tv_id */
14883 PROP_cfglayout, /* properties_required */
14884 0, /* properties_provided */
14885 0, /* properties_destroyed */
14886 0, /* todo_flags_start */
14887 TODO_df_finish, /* todo_flags_finish */
14890 class pass_combine : public rtl_opt_pass
14892 public:
14893 pass_combine (gcc::context *ctxt)
14894 : rtl_opt_pass (pass_data_combine, ctxt)
14897 /* opt_pass methods: */
14898 virtual bool gate (function *) { return (optimize > 0); }
14899 virtual unsigned int execute (function *)
14901 return rest_of_handle_combine ();
14904 }; // class pass_combine
14906 } // anon namespace
14908 rtl_opt_pass *
14909 make_pass_combine (gcc::context *ctxt)
14911 return new pass_combine (ctxt);