1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;; This gcc Version 2 machine description is inspired by sparc.md and
26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;; Uses of UNSPEC in this file:
31 [(UNSPEC_CFFC 0) ; canonicalize_funcptr_for_compare
32 (UNSPEC_GOTO 1) ; indirect_goto
33 (UNSPEC_DLTIND14R 2) ;
42 (UNSPEC_TLSLDM_PIC 11)
49 [(UNSPECV_BLOCKAGE 0) ; blockage
50 (UNSPECV_DCACHE 1) ; dcacheflush
51 (UNSPECV_ICACHE 2) ; icacheflush
52 (UNSPECV_OPC 3) ; outline_prologue_call
53 (UNSPECV_OEC 4) ; outline_epilogue_call
54 (UNSPECV_LONGJMP 5) ; builtin_longjmp
57 ;; Maximum pc-relative branch offsets.
59 ;; These numbers are a bit smaller than the maximum allowable offsets
60 ;; so that a few instructions may be inserted before the actual branch.
63 [(MAX_12BIT_OFFSET 8184) ; 12-bit branch
64 (MAX_17BIT_OFFSET 262100) ; 17-bit branch
67 ;; Mode and code iterators
69 ;; This mode iterator allows :P to be used for patterns that operate on
70 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
71 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
73 ;; This attribute defines the condition prefix for word and double word
74 ;; add, compare, subtract and logical instructions.
75 (define_mode_attr dwc [(SI "") (DI "*")])
77 ;; Insn type. Used to default other attribute values.
79 ;; type "unary" insns have one input operand (1) and one output operand (0)
80 ;; type "binary" insns have two input operands (1,2) and one output (0)
83 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch,fpstore_load,store_fpload"
84 (const_string "binary"))
86 (define_attr "pa_combine_type"
87 "fmpy,faddsub,uncond_branch,addmove,none"
88 (const_string "none"))
90 ;; Processor type (for scheduling, not code generation) -- this attribute
91 ;; must exactly match the processor_type enumeration in pa.h.
93 ;; FIXME: Add 800 scheduling for completeness?
95 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
97 ;; Length (in # of bytes).
98 (define_attr "length" ""
99 (cond [(eq_attr "type" "load,fpload")
100 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
101 (const_int 8) (const_int 4))
103 (eq_attr "type" "store,fpstore")
104 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
105 (const_int 8) (const_int 4))
107 (eq_attr "type" "binary,shift,nullshift")
108 (if_then_else (match_operand 2 "arith_operand" "")
109 (const_int 4) (const_int 12))
111 (eq_attr "type" "move,unary,shift,nullshift")
112 (if_then_else (match_operand 1 "arith_operand" "")
113 (const_int 4) (const_int 8))]
117 (define_asm_attributes
118 [(set_attr "length" "4")
119 (set_attr "type" "multi")])
121 ;; Attributes for instruction and branch scheduling
123 ;; For conditional branches.
124 (define_attr "in_branch_delay" "false,true"
125 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
126 (eq_attr "length" "4"))
127 (const_string "true")
128 (const_string "false")))
130 ;; Disallow instructions which use the FPU since they will tie up the FPU
131 ;; even if the instruction is nullified.
132 (define_attr "in_nullified_branch_delay" "false,true"
133 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
134 (eq_attr "length" "4"))
135 (const_string "true")
136 (const_string "false")))
138 ;; For calls and millicode calls. Allow unconditional branches in the
140 (define_attr "in_call_delay" "false,true"
141 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
142 (eq_attr "length" "4"))
143 (const_string "true")
144 (eq_attr "type" "uncond_branch")
145 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
147 (const_string "true")
148 (const_string "false"))]
149 (const_string "false")))
152 ;; Call delay slot description.
153 (define_delay (eq_attr "type" "call")
154 [(eq_attr "in_call_delay" "true") (nil) (nil)])
156 ;; Millicode call delay slot description.
157 (define_delay (eq_attr "type" "milli")
158 [(eq_attr "in_call_delay" "true") (nil) (nil)])
160 ;; Return and other similar instructions.
161 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
162 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
164 ;; Floating point conditional branch delay slot description.
165 (define_delay (eq_attr "type" "fbranch")
166 [(eq_attr "in_branch_delay" "true")
167 (eq_attr "in_nullified_branch_delay" "true")
170 ;; Integer conditional branch delay slot description.
171 ;; Nullification of conditional branches on the PA is dependent on the
172 ;; direction of the branch. Forward branches nullify true and
173 ;; backward branches nullify false. If the direction is unknown
174 ;; then nullification is not allowed.
175 (define_delay (eq_attr "type" "cbranch")
176 [(eq_attr "in_branch_delay" "true")
177 (and (eq_attr "in_nullified_branch_delay" "true")
178 (attr_flag "forward"))
179 (and (eq_attr "in_nullified_branch_delay" "true")
180 (attr_flag "backward"))])
182 (define_delay (and (eq_attr "type" "uncond_branch")
183 (eq (symbol_ref "following_call (insn)")
185 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
187 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
188 ;; load: 2, fpload: 3
189 ;; store, fpstore: 3, no D-cache operations should be scheduled.
191 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
193 ;; Instruction Time Unit Minimum Distance (unit contention)
200 ;; fmpyadd 3 ALU,MPY 2
201 ;; fmpysub 3 ALU,MPY 2
202 ;; fmpycfxt 3 ALU,MPY 2
205 ;; fdiv,sgl 10 MPY 10
206 ;; fdiv,dbl 12 MPY 12
207 ;; fsqrt,sgl 14 MPY 14
208 ;; fsqrt,dbl 18 MPY 18
210 ;; We don't model fmpyadd/fmpysub properly as those instructions
211 ;; keep both the FP ALU and MPY units busy. Given that these
212 ;; processors are obsolete, I'm not going to spend the time to
213 ;; model those instructions correctly.
215 (define_automaton "pa700")
216 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
218 (define_insn_reservation "W0" 4
219 (and (eq_attr "type" "fpcc")
220 (eq_attr "cpu" "700"))
223 (define_insn_reservation "W1" 3
224 (and (eq_attr "type" "fpalu")
225 (eq_attr "cpu" "700"))
228 (define_insn_reservation "W2" 3
229 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
230 (eq_attr "cpu" "700"))
233 (define_insn_reservation "W3" 10
234 (and (eq_attr "type" "fpdivsgl")
235 (eq_attr "cpu" "700"))
238 (define_insn_reservation "W4" 12
239 (and (eq_attr "type" "fpdivdbl")
240 (eq_attr "cpu" "700"))
243 (define_insn_reservation "W5" 14
244 (and (eq_attr "type" "fpsqrtsgl")
245 (eq_attr "cpu" "700"))
248 (define_insn_reservation "W6" 18
249 (and (eq_attr "type" "fpsqrtdbl")
250 (eq_attr "cpu" "700"))
253 (define_insn_reservation "W7" 2
254 (and (eq_attr "type" "load")
255 (eq_attr "cpu" "700"))
258 (define_insn_reservation "W8" 2
259 (and (eq_attr "type" "fpload")
260 (eq_attr "cpu" "700"))
263 (define_insn_reservation "W9" 3
264 (and (eq_attr "type" "store")
265 (eq_attr "cpu" "700"))
268 (define_insn_reservation "W10" 3
269 (and (eq_attr "type" "fpstore")
270 (eq_attr "cpu" "700"))
273 (define_insn_reservation "W11" 5
274 (and (eq_attr "type" "fpstore_load")
275 (eq_attr "cpu" "700"))
278 (define_insn_reservation "W12" 6
279 (and (eq_attr "type" "store_fpload")
280 (eq_attr "cpu" "700"))
283 (define_insn_reservation "W13" 1
284 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
285 (eq_attr "cpu" "700"))
288 ;; We have a bypass for all computations in the FP unit which feed an
289 ;; FP store as long as the sizes are the same.
290 (define_bypass 2 "W1,W2" "W10,W11" "hppa_fpstore_bypass_p")
291 (define_bypass 9 "W3" "W10,W11" "hppa_fpstore_bypass_p")
292 (define_bypass 11 "W4" "W10,W11" "hppa_fpstore_bypass_p")
293 (define_bypass 13 "W5" "W10,W11" "hppa_fpstore_bypass_p")
294 (define_bypass 17 "W6" "W10,W11" "hppa_fpstore_bypass_p")
296 ;; We have an "anti-bypass" for FP loads which feed an FP store.
297 (define_bypass 4 "W8,W12" "W10,W11" "hppa_fpstore_bypass_p")
299 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
300 ;; floating point computations with non-floating point computations (fp loads
301 ;; and stores are not fp computations).
303 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
304 ;; take two cycles, during which no Dcache operations should be scheduled.
305 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
306 ;; all have the same memory characteristics if one disregards cache misses.
308 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
309 ;; There's no value in modeling the ALU and MUL separately though
310 ;; since there can never be a functional unit conflict given the
311 ;; latency and issue rates for those units.
314 ;; Instruction Time Unit Minimum Distance (unit contention)
321 ;; fmpyadd 2 ALU,MPY 1
322 ;; fmpysub 2 ALU,MPY 1
323 ;; fmpycfxt 2 ALU,MPY 1
327 ;; fdiv,dbl 15 DIV 15
329 ;; fsqrt,dbl 15 DIV 15
331 (define_automaton "pa7100")
332 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
334 (define_insn_reservation "X0" 2
335 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
336 (eq_attr "cpu" "7100"))
339 (define_insn_reservation "X1" 8
340 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
341 (eq_attr "cpu" "7100"))
342 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
344 (define_insn_reservation "X2" 15
345 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
346 (eq_attr "cpu" "7100"))
347 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
349 (define_insn_reservation "X3" 2
350 (and (eq_attr "type" "load")
351 (eq_attr "cpu" "7100"))
354 (define_insn_reservation "X4" 2
355 (and (eq_attr "type" "fpload")
356 (eq_attr "cpu" "7100"))
359 (define_insn_reservation "X5" 2
360 (and (eq_attr "type" "store")
361 (eq_attr "cpu" "7100"))
362 "i_7100+mem_7100,mem_7100")
364 (define_insn_reservation "X6" 2
365 (and (eq_attr "type" "fpstore")
366 (eq_attr "cpu" "7100"))
367 "i_7100+mem_7100,mem_7100")
369 (define_insn_reservation "X7" 4
370 (and (eq_attr "type" "fpstore_load")
371 (eq_attr "cpu" "7100"))
372 "i_7100+mem_7100,mem_7100*3")
374 (define_insn_reservation "X8" 4
375 (and (eq_attr "type" "store_fpload")
376 (eq_attr "cpu" "7100"))
377 "i_7100+mem_7100,mem_7100*3")
379 (define_insn_reservation "X9" 1
380 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
381 (eq_attr "cpu" "7100"))
384 ;; We have a bypass for all computations in the FP unit which feed an
385 ;; FP store as long as the sizes are the same.
386 (define_bypass 1 "X0" "X6,X7" "hppa_fpstore_bypass_p")
387 (define_bypass 7 "X1" "X6,X7" "hppa_fpstore_bypass_p")
388 (define_bypass 14 "X2" "X6,X7" "hppa_fpstore_bypass_p")
390 ;; We have an "anti-bypass" for FP loads which feed an FP store.
391 (define_bypass 3 "X4,X8" "X6,X7" "hppa_fpstore_bypass_p")
393 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
394 ;; There's no value in modeling the ALU and MUL separately though
395 ;; since there can never be a functional unit conflict that
396 ;; can be avoided given the latency, issue rates and mandatory
397 ;; one cycle cpu-wide lock for a double precision fp multiply.
400 ;; Instruction Time Unit Minimum Distance (unit contention)
407 ;; fmpyadd,sgl 2 ALU,MPY 1
408 ;; fmpyadd,dbl 3 ALU,MPY 2
409 ;; fmpysub,sgl 2 ALU,MPY 1
410 ;; fmpysub,dbl 3 ALU,MPY 2
411 ;; fmpycfxt,sgl 2 ALU,MPY 1
412 ;; fmpycfxt,dbl 3 ALU,MPY 2
417 ;; fdiv,dbl 15 DIV 15
419 ;; fsqrt,dbl 15 DIV 15
421 ;; The PA7200 is just like the PA7100LC except that there is
422 ;; no store-store penalty.
424 ;; The PA7300 is just like the PA7200 except that there is
425 ;; no store-load penalty.
427 ;; Note there are some aspects of the 7100LC we are not modeling
428 ;; at the moment. I'll be reviewing the 7100LC scheduling info
429 ;; shortly and updating this description.
433 ;; other issue modeling
435 (define_automaton "pa7100lc")
436 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
437 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
438 (define_cpu_unit "mem_7100lc" "pa7100lc")
440 ;; Double precision multiplies lock the entire CPU for one
441 ;; cycle. There is no way to avoid this lock and trying to
442 ;; schedule around the lock is pointless and thus there is no
443 ;; value in trying to model this lock.
445 ;; Not modeling the lock allows us to treat fp multiplies just
446 ;; like any other FP alu instruction. It allows for a smaller
447 ;; DFA and may reduce register pressure.
448 (define_insn_reservation "Y0" 2
449 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
450 (eq_attr "cpu" "7100LC,7200,7300"))
451 "f_7100lc,fpmac_7100lc")
453 ;; fp division and sqrt instructions lock the entire CPU for
454 ;; 7 cycles (single precision) or 14 cycles (double precision).
455 ;; There is no way to avoid this lock and trying to schedule
456 ;; around the lock is pointless and thus there is no value in
457 ;; trying to model this lock. Not modeling the lock allows
458 ;; for a smaller DFA and may reduce register pressure.
459 (define_insn_reservation "Y1" 1
460 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
461 (eq_attr "cpu" "7100LC,7200,7300"))
464 (define_insn_reservation "Y2" 2
465 (and (eq_attr "type" "load")
466 (eq_attr "cpu" "7100LC,7200,7300"))
467 "i1_7100lc+mem_7100lc")
469 (define_insn_reservation "Y3" 2
470 (and (eq_attr "type" "fpload")
471 (eq_attr "cpu" "7100LC,7200,7300"))
472 "i1_7100lc+mem_7100lc")
474 (define_insn_reservation "Y4" 2
475 (and (eq_attr "type" "store")
476 (eq_attr "cpu" "7100LC"))
477 "i1_7100lc+mem_7100lc,mem_7100lc")
479 (define_insn_reservation "Y5" 2
480 (and (eq_attr "type" "fpstore")
481 (eq_attr "cpu" "7100LC"))
482 "i1_7100lc+mem_7100lc,mem_7100lc")
484 (define_insn_reservation "Y6" 4
485 (and (eq_attr "type" "fpstore_load")
486 (eq_attr "cpu" "7100LC"))
487 "i1_7100lc+mem_7100lc,mem_7100lc*3")
489 (define_insn_reservation "Y7" 4
490 (and (eq_attr "type" "store_fpload")
491 (eq_attr "cpu" "7100LC"))
492 "i1_7100lc+mem_7100lc,mem_7100lc*3")
494 (define_insn_reservation "Y8" 1
495 (and (eq_attr "type" "shift,nullshift")
496 (eq_attr "cpu" "7100LC,7200,7300"))
499 (define_insn_reservation "Y9" 1
500 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
501 (eq_attr "cpu" "7100LC,7200,7300"))
502 "(i0_7100lc|i1_7100lc)")
504 ;; The 7200 has a store-load penalty
505 (define_insn_reservation "Y10" 2
506 (and (eq_attr "type" "store")
507 (eq_attr "cpu" "7200"))
508 "i1_7100lc,mem_7100lc")
510 (define_insn_reservation "Y11" 2
511 (and (eq_attr "type" "fpstore")
512 (eq_attr "cpu" "7200"))
513 "i1_7100lc,mem_7100lc")
515 (define_insn_reservation "Y12" 4
516 (and (eq_attr "type" "fpstore_load")
517 (eq_attr "cpu" "7200"))
518 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
520 (define_insn_reservation "Y13" 4
521 (and (eq_attr "type" "store_fpload")
522 (eq_attr "cpu" "7200"))
523 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
525 ;; The 7300 has no penalty for store-store or store-load
526 (define_insn_reservation "Y14" 2
527 (and (eq_attr "type" "store")
528 (eq_attr "cpu" "7300"))
531 (define_insn_reservation "Y15" 2
532 (and (eq_attr "type" "fpstore")
533 (eq_attr "cpu" "7300"))
536 (define_insn_reservation "Y16" 4
537 (and (eq_attr "type" "fpstore_load")
538 (eq_attr "cpu" "7300"))
539 "i1_7100lc,i1_7100lc+mem_7100lc")
541 (define_insn_reservation "Y17" 4
542 (and (eq_attr "type" "store_fpload")
543 (eq_attr "cpu" "7300"))
544 "i1_7100lc,i1_7100lc+mem_7100lc")
546 ;; We have an "anti-bypass" for FP loads which feed an FP store.
547 (define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "hppa_fpstore_bypass_p")
549 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
550 ;; traditional architecture.
552 ;; The PA8000 has a large (56) entry reorder buffer that is split between
553 ;; memory and non-memory operations.
555 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
556 ;; the function units, with the exception of branches and multi-output
557 ;; instructions. The PA8000 can retire two non-memory operations per cycle
558 ;; and two memory operations per cycle, only one of which may be a store.
560 ;; Given the large reorder buffer, the processor can hide most latencies.
561 ;; According to HP, they've got the best results by scheduling for retirement
562 ;; bandwidth with limited latency scheduling for floating point operations.
563 ;; Latency for integer operations and memory references is ignored.
566 ;; We claim floating point operations have a 2 cycle latency and are
567 ;; fully pipelined, except for div and sqrt which are not pipelined and
568 ;; take from 17 to 31 cycles to complete.
570 ;; It's worth noting that there is no way to saturate all the functional
571 ;; units on the PA8000 as there is not enough issue bandwidth.
573 (define_automaton "pa8000")
574 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
575 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
576 (define_cpu_unit "store_8000" "pa8000")
577 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
578 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
579 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
580 (define_reservation "im_8000" "im0_8000 | im1_8000")
581 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
582 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
583 (define_reservation "f_8000" "f0_8000 | f1_8000")
584 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
586 ;; We can issue any two memops per cycle, but we can only retire
587 ;; one memory store per cycle. We assume that the reorder buffer
588 ;; will hide any memory latencies per HP's recommendation.
589 (define_insn_reservation "Z0" 0
591 (eq_attr "type" "load,fpload")
592 (eq_attr "cpu" "8000"))
595 (define_insn_reservation "Z1" 0
597 (eq_attr "type" "store,fpstore")
598 (eq_attr "cpu" "8000"))
599 "im_8000,rm_8000+store_8000")
601 (define_insn_reservation "Z2" 0
602 (and (eq_attr "type" "fpstore_load,store_fpload")
603 (eq_attr "cpu" "8000"))
604 "im_8000,rm_8000+store_8000,im_8000,rm_8000")
606 ;; We can issue and retire two non-memory operations per cycle with
607 ;; a few exceptions (branches). This group catches those we want
608 ;; to assume have zero latency.
609 (define_insn_reservation "Z3" 0
611 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
612 (eq_attr "cpu" "8000"))
615 ;; Branches use both slots in the non-memory issue and
617 (define_insn_reservation "Z4" 0
619 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
620 (eq_attr "cpu" "8000"))
621 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
623 ;; We partial latency schedule the floating point units.
624 ;; They can issue/retire two at a time in the non-memory
625 ;; units. We fix their latency at 2 cycles and they
626 ;; are fully pipelined.
627 (define_insn_reservation "Z5" 1
629 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
630 (eq_attr "cpu" "8000"))
631 "inm_8000,f_8000,rnm_8000")
633 ;; The fdivsqrt units are not pipelined and have a very long latency.
634 ;; To keep the DFA from exploding, we do not show all the
635 ;; reservations for the divsqrt unit.
636 (define_insn_reservation "Z6" 17
638 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
639 (eq_attr "cpu" "8000"))
640 "inm_8000,fdivsqrt_8000*6,rnm_8000")
642 (define_insn_reservation "Z7" 31
644 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
645 (eq_attr "cpu" "8000"))
646 "inm_8000,fdivsqrt_8000*6,rnm_8000")
648 ;; Operand and operator predicates and constraints
650 (include "predicates.md")
651 (include "constraints.md")
653 ;; Compare instructions.
654 ;; This controls RTL generation and register allocation.
658 (match_operator:CCFP 2 "comparison_operator"
659 [(match_operand:SF 0 "reg_or_0_operand" "fG")
660 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
661 "! TARGET_SOFT_FLOAT"
662 "fcmp,sgl,%Y2 %f0,%f1"
663 [(set_attr "length" "4")
664 (set_attr "type" "fpcc")])
668 (match_operator:CCFP 2 "comparison_operator"
669 [(match_operand:DF 0 "reg_or_0_operand" "fG")
670 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
671 "! TARGET_SOFT_FLOAT"
672 "fcmp,dbl,%Y2 %f0,%f1"
673 [(set_attr "length" "4")
674 (set_attr "type" "fpcc")])
676 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
677 ;; placeholders. This is necessary in rare situations when a
678 ;; placeholder is re-emitted (see PR 8705).
680 (define_expand "movccfp"
682 (match_operand 0 "const_int_operand" ""))]
683 "! TARGET_SOFT_FLOAT"
686 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
690 ;; The following patterns are optimization placeholders. In almost
691 ;; all cases, the user of the condition code will be simplified and the
692 ;; original condition code setting insn should be eliminated.
694 (define_insn "*movccfp0"
697 "! TARGET_SOFT_FLOAT"
698 "fcmp,dbl,= %%fr0,%%fr0"
699 [(set_attr "length" "4")
700 (set_attr "type" "fpcc")])
702 (define_insn "*movccfp1"
705 "! TARGET_SOFT_FLOAT"
706 "fcmp,dbl,!= %%fr0,%%fr0"
707 [(set_attr "length" "4")
708 (set_attr "type" "fpcc")])
712 (define_expand "cstoresi4"
713 [(set (match_operand:SI 0 "register_operand")
714 (match_operator:SI 1 "ordered_comparison_operator"
715 [(match_operand:SI 2 "reg_or_0_operand" "")
716 (match_operand:SI 3 "arith5_operand" "")]))]
720 ;; Instruction canonicalization puts immediate operands second, which
721 ;; is the reverse of what we want.
724 [(set (match_operand:SI 0 "register_operand" "=r")
725 (match_operator:SI 3 "comparison_operator"
726 [(match_operand:SI 1 "register_operand" "r")
727 (match_operand:SI 2 "arith11_operand" "rI")]))]
729 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
730 [(set_attr "type" "binary")
731 (set_attr "length" "8")])
734 [(set (match_operand:DI 0 "register_operand" "=r")
735 (match_operator:DI 3 "comparison_operator"
736 [(match_operand:DI 1 "register_operand" "r")
737 (match_operand:DI 2 "arith11_operand" "rI")]))]
739 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
740 [(set_attr "type" "binary")
741 (set_attr "length" "8")])
743 (define_insn "iorscc"
744 [(set (match_operand:SI 0 "register_operand" "=r")
745 (ior:SI (match_operator:SI 3 "comparison_operator"
746 [(match_operand:SI 1 "register_operand" "r")
747 (match_operand:SI 2 "arith11_operand" "rI")])
748 (match_operator:SI 6 "comparison_operator"
749 [(match_operand:SI 4 "register_operand" "r")
750 (match_operand:SI 5 "arith11_operand" "rI")])))]
752 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
753 [(set_attr "type" "binary")
754 (set_attr "length" "12")])
757 [(set (match_operand:DI 0 "register_operand" "=r")
758 (ior:DI (match_operator:DI 3 "comparison_operator"
759 [(match_operand:DI 1 "register_operand" "r")
760 (match_operand:DI 2 "arith11_operand" "rI")])
761 (match_operator:DI 6 "comparison_operator"
762 [(match_operand:DI 4 "register_operand" "r")
763 (match_operand:DI 5 "arith11_operand" "rI")])))]
765 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
766 [(set_attr "type" "binary")
767 (set_attr "length" "12")])
769 ;; Combiner patterns for common operations performed with the output
770 ;; from an scc insn (negscc and incscc).
771 (define_insn "negscc"
772 [(set (match_operand:SI 0 "register_operand" "=r")
773 (neg:SI (match_operator:SI 3 "comparison_operator"
774 [(match_operand:SI 1 "register_operand" "r")
775 (match_operand:SI 2 "arith11_operand" "rI")])))]
777 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
778 [(set_attr "type" "binary")
779 (set_attr "length" "8")])
782 [(set (match_operand:DI 0 "register_operand" "=r")
783 (neg:DI (match_operator:DI 3 "comparison_operator"
784 [(match_operand:DI 1 "register_operand" "r")
785 (match_operand:DI 2 "arith11_operand" "rI")])))]
787 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
788 [(set_attr "type" "binary")
789 (set_attr "length" "8")])
791 ;; Patterns for adding/subtracting the result of a boolean expression from
792 ;; a register. First we have special patterns that make use of the carry
793 ;; bit, and output only two instructions. For the cases we can't in
794 ;; general do in two instructions, the incscc pattern at the end outputs
795 ;; two or three instructions.
798 [(set (match_operand:SI 0 "register_operand" "=r")
799 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
800 (match_operand:SI 3 "arith11_operand" "rI"))
801 (match_operand:SI 1 "register_operand" "r")))]
803 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
804 [(set_attr "type" "binary")
805 (set_attr "length" "8")])
808 [(set (match_operand:DI 0 "register_operand" "=r")
809 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
810 (match_operand:DI 3 "arith11_operand" "rI"))
811 (match_operand:DI 1 "register_operand" "r")))]
813 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
814 [(set_attr "type" "binary")
815 (set_attr "length" "8")])
817 ; This need only accept registers for op3, since canonicalization
818 ; replaces geu with gtu when op3 is an integer.
820 [(set (match_operand:SI 0 "register_operand" "=r")
821 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
822 (match_operand:SI 3 "register_operand" "r"))
823 (match_operand:SI 1 "register_operand" "r")))]
825 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
826 [(set_attr "type" "binary")
827 (set_attr "length" "8")])
830 [(set (match_operand:DI 0 "register_operand" "=r")
831 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
832 (match_operand:DI 3 "register_operand" "r"))
833 (match_operand:DI 1 "register_operand" "r")))]
835 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
836 [(set_attr "type" "binary")
837 (set_attr "length" "8")])
839 ; Match only integers for op3 here. This is used as canonical form of the
840 ; geu pattern when op3 is an integer. Don't match registers since we can't
841 ; make better code than the general incscc pattern.
843 [(set (match_operand:SI 0 "register_operand" "=r")
844 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
845 (match_operand:SI 3 "int11_operand" "I"))
846 (match_operand:SI 1 "register_operand" "r")))]
848 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
849 [(set_attr "type" "binary")
850 (set_attr "length" "8")])
853 [(set (match_operand:DI 0 "register_operand" "=r")
854 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
855 (match_operand:DI 3 "int11_operand" "I"))
856 (match_operand:DI 1 "register_operand" "r")))]
858 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
859 [(set_attr "type" "binary")
860 (set_attr "length" "8")])
862 (define_insn "incscc"
863 [(set (match_operand:SI 0 "register_operand" "=r,r")
864 (plus:SI (match_operator:SI 4 "comparison_operator"
865 [(match_operand:SI 2 "register_operand" "r,r")
866 (match_operand:SI 3 "arith11_operand" "rI,rI")])
867 (match_operand:SI 1 "register_operand" "0,?r")))]
870 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
871 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
872 [(set_attr "type" "binary,binary")
873 (set_attr "length" "8,12")])
876 [(set (match_operand:DI 0 "register_operand" "=r,r")
877 (plus:DI (match_operator:DI 4 "comparison_operator"
878 [(match_operand:DI 2 "register_operand" "r,r")
879 (match_operand:DI 3 "arith11_operand" "rI,rI")])
880 (match_operand:DI 1 "register_operand" "0,?r")))]
883 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
884 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
885 [(set_attr "type" "binary,binary")
886 (set_attr "length" "8,12")])
889 [(set (match_operand:SI 0 "register_operand" "=r")
890 (minus:SI (match_operand:SI 1 "register_operand" "r")
891 (gtu:SI (match_operand:SI 2 "register_operand" "r")
892 (match_operand:SI 3 "arith11_operand" "rI"))))]
894 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
895 [(set_attr "type" "binary")
896 (set_attr "length" "8")])
899 [(set (match_operand:DI 0 "register_operand" "=r")
900 (minus:DI (match_operand:DI 1 "register_operand" "r")
901 (gtu:DI (match_operand:DI 2 "register_operand" "r")
902 (match_operand:DI 3 "arith11_operand" "rI"))))]
904 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
905 [(set_attr "type" "binary")
906 (set_attr "length" "8")])
909 [(set (match_operand:SI 0 "register_operand" "=r")
910 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
911 (gtu:SI (match_operand:SI 2 "register_operand" "r")
912 (match_operand:SI 3 "arith11_operand" "rI")))
913 (match_operand:SI 4 "register_operand" "r")))]
915 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
916 [(set_attr "type" "binary")
917 (set_attr "length" "8")])
920 [(set (match_operand:DI 0 "register_operand" "=r")
921 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
922 (gtu:DI (match_operand:DI 2 "register_operand" "r")
923 (match_operand:DI 3 "arith11_operand" "rI")))
924 (match_operand:DI 4 "register_operand" "r")))]
926 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
927 [(set_attr "type" "binary")
928 (set_attr "length" "8")])
930 ; This need only accept registers for op3, since canonicalization
931 ; replaces ltu with leu when op3 is an integer.
933 [(set (match_operand:SI 0 "register_operand" "=r")
934 (minus:SI (match_operand:SI 1 "register_operand" "r")
935 (ltu:SI (match_operand:SI 2 "register_operand" "r")
936 (match_operand:SI 3 "register_operand" "r"))))]
938 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
939 [(set_attr "type" "binary")
940 (set_attr "length" "8")])
943 [(set (match_operand:DI 0 "register_operand" "=r")
944 (minus:DI (match_operand:DI 1 "register_operand" "r")
945 (ltu:DI (match_operand:DI 2 "register_operand" "r")
946 (match_operand:DI 3 "register_operand" "r"))))]
948 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
949 [(set_attr "type" "binary")
950 (set_attr "length" "8")])
953 [(set (match_operand:SI 0 "register_operand" "=r")
954 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
955 (ltu:SI (match_operand:SI 2 "register_operand" "r")
956 (match_operand:SI 3 "register_operand" "r")))
957 (match_operand:SI 4 "register_operand" "r")))]
959 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
960 [(set_attr "type" "binary")
961 (set_attr "length" "8")])
964 [(set (match_operand:DI 0 "register_operand" "=r")
965 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
966 (ltu:DI (match_operand:DI 2 "register_operand" "r")
967 (match_operand:DI 3 "register_operand" "r")))
968 (match_operand:DI 4 "register_operand" "r")))]
970 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
971 [(set_attr "type" "binary")
972 (set_attr "length" "8")])
974 ; Match only integers for op3 here. This is used as canonical form of the
975 ; ltu pattern when op3 is an integer. Don't match registers since we can't
976 ; make better code than the general incscc pattern.
978 [(set (match_operand:SI 0 "register_operand" "=r")
979 (minus:SI (match_operand:SI 1 "register_operand" "r")
980 (leu:SI (match_operand:SI 2 "register_operand" "r")
981 (match_operand:SI 3 "int11_operand" "I"))))]
983 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
984 [(set_attr "type" "binary")
985 (set_attr "length" "8")])
988 [(set (match_operand:DI 0 "register_operand" "=r")
989 (minus:DI (match_operand:DI 1 "register_operand" "r")
990 (leu:DI (match_operand:DI 2 "register_operand" "r")
991 (match_operand:DI 3 "int11_operand" "I"))))]
993 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
994 [(set_attr "type" "binary")
995 (set_attr "length" "8")])
998 [(set (match_operand:SI 0 "register_operand" "=r")
999 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1000 (leu:SI (match_operand:SI 2 "register_operand" "r")
1001 (match_operand:SI 3 "int11_operand" "I")))
1002 (match_operand:SI 4 "register_operand" "r")))]
1004 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1005 [(set_attr "type" "binary")
1006 (set_attr "length" "8")])
1009 [(set (match_operand:DI 0 "register_operand" "=r")
1010 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1011 (leu:DI (match_operand:DI 2 "register_operand" "r")
1012 (match_operand:DI 3 "int11_operand" "I")))
1013 (match_operand:DI 4 "register_operand" "r")))]
1015 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1016 [(set_attr "type" "binary")
1017 (set_attr "length" "8")])
1019 (define_insn "decscc"
1020 [(set (match_operand:SI 0 "register_operand" "=r,r")
1021 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1022 (match_operator:SI 4 "comparison_operator"
1023 [(match_operand:SI 2 "register_operand" "r,r")
1024 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1027 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1028 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1029 [(set_attr "type" "binary,binary")
1030 (set_attr "length" "8,12")])
1033 [(set (match_operand:DI 0 "register_operand" "=r,r")
1034 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1035 (match_operator:DI 4 "comparison_operator"
1036 [(match_operand:DI 2 "register_operand" "r,r")
1037 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1040 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1041 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1042 [(set_attr "type" "binary,binary")
1043 (set_attr "length" "8,12")])
1045 ; Patterns for max and min. (There is no need for an earlyclobber in the
1046 ; last alternative since the middle alternative will match if op0 == op1.)
1048 (define_insn "sminsi3"
1049 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1050 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1051 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1054 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1055 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1056 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1057 [(set_attr "type" "multi,multi,multi")
1058 (set_attr "length" "8,8,8")])
1060 (define_insn "smindi3"
1061 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1062 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1063 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1066 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1067 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1068 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1069 [(set_attr "type" "multi,multi,multi")
1070 (set_attr "length" "8,8,8")])
1072 (define_insn "uminsi3"
1073 [(set (match_operand:SI 0 "register_operand" "=r,r")
1074 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1075 (match_operand:SI 2 "arith11_operand" "r,I")))]
1078 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1079 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1080 [(set_attr "type" "multi,multi")
1081 (set_attr "length" "8,8")])
1083 (define_insn "umindi3"
1084 [(set (match_operand:DI 0 "register_operand" "=r,r")
1085 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1086 (match_operand:DI 2 "arith11_operand" "r,I")))]
1089 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1090 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1091 [(set_attr "type" "multi,multi")
1092 (set_attr "length" "8,8")])
1094 (define_insn "smaxsi3"
1095 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1096 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1097 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1100 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1101 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1102 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1103 [(set_attr "type" "multi,multi,multi")
1104 (set_attr "length" "8,8,8")])
1106 (define_insn "smaxdi3"
1107 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1108 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1109 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1112 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1113 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1114 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1115 [(set_attr "type" "multi,multi,multi")
1116 (set_attr "length" "8,8,8")])
1118 (define_insn "umaxsi3"
1119 [(set (match_operand:SI 0 "register_operand" "=r,r")
1120 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1121 (match_operand:SI 2 "arith11_operand" "r,I")))]
1124 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1125 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1126 [(set_attr "type" "multi,multi")
1127 (set_attr "length" "8,8")])
1129 (define_insn "umaxdi3"
1130 [(set (match_operand:DI 0 "register_operand" "=r,r")
1131 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1132 (match_operand:DI 2 "arith11_operand" "r,I")))]
1135 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1136 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1137 [(set_attr "type" "multi,multi")
1138 (set_attr "length" "8,8")])
1140 (define_insn "abssi2"
1141 [(set (match_operand:SI 0 "register_operand" "=r")
1142 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1144 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1145 [(set_attr "type" "multi")
1146 (set_attr "length" "8")])
1148 (define_insn "absdi2"
1149 [(set (match_operand:DI 0 "register_operand" "=r")
1150 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1152 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1153 [(set_attr "type" "multi")
1154 (set_attr "length" "8")])
1156 ;;; Experimental conditional move patterns
1158 (define_expand "movsicc"
1159 [(set (match_operand:SI 0 "register_operand" "")
1161 (match_operand 1 "comparison_operator" "")
1162 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1163 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1167 if (GET_MODE (XEXP (operands[1], 0)) != SImode
1168 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1172 ;; We used to accept any register for op1.
1174 ;; However, it loses sometimes because the compiler will end up using
1175 ;; different registers for op0 and op1 in some critical cases. local-alloc
1176 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1178 ;; If/when global register allocation supports tying we should allow any
1179 ;; register for op1 again.
1181 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1183 (match_operator 2 "comparison_operator"
1184 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1185 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1186 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1190 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1191 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1192 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1193 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1194 [(set_attr "type" "multi,multi,multi,nullshift")
1195 (set_attr "length" "8,8,8,8")])
1198 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1200 (match_operator 5 "comparison_operator"
1201 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1202 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1203 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1204 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1207 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1208 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1209 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1210 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1211 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1212 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1213 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1214 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1215 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1216 (set_attr "length" "8,8,8,8,8,8,8,8")])
1218 (define_expand "movdicc"
1219 [(set (match_operand:DI 0 "register_operand" "")
1221 (match_operand 1 "comparison_operator" "")
1222 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1223 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1227 if (GET_MODE (XEXP (operands[1], 0)) != DImode
1228 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1232 ; We need the first constraint alternative in order to avoid
1233 ; earlyclobbers on all other alternatives.
1235 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1237 (match_operator 2 "comparison_operator"
1238 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1239 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1240 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1244 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1245 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1246 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1247 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1248 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1249 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1250 (set_attr "length" "8,8,8,8,8")])
1253 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1255 (match_operator 5 "comparison_operator"
1256 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1257 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1258 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1259 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1262 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1263 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1264 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1265 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1266 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1267 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1268 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1269 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1270 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1271 (set_attr "length" "8,8,8,8,8,8,8,8")])
1273 ;; Conditional Branches
1275 (define_expand "cbranchdi4"
1277 (if_then_else (match_operator 0 "ordered_comparison_operator"
1278 [(match_operand:DI 1 "reg_or_0_operand" "")
1279 (match_operand:DI 2 "register_operand" "")])
1280 (label_ref (match_operand 3 "" ""))
1285 (define_expand "cbranchsi4"
1287 (if_then_else (match_operator 0 "ordered_comparison_operator"
1288 [(match_operand:SI 1 "reg_or_0_operand" "")
1289 (match_operand:SI 2 "arith5_operand" "")])
1290 (label_ref (match_operand 3 "" ""))
1295 (define_expand "cbranchsf4"
1297 (if_then_else (match_operator 0 "comparison_operator"
1298 [(match_operand:SF 1 "reg_or_0_operand" "")
1299 (match_operand:SF 2 "reg_or_0_operand" "")])
1300 (label_ref (match_operand 3 "" ""))
1305 emit_bcond_fp (operands);
1310 (define_expand "cbranchdf4"
1312 (if_then_else (match_operator 0 "comparison_operator"
1313 [(match_operand:DF 1 "reg_or_0_operand" "")
1314 (match_operand:DF 2 "reg_or_0_operand" "")])
1315 (label_ref (match_operand 3 "" ""))
1320 emit_bcond_fp (operands);
1324 ;; Match the branch patterns.
1327 ;; Note a long backward conditional branch with an annulled delay slot
1328 ;; has a length of 12.
1332 (match_operator 3 "comparison_operator"
1333 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1334 (match_operand:SI 2 "arith5_operand" "rL")])
1335 (label_ref (match_operand 0 "" ""))
1340 return output_cbranch (operands, 0, insn);
1342 [(set_attr "type" "cbranch")
1343 (set (attr "length")
1344 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1345 (const_int MAX_12BIT_OFFSET))
1347 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1348 (const_int MAX_17BIT_OFFSET))
1350 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1352 (eq (symbol_ref "flag_pic") (const_int 0))
1356 ;; Match the negated branch.
1361 (match_operator 3 "comparison_operator"
1362 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1363 (match_operand:SI 2 "arith5_operand" "rL")])
1365 (label_ref (match_operand 0 "" ""))))]
1369 return output_cbranch (operands, 1, insn);
1371 [(set_attr "type" "cbranch")
1372 (set (attr "length")
1373 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1374 (const_int MAX_12BIT_OFFSET))
1376 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1377 (const_int MAX_17BIT_OFFSET))
1379 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1381 (eq (symbol_ref "flag_pic") (const_int 0))
1388 (match_operator 3 "comparison_operator"
1389 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1390 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1391 (label_ref (match_operand 0 "" ""))
1396 return output_cbranch (operands, 0, insn);
1398 [(set_attr "type" "cbranch")
1399 (set (attr "length")
1400 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1401 (const_int MAX_12BIT_OFFSET))
1403 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1404 (const_int MAX_17BIT_OFFSET))
1406 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1408 (eq (symbol_ref "flag_pic") (const_int 0))
1412 ;; Match the negated branch.
1417 (match_operator 3 "comparison_operator"
1418 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1419 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1421 (label_ref (match_operand 0 "" ""))))]
1425 return output_cbranch (operands, 1, insn);
1427 [(set_attr "type" "cbranch")
1428 (set (attr "length")
1429 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1430 (const_int MAX_12BIT_OFFSET))
1432 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1433 (const_int MAX_17BIT_OFFSET))
1435 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1437 (eq (symbol_ref "flag_pic") (const_int 0))
1443 (match_operator 3 "cmpib_comparison_operator"
1444 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1445 (match_operand:DI 2 "arith5_operand" "rL")])
1446 (label_ref (match_operand 0 "" ""))
1451 return output_cbranch (operands, 0, insn);
1453 [(set_attr "type" "cbranch")
1454 (set (attr "length")
1455 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1456 (const_int MAX_12BIT_OFFSET))
1458 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1459 (const_int MAX_17BIT_OFFSET))
1461 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1463 (eq (symbol_ref "flag_pic") (const_int 0))
1467 ;; Match the negated branch.
1472 (match_operator 3 "cmpib_comparison_operator"
1473 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1474 (match_operand:DI 2 "arith5_operand" "rL")])
1476 (label_ref (match_operand 0 "" ""))))]
1480 return output_cbranch (operands, 1, insn);
1482 [(set_attr "type" "cbranch")
1483 (set (attr "length")
1484 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1485 (const_int MAX_12BIT_OFFSET))
1487 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1488 (const_int MAX_17BIT_OFFSET))
1490 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1492 (eq (symbol_ref "flag_pic") (const_int 0))
1496 ;; Branch on Bit patterns.
1500 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1502 (match_operand:SI 1 "uint5_operand" ""))
1504 (label_ref (match_operand 2 "" ""))
1509 return output_bb (operands, 0, insn, 0);
1511 [(set_attr "type" "cbranch")
1512 (set (attr "length")
1513 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1514 (const_int MAX_12BIT_OFFSET))
1516 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1517 (const_int MAX_17BIT_OFFSET))
1519 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1521 (eq (symbol_ref "flag_pic") (const_int 0))
1528 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1530 (match_operand:DI 1 "uint32_operand" ""))
1532 (label_ref (match_operand 2 "" ""))
1537 return output_bb (operands, 0, insn, 0);
1539 [(set_attr "type" "cbranch")
1540 (set (attr "length")
1541 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1542 (const_int MAX_12BIT_OFFSET))
1544 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1545 (const_int MAX_17BIT_OFFSET))
1547 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1549 (eq (symbol_ref "flag_pic") (const_int 0))
1556 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1558 (match_operand:SI 1 "uint5_operand" ""))
1561 (label_ref (match_operand 2 "" ""))))]
1565 return output_bb (operands, 1, insn, 0);
1567 [(set_attr "type" "cbranch")
1568 (set (attr "length")
1569 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1570 (const_int MAX_12BIT_OFFSET))
1572 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1573 (const_int MAX_17BIT_OFFSET))
1575 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1577 (eq (symbol_ref "flag_pic") (const_int 0))
1584 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1586 (match_operand:DI 1 "uint32_operand" ""))
1589 (label_ref (match_operand 2 "" ""))))]
1593 return output_bb (operands, 1, insn, 0);
1595 [(set_attr "type" "cbranch")
1596 (set (attr "length")
1597 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1598 (const_int MAX_12BIT_OFFSET))
1600 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1601 (const_int MAX_17BIT_OFFSET))
1603 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1605 (eq (symbol_ref "flag_pic") (const_int 0))
1612 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1614 (match_operand:SI 1 "uint5_operand" ""))
1616 (label_ref (match_operand 2 "" ""))
1621 return output_bb (operands, 0, insn, 1);
1623 [(set_attr "type" "cbranch")
1624 (set (attr "length")
1625 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1626 (const_int MAX_12BIT_OFFSET))
1628 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1629 (const_int MAX_17BIT_OFFSET))
1631 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1633 (eq (symbol_ref "flag_pic") (const_int 0))
1640 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1642 (match_operand:DI 1 "uint32_operand" ""))
1644 (label_ref (match_operand 2 "" ""))
1649 return output_bb (operands, 0, insn, 1);
1651 [(set_attr "type" "cbranch")
1652 (set (attr "length")
1653 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1654 (const_int MAX_12BIT_OFFSET))
1656 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1657 (const_int MAX_17BIT_OFFSET))
1659 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1661 (eq (symbol_ref "flag_pic") (const_int 0))
1668 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1670 (match_operand:SI 1 "uint5_operand" ""))
1673 (label_ref (match_operand 2 "" ""))))]
1677 return output_bb (operands, 1, insn, 1);
1679 [(set_attr "type" "cbranch")
1680 (set (attr "length")
1681 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1682 (const_int MAX_12BIT_OFFSET))
1684 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1685 (const_int MAX_17BIT_OFFSET))
1687 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1689 (eq (symbol_ref "flag_pic") (const_int 0))
1696 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1698 (match_operand:DI 1 "uint32_operand" ""))
1701 (label_ref (match_operand 2 "" ""))))]
1705 return output_bb (operands, 1, insn, 1);
1707 [(set_attr "type" "cbranch")
1708 (set (attr "length")
1709 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1710 (const_int MAX_12BIT_OFFSET))
1712 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1713 (const_int MAX_17BIT_OFFSET))
1715 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1717 (eq (symbol_ref "flag_pic") (const_int 0))
1721 ;; Branch on Variable Bit patterns.
1725 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1727 (match_operand:SI 1 "register_operand" "q"))
1729 (label_ref (match_operand 2 "" ""))
1734 return output_bvb (operands, 0, insn, 0);
1736 [(set_attr "type" "cbranch")
1737 (set (attr "length")
1738 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1739 (const_int MAX_12BIT_OFFSET))
1741 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1742 (const_int MAX_17BIT_OFFSET))
1744 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1746 (eq (symbol_ref "flag_pic") (const_int 0))
1753 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1755 (match_operand:DI 1 "register_operand" "q"))
1757 (label_ref (match_operand 2 "" ""))
1762 return output_bvb (operands, 0, insn, 0);
1764 [(set_attr "type" "cbranch")
1765 (set (attr "length")
1766 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1767 (const_int MAX_12BIT_OFFSET))
1769 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1770 (const_int MAX_17BIT_OFFSET))
1772 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1774 (eq (symbol_ref "flag_pic") (const_int 0))
1781 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1783 (match_operand:SI 1 "register_operand" "q"))
1786 (label_ref (match_operand 2 "" ""))))]
1790 return output_bvb (operands, 1, insn, 0);
1792 [(set_attr "type" "cbranch")
1793 (set (attr "length")
1794 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1795 (const_int MAX_12BIT_OFFSET))
1797 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1798 (const_int MAX_17BIT_OFFSET))
1800 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1802 (eq (symbol_ref "flag_pic") (const_int 0))
1809 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1811 (match_operand:DI 1 "register_operand" "q"))
1814 (label_ref (match_operand 2 "" ""))))]
1818 return output_bvb (operands, 1, insn, 0);
1820 [(set_attr "type" "cbranch")
1821 (set (attr "length")
1822 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1823 (const_int MAX_12BIT_OFFSET))
1825 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1826 (const_int MAX_17BIT_OFFSET))
1828 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1830 (eq (symbol_ref "flag_pic") (const_int 0))
1837 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1839 (match_operand:SI 1 "register_operand" "q"))
1841 (label_ref (match_operand 2 "" ""))
1846 return output_bvb (operands, 0, insn, 1);
1848 [(set_attr "type" "cbranch")
1849 (set (attr "length")
1850 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1851 (const_int MAX_12BIT_OFFSET))
1853 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1854 (const_int MAX_17BIT_OFFSET))
1856 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1858 (eq (symbol_ref "flag_pic") (const_int 0))
1865 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1867 (match_operand:DI 1 "register_operand" "q"))
1869 (label_ref (match_operand 2 "" ""))
1874 return output_bvb (operands, 0, insn, 1);
1876 [(set_attr "type" "cbranch")
1877 (set (attr "length")
1878 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1879 (const_int MAX_12BIT_OFFSET))
1881 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1882 (const_int MAX_17BIT_OFFSET))
1884 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1886 (eq (symbol_ref "flag_pic") (const_int 0))
1893 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1895 (match_operand:SI 1 "register_operand" "q"))
1898 (label_ref (match_operand 2 "" ""))))]
1902 return output_bvb (operands, 1, insn, 1);
1904 [(set_attr "type" "cbranch")
1905 (set (attr "length")
1906 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1907 (const_int MAX_12BIT_OFFSET))
1909 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1910 (const_int MAX_17BIT_OFFSET))
1912 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1914 (eq (symbol_ref "flag_pic") (const_int 0))
1921 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1923 (match_operand:DI 1 "register_operand" "q"))
1926 (label_ref (match_operand 2 "" ""))))]
1930 return output_bvb (operands, 1, insn, 1);
1932 [(set_attr "type" "cbranch")
1933 (set (attr "length")
1934 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1935 (const_int MAX_12BIT_OFFSET))
1937 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1938 (const_int MAX_17BIT_OFFSET))
1940 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1942 (eq (symbol_ref "flag_pic") (const_int 0))
1946 ;; Floating point branches
1948 ;; ??? Nullification is handled differently from other branches.
1949 ;; If nullification is specified, the delay slot is nullified on any
1950 ;; taken branch regardless of branch direction.
1952 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
1953 (label_ref (match_operand 0 "" ""))
1955 "!TARGET_SOFT_FLOAT"
1958 int length = get_attr_length (insn);
1960 int nullify, xdelay;
1963 return \"ftest\;b%* %l0\";
1965 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
1969 xoperands[0] = GEN_INT (length - 8);
1975 xoperands[0] = GEN_INT (length - 4);
1979 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
1981 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
1982 return output_lbranch (operands[0], insn, xdelay);
1984 [(set_attr "type" "fbranch")
1985 (set (attr "length")
1986 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1987 (const_int MAX_17BIT_OFFSET))
1989 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1991 (eq (symbol_ref "flag_pic") (const_int 0))
1996 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
1998 (label_ref (match_operand 0 "" ""))))]
1999 "!TARGET_SOFT_FLOAT"
2002 int length = get_attr_length (insn);
2004 int nullify, xdelay;
2007 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2009 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2013 xoperands[0] = GEN_INT (length - 4);
2019 xoperands[0] = GEN_INT (length);
2023 output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
2025 output_asm_insn (\"ftest\;b .+%0\", xoperands);
2026 return output_lbranch (operands[0], insn, xdelay);
2028 [(set_attr "type" "fbranch")
2029 (set (attr "length")
2030 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2031 (const_int MAX_17BIT_OFFSET))
2033 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2035 (eq (symbol_ref "flag_pic") (const_int 0))
2039 ;; Move instructions
2041 (define_expand "movsi"
2042 [(set (match_operand:SI 0 "general_operand" "")
2043 (match_operand:SI 1 "general_operand" ""))]
2047 if (emit_move_sequence (operands, SImode, 0))
2051 ;; Handle SImode input reloads requiring %r1 as a scratch register.
2052 (define_expand "reload_insi_r1"
2053 [(set (match_operand:SI 0 "register_operand" "=Z")
2054 (match_operand:SI 1 "non_hard_reg_operand" ""))
2055 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
2059 if (emit_move_sequence (operands, SImode, operands[2]))
2062 /* We don't want the clobber emitted, so handle this ourselves. */
2063 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2067 ;; Handle SImode input reloads requiring a general register as a
2068 ;; scratch register.
2069 (define_expand "reload_insi"
2070 [(set (match_operand:SI 0 "register_operand" "=Z")
2071 (match_operand:SI 1 "non_hard_reg_operand" ""))
2072 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2076 if (emit_move_sequence (operands, SImode, operands[2]))
2079 /* We don't want the clobber emitted, so handle this ourselves. */
2080 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2084 ;; Handle SImode output reloads requiring a general register as a
2085 ;; scratch register.
2086 (define_expand "reload_outsi"
2087 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2088 (match_operand:SI 1 "register_operand" "Z"))
2089 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2093 if (emit_move_sequence (operands, SImode, operands[2]))
2096 /* We don't want the clobber emitted, so handle this ourselves. */
2097 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2102 [(set (match_operand:SI 0 "move_dest_operand"
2103 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
2104 (match_operand:SI 1 "move_src_operand"
2105 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
2106 "(register_operand (operands[0], SImode)
2107 || reg_or_0_operand (operands[1], SImode))
2108 && !TARGET_SOFT_FLOAT
2115 {zdepi|depwi,z} %Z1,%0
2119 {mfctl|mfctl,w} %%sar,%0
2123 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
2124 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
2125 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload")
2126 (set_attr "pa_combine_type" "addmove")
2127 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
2130 [(set (match_operand:SI 0 "move_dest_operand"
2131 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2132 (match_operand:SI 1 "move_src_operand"
2133 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2134 "(register_operand (operands[0], SImode)
2135 || reg_or_0_operand (operands[1], SImode))
2136 && !TARGET_SOFT_FLOAT
2143 {zdepi|depwi,z} %Z1,%0
2147 {mfctl|mfctl,w} %%sar,%0
2151 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2152 (set_attr "pa_combine_type" "addmove")
2153 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2156 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2157 (match_operand:SI 1 "register_operand" "f"))]
2159 && !TARGET_DISABLE_INDEXING
2160 && reload_completed"
2162 [(set_attr "type" "fpstore")
2163 (set_attr "pa_combine_type" "addmove")
2164 (set_attr "length" "4")])
2166 ; Rewrite RTL using an indexed store. This will allow the insn that
2167 ; computes the address to be deleted if the register it sets is dead.
2169 [(set (match_operand:SI 0 "register_operand" "")
2170 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2172 (match_operand:SI 2 "register_operand" "")))
2173 (set (mem:SI (match_dup 0))
2174 (match_operand:SI 3 "register_operand" ""))]
2176 && !TARGET_DISABLE_INDEXING
2177 && REG_OK_FOR_BASE_P (operands[2])
2178 && FP_REGNO_P (REGNO (operands[3]))"
2179 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2181 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2186 [(set (match_operand:SI 0 "register_operand" "")
2187 (plus:SI (match_operand:SI 2 "register_operand" "")
2188 (mult:SI (match_operand:SI 1 "register_operand" "")
2190 (set (mem:SI (match_dup 0))
2191 (match_operand:SI 3 "register_operand" ""))]
2193 && !TARGET_DISABLE_INDEXING
2194 && REG_OK_FOR_BASE_P (operands[2])
2195 && FP_REGNO_P (REGNO (operands[3]))"
2196 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2198 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2203 [(set (match_operand:DI 0 "register_operand" "")
2204 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2206 (match_operand:DI 2 "register_operand" "")))
2207 (set (mem:SI (match_dup 0))
2208 (match_operand:SI 3 "register_operand" ""))]
2210 && !TARGET_DISABLE_INDEXING
2212 && REG_OK_FOR_BASE_P (operands[2])
2213 && FP_REGNO_P (REGNO (operands[3]))"
2214 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2216 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2221 [(set (match_operand:DI 0 "register_operand" "")
2222 (plus:DI (match_operand:DI 2 "register_operand" "")
2223 (mult:DI (match_operand:DI 1 "register_operand" "")
2225 (set (mem:SI (match_dup 0))
2226 (match_operand:SI 3 "register_operand" ""))]
2228 && !TARGET_DISABLE_INDEXING
2230 && REG_OK_FOR_BASE_P (operands[2])
2231 && FP_REGNO_P (REGNO (operands[3]))"
2232 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2234 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2239 [(set (match_operand:SI 0 "register_operand" "")
2240 (plus:SI (match_operand:SI 1 "register_operand" "")
2241 (match_operand:SI 2 "register_operand" "")))
2242 (set (mem:SI (match_dup 0))
2243 (match_operand:SI 3 "register_operand" ""))]
2245 && !TARGET_DISABLE_INDEXING
2246 && TARGET_NO_SPACE_REGS
2247 && REG_OK_FOR_INDEX_P (operands[1])
2248 && REG_OK_FOR_BASE_P (operands[2])
2249 && FP_REGNO_P (REGNO (operands[3]))"
2250 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2252 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2256 [(set (match_operand:SI 0 "register_operand" "")
2257 (plus:SI (match_operand:SI 1 "register_operand" "")
2258 (match_operand:SI 2 "register_operand" "")))
2259 (set (mem:SI (match_dup 0))
2260 (match_operand:SI 3 "register_operand" ""))]
2262 && !TARGET_DISABLE_INDEXING
2263 && TARGET_NO_SPACE_REGS
2264 && REG_OK_FOR_BASE_P (operands[1])
2265 && REG_OK_FOR_INDEX_P (operands[2])
2266 && FP_REGNO_P (REGNO (operands[3]))"
2267 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2269 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2273 [(set (match_operand:DI 0 "register_operand" "")
2274 (plus:DI (match_operand:DI 1 "register_operand" "")
2275 (match_operand:DI 2 "register_operand" "")))
2276 (set (mem:SI (match_dup 0))
2277 (match_operand:SI 3 "register_operand" ""))]
2279 && !TARGET_DISABLE_INDEXING
2281 && TARGET_NO_SPACE_REGS
2282 && REG_OK_FOR_INDEX_P (operands[1])
2283 && REG_OK_FOR_BASE_P (operands[2])
2284 && FP_REGNO_P (REGNO (operands[3]))"
2285 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2287 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2291 [(set (match_operand:DI 0 "register_operand" "")
2292 (plus:DI (match_operand:DI 1 "register_operand" "")
2293 (match_operand:DI 2 "register_operand" "")))
2294 (set (mem:SI (match_dup 0))
2295 (match_operand:SI 3 "register_operand" ""))]
2297 && !TARGET_DISABLE_INDEXING
2299 && TARGET_NO_SPACE_REGS
2300 && REG_OK_FOR_BASE_P (operands[1])
2301 && REG_OK_FOR_INDEX_P (operands[2])
2302 && FP_REGNO_P (REGNO (operands[3]))"
2303 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2305 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2309 [(set (match_operand:SI 0 "move_dest_operand"
2310 "=r,r,r,r,r,r,Q,!*q,!r")
2311 (match_operand:SI 1 "move_src_operand"
2312 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2313 "(register_operand (operands[0], SImode)
2314 || reg_or_0_operand (operands[1], SImode))
2315 && TARGET_SOFT_FLOAT"
2321 {zdepi|depwi,z} %Z1,%0
2325 {mfctl|mfctl,w} %%sar,%0"
2326 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2327 (set_attr "pa_combine_type" "addmove")
2328 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2330 ;; Load or store with base-register modification.
2332 [(set (match_operand:SI 0 "register_operand" "=r")
2333 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2334 (match_operand:DI 2 "int5_operand" "L"))))
2336 (plus:DI (match_dup 1) (match_dup 2)))]
2339 [(set_attr "type" "load")
2340 (set_attr "length" "4")])
2342 ; And a zero extended variant.
2344 [(set (match_operand:DI 0 "register_operand" "=r")
2345 (zero_extend:DI (mem:SI
2347 (match_operand:DI 1 "register_operand" "+r")
2348 (match_operand:DI 2 "int5_operand" "L")))))
2350 (plus:DI (match_dup 1) (match_dup 2)))]
2353 [(set_attr "type" "load")
2354 (set_attr "length" "4")])
2356 (define_expand "pre_load"
2357 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2358 (mem (plus (match_operand 1 "register_operand" "")
2359 (match_operand 2 "pre_cint_operand" ""))))
2361 (plus (match_dup 1) (match_dup 2)))])]
2367 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2370 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2374 (define_insn "pre_ldw"
2375 [(set (match_operand:SI 0 "register_operand" "=r")
2376 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2377 (match_operand:SI 2 "pre_cint_operand" ""))))
2379 (plus:SI (match_dup 1) (match_dup 2)))]
2383 if (INTVAL (operands[2]) < 0)
2384 return \"{ldwm|ldw,mb} %2(%1),%0\";
2385 return \"{ldws|ldw},mb %2(%1),%0\";
2387 [(set_attr "type" "load")
2388 (set_attr "length" "4")])
2390 (define_insn "pre_ldd"
2391 [(set (match_operand:DI 0 "register_operand" "=r")
2392 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2393 (match_operand:DI 2 "pre_cint_operand" ""))))
2395 (plus:DI (match_dup 1) (match_dup 2)))]
2398 [(set_attr "type" "load")
2399 (set_attr "length" "4")])
2402 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2403 (match_operand:SI 1 "pre_cint_operand" "")))
2404 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2406 (plus:SI (match_dup 0) (match_dup 1)))]
2410 if (INTVAL (operands[1]) < 0)
2411 return \"{stwm|stw,mb} %r2,%1(%0)\";
2412 return \"{stws|stw},mb %r2,%1(%0)\";
2414 [(set_attr "type" "store")
2415 (set_attr "length" "4")])
2418 [(set (match_operand:SI 0 "register_operand" "=r")
2419 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2421 (plus:SI (match_dup 1)
2422 (match_operand:SI 2 "post_cint_operand" "")))]
2426 if (INTVAL (operands[2]) > 0)
2427 return \"{ldwm|ldw,ma} %2(%1),%0\";
2428 return \"{ldws|ldw},ma %2(%1),%0\";
2430 [(set_attr "type" "load")
2431 (set_attr "length" "4")])
2433 (define_expand "post_store"
2434 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2435 (match_operand 1 "reg_or_0_operand" ""))
2438 (match_operand 2 "post_cint_operand" "")))])]
2444 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2447 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2451 (define_insn "post_stw"
2452 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2453 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2455 (plus:SI (match_dup 0)
2456 (match_operand:SI 2 "post_cint_operand" "")))]
2460 if (INTVAL (operands[2]) > 0)
2461 return \"{stwm|stw,ma} %r1,%2(%0)\";
2462 return \"{stws|stw},ma %r1,%2(%0)\";
2464 [(set_attr "type" "store")
2465 (set_attr "length" "4")])
2467 (define_insn "post_std"
2468 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2469 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2471 (plus:DI (match_dup 0)
2472 (match_operand:DI 2 "post_cint_operand" "")))]
2475 [(set_attr "type" "store")
2476 (set_attr "length" "4")])
2478 ;; For loading the address of a label while generating PIC code.
2479 ;; Note since this pattern can be created at reload time (via movsi), all
2480 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2482 [(set (match_operand 0 "pmode_register_operand" "=a")
2483 (match_operand 1 "pic_label_operand" ""))]
2489 xoperands[0] = operands[0];
2490 xoperands[1] = operands[1];
2491 xoperands[2] = gen_label_rtx ();
2493 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2494 CODE_LABEL_NUMBER (xoperands[2]));
2495 output_asm_insn (\"mfia %0\", xoperands);
2497 /* If we're trying to load the address of a label that happens to be
2498 close, then we can use a shorter sequence. */
2499 if (GET_CODE (operands[1]) == LABEL_REF
2500 && !LABEL_REF_NONLOCAL_P (operands[1])
2501 && INSN_ADDRESSES_SET_P ()
2502 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2503 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2504 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2507 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2508 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2512 [(set_attr "type" "multi")
2513 (set_attr "length" "12")]) ; 8 or 12
2516 [(set (match_operand 0 "pmode_register_operand" "=a")
2517 (match_operand 1 "pic_label_operand" ""))]
2523 xoperands[0] = operands[0];
2524 xoperands[1] = operands[1];
2525 xoperands[2] = gen_label_rtx ();
2527 output_asm_insn (\"bl .+8,%0\", xoperands);
2528 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2529 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2530 CODE_LABEL_NUMBER (xoperands[2]));
2532 /* If we're trying to load the address of a label that happens to be
2533 close, then we can use a shorter sequence. */
2534 if (GET_CODE (operands[1]) == LABEL_REF
2535 && !LABEL_REF_NONLOCAL_P (operands[1])
2536 && INSN_ADDRESSES_SET_P ()
2537 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2538 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2539 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2542 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2543 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2547 [(set_attr "type" "multi")
2548 (set_attr "length" "16")]) ; 12 or 16
2551 [(set (match_operand:SI 0 "register_operand" "=a")
2552 (plus:SI (match_operand:SI 1 "register_operand" "r")
2553 (high:SI (match_operand 2 "" ""))))]
2554 "symbolic_operand (operands[2], Pmode)
2555 && ! function_label_operand (operands[2], Pmode)
2558 [(set_attr "type" "binary")
2559 (set_attr "length" "4")])
2562 [(set (match_operand:DI 0 "register_operand" "=a")
2563 (plus:DI (match_operand:DI 1 "register_operand" "r")
2564 (high:DI (match_operand 2 "" ""))))]
2565 "symbolic_operand (operands[2], Pmode)
2566 && ! function_label_operand (operands[2], Pmode)
2570 [(set_attr "type" "binary")
2571 (set_attr "length" "4")])
2573 ;; Always use addil rather than ldil;add sequences. This allows the
2574 ;; HP linker to eliminate the dp relocation if the symbolic operand
2575 ;; lives in the TEXT space.
2577 [(set (match_operand:SI 0 "register_operand" "=a")
2578 (high:SI (match_operand 1 "" "")))]
2579 "symbolic_operand (operands[1], Pmode)
2580 && ! function_label_operand (operands[1], Pmode)
2581 && ! read_only_operand (operands[1], Pmode)
2585 if (TARGET_LONG_LOAD_STORE)
2586 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2588 return \"addil LR'%H1,%%r27\";
2590 [(set_attr "type" "binary")
2591 (set (attr "length")
2592 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2597 ;; This is for use in the prologue/epilogue code. We need it
2598 ;; to add large constants to a stack pointer or frame pointer.
2599 ;; Because of the additional %r1 pressure, we probably do not
2600 ;; want to use this in general code, so make it available
2601 ;; only after reload.
2603 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2604 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2605 (high:SI (match_operand 2 "const_int_operand" ""))))]
2609 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2610 [(set_attr "type" "binary,binary")
2611 (set_attr "length" "4,8")])
2614 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2615 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2616 (high:DI (match_operand 2 "const_int_operand" ""))))]
2617 "reload_completed && TARGET_64BIT"
2620 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2621 [(set_attr "type" "binary,binary")
2622 (set_attr "length" "4,8")])
2625 [(set (match_operand:SI 0 "register_operand" "=r")
2626 (high:SI (match_operand 1 "" "")))]
2627 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2628 && !is_function_label_plus_const (operands[1])"
2631 if (symbolic_operand (operands[1], Pmode))
2632 return \"ldil LR'%H1,%0\";
2634 return \"ldil L'%G1,%0\";
2636 [(set_attr "type" "move")
2637 (set_attr "length" "4")])
2640 [(set (match_operand:DI 0 "register_operand" "=r")
2641 (high:DI (match_operand 1 "const_int_operand" "")))]
2644 [(set_attr "type" "move")
2645 (set_attr "length" "4")])
2648 [(set (match_operand:DI 0 "register_operand" "=r")
2649 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2650 (match_operand:DI 2 "const_int_operand" "i")))]
2653 [(set_attr "type" "move")
2654 (set_attr "length" "4")])
2657 [(set (match_operand:SI 0 "register_operand" "=r")
2658 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2659 (match_operand:SI 2 "immediate_operand" "i")))]
2660 "!is_function_label_plus_const (operands[2])"
2663 gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
2665 if (symbolic_operand (operands[2], Pmode))
2666 return \"ldo RR'%G2(%1),%0\";
2668 return \"ldo R'%G2(%1),%0\";
2670 [(set_attr "type" "move")
2671 (set_attr "length" "4")])
2673 ;; Now that a symbolic_address plus a constant is broken up early
2674 ;; in the compilation phase (for better CSE) we need a special
2675 ;; combiner pattern to load the symbolic address plus the constant
2676 ;; in only 2 instructions. (For cases where the symbolic address
2677 ;; was not a common subexpression.)
2679 [(set (match_operand:SI 0 "register_operand" "")
2680 (match_operand:SI 1 "symbolic_operand" ""))
2681 (clobber (match_operand:SI 2 "register_operand" ""))]
2682 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2683 [(set (match_dup 2) (high:SI (match_dup 1)))
2684 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2687 ;; hppa_legitimize_address goes to a great deal of trouble to
2688 ;; create addresses which use indexing. In some cases, this
2689 ;; is a lose because there isn't any store instructions which
2690 ;; allow indexed addresses (with integer register source).
2692 ;; These define_splits try to turn a 3 insn store into
2693 ;; a 2 insn store with some creative RTL rewriting.
2695 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2696 (match_operand:SI 1 "shadd_operand" ""))
2697 (plus:SI (match_operand:SI 2 "register_operand" "")
2698 (match_operand:SI 3 "const_int_operand" ""))))
2699 (match_operand:SI 4 "register_operand" ""))
2700 (clobber (match_operand:SI 5 "register_operand" ""))]
2702 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2704 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2708 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2709 (match_operand:SI 1 "shadd_operand" ""))
2710 (plus:SI (match_operand:SI 2 "register_operand" "")
2711 (match_operand:SI 3 "const_int_operand" ""))))
2712 (match_operand:HI 4 "register_operand" ""))
2713 (clobber (match_operand:SI 5 "register_operand" ""))]
2715 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2717 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2721 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2722 (match_operand:SI 1 "shadd_operand" ""))
2723 (plus:SI (match_operand:SI 2 "register_operand" "")
2724 (match_operand:SI 3 "const_int_operand" ""))))
2725 (match_operand:QI 4 "register_operand" ""))
2726 (clobber (match_operand:SI 5 "register_operand" ""))]
2728 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2730 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2733 (define_expand "movhi"
2734 [(set (match_operand:HI 0 "general_operand" "")
2735 (match_operand:HI 1 "general_operand" ""))]
2739 if (emit_move_sequence (operands, HImode, 0))
2744 [(set (match_operand:HI 0 "move_dest_operand"
2745 "=r,r,r,r,r,Q,!*q,!r")
2746 (match_operand:HI 1 "move_src_operand"
2747 "r,J,N,K,RQ,rM,!rM,!*q"))]
2748 "(register_operand (operands[0], HImode)
2749 || reg_or_0_operand (operands[1], HImode))"
2754 {zdepi|depwi,z} %Z1,%0
2758 {mfctl|mfctl,w} %sar,%0"
2759 [(set_attr "type" "move,move,move,shift,load,store,move,move")
2760 (set_attr "pa_combine_type" "addmove")
2761 (set_attr "length" "4,4,4,4,4,4,4,4")])
2764 [(set (match_operand:HI 0 "register_operand" "=r")
2765 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2766 (match_operand:SI 2 "int5_operand" "L"))))
2768 (plus:SI (match_dup 1) (match_dup 2)))]
2770 "{ldhs|ldh},mb %2(%1),%0"
2771 [(set_attr "type" "load")
2772 (set_attr "length" "4")])
2775 [(set (match_operand:HI 0 "register_operand" "=r")
2776 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2777 (match_operand:DI 2 "int5_operand" "L"))))
2779 (plus:DI (match_dup 1) (match_dup 2)))]
2782 [(set_attr "type" "load")
2783 (set_attr "length" "4")])
2785 ; And a zero extended variant.
2787 [(set (match_operand:DI 0 "register_operand" "=r")
2788 (zero_extend:DI (mem:HI
2790 (match_operand:DI 1 "register_operand" "+r")
2791 (match_operand:DI 2 "int5_operand" "L")))))
2793 (plus:DI (match_dup 1) (match_dup 2)))]
2796 [(set_attr "type" "load")
2797 (set_attr "length" "4")])
2800 [(set (match_operand:SI 0 "register_operand" "=r")
2801 (zero_extend:SI (mem:HI
2803 (match_operand:SI 1 "register_operand" "+r")
2804 (match_operand:SI 2 "int5_operand" "L")))))
2806 (plus:SI (match_dup 1) (match_dup 2)))]
2808 "{ldhs|ldh},mb %2(%1),%0"
2809 [(set_attr "type" "load")
2810 (set_attr "length" "4")])
2813 [(set (match_operand:SI 0 "register_operand" "=r")
2814 (zero_extend:SI (mem:HI
2816 (match_operand:DI 1 "register_operand" "+r")
2817 (match_operand:DI 2 "int5_operand" "L")))))
2819 (plus:DI (match_dup 1) (match_dup 2)))]
2822 [(set_attr "type" "load")
2823 (set_attr "length" "4")])
2826 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2827 (match_operand:SI 1 "int5_operand" "L")))
2828 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2830 (plus:SI (match_dup 0) (match_dup 1)))]
2832 "{sths|sth},mb %r2,%1(%0)"
2833 [(set_attr "type" "store")
2834 (set_attr "length" "4")])
2837 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2838 (match_operand:DI 1 "int5_operand" "L")))
2839 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2841 (plus:DI (match_dup 0) (match_dup 1)))]
2844 [(set_attr "type" "store")
2845 (set_attr "length" "4")])
2848 [(set (match_operand:HI 0 "register_operand" "=r")
2849 (plus:HI (match_operand:HI 1 "register_operand" "r")
2850 (match_operand 2 "const_int_operand" "J")))]
2853 [(set_attr "type" "binary")
2854 (set_attr "pa_combine_type" "addmove")
2855 (set_attr "length" "4")])
2857 (define_expand "movqi"
2858 [(set (match_operand:QI 0 "general_operand" "")
2859 (match_operand:QI 1 "general_operand" ""))]
2863 if (emit_move_sequence (operands, QImode, 0))
2868 [(set (match_operand:QI 0 "move_dest_operand"
2869 "=r,r,r,r,r,Q,!*q,!r")
2870 (match_operand:QI 1 "move_src_operand"
2871 "r,J,N,K,RQ,rM,!rM,!*q"))]
2872 "(register_operand (operands[0], QImode)
2873 || reg_or_0_operand (operands[1], QImode))"
2878 {zdepi|depwi,z} %Z1,%0
2882 {mfctl|mfctl,w} %%sar,%0"
2883 [(set_attr "type" "move,move,move,shift,load,store,move,move")
2884 (set_attr "pa_combine_type" "addmove")
2885 (set_attr "length" "4,4,4,4,4,4,4,4")])
2888 [(set (match_operand:QI 0 "register_operand" "=r")
2889 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2890 (match_operand:SI 2 "int5_operand" "L"))))
2891 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2893 "{ldbs|ldb},mb %2(%1),%0"
2894 [(set_attr "type" "load")
2895 (set_attr "length" "4")])
2898 [(set (match_operand:QI 0 "register_operand" "=r")
2899 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2900 (match_operand:DI 2 "int5_operand" "L"))))
2901 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
2904 [(set_attr "type" "load")
2905 (set_attr "length" "4")])
2907 ; Now the same thing with zero extensions.
2909 [(set (match_operand:DI 0 "register_operand" "=r")
2910 (zero_extend:DI (mem:QI (plus:DI
2911 (match_operand:DI 1 "register_operand" "+r")
2912 (match_operand:DI 2 "int5_operand" "L")))))
2913 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
2916 [(set_attr "type" "load")
2917 (set_attr "length" "4")])
2920 [(set (match_operand:SI 0 "register_operand" "=r")
2921 (zero_extend:SI (mem:QI (plus:SI
2922 (match_operand:SI 1 "register_operand" "+r")
2923 (match_operand:SI 2 "int5_operand" "L")))))
2924 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2926 "{ldbs|ldb},mb %2(%1),%0"
2927 [(set_attr "type" "load")
2928 (set_attr "length" "4")])
2931 [(set (match_operand:SI 0 "register_operand" "=r")
2932 (zero_extend:SI (mem:QI (plus:DI
2933 (match_operand:DI 1 "register_operand" "+r")
2934 (match_operand:DI 2 "int5_operand" "L")))))
2935 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
2938 [(set_attr "type" "load")
2939 (set_attr "length" "4")])
2942 [(set (match_operand:HI 0 "register_operand" "=r")
2943 (zero_extend:HI (mem:QI (plus:SI
2944 (match_operand:SI 1 "register_operand" "+r")
2945 (match_operand:SI 2 "int5_operand" "L")))))
2946 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2948 "{ldbs|ldb},mb %2(%1),%0"
2949 [(set_attr "type" "load")
2950 (set_attr "length" "4")])
2953 [(set (match_operand:HI 0 "register_operand" "=r")
2954 (zero_extend:HI (mem:QI (plus:DI
2955 (match_operand:DI 1 "register_operand" "+r")
2956 (match_operand:DI 2 "int5_operand" "L")))))
2957 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
2960 [(set_attr "type" "load")
2961 (set_attr "length" "4")])
2964 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2965 (match_operand:SI 1 "int5_operand" "L")))
2966 (match_operand:QI 2 "reg_or_0_operand" "rM"))
2968 (plus:SI (match_dup 0) (match_dup 1)))]
2970 "{stbs|stb},mb %r2,%1(%0)"
2971 [(set_attr "type" "store")
2972 (set_attr "length" "4")])
2975 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2976 (match_operand:DI 1 "int5_operand" "L")))
2977 (match_operand:QI 2 "reg_or_0_operand" "rM"))
2979 (plus:DI (match_dup 0) (match_dup 1)))]
2982 [(set_attr "type" "store")
2983 (set_attr "length" "4")])
2985 ;; The definition of this insn does not really explain what it does,
2986 ;; but it should suffice that anything generated as this insn will be
2987 ;; recognized as a movmemsi operation, and that it will not successfully
2988 ;; combine with anything.
2989 (define_expand "movmemsi"
2990 [(parallel [(set (match_operand:BLK 0 "" "")
2991 (match_operand:BLK 1 "" ""))
2992 (clobber (match_dup 4))
2993 (clobber (match_dup 5))
2994 (clobber (match_dup 6))
2995 (clobber (match_dup 7))
2996 (clobber (match_dup 8))
2997 (use (match_operand:SI 2 "arith_operand" ""))
2998 (use (match_operand:SI 3 "const_int_operand" ""))])]
2999 "!TARGET_64BIT && optimize > 0"
3004 /* HP provides very fast block move library routine for the PA;
3005 this routine includes:
3007 4x4 byte at a time block moves,
3008 1x4 byte at a time with alignment checked at runtime with
3009 attempts to align the source and destination as needed
3012 With that in mind, here's the heuristics to try and guess when
3013 the inlined block move will be better than the library block
3016 If the size isn't constant, then always use the library routines.
3018 If the size is large in respect to the known alignment, then use
3019 the library routines.
3021 If the size is small in respect to the known alignment, then open
3022 code the copy (since that will lead to better scheduling).
3024 Else use the block move pattern. */
3026 /* Undetermined size, use the library routine. */
3027 if (GET_CODE (operands[2]) != CONST_INT)
3030 size = INTVAL (operands[2]);
3031 align = INTVAL (operands[3]);
3032 align = align > 4 ? 4 : align;
3034 /* If size/alignment is large, then use the library routines. */
3035 if (size / align > 16)
3038 /* This does happen, but not often enough to worry much about. */
3039 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3042 /* Fall through means we're going to use our block move pattern. */
3044 = replace_equiv_address (operands[0],
3045 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3047 = replace_equiv_address (operands[1],
3048 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3049 operands[4] = gen_reg_rtx (SImode);
3050 operands[5] = gen_reg_rtx (SImode);
3051 operands[6] = gen_reg_rtx (SImode);
3052 operands[7] = gen_reg_rtx (SImode);
3053 operands[8] = gen_reg_rtx (SImode);
3056 ;; The operand constraints are written like this to support both compile-time
3057 ;; and run-time determined byte counts. The expander and output_block_move
3058 ;; only support compile-time determined counts at this time.
3060 ;; If the count is run-time determined, the register with the byte count
3061 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3063 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3064 ;; broke this semantic for pseudo registers. We can't use match_scratch
3065 ;; as this requires two registers in the class R1_REGS when the MEMs for
3066 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3067 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3068 ;; respectively. We then split or peephole optimize after reload.
3069 (define_insn "movmemsi_prereload"
3070 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3071 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3072 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3073 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3074 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3075 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3076 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3077 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3078 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3081 [(set_attr "type" "multi,multi")])
3084 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3085 (match_operand:BLK 1 "memory_operand" ""))
3086 (clobber (match_operand:SI 2 "register_operand" ""))
3087 (clobber (match_operand:SI 3 "register_operand" ""))
3088 (clobber (match_operand:SI 6 "register_operand" ""))
3089 (clobber (match_operand:SI 7 "register_operand" ""))
3090 (clobber (match_operand:SI 8 "register_operand" ""))
3091 (use (match_operand:SI 4 "arith_operand" ""))
3092 (use (match_operand:SI 5 "const_int_operand" ""))])]
3093 "!TARGET_64BIT && reload_completed && !flag_peephole2
3094 && GET_CODE (operands[0]) == MEM
3095 && register_operand (XEXP (operands[0], 0), SImode)
3096 && GET_CODE (operands[1]) == MEM
3097 && register_operand (XEXP (operands[1], 0), SImode)"
3098 [(set (match_dup 7) (match_dup 9))
3099 (set (match_dup 8) (match_dup 10))
3100 (parallel [(set (match_dup 0) (match_dup 1))
3101 (clobber (match_dup 2))
3102 (clobber (match_dup 3))
3103 (clobber (match_dup 6))
3104 (clobber (match_dup 7))
3105 (clobber (match_dup 8))
3111 operands[9] = XEXP (operands[0], 0);
3112 operands[10] = XEXP (operands[1], 0);
3113 operands[0] = replace_equiv_address (operands[0], operands[7]);
3114 operands[1] = replace_equiv_address (operands[1], operands[8]);
3118 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3119 (match_operand:BLK 1 "memory_operand" ""))
3120 (clobber (match_operand:SI 2 "register_operand" ""))
3121 (clobber (match_operand:SI 3 "register_operand" ""))
3122 (clobber (match_operand:SI 6 "register_operand" ""))
3123 (clobber (match_operand:SI 7 "register_operand" ""))
3124 (clobber (match_operand:SI 8 "register_operand" ""))
3125 (use (match_operand:SI 4 "arith_operand" ""))
3126 (use (match_operand:SI 5 "const_int_operand" ""))])]
3128 && GET_CODE (operands[0]) == MEM
3129 && register_operand (XEXP (operands[0], 0), SImode)
3130 && GET_CODE (operands[1]) == MEM
3131 && register_operand (XEXP (operands[1], 0), SImode)"
3132 [(parallel [(set (match_dup 0) (match_dup 1))
3133 (clobber (match_dup 2))
3134 (clobber (match_dup 3))
3135 (clobber (match_dup 6))
3136 (clobber (match_dup 7))
3137 (clobber (match_dup 8))
3143 rtx addr = XEXP (operands[0], 0);
3144 if (dead_or_set_p (curr_insn, addr))
3148 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3149 operands[0] = replace_equiv_address (operands[0], operands[7]);
3152 addr = XEXP (operands[1], 0);
3153 if (dead_or_set_p (curr_insn, addr))
3157 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3158 operands[1] = replace_equiv_address (operands[1], operands[8]);
3162 (define_insn "movmemsi_postreload"
3163 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3164 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3165 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3166 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3167 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3168 (clobber (match_dup 0))
3169 (clobber (match_dup 1))
3170 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3171 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3173 "!TARGET_64BIT && reload_completed"
3174 "* return output_block_move (operands, !which_alternative);"
3175 [(set_attr "type" "multi,multi")])
3177 (define_expand "movmemdi"
3178 [(parallel [(set (match_operand:BLK 0 "" "")
3179 (match_operand:BLK 1 "" ""))
3180 (clobber (match_dup 4))
3181 (clobber (match_dup 5))
3182 (clobber (match_dup 6))
3183 (clobber (match_dup 7))
3184 (clobber (match_dup 8))
3185 (use (match_operand:DI 2 "arith_operand" ""))
3186 (use (match_operand:DI 3 "const_int_operand" ""))])]
3187 "TARGET_64BIT && optimize > 0"
3192 /* HP provides very fast block move library routine for the PA;
3193 this routine includes:
3195 4x4 byte at a time block moves,
3196 1x4 byte at a time with alignment checked at runtime with
3197 attempts to align the source and destination as needed
3200 With that in mind, here's the heuristics to try and guess when
3201 the inlined block move will be better than the library block
3204 If the size isn't constant, then always use the library routines.
3206 If the size is large in respect to the known alignment, then use
3207 the library routines.
3209 If the size is small in respect to the known alignment, then open
3210 code the copy (since that will lead to better scheduling).
3212 Else use the block move pattern. */
3214 /* Undetermined size, use the library routine. */
3215 if (GET_CODE (operands[2]) != CONST_INT)
3218 size = INTVAL (operands[2]);
3219 align = INTVAL (operands[3]);
3220 align = align > 8 ? 8 : align;
3222 /* If size/alignment is large, then use the library routines. */
3223 if (size / align > 16)
3226 /* This does happen, but not often enough to worry much about. */
3227 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3230 /* Fall through means we're going to use our block move pattern. */
3232 = replace_equiv_address (operands[0],
3233 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3235 = replace_equiv_address (operands[1],
3236 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3237 operands[4] = gen_reg_rtx (DImode);
3238 operands[5] = gen_reg_rtx (DImode);
3239 operands[6] = gen_reg_rtx (DImode);
3240 operands[7] = gen_reg_rtx (DImode);
3241 operands[8] = gen_reg_rtx (DImode);
3244 ;; The operand constraints are written like this to support both compile-time
3245 ;; and run-time determined byte counts. The expander and output_block_move
3246 ;; only support compile-time determined counts at this time.
3248 ;; If the count is run-time determined, the register with the byte count
3249 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3251 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3252 ;; broke this semantic for pseudo registers. We can't use match_scratch
3253 ;; as this requires two registers in the class R1_REGS when the MEMs for
3254 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3255 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3256 ;; respectively. We then split or peephole optimize after reload.
3257 (define_insn "movmemdi_prereload"
3258 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3259 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3260 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3261 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3262 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3263 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3264 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3265 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3266 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3269 [(set_attr "type" "multi,multi")])
3272 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3273 (match_operand:BLK 1 "memory_operand" ""))
3274 (clobber (match_operand:DI 2 "register_operand" ""))
3275 (clobber (match_operand:DI 3 "register_operand" ""))
3276 (clobber (match_operand:DI 6 "register_operand" ""))
3277 (clobber (match_operand:DI 7 "register_operand" ""))
3278 (clobber (match_operand:DI 8 "register_operand" ""))
3279 (use (match_operand:DI 4 "arith_operand" ""))
3280 (use (match_operand:DI 5 "const_int_operand" ""))])]
3281 "TARGET_64BIT && reload_completed && !flag_peephole2
3282 && GET_CODE (operands[0]) == MEM
3283 && register_operand (XEXP (operands[0], 0), DImode)
3284 && GET_CODE (operands[1]) == MEM
3285 && register_operand (XEXP (operands[1], 0), DImode)"
3286 [(set (match_dup 7) (match_dup 9))
3287 (set (match_dup 8) (match_dup 10))
3288 (parallel [(set (match_dup 0) (match_dup 1))
3289 (clobber (match_dup 2))
3290 (clobber (match_dup 3))
3291 (clobber (match_dup 6))
3292 (clobber (match_dup 7))
3293 (clobber (match_dup 8))
3299 operands[9] = XEXP (operands[0], 0);
3300 operands[10] = XEXP (operands[1], 0);
3301 operands[0] = replace_equiv_address (operands[0], operands[7]);
3302 operands[1] = replace_equiv_address (operands[1], operands[8]);
3306 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3307 (match_operand:BLK 1 "memory_operand" ""))
3308 (clobber (match_operand:DI 2 "register_operand" ""))
3309 (clobber (match_operand:DI 3 "register_operand" ""))
3310 (clobber (match_operand:DI 6 "register_operand" ""))
3311 (clobber (match_operand:DI 7 "register_operand" ""))
3312 (clobber (match_operand:DI 8 "register_operand" ""))
3313 (use (match_operand:DI 4 "arith_operand" ""))
3314 (use (match_operand:DI 5 "const_int_operand" ""))])]
3316 && GET_CODE (operands[0]) == MEM
3317 && register_operand (XEXP (operands[0], 0), DImode)
3318 && GET_CODE (operands[1]) == MEM
3319 && register_operand (XEXP (operands[1], 0), DImode)"
3320 [(parallel [(set (match_dup 0) (match_dup 1))
3321 (clobber (match_dup 2))
3322 (clobber (match_dup 3))
3323 (clobber (match_dup 6))
3324 (clobber (match_dup 7))
3325 (clobber (match_dup 8))
3331 rtx addr = XEXP (operands[0], 0);
3332 if (dead_or_set_p (curr_insn, addr))
3336 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3337 operands[0] = replace_equiv_address (operands[0], operands[7]);
3340 addr = XEXP (operands[1], 0);
3341 if (dead_or_set_p (curr_insn, addr))
3345 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3346 operands[1] = replace_equiv_address (operands[1], operands[8]);
3350 (define_insn "movmemdi_postreload"
3351 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3352 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3353 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3354 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3355 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3356 (clobber (match_dup 0))
3357 (clobber (match_dup 1))
3358 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3359 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3361 "TARGET_64BIT && reload_completed"
3362 "* return output_block_move (operands, !which_alternative);"
3363 [(set_attr "type" "multi,multi")])
3365 (define_expand "setmemsi"
3366 [(parallel [(set (match_operand:BLK 0 "" "")
3367 (match_operand 2 "const_int_operand" ""))
3368 (clobber (match_dup 4))
3369 (clobber (match_dup 5))
3370 (use (match_operand:SI 1 "arith_operand" ""))
3371 (use (match_operand:SI 3 "const_int_operand" ""))])]
3372 "!TARGET_64BIT && optimize > 0"
3377 /* If value to set is not zero, use the library routine. */
3378 if (operands[2] != const0_rtx)
3381 /* Undetermined size, use the library routine. */
3382 if (GET_CODE (operands[1]) != CONST_INT)
3385 size = INTVAL (operands[1]);
3386 align = INTVAL (operands[3]);
3387 align = align > 4 ? 4 : align;
3389 /* If size/alignment is large, then use the library routines. */
3390 if (size / align > 16)
3393 /* This does happen, but not often enough to worry much about. */
3394 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3397 /* Fall through means we're going to use our block clear pattern. */
3399 = replace_equiv_address (operands[0],
3400 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3401 operands[4] = gen_reg_rtx (SImode);
3402 operands[5] = gen_reg_rtx (SImode);
3405 (define_insn "clrmemsi_prereload"
3406 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3408 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3409 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3410 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3411 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3414 [(set_attr "type" "multi,multi")])
3417 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3419 (clobber (match_operand:SI 1 "register_operand" ""))
3420 (clobber (match_operand:SI 4 "register_operand" ""))
3421 (use (match_operand:SI 2 "arith_operand" ""))
3422 (use (match_operand:SI 3 "const_int_operand" ""))])]
3423 "!TARGET_64BIT && reload_completed && !flag_peephole2
3424 && GET_CODE (operands[0]) == MEM
3425 && register_operand (XEXP (operands[0], 0), SImode)"
3426 [(set (match_dup 4) (match_dup 5))
3427 (parallel [(set (match_dup 0) (const_int 0))
3428 (clobber (match_dup 1))
3429 (clobber (match_dup 4))
3435 operands[5] = XEXP (operands[0], 0);
3436 operands[0] = replace_equiv_address (operands[0], operands[4]);
3440 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3442 (clobber (match_operand:SI 1 "register_operand" ""))
3443 (clobber (match_operand:SI 4 "register_operand" ""))
3444 (use (match_operand:SI 2 "arith_operand" ""))
3445 (use (match_operand:SI 3 "const_int_operand" ""))])]
3447 && GET_CODE (operands[0]) == MEM
3448 && register_operand (XEXP (operands[0], 0), SImode)"
3449 [(parallel [(set (match_dup 0) (const_int 0))
3450 (clobber (match_dup 1))
3451 (clobber (match_dup 4))
3457 rtx addr = XEXP (operands[0], 0);
3458 if (dead_or_set_p (curr_insn, addr))
3462 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3463 operands[0] = replace_equiv_address (operands[0], operands[4]);
3467 (define_insn "clrmemsi_postreload"
3468 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3470 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3471 (clobber (match_dup 0))
3472 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3473 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3475 "!TARGET_64BIT && reload_completed"
3476 "* return output_block_clear (operands, !which_alternative);"
3477 [(set_attr "type" "multi,multi")])
3479 (define_expand "setmemdi"
3480 [(parallel [(set (match_operand:BLK 0 "" "")
3481 (match_operand 2 "const_int_operand" ""))
3482 (clobber (match_dup 4))
3483 (clobber (match_dup 5))
3484 (use (match_operand:DI 1 "arith_operand" ""))
3485 (use (match_operand:DI 3 "const_int_operand" ""))])]
3486 "TARGET_64BIT && optimize > 0"
3491 /* If value to set is not zero, use the library routine. */
3492 if (operands[2] != const0_rtx)
3495 /* Undetermined size, use the library routine. */
3496 if (GET_CODE (operands[1]) != CONST_INT)
3499 size = INTVAL (operands[1]);
3500 align = INTVAL (operands[3]);
3501 align = align > 8 ? 8 : align;
3503 /* If size/alignment is large, then use the library routines. */
3504 if (size / align > 16)
3507 /* This does happen, but not often enough to worry much about. */
3508 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3511 /* Fall through means we're going to use our block clear pattern. */
3513 = replace_equiv_address (operands[0],
3514 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3515 operands[4] = gen_reg_rtx (DImode);
3516 operands[5] = gen_reg_rtx (DImode);
3519 (define_insn "clrmemdi_prereload"
3520 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3522 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3523 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3524 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3525 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3528 [(set_attr "type" "multi,multi")])
3531 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3533 (clobber (match_operand:DI 1 "register_operand" ""))
3534 (clobber (match_operand:DI 4 "register_operand" ""))
3535 (use (match_operand:DI 2 "arith_operand" ""))
3536 (use (match_operand:DI 3 "const_int_operand" ""))])]
3537 "TARGET_64BIT && reload_completed && !flag_peephole2
3538 && GET_CODE (operands[0]) == MEM
3539 && register_operand (XEXP (operands[0], 0), DImode)"
3540 [(set (match_dup 4) (match_dup 5))
3541 (parallel [(set (match_dup 0) (const_int 0))
3542 (clobber (match_dup 1))
3543 (clobber (match_dup 4))
3549 operands[5] = XEXP (operands[0], 0);
3550 operands[0] = replace_equiv_address (operands[0], operands[4]);
3554 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3556 (clobber (match_operand:DI 1 "register_operand" ""))
3557 (clobber (match_operand:DI 4 "register_operand" ""))
3558 (use (match_operand:DI 2 "arith_operand" ""))
3559 (use (match_operand:DI 3 "const_int_operand" ""))])]
3561 && GET_CODE (operands[0]) == MEM
3562 && register_operand (XEXP (operands[0], 0), DImode)"
3563 [(parallel [(set (match_dup 0) (const_int 0))
3564 (clobber (match_dup 1))
3565 (clobber (match_dup 4))
3571 rtx addr = XEXP (operands[0], 0);
3572 if (dead_or_set_p (curr_insn, addr))
3576 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3577 operands[0] = replace_equiv_address (operands[0], operands[4]);
3581 (define_insn "clrmemdi_postreload"
3582 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3584 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3585 (clobber (match_dup 0))
3586 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3587 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3589 "TARGET_64BIT && reload_completed"
3590 "* return output_block_clear (operands, !which_alternative);"
3591 [(set_attr "type" "multi,multi")])
3593 ;; Floating point move insns
3595 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3596 ;; to be reloaded by putting the constant into memory when
3597 ;; reg is a floating point register.
3599 ;; For integer registers we use ldil;ldo to set the appropriate
3602 ;; This must come before the movdf pattern, and it must be present
3603 ;; to handle obscure reloading cases.
3605 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3606 (match_operand:DF 1 "" "?F,m"))]
3607 "GET_CODE (operands[1]) == CONST_DOUBLE
3608 && operands[1] != CONST0_RTX (DFmode)
3610 && !TARGET_SOFT_FLOAT"
3611 "* return (which_alternative == 0 ? output_move_double (operands)
3612 : \"fldd%F1 %1,%0\");"
3613 [(set_attr "type" "move,fpload")
3614 (set_attr "length" "16,4")])
3616 (define_expand "movdf"
3617 [(set (match_operand:DF 0 "general_operand" "")
3618 (match_operand:DF 1 "general_operand" ""))]
3622 if (GET_CODE (operands[1]) == CONST_DOUBLE
3623 && operands[1] != CONST0_RTX (DFmode))
3625 /* Reject CONST_DOUBLE loads to all hard registers when
3626 generating 64-bit code and to floating point registers
3627 when generating 32-bit code. */
3628 if (REG_P (operands[0])
3629 && HARD_REGISTER_P (operands[0])
3630 && (TARGET_64BIT || REGNO (operands[0]) >= 32))
3634 operands[1] = force_const_mem (DFmode, operands[1]);
3637 if (emit_move_sequence (operands, DFmode, 0))
3641 ;; Handle DFmode input reloads requiring a general register as a
3642 ;; scratch register.
3643 (define_expand "reload_indf"
3644 [(set (match_operand:DF 0 "register_operand" "=Z")
3645 (match_operand:DF 1 "non_hard_reg_operand" ""))
3646 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3650 if (emit_move_sequence (operands, DFmode, operands[2]))
3653 /* We don't want the clobber emitted, so handle this ourselves. */
3654 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3658 ;; Handle DFmode output reloads requiring a general register as a
3659 ;; scratch register.
3660 (define_expand "reload_outdf"
3661 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3662 (match_operand:DF 1 "register_operand" "Z"))
3663 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3667 if (emit_move_sequence (operands, DFmode, operands[2]))
3670 /* We don't want the clobber emitted, so handle this ourselves. */
3671 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3676 [(set (match_operand:DF 0 "move_dest_operand"
3677 "=f,*r,Q,?o,?Q,f,*r,*r,?*r,?f")
3678 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3679 "fG,*rG,f,*r,*r,RQ,o,RQ,f,*r"))]
3680 "(register_operand (operands[0], DFmode)
3681 || reg_or_0_operand (operands[1], DFmode))
3682 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3683 && GET_CODE (operands[0]) == MEM)
3685 && !TARGET_SOFT_FLOAT"
3688 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3689 || operands[1] == CONST0_RTX (DFmode))
3690 && !(REG_P (operands[0]) && REG_P (operands[1])
3691 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
3692 return output_fp_move_double (operands);
3693 return output_move_double (operands);
3695 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,fpstore_load,store_fpload")
3696 (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
3699 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3700 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3702 && !TARGET_DISABLE_INDEXING
3703 && reload_completed"
3705 [(set_attr "type" "fpstore")
3706 (set_attr "pa_combine_type" "addmove")
3707 (set_attr "length" "4")])
3710 [(set (match_operand:SI 0 "register_operand" "")
3711 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3713 (match_operand:SI 2 "register_operand" "")))
3714 (set (mem:DF (match_dup 0))
3715 (match_operand:DF 3 "register_operand" ""))]
3717 && !TARGET_DISABLE_INDEXING
3718 && REG_OK_FOR_BASE_P (operands[2])
3719 && FP_REGNO_P (REGNO (operands[3]))"
3720 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3722 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3727 [(set (match_operand:SI 0 "register_operand" "")
3728 (plus:SI (match_operand:SI 2 "register_operand" "")
3729 (mult:SI (match_operand:SI 1 "register_operand" "")
3731 (set (mem:DF (match_dup 0))
3732 (match_operand:DF 3 "register_operand" ""))]
3734 && !TARGET_DISABLE_INDEXING
3735 && REG_OK_FOR_BASE_P (operands[2])
3736 && FP_REGNO_P (REGNO (operands[3]))"
3737 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3739 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3744 [(set (match_operand:DI 0 "register_operand" "")
3745 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
3747 (match_operand:DI 2 "register_operand" "")))
3748 (set (mem:DF (match_dup 0))
3749 (match_operand:DF 3 "register_operand" ""))]
3751 && !TARGET_DISABLE_INDEXING
3753 && REG_OK_FOR_BASE_P (operands[2])
3754 && FP_REGNO_P (REGNO (operands[3]))"
3755 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3757 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3762 [(set (match_operand:DI 0 "register_operand" "")
3763 (plus:DI (match_operand:DI 2 "register_operand" "")
3764 (mult:DI (match_operand:DI 1 "register_operand" "")
3766 (set (mem:DF (match_dup 0))
3767 (match_operand:DF 3 "register_operand" ""))]
3769 && !TARGET_DISABLE_INDEXING
3771 && REG_OK_FOR_BASE_P (operands[2])
3772 && FP_REGNO_P (REGNO (operands[3]))"
3773 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3775 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3780 [(set (match_operand:SI 0 "register_operand" "")
3781 (plus:SI (match_operand:SI 1 "register_operand" "")
3782 (match_operand:SI 2 "register_operand" "")))
3783 (set (mem:DF (match_dup 0))
3784 (match_operand:DF 3 "register_operand" ""))]
3786 && !TARGET_DISABLE_INDEXING
3787 && TARGET_NO_SPACE_REGS
3788 && REG_OK_FOR_INDEX_P (operands[1])
3789 && REG_OK_FOR_BASE_P (operands[2])
3790 && FP_REGNO_P (REGNO (operands[3]))"
3791 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3793 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3797 [(set (match_operand:SI 0 "register_operand" "")
3798 (plus:SI (match_operand:SI 1 "register_operand" "")
3799 (match_operand:SI 2 "register_operand" "")))
3800 (set (mem:DF (match_dup 0))
3801 (match_operand:DF 3 "register_operand" ""))]
3803 && !TARGET_DISABLE_INDEXING
3804 && TARGET_NO_SPACE_REGS
3805 && REG_OK_FOR_BASE_P (operands[1])
3806 && REG_OK_FOR_INDEX_P (operands[2])
3807 && FP_REGNO_P (REGNO (operands[3]))"
3808 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3810 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3814 [(set (match_operand:DI 0 "register_operand" "")
3815 (plus:DI (match_operand:DI 1 "register_operand" "")
3816 (match_operand:DI 2 "register_operand" "")))
3817 (set (mem:DF (match_dup 0))
3818 (match_operand:DF 3 "register_operand" ""))]
3820 && !TARGET_DISABLE_INDEXING
3822 && TARGET_NO_SPACE_REGS
3823 && REG_OK_FOR_INDEX_P (operands[1])
3824 && REG_OK_FOR_BASE_P (operands[2])
3825 && FP_REGNO_P (REGNO (operands[3]))"
3826 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
3828 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3832 [(set (match_operand:DI 0 "register_operand" "")
3833 (plus:DI (match_operand:DI 1 "register_operand" "")
3834 (match_operand:DI 2 "register_operand" "")))
3835 (set (mem:DF (match_dup 0))
3836 (match_operand:DF 3 "register_operand" ""))]
3838 && !TARGET_DISABLE_INDEXING
3840 && TARGET_NO_SPACE_REGS
3841 && REG_OK_FOR_BASE_P (operands[1])
3842 && REG_OK_FOR_INDEX_P (operands[2])
3843 && FP_REGNO_P (REGNO (operands[3]))"
3844 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
3846 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
3850 [(set (match_operand:DF 0 "move_dest_operand"
3852 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3854 "(register_operand (operands[0], DFmode)
3855 || reg_or_0_operand (operands[1], DFmode))
3857 && TARGET_SOFT_FLOAT"
3860 return output_move_double (operands);
3862 [(set_attr "type" "move,store,store,load,load")
3863 (set_attr "length" "8,8,16,8,16")])
3866 [(set (match_operand:DF 0 "move_dest_operand"
3867 "=!*r,*r,*r,*r,*r,Q,f,f,T")
3868 (match_operand:DF 1 "move_src_operand"
3869 "!*r,J,N,K,RQ,*rG,fG,RT,f"))]
3870 "(register_operand (operands[0], DFmode)
3871 || reg_or_0_operand (operands[1], DFmode))
3872 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
3883 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
3884 (set_attr "pa_combine_type" "addmove")
3885 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3888 (define_expand "movdi"
3889 [(set (match_operand:DI 0 "general_operand" "")
3890 (match_operand:DI 1 "general_operand" ""))]
3894 /* Except for zero, we don't support loading a CONST_INT directly
3895 to a hard floating-point register since a scratch register is
3896 needed for the operation. While the operation could be handled
3897 before register allocation, the simplest solution is to fail. */
3899 && GET_CODE (operands[1]) == CONST_INT
3900 && operands[1] != CONST0_RTX (DImode)
3901 && REG_P (operands[0])
3902 && HARD_REGISTER_P (operands[0])
3903 && REGNO (operands[0]) >= 32)
3906 if (emit_move_sequence (operands, DImode, 0))
3910 ;; Handle DImode input reloads requiring %r1 as a scratch register.
3911 (define_expand "reload_indi_r1"
3912 [(set (match_operand:DI 0 "register_operand" "=Z")
3913 (match_operand:DI 1 "non_hard_reg_operand" ""))
3914 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
3918 if (emit_move_sequence (operands, DImode, operands[2]))
3921 /* We don't want the clobber emitted, so handle this ourselves. */
3922 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3926 ;; Handle DImode input reloads requiring a general register as a
3927 ;; scratch register.
3928 (define_expand "reload_indi"
3929 [(set (match_operand:DI 0 "register_operand" "=Z")
3930 (match_operand:DI 1 "non_hard_reg_operand" ""))
3931 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3935 if (emit_move_sequence (operands, DImode, operands[2]))
3938 /* We don't want the clobber emitted, so handle this ourselves. */
3939 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3943 ;; Handle DImode output reloads requiring a general register as a
3944 ;; scratch register.
3945 (define_expand "reload_outdi"
3946 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
3947 (match_operand:DI 1 "register_operand" "Z"))
3948 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3952 if (emit_move_sequence (operands, DImode, operands[2]))
3955 /* We don't want the clobber emitted, so handle this ourselves. */
3956 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3961 [(set (match_operand:DI 0 "register_operand" "=r")
3962 (high:DI (match_operand 1 "" "")))]
3966 rtx op0 = operands[0];
3967 rtx op1 = operands[1];
3969 switch (GET_CODE (op1))
3972 #if HOST_BITS_PER_WIDE_INT <= 32
3973 operands[0] = operand_subword (op0, 1, 0, DImode);
3974 output_asm_insn (\"ldil L'%1,%0\", operands);
3976 operands[0] = operand_subword (op0, 0, 0, DImode);
3977 if (INTVAL (op1) < 0)
3978 output_asm_insn (\"ldi -1,%0\", operands);
3980 output_asm_insn (\"ldi 0,%0\", operands);
3982 operands[0] = operand_subword (op0, 1, 0, DImode);
3983 operands[1] = GEN_INT (INTVAL (op1) & 0xffffffff);
3984 output_asm_insn (\"ldil L'%1,%0\", operands);
3986 operands[0] = operand_subword (op0, 0, 0, DImode);
3987 operands[1] = GEN_INT (INTVAL (op1) >> 32);
3988 output_asm_insn (singlemove_string (operands), operands);
3993 operands[0] = operand_subword (op0, 1, 0, DImode);
3994 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
3995 output_asm_insn (\"ldil L'%1,%0\", operands);
3997 operands[0] = operand_subword (op0, 0, 0, DImode);
3998 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
3999 output_asm_insn (singlemove_string (operands), operands);
4007 [(set_attr "type" "move")
4008 (set_attr "length" "12")])
4011 [(set (match_operand:DI 0 "move_dest_operand"
4012 "=r,o,Q,r,r,r,*f,*f,T,?r,?*f")
4013 (match_operand:DI 1 "general_operand"
4014 "rM,r,r,o*R,Q,i,*fM,RT,*f,*f,r"))]
4015 "(register_operand (operands[0], DImode)
4016 || reg_or_0_operand (operands[1], DImode))
4018 && !TARGET_SOFT_FLOAT"
4021 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4022 || operands[1] == CONST0_RTX (DFmode))
4023 && !(REG_P (operands[0]) && REG_P (operands[1])
4024 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4025 return output_fp_move_double (operands);
4026 return output_move_double (operands);
4029 "move,store,store,load,load,multi,fpalu,fpload,fpstore,fpstore_load,store_fpload")
4030 (set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
4033 [(set (match_operand:DI 0 "move_dest_operand"
4034 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4035 (match_operand:DI 1 "move_src_operand"
4036 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4037 "(register_operand (operands[0], DImode)
4038 || reg_or_0_operand (operands[1], DImode))
4039 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4049 {mfctl|mfctl,w} %%sar,%0
4053 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4054 (set_attr "pa_combine_type" "addmove")
4055 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4058 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4059 (match_operand:DI 1 "register_operand" "f"))]
4062 && !TARGET_DISABLE_INDEXING
4063 && reload_completed"
4065 [(set_attr "type" "fpstore")
4066 (set_attr "pa_combine_type" "addmove")
4067 (set_attr "length" "4")])
4070 [(set (match_operand:DI 0 "register_operand" "")
4071 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4073 (match_operand:DI 2 "register_operand" "")))
4074 (set (mem:DI (match_dup 0))
4075 (match_operand:DI 3 "register_operand" ""))]
4077 && !TARGET_DISABLE_INDEXING
4079 && REG_OK_FOR_BASE_P (operands[2])
4080 && FP_REGNO_P (REGNO (operands[3]))"
4081 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4083 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4088 [(set (match_operand:DI 0 "register_operand" "")
4089 (plus:DI (match_operand:DI 2 "register_operand" "")
4090 (mult:DI (match_operand:DI 1 "register_operand" "")
4092 (set (mem:DI (match_dup 0))
4093 (match_operand:DI 3 "register_operand" ""))]
4095 && !TARGET_DISABLE_INDEXING
4097 && REG_OK_FOR_BASE_P (operands[2])
4098 && FP_REGNO_P (REGNO (operands[3]))"
4099 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4101 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4106 [(set (match_operand:DI 0 "register_operand" "")
4107 (plus:DI (match_operand:DI 1 "register_operand" "")
4108 (match_operand:DI 2 "register_operand" "")))
4109 (set (mem:DI (match_dup 0))
4110 (match_operand:DI 3 "register_operand" ""))]
4112 && !TARGET_DISABLE_INDEXING
4114 && TARGET_NO_SPACE_REGS
4115 && REG_OK_FOR_INDEX_P (operands[1])
4116 && REG_OK_FOR_BASE_P (operands[2])
4117 && FP_REGNO_P (REGNO (operands[3]))"
4118 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4120 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4124 [(set (match_operand:DI 0 "register_operand" "")
4125 (plus:DI (match_operand:DI 1 "register_operand" "")
4126 (match_operand:DI 2 "register_operand" "")))
4127 (set (mem:DI (match_dup 0))
4128 (match_operand:DI 3 "register_operand" ""))]
4130 && !TARGET_DISABLE_INDEXING
4132 && TARGET_NO_SPACE_REGS
4133 && REG_OK_FOR_BASE_P (operands[1])
4134 && REG_OK_FOR_INDEX_P (operands[2])
4135 && FP_REGNO_P (REGNO (operands[3]))"
4136 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4138 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4142 [(set (match_operand:DI 0 "move_dest_operand"
4144 (match_operand:DI 1 "general_operand"
4146 "(register_operand (operands[0], DImode)
4147 || reg_or_0_operand (operands[1], DImode))
4149 && TARGET_SOFT_FLOAT"
4152 return output_move_double (operands);
4154 [(set_attr "type" "move,store,store,load,load,multi")
4155 (set_attr "length" "8,8,16,8,16,16")])
4158 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4159 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4160 (match_operand:DI 2 "immediate_operand" "i,i")))]
4164 /* Don't output a 64-bit constant, since we can't trust the assembler to
4165 handle it correctly. */
4166 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4167 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4168 else if (HOST_BITS_PER_WIDE_INT > 32
4169 && GET_CODE (operands[2]) == CONST_INT)
4170 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
4171 if (which_alternative == 1)
4172 output_asm_insn (\"copy %1,%0\", operands);
4173 return \"ldo R'%G2(%R1),%R0\";
4175 [(set_attr "type" "move,move")
4176 (set_attr "length" "4,8")])
4178 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4179 ;; to be reloaded by putting the constant into memory when
4180 ;; reg is a floating point register.
4182 ;; For integer registers we use ldil;ldo to set the appropriate
4185 ;; This must come before the movsf pattern, and it must be present
4186 ;; to handle obscure reloading cases.
4188 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4189 (match_operand:SF 1 "" "?F,m"))]
4190 "GET_CODE (operands[1]) == CONST_DOUBLE
4191 && operands[1] != CONST0_RTX (SFmode)
4192 && ! TARGET_SOFT_FLOAT"
4193 "* return (which_alternative == 0 ? singlemove_string (operands)
4194 : \" fldw%F1 %1,%0\");"
4195 [(set_attr "type" "move,fpload")
4196 (set_attr "length" "8,4")])
4198 (define_expand "movsf"
4199 [(set (match_operand:SF 0 "general_operand" "")
4200 (match_operand:SF 1 "general_operand" ""))]
4204 /* Reject CONST_DOUBLE loads to floating point registers. */
4205 if (GET_CODE (operands[1]) == CONST_DOUBLE
4206 && operands[1] != CONST0_RTX (SFmode)
4207 && REG_P (operands[0])
4208 && HARD_REGISTER_P (operands[0])
4209 && REGNO (operands[0]) >= 32)
4212 if (emit_move_sequence (operands, SFmode, 0))
4216 ;; Handle SFmode input reloads requiring a general register as a
4217 ;; scratch register.
4218 (define_expand "reload_insf"
4219 [(set (match_operand:SF 0 "register_operand" "=Z")
4220 (match_operand:SF 1 "non_hard_reg_operand" ""))
4221 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4225 if (emit_move_sequence (operands, SFmode, operands[2]))
4228 /* We don't want the clobber emitted, so handle this ourselves. */
4229 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4233 ;; Handle SFmode output reloads requiring a general register as a
4234 ;; scratch register.
4235 (define_expand "reload_outsf"
4236 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4237 (match_operand:SF 1 "register_operand" "Z"))
4238 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4242 if (emit_move_sequence (operands, SFmode, operands[2]))
4245 /* We don't want the clobber emitted, so handle this ourselves. */
4246 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4251 [(set (match_operand:SF 0 "move_dest_operand"
4252 "=f,!*r,f,*r,Q,Q,?*r,?f")
4253 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4254 "fG,!*rG,RQ,RQ,f,*rG,f,*r"))]
4255 "(register_operand (operands[0], SFmode)
4256 || reg_or_0_operand (operands[1], SFmode))
4257 && !TARGET_SOFT_FLOAT
4266 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
4267 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
4268 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,fpstore_load,store_fpload")
4269 (set_attr "pa_combine_type" "addmove")
4270 (set_attr "length" "4,4,4,4,4,4,8,8")])
4273 [(set (match_operand:SF 0 "move_dest_operand"
4275 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4276 "fG,!*rG,RQ,RQ,f,*rG"))]
4277 "(register_operand (operands[0], SFmode)
4278 || reg_or_0_operand (operands[1], SFmode))
4279 && !TARGET_SOFT_FLOAT
4288 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4289 (set_attr "pa_combine_type" "addmove")
4290 (set_attr "length" "4,4,4,4,4,4")])
4293 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4294 (match_operand:SF 1 "register_operand" "f"))]
4296 && !TARGET_DISABLE_INDEXING
4297 && reload_completed"
4299 [(set_attr "type" "fpstore")
4300 (set_attr "pa_combine_type" "addmove")
4301 (set_attr "length" "4")])
4304 [(set (match_operand:SI 0 "register_operand" "")
4305 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4307 (match_operand:SI 2 "register_operand" "")))
4308 (set (mem:SF (match_dup 0))
4309 (match_operand:SF 3 "register_operand" ""))]
4311 && !TARGET_DISABLE_INDEXING
4312 && REG_OK_FOR_BASE_P (operands[2])
4313 && FP_REGNO_P (REGNO (operands[3]))"
4314 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4316 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4321 [(set (match_operand:SI 0 "register_operand" "")
4322 (plus:SI (match_operand:SI 2 "register_operand" "")
4323 (mult:SI (match_operand:SI 1 "register_operand" "")
4325 (set (mem:SF (match_dup 0))
4326 (match_operand:SF 3 "register_operand" ""))]
4328 && !TARGET_DISABLE_INDEXING
4329 && REG_OK_FOR_BASE_P (operands[2])
4330 && FP_REGNO_P (REGNO (operands[3]))"
4331 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4333 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4338 [(set (match_operand:DI 0 "register_operand" "")
4339 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4341 (match_operand:DI 2 "register_operand" "")))
4342 (set (mem:SF (match_dup 0))
4343 (match_operand:SF 3 "register_operand" ""))]
4345 && !TARGET_DISABLE_INDEXING
4347 && REG_OK_FOR_BASE_P (operands[2])
4348 && FP_REGNO_P (REGNO (operands[3]))"
4349 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4351 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4356 [(set (match_operand:DI 0 "register_operand" "")
4357 (plus:DI (match_operand:DI 2 "register_operand" "")
4358 (mult:DI (match_operand:DI 1 "register_operand" "")
4360 (set (mem:SF (match_dup 0))
4361 (match_operand:SF 3 "register_operand" ""))]
4363 && !TARGET_DISABLE_INDEXING
4365 && REG_OK_FOR_BASE_P (operands[2])
4366 && FP_REGNO_P (REGNO (operands[3]))"
4367 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4369 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4374 [(set (match_operand:SI 0 "register_operand" "")
4375 (plus:SI (match_operand:SI 1 "register_operand" "")
4376 (match_operand:SI 2 "register_operand" "")))
4377 (set (mem:SF (match_dup 0))
4378 (match_operand:SF 3 "register_operand" ""))]
4380 && !TARGET_DISABLE_INDEXING
4381 && TARGET_NO_SPACE_REGS
4382 && REG_OK_FOR_INDEX_P (operands[1])
4383 && REG_OK_FOR_BASE_P (operands[2])
4384 && FP_REGNO_P (REGNO (operands[3]))"
4385 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4387 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4391 [(set (match_operand:SI 0 "register_operand" "")
4392 (plus:SI (match_operand:SI 1 "register_operand" "")
4393 (match_operand:SI 2 "register_operand" "")))
4394 (set (mem:SF (match_dup 0))
4395 (match_operand:SF 3 "register_operand" ""))]
4397 && !TARGET_DISABLE_INDEXING
4398 && TARGET_NO_SPACE_REGS
4399 && REG_OK_FOR_BASE_P (operands[1])
4400 && REG_OK_FOR_INDEX_P (operands[2])
4401 && FP_REGNO_P (REGNO (operands[3]))"
4402 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4404 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4408 [(set (match_operand:DI 0 "register_operand" "")
4409 (plus:DI (match_operand:DI 1 "register_operand" "")
4410 (match_operand:DI 2 "register_operand" "")))
4411 (set (mem:SF (match_dup 0))
4412 (match_operand:SF 3 "register_operand" ""))]
4414 && !TARGET_DISABLE_INDEXING
4416 && TARGET_NO_SPACE_REGS
4417 && REG_OK_FOR_INDEX_P (operands[1])
4418 && REG_OK_FOR_BASE_P (operands[2])
4419 && FP_REGNO_P (REGNO (operands[3]))"
4420 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4422 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4426 [(set (match_operand:DI 0 "register_operand" "")
4427 (plus:DI (match_operand:DI 1 "register_operand" "")
4428 (match_operand:DI 2 "register_operand" "")))
4429 (set (mem:SF (match_dup 0))
4430 (match_operand:SF 3 "register_operand" ""))]
4432 && !TARGET_DISABLE_INDEXING
4434 && TARGET_NO_SPACE_REGS
4435 && REG_OK_FOR_BASE_P (operands[1])
4436 && REG_OK_FOR_INDEX_P (operands[2])
4437 && FP_REGNO_P (REGNO (operands[3]))"
4438 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4440 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4444 [(set (match_operand:SF 0 "move_dest_operand"
4446 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4448 "(register_operand (operands[0], SFmode)
4449 || reg_or_0_operand (operands[1], SFmode))
4450 && TARGET_SOFT_FLOAT"
4455 [(set_attr "type" "move,load,store")
4456 (set_attr "pa_combine_type" "addmove")
4457 (set_attr "length" "4,4,4")])
4461 ;;- zero extension instructions
4462 ;; We have define_expand for zero extension patterns to make sure the
4463 ;; operands get loaded into registers. The define_insns accept
4464 ;; memory operands. This gives us better overall code than just
4465 ;; having a pattern that does or does not accept memory operands.
4467 (define_expand "zero_extendqihi2"
4468 [(set (match_operand:HI 0 "register_operand" "")
4470 (match_operand:QI 1 "register_operand" "")))]
4475 [(set (match_operand:HI 0 "register_operand" "=r,r")
4477 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4478 "GET_CODE (operands[1]) != CONST_INT"
4480 {extru|extrw,u} %1,31,8,%0
4482 [(set_attr "type" "shift,load")
4483 (set_attr "length" "4,4")])
4485 (define_expand "zero_extendqisi2"
4486 [(set (match_operand:SI 0 "register_operand" "")
4488 (match_operand:QI 1 "register_operand" "")))]
4493 [(set (match_operand:SI 0 "register_operand" "=r,r")
4495 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4496 "GET_CODE (operands[1]) != CONST_INT"
4498 {extru|extrw,u} %1,31,8,%0
4500 [(set_attr "type" "shift,load")
4501 (set_attr "length" "4,4")])
4503 (define_expand "zero_extendhisi2"
4504 [(set (match_operand:SI 0 "register_operand" "")
4506 (match_operand:HI 1 "register_operand" "")))]
4511 [(set (match_operand:SI 0 "register_operand" "=r,r")
4513 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4514 "GET_CODE (operands[1]) != CONST_INT"
4516 {extru|extrw,u} %1,31,16,%0
4518 [(set_attr "type" "shift,load")
4519 (set_attr "length" "4,4")])
4521 (define_expand "zero_extendqidi2"
4522 [(set (match_operand:DI 0 "register_operand" "")
4524 (match_operand:QI 1 "register_operand" "")))]
4529 [(set (match_operand:DI 0 "register_operand" "=r,r")
4531 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4532 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4536 [(set_attr "type" "shift,load")
4537 (set_attr "length" "4,4")])
4539 (define_expand "zero_extendhidi2"
4540 [(set (match_operand:DI 0 "register_operand" "")
4542 (match_operand:HI 1 "register_operand" "")))]
4547 [(set (match_operand:DI 0 "register_operand" "=r,r")
4549 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4550 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4554 [(set_attr "type" "shift,load")
4555 (set_attr "length" "4,4")])
4557 (define_expand "zero_extendsidi2"
4558 [(set (match_operand:DI 0 "register_operand" "")
4560 (match_operand:SI 1 "register_operand" "")))]
4565 [(set (match_operand:DI 0 "register_operand" "=r,r")
4567 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4568 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4572 [(set_attr "type" "shift,load")
4573 (set_attr "length" "4,4")])
4575 ;;- sign extension instructions
4577 (define_insn "extendhisi2"
4578 [(set (match_operand:SI 0 "register_operand" "=r")
4579 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4581 "{extrs|extrw,s} %1,31,16,%0"
4582 [(set_attr "type" "shift")
4583 (set_attr "length" "4")])
4585 (define_insn "extendqihi2"
4586 [(set (match_operand:HI 0 "register_operand" "=r")
4587 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4589 "{extrs|extrw,s} %1,31,8,%0"
4590 [(set_attr "type" "shift")
4591 (set_attr "length" "4")])
4593 (define_insn "extendqisi2"
4594 [(set (match_operand:SI 0 "register_operand" "=r")
4595 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4597 "{extrs|extrw,s} %1,31,8,%0"
4598 [(set_attr "type" "shift")
4599 (set_attr "length" "4")])
4601 (define_insn "extendqidi2"
4602 [(set (match_operand:DI 0 "register_operand" "=r")
4603 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4605 "extrd,s %1,63,8,%0"
4606 [(set_attr "type" "shift")
4607 (set_attr "length" "4")])
4609 (define_insn "extendhidi2"
4610 [(set (match_operand:DI 0 "register_operand" "=r")
4611 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4613 "extrd,s %1,63,16,%0"
4614 [(set_attr "type" "shift")
4615 (set_attr "length" "4")])
4617 (define_insn "extendsidi2"
4618 [(set (match_operand:DI 0 "register_operand" "=r")
4619 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4621 "extrd,s %1,63,32,%0"
4622 [(set_attr "type" "shift")
4623 (set_attr "length" "4")])
4626 ;; Conversions between float and double.
4628 (define_insn "extendsfdf2"
4629 [(set (match_operand:DF 0 "register_operand" "=f")
4631 (match_operand:SF 1 "register_operand" "f")))]
4632 "! TARGET_SOFT_FLOAT"
4633 "{fcnvff|fcnv},sgl,dbl %1,%0"
4634 [(set_attr "type" "fpalu")
4635 (set_attr "length" "4")])
4637 (define_insn "truncdfsf2"
4638 [(set (match_operand:SF 0 "register_operand" "=f")
4640 (match_operand:DF 1 "register_operand" "f")))]
4641 "! TARGET_SOFT_FLOAT"
4642 "{fcnvff|fcnv},dbl,sgl %1,%0"
4643 [(set_attr "type" "fpalu")
4644 (set_attr "length" "4")])
4646 ;; Conversion between fixed point and floating point.
4647 ;; Note that among the fix-to-float insns
4648 ;; the ones that start with SImode come first.
4649 ;; That is so that an operand that is a CONST_INT
4650 ;; (and therefore lacks a specific machine mode).
4651 ;; will be recognized as SImode (which is always valid)
4652 ;; rather than as QImode or HImode.
4654 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4655 ;; to be reloaded by putting the constant into memory.
4656 ;; It must come before the more general floatsisf2 pattern.
4658 [(set (match_operand:SF 0 "register_operand" "=f")
4659 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4660 "! TARGET_SOFT_FLOAT"
4661 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4662 [(set_attr "type" "fpalu")
4663 (set_attr "length" "8")])
4665 (define_insn "floatsisf2"
4666 [(set (match_operand:SF 0 "register_operand" "=f")
4667 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4668 "! TARGET_SOFT_FLOAT"
4669 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4670 [(set_attr "type" "fpalu")
4671 (set_attr "length" "4")])
4673 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4674 ;; to be reloaded by putting the constant into memory.
4675 ;; It must come before the more general floatsidf2 pattern.
4677 [(set (match_operand:DF 0 "register_operand" "=f")
4678 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4679 "! TARGET_SOFT_FLOAT"
4680 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4681 [(set_attr "type" "fpalu")
4682 (set_attr "length" "8")])
4684 (define_insn "floatsidf2"
4685 [(set (match_operand:DF 0 "register_operand" "=f")
4686 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4687 "! TARGET_SOFT_FLOAT"
4688 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4689 [(set_attr "type" "fpalu")
4690 (set_attr "length" "4")])
4692 (define_expand "floatunssisf2"
4693 [(set (subreg:SI (match_dup 2) 4)
4694 (match_operand:SI 1 "register_operand" ""))
4695 (set (subreg:SI (match_dup 2) 0)
4697 (set (match_operand:SF 0 "register_operand" "")
4698 (float:SF (match_dup 2)))]
4699 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4704 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4707 operands[2] = gen_reg_rtx (DImode);
4710 (define_expand "floatunssidf2"
4711 [(set (subreg:SI (match_dup 2) 4)
4712 (match_operand:SI 1 "register_operand" ""))
4713 (set (subreg:SI (match_dup 2) 0)
4715 (set (match_operand:DF 0 "register_operand" "")
4716 (float:DF (match_dup 2)))]
4717 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4722 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4725 operands[2] = gen_reg_rtx (DImode);
4728 (define_insn "floatdisf2"
4729 [(set (match_operand:SF 0 "register_operand" "=f")
4730 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4731 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4732 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4733 [(set_attr "type" "fpalu")
4734 (set_attr "length" "4")])
4736 (define_insn "floatdidf2"
4737 [(set (match_operand:DF 0 "register_operand" "=f")
4738 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4739 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4740 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4741 [(set_attr "type" "fpalu")
4742 (set_attr "length" "4")])
4744 ;; Convert a float to an actual integer.
4745 ;; Truncation is performed as part of the conversion.
4747 (define_insn "fix_truncsfsi2"
4748 [(set (match_operand:SI 0 "register_operand" "=f")
4749 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4750 "! TARGET_SOFT_FLOAT"
4751 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4752 [(set_attr "type" "fpalu")
4753 (set_attr "length" "4")])
4755 (define_insn "fix_truncdfsi2"
4756 [(set (match_operand:SI 0 "register_operand" "=f")
4757 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4758 "! TARGET_SOFT_FLOAT"
4759 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4760 [(set_attr "type" "fpalu")
4761 (set_attr "length" "4")])
4763 (define_insn "fix_truncsfdi2"
4764 [(set (match_operand:DI 0 "register_operand" "=f")
4765 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4766 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4767 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4768 [(set_attr "type" "fpalu")
4769 (set_attr "length" "4")])
4771 (define_insn "fix_truncdfdi2"
4772 [(set (match_operand:DI 0 "register_operand" "=f")
4773 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4774 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4775 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4776 [(set_attr "type" "fpalu")
4777 (set_attr "length" "4")])
4779 (define_insn "floatunssidf2_pa20"
4780 [(set (match_operand:DF 0 "register_operand" "=f")
4781 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4782 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4784 [(set_attr "type" "fpalu")
4785 (set_attr "length" "4")])
4787 (define_insn "floatunssisf2_pa20"
4788 [(set (match_operand:SF 0 "register_operand" "=f")
4789 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4790 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4792 [(set_attr "type" "fpalu")
4793 (set_attr "length" "4")])
4795 (define_insn "floatunsdisf2"
4796 [(set (match_operand:SF 0 "register_operand" "=f")
4797 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4798 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4799 "fcnv,udw,sgl %1,%0"
4800 [(set_attr "type" "fpalu")
4801 (set_attr "length" "4")])
4803 (define_insn "floatunsdidf2"
4804 [(set (match_operand:DF 0 "register_operand" "=f")
4805 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4806 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4807 "fcnv,udw,dbl %1,%0"
4808 [(set_attr "type" "fpalu")
4809 (set_attr "length" "4")])
4811 (define_insn "fixuns_truncsfsi2"
4812 [(set (match_operand:SI 0 "register_operand" "=f")
4813 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4814 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4815 "fcnv,t,sgl,uw %1,%0"
4816 [(set_attr "type" "fpalu")
4817 (set_attr "length" "4")])
4819 (define_insn "fixuns_truncdfsi2"
4820 [(set (match_operand:SI 0 "register_operand" "=f")
4821 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4822 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4823 "fcnv,t,dbl,uw %1,%0"
4824 [(set_attr "type" "fpalu")
4825 (set_attr "length" "4")])
4827 (define_insn "fixuns_truncsfdi2"
4828 [(set (match_operand:DI 0 "register_operand" "=f")
4829 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4830 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4831 "fcnv,t,sgl,udw %1,%0"
4832 [(set_attr "type" "fpalu")
4833 (set_attr "length" "4")])
4835 (define_insn "fixuns_truncdfdi2"
4836 [(set (match_operand:DI 0 "register_operand" "=f")
4837 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4838 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4839 "fcnv,t,dbl,udw %1,%0"
4840 [(set_attr "type" "fpalu")
4841 (set_attr "length" "4")])
4843 ;;- arithmetic instructions
4845 (define_expand "adddi3"
4846 [(set (match_operand:DI 0 "register_operand" "")
4847 (plus:DI (match_operand:DI 1 "register_operand" "")
4848 (match_operand:DI 2 "adddi3_operand" "")))]
4853 [(set (match_operand:DI 0 "register_operand" "=r")
4854 (plus:DI (match_operand:DI 1 "register_operand" "%r")
4855 (match_operand:DI 2 "arith11_operand" "rI")))]
4859 if (GET_CODE (operands[2]) == CONST_INT)
4861 if (INTVAL (operands[2]) >= 0)
4862 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
4864 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
4867 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
4869 [(set_attr "type" "binary")
4870 (set_attr "length" "8")])
4873 [(set (match_operand:DI 0 "register_operand" "=r,r")
4874 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4875 (match_operand:DI 2 "arith_operand" "r,J")))]
4880 [(set_attr "type" "binary,binary")
4881 (set_attr "pa_combine_type" "addmove")
4882 (set_attr "length" "4,4")])
4885 [(set (match_operand:DI 0 "register_operand" "=r")
4886 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4887 (match_operand:DI 2 "register_operand" "r")))]
4890 [(set_attr "type" "binary")
4891 (set_attr "length" "4")])
4894 [(set (match_operand:SI 0 "register_operand" "=r")
4895 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4896 (match_operand:SI 2 "register_operand" "r")))]
4899 [(set_attr "type" "binary")
4900 (set_attr "length" "4")])
4902 (define_expand "addvdi3"
4903 [(parallel [(set (match_operand:DI 0 "register_operand" "")
4904 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "")
4905 (match_operand:DI 2 "arith11_operand" "")))
4906 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
4907 (sign_extend:TI (match_dup 2)))
4908 (sign_extend:TI (plus:DI (match_dup 1)
4915 [(set (match_operand:DI 0 "register_operand" "=r,r")
4916 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM")
4917 (match_operand:DI 2 "arith11_operand" "r,I")))
4918 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
4919 (sign_extend:TI (match_dup 2)))
4920 (sign_extend:TI (plus:DI (match_dup 1)
4926 addi,tsv,* %2,%1,%0"
4927 [(set_attr "type" "binary,binary")
4928 (set_attr "length" "4,4")])
4931 [(set (match_operand:DI 0 "register_operand" "=r")
4932 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM")
4933 (match_operand:DI 2 "arith11_operand" "rI")))
4934 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
4935 (sign_extend:TI (match_dup 2)))
4936 (sign_extend:TI (plus:DI (match_dup 1)
4942 if (GET_CODE (operands[2]) == CONST_INT)
4944 if (INTVAL (operands[2]) >= 0)
4945 return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
4947 return \"addi %2,%R1,%R0\;{subbo|sub,b,tsv} %1,%%r0,%0\";
4950 return \"add %R2,%R1,%R0\;{addco|add,c,tsv} %2,%1,%0\";
4952 [(set_attr "type" "binary")
4953 (set_attr "length" "8")])
4955 ;; define_splits to optimize cases of adding a constant integer
4956 ;; to a register when the constant does not fit in 14 bits. */
4958 [(set (match_operand:SI 0 "register_operand" "")
4959 (plus:SI (match_operand:SI 1 "register_operand" "")
4960 (match_operand:SI 2 "const_int_operand" "")))
4961 (clobber (match_operand:SI 4 "register_operand" ""))]
4962 "! cint_ok_for_move (INTVAL (operands[2]))
4963 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
4964 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
4965 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
4968 int val = INTVAL (operands[2]);
4969 int low = (val < 0) ? -0x2000 : 0x1fff;
4970 int rest = val - low;
4972 operands[2] = GEN_INT (rest);
4973 operands[3] = GEN_INT (low);
4977 [(set (match_operand:SI 0 "register_operand" "")
4978 (plus:SI (match_operand:SI 1 "register_operand" "")
4979 (match_operand:SI 2 "const_int_operand" "")))
4980 (clobber (match_operand:SI 4 "register_operand" ""))]
4981 "! cint_ok_for_move (INTVAL (operands[2]))"
4982 [(set (match_dup 4) (match_dup 2))
4983 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
4987 HOST_WIDE_INT intval = INTVAL (operands[2]);
4989 /* Try dividing the constant by 2, then 4, and finally 8 to see
4990 if we can get a constant which can be loaded into a register
4991 in a single instruction (cint_ok_for_move).
4993 If that fails, try to negate the constant and subtract it
4994 from our input operand. */
4995 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
4997 operands[2] = GEN_INT (intval / 2);
4998 operands[3] = const2_rtx;
5000 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
5002 operands[2] = GEN_INT (intval / 4);
5003 operands[3] = GEN_INT (4);
5005 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
5007 operands[2] = GEN_INT (intval / 8);
5008 operands[3] = GEN_INT (8);
5010 else if (cint_ok_for_move (-intval))
5012 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
5013 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5020 (define_insn "addsi3"
5021 [(set (match_operand:SI 0 "register_operand" "=r,r")
5022 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5023 (match_operand:SI 2 "arith_operand" "r,J")))]
5026 {addl|add,l} %1,%2,%0
5028 [(set_attr "type" "binary,binary")
5029 (set_attr "pa_combine_type" "addmove")
5030 (set_attr "length" "4,4")])
5032 (define_insn "addvsi3"
5033 [(set (match_operand:SI 0 "register_operand" "=r,r")
5034 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rM,rM")
5035 (match_operand:SI 2 "arith11_operand" "r,I")))
5036 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
5037 (sign_extend:DI (match_dup 2)))
5038 (sign_extend:DI (plus:SI (match_dup 1)
5043 {addo|add,tsv} %2,%1,%0
5044 {addio|addi,tsv} %2,%1,%0"
5045 [(set_attr "type" "binary,binary")
5046 (set_attr "length" "4,4")])
5048 (define_expand "subdi3"
5049 [(set (match_operand:DI 0 "register_operand" "")
5050 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5051 (match_operand:DI 2 "reg_or_0_operand" "")))]
5056 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5057 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5058 (match_operand:DI 2 "reg_or_0_operand" "rM,rM,!rM")))]
5064 [(set_attr "type" "binary,binary,move")
5065 (set_attr "length" "4,4,4")])
5068 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5069 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5070 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))]
5074 if (GET_CODE (operands[1]) == CONST_INT)
5076 if (INTVAL (operands[1]) >= 0)
5077 return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
5079 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subb|sub,b} %0,%2,%0\";
5082 return \"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0\";
5084 [(set_attr "type" "binary")
5085 (set (attr "length")
5086 (if_then_else (eq_attr "alternative" "0")
5088 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5093 (define_expand "subvdi3"
5094 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5095 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5096 (match_operand:DI 2 "reg_or_0_operand" "")))
5097 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5098 (sign_extend:TI (match_dup 2)))
5099 (sign_extend:TI (minus:DI (match_dup 1)
5106 [(set (match_operand:DI 0 "register_operand" "=r,r")
5107 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5108 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5109 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5110 (sign_extend:TI (match_dup 2)))
5111 (sign_extend:TI (minus:DI (match_dup 1)
5116 {subo|sub,tsv} %1,%2,%0
5117 {subio|subi,tsv} %1,%2,%0"
5118 [(set_attr "type" "binary,binary")
5119 (set_attr "length" "4,4")])
5122 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5123 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5124 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5125 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5126 (sign_extend:TI (match_dup 2)))
5127 (sign_extend:TI (minus:DI (match_dup 1)
5133 if (GET_CODE (operands[1]) == CONST_INT)
5135 if (INTVAL (operands[1]) >= 0)
5136 return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
5138 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subbo|sub,b,tsv} %0,%2,%0\";
5141 return \"sub %R1,%R2,%R0\;{subbo|sub,b,tsv} %1,%2,%0\";
5143 [(set_attr "type" "binary,binary")
5144 (set (attr "length")
5145 (if_then_else (eq_attr "alternative" "0")
5147 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5152 (define_expand "subsi3"
5153 [(set (match_operand:SI 0 "register_operand" "")
5154 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5155 (match_operand:SI 2 "register_operand" "")))]
5160 [(set (match_operand:SI 0 "register_operand" "=r,r")
5161 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5162 (match_operand:SI 2 "register_operand" "r,r")))]
5167 [(set_attr "type" "binary,binary")
5168 (set_attr "length" "4,4")])
5171 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5172 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5173 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5179 [(set_attr "type" "binary,binary,move")
5180 (set_attr "length" "4,4,4")])
5182 (define_insn "subvsi3"
5183 [(set (match_operand:SI 0 "register_operand" "=r,r")
5184 (minus:SI (match_operand:SI 1 "arith11_operand" "rM,I")
5185 (match_operand:SI 2 "reg_or_0_operand" "rM,rM")))
5186 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
5187 (sign_extend:DI (match_dup 2)))
5188 (sign_extend:DI (minus:SI (match_dup 1)
5193 {subo|sub,tsv} %1,%2,%0
5194 {subio|subi,tsv} %1,%2,%0"
5195 [(set_attr "type" "binary,binary")
5196 (set_attr "length" "4,4")])
5198 ;; Clobbering a "register_operand" instead of a match_scratch
5199 ;; in operand3 of millicode calls avoids spilling %r1 and
5200 ;; produces better code.
5202 ;; The mulsi3 insns set up registers for the millicode call.
5203 (define_expand "mulsi3"
5204 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5205 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5206 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5207 (clobber (match_dup 3))
5208 (clobber (reg:SI 26))
5209 (clobber (reg:SI 25))
5210 (clobber (match_dup 4))])
5211 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5215 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5216 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5218 rtx scratch = gen_reg_rtx (DImode);
5219 operands[1] = force_reg (SImode, operands[1]);
5220 operands[2] = force_reg (SImode, operands[2]);
5221 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5222 emit_insn (gen_movsi (operands[0],
5223 gen_rtx_SUBREG (SImode, scratch,
5224 GET_MODE_SIZE (SImode))));
5227 operands[3] = gen_reg_rtx (SImode);
5230 (define_insn "umulsidi3"
5231 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5232 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5233 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5234 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5236 [(set_attr "type" "fpmuldbl")
5237 (set_attr "length" "4")])
5240 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5241 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5242 (match_operand:DI 2 "uint32_operand" "f")))]
5243 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5245 [(set_attr "type" "fpmuldbl")
5246 (set_attr "length" "4")])
5249 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5250 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5251 (match_operand:DI 2 "uint32_operand" "f")))]
5252 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5254 [(set_attr "type" "fpmuldbl")
5255 (set_attr "length" "4")])
5258 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5259 (clobber (match_operand:SI 0 "register_operand" "=a"))
5260 (clobber (reg:SI 26))
5261 (clobber (reg:SI 25))
5262 (clobber (reg:SI 31))]
5264 "* return output_mul_insn (0, insn);"
5265 [(set_attr "type" "milli")
5266 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5269 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5270 (clobber (match_operand:SI 0 "register_operand" "=a"))
5271 (clobber (reg:SI 26))
5272 (clobber (reg:SI 25))
5273 (clobber (reg:SI 2))]
5275 "* return output_mul_insn (0, insn);"
5276 [(set_attr "type" "milli")
5277 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5279 (define_expand "muldi3"
5280 [(set (match_operand:DI 0 "register_operand" "")
5281 (mult:DI (match_operand:DI 1 "register_operand" "")
5282 (match_operand:DI 2 "register_operand" "")))]
5283 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5286 rtx low_product = gen_reg_rtx (DImode);
5287 rtx cross_product1 = gen_reg_rtx (DImode);
5288 rtx cross_product2 = gen_reg_rtx (DImode);
5289 rtx cross_scratch = gen_reg_rtx (DImode);
5290 rtx cross_product = gen_reg_rtx (DImode);
5291 rtx op1l, op1r, op2l, op2r;
5292 rtx op1shifted, op2shifted;
5294 op1shifted = gen_reg_rtx (DImode);
5295 op2shifted = gen_reg_rtx (DImode);
5296 op1l = gen_reg_rtx (SImode);
5297 op1r = gen_reg_rtx (SImode);
5298 op2l = gen_reg_rtx (SImode);
5299 op2r = gen_reg_rtx (SImode);
5301 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5303 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5305 op1r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[1], 4));
5306 op2r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[2], 4));
5307 op1l = force_reg (SImode, gen_rtx_SUBREG (SImode, op1shifted, 4));
5308 op2l = force_reg (SImode, gen_rtx_SUBREG (SImode, op2shifted, 4));
5310 /* Emit multiplies for the cross products. */
5311 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5312 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5314 /* Emit a multiply for the low sub-word. */
5315 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5317 /* Sum the cross products and shift them into proper position. */
5318 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5319 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5321 /* Add the cross product to the low product and store the result
5322 into the output operand . */
5323 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5327 ;;; Division and mod.
5328 (define_expand "divsi3"
5329 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5330 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5331 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5332 (clobber (match_dup 3))
5333 (clobber (match_dup 4))
5334 (clobber (reg:SI 26))
5335 (clobber (reg:SI 25))
5336 (clobber (match_dup 5))])
5337 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5341 operands[3] = gen_reg_rtx (SImode);
5344 operands[5] = gen_rtx_REG (SImode, 2);
5345 operands[4] = operands[5];
5349 operands[5] = gen_rtx_REG (SImode, 31);
5350 operands[4] = gen_reg_rtx (SImode);
5352 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5358 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5359 (clobber (match_operand:SI 1 "register_operand" "=a"))
5360 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5361 (clobber (reg:SI 26))
5362 (clobber (reg:SI 25))
5363 (clobber (reg:SI 31))]
5366 return output_div_insn (operands, 0, insn);"
5367 [(set_attr "type" "milli")
5368 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5372 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5373 (clobber (match_operand:SI 1 "register_operand" "=a"))
5374 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5375 (clobber (reg:SI 26))
5376 (clobber (reg:SI 25))
5377 (clobber (reg:SI 2))]
5380 return output_div_insn (operands, 0, insn);"
5381 [(set_attr "type" "milli")
5382 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5384 (define_expand "udivsi3"
5385 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5386 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5387 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5388 (clobber (match_dup 3))
5389 (clobber (match_dup 4))
5390 (clobber (reg:SI 26))
5391 (clobber (reg:SI 25))
5392 (clobber (match_dup 5))])
5393 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5397 operands[3] = gen_reg_rtx (SImode);
5401 operands[5] = gen_rtx_REG (SImode, 2);
5402 operands[4] = operands[5];
5406 operands[5] = gen_rtx_REG (SImode, 31);
5407 operands[4] = gen_reg_rtx (SImode);
5409 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5415 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5416 (clobber (match_operand:SI 1 "register_operand" "=a"))
5417 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5418 (clobber (reg:SI 26))
5419 (clobber (reg:SI 25))
5420 (clobber (reg:SI 31))]
5423 return output_div_insn (operands, 1, insn);"
5424 [(set_attr "type" "milli")
5425 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5429 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5430 (clobber (match_operand:SI 1 "register_operand" "=a"))
5431 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5432 (clobber (reg:SI 26))
5433 (clobber (reg:SI 25))
5434 (clobber (reg:SI 2))]
5437 return output_div_insn (operands, 1, insn);"
5438 [(set_attr "type" "milli")
5439 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5441 (define_expand "modsi3"
5442 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5443 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5444 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5445 (clobber (match_dup 3))
5446 (clobber (match_dup 4))
5447 (clobber (reg:SI 26))
5448 (clobber (reg:SI 25))
5449 (clobber (match_dup 5))])
5450 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5456 operands[5] = gen_rtx_REG (SImode, 2);
5457 operands[4] = operands[5];
5461 operands[5] = gen_rtx_REG (SImode, 31);
5462 operands[4] = gen_reg_rtx (SImode);
5464 operands[3] = gen_reg_rtx (SImode);
5468 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5469 (clobber (match_operand:SI 0 "register_operand" "=a"))
5470 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5471 (clobber (reg:SI 26))
5472 (clobber (reg:SI 25))
5473 (clobber (reg:SI 31))]
5476 return output_mod_insn (0, insn);"
5477 [(set_attr "type" "milli")
5478 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5481 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5482 (clobber (match_operand:SI 0 "register_operand" "=a"))
5483 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5484 (clobber (reg:SI 26))
5485 (clobber (reg:SI 25))
5486 (clobber (reg:SI 2))]
5489 return output_mod_insn (0, insn);"
5490 [(set_attr "type" "milli")
5491 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5493 (define_expand "umodsi3"
5494 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5495 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5496 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5497 (clobber (match_dup 3))
5498 (clobber (match_dup 4))
5499 (clobber (reg:SI 26))
5500 (clobber (reg:SI 25))
5501 (clobber (match_dup 5))])
5502 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5508 operands[5] = gen_rtx_REG (SImode, 2);
5509 operands[4] = operands[5];
5513 operands[5] = gen_rtx_REG (SImode, 31);
5514 operands[4] = gen_reg_rtx (SImode);
5516 operands[3] = gen_reg_rtx (SImode);
5520 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5521 (clobber (match_operand:SI 0 "register_operand" "=a"))
5522 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5523 (clobber (reg:SI 26))
5524 (clobber (reg:SI 25))
5525 (clobber (reg:SI 31))]
5528 return output_mod_insn (1, insn);"
5529 [(set_attr "type" "milli")
5530 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5533 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5534 (clobber (match_operand:SI 0 "register_operand" "=a"))
5535 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5536 (clobber (reg:SI 26))
5537 (clobber (reg:SI 25))
5538 (clobber (reg:SI 2))]
5541 return output_mod_insn (1, insn);"
5542 [(set_attr "type" "milli")
5543 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5545 ;;- and instructions
5546 ;; We define DImode `and` so with DImode `not` we can get
5547 ;; DImode `andn`. Other combinations are possible.
5549 (define_expand "anddi3"
5550 [(set (match_operand:DI 0 "register_operand" "")
5551 (and:DI (match_operand:DI 1 "register_operand" "")
5552 (match_operand:DI 2 "and_operand" "")))]
5556 /* Both operands must be register operands. */
5557 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
5562 [(set (match_operand:DI 0 "register_operand" "=r")
5563 (and:DI (match_operand:DI 1 "register_operand" "%r")
5564 (match_operand:DI 2 "register_operand" "r")))]
5566 "and %1,%2,%0\;and %R1,%R2,%R0"
5567 [(set_attr "type" "binary")
5568 (set_attr "length" "8")])
5571 [(set (match_operand:DI 0 "register_operand" "=r,r")
5572 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5573 (match_operand:DI 2 "and_operand" "rO,P")))]
5575 "* return output_64bit_and (operands); "
5576 [(set_attr "type" "binary")
5577 (set_attr "length" "4")])
5579 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5580 ; constant with ldil;ldo.
5581 (define_insn "andsi3"
5582 [(set (match_operand:SI 0 "register_operand" "=r,r")
5583 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5584 (match_operand:SI 2 "and_operand" "rO,P")))]
5586 "* return output_and (operands); "
5587 [(set_attr "type" "binary,shift")
5588 (set_attr "length" "4,4")])
5591 [(set (match_operand:DI 0 "register_operand" "=r")
5592 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5593 (match_operand:DI 2 "register_operand" "r")))]
5595 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
5596 [(set_attr "type" "binary")
5597 (set_attr "length" "8")])
5600 [(set (match_operand:DI 0 "register_operand" "=r")
5601 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5602 (match_operand:DI 2 "register_operand" "r")))]
5605 [(set_attr "type" "binary")
5606 (set_attr "length" "4")])
5609 [(set (match_operand:SI 0 "register_operand" "=r")
5610 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5611 (match_operand:SI 2 "register_operand" "r")))]
5614 [(set_attr "type" "binary")
5615 (set_attr "length" "4")])
5617 (define_expand "iordi3"
5618 [(set (match_operand:DI 0 "register_operand" "")
5619 (ior:DI (match_operand:DI 1 "register_operand" "")
5620 (match_operand:DI 2 "ior_operand" "")))]
5624 /* Both operands must be register operands. */
5625 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
5630 [(set (match_operand:DI 0 "register_operand" "=r")
5631 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5632 (match_operand:DI 2 "register_operand" "r")))]
5634 "or %1,%2,%0\;or %R1,%R2,%R0"
5635 [(set_attr "type" "binary")
5636 (set_attr "length" "8")])
5639 [(set (match_operand:DI 0 "register_operand" "=r,r")
5640 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5641 (match_operand:DI 2 "ior_operand" "M,i")))]
5643 "* return output_64bit_ior (operands); "
5644 [(set_attr "type" "binary,shift")
5645 (set_attr "length" "4,4")])
5648 [(set (match_operand:DI 0 "register_operand" "=r")
5649 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5650 (match_operand:DI 2 "register_operand" "r")))]
5653 [(set_attr "type" "binary")
5654 (set_attr "length" "4")])
5656 ;; Need a define_expand because we've run out of CONST_OK... characters.
5657 (define_expand "iorsi3"
5658 [(set (match_operand:SI 0 "register_operand" "")
5659 (ior:SI (match_operand:SI 1 "register_operand" "")
5660 (match_operand:SI 2 "arith32_operand" "")))]
5664 if (! (ior_operand (operands[2], SImode)
5665 || register_operand (operands[2], SImode)))
5666 operands[2] = force_reg (SImode, operands[2]);
5670 [(set (match_operand:SI 0 "register_operand" "=r,r")
5671 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5672 (match_operand:SI 2 "ior_operand" "M,i")))]
5674 "* return output_ior (operands); "
5675 [(set_attr "type" "binary,shift")
5676 (set_attr "length" "4,4")])
5679 [(set (match_operand:SI 0 "register_operand" "=r")
5680 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5681 (match_operand:SI 2 "register_operand" "r")))]
5684 [(set_attr "type" "binary")
5685 (set_attr "length" "4")])
5687 (define_expand "xordi3"
5688 [(set (match_operand:DI 0 "register_operand" "")
5689 (xor:DI (match_operand:DI 1 "register_operand" "")
5690 (match_operand:DI 2 "register_operand" "")))]
5697 [(set (match_operand:DI 0 "register_operand" "=r")
5698 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5699 (match_operand:DI 2 "register_operand" "r")))]
5701 "xor %1,%2,%0\;xor %R1,%R2,%R0"
5702 [(set_attr "type" "binary")
5703 (set_attr "length" "8")])
5706 [(set (match_operand:DI 0 "register_operand" "=r")
5707 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5708 (match_operand:DI 2 "register_operand" "r")))]
5711 [(set_attr "type" "binary")
5712 (set_attr "length" "4")])
5714 (define_insn "xorsi3"
5715 [(set (match_operand:SI 0 "register_operand" "=r")
5716 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5717 (match_operand:SI 2 "register_operand" "r")))]
5720 [(set_attr "type" "binary")
5721 (set_attr "length" "4")])
5723 (define_expand "negdi2"
5724 [(set (match_operand:DI 0 "register_operand" "")
5725 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5730 [(set (match_operand:DI 0 "register_operand" "=r")
5731 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5733 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5734 [(set_attr "type" "unary")
5735 (set_attr "length" "8")])
5738 [(set (match_operand:DI 0 "register_operand" "=r")
5739 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5742 [(set_attr "type" "unary")
5743 (set_attr "length" "4")])
5745 (define_expand "negvdi2"
5746 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5747 (neg:DI (match_operand:DI 1 "register_operand" "")))
5748 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5749 (sign_extend:TI (neg:DI (match_dup 1))))
5755 [(set (match_operand:DI 0 "register_operand" "=r")
5756 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5757 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5758 (sign_extend:TI (neg:DI (match_dup 1))))
5761 "sub %%r0,%R1,%R0\;{subbo|sub,b,tsv} %%r0,%1,%0"
5762 [(set_attr "type" "unary")
5763 (set_attr "length" "8")])
5766 [(set (match_operand:DI 0 "register_operand" "=r")
5767 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5768 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5769 (sign_extend:TI (neg:DI (match_dup 1))))
5772 "sub,tsv %%r0,%1,%0"
5773 [(set_attr "type" "unary")
5774 (set_attr "length" "4")])
5776 (define_insn "negsi2"
5777 [(set (match_operand:SI 0 "register_operand" "=r")
5778 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5781 [(set_attr "type" "unary")
5782 (set_attr "length" "4")])
5784 (define_insn "negvsi2"
5785 [(set (match_operand:SI 0 "register_operand" "=r")
5786 (neg:SI (match_operand:SI 1 "register_operand" "r")))
5787 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
5788 (sign_extend:DI (neg:SI (match_dup 1))))
5791 "{subo|sub,tsv} %%r0,%1,%0"
5792 [(set_attr "type" "unary")
5793 (set_attr "length" "4")])
5795 (define_expand "one_cmpldi2"
5796 [(set (match_operand:DI 0 "register_operand" "")
5797 (not:DI (match_operand:DI 1 "register_operand" "")))]
5804 [(set (match_operand:DI 0 "register_operand" "=r")
5805 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5807 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5808 [(set_attr "type" "unary")
5809 (set_attr "length" "8")])
5812 [(set (match_operand:DI 0 "register_operand" "=r")
5813 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5816 [(set_attr "type" "unary")
5817 (set_attr "length" "4")])
5819 (define_insn "one_cmplsi2"
5820 [(set (match_operand:SI 0 "register_operand" "=r")
5821 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5824 [(set_attr "type" "unary")
5825 (set_attr "length" "4")])
5827 ;; Floating point arithmetic instructions.
5829 (define_insn "adddf3"
5830 [(set (match_operand:DF 0 "register_operand" "=f")
5831 (plus:DF (match_operand:DF 1 "register_operand" "f")
5832 (match_operand:DF 2 "register_operand" "f")))]
5833 "! TARGET_SOFT_FLOAT"
5835 [(set_attr "type" "fpalu")
5836 (set_attr "pa_combine_type" "faddsub")
5837 (set_attr "length" "4")])
5839 (define_insn "addsf3"
5840 [(set (match_operand:SF 0 "register_operand" "=f")
5841 (plus:SF (match_operand:SF 1 "register_operand" "f")
5842 (match_operand:SF 2 "register_operand" "f")))]
5843 "! TARGET_SOFT_FLOAT"
5845 [(set_attr "type" "fpalu")
5846 (set_attr "pa_combine_type" "faddsub")
5847 (set_attr "length" "4")])
5849 (define_insn "subdf3"
5850 [(set (match_operand:DF 0 "register_operand" "=f")
5851 (minus:DF (match_operand:DF 1 "register_operand" "f")
5852 (match_operand:DF 2 "register_operand" "f")))]
5853 "! TARGET_SOFT_FLOAT"
5855 [(set_attr "type" "fpalu")
5856 (set_attr "pa_combine_type" "faddsub")
5857 (set_attr "length" "4")])
5859 (define_insn "subsf3"
5860 [(set (match_operand:SF 0 "register_operand" "=f")
5861 (minus:SF (match_operand:SF 1 "register_operand" "f")
5862 (match_operand:SF 2 "register_operand" "f")))]
5863 "! TARGET_SOFT_FLOAT"
5865 [(set_attr "type" "fpalu")
5866 (set_attr "pa_combine_type" "faddsub")
5867 (set_attr "length" "4")])
5869 (define_insn "muldf3"
5870 [(set (match_operand:DF 0 "register_operand" "=f")
5871 (mult:DF (match_operand:DF 1 "register_operand" "f")
5872 (match_operand:DF 2 "register_operand" "f")))]
5873 "! TARGET_SOFT_FLOAT"
5875 [(set_attr "type" "fpmuldbl")
5876 (set_attr "pa_combine_type" "fmpy")
5877 (set_attr "length" "4")])
5879 (define_insn "mulsf3"
5880 [(set (match_operand:SF 0 "register_operand" "=f")
5881 (mult:SF (match_operand:SF 1 "register_operand" "f")
5882 (match_operand:SF 2 "register_operand" "f")))]
5883 "! TARGET_SOFT_FLOAT"
5885 [(set_attr "type" "fpmulsgl")
5886 (set_attr "pa_combine_type" "fmpy")
5887 (set_attr "length" "4")])
5889 (define_insn "divdf3"
5890 [(set (match_operand:DF 0 "register_operand" "=f")
5891 (div:DF (match_operand:DF 1 "register_operand" "f")
5892 (match_operand:DF 2 "register_operand" "f")))]
5893 "! TARGET_SOFT_FLOAT"
5895 [(set_attr "type" "fpdivdbl")
5896 (set_attr "length" "4")])
5898 (define_insn "divsf3"
5899 [(set (match_operand:SF 0 "register_operand" "=f")
5900 (div:SF (match_operand:SF 1 "register_operand" "f")
5901 (match_operand:SF 2 "register_operand" "f")))]
5902 "! TARGET_SOFT_FLOAT"
5904 [(set_attr "type" "fpdivsgl")
5905 (set_attr "length" "4")])
5907 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
5908 ;; negation can be done by subtracting from plus zero. However, this
5909 ;; violates the IEEE standard when negating plus and minus zero.
5910 (define_expand "negdf2"
5911 [(parallel [(set (match_operand:DF 0 "register_operand" "")
5912 (neg:DF (match_operand:DF 1 "register_operand" "")))
5913 (use (match_dup 2))])]
5914 "! TARGET_SOFT_FLOAT"
5916 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5917 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
5920 operands[2] = force_reg (DFmode,
5921 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
5922 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
5927 (define_insn "negdf2_fast"
5928 [(set (match_operand:DF 0 "register_operand" "=f")
5929 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
5930 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5934 return \"fneg,dbl %1,%0\";
5936 return \"fsub,dbl %%fr0,%1,%0\";
5938 [(set_attr "type" "fpalu")
5939 (set_attr "length" "4")])
5941 (define_expand "negsf2"
5942 [(parallel [(set (match_operand:SF 0 "register_operand" "")
5943 (neg:SF (match_operand:SF 1 "register_operand" "")))
5944 (use (match_dup 2))])]
5945 "! TARGET_SOFT_FLOAT"
5947 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5948 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
5951 operands[2] = force_reg (SFmode,
5952 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
5953 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
5958 (define_insn "negsf2_fast"
5959 [(set (match_operand:SF 0 "register_operand" "=f")
5960 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
5961 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5965 return \"fneg,sgl %1,%0\";
5967 return \"fsub,sgl %%fr0,%1,%0\";
5969 [(set_attr "type" "fpalu")
5970 (set_attr "length" "4")])
5972 (define_insn "absdf2"
5973 [(set (match_operand:DF 0 "register_operand" "=f")
5974 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
5975 "! TARGET_SOFT_FLOAT"
5977 [(set_attr "type" "fpalu")
5978 (set_attr "length" "4")])
5980 (define_insn "abssf2"
5981 [(set (match_operand:SF 0 "register_operand" "=f")
5982 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
5983 "! TARGET_SOFT_FLOAT"
5985 [(set_attr "type" "fpalu")
5986 (set_attr "length" "4")])
5988 (define_insn "sqrtdf2"
5989 [(set (match_operand:DF 0 "register_operand" "=f")
5990 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
5991 "! TARGET_SOFT_FLOAT"
5993 [(set_attr "type" "fpsqrtdbl")
5994 (set_attr "length" "4")])
5996 (define_insn "sqrtsf2"
5997 [(set (match_operand:SF 0 "register_operand" "=f")
5998 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
5999 "! TARGET_SOFT_FLOAT"
6001 [(set_attr "type" "fpsqrtsgl")
6002 (set_attr "length" "4")])
6004 ;; PA 2.0 floating point instructions
6008 [(set (match_operand:DF 0 "register_operand" "=f")
6009 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6010 (match_operand:DF 2 "register_operand" "f"))
6011 (match_operand:DF 3 "register_operand" "f")))]
6012 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6013 "fmpyfadd,dbl %1,%2,%3,%0"
6014 [(set_attr "type" "fpmuldbl")
6015 (set_attr "length" "4")])
6018 [(set (match_operand:DF 0 "register_operand" "=f")
6019 (plus:DF (match_operand:DF 1 "register_operand" "f")
6020 (mult:DF (match_operand:DF 2 "register_operand" "f")
6021 (match_operand:DF 3 "register_operand" "f"))))]
6022 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6023 "fmpyfadd,dbl %2,%3,%1,%0"
6024 [(set_attr "type" "fpmuldbl")
6025 (set_attr "length" "4")])
6028 [(set (match_operand:SF 0 "register_operand" "=f")
6029 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6030 (match_operand:SF 2 "register_operand" "f"))
6031 (match_operand:SF 3 "register_operand" "f")))]
6032 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6033 "fmpyfadd,sgl %1,%2,%3,%0"
6034 [(set_attr "type" "fpmulsgl")
6035 (set_attr "length" "4")])
6038 [(set (match_operand:SF 0 "register_operand" "=f")
6039 (plus:SF (match_operand:SF 1 "register_operand" "f")
6040 (mult:SF (match_operand:SF 2 "register_operand" "f")
6041 (match_operand:SF 3 "register_operand" "f"))))]
6042 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6043 "fmpyfadd,sgl %2,%3,%1,%0"
6044 [(set_attr "type" "fpmulsgl")
6045 (set_attr "length" "4")])
6047 ; fmpynfadd patterns
6049 [(set (match_operand:DF 0 "register_operand" "=f")
6050 (minus:DF (match_operand:DF 1 "register_operand" "f")
6051 (mult:DF (match_operand:DF 2 "register_operand" "f")
6052 (match_operand:DF 3 "register_operand" "f"))))]
6053 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6054 "fmpynfadd,dbl %2,%3,%1,%0"
6055 [(set_attr "type" "fpmuldbl")
6056 (set_attr "length" "4")])
6059 [(set (match_operand:SF 0 "register_operand" "=f")
6060 (minus:SF (match_operand:SF 1 "register_operand" "f")
6061 (mult:SF (match_operand:SF 2 "register_operand" "f")
6062 (match_operand:SF 3 "register_operand" "f"))))]
6063 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6064 "fmpynfadd,sgl %2,%3,%1,%0"
6065 [(set_attr "type" "fpmulsgl")
6066 (set_attr "length" "4")])
6070 [(set (match_operand:DF 0 "register_operand" "=f")
6071 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
6072 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6074 [(set_attr "type" "fpalu")
6075 (set_attr "length" "4")])
6078 [(set (match_operand:SF 0 "register_operand" "=f")
6079 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
6080 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6082 [(set_attr "type" "fpalu")
6083 (set_attr "length" "4")])
6085 ;; Generating a fused multiply sequence is a win for this case as it will
6086 ;; reduce the latency for the fused case without impacting the plain
6089 ;; Similar possibilities exist for fnegabs, shadd and other insns which
6090 ;; perform two operations with the result of the first feeding the second.
6092 [(set (match_operand:DF 0 "register_operand" "=f")
6093 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6094 (match_operand:DF 2 "register_operand" "f"))
6095 (match_operand:DF 3 "register_operand" "f")))
6096 (set (match_operand:DF 4 "register_operand" "=&f")
6097 (mult:DF (match_dup 1) (match_dup 2)))]
6098 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6099 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6100 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6102 [(set_attr "type" "fpmuldbl")
6103 (set_attr "length" "8")])
6105 ;; We want to split this up during scheduling since we want both insns
6106 ;; to schedule independently.
6108 [(set (match_operand:DF 0 "register_operand" "")
6109 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6110 (match_operand:DF 2 "register_operand" ""))
6111 (match_operand:DF 3 "register_operand" "")))
6112 (set (match_operand:DF 4 "register_operand" "")
6113 (mult:DF (match_dup 1) (match_dup 2)))]
6114 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6115 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6116 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
6121 [(set (match_operand:SF 0 "register_operand" "=f")
6122 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6123 (match_operand:SF 2 "register_operand" "f"))
6124 (match_operand:SF 3 "register_operand" "f")))
6125 (set (match_operand:SF 4 "register_operand" "=&f")
6126 (mult:SF (match_dup 1) (match_dup 2)))]
6127 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6128 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6129 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6131 [(set_attr "type" "fpmuldbl")
6132 (set_attr "length" "8")])
6134 ;; We want to split this up during scheduling since we want both insns
6135 ;; to schedule independently.
6137 [(set (match_operand:SF 0 "register_operand" "")
6138 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6139 (match_operand:SF 2 "register_operand" ""))
6140 (match_operand:SF 3 "register_operand" "")))
6141 (set (match_operand:SF 4 "register_operand" "")
6142 (mult:SF (match_dup 1) (match_dup 2)))]
6143 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6144 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6145 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
6149 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6152 [(set (match_operand:DF 0 "register_operand" "=f")
6153 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6154 (match_operand:DF 2 "register_operand" "f"))))]
6155 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6156 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6157 [(set_attr "type" "fpmuldbl")
6158 (set_attr "length" "4")])
6161 [(set (match_operand:SF 0 "register_operand" "=f")
6162 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6163 (match_operand:SF 2 "register_operand" "f"))))]
6164 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6165 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6166 [(set_attr "type" "fpmuldbl")
6167 (set_attr "length" "4")])
6170 [(set (match_operand:DF 0 "register_operand" "=f")
6171 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6172 (match_operand:DF 2 "register_operand" "f"))))
6173 (set (match_operand:DF 3 "register_operand" "=&f")
6174 (mult:DF (match_dup 1) (match_dup 2)))]
6175 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6176 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6177 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6179 [(set_attr "type" "fpmuldbl")
6180 (set_attr "length" "8")])
6183 [(set (match_operand:DF 0 "register_operand" "")
6184 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6185 (match_operand:DF 2 "register_operand" ""))))
6186 (set (match_operand:DF 3 "register_operand" "")
6187 (mult:DF (match_dup 1) (match_dup 2)))]
6188 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6189 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6190 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6194 [(set (match_operand:SF 0 "register_operand" "=f")
6195 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6196 (match_operand:SF 2 "register_operand" "f"))))
6197 (set (match_operand:SF 3 "register_operand" "=&f")
6198 (mult:SF (match_dup 1) (match_dup 2)))]
6199 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6200 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6201 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6203 [(set_attr "type" "fpmuldbl")
6204 (set_attr "length" "8")])
6207 [(set (match_operand:SF 0 "register_operand" "")
6208 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6209 (match_operand:SF 2 "register_operand" ""))))
6210 (set (match_operand:SF 3 "register_operand" "")
6211 (mult:SF (match_dup 1) (match_dup 2)))]
6212 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6213 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6214 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6217 ;; Now fused multiplies with the result of the multiply negated.
6219 [(set (match_operand:DF 0 "register_operand" "=f")
6220 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6221 (match_operand:DF 2 "register_operand" "f")))
6222 (match_operand:DF 3 "register_operand" "f")))]
6223 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6224 "fmpynfadd,dbl %1,%2,%3,%0"
6225 [(set_attr "type" "fpmuldbl")
6226 (set_attr "length" "4")])
6229 [(set (match_operand:SF 0 "register_operand" "=f")
6230 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6231 (match_operand:SF 2 "register_operand" "f")))
6232 (match_operand:SF 3 "register_operand" "f")))]
6233 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6234 "fmpynfadd,sgl %1,%2,%3,%0"
6235 [(set_attr "type" "fpmuldbl")
6236 (set_attr "length" "4")])
6239 [(set (match_operand:DF 0 "register_operand" "=f")
6240 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6241 (match_operand:DF 2 "register_operand" "f")))
6242 (match_operand:DF 3 "register_operand" "f")))
6243 (set (match_operand:DF 4 "register_operand" "=&f")
6244 (mult:DF (match_dup 1) (match_dup 2)))]
6245 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6246 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6247 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6249 [(set_attr "type" "fpmuldbl")
6250 (set_attr "length" "8")])
6253 [(set (match_operand:DF 0 "register_operand" "")
6254 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6255 (match_operand:DF 2 "register_operand" "")))
6256 (match_operand:DF 3 "register_operand" "")))
6257 (set (match_operand:DF 4 "register_operand" "")
6258 (mult:DF (match_dup 1) (match_dup 2)))]
6259 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6260 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6261 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6266 [(set (match_operand:SF 0 "register_operand" "=f")
6267 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6268 (match_operand:SF 2 "register_operand" "f")))
6269 (match_operand:SF 3 "register_operand" "f")))
6270 (set (match_operand:SF 4 "register_operand" "=&f")
6271 (mult:SF (match_dup 1) (match_dup 2)))]
6272 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6273 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6274 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6276 [(set_attr "type" "fpmuldbl")
6277 (set_attr "length" "8")])
6280 [(set (match_operand:SF 0 "register_operand" "")
6281 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6282 (match_operand:SF 2 "register_operand" "")))
6283 (match_operand:SF 3 "register_operand" "")))
6284 (set (match_operand:SF 4 "register_operand" "")
6285 (mult:SF (match_dup 1) (match_dup 2)))]
6286 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6287 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6288 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6293 [(set (match_operand:DF 0 "register_operand" "=f")
6294 (minus:DF (match_operand:DF 3 "register_operand" "f")
6295 (mult:DF (match_operand:DF 1 "register_operand" "f")
6296 (match_operand:DF 2 "register_operand" "f"))))
6297 (set (match_operand:DF 4 "register_operand" "=&f")
6298 (mult:DF (match_dup 1) (match_dup 2)))]
6299 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6300 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6301 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6303 [(set_attr "type" "fpmuldbl")
6304 (set_attr "length" "8")])
6307 [(set (match_operand:DF 0 "register_operand" "")
6308 (minus:DF (match_operand:DF 3 "register_operand" "")
6309 (mult:DF (match_operand:DF 1 "register_operand" "")
6310 (match_operand:DF 2 "register_operand" ""))))
6311 (set (match_operand:DF 4 "register_operand" "")
6312 (mult:DF (match_dup 1) (match_dup 2)))]
6313 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6314 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6315 (set (match_dup 0) (minus:DF (match_dup 3)
6316 (mult:DF (match_dup 1) (match_dup 2))))]
6320 [(set (match_operand:SF 0 "register_operand" "=f")
6321 (minus:SF (match_operand:SF 3 "register_operand" "f")
6322 (mult:SF (match_operand:SF 1 "register_operand" "f")
6323 (match_operand:SF 2 "register_operand" "f"))))
6324 (set (match_operand:SF 4 "register_operand" "=&f")
6325 (mult:SF (match_dup 1) (match_dup 2)))]
6326 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6327 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6328 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6330 [(set_attr "type" "fpmuldbl")
6331 (set_attr "length" "8")])
6334 [(set (match_operand:SF 0 "register_operand" "")
6335 (minus:SF (match_operand:SF 3 "register_operand" "")
6336 (mult:SF (match_operand:SF 1 "register_operand" "")
6337 (match_operand:SF 2 "register_operand" ""))))
6338 (set (match_operand:SF 4 "register_operand" "")
6339 (mult:SF (match_dup 1) (match_dup 2)))]
6340 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6341 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6342 (set (match_dup 0) (minus:SF (match_dup 3)
6343 (mult:SF (match_dup 1) (match_dup 2))))]
6347 [(set (match_operand:DF 0 "register_operand" "=f")
6348 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6349 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6350 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6351 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6353 [(set_attr "type" "fpalu")
6354 (set_attr "length" "8")])
6357 [(set (match_operand:DF 0 "register_operand" "")
6358 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6359 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6360 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6361 [(set (match_dup 2) (abs:DF (match_dup 1)))
6362 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6366 [(set (match_operand:SF 0 "register_operand" "=f")
6367 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6368 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6369 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6370 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6372 [(set_attr "type" "fpalu")
6373 (set_attr "length" "8")])
6376 [(set (match_operand:SF 0 "register_operand" "")
6377 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6378 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6379 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6380 [(set (match_dup 2) (abs:SF (match_dup 1)))
6381 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6384 ;;- Shift instructions
6386 ;; Optimized special case of shifting.
6389 [(set (match_operand:SI 0 "register_operand" "=r")
6390 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6394 [(set_attr "type" "load")
6395 (set_attr "length" "4")])
6398 [(set (match_operand:SI 0 "register_operand" "=r")
6399 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6403 [(set_attr "type" "load")
6404 (set_attr "length" "4")])
6407 [(set (match_operand:SI 0 "register_operand" "=r")
6408 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6409 (match_operand:SI 3 "shadd_operand" ""))
6410 (match_operand:SI 1 "register_operand" "r")))]
6412 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6413 [(set_attr "type" "binary")
6414 (set_attr "length" "4")])
6417 [(set (match_operand:DI 0 "register_operand" "=r")
6418 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6419 (match_operand:DI 3 "shadd_operand" ""))
6420 (match_operand:DI 1 "register_operand" "r")))]
6422 "shladd,l %2,%O3,%1,%0"
6423 [(set_attr "type" "binary")
6424 (set_attr "length" "4")])
6426 (define_expand "ashlsi3"
6427 [(set (match_operand:SI 0 "register_operand" "")
6428 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6429 (match_operand:SI 2 "arith32_operand" "")))]
6433 if (GET_CODE (operands[2]) != CONST_INT)
6435 rtx temp = gen_reg_rtx (SImode);
6436 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6437 if (GET_CODE (operands[1]) == CONST_INT)
6438 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6440 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6443 /* Make sure both inputs are not constants,
6444 there are no patterns for that. */
6445 operands[1] = force_reg (SImode, operands[1]);
6449 [(set (match_operand:SI 0 "register_operand" "=r")
6450 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6451 (match_operand:SI 2 "const_int_operand" "n")))]
6453 "{zdep|depw,z} %1,%P2,%L2,%0"
6454 [(set_attr "type" "shift")
6455 (set_attr "length" "4")])
6457 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6458 ; Doing it like this makes slightly better code since reload can
6459 ; replace a register with a known value in range -16..15 with a
6460 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6461 ; but since we have no more CONST_OK... characters, that is not
6463 (define_insn "zvdep32"
6464 [(set (match_operand:SI 0 "register_operand" "=r,r")
6465 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6466 (minus:SI (const_int 31)
6467 (match_operand:SI 2 "register_operand" "q,q"))))]
6470 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6471 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6472 [(set_attr "type" "shift,shift")
6473 (set_attr "length" "4,4")])
6475 (define_insn "zvdep_imm32"
6476 [(set (match_operand:SI 0 "register_operand" "=r")
6477 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6478 (minus:SI (const_int 31)
6479 (match_operand:SI 2 "register_operand" "q"))))]
6483 int x = INTVAL (operands[1]);
6484 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6485 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6486 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6488 [(set_attr "type" "shift")
6489 (set_attr "length" "4")])
6491 (define_insn "vdepi_ior"
6492 [(set (match_operand:SI 0 "register_operand" "=r")
6493 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6494 (minus:SI (const_int 31)
6495 (match_operand:SI 2 "register_operand" "q")))
6496 (match_operand:SI 3 "register_operand" "0")))]
6497 ; accept ...0001...1, can this be generalized?
6498 "exact_log2 (INTVAL (operands[1]) + 1) > 0"
6501 int x = INTVAL (operands[1]);
6502 operands[2] = GEN_INT (exact_log2 (x + 1));
6503 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6505 [(set_attr "type" "shift")
6506 (set_attr "length" "4")])
6508 (define_insn "vdepi_and"
6509 [(set (match_operand:SI 0 "register_operand" "=r")
6510 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6511 (minus:SI (const_int 31)
6512 (match_operand:SI 2 "register_operand" "q")))
6513 (match_operand:SI 3 "register_operand" "0")))]
6514 ; this can be generalized...!
6515 "INTVAL (operands[1]) == -2"
6518 int x = INTVAL (operands[1]);
6519 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6520 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6522 [(set_attr "type" "shift")
6523 (set_attr "length" "4")])
6525 (define_expand "ashldi3"
6526 [(set (match_operand:DI 0 "register_operand" "")
6527 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6528 (match_operand:DI 2 "arith32_operand" "")))]
6532 if (GET_CODE (operands[2]) != CONST_INT)
6534 rtx temp = gen_reg_rtx (DImode);
6535 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6536 if (GET_CODE (operands[1]) == CONST_INT)
6537 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6539 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6542 /* Make sure both inputs are not constants,
6543 there are no patterns for that. */
6544 operands[1] = force_reg (DImode, operands[1]);
6548 [(set (match_operand:DI 0 "register_operand" "=r")
6549 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6550 (match_operand:DI 2 "const_int_operand" "n")))]
6552 "depd,z %1,%p2,%Q2,%0"
6553 [(set_attr "type" "shift")
6554 (set_attr "length" "4")])
6556 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6557 ; Doing it like this makes slightly better code since reload can
6558 ; replace a register with a known value in range -16..15 with a
6559 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6560 ; but since we have no more CONST_OK... characters, that is not
6562 (define_insn "zvdep64"
6563 [(set (match_operand:DI 0 "register_operand" "=r,r")
6564 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6565 (minus:DI (const_int 63)
6566 (match_operand:DI 2 "register_operand" "q,q"))))]
6569 depd,z %1,%%sar,64,%0
6570 depdi,z %1,%%sar,64,%0"
6571 [(set_attr "type" "shift,shift")
6572 (set_attr "length" "4,4")])
6574 (define_insn "zvdep_imm64"
6575 [(set (match_operand:DI 0 "register_operand" "=r")
6576 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6577 (minus:DI (const_int 63)
6578 (match_operand:DI 2 "register_operand" "q"))))]
6582 int x = INTVAL (operands[1]);
6583 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6584 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6585 return \"depdi,z %1,%%sar,%2,%0\";
6587 [(set_attr "type" "shift")
6588 (set_attr "length" "4")])
6591 [(set (match_operand:DI 0 "register_operand" "=r")
6592 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6593 (minus:DI (const_int 63)
6594 (match_operand:DI 2 "register_operand" "q")))
6595 (match_operand:DI 3 "register_operand" "0")))]
6596 ; accept ...0001...1, can this be generalized?
6597 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) > 0"
6600 int x = INTVAL (operands[1]);
6601 operands[2] = GEN_INT (exact_log2 (x + 1));
6602 return \"depdi -1,%%sar,%2,%0\";
6604 [(set_attr "type" "shift")
6605 (set_attr "length" "4")])
6608 [(set (match_operand:DI 0 "register_operand" "=r")
6609 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6610 (minus:DI (const_int 63)
6611 (match_operand:DI 2 "register_operand" "q")))
6612 (match_operand:DI 3 "register_operand" "0")))]
6613 ; this can be generalized...!
6614 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6617 int x = INTVAL (operands[1]);
6618 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6619 return \"depdi 0,%%sar,%2,%0\";
6621 [(set_attr "type" "shift")
6622 (set_attr "length" "4")])
6624 (define_expand "ashrsi3"
6625 [(set (match_operand:SI 0 "register_operand" "")
6626 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6627 (match_operand:SI 2 "arith32_operand" "")))]
6631 if (GET_CODE (operands[2]) != CONST_INT)
6633 rtx temp = gen_reg_rtx (SImode);
6634 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6635 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6641 [(set (match_operand:SI 0 "register_operand" "=r")
6642 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6643 (match_operand:SI 2 "const_int_operand" "n")))]
6645 "{extrs|extrw,s} %1,%P2,%L2,%0"
6646 [(set_attr "type" "shift")
6647 (set_attr "length" "4")])
6649 (define_insn "vextrs32"
6650 [(set (match_operand:SI 0 "register_operand" "=r")
6651 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6652 (minus:SI (const_int 31)
6653 (match_operand:SI 2 "register_operand" "q"))))]
6655 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6656 [(set_attr "type" "shift")
6657 (set_attr "length" "4")])
6659 (define_expand "ashrdi3"
6660 [(set (match_operand:DI 0 "register_operand" "")
6661 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6662 (match_operand:DI 2 "arith32_operand" "")))]
6666 if (GET_CODE (operands[2]) != CONST_INT)
6668 rtx temp = gen_reg_rtx (DImode);
6669 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6670 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6676 [(set (match_operand:DI 0 "register_operand" "=r")
6677 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6678 (match_operand:DI 2 "const_int_operand" "n")))]
6680 "extrd,s %1,%p2,%Q2,%0"
6681 [(set_attr "type" "shift")
6682 (set_attr "length" "4")])
6684 (define_insn "vextrs64"
6685 [(set (match_operand:DI 0 "register_operand" "=r")
6686 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6687 (minus:DI (const_int 63)
6688 (match_operand:DI 2 "register_operand" "q"))))]
6690 "extrd,s %1,%%sar,64,%0"
6691 [(set_attr "type" "shift")
6692 (set_attr "length" "4")])
6694 (define_insn "lshrsi3"
6695 [(set (match_operand:SI 0 "register_operand" "=r,r")
6696 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6697 (match_operand:SI 2 "arith32_operand" "q,n")))]
6700 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6701 {extru|extrw,u} %1,%P2,%L2,%0"
6702 [(set_attr "type" "shift")
6703 (set_attr "length" "4")])
6705 (define_insn "lshrdi3"
6706 [(set (match_operand:DI 0 "register_operand" "=r,r")
6707 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6708 (match_operand:DI 2 "arith32_operand" "q,n")))]
6711 shrpd %%r0,%1,%%sar,%0
6712 extrd,u %1,%p2,%Q2,%0"
6713 [(set_attr "type" "shift")
6714 (set_attr "length" "4")])
6716 (define_insn "rotrsi3"
6717 [(set (match_operand:SI 0 "register_operand" "=r,r")
6718 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6719 (match_operand:SI 2 "arith32_operand" "q,n")))]
6723 if (GET_CODE (operands[2]) == CONST_INT)
6725 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6726 return \"{shd|shrpw} %1,%1,%2,%0\";
6729 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6731 [(set_attr "type" "shift")
6732 (set_attr "length" "4")])
6734 (define_expand "rotlsi3"
6735 [(set (match_operand:SI 0 "register_operand" "")
6736 (rotate:SI (match_operand:SI 1 "register_operand" "")
6737 (match_operand:SI 2 "arith32_operand" "")))]
6741 if (GET_CODE (operands[2]) != CONST_INT)
6743 rtx temp = gen_reg_rtx (SImode);
6744 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6745 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6748 /* Else expand normally. */
6752 [(set (match_operand:SI 0 "register_operand" "=r")
6753 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6754 (match_operand:SI 2 "const_int_operand" "n")))]
6758 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6759 return \"{shd|shrpw} %1,%1,%2,%0\";
6761 [(set_attr "type" "shift")
6762 (set_attr "length" "4")])
6765 [(set (match_operand:SI 0 "register_operand" "=r")
6766 (match_operator:SI 5 "plus_xor_ior_operator"
6767 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6768 (match_operand:SI 3 "const_int_operand" "n"))
6769 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6770 (match_operand:SI 4 "const_int_operand" "n"))]))]
6771 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6772 "{shd|shrpw} %1,%2,%4,%0"
6773 [(set_attr "type" "shift")
6774 (set_attr "length" "4")])
6777 [(set (match_operand:SI 0 "register_operand" "=r")
6778 (match_operator:SI 5 "plus_xor_ior_operator"
6779 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6780 (match_operand:SI 4 "const_int_operand" "n"))
6781 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6782 (match_operand:SI 3 "const_int_operand" "n"))]))]
6783 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6784 "{shd|shrpw} %1,%2,%4,%0"
6785 [(set_attr "type" "shift")
6786 (set_attr "length" "4")])
6789 [(set (match_operand:SI 0 "register_operand" "=r")
6790 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6791 (match_operand:SI 2 "const_int_operand" ""))
6792 (match_operand:SI 3 "const_int_operand" "")))]
6793 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) > 0"
6796 int cnt = INTVAL (operands[2]) & 31;
6797 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6798 operands[2] = GEN_INT (31 - cnt);
6799 return \"{zdep|depw,z} %1,%2,%3,%0\";
6801 [(set_attr "type" "shift")
6802 (set_attr "length" "4")])
6804 ;; Unconditional and other jump instructions.
6806 ;; This is used for most returns.
6807 (define_insn "return_internal"
6814 return \"bve%* (%%r2)\";
6815 return \"bv%* %%r0(%%r2)\";
6817 [(set_attr "type" "branch")
6818 (set_attr "length" "4")])
6820 ;; This is used for eh returns which bypass the return stub.
6821 (define_insn "return_external_pic"
6823 (clobber (reg:SI 1))
6825 "!TARGET_NO_SPACE_REGS
6827 && flag_pic && crtl->calls_eh_return"
6828 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6829 [(set_attr "type" "branch")
6830 (set_attr "length" "12")])
6832 (define_expand "prologue"
6835 "hppa_expand_prologue ();DONE;")
6837 (define_expand "sibcall_epilogue"
6842 hppa_expand_epilogue ();
6846 (define_expand "epilogue"
6853 /* Try to use the trivial return first. Else use the full epilogue. */
6854 if (reload_completed
6855 && !frame_pointer_needed
6856 && !df_regs_ever_live_p (2)
6857 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1))
6858 x = gen_return_internal ();
6861 hppa_expand_epilogue ();
6863 /* EH returns bypass the normal return stub. Thus, we must do an
6864 interspace branch to return from functions that call eh_return.
6865 This is only a problem for returns from shared code on ports
6866 using space registers. */
6867 if (!TARGET_NO_SPACE_REGS
6869 && flag_pic && crtl->calls_eh_return)
6870 x = gen_return_external_pic ();
6872 x = gen_return_internal ();
6878 ; Used by hppa_profile_hook to load the starting address of the current
6879 ; function; operand 1 contains the address of the label in operand 3
6880 (define_insn "load_offset_label_address"
6881 [(set (match_operand:SI 0 "register_operand" "=r")
6882 (plus:SI (match_operand:SI 1 "register_operand" "r")
6883 (minus:SI (match_operand:SI 2 "" "")
6884 (label_ref:SI (match_operand 3 "" "")))))]
6887 [(set_attr "type" "multi")
6888 (set_attr "length" "4")])
6890 ; Output a code label and load its address.
6891 (define_insn "lcla1"
6892 [(set (match_operand:SI 0 "register_operand" "=r")
6893 (label_ref:SI (match_operand 1 "" "")))
6898 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6899 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6900 CODE_LABEL_NUMBER (operands[1]));
6903 [(set_attr "type" "multi")
6904 (set_attr "length" "8")])
6906 (define_insn "lcla2"
6907 [(set (match_operand:SI 0 "register_operand" "=r")
6908 (label_ref:SI (match_operand 1 "" "")))
6913 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6914 CODE_LABEL_NUMBER (operands[1]));
6917 [(set_attr "type" "move")
6918 (set_attr "length" "4")])
6920 (define_insn "blockage"
6921 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
6924 [(set_attr "length" "0")])
6927 [(set (pc) (label_ref (match_operand 0 "" "")))]
6931 /* An unconditional branch which can reach its target. */
6932 if (get_attr_length (insn) < 16)
6935 return output_lbranch (operands[0], insn, 1);
6937 [(set_attr "type" "uncond_branch")
6938 (set_attr "pa_combine_type" "uncond_branch")
6939 (set (attr "length")
6940 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
6941 (if_then_else (lt (abs (minus (match_dup 0)
6942 (plus (pc) (const_int 8))))
6943 (const_int MAX_12BIT_OFFSET))
6946 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
6947 (const_int MAX_17BIT_OFFSET))
6949 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
6951 (eq (symbol_ref "flag_pic") (const_int 0))
6955 ;;; Hope this is only within a function...
6956 (define_insn "indirect_jump"
6957 [(set (pc) (match_operand 0 "register_operand" "r"))]
6958 "GET_MODE (operands[0]) == word_mode"
6960 [(set_attr "type" "branch")
6961 (set_attr "length" "4")])
6963 ;;; An indirect jump can be optimized to a direct jump. GAS for the
6964 ;;; SOM target doesn't allow branching to a label inside a function.
6965 ;;; We also don't correctly compute branch distances for labels
6966 ;;; outside the current function. Thus, we use an indirect jump can't
6967 ;;; be optimized to a direct jump for all targets. We assume that
6968 ;;; the branch target is in the same space (i.e., nested function
6969 ;;; jumping to a label in an outer function in the same translation
6971 (define_expand "nonlocal_goto"
6972 [(use (match_operand 0 "general_operand" ""))
6973 (use (match_operand 1 "general_operand" ""))
6974 (use (match_operand 2 "general_operand" ""))
6975 (use (match_operand 3 "general_operand" ""))]
6978 rtx lab = operands[1];
6979 rtx stack = operands[2];
6980 rtx fp = operands[3];
6982 lab = copy_to_reg (lab);
6984 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
6985 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
6987 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
6988 instead of the hard_frame_pointer_rtx in the save area. As a
6989 result, an extra instruction is needed to adjust for the offset
6990 of the virtual stack variables and the frame pointer. */
6991 if (GET_CODE (fp) != REG)
6992 fp = force_reg (Pmode, fp);
6993 emit_move_insn (virtual_stack_vars_rtx, fp);
6995 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6997 emit_use (hard_frame_pointer_rtx);
6998 emit_use (stack_pointer_rtx);
7000 /* Nonlocal goto jumps are only used between functions in the same
7001 translation unit. Thus, we can avoid the extra overhead of an
7003 emit_jump_insn (gen_indirect_goto (lab));
7008 (define_insn "indirect_goto"
7009 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
7010 "GET_MODE (operands[0]) == word_mode"
7012 [(set_attr "type" "branch")
7013 (set_attr "length" "4")])
7015 ;;; This jump is used in branch tables where the insn length is fixed.
7016 ;;; The length of this insn is adjusted if the delay slot is not filled.
7017 (define_insn "short_jump"
7018 [(set (pc) (label_ref (match_operand 0 "" "")))
7022 [(set_attr "type" "btable_branch")
7023 (set_attr "length" "4")])
7025 ;; Subroutines of "casesi".
7026 ;; operand 0 is index
7027 ;; operand 1 is the minimum bound
7028 ;; operand 2 is the maximum bound - minimum bound + 1
7029 ;; operand 3 is CODE_LABEL for the table;
7030 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7032 (define_expand "casesi"
7033 [(match_operand:SI 0 "general_operand" "")
7034 (match_operand:SI 1 "const_int_operand" "")
7035 (match_operand:SI 2 "const_int_operand" "")
7036 (match_operand 3 "" "")
7037 (match_operand 4 "" "")]
7041 if (GET_CODE (operands[0]) != REG)
7042 operands[0] = force_reg (SImode, operands[0]);
7044 if (operands[1] != const0_rtx)
7046 rtx index = gen_reg_rtx (SImode);
7048 operands[1] = GEN_INT (-INTVAL (operands[1]));
7049 if (!INT_14_BITS (operands[1]))
7050 operands[1] = force_reg (SImode, operands[1]);
7051 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
7052 operands[0] = index;
7055 /* In 64bit mode we must make sure to wipe the upper bits of the register
7056 just in case the addition overflowed or we had random bits in the
7057 high part of the register. */
7060 rtx index = gen_reg_rtx (DImode);
7062 emit_insn (gen_extendsidi2 (index, operands[0]));
7063 operands[0] = gen_rtx_SUBREG (SImode, index, 4);
7066 if (!INT_5_BITS (operands[2]))
7067 operands[2] = force_reg (SImode, operands[2]);
7069 /* This branch prevents us finding an insn for the delay slot of the
7070 following vectored branch. It might be possible to use the delay
7071 slot if an index value of -1 was used to transfer to the out-of-range
7072 label. In order to do this, we would have to output the -1 vector
7073 element after the delay insn. The casesi output code would have to
7074 check if the casesi insn is in a delay branch sequence and output
7075 the delay insn if one is found. If this was done, then it might
7076 then be worthwhile to split the casesi patterns to improve scheduling.
7077 However, it's not clear that all this extra complexity is worth
7080 rtx test = gen_rtx_GTU (VOIDmode, operands[0], operands[2]);
7081 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
7084 if (TARGET_BIG_SWITCH)
7087 emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
7089 emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
7091 emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
7094 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
7098 ;;; The rtl for this pattern doesn't accurately describe what the insn
7099 ;;; actually does, particularly when case-vector elements are exploded
7100 ;;; in pa_reorg. However, the initial SET in these patterns must show
7101 ;;; the connection of the insn to the following jump table.
7102 (define_insn "casesi0"
7103 [(set (pc) (mem:SI (plus:SI
7104 (mult:SI (match_operand:SI 0 "register_operand" "r")
7106 (label_ref (match_operand 1 "" "")))))]
7108 "blr,n %0,%%r0\;nop"
7109 [(set_attr "type" "multi")
7110 (set_attr "length" "8")])
7112 ;;; 32-bit code, absolute branch table.
7113 (define_insn "casesi32"
7114 [(set (pc) (mem:SI (plus:SI
7115 (mult:SI (match_operand:SI 0 "register_operand" "r")
7117 (label_ref (match_operand 1 "" "")))))
7118 (clobber (match_scratch:SI 2 "=&r"))]
7120 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
7121 [(set_attr "type" "multi")
7122 (set_attr "length" "16")])
7124 ;;; 32-bit code, relative branch table.
7125 (define_insn "casesi32p"
7126 [(set (pc) (mem:SI (plus:SI
7127 (mult:SI (match_operand:SI 0 "register_operand" "r")
7129 (label_ref (match_operand 1 "" "")))))
7130 (clobber (match_scratch:SI 2 "=&r"))
7131 (clobber (match_scratch:SI 3 "=&r"))]
7133 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {%l1-.|%l1+4-.}(%2),%2\;\
7134 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7135 [(set_attr "type" "multi")
7136 (set (attr "length")
7137 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
7141 ;;; 64-bit code, 32-bit relative branch table.
7142 (define_insn "casesi64p"
7143 [(set (pc) (mem:DI (plus:DI
7144 (mult:DI (sign_extend:DI
7145 (match_operand:SI 0 "register_operand" "r"))
7147 (label_ref (match_operand 1 "" "")))))
7148 (clobber (match_scratch:DI 2 "=&r"))
7149 (clobber (match_scratch:DI 3 "=&r"))]
7151 "mfia %2\;ldo %l1+4-.(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7152 add,l %2,%3,%3\;bv,n %%r0(%3)"
7153 [(set_attr "type" "multi")
7154 (set_attr "length" "24")])
7158 ;;- jump to subroutine
7160 (define_expand "call"
7161 [(parallel [(call (match_operand:SI 0 "" "")
7162 (match_operand 1 "" ""))
7163 (clobber (reg:SI 2))])]
7168 rtx nb = operands[1];
7170 if (TARGET_PORTABLE_RUNTIME)
7171 op = force_reg (SImode, XEXP (operands[0], 0));
7173 op = XEXP (operands[0], 0);
7177 if (!virtuals_instantiated)
7178 emit_move_insn (arg_pointer_rtx,
7179 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7183 /* The loop pass can generate new libcalls after the virtual
7184 registers are instantiated when fpregs are disabled because
7185 the only method that we have for doing DImode multiplication
7186 is with a libcall. This could be trouble if we haven't
7187 allocated enough space for the outgoing arguments. */
7188 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7190 emit_move_insn (arg_pointer_rtx,
7191 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7192 GEN_INT (STACK_POINTER_OFFSET + 64)));
7196 /* Use two different patterns for calls to explicitly named functions
7197 and calls through function pointers. This is necessary as these two
7198 types of calls use different calling conventions, and CSE might try
7199 to change the named call into an indirect call in some cases (using
7200 two patterns keeps CSE from performing this optimization).
7202 We now use even more call patterns as there was a subtle bug in
7203 attempting to restore the pic register after a call using a simple
7204 move insn. During reload, a instruction involving a pseudo register
7205 with no explicit dependence on the PIC register can be converted
7206 to an equivalent load from memory using the PIC register. If we
7207 emit a simple move to restore the PIC register in the initial rtl
7208 generation, then it can potentially be repositioned during scheduling.
7209 and an instruction that eventually uses the PIC register may end up
7210 between the call and the PIC register restore.
7212 This only worked because there is a post call group of instructions
7213 that are scheduled with the call. These instructions are included
7214 in the same basic block as the call. However, calls can throw in
7215 C++ code and a basic block has to terminate at the call if the call
7216 can throw. This results in the PIC register restore being scheduled
7217 independently from the call. So, we now hide the save and restore
7218 of the PIC register in the call pattern until after reload. Then,
7219 we split the moves out. A small side benefit is that we now don't
7220 need to have a use of the PIC register in the return pattern and
7221 the final save/restore operation is not needed.
7223 I elected to just use register %r4 in the PIC patterns instead
7224 of trying to force hppa_pic_save_rtx () to a callee saved register.
7225 This might have required a new register class and constraint. It
7226 was also simpler to just handle the restore from a register than a
7230 rtx r4 = gen_rtx_REG (word_mode, 4);
7231 if (GET_CODE (op) == SYMBOL_REF)
7232 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb, r4));
7235 op = force_reg (word_mode, op);
7236 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb, r4));
7241 if (GET_CODE (op) == SYMBOL_REF)
7245 rtx r4 = gen_rtx_REG (word_mode, 4);
7246 call_insn = emit_call_insn (gen_call_symref_pic (op, nb, r4));
7249 call_insn = emit_call_insn (gen_call_symref (op, nb));
7253 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7254 emit_move_insn (tmpreg, force_reg (word_mode, op));
7257 rtx r4 = gen_rtx_REG (word_mode, 4);
7258 call_insn = emit_call_insn (gen_call_reg_pic (nb, r4));
7261 call_insn = emit_call_insn (gen_call_reg (nb));
7268 ;; We use function calls to set the attribute length of calls and millicode
7269 ;; calls. This is necessary because of the large variety of call sequences.
7270 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7271 ;; we need the same calculation in several places, maintenance becomes a
7274 ;; However, this has a subtle impact on branch shortening. When the
7275 ;; expression used to set the length attribute of an instruction depends
7276 ;; on a relative address (e.g., pc or a branch address), genattrtab
7277 ;; notes that the insn's length is variable, and attempts to determine a
7278 ;; worst-case default length and code to compute an insn's current length.
7280 ;; The use of a function call hides the variable dependence of our calls
7281 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7282 ;; as variable and it only generates code for the default case using our
7283 ;; function call. Because of this, calls and millicode calls have a fixed
7284 ;; length in the branch shortening pass, and some branches will use a longer
7285 ;; code sequence than necessary. However, the length of any given call
7286 ;; will still reflect its final code location and it may be shorter than
7287 ;; the initial length estimate.
7289 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7290 ;; in the set. However, when genattrtab hits a function call in its attempt
7291 ;; to compute the default length, it marks the result as unknown and sets
7292 ;; the default result to MAX_INT ;-( One possible fix that would allow
7293 ;; calls to participate in branch shortening would be to make the call to
7294 ;; insn_default_length a target option. Then, we could massage unknown
7295 ;; results. Another fix might be to change genattrtab so that it just does
7296 ;; the call in the variable case as it already does for the fixed case.
7298 (define_insn "call_symref"
7299 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7300 (match_operand 1 "" "i"))
7301 (clobber (reg:SI 1))
7302 (clobber (reg:SI 2))
7303 (use (const_int 0))]
7304 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7307 output_arg_descriptor (insn);
7308 return output_call (insn, operands[0], 0);
7310 [(set_attr "type" "call")
7311 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7313 (define_insn "call_symref_pic"
7314 [(set (match_operand:SI 2 "register_operand" "=&r") (reg:SI 19))
7315 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7316 (match_operand 1 "" "i"))
7317 (clobber (reg:SI 1))
7318 (clobber (reg:SI 2))
7321 (use (const_int 0))]
7322 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7325 ;; Split out the PIC register save and restore after reload. As the
7326 ;; split is done after reload, there are some situations in which we
7327 ;; unnecessarily save and restore %r4. This happens when there is a
7328 ;; single call and the PIC register is not used after the call.
7330 ;; The split has to be done since call_from_call_insn () can't handle
7331 ;; the pattern as is. Noreturn calls are special because they have to
7332 ;; terminate the basic block. The split has to contain more than one
7335 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
7336 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7337 (match_operand 1 "" ""))
7338 (clobber (reg:SI 1))
7339 (clobber (reg:SI 2))
7342 (use (const_int 0))])]
7343 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7344 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7345 [(set (match_dup 2) (reg:SI 19))
7346 (parallel [(call (mem:SI (match_dup 0))
7348 (clobber (reg:SI 1))
7349 (clobber (reg:SI 2))
7351 (use (const_int 0))])]
7355 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
7356 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7357 (match_operand 1 "" ""))
7358 (clobber (reg:SI 1))
7359 (clobber (reg:SI 2))
7362 (use (const_int 0))])]
7363 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7364 [(set (match_dup 2) (reg:SI 19))
7365 (parallel [(call (mem:SI (match_dup 0))
7367 (clobber (reg:SI 1))
7368 (clobber (reg:SI 2))
7370 (use (const_int 0))])
7371 (set (reg:SI 19) (match_dup 2))]
7374 (define_insn "*call_symref_pic_post_reload"
7375 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7376 (match_operand 1 "" "i"))
7377 (clobber (reg:SI 1))
7378 (clobber (reg:SI 2))
7380 (use (const_int 0))]
7381 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7384 output_arg_descriptor (insn);
7385 return output_call (insn, operands[0], 0);
7387 [(set_attr "type" "call")
7388 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7390 ;; This pattern is split if it is necessary to save and restore the
7392 (define_insn "call_symref_64bit"
7393 [(set (match_operand:DI 2 "register_operand" "=&r") (reg:DI 27))
7394 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7395 (match_operand 1 "" "i"))
7396 (clobber (reg:DI 1))
7397 (clobber (reg:DI 2))
7401 (use (const_int 0))]
7405 ;; Split out the PIC register save and restore after reload. As the
7406 ;; split is done after reload, there are some situations in which we
7407 ;; unnecessarily save and restore %r4. This happens when there is a
7408 ;; single call and the PIC register is not used after the call.
7410 ;; The split has to be done since call_from_call_insn () can't handle
7411 ;; the pattern as is. Noreturn calls are special because they have to
7412 ;; terminate the basic block. The split has to contain more than one
7415 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7416 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7417 (match_operand 1 "" ""))
7418 (clobber (reg:DI 1))
7419 (clobber (reg:DI 2))
7423 (use (const_int 0))])]
7424 "TARGET_64BIT && reload_completed
7425 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7426 [(set (match_dup 2) (reg:DI 27))
7427 (parallel [(call (mem:SI (match_dup 0))
7429 (clobber (reg:DI 1))
7430 (clobber (reg:DI 2))
7433 (use (const_int 0))])]
7437 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7438 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7439 (match_operand 1 "" ""))
7440 (clobber (reg:DI 1))
7441 (clobber (reg:DI 2))
7445 (use (const_int 0))])]
7446 "TARGET_64BIT && reload_completed"
7447 [(set (match_dup 2) (reg:DI 27))
7448 (parallel [(call (mem:SI (match_dup 0))
7450 (clobber (reg:DI 1))
7451 (clobber (reg:DI 2))
7454 (use (const_int 0))])
7455 (set (reg:DI 27) (match_dup 2))]
7458 (define_insn "*call_symref_64bit_post_reload"
7459 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7460 (match_operand 1 "" "i"))
7461 (clobber (reg:DI 1))
7462 (clobber (reg:DI 2))
7465 (use (const_int 0))]
7469 output_arg_descriptor (insn);
7470 return output_call (insn, operands[0], 0);
7472 [(set_attr "type" "call")
7473 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7475 (define_insn "call_reg"
7476 [(call (mem:SI (reg:SI 22))
7477 (match_operand 0 "" "i"))
7478 (clobber (reg:SI 1))
7479 (clobber (reg:SI 2))
7480 (use (const_int 1))]
7484 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7486 [(set_attr "type" "dyncall")
7487 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7489 ;; This pattern is split if it is necessary to save and restore the
7491 (define_insn "call_reg_pic"
7492 [(set (match_operand:SI 1 "register_operand" "=&r") (reg:SI 19))
7493 (call (mem:SI (reg:SI 22))
7494 (match_operand 0 "" "i"))
7495 (clobber (reg:SI 1))
7496 (clobber (reg:SI 2))
7499 (use (const_int 1))]
7503 ;; Split out the PIC register save and restore after reload. As the
7504 ;; split is done after reload, there are some situations in which we
7505 ;; unnecessarily save and restore %r4. This happens when there is a
7506 ;; single call and the PIC register is not used after the call.
7508 ;; The split has to be done since call_from_call_insn () can't handle
7509 ;; the pattern as is. Noreturn calls are special because they have to
7510 ;; terminate the basic block. The split has to contain more than one
7513 [(parallel [(set (match_operand:SI 1 "register_operand" "") (reg:SI 19))
7514 (call (mem:SI (reg:SI 22))
7515 (match_operand 0 "" ""))
7516 (clobber (reg:SI 1))
7517 (clobber (reg:SI 2))
7520 (use (const_int 1))])]
7521 "!TARGET_64BIT && reload_completed
7522 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7523 [(set (match_dup 1) (reg:SI 19))
7524 (parallel [(call (mem:SI (reg:SI 22))
7526 (clobber (reg:SI 1))
7527 (clobber (reg:SI 2))
7529 (use (const_int 1))])]
7533 [(parallel [(set (match_operand:SI 1 "register_operand" "") (reg:SI 19))
7534 (call (mem:SI (reg:SI 22))
7535 (match_operand 0 "" ""))
7536 (clobber (reg:SI 1))
7537 (clobber (reg:SI 2))
7540 (use (const_int 1))])]
7541 "!TARGET_64BIT && reload_completed"
7542 [(set (match_dup 1) (reg:SI 19))
7543 (parallel [(call (mem:SI (reg:SI 22))
7545 (clobber (reg:SI 1))
7546 (clobber (reg:SI 2))
7548 (use (const_int 1))])
7549 (set (reg:SI 19) (match_dup 1))]
7552 (define_insn "*call_reg_pic_post_reload"
7553 [(call (mem:SI (reg:SI 22))
7554 (match_operand 0 "" "i"))
7555 (clobber (reg:SI 1))
7556 (clobber (reg:SI 2))
7558 (use (const_int 1))]
7562 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7564 [(set_attr "type" "dyncall")
7565 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7567 ;; This pattern is split if it is necessary to save and restore the
7569 (define_insn "call_reg_64bit"
7570 [(set (match_operand:DI 2 "register_operand" "=&r") (reg:DI 27))
7571 (call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7572 (match_operand 1 "" "i"))
7573 (clobber (reg:DI 1))
7574 (clobber (reg:DI 2))
7578 (use (const_int 1))]
7582 ;; Split out the PIC register save and restore after reload. As the
7583 ;; split is done after reload, there are some situations in which we
7584 ;; unnecessarily save and restore %r4. This happens when there is a
7585 ;; single call and the PIC register is not used after the call.
7587 ;; The split has to be done since call_from_call_insn () can't handle
7588 ;; the pattern as is. Noreturn calls are special because they have to
7589 ;; terminate the basic block. The split has to contain more than one
7592 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7593 (call (mem:SI (match_operand 0 "register_operand" ""))
7594 (match_operand 1 "" ""))
7595 (clobber (reg:DI 1))
7596 (clobber (reg:DI 2))
7600 (use (const_int 1))])]
7601 "TARGET_64BIT && reload_completed
7602 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7603 [(set (match_dup 2) (reg:DI 27))
7604 (parallel [(call (mem:SI (match_dup 0))
7606 (clobber (reg:DI 1))
7607 (clobber (reg:DI 2))
7610 (use (const_int 1))])]
7614 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7615 (call (mem:SI (match_operand 0 "register_operand" ""))
7616 (match_operand 1 "" ""))
7617 (clobber (reg:DI 1))
7618 (clobber (reg:DI 2))
7622 (use (const_int 1))])]
7623 "TARGET_64BIT && reload_completed"
7624 [(set (match_dup 2) (reg:DI 27))
7625 (parallel [(call (mem:SI (match_dup 0))
7627 (clobber (reg:DI 1))
7628 (clobber (reg:DI 2))
7631 (use (const_int 1))])
7632 (set (reg:DI 27) (match_dup 2))]
7635 (define_insn "*call_reg_64bit_post_reload"
7636 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7637 (match_operand 1 "" "i"))
7638 (clobber (reg:DI 1))
7639 (clobber (reg:DI 2))
7642 (use (const_int 1))]
7646 return output_indirect_call (insn, operands[0]);
7648 [(set_attr "type" "dyncall")
7649 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7651 (define_expand "call_value"
7652 [(parallel [(set (match_operand 0 "" "")
7653 (call (match_operand:SI 1 "" "")
7654 (match_operand 2 "" "")))
7655 (clobber (reg:SI 2))])]
7660 rtx dst = operands[0];
7661 rtx nb = operands[2];
7663 if (TARGET_PORTABLE_RUNTIME)
7664 op = force_reg (SImode, XEXP (operands[1], 0));
7666 op = XEXP (operands[1], 0);
7670 if (!virtuals_instantiated)
7671 emit_move_insn (arg_pointer_rtx,
7672 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7676 /* The loop pass can generate new libcalls after the virtual
7677 registers are instantiated when fpregs are disabled because
7678 the only method that we have for doing DImode multiplication
7679 is with a libcall. This could be trouble if we haven't
7680 allocated enough space for the outgoing arguments. */
7681 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7683 emit_move_insn (arg_pointer_rtx,
7684 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7685 GEN_INT (STACK_POINTER_OFFSET + 64)));
7689 /* Use two different patterns for calls to explicitly named functions
7690 and calls through function pointers. This is necessary as these two
7691 types of calls use different calling conventions, and CSE might try
7692 to change the named call into an indirect call in some cases (using
7693 two patterns keeps CSE from performing this optimization).
7695 We now use even more call patterns as there was a subtle bug in
7696 attempting to restore the pic register after a call using a simple
7697 move insn. During reload, a instruction involving a pseudo register
7698 with no explicit dependence on the PIC register can be converted
7699 to an equivalent load from memory using the PIC register. If we
7700 emit a simple move to restore the PIC register in the initial rtl
7701 generation, then it can potentially be repositioned during scheduling.
7702 and an instruction that eventually uses the PIC register may end up
7703 between the call and the PIC register restore.
7705 This only worked because there is a post call group of instructions
7706 that are scheduled with the call. These instructions are included
7707 in the same basic block as the call. However, calls can throw in
7708 C++ code and a basic block has to terminate at the call if the call
7709 can throw. This results in the PIC register restore being scheduled
7710 independently from the call. So, we now hide the save and restore
7711 of the PIC register in the call pattern until after reload. Then,
7712 we split the moves out. A small side benefit is that we now don't
7713 need to have a use of the PIC register in the return pattern and
7714 the final save/restore operation is not needed.
7716 I elected to just use register %r4 in the PIC patterns instead
7717 of trying to force hppa_pic_save_rtx () to a callee saved register.
7718 This might have required a new register class and constraint. It
7719 was also simpler to just handle the restore from a register than a
7723 rtx r4 = gen_rtx_REG (word_mode, 4);
7724 if (GET_CODE (op) == SYMBOL_REF)
7726 = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb, r4));
7729 op = force_reg (word_mode, op);
7731 = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb, r4));
7736 if (GET_CODE (op) == SYMBOL_REF)
7740 rtx r4 = gen_rtx_REG (word_mode, 4);
7742 = emit_call_insn (gen_call_val_symref_pic (dst, op, nb, r4));
7745 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
7749 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7750 emit_move_insn (tmpreg, force_reg (word_mode, op));
7753 rtx r4 = gen_rtx_REG (word_mode, 4);
7754 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb, r4));
7757 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
7764 (define_insn "call_val_symref"
7765 [(set (match_operand 0 "" "")
7766 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7767 (match_operand 2 "" "i")))
7768 (clobber (reg:SI 1))
7769 (clobber (reg:SI 2))
7770 (use (const_int 0))]
7771 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7774 output_arg_descriptor (insn);
7775 return output_call (insn, operands[1], 0);
7777 [(set_attr "type" "call")
7778 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7780 (define_insn "call_val_symref_pic"
7781 [(set (match_operand:SI 3 "register_operand" "=&r") (reg:SI 19))
7782 (set (match_operand 0 "" "")
7783 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7784 (match_operand 2 "" "i")))
7785 (clobber (reg:SI 1))
7786 (clobber (reg:SI 2))
7789 (use (const_int 0))]
7790 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7793 ;; Split out the PIC register save and restore after reload. As the
7794 ;; split is done after reload, there are some situations in which we
7795 ;; unnecessarily save and restore %r4. This happens when there is a
7796 ;; single call and the PIC register is not used after the call.
7798 ;; The split has to be done since call_from_call_insn () can't handle
7799 ;; the pattern as is. Noreturn calls are special because they have to
7800 ;; terminate the basic block. The split has to contain more than one
7803 [(parallel [(set (match_operand:SI 3 "register_operand" "") (reg:SI 19))
7804 (set (match_operand 0 "" "")
7805 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7806 (match_operand 2 "" "")))
7807 (clobber (reg:SI 1))
7808 (clobber (reg:SI 2))
7811 (use (const_int 0))])]
7812 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7813 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7814 [(set (match_dup 3) (reg:SI 19))
7815 (parallel [(set (match_dup 0)
7816 (call (mem:SI (match_dup 1))
7818 (clobber (reg:SI 1))
7819 (clobber (reg:SI 2))
7821 (use (const_int 0))])]
7825 [(parallel [(set (match_operand:SI 3 "register_operand" "") (reg:SI 19))
7826 (set (match_operand 0 "" "")
7827 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7828 (match_operand 2 "" "")))
7829 (clobber (reg:SI 1))
7830 (clobber (reg:SI 2))
7833 (use (const_int 0))])]
7834 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7835 [(set (match_dup 3) (reg:SI 19))
7836 (parallel [(set (match_dup 0)
7837 (call (mem:SI (match_dup 1))
7839 (clobber (reg:SI 1))
7840 (clobber (reg:SI 2))
7842 (use (const_int 0))])
7843 (set (reg:SI 19) (match_dup 3))]
7846 (define_insn "*call_val_symref_pic_post_reload"
7847 [(set (match_operand 0 "" "")
7848 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7849 (match_operand 2 "" "i")))
7850 (clobber (reg:SI 1))
7851 (clobber (reg:SI 2))
7853 (use (const_int 0))]
7854 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7857 output_arg_descriptor (insn);
7858 return output_call (insn, operands[1], 0);
7860 [(set_attr "type" "call")
7861 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7863 ;; This pattern is split if it is necessary to save and restore the
7865 (define_insn "call_val_symref_64bit"
7866 [(set (match_operand:DI 3 "register_operand" "=&r") (reg:DI 27))
7867 (set (match_operand 0 "" "")
7868 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7869 (match_operand 2 "" "i")))
7870 (clobber (reg:DI 1))
7871 (clobber (reg:DI 2))
7875 (use (const_int 0))]
7879 ;; Split out the PIC register save and restore after reload. As the
7880 ;; split is done after reload, there are some situations in which we
7881 ;; unnecessarily save and restore %r4. This happens when there is a
7882 ;; single call and the PIC register is not used after the call.
7884 ;; The split has to be done since call_from_call_insn () can't handle
7885 ;; the pattern as is. Noreturn calls are special because they have to
7886 ;; terminate the basic block. The split has to contain more than one
7889 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
7890 (set (match_operand 0 "" "")
7891 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7892 (match_operand 2 "" "")))
7893 (clobber (reg:DI 1))
7894 (clobber (reg:DI 2))
7898 (use (const_int 0))])]
7899 "TARGET_64BIT && reload_completed
7900 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7901 [(set (match_dup 3) (reg:DI 27))
7902 (parallel [(set (match_dup 0)
7903 (call (mem:SI (match_dup 1))
7905 (clobber (reg:DI 1))
7906 (clobber (reg:DI 2))
7909 (use (const_int 0))])]
7913 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
7914 (set (match_operand 0 "" "")
7915 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7916 (match_operand 2 "" "")))
7917 (clobber (reg:DI 1))
7918 (clobber (reg:DI 2))
7922 (use (const_int 0))])]
7923 "TARGET_64BIT && reload_completed"
7924 [(set (match_dup 3) (reg:DI 27))
7925 (parallel [(set (match_dup 0)
7926 (call (mem:SI (match_dup 1))
7928 (clobber (reg:DI 1))
7929 (clobber (reg:DI 2))
7932 (use (const_int 0))])
7933 (set (reg:DI 27) (match_dup 3))]
7936 (define_insn "*call_val_symref_64bit_post_reload"
7937 [(set (match_operand 0 "" "")
7938 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7939 (match_operand 2 "" "i")))
7940 (clobber (reg:DI 1))
7941 (clobber (reg:DI 2))
7944 (use (const_int 0))]
7948 output_arg_descriptor (insn);
7949 return output_call (insn, operands[1], 0);
7951 [(set_attr "type" "call")
7952 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7954 (define_insn "call_val_reg"
7955 [(set (match_operand 0 "" "")
7956 (call (mem:SI (reg:SI 22))
7957 (match_operand 1 "" "i")))
7958 (clobber (reg:SI 1))
7959 (clobber (reg:SI 2))
7960 (use (const_int 1))]
7964 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7966 [(set_attr "type" "dyncall")
7967 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7969 ;; This pattern is split if it is necessary to save and restore the
7971 (define_insn "call_val_reg_pic"
7972 [(set (match_operand:SI 2 "register_operand" "=&r") (reg:SI 19))
7973 (set (match_operand 0 "" "")
7974 (call (mem:SI (reg:SI 22))
7975 (match_operand 1 "" "i")))
7976 (clobber (reg:SI 1))
7977 (clobber (reg:SI 2))
7980 (use (const_int 1))]
7984 ;; Split out the PIC register save and restore after reload. As the
7985 ;; split is done after reload, there are some situations in which we
7986 ;; unnecessarily save and restore %r4. This happens when there is a
7987 ;; single call and the PIC register is not used after the call.
7989 ;; The split has to be done since call_from_call_insn () can't handle
7990 ;; the pattern as is. Noreturn calls are special because they have to
7991 ;; terminate the basic block. The split has to contain more than one
7994 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
7995 (set (match_operand 0 "" "")
7996 (call (mem:SI (reg:SI 22))
7997 (match_operand 1 "" "")))
7998 (clobber (reg:SI 1))
7999 (clobber (reg:SI 2))
8002 (use (const_int 1))])]
8003 "!TARGET_64BIT && reload_completed
8004 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8005 [(set (match_dup 2) (reg:SI 19))
8006 (parallel [(set (match_dup 0)
8007 (call (mem:SI (reg:SI 22))
8009 (clobber (reg:SI 1))
8010 (clobber (reg:SI 2))
8012 (use (const_int 1))])]
8016 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
8017 (set (match_operand 0 "" "")
8018 (call (mem:SI (reg:SI 22))
8019 (match_operand 1 "" "")))
8020 (clobber (reg:SI 1))
8021 (clobber (reg:SI 2))
8024 (use (const_int 1))])]
8025 "!TARGET_64BIT && reload_completed"
8026 [(set (match_dup 2) (reg:SI 19))
8027 (parallel [(set (match_dup 0)
8028 (call (mem:SI (reg:SI 22))
8030 (clobber (reg:SI 1))
8031 (clobber (reg:SI 2))
8033 (use (const_int 1))])
8034 (set (reg:SI 19) (match_dup 2))]
8037 (define_insn "*call_val_reg_pic_post_reload"
8038 [(set (match_operand 0 "" "")
8039 (call (mem:SI (reg:SI 22))
8040 (match_operand 1 "" "i")))
8041 (clobber (reg:SI 1))
8042 (clobber (reg:SI 2))
8044 (use (const_int 1))]
8048 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8050 [(set_attr "type" "dyncall")
8051 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8053 ;; This pattern is split if it is necessary to save and restore the
8055 (define_insn "call_val_reg_64bit"
8056 [(set (match_operand:DI 3 "register_operand" "=&r") (reg:DI 27))
8057 (set (match_operand 0 "" "")
8058 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8059 (match_operand 2 "" "i")))
8060 (clobber (reg:DI 1))
8061 (clobber (reg:DI 2))
8065 (use (const_int 1))]
8069 ;; Split out the PIC register save and restore after reload. As the
8070 ;; split is done after reload, there are some situations in which we
8071 ;; unnecessarily save and restore %r4. This happens when there is a
8072 ;; single call and the PIC register is not used after the call.
8074 ;; The split has to be done since call_from_call_insn () can't handle
8075 ;; the pattern as is. Noreturn calls are special because they have to
8076 ;; terminate the basic block. The split has to contain more than one
8079 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
8080 (set (match_operand 0 "" "")
8081 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8082 (match_operand 2 "" "")))
8083 (clobber (reg:DI 1))
8084 (clobber (reg:DI 2))
8088 (use (const_int 1))])]
8089 "TARGET_64BIT && reload_completed
8090 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8091 [(set (match_dup 3) (reg:DI 27))
8092 (parallel [(set (match_dup 0)
8093 (call (mem:SI (match_dup 1))
8095 (clobber (reg:DI 1))
8096 (clobber (reg:DI 2))
8099 (use (const_int 1))])]
8103 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
8104 (set (match_operand 0 "" "")
8105 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8106 (match_operand 2 "" "")))
8107 (clobber (reg:DI 1))
8108 (clobber (reg:DI 2))
8112 (use (const_int 1))])]
8113 "TARGET_64BIT && reload_completed"
8114 [(set (match_dup 3) (reg:DI 27))
8115 (parallel [(set (match_dup 0)
8116 (call (mem:SI (match_dup 1))
8118 (clobber (reg:DI 1))
8119 (clobber (reg:DI 2))
8122 (use (const_int 1))])
8123 (set (reg:DI 27) (match_dup 3))]
8126 (define_insn "*call_val_reg_64bit_post_reload"
8127 [(set (match_operand 0 "" "")
8128 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8129 (match_operand 2 "" "i")))
8130 (clobber (reg:DI 1))
8131 (clobber (reg:DI 2))
8134 (use (const_int 1))]
8138 return output_indirect_call (insn, operands[1]);
8140 [(set_attr "type" "dyncall")
8141 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8143 ;; Call subroutine returning any type.
8145 (define_expand "untyped_call"
8146 [(parallel [(call (match_operand 0 "" "")
8148 (match_operand 1 "" "")
8149 (match_operand 2 "" "")])]
8155 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
8157 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8159 rtx set = XVECEXP (operands[2], 0, i);
8160 emit_move_insn (SET_DEST (set), SET_SRC (set));
8163 /* The optimizer does not know that the call sets the function value
8164 registers we stored in the result block. We avoid problems by
8165 claiming that all hard registers are used and clobbered at this
8167 emit_insn (gen_blockage ());
8172 (define_expand "sibcall"
8173 [(call (match_operand:SI 0 "" "")
8174 (match_operand 1 "" ""))]
8175 "!TARGET_PORTABLE_RUNTIME"
8179 rtx nb = operands[1];
8181 op = XEXP (operands[0], 0);
8185 if (!virtuals_instantiated)
8186 emit_move_insn (arg_pointer_rtx,
8187 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8191 /* The loop pass can generate new libcalls after the virtual
8192 registers are instantiated when fpregs are disabled because
8193 the only method that we have for doing DImode multiplication
8194 is with a libcall. This could be trouble if we haven't
8195 allocated enough space for the outgoing arguments. */
8196 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8198 emit_move_insn (arg_pointer_rtx,
8199 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8200 GEN_INT (STACK_POINTER_OFFSET + 64)));
8204 /* Indirect sibling calls are not allowed. */
8206 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8208 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8210 call_insn = emit_call_insn (call_insn);
8213 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8215 /* We don't have to restore the PIC register. */
8217 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8222 (define_insn "sibcall_internal_symref"
8223 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8224 (match_operand 1 "" "i"))
8225 (clobber (reg:SI 1))
8227 (use (const_int 0))]
8228 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8231 output_arg_descriptor (insn);
8232 return output_call (insn, operands[0], 1);
8234 [(set_attr "type" "call")
8235 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8237 (define_insn "sibcall_internal_symref_64bit"
8238 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8239 (match_operand 1 "" "i"))
8240 (clobber (reg:DI 1))
8242 (use (const_int 0))]
8246 output_arg_descriptor (insn);
8247 return output_call (insn, operands[0], 1);
8249 [(set_attr "type" "call")
8250 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8252 (define_expand "sibcall_value"
8253 [(set (match_operand 0 "" "")
8254 (call (match_operand:SI 1 "" "")
8255 (match_operand 2 "" "")))]
8256 "!TARGET_PORTABLE_RUNTIME"
8260 rtx nb = operands[1];
8262 op = XEXP (operands[1], 0);
8266 if (!virtuals_instantiated)
8267 emit_move_insn (arg_pointer_rtx,
8268 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8272 /* The loop pass can generate new libcalls after the virtual
8273 registers are instantiated when fpregs are disabled because
8274 the only method that we have for doing DImode multiplication
8275 is with a libcall. This could be trouble if we haven't
8276 allocated enough space for the outgoing arguments. */
8277 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8279 emit_move_insn (arg_pointer_rtx,
8280 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8281 GEN_INT (STACK_POINTER_OFFSET + 64)));
8285 /* Indirect sibling calls are not allowed. */
8288 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8291 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8293 call_insn = emit_call_insn (call_insn);
8296 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8298 /* We don't have to restore the PIC register. */
8300 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8305 (define_insn "sibcall_value_internal_symref"
8306 [(set (match_operand 0 "" "")
8307 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8308 (match_operand 2 "" "i")))
8309 (clobber (reg:SI 1))
8311 (use (const_int 0))]
8312 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8315 output_arg_descriptor (insn);
8316 return output_call (insn, operands[1], 1);
8318 [(set_attr "type" "call")
8319 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8321 (define_insn "sibcall_value_internal_symref_64bit"
8322 [(set (match_operand 0 "" "")
8323 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8324 (match_operand 2 "" "i")))
8325 (clobber (reg:DI 1))
8327 (use (const_int 0))]
8331 output_arg_descriptor (insn);
8332 return output_call (insn, operands[1], 1);
8334 [(set_attr "type" "call")
8335 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8341 [(set_attr "type" "move")
8342 (set_attr "length" "4")])
8344 ;; These are just placeholders so we know where branch tables
8346 (define_insn "begin_brtab"
8351 /* Only GAS actually supports this pseudo-op. */
8353 return \".begin_brtab\";
8357 [(set_attr "type" "move")
8358 (set_attr "length" "0")])
8360 (define_insn "end_brtab"
8365 /* Only GAS actually supports this pseudo-op. */
8367 return \".end_brtab\";
8371 [(set_attr "type" "move")
8372 (set_attr "length" "0")])
8374 ;;; EH does longjmp's from and within the data section. Thus,
8375 ;;; an interspace branch is required for the longjmp implementation.
8376 ;;; Registers r1 and r2 are used as scratch registers for the jump
8378 (define_expand "interspace_jump"
8380 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8381 (clobber (match_dup 1))])]
8385 operands[1] = gen_rtx_REG (word_mode, 2);
8389 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8390 (clobber (reg:SI 2))]
8391 "TARGET_PA_20 && !TARGET_64BIT"
8393 [(set_attr "type" "branch")
8394 (set_attr "length" "4")])
8397 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8398 (clobber (reg:SI 2))]
8399 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8401 [(set_attr "type" "branch")
8402 (set_attr "length" "4")])
8405 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8406 (clobber (reg:SI 2))]
8408 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8409 [(set_attr "type" "branch")
8410 (set_attr "length" "12")])
8413 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8414 (clobber (reg:DI 2))]
8417 [(set_attr "type" "branch")
8418 (set_attr "length" "4")])
8420 (define_expand "builtin_longjmp"
8421 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8425 /* The elements of the buffer are, in order: */
8426 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8427 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8428 POINTER_SIZE / BITS_PER_UNIT));
8429 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8430 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8431 rtx pv = gen_rtx_REG (Pmode, 1);
8433 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
8434 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
8436 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
8437 instead of the hard_frame_pointer_rtx in the save area. We need
8438 to adjust for the offset between these two values when we have
8439 a nonlocal_goto pattern. When we don't have a nonlocal_goto
8440 pattern, the receiver performs the adjustment. */
8441 #ifdef HAVE_nonlocal_goto
8442 if (HAVE_nonlocal_goto)
8443 emit_move_insn (virtual_stack_vars_rtx, force_reg (Pmode, fp));
8446 emit_move_insn (hard_frame_pointer_rtx, fp);
8448 /* This bit is the same as expand_builtin_longjmp. */
8449 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8450 emit_use (hard_frame_pointer_rtx);
8451 emit_use (stack_pointer_rtx);
8453 /* Load the label we are jumping through into r1 so that we know
8454 where to look for it when we get back to setjmp's function for
8455 restoring the gp. */
8456 emit_move_insn (pv, lab);
8458 /* Prevent the insns above from being scheduled into the delay slot
8459 of the interspace jump because the space register could change. */
8460 emit_insn (gen_blockage ());
8462 emit_jump_insn (gen_interspace_jump (pv));
8467 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8468 (define_expand "extzv"
8469 [(set (match_operand 0 "register_operand" "")
8470 (zero_extract (match_operand 1 "register_operand" "")
8471 (match_operand 2 "uint32_operand" "")
8472 (match_operand 3 "uint32_operand" "")))]
8476 HOST_WIDE_INT len = INTVAL (operands[2]);
8477 HOST_WIDE_INT pos = INTVAL (operands[3]);
8479 /* PA extraction insns don't support zero length bitfields or fields
8480 extending beyond the left or right-most bits. Also, we reject lengths
8481 equal to a word as they are better handled by the move patterns. */
8482 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8485 /* From mips.md: extract_bit_field doesn't verify that our source
8486 matches the predicate, so check it again here. */
8487 if (!register_operand (operands[1], VOIDmode))
8491 emit_insn (gen_extzv_64 (operands[0], operands[1],
8492 operands[2], operands[3]));
8494 emit_insn (gen_extzv_32 (operands[0], operands[1],
8495 operands[2], operands[3]));
8499 (define_insn "extzv_32"
8500 [(set (match_operand:SI 0 "register_operand" "=r")
8501 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8502 (match_operand:SI 2 "uint5_operand" "")
8503 (match_operand:SI 3 "uint5_operand" "")))]
8505 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8506 [(set_attr "type" "shift")
8507 (set_attr "length" "4")])
8510 [(set (match_operand:SI 0 "register_operand" "=r")
8511 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8513 (match_operand:SI 2 "register_operand" "q")))]
8515 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8516 [(set_attr "type" "shift")
8517 (set_attr "length" "4")])
8519 (define_insn "extzv_64"
8520 [(set (match_operand:DI 0 "register_operand" "=r")
8521 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8522 (match_operand:DI 2 "uint32_operand" "")
8523 (match_operand:DI 3 "uint32_operand" "")))]
8525 "extrd,u %1,%3+%2-1,%2,%0"
8526 [(set_attr "type" "shift")
8527 (set_attr "length" "4")])
8530 [(set (match_operand:DI 0 "register_operand" "=r")
8531 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8533 (match_operand:DI 2 "register_operand" "q")))]
8535 "extrd,u %1,%%sar,1,%0"
8536 [(set_attr "type" "shift")
8537 (set_attr "length" "4")])
8539 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8540 (define_expand "extv"
8541 [(set (match_operand 0 "register_operand" "")
8542 (sign_extract (match_operand 1 "register_operand" "")
8543 (match_operand 2 "uint32_operand" "")
8544 (match_operand 3 "uint32_operand" "")))]
8548 HOST_WIDE_INT len = INTVAL (operands[2]);
8549 HOST_WIDE_INT pos = INTVAL (operands[3]);
8551 /* PA extraction insns don't support zero length bitfields or fields
8552 extending beyond the left or right-most bits. Also, we reject lengths
8553 equal to a word as they are better handled by the move patterns. */
8554 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8557 /* From mips.md: extract_bit_field doesn't verify that our source
8558 matches the predicate, so check it again here. */
8559 if (!register_operand (operands[1], VOIDmode))
8563 emit_insn (gen_extv_64 (operands[0], operands[1],
8564 operands[2], operands[3]));
8566 emit_insn (gen_extv_32 (operands[0], operands[1],
8567 operands[2], operands[3]));
8571 (define_insn "extv_32"
8572 [(set (match_operand:SI 0 "register_operand" "=r")
8573 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8574 (match_operand:SI 2 "uint5_operand" "")
8575 (match_operand:SI 3 "uint5_operand" "")))]
8577 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8578 [(set_attr "type" "shift")
8579 (set_attr "length" "4")])
8582 [(set (match_operand:SI 0 "register_operand" "=r")
8583 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8585 (match_operand:SI 2 "register_operand" "q")))]
8587 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8588 [(set_attr "type" "shift")
8589 (set_attr "length" "4")])
8591 (define_insn "extv_64"
8592 [(set (match_operand:DI 0 "register_operand" "=r")
8593 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8594 (match_operand:DI 2 "uint32_operand" "")
8595 (match_operand:DI 3 "uint32_operand" "")))]
8597 "extrd,s %1,%3+%2-1,%2,%0"
8598 [(set_attr "type" "shift")
8599 (set_attr "length" "4")])
8602 [(set (match_operand:DI 0 "register_operand" "=r")
8603 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8605 (match_operand:DI 2 "register_operand" "q")))]
8607 "extrd,s %1,%%sar,1,%0"
8608 [(set_attr "type" "shift")
8609 (set_attr "length" "4")])
8611 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8612 (define_expand "insv"
8613 [(set (zero_extract (match_operand 0 "register_operand" "")
8614 (match_operand 1 "uint32_operand" "")
8615 (match_operand 2 "uint32_operand" ""))
8616 (match_operand 3 "arith5_operand" ""))]
8620 HOST_WIDE_INT len = INTVAL (operands[1]);
8621 HOST_WIDE_INT pos = INTVAL (operands[2]);
8623 /* PA insertion insns don't support zero length bitfields or fields
8624 extending beyond the left or right-most bits. Also, we reject lengths
8625 equal to a word as they are better handled by the move patterns. */
8626 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8629 /* From mips.md: insert_bit_field doesn't verify that our destination
8630 matches the predicate, so check it again here. */
8631 if (!register_operand (operands[0], VOIDmode))
8635 emit_insn (gen_insv_64 (operands[0], operands[1],
8636 operands[2], operands[3]));
8638 emit_insn (gen_insv_32 (operands[0], operands[1],
8639 operands[2], operands[3]));
8643 (define_insn "insv_32"
8644 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8645 (match_operand:SI 1 "uint5_operand" "")
8646 (match_operand:SI 2 "uint5_operand" ""))
8647 (match_operand:SI 3 "arith5_operand" "r,L"))]
8650 {dep|depw} %3,%2+%1-1,%1,%0
8651 {depi|depwi} %3,%2+%1-1,%1,%0"
8652 [(set_attr "type" "shift,shift")
8653 (set_attr "length" "4,4")])
8655 ;; Optimize insertion of const_int values of type 1...1xxxx.
8657 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8658 (match_operand:SI 1 "uint5_operand" "")
8659 (match_operand:SI 2 "uint5_operand" ""))
8660 (match_operand:SI 3 "const_int_operand" ""))]
8661 "(INTVAL (operands[3]) & 0x10) != 0 &&
8662 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8665 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8666 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8668 [(set_attr "type" "shift")
8669 (set_attr "length" "4")])
8671 (define_insn "insv_64"
8672 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8673 (match_operand:DI 1 "uint32_operand" "")
8674 (match_operand:DI 2 "uint32_operand" ""))
8675 (match_operand:DI 3 "arith32_operand" "r,L"))]
8678 depd %3,%2+%1-1,%1,%0
8679 depdi %3,%2+%1-1,%1,%0"
8680 [(set_attr "type" "shift,shift")
8681 (set_attr "length" "4,4")])
8683 ;; Optimize insertion of const_int values of type 1...1xxxx.
8685 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
8686 (match_operand:DI 1 "uint32_operand" "")
8687 (match_operand:DI 2 "uint32_operand" ""))
8688 (match_operand:DI 3 "const_int_operand" ""))]
8689 "(INTVAL (operands[3]) & 0x10) != 0
8691 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8694 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8695 return \"depdi %3,%2+%1-1,%1,%0\";
8697 [(set_attr "type" "shift")
8698 (set_attr "length" "4")])
8701 [(set (match_operand:DI 0 "register_operand" "=r")
8702 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
8705 "depd,z %1,31,32,%0"
8706 [(set_attr "type" "shift")
8707 (set_attr "length" "4")])
8709 ;; This insn is used for some loop tests, typically loops reversed when
8710 ;; strength reduction is used. It is actually created when the instruction
8711 ;; combination phase combines the special loop test. Since this insn
8712 ;; is both a jump insn and has an output, it must deal with its own
8713 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
8714 ;; to not choose the register alternatives in the event a reload is needed.
8715 (define_insn "decrement_and_branch_until_zero"
8718 (match_operator 2 "comparison_operator"
8720 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
8721 (match_operand:SI 1 "int5_operand" "L,L,L"))
8723 (label_ref (match_operand 3 "" ""))
8726 (plus:SI (match_dup 0) (match_dup 1)))
8727 (clobber (match_scratch:SI 4 "=X,r,r"))]
8729 "* return output_dbra (operands, insn, which_alternative); "
8730 ;; Do not expect to understand this the first time through.
8731 [(set_attr "type" "cbranch,multi,multi")
8732 (set (attr "length")
8733 (if_then_else (eq_attr "alternative" "0")
8734 ;; Loop counter in register case
8735 ;; Short branch has length of 4
8736 ;; Long branch has length of 8, 20, 24 or 28
8737 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8738 (const_int MAX_12BIT_OFFSET))
8740 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8741 (const_int MAX_17BIT_OFFSET))
8743 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8745 (eq (symbol_ref "flag_pic") (const_int 0))
8749 ;; Loop counter in FP reg case.
8750 ;; Extra goo to deal with additional reload insns.
8751 (if_then_else (eq_attr "alternative" "1")
8752 (if_then_else (lt (match_dup 3) (pc))
8753 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8754 (const_int MAX_12BIT_OFFSET))
8756 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8757 (const_int MAX_17BIT_OFFSET))
8759 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8761 (eq (symbol_ref "flag_pic") (const_int 0))
8764 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8765 (const_int MAX_12BIT_OFFSET))
8767 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8768 (const_int MAX_17BIT_OFFSET))
8770 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8772 (eq (symbol_ref "flag_pic") (const_int 0))
8776 ;; Loop counter in memory case.
8777 ;; Extra goo to deal with additional reload insns.
8778 (if_then_else (lt (match_dup 3) (pc))
8779 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8780 (const_int MAX_12BIT_OFFSET))
8782 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8783 (const_int MAX_17BIT_OFFSET))
8785 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8787 (eq (symbol_ref "flag_pic") (const_int 0))
8790 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8791 (const_int MAX_12BIT_OFFSET))
8793 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8794 (const_int MAX_17BIT_OFFSET))
8796 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8798 (eq (symbol_ref "flag_pic") (const_int 0))
8800 (const_int 36))))))])
8805 (match_operator 2 "movb_comparison_operator"
8806 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8807 (label_ref (match_operand 3 "" ""))
8809 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8812 "* return output_movb (operands, insn, which_alternative, 0); "
8813 ;; Do not expect to understand this the first time through.
8814 [(set_attr "type" "cbranch,multi,multi,multi")
8815 (set (attr "length")
8816 (if_then_else (eq_attr "alternative" "0")
8817 ;; Loop counter in register case
8818 ;; Short branch has length of 4
8819 ;; Long branch has length of 8, 20, 24 or 28
8820 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8821 (const_int MAX_12BIT_OFFSET))
8823 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8824 (const_int MAX_17BIT_OFFSET))
8826 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8828 (eq (symbol_ref "flag_pic") (const_int 0))
8832 ;; Loop counter in FP reg case.
8833 ;; Extra goo to deal with additional reload insns.
8834 (if_then_else (eq_attr "alternative" "1")
8835 (if_then_else (lt (match_dup 3) (pc))
8836 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8837 (const_int MAX_12BIT_OFFSET))
8839 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8840 (const_int MAX_17BIT_OFFSET))
8842 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8844 (eq (symbol_ref "flag_pic") (const_int 0))
8847 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8848 (const_int MAX_12BIT_OFFSET))
8850 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8851 (const_int MAX_17BIT_OFFSET))
8853 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8855 (eq (symbol_ref "flag_pic") (const_int 0))
8859 ;; Loop counter in memory or sar case.
8860 ;; Extra goo to deal with additional reload insns.
8861 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8862 (const_int MAX_12BIT_OFFSET))
8864 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8865 (const_int MAX_17BIT_OFFSET))
8867 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8869 (eq (symbol_ref "flag_pic") (const_int 0))
8871 (const_int 32)))))])
8873 ;; Handle negated branch.
8877 (match_operator 2 "movb_comparison_operator"
8878 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8880 (label_ref (match_operand 3 "" ""))))
8881 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8884 "* return output_movb (operands, insn, which_alternative, 1); "
8885 ;; Do not expect to understand this the first time through.
8886 [(set_attr "type" "cbranch,multi,multi,multi")
8887 (set (attr "length")
8888 (if_then_else (eq_attr "alternative" "0")
8889 ;; Loop counter in register case
8890 ;; Short branch has length of 4
8891 ;; Long branch has length of 8
8892 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8893 (const_int MAX_12BIT_OFFSET))
8895 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8896 (const_int MAX_17BIT_OFFSET))
8898 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8900 (eq (symbol_ref "flag_pic") (const_int 0))
8904 ;; Loop counter in FP reg case.
8905 ;; Extra goo to deal with additional reload insns.
8906 (if_then_else (eq_attr "alternative" "1")
8907 (if_then_else (lt (match_dup 3) (pc))
8908 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8909 (const_int MAX_12BIT_OFFSET))
8911 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8912 (const_int MAX_17BIT_OFFSET))
8914 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8916 (eq (symbol_ref "flag_pic") (const_int 0))
8919 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8920 (const_int MAX_12BIT_OFFSET))
8922 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8923 (const_int MAX_17BIT_OFFSET))
8925 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8927 (eq (symbol_ref "flag_pic") (const_int 0))
8931 ;; Loop counter in memory or SAR case.
8932 ;; Extra goo to deal with additional reload insns.
8933 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8934 (const_int MAX_12BIT_OFFSET))
8936 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8937 (const_int MAX_17BIT_OFFSET))
8939 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8941 (eq (symbol_ref "flag_pic") (const_int 0))
8943 (const_int 32)))))])
8946 [(set (pc) (label_ref (match_operand 3 "" "" )))
8947 (set (match_operand:SI 0 "ireg_operand" "=r")
8948 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
8949 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
8950 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
8953 return output_parallel_addb (operands, insn);
8955 [(set_attr "type" "parallel_branch")
8956 (set (attr "length")
8957 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8958 (const_int MAX_12BIT_OFFSET))
8960 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8961 (const_int MAX_17BIT_OFFSET))
8963 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8965 (eq (symbol_ref "flag_pic") (const_int 0))
8970 [(set (pc) (label_ref (match_operand 2 "" "" )))
8971 (set (match_operand:SF 0 "ireg_operand" "=r")
8972 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
8976 return output_parallel_movb (operands, insn);
8978 [(set_attr "type" "parallel_branch")
8979 (set (attr "length")
8980 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8981 (const_int MAX_12BIT_OFFSET))
8983 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8984 (const_int MAX_17BIT_OFFSET))
8986 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8988 (eq (symbol_ref "flag_pic") (const_int 0))
8993 [(set (pc) (label_ref (match_operand 2 "" "" )))
8994 (set (match_operand:SI 0 "ireg_operand" "=r")
8995 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
8999 return output_parallel_movb (operands, insn);
9001 [(set_attr "type" "parallel_branch")
9002 (set (attr "length")
9003 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9004 (const_int MAX_12BIT_OFFSET))
9006 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9007 (const_int MAX_17BIT_OFFSET))
9009 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9011 (eq (symbol_ref "flag_pic") (const_int 0))
9016 [(set (pc) (label_ref (match_operand 2 "" "" )))
9017 (set (match_operand:HI 0 "ireg_operand" "=r")
9018 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
9022 return output_parallel_movb (operands, insn);
9024 [(set_attr "type" "parallel_branch")
9025 (set (attr "length")
9026 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9027 (const_int MAX_12BIT_OFFSET))
9029 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9030 (const_int MAX_17BIT_OFFSET))
9032 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9034 (eq (symbol_ref "flag_pic") (const_int 0))
9039 [(set (pc) (label_ref (match_operand 2 "" "" )))
9040 (set (match_operand:QI 0 "ireg_operand" "=r")
9041 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
9045 return output_parallel_movb (operands, insn);
9047 [(set_attr "type" "parallel_branch")
9048 (set (attr "length")
9049 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9050 (const_int MAX_12BIT_OFFSET))
9052 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9053 (const_int MAX_17BIT_OFFSET))
9055 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9057 (eq (symbol_ref "flag_pic") (const_int 0))
9062 [(set (match_operand 0 "register_operand" "=f")
9063 (mult (match_operand 1 "register_operand" "f")
9064 (match_operand 2 "register_operand" "f")))
9065 (set (match_operand 3 "register_operand" "+f")
9066 (plus (match_operand 4 "register_operand" "f")
9067 (match_operand 5 "register_operand" "f")))]
9068 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9069 && reload_completed && fmpyaddoperands (operands)"
9072 if (GET_MODE (operands[0]) == DFmode)
9074 if (rtx_equal_p (operands[3], operands[5]))
9075 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9077 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9081 if (rtx_equal_p (operands[3], operands[5]))
9082 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9084 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9087 [(set_attr "type" "fpalu")
9088 (set_attr "length" "4")])
9091 [(set (match_operand 3 "register_operand" "+f")
9092 (plus (match_operand 4 "register_operand" "f")
9093 (match_operand 5 "register_operand" "f")))
9094 (set (match_operand 0 "register_operand" "=f")
9095 (mult (match_operand 1 "register_operand" "f")
9096 (match_operand 2 "register_operand" "f")))]
9097 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9098 && reload_completed && fmpyaddoperands (operands)"
9101 if (GET_MODE (operands[0]) == DFmode)
9103 if (rtx_equal_p (operands[3], operands[5]))
9104 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9106 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9110 if (rtx_equal_p (operands[3], operands[5]))
9111 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9113 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9116 [(set_attr "type" "fpalu")
9117 (set_attr "length" "4")])
9120 [(set (match_operand 0 "register_operand" "=f")
9121 (mult (match_operand 1 "register_operand" "f")
9122 (match_operand 2 "register_operand" "f")))
9123 (set (match_operand 3 "register_operand" "+f")
9124 (minus (match_operand 4 "register_operand" "f")
9125 (match_operand 5 "register_operand" "f")))]
9126 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9127 && reload_completed && fmpysuboperands (operands)"
9130 if (GET_MODE (operands[0]) == DFmode)
9131 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9133 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9135 [(set_attr "type" "fpalu")
9136 (set_attr "length" "4")])
9139 [(set (match_operand 3 "register_operand" "+f")
9140 (minus (match_operand 4 "register_operand" "f")
9141 (match_operand 5 "register_operand" "f")))
9142 (set (match_operand 0 "register_operand" "=f")
9143 (mult (match_operand 1 "register_operand" "f")
9144 (match_operand 2 "register_operand" "f")))]
9145 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9146 && reload_completed && fmpysuboperands (operands)"
9149 if (GET_MODE (operands[0]) == DFmode)
9150 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9152 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9154 [(set_attr "type" "fpalu")
9155 (set_attr "length" "4")])
9157 ;; The following two patterns are used by the trampoline code for nested
9158 ;; functions. They flush the I and D cache lines from the start address
9159 ;; (operand0) to the end address (operand1). No lines are flushed if the
9160 ;; end address is less than the start address (unsigned).
9162 ;; Because the range of memory flushed is variable and the size of a MEM
9163 ;; can only be a CONST_INT, the patterns specify that they perform an
9164 ;; unspecified volatile operation on all memory.
9166 ;; The address range for an icache flush must lie within a single
9167 ;; space on targets with non-equivalent space registers.
9169 ;; Operand 0 contains the start address.
9170 ;; Operand 1 contains the end address.
9171 ;; Operand 2 contains the line length to use.
9172 (define_insn "dcacheflush<P:mode>"
9174 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
9175 (use (match_operand 0 "pmode_register_operand" "r"))
9176 (use (match_operand 1 "pmode_register_operand" "r"))
9177 (use (match_operand 2 "pmode_register_operand" "r"))
9178 (clobber (match_scratch:P 3 "=&0"))]
9180 "cmpb,<dwc><<=,n %3,%1,.\;fdc,m %2(%3)\;sync"
9181 [(set_attr "type" "multi")
9182 (set_attr "length" "12")])
9184 (define_insn "icacheflush<P:mode>"
9186 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
9187 (use (match_operand 0 "pmode_register_operand" "r"))
9188 (use (match_operand 1 "pmode_register_operand" "r"))
9189 (use (match_operand 2 "pmode_register_operand" "r"))
9190 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
9191 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
9192 (clobber (match_scratch:P 5 "=&0"))]
9194 "mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<dwc><<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
9195 [(set_attr "type" "multi")
9196 (set_attr "length" "52")])
9198 ;; An out-of-line prologue.
9199 (define_insn "outline_prologue_call"
9200 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9201 (clobber (reg:SI 31))
9202 (clobber (reg:SI 22))
9203 (clobber (reg:SI 21))
9204 (clobber (reg:SI 20))
9205 (clobber (reg:SI 19))
9206 (clobber (reg:SI 1))]
9211 /* We need two different versions depending on whether or not we
9212 need a frame pointer. Also note that we return to the instruction
9213 immediately after the branch rather than two instructions after the
9214 break as normally is the case. */
9215 if (frame_pointer_needed)
9217 /* Must import the magic millicode routine(s). */
9218 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9220 if (TARGET_PORTABLE_RUNTIME)
9222 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9223 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9227 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9231 /* Must import the magic millicode routine(s). */
9232 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9234 if (TARGET_PORTABLE_RUNTIME)
9236 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9237 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9240 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9244 [(set_attr "type" "multi")
9245 (set_attr "length" "8")])
9247 ;; An out-of-line epilogue.
9248 (define_insn "outline_epilogue_call"
9249 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9252 (clobber (reg:SI 31))
9253 (clobber (reg:SI 22))
9254 (clobber (reg:SI 21))
9255 (clobber (reg:SI 20))
9256 (clobber (reg:SI 19))
9257 (clobber (reg:SI 2))
9258 (clobber (reg:SI 1))]
9263 /* We need two different versions depending on whether or not we
9264 need a frame pointer. Also note that we return to the instruction
9265 immediately after the branch rather than two instructions after the
9266 break as normally is the case. */
9267 if (frame_pointer_needed)
9269 /* Must import the magic millicode routine. */
9270 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9272 /* The out-of-line prologue will make sure we return to the right
9274 if (TARGET_PORTABLE_RUNTIME)
9276 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9277 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9281 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9285 /* Must import the magic millicode routine. */
9286 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9288 /* The out-of-line prologue will make sure we return to the right
9290 if (TARGET_PORTABLE_RUNTIME)
9292 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9293 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9296 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9300 [(set_attr "type" "multi")
9301 (set_attr "length" "8")])
9303 ;; Given a function pointer, canonicalize it so it can be
9304 ;; reliably compared to another function pointer. */
9305 (define_expand "canonicalize_funcptr_for_compare"
9306 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9307 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9308 (clobber (match_dup 2))
9309 (clobber (reg:SI 26))
9310 (clobber (reg:SI 22))
9311 (clobber (reg:SI 31))])
9312 (set (match_operand:SI 0 "register_operand" "")
9314 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9319 rtx canonicalize_funcptr_for_compare_libfunc
9320 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9322 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9323 operands[0], LCT_NORMAL, Pmode,
9324 1, operands[1], Pmode);
9328 operands[2] = gen_reg_rtx (SImode);
9329 if (GET_CODE (operands[1]) != REG)
9331 rtx tmp = gen_reg_rtx (Pmode);
9332 emit_move_insn (tmp, operands[1]);
9337 (define_insn "*$$sh_func_adrs"
9338 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9339 (clobber (match_operand:SI 0 "register_operand" "=a"))
9340 (clobber (reg:SI 26))
9341 (clobber (reg:SI 22))
9342 (clobber (reg:SI 31))]
9346 int length = get_attr_length (insn);
9349 xoperands[0] = GEN_INT (length - 8);
9350 xoperands[1] = GEN_INT (length - 16);
9352 /* Must import the magic millicode routine. */
9353 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9355 /* This is absolutely amazing.
9357 First, copy our input parameter into %r29 just in case we don't
9358 need to call $$sh_func_adrs. */
9359 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9360 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9362 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9363 we use %r26 unchanged. */
9364 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9365 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9367 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9368 4096, then again we use %r26 unchanged. */
9369 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9371 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9372 return output_millicode_call (insn,
9373 gen_rtx_SYMBOL_REF (SImode,
9374 \"$$sh_func_adrs\"));
9376 [(set_attr "type" "multi")
9377 (set (attr "length")
9378 (plus (symbol_ref "attr_length_millicode_call (insn)")
9381 ;; On the PA, the PIC register is call clobbered, so it must
9382 ;; be saved & restored around calls by the caller. If the call
9383 ;; doesn't return normally (nonlocal goto, or an exception is
9384 ;; thrown), then the code at the exception handler label must
9385 ;; restore the PIC register.
9386 (define_expand "exception_receiver"
9391 /* On the 64-bit port, we need a blockage because there is
9392 confusion regarding the dependence of the restore on the
9393 frame pointer. As a result, the frame pointer and pic
9394 register restores sometimes are interchanged erroneously. */
9396 emit_insn (gen_blockage ());
9397 /* Restore the PIC register using hppa_pic_save_rtx (). The
9398 PIC register is not saved in the frame in 64-bit ABI. */
9399 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9400 emit_insn (gen_blockage ());
9404 (define_expand "builtin_setjmp_receiver"
9405 [(label_ref (match_operand 0 "" ""))]
9410 emit_insn (gen_blockage ());
9411 /* Restore the PIC register. Hopefully, this will always be from
9412 a stack slot. The only registers that are valid after a
9413 builtin_longjmp are the stack and frame pointers. */
9414 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9415 emit_insn (gen_blockage ());
9419 ;; Allocate new stack space and update the saved stack pointer in the
9420 ;; frame marker. The HP C compilers also copy additional words in the
9421 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9422 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9423 ;; currently don't copy these values.
9425 ;; Since the copy of the frame marker can't be done atomically, I
9426 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9427 ;; The HP compilers appear to raise the stack and copy the frame
9428 ;; marker in a strict instruction sequence. This suggests that the
9429 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9430 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9431 ;; as GAS doesn't support it, or try to keep the instructions emitted
9432 ;; here in strict sequence.
9433 (define_expand "allocate_stack"
9434 [(match_operand 0 "" "")
9435 (match_operand 1 "" "")]
9441 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9442 in operand 0 before adjusting the stack. */
9443 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9444 anti_adjust_stack (operands[1]);
9445 if (TARGET_HPUX_UNWIND_LIBRARY)
9447 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9448 GEN_INT (TARGET_64BIT ? -8 : -4));
9449 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9451 if (!TARGET_64BIT && flag_pic)
9453 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9454 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
9459 (define_expand "prefetch"
9460 [(match_operand 0 "address_operand" "")
9461 (match_operand 1 "const_int_operand" "")
9462 (match_operand 2 "const_int_operand" "")]
9465 int locality = INTVAL (operands[2]);
9467 gcc_assert (locality >= 0 && locality <= 3);
9469 /* Change operand[0] to a MEM as we don't have the infrastructure
9470 to output all the supported address modes for ldw/ldd when we use
9471 the address directly. However, we do have it for MEMs. */
9472 operands[0] = gen_rtx_MEM (QImode, operands[0]);
9474 /* If the address isn't valid for the prefetch, replace it. */
9477 if (!prefetch_nocc_operand (operands[0], QImode))
9479 = replace_equiv_address (operands[0],
9480 copy_to_mode_reg (Pmode,
9481 XEXP (operands[0], 0)));
9482 emit_insn (gen_prefetch_nocc (operands[0], operands[1], operands[2]));
9486 if (!prefetch_cc_operand (operands[0], QImode))
9488 = replace_equiv_address (operands[0],
9489 copy_to_mode_reg (Pmode,
9490 XEXP (operands[0], 0)));
9491 emit_insn (gen_prefetch_cc (operands[0], operands[1], operands[2]));
9496 (define_insn "prefetch_cc"
9497 [(prefetch (match_operand:QI 0 "prefetch_cc_operand" "RW")
9498 (match_operand:SI 1 "const_int_operand" "n")
9499 (match_operand:SI 2 "const_int_operand" "n"))]
9500 "TARGET_PA_20 && operands[2] == const0_rtx"
9502 /* The SL cache-control completor indicates good spatial locality but
9503 poor temporal locality. The ldw instruction with a target of general
9504 register 0 prefetches a cache line for a read. The ldd instruction
9505 prefetches a cache line for a write. */
9506 static const char * const instr[2] = {
9507 "ldw%M0,sl %0,%%r0",
9510 int read_or_write = INTVAL (operands[1]);
9512 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
9514 return instr [read_or_write];
9516 [(set_attr "type" "load")
9517 (set_attr "length" "4")])
9519 (define_insn "prefetch_nocc"
9520 [(prefetch (match_operand:QI 0 "prefetch_nocc_operand" "A,RQ")
9521 (match_operand:SI 1 "const_int_operand" "n,n")
9522 (match_operand:SI 2 "const_int_operand" "n,n"))]
9523 "TARGET_PA_20 && operands[2] != const0_rtx"
9525 /* The ldw instruction with a target of general register 0 prefetches
9526 a cache line for a read. The ldd instruction prefetches a cache line
9528 static const char * const instr[2][2] = {
9538 int read_or_write = INTVAL (operands[1]);
9540 gcc_assert (which_alternative == 0 || which_alternative == 1);
9541 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
9543 return instr [which_alternative][read_or_write];
9545 [(set_attr "type" "load")
9546 (set_attr "length" "4")])
9550 (define_insn "tgd_load"
9551 [(set (match_operand:SI 0 "register_operand" "=r")
9552 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD))
9553 (clobber (reg:SI 1))
9558 return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\";
9560 [(set_attr "type" "multi")
9561 (set_attr "length" "8")])
9563 (define_insn "tgd_load_pic"
9564 [(set (match_operand:SI 0 "register_operand" "=r")
9565 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD_PIC))
9566 (clobber (reg:SI 1))
9571 return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\";
9573 [(set_attr "type" "multi")
9574 (set_attr "length" "8")])
9576 (define_insn "tld_load"
9577 [(set (match_operand:SI 0 "register_operand" "=r")
9578 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM))
9579 (clobber (reg:SI 1))
9584 return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\";
9586 [(set_attr "type" "multi")
9587 (set_attr "length" "8")])
9589 (define_insn "tld_load_pic"
9590 [(set (match_operand:SI 0 "register_operand" "=r")
9591 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM_PIC))
9592 (clobber (reg:SI 1))
9597 return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\";
9599 [(set_attr "type" "multi")
9600 (set_attr "length" "8")])
9602 (define_insn "tld_offset_load"
9603 [(set (match_operand:SI 0 "register_operand" "=r")
9604 (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
9606 (match_operand:SI 2 "register_operand" "r")))
9607 (clobber (reg:SI 1))]
9611 return \"addil LR'%1-$tls_dtpoff$,%2\;ldo RR'%1-$tls_dtpoff$(%%r1),%0\";
9613 [(set_attr "type" "multi")
9614 (set_attr "length" "8")])
9616 (define_insn "tp_load"
9617 [(set (match_operand:SI 0 "register_operand" "=r")
9618 (unspec:SI [(const_int 0)] UNSPEC_TP))]
9621 [(set_attr "type" "multi")
9622 (set_attr "length" "4")])
9624 (define_insn "tie_load"
9625 [(set (match_operand:SI 0 "register_operand" "=r")
9626 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE))
9627 (clobber (reg:SI 1))
9632 return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\";
9634 [(set_attr "type" "multi")
9635 (set_attr "length" "8")])
9637 (define_insn "tie_load_pic"
9638 [(set (match_operand:SI 0 "register_operand" "=r")
9639 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE_PIC))
9640 (clobber (reg:SI 1))
9645 return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\";
9647 [(set_attr "type" "multi")
9648 (set_attr "length" "8")])
9650 (define_insn "tle_load"
9651 [(set (match_operand:SI 0 "register_operand" "=r")
9652 (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
9654 (match_operand:SI 2 "register_operand" "r")))
9655 (clobber (reg:SI 1))]
9657 "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
9658 [(set_attr "type" "multi")
9659 (set_attr "length" "8")])