1 ;; GCC machine description for NEC V850
2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2002, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Jeff Law (law@cygnus.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;; The original PO technology requires these to be ordered by speed,
24 ;; so that assigner will pick the fastest.
26 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;; The V851 manual states that the instruction address space is 16M;
29 ;; the various branch/call instructions only have a 22bit offset (4M range).
31 ;; One day we'll probably need to handle calls to targets more than 4M
34 ;; The size of instructions in bytes.
36 (define_attr "length" ""
39 (define_attr "long_calls" "yes,no"
40 (const (if_then_else (symbol_ref "TARGET_LONG_CALLS")
42 (const_string "no"))))
44 ;; Types of instructions (for scheduling purposes).
46 (define_attr "type" "load,mult,other"
47 (const_string "other"))
49 ;; Condition code settings.
50 ;; none - insn does not affect cc
51 ;; none_0hit - insn does not affect cc but it does modify operand 0
52 ;; This attribute is used to keep track of when operand 0 changes.
53 ;; See the description of NOTICE_UPDATE_CC for more info.
54 ;; set_znv - sets z,n,v to usable values; c is unknown.
55 ;; set_zn - sets z,n to usable values; v,c is unknown.
56 ;; compare - compare instruction
57 ;; clobber - value of cc is unknown
58 (define_attr "cc" "none,none_0hit,set_zn,set_znv,compare,clobber"
59 (const_string "clobber"))
61 ;; Function units for the V850. As best as I can tell, there's
62 ;; a traditional memory load/use stall as well as a stall if
63 ;; the result of a multiply is used too early.
65 (define_insn_reservation "v850_other" 1
66 (eq_attr "type" "other")
68 (define_insn_reservation "v850_mult" 2
69 (eq_attr "type" "mult")
71 (define_insn_reservation "v850_memory" 2
72 (eq_attr "type" "load")
75 (include "predicates.md")
77 ;; ----------------------------------------------------------------------
79 ;; ----------------------------------------------------------------------
83 (define_expand "movqi"
84 [(set (match_operand:QI 0 "general_operand" "")
85 (match_operand:QI 1 "general_operand" ""))]
89 /* One of the ops has to be in a register or 0 */
90 if (!register_operand (operand0, QImode)
91 && !reg_or_0_operand (operand1, QImode))
92 operands[1] = copy_to_mode_reg (QImode, operand1);
95 (define_insn "*movqi_internal"
96 [(set (match_operand:QI 0 "general_operand" "=r,r,r,Q,r,m,m")
97 (match_operand:QI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
98 "register_operand (operands[0], QImode)
99 || reg_or_0_operand (operands[1], QImode)"
100 "* return output_move_single (operands);"
101 [(set_attr "length" "2,4,2,2,4,4,4")
102 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
103 (set_attr "type" "other,other,load,other,load,other,other")])
107 (define_expand "movhi"
108 [(set (match_operand:HI 0 "general_operand" "")
109 (match_operand:HI 1 "general_operand" ""))]
113 /* One of the ops has to be in a register or 0 */
114 if (!register_operand (operand0, HImode)
115 && !reg_or_0_operand (operand1, HImode))
116 operands[1] = copy_to_mode_reg (HImode, operand1);
119 (define_insn "*movhi_internal"
120 [(set (match_operand:HI 0 "general_operand" "=r,r,r,Q,r,m,m")
121 (match_operand:HI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
122 "register_operand (operands[0], HImode)
123 || reg_or_0_operand (operands[1], HImode)"
124 "* return output_move_single (operands);"
125 [(set_attr "length" "2,4,2,2,4,4,4")
126 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
127 (set_attr "type" "other,other,load,other,load,other,other")])
131 (define_insn "*movsi_high"
132 [(set (match_operand:SI 0 "register_operand" "=r")
133 (high:SI (match_operand 1 "" "")))]
136 [(set_attr "length" "4")
137 (set_attr "cc" "none_0hit")
138 (set_attr "type" "other")])
140 (define_insn "*movsi_lo"
141 [(set (match_operand:SI 0 "register_operand" "=r")
142 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
143 (match_operand:SI 2 "immediate_operand" "i")))]
146 [(set_attr "length" "4")
147 (set_attr "cc" "none_0hit")
148 (set_attr "type" "other")])
150 (define_expand "movsi"
151 [(set (match_operand:SI 0 "general_operand" "")
152 (match_operand:SI 1 "general_operand" ""))]
156 /* One of the ops has to be in a register or 0 */
157 if (!register_operand (operand0, SImode)
158 && !reg_or_0_operand (operand1, SImode))
159 operands[1] = copy_to_mode_reg (SImode, operand1);
161 /* Some constants, as well as symbolic operands
162 must be done with HIGH & LO_SUM patterns. */
163 if (CONSTANT_P (operands[1])
164 && GET_CODE (operands[1]) != HIGH
166 && !special_symbolref_operand (operands[1], VOIDmode)
167 && !(GET_CODE (operands[1]) == CONST_INT
168 && (CONST_OK_FOR_J (INTVAL (operands[1]))
169 || CONST_OK_FOR_K (INTVAL (operands[1]))
170 || CONST_OK_FOR_L (INTVAL (operands[1])))))
174 if (reload_in_progress || reload_completed)
177 temp = gen_reg_rtx (SImode);
179 emit_insn (gen_rtx_SET (SImode, temp,
180 gen_rtx_HIGH (SImode, operand1)));
181 emit_insn (gen_rtx_SET (SImode, operand0,
182 gen_rtx_LO_SUM (SImode, temp, operand1)));
187 ;; This is the same as the following pattern, except that it includes
188 ;; support for arbitrary 32 bit immediates.
190 ;; ??? This always loads addresses using hilo. If the only use of this address
191 ;; was in a load/store, then we would get smaller code if we only loaded the
192 ;; upper part with hi, and then put the lower part in the load/store insn.
194 (define_insn "*movsi_internal_v850e"
195 [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m,r")
196 (match_operand:SI 1 "general_operand" "Jr,K,L,Q,Ir,m,R,r,I,i"))]
198 && (register_operand (operands[0], SImode)
199 || reg_or_0_operand (operands[1], SImode))"
200 "* return output_move_single (operands);"
201 [(set_attr "length" "2,4,4,2,2,4,4,4,4,6")
202 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
203 (set_attr "type" "other,other,other,load,other,load,other,other,other,other")])
205 (define_insn "*movsi_internal"
206 [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m")
207 (match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))]
208 "register_operand (operands[0], SImode)
209 || reg_or_0_operand (operands[1], SImode)"
210 "* return output_move_single (operands);"
211 [(set_attr "length" "2,4,4,2,2,4,4,4,4")
212 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
213 (set_attr "type" "other,other,other,load,other,load,other,other,other")])
217 (define_expand "movdi"
218 [(set (match_operand:DI 0 "general_operand" "")
219 (match_operand:DI 1 "general_operand" ""))]
223 /* One of the ops has to be in a register or 0 */
224 if (!register_operand (operand0, DImode)
225 && !reg_or_0_operand (operand1, DImode))
226 operands[1] = copy_to_mode_reg (DImode, operand1);
229 (define_insn "*movdi_internal"
230 [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,m,r")
231 (match_operand:DI 1 "general_operand" "Jr,K,L,i,m,r,IG,iF"))]
232 "register_operand (operands[0], DImode)
233 || reg_or_0_operand (operands[1], DImode)"
234 "* return output_move_double (operands);"
235 [(set_attr "length" "4,8,8,16,8,8,8,16")
236 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
237 (set_attr "type" "other,other,other,other,load,other,other,other")])
239 (define_expand "movsf"
240 [(set (match_operand:SF 0 "general_operand" "")
241 (match_operand:SF 1 "general_operand" ""))]
245 /* One of the ops has to be in a register or 0 */
246 if (!register_operand (operand0, SFmode)
247 && !reg_or_0_operand (operand1, SFmode))
248 operands[1] = copy_to_mode_reg (SFmode, operand1);
251 (define_insn "*movsf_internal"
252 [(set (match_operand:SF 0 "general_operand" "=r,r,r,r,r,Q,r,m,m,r")
253 (match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))]
254 "register_operand (operands[0], SFmode)
255 || reg_or_0_operand (operands[1], SFmode)"
256 "* return output_move_single (operands);"
257 [(set_attr "length" "2,4,4,8,2,2,4,4,4,8")
258 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
259 (set_attr "type" "other,other,other,other,load,other,load,other,other,other")])
261 (define_expand "movdf"
262 [(set (match_operand:DF 0 "general_operand" "")
263 (match_operand:DF 1 "general_operand" ""))]
267 /* One of the ops has to be in a register or 0 */
268 if (!register_operand (operand0, DFmode)
269 && !reg_or_0_operand (operand1, DFmode))
270 operands[1] = copy_to_mode_reg (DFmode, operand1);
273 (define_insn "*movdf_internal"
274 [(set (match_operand:DF 0 "general_operand" "=r,r,r,r,r,m,m,r")
275 (match_operand:DF 1 "general_operand" "Jr,K,L,i,m,r,IG,iF"))]
276 "register_operand (operands[0], DFmode)
277 || reg_or_0_operand (operands[1], DFmode)"
278 "* return output_move_double (operands);"
279 [(set_attr "length" "4,8,8,16,8,8,8,16")
280 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
281 (set_attr "type" "other,other,other,other,load,other,other,other")])
284 ;; ----------------------------------------------------------------------
286 ;; ----------------------------------------------------------------------
288 (define_insn "*v850_tst1"
289 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
291 (match_operand:QI 1 "const_int_operand" "n")))]
294 [(set_attr "length" "4")
295 (set_attr "cc" "clobber")])
297 ;; This replaces ld.b;sar;andi with tst1;setf nz.
299 ;; ??? The zero_extract sets the Z bit to the opposite of what one would
300 ;; expect. This perhaps should be wrapped in a (eq: X (const_int 0)).
303 [(set (match_operand:SI 0 "register_operand" "")
304 (zero_extract:SI (match_operand:QI 1 "memory_operand" "")
306 (match_operand 2 "const_int_operand" "")))]
308 [(set (cc0) (zero_extract:SI (match_dup 1)
311 (set (match_dup 0) (ne:SI (cc0) (const_int 0)))])
314 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
317 [(set_attr "length" "2")
318 (set_attr "cc" "set_znv")])
322 (compare (match_operand:SI 0 "register_operand" "r,r")
323 (match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
328 [(set_attr "length" "2,2")
329 (set_attr "cc" "compare")])
331 ;; ----------------------------------------------------------------------
333 ;; ----------------------------------------------------------------------
335 (define_insn "addsi3"
336 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
337 (plus:SI (match_operand:SI 1 "register_operand" "%0,r,r")
338 (match_operand:SI 2 "nonmemory_operand" "rJ,K,U")))]
344 [(set_attr "length" "2,4,4")
345 (set_attr "cc" "set_zn,set_zn,set_zn")])
347 ;; ----------------------------------------------------------------------
348 ;; SUBTRACT INSTRUCTIONS
349 ;; ----------------------------------------------------------------------
351 (define_insn "subsi3"
352 [(set (match_operand:SI 0 "register_operand" "=r,r")
353 (minus:SI (match_operand:SI 1 "register_operand" "0,r")
354 (match_operand:SI 2 "register_operand" "r,0")))]
359 [(set_attr "length" "2,2")
360 (set_attr "cc" "set_zn")])
362 (define_insn "negsi2"
363 [(set (match_operand:SI 0 "register_operand" "=r")
364 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
367 [(set_attr "length" "2")
368 (set_attr "cc" "set_zn")])
370 ;; ----------------------------------------------------------------------
371 ;; MULTIPLY INSTRUCTIONS
372 ;; ----------------------------------------------------------------------
374 (define_expand "mulhisi3"
375 [(set (match_operand:SI 0 "register_operand" "")
377 (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
378 (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))]
380 "if (GET_CODE (operands[2]) == CONST_INT)
382 emit_insn (gen_mulhisi3_internal2 (operands[0], operands[1], operands[2]));
386 (define_insn "*mulhisi3_internal1"
387 [(set (match_operand:SI 0 "register_operand" "=r")
389 (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
390 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
393 [(set_attr "length" "2")
394 (set_attr "cc" "none_0hit")
395 (set_attr "type" "mult")])
397 (define_insn "mulhisi3_internal2"
398 [(set (match_operand:SI 0 "register_operand" "=r,r")
400 (sign_extend:SI (match_operand:HI 1 "register_operand" "%0,r"))
401 (match_operand:HI 2 "const_int_operand" "J,K")))]
406 [(set_attr "length" "2,4")
407 (set_attr "cc" "none_0hit,none_0hit")
408 (set_attr "type" "mult")])
410 ;; ??? The scheduling info is probably wrong.
412 ;; ??? This instruction can also generate the 32 bit highpart, but using it
413 ;; may increase code size counter to the desired result.
415 ;; ??? This instructions can also give a DImode result.
417 ;; ??? There is unsigned version, but it matters only for the DImode/highpart
420 (define_insn "mulsi3"
421 [(set (match_operand:SI 0 "register_operand" "=r")
422 (mult:SI (match_operand:SI 1 "register_operand" "%0")
423 (match_operand:SI 2 "reg_or_int9_operand" "rO")))]
426 [(set_attr "length" "4")
427 (set_attr "cc" "none_0hit")
428 (set_attr "type" "mult")])
430 ;; ----------------------------------------------------------------------
431 ;; DIVIDE INSTRUCTIONS
432 ;; ----------------------------------------------------------------------
434 ;; ??? These insns do set the Z/N condition codes, except that they are based
435 ;; on only one of the two results, so it doesn't seem to make sense to use
438 ;; ??? The scheduling info is probably wrong.
440 (define_insn "divmodsi4"
441 [(set (match_operand:SI 0 "register_operand" "=r")
442 (div:SI (match_operand:SI 1 "register_operand" "0")
443 (match_operand:SI 2 "register_operand" "r")))
444 (set (match_operand:SI 3 "register_operand" "=r")
445 (mod:SI (match_dup 1)
449 [(set_attr "length" "4")
450 (set_attr "cc" "clobber")
451 (set_attr "type" "other")])
453 (define_insn "udivmodsi4"
454 [(set (match_operand:SI 0 "register_operand" "=r")
455 (udiv:SI (match_operand:SI 1 "register_operand" "0")
456 (match_operand:SI 2 "register_operand" "r")))
457 (set (match_operand:SI 3 "register_operand" "=r")
458 (umod:SI (match_dup 1)
462 [(set_attr "length" "4")
463 (set_attr "cc" "clobber")
464 (set_attr "type" "other")])
466 ;; ??? There is a 2 byte instruction for generating only the quotient.
467 ;; However, it isn't clear how to compute the length field correctly.
469 (define_insn "divmodhi4"
470 [(set (match_operand:HI 0 "register_operand" "=r")
471 (div:HI (match_operand:HI 1 "register_operand" "0")
472 (match_operand:HI 2 "register_operand" "r")))
473 (set (match_operand:HI 3 "register_operand" "=r")
474 (mod:HI (match_dup 1)
478 [(set_attr "length" "4")
479 (set_attr "cc" "clobber")
480 (set_attr "type" "other")])
482 ;; Half-words are sign-extended by default, so we must zero extend to a word
483 ;; here before doing the divide.
485 (define_insn "udivmodhi4"
486 [(set (match_operand:HI 0 "register_operand" "=r")
487 (udiv:HI (match_operand:HI 1 "register_operand" "0")
488 (match_operand:HI 2 "register_operand" "r")))
489 (set (match_operand:HI 3 "register_operand" "=r")
490 (umod:HI (match_dup 1)
493 "zxh %0 ; divhu %2,%0,%3"
494 [(set_attr "length" "4")
495 (set_attr "cc" "clobber")
496 (set_attr "type" "other")])
498 ;; ----------------------------------------------------------------------
500 ;; ----------------------------------------------------------------------
502 (define_insn "*v850_clr1_1"
503 [(set (match_operand:QI 0 "memory_operand" "=m")
505 (and:SI (subreg:SI (match_dup 0) 0)
506 (match_operand:QI 1 "not_power_of_two_operand" "")) 0))]
511 xoperands[0] = operands[0];
512 xoperands[1] = GEN_INT (~INTVAL (operands[1]) & 0xff);
513 output_asm_insn (\"clr1 %M1,%0\", xoperands);
516 [(set_attr "length" "4")
517 (set_attr "cc" "clobber")])
519 (define_insn "*v850_clr1_2"
520 [(set (match_operand:HI 0 "indirect_operand" "=m")
522 (and:SI (subreg:SI (match_dup 0) 0)
523 (match_operand:HI 1 "not_power_of_two_operand" "")) 0))]
527 int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffff);
530 xoperands[0] = gen_rtx_MEM (QImode,
531 plus_constant (XEXP (operands[0], 0), log2 / 8));
532 xoperands[1] = GEN_INT (log2 % 8);
533 output_asm_insn (\"clr1 %1,%0\", xoperands);
536 [(set_attr "length" "4")
537 (set_attr "cc" "clobber")])
539 (define_insn "*v850_clr1_3"
540 [(set (match_operand:SI 0 "indirect_operand" "=m")
541 (and:SI (match_dup 0)
542 (match_operand:SI 1 "not_power_of_two_operand" "")))]
546 int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffffffff);
549 xoperands[0] = gen_rtx_MEM (QImode,
550 plus_constant (XEXP (operands[0], 0), log2 / 8));
551 xoperands[1] = GEN_INT (log2 % 8);
552 output_asm_insn (\"clr1 %1,%0\", xoperands);
555 [(set_attr "length" "4")
556 (set_attr "cc" "clobber")])
558 (define_insn "andsi3"
559 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
560 (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
561 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
567 [(set_attr "length" "2,2,4")
568 (set_attr "cc" "set_znv")])
570 ;; ----------------------------------------------------------------------
572 ;; ----------------------------------------------------------------------
574 (define_insn "*v850_set1_1"
575 [(set (match_operand:QI 0 "memory_operand" "=m")
576 (subreg:QI (ior:SI (subreg:SI (match_dup 0) 0)
577 (match_operand 1 "power_of_two_operand" "")) 0))]
580 [(set_attr "length" "4")
581 (set_attr "cc" "clobber")])
583 (define_insn "*v850_set1_2"
584 [(set (match_operand:HI 0 "indirect_operand" "=m")
585 (subreg:HI (ior:SI (subreg:SI (match_dup 0) 0)
586 (match_operand 1 "power_of_two_operand" "")) 0))]
590 int log2 = exact_log2 (INTVAL (operands[1]));
593 return \"set1 %M1,%0\";
597 xoperands[0] = gen_rtx_MEM (QImode,
598 plus_constant (XEXP (operands[0], 0),
600 xoperands[1] = GEN_INT (log2 % 8);
601 output_asm_insn (\"set1 %1,%0\", xoperands);
605 [(set_attr "length" "4")
606 (set_attr "cc" "clobber")])
608 (define_insn "*v850_set1_3"
609 [(set (match_operand:SI 0 "indirect_operand" "=m")
610 (ior:SI (match_dup 0)
611 (match_operand 1 "power_of_two_operand" "")))]
615 int log2 = exact_log2 (INTVAL (operands[1]));
618 return \"set1 %M1,%0\";
622 xoperands[0] = gen_rtx_MEM (QImode,
623 plus_constant (XEXP (operands[0], 0),
625 xoperands[1] = GEN_INT (log2 % 8);
626 output_asm_insn (\"set1 %1,%0\", xoperands);
630 [(set_attr "length" "4")
631 (set_attr "cc" "clobber")])
633 (define_insn "iorsi3"
634 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
635 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
636 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
642 [(set_attr "length" "2,2,4")
643 (set_attr "cc" "set_znv")])
645 ;; ----------------------------------------------------------------------
647 ;; ----------------------------------------------------------------------
649 (define_insn "*v850_not1_1"
650 [(set (match_operand:QI 0 "memory_operand" "=m")
651 (subreg:QI (xor:SI (subreg:SI (match_dup 0) 0)
652 (match_operand 1 "power_of_two_operand" "")) 0))]
655 [(set_attr "length" "4")
656 (set_attr "cc" "clobber")])
658 (define_insn "*v850_not1_2"
659 [(set (match_operand:HI 0 "indirect_operand" "=m")
660 (subreg:HI (xor:SI (subreg:SI (match_dup 0) 0)
661 (match_operand 1 "power_of_two_operand" "")) 0))]
665 int log2 = exact_log2 (INTVAL (operands[1]));
668 return \"not1 %M1,%0\";
672 xoperands[0] = gen_rtx_MEM (QImode,
673 plus_constant (XEXP (operands[0], 0),
675 xoperands[1] = GEN_INT (log2 % 8);
676 output_asm_insn (\"not1 %1,%0\", xoperands);
680 [(set_attr "length" "4")
681 (set_attr "cc" "clobber")])
683 (define_insn "*v850_not1_3"
684 [(set (match_operand:SI 0 "indirect_operand" "=m")
685 (xor:SI (match_dup 0)
686 (match_operand 1 "power_of_two_operand" "")))]
690 int log2 = exact_log2 (INTVAL (operands[1]));
693 return \"not1 %M1,%0\";
697 xoperands[0] = gen_rtx_MEM (QImode,
698 plus_constant (XEXP (operands[0], 0),
700 xoperands[1] = GEN_INT (log2 % 8);
701 output_asm_insn (\"not1 %1,%0\", xoperands);
705 [(set_attr "length" "4")
706 (set_attr "cc" "clobber")])
708 (define_insn "xorsi3"
709 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
710 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
711 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
717 [(set_attr "length" "2,2,4")
718 (set_attr "cc" "set_znv")])
720 ;; ----------------------------------------------------------------------
722 ;; ----------------------------------------------------------------------
724 (define_insn "one_cmplsi2"
725 [(set (match_operand:SI 0 "register_operand" "=r")
726 (not:SI (match_operand:SI 1 "register_operand" "r")))]
729 [(set_attr "length" "2")
730 (set_attr "cc" "set_znv")])
732 ;; -----------------------------------------------------------------
734 ;; -----------------------------------------------------------------
736 ;; ??? Is it worth defining insv and extv for the V850 series?!?
738 ;; An insv pattern would be useful, but does not get used because
739 ;; store_bit_field never calls insv when storing a constant value into a
740 ;; single-bit bitfield.
742 ;; extv/extzv patterns would be useful, but do not get used because
743 ;; optimize_bitfield_compare in fold-const usually converts single
744 ;; bit extracts into an AND with a mask.
746 ;; -----------------------------------------------------------------
748 ;; -----------------------------------------------------------------
751 [(set (match_operand:SI 0 "register_operand" "=r")
752 (le:SI (cc0) (const_int 0)))]
756 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
759 return \"setf le,%0\";
761 [(set_attr "length" "4")
762 (set_attr "cc" "none_0hit")])
765 [(set (match_operand:SI 0 "register_operand" "=r")
766 (leu:SI (cc0) (const_int 0)))]
769 [(set_attr "length" "4")
770 (set_attr "cc" "none_0hit")])
773 [(set (match_operand:SI 0 "register_operand" "=r")
774 (ge:SI (cc0) (const_int 0)))]
778 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
781 return \"setf ge,%0\";
783 [(set_attr "length" "4")
784 (set_attr "cc" "none_0hit")])
787 [(set (match_operand:SI 0 "register_operand" "=r")
788 (geu:SI (cc0) (const_int 0)))]
791 [(set_attr "length" "4")
792 (set_attr "cc" "none_0hit")])
795 [(set (match_operand:SI 0 "register_operand" "=r")
796 (lt:SI (cc0) (const_int 0)))]
800 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
803 return \"setf lt,%0\";
805 [(set_attr "length" "4")
806 (set_attr "cc" "none_0hit")])
809 [(set (match_operand:SI 0 "register_operand" "=r")
810 (ltu:SI (cc0) (const_int 0)))]
813 [(set_attr "length" "4")
814 (set_attr "cc" "none_0hit")])
817 [(set (match_operand:SI 0 "register_operand" "=r")
818 (gt:SI (cc0) (const_int 0)))]
822 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
825 return \"setf gt,%0\";
827 [(set_attr "length" "4")
828 (set_attr "cc" "none_0hit")])
831 [(set (match_operand:SI 0 "register_operand" "=r")
832 (gtu:SI (cc0) (const_int 0)))]
835 [(set_attr "length" "4")
836 (set_attr "cc" "none_0hit")])
839 [(set (match_operand:SI 0 "register_operand" "=r")
840 (eq:SI (cc0) (const_int 0)))]
843 [(set_attr "length" "4")
844 (set_attr "cc" "none_0hit")])
847 [(set (match_operand:SI 0 "register_operand" "=r")
848 (ne:SI (cc0) (const_int 0)))]
851 [(set_attr "length" "4")
852 (set_attr "cc" "none_0hit")])
854 ;; ----------------------------------------------------------------------
855 ;; CONDITIONAL MOVE INSTRUCTIONS
856 ;; ----------------------------------------------------------------------
858 ;; Instructions using cc0 aren't allowed to have input reloads, so we must
859 ;; hide the fact that this instruction uses cc0. We do so by including the
860 ;; compare instruction inside it.
862 ;; ??? This is very ugly. The right way to do this is to modify cmpsi so
863 ;; that it doesn't emit RTL, and then modify the bcc/scc patterns so that
864 ;; they emit RTL for the compare instruction. Unfortunately, this requires
865 ;; lots of changes that will be hard to sanitize. So for now, cmpsi still
866 ;; emits RTL, and I get the compare operands here from the previous insn.
868 (define_expand "movsicc"
869 [(set (match_operand:SI 0 "register_operand" "=r")
871 (match_operator 1 "comparison_operator"
872 [(match_dup 4) (match_dup 5)])
873 (match_operand:SI 2 "reg_or_const_operand" "rJ")
874 (match_operand:SI 3 "reg_or_const_operand" "rI")))]
878 rtx insn = get_last_insn_anywhere ();
881 if ( (GET_CODE (operands[2]) == CONST_INT
882 && GET_CODE (operands[3]) == CONST_INT))
884 int o2 = INTVAL (operands[2]);
885 int o3 = INTVAL (operands[3]);
887 if (o2 == 1 && o3 == 0)
889 if (o3 == 1 && o2 == 0)
891 if (o2 == 0 && (o3 < -16 || o3 > 15) && exact_log2 (o3) >= 0)
892 FAIL; /* setf + shift */
893 if (o3 == 0 && (o2 < -16 || o2 > 15) && exact_log2 (o2) >=0)
894 FAIL; /* setf + shift */
896 operands[2] = copy_to_mode_reg (SImode, operands[2]);
898 operands[3] = copy_to_mode_reg (SImode, operands[3]);
902 if (GET_CODE (operands[2]) != REG)
903 operands[2] = copy_to_mode_reg (SImode,operands[2]);
904 if (GET_CODE (operands[3]) != REG)
905 operands[3] = copy_to_mode_reg (SImode, operands[3]);
907 gcc_assert (GET_CODE (insn) == INSN
908 && GET_CODE (PATTERN (insn)) == SET
909 && SET_DEST (PATTERN (insn)) == cc0_rtx);
911 src = SET_SRC (PATTERN (insn));
913 switch (GET_CODE (src))
916 operands[4] = XEXP (src, 0);
917 operands[5] = XEXP (src, 1);
923 operands[5] = const0_rtx;
931 ;; ??? Clobbering the condition codes is overkill.
933 ;; ??? We sometimes emit an unnecessary compare instruction because the
934 ;; condition codes may have already been set by an earlier instruction,
935 ;; but we have no code here to avoid the compare if it is unnecessary.
937 (define_insn "*movsicc_normal"
938 [(set (match_operand:SI 0 "register_operand" "=r")
940 (match_operator 1 "comparison_operator"
941 [(match_operand:SI 4 "register_operand" "r")
942 (match_operand:SI 5 "reg_or_int5_operand" "rJ")])
943 (match_operand:SI 2 "reg_or_int5_operand" "rJ")
944 (match_operand:SI 3 "reg_or_0_operand" "rI")))]
946 "cmp %5,%4 ; cmov %c1,%2,%z3,%0"
947 [(set_attr "length" "6")
948 (set_attr "cc" "clobber")])
950 (define_insn "*movsicc_reversed"
951 [(set (match_operand:SI 0 "register_operand" "=r")
953 (match_operator 1 "comparison_operator"
954 [(match_operand:SI 4 "register_operand" "r")
955 (match_operand:SI 5 "reg_or_int5_operand" "rJ")])
956 (match_operand:SI 2 "reg_or_0_operand" "rI")
957 (match_operand:SI 3 "reg_or_int5_operand" "rJ")))]
959 "cmp %5,%4 ; cmov %C1,%3,%z2,%0"
960 [(set_attr "length" "6")
961 (set_attr "cc" "clobber")])
963 (define_insn "*movsicc_tst1"
964 [(set (match_operand:SI 0 "register_operand" "=r")
966 (match_operator 1 "comparison_operator"
968 (match_operand:QI 2 "memory_operand" "m")
970 (match_operand 3 "const_int_operand" "n"))
972 (match_operand:SI 4 "reg_or_int5_operand" "rJ")
973 (match_operand:SI 5 "reg_or_0_operand" "rI")))]
975 "tst1 %3,%2 ; cmov %c1,%4,%z5,%0"
976 [(set_attr "length" "8")
977 (set_attr "cc" "clobber")])
979 (define_insn "*movsicc_tst1_reversed"
980 [(set (match_operand:SI 0 "register_operand" "=r")
982 (match_operator 1 "comparison_operator"
984 (match_operand:QI 2 "memory_operand" "m")
986 (match_operand 3 "const_int_operand" "n"))
988 (match_operand:SI 4 "reg_or_0_operand" "rI")
989 (match_operand:SI 5 "reg_or_int5_operand" "rJ")))]
991 "tst1 %3,%2 ; cmov %C1,%5,%z4,%0"
992 [(set_attr "length" "8")
993 (set_attr "cc" "clobber")])
995 ;; Matching for sasf requires combining 4 instructions, so we provide a
996 ;; dummy pattern to match the first 3, which will always be turned into the
997 ;; second pattern by subsequent combining. As above, we must include the
998 ;; comparison to avoid input reloads in an insn using cc0.
1000 (define_insn "*sasf_1"
1001 [(set (match_operand:SI 0 "register_operand" "")
1002 (ior:SI (match_operator 1 "comparison_operator" [(cc0) (const_int 0)])
1003 (ashift:SI (match_operand:SI 2 "register_operand" "")
1006 "* gcc_unreachable ();")
1008 (define_insn "*sasf_2"
1009 [(set (match_operand:SI 0 "register_operand" "=r")
1011 (match_operator 1 "comparison_operator"
1012 [(match_operand:SI 3 "register_operand" "r")
1013 (match_operand:SI 4 "reg_or_int5_operand" "rJ")])
1014 (ashift:SI (match_operand:SI 2 "register_operand" "0")
1017 "cmp %4,%3 ; sasf %c1,%0"
1018 [(set_attr "length" "6")
1019 (set_attr "cc" "clobber")])
1022 [(set (match_operand:SI 0 "register_operand" "")
1024 (match_operator 1 "comparison_operator"
1025 [(match_operand:SI 4 "register_operand" "")
1026 (match_operand:SI 5 "reg_or_int5_operand" "")])
1027 (match_operand:SI 2 "const_int_operand" "")
1028 (match_operand:SI 3 "const_int_operand" "")))]
1030 && ((INTVAL (operands[2]) ^ INTVAL (operands[3])) == 1)
1031 && ((INTVAL (operands[2]) + INTVAL (operands[3])) != 1)
1032 && (GET_CODE (operands[5]) == CONST_INT
1033 || REGNO (operands[0]) != REGNO (operands[5]))
1034 && REGNO (operands[0]) != REGNO (operands[4])"
1035 [(set (match_dup 0) (match_dup 6))
1037 (ior:SI (match_op_dup 7 [(match_dup 4) (match_dup 5)])
1038 (ashift:SI (match_dup 0) (const_int 1))))]
1041 operands[6] = GEN_INT (INTVAL (operands[2]) >> 1);
1042 if (INTVAL (operands[2]) & 0x1)
1043 operands[7] = operands[1];
1045 operands[7] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])),
1046 GET_MODE (operands[1]),
1047 XEXP (operands[1], 0), XEXP (operands[1], 1));
1049 ;; ---------------------------------------------------------------------
1050 ;; BYTE SWAP INSTRUCTIONS
1051 ;; ---------------------------------------------------------------------
1053 (define_expand "rotlhi3"
1054 [(set (match_operand:HI 0 "register_operand" "")
1055 (rotate:HI (match_operand:HI 1 "register_operand" "")
1056 (match_operand:HI 2 "const_int_operand" "")))]
1060 if (INTVAL (operands[2]) != 8)
1064 (define_insn "*rotlhi3_8"
1065 [(set (match_operand:HI 0 "register_operand" "=r")
1066 (rotate:HI (match_operand:HI 1 "register_operand" "r")
1070 [(set_attr "length" "4")
1071 (set_attr "cc" "clobber")])
1073 (define_expand "rotlsi3"
1074 [(set (match_operand:SI 0 "register_operand" "")
1075 (rotate:SI (match_operand:SI 1 "register_operand" "")
1076 (match_operand:SI 2 "const_int_operand" "")))]
1080 if (INTVAL (operands[2]) != 16)
1084 (define_insn "*rotlsi3_16"
1085 [(set (match_operand:SI 0 "register_operand" "=r")
1086 (rotate:SI (match_operand:SI 1 "register_operand" "r")
1090 [(set_attr "length" "4")
1091 (set_attr "cc" "clobber")])
1093 ;; ----------------------------------------------------------------------
1094 ;; JUMP INSTRUCTIONS
1095 ;; ----------------------------------------------------------------------
1097 ;; Conditional jump instructions
1099 (define_expand "ble"
1101 (if_then_else (le (cc0)
1103 (label_ref (match_operand 0 "" ""))
1108 (define_expand "bleu"
1110 (if_then_else (leu (cc0)
1112 (label_ref (match_operand 0 "" ""))
1117 (define_expand "bge"
1119 (if_then_else (ge (cc0)
1121 (label_ref (match_operand 0 "" ""))
1126 (define_expand "bgeu"
1128 (if_then_else (geu (cc0)
1130 (label_ref (match_operand 0 "" ""))
1135 (define_expand "blt"
1137 (if_then_else (lt (cc0)
1139 (label_ref (match_operand 0 "" ""))
1144 (define_expand "bltu"
1146 (if_then_else (ltu (cc0)
1148 (label_ref (match_operand 0 "" ""))
1153 (define_expand "bgt"
1155 (if_then_else (gt (cc0)
1157 (label_ref (match_operand 0 "" ""))
1162 (define_expand "bgtu"
1164 (if_then_else (gtu (cc0)
1166 (label_ref (match_operand 0 "" ""))
1171 (define_expand "beq"
1173 (if_then_else (eq (cc0)
1175 (label_ref (match_operand 0 "" ""))
1180 (define_expand "bne"
1182 (if_then_else (ne (cc0)
1184 (label_ref (match_operand 0 "" ""))
1189 (define_insn "*branch_normal"
1191 (if_then_else (match_operator 1 "comparison_operator"
1192 [(cc0) (const_int 0)])
1193 (label_ref (match_operand 0 "" ""))
1198 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1199 && (GET_CODE (operands[1]) == GT
1200 || GET_CODE (operands[1]) == GE
1201 || GET_CODE (operands[1]) == LE
1202 || GET_CODE (operands[1]) == LT))
1205 if (get_attr_length (insn) == 2)
1206 return \"b%b1 %l0\";
1208 return \"b%B1 .+6 ; jr %l0\";
1210 [(set (attr "length")
1211 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1215 (set_attr "cc" "none")])
1217 (define_insn "*branch_invert"
1219 (if_then_else (match_operator 1 "comparison_operator"
1220 [(cc0) (const_int 0)])
1222 (label_ref (match_operand 0 "" ""))))]
1226 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1227 && (GET_CODE (operands[1]) == GT
1228 || GET_CODE (operands[1]) == GE
1229 || GET_CODE (operands[1]) == LE
1230 || GET_CODE (operands[1]) == LT))
1232 if (get_attr_length (insn) == 2)
1233 return \"b%B1 %l0\";
1235 return \"b%b1 .+6 ; jr %l0\";
1237 [(set (attr "length")
1238 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1242 (set_attr "cc" "none")])
1244 ;; Unconditional and other jump instructions.
1248 (label_ref (match_operand 0 "" "")))]
1252 if (get_attr_length (insn) == 2)
1257 [(set (attr "length")
1258 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1262 (set_attr "cc" "none")])
1264 (define_insn "indirect_jump"
1265 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1268 [(set_attr "length" "2")
1269 (set_attr "cc" "none")])
1271 (define_insn "tablejump"
1272 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1273 (use (label_ref (match_operand 1 "" "")))]
1276 [(set_attr "length" "2")
1277 (set_attr "cc" "none")])
1279 (define_insn "switch"
1284 (plus:SI (ashift:SI (match_operand:SI 0 "register_operand" "r")
1286 (label_ref (match_operand 1 "" "")))))
1287 (label_ref (match_dup 1))))]
1290 [(set_attr "length" "2")
1291 (set_attr "cc" "none")])
1293 (define_expand "casesi"
1294 [(match_operand:SI 0 "register_operand" "")
1295 (match_operand:SI 1 "register_operand" "")
1296 (match_operand:SI 2 "register_operand" "")
1297 (match_operand 3 "" "") (match_operand 4 "" "")]
1301 rtx reg = gen_reg_rtx (SImode);
1302 rtx tableaddress = gen_reg_rtx (SImode);
1305 /* Subtract the lower bound from the index. */
1306 emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
1307 /* Compare the result against the number of table entries. */
1308 emit_insn (gen_cmpsi (reg, operands[2]));
1309 /* Branch to the default label if out of range of the table. */
1310 emit_jump_insn (gen_bgtu (operands[4]));
1312 if (! TARGET_BIG_SWITCH && TARGET_V850E)
1314 emit_jump_insn (gen_switch (reg, operands[3]));
1318 /* Shift index for the table array access. */
1319 emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1)));
1320 /* Load the table address into a pseudo. */
1321 emit_insn (gen_movsi (tableaddress,
1322 gen_rtx_LABEL_REF (Pmode, operands[3])));
1323 /* Add the table address to the index. */
1324 emit_insn (gen_addsi3 (reg, reg, tableaddress));
1325 /* Load the table entry. */
1326 mem = gen_const_mem (CASE_VECTOR_MODE, reg);
1327 if (! TARGET_BIG_SWITCH)
1329 rtx reg2 = gen_reg_rtx (HImode);
1330 emit_insn (gen_movhi (reg2, mem));
1331 emit_insn (gen_extendhisi2 (reg, reg2));
1334 emit_insn (gen_movsi (reg, mem));
1335 /* Add the table address. */
1336 emit_insn (gen_addsi3 (reg, reg, tableaddress));
1337 /* Branch to the switch label. */
1338 emit_jump_insn (gen_tablejump (reg, operands[3]));
1342 ;; Call subroutine with no return value.
1344 (define_expand "call"
1345 [(call (match_operand:QI 0 "general_operand" "")
1346 (match_operand:SI 1 "general_operand" ""))]
1350 if (! call_address_operand (XEXP (operands[0], 0), QImode)
1351 || TARGET_LONG_CALLS)
1352 XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
1353 if (TARGET_LONG_CALLS)
1354 emit_call_insn (gen_call_internal_long (XEXP (operands[0], 0), operands[1]));
1356 emit_call_insn (gen_call_internal_short (XEXP (operands[0], 0), operands[1]));
1361 (define_insn "call_internal_short"
1362 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
1363 (match_operand:SI 1 "general_operand" "g,g"))
1364 (clobber (reg:SI 31))]
1365 "! TARGET_LONG_CALLS"
1368 jarl .+4,r31 ; add 4,r31 ; jmp %0"
1369 [(set_attr "length" "4,8")]
1372 (define_insn "call_internal_long"
1373 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
1374 (match_operand:SI 1 "general_operand" "g,g"))
1375 (clobber (reg:SI 31))]
1379 if (which_alternative == 0)
1381 if (GET_CODE (operands[0]) == REG)
1382 return \"jarl %0,r31\";
1384 return \"movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11\";
1387 return \"jarl .+4,r31 ; add 4,r31 ; jmp %0\";
1389 [(set_attr "length" "16,8")]
1392 ;; Call subroutine, returning value in operand 0
1393 ;; (which must be a hard register).
1395 (define_expand "call_value"
1396 [(set (match_operand 0 "" "")
1397 (call (match_operand:QI 1 "general_operand" "")
1398 (match_operand:SI 2 "general_operand" "")))]
1402 if (! call_address_operand (XEXP (operands[1], 0), QImode)
1403 || TARGET_LONG_CALLS)
1404 XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
1405 if (TARGET_LONG_CALLS)
1406 emit_call_insn (gen_call_value_internal_long (operands[0],
1407 XEXP (operands[1], 0),
1410 emit_call_insn (gen_call_value_internal_short (operands[0],
1411 XEXP (operands[1], 0),
1416 (define_insn "call_value_internal_short"
1417 [(set (match_operand 0 "" "=r,r")
1418 (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
1419 (match_operand:SI 2 "general_operand" "g,g")))
1420 (clobber (reg:SI 31))]
1421 "! TARGET_LONG_CALLS"
1424 jarl .+4,r31 ; add 4,r31 ; jmp %1"
1425 [(set_attr "length" "4,8")]
1428 (define_insn "call_value_internal_long"
1429 [(set (match_operand 0 "" "=r,r")
1430 (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
1431 (match_operand:SI 2 "general_operand" "g,g")))
1432 (clobber (reg:SI 31))]
1436 if (which_alternative == 0)
1438 if (GET_CODE (operands[1]) == REG)
1439 return \"jarl %1, r31\";
1441 /* Reload can generate this pattern.... */
1442 return \"movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11\";
1445 return \"jarl .+4, r31 ; add 4, r31 ; jmp %1\";
1447 [(set_attr "length" "16,8")]
1454 [(set_attr "length" "2")
1455 (set_attr "cc" "none")])
1457 ;; ----------------------------------------------------------------------
1458 ;; EXTEND INSTRUCTIONS
1459 ;; ----------------------------------------------------------------------
1462 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1464 (match_operand:HI 1 "nonimmediate_operand" "0,r,T,m")))]
1471 [(set_attr "length" "2,4,2,4")
1472 (set_attr "cc" "none_0hit,set_znv,none_0hit,none_0hit")])
1474 (define_insn "zero_extendhisi2"
1475 [(set (match_operand:SI 0 "register_operand" "=r")
1477 (match_operand:HI 1 "register_operand" "r")))]
1480 [(set_attr "length" "4")
1481 (set_attr "cc" "set_znv")])
1484 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1486 (match_operand:QI 1 "nonimmediate_operand" "0,r,T,m")))]
1493 [(set_attr "length" "2,4,2,4")
1494 (set_attr "cc" "none_0hit,set_znv,none_0hit,none_0hit")])
1496 (define_insn "zero_extendqisi2"
1497 [(set (match_operand:SI 0 "register_operand" "=r")
1499 (match_operand:QI 1 "register_operand" "r")))]
1502 [(set_attr "length" "4")
1503 (set_attr "cc" "set_znv")])
1505 ;;- sign extension instructions
1507 ;; ??? The extendhisi2 pattern should not emit shifts for v850e?
1509 (define_insn "*extendhisi_insn"
1510 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1511 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,Q,m")))]
1517 [(set_attr "length" "2,2,4")
1518 (set_attr "cc" "none_0hit,none_0hit,none_0hit")])
1520 ;; ??? This is missing a sign extend from memory pattern to match the ld.h
1523 (define_expand "extendhisi2"
1525 (ashift:SI (match_operand:HI 1 "register_operand" "")
1527 (set (match_operand:SI 0 "register_operand" "")
1528 (ashiftrt:SI (match_dup 2)
1533 operands[1] = gen_lowpart (SImode, operands[1]);
1534 operands[2] = gen_reg_rtx (SImode);
1537 ;; ??? The extendqisi2 pattern should not emit shifts for v850e?
1539 (define_insn "*extendqisi_insn"
1540 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1541 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,Q,m")))]
1547 [(set_attr "length" "2,2,4")
1548 (set_attr "cc" "none_0hit,none_0hit,none_0hit")])
1550 ;; ??? This is missing a sign extend from memory pattern to match the ld.b
1553 (define_expand "extendqisi2"
1555 (ashift:SI (match_operand:QI 1 "register_operand" "")
1557 (set (match_operand:SI 0 "register_operand" "")
1558 (ashiftrt:SI (match_dup 2)
1563 operands[1] = gen_lowpart (SImode, operands[1]);
1564 operands[2] = gen_reg_rtx (SImode);
1567 ;; ----------------------------------------------------------------------
1569 ;; ----------------------------------------------------------------------
1571 (define_insn "ashlsi3"
1572 [(set (match_operand:SI 0 "register_operand" "=r,r")
1574 (match_operand:SI 1 "register_operand" "0,0")
1575 (match_operand:SI 2 "nonmemory_operand" "r,N")))]
1580 [(set_attr "length" "4,2")
1581 (set_attr "cc" "set_znv")])
1583 (define_insn "lshrsi3"
1584 [(set (match_operand:SI 0 "register_operand" "=r,r")
1586 (match_operand:SI 1 "register_operand" "0,0")
1587 (match_operand:SI 2 "nonmemory_operand" "r,N")))]
1592 [(set_attr "length" "4,2")
1593 (set_attr "cc" "set_znv")])
1595 (define_insn "ashrsi3"
1596 [(set (match_operand:SI 0 "register_operand" "=r,r")
1598 (match_operand:SI 1 "register_operand" "0,0")
1599 (match_operand:SI 2 "nonmemory_operand" "r,N")))]
1604 [(set_attr "length" "4,2")
1605 (set_attr "cc" "set_znv")])
1607 ;; ----------------------------------------------------------------------
1608 ;; PROLOGUE/EPILOGUE
1609 ;; ----------------------------------------------------------------------
1610 (define_expand "prologue"
1613 "expand_prologue (); DONE;")
1615 (define_expand "epilogue"
1620 /* Try to use the trivial return first. Else use the
1623 emit_jump_insn (gen_return ());
1629 (define_insn "return"
1631 "reload_completed && compute_frame_size (get_frame_size (), (long *)0) == 0"
1633 [(set_attr "length" "2")
1634 (set_attr "cc" "none")])
1636 (define_insn "return_internal"
1641 [(set_attr "length" "2")
1642 (set_attr "cc" "none")])
1646 ;; ----------------------------------------------------------------------
1647 ;; HELPER INSTRUCTIONS for saving the prologue and epilog registers
1648 ;; ----------------------------------------------------------------------
1650 ;; This pattern will match a stack adjust RTX followed by any number of push
1651 ;; RTXs. These RTXs will then be turned into a suitable call to a worker
1655 ;; Actually, convert the RTXs into a PREPARE instruction.
1658 [(match_parallel 0 "pattern_is_ok_for_prepare"
1660 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1661 (set (mem:SI (plus:SI (reg:SI 3)
1662 (match_operand:SI 2 "immediate_operand" "i")))
1663 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
1664 "TARGET_PROLOG_FUNCTION && TARGET_V850E"
1665 "* return construct_prepare_instruction (operands[0]);
1667 [(set_attr "length" "4")
1668 (set_attr "cc" "none")])
1671 [(match_parallel 0 "pattern_is_ok_for_prologue"
1673 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1674 (set (mem:SI (plus:SI (reg:SI 3)
1675 (match_operand:SI 2 "immediate_operand" "i")))
1676 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
1677 "TARGET_PROLOG_FUNCTION && TARGET_V850"
1678 "* return construct_save_jarl (operands[0]);
1680 [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
1682 (const_string "4")))
1683 (set_attr "cc" "clobber")])
1686 ;; Actually, turn the RTXs into a DISPOSE instruction.
1689 [(match_parallel 0 "pattern_is_ok_for_dispose"
1692 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1693 (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r")
1694 (mem:SI (plus:SI (reg:SI 3)
1695 (match_operand:SI 3 "immediate_operand" "i"))))])]
1696 "TARGET_PROLOG_FUNCTION && TARGET_V850E"
1697 "* return construct_dispose_instruction (operands[0]);
1699 [(set_attr "length" "4")
1700 (set_attr "cc" "none")])
1702 ;; This pattern will match a return RTX followed by any number of pop RTXs
1703 ;; and possible a stack adjustment as well. These RTXs will be turned into
1704 ;; a suitable call to a worker function.
1707 [(match_parallel 0 "pattern_is_ok_for_epilogue"
1710 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1711 (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r")
1712 (mem:SI (plus:SI (reg:SI 3)
1713 (match_operand:SI 3 "immediate_operand" "i"))))])]
1714 "TARGET_PROLOG_FUNCTION && TARGET_V850"
1715 "* return construct_restore_jr (operands[0]);
1717 [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
1719 (const_string "4")))
1720 (set_attr "cc" "clobber")])
1722 ;; Initialize an interrupt function. Do not depend on TARGET_PROLOG_FUNCTION.
1723 (define_insn "callt_save_interrupt"
1724 [(unspec_volatile [(const_int 0)] 2)]
1725 "TARGET_V850E && !TARGET_DISABLE_CALLT"
1726 ;; The CALLT instruction stores the next address of CALLT to CTPC register
1727 ;; without saving its previous value. So if the interrupt handler
1728 ;; or its caller could possibly execute the CALLT insn, save_interrupt
1729 ;; MUST NOT be called via CALLT.
1732 output_asm_insn (\"addi -24, sp, sp\", operands);
1733 output_asm_insn (\"st.w r10, 12[sp]\", operands);
1734 output_asm_insn (\"stsr ctpc, r10\", operands);
1735 output_asm_insn (\"st.w r10, 16[sp]\", operands);
1736 output_asm_insn (\"stsr ctpsw, r10\", operands);
1737 output_asm_insn (\"st.w r10, 20[sp]\", operands);
1738 output_asm_insn (\"callt ctoff(__callt_save_interrupt)\", operands);
1741 [(set_attr "length" "26")
1742 (set_attr "cc" "none")])
1744 (define_insn "callt_return_interrupt"
1745 [(unspec_volatile [(const_int 0)] 3)]
1746 "TARGET_V850E && !TARGET_DISABLE_CALLT"
1747 "callt ctoff(__callt_return_interrupt)"
1748 [(set_attr "length" "2")
1749 (set_attr "cc" "clobber")])
1751 (define_insn "save_interrupt"
1752 [(set (reg:SI 3) (plus:SI (reg:SI 3) (const_int -16)))
1753 (set (mem:SI (plus:SI (reg:SI 3) (const_int -16))) (reg:SI 30))
1754 (set (mem:SI (plus:SI (reg:SI 3) (const_int -12))) (reg:SI 4))
1755 (set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 1))
1756 (set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 10))]
1760 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
1761 return \"add -16,sp\;st.w r10,12[sp]\;jarl __save_interrupt,r10\";
1764 output_asm_insn (\"add -16, sp\", operands);
1765 output_asm_insn (\"st.w r10, 12[sp]\", operands);
1766 output_asm_insn (\"st.w ep, 0[sp]\", operands);
1767 output_asm_insn (\"st.w gp, 4[sp]\", operands);
1768 output_asm_insn (\"st.w r1, 8[sp]\", operands);
1769 output_asm_insn (\"movhi hi(__ep), r0, ep\", operands);
1770 output_asm_insn (\"movea lo(__ep), ep, ep\", operands);
1771 output_asm_insn (\"movhi hi(__gp), r0, gp\", operands);
1772 output_asm_insn (\"movea lo(__gp), gp, gp\", operands);
1776 [(set (attr "length")
1777 (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0))
1780 (set_attr "cc" "clobber")])
1782 ;; Restore r1, r4, r10, and return from the interrupt
1783 (define_insn "return_interrupt"
1785 (set (reg:SI 3) (plus:SI (reg:SI 3) (const_int 16)))
1786 (set (reg:SI 10) (mem:SI (plus:SI (reg:SI 3) (const_int 12))))
1787 (set (reg:SI 1) (mem:SI (plus:SI (reg:SI 3) (const_int 8))))
1788 (set (reg:SI 4) (mem:SI (plus:SI (reg:SI 3) (const_int 4))))
1789 (set (reg:SI 30) (mem:SI (reg:SI 3)))]
1793 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
1794 return \"jr __return_interrupt\";
1797 output_asm_insn (\"ld.w 0[sp], ep\", operands);
1798 output_asm_insn (\"ld.w 4[sp], gp\", operands);
1799 output_asm_insn (\"ld.w 8[sp], r1\", operands);
1800 output_asm_insn (\"ld.w 12[sp], r10\", operands);
1801 output_asm_insn (\"addi 16, sp, sp\", operands);
1802 output_asm_insn (\"reti\", operands);
1806 [(set (attr "length")
1807 (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0))
1810 (set_attr "cc" "clobber")])
1812 ;; Save all registers except for the registers saved in save_interrupt when
1813 ;; an interrupt function makes a call.
1814 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1815 ;; all of memory. This blocks insns from being moved across this point.
1816 ;; This is needed because the rest of the compiler is not ready to handle
1817 ;; insns this complicated.
1819 (define_insn "callt_save_all_interrupt"
1820 [(unspec_volatile [(const_int 0)] 0)]
1821 "TARGET_V850E && !TARGET_DISABLE_CALLT"
1822 "callt ctoff(__callt_save_all_interrupt)"
1823 [(set_attr "length" "2")
1824 (set_attr "cc" "none")])
1826 (define_insn "save_all_interrupt"
1827 [(unspec_volatile [(const_int 0)] 0)]
1831 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
1832 return \"jarl __save_all_interrupt,r10\";
1834 output_asm_insn (\"addi -120, sp, sp\", operands);
1835 output_asm_insn (\"mov ep, r1\", operands);
1836 output_asm_insn (\"mov sp, ep\", operands);
1837 output_asm_insn (\"sst.w r31, 116[ep]\", operands);
1838 output_asm_insn (\"sst.w r2, 112[ep]\", operands);
1839 output_asm_insn (\"sst.w gp, 108[ep]\", operands);
1840 output_asm_insn (\"sst.w r6, 104[ep]\", operands);
1841 output_asm_insn (\"sst.w r7, 100[ep]\", operands);
1842 output_asm_insn (\"sst.w r8, 96[ep]\", operands);
1843 output_asm_insn (\"sst.w r9, 92[ep]\", operands);
1844 output_asm_insn (\"sst.w r11, 88[ep]\", operands);
1845 output_asm_insn (\"sst.w r12, 84[ep]\", operands);
1846 output_asm_insn (\"sst.w r13, 80[ep]\", operands);
1847 output_asm_insn (\"sst.w r14, 76[ep]\", operands);
1848 output_asm_insn (\"sst.w r15, 72[ep]\", operands);
1849 output_asm_insn (\"sst.w r16, 68[ep]\", operands);
1850 output_asm_insn (\"sst.w r17, 64[ep]\", operands);
1851 output_asm_insn (\"sst.w r18, 60[ep]\", operands);
1852 output_asm_insn (\"sst.w r19, 56[ep]\", operands);
1853 output_asm_insn (\"sst.w r20, 52[ep]\", operands);
1854 output_asm_insn (\"sst.w r21, 48[ep]\", operands);
1855 output_asm_insn (\"sst.w r22, 44[ep]\", operands);
1856 output_asm_insn (\"sst.w r23, 40[ep]\", operands);
1857 output_asm_insn (\"sst.w r24, 36[ep]\", operands);
1858 output_asm_insn (\"sst.w r25, 32[ep]\", operands);
1859 output_asm_insn (\"sst.w r26, 28[ep]\", operands);
1860 output_asm_insn (\"sst.w r27, 24[ep]\", operands);
1861 output_asm_insn (\"sst.w r28, 20[ep]\", operands);
1862 output_asm_insn (\"sst.w r29, 16[ep]\", operands);
1863 output_asm_insn (\"mov r1, ep\", operands);
1866 [(set (attr "length")
1867 (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0))
1871 (set_attr "cc" "clobber")])
1873 (define_insn "_save_all_interrupt"
1874 [(unspec_volatile [(const_int 0)] 0)]
1875 "TARGET_V850 && ! TARGET_LONG_CALLS"
1876 "jarl __save_all_interrupt,r10"
1877 [(set_attr "length" "4")
1878 (set_attr "cc" "clobber")])
1880 ;; Restore all registers saved when an interrupt function makes a call.
1881 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1882 ;; all of memory. This blocks insns from being moved across this point.
1883 ;; This is needed because the rest of the compiler is not ready to handle
1884 ;; insns this complicated.
1886 (define_insn "callt_restore_all_interrupt"
1887 [(unspec_volatile [(const_int 0)] 1)]
1888 "TARGET_V850E && !TARGET_DISABLE_CALLT"
1889 "callt ctoff(__callt_restore_all_interrupt)"
1890 [(set_attr "length" "2")
1891 (set_attr "cc" "none")])
1893 (define_insn "restore_all_interrupt"
1894 [(unspec_volatile [(const_int 0)] 1)]
1898 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
1899 return \"jarl __restore_all_interrupt,r10\";
1902 output_asm_insn (\"mov ep, r1\", operands);
1903 output_asm_insn (\"mov sp, ep\", operands);
1904 output_asm_insn (\"sld.w 116[ep], r31\", operands);
1905 output_asm_insn (\"sld.w 112[ep], r2\", operands);
1906 output_asm_insn (\"sld.w 108[ep], gp\", operands);
1907 output_asm_insn (\"sld.w 104[ep], r6\", operands);
1908 output_asm_insn (\"sld.w 100[ep], r7\", operands);
1909 output_asm_insn (\"sld.w 96[ep], r8\", operands);
1910 output_asm_insn (\"sld.w 92[ep], r9\", operands);
1911 output_asm_insn (\"sld.w 88[ep], r11\", operands);
1912 output_asm_insn (\"sld.w 84[ep], r12\", operands);
1913 output_asm_insn (\"sld.w 80[ep], r13\", operands);
1914 output_asm_insn (\"sld.w 76[ep], r14\", operands);
1915 output_asm_insn (\"sld.w 72[ep], r15\", operands);
1916 output_asm_insn (\"sld.w 68[ep], r16\", operands);
1917 output_asm_insn (\"sld.w 64[ep], r17\", operands);
1918 output_asm_insn (\"sld.w 60[ep], r18\", operands);
1919 output_asm_insn (\"sld.w 56[ep], r19\", operands);
1920 output_asm_insn (\"sld.w 52[ep], r20\", operands);
1921 output_asm_insn (\"sld.w 48[ep], r21\", operands);
1922 output_asm_insn (\"sld.w 44[ep], r22\", operands);
1923 output_asm_insn (\"sld.w 40[ep], r23\", operands);
1924 output_asm_insn (\"sld.w 36[ep], r24\", operands);
1925 output_asm_insn (\"sld.w 32[ep], r25\", operands);
1926 output_asm_insn (\"sld.w 28[ep], r26\", operands);
1927 output_asm_insn (\"sld.w 24[ep], r27\", operands);
1928 output_asm_insn (\"sld.w 20[ep], r28\", operands);
1929 output_asm_insn (\"sld.w 16[ep], r29\", operands);
1930 output_asm_insn (\"mov r1, ep\", operands);
1931 output_asm_insn (\"addi 120, sp, sp\", operands);
1935 [(set (attr "length")
1936 (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0))
1940 (set_attr "cc" "clobber")])
1942 (define_insn "_restore_all_interrupt"
1943 [(unspec_volatile [(const_int 0)] 1)]
1944 "TARGET_V850 && ! TARGET_LONG_CALLS"
1945 "jarl __restore_all_interrupt,r10"
1946 [(set_attr "length" "4")
1947 (set_attr "cc" "clobber")])
1949 ;; Save r6-r9 for a variable argument function
1950 (define_insn "save_r6_r9_v850e"
1951 [(set (mem:SI (reg:SI 3)) (reg:SI 6))
1952 (set (mem:SI (plus:SI (reg:SI 3) (const_int 4))) (reg:SI 7))
1953 (set (mem:SI (plus:SI (reg:SI 3) (const_int 8))) (reg:SI 8))
1954 (set (mem:SI (plus:SI (reg:SI 3) (const_int 12))) (reg:SI 9))
1956 "TARGET_PROLOG_FUNCTION && TARGET_V850E && !TARGET_DISABLE_CALLT"
1957 "callt ctoff(__callt_save_r6_r9)"
1958 [(set_attr "length" "2")
1959 (set_attr "cc" "none")])
1961 (define_insn "save_r6_r9"
1962 [(set (mem:SI (reg:SI 3)) (reg:SI 6))
1963 (set (mem:SI (plus:SI (reg:SI 3) (const_int 4))) (reg:SI 7))
1964 (set (mem:SI (plus:SI (reg:SI 3) (const_int 8))) (reg:SI 8))
1965 (set (mem:SI (plus:SI (reg:SI 3) (const_int 12))) (reg:SI 9))
1966 (clobber (reg:SI 10))]
1967 "TARGET_PROLOG_FUNCTION && ! TARGET_LONG_CALLS"
1968 "jarl __save_r6_r9,r10"
1969 [(set_attr "length" "4")
1970 (set_attr "cc" "clobber")])