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1 /* Definitions of target machine for GNU compiler, for IBM S/390
2 Copyright (C) 1999-2014 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com).
5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
12 version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
23 #ifndef _S390_H
24 #define _S390_H
26 /* Optional architectural facilities supported by the processor. */
28 enum processor_flags
29 {
39 };
41 /* This is necessary to avoid a warning about comparing different enum
42 types. */
43 #define s390_tune_attr ((enum attr_cpu)s390_tune)
45 /* These flags indicate that the generated code should run on a cpu
46 providing the respective hardware facility regardless of the
47 current cpu mode (ESA or z/Architecture). */
49 #define TARGET_CPU_IEEE_FLOAT \
50 (s390_arch_flags & PF_IEEE_FLOAT)
51 #define TARGET_CPU_ZARCH \
52 (s390_arch_flags & PF_ZARCH)
53 #define TARGET_CPU_LONG_DISPLACEMENT \
54 (s390_arch_flags & PF_LONG_DISPLACEMENT)
55 #define TARGET_CPU_EXTIMM \
56 (s390_arch_flags & PF_EXTIMM)
57 #define TARGET_CPU_DFP \
58 (s390_arch_flags & PF_DFP)
59 #define TARGET_CPU_Z10 \
60 (s390_arch_flags & PF_Z10)
61 #define TARGET_CPU_Z196 \
62 (s390_arch_flags & PF_Z196)
63 #define TARGET_CPU_ZEC12 \
64 (s390_arch_flags & PF_ZEC12)
65 #define TARGET_CPU_HTM \
66 (s390_arch_flags & PF_TX)
68 /* These flags indicate that the generated code should run on a cpu
69 providing the respective hardware facility when run in
70 z/Architecture mode. */
72 #define TARGET_LONG_DISPLACEMENT \
73 (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT)
74 #define TARGET_EXTIMM \
75 (TARGET_ZARCH && TARGET_CPU_EXTIMM)
76 #define TARGET_DFP \
77 (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT)
78 #define TARGET_Z10 \
79 (TARGET_ZARCH && TARGET_CPU_Z10)
80 #define TARGET_Z196 \
81 (TARGET_ZARCH && TARGET_CPU_Z196)
82 #define TARGET_ZEC12 \
83 (TARGET_ZARCH && TARGET_CPU_ZEC12)
84 #define TARGET_HTM (TARGET_OPT_HTM)
87 #define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196)
89 /* Run-time target specification. */
91 /* Defaults for option flags defined only on some subtargets. */
92 #ifndef TARGET_TPF_PROFILING
93 #define TARGET_TPF_PROFILING 0
94 #endif
96 /* This will be overridden by OS headers. */
97 #define TARGET_TPF 0
99 /* Target CPU builtins. */
100 #define TARGET_CPU_CPP_BUILTINS() \
101 do \
102 { \
106 if (TARGET_ZARCH) \
108 if (TARGET_64BIT) \
110 if (TARGET_LONG_DOUBLE_128) \
112 if (TARGET_HTM) \
114 } \
115 while (0)
117 #ifdef DEFAULT_TARGET_64BIT
118 #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP | MASK_OPT_HTM)
119 #else
120 #define TARGET_DEFAULT 0
121 #endif
123 /* Support for configure-time defaults. */
124 #define OPTION_DEFAULT_SPECS \
129 /* Defaulting rules. */
130 #ifdef DEFAULT_TARGET_64BIT
131 #define DRIVER_SELF_SPECS \
134 "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
135 #else
136 #define DRIVER_SELF_SPECS \
139 "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
140 #endif
142 /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */
143 #define S390_TDC_POSITIVE_ZERO (1 << 11)
144 #define S390_TDC_NEGATIVE_ZERO (1 << 10)
145 #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER (1 << 9)
146 #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER (1 << 8)
147 #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7)
148 #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6)
149 #define S390_TDC_POSITIVE_INFINITY (1 << 5)
150 #define S390_TDC_NEGATIVE_INFINITY (1 << 4)
151 #define S390_TDC_POSITIVE_QUIET_NAN (1 << 3)
152 #define S390_TDC_NEGATIVE_QUIET_NAN (1 << 2)
153 #define S390_TDC_POSITIVE_SIGNALING_NAN (1 << 1)
154 #define S390_TDC_NEGATIVE_SIGNALING_NAN (1 << 0)
156 /* The following values are different for DFP. */
157 #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9)
158 #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8)
159 #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7)
160 #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6)
162 /* For signbit, the BFP-DFP-difference makes no difference. */
163 #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \
164 | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \
165 | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\
166 | S390_TDC_NEGATIVE_INFINITY \
167 | S390_TDC_NEGATIVE_QUIET_NAN \
168 | S390_TDC_NEGATIVE_SIGNALING_NAN )
170 #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \
171 | S390_TDC_NEGATIVE_INFINITY )
173 /* This is used by float.h to define the float_t and double_t data
174 types. For historical reasons both are double on s390 what cannot
175 be changed anymore. */
176 #define TARGET_FLT_EVAL_METHOD 1
178 /* Target machine storage layout. */
180 /* Everything is big-endian. */
181 #define BITS_BIG_ENDIAN 1
182 #define BYTES_BIG_ENDIAN 1
183 #define WORDS_BIG_ENDIAN 1
185 #define STACK_SIZE_MODE (Pmode)
187 #ifndef IN_LIBGCC2
189 /* Width of a word, in units (bytes). */
190 #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4)
192 /* Width of a pointer. To be used instead of UNITS_PER_WORD in
193 ABI-relevant contexts. This always matches
194 GET_MODE_SIZE (Pmode). */
195 #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4)
196 #define MIN_UNITS_PER_WORD 4
197 #define MAX_BITS_PER_WORD 64
198 #else
200 /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether
201 the library should export TImode functions or not. Thus, we have
202 to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */
203 #ifdef __s390x__
204 #define UNITS_PER_WORD 8
205 #else
206 #define UNITS_PER_WORD 4
207 #endif
208 #endif
210 /* Width of a pointer, in bits. */
211 #define POINTER_SIZE (TARGET_64BIT ? 64 : 32)
213 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
214 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
216 /* Boundary (in *bits*) on which stack pointer should be aligned. */
217 #define STACK_BOUNDARY 64
219 /* Allocation boundary (in *bits*) for the code of a function. */
220 #define FUNCTION_BOUNDARY 64
222 /* There is no point aligning anything to a rounder boundary than this. */
223 #define BIGGEST_ALIGNMENT 64
225 /* Alignment of field after `int : 0' in a structure. */
226 #define EMPTY_FIELD_BOUNDARY 32
228 /* Alignment on even addresses for LARL instruction. */
229 #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
230 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
232 /* Alignment is not required by the hardware. */
233 #define STRICT_ALIGNMENT 0
235 /* Mode of stack savearea.
236 FUNCTION is VOIDmode because calling convention maintains SP.
237 BLOCK needs Pmode for SP.
238 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
239 #define STACK_SAVEAREA_MODE(LEVEL) \
240 (LEVEL == SAVE_FUNCTION ? VOIDmode \
241 : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode)
244 /* Type layout. */
246 /* Sizes in bits of the source language data types. */
247 #define SHORT_TYPE_SIZE 16
248 #define INT_TYPE_SIZE 32
249 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32)
250 #define LONG_LONG_TYPE_SIZE 64
251 #define FLOAT_TYPE_SIZE 32
252 #define DOUBLE_TYPE_SIZE 64
253 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64)
255 /* Work around target_flags dependency in ada/targtyps.c. */
256 #define WIDEST_HARDWARE_FP_SIZE 64
258 /* We use "unsigned char" as default. */
259 #define DEFAULT_SIGNED_CHAR 0
262 /* Register usage. */
264 /* We have 16 general purpose registers (registers 0-15),
265 and 16 floating point registers (registers 16-31).
266 (On non-IEEE machines, we have only 4 fp registers.)
268 Amongst the general purpose registers, some are used
269 for specific purposes:
270 GPR 11: Hard frame pointer (if needed)
271 GPR 12: Global offset table pointer (if needed)
272 GPR 13: Literal pool base register
273 GPR 14: Return address register
274 GPR 15: Stack pointer
276 Registers 32-35 are 'fake' hard registers that do not
277 correspond to actual hardware:
278 Reg 32: Argument pointer
279 Reg 33: Condition code
280 Reg 34: Frame pointer
281 Reg 35: Return address pointer
283 Registers 36 and 37 are mapped to access registers
284 0 and 1, used to implement thread-local storage. */
286 #define FIRST_PSEUDO_REGISTER 38
288 /* Standard register usage. */
289 #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16)
290 #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16)
291 #define FP_REGNO_P(N) ((N) >= 16 && (N) < 32)
292 #define CC_REGNO_P(N) ((N) == 33)
293 #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35)
294 #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37)
296 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
297 #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X)))
298 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
299 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
300 #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X)))
301 #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X)))
303 /* Set up fixed registers and calling convention:
305 GPRs 0-5 are always call-clobbered,
306 GPRs 6-15 are always call-saved.
307 GPR 12 is fixed if used as GOT pointer.
308 GPR 13 is always fixed (as literal pool pointer).
309 GPR 14 is always fixed on S/390 machines (as return address).
310 GPR 15 is always fixed (as stack pointer).
311 The 'fake' hard registers are call-clobbered and fixed.
312 The access registers are call-saved and fixed.
314 On 31-bit, FPRs 18-19 are call-clobbered;
315 on 64-bit, FPRs 24-31 are call-clobbered.
316 The remaining FPRs are call-saved. */
318 #define FIXED_REGISTERS \
319 { 0, 0, 0, 0, \
320 0, 0, 0, 0, \
321 0, 0, 0, 0, \
322 0, 1, 1, 1, \
323 0, 0, 0, 0, \
324 0, 0, 0, 0, \
325 0, 0, 0, 0, \
326 0, 0, 0, 0, \
327 1, 1, 1, 1, \
328 1, 1 }
330 #define CALL_USED_REGISTERS \
331 { 1, 1, 1, 1, \
332 1, 1, 0, 0, \
333 0, 0, 0, 0, \
334 0, 1, 1, 1, \
335 1, 1, 1, 1, \
336 1, 1, 1, 1, \
337 1, 1, 1, 1, \
338 1, 1, 1, 1, \
339 1, 1, 1, 1, \
340 1, 1 }
342 #define CALL_REALLY_USED_REGISTERS \
343 { 1, 1, 1, 1, \
344 1, 1, 0, 0, \
345 0, 0, 0, 0, \
346 0, 0, 0, 0, \
347 1, 1, 1, 1, \
348 1, 1, 1, 1, \
349 1, 1, 1, 1, \
350 1, 1, 1, 1, \
351 1, 1, 1, 1, \
352 0, 0 }
354 /* Preferred register allocation order. */
355 #define REG_ALLOC_ORDER \
356 { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \
357 16, 17, 18, 19, 20, 21, 22, 23, \
358 24, 25, 26, 27, 28, 29, 30, 31, \
359 15, 32, 33, 34, 35, 36, 37 }
362 /* Fitting values into registers. */
364 /* Integer modes <= word size fit into any GPR.
365 Integer modes > word size fit into successive GPRs, starting with
366 an even-numbered register.
367 SImode and DImode fit into FPRs as well.
369 Floating point modes <= word size fit into any FPR or GPR.
370 Floating point modes > word size (i.e. DFmode on 32-bit) fit
371 into any FPR, or an even-odd GPR pair.
372 TFmode fits only into an even-odd FPR pair.
374 Complex floating point modes fit either into two FPRs, or into
375 successive GPRs (again starting with an even number).
376 TCmode fits only into two successive even-odd FPR pairs.
378 Condition code modes fit only into the CC register. */
380 /* Because all registers in a class have the same size HARD_REGNO_NREGS
381 is equivalent to CLASS_MAX_NREGS. */
382 #define HARD_REGNO_NREGS(REGNO, MODE) \
383 s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE))
385 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
386 s390_hard_regno_mode_ok ((REGNO), (MODE))
388 #define HARD_REGNO_RENAME_OK(FROM, TO) \
389 s390_hard_regno_rename_ok (FROM, TO)
391 #define MODES_TIEABLE_P(MODE1, MODE2) \
392 (((MODE1) == SFmode || (MODE1) == DFmode) \
393 == ((MODE2) == SFmode || (MODE2) == DFmode))
395 /* When generating code that runs in z/Architecture mode,
396 but conforms to the 31-bit ABI, GPRs can hold 8 bytes;
397 the ABI guarantees only that the lower 4 bytes are
398 saved across calls, however. */
399 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
400 (!TARGET_64BIT && TARGET_ZARCH \
401 && GET_MODE_SIZE (MODE) > 4 \
402 && (((REGNO) >= 6 && (REGNO) <= 15) || (REGNO) == 32))
404 /* Maximum number of registers to represent a value of mode MODE
405 in a register of class CLASS. */
406 #define CLASS_MAX_NREGS(CLASS, MODE) \
407 s390_class_max_nregs ((CLASS), (MODE))
409 /* If a 4-byte value is loaded into a FPR, it is placed into the
410 *upper* half of the register, not the lower. Therefore, we
411 cannot use SUBREGs to switch between modes in FP registers.
412 Likewise for access registers, since they have only half the
413 word size on 64-bit. */
414 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
415 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
416 ? ((reg_classes_intersect_p (FP_REGS, CLASS) \
417 && (GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8)) \
418 || reg_classes_intersect_p (ACCESS_REGS, CLASS)) : 0)
420 /* Register classes. */
422 /* We use the following register classes:
423 GENERAL_REGS All general purpose registers
424 ADDR_REGS All general purpose registers except %r0
425 (These registers can be used in address generation)
426 FP_REGS All floating point registers
427 CC_REGS The condition code register
428 ACCESS_REGS The access registers
430 GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS
431 ADDR_FP_REGS Union of ADDR_REGS and FP_REGS
432 GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS
433 ADDR_CC_REGS Union of ADDR_REGS and CC_REGS
435 NO_REGS No registers
436 ALL_REGS All registers
438 Note that the 'fake' frame pointer and argument pointer registers
439 are included amongst the address registers here. */
441 enum reg_class
442 {
446 ALL_REGS, LIM_REG_CLASSES
447 };
448 #define N_REG_CLASSES (int) LIM_REG_CLASSES
450 #define REG_CLASS_NAMES \
455 /* Class -> register mapping. */
456 #define REG_CLASS_CONTENTS \
457 { \
469 }
471 /* In some case register allocation order is not enough for IRA to
472 generate a good code. The following macro (if defined) increases
473 cost of REGNO for a pseudo approximately by pseudo usage frequency
474 multiplied by the macro value.
476 We avoid usage of BASE_REGNUM by nonzero macro value because the
477 reload can decide not to use the hard register because some
478 constant was forced to be in memory. */
479 #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) \
480 (regno == BASE_REGNUM ? 0.0 : 0.5)
482 /* Register -> class mapping. */
484 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
486 /* ADDR_REGS can be used as base or index register. */
487 #define INDEX_REG_CLASS ADDR_REGS
488 #define BASE_REG_CLASS ADDR_REGS
490 /* Check whether REGNO is a hard register of the suitable class
491 or a pseudo register currently allocated to one such. */
492 #define REGNO_OK_FOR_INDEX_P(REGNO) \
493 (((REGNO) < FIRST_PSEUDO_REGISTER \
494 && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \
495 || ADDR_REGNO_P (reg_renumber[REGNO]))
496 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
499 /* We need secondary memory to move data between GPRs and FPRs. With
500 DFP the ldgr lgdr instructions are available. But these
501 instructions do not handle GPR pairs so it is not possible for 31
502 bit. */
503 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
504 ((CLASS1) != (CLASS2) \
505 && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS) \
506 && (!TARGET_DFP || !TARGET_64BIT || GET_MODE_SIZE (MODE) != 8))
508 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
509 because the movsi and movsf patterns don't handle r/f moves. */
510 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
511 (GET_MODE_BITSIZE (MODE) < 32 \
512 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
513 : MODE)
516 /* Stack layout and calling conventions. */
518 /* Our stack grows from higher to lower addresses. However, local variables
519 are accessed by positive offsets, and function arguments are stored at
520 increasing addresses. */
521 #define STACK_GROWS_DOWNWARD
522 #define FRAME_GROWS_DOWNWARD 1
523 /* #undef ARGS_GROW_DOWNWARD */
525 /* The basic stack layout looks like this: the stack pointer points
526 to the register save area for called functions. Above that area
527 is the location to place outgoing arguments. Above those follow
528 dynamic allocations (alloca), and finally the local variables. */
530 /* Offset from stack-pointer to first location of outgoing args. */
531 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96)
533 /* Offset within stack frame to start allocating local variables at. */
534 #define STARTING_FRAME_OFFSET 0
536 /* Offset from the stack pointer register to an item dynamically
537 allocated on the stack, e.g., by `alloca'. */
538 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
539 (STACK_POINTER_OFFSET + crtl->outgoing_args_size)
541 /* Offset of first parameter from the argument pointer register value.
542 We have a fake argument pointer register that points directly to
543 the argument area. */
544 #define FIRST_PARM_OFFSET(FNDECL) 0
546 /* Defining this macro makes __builtin_frame_address(0) and
547 __builtin_return_address(0) work with -fomit-frame-pointer. */
548 #define INITIAL_FRAME_ADDRESS_RTX \
549 (plus_constant (Pmode, arg_pointer_rtx, -STACK_POINTER_OFFSET))
551 /* The return address of the current frame is retrieved
552 from the initial value of register RETURN_REGNUM.
553 For frames farther back, we use the stack slot where
554 the corresponding RETURN_REGNUM register was saved. */
555 #define DYNAMIC_CHAIN_ADDRESS(FRAME) \
556 (TARGET_PACKED_STACK ? \
557 plus_constant (Pmode, (FRAME), \
558 STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME))
560 /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of
561 builtin_frame_address. Otherwise arg pointer -
562 STACK_POINTER_OFFSET would be returned for
563 __builtin_frame_address(0) what might result in an address pointing
564 somewhere into the middle of the local variables since the packed
565 stack layout generally does not need all the bytes in the register
566 save area. */
567 #define FRAME_ADDR_RTX(FRAME) \
568 DYNAMIC_CHAIN_ADDRESS ((FRAME))
570 #define RETURN_ADDR_RTX(COUNT, FRAME) \
571 s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
573 /* In 31-bit mode, we need to mask off the high bit of return addresses. */
574 #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff))
577 /* Exception handling. */
579 /* Describe calling conventions for DWARF-2 exception handling. */
580 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM)
581 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
582 #define DWARF_FRAME_RETURN_COLUMN 14
584 /* Describe how we implement __builtin_eh_return. */
585 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM)
586 #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx)
588 /* Select a format to encode pointers in exception handling data. */
589 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
590 (flag_pic \
591 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
592 : DW_EH_PE_absptr)
594 /* Register save slot alignment. */
595 #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG)
597 /* Let the assembler generate debug line info. */
598 #define DWARF2_ASM_LINE_DEBUG_INFO 1
601 /* Frame registers. */
603 #define STACK_POINTER_REGNUM 15
604 #define FRAME_POINTER_REGNUM 34
605 #define HARD_FRAME_POINTER_REGNUM 11
606 #define ARG_POINTER_REGNUM 32
607 #define RETURN_ADDRESS_POINTER_REGNUM 35
609 /* The static chain must be call-clobbered, but not used for
610 function argument passing. As register 1 is clobbered by
611 the trampoline code, we only have one option. */
612 #define STATIC_CHAIN_REGNUM 0
614 /* Number of hardware registers that go into the DWARF-2 unwind info.
615 To avoid ABI incompatibility, this number must not change even as
616 'fake' hard registers are added or removed. */
617 #define DWARF_FRAME_REGISTERS 34
620 /* Frame pointer and argument pointer elimination. */
622 #define ELIMINABLE_REGS \
623 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
624 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
625 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
626 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
627 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
628 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
629 { BASE_REGNUM, BASE_REGNUM }}
631 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
632 (OFFSET) = s390_initial_elimination_offset ((FROM), (TO))
635 /* Stack arguments. */
637 /* We need current_function_outgoing_args to be valid. */
638 #define ACCUMULATE_OUTGOING_ARGS 1
641 /* Register arguments. */
644 {
647 }
648 CUMULATIVE_ARGS;
650 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \
651 ((CUM).gprs=0, (CUM).fprs=0)
653 /* Arguments can be placed in general registers 2 to 6, or in floating
654 point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64
655 bit. */
656 #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \
657 (N) == 16 || (N) == 17 || (TARGET_64BIT && ((N) == 18 || (N) == 19)))
660 /* Only gpr 2 and fpr 0 are ever used as return registers. */
661 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16)
664 /* Function entry and exit. */
666 /* When returning from a function, the stack pointer does not matter. */
667 #define EXIT_IGNORE_STACK 1
670 /* Profiling. */
672 #define FUNCTION_PROFILER(FILE, LABELNO) \
673 s390_function_profiler ((FILE), ((LABELNO)))
675 #define PROFILE_BEFORE_PROLOGUE 1
678 /* Trampolines for nested functions. */
680 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16)
681 #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD
683 /* Addressing modes, and classification of registers for them. */
685 /* Recognize any constant value that is a valid address. */
686 #define CONSTANT_ADDRESS_P(X) 0
688 /* Maximum number of registers that can appear in a valid memory address. */
689 #define MAX_REGS_PER_ADDRESS 2
691 /* This definition replaces the formerly used 'm' constraint with a
692 different constraint letter in order to avoid changing semantics of
693 the 'm' constraint when accepting new address formats in
694 TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here
695 must not be used in insn definitions or inline assemblies. */
698 /* Try a machine-dependent way of reloading an illegitimate address
699 operand. If we find one, push the reload and jump to WIN. This
700 macro is used in only one place: `find_reloads_address' in reload.c. */
701 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
702 do { \
703 rtx new_rtx = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE)); \
704 if (new_rtx) \
705 { \
706 (AD) = new_rtx; \
707 goto WIN; \
708 } \
709 } while (0)
711 /* Helper macro for s390.c and s390.md to check for symbolic constants. */
712 #define SYMBOLIC_CONST(X) \
713 (GET_CODE (X) == SYMBOL_REF \
714 || GET_CODE (X) == LABEL_REF \
715 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
717 #define TLS_SYMBOLIC_CONST(X) \
718 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \
719 || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X)))
722 /* Condition codes. */
724 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
725 return the mode to be used for the comparison. */
726 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
728 /* Relative costs of operations. */
730 /* A C expression for the cost of a branch instruction. A value of 1
731 is the default; other values are interpreted relative to that. */
732 #define BRANCH_COST(speed_p, predictable_p) s390_branch_cost
734 /* Nonzero if access to memory by bytes is slow and undesirable. */
735 #define SLOW_BYTE_ACCESS 1
737 /* An integer expression for the size in bits of the largest integer machine
738 mode that should actually be used. We allow pairs of registers. */
739 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
741 /* The maximum number of bytes that a single instruction can move quickly
742 between memory and registers or between two memory locations. */
743 #define MOVE_MAX (TARGET_ZARCH ? 16 : 8)
744 #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4)
745 #define MAX_MOVE_MAX 16
747 /* Don't perform CSE on function addresses. */
748 #define NO_FUNCTION_CSE
750 /* This value is used in tree-sra to decide whether it might benefical
751 to split a struct move into several word-size moves. For S/390
752 only small values make sense here since struct moves are relatively
753 cheap thanks to mvc so the small default value chosen for archs
754 with memmove patterns should be ok. But this value is multiplied
755 in tree-sra with UNITS_PER_WORD to make a decision so we adjust it
756 here to compensate for that factor since mvc costs exactly the same
757 on 31 and 64 bit. */
758 #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4)
761 /* Sections. */
763 /* Output before read-only data. */
766 /* Output before writable (initialized) data. */
769 /* Output before writable (uninitialized) data. */
772 /* S/390 constant pool breaks the devices in crtstuff.c to control section
773 in where code resides. We have to write it as asm code. */
774 #ifndef __s390x__
775 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
782 #endif
785 /* Position independent code. */
787 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM)
789 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
792 /* Assembler file format. */
794 /* Character to start a comment. */
797 /* Declare an uninitialized external linkage data object. */
798 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
799 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
801 /* Globalizing directive for a label. */
804 /* Advance the location counter to a multiple of 2**LOG bytes. */
805 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
808 /* Advance the location counter by SIZE bytes. */
809 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
812 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */
815 #define LABEL_ALIGN(LABEL) \
816 s390_label_align (LABEL)
818 /* How to refer to registers in assembler output. This sequence is
819 indexed by compiler's hard-register-number (see above). */
820 #define REGISTER_NAMES \
826 }
828 /* Print operand X (an rtx) in assembler syntax to file FILE. */
829 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
830 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
832 /* Output an element of a case-vector that is absolute. */
833 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
834 do { \
835 char buf[32]; \
836 fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \
838 assemble_name ((FILE), buf); \
840 } while (0)
842 /* Output an element of a case-vector that is relative. */
843 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
844 do { \
845 char buf[32]; \
846 fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \
848 assemble_name ((FILE), buf); \
851 assemble_name ((FILE), buf); \
853 } while (0)
855 /* Mark the return register as used by the epilogue so that we can
856 use it in unadorned (return) and (simple_return) instructions. */
857 #define EPILOGUE_USES(REGNO) ((REGNO) == RETURN_REGNUM)
859 #undef ASM_OUTPUT_FUNCTION_LABEL
860 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \
861 s390_asm_output_function_label (FILE, NAME, DECL)
863 /* Miscellaneous parameters. */
865 /* Specify the machine mode that this machine uses for the index in the
866 tablejump instruction. */
867 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
869 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
870 is done just by pretending it is already truncated. */
871 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
873 /* Specify the machine mode that pointers have.
874 After generation of rtl, the compiler makes no further distinction
875 between pointers and any other objects of this machine mode. */
876 #define Pmode ((machine_mode) (TARGET_64BIT ? DImode : SImode))
878 /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */
879 #define POINTERS_EXTEND_UNSIGNED -1
881 /* A function address in a call instruction is a byte address (for
882 indexing purposes) so give the MEM rtx a byte's mode. */
883 #define FUNCTION_MODE QImode
885 /* Specify the value which is used when clz operand is zero. */
886 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1)
888 /* Machine-specific symbol_ref flags. */
889 #define SYMBOL_FLAG_ALIGN1 (SYMBOL_FLAG_MACH_DEP << 0)
890 #define SYMBOL_REF_ALIGN1_P(X) \
891 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1))
892 #define SYMBOL_FLAG_NOT_NATURALLY_ALIGNED (SYMBOL_FLAG_MACH_DEP << 1)
893 #define SYMBOL_REF_NOT_NATURALLY_ALIGNED_P(X) \
894 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_NOT_NATURALLY_ALIGNED))
896 /* Check whether integer displacement is in range. */
897 #define DISP_IN_RANGE(d) \
898 (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \
899 : ((d) >= 0 && (d) <= 4095))
901 /* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c. */
902 #define READ_CAN_USE_WRITE_PREFETCH 1
905 #endif