1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992-2014 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "stor-layout.h"
31 #include "stringpool.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
47 #include "insn-codes.h"
49 #include "diagnostic-core.h"
50 #include "c-family/c-pragma.h" /* ??? */
52 #include "tm-constrs.h"
55 #include "target-def.h"
56 #include "dominance.h"
62 #include "cfgcleanup.h"
64 #include "basic-block.h"
68 /* Classifies a h8300_src_operand or h8300_dst_operand.
71 A constant operand of some sort.
77 A memory reference with a constant address.
80 A memory reference with a register as its address.
83 Some other kind of memory reference. */
84 enum h8300_operand_class
94 /* For a general two-operand instruction, element [X][Y] gives
95 the length of the opcode fields when the first operand has class
96 (X + 1) and the second has class Y. */
97 typedef unsigned char h8300_length_table
[NUM_H8OPS
- 1][NUM_H8OPS
];
99 /* Forward declarations. */
100 static const char *byte_reg (rtx
, int);
101 static int h8300_interrupt_function_p (tree
);
102 static int h8300_saveall_function_p (tree
);
103 static int h8300_monitor_function_p (tree
);
104 static int h8300_os_task_function_p (tree
);
105 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT
, bool);
106 static HOST_WIDE_INT
round_frame_size (HOST_WIDE_INT
);
107 static unsigned int compute_saved_regs (void);
108 static const char *cond_string (enum rtx_code
);
109 static unsigned int h8300_asm_insn_count (const char *);
110 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
111 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
112 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
113 static void h8300_print_operand_address (FILE *, rtx
);
114 static void h8300_print_operand (FILE *, rtx
, int);
115 static bool h8300_print_operand_punct_valid_p (unsigned char code
);
116 #ifndef OBJECT_FORMAT_ELF
117 static void h8300_asm_named_section (const char *, unsigned int, tree
);
119 static int h8300_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
120 static int h8300_and_costs (rtx
);
121 static int h8300_shift_costs (rtx
);
122 static void h8300_push_pop (int, int, bool, bool);
123 static int h8300_stack_offset_p (rtx
, int);
124 static int h8300_ldm_stm_regno (rtx
, int, int, int);
125 static void h8300_reorg (void);
126 static unsigned int h8300_constant_length (rtx
);
127 static unsigned int h8300_displacement_length (rtx
, int);
128 static unsigned int h8300_classify_operand (rtx
, int, enum h8300_operand_class
*);
129 static unsigned int h8300_length_from_table (rtx
, rtx
, const h8300_length_table
*);
130 static unsigned int h8300_unary_length (rtx
);
131 static unsigned int h8300_short_immediate_length (rtx
);
132 static unsigned int h8300_bitfield_length (rtx
, rtx
);
133 static unsigned int h8300_binary_length (rtx_insn
*, const h8300_length_table
*);
134 static bool h8300_short_move_mem_p (rtx
, enum rtx_code
);
135 static unsigned int h8300_move_length (rtx
*, const h8300_length_table
*);
136 static bool h8300_hard_regno_scratch_ok (unsigned int);
137 static rtx
h8300_get_index (rtx
, machine_mode mode
, int *);
139 /* CPU_TYPE, says what cpu we're compiling for. */
142 /* True if a #pragma interrupt has been seen for the current function. */
143 static int pragma_interrupt
;
145 /* True if a #pragma saveall has been seen for the current function. */
146 static int pragma_saveall
;
148 static const char *const names_big
[] =
149 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
151 static const char *const names_extended
[] =
152 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
154 static const char *const names_upper_extended
[] =
155 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
157 /* Points to one of the above. */
158 /* ??? The above could be put in an array indexed by CPU_TYPE. */
159 const char * const *h8_reg_names
;
161 /* Various operations needed by the following, indexed by CPU_TYPE. */
163 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
165 /* Value of MOVE_RATIO. */
166 int h8300_move_ratio
;
168 /* See below where shifts are handled for explanation of this enum. */
178 /* Symbols of the various shifts which can be used as indices. */
182 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
185 /* Macros to keep the shift algorithm tables small. */
186 #define INL SHIFT_INLINE
187 #define ROT SHIFT_ROT_AND
188 #define LOP SHIFT_LOOP
189 #define SPC SHIFT_SPECIAL
191 /* The shift algorithms for each machine, mode, shift type, and shift
192 count are defined below. The three tables below correspond to
193 QImode, HImode, and SImode, respectively. Each table is organized
194 by, in the order of indices, machine, shift type, and shift count. */
196 static enum shift_alg shift_alg_qi
[3][3][8] = {
199 /* 0 1 2 3 4 5 6 7 */
200 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
201 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
202 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
206 /* 0 1 2 3 4 5 6 7 */
207 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
208 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
209 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
213 /* 0 1 2 3 4 5 6 7 */
214 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
215 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
216 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
220 static enum shift_alg shift_alg_hi
[3][3][16] = {
223 /* 0 1 2 3 4 5 6 7 */
224 /* 8 9 10 11 12 13 14 15 */
225 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
226 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
227 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
228 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
229 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
230 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
234 /* 0 1 2 3 4 5 6 7 */
235 /* 8 9 10 11 12 13 14 15 */
236 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
237 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
238 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
239 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
240 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
241 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
245 /* 0 1 2 3 4 5 6 7 */
246 /* 8 9 10 11 12 13 14 15 */
247 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
248 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
249 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
250 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
251 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
252 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
256 static enum shift_alg shift_alg_si
[3][3][32] = {
259 /* 0 1 2 3 4 5 6 7 */
260 /* 8 9 10 11 12 13 14 15 */
261 /* 16 17 18 19 20 21 22 23 */
262 /* 24 25 26 27 28 29 30 31 */
263 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
264 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
265 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
266 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
267 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
268 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
269 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
270 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
271 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
272 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
273 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
274 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
278 /* 0 1 2 3 4 5 6 7 */
279 /* 8 9 10 11 12 13 14 15 */
280 /* 16 17 18 19 20 21 22 23 */
281 /* 24 25 26 27 28 29 30 31 */
282 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
283 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
284 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
285 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
286 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
287 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
288 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
289 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
290 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
291 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
292 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
293 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
297 /* 0 1 2 3 4 5 6 7 */
298 /* 8 9 10 11 12 13 14 15 */
299 /* 16 17 18 19 20 21 22 23 */
300 /* 24 25 26 27 28 29 30 31 */
301 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
302 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
303 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
304 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
305 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
306 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
307 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
308 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
309 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
310 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
311 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
312 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
328 /* Initialize various cpu specific globals at start up. */
331 h8300_option_override (void)
333 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
334 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
335 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
337 #ifndef OBJECT_FORMAT_ELF
340 error ("-msx is not supported in coff");
341 target_flags
|= MASK_H8300S
;
347 cpu_type
= (int) CPU_H8300
;
348 h8_reg_names
= names_big
;
352 /* For this we treat the H8/300H and H8S the same. */
353 cpu_type
= (int) CPU_H8300H
;
354 h8_reg_names
= names_extended
;
356 h8_push_op
= h8_push_ops
[cpu_type
];
357 h8_pop_op
= h8_pop_ops
[cpu_type
];
358 h8_mov_op
= h8_mov_ops
[cpu_type
];
360 if (!TARGET_H8300S
&& TARGET_MAC
)
362 error ("-ms2600 is used without -ms");
363 target_flags
|= MASK_H8300S_1
;
366 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
368 error ("-mn is used without -mh or -ms or -msx");
369 target_flags
^= MASK_NORMAL_MODE
;
372 if (! TARGET_H8300S
&& TARGET_EXR
)
374 error ("-mexr is used without -ms");
375 target_flags
|= MASK_H8300S_1
;
378 if (TARGET_H8300
&& TARGET_INT32
)
380 error ("-mint32 is not supported for H8300 and H8300L targets");
381 target_flags
^= MASK_INT32
;
384 if ((!TARGET_H8300S
&& TARGET_EXR
) && (!TARGET_H8300SX
&& TARGET_EXR
))
386 error ("-mexr is used without -ms or -msx");
387 target_flags
|= MASK_H8300S_1
;
390 if ((!TARGET_H8300S
&& TARGET_NEXR
) && (!TARGET_H8300SX
&& TARGET_NEXR
))
392 warning (OPT_mno_exr
, "-mno-exr valid only with -ms or -msx \
396 /* Some of the shifts are optimized for speed by default.
397 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
398 If optimizing for size, change shift_alg for those shift to
403 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
404 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
405 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
406 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
408 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
409 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
411 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
412 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
415 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
416 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
418 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
419 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
421 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
422 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
423 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
424 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
427 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
430 /* Work out a value for MOVE_RATIO. */
433 /* Memory-memory moves are quite expensive without the
434 h8sx instructions. */
435 h8300_move_ratio
= 3;
437 else if (flag_omit_frame_pointer
)
439 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
440 sometimes be as short as two individual memory-to-memory moves,
441 but since they use all the call-saved registers, it seems better
442 to allow up to three moves here. */
443 h8300_move_ratio
= 4;
445 else if (optimize_size
)
447 /* In this case we don't use movmd sequences since they tend
448 to be longer than calls to memcpy(). Memory-to-memory
449 moves are cheaper than for !TARGET_H8300SX, so it makes
450 sense to have a slightly higher threshold. */
451 h8300_move_ratio
= 4;
455 /* We use movmd sequences for some moves since it can be quicker
456 than calling memcpy(). The sequences will need to save and
457 restore er6 though, so bump up the cost. */
458 h8300_move_ratio
= 6;
461 /* This target defaults to strict volatile bitfields. */
462 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
463 flag_strict_volatile_bitfields
= 1;
466 /* Return the byte register name for a register rtx X. B should be 0
467 if you want a lower byte register. B should be 1 if you want an
468 upper byte register. */
471 byte_reg (rtx x
, int b
)
473 static const char *const names_small
[] = {
474 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
475 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
478 gcc_assert (REG_P (x
));
480 return names_small
[REGNO (x
) * 2 + b
];
483 /* REGNO must be saved/restored across calls if this macro is true. */
485 #define WORD_REG_USED(regno) \
487 /* No need to save registers if this function will not return. */ \
488 && ! TREE_THIS_VOLATILE (current_function_decl) \
489 && (h8300_saveall_function_p (current_function_decl) \
490 /* Save any call saved register that was used. */ \
491 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
492 /* Save the frame pointer if it was used. */ \
493 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
494 /* Save any register used in an interrupt handler. */ \
495 || (h8300_current_function_interrupt_function_p () \
496 && df_regs_ever_live_p (regno)) \
497 /* Save call clobbered registers in non-leaf interrupt \
499 || (h8300_current_function_interrupt_function_p () \
500 && call_used_regs[regno] \
503 /* We use this to wrap all emitted insns in the prologue. */
505 F (rtx_insn
*x
, bool set_it
)
508 RTX_FRAME_RELATED_P (x
) = 1;
512 /* Mark all the subexpressions of the PARALLEL rtx PAR as
513 frame-related. Return PAR.
515 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
516 PARALLEL rtx other than the first if they do not have the
517 FRAME_RELATED flag set on them. */
521 int len
= XVECLEN (par
, 0);
524 for (i
= 0; i
< len
; i
++)
525 F (as_a
<rtx_insn
*> (XVECEXP (par
, 0, i
)), true);
530 /* Output assembly language to FILE for the operation OP with operand size
531 SIZE to adjust the stack pointer. */
534 h8300_emit_stack_adjustment (int sign
, HOST_WIDE_INT size
, bool in_prologue
)
536 /* If the frame size is 0, we don't have anything to do. */
540 /* H8/300 cannot add/subtract a large constant with a single
541 instruction. If a temporary register is available, load the
542 constant to it and then do the addition. */
545 && !h8300_current_function_interrupt_function_p ()
546 && !(cfun
->static_chain_decl
!= NULL
&& sign
< 0))
548 rtx r3
= gen_rtx_REG (Pmode
, 3);
549 F (emit_insn (gen_movhi (r3
, GEN_INT (sign
* size
))), in_prologue
);
550 F (emit_insn (gen_addhi3 (stack_pointer_rtx
,
551 stack_pointer_rtx
, r3
)), in_prologue
);
555 /* The stack adjustment made here is further optimized by the
556 splitter. In case of H8/300, the splitter always splits the
557 addition emitted here to make the adjustment interrupt-safe.
558 FIXME: We don't always tag those, because we don't know what
559 the splitter will do. */
562 rtx_insn
*x
= emit_insn (gen_addhi3 (stack_pointer_rtx
,
564 GEN_INT (sign
* size
)));
569 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
570 stack_pointer_rtx
, GEN_INT (sign
* size
))), in_prologue
);
574 /* Round up frame size SIZE. */
577 round_frame_size (HOST_WIDE_INT size
)
579 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
580 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
583 /* Compute which registers to push/pop.
584 Return a bit vector of registers. */
587 compute_saved_regs (void)
589 unsigned int saved_regs
= 0;
592 /* Construct a bit vector of registers to be pushed/popped. */
593 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
595 if (WORD_REG_USED (regno
))
596 saved_regs
|= 1 << regno
;
599 /* Don't push/pop the frame pointer as it is treated separately. */
600 if (frame_pointer_needed
)
601 saved_regs
&= ~(1 << HARD_FRAME_POINTER_REGNUM
);
606 /* Emit an insn to push register RN. */
611 rtx reg
= gen_rtx_REG (word_mode
, rn
);
615 x
= gen_push_h8300 (reg
);
616 else if (!TARGET_NORMAL_MODE
)
617 x
= gen_push_h8300hs_advanced (reg
);
619 x
= gen_push_h8300hs_normal (reg
);
620 x
= F (emit_insn (x
), true);
621 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
625 /* Emit an insn to pop register RN. */
630 rtx reg
= gen_rtx_REG (word_mode
, rn
);
634 x
= gen_pop_h8300 (reg
);
635 else if (!TARGET_NORMAL_MODE
)
636 x
= gen_pop_h8300hs_advanced (reg
);
638 x
= gen_pop_h8300hs_normal (reg
);
640 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
644 /* Emit an instruction to push or pop NREGS consecutive registers
645 starting at register REGNO. POP_P selects a pop rather than a
646 push and RETURN_P is true if the instruction should return.
648 It must be possible to do the requested operation in a single
649 instruction. If NREGS == 1 && !RETURN_P, use a normal push
650 or pop insn. Otherwise emit a parallel of the form:
653 [(return) ;; if RETURN_P
654 (save or restore REGNO)
655 (save or restore REGNO + 1)
657 (save or restore REGNO + NREGS - 1)
658 (set sp (plus sp (const_int adjust)))] */
661 h8300_push_pop (int regno
, int nregs
, bool pop_p
, bool return_p
)
667 /* See whether we can use a simple push or pop. */
668 if (!return_p
&& nregs
== 1)
677 /* We need one element for the return insn, if present, one for each
678 register, and one for stack adjustment. */
679 vec
= rtvec_alloc ((return_p
? 1 : 0) + nregs
+ 1);
680 sp
= stack_pointer_rtx
;
683 /* Add the return instruction. */
686 RTVEC_ELT (vec
, i
) = ret_rtx
;
690 /* Add the register moves. */
691 for (j
= 0; j
< nregs
; j
++)
697 /* Register REGNO + NREGS - 1 is popped first. Before the
698 stack adjustment, its slot is at address @sp. */
699 lhs
= gen_rtx_REG (SImode
, regno
+ j
);
700 rhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
,
701 (nregs
- j
- 1) * 4));
705 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
706 lhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
, (j
+ 1) * -4));
707 rhs
= gen_rtx_REG (SImode
, regno
+ j
);
709 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, lhs
, rhs
);
712 /* Add the stack adjustment. */
713 offset
= GEN_INT ((pop_p
? nregs
: -nregs
) * 4);
714 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, sp
,
715 gen_rtx_PLUS (Pmode
, sp
, offset
));
717 x
= gen_rtx_PARALLEL (VOIDmode
, vec
);
727 /* Return true if X has the value sp + OFFSET. */
730 h8300_stack_offset_p (rtx x
, int offset
)
733 return x
== stack_pointer_rtx
;
735 return (GET_CODE (x
) == PLUS
736 && XEXP (x
, 0) == stack_pointer_rtx
737 && GET_CODE (XEXP (x
, 1)) == CONST_INT
738 && INTVAL (XEXP (x
, 1)) == offset
);
741 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
742 something that may be an ldm or stm instruction. If it fits
743 the required template, return the register it loads or stores,
746 LOAD_P is true if X should be a load, false if it should be a store.
747 NREGS is the number of registers that the whole instruction is expected
748 to load or store. INDEX is the index of the register that X should
749 load or store, relative to the lowest-numbered register. */
752 h8300_ldm_stm_regno (rtx x
, int load_p
, int index
, int nregs
)
754 int regindex
, memindex
, offset
;
757 regindex
= 0, memindex
= 1, offset
= (nregs
- index
- 1) * 4;
759 memindex
= 0, regindex
= 1, offset
= (index
+ 1) * -4;
761 if (GET_CODE (x
) == SET
762 && GET_CODE (XEXP (x
, regindex
)) == REG
763 && GET_CODE (XEXP (x
, memindex
)) == MEM
764 && h8300_stack_offset_p (XEXP (XEXP (x
, memindex
), 0), offset
))
765 return REGNO (XEXP (x
, regindex
));
770 /* Return true if the elements of VEC starting at FIRST describe an
771 ldm or stm instruction (LOAD_P says which). */
774 h8300_ldm_stm_parallel (rtvec vec
, int load_p
, int first
)
777 int nregs
, i
, regno
, adjust
;
779 /* There must be a stack adjustment, a register move, and at least one
780 other operation (a return or another register move). */
781 if (GET_NUM_ELEM (vec
) < 3)
784 /* Get the range of registers to be pushed or popped. */
785 nregs
= GET_NUM_ELEM (vec
) - first
- 1;
786 regno
= h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
), load_p
, 0, nregs
);
788 /* Check that the call to h8300_ldm_stm_regno succeeded and
789 that we're only dealing with GPRs. */
790 if (regno
< 0 || regno
+ nregs
> 8)
793 /* 2-register h8s instructions must start with an even-numbered register.
794 3- and 4-register instructions must start with er0 or er4. */
797 if ((regno
& 1) != 0)
799 if (nregs
> 2 && (regno
& 3) != 0)
803 /* Check the other loads or stores. */
804 for (i
= 1; i
< nregs
; i
++)
805 if (h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
+ i
), load_p
, i
, nregs
)
809 /* Check the stack adjustment. */
810 last
= RTVEC_ELT (vec
, first
+ nregs
);
811 adjust
= (load_p
? nregs
: -nregs
) * 4;
812 return (GET_CODE (last
) == SET
813 && SET_DEST (last
) == stack_pointer_rtx
814 && h8300_stack_offset_p (SET_SRC (last
), adjust
));
817 /* This is what the stack looks like after the prolog of
818 a function with a frame has been set up:
824 <saved registers> <- sp
826 This is what the stack looks like after the prolog of
827 a function which doesn't have a frame:
832 <saved registers> <- sp
835 /* Generate RTL code for the function prologue. */
838 h8300_expand_prologue (void)
844 /* If the current function has the OS_Task attribute set, then
845 we have a naked prologue. */
846 if (h8300_os_task_function_p (current_function_decl
))
849 if (h8300_monitor_function_p (current_function_decl
))
850 /* The monitor function act as normal functions, which means it
851 can accept parameters and return values. In addition to this,
852 interrupts are masked in prologue and return with "rte" in epilogue. */
853 emit_insn (gen_monitor_prologue ());
855 if (frame_pointer_needed
)
858 push (HARD_FRAME_POINTER_REGNUM
);
859 F (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
), true);
862 /* Push the rest of the registers in ascending order. */
863 saved_regs
= compute_saved_regs ();
864 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
867 if (saved_regs
& (1 << regno
))
871 /* See how many registers we can push at the same time. */
872 if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
873 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
876 else if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
877 && ((saved_regs
>> regno
) & 0x07) == 0x07)
880 else if ((!TARGET_H8300SX
|| (regno
& 1) == 0)
881 && ((saved_regs
>> regno
) & 0x03) == 0x03)
885 h8300_push_pop (regno
, n_regs
, false, false);
889 /* Leave room for locals. */
890 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
893 /* Return nonzero if we can use "rts" for the function currently being
897 h8300_can_use_return_insn_p (void)
899 return (reload_completed
900 && !frame_pointer_needed
901 && get_frame_size () == 0
902 && compute_saved_regs () == 0);
905 /* Generate RTL code for the function epilogue. */
908 h8300_expand_epilogue (void)
913 HOST_WIDE_INT frame_size
;
916 if (h8300_os_task_function_p (current_function_decl
))
917 /* OS_Task epilogues are nearly naked -- they just have an
921 frame_size
= round_frame_size (get_frame_size ());
924 /* Deallocate locals. */
925 h8300_emit_stack_adjustment (1, frame_size
, false);
927 /* Pop the saved registers in descending order. */
928 saved_regs
= compute_saved_regs ();
929 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
932 if (saved_regs
& (1 << regno
))
936 /* See how many registers we can pop at the same time. */
937 if ((TARGET_H8300SX
|| (regno
& 3) == 3)
938 && ((saved_regs
<< 3 >> regno
) & 0x0f) == 0x0f)
941 else if ((TARGET_H8300SX
|| (regno
& 3) == 2)
942 && ((saved_regs
<< 2 >> regno
) & 0x07) == 0x07)
945 else if ((TARGET_H8300SX
|| (regno
& 1) == 1)
946 && ((saved_regs
<< 1 >> regno
) & 0x03) == 0x03)
950 /* See if this pop would be the last insn before the return.
951 If so, use rte/l or rts/l instead of pop or ldm.l. */
953 && !frame_pointer_needed
955 && (saved_regs
& ((1 << (regno
- n_regs
+ 1)) - 1)) == 0)
958 h8300_push_pop (regno
- n_regs
+ 1, n_regs
, true, returned_p
);
962 /* Pop frame pointer if we had one. */
963 if (frame_pointer_needed
)
967 h8300_push_pop (HARD_FRAME_POINTER_REGNUM
, 1, true, returned_p
);
971 emit_jump_insn (ret_rtx
);
974 /* Return nonzero if the current function is an interrupt
978 h8300_current_function_interrupt_function_p (void)
980 return (h8300_interrupt_function_p (current_function_decl
));
984 h8300_current_function_monitor_function_p ()
986 return (h8300_monitor_function_p (current_function_decl
));
989 /* Output assembly code for the start of the file. */
992 h8300_file_start (void)
994 default_file_start ();
997 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
998 else if (TARGET_H8300SX
)
999 fputs (TARGET_NORMAL_MODE
? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file
);
1000 else if (TARGET_H8300S
)
1001 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
1004 /* Output assembly language code for the end of file. */
1007 h8300_file_end (void)
1009 fputs ("\t.end\n", asm_out_file
);
1012 /* Split an add of a small constant into two adds/subs insns.
1014 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1015 instead of adds/subs. */
1018 split_adds_subs (machine_mode mode
, rtx
*operands
)
1020 HOST_WIDE_INT val
= INTVAL (operands
[1]);
1021 rtx reg
= operands
[0];
1022 HOST_WIDE_INT sign
= 1;
1023 HOST_WIDE_INT amount
;
1024 rtx (*gen_add
) (rtx
, rtx
, rtx
);
1026 /* Force VAL to be positive so that we do not have to consider the
1037 gen_add
= gen_addhi3
;
1041 gen_add
= gen_addsi3
;
1048 /* Try different amounts in descending order. */
1049 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
1053 for (; val
>= amount
; val
-= amount
)
1054 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
1060 /* Handle machine specific pragmas for compatibility with existing
1061 compilers for the H8/300.
1063 pragma saveall generates prologue/epilogue code which saves and
1064 restores all the registers on function entry.
1066 pragma interrupt saves and restores all registers, and exits with
1067 an rte instruction rather than an rts. A pointer to a function
1068 with this attribute may be safely used in an interrupt vector. */
1071 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1073 pragma_interrupt
= 1;
1077 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1082 /* If the next function argument with MODE and TYPE is to be passed in
1083 a register, return a reg RTX for the hard register in which to pass
1084 the argument. CUM represents the state after the last argument.
1085 If the argument is to be pushed, NULL_RTX is returned.
1087 On the H8/300 all normal args are pushed, unless -mquickcall in which
1088 case the first 3 arguments are passed in registers. */
1091 h8300_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
1092 const_tree type
, bool named
)
1094 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1096 static const char *const hand_list
[] = {
1115 rtx result
= NULL_RTX
;
1119 /* Never pass unnamed arguments in registers. */
1123 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1124 if (TARGET_QUICKCALL
)
1127 /* If calling hand written assembler, use 4 regs of args. */
1130 const char * const *p
;
1132 fname
= XSTR (cum
->libcall
, 0);
1134 /* See if this libcall is one of the hand coded ones. */
1135 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1146 if (mode
== BLKmode
)
1147 size
= int_size_in_bytes (type
);
1149 size
= GET_MODE_SIZE (mode
);
1151 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1152 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1153 result
= gen_rtx_REG (mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1159 /* Update the data in CUM to advance over an argument
1160 of mode MODE and data type TYPE.
1161 (TYPE is null for libcalls where that information may not be available.) */
1164 h8300_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1165 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1167 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1169 cum
->nbytes
+= (mode
!= BLKmode
1170 ? (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
1171 : (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
);
1175 /* Implements TARGET_REGISTER_MOVE_COST.
1177 Any SI register-to-register move may need to be reloaded,
1178 so inmplement h8300_register_move_cost to return > 2 so that reload never
1182 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1183 reg_class_t from
, reg_class_t to
)
1185 if (from
== MAC_REGS
|| to
== MAC_REG
)
1191 /* Compute the cost of an and insn. */
1194 h8300_and_costs (rtx x
)
1198 if (GET_MODE (x
) == QImode
)
1201 if (GET_MODE (x
) != HImode
1202 && GET_MODE (x
) != SImode
)
1206 operands
[1] = XEXP (x
, 0);
1207 operands
[2] = XEXP (x
, 1);
1209 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1212 /* Compute the cost of a shift insn. */
1215 h8300_shift_costs (rtx x
)
1219 if (GET_MODE (x
) != QImode
1220 && GET_MODE (x
) != HImode
1221 && GET_MODE (x
) != SImode
)
1226 operands
[2] = XEXP (x
, 1);
1228 return compute_a_shift_length (NULL
, operands
) / 2;
1231 /* Worker function for TARGET_RTX_COSTS. */
1234 h8300_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
1235 int *total
, bool speed
)
1237 if (TARGET_H8300SX
&& outer_code
== MEM
)
1239 /* Estimate the number of execution states needed to calculate
1241 if (register_operand (x
, VOIDmode
)
1242 || GET_CODE (x
) == POST_INC
1243 || GET_CODE (x
) == POST_DEC
1247 *total
= COSTS_N_INSNS (1);
1255 HOST_WIDE_INT n
= INTVAL (x
);
1259 /* Constant operands need the same number of processor
1260 states as register operands. Although we could try to
1261 use a size-based cost for !speed, the lack of
1262 of a mode makes the results very unpredictable. */
1266 if (-4 <= n
&& n
<= 4)
1277 *total
= 0 + (outer_code
== SET
);
1281 if (TARGET_H8300H
|| TARGET_H8300S
)
1282 *total
= 0 + (outer_code
== SET
);
1297 /* See comment for CONST_INT. */
1309 if (XEXP (x
, 1) == const0_rtx
)
1314 if (!h8300_dst_operand (XEXP (x
, 0), VOIDmode
)
1315 || !h8300_src_operand (XEXP (x
, 1), VOIDmode
))
1317 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1320 /* We say that MOD and DIV are so expensive because otherwise we'll
1321 generate some really horrible code for division of a power of two. */
1327 switch (GET_MODE (x
))
1331 *total
= COSTS_N_INSNS (!speed
? 4 : 10);
1335 *total
= COSTS_N_INSNS (!speed
? 4 : 18);
1341 *total
= COSTS_N_INSNS (12);
1346 switch (GET_MODE (x
))
1350 *total
= COSTS_N_INSNS (2);
1354 *total
= COSTS_N_INSNS (5);
1360 *total
= COSTS_N_INSNS (4);
1366 if (h8sx_binary_shift_operator (x
, VOIDmode
))
1368 *total
= COSTS_N_INSNS (2);
1371 else if (h8sx_unary_shift_operator (x
, VOIDmode
))
1373 *total
= COSTS_N_INSNS (1);
1376 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1381 if (GET_MODE (x
) == HImode
)
1388 *total
= COSTS_N_INSNS (1);
1393 /* Documentation for the machine specific operand escapes:
1395 'E' like s but negative.
1396 'F' like t but negative.
1397 'G' constant just the negative
1398 'R' print operand as a byte:8 address if appropriate, else fall back to
1400 'S' print operand as a long word
1401 'T' print operand as a word
1402 'V' find the set bit, and print its number.
1403 'W' find the clear bit, and print its number.
1404 'X' print operand as a byte
1405 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1406 If this operand isn't a register, fall back to 'R' handling.
1408 'c' print the opcode corresponding to rtl
1409 'e' first word of 32-bit value - if reg, then least reg. if mem
1410 then least. if const then most sig word
1411 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1412 then +2. if const then least sig word
1413 'j' print operand as condition code.
1414 'k' print operand as reverse condition code.
1415 'm' convert an integer operand to a size suffix (.b, .w or .l)
1416 'o' print an integer without a leading '#'
1417 's' print as low byte of 16-bit value
1418 't' print as high byte of 16-bit value
1419 'w' print as low byte of 32-bit value
1420 'x' print as 2nd byte of 32-bit value
1421 'y' print as 3rd byte of 32-bit value
1422 'z' print as msb of 32-bit value
1425 /* Return assembly language string which identifies a comparison type. */
1428 cond_string (enum rtx_code code
)
1457 /* Print operand X using operand code CODE to assembly language output file
1461 h8300_print_operand (FILE *file
, rtx x
, int code
)
1463 /* This is used for communication between codes V,W,Z and Y. */
1469 if (h8300_constant_length (x
) == 2)
1470 fprintf (file
, ":16");
1472 fprintf (file
, ":32");
1475 switch (GET_CODE (x
))
1478 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1481 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1488 switch (GET_CODE (x
))
1491 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1494 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1501 gcc_assert (GET_CODE (x
) == CONST_INT
);
1502 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1505 if (GET_CODE (x
) == REG
)
1506 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1511 if (GET_CODE (x
) == REG
)
1512 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1517 bitint
= (INTVAL (x
) & 0xffff);
1518 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1)
1519 bitint
= exact_log2 (bitint
& 0xff);
1521 bitint
= exact_log2 ((bitint
>> 8) & 0xff);
1522 gcc_assert (bitint
>= 0);
1523 fprintf (file
, "#%d", bitint
);
1526 bitint
= ((~INTVAL (x
)) & 0xffff);
1527 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1 )
1528 bitint
= exact_log2 (bitint
& 0xff);
1530 bitint
= (exact_log2 ((bitint
>> 8) & 0xff));
1531 gcc_assert (bitint
>= 0);
1532 fprintf (file
, "#%d", bitint
);
1536 if (GET_CODE (x
) == REG
)
1537 fprintf (file
, "%s", byte_reg (x
, 0));
1542 gcc_assert (bitint
>= 0);
1543 if (GET_CODE (x
) == REG
)
1544 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1546 h8300_print_operand (file
, x
, 'R');
1550 bitint
= INTVAL (x
);
1551 fprintf (file
, "#%d", bitint
& 7);
1554 switch (GET_CODE (x
))
1557 fprintf (file
, "or");
1560 fprintf (file
, "xor");
1563 fprintf (file
, "and");
1570 switch (GET_CODE (x
))
1574 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1576 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1579 h8300_print_operand (file
, x
, 0);
1582 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1588 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1589 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1590 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1599 switch (GET_CODE (x
))
1603 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1605 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1608 x
= adjust_address (x
, HImode
, 2);
1609 h8300_print_operand (file
, x
, 0);
1612 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1618 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1619 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1620 fprintf (file
, "#%ld", (val
& 0xffff));
1628 fputs (cond_string (GET_CODE (x
)), file
);
1631 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1634 gcc_assert (GET_CODE (x
) == CONST_INT
);
1654 h8300_print_operand_address (file
, x
);
1657 if (GET_CODE (x
) == CONST_INT
)
1658 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1660 fprintf (file
, "%s", byte_reg (x
, 0));
1663 if (GET_CODE (x
) == CONST_INT
)
1664 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1666 fprintf (file
, "%s", byte_reg (x
, 1));
1669 if (GET_CODE (x
) == CONST_INT
)
1670 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1672 fprintf (file
, "%s",
1673 byte_reg (x
, TARGET_H8300
? 2 : 0));
1676 if (GET_CODE (x
) == CONST_INT
)
1677 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1679 fprintf (file
, "%s",
1680 byte_reg (x
, TARGET_H8300
? 3 : 1));
1683 if (GET_CODE (x
) == CONST_INT
)
1684 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1686 fprintf (file
, "%s", byte_reg (x
, 0));
1689 if (GET_CODE (x
) == CONST_INT
)
1690 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1692 fprintf (file
, "%s", byte_reg (x
, 1));
1697 switch (GET_CODE (x
))
1700 switch (GET_MODE (x
))
1703 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1704 fprintf (file
, "%s", byte_reg (x
, 0));
1705 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1706 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1710 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1714 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1723 rtx addr
= XEXP (x
, 0);
1725 fprintf (file
, "@");
1726 output_address (addr
);
1728 /* Add a length suffix to constant addresses. Although this
1729 is often unnecessary, it helps to avoid ambiguity in the
1730 syntax of mova. If we wrote an insn like:
1732 mova/w.l @(1,@foo.b),er0
1734 then .b would be considered part of the symbol name.
1735 Adding a length after foo will avoid this. */
1736 if (CONSTANT_P (addr
))
1740 /* Used for mov.b and bit operations. */
1741 if (h8300_eightbit_constant_address_p (addr
))
1743 fprintf (file
, ":8");
1747 /* Fall through. We should not get here if we are
1748 processing bit operations on H8/300 or H8/300H
1749 because 'U' constraint does not allow bit
1750 operations on the tiny area on these machines. */
1755 if (h8300_constant_length (addr
) == 2)
1756 fprintf (file
, ":16");
1758 fprintf (file
, ":32");
1770 fprintf (file
, "#");
1771 h8300_print_operand_address (file
, x
);
1777 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1778 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1779 fprintf (file
, "#%ld", val
);
1788 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1791 h8300_print_operand_punct_valid_p (unsigned char code
)
1793 return (code
== '#');
1796 /* Output assembly language output for the address ADDR to FILE. */
1799 h8300_print_operand_address (FILE *file
, rtx addr
)
1804 switch (GET_CODE (addr
))
1807 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1811 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1815 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1819 fprintf (file
, "+%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1823 fprintf (file
, "%s-", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1827 fprintf (file
, "(");
1829 index
= h8300_get_index (XEXP (addr
, 0), VOIDmode
, &size
);
1830 if (GET_CODE (index
) == REG
)
1833 h8300_print_operand_address (file
, XEXP (addr
, 1));
1834 fprintf (file
, ",");
1838 h8300_print_operand_address (file
, index
);
1842 h8300_print_operand (file
, index
, 'X');
1847 h8300_print_operand (file
, index
, 'T');
1852 h8300_print_operand (file
, index
, 'S');
1856 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1861 h8300_print_operand_address (file
, XEXP (addr
, 0));
1862 fprintf (file
, "+");
1863 h8300_print_operand_address (file
, XEXP (addr
, 1));
1865 fprintf (file
, ")");
1870 /* Since the H8/300 only has 16-bit pointers, negative values are also
1871 those >= 32768. This happens for example with pointer minus a
1872 constant. We don't want to turn (char *p - 2) into
1873 (char *p + 65534) because loop unrolling can build upon this
1874 (IE: char *p + 131068). */
1875 int n
= INTVAL (addr
);
1877 n
= (int) (short) n
;
1878 fprintf (file
, "%d", n
);
1883 output_addr_const (file
, addr
);
1888 /* Output all insn addresses and their sizes into the assembly language
1889 output file. This is helpful for debugging whether the length attributes
1890 in the md file are correct. This is not meant to be a user selectable
1894 final_prescan_insn (rtx_insn
*insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1895 int num_operands ATTRIBUTE_UNUSED
)
1897 /* This holds the last insn address. */
1898 static int last_insn_address
= 0;
1900 const int uid
= INSN_UID (insn
);
1902 if (TARGET_ADDRESSES
)
1904 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
1905 INSN_ADDRESSES (uid
) - last_insn_address
);
1906 last_insn_address
= INSN_ADDRESSES (uid
);
1910 /* Prepare for an SI sized move. */
1913 h8300_expand_movsi (rtx operands
[])
1915 rtx src
= operands
[1];
1916 rtx dst
= operands
[0];
1917 if (!reload_in_progress
&& !reload_completed
)
1919 if (!register_operand (dst
, GET_MODE (dst
)))
1921 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1922 emit_move_insn (tmp
, src
);
1929 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1930 Frame pointer elimination is automatically handled.
1932 For the h8300, if frame pointer elimination is being done, we would like to
1933 convert ap and rp into sp, not fp.
1935 All other eliminations are valid. */
1938 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
1940 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
1943 /* Conditionally modify register usage based on target flags. */
1946 h8300_conditional_register_usage (void)
1949 fixed_regs
[MAC_REG
] = call_used_regs
[MAC_REG
] = 1;
1952 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1953 Define the offset between two registers, one to be eliminated, and
1954 the other its replacement, at the start of a routine. */
1957 h8300_initial_elimination_offset (int from
, int to
)
1959 /* The number of bytes that the return address takes on the stack. */
1960 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
1962 /* The number of bytes that the saved frame pointer takes on the stack. */
1963 int fp_size
= frame_pointer_needed
* UNITS_PER_WORD
;
1965 /* The number of bytes that the saved registers, excluding the frame
1966 pointer, take on the stack. */
1967 int saved_regs_size
= 0;
1969 /* The number of bytes that the locals takes on the stack. */
1970 int frame_size
= round_frame_size (get_frame_size ());
1974 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
1975 if (WORD_REG_USED (regno
))
1976 saved_regs_size
+= UNITS_PER_WORD
;
1978 /* Adjust saved_regs_size because the above loop took the frame
1979 pointer int account. */
1980 saved_regs_size
-= fp_size
;
1984 case HARD_FRAME_POINTER_REGNUM
:
1987 case ARG_POINTER_REGNUM
:
1988 return pc_size
+ fp_size
;
1989 case RETURN_ADDRESS_POINTER_REGNUM
:
1991 case FRAME_POINTER_REGNUM
:
1992 return -saved_regs_size
;
1997 case STACK_POINTER_REGNUM
:
2000 case ARG_POINTER_REGNUM
:
2001 return pc_size
+ saved_regs_size
+ frame_size
;
2002 case RETURN_ADDRESS_POINTER_REGNUM
:
2003 return saved_regs_size
+ frame_size
;
2004 case FRAME_POINTER_REGNUM
:
2016 /* Worker function for RETURN_ADDR_RTX. */
2019 h8300_return_addr_rtx (int count
, rtx frame
)
2024 ret
= gen_rtx_MEM (Pmode
,
2025 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
2026 else if (flag_omit_frame_pointer
)
2029 ret
= gen_rtx_MEM (Pmode
,
2030 memory_address (Pmode
,
2031 plus_constant (Pmode
, frame
,
2033 set_mem_alias_set (ret
, get_frame_alias_set ());
2037 /* Update the condition code from the insn. */
2040 notice_update_cc (rtx body
, rtx_insn
*insn
)
2044 switch (get_attr_cc (insn
))
2047 /* Insn does not affect CC at all. */
2051 /* Insn does not change CC, but the 0'th operand has been changed. */
2052 if (cc_status
.value1
!= 0
2053 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
2054 cc_status
.value1
= 0;
2055 if (cc_status
.value2
!= 0
2056 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
2057 cc_status
.value2
= 0;
2061 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2062 The V flag is unusable. The C flag may or may not be known but
2063 that's ok because alter_cond will change tests to use EQ/NE. */
2065 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
2066 set
= single_set (insn
);
2067 cc_status
.value1
= SET_SRC (set
);
2068 if (SET_DEST (set
) != cc0_rtx
)
2069 cc_status
.value2
= SET_DEST (set
);
2073 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2074 The C flag may or may not be known but that's ok because
2075 alter_cond will change tests to use EQ/NE. */
2077 cc_status
.flags
|= CC_NO_CARRY
;
2078 set
= single_set (insn
);
2079 cc_status
.value1
= SET_SRC (set
);
2080 if (SET_DEST (set
) != cc0_rtx
)
2082 /* If the destination is STRICT_LOW_PART, strip off
2084 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
2085 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
2087 cc_status
.value2
= SET_DEST (set
);
2092 /* The insn is a compare instruction. */
2094 cc_status
.value1
= SET_SRC (body
);
2098 /* Insn doesn't leave CC in a usable state. */
2104 /* Given that X occurs in an address of the form (plus X constant),
2105 return the part of X that is expected to be a register. There are
2106 four kinds of addressing mode to recognize:
2113 If SIZE is nonnull, and the address is one of the last three forms,
2114 set *SIZE to the index multiplication factor. Set it to 0 for
2115 plain @(dd,Rn) addresses.
2117 MODE is the mode of the value being accessed. It can be VOIDmode
2118 if the address is known to be valid, but its mode is unknown. */
2121 h8300_get_index (rtx x
, machine_mode mode
, int *size
)
2128 factor
= (mode
== VOIDmode
? 0 : GET_MODE_SIZE (mode
));
2131 && (mode
== VOIDmode
2132 || GET_MODE_CLASS (mode
) == MODE_INT
2133 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2135 if (factor
<= 1 && GET_CODE (x
) == ZERO_EXTEND
)
2137 /* When accessing byte-sized values, the index can be
2138 a zero-extended QImode or HImode register. */
2139 *size
= GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)));
2144 /* We're looking for addresses of the form:
2147 or (mult (zero_extend X) I)
2149 where I is the size of the operand being accessed.
2150 The canonical form of the second expression is:
2152 (and (mult (subreg X) I) J)
2154 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2157 if (GET_CODE (x
) == AND
2158 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2160 || INTVAL (XEXP (x
, 1)) == 0xff * factor
2161 || INTVAL (XEXP (x
, 1)) == 0xffff * factor
))
2163 index
= XEXP (x
, 0);
2164 *size
= (INTVAL (XEXP (x
, 1)) >= 0xffff ? 2 : 1);
2172 if (GET_CODE (index
) == MULT
2173 && GET_CODE (XEXP (index
, 1)) == CONST_INT
2174 && (factor
== 0 || factor
== INTVAL (XEXP (index
, 1))))
2175 return XEXP (index
, 0);
2182 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2184 On the H8/300, the predecrement and postincrement address depend thus
2185 (the amount of decrement or increment being the length of the operand). */
2188 h8300_mode_dependent_address_p (const_rtx addr
,
2189 addr_space_t as ATTRIBUTE_UNUSED
)
2191 if (GET_CODE (addr
) == PLUS
2192 && h8300_get_index (XEXP (addr
, 0), VOIDmode
, 0) != XEXP (addr
, 0))
2198 static const h8300_length_table addb_length_table
=
2200 /* #xx Rs @aa @Rs @xx */
2201 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2202 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2203 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2204 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2207 static const h8300_length_table addw_length_table
=
2209 /* #xx Rs @aa @Rs @xx */
2210 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2211 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2212 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2213 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2216 static const h8300_length_table addl_length_table
=
2218 /* #xx Rs @aa @Rs @xx */
2219 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2220 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2221 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2222 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2225 #define logicb_length_table addb_length_table
2226 #define logicw_length_table addw_length_table
2228 static const h8300_length_table logicl_length_table
=
2230 /* #xx Rs @aa @Rs @xx */
2231 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2232 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2233 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2234 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2237 static const h8300_length_table movb_length_table
=
2239 /* #xx Rs @aa @Rs @xx */
2240 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2241 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2242 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2243 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2246 #define movw_length_table movb_length_table
2248 static const h8300_length_table movl_length_table
=
2250 /* #xx Rs @aa @Rs @xx */
2251 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2252 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2253 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2254 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2257 /* Return the size of the given address or displacement constant. */
2260 h8300_constant_length (rtx constant
)
2262 /* Check for (@d:16,Reg). */
2263 if (GET_CODE (constant
) == CONST_INT
2264 && IN_RANGE (INTVAL (constant
), -0x8000, 0x7fff))
2267 /* Check for (@d:16,Reg) in cases where the displacement is
2268 an absolute address. */
2269 if (Pmode
== HImode
|| h8300_tiny_constant_address_p (constant
))
2275 /* Return the size of a displacement field in address ADDR, which should
2276 have the form (plus X constant). SIZE is the number of bytes being
2280 h8300_displacement_length (rtx addr
, int size
)
2284 offset
= XEXP (addr
, 1);
2286 /* Check for @(d:2,Reg). */
2287 if (register_operand (XEXP (addr
, 0), VOIDmode
)
2288 && GET_CODE (offset
) == CONST_INT
2289 && (INTVAL (offset
) == size
2290 || INTVAL (offset
) == size
* 2
2291 || INTVAL (offset
) == size
* 3))
2294 return h8300_constant_length (offset
);
2297 /* Store the class of operand OP in *OPCLASS and return the length of any
2298 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2299 can be null if only the length is needed. */
2302 h8300_classify_operand (rtx op
, int size
, enum h8300_operand_class
*opclass
)
2304 enum h8300_operand_class dummy
;
2309 if (CONSTANT_P (op
))
2311 *opclass
= H8OP_IMMEDIATE
;
2313 /* Byte-sized immediates are stored in the opcode fields. */
2317 /* If this is a 32-bit instruction, see whether the constant
2318 will fit into a 16-bit immediate field. */
2321 && GET_CODE (op
) == CONST_INT
2322 && IN_RANGE (INTVAL (op
), 0, 0xffff))
2327 else if (GET_CODE (op
) == MEM
)
2330 if (CONSTANT_P (op
))
2332 *opclass
= H8OP_MEM_ABSOLUTE
;
2333 return h8300_constant_length (op
);
2335 else if (GET_CODE (op
) == PLUS
&& CONSTANT_P (XEXP (op
, 1)))
2337 *opclass
= H8OP_MEM_COMPLEX
;
2338 return h8300_displacement_length (op
, size
);
2340 else if (GET_RTX_CLASS (GET_CODE (op
)) == RTX_AUTOINC
)
2342 *opclass
= H8OP_MEM_COMPLEX
;
2345 else if (register_operand (op
, VOIDmode
))
2347 *opclass
= H8OP_MEM_BASE
;
2351 gcc_assert (register_operand (op
, VOIDmode
));
2352 *opclass
= H8OP_REGISTER
;
2356 /* Return the length of the instruction described by TABLE given that
2357 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2358 and OP2 must be an h8300_src_operand. */
2361 h8300_length_from_table (rtx op1
, rtx op2
, const h8300_length_table
*table
)
2363 enum h8300_operand_class op1_class
, op2_class
;
2364 unsigned int size
, immediate_length
;
2366 size
= GET_MODE_SIZE (GET_MODE (op1
));
2367 immediate_length
= (h8300_classify_operand (op1
, size
, &op1_class
)
2368 + h8300_classify_operand (op2
, size
, &op2_class
));
2369 return immediate_length
+ (*table
)[op1_class
- 1][op2_class
];
2372 /* Return the length of a unary instruction such as neg or not given that
2373 its operand is OP. */
2376 h8300_unary_length (rtx op
)
2378 enum h8300_operand_class opclass
;
2379 unsigned int size
, operand_length
;
2381 size
= GET_MODE_SIZE (GET_MODE (op
));
2382 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2389 return (size
== 4 ? 6 : 4);
2391 case H8OP_MEM_ABSOLUTE
:
2392 return operand_length
+ (size
== 4 ? 6 : 4);
2394 case H8OP_MEM_COMPLEX
:
2395 return operand_length
+ 6;
2402 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2405 h8300_short_immediate_length (rtx op
)
2407 enum h8300_operand_class opclass
;
2408 unsigned int size
, operand_length
;
2410 size
= GET_MODE_SIZE (GET_MODE (op
));
2411 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2419 case H8OP_MEM_ABSOLUTE
:
2420 case H8OP_MEM_COMPLEX
:
2421 return 4 + operand_length
;
2428 /* Likewise bitfield load and store instructions. */
2431 h8300_bitfield_length (rtx op
, rtx op2
)
2433 enum h8300_operand_class opclass
;
2434 unsigned int size
, operand_length
;
2436 if (GET_CODE (op
) == REG
)
2438 gcc_assert (GET_CODE (op
) != REG
);
2440 size
= GET_MODE_SIZE (GET_MODE (op
));
2441 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2446 case H8OP_MEM_ABSOLUTE
:
2447 case H8OP_MEM_COMPLEX
:
2448 return 4 + operand_length
;
2455 /* Calculate the length of general binary instruction INSN using TABLE. */
2458 h8300_binary_length (rtx_insn
*insn
, const h8300_length_table
*table
)
2462 set
= single_set (insn
);
2465 if (BINARY_P (SET_SRC (set
)))
2466 return h8300_length_from_table (XEXP (SET_SRC (set
), 0),
2467 XEXP (SET_SRC (set
), 1), table
);
2470 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set
))) == RTX_TERNARY
);
2471 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set
), 1), 0),
2472 XEXP (XEXP (SET_SRC (set
), 1), 1),
2477 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2478 memory reference and either (1) it has the form @(d:16,Rn) or
2479 (2) its address has the code given by INC_CODE. */
2482 h8300_short_move_mem_p (rtx op
, enum rtx_code inc_code
)
2487 if (GET_CODE (op
) != MEM
)
2490 addr
= XEXP (op
, 0);
2491 size
= GET_MODE_SIZE (GET_MODE (op
));
2492 if (size
!= 1 && size
!= 2)
2495 return (GET_CODE (addr
) == inc_code
2496 || (GET_CODE (addr
) == PLUS
2497 && GET_CODE (XEXP (addr
, 0)) == REG
2498 && h8300_displacement_length (addr
, size
) == 2));
2501 /* Calculate the length of move instruction INSN using the given length
2502 table. Although the tables are correct for most cases, there is some
2503 irregularity in the length of mov.b and mov.w. The following forms:
2510 are two bytes shorter than most other "mov Rs, @complex" or
2511 "mov @complex,Rd" combinations. */
2514 h8300_move_length (rtx
*operands
, const h8300_length_table
*table
)
2518 size
= h8300_length_from_table (operands
[0], operands
[1], table
);
2519 if (REG_P (operands
[0]) && h8300_short_move_mem_p (operands
[1], POST_INC
))
2521 if (REG_P (operands
[1]) && h8300_short_move_mem_p (operands
[0], PRE_DEC
))
2526 /* Return the length of a mova instruction with the given operands.
2527 DEST is the register destination, SRC is the source address and
2528 OFFSET is the 16-bit or 32-bit displacement. */
2531 h8300_mova_length (rtx dest
, rtx src
, rtx offset
)
2536 + h8300_constant_length (offset
)
2537 + h8300_classify_operand (src
, GET_MODE_SIZE (GET_MODE (src
)), 0));
2538 if (!REG_P (dest
) || !REG_P (src
) || REGNO (src
) != REGNO (dest
))
2543 /* Compute the length of INSN based on its length_table attribute.
2544 OPERANDS is the array of its operands. */
2547 h8300_insn_length_from_table (rtx_insn
*insn
, rtx
* operands
)
2549 switch (get_attr_length_table (insn
))
2551 case LENGTH_TABLE_NONE
:
2554 case LENGTH_TABLE_ADDB
:
2555 return h8300_binary_length (insn
, &addb_length_table
);
2557 case LENGTH_TABLE_ADDW
:
2558 return h8300_binary_length (insn
, &addw_length_table
);
2560 case LENGTH_TABLE_ADDL
:
2561 return h8300_binary_length (insn
, &addl_length_table
);
2563 case LENGTH_TABLE_LOGICB
:
2564 return h8300_binary_length (insn
, &logicb_length_table
);
2566 case LENGTH_TABLE_MOVB
:
2567 return h8300_move_length (operands
, &movb_length_table
);
2569 case LENGTH_TABLE_MOVW
:
2570 return h8300_move_length (operands
, &movw_length_table
);
2572 case LENGTH_TABLE_MOVL
:
2573 return h8300_move_length (operands
, &movl_length_table
);
2575 case LENGTH_TABLE_MOVA
:
2576 return h8300_mova_length (operands
[0], operands
[1], operands
[2]);
2578 case LENGTH_TABLE_MOVA_ZERO
:
2579 return h8300_mova_length (operands
[0], operands
[1], const0_rtx
);
2581 case LENGTH_TABLE_UNARY
:
2582 return h8300_unary_length (operands
[0]);
2584 case LENGTH_TABLE_MOV_IMM4
:
2585 return 2 + h8300_classify_operand (operands
[0], 0, 0);
2587 case LENGTH_TABLE_SHORT_IMMEDIATE
:
2588 return h8300_short_immediate_length (operands
[0]);
2590 case LENGTH_TABLE_BITFIELD
:
2591 return h8300_bitfield_length (operands
[0], operands
[1]);
2593 case LENGTH_TABLE_BITBRANCH
:
2594 return h8300_bitfield_length (operands
[1], operands
[2]) - 2;
2601 /* Return true if LHS and RHS are memory references that can be mapped
2602 to the same h8sx assembly operand. LHS appears as the destination of
2603 an instruction and RHS appears as a source.
2605 Three cases are allowed:
2607 - RHS is @+Rn or @-Rn, LHS is @Rn
2608 - RHS is @Rn, LHS is @Rn+ or @Rn-
2609 - RHS and LHS have the same address and neither has side effects. */
2612 h8sx_mergeable_memrefs_p (rtx lhs
, rtx rhs
)
2614 if (GET_CODE (rhs
) == MEM
&& GET_CODE (lhs
) == MEM
)
2616 rhs
= XEXP (rhs
, 0);
2617 lhs
= XEXP (lhs
, 0);
2619 if (GET_CODE (rhs
) == PRE_INC
|| GET_CODE (rhs
) == PRE_DEC
)
2620 return rtx_equal_p (XEXP (rhs
, 0), lhs
);
2622 if (GET_CODE (lhs
) == POST_INC
|| GET_CODE (lhs
) == POST_DEC
)
2623 return rtx_equal_p (rhs
, XEXP (lhs
, 0));
2625 if (rtx_equal_p (rhs
, lhs
))
2631 /* Return true if OPERANDS[1] can be mapped to the same assembly
2632 operand as OPERANDS[0]. */
2635 h8300_operands_match_p (rtx
*operands
)
2637 if (register_operand (operands
[0], VOIDmode
)
2638 && register_operand (operands
[1], VOIDmode
))
2641 if (h8sx_mergeable_memrefs_p (operands
[0], operands
[1]))
2647 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2648 region DEST. The two regions do not overlap and have the common
2649 alignment given by ALIGNMENT. Return true on success.
2651 Using movmd for variable-length moves seems to involve some
2652 complex trade-offs. For instance:
2654 - Preparing for a movmd instruction is similar to preparing
2655 for a memcpy. The main difference is that the arguments
2656 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2658 - Since movmd clobbers the frame pointer, we need to save
2659 and restore it somehow when frame_pointer_needed. This can
2660 sometimes make movmd sequences longer than calls to memcpy().
2662 - The counter register is 16 bits, so the instruction is only
2663 suitable for variable-length moves when sizeof (size_t) == 2.
2664 That's only true in normal mode.
2666 - We will often lack static alignment information. Falling back
2667 on movmd.b would likely be slower than calling memcpy(), at least
2670 This function therefore only uses movmd when the length is a
2671 known constant, and only then if -fomit-frame-pointer is in
2672 effect or if we're not optimizing for size.
2674 At the moment the function uses movmd for all in-range constants,
2675 but it might be better to fall back on memcpy() for large moves
2676 if ALIGNMENT == 1. */
2679 h8sx_emit_movmd (rtx dest
, rtx src
, rtx length
,
2680 HOST_WIDE_INT alignment
)
2682 if (!flag_omit_frame_pointer
&& optimize_size
)
2685 if (GET_CODE (length
) == CONST_INT
)
2687 rtx dest_reg
, src_reg
, first_dest
, first_src
;
2691 /* Use movmd.l if the alignment allows it, otherwise fall back
2693 factor
= (alignment
>= 2 ? 4 : 1);
2695 /* Make sure the length is within range. We can handle counter
2696 values up to 65536, although HImode truncation will make
2697 the count appear negative in rtl dumps. */
2698 n
= INTVAL (length
);
2699 if (n
<= 0 || n
/ factor
> 65536)
2702 /* Create temporary registers for the source and destination
2703 pointers. Initialize them to the start of each region. */
2704 dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
2705 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
2707 /* Create references to the movmd source and destination blocks. */
2708 first_dest
= replace_equiv_address (dest
, dest_reg
);
2709 first_src
= replace_equiv_address (src
, src_reg
);
2711 set_mem_size (first_dest
, n
& -factor
);
2712 set_mem_size (first_src
, n
& -factor
);
2714 length
= copy_to_mode_reg (HImode
, gen_int_mode (n
/ factor
, HImode
));
2715 emit_insn (gen_movmd (first_dest
, first_src
, length
, GEN_INT (factor
)));
2717 if ((n
& -factor
) != n
)
2719 /* Move SRC and DEST past the region we just copied.
2720 This is done to update the memory attributes. */
2721 dest
= adjust_address (dest
, BLKmode
, n
& -factor
);
2722 src
= adjust_address (src
, BLKmode
, n
& -factor
);
2724 /* Replace the addresses with the source and destination
2725 registers, which movmd has left with the right values. */
2726 dest
= replace_equiv_address (dest
, dest_reg
);
2727 src
= replace_equiv_address (src
, src_reg
);
2729 /* Mop up the left-over bytes. */
2731 emit_move_insn (adjust_address (dest
, HImode
, 0),
2732 adjust_address (src
, HImode
, 0));
2734 emit_move_insn (adjust_address (dest
, QImode
, n
& 2),
2735 adjust_address (src
, QImode
, n
& 2));
2742 /* Move ADDR into er6 after pushing its old value onto the stack. */
2745 h8300_swap_into_er6 (rtx addr
)
2747 rtx insn
= push (HARD_FRAME_POINTER_REGNUM
);
2748 if (frame_pointer_needed
)
2749 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2750 plus_constant (Pmode
, gen_rtx_MEM (Pmode
, stack_pointer_rtx
),
2751 2 * UNITS_PER_WORD
));
2753 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2754 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
2755 plus_constant (Pmode
, stack_pointer_rtx
, 4)));
2757 emit_move_insn (hard_frame_pointer_rtx
, addr
);
2758 if (REGNO (addr
) == SP_REG
)
2759 emit_move_insn (hard_frame_pointer_rtx
,
2760 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2761 GET_MODE_SIZE (word_mode
)));
2764 /* Move the current value of er6 into ADDR and pop its old value
2768 h8300_swap_out_of_er6 (rtx addr
)
2772 if (REGNO (addr
) != SP_REG
)
2773 emit_move_insn (addr
, hard_frame_pointer_rtx
);
2775 insn
= pop (HARD_FRAME_POINTER_REGNUM
);
2776 RTX_FRAME_RELATED_P (insn
) = 1;
2777 if (frame_pointer_needed
)
2778 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2779 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2780 2 * UNITS_PER_WORD
));
2782 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2783 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
2784 plus_constant (Pmode
, stack_pointer_rtx
, -4)));
2787 /* Return the length of mov instruction. */
2790 compute_mov_length (rtx
*operands
)
2792 /* If the mov instruction involves a memory operand, we compute the
2793 length, assuming the largest addressing mode is used, and then
2794 adjust later in the function. Otherwise, we compute and return
2795 the exact length in one step. */
2796 machine_mode mode
= GET_MODE (operands
[0]);
2797 rtx dest
= operands
[0];
2798 rtx src
= operands
[1];
2801 if (GET_CODE (src
) == MEM
)
2802 addr
= XEXP (src
, 0);
2803 else if (GET_CODE (dest
) == MEM
)
2804 addr
= XEXP (dest
, 0);
2810 unsigned int base_length
;
2815 if (addr
== NULL_RTX
)
2818 /* The eightbit addressing is available only in QImode, so
2819 go ahead and take care of it. */
2820 if (h8300_eightbit_constant_address_p (addr
))
2827 if (addr
== NULL_RTX
)
2832 if (src
== const0_rtx
)
2842 if (addr
== NULL_RTX
)
2847 if (GET_CODE (src
) == CONST_INT
)
2849 if (src
== const0_rtx
)
2852 if ((INTVAL (src
) & 0xffff) == 0)
2855 if ((INTVAL (src
) & 0xffff) == 0)
2858 if ((INTVAL (src
) & 0xffff)
2859 == ((INTVAL (src
) >> 16) & 0xffff))
2869 if (addr
== NULL_RTX
)
2874 if (satisfies_constraint_G (src
))
2887 /* Adjust the length based on the addressing mode used.
2888 Specifically, we subtract the difference between the actual
2889 length and the longest one, which is @(d:16,Rs). For SImode
2890 and SFmode, we double the adjustment because two mov.w are
2891 used to do the job. */
2893 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2894 if (GET_CODE (addr
) == PRE_DEC
2895 || GET_CODE (addr
) == POST_INC
)
2897 if (mode
== QImode
|| mode
== HImode
)
2898 return base_length
- 2;
2900 /* In SImode and SFmode, we use two mov.w instructions, so
2901 double the adjustment. */
2902 return base_length
- 4;
2905 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2906 in SImode and SFmode, the second mov.w involves an address
2907 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2909 if (GET_CODE (addr
) == REG
)
2910 return base_length
- 2;
2916 unsigned int base_length
;
2921 if (addr
== NULL_RTX
)
2924 /* The eightbit addressing is available only in QImode, so
2925 go ahead and take care of it. */
2926 if (h8300_eightbit_constant_address_p (addr
))
2933 if (addr
== NULL_RTX
)
2938 if (src
== const0_rtx
)
2948 if (addr
== NULL_RTX
)
2952 if (REGNO (src
) == MAC_REG
|| REGNO (dest
) == MAC_REG
)
2958 if (GET_CODE (src
) == CONST_INT
)
2960 int val
= INTVAL (src
);
2965 if (val
== (val
& 0x00ff) || val
== (val
& 0xff00))
2968 switch (val
& 0xffffffff)
2989 if (addr
== NULL_RTX
)
2994 if (satisfies_constraint_G (src
))
3007 /* Adjust the length based on the addressing mode used.
3008 Specifically, we subtract the difference between the actual
3009 length and the longest one, which is @(d:24,ERs). */
3011 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3012 if (GET_CODE (addr
) == PRE_DEC
3013 || GET_CODE (addr
) == POST_INC
)
3014 return base_length
- 6;
3016 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3017 if (GET_CODE (addr
) == REG
)
3018 return base_length
- 6;
3020 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3022 if (GET_CODE (addr
) == PLUS
3023 && GET_CODE (XEXP (addr
, 0)) == REG
3024 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
3025 && INTVAL (XEXP (addr
, 1)) > -32768
3026 && INTVAL (XEXP (addr
, 1)) < 32767)
3027 return base_length
- 4;
3029 /* @aa:16 is 4 bytes shorter than the longest. */
3030 if (h8300_tiny_constant_address_p (addr
))
3031 return base_length
- 4;
3033 /* @aa:24 is 2 bytes shorter than the longest. */
3034 if (CONSTANT_P (addr
))
3035 return base_length
- 2;
3041 /* Output an addition insn. */
3044 output_plussi (rtx
*operands
)
3046 machine_mode mode
= GET_MODE (operands
[0]);
3048 gcc_assert (mode
== SImode
);
3052 if (GET_CODE (operands
[2]) == REG
)
3053 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3055 if (GET_CODE (operands
[2]) == CONST_INT
)
3057 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3059 if ((n
& 0xffffff) == 0)
3060 return "add\t%z2,%z0";
3061 if ((n
& 0xffff) == 0)
3062 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3063 if ((n
& 0xff) == 0)
3064 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3067 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3071 if (GET_CODE (operands
[2]) == CONST_INT
3072 && register_operand (operands
[1], VOIDmode
))
3074 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3076 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3077 return "add.l\t%S2,%S0";
3078 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3079 return "sub.l\t%G2,%S0";
3081 /* See if we can finish with 2 bytes. */
3083 switch ((unsigned int) intval
& 0xffffffff)
3088 return "adds\t%2,%S0";
3093 return "subs\t%G2,%S0";
3097 operands
[2] = GEN_INT (intval
>> 16);
3098 return "inc.w\t%2,%e0";
3102 operands
[2] = GEN_INT (intval
>> 16);
3103 return "dec.w\t%G2,%e0";
3106 /* See if we can finish with 4 bytes. */
3107 if ((intval
& 0xffff) == 0)
3109 operands
[2] = GEN_INT (intval
>> 16);
3110 return "add.w\t%2,%e0";
3114 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3116 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
3117 return "sub.l\t%S2,%S0";
3119 return "add.l\t%S2,%S0";
3123 /* ??? It would be much easier to add the h8sx stuff if a single function
3124 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3125 /* Compute the length of an addition insn. */
3128 compute_plussi_length (rtx
*operands
)
3130 machine_mode mode
= GET_MODE (operands
[0]);
3132 gcc_assert (mode
== SImode
);
3136 if (GET_CODE (operands
[2]) == REG
)
3139 if (GET_CODE (operands
[2]) == CONST_INT
)
3141 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3143 if ((n
& 0xffffff) == 0)
3145 if ((n
& 0xffff) == 0)
3147 if ((n
& 0xff) == 0)
3155 if (GET_CODE (operands
[2]) == CONST_INT
3156 && register_operand (operands
[1], VOIDmode
))
3158 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3160 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3162 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3165 /* See if we can finish with 2 bytes. */
3167 switch ((unsigned int) intval
& 0xffffffff)
3188 /* See if we can finish with 4 bytes. */
3189 if ((intval
& 0xffff) == 0)
3193 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3194 return h8300_length_from_table (operands
[0],
3195 GEN_INT (-INTVAL (operands
[2])),
3196 &addl_length_table
);
3198 return h8300_length_from_table (operands
[0], operands
[2],
3199 &addl_length_table
);
3204 /* Compute which flag bits are valid after an addition insn. */
3207 compute_plussi_cc (rtx
*operands
)
3209 machine_mode mode
= GET_MODE (operands
[0]);
3211 gcc_assert (mode
== SImode
);
3219 if (GET_CODE (operands
[2]) == CONST_INT
3220 && register_operand (operands
[1], VOIDmode
))
3222 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3224 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3226 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3229 /* See if we can finish with 2 bytes. */
3231 switch ((unsigned int) intval
& 0xffffffff)
3236 return CC_NONE_0HIT
;
3241 return CC_NONE_0HIT
;
3252 /* See if we can finish with 4 bytes. */
3253 if ((intval
& 0xffff) == 0)
3261 /* Output a logical insn. */
3264 output_logical_op (machine_mode mode
, rtx
*operands
)
3266 /* Figure out the logical op that we need to perform. */
3267 enum rtx_code code
= GET_CODE (operands
[3]);
3268 /* Pretend that every byte is affected if both operands are registers. */
3269 const unsigned HOST_WIDE_INT intval
=
3270 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3271 /* Always use the full instruction if the
3272 first operand is in memory. It is better
3273 to use define_splits to generate the shorter
3274 sequence where valid. */
3275 && register_operand (operands
[1], VOIDmode
)
3276 ? INTVAL (operands
[2]) : 0x55555555);
3277 /* The determinant of the algorithm. If we perform an AND, 0
3278 affects a bit. Otherwise, 1 affects a bit. */
3279 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3280 /* Break up DET into pieces. */
3281 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3282 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3283 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3284 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3285 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3286 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3287 int lower_half_easy_p
= 0;
3288 int upper_half_easy_p
= 0;
3289 /* The name of an insn. */
3311 /* First, see if we can finish with one insn. */
3312 if ((TARGET_H8300H
|| TARGET_H8300S
)
3316 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
3317 output_asm_insn (insn_buf
, operands
);
3321 /* Take care of the lower byte. */
3324 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
3325 output_asm_insn (insn_buf
, operands
);
3327 /* Take care of the upper byte. */
3330 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
3331 output_asm_insn (insn_buf
, operands
);
3336 if (TARGET_H8300H
|| TARGET_H8300S
)
3338 /* Determine if the lower half can be taken care of in no more
3340 lower_half_easy_p
= (b0
== 0
3342 || (code
!= IOR
&& w0
== 0xffff));
3344 /* Determine if the upper half can be taken care of in no more
3346 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3347 || (code
== AND
&& w1
== 0xff00));
3350 /* Check if doing everything with one insn is no worse than
3351 using multiple insns. */
3352 if ((TARGET_H8300H
|| TARGET_H8300S
)
3353 && w0
!= 0 && w1
!= 0
3354 && !(lower_half_easy_p
&& upper_half_easy_p
)
3355 && !(code
== IOR
&& w1
== 0xffff
3356 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3358 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
3359 output_asm_insn (insn_buf
, operands
);
3363 /* Take care of the lower and upper words individually. For
3364 each word, we try different methods in the order of
3366 1) the special insn (in case of AND or XOR),
3367 2) the word-wise insn, and
3368 3) The byte-wise insn. */
3370 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3371 output_asm_insn ((code
== AND
)
3372 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3374 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3378 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
3379 output_asm_insn (insn_buf
, operands
);
3385 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
3386 output_asm_insn (insn_buf
, operands
);
3390 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
3391 output_asm_insn (insn_buf
, operands
);
3396 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3397 output_asm_insn ((code
== AND
)
3398 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3400 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3403 && (w0
& 0x8000) != 0)
3405 output_asm_insn ("exts.l\t%S0", operands
);
3407 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3411 output_asm_insn ("extu.w\t%e0", operands
);
3413 else if (TARGET_H8300H
|| TARGET_H8300S
)
3417 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
3418 output_asm_insn (insn_buf
, operands
);
3425 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
3426 output_asm_insn (insn_buf
, operands
);
3430 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
3431 output_asm_insn (insn_buf
, operands
);
3442 /* Compute the length of a logical insn. */
3445 compute_logical_op_length (machine_mode mode
, rtx
*operands
)
3447 /* Figure out the logical op that we need to perform. */
3448 enum rtx_code code
= GET_CODE (operands
[3]);
3449 /* Pretend that every byte is affected if both operands are registers. */
3450 const unsigned HOST_WIDE_INT intval
=
3451 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3452 /* Always use the full instruction if the
3453 first operand is in memory. It is better
3454 to use define_splits to generate the shorter
3455 sequence where valid. */
3456 && register_operand (operands
[1], VOIDmode
)
3457 ? INTVAL (operands
[2]) : 0x55555555);
3458 /* The determinant of the algorithm. If we perform an AND, 0
3459 affects a bit. Otherwise, 1 affects a bit. */
3460 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3461 /* Break up DET into pieces. */
3462 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3463 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3464 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3465 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3466 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3467 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3468 int lower_half_easy_p
= 0;
3469 int upper_half_easy_p
= 0;
3471 unsigned int length
= 0;
3476 /* First, see if we can finish with one insn. */
3477 if ((TARGET_H8300H
|| TARGET_H8300S
)
3481 length
= h8300_length_from_table (operands
[1], operands
[2],
3482 &logicw_length_table
);
3486 /* Take care of the lower byte. */
3490 /* Take care of the upper byte. */
3496 if (TARGET_H8300H
|| TARGET_H8300S
)
3498 /* Determine if the lower half can be taken care of in no more
3500 lower_half_easy_p
= (b0
== 0
3502 || (code
!= IOR
&& w0
== 0xffff));
3504 /* Determine if the upper half can be taken care of in no more
3506 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3507 || (code
== AND
&& w1
== 0xff00));
3510 /* Check if doing everything with one insn is no worse than
3511 using multiple insns. */
3512 if ((TARGET_H8300H
|| TARGET_H8300S
)
3513 && w0
!= 0 && w1
!= 0
3514 && !(lower_half_easy_p
&& upper_half_easy_p
)
3515 && !(code
== IOR
&& w1
== 0xffff
3516 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3518 length
= h8300_length_from_table (operands
[1], operands
[2],
3519 &logicl_length_table
);
3523 /* Take care of the lower and upper words individually. For
3524 each word, we try different methods in the order of
3526 1) the special insn (in case of AND or XOR),
3527 2) the word-wise insn, and
3528 3) The byte-wise insn. */
3530 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3534 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3550 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3554 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3557 && (w0
& 0x8000) != 0)
3561 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3567 else if (TARGET_H8300H
|| TARGET_H8300S
)
3588 /* Compute which flag bits are valid after a logical insn. */
3591 compute_logical_op_cc (machine_mode mode
, rtx
*operands
)
3593 /* Figure out the logical op that we need to perform. */
3594 enum rtx_code code
= GET_CODE (operands
[3]);
3595 /* Pretend that every byte is affected if both operands are registers. */
3596 const unsigned HOST_WIDE_INT intval
=
3597 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3598 /* Always use the full instruction if the
3599 first operand is in memory. It is better
3600 to use define_splits to generate the shorter
3601 sequence where valid. */
3602 && register_operand (operands
[1], VOIDmode
)
3603 ? INTVAL (operands
[2]) : 0x55555555);
3604 /* The determinant of the algorithm. If we perform an AND, 0
3605 affects a bit. Otherwise, 1 affects a bit. */
3606 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3607 /* Break up DET into pieces. */
3608 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3609 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3610 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3611 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3612 int lower_half_easy_p
= 0;
3613 int upper_half_easy_p
= 0;
3614 /* Condition code. */
3615 enum attr_cc cc
= CC_CLOBBER
;
3620 /* First, see if we can finish with one insn. */
3621 if ((TARGET_H8300H
|| TARGET_H8300S
)
3629 if (TARGET_H8300H
|| TARGET_H8300S
)
3631 /* Determine if the lower half can be taken care of in no more
3633 lower_half_easy_p
= (b0
== 0
3635 || (code
!= IOR
&& w0
== 0xffff));
3637 /* Determine if the upper half can be taken care of in no more
3639 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3640 || (code
== AND
&& w1
== 0xff00));
3643 /* Check if doing everything with one insn is no worse than
3644 using multiple insns. */
3645 if ((TARGET_H8300H
|| TARGET_H8300S
)
3646 && w0
!= 0 && w1
!= 0
3647 && !(lower_half_easy_p
&& upper_half_easy_p
)
3648 && !(code
== IOR
&& w1
== 0xffff
3649 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3655 if ((TARGET_H8300H
|| TARGET_H8300S
)
3658 && (w0
& 0x8000) != 0)
3670 /* Expand a conditional branch. */
3673 h8300_expand_branch (rtx operands
[])
3675 enum rtx_code code
= GET_CODE (operands
[0]);
3676 rtx op0
= operands
[1];
3677 rtx op1
= operands
[2];
3678 rtx label
= operands
[3];
3681 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3682 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
, tmp
));
3684 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
3685 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
3686 gen_rtx_LABEL_REF (VOIDmode
, label
),
3688 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
3692 /* Expand a conditional store. */
3695 h8300_expand_store (rtx operands
[])
3697 rtx dest
= operands
[0];
3698 enum rtx_code code
= GET_CODE (operands
[1]);
3699 rtx op0
= operands
[2];
3700 rtx op1
= operands
[3];
3703 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3704 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
, tmp
));
3706 tmp
= gen_rtx_fmt_ee (code
, GET_MODE (dest
), cc0_rtx
, const0_rtx
);
3707 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
3712 We devote a fair bit of code to getting efficient shifts since we
3713 can only shift one bit at a time on the H8/300 and H8/300H and only
3714 one or two bits at a time on the H8S.
3716 All shift code falls into one of the following ways of
3719 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3720 when a straight line shift is about the same size or smaller than
3723 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3724 off the bits we don't need. This is used when only a few of the
3725 bits in the original value will survive in the shifted value.
3727 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3728 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3729 shifts can be added if the shift count is slightly more than 8 or
3730 16. This case also includes other oddballs that are not worth
3733 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3735 For each shift count, we try to use code that has no trade-off
3736 between code size and speed whenever possible.
3738 If the trade-off is unavoidable, we try to be reasonable.
3739 Specifically, the fastest version is one instruction longer than
3740 the shortest version, we take the fastest version. We also provide
3741 the use a way to switch back to the shortest version with -Os.
3743 For the details of the shift algorithms for various shift counts,
3744 refer to shift_alg_[qhs]i. */
3746 /* Classify a shift with the given mode and code. OP is the shift amount. */
3748 enum h8sx_shift_type
3749 h8sx_classify_shift (machine_mode mode
, enum rtx_code code
, rtx op
)
3751 if (!TARGET_H8300SX
)
3752 return H8SX_SHIFT_NONE
;
3758 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3759 if (GET_CODE (op
) != CONST_INT
)
3760 return H8SX_SHIFT_BINARY
;
3762 /* Reject out-of-range shift amounts. */
3763 if (INTVAL (op
) <= 0 || INTVAL (op
) >= GET_MODE_BITSIZE (mode
))
3764 return H8SX_SHIFT_NONE
;
3766 /* Power-of-2 shifts are effectively unary operations. */
3767 if (exact_log2 (INTVAL (op
)) >= 0)
3768 return H8SX_SHIFT_UNARY
;
3770 return H8SX_SHIFT_BINARY
;
3773 if (op
== const1_rtx
|| op
== const2_rtx
)
3774 return H8SX_SHIFT_UNARY
;
3775 return H8SX_SHIFT_NONE
;
3778 if (GET_CODE (op
) == CONST_INT
3779 && (INTVAL (op
) == 1
3781 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 2
3782 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 1))
3783 return H8SX_SHIFT_UNARY
;
3784 return H8SX_SHIFT_NONE
;
3787 return H8SX_SHIFT_NONE
;
3791 /* Return the asm template for a single h8sx shift instruction.
3792 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3793 is the source and OPERANDS[3] is the shift. SUFFIX is the
3794 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3795 prefix for the destination operand. */
3798 output_h8sx_shift (rtx
*operands
, int suffix
, int optype
)
3800 static char buffer
[16];
3803 switch (GET_CODE (operands
[3]))
3819 if (INTVAL (operands
[2]) > 2)
3821 /* This is really a right rotate. */
3822 operands
[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands
[0]))
3823 - INTVAL (operands
[2]));
3831 if (operands
[2] == const1_rtx
)
3832 sprintf (buffer
, "%s.%c\t%%%c0", stem
, suffix
, optype
);
3834 sprintf (buffer
, "%s.%c\t%%X2,%%%c0", stem
, suffix
, optype
);
3838 /* Emit code to do shifts. */
3841 expand_a_shift (machine_mode mode
, enum rtx_code code
, rtx operands
[])
3843 switch (h8sx_classify_shift (mode
, code
, operands
[2]))
3845 case H8SX_SHIFT_BINARY
:
3846 operands
[1] = force_reg (mode
, operands
[1]);
3849 case H8SX_SHIFT_UNARY
:
3852 case H8SX_SHIFT_NONE
:
3856 emit_move_insn (copy_rtx (operands
[0]), operands
[1]);
3858 /* Need a loop to get all the bits we want - we generate the
3859 code at emit time, but need to allocate a scratch reg now. */
3861 emit_insn (gen_rtx_PARALLEL
3864 gen_rtx_SET (VOIDmode
, copy_rtx (operands
[0]),
3865 gen_rtx_fmt_ee (code
, mode
,
3866 copy_rtx (operands
[0]), operands
[2])),
3867 gen_rtx_CLOBBER (VOIDmode
,
3868 gen_rtx_SCRATCH (QImode
)))));
3872 /* Symbols of the various modes which can be used as indices. */
3876 QIshift
, HIshift
, SIshift
3879 /* For single bit shift insns, record assembler and what bits of the
3880 condition code are valid afterwards (represented as various CC_FOO
3881 bits, 0 means CC isn't left in a usable state). */
3885 const char *const assembler
;
3886 const enum attr_cc cc_valid
;
3889 /* Assembler instruction shift table.
3891 These tables are used to look up the basic shifts.
3892 They are indexed by cpu, shift_type, and mode. */
3894 static const struct shift_insn shift_one
[2][3][3] =
3900 { "shll\t%X0", CC_SET_ZNV
},
3901 { "add.w\t%T0,%T0", CC_SET_ZN
},
3902 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
3904 /* SHIFT_LSHIFTRT */
3906 { "shlr\t%X0", CC_SET_ZNV
},
3907 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3908 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3910 /* SHIFT_ASHIFTRT */
3912 { "shar\t%X0", CC_SET_ZNV
},
3913 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3914 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3921 { "shll.b\t%X0", CC_SET_ZNV
},
3922 { "shll.w\t%T0", CC_SET_ZNV
},
3923 { "shll.l\t%S0", CC_SET_ZNV
}
3925 /* SHIFT_LSHIFTRT */
3927 { "shlr.b\t%X0", CC_SET_ZNV
},
3928 { "shlr.w\t%T0", CC_SET_ZNV
},
3929 { "shlr.l\t%S0", CC_SET_ZNV
}
3931 /* SHIFT_ASHIFTRT */
3933 { "shar.b\t%X0", CC_SET_ZNV
},
3934 { "shar.w\t%T0", CC_SET_ZNV
},
3935 { "shar.l\t%S0", CC_SET_ZNV
}
3940 static const struct shift_insn shift_two
[3][3] =
3944 { "shll.b\t#2,%X0", CC_SET_ZNV
},
3945 { "shll.w\t#2,%T0", CC_SET_ZNV
},
3946 { "shll.l\t#2,%S0", CC_SET_ZNV
}
3948 /* SHIFT_LSHIFTRT */
3950 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
3951 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
3952 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
3954 /* SHIFT_ASHIFTRT */
3956 { "shar.b\t#2,%X0", CC_SET_ZNV
},
3957 { "shar.w\t#2,%T0", CC_SET_ZNV
},
3958 { "shar.l\t#2,%S0", CC_SET_ZNV
}
3962 /* Rotates are organized by which shift they'll be used in implementing.
3963 There's no need to record whether the cc is valid afterwards because
3964 it is the AND insn that will decide this. */
3966 static const char *const rotate_one
[2][3][3] =
3973 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3976 /* SHIFT_LSHIFTRT */
3979 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3982 /* SHIFT_ASHIFTRT */
3985 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3997 /* SHIFT_LSHIFTRT */
4003 /* SHIFT_ASHIFTRT */
4012 static const char *const rotate_two
[3][3] =
4020 /* SHIFT_LSHIFTRT */
4026 /* SHIFT_ASHIFTRT */
4035 /* Shift algorithm. */
4038 /* The number of bits to be shifted by shift1 and shift2. Valid
4039 when ALG is SHIFT_SPECIAL. */
4040 unsigned int remainder
;
4042 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4043 const char *special
;
4045 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
4046 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4049 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
4050 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4053 /* CC status for SHIFT_INLINE. */
4054 enum attr_cc cc_inline
;
4056 /* CC status for SHIFT_SPECIAL. */
4057 enum attr_cc cc_special
;
4060 static void get_shift_alg (enum shift_type
,
4061 enum shift_mode
, unsigned int,
4062 struct shift_info
*);
4064 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4065 best algorithm for doing the shift. The assembler code is stored
4066 in the pointers in INFO. We achieve the maximum efficiency in most
4067 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4068 SImode in particular have a lot of room to optimize.
4070 We first determine the strategy of the shift algorithm by a table
4071 lookup. If that tells us to use a hand crafted assembly code, we
4072 go into the big switch statement to find what that is. Otherwise,
4073 we resort to a generic way, such as inlining. In either case, the
4074 result is returned through INFO. */
4077 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
4078 unsigned int count
, struct shift_info
*info
)
4082 /* Find the target CPU. */
4085 else if (TARGET_H8300H
)
4090 /* Find the shift algorithm. */
4091 info
->alg
= SHIFT_LOOP
;
4095 if (count
< GET_MODE_BITSIZE (QImode
))
4096 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
4100 if (count
< GET_MODE_BITSIZE (HImode
))
4101 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
4105 if (count
< GET_MODE_BITSIZE (SImode
))
4106 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
4113 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4117 info
->remainder
= count
;
4121 /* It is up to the caller to know that looping clobbers cc. */
4122 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4123 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4124 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4128 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
4129 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
4130 info
->cc_inline
= CC_CLOBBER
;
4134 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4135 info
->remainder
= 0;
4136 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4137 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4138 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4139 info
->cc_special
= CC_CLOBBER
;
4143 /* Here we only deal with SHIFT_SPECIAL. */
4147 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4148 through the entire value. */
4149 gcc_assert (shift_type
== SHIFT_ASHIFTRT
&& count
== 7);
4150 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
4160 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4162 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4164 case SHIFT_LSHIFTRT
:
4166 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4168 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4170 case SHIFT_ASHIFTRT
:
4171 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4175 else if ((8 <= count
&& count
<= 13)
4176 || (TARGET_H8300S
&& count
== 14))
4178 info
->remainder
= count
- 8;
4183 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4185 case SHIFT_LSHIFTRT
:
4188 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4189 info
->shift1
= "shlr.b\t%s0";
4190 info
->cc_inline
= CC_SET_ZNV
;
4194 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
4195 info
->cc_special
= CC_SET_ZNV
;
4198 case SHIFT_ASHIFTRT
:
4201 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4202 info
->shift1
= "shar.b\t%s0";
4206 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
4207 info
->cc_special
= CC_SET_ZNV
;
4212 else if (count
== 14)
4218 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4220 case SHIFT_LSHIFTRT
:
4222 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4224 case SHIFT_ASHIFTRT
:
4226 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4227 else if (TARGET_H8300H
)
4229 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4230 info
->cc_special
= CC_SET_ZNV
;
4232 else /* TARGET_H8300S */
4237 else if (count
== 15)
4242 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4244 case SHIFT_LSHIFTRT
:
4245 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4247 case SHIFT_ASHIFTRT
:
4248 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4255 if (TARGET_H8300
&& 8 <= count
&& count
<= 9)
4257 info
->remainder
= count
- 8;
4262 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4264 case SHIFT_LSHIFTRT
:
4265 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4266 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4268 case SHIFT_ASHIFTRT
:
4269 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4273 else if (count
== 8 && !TARGET_H8300
)
4278 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4280 case SHIFT_LSHIFTRT
:
4281 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4283 case SHIFT_ASHIFTRT
:
4284 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4288 else if (count
== 15 && TARGET_H8300
)
4294 case SHIFT_LSHIFTRT
:
4295 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4297 case SHIFT_ASHIFTRT
:
4298 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4302 else if (count
== 15 && !TARGET_H8300
)
4307 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4308 info
->cc_special
= CC_SET_ZNV
;
4310 case SHIFT_LSHIFTRT
:
4311 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4312 info
->cc_special
= CC_SET_ZNV
;
4314 case SHIFT_ASHIFTRT
:
4318 else if ((TARGET_H8300
&& 16 <= count
&& count
<= 20)
4319 || (TARGET_H8300H
&& 16 <= count
&& count
<= 19)
4320 || (TARGET_H8300S
&& 16 <= count
&& count
<= 21))
4322 info
->remainder
= count
- 16;
4327 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4329 info
->shift1
= "add.w\t%e0,%e0";
4331 case SHIFT_LSHIFTRT
:
4334 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4335 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
4339 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
4340 info
->cc_special
= CC_SET_ZNV
;
4343 case SHIFT_ASHIFTRT
:
4346 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4347 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
4351 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
4352 info
->cc_special
= CC_SET_ZNV
;
4357 else if (TARGET_H8300
&& 24 <= count
&& count
<= 28)
4359 info
->remainder
= count
- 24;
4364 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4365 info
->shift1
= "shll.b\t%z0";
4366 info
->cc_inline
= CC_SET_ZNV
;
4368 case SHIFT_LSHIFTRT
:
4369 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4370 info
->shift1
= "shlr.b\t%w0";
4371 info
->cc_inline
= CC_SET_ZNV
;
4373 case SHIFT_ASHIFTRT
:
4374 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4375 info
->shift1
= "shar.b\t%w0";
4376 info
->cc_inline
= CC_SET_ZNV
;
4380 else if ((TARGET_H8300H
&& count
== 24)
4381 || (TARGET_H8300S
&& 24 <= count
&& count
<= 25))
4383 info
->remainder
= count
- 24;
4388 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4390 case SHIFT_LSHIFTRT
:
4391 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4392 info
->cc_special
= CC_SET_ZNV
;
4394 case SHIFT_ASHIFTRT
:
4395 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4396 info
->cc_special
= CC_SET_ZNV
;
4400 else if (!TARGET_H8300
&& count
== 28)
4406 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4408 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4410 case SHIFT_LSHIFTRT
:
4413 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4414 info
->cc_special
= CC_SET_ZNV
;
4417 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4419 case SHIFT_ASHIFTRT
:
4423 else if (!TARGET_H8300
&& count
== 29)
4429 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4431 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4433 case SHIFT_LSHIFTRT
:
4436 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4437 info
->cc_special
= CC_SET_ZNV
;
4441 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4442 info
->cc_special
= CC_SET_ZNV
;
4445 case SHIFT_ASHIFTRT
:
4449 else if (!TARGET_H8300
&& count
== 30)
4455 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4457 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4459 case SHIFT_LSHIFTRT
:
4461 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4463 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4465 case SHIFT_ASHIFTRT
:
4469 else if (count
== 31)
4476 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4478 case SHIFT_LSHIFTRT
:
4479 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4481 case SHIFT_ASHIFTRT
:
4482 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4491 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4492 info
->cc_special
= CC_SET_ZNV
;
4494 case SHIFT_LSHIFTRT
:
4495 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4496 info
->cc_special
= CC_SET_ZNV
;
4498 case SHIFT_ASHIFTRT
:
4499 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4500 info
->cc_special
= CC_SET_ZNV
;
4513 info
->shift2
= NULL
;
4516 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4517 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4520 h8300_shift_needs_scratch_p (int count
, machine_mode mode
)
4525 if (GET_MODE_BITSIZE (mode
) <= count
)
4528 /* Find out the target CPU. */
4531 else if (TARGET_H8300H
)
4536 /* Find the shift algorithm. */
4540 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
4541 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
4542 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
4546 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
4547 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
4548 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
4552 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
4553 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
4554 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
4561 /* On H8/300H, count == 8 uses a scratch register. */
4562 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
4563 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
4566 /* Output the assembler code for doing shifts. */
4569 output_a_shift (rtx
*operands
)
4571 static int loopend_lab
;
4572 rtx shift
= operands
[3];
4573 machine_mode mode
= GET_MODE (shift
);
4574 enum rtx_code code
= GET_CODE (shift
);
4575 enum shift_type shift_type
;
4576 enum shift_mode shift_mode
;
4577 struct shift_info info
;
4585 shift_mode
= QIshift
;
4588 shift_mode
= HIshift
;
4591 shift_mode
= SIshift
;
4600 shift_type
= SHIFT_ASHIFTRT
;
4603 shift_type
= SHIFT_LSHIFTRT
;
4606 shift_type
= SHIFT_ASHIFT
;
4612 /* This case must be taken care of by one of the two splitters
4613 that convert a variable shift into a loop. */
4614 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4616 n
= INTVAL (operands
[2]);
4618 /* If the count is negative, make it 0. */
4621 /* If the count is too big, truncate it.
4622 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4623 do the intuitive thing. */
4624 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4625 n
= GET_MODE_BITSIZE (mode
);
4627 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4632 output_asm_insn (info
.special
, operands
);
4638 /* Emit two bit shifts first. */
4639 if (info
.shift2
!= NULL
)
4641 for (; n
> 1; n
-= 2)
4642 output_asm_insn (info
.shift2
, operands
);
4645 /* Now emit one bit shifts for any residual. */
4647 output_asm_insn (info
.shift1
, operands
);
4652 int m
= GET_MODE_BITSIZE (mode
) - n
;
4653 const int mask
= (shift_type
== SHIFT_ASHIFT
4654 ? ((1 << m
) - 1) << n
4658 /* Not all possibilities of rotate are supported. They shouldn't
4659 be generated, but let's watch for 'em. */
4660 gcc_assert (info
.shift1
);
4662 /* Emit two bit rotates first. */
4663 if (info
.shift2
!= NULL
)
4665 for (; m
> 1; m
-= 2)
4666 output_asm_insn (info
.shift2
, operands
);
4669 /* Now single bit rotates for any residual. */
4671 output_asm_insn (info
.shift1
, operands
);
4673 /* Now mask off the high bits. */
4677 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
4681 gcc_assert (TARGET_H8300H
|| TARGET_H8300S
);
4682 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
4689 output_asm_insn (insn_buf
, operands
);
4694 /* A loop to shift by a "large" constant value.
4695 If we have shift-by-2 insns, use them. */
4696 if (info
.shift2
!= NULL
)
4698 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
4699 names_big
[REGNO (operands
[4])]);
4700 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4701 output_asm_insn (info
.shift2
, operands
);
4702 output_asm_insn ("add #0xff,%X4", operands
);
4703 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4705 output_asm_insn (info
.shift1
, operands
);
4709 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
4710 names_big
[REGNO (operands
[4])]);
4711 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4712 output_asm_insn (info
.shift1
, operands
);
4713 output_asm_insn ("add #0xff,%X4", operands
);
4714 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4723 /* Count the number of assembly instructions in a string TEMPL. */
4726 h8300_asm_insn_count (const char *templ
)
4728 unsigned int count
= 1;
4730 for (; *templ
; templ
++)
4737 /* Compute the length of a shift insn. */
4740 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4742 rtx shift
= operands
[3];
4743 machine_mode mode
= GET_MODE (shift
);
4744 enum rtx_code code
= GET_CODE (shift
);
4745 enum shift_type shift_type
;
4746 enum shift_mode shift_mode
;
4747 struct shift_info info
;
4748 unsigned int wlength
= 0;
4753 shift_mode
= QIshift
;
4756 shift_mode
= HIshift
;
4759 shift_mode
= SIshift
;
4768 shift_type
= SHIFT_ASHIFTRT
;
4771 shift_type
= SHIFT_LSHIFTRT
;
4774 shift_type
= SHIFT_ASHIFT
;
4780 if (GET_CODE (operands
[2]) != CONST_INT
)
4782 /* Get the assembler code to do one shift. */
4783 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
4785 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
4789 int n
= INTVAL (operands
[2]);
4791 /* If the count is negative, make it 0. */
4794 /* If the count is too big, truncate it.
4795 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4796 do the intuitive thing. */
4797 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4798 n
= GET_MODE_BITSIZE (mode
);
4800 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4805 wlength
+= h8300_asm_insn_count (info
.special
);
4807 /* Every assembly instruction used in SHIFT_SPECIAL case
4808 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4809 see xor.l, we just pretend that xor.l counts as two insns
4810 so that the insn length will be computed correctly. */
4811 if (strstr (info
.special
, "xor.l") != NULL
)
4819 if (info
.shift2
!= NULL
)
4821 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
4825 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
4831 int m
= GET_MODE_BITSIZE (mode
) - n
;
4833 /* Not all possibilities of rotate are supported. They shouldn't
4834 be generated, but let's watch for 'em. */
4835 gcc_assert (info
.shift1
);
4837 if (info
.shift2
!= NULL
)
4839 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
4843 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
4845 /* Now mask off the high bits. */
4855 gcc_assert (!TARGET_H8300
);
4865 /* A loop to shift by a "large" constant value.
4866 If we have shift-by-2 insns, use them. */
4867 if (info
.shift2
!= NULL
)
4869 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
4871 wlength
+= h8300_asm_insn_count (info
.shift1
);
4875 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
4885 /* Compute which flag bits are valid after a shift insn. */
4888 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4890 rtx shift
= operands
[3];
4891 machine_mode mode
= GET_MODE (shift
);
4892 enum rtx_code code
= GET_CODE (shift
);
4893 enum shift_type shift_type
;
4894 enum shift_mode shift_mode
;
4895 struct shift_info info
;
4901 shift_mode
= QIshift
;
4904 shift_mode
= HIshift
;
4907 shift_mode
= SIshift
;
4916 shift_type
= SHIFT_ASHIFTRT
;
4919 shift_type
= SHIFT_LSHIFTRT
;
4922 shift_type
= SHIFT_ASHIFT
;
4928 /* This case must be taken care of by one of the two splitters
4929 that convert a variable shift into a loop. */
4930 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4932 n
= INTVAL (operands
[2]);
4934 /* If the count is negative, make it 0. */
4937 /* If the count is too big, truncate it.
4938 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4939 do the intuitive thing. */
4940 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4941 n
= GET_MODE_BITSIZE (mode
);
4943 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4948 if (info
.remainder
== 0)
4949 return info
.cc_special
;
4954 return info
.cc_inline
;
4957 /* This case always ends with an and instruction. */
4961 /* A loop to shift by a "large" constant value.
4962 If we have shift-by-2 insns, use them. */
4963 if (info
.shift2
!= NULL
)
4966 return info
.cc_inline
;
4975 /* A rotation by a non-constant will cause a loop to be generated, in
4976 which a rotation by one bit is used. A rotation by a constant,
4977 including the one in the loop, will be taken care of by
4978 output_a_rotate () at the insn emit time. */
4981 expand_a_rotate (rtx operands
[])
4983 rtx dst
= operands
[0];
4984 rtx src
= operands
[1];
4985 rtx rotate_amount
= operands
[2];
4986 machine_mode mode
= GET_MODE (dst
);
4988 if (h8sx_classify_shift (mode
, ROTATE
, rotate_amount
) == H8SX_SHIFT_UNARY
)
4991 /* We rotate in place. */
4992 emit_move_insn (dst
, src
);
4994 if (GET_CODE (rotate_amount
) != CONST_INT
)
4996 rtx counter
= gen_reg_rtx (QImode
);
4997 rtx_code_label
*start_label
= gen_label_rtx ();
4998 rtx_code_label
*end_label
= gen_label_rtx ();
5000 /* If the rotate amount is less than or equal to 0,
5001 we go out of the loop. */
5002 emit_cmp_and_jump_insns (rotate_amount
, const0_rtx
, LE
, NULL_RTX
,
5003 QImode
, 0, end_label
);
5005 /* Initialize the loop counter. */
5006 emit_move_insn (counter
, rotate_amount
);
5008 emit_label (start_label
);
5010 /* Rotate by one bit. */
5014 emit_insn (gen_rotlqi3_1 (dst
, dst
, const1_rtx
));
5017 emit_insn (gen_rotlhi3_1 (dst
, dst
, const1_rtx
));
5020 emit_insn (gen_rotlsi3_1 (dst
, dst
, const1_rtx
));
5026 /* Decrement the counter by 1. */
5027 emit_insn (gen_addqi3 (counter
, counter
, constm1_rtx
));
5029 /* If the loop counter is nonzero, we go back to the beginning
5031 emit_cmp_and_jump_insns (counter
, const0_rtx
, NE
, NULL_RTX
, QImode
, 1,
5034 emit_label (end_label
);
5038 /* Rotate by AMOUNT bits. */
5042 emit_insn (gen_rotlqi3_1 (dst
, dst
, rotate_amount
));
5045 emit_insn (gen_rotlhi3_1 (dst
, dst
, rotate_amount
));
5048 emit_insn (gen_rotlsi3_1 (dst
, dst
, rotate_amount
));
5058 /* Output a rotate insn. */
5061 output_a_rotate (enum rtx_code code
, rtx
*operands
)
5063 rtx dst
= operands
[0];
5064 rtx rotate_amount
= operands
[2];
5065 enum shift_mode rotate_mode
;
5066 enum shift_type rotate_type
;
5067 const char *insn_buf
;
5070 machine_mode mode
= GET_MODE (dst
);
5072 gcc_assert (GET_CODE (rotate_amount
) == CONST_INT
);
5077 rotate_mode
= QIshift
;
5080 rotate_mode
= HIshift
;
5083 rotate_mode
= SIshift
;
5092 rotate_type
= SHIFT_ASHIFT
;
5095 rotate_type
= SHIFT_LSHIFTRT
;
5101 amount
= INTVAL (rotate_amount
);
5103 /* Clean up AMOUNT. */
5106 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5107 amount
= GET_MODE_BITSIZE (mode
);
5109 /* Determine the faster direction. After this phase, amount will be
5110 at most a half of GET_MODE_BITSIZE (mode). */
5111 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5113 /* Flip the direction. */
5114 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5116 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5119 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5120 boost up the rotation. */
5121 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5122 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5123 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5124 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5125 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5130 /* This code works on any family. */
5131 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5132 output_asm_insn (insn_buf
, operands
);
5136 /* This code works on the H8/300H and H8S. */
5137 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5138 output_asm_insn (insn_buf
, operands
);
5145 /* Adjust AMOUNT and flip the direction. */
5146 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5148 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5151 /* Output rotate insns. */
5152 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
5155 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
5157 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
5159 for (; amount
>= bits
; amount
-= bits
)
5160 output_asm_insn (insn_buf
, operands
);
5166 /* Compute the length of a rotate insn. */
5169 compute_a_rotate_length (rtx
*operands
)
5171 rtx src
= operands
[1];
5172 rtx amount_rtx
= operands
[2];
5173 machine_mode mode
= GET_MODE (src
);
5175 unsigned int length
= 0;
5177 gcc_assert (GET_CODE (amount_rtx
) == CONST_INT
);
5179 amount
= INTVAL (amount_rtx
);
5181 /* Clean up AMOUNT. */
5184 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5185 amount
= GET_MODE_BITSIZE (mode
);
5187 /* Determine the faster direction. After this phase, amount
5188 will be at most a half of GET_MODE_BITSIZE (mode). */
5189 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5190 /* Flip the direction. */
5191 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5193 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5194 boost up the rotation. */
5195 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5196 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5197 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5198 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5199 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5201 /* Adjust AMOUNT and flip the direction. */
5202 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5206 /* We use 2-bit rotations on the H8S. */
5208 amount
= amount
/ 2 + amount
% 2;
5210 /* The H8/300 uses three insns to rotate one bit, taking 6
5212 length
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
5217 /* Fix the operands of a gen_xxx so that it could become a bit
5221 fix_bit_operand (rtx
*operands
, enum rtx_code code
)
5223 /* The bit_operand predicate accepts any memory during RTL generation, but
5224 only 'U' memory afterwards, so if this is a MEM operand, we must force
5225 it to be valid for 'U' by reloading the address. */
5228 ? single_zero_operand (operands
[2], QImode
)
5229 : single_one_operand (operands
[2], QImode
))
5231 /* OK to have a memory dest. */
5232 if (GET_CODE (operands
[0]) == MEM
5233 && !satisfies_constraint_U (operands
[0]))
5235 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
5236 copy_to_mode_reg (Pmode
,
5237 XEXP (operands
[0], 0)));
5238 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5242 if (GET_CODE (operands
[1]) == MEM
5243 && !satisfies_constraint_U (operands
[1]))
5245 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
5246 copy_to_mode_reg (Pmode
,
5247 XEXP (operands
[1], 0)));
5248 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5254 /* Dest and src op must be register. */
5256 operands
[1] = force_reg (QImode
, operands
[1]);
5258 rtx res
= gen_reg_rtx (QImode
);
5262 emit_insn (gen_andqi3_1 (res
, operands
[1], operands
[2]));
5265 emit_insn (gen_iorqi3_1 (res
, operands
[1], operands
[2]));
5268 emit_insn (gen_xorqi3_1 (res
, operands
[1], operands
[2]));
5273 emit_insn (gen_movqi (operands
[0], res
));
5278 /* Return nonzero if FUNC is an interrupt function as specified
5279 by the "interrupt" attribute. */
5282 h8300_interrupt_function_p (tree func
)
5286 if (TREE_CODE (func
) != FUNCTION_DECL
)
5289 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
5290 return a
!= NULL_TREE
;
5293 /* Return nonzero if FUNC is a saveall function as specified by the
5294 "saveall" attribute. */
5297 h8300_saveall_function_p (tree func
)
5301 if (TREE_CODE (func
) != FUNCTION_DECL
)
5304 a
= lookup_attribute ("saveall", DECL_ATTRIBUTES (func
));
5305 return a
!= NULL_TREE
;
5308 /* Return nonzero if FUNC is an OS_Task function as specified
5309 by the "OS_Task" attribute. */
5312 h8300_os_task_function_p (tree func
)
5316 if (TREE_CODE (func
) != FUNCTION_DECL
)
5319 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
5320 return a
!= NULL_TREE
;
5323 /* Return nonzero if FUNC is a monitor function as specified
5324 by the "monitor" attribute. */
5327 h8300_monitor_function_p (tree func
)
5331 if (TREE_CODE (func
) != FUNCTION_DECL
)
5334 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
5335 return a
!= NULL_TREE
;
5338 /* Return nonzero if FUNC is a function that should be called
5339 through the function vector. */
5342 h8300_funcvec_function_p (tree func
)
5346 if (TREE_CODE (func
) != FUNCTION_DECL
)
5349 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
5350 return a
!= NULL_TREE
;
5353 /* Return nonzero if DECL is a variable that's in the eight bit
5357 h8300_eightbit_data_p (tree decl
)
5361 if (TREE_CODE (decl
) != VAR_DECL
)
5364 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
5365 return a
!= NULL_TREE
;
5368 /* Return nonzero if DECL is a variable that's in the tiny
5372 h8300_tiny_data_p (tree decl
)
5376 if (TREE_CODE (decl
) != VAR_DECL
)
5379 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
5380 return a
!= NULL_TREE
;
5383 /* Generate an 'interrupt_handler' attribute for decls. We convert
5384 all the pragmas to corresponding attributes. */
5387 h8300_insert_attributes (tree node
, tree
*attributes
)
5389 if (TREE_CODE (node
) == FUNCTION_DECL
)
5391 if (pragma_interrupt
)
5393 pragma_interrupt
= 0;
5395 /* Add an 'interrupt_handler' attribute. */
5396 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
5404 /* Add an 'saveall' attribute. */
5405 *attributes
= tree_cons (get_identifier ("saveall"),
5411 /* Supported attributes:
5413 interrupt_handler: output a prologue and epilogue suitable for an
5416 saveall: output a prologue and epilogue that saves and restores
5417 all registers except the stack pointer.
5419 function_vector: This function should be called through the
5422 eightbit_data: This variable lives in the 8-bit data area and can
5423 be referenced with 8-bit absolute memory addresses.
5425 tiny_data: This variable lives in the tiny data area and can be
5426 referenced with 16-bit absolute memory references. */
5428 static const struct attribute_spec h8300_attribute_table
[] =
5430 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5431 affects_type_identity } */
5432 { "interrupt_handler", 0, 0, true, false, false,
5433 h8300_handle_fndecl_attribute
, NULL
, false },
5434 { "saveall", 0, 0, true, false, false,
5435 h8300_handle_fndecl_attribute
, NULL
, false },
5436 { "OS_Task", 0, 0, true, false, false,
5437 h8300_handle_fndecl_attribute
, NULL
, false },
5438 { "monitor", 0, 0, true, false, false,
5439 h8300_handle_fndecl_attribute
, NULL
, false },
5440 { "function_vector", 0, 0, true, false, false,
5441 h8300_handle_fndecl_attribute
, NULL
, false },
5442 { "eightbit_data", 0, 0, true, false, false,
5443 h8300_handle_eightbit_data_attribute
, NULL
, false },
5444 { "tiny_data", 0, 0, true, false, false,
5445 h8300_handle_tiny_data_attribute
, NULL
, false },
5446 { NULL
, 0, 0, false, false, false, NULL
, NULL
, false }
5450 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5451 struct attribute_spec.handler. */
5453 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
5454 tree args ATTRIBUTE_UNUSED
,
5455 int flags ATTRIBUTE_UNUSED
,
5458 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5460 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5462 *no_add_attrs
= true;
5468 /* Handle an "eightbit_data" attribute; arguments as in
5469 struct attribute_spec.handler. */
5471 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
5472 tree args ATTRIBUTE_UNUSED
,
5473 int flags ATTRIBUTE_UNUSED
,
5478 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5480 set_decl_section_name (decl
, ".eight");
5484 warning (OPT_Wattributes
, "%qE attribute ignored",
5486 *no_add_attrs
= true;
5492 /* Handle an "tiny_data" attribute; arguments as in
5493 struct attribute_spec.handler. */
5495 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
5496 tree args ATTRIBUTE_UNUSED
,
5497 int flags ATTRIBUTE_UNUSED
,
5502 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5504 set_decl_section_name (decl
, ".tiny");
5508 warning (OPT_Wattributes
, "%qE attribute ignored",
5510 *no_add_attrs
= true;
5516 /* Mark function vectors, and various small data objects. */
5519 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
5521 int extra_flags
= 0;
5523 default_encode_section_info (decl
, rtl
, first
);
5525 if (TREE_CODE (decl
) == FUNCTION_DECL
5526 && h8300_funcvec_function_p (decl
))
5527 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
5528 else if (TREE_CODE (decl
) == VAR_DECL
5529 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
5531 if (h8300_eightbit_data_p (decl
))
5532 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
5533 else if (first
&& h8300_tiny_data_p (decl
))
5534 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
5538 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
5541 /* Output a single-bit extraction. */
5544 output_simode_bld (int bild
, rtx operands
[])
5548 /* Clear the destination register. */
5549 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
5551 /* Now output the bit load or bit inverse load, and store it in
5554 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5556 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5558 output_asm_insn ("bst\t#0,%w0", operands
);
5562 /* Determine if we can clear the destination first. */
5563 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
5564 && REGNO (operands
[0]) != REGNO (operands
[1]));
5567 output_asm_insn ("sub.l\t%S0,%S0", operands
);
5569 /* Output the bit load or bit inverse load. */
5571 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5573 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5576 output_asm_insn ("xor.l\t%S0,%S0", operands
);
5578 /* Perform the bit store. */
5579 output_asm_insn ("rotxl.l\t%S0", operands
);
5586 /* Delayed-branch scheduling is more effective if we have some idea
5587 how long each instruction will be. Use a shorten_branches pass
5588 to get an initial estimate. */
5593 if (flag_delayed_branch
)
5594 shorten_branches (get_insns ());
5597 #ifndef OBJECT_FORMAT_ELF
5599 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
,
5602 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5603 fprintf (asm_out_file
, "\t.section %s\n", name
);
5605 #endif /* ! OBJECT_FORMAT_ELF */
5607 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5608 which is a special case of the 'R' operand. */
5611 h8300_eightbit_constant_address_p (rtx x
)
5613 /* The ranges of the 8-bit area. */
5614 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
5615 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
5616 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
5617 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
5618 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
5619 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
5621 unsigned HOST_WIDE_INT addr
;
5623 /* We accept symbols declared with eightbit_data. */
5624 if (GET_CODE (x
) == SYMBOL_REF
)
5625 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
5627 if (GET_CODE (x
) != CONST_INT
)
5633 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
5634 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
5635 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
5638 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5639 on H8/300H and H8S. */
5642 h8300_tiny_constant_address_p (rtx x
)
5644 /* The ranges of the 16-bit area. */
5645 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
5646 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
5647 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
5648 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
5649 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
5650 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
5651 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
5652 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
5654 unsigned HOST_WIDE_INT addr
;
5656 switch (GET_CODE (x
))
5659 /* In the normal mode, any symbol fits in the 16-bit absolute
5660 address range. We also accept symbols declared with
5662 return (TARGET_NORMAL_MODE
5663 || (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0);
5667 return (TARGET_NORMAL_MODE
5669 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
5671 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
5674 return TARGET_NORMAL_MODE
;
5682 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5683 locations that can be accessed as a 16-bit word. */
5686 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
5688 HOST_WIDE_INT offset1
, offset2
;
5696 else if (GET_CODE (addr1
) == PLUS
5697 && REG_P (XEXP (addr1
, 0))
5698 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
5700 reg1
= XEXP (addr1
, 0);
5701 offset1
= INTVAL (XEXP (addr1
, 1));
5711 else if (GET_CODE (addr2
) == PLUS
5712 && REG_P (XEXP (addr2
, 0))
5713 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
5715 reg2
= XEXP (addr2
, 0);
5716 offset2
= INTVAL (XEXP (addr2
, 1));
5721 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
5722 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
5724 && offset1
+ 1 == offset2
)
5730 /* Return nonzero if we have the same comparison insn as I3 two insns
5731 before I3. I3 is assumed to be a comparison insn. */
5734 same_cmp_preceding_p (rtx i3
)
5738 /* Make sure we have a sequence of three insns. */
5739 i2
= prev_nonnote_insn (i3
);
5742 i1
= prev_nonnote_insn (i2
);
5746 return (INSN_P (i1
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5747 && any_condjump_p (i2
) && onlyjump_p (i2
));
5750 /* Return nonzero if we have the same comparison insn as I1 two insns
5751 after I1. I1 is assumed to be a comparison insn. */
5754 same_cmp_following_p (rtx i1
)
5758 /* Make sure we have a sequence of three insns. */
5759 i2
= next_nonnote_insn (i1
);
5762 i3
= next_nonnote_insn (i2
);
5766 return (INSN_P (i3
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5767 && any_condjump_p (i2
) && onlyjump_p (i2
));
5770 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5771 (or pops) N registers. OPERANDS are assumed to be an array of
5775 h8300_regs_ok_for_stm (int n
, rtx operands
[])
5780 return ((REGNO (operands
[0]) == 0 && REGNO (operands
[1]) == 1)
5781 || (REGNO (operands
[0]) == 2 && REGNO (operands
[1]) == 3)
5782 || (REGNO (operands
[0]) == 4 && REGNO (operands
[1]) == 5));
5784 return ((REGNO (operands
[0]) == 0
5785 && REGNO (operands
[1]) == 1
5786 && REGNO (operands
[2]) == 2)
5787 || (REGNO (operands
[0]) == 4
5788 && REGNO (operands
[1]) == 5
5789 && REGNO (operands
[2]) == 6));
5792 return (REGNO (operands
[0]) == 0
5793 && REGNO (operands
[1]) == 1
5794 && REGNO (operands
[2]) == 2
5795 && REGNO (operands
[3]) == 3);
5801 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5804 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5805 unsigned int new_reg
)
5807 /* Interrupt functions can only use registers that have already been
5808 saved by the prologue, even if they would normally be
5811 if (h8300_current_function_interrupt_function_p ()
5812 && !df_regs_ever_live_p (new_reg
))
5818 /* Returns true if register REGNO is safe to be allocated as a scratch
5819 register in the current function. */
5822 h8300_hard_regno_scratch_ok (unsigned int regno
)
5824 if (h8300_current_function_interrupt_function_p ()
5825 && ! WORD_REG_USED (regno
))
5832 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5835 h8300_rtx_ok_for_base_p (rtx x
, int strict
)
5837 /* Strip off SUBREG if any. */
5838 if (GET_CODE (x
) == SUBREG
)
5843 ? REG_OK_FOR_BASE_STRICT_P (x
)
5844 : REG_OK_FOR_BASE_NONSTRICT_P (x
)));
5847 /* Return nozero if X is a legitimate address. On the H8/300, a
5848 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5849 CONSTANT_ADDRESS. */
5852 h8300_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
5854 /* The register indirect addresses like @er0 is always valid. */
5855 if (h8300_rtx_ok_for_base_p (x
, strict
))
5858 if (CONSTANT_ADDRESS_P (x
))
5862 && ( GET_CODE (x
) == PRE_INC
5863 || GET_CODE (x
) == PRE_DEC
5864 || GET_CODE (x
) == POST_INC
5865 || GET_CODE (x
) == POST_DEC
)
5866 && h8300_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
5869 if (GET_CODE (x
) == PLUS
5870 && CONSTANT_ADDRESS_P (XEXP (x
, 1))
5871 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x
, 0),
5878 /* Worker function for HARD_REGNO_NREGS.
5880 We pretend the MAC register is 32bits -- we don't have any data
5881 types on the H8 series to handle more than 32bits. */
5884 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED
, machine_mode mode
)
5886 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5889 /* Worker function for HARD_REGNO_MODE_OK. */
5892 h8300_hard_regno_mode_ok (int regno
, machine_mode mode
)
5895 /* If an even reg, then anything goes. Otherwise the mode must be
5897 return ((regno
& 1) == 0) || (mode
== HImode
) || (mode
== QImode
);
5899 /* MAC register can only be of SImode. Otherwise, anything
5901 return regno
== MAC_REG
? mode
== SImode
: 1;
5904 /* Helper function for the move patterns. Make sure a move is legitimate. */
5907 h8300_move_ok (rtx dest
, rtx src
)
5911 /* Validate that at least one operand is a register. */
5914 if (MEM_P (src
) || CONSTANT_P (src
))
5916 addr
= XEXP (dest
, 0);
5919 else if (MEM_P (src
))
5921 addr
= XEXP (src
, 0);
5927 /* Validate that auto-inc doesn't affect OTHER. */
5928 if (GET_RTX_CLASS (GET_CODE (addr
)) != RTX_AUTOINC
)
5930 addr
= XEXP (addr
, 0);
5932 if (addr
== stack_pointer_rtx
)
5933 return register_no_sp_elim_operand (other
, VOIDmode
);
5935 return !reg_overlap_mentioned_p(other
, addr
);
5938 /* Perform target dependent optabs initialization. */
5940 h8300_init_libfuncs (void)
5942 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
5943 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
5944 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
5945 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
5946 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
5949 /* Worker function for TARGET_FUNCTION_VALUE.
5951 On the H8 the return value is in R0/R1. */
5954 h8300_function_value (const_tree ret_type
,
5955 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
5956 bool outgoing ATTRIBUTE_UNUSED
)
5958 return gen_rtx_REG (TYPE_MODE (ret_type
), R0_REG
);
5961 /* Worker function for TARGET_LIBCALL_VALUE.
5963 On the H8 the return value is in R0/R1. */
5966 h8300_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5968 return gen_rtx_REG (mode
, R0_REG
);
5971 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5973 On the H8, R0 is the only register thus used. */
5976 h8300_function_value_regno_p (const unsigned int regno
)
5978 return (regno
== R0_REG
);
5981 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5984 h8300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5986 return (TYPE_MODE (type
) == BLKmode
5987 || GET_MODE_SIZE (TYPE_MODE (type
)) > (TARGET_H8300
? 4 : 8));
5990 /* We emit the entire trampoline here. Depending on the pointer size,
5991 we use a different trampoline.
5995 1 0000 7903xxxx mov.w #0x1234,r3
5996 2 0004 5A00xxxx jmp @0x1234
6001 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
6002 3 0006 5Axxxxxx jmp @0x123456
6007 h8300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
6009 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6012 if (Pmode
== HImode
)
6014 mem
= adjust_address (m_tramp
, HImode
, 0);
6015 emit_move_insn (mem
, GEN_INT (0x7903));
6016 mem
= adjust_address (m_tramp
, Pmode
, 2);
6017 emit_move_insn (mem
, cxt
);
6018 mem
= adjust_address (m_tramp
, HImode
, 4);
6019 emit_move_insn (mem
, GEN_INT (0x5a00));
6020 mem
= adjust_address (m_tramp
, Pmode
, 6);
6021 emit_move_insn (mem
, fnaddr
);
6027 mem
= adjust_address (m_tramp
, HImode
, 0);
6028 emit_move_insn (mem
, GEN_INT (0x7a03));
6029 mem
= adjust_address (m_tramp
, Pmode
, 2);
6030 emit_move_insn (mem
, cxt
);
6032 tem
= copy_to_reg (fnaddr
);
6033 emit_insn (gen_andsi3 (tem
, tem
, GEN_INT (0x00ffffff)));
6034 emit_insn (gen_iorsi3 (tem
, tem
, GEN_INT (0x5a000000)));
6035 mem
= adjust_address (m_tramp
, SImode
, 6);
6036 emit_move_insn (mem
, tem
);
6040 /* Initialize the GCC target structure. */
6041 #undef TARGET_ATTRIBUTE_TABLE
6042 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6044 #undef TARGET_ASM_ALIGNED_HI_OP
6045 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6047 #undef TARGET_ASM_FILE_START
6048 #define TARGET_ASM_FILE_START h8300_file_start
6049 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6050 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6052 #undef TARGET_ASM_FILE_END
6053 #define TARGET_ASM_FILE_END h8300_file_end
6055 #undef TARGET_PRINT_OPERAND
6056 #define TARGET_PRINT_OPERAND h8300_print_operand
6057 #undef TARGET_PRINT_OPERAND_ADDRESS
6058 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6059 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6060 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6062 #undef TARGET_ENCODE_SECTION_INFO
6063 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6065 #undef TARGET_INSERT_ATTRIBUTES
6066 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6068 #undef TARGET_REGISTER_MOVE_COST
6069 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6071 #undef TARGET_RTX_COSTS
6072 #define TARGET_RTX_COSTS h8300_rtx_costs
6074 #undef TARGET_INIT_LIBFUNCS
6075 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6077 #undef TARGET_FUNCTION_VALUE
6078 #define TARGET_FUNCTION_VALUE h8300_function_value
6080 #undef TARGET_LIBCALL_VALUE
6081 #define TARGET_LIBCALL_VALUE h8300_libcall_value
6083 #undef TARGET_FUNCTION_VALUE_REGNO_P
6084 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6086 #undef TARGET_RETURN_IN_MEMORY
6087 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6089 #undef TARGET_FUNCTION_ARG
6090 #define TARGET_FUNCTION_ARG h8300_function_arg
6092 #undef TARGET_FUNCTION_ARG_ADVANCE
6093 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6095 #undef TARGET_MACHINE_DEPENDENT_REORG
6096 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6098 #undef TARGET_HARD_REGNO_SCRATCH_OK
6099 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6101 #undef TARGET_LEGITIMATE_ADDRESS_P
6102 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6104 #undef TARGET_CAN_ELIMINATE
6105 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
6107 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6108 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6110 #undef TARGET_TRAMPOLINE_INIT
6111 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6113 #undef TARGET_OPTION_OVERRIDE
6114 #define TARGET_OPTION_OVERRIDE h8300_option_override
6116 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6117 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6119 struct gcc_target targetm
= TARGET_INITIALIZER
;