1 /* Copyright (C) 1997-2014 Free Software Foundation, Inc.
2 Contributed by Red Hat, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "stor-layout.h"
27 #include "stringpool.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
48 #include "insn-codes.h"
50 #include "diagnostic-core.h"
52 #include "dominance.h"
58 #include "cfgcleanup.h"
59 #include "basic-block.h"
63 #include "target-def.h"
64 #include "targhooks.h"
65 #include "langhooks.h"
73 #define FRV_INLINE inline
76 /* The maximum number of distinct NOP patterns. There are three:
77 nop, fnop and mnop. */
78 #define NUM_NOP_PATTERNS 3
80 /* Classification of instructions and units: integer, floating-point/media,
81 branch and control. */
82 enum frv_insn_group
{ GROUP_I
, GROUP_FM
, GROUP_B
, GROUP_C
, NUM_GROUPS
};
84 /* The DFA names of the units, in packet order. */
85 static const char *const frv_unit_names
[] =
95 /* The classification of each unit in frv_unit_names[]. */
96 static const enum frv_insn_group frv_unit_groups
[ARRAY_SIZE (frv_unit_names
)] =
106 /* Return the DFA unit code associated with the Nth unit of integer
107 or floating-point group GROUP, */
108 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
110 /* Return the number of integer or floating-point unit UNIT
111 (1 for I1, 2 for F2, etc.). */
112 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
114 /* The DFA unit number for each unit in frv_unit_names[]. */
115 static int frv_unit_codes
[ARRAY_SIZE (frv_unit_names
)];
117 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
118 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
119 no instruction of type T has been seen. */
120 static unsigned int frv_type_to_unit
[TYPE_UNKNOWN
+ 1];
122 /* An array of dummy nop INSNs, one for each type of nop that the
124 static GTY(()) rtx_insn
*frv_nops
[NUM_NOP_PATTERNS
];
126 /* The number of nop instructions in frv_nops[]. */
127 static unsigned int frv_num_nops
;
129 /* The type of access. FRV_IO_UNKNOWN means the access can be either
130 a read or a write. */
131 enum frv_io_type
{ FRV_IO_UNKNOWN
, FRV_IO_READ
, FRV_IO_WRITE
};
133 /* Information about one __builtin_read or __builtin_write access, or
134 the combination of several such accesses. The most general value
135 is all-zeros (an unknown access to an unknown address). */
137 enum frv_io_type type
;
139 /* The constant address being accessed, or zero if not known. */
140 HOST_WIDE_INT const_address
;
142 /* The run-time address, as used in operand 0 of the membar pattern. */
146 /* Return true if instruction INSN should be packed with the following
148 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
150 /* Set the value of PACKING_FLAG_P(INSN). */
151 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
152 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
154 /* Loop with REG set to each hard register in rtx X. */
155 #define FOR_EACH_REGNO(REG, X) \
156 for (REG = REGNO (X); \
157 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
160 /* This structure contains machine specific function data. */
161 struct GTY(()) machine_function
163 /* True if we have created an rtx that relies on the stack frame. */
166 /* True if this function contains at least one __builtin_{read,write}*. */
170 /* Temporary register allocation support structure. */
171 typedef struct frv_tmp_reg_struct
173 HARD_REG_SET regs
; /* possible registers to allocate */
174 int next_reg
[N_REG_CLASSES
]; /* next register to allocate per class */
178 /* Register state information for VLIW re-packing phase. */
179 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
180 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
181 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
182 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
184 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
186 typedef unsigned char regstate_t
;
188 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
196 /* Information required by frv_frame_access. */
199 /* This field is FRV_LOAD if registers are to be loaded from the stack and
200 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
201 the move is being done by the prologue code while FRV_LOAD implies it
202 is being done by the epilogue. */
203 enum frv_stack_op op
;
205 /* The base register to use when accessing the stack. This may be the
206 frame pointer, stack pointer, or a temporary. The choice of register
207 depends on which part of the frame is being accessed and how big the
211 /* The offset of BASE from the bottom of the current frame, in bytes. */
213 } frv_frame_accessor_t
;
215 /* Conditional execution support gathered together in one structure. */
218 /* Linked list of insns to add if the conditional execution conversion was
219 successful. Each link points to an EXPR_LIST which points to the pattern
220 of the insn to add, and the insn to be inserted before. */
221 rtx added_insns_list
;
223 /* Identify which registers are safe to allocate for if conversions to
224 conditional execution. We keep the last allocated register in the
225 register classes between COND_EXEC statements. This will mean we allocate
226 different registers for each different COND_EXEC group if we can. This
227 might allow the scheduler to intermix two different COND_EXEC sections. */
228 frv_tmp_reg_t tmp_reg
;
230 /* For nested IFs, identify which CC registers are used outside of setting
231 via a compare isnsn, and using via a check insn. This will allow us to
232 know if we can rewrite the register to use a different register that will
233 be paired with the CR register controlling the nested IF-THEN blocks. */
234 HARD_REG_SET nested_cc_ok_rewrite
;
236 /* Temporary registers allocated to hold constants during conditional
238 rtx scratch_regs
[FIRST_PSEUDO_REGISTER
];
240 /* Current number of temp registers available. */
241 int cur_scratch_regs
;
243 /* Number of nested conditional execution blocks. */
244 int num_nested_cond_exec
;
246 /* Map of insns that set up constants in scratch registers. */
247 bitmap scratch_insns_bitmap
;
249 /* Conditional execution test register (CC0..CC7). */
252 /* Conditional execution compare register that is paired with cr_reg, so that
253 nested compares can be done. The csubcc and caddcc instructions don't
254 have enough bits to specify both a CC register to be set and a CR register
255 to do the test on, so the same bit number is used for both. Needless to
256 say, this is rather inconvenient for GCC. */
259 /* Extra CR registers used for &&, ||. */
263 /* Previous CR used in nested if, to make sure we are dealing with the same
264 nested if as the previous statement. */
265 rtx last_nested_if_cr
;
269 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt
;
271 /* Map register number to smallest register class. */
272 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
];
274 /* Cached value of frv_stack_info. */
275 static frv_stack_t
*frv_stack_cache
= (frv_stack_t
*)0;
277 /* Forward references */
279 static void frv_option_override (void);
280 static bool frv_legitimate_address_p (machine_mode
, rtx
, bool);
281 static int frv_default_flags_for_cpu (void);
282 static int frv_string_begins_with (const char *, const char *);
283 static FRV_INLINE
bool frv_small_data_reloc_p (rtx
, int);
284 static void frv_print_operand (FILE *, rtx
, int);
285 static void frv_print_operand_address (FILE *, rtx
);
286 static bool frv_print_operand_punct_valid_p (unsigned char code
);
287 static void frv_print_operand_memory_reference_reg
289 static void frv_print_operand_memory_reference (FILE *, rtx
, int);
290 static int frv_print_operand_jump_hint (rtx_insn
*);
291 static const char *comparison_string (enum rtx_code
, rtx
);
292 static rtx
frv_function_value (const_tree
, const_tree
,
294 static rtx
frv_libcall_value (machine_mode
,
296 static FRV_INLINE
int frv_regno_ok_for_base_p (int, int);
297 static rtx
single_set_pattern (rtx
);
298 static int frv_function_contains_far_jump (void);
299 static rtx
frv_alloc_temp_reg (frv_tmp_reg_t
*,
303 static rtx
frv_frame_offset_rtx (int);
304 static rtx
frv_frame_mem (machine_mode
, rtx
, int);
305 static rtx
frv_dwarf_store (rtx
, int);
306 static void frv_frame_insn (rtx
, rtx
);
307 static void frv_frame_access (frv_frame_accessor_t
*,
309 static void frv_frame_access_multi (frv_frame_accessor_t
*,
311 static void frv_frame_access_standard_regs (enum frv_stack_op
,
313 static struct machine_function
*frv_init_machine_status (void);
314 static rtx
frv_int_to_acc (enum insn_code
, int, rtx
);
315 static machine_mode
frv_matching_accg_mode (machine_mode
);
316 static rtx
frv_read_argument (tree
, unsigned int);
317 static rtx
frv_read_iacc_argument (machine_mode
, tree
, unsigned int);
318 static int frv_check_constant_argument (enum insn_code
, int, rtx
);
319 static rtx
frv_legitimize_target (enum insn_code
, rtx
);
320 static rtx
frv_legitimize_argument (enum insn_code
, int, rtx
);
321 static rtx
frv_legitimize_tls_address (rtx
, enum tls_model
);
322 static rtx
frv_legitimize_address (rtx
, rtx
, machine_mode
);
323 static rtx
frv_expand_set_builtin (enum insn_code
, tree
, rtx
);
324 static rtx
frv_expand_unop_builtin (enum insn_code
, tree
, rtx
);
325 static rtx
frv_expand_binop_builtin (enum insn_code
, tree
, rtx
);
326 static rtx
frv_expand_cut_builtin (enum insn_code
, tree
, rtx
);
327 static rtx
frv_expand_binopimm_builtin (enum insn_code
, tree
, rtx
);
328 static rtx
frv_expand_voidbinop_builtin (enum insn_code
, tree
);
329 static rtx
frv_expand_int_void2arg (enum insn_code
, tree
);
330 static rtx
frv_expand_prefetches (enum insn_code
, tree
);
331 static rtx
frv_expand_voidtriop_builtin (enum insn_code
, tree
);
332 static rtx
frv_expand_voidaccop_builtin (enum insn_code
, tree
);
333 static rtx
frv_expand_mclracc_builtin (tree
);
334 static rtx
frv_expand_mrdacc_builtin (enum insn_code
, tree
);
335 static rtx
frv_expand_mwtacc_builtin (enum insn_code
, tree
);
336 static rtx
frv_expand_noargs_builtin (enum insn_code
);
337 static void frv_split_iacc_move (rtx
, rtx
);
338 static rtx
frv_emit_comparison (enum rtx_code
, rtx
, rtx
);
339 static void frv_ifcvt_add_insn (rtx
, rtx
, int);
340 static rtx
frv_ifcvt_rewrite_mem (rtx
, machine_mode
, rtx
);
341 static rtx
frv_ifcvt_load_value (rtx
, rtx
);
342 static unsigned int frv_insn_unit (rtx_insn
*);
343 static bool frv_issues_to_branch_unit_p (rtx_insn
*);
344 static int frv_cond_flags (rtx
);
345 static bool frv_regstate_conflict_p (regstate_t
, regstate_t
);
346 static bool frv_registers_conflict_p (rtx
);
347 static void frv_registers_update_1 (rtx
, const_rtx
, void *);
348 static void frv_registers_update (rtx
);
349 static void frv_start_packet (void);
350 static void frv_start_packet_block (void);
351 static void frv_finish_packet (void (*) (void));
352 static bool frv_pack_insn_p (rtx_insn
*);
353 static void frv_add_insn_to_packet (rtx_insn
*);
354 static void frv_insert_nop_in_packet (rtx_insn
*);
355 static bool frv_for_each_packet (void (*) (void));
356 static bool frv_sort_insn_group_1 (enum frv_insn_group
,
357 unsigned int, unsigned int,
358 unsigned int, unsigned int,
360 static int frv_compare_insns (const void *, const void *);
361 static void frv_sort_insn_group (enum frv_insn_group
);
362 static void frv_reorder_packet (void);
363 static void frv_fill_unused_units (enum frv_insn_group
);
364 static void frv_align_label (void);
365 static void frv_reorg_packet (void);
366 static void frv_register_nop (rtx
);
367 static void frv_reorg (void);
368 static void frv_pack_insns (void);
369 static void frv_function_prologue (FILE *, HOST_WIDE_INT
);
370 static void frv_function_epilogue (FILE *, HOST_WIDE_INT
);
371 static bool frv_assemble_integer (rtx
, unsigned, int);
372 static void frv_init_builtins (void);
373 static rtx
frv_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
374 static void frv_init_libfuncs (void);
375 static bool frv_in_small_data_p (const_tree
);
376 static void frv_asm_output_mi_thunk
377 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
378 static void frv_setup_incoming_varargs (cumulative_args_t
,
381 static rtx
frv_expand_builtin_saveregs (void);
382 static void frv_expand_builtin_va_start (tree
, rtx
);
383 static bool frv_rtx_costs (rtx
, int, int, int, int*,
385 static int frv_register_move_cost (machine_mode
,
386 reg_class_t
, reg_class_t
);
387 static int frv_memory_move_cost (machine_mode
,
389 static void frv_asm_out_constructor (rtx
, int);
390 static void frv_asm_out_destructor (rtx
, int);
391 static bool frv_function_symbol_referenced_p (rtx
);
392 static bool frv_legitimate_constant_p (machine_mode
, rtx
);
393 static bool frv_cannot_force_const_mem (machine_mode
, rtx
);
394 static const char *unspec_got_name (int);
395 static void frv_output_const_unspec (FILE *,
396 const struct frv_unspec
*);
397 static bool frv_function_ok_for_sibcall (tree
, tree
);
398 static rtx
frv_struct_value_rtx (tree
, int);
399 static bool frv_must_pass_in_stack (machine_mode mode
, const_tree type
);
400 static int frv_arg_partial_bytes (cumulative_args_t
, machine_mode
,
402 static rtx
frv_function_arg (cumulative_args_t
, machine_mode
,
404 static rtx
frv_function_incoming_arg (cumulative_args_t
, machine_mode
,
406 static void frv_function_arg_advance (cumulative_args_t
, machine_mode
,
408 static unsigned int frv_function_arg_boundary (machine_mode
,
410 static void frv_output_dwarf_dtprel (FILE *, int, rtx
)
412 static reg_class_t
frv_secondary_reload (bool, rtx
, reg_class_t
,
414 secondary_reload_info
*);
415 static bool frv_frame_pointer_required (void);
416 static bool frv_can_eliminate (const int, const int);
417 static void frv_conditional_register_usage (void);
418 static void frv_trampoline_init (rtx
, tree
, rtx
);
419 static bool frv_class_likely_spilled_p (reg_class_t
);
421 /* Initialize the GCC target structure. */
422 #undef TARGET_PRINT_OPERAND
423 #define TARGET_PRINT_OPERAND frv_print_operand
424 #undef TARGET_PRINT_OPERAND_ADDRESS
425 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
426 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
427 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
428 #undef TARGET_ASM_FUNCTION_PROLOGUE
429 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
430 #undef TARGET_ASM_FUNCTION_EPILOGUE
431 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
432 #undef TARGET_ASM_INTEGER
433 #define TARGET_ASM_INTEGER frv_assemble_integer
434 #undef TARGET_OPTION_OVERRIDE
435 #define TARGET_OPTION_OVERRIDE frv_option_override
436 #undef TARGET_INIT_BUILTINS
437 #define TARGET_INIT_BUILTINS frv_init_builtins
438 #undef TARGET_EXPAND_BUILTIN
439 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
440 #undef TARGET_INIT_LIBFUNCS
441 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
442 #undef TARGET_IN_SMALL_DATA_P
443 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
444 #undef TARGET_REGISTER_MOVE_COST
445 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost
446 #undef TARGET_MEMORY_MOVE_COST
447 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
448 #undef TARGET_RTX_COSTS
449 #define TARGET_RTX_COSTS frv_rtx_costs
450 #undef TARGET_ASM_CONSTRUCTOR
451 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
452 #undef TARGET_ASM_DESTRUCTOR
453 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
455 #undef TARGET_ASM_OUTPUT_MI_THUNK
456 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
457 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
458 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
460 #undef TARGET_SCHED_ISSUE_RATE
461 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
463 #undef TARGET_LEGITIMIZE_ADDRESS
464 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
466 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
467 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
468 #undef TARGET_LEGITIMATE_CONSTANT_P
469 #define TARGET_LEGITIMATE_CONSTANT_P frv_legitimate_constant_p
470 #undef TARGET_CANNOT_FORCE_CONST_MEM
471 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
473 #undef TARGET_HAVE_TLS
474 #define TARGET_HAVE_TLS HAVE_AS_TLS
476 #undef TARGET_STRUCT_VALUE_RTX
477 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
478 #undef TARGET_MUST_PASS_IN_STACK
479 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
480 #undef TARGET_PASS_BY_REFERENCE
481 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
482 #undef TARGET_ARG_PARTIAL_BYTES
483 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
484 #undef TARGET_FUNCTION_ARG
485 #define TARGET_FUNCTION_ARG frv_function_arg
486 #undef TARGET_FUNCTION_INCOMING_ARG
487 #define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg
488 #undef TARGET_FUNCTION_ARG_ADVANCE
489 #define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance
490 #undef TARGET_FUNCTION_ARG_BOUNDARY
491 #define TARGET_FUNCTION_ARG_BOUNDARY frv_function_arg_boundary
493 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
494 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
495 #undef TARGET_SETUP_INCOMING_VARARGS
496 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
497 #undef TARGET_MACHINE_DEPENDENT_REORG
498 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
500 #undef TARGET_EXPAND_BUILTIN_VA_START
501 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
504 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
505 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
508 #undef TARGET_CLASS_LIKELY_SPILLED_P
509 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
511 #undef TARGET_SECONDARY_RELOAD
512 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
514 #undef TARGET_LEGITIMATE_ADDRESS_P
515 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
517 #undef TARGET_FRAME_POINTER_REQUIRED
518 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
520 #undef TARGET_CAN_ELIMINATE
521 #define TARGET_CAN_ELIMINATE frv_can_eliminate
523 #undef TARGET_CONDITIONAL_REGISTER_USAGE
524 #define TARGET_CONDITIONAL_REGISTER_USAGE frv_conditional_register_usage
526 #undef TARGET_TRAMPOLINE_INIT
527 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
529 #undef TARGET_FUNCTION_VALUE
530 #define TARGET_FUNCTION_VALUE frv_function_value
531 #undef TARGET_LIBCALL_VALUE
532 #define TARGET_LIBCALL_VALUE frv_libcall_value
534 struct gcc_target targetm
= TARGET_INITIALIZER
;
536 #define FRV_SYMBOL_REF_TLS_P(RTX) \
537 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
540 /* Any function call that satisfies the machine-independent
541 requirements is eligible on FR-V. */
544 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
545 tree exp ATTRIBUTE_UNUSED
)
550 /* Return true if SYMBOL is a small data symbol and relocation RELOC
551 can be used to access it directly in a load or store. */
553 static FRV_INLINE
bool
554 frv_small_data_reloc_p (rtx symbol
, int reloc
)
556 return (GET_CODE (symbol
) == SYMBOL_REF
557 && SYMBOL_REF_SMALL_P (symbol
)
558 && (!TARGET_FDPIC
|| flag_pic
== 1)
559 && (reloc
== R_FRV_GOTOFF12
|| reloc
== R_FRV_GPREL12
));
562 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
566 frv_const_unspec_p (rtx x
, struct frv_unspec
*unspec
)
568 if (GET_CODE (x
) == CONST
)
572 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
574 unspec
->offset
+= INTVAL (XEXP (x
, 1));
577 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_GOT
)
579 unspec
->symbol
= XVECEXP (x
, 0, 0);
580 unspec
->reloc
= INTVAL (XVECEXP (x
, 0, 1));
582 if (unspec
->offset
== 0)
585 if (frv_small_data_reloc_p (unspec
->symbol
, unspec
->reloc
)
586 && unspec
->offset
> 0
587 && unspec
->offset
< g_switch_value
)
594 /* Decide whether we can force certain constants to memory. If we
595 decide we can't, the caller should be able to cope with it in
598 We never allow constants to be forced into memory for TARGET_FDPIC.
599 This is necessary for several reasons:
601 1. Since frv_legitimate_constant_p rejects constant pool addresses, the
602 target-independent code will try to force them into the constant
603 pool, thus leading to infinite recursion.
605 2. We can never introduce new constant pool references during reload.
606 Any such reference would require use of the pseudo FDPIC register.
608 3. We can't represent a constant added to a function pointer (which is
609 not the same as a pointer to a function+constant).
611 4. In many cases, it's more efficient to calculate the constant in-line. */
614 frv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
,
615 rtx x ATTRIBUTE_UNUSED
)
621 frv_default_flags_for_cpu (void)
623 switch (frv_cpu_type
)
625 case FRV_CPU_GENERIC
:
626 return MASK_DEFAULT_FRV
;
629 return MASK_DEFAULT_FR550
;
633 return MASK_DEFAULT_FR500
;
636 return MASK_DEFAULT_FR450
;
640 return MASK_DEFAULT_FR400
;
644 return MASK_DEFAULT_SIMPLE
;
651 /* Implement TARGET_OPTION_OVERRIDE. */
654 frv_option_override (void)
659 target_flags
|= (frv_default_flags_for_cpu () & ~target_flags_explicit
);
661 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
662 linker about linking pic and non-pic code. */
665 if (!flag_pic
) /* -fPIC */
668 if (!global_options_set
.x_g_switch_value
) /* -G0 */
674 /* A C expression whose value is a register class containing hard
675 register REGNO. In general there is more than one such class;
676 choose a class which is "minimal", meaning that no smaller class
677 also contains the register. */
679 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
681 enum reg_class rclass
;
685 int gpr_reg
= regno
- GPR_FIRST
;
687 if (gpr_reg
== GR8_REG
)
690 else if (gpr_reg
== GR9_REG
)
693 else if (gpr_reg
== GR14_REG
)
694 rclass
= FDPIC_FPTR_REGS
;
696 else if (gpr_reg
== FDPIC_REGNO
)
699 else if ((gpr_reg
& 3) == 0)
702 else if ((gpr_reg
& 1) == 0)
709 else if (FPR_P (regno
))
711 int fpr_reg
= regno
- GPR_FIRST
;
712 if ((fpr_reg
& 3) == 0)
713 rclass
= QUAD_FPR_REGS
;
715 else if ((fpr_reg
& 1) == 0)
722 else if (regno
== LR_REGNO
)
725 else if (regno
== LCR_REGNO
)
728 else if (ICC_P (regno
))
731 else if (FCC_P (regno
))
734 else if (ICR_P (regno
))
737 else if (FCR_P (regno
))
740 else if (ACC_P (regno
))
742 int r
= regno
- ACC_FIRST
;
744 rclass
= QUAD_ACC_REGS
;
745 else if ((r
& 1) == 0)
746 rclass
= EVEN_ACC_REGS
;
751 else if (ACCG_P (regno
))
757 regno_reg_class
[regno
] = rclass
;
760 /* Check for small data option */
761 if (!global_options_set
.x_g_switch_value
&& !TARGET_LIBPIC
)
762 g_switch_value
= SDATA_DEFAULT_SIZE
;
764 /* There is no single unaligned SI op for PIC code. Sometimes we
765 need to use ".4byte" and sometimes we need to use ".picptr".
766 See frv_assemble_integer for details. */
767 if (flag_pic
|| TARGET_FDPIC
)
768 targetm
.asm_out
.unaligned_op
.si
= 0;
770 if ((target_flags_explicit
& MASK_LINKED_FP
) == 0)
771 target_flags
|= MASK_LINKED_FP
;
773 if ((target_flags_explicit
& MASK_OPTIMIZE_MEMBAR
) == 0)
774 target_flags
|= MASK_OPTIMIZE_MEMBAR
;
776 for (i
= 0; i
< ARRAY_SIZE (frv_unit_names
); i
++)
777 frv_unit_codes
[i
] = get_cpu_unit_code (frv_unit_names
[i
]);
779 for (i
= 0; i
< ARRAY_SIZE (frv_type_to_unit
); i
++)
780 frv_type_to_unit
[i
] = ARRAY_SIZE (frv_unit_codes
);
782 init_machine_status
= frv_init_machine_status
;
786 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
789 frv_string_begins_with (const char *name
, const char *prefix
)
791 const int prefix_len
= strlen (prefix
);
793 /* Remember: NAME's length includes the null terminator. */
794 return (strncmp (name
, prefix
, prefix_len
) == 0);
797 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
800 frv_conditional_register_usage (void)
804 for (i
= GPR_FIRST
+ NUM_GPRS
; i
<= GPR_LAST
; i
++)
805 fixed_regs
[i
] = call_used_regs
[i
] = 1;
807 for (i
= FPR_FIRST
+ NUM_FPRS
; i
<= FPR_LAST
; i
++)
808 fixed_regs
[i
] = call_used_regs
[i
] = 1;
810 /* Reserve the registers used for conditional execution. At present, we need
811 1 ICC and 1 ICR register. */
812 fixed_regs
[ICC_TEMP
] = call_used_regs
[ICC_TEMP
] = 1;
813 fixed_regs
[ICR_TEMP
] = call_used_regs
[ICR_TEMP
] = 1;
817 fixed_regs
[ICC_FIRST
] = call_used_regs
[ICC_FIRST
] = 1;
818 fixed_regs
[FCC_FIRST
] = call_used_regs
[FCC_FIRST
] = 1;
819 fixed_regs
[ICR_FIRST
] = call_used_regs
[ICR_FIRST
] = 1;
820 fixed_regs
[FCR_FIRST
] = call_used_regs
[FCR_FIRST
] = 1;
824 fixed_regs
[GPR_FIRST
+ 16] = fixed_regs
[GPR_FIRST
+ 17] =
825 call_used_regs
[GPR_FIRST
+ 16] = call_used_regs
[GPR_FIRST
+ 17] = 0;
828 /* If -fpic, SDA_BASE_REG is the PIC register. */
829 if (g_switch_value
== 0 && !flag_pic
)
830 fixed_regs
[SDA_BASE_REG
] = call_used_regs
[SDA_BASE_REG
] = 0;
833 fixed_regs
[PIC_REGNO
] = call_used_regs
[PIC_REGNO
] = 0;
839 * Compute the stack frame layout
842 * +---------------+-----------------------+-----------------------+
843 * |Register |type |caller-save/callee-save|
844 * +---------------+-----------------------+-----------------------+
845 * |GR0 |Zero register | - |
846 * |GR1 |Stack pointer(SP) | - |
847 * |GR2 |Frame pointer(FP) | - |
848 * |GR3 |Hidden parameter | caller save |
849 * |GR4-GR7 | - | caller save |
850 * |GR8-GR13 |Argument register | caller save |
851 * |GR14-GR15 | - | caller save |
852 * |GR16-GR31 | - | callee save |
853 * |GR32-GR47 | - | caller save |
854 * |GR48-GR63 | - | callee save |
855 * |FR0-FR15 | - | caller save |
856 * |FR16-FR31 | - | callee save |
857 * |FR32-FR47 | - | caller save |
858 * |FR48-FR63 | - | callee save |
859 * +---------------+-----------------------+-----------------------+
863 * SP-> |-----------------------------------|
865 * |-----------------------------------|
866 * | Register save area |
867 * |-----------------------------------|
868 * | Local variable save area |
869 * FP-> |-----------------------------------|
871 * |-----------------------------------|
872 * | Hidden parameter save area |
873 * |-----------------------------------|
874 * | Return address(LR) storage area |
875 * |-----------------------------------|
876 * | Padding for alignment |
877 * |-----------------------------------|
878 * | Register argument area |
879 * OLD SP-> |-----------------------------------|
881 * |-----------------------------------|
884 * Argument area/Parameter area:
886 * When a function is called, this area is used for argument transfer. When
887 * the argument is set up by the caller function, this area is referred to as
888 * the argument area. When the argument is referenced by the callee function,
889 * this area is referred to as the parameter area. The area is allocated when
890 * all arguments cannot be placed on the argument register at the time of
893 * Register save area:
895 * This is a register save area that must be guaranteed for the caller
896 * function. This area is not secured when the register save operation is not
899 * Local variable save area:
901 * This is the area for local variables and temporary variables.
905 * This area stores the FP value of the caller function.
907 * Hidden parameter save area:
909 * This area stores the start address of the return value storage
910 * area for a struct/union return function.
911 * When a struct/union is used as the return value, the caller
912 * function stores the return value storage area start address in
913 * register GR3 and passes it to the caller function.
914 * The callee function interprets the address stored in the GR3
915 * as the return value storage area start address.
916 * When register GR3 needs to be saved into memory, the callee
917 * function saves it in the hidden parameter save area. This
918 * area is not secured when the save operation is not needed.
920 * Return address(LR) storage area:
922 * This area saves the LR. The LR stores the address of a return to the caller
923 * function for the purpose of function calling.
925 * Argument register area:
927 * This area saves the argument register. This area is not secured when the
928 * save operation is not needed.
932 * Arguments, the count of which equals the count of argument registers (6
933 * words), are positioned in registers GR8 to GR13 and delivered to the callee
934 * function. When a struct/union return function is called, the return value
935 * area address is stored in register GR3. Arguments not placed in the
936 * argument registers will be stored in the stack argument area for transfer
937 * purposes. When an 8-byte type argument is to be delivered using registers,
938 * it is divided into two and placed in two registers for transfer. When
939 * argument registers must be saved to memory, the callee function secures an
940 * argument register save area in the stack. In this case, a continuous
941 * argument register save area must be established in the parameter area. The
942 * argument register save area must be allocated as needed to cover the size of
943 * the argument register to be saved. If the function has a variable count of
944 * arguments, it saves all argument registers in the argument register save
947 * Argument Extension Format:
949 * When an argument is to be stored in the stack, its type is converted to an
950 * extended type in accordance with the individual argument type. The argument
951 * is freed by the caller function after the return from the callee function is
954 * +-----------------------+---------------+------------------------+
955 * | Argument Type |Extended Type |Stack Storage Size(byte)|
956 * +-----------------------+---------------+------------------------+
958 * |signed char |int | 4 |
959 * |unsigned char |int | 4 |
960 * |[signed] short int |int | 4 |
961 * |unsigned short int |int | 4 |
962 * |[signed] int |No extension | 4 |
963 * |unsigned int |No extension | 4 |
964 * |[signed] long int |No extension | 4 |
965 * |unsigned long int |No extension | 4 |
966 * |[signed] long long int |No extension | 8 |
967 * |unsigned long long int |No extension | 8 |
968 * |float |double | 8 |
969 * |double |No extension | 8 |
970 * |long double |No extension | 8 |
971 * |pointer |No extension | 4 |
972 * |struct/union |- | 4 (*1) |
973 * +-----------------------+---------------+------------------------+
975 * When a struct/union is to be delivered as an argument, the caller copies it
976 * to the local variable area and delivers the address of that area.
980 * +-------------------------------+----------------------+
981 * |Return Value Type |Return Value Interface|
982 * +-------------------------------+----------------------+
984 * |[signed|unsigned] char |GR8 |
985 * |[signed|unsigned] short int |GR8 |
986 * |[signed|unsigned] int |GR8 |
987 * |[signed|unsigned] long int |GR8 |
989 * |[signed|unsigned] long long int|GR8 & GR9 |
991 * |double |GR8 & GR9 |
992 * |long double |GR8 & GR9 |
993 * |struct/union |(*1) |
994 * +-------------------------------+----------------------+
996 * When a struct/union is used as the return value, the caller function stores
997 * the start address of the return value storage area into GR3 and then passes
998 * it to the callee function. The callee function interprets GR3 as the start
999 * address of the return value storage area. When this address needs to be
1000 * saved in memory, the callee function secures the hidden parameter save area
1001 * and saves the address in that area.
1005 frv_stack_info (void)
1007 static frv_stack_t info
, zero_info
;
1008 frv_stack_t
*info_ptr
= &info
;
1009 tree fndecl
= current_function_decl
;
1017 /* If we've already calculated the values and reload is complete,
1019 if (frv_stack_cache
)
1020 return frv_stack_cache
;
1022 /* Zero all fields. */
1025 /* Set up the register range information. */
1026 info_ptr
->regs
[STACK_REGS_GPR
].name
= "gpr";
1027 info_ptr
->regs
[STACK_REGS_GPR
].first
= LAST_ARG_REGNUM
+ 1;
1028 info_ptr
->regs
[STACK_REGS_GPR
].last
= GPR_LAST
;
1029 info_ptr
->regs
[STACK_REGS_GPR
].dword_p
= TRUE
;
1031 info_ptr
->regs
[STACK_REGS_FPR
].name
= "fpr";
1032 info_ptr
->regs
[STACK_REGS_FPR
].first
= FPR_FIRST
;
1033 info_ptr
->regs
[STACK_REGS_FPR
].last
= FPR_LAST
;
1034 info_ptr
->regs
[STACK_REGS_FPR
].dword_p
= TRUE
;
1036 info_ptr
->regs
[STACK_REGS_LR
].name
= "lr";
1037 info_ptr
->regs
[STACK_REGS_LR
].first
= LR_REGNO
;
1038 info_ptr
->regs
[STACK_REGS_LR
].last
= LR_REGNO
;
1039 info_ptr
->regs
[STACK_REGS_LR
].special_p
= 1;
1041 info_ptr
->regs
[STACK_REGS_CC
].name
= "cc";
1042 info_ptr
->regs
[STACK_REGS_CC
].first
= CC_FIRST
;
1043 info_ptr
->regs
[STACK_REGS_CC
].last
= CC_LAST
;
1044 info_ptr
->regs
[STACK_REGS_CC
].field_p
= TRUE
;
1046 info_ptr
->regs
[STACK_REGS_LCR
].name
= "lcr";
1047 info_ptr
->regs
[STACK_REGS_LCR
].first
= LCR_REGNO
;
1048 info_ptr
->regs
[STACK_REGS_LCR
].last
= LCR_REGNO
;
1050 info_ptr
->regs
[STACK_REGS_STDARG
].name
= "stdarg";
1051 info_ptr
->regs
[STACK_REGS_STDARG
].first
= FIRST_ARG_REGNUM
;
1052 info_ptr
->regs
[STACK_REGS_STDARG
].last
= LAST_ARG_REGNUM
;
1053 info_ptr
->regs
[STACK_REGS_STDARG
].dword_p
= 1;
1054 info_ptr
->regs
[STACK_REGS_STDARG
].special_p
= 1;
1056 info_ptr
->regs
[STACK_REGS_STRUCT
].name
= "struct";
1057 info_ptr
->regs
[STACK_REGS_STRUCT
].first
= FRV_STRUCT_VALUE_REGNUM
;
1058 info_ptr
->regs
[STACK_REGS_STRUCT
].last
= FRV_STRUCT_VALUE_REGNUM
;
1059 info_ptr
->regs
[STACK_REGS_STRUCT
].special_p
= 1;
1061 info_ptr
->regs
[STACK_REGS_FP
].name
= "fp";
1062 info_ptr
->regs
[STACK_REGS_FP
].first
= FRAME_POINTER_REGNUM
;
1063 info_ptr
->regs
[STACK_REGS_FP
].last
= FRAME_POINTER_REGNUM
;
1064 info_ptr
->regs
[STACK_REGS_FP
].special_p
= 1;
1066 /* Determine if this is a stdarg function. If so, allocate space to store
1073 /* Find the last argument, and see if it is __builtin_va_alist. */
1074 for (cur_arg
= DECL_ARGUMENTS (fndecl
); cur_arg
!= (tree
)0; cur_arg
= next_arg
)
1076 next_arg
= DECL_CHAIN (cur_arg
);
1077 if (next_arg
== (tree
)0)
1079 if (DECL_NAME (cur_arg
)
1080 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)), "__builtin_va_alist"))
1088 /* Iterate over all of the register ranges. */
1089 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1091 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1092 int first
= reg_ptr
->first
;
1093 int last
= reg_ptr
->last
;
1095 int size_2words
= 0;
1098 /* Calculate which registers need to be saved & save area size. */
1102 for (regno
= first
; regno
<= last
; regno
++)
1104 if ((df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1105 || (crtl
->calls_eh_return
1106 && (regno
>= FIRST_EH_REGNUM
&& regno
<= LAST_EH_REGNUM
))
1107 || (!TARGET_FDPIC
&& flag_pic
1108 && crtl
->uses_pic_offset_table
&& regno
== PIC_REGNO
))
1110 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1111 size_1word
+= UNITS_PER_WORD
;
1116 /* Calculate whether we need to create a frame after everything else
1117 has been processed. */
1122 if (df_regs_ever_live_p (LR_REGNO
)
1124 /* This is set for __builtin_return_address, etc. */
1125 || cfun
->machine
->frame_needed
1126 || (TARGET_LINKED_FP
&& frame_pointer_needed
)
1127 || (!TARGET_FDPIC
&& flag_pic
1128 && crtl
->uses_pic_offset_table
))
1130 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1131 size_1word
+= UNITS_PER_WORD
;
1135 case STACK_REGS_STDARG
:
1138 /* If this is a stdarg function with a non varardic
1139 argument split between registers and the stack,
1140 adjust the saved registers downward. */
1141 last
-= (ADDR_ALIGN (crtl
->args
.pretend_args_size
, UNITS_PER_WORD
)
1144 for (regno
= first
; regno
<= last
; regno
++)
1146 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1147 size_1word
+= UNITS_PER_WORD
;
1150 info_ptr
->stdarg_size
= size_1word
;
1154 case STACK_REGS_STRUCT
:
1155 if (cfun
->returns_struct
)
1157 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1158 size_1word
+= UNITS_PER_WORD
;
1166 /* If this is a field, it only takes one word. */
1167 if (reg_ptr
->field_p
)
1168 size_1word
= UNITS_PER_WORD
;
1170 /* Determine which register pairs can be saved together. */
1171 else if (reg_ptr
->dword_p
&& TARGET_DWORD
)
1173 for (regno
= first
; regno
< last
; regno
+= 2)
1175 if (info_ptr
->save_p
[regno
] && info_ptr
->save_p
[regno
+1])
1177 size_2words
+= 2 * UNITS_PER_WORD
;
1178 size_1word
-= 2 * UNITS_PER_WORD
;
1179 info_ptr
->save_p
[regno
] = REG_SAVE_2WORDS
;
1180 info_ptr
->save_p
[regno
+1] = REG_SAVE_NO_SAVE
;
1185 reg_ptr
->size_1word
= size_1word
;
1186 reg_ptr
->size_2words
= size_2words
;
1188 if (! reg_ptr
->special_p
)
1190 info_ptr
->regs_size_1word
+= size_1word
;
1191 info_ptr
->regs_size_2words
+= size_2words
;
1196 /* Set up the sizes of each each field in the frame body, making the sizes
1197 of each be divisible by the size of a dword if dword operations might
1198 be used, or the size of a word otherwise. */
1199 alignment
= (TARGET_DWORD
? 2 * UNITS_PER_WORD
: UNITS_PER_WORD
);
1201 info_ptr
->parameter_size
= ADDR_ALIGN (crtl
->outgoing_args_size
, alignment
);
1202 info_ptr
->regs_size
= ADDR_ALIGN (info_ptr
->regs_size_2words
1203 + info_ptr
->regs_size_1word
,
1205 info_ptr
->vars_size
= ADDR_ALIGN (get_frame_size (), alignment
);
1207 info_ptr
->pretend_size
= crtl
->args
.pretend_args_size
;
1209 /* Work out the size of the frame, excluding the header. Both the frame
1210 body and register parameter area will be dword-aligned. */
1211 info_ptr
->total_size
1212 = (ADDR_ALIGN (info_ptr
->parameter_size
1213 + info_ptr
->regs_size
1214 + info_ptr
->vars_size
,
1216 + ADDR_ALIGN (info_ptr
->pretend_size
1217 + info_ptr
->stdarg_size
,
1218 2 * UNITS_PER_WORD
));
1220 /* See if we need to create a frame at all, if so add header area. */
1221 if (info_ptr
->total_size
> 0
1222 || frame_pointer_needed
1223 || info_ptr
->regs
[STACK_REGS_LR
].size_1word
> 0
1224 || info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
> 0)
1226 offset
= info_ptr
->parameter_size
;
1227 info_ptr
->header_size
= 4 * UNITS_PER_WORD
;
1228 info_ptr
->total_size
+= 4 * UNITS_PER_WORD
;
1230 /* Calculate the offsets to save normal register pairs. */
1231 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1233 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1234 if (! reg_ptr
->special_p
)
1236 int first
= reg_ptr
->first
;
1237 int last
= reg_ptr
->last
;
1240 for (regno
= first
; regno
<= last
; regno
++)
1241 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
1242 && regno
!= FRAME_POINTER_REGNUM
1243 && (regno
< FIRST_ARG_REGNUM
1244 || regno
> LAST_ARG_REGNUM
))
1246 info_ptr
->reg_offset
[regno
] = offset
;
1247 offset
+= 2 * UNITS_PER_WORD
;
1252 /* Calculate the offsets to save normal single registers. */
1253 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1255 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1256 if (! reg_ptr
->special_p
)
1258 int first
= reg_ptr
->first
;
1259 int last
= reg_ptr
->last
;
1262 for (regno
= first
; regno
<= last
; regno
++)
1263 if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
1264 && regno
!= FRAME_POINTER_REGNUM
1265 && (regno
< FIRST_ARG_REGNUM
1266 || regno
> LAST_ARG_REGNUM
))
1268 info_ptr
->reg_offset
[regno
] = offset
;
1269 offset
+= UNITS_PER_WORD
;
1274 /* Calculate the offset to save the local variables at. */
1275 offset
= ADDR_ALIGN (offset
, alignment
);
1276 if (info_ptr
->vars_size
)
1278 info_ptr
->vars_offset
= offset
;
1279 offset
+= info_ptr
->vars_size
;
1282 /* Align header to a dword-boundary. */
1283 offset
= ADDR_ALIGN (offset
, 2 * UNITS_PER_WORD
);
1285 /* Calculate the offsets in the fixed frame. */
1286 info_ptr
->save_p
[FRAME_POINTER_REGNUM
] = REG_SAVE_1WORD
;
1287 info_ptr
->reg_offset
[FRAME_POINTER_REGNUM
] = offset
;
1288 info_ptr
->regs
[STACK_REGS_FP
].size_1word
= UNITS_PER_WORD
;
1290 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1291 info_ptr
->reg_offset
[LR_REGNO
] = offset
+ 2*UNITS_PER_WORD
;
1292 info_ptr
->regs
[STACK_REGS_LR
].size_1word
= UNITS_PER_WORD
;
1294 if (cfun
->returns_struct
)
1296 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1297 info_ptr
->reg_offset
[FRV_STRUCT_VALUE_REGNUM
] = offset
+ UNITS_PER_WORD
;
1298 info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
= UNITS_PER_WORD
;
1301 /* Calculate the offsets to store the arguments passed in registers
1302 for stdarg functions. The register pairs are first and the single
1303 register if any is last. The register save area starts on a
1305 if (info_ptr
->stdarg_size
)
1307 int first
= info_ptr
->regs
[STACK_REGS_STDARG
].first
;
1308 int last
= info_ptr
->regs
[STACK_REGS_STDARG
].last
;
1311 /* Skip the header. */
1312 offset
+= 4 * UNITS_PER_WORD
;
1313 for (regno
= first
; regno
<= last
; regno
++)
1315 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
)
1317 info_ptr
->reg_offset
[regno
] = offset
;
1318 offset
+= 2 * UNITS_PER_WORD
;
1320 else if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
)
1322 info_ptr
->reg_offset
[regno
] = offset
;
1323 offset
+= UNITS_PER_WORD
;
1329 if (reload_completed
)
1330 frv_stack_cache
= info_ptr
;
1336 /* Print the information about the frv stack offsets, etc. when debugging. */
1339 frv_debug_stack (frv_stack_t
*info
)
1344 info
= frv_stack_info ();
1346 fprintf (stderr
, "\nStack information for function %s:\n",
1347 ((current_function_decl
&& DECL_NAME (current_function_decl
))
1348 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
1351 fprintf (stderr
, "\ttotal_size\t= %6d\n", info
->total_size
);
1352 fprintf (stderr
, "\tvars_size\t= %6d\n", info
->vars_size
);
1353 fprintf (stderr
, "\tparam_size\t= %6d\n", info
->parameter_size
);
1354 fprintf (stderr
, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1355 info
->regs_size
, info
->regs_size_1word
, info
->regs_size_2words
);
1357 fprintf (stderr
, "\theader_size\t= %6d\n", info
->header_size
);
1358 fprintf (stderr
, "\tpretend_size\t= %6d\n", info
->pretend_size
);
1359 fprintf (stderr
, "\tvars_offset\t= %6d\n", info
->vars_offset
);
1360 fprintf (stderr
, "\tregs_offset\t= %6d\n", info
->regs_offset
);
1362 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1364 frv_stack_regs_t
*regs
= &(info
->regs
[range
]);
1365 if ((regs
->size_1word
+ regs
->size_2words
) > 0)
1367 int first
= regs
->first
;
1368 int last
= regs
->last
;
1371 fprintf (stderr
, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1372 regs
->name
, regs
->size_1word
+ regs
->size_2words
,
1373 regs
->size_1word
, regs
->size_2words
);
1375 for (regno
= first
; regno
<= last
; regno
++)
1377 if (info
->save_p
[regno
] == REG_SAVE_1WORD
)
1378 fprintf (stderr
, " %s (%d)", reg_names
[regno
],
1379 info
->reg_offset
[regno
]);
1381 else if (info
->save_p
[regno
] == REG_SAVE_2WORDS
)
1382 fprintf (stderr
, " %s-%s (%d)", reg_names
[regno
],
1383 reg_names
[regno
+1], info
->reg_offset
[regno
]);
1386 fputc ('\n', stderr
);
1396 /* Used during final to control the packing of insns. The value is
1397 1 if the current instruction should be packed with the next one,
1398 0 if it shouldn't or -1 if packing is disabled altogether. */
1400 static int frv_insn_packing_flag
;
1402 /* True if the current function contains a far jump. */
1405 frv_function_contains_far_jump (void)
1407 rtx_insn
*insn
= get_insns ();
1410 && get_attr_far_jump (insn
) == FAR_JUMP_YES
))
1411 insn
= NEXT_INSN (insn
);
1412 return (insn
!= NULL
);
1415 /* For the FRV, this function makes sure that a function with far jumps
1416 will return correctly. It also does the VLIW packing. */
1419 frv_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1421 rtx_insn
*insn
, *next
, *last_call
;
1423 /* If no frame was created, check whether the function uses a call
1424 instruction to implement a far jump. If so, save the link in gr3 and
1425 replace all returns to LR with returns to GR3. GR3 is used because it
1426 is call-clobbered, because is not available to the register allocator,
1427 and because all functions that take a hidden argument pointer will have
1429 if (frv_stack_info ()->total_size
== 0 && frv_function_contains_far_jump ())
1433 /* Just to check that the above comment is true. */
1434 gcc_assert (!df_regs_ever_live_p (GPR_FIRST
+ 3));
1436 /* Generate the instruction that saves the link register. */
1437 fprintf (file
, "\tmovsg lr,gr3\n");
1439 /* Replace the LR with GR3 in *return_internal patterns. The insn
1440 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1441 simply emit a different assembly directive because bralr and jmpl
1442 execute in different units. */
1443 for (insn
= get_insns(); insn
!= NULL
; insn
= NEXT_INSN (insn
))
1446 rtx pattern
= PATTERN (insn
);
1447 if (GET_CODE (pattern
) == PARALLEL
1448 && XVECLEN (pattern
, 0) >= 2
1449 && GET_CODE (XVECEXP (pattern
, 0, 0)) == RETURN
1450 && GET_CODE (XVECEXP (pattern
, 0, 1)) == USE
)
1452 rtx address
= XEXP (XVECEXP (pattern
, 0, 1), 0);
1453 if (GET_CODE (address
) == REG
&& REGNO (address
) == LR_REGNO
)
1454 SET_REGNO (address
, GPR_FIRST
+ 3);
1461 /* Allow the garbage collector to free the nops created by frv_reorg. */
1462 memset (frv_nops
, 0, sizeof (frv_nops
));
1464 /* Locate CALL_ARG_LOCATION notes that have been misplaced
1465 and move them back to where they should be located. */
1467 for (insn
= get_insns (); insn
; insn
= next
)
1469 next
= NEXT_INSN (insn
);
1471 || (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
1472 && CALL_P (XVECEXP (PATTERN (insn
), 0, 0))))
1475 if (!NOTE_P (insn
) || NOTE_KIND (insn
) != NOTE_INSN_CALL_ARG_LOCATION
)
1478 if (NEXT_INSN (last_call
) == insn
)
1481 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
1482 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
1483 SET_PREV_INSN (insn
) = last_call
;
1484 SET_NEXT_INSN (insn
) = NEXT_INSN (last_call
);
1485 SET_PREV_INSN (NEXT_INSN (insn
)) = insn
;
1486 SET_NEXT_INSN (PREV_INSN (insn
)) = insn
;
1492 /* Return the next available temporary register in a given class. */
1495 frv_alloc_temp_reg (
1496 frv_tmp_reg_t
*info
, /* which registers are available */
1497 enum reg_class rclass
, /* register class desired */
1498 machine_mode mode
, /* mode to allocate register with */
1499 int mark_as_used
, /* register not available after allocation */
1500 int no_abort
) /* return NULL instead of aborting */
1502 int regno
= info
->next_reg
[ (int)rclass
];
1503 int orig_regno
= regno
;
1504 HARD_REG_SET
*reg_in_class
= ®_class_contents
[ (int)rclass
];
1509 if (TEST_HARD_REG_BIT (*reg_in_class
, regno
)
1510 && TEST_HARD_REG_BIT (info
->regs
, regno
))
1513 if (++regno
>= FIRST_PSEUDO_REGISTER
)
1515 if (regno
== orig_regno
)
1517 gcc_assert (no_abort
);
1522 nr
= HARD_REGNO_NREGS (regno
, mode
);
1523 info
->next_reg
[ (int)rclass
] = regno
+ nr
;
1526 for (i
= 0; i
< nr
; i
++)
1527 CLEAR_HARD_REG_BIT (info
->regs
, regno
+i
);
1529 return gen_rtx_REG (mode
, regno
);
1533 /* Return an rtx with the value OFFSET, which will either be a register or a
1534 signed 12-bit integer. It can be used as the second operand in an "add"
1535 instruction, or as the index in a load or store.
1537 The function returns a constant rtx if OFFSET is small enough, otherwise
1538 it loads the constant into register OFFSET_REGNO and returns that. */
1540 frv_frame_offset_rtx (int offset
)
1542 rtx offset_rtx
= GEN_INT (offset
);
1543 if (IN_RANGE (offset
, -2048, 2047))
1547 rtx reg_rtx
= gen_rtx_REG (SImode
, OFFSET_REGNO
);
1548 if (IN_RANGE (offset
, -32768, 32767))
1549 emit_insn (gen_movsi (reg_rtx
, offset_rtx
));
1552 emit_insn (gen_movsi_high (reg_rtx
, offset_rtx
));
1553 emit_insn (gen_movsi_lo_sum (reg_rtx
, offset_rtx
));
1559 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1560 prologue and epilogue uses such expressions to access the stack. */
1562 frv_frame_mem (machine_mode mode
, rtx base
, int offset
)
1564 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
,
1566 frv_frame_offset_rtx (offset
)));
1569 /* Generate a frame-related expression:
1571 (set REG (mem (plus (sp) (const_int OFFSET)))).
1573 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1574 instructions. Marking the expressions as frame-related is superfluous if
1575 the note contains just a single set. But if the note contains a PARALLEL
1576 or SEQUENCE that has several sets, each set must be individually marked
1577 as frame-related. */
1579 frv_dwarf_store (rtx reg
, int offset
)
1581 rtx set
= gen_rtx_SET (VOIDmode
,
1582 gen_rtx_MEM (GET_MODE (reg
),
1583 plus_constant (Pmode
, stack_pointer_rtx
,
1586 RTX_FRAME_RELATED_P (set
) = 1;
1590 /* Emit a frame-related instruction whose pattern is PATTERN. The
1591 instruction is the last in a sequence that cumulatively performs the
1592 operation described by DWARF_PATTERN. The instruction is marked as
1593 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1596 frv_frame_insn (rtx pattern
, rtx dwarf_pattern
)
1598 rtx insn
= emit_insn (pattern
);
1599 RTX_FRAME_RELATED_P (insn
) = 1;
1600 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
1605 /* Emit instructions that transfer REG to or from the memory location (sp +
1606 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1607 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1608 function to store registers and only the epilogue uses it to load them.
1610 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1611 The generated instruction will use BASE as its base register. BASE may
1612 simply be the stack pointer, but if several accesses are being made to a
1613 region far away from the stack pointer, it may be more efficient to set
1614 up a temporary instead.
1616 Store instructions will be frame-related and will be annotated with the
1617 overall effect of the store. Load instructions will be followed by a
1618 (use) to prevent later optimizations from zapping them.
1620 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1621 as a temporary in such cases. */
1623 frv_frame_access (frv_frame_accessor_t
*accessor
, rtx reg
, int stack_offset
)
1625 machine_mode mode
= GET_MODE (reg
);
1626 rtx mem
= frv_frame_mem (mode
,
1628 stack_offset
- accessor
->base_offset
);
1630 if (accessor
->op
== FRV_LOAD
)
1632 if (SPR_P (REGNO (reg
)))
1634 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1635 emit_insn (gen_rtx_SET (VOIDmode
, temp
, mem
));
1636 emit_insn (gen_rtx_SET (VOIDmode
, reg
, temp
));
1640 /* We cannot use reg+reg addressing for DImode access. */
1642 && GET_CODE (XEXP (mem
, 0)) == PLUS
1643 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1644 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1646 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1648 emit_move_insn (temp
,
1649 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1650 XEXP (XEXP (mem
, 0), 1)));
1651 mem
= gen_rtx_MEM (DImode
, temp
);
1653 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
1659 if (SPR_P (REGNO (reg
)))
1661 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1662 emit_insn (gen_rtx_SET (VOIDmode
, temp
, reg
));
1663 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, temp
),
1664 frv_dwarf_store (reg
, stack_offset
));
1666 else if (mode
== DImode
)
1668 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1669 with a separate save for each register. */
1670 rtx reg1
= gen_rtx_REG (SImode
, REGNO (reg
));
1671 rtx reg2
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
1672 rtx set1
= frv_dwarf_store (reg1
, stack_offset
);
1673 rtx set2
= frv_dwarf_store (reg2
, stack_offset
+ 4);
1675 /* Also we cannot use reg+reg addressing. */
1676 if (GET_CODE (XEXP (mem
, 0)) == PLUS
1677 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1678 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1680 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1681 emit_move_insn (temp
,
1682 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1683 XEXP (XEXP (mem
, 0), 1)));
1684 mem
= gen_rtx_MEM (DImode
, temp
);
1687 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1688 gen_rtx_PARALLEL (VOIDmode
,
1689 gen_rtvec (2, set1
, set2
)));
1692 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1693 frv_dwarf_store (reg
, stack_offset
));
1697 /* A function that uses frv_frame_access to transfer a group of registers to
1698 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1699 is the stack information generated by frv_stack_info, and REG_SET is the
1700 number of the register set to transfer. */
1702 frv_frame_access_multi (frv_frame_accessor_t
*accessor
,
1706 frv_stack_regs_t
*regs_info
;
1709 regs_info
= &info
->regs
[reg_set
];
1710 for (regno
= regs_info
->first
; regno
<= regs_info
->last
; regno
++)
1711 if (info
->save_p
[regno
])
1712 frv_frame_access (accessor
,
1713 info
->save_p
[regno
] == REG_SAVE_2WORDS
1714 ? gen_rtx_REG (DImode
, regno
)
1715 : gen_rtx_REG (SImode
, regno
),
1716 info
->reg_offset
[regno
]);
1719 /* Save or restore callee-saved registers that are kept outside the frame
1720 header. The function saves the registers if OP is FRV_STORE and restores
1721 them if OP is FRV_LOAD. INFO is the stack information generated by
1724 frv_frame_access_standard_regs (enum frv_stack_op op
, frv_stack_t
*info
)
1726 frv_frame_accessor_t accessor
;
1729 accessor
.base
= stack_pointer_rtx
;
1730 accessor
.base_offset
= 0;
1731 frv_frame_access_multi (&accessor
, info
, STACK_REGS_GPR
);
1732 frv_frame_access_multi (&accessor
, info
, STACK_REGS_FPR
);
1733 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LCR
);
1737 /* Called after register allocation to add any instructions needed for the
1738 prologue. Using a prologue insn is favored compared to putting all of the
1739 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1740 it allows the scheduler to intermix instructions with the saves of
1741 the caller saved registers. In some cases, it might be necessary
1742 to emit a barrier instruction as the last insn to prevent such
1745 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1746 so that the debug info generation code can handle them properly. */
1748 frv_expand_prologue (void)
1750 frv_stack_t
*info
= frv_stack_info ();
1751 rtx sp
= stack_pointer_rtx
;
1752 rtx fp
= frame_pointer_rtx
;
1753 frv_frame_accessor_t accessor
;
1755 if (TARGET_DEBUG_STACK
)
1756 frv_debug_stack (info
);
1758 if (flag_stack_usage_info
)
1759 current_function_static_stack_size
= info
->total_size
;
1761 if (info
->total_size
== 0)
1764 /* We're interested in three areas of the frame here:
1766 A: the register save area
1768 C: the header after B
1770 If the frame pointer isn't used, we'll have to set up A, B and C
1771 using the stack pointer. If the frame pointer is used, we'll access
1775 B: set up using sp or a temporary (see below)
1778 We set up B using the stack pointer if the frame is small enough.
1779 Otherwise, it's more efficient to copy the old stack pointer into a
1780 temporary and use that.
1782 Note that it's important to make sure the prologue and epilogue use the
1783 same registers to access A and C, since doing otherwise will confuse
1784 the aliasing code. */
1786 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1787 isn't used, the same method will serve for C. */
1788 accessor
.op
= FRV_STORE
;
1789 if (frame_pointer_needed
&& info
->total_size
> 2048)
1791 accessor
.base
= gen_rtx_REG (Pmode
, OLD_SP_REGNO
);
1792 accessor
.base_offset
= info
->total_size
;
1793 emit_insn (gen_movsi (accessor
.base
, sp
));
1797 accessor
.base
= stack_pointer_rtx
;
1798 accessor
.base_offset
= 0;
1801 /* Allocate the stack space. */
1803 rtx asm_offset
= frv_frame_offset_rtx (-info
->total_size
);
1804 rtx dwarf_offset
= GEN_INT (-info
->total_size
);
1806 frv_frame_insn (gen_stack_adjust (sp
, sp
, asm_offset
),
1809 gen_rtx_PLUS (Pmode
, sp
, dwarf_offset
)));
1812 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1813 and point the new one to that location. */
1814 if (frame_pointer_needed
)
1816 int fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1818 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1819 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1821 rtx asm_src
= plus_constant (Pmode
, accessor
.base
,
1822 fp_offset
- accessor
.base_offset
);
1823 rtx dwarf_src
= plus_constant (Pmode
, sp
, fp_offset
);
1825 /* Store the old frame pointer at (sp + FP_OFFSET). */
1826 frv_frame_access (&accessor
, fp
, fp_offset
);
1828 /* Set up the new frame pointer. */
1829 frv_frame_insn (gen_rtx_SET (VOIDmode
, fp
, asm_src
),
1830 gen_rtx_SET (VOIDmode
, fp
, dwarf_src
));
1832 /* Access region C from the frame pointer. */
1834 accessor
.base_offset
= fp_offset
;
1837 /* Set up region C. */
1838 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STRUCT
);
1839 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LR
);
1840 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STDARG
);
1842 /* Set up region A. */
1843 frv_frame_access_standard_regs (FRV_STORE
, info
);
1845 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1846 scheduler from moving loads before the stores saving the registers. */
1847 if (info
->stdarg_size
> 0)
1848 emit_insn (gen_blockage ());
1850 /* Set up pic register/small data register for this function. */
1851 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
1852 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode
, PIC_REGNO
),
1853 gen_rtx_REG (Pmode
, LR_REGNO
),
1854 gen_rtx_REG (SImode
, OFFSET_REGNO
)));
1858 /* Under frv, all of the work is done via frv_expand_epilogue, but
1859 this function provides a convenient place to do cleanup. */
1862 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
1863 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1865 frv_stack_cache
= (frv_stack_t
*)0;
1867 /* Zap last used registers for conditional execution. */
1868 memset (&frv_ifcvt
.tmp_reg
, 0, sizeof (frv_ifcvt
.tmp_reg
));
1870 /* Release the bitmap of created insns. */
1871 BITMAP_FREE (frv_ifcvt
.scratch_insns_bitmap
);
1875 /* Called after register allocation to add any instructions needed for the
1876 epilogue. Using an epilogue insn is favored compared to putting all of the
1877 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1878 it allows the scheduler to intermix instructions with the saves of
1879 the caller saved registers. In some cases, it might be necessary
1880 to emit a barrier instruction as the last insn to prevent such
1884 frv_expand_epilogue (bool emit_return
)
1886 frv_stack_t
*info
= frv_stack_info ();
1887 rtx fp
= frame_pointer_rtx
;
1888 rtx sp
= stack_pointer_rtx
;
1892 fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1894 /* Restore the stack pointer to its original value if alloca or the like
1896 if (! crtl
->sp_is_unchanging
)
1897 emit_insn (gen_addsi3 (sp
, fp
, frv_frame_offset_rtx (-fp_offset
)));
1899 /* Restore the callee-saved registers that were used in this function. */
1900 frv_frame_access_standard_regs (FRV_LOAD
, info
);
1902 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1903 no return instruction should be emitted. */
1904 if (info
->save_p
[LR_REGNO
])
1909 /* Use the same method to access the link register's slot as we did in
1910 the prologue. In other words, use the frame pointer if available,
1911 otherwise use the stack pointer.
1913 LR_OFFSET is the offset of the link register's slot from the start
1914 of the frame and MEM is a memory rtx for it. */
1915 lr_offset
= info
->reg_offset
[LR_REGNO
];
1916 if (frame_pointer_needed
)
1917 mem
= frv_frame_mem (Pmode
, fp
, lr_offset
- fp_offset
);
1919 mem
= frv_frame_mem (Pmode
, sp
, lr_offset
);
1921 /* Load the old link register into a GPR. */
1922 return_addr
= gen_rtx_REG (Pmode
, TEMP_REGNO
);
1923 emit_insn (gen_rtx_SET (VOIDmode
, return_addr
, mem
));
1926 return_addr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1928 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1929 the load is preserved. */
1930 if (frame_pointer_needed
)
1932 emit_insn (gen_rtx_SET (VOIDmode
, fp
, gen_rtx_MEM (Pmode
, fp
)));
1936 /* Deallocate the stack frame. */
1937 if (info
->total_size
!= 0)
1939 rtx offset
= frv_frame_offset_rtx (info
->total_size
);
1940 emit_insn (gen_stack_adjust (sp
, sp
, offset
));
1943 /* If this function uses eh_return, add the final stack adjustment now. */
1944 if (crtl
->calls_eh_return
)
1945 emit_insn (gen_stack_adjust (sp
, sp
, EH_RETURN_STACKADJ_RTX
));
1948 emit_jump_insn (gen_epilogue_return (return_addr
));
1951 rtx lr
= return_addr
;
1953 if (REGNO (return_addr
) != LR_REGNO
)
1955 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1956 emit_move_insn (lr
, return_addr
);
1964 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1967 frv_asm_output_mi_thunk (FILE *file
,
1968 tree thunk_fndecl ATTRIBUTE_UNUSED
,
1969 HOST_WIDE_INT delta
,
1970 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
1973 const char *name_func
= XSTR (XEXP (DECL_RTL (function
), 0), 0);
1974 const char *name_arg0
= reg_names
[FIRST_ARG_REGNUM
];
1975 const char *name_jmp
= reg_names
[JUMP_REGNO
];
1976 const char *parallel
= (frv_issue_rate () > 1 ? ".p" : "");
1978 /* Do the add using an addi if possible. */
1979 if (IN_RANGE (delta
, -2048, 2047))
1980 fprintf (file
, "\taddi %s,#%d,%s\n", name_arg0
, (int) delta
, name_arg0
);
1983 const char *const name_add
= reg_names
[TEMP_REGNO
];
1984 fprintf (file
, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1985 parallel
, delta
, name_add
);
1986 fprintf (file
, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1988 fprintf (file
, "\tadd %s,%s,%s\n", name_add
, name_arg0
, name_arg0
);
1993 const char *name_pic
= reg_names
[FDPIC_REGNO
];
1994 name_jmp
= reg_names
[FDPIC_FPTR_REGNO
];
1998 fprintf (file
, "\tsethi%s #gotofffuncdeschi(", parallel
);
1999 assemble_name (file
, name_func
);
2000 fprintf (file
, "),%s\n", name_jmp
);
2002 fprintf (file
, "\tsetlo #gotofffuncdesclo(");
2003 assemble_name (file
, name_func
);
2004 fprintf (file
, "),%s\n", name_jmp
);
2006 fprintf (file
, "\tldd @(%s,%s), %s\n", name_jmp
, name_pic
, name_jmp
);
2010 fprintf (file
, "\tlddo @(%s,#gotofffuncdesc12(", name_pic
);
2011 assemble_name (file
, name_func
);
2012 fprintf (file
, "\t)), %s\n", name_jmp
);
2017 fprintf (file
, "\tsethi%s #hi(", parallel
);
2018 assemble_name (file
, name_func
);
2019 fprintf (file
, "),%s\n", name_jmp
);
2021 fprintf (file
, "\tsetlo #lo(");
2022 assemble_name (file
, name_func
);
2023 fprintf (file
, "),%s\n", name_jmp
);
2027 /* Use JUMP_REGNO as a temporary PIC register. */
2028 const char *name_lr
= reg_names
[LR_REGNO
];
2029 const char *name_gppic
= name_jmp
;
2030 const char *name_tmp
= reg_names
[TEMP_REGNO
];
2032 fprintf (file
, "\tmovsg %s,%s\n", name_lr
, name_tmp
);
2033 fprintf (file
, "\tcall 1f\n");
2034 fprintf (file
, "1:\tmovsg %s,%s\n", name_lr
, name_gppic
);
2035 fprintf (file
, "\tmovgs %s,%s\n", name_tmp
, name_lr
);
2036 fprintf (file
, "\tsethi%s #gprelhi(1b),%s\n", parallel
, name_tmp
);
2037 fprintf (file
, "\tsetlo #gprello(1b),%s\n", name_tmp
);
2038 fprintf (file
, "\tsub %s,%s,%s\n", name_gppic
, name_tmp
, name_gppic
);
2040 fprintf (file
, "\tsethi%s #gprelhi(", parallel
);
2041 assemble_name (file
, name_func
);
2042 fprintf (file
, "),%s\n", name_tmp
);
2044 fprintf (file
, "\tsetlo #gprello(");
2045 assemble_name (file
, name_func
);
2046 fprintf (file
, "),%s\n", name_tmp
);
2048 fprintf (file
, "\tadd %s,%s,%s\n", name_gppic
, name_tmp
, name_jmp
);
2051 /* Jump to the function address. */
2052 fprintf (file
, "\tjmpl @(%s,%s)\n", name_jmp
, reg_names
[GPR_FIRST
+0]);
2057 /* On frv, create a frame whenever we need to create stack. */
2060 frv_frame_pointer_required (void)
2062 /* If we forgoing the usual linkage requirements, we only need
2063 a frame pointer if the stack pointer might change. */
2064 if (!TARGET_LINKED_FP
)
2065 return !crtl
->sp_is_unchanging
;
2067 if (! crtl
->is_leaf
)
2070 if (get_frame_size () != 0)
2076 if (!crtl
->sp_is_unchanging
)
2079 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
2085 if (cfun
->machine
->frame_needed
)
2092 /* Worker function for TARGET_CAN_ELIMINATE. */
2095 frv_can_eliminate (const int from
, const int to
)
2097 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
2098 ? ! frame_pointer_needed
2102 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2103 initial difference between the specified pair of registers. This macro must
2104 be defined if `ELIMINABLE_REGS' is defined. */
2106 /* See frv_stack_info for more details on the frv stack frame. */
2109 frv_initial_elimination_offset (int from
, int to
)
2111 frv_stack_t
*info
= frv_stack_info ();
2114 if (to
== STACK_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2115 ret
= info
->total_size
- info
->pretend_size
;
2117 else if (to
== STACK_POINTER_REGNUM
&& from
== FRAME_POINTER_REGNUM
)
2118 ret
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
2120 else if (to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2121 ret
= (info
->total_size
2122 - info
->reg_offset
[FRAME_POINTER_REGNUM
]
2123 - info
->pretend_size
);
2128 if (TARGET_DEBUG_STACK
)
2129 fprintf (stderr
, "Eliminate %s to %s by adding %d\n",
2130 reg_names
[from
], reg_names
[to
], ret
);
2136 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2139 frv_setup_incoming_varargs (cumulative_args_t cum_v
,
2141 tree type ATTRIBUTE_UNUSED
,
2145 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2147 if (TARGET_DEBUG_ARG
)
2149 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2150 *cum
, GET_MODE_NAME (mode
), *pretend_size
, second_time
);
2154 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2157 frv_expand_builtin_saveregs (void)
2159 int offset
= UNITS_PER_WORD
* FRV_NUM_ARG_REGS
;
2161 if (TARGET_DEBUG_ARG
)
2162 fprintf (stderr
, "expand_builtin_saveregs: offset from ap = %d\n",
2165 return gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
, GEN_INT (- offset
));
2169 /* Expand __builtin_va_start to do the va_start macro. */
2172 frv_expand_builtin_va_start (tree valist
, rtx nextarg
)
2175 int num
= crtl
->args
.info
- FIRST_ARG_REGNUM
- FRV_NUM_ARG_REGS
;
2177 nextarg
= gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
,
2178 GEN_INT (UNITS_PER_WORD
* num
));
2180 if (TARGET_DEBUG_ARG
)
2182 fprintf (stderr
, "va_start: args_info = %d, num = %d\n",
2183 crtl
->args
.info
, num
);
2185 debug_rtx (nextarg
);
2188 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
2189 fold_convert (TREE_TYPE (valist
),
2190 make_tree (sizetype
, nextarg
)));
2191 TREE_SIDE_EFFECTS (t
) = 1;
2193 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2197 /* Expand a block move operation, and return 1 if successful. Return 0
2198 if we should let the compiler generate normal code.
2200 operands[0] is the destination
2201 operands[1] is the source
2202 operands[2] is the length
2203 operands[3] is the alignment */
2205 /* Maximum number of loads to do before doing the stores */
2206 #ifndef MAX_MOVE_REG
2207 #define MAX_MOVE_REG 4
2210 /* Maximum number of total loads to do. */
2211 #ifndef TOTAL_MOVE_REG
2212 #define TOTAL_MOVE_REG 8
2216 frv_expand_block_move (rtx operands
[])
2218 rtx orig_dest
= operands
[0];
2219 rtx orig_src
= operands
[1];
2220 rtx bytes_rtx
= operands
[2];
2221 rtx align_rtx
= operands
[3];
2222 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2235 rtx stores
[MAX_MOVE_REG
];
2239 /* If this is not a fixed size move, just call memcpy. */
2243 /* This should be a fixed size alignment. */
2244 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2246 align
= INTVAL (align_rtx
);
2248 /* Anything to move? */
2249 bytes
= INTVAL (bytes_rtx
);
2253 /* Don't support real large moves. */
2254 if (bytes
> TOTAL_MOVE_REG
*align
)
2257 /* Move the address into scratch registers. */
2258 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2259 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2261 num_reg
= offset
= 0;
2262 for ( ; bytes
> 0; (bytes
-= move_bytes
), (offset
+= move_bytes
))
2264 /* Calculate the correct offset for src/dest. */
2268 dest_addr
= dest_reg
;
2272 src_addr
= plus_constant (Pmode
, src_reg
, offset
);
2273 dest_addr
= plus_constant (Pmode
, dest_reg
, offset
);
2276 /* Generate the appropriate load and store, saving the stores
2278 if (bytes
>= 4 && align
>= 4)
2280 else if (bytes
>= 2 && align
>= 2)
2285 move_bytes
= GET_MODE_SIZE (mode
);
2286 tmp_reg
= gen_reg_rtx (mode
);
2287 src_mem
= change_address (orig_src
, mode
, src_addr
);
2288 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2289 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
, src_mem
));
2290 stores
[num_reg
++] = gen_rtx_SET (VOIDmode
, dest_mem
, tmp_reg
);
2292 if (num_reg
>= MAX_MOVE_REG
)
2294 for (i
= 0; i
< num_reg
; i
++)
2295 emit_insn (stores
[i
]);
2300 for (i
= 0; i
< num_reg
; i
++)
2301 emit_insn (stores
[i
]);
2307 /* Expand a block clear operation, and return 1 if successful. Return 0
2308 if we should let the compiler generate normal code.
2310 operands[0] is the destination
2311 operands[1] is the length
2312 operands[3] is the alignment */
2315 frv_expand_block_clear (rtx operands
[])
2317 rtx orig_dest
= operands
[0];
2318 rtx bytes_rtx
= operands
[1];
2319 rtx align_rtx
= operands
[3];
2320 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2330 /* If this is not a fixed size move, just call memcpy. */
2334 /* This should be a fixed size alignment. */
2335 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2337 align
= INTVAL (align_rtx
);
2339 /* Anything to move? */
2340 bytes
= INTVAL (bytes_rtx
);
2344 /* Don't support real large clears. */
2345 if (bytes
> TOTAL_MOVE_REG
*align
)
2348 /* Move the address into a scratch register. */
2349 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2352 for ( ; bytes
> 0; (bytes
-= clear_bytes
), (offset
+= clear_bytes
))
2354 /* Calculate the correct offset for src/dest. */
2355 dest_addr
= ((offset
== 0)
2357 : plus_constant (Pmode
, dest_reg
, offset
));
2359 /* Generate the appropriate store of gr0. */
2360 if (bytes
>= 4 && align
>= 4)
2362 else if (bytes
>= 2 && align
>= 2)
2367 clear_bytes
= GET_MODE_SIZE (mode
);
2368 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2369 emit_insn (gen_rtx_SET (VOIDmode
, dest_mem
, const0_rtx
));
2376 /* The following variable is used to output modifiers of assembler
2377 code of the current output insn. */
2379 static rtx
*frv_insn_operands
;
2381 /* The following function is used to add assembler insn code suffix .p
2382 if it is necessary. */
2385 frv_asm_output_opcode (FILE *f
, const char *ptr
)
2389 if (frv_insn_packing_flag
<= 0)
2392 for (; *ptr
&& *ptr
!= ' ' && *ptr
!= '\t';)
2395 if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2396 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2398 int letter
= *ptr
++;
2401 frv_print_operand (f
, frv_insn_operands
[c
], letter
);
2402 while ((c
= *ptr
) >= '0' && c
<= '9')
2414 /* Set up the packing bit for the current output insn. Note that this
2415 function is not called for asm insns. */
2418 frv_final_prescan_insn (rtx_insn
*insn
, rtx
*opvec
,
2419 int noperands ATTRIBUTE_UNUSED
)
2423 if (frv_insn_packing_flag
>= 0)
2425 frv_insn_operands
= opvec
;
2426 frv_insn_packing_flag
= PACKING_FLAG_P (insn
);
2428 else if (recog_memoized (insn
) >= 0
2429 && get_attr_acc_group (insn
) == ACC_GROUP_ODD
)
2430 /* Packing optimizations have been disabled, but INSN can only
2431 be issued in M1. Insert an mnop in M0. */
2432 fprintf (asm_out_file
, "\tmnop.p\n");
2438 /* A C expression whose value is RTL representing the address in a stack frame
2439 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2440 an RTL expression for the address of the stack frame itself.
2442 If you don't define this macro, the default is to return the value of
2443 FRAMEADDR--that is, the stack frame address is also the address of the stack
2444 word that points to the previous frame. */
2446 /* The default is correct, but we need to make sure the frame gets created. */
2448 frv_dynamic_chain_address (rtx frame
)
2450 cfun
->machine
->frame_needed
= 1;
2455 /* A C expression whose value is RTL representing the value of the return
2456 address for the frame COUNT steps up from the current frame, after the
2457 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2458 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2461 The value of the expression must always be the correct address when COUNT is
2462 zero, but may be `NULL_RTX' if there is not way to determine the return
2463 address of other frames. */
2466 frv_return_addr_rtx (int count
, rtx frame
)
2470 cfun
->machine
->frame_needed
= 1;
2471 return gen_rtx_MEM (Pmode
, plus_constant (Pmode
, frame
, 8));
2474 /* Given a memory reference MEMREF, interpret the referenced memory as
2475 an array of MODE values, and return a reference to the element
2476 specified by INDEX. Assume that any pre-modification implicit in
2477 MEMREF has already happened.
2479 MEMREF must be a legitimate operand for modes larger than SImode.
2480 frv_legitimate_address_p forbids register+register addresses, which
2481 this function cannot handle. */
2483 frv_index_memory (rtx memref
, machine_mode mode
, int index
)
2485 rtx base
= XEXP (memref
, 0);
2486 if (GET_CODE (base
) == PRE_MODIFY
)
2487 base
= XEXP (base
, 0);
2488 return change_address (memref
, mode
,
2489 plus_constant (Pmode
, base
,
2490 index
* GET_MODE_SIZE (mode
)));
2494 /* Print a memory address as an operand to reference that memory location. */
2496 frv_print_operand_address (FILE * stream
, rtx x
)
2498 if (GET_CODE (x
) == MEM
)
2501 switch (GET_CODE (x
))
2504 fputs (reg_names
[ REGNO (x
)], stream
);
2508 fprintf (stream
, "%ld", (long) INTVAL (x
));
2512 assemble_name (stream
, XSTR (x
, 0));
2517 output_addr_const (stream
, x
);
2521 /* Poorly constructed asm statements can trigger this alternative.
2522 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2523 frv_print_operand_memory_reference (stream
, x
, 0);
2530 fatal_insn ("bad insn to frv_print_operand_address:", x
);
2535 frv_print_operand_memory_reference_reg (FILE * stream
, rtx x
)
2537 int regno
= true_regnum (x
);
2539 fputs (reg_names
[regno
], stream
);
2541 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x
);
2544 /* Print a memory reference suitable for the ld/st instructions. */
2547 frv_print_operand_memory_reference (FILE * stream
, rtx x
, int addr_offset
)
2549 struct frv_unspec unspec
;
2553 switch (GET_CODE (x
))
2560 case PRE_MODIFY
: /* (pre_modify (reg) (plus (reg) (reg))) */
2562 x1
= XEXP (XEXP (x
, 1), 1);
2572 if (GET_CODE (x0
) == CONST_INT
)
2580 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2589 else if (GET_CODE (x1
) != CONST_INT
)
2590 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2593 fputs ("@(", stream
);
2595 fputs (reg_names
[GPR_R0
], stream
);
2596 else if (GET_CODE (x0
) == REG
|| GET_CODE (x0
) == SUBREG
)
2597 frv_print_operand_memory_reference_reg (stream
, x0
);
2599 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2601 fputs (",", stream
);
2603 fputs (reg_names
[GPR_R0
], stream
);
2607 switch (GET_CODE (x1
))
2611 frv_print_operand_memory_reference_reg (stream
, x1
);
2615 fprintf (stream
, "%ld", (long) (INTVAL (x1
) + addr_offset
));
2619 if (!frv_const_unspec_p (x1
, &unspec
))
2620 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1
);
2621 frv_output_const_unspec (stream
, &unspec
);
2625 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2629 fputs (")", stream
);
2633 /* Return 2 for likely branches and 0 for non-likely branches */
2635 #define FRV_JUMP_LIKELY 2
2636 #define FRV_JUMP_NOT_LIKELY 0
2639 frv_print_operand_jump_hint (rtx_insn
*insn
)
2645 enum { UNKNOWN
, BACKWARD
, FORWARD
} jump_type
= UNKNOWN
;
2647 gcc_assert (JUMP_P (insn
));
2649 /* Assume any non-conditional jump is likely. */
2650 if (! any_condjump_p (insn
))
2651 ret
= FRV_JUMP_LIKELY
;
2655 labelref
= condjump_label (insn
);
2658 rtx label
= XEXP (labelref
, 0);
2659 jump_type
= (insn_current_address
> INSN_ADDRESSES (INSN_UID (label
))
2664 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
2666 ret
= ((jump_type
== BACKWARD
) ? FRV_JUMP_LIKELY
: FRV_JUMP_NOT_LIKELY
);
2670 prob
= XINT (note
, 0);
2671 ret
= ((prob
>= (REG_BR_PROB_BASE
/ 2))
2673 : FRV_JUMP_NOT_LIKELY
);
2685 case UNKNOWN
: direction
= "unknown jump direction"; break;
2686 case BACKWARD
: direction
= "jump backward"; break;
2687 case FORWARD
: direction
= "jump forward"; break;
2691 "%s: uid %ld, %s, probability = %d, max prob. = %d, hint = %d\n",
2692 IDENTIFIER_POINTER (DECL_NAME (current_function_decl
)),
2693 (long)INSN_UID (insn
), direction
, prob
,
2694 REG_BR_PROB_BASE
, ret
);
2702 /* Return the comparison operator to use for CODE given that the ICC
2706 comparison_string (enum rtx_code code
, rtx op0
)
2708 bool is_nz_p
= GET_MODE (op0
) == CC_NZmode
;
2711 default: output_operand_lossage ("bad condition code");
2712 case EQ
: return "eq";
2713 case NE
: return "ne";
2714 case LT
: return is_nz_p
? "n" : "lt";
2715 case LE
: return "le";
2716 case GT
: return "gt";
2717 case GE
: return is_nz_p
? "p" : "ge";
2718 case LTU
: return is_nz_p
? "no" : "c";
2719 case LEU
: return is_nz_p
? "eq" : "ls";
2720 case GTU
: return is_nz_p
? "ne" : "hi";
2721 case GEU
: return is_nz_p
? "ra" : "nc";
2725 /* Print an operand to an assembler instruction.
2727 `%' followed by a letter and a digit says to output an operand in an
2728 alternate fashion. Four letters have standard, built-in meanings
2729 described below. The hook `TARGET_PRINT_OPERAND' can define
2730 additional letters with nonstandard meanings.
2732 `%cDIGIT' can be used to substitute an operand that is a constant value
2733 without the syntax that normally indicates an immediate operand.
2735 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2738 `%aDIGIT' can be used to substitute an operand as if it were a memory
2739 reference, with the actual operand treated as the address. This may be
2740 useful when outputting a "load address" instruction, because often the
2741 assembler syntax for such an instruction requires you to write the operand
2742 as if it were a memory reference.
2744 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2746 `%=' outputs a number which is unique to each instruction in the entire
2747 compilation. This is useful for making local labels to be referred to more
2748 than once in a single template that generates multiple assembler
2751 `%' followed by a punctuation character specifies a substitution that
2752 does not use an operand. Only one case is standard: `%%' outputs a
2753 `%' into the assembler code. Other nonstandard cases can be defined
2754 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2755 punctuation characters are valid with the
2756 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2759 frv_print_operand (FILE * file
, rtx x
, int code
)
2761 struct frv_unspec unspec
;
2762 HOST_WIDE_INT value
;
2765 if (code
!= 0 && !ISALPHA (code
))
2768 else if (GET_CODE (x
) == CONST_INT
)
2771 else if (GET_CODE (x
) == CONST_DOUBLE
)
2773 if (GET_MODE (x
) == SFmode
)
2778 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
2779 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2783 else if (GET_MODE (x
) == VOIDmode
)
2784 value
= CONST_DOUBLE_LOW (x
);
2787 fatal_insn ("bad insn in frv_print_operand, bad const_double", x
);
2798 fputs (reg_names
[GPR_R0
], file
);
2802 fprintf (file
, "%d", frv_print_operand_jump_hint (current_output_insn
));
2806 /* Output small data area base register (gr16). */
2807 fputs (reg_names
[SDA_BASE_REG
], file
);
2811 /* Output pic register (gr17). */
2812 fputs (reg_names
[PIC_REGNO
], file
);
2816 /* Output the temporary integer CCR register. */
2817 fputs (reg_names
[ICR_TEMP
], file
);
2821 /* Output the temporary integer CC register. */
2822 fputs (reg_names
[ICC_TEMP
], file
);
2825 /* case 'a': print an address. */
2828 /* Print appropriate test for integer branch false operation. */
2829 fputs (comparison_string (reverse_condition (GET_CODE (x
)),
2830 XEXP (x
, 0)), file
);
2834 /* Print appropriate test for integer branch true operation. */
2835 fputs (comparison_string (GET_CODE (x
), XEXP (x
, 0)), file
);
2839 /* Print 1 for a NE and 0 for an EQ to give the final argument
2840 for a conditional instruction. */
2841 if (GET_CODE (x
) == NE
)
2844 else if (GET_CODE (x
) == EQ
)
2848 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x
);
2852 /* Print appropriate test for floating point branch false operation. */
2853 switch (GET_CODE (x
))
2856 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x
);
2858 case EQ
: fputs ("ne", file
); break;
2859 case NE
: fputs ("eq", file
); break;
2860 case LT
: fputs ("uge", file
); break;
2861 case LE
: fputs ("ug", file
); break;
2862 case GT
: fputs ("ule", file
); break;
2863 case GE
: fputs ("ul", file
); break;
2868 /* Print appropriate test for floating point branch true operation. */
2869 switch (GET_CODE (x
))
2872 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x
);
2874 case EQ
: fputs ("eq", file
); break;
2875 case NE
: fputs ("ne", file
); break;
2876 case LT
: fputs ("lt", file
); break;
2877 case LE
: fputs ("le", file
); break;
2878 case GT
: fputs ("gt", file
); break;
2879 case GE
: fputs ("ge", file
); break;
2884 /* Print appropriate GOT function. */
2885 if (GET_CODE (x
) != CONST_INT
)
2886 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x
);
2887 fputs (unspec_got_name (INTVAL (x
)), file
);
2891 /* Print 'i' if the operand is a constant, or is a memory reference that
2893 if (GET_CODE (x
) == MEM
)
2894 x
= ((GET_CODE (XEXP (x
, 0)) == PLUS
)
2895 ? XEXP (XEXP (x
, 0), 1)
2897 else if (GET_CODE (x
) == PLUS
)
2900 switch (GET_CODE (x
))
2914 /* For jump instructions, print 'i' if the operand is a constant or
2915 is an expression that adds a constant. */
2916 if (GET_CODE (x
) == CONST_INT
)
2921 if (GET_CODE (x
) == CONST_INT
2922 || (GET_CODE (x
) == PLUS
2923 && (GET_CODE (XEXP (x
, 1)) == CONST_INT
2924 || GET_CODE (XEXP (x
, 0)) == CONST_INT
)))
2930 /* Print the lower register of a double word register pair */
2931 if (GET_CODE (x
) == REG
)
2932 fputs (reg_names
[ REGNO (x
)+1 ], file
);
2934 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x
);
2937 /* case 'l': print a LABEL_REF. */
2941 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2942 for the second word of double memory operations. */
2943 offset
= (code
== 'M') ? 0 : UNITS_PER_WORD
;
2944 switch (GET_CODE (x
))
2947 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x
);
2950 frv_print_operand_memory_reference (file
, XEXP (x
, 0), offset
);
2958 frv_print_operand_memory_reference (file
, x
, offset
);
2964 /* Print the opcode of a command. */
2965 switch (GET_CODE (x
))
2968 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x
);
2970 case PLUS
: fputs ("add", file
); break;
2971 case MINUS
: fputs ("sub", file
); break;
2972 case AND
: fputs ("and", file
); break;
2973 case IOR
: fputs ("or", file
); break;
2974 case XOR
: fputs ("xor", file
); break;
2975 case ASHIFT
: fputs ("sll", file
); break;
2976 case ASHIFTRT
: fputs ("sra", file
); break;
2977 case LSHIFTRT
: fputs ("srl", file
); break;
2981 /* case 'n': negate and print a constant int. */
2984 /* Print PIC label using operand as the number. */
2985 if (GET_CODE (x
) != CONST_INT
)
2986 fatal_insn ("bad insn to frv_print_operand, P modifier:", x
);
2988 fprintf (file
, ".LCF%ld", (long)INTVAL (x
));
2992 /* Print 'u' if the operand is a update load/store. */
2993 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
2998 /* If value is 0, print gr0, otherwise it must be a register. */
2999 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0)
3000 fputs (reg_names
[GPR_R0
], file
);
3002 else if (GET_CODE (x
) == REG
)
3003 fputs (reg_names
[REGNO (x
)], file
);
3006 fatal_insn ("bad insn in frv_print_operand, z case", x
);
3010 /* Print constant in hex. */
3011 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
3013 fprintf (file
, "%s0x%.4lx", IMMEDIATE_PREFIX
, (long) value
);
3020 if (GET_CODE (x
) == REG
)
3021 fputs (reg_names
[REGNO (x
)], file
);
3023 else if (GET_CODE (x
) == CONST_INT
3024 || GET_CODE (x
) == CONST_DOUBLE
)
3025 fprintf (file
, "%s%ld", IMMEDIATE_PREFIX
, (long) value
);
3027 else if (frv_const_unspec_p (x
, &unspec
))
3028 frv_output_const_unspec (file
, &unspec
);
3030 else if (GET_CODE (x
) == MEM
)
3031 frv_print_operand_address (file
, XEXP (x
, 0));
3033 else if (CONSTANT_ADDRESS_P (x
))
3034 frv_print_operand_address (file
, x
);
3037 fatal_insn ("bad insn in frv_print_operand, 0 case", x
);
3042 fatal_insn ("frv_print_operand: unknown code", x
);
3050 frv_print_operand_punct_valid_p (unsigned char code
)
3052 return (code
== '.' || code
== '#' || code
== '@' || code
== '~'
3053 || code
== '*' || code
== '&');
3057 /* A C statement (sans semicolon) for initializing the variable CUM for the
3058 state at the beginning of the argument list. The variable has type
3059 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3060 of the function which will receive the args, or 0 if the args are to a
3061 compiler support library function. The value of INDIRECT is nonzero when
3062 processing an indirect call, for example a call through a function pointer.
3063 The value of INDIRECT is zero for a call to an explicitly named function, a
3064 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3065 arguments for the function being compiled.
3067 When processing a call to a compiler support library function, LIBNAME
3068 identifies which one. It is a `symbol_ref' rtx which contains the name of
3069 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3070 being processed. Thus, each time this macro is called, either LIBNAME or
3071 FNTYPE is nonzero, but never both of them at once. */
3074 frv_init_cumulative_args (CUMULATIVE_ARGS
*cum
,
3080 *cum
= FIRST_ARG_REGNUM
;
3082 if (TARGET_DEBUG_ARG
)
3084 fprintf (stderr
, "\ninit_cumulative_args:");
3085 if (!fndecl
&& fntype
)
3086 fputs (" indirect", stderr
);
3089 fputs (" incoming", stderr
);
3093 tree ret_type
= TREE_TYPE (fntype
);
3094 fprintf (stderr
, " return=%s,",
3095 get_tree_code_name (TREE_CODE (ret_type
)));
3098 if (libname
&& GET_CODE (libname
) == SYMBOL_REF
)
3099 fprintf (stderr
, " libname=%s", XSTR (libname
, 0));
3101 if (cfun
->returns_struct
)
3102 fprintf (stderr
, " return-struct");
3104 putc ('\n', stderr
);
3109 /* Return true if we should pass an argument on the stack rather than
3113 frv_must_pass_in_stack (machine_mode mode
, const_tree type
)
3115 if (mode
== BLKmode
)
3119 return AGGREGATE_TYPE_P (type
);
3122 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3123 argument with the specified mode and type. If it is not defined,
3124 `PARM_BOUNDARY' is used for all arguments. */
3127 frv_function_arg_boundary (machine_mode mode ATTRIBUTE_UNUSED
,
3128 const_tree type ATTRIBUTE_UNUSED
)
3130 return BITS_PER_WORD
;
3134 frv_function_arg_1 (cumulative_args_t cum_v
, machine_mode mode
,
3135 const_tree type ATTRIBUTE_UNUSED
, bool named
,
3136 bool incoming ATTRIBUTE_UNUSED
)
3138 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3140 machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3145 /* Return a marker for use in the call instruction. */
3146 if (xmode
== VOIDmode
)
3152 else if (arg_num
<= LAST_ARG_REGNUM
)
3154 ret
= gen_rtx_REG (xmode
, arg_num
);
3155 debstr
= reg_names
[arg_num
];
3164 if (TARGET_DEBUG_ARG
)
3166 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3167 arg_num
, GET_MODE_NAME (mode
), named
, GET_MODE_SIZE (mode
), debstr
);
3173 frv_function_arg (cumulative_args_t cum
, machine_mode mode
,
3174 const_tree type
, bool named
)
3176 return frv_function_arg_1 (cum
, mode
, type
, named
, false);
3180 frv_function_incoming_arg (cumulative_args_t cum
, machine_mode mode
,
3181 const_tree type
, bool named
)
3183 return frv_function_arg_1 (cum
, mode
, type
, named
, true);
3187 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3188 advance past an argument in the argument list. The values MODE, TYPE and
3189 NAMED describe that argument. Once this is done, the variable CUM is
3190 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3192 This macro need not do anything if the argument in question was passed on
3193 the stack. The compiler knows how to track the amount of stack space used
3194 for arguments without any special help. */
3197 frv_function_arg_advance (cumulative_args_t cum_v
,
3199 const_tree type ATTRIBUTE_UNUSED
,
3202 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3204 machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3205 int bytes
= GET_MODE_SIZE (xmode
);
3206 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3209 *cum
= arg_num
+ words
;
3211 if (TARGET_DEBUG_ARG
)
3213 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3214 arg_num
, GET_MODE_NAME (mode
), named
, words
* UNITS_PER_WORD
);
3218 /* A C expression for the number of words, at the beginning of an argument,
3219 must be put in registers. The value must be zero for arguments that are
3220 passed entirely in registers or that are entirely pushed on the stack.
3222 On some machines, certain arguments must be passed partially in registers
3223 and partially in memory. On these machines, typically the first N words of
3224 arguments are passed in registers, and the rest on the stack. If a
3225 multi-word argument (a `double' or a structure) crosses that boundary, its
3226 first few words must be passed in registers and the rest must be pushed.
3227 This macro tells the compiler when this occurs, and how many of the words
3228 should go in registers.
3230 `FUNCTION_ARG' for these arguments should return the first register to be
3231 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3232 the called function. */
3235 frv_arg_partial_bytes (cumulative_args_t cum
, machine_mode mode
,
3236 tree type ATTRIBUTE_UNUSED
, bool named ATTRIBUTE_UNUSED
)
3239 machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3240 int bytes
= GET_MODE_SIZE (xmode
);
3241 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3242 int arg_num
= *get_cumulative_args (cum
);
3245 ret
= ((arg_num
<= LAST_ARG_REGNUM
&& arg_num
+ words
> LAST_ARG_REGNUM
+1)
3246 ? LAST_ARG_REGNUM
- arg_num
+ 1
3248 ret
*= UNITS_PER_WORD
;
3250 if (TARGET_DEBUG_ARG
&& ret
)
3251 fprintf (stderr
, "frv_arg_partial_bytes: %d\n", ret
);
3257 /* Implements TARGET_FUNCTION_VALUE. */
3260 frv_function_value (const_tree valtype
,
3261 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
3262 bool outgoing ATTRIBUTE_UNUSED
)
3264 return gen_rtx_REG (TYPE_MODE (valtype
), RETURN_VALUE_REGNUM
);
3268 /* Implements TARGET_LIBCALL_VALUE. */
3271 frv_libcall_value (machine_mode mode
,
3272 const_rtx fun ATTRIBUTE_UNUSED
)
3274 return gen_rtx_REG (mode
, RETURN_VALUE_REGNUM
);
3278 /* Implements FUNCTION_VALUE_REGNO_P. */
3281 frv_function_value_regno_p (const unsigned int regno
)
3283 return (regno
== RETURN_VALUE_REGNUM
);
3286 /* Return true if a register is ok to use as a base or index register. */
3288 static FRV_INLINE
int
3289 frv_regno_ok_for_base_p (int regno
, int strict_p
)
3295 return (reg_renumber
[regno
] >= 0 && GPR_P (reg_renumber
[regno
]));
3297 if (regno
== ARG_POINTER_REGNUM
)
3300 return (regno
>= FIRST_PSEUDO_REGISTER
);
3304 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3305 RTX) is a legitimate memory address on the target machine for a memory
3306 operand of mode MODE.
3308 It usually pays to define several simpler macros to serve as subroutines for
3309 this one. Otherwise it may be too complicated to understand.
3311 This macro must exist in two variants: a strict variant and a non-strict
3312 one. The strict variant is used in the reload pass. It must be defined so
3313 that any pseudo-register that has not been allocated a hard register is
3314 considered a memory reference. In contexts where some kind of register is
3315 required, a pseudo-register with no hard register must be rejected.
3317 The non-strict variant is used in other passes. It must be defined to
3318 accept all pseudo-registers in every context where some kind of register is
3321 Compiler source files that want to use the strict variant of this macro
3322 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3323 conditional to define the strict variant in that case and the non-strict
3326 Normally, constant addresses which are the sum of a `symbol_ref' and an
3327 integer are stored inside a `const' RTX to mark them as constant.
3328 Therefore, there is no need to recognize such sums specifically as
3329 legitimate addresses. Normally you would simply recognize any `const' as
3332 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3333 constant sums that are not marked with `const'. It assumes that a
3334 naked `plus' indicates indexing. If so, then you *must* reject such
3335 naked constant sums as illegitimate addresses, so that none of them
3336 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3339 frv_legitimate_address_p_1 (machine_mode mode
,
3343 int allow_double_reg_p
)
3347 HOST_WIDE_INT value
;
3350 if (FRV_SYMBOL_REF_TLS_P (x
))
3353 switch (GET_CODE (x
))
3360 if (GET_CODE (x
) != REG
)
3366 ret
= frv_regno_ok_for_base_p (REGNO (x
), strict_p
);
3372 if (GET_CODE (x0
) != REG
3373 || ! frv_regno_ok_for_base_p (REGNO (x0
), strict_p
)
3374 || GET_CODE (x1
) != PLUS
3375 || ! rtx_equal_p (x0
, XEXP (x1
, 0))
3376 || GET_CODE (XEXP (x1
, 1)) != REG
3377 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1
, 1)), strict_p
))
3384 /* 12-bit immediate */
3389 ret
= IN_RANGE (INTVAL (x
), -2048, 2047);
3391 /* If we can't use load/store double operations, make sure we can
3392 address the second word. */
3393 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3394 ret
= IN_RANGE (INTVAL (x
) + GET_MODE_SIZE (mode
) - 1,
3403 if (GET_CODE (x0
) == SUBREG
)
3404 x0
= SUBREG_REG (x0
);
3406 if (GET_CODE (x0
) != REG
)
3409 regno0
= REGNO (x0
);
3410 if (!frv_regno_ok_for_base_p (regno0
, strict_p
))
3413 switch (GET_CODE (x1
))
3419 x1
= SUBREG_REG (x1
);
3420 if (GET_CODE (x1
) != REG
)
3426 /* Do not allow reg+reg addressing for modes > 1 word if we
3427 can't depend on having move double instructions. */
3428 if (!allow_double_reg_p
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3431 ret
= frv_regno_ok_for_base_p (REGNO (x1
), strict_p
);
3435 /* 12-bit immediate */
3440 value
= INTVAL (x1
);
3441 ret
= IN_RANGE (value
, -2048, 2047);
3443 /* If we can't use load/store double operations, make sure we can
3444 address the second word. */
3445 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3446 ret
= IN_RANGE (value
+ GET_MODE_SIZE (mode
) - 1, -2048, 2047);
3451 if (!condexec_p
&& got12_operand (x1
, VOIDmode
))
3459 if (TARGET_DEBUG_ADDR
)
3461 fprintf (stderr
, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3462 GET_MODE_NAME (mode
), ret
, (strict_p
) ? "" : "not ",
3463 (condexec_p
) ? ", inside conditional code" : "");
3471 frv_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
3473 return frv_legitimate_address_p_1 (mode
, x
, strict_p
, FALSE
, FALSE
);
3476 /* Given an ADDR, generate code to inline the PLT. */
3478 gen_inlined_tls_plt (rtx addr
)
3481 rtx picreg
= get_hard_reg_initial_val (Pmode
, FDPIC_REG
);
3484 dest
= gen_reg_rtx (DImode
);
3491 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3492 calll #gettlsoff(ADDR)@(gr8, gr0)
3494 emit_insn (gen_tls_lddi (dest
, addr
, picreg
));
3501 sethi.p #gottlsdeschi(ADDR), gr8
3502 setlo #gottlsdesclo(ADDR), gr8
3503 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3504 calll #gettlsoff(ADDR)@(gr8, gr0)
3506 rtx reguse
= gen_reg_rtx (Pmode
);
3507 emit_insn (gen_tlsoff_hilo (reguse
, addr
, GEN_INT (R_FRV_GOTTLSDESCHI
)));
3508 emit_insn (gen_tls_tlsdesc_ldd (dest
, picreg
, reguse
, addr
));
3511 retval
= gen_reg_rtx (Pmode
);
3512 emit_insn (gen_tls_indirect_call (retval
, addr
, dest
, picreg
));
3516 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3517 the destination address. */
3519 gen_tlsmoff (rtx addr
, rtx reg
)
3521 rtx dest
= gen_reg_rtx (Pmode
);
3525 /* sethi.p #tlsmoffhi(x), grA
3526 setlo #tlsmofflo(x), grA
3528 dest
= gen_reg_rtx (Pmode
);
3529 emit_insn (gen_tlsoff_hilo (dest
, addr
,
3530 GEN_INT (R_FRV_TLSMOFFHI
)));
3531 dest
= gen_rtx_PLUS (Pmode
, dest
, reg
);
3535 /* addi grB, #tlsmoff12(x), grC
3537 ld/st @(grB, #tlsmoff12(x)), grC
3539 dest
= gen_reg_rtx (Pmode
);
3540 emit_insn (gen_symGOTOFF2reg_i (dest
, addr
, reg
,
3541 GEN_INT (R_FRV_TLSMOFF12
)));
3546 /* Generate code for a TLS address. */
3548 frv_legitimize_tls_address (rtx addr
, enum tls_model model
)
3550 rtx dest
, tp
= gen_rtx_REG (Pmode
, 29);
3551 rtx picreg
= get_hard_reg_initial_val (Pmode
, 15);
3555 case TLS_MODEL_INITIAL_EXEC
:
3559 ldi @(gr15, #gottlsoff12(x)), gr5
3561 dest
= gen_reg_rtx (Pmode
);
3562 emit_insn (gen_tls_load_gottlsoff12 (dest
, addr
, picreg
));
3563 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3567 /* -fPIC or anything else.
3569 sethi.p #gottlsoffhi(x), gr14
3570 setlo #gottlsofflo(x), gr14
3571 ld #tlsoff(x)@(gr15, gr14), gr9
3573 rtx tmp
= gen_reg_rtx (Pmode
);
3574 dest
= gen_reg_rtx (Pmode
);
3575 emit_insn (gen_tlsoff_hilo (tmp
, addr
,
3576 GEN_INT (R_FRV_GOTTLSOFF_HI
)));
3578 emit_insn (gen_tls_tlsoff_ld (dest
, picreg
, tmp
, addr
));
3579 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3582 case TLS_MODEL_LOCAL_DYNAMIC
:
3586 if (TARGET_INLINE_PLT
)
3587 retval
= gen_inlined_tls_plt (GEN_INT (0));
3590 /* call #gettlsoff(0) */
3591 retval
= gen_reg_rtx (Pmode
);
3592 emit_insn (gen_call_gettlsoff (retval
, GEN_INT (0), picreg
));
3595 reg
= gen_reg_rtx (Pmode
);
3596 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
3597 gen_rtx_PLUS (Pmode
,
3600 dest
= gen_tlsmoff (addr
, reg
);
3603 dest = gen_reg_rtx (Pmode);
3604 emit_insn (gen_tlsoff_hilo (dest, addr,
3605 GEN_INT (R_FRV_TLSMOFFHI)));
3606 dest = gen_rtx_PLUS (Pmode, dest, reg);
3610 case TLS_MODEL_LOCAL_EXEC
:
3611 dest
= gen_tlsmoff (addr
, gen_rtx_REG (Pmode
, 29));
3613 case TLS_MODEL_GLOBAL_DYNAMIC
:
3617 if (TARGET_INLINE_PLT
)
3618 retval
= gen_inlined_tls_plt (addr
);
3621 /* call #gettlsoff(x) */
3622 retval
= gen_reg_rtx (Pmode
);
3623 emit_insn (gen_call_gettlsoff (retval
, addr
, picreg
));
3625 dest
= gen_rtx_PLUS (Pmode
, retval
, tp
);
3636 frv_legitimize_address (rtx x
,
3637 rtx oldx ATTRIBUTE_UNUSED
,
3638 machine_mode mode ATTRIBUTE_UNUSED
)
3640 if (GET_CODE (x
) == SYMBOL_REF
)
3642 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3644 return frv_legitimize_tls_address (x
, model
);
3650 /* Test whether a local function descriptor is canonical, i.e.,
3651 whether we can use FUNCDESC_GOTOFF to compute the address of the
3655 frv_local_funcdesc_p (rtx fnx
)
3658 enum symbol_visibility vis
;
3661 if (! SYMBOL_REF_LOCAL_P (fnx
))
3664 fn
= SYMBOL_REF_DECL (fnx
);
3669 vis
= DECL_VISIBILITY (fn
);
3671 if (vis
== VISIBILITY_PROTECTED
)
3672 /* Private function descriptors for protected functions are not
3673 canonical. Temporarily change the visibility to global. */
3674 vis
= VISIBILITY_DEFAULT
;
3675 else if (flag_shlib
)
3676 /* If we're already compiling for a shared library (that, unlike
3677 executables, can't assume that the existence of a definition
3678 implies local binding), we can skip the re-testing. */
3681 ret
= default_binds_local_p_1 (fn
, flag_pic
);
3683 DECL_VISIBILITY (fn
) = vis
;
3688 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3692 frv_gen_GPsym2reg (rtx dest
, rtx src
)
3694 tree gp
= get_identifier ("_gp");
3695 rtx gp_sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (gp
));
3697 return gen_symGOT2reg (dest
, gp_sym
, src
, GEN_INT (R_FRV_GOT12
));
3701 unspec_got_name (int i
)
3705 case R_FRV_GOT12
: return "got12";
3706 case R_FRV_GOTHI
: return "gothi";
3707 case R_FRV_GOTLO
: return "gotlo";
3708 case R_FRV_FUNCDESC
: return "funcdesc";
3709 case R_FRV_FUNCDESC_GOT12
: return "gotfuncdesc12";
3710 case R_FRV_FUNCDESC_GOTHI
: return "gotfuncdeschi";
3711 case R_FRV_FUNCDESC_GOTLO
: return "gotfuncdesclo";
3712 case R_FRV_FUNCDESC_VALUE
: return "funcdescvalue";
3713 case R_FRV_FUNCDESC_GOTOFF12
: return "gotofffuncdesc12";
3714 case R_FRV_FUNCDESC_GOTOFFHI
: return "gotofffuncdeschi";
3715 case R_FRV_FUNCDESC_GOTOFFLO
: return "gotofffuncdesclo";
3716 case R_FRV_GOTOFF12
: return "gotoff12";
3717 case R_FRV_GOTOFFHI
: return "gotoffhi";
3718 case R_FRV_GOTOFFLO
: return "gotofflo";
3719 case R_FRV_GPREL12
: return "gprel12";
3720 case R_FRV_GPRELHI
: return "gprelhi";
3721 case R_FRV_GPRELLO
: return "gprello";
3722 case R_FRV_GOTTLSOFF_HI
: return "gottlsoffhi";
3723 case R_FRV_GOTTLSOFF_LO
: return "gottlsofflo";
3724 case R_FRV_TLSMOFFHI
: return "tlsmoffhi";
3725 case R_FRV_TLSMOFFLO
: return "tlsmofflo";
3726 case R_FRV_TLSMOFF12
: return "tlsmoff12";
3727 case R_FRV_TLSDESCHI
: return "tlsdeschi";
3728 case R_FRV_TLSDESCLO
: return "tlsdesclo";
3729 case R_FRV_GOTTLSDESCHI
: return "gottlsdeschi";
3730 case R_FRV_GOTTLSDESCLO
: return "gottlsdesclo";
3731 default: gcc_unreachable ();
3735 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3736 is added inside the relocation operator. */
3739 frv_output_const_unspec (FILE *stream
, const struct frv_unspec
*unspec
)
3741 fprintf (stream
, "#%s(", unspec_got_name (unspec
->reloc
));
3742 output_addr_const (stream
, plus_constant (Pmode
, unspec
->symbol
,
3744 fputs (")", stream
);
3747 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3748 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3749 otherwise return ORIG_X. */
3752 frv_find_base_term (rtx x
)
3754 struct frv_unspec unspec
;
3756 if (frv_const_unspec_p (x
, &unspec
)
3757 && frv_small_data_reloc_p (unspec
.symbol
, unspec
.reloc
))
3758 return plus_constant (Pmode
, unspec
.symbol
, unspec
.offset
);
3763 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3764 the operand is used by a predicated instruction. */
3767 frv_legitimate_memory_operand (rtx op
, machine_mode mode
, int condexec_p
)
3769 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
3770 && GET_CODE (op
) == MEM
3771 && frv_legitimate_address_p_1 (mode
, XEXP (op
, 0),
3772 reload_completed
, condexec_p
, FALSE
));
3776 frv_expand_fdpic_call (rtx
*operands
, bool ret_value
, bool sibcall
)
3778 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
3779 rtx picreg
= get_hard_reg_initial_val (SImode
, FDPIC_REG
);
3785 rvrtx
= operands
[0];
3789 addr
= XEXP (operands
[0], 0);
3791 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3792 any calls that would involve a PLT, but can't tell, since we
3793 don't know whether an extern function is going to be provided by
3794 a separate translation unit or imported from a separate module.
3795 When compiling for shared libraries, if the function has default
3796 visibility, we assume it's overridable, so we inline the PLT, but
3797 for executables, we don't really have a way to make a good
3798 decision: a function is as likely to be imported from a shared
3799 library as it is to be defined in the executable itself. We
3800 assume executables will get global functions defined locally,
3801 whereas shared libraries will have them potentially overridden,
3802 so we only inline PLTs when compiling for shared libraries.
3804 In order to mark a function as local to a shared library, any
3805 non-default visibility attribute suffices. Unfortunately,
3806 there's no simple way to tag a function declaration as ``in a
3807 different module'', which we could then use to trigger PLT
3808 inlining on executables. There's -minline-plt, but it affects
3809 all external functions, so one would have to also mark function
3810 declarations available in the same module with non-default
3811 visibility, which is advantageous in itself. */
3812 if (GET_CODE (addr
) == SYMBOL_REF
3813 && ((!SYMBOL_REF_LOCAL_P (addr
) && TARGET_INLINE_PLT
)
3817 dest
= gen_reg_rtx (SImode
);
3819 x
= gen_symGOTOFF2reg_hilo (dest
, addr
, OUR_FDPIC_REG
,
3820 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3822 x
= gen_symGOTOFF2reg (dest
, addr
, OUR_FDPIC_REG
,
3823 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3825 crtl
->uses_pic_offset_table
= TRUE
;
3828 else if (GET_CODE (addr
) == SYMBOL_REF
)
3830 /* These are always either local, or handled through a local
3833 c
= gen_call_value_fdpicsi (rvrtx
, addr
, operands
[1],
3834 operands
[2], picreg
, lr
);
3836 c
= gen_call_fdpicsi (addr
, operands
[1], operands
[2], picreg
, lr
);
3840 else if (! ldd_address_operand (addr
, Pmode
))
3841 addr
= force_reg (Pmode
, addr
);
3843 picreg
= gen_reg_rtx (DImode
);
3844 emit_insn (gen_movdi_ldd (picreg
, addr
));
3846 if (sibcall
&& ret_value
)
3847 c
= gen_sibcall_value_fdpicdi (rvrtx
, picreg
, const0_rtx
);
3849 c
= gen_sibcall_fdpicdi (picreg
, const0_rtx
);
3851 c
= gen_call_value_fdpicdi (rvrtx
, picreg
, const0_rtx
, lr
);
3853 c
= gen_call_fdpicdi (picreg
, const0_rtx
, lr
);
3857 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3858 process these separately from any offsets, such that we add any
3859 offsets to the function descriptor (the actual pointer), not to the
3860 function address. */
3863 frv_function_symbol_referenced_p (rtx x
)
3869 if (GET_CODE (x
) == SYMBOL_REF
)
3870 return SYMBOL_REF_FUNCTION_P (x
);
3872 length
= GET_RTX_LENGTH (GET_CODE (x
));
3873 format
= GET_RTX_FORMAT (GET_CODE (x
));
3875 for (j
= 0; j
< length
; ++j
)
3880 if (frv_function_symbol_referenced_p (XEXP (x
, j
)))
3886 if (XVEC (x
, j
) != 0)
3889 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
3890 if (frv_function_symbol_referenced_p (XVECEXP (x
, j
, k
)))
3896 /* Nothing to do. */
3904 /* Return true if the memory operand is one that can be conditionally
3908 condexec_memory_operand (rtx op
, machine_mode mode
)
3910 machine_mode op_mode
= GET_MODE (op
);
3913 if (mode
!= VOIDmode
&& op_mode
!= mode
)
3928 if (GET_CODE (op
) != MEM
)
3931 addr
= XEXP (op
, 0);
3932 return frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
);
3935 /* Return true if the bare return instruction can be used outside of the
3936 epilog code. For frv, we only do it if there was no stack allocation. */
3939 direct_return_p (void)
3943 if (!reload_completed
)
3946 info
= frv_stack_info ();
3947 return (info
->total_size
== 0);
3952 frv_emit_move (machine_mode mode
, rtx dest
, rtx src
)
3954 if (GET_CODE (src
) == SYMBOL_REF
)
3956 enum tls_model model
= SYMBOL_REF_TLS_MODEL (src
);
3958 src
= frv_legitimize_tls_address (src
, model
);
3964 if (frv_emit_movsi (dest
, src
))
3973 if (!reload_in_progress
3974 && !reload_completed
3975 && !register_operand (dest
, mode
)
3976 && !reg_or_0_operand (src
, mode
))
3977 src
= copy_to_mode_reg (mode
, src
);
3984 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3987 /* Emit code to handle a MOVSI, adding in the small data register or pic
3988 register if needed to load up addresses. Return TRUE if the appropriate
3989 instructions are emitted. */
3992 frv_emit_movsi (rtx dest
, rtx src
)
3994 int base_regno
= -1;
3997 struct frv_unspec old_unspec
;
3999 if (!reload_in_progress
4000 && !reload_completed
4001 && !register_operand (dest
, SImode
)
4002 && (!reg_or_0_operand (src
, SImode
)
4003 /* Virtual registers will almost always be replaced by an
4004 add instruction, so expose this to CSE by copying to
4005 an intermediate register. */
4006 || (GET_CODE (src
) == REG
4007 && IN_RANGE (REGNO (src
),
4008 FIRST_VIRTUAL_REGISTER
,
4009 LAST_VIRTUAL_POINTER_REGISTER
))))
4011 emit_insn (gen_rtx_SET (VOIDmode
, dest
, copy_to_mode_reg (SImode
, src
)));
4015 /* Explicitly add in the PIC or small data register if needed. */
4016 switch (GET_CODE (src
))
4025 /* Using GPREL12, we use a single GOT entry for all symbols
4026 in read-only sections, but trade sequences such as:
4028 sethi #gothi(label), gr#
4029 setlo #gotlo(label), gr#
4034 ld @(gr15,#got12(_gp)), gr#
4035 sethi #gprelhi(label), gr##
4036 setlo #gprello(label), gr##
4039 We may often be able to share gr# for multiple
4040 computations of GPREL addresses, and we may often fold
4041 the final add into the pair of registers of a load or
4042 store instruction, so it's often profitable. Even when
4043 optimizing for size, we're trading a GOT entry for an
4044 additional instruction, which trades GOT space
4045 (read-write) for code size (read-only, shareable), as
4046 long as the symbol is not used in more than two different
4049 With -fpie/-fpic, we'd be trading a single load for a
4050 sequence of 4 instructions, because the offset of the
4051 label can't be assumed to be addressable with 12 bits, so
4052 we don't do this. */
4053 if (TARGET_GPREL_RO
)
4054 unspec
= R_FRV_GPREL12
;
4056 unspec
= R_FRV_GOT12
;
4059 base_regno
= PIC_REGNO
;
4064 if (frv_const_unspec_p (src
, &old_unspec
))
4067 if (TARGET_FDPIC
&& frv_function_symbol_referenced_p (XEXP (src
, 0)))
4070 src
= force_reg (GET_MODE (XEXP (src
, 0)), XEXP (src
, 0));
4071 emit_move_insn (dest
, src
);
4076 sym
= XEXP (sym
, 0);
4077 if (GET_CODE (sym
) == PLUS
4078 && GET_CODE (XEXP (sym
, 0)) == SYMBOL_REF
4079 && GET_CODE (XEXP (sym
, 1)) == CONST_INT
)
4080 sym
= XEXP (sym
, 0);
4081 if (GET_CODE (sym
) == SYMBOL_REF
)
4083 else if (GET_CODE (sym
) == LABEL_REF
)
4086 goto handle_whatever
;
4094 enum tls_model model
= SYMBOL_REF_TLS_MODEL (sym
);
4098 src
= frv_legitimize_tls_address (src
, model
);
4099 emit_move_insn (dest
, src
);
4103 if (SYMBOL_REF_FUNCTION_P (sym
))
4105 if (frv_local_funcdesc_p (sym
))
4106 unspec
= R_FRV_FUNCDESC_GOTOFF12
;
4108 unspec
= R_FRV_FUNCDESC_GOT12
;
4112 if (CONSTANT_POOL_ADDRESS_P (sym
))
4113 switch (GET_CODE (get_pool_constant (sym
)))
4120 unspec
= R_FRV_GOTOFF12
;
4125 if (TARGET_GPREL_RO
)
4126 unspec
= R_FRV_GPREL12
;
4128 unspec
= R_FRV_GOT12
;
4131 else if (SYMBOL_REF_LOCAL_P (sym
)
4132 && !SYMBOL_REF_EXTERNAL_P (sym
)
4133 && SYMBOL_REF_DECL (sym
)
4134 && (!DECL_P (SYMBOL_REF_DECL (sym
))
4135 || !DECL_COMMON (SYMBOL_REF_DECL (sym
))))
4137 tree decl
= SYMBOL_REF_DECL (sym
);
4138 tree init
= TREE_CODE (decl
) == VAR_DECL
4139 ? DECL_INITIAL (decl
)
4140 : TREE_CODE (decl
) == CONSTRUCTOR
4143 bool named_section
, readonly
;
4145 if (init
&& init
!= error_mark_node
)
4146 reloc
= compute_reloc_for_constant (init
);
4148 named_section
= TREE_CODE (decl
) == VAR_DECL
4149 && lookup_attribute ("section", DECL_ATTRIBUTES (decl
));
4150 readonly
= decl_readonly_section (decl
, reloc
);
4153 unspec
= R_FRV_GOT12
;
4155 unspec
= R_FRV_GOTOFF12
;
4156 else if (readonly
&& TARGET_GPREL_RO
)
4157 unspec
= R_FRV_GPREL12
;
4159 unspec
= R_FRV_GOT12
;
4162 unspec
= R_FRV_GOT12
;
4166 else if (SYMBOL_REF_SMALL_P (sym
))
4167 base_regno
= SDA_BASE_REG
;
4170 base_regno
= PIC_REGNO
;
4175 if (base_regno
>= 0)
4177 if (GET_CODE (sym
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_P (sym
))
4178 emit_insn (gen_symGOTOFF2reg (dest
, src
,
4179 gen_rtx_REG (Pmode
, base_regno
),
4180 GEN_INT (R_FRV_GPREL12
)));
4182 emit_insn (gen_symGOTOFF2reg_hilo (dest
, src
,
4183 gen_rtx_REG (Pmode
, base_regno
),
4184 GEN_INT (R_FRV_GPREL12
)));
4185 if (base_regno
== PIC_REGNO
)
4186 crtl
->uses_pic_offset_table
= TRUE
;
4194 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4195 new uses of it once reload has begun. */
4196 gcc_assert (!reload_in_progress
&& !reload_completed
);
4200 case R_FRV_GOTOFF12
:
4201 if (!frv_small_data_reloc_p (sym
, unspec
))
4202 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4205 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4208 if (!frv_small_data_reloc_p (sym
, unspec
))
4209 x
= gen_symGPREL2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4212 x
= gen_symGPREL2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4214 case R_FRV_FUNCDESC_GOTOFF12
:
4216 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4219 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4223 x
= gen_symGOT2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4226 x
= gen_symGOT2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4230 crtl
->uses_pic_offset_table
= TRUE
;
4239 /* Return a string to output a single word move. */
4242 output_move_single (rtx operands
[], rtx insn
)
4244 rtx dest
= operands
[0];
4245 rtx src
= operands
[1];
4247 if (GET_CODE (dest
) == REG
)
4249 int dest_regno
= REGNO (dest
);
4250 machine_mode mode
= GET_MODE (dest
);
4252 if (GPR_P (dest_regno
))
4254 if (GET_CODE (src
) == REG
)
4256 /* gpr <- some sort of register */
4257 int src_regno
= REGNO (src
);
4259 if (GPR_P (src_regno
))
4260 return "mov %1, %0";
4262 else if (FPR_P (src_regno
))
4263 return "movfg %1, %0";
4265 else if (SPR_P (src_regno
))
4266 return "movsg %1, %0";
4269 else if (GET_CODE (src
) == MEM
)
4278 return "ldsb%I1%U1 %M1,%0";
4281 return "ldsh%I1%U1 %M1,%0";
4285 return "ld%I1%U1 %M1, %0";
4289 else if (GET_CODE (src
) == CONST_INT
4290 || GET_CODE (src
) == CONST_DOUBLE
)
4292 /* gpr <- integer/floating constant */
4293 HOST_WIDE_INT value
;
4295 if (GET_CODE (src
) == CONST_INT
)
4296 value
= INTVAL (src
);
4298 else if (mode
== SFmode
)
4303 REAL_VALUE_FROM_CONST_DOUBLE (rv
, src
);
4304 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4309 value
= CONST_DOUBLE_LOW (src
);
4311 if (IN_RANGE (value
, -32768, 32767))
4312 return "setlos %1, %0";
4317 else if (GET_CODE (src
) == SYMBOL_REF
4318 || GET_CODE (src
) == LABEL_REF
4319 || GET_CODE (src
) == CONST
)
4325 else if (FPR_P (dest_regno
))
4327 if (GET_CODE (src
) == REG
)
4329 /* fpr <- some sort of register */
4330 int src_regno
= REGNO (src
);
4332 if (GPR_P (src_regno
))
4333 return "movgf %1, %0";
4335 else if (FPR_P (src_regno
))
4337 if (TARGET_HARD_FLOAT
)
4338 return "fmovs %1, %0";
4340 return "mor %1, %1, %0";
4344 else if (GET_CODE (src
) == MEM
)
4353 return "ldbf%I1%U1 %M1,%0";
4356 return "ldhf%I1%U1 %M1,%0";
4360 return "ldf%I1%U1 %M1, %0";
4364 else if (ZERO_P (src
))
4365 return "movgf %., %0";
4368 else if (SPR_P (dest_regno
))
4370 if (GET_CODE (src
) == REG
)
4372 /* spr <- some sort of register */
4373 int src_regno
= REGNO (src
);
4375 if (GPR_P (src_regno
))
4376 return "movgs %1, %0";
4378 else if (ZERO_P (src
))
4379 return "movgs %., %0";
4383 else if (GET_CODE (dest
) == MEM
)
4385 if (GET_CODE (src
) == REG
)
4387 int src_regno
= REGNO (src
);
4388 machine_mode mode
= GET_MODE (dest
);
4390 if (GPR_P (src_regno
))
4398 return "stb%I0%U0 %1, %M0";
4401 return "sth%I0%U0 %1, %M0";
4405 return "st%I0%U0 %1, %M0";
4409 else if (FPR_P (src_regno
))
4417 return "stbf%I0%U0 %1, %M0";
4420 return "sthf%I0%U0 %1, %M0";
4424 return "stf%I0%U0 %1, %M0";
4429 else if (ZERO_P (src
))
4431 switch (GET_MODE (dest
))
4437 return "stb%I0%U0 %., %M0";
4440 return "sth%I0%U0 %., %M0";
4444 return "st%I0%U0 %., %M0";
4449 fatal_insn ("bad output_move_single operand", insn
);
4454 /* Return a string to output a double word move. */
4457 output_move_double (rtx operands
[], rtx insn
)
4459 rtx dest
= operands
[0];
4460 rtx src
= operands
[1];
4461 machine_mode mode
= GET_MODE (dest
);
4463 if (GET_CODE (dest
) == REG
)
4465 int dest_regno
= REGNO (dest
);
4467 if (GPR_P (dest_regno
))
4469 if (GET_CODE (src
) == REG
)
4471 /* gpr <- some sort of register */
4472 int src_regno
= REGNO (src
);
4474 if (GPR_P (src_regno
))
4477 else if (FPR_P (src_regno
))
4479 if (((dest_regno
- GPR_FIRST
) & 1) == 0
4480 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4481 return "movfgd %1, %0";
4487 else if (GET_CODE (src
) == MEM
)
4490 if (dbl_memory_one_insn_operand (src
, mode
))
4491 return "ldd%I1%U1 %M1, %0";
4496 else if (GET_CODE (src
) == CONST_INT
4497 || GET_CODE (src
) == CONST_DOUBLE
)
4501 else if (FPR_P (dest_regno
))
4503 if (GET_CODE (src
) == REG
)
4505 /* fpr <- some sort of register */
4506 int src_regno
= REGNO (src
);
4508 if (GPR_P (src_regno
))
4510 if (((dest_regno
- FPR_FIRST
) & 1) == 0
4511 && ((src_regno
- GPR_FIRST
) & 1) == 0)
4512 return "movgfd %1, %0";
4517 else if (FPR_P (src_regno
))
4520 && ((dest_regno
- FPR_FIRST
) & 1) == 0
4521 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4522 return "fmovd %1, %0";
4528 else if (GET_CODE (src
) == MEM
)
4531 if (dbl_memory_one_insn_operand (src
, mode
))
4532 return "lddf%I1%U1 %M1, %0";
4537 else if (ZERO_P (src
))
4542 else if (GET_CODE (dest
) == MEM
)
4544 if (GET_CODE (src
) == REG
)
4546 int src_regno
= REGNO (src
);
4548 if (GPR_P (src_regno
))
4550 if (((src_regno
- GPR_FIRST
) & 1) == 0
4551 && dbl_memory_one_insn_operand (dest
, mode
))
4552 return "std%I0%U0 %1, %M0";
4557 if (FPR_P (src_regno
))
4559 if (((src_regno
- FPR_FIRST
) & 1) == 0
4560 && dbl_memory_one_insn_operand (dest
, mode
))
4561 return "stdf%I0%U0 %1, %M0";
4567 else if (ZERO_P (src
))
4569 if (dbl_memory_one_insn_operand (dest
, mode
))
4570 return "std%I0%U0 %., %M0";
4576 fatal_insn ("bad output_move_double operand", insn
);
4581 /* Return a string to output a single word conditional move.
4582 Operand0 -- EQ/NE of ccr register and 0
4583 Operand1 -- CCR register
4584 Operand2 -- destination
4585 Operand3 -- source */
4588 output_condmove_single (rtx operands
[], rtx insn
)
4590 rtx dest
= operands
[2];
4591 rtx src
= operands
[3];
4593 if (GET_CODE (dest
) == REG
)
4595 int dest_regno
= REGNO (dest
);
4596 machine_mode mode
= GET_MODE (dest
);
4598 if (GPR_P (dest_regno
))
4600 if (GET_CODE (src
) == REG
)
4602 /* gpr <- some sort of register */
4603 int src_regno
= REGNO (src
);
4605 if (GPR_P (src_regno
))
4606 return "cmov %z3, %2, %1, %e0";
4608 else if (FPR_P (src_regno
))
4609 return "cmovfg %3, %2, %1, %e0";
4612 else if (GET_CODE (src
) == MEM
)
4621 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4624 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4628 return "cld%I3%U3 %M3, %2, %1, %e0";
4632 else if (ZERO_P (src
))
4633 return "cmov %., %2, %1, %e0";
4636 else if (FPR_P (dest_regno
))
4638 if (GET_CODE (src
) == REG
)
4640 /* fpr <- some sort of register */
4641 int src_regno
= REGNO (src
);
4643 if (GPR_P (src_regno
))
4644 return "cmovgf %3, %2, %1, %e0";
4646 else if (FPR_P (src_regno
))
4648 if (TARGET_HARD_FLOAT
)
4649 return "cfmovs %3,%2,%1,%e0";
4651 return "cmor %3, %3, %2, %1, %e0";
4655 else if (GET_CODE (src
) == MEM
)
4658 if (mode
== SImode
|| mode
== SFmode
)
4659 return "cldf%I3%U3 %M3, %2, %1, %e0";
4662 else if (ZERO_P (src
))
4663 return "cmovgf %., %2, %1, %e0";
4667 else if (GET_CODE (dest
) == MEM
)
4669 if (GET_CODE (src
) == REG
)
4671 int src_regno
= REGNO (src
);
4672 machine_mode mode
= GET_MODE (dest
);
4674 if (GPR_P (src_regno
))
4682 return "cstb%I2%U2 %3, %M2, %1, %e0";
4685 return "csth%I2%U2 %3, %M2, %1, %e0";
4689 return "cst%I2%U2 %3, %M2, %1, %e0";
4693 else if (FPR_P (src_regno
) && (mode
== SImode
|| mode
== SFmode
))
4694 return "cstf%I2%U2 %3, %M2, %1, %e0";
4697 else if (ZERO_P (src
))
4699 machine_mode mode
= GET_MODE (dest
);
4706 return "cstb%I2%U2 %., %M2, %1, %e0";
4709 return "csth%I2%U2 %., %M2, %1, %e0";
4713 return "cst%I2%U2 %., %M2, %1, %e0";
4718 fatal_insn ("bad output_condmove_single operand", insn
);
4723 /* Emit the appropriate code to do a comparison, returning the register the
4724 comparison was done it. */
4727 frv_emit_comparison (enum rtx_code test
, rtx op0
, rtx op1
)
4729 machine_mode cc_mode
;
4732 /* Floating point doesn't have comparison against a constant. */
4733 if (GET_MODE (op0
) == CC_FPmode
&& GET_CODE (op1
) != REG
)
4734 op1
= force_reg (GET_MODE (op0
), op1
);
4736 /* Possibly disable using anything but a fixed register in order to work
4737 around cse moving comparisons past function calls. */
4738 cc_mode
= SELECT_CC_MODE (test
, op0
, op1
);
4739 cc_reg
= ((TARGET_ALLOC_CC
)
4740 ? gen_reg_rtx (cc_mode
)
4741 : gen_rtx_REG (cc_mode
,
4742 (cc_mode
== CC_FPmode
) ? FCC_FIRST
: ICC_FIRST
));
4744 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
4745 gen_rtx_COMPARE (cc_mode
, op0
, op1
)));
4751 /* Emit code for a conditional branch.
4752 XXX: I originally wanted to add a clobber of a CCR register to use in
4753 conditional execution, but that confuses the rest of the compiler. */
4756 frv_emit_cond_branch (rtx operands
[])
4761 enum rtx_code test
= GET_CODE (operands
[0]);
4762 rtx cc_reg
= frv_emit_comparison (test
, operands
[1], operands
[2]);
4763 machine_mode cc_mode
= GET_MODE (cc_reg
);
4765 /* Branches generate:
4767 (if_then_else (<test>, <cc_reg>, (const_int 0))
4768 (label_ref <branch_label>)
4770 label_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
4771 test_rtx
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4772 if_else
= gen_rtx_IF_THEN_ELSE (cc_mode
, test_rtx
, label_ref
, pc_rtx
);
4773 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_else
));
4778 /* Emit code to set a gpr to 1/0 based on a comparison. */
4781 frv_emit_scc (rtx operands
[])
4787 enum rtx_code test
= GET_CODE (operands
[1]);
4788 rtx cc_reg
= frv_emit_comparison (test
, operands
[2], operands
[3]);
4790 /* SCC instructions generate:
4791 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4792 (clobber (<ccr_reg>))]) */
4793 test_rtx
= gen_rtx_fmt_ee (test
, SImode
, cc_reg
, const0_rtx
);
4794 set
= gen_rtx_SET (VOIDmode
, operands
[0], test_rtx
);
4796 cr_reg
= ((TARGET_ALLOC_CC
)
4797 ? gen_reg_rtx (CC_CCRmode
)
4798 : gen_rtx_REG (CC_CCRmode
,
4799 ((GET_MODE (cc_reg
) == CC_FPmode
)
4803 clobber
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4804 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
4809 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4810 the separate insns. */
4813 frv_split_scc (rtx dest
, rtx test
, rtx cc_reg
, rtx cr_reg
, HOST_WIDE_INT value
)
4819 /* Set the appropriate CCR bit. */
4820 emit_insn (gen_rtx_SET (VOIDmode
,
4822 gen_rtx_fmt_ee (GET_CODE (test
),
4827 /* Move the value into the destination. */
4828 emit_move_insn (dest
, GEN_INT (value
));
4830 /* Move 0 into the destination if the test failed */
4831 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4832 gen_rtx_EQ (GET_MODE (cr_reg
),
4835 gen_rtx_SET (VOIDmode
, dest
, const0_rtx
)));
4837 /* Finish up, return sequence. */
4844 /* Emit the code for a conditional move, return TRUE if we could do the
4848 frv_emit_cond_move (rtx dest
, rtx test_rtx
, rtx src1
, rtx src2
)
4855 enum rtx_code test
= GET_CODE (test_rtx
);
4856 rtx cc_reg
= frv_emit_comparison (test
,
4857 XEXP (test_rtx
, 0), XEXP (test_rtx
, 1));
4858 machine_mode cc_mode
= GET_MODE (cc_reg
);
4860 /* Conditional move instructions generate:
4861 (parallel [(set <target>
4862 (if_then_else (<test> <cc_reg> (const_int 0))
4865 (clobber (<ccr_reg>))]) */
4867 /* Handle various cases of conditional move involving two constants. */
4868 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4870 HOST_WIDE_INT value1
= INTVAL (src1
);
4871 HOST_WIDE_INT value2
= INTVAL (src2
);
4873 /* Having 0 as one of the constants can be done by loading the other
4874 constant, and optionally moving in gr0. */
4875 if (value1
== 0 || value2
== 0)
4878 /* If the first value is within an addi range and also the difference
4879 between the two fits in an addi's range, load up the difference, then
4880 conditionally move in 0, and then unconditionally add the first
4882 else if (IN_RANGE (value1
, -2048, 2047)
4883 && IN_RANGE (value2
- value1
, -2048, 2047))
4886 /* If neither condition holds, just force the constant into a
4890 src1
= force_reg (GET_MODE (dest
), src1
);
4891 src2
= force_reg (GET_MODE (dest
), src2
);
4895 /* If one value is a register, insure the other value is either 0 or a
4899 if (GET_CODE (src1
) == CONST_INT
&& INTVAL (src1
) != 0)
4900 src1
= force_reg (GET_MODE (dest
), src1
);
4902 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
4903 src2
= force_reg (GET_MODE (dest
), src2
);
4906 test2
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4907 if_rtx
= gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), test2
, src1
, src2
);
4909 set
= gen_rtx_SET (VOIDmode
, dest
, if_rtx
);
4911 cr_reg
= ((TARGET_ALLOC_CC
)
4912 ? gen_reg_rtx (CC_CCRmode
)
4913 : gen_rtx_REG (CC_CCRmode
,
4914 (cc_mode
== CC_FPmode
) ? FCR_FIRST
: ICR_FIRST
));
4916 clobber_cc
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4917 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber_cc
)));
4922 /* Split a conditional move into constituent parts, returning a SEQUENCE
4923 containing all of the insns. */
4926 frv_split_cond_move (rtx operands
[])
4928 rtx dest
= operands
[0];
4929 rtx test
= operands
[1];
4930 rtx cc_reg
= operands
[2];
4931 rtx src1
= operands
[3];
4932 rtx src2
= operands
[4];
4933 rtx cr_reg
= operands
[5];
4935 machine_mode cr_mode
= GET_MODE (cr_reg
);
4939 /* Set the appropriate CCR bit. */
4940 emit_insn (gen_rtx_SET (VOIDmode
,
4942 gen_rtx_fmt_ee (GET_CODE (test
),
4947 /* Handle various cases of conditional move involving two constants. */
4948 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4950 HOST_WIDE_INT value1
= INTVAL (src1
);
4951 HOST_WIDE_INT value2
= INTVAL (src2
);
4953 /* Having 0 as one of the constants can be done by loading the other
4954 constant, and optionally moving in gr0. */
4957 emit_move_insn (dest
, src2
);
4958 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4959 gen_rtx_NE (cr_mode
, cr_reg
,
4961 gen_rtx_SET (VOIDmode
, dest
, src1
)));
4964 else if (value2
== 0)
4966 emit_move_insn (dest
, src1
);
4967 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4968 gen_rtx_EQ (cr_mode
, cr_reg
,
4970 gen_rtx_SET (VOIDmode
, dest
, src2
)));
4973 /* If the first value is within an addi range and also the difference
4974 between the two fits in an addi's range, load up the difference, then
4975 conditionally move in 0, and then unconditionally add the first
4977 else if (IN_RANGE (value1
, -2048, 2047)
4978 && IN_RANGE (value2
- value1
, -2048, 2047))
4980 rtx dest_si
= ((GET_MODE (dest
) == SImode
)
4982 : gen_rtx_SUBREG (SImode
, dest
, 0));
4984 emit_move_insn (dest_si
, GEN_INT (value2
- value1
));
4985 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4986 gen_rtx_NE (cr_mode
, cr_reg
,
4988 gen_rtx_SET (VOIDmode
, dest_si
,
4990 emit_insn (gen_addsi3 (dest_si
, dest_si
, src1
));
4998 /* Emit the conditional move for the test being true if needed. */
4999 if (! rtx_equal_p (dest
, src1
))
5000 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5001 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5002 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5004 /* Emit the conditional move for the test being false if needed. */
5005 if (! rtx_equal_p (dest
, src2
))
5006 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5007 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
5008 gen_rtx_SET (VOIDmode
, dest
, src2
)));
5011 /* Finish up, return sequence. */
5018 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5019 memory location that is not known to be dword-aligned. */
5021 frv_split_double_load (rtx dest
, rtx source
)
5023 int regno
= REGNO (dest
);
5024 rtx dest1
= gen_highpart (SImode
, dest
);
5025 rtx dest2
= gen_lowpart (SImode
, dest
);
5026 rtx address
= XEXP (source
, 0);
5028 /* If the address is pre-modified, load the lower-numbered register
5029 first, then load the other register using an integer offset from
5030 the modified base register. This order should always be safe,
5031 since the pre-modification cannot affect the same registers as the
5034 The situation for other loads is more complicated. Loading one
5035 of the registers could affect the value of ADDRESS, so we must
5036 be careful which order we do them in. */
5037 if (GET_CODE (address
) == PRE_MODIFY
5038 || ! refers_to_regno_p (regno
, regno
+ 1, address
, NULL
))
5040 /* It is safe to load the lower-numbered register first. */
5041 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5042 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5046 /* ADDRESS is not pre-modified and the address depends on the
5047 lower-numbered register. Load the higher-numbered register
5049 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5050 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5054 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5055 and SOURCE is either a double register or the constant zero. */
5057 frv_split_double_store (rtx dest
, rtx source
)
5059 rtx dest1
= change_address (dest
, SImode
, NULL
);
5060 rtx dest2
= frv_index_memory (dest
, SImode
, 1);
5061 if (ZERO_P (source
))
5063 emit_move_insn (dest1
, CONST0_RTX (SImode
));
5064 emit_move_insn (dest2
, CONST0_RTX (SImode
));
5068 emit_move_insn (dest1
, gen_highpart (SImode
, source
));
5069 emit_move_insn (dest2
, gen_lowpart (SImode
, source
));
5074 /* Split a min/max operation returning a SEQUENCE containing all of the
5078 frv_split_minmax (rtx operands
[])
5080 rtx dest
= operands
[0];
5081 rtx minmax
= operands
[1];
5082 rtx src1
= operands
[2];
5083 rtx src2
= operands
[3];
5084 rtx cc_reg
= operands
[4];
5085 rtx cr_reg
= operands
[5];
5087 enum rtx_code test_code
;
5088 machine_mode cr_mode
= GET_MODE (cr_reg
);
5092 /* Figure out which test to use. */
5093 switch (GET_CODE (minmax
))
5098 case SMIN
: test_code
= LT
; break;
5099 case SMAX
: test_code
= GT
; break;
5100 case UMIN
: test_code
= LTU
; break;
5101 case UMAX
: test_code
= GTU
; break;
5104 /* Issue the compare instruction. */
5105 emit_insn (gen_rtx_SET (VOIDmode
,
5107 gen_rtx_COMPARE (GET_MODE (cc_reg
),
5110 /* Set the appropriate CCR bit. */
5111 emit_insn (gen_rtx_SET (VOIDmode
,
5113 gen_rtx_fmt_ee (test_code
,
5118 /* If are taking the min/max of a nonzero constant, load that first, and
5119 then do a conditional move of the other value. */
5120 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
5122 gcc_assert (!rtx_equal_p (dest
, src1
));
5124 emit_move_insn (dest
, src2
);
5125 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5126 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5127 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5130 /* Otherwise, do each half of the move. */
5133 /* Emit the conditional move for the test being true if needed. */
5134 if (! rtx_equal_p (dest
, src1
))
5135 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5136 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5137 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5139 /* Emit the conditional move for the test being false if needed. */
5140 if (! rtx_equal_p (dest
, src2
))
5141 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5142 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
5143 gen_rtx_SET (VOIDmode
, dest
, src2
)));
5146 /* Finish up, return sequence. */
5153 /* Split an integer abs operation returning a SEQUENCE containing all of the
5157 frv_split_abs (rtx operands
[])
5159 rtx dest
= operands
[0];
5160 rtx src
= operands
[1];
5161 rtx cc_reg
= operands
[2];
5162 rtx cr_reg
= operands
[3];
5167 /* Issue the compare < 0 instruction. */
5168 emit_insn (gen_rtx_SET (VOIDmode
,
5170 gen_rtx_COMPARE (CCmode
, src
, const0_rtx
)));
5172 /* Set the appropriate CCR bit. */
5173 emit_insn (gen_rtx_SET (VOIDmode
,
5175 gen_rtx_fmt_ee (LT
, CC_CCRmode
, cc_reg
, const0_rtx
)));
5177 /* Emit the conditional negate if the value is negative. */
5178 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5179 gen_rtx_NE (CC_CCRmode
, cr_reg
, const0_rtx
),
5180 gen_negsi2 (dest
, src
)));
5182 /* Emit the conditional move for the test being false if needed. */
5183 if (! rtx_equal_p (dest
, src
))
5184 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5185 gen_rtx_EQ (CC_CCRmode
, cr_reg
, const0_rtx
),
5186 gen_rtx_SET (VOIDmode
, dest
, src
)));
5188 /* Finish up, return sequence. */
5195 /* Initialize machine-specific if-conversion data.
5196 On the FR-V, we don't have any extra fields per se, but it is useful hook to
5197 initialize the static storage. */
5199 frv_ifcvt_machdep_init (void *ce_info ATTRIBUTE_UNUSED
)
5201 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5202 frv_ifcvt
.cur_scratch_regs
= 0;
5203 frv_ifcvt
.num_nested_cond_exec
= 0;
5204 frv_ifcvt
.cr_reg
= NULL_RTX
;
5205 frv_ifcvt
.nested_cc_reg
= NULL_RTX
;
5206 frv_ifcvt
.extra_int_cr
= NULL_RTX
;
5207 frv_ifcvt
.extra_fp_cr
= NULL_RTX
;
5208 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5212 /* Internal function to add a potential insn to the list of insns to be inserted
5213 if the conditional execution conversion is successful. */
5216 frv_ifcvt_add_insn (rtx pattern
, rtx insn
, int before_p
)
5218 rtx link
= alloc_EXPR_LIST (VOIDmode
, pattern
, insn
);
5220 link
->jump
= before_p
; /* Mark to add this before or after insn. */
5221 frv_ifcvt
.added_insns_list
= alloc_EXPR_LIST (VOIDmode
, link
,
5222 frv_ifcvt
.added_insns_list
);
5224 if (TARGET_DEBUG_COND_EXEC
)
5227 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5228 (before_p
) ? "before" : "after",
5229 (int)INSN_UID (insn
));
5231 debug_rtx (pattern
);
5236 /* A C expression to modify the code described by the conditional if
5237 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5238 FALSE_EXPR for converting if-then and if-then-else code to conditional
5239 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5240 tests cannot be converted. */
5243 frv_ifcvt_modify_tests (ce_if_block
*ce_info
, rtx
*p_true
, rtx
*p_false
)
5245 basic_block test_bb
= ce_info
->test_bb
; /* test basic block */
5246 basic_block then_bb
= ce_info
->then_bb
; /* THEN */
5247 basic_block else_bb
= ce_info
->else_bb
; /* ELSE or NULL */
5248 basic_block join_bb
= ce_info
->join_bb
; /* join block or NULL */
5249 rtx true_expr
= *p_true
;
5253 machine_mode mode
= GET_MODE (true_expr
);
5257 frv_tmp_reg_t
*tmp_reg
= &frv_ifcvt
.tmp_reg
;
5259 rtx sub_cond_exec_reg
;
5261 enum rtx_code code_true
;
5262 enum rtx_code code_false
;
5263 enum reg_class cc_class
;
5264 enum reg_class cr_class
;
5267 reg_set_iterator rsi
;
5269 /* Make sure we are only dealing with hard registers. Also honor the
5270 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5272 if (!reload_completed
|| !TARGET_COND_EXEC
5273 || (!TARGET_NESTED_CE
&& ce_info
->pass
> 1))
5276 /* Figure out which registers we can allocate for our own purposes. Only
5277 consider registers that are not preserved across function calls and are
5278 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5279 if we did not need to use them in reloading other registers. */
5280 memset (&tmp_reg
->regs
, 0, sizeof (tmp_reg
->regs
));
5281 COPY_HARD_REG_SET (tmp_reg
->regs
, call_used_reg_set
);
5282 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, fixed_reg_set
);
5283 SET_HARD_REG_BIT (tmp_reg
->regs
, ICC_TEMP
);
5284 SET_HARD_REG_BIT (tmp_reg
->regs
, ICR_TEMP
);
5286 /* If this is a nested IF, we need to discover whether the CC registers that
5287 are set/used inside of the block are used anywhere else. If not, we can
5288 change them to be the CC register that is paired with the CR register that
5289 controls the outermost IF block. */
5290 if (ce_info
->pass
> 1)
5292 CLEAR_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
);
5293 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5294 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5296 if (REGNO_REG_SET_P (df_get_live_in (then_bb
), j
))
5300 && REGNO_REG_SET_P (df_get_live_in (else_bb
), j
))
5304 && REGNO_REG_SET_P (df_get_live_in (join_bb
), j
))
5307 SET_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
);
5311 for (j
= 0; j
< frv_ifcvt
.cur_scratch_regs
; j
++)
5312 frv_ifcvt
.scratch_regs
[j
] = NULL_RTX
;
5314 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5315 frv_ifcvt
.cur_scratch_regs
= 0;
5317 bb
= (basic_block
*) alloca ((2 + ce_info
->num_multiple_test_blocks
)
5318 * sizeof (basic_block
));
5324 /* Remove anything live at the beginning of the join block from being
5325 available for allocation. */
5326 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb
), 0, regno
, rsi
)
5328 if (regno
< FIRST_PSEUDO_REGISTER
)
5329 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5333 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5335 if (ce_info
->num_multiple_test_blocks
)
5337 basic_block multiple_test_bb
= ce_info
->last_test_bb
;
5339 while (multiple_test_bb
!= test_bb
)
5341 bb
[num_bb
++] = multiple_test_bb
;
5342 multiple_test_bb
= EDGE_PRED (multiple_test_bb
, 0)->src
;
5346 /* Add in the THEN and ELSE blocks to be scanned. */
5347 bb
[num_bb
++] = then_bb
;
5349 bb
[num_bb
++] = else_bb
;
5351 sub_cond_exec_reg
= NULL_RTX
;
5352 frv_ifcvt
.num_nested_cond_exec
= 0;
5354 /* Scan all of the blocks for registers that must not be allocated. */
5355 for (j
= 0; j
< num_bb
; j
++)
5357 rtx_insn
*last_insn
= BB_END (bb
[j
]);
5358 rtx_insn
*insn
= BB_HEAD (bb
[j
]);
5362 fprintf (dump_file
, "Scanning %s block %d, start %d, end %d\n",
5363 (bb
[j
] == else_bb
) ? "else" : ((bb
[j
] == then_bb
) ? "then" : "test"),
5365 (int) INSN_UID (BB_HEAD (bb
[j
])),
5366 (int) INSN_UID (BB_END (bb
[j
])));
5368 /* Anything live at the beginning of the block is obviously unavailable
5370 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb
[j
]), 0, regno
, rsi
)
5372 if (regno
< FIRST_PSEUDO_REGISTER
)
5373 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5376 /* Loop through the insns in the block. */
5379 /* Mark any new registers that are created as being unavailable for
5380 allocation. Also see if the CC register used in nested IFs can be
5386 int skip_nested_if
= FALSE
;
5387 HARD_REG_SET mentioned_regs
;
5389 CLEAR_HARD_REG_SET (mentioned_regs
);
5390 find_all_hard_regs (PATTERN (insn
), &mentioned_regs
);
5391 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, mentioned_regs
);
5393 pattern
= PATTERN (insn
);
5394 if (GET_CODE (pattern
) == COND_EXEC
)
5396 rtx reg
= XEXP (COND_EXEC_TEST (pattern
), 0);
5398 if (reg
!= sub_cond_exec_reg
)
5400 sub_cond_exec_reg
= reg
;
5401 frv_ifcvt
.num_nested_cond_exec
++;
5405 set
= single_set_pattern (pattern
);
5408 rtx dest
= SET_DEST (set
);
5409 rtx src
= SET_SRC (set
);
5411 if (GET_CODE (dest
) == REG
)
5413 int regno
= REGNO (dest
);
5414 enum rtx_code src_code
= GET_CODE (src
);
5416 if (CC_P (regno
) && src_code
== COMPARE
)
5417 skip_nested_if
= TRUE
;
5419 else if (CR_P (regno
)
5420 && (src_code
== IF_THEN_ELSE
5421 || COMPARISON_P (src
)))
5422 skip_nested_if
= TRUE
;
5426 if (! skip_nested_if
)
5427 AND_COMPL_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
,
5431 if (insn
== last_insn
)
5434 insn
= NEXT_INSN (insn
);
5438 /* If this is a nested if, rewrite the CC registers that are available to
5439 include the ones that can be rewritten, to increase the chance of being
5440 able to allocate a paired CC/CR register combination. */
5441 if (ce_info
->pass
> 1)
5443 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5444 if (TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
))
5445 SET_HARD_REG_BIT (tmp_reg
->regs
, j
);
5447 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, j
);
5453 fprintf (dump_file
, "Available GPRs: ");
5455 for (j
= GPR_FIRST
; j
<= GPR_LAST
; j
++)
5456 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5458 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5459 if (++num_gprs
> GPR_TEMP_NUM
+2)
5463 fprintf (dump_file
, "%s\nAvailable CRs: ",
5464 (num_gprs
> GPR_TEMP_NUM
+2) ? " ..." : "");
5466 for (j
= CR_FIRST
; j
<= CR_LAST
; j
++)
5467 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5468 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5470 fputs ("\n", dump_file
);
5472 if (ce_info
->pass
> 1)
5474 fprintf (dump_file
, "Modifiable CCs: ");
5475 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5476 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5477 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5479 fprintf (dump_file
, "\n%d nested COND_EXEC statements\n",
5480 frv_ifcvt
.num_nested_cond_exec
);
5484 /* Allocate the appropriate temporary condition code register. Try to
5485 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5486 that conditional cmp's can be done. */
5487 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5489 cr_class
= ICR_REGS
;
5490 cc_class
= ICC_REGS
;
5491 cc_first
= ICC_FIRST
;
5494 else if (mode
== CC_FPmode
)
5496 cr_class
= FCR_REGS
;
5497 cc_class
= FCC_REGS
;
5498 cc_first
= FCC_FIRST
;
5503 cc_first
= cc_last
= 0;
5504 cr_class
= cc_class
= NO_REGS
;
5507 cc
= XEXP (true_expr
, 0);
5508 nested_cc
= cr
= NULL_RTX
;
5509 if (cc_class
!= NO_REGS
)
5511 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5512 so we can execute a csubcc/caddcc/cfcmps instruction. */
5515 for (cc_regno
= cc_first
; cc_regno
<= cc_last
; cc_regno
++)
5517 int cr_regno
= cc_regno
- CC_FIRST
+ CR_FIRST
;
5519 if (TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cc_regno
)
5520 && TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cr_regno
))
5522 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cr_class
] = cr_regno
;
5523 cr
= frv_alloc_temp_reg (tmp_reg
, cr_class
, CC_CCRmode
, TRUE
,
5526 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cc_class
] = cc_regno
;
5527 nested_cc
= frv_alloc_temp_reg (tmp_reg
, cc_class
, CCmode
,
5537 fprintf (dump_file
, "Could not allocate a CR temporary register\n");
5544 "Will use %s for conditional execution, %s for nested comparisons\n",
5545 reg_names
[ REGNO (cr
)],
5546 (nested_cc
) ? reg_names
[ REGNO (nested_cc
) ] : "<none>");
5548 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5549 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5550 bit being true. We don't do this for floating point, because of NaNs. */
5551 code
= GET_CODE (true_expr
);
5552 if (GET_MODE (cc
) != CC_FPmode
)
5554 code
= reverse_condition (code
);
5564 check_insn
= gen_rtx_SET (VOIDmode
, cr
,
5565 gen_rtx_fmt_ee (code
, CC_CCRmode
, cc
, const0_rtx
));
5567 /* Record the check insn to be inserted later. */
5568 frv_ifcvt_add_insn (check_insn
, BB_END (test_bb
), TRUE
);
5570 /* Update the tests. */
5571 frv_ifcvt
.cr_reg
= cr
;
5572 frv_ifcvt
.nested_cc_reg
= nested_cc
;
5573 *p_true
= gen_rtx_fmt_ee (code_true
, CC_CCRmode
, cr
, const0_rtx
);
5574 *p_false
= gen_rtx_fmt_ee (code_false
, CC_CCRmode
, cr
, const0_rtx
);
5577 /* Fail, don't do this conditional execution. */
5580 *p_false
= NULL_RTX
;
5582 fprintf (dump_file
, "Disabling this conditional execution.\n");
5588 /* A C expression to modify the code described by the conditional if
5589 information CE_INFO, for the basic block BB, possibly updating the tests in
5590 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5591 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5592 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5594 /* p_true and p_false are given expressions of the form:
5596 (and (eq:CC_CCR (reg:CC_CCR)
5602 frv_ifcvt_modify_multiple_tests (ce_if_block
*ce_info
,
5607 rtx old_true
= XEXP (*p_true
, 0);
5608 rtx old_false
= XEXP (*p_false
, 0);
5609 rtx true_expr
= XEXP (*p_true
, 1);
5610 rtx false_expr
= XEXP (*p_false
, 1);
5613 rtx cr
= XEXP (old_true
, 0);
5615 rtx new_cr
= NULL_RTX
;
5616 rtx
*p_new_cr
= (rtx
*)0;
5620 enum reg_class cr_class
;
5621 machine_mode mode
= GET_MODE (true_expr
);
5622 rtx (*logical_func
)(rtx
, rtx
, rtx
);
5624 if (TARGET_DEBUG_COND_EXEC
)
5627 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5628 ce_info
->and_and_p
? "&&" : "||");
5630 debug_rtx (*p_true
);
5632 fputs ("\nfalse insn:\n", stderr
);
5633 debug_rtx (*p_false
);
5636 if (!TARGET_MULTI_CE
)
5639 if (GET_CODE (cr
) != REG
)
5642 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5644 cr_class
= ICR_REGS
;
5645 p_new_cr
= &frv_ifcvt
.extra_int_cr
;
5647 else if (mode
== CC_FPmode
)
5649 cr_class
= FCR_REGS
;
5650 p_new_cr
= &frv_ifcvt
.extra_fp_cr
;
5655 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5656 more &&/|| tests. */
5660 new_cr
= *p_new_cr
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, cr_class
,
5661 CC_CCRmode
, TRUE
, TRUE
);
5666 if (ce_info
->and_and_p
)
5668 old_test
= old_false
;
5669 test_expr
= true_expr
;
5670 logical_func
= (GET_CODE (old_true
) == EQ
) ? gen_andcr
: gen_andncr
;
5671 *p_true
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5672 *p_false
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5676 old_test
= old_false
;
5677 test_expr
= false_expr
;
5678 logical_func
= (GET_CODE (old_false
) == EQ
) ? gen_orcr
: gen_orncr
;
5679 *p_true
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5680 *p_false
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5683 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5684 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5686 frv_ifcvt_add_insn ((*logical_func
) (cr
, cr
, new_cr
), BB_END (bb
), TRUE
);
5688 /* Now add the conditional check insn. */
5689 cc
= XEXP (test_expr
, 0);
5690 compare
= gen_rtx_fmt_ee (GET_CODE (test_expr
), CC_CCRmode
, cc
, const0_rtx
);
5691 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, old_test
, compare
, const0_rtx
);
5693 check_insn
= gen_rtx_SET (VOIDmode
, new_cr
, if_else
);
5695 /* Add the new check insn to the list of check insns that need to be
5697 frv_ifcvt_add_insn (check_insn
, BB_END (bb
), TRUE
);
5699 if (TARGET_DEBUG_COND_EXEC
)
5701 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5704 debug_rtx (*p_true
);
5706 fputs ("\nfalse insn:\n", stderr
);
5707 debug_rtx (*p_false
);
5713 *p_true
= *p_false
= NULL_RTX
;
5715 /* If we allocated a CR register, release it. */
5718 CLEAR_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, REGNO (new_cr
));
5719 *p_new_cr
= NULL_RTX
;
5722 if (TARGET_DEBUG_COND_EXEC
)
5723 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr
);
5729 /* Return a register which will be loaded with a value if an IF block is
5730 converted to conditional execution. This is used to rewrite instructions
5731 that use constants to ones that just use registers. */
5734 frv_ifcvt_load_value (rtx value
, rtx insn ATTRIBUTE_UNUSED
)
5736 int num_alloc
= frv_ifcvt
.cur_scratch_regs
;
5740 /* We know gr0 == 0, so replace any errant uses. */
5741 if (value
== const0_rtx
)
5742 return gen_rtx_REG (SImode
, GPR_FIRST
);
5744 /* First search all registers currently loaded to see if we have an
5745 applicable constant. */
5746 if (CONSTANT_P (value
)
5747 || (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
))
5749 for (i
= 0; i
< num_alloc
; i
++)
5751 if (rtx_equal_p (SET_SRC (frv_ifcvt
.scratch_regs
[i
]), value
))
5752 return SET_DEST (frv_ifcvt
.scratch_regs
[i
]);
5756 /* Have we exhausted the number of registers available? */
5757 if (num_alloc
>= GPR_TEMP_NUM
)
5760 fprintf (dump_file
, "Too many temporary registers allocated\n");
5765 /* Allocate the new register. */
5766 reg
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, GPR_REGS
, SImode
, TRUE
, TRUE
);
5770 fputs ("Could not find a scratch register\n", dump_file
);
5775 frv_ifcvt
.cur_scratch_regs
++;
5776 frv_ifcvt
.scratch_regs
[num_alloc
] = gen_rtx_SET (VOIDmode
, reg
, value
);
5780 if (GET_CODE (value
) == CONST_INT
)
5781 fprintf (dump_file
, "Register %s will hold %ld\n",
5782 reg_names
[ REGNO (reg
)], (long)INTVAL (value
));
5784 else if (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
)
5785 fprintf (dump_file
, "Register %s will hold LR\n",
5786 reg_names
[ REGNO (reg
)]);
5789 fprintf (dump_file
, "Register %s will hold a saved value\n",
5790 reg_names
[ REGNO (reg
)]);
5797 /* Update a MEM used in conditional code that might contain an offset to put
5798 the offset into a scratch register, so that the conditional load/store
5799 operations can be used. This function returns the original pointer if the
5800 MEM is valid to use in conditional code, NULL if we can't load up the offset
5801 into a temporary register, or the new MEM if we were successful. */
5804 frv_ifcvt_rewrite_mem (rtx mem
, machine_mode mode
, rtx insn
)
5806 rtx addr
= XEXP (mem
, 0);
5808 if (!frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
))
5810 if (GET_CODE (addr
) == PLUS
)
5812 rtx addr_op0
= XEXP (addr
, 0);
5813 rtx addr_op1
= XEXP (addr
, 1);
5815 if (GET_CODE (addr_op0
) == REG
&& CONSTANT_P (addr_op1
))
5817 rtx reg
= frv_ifcvt_load_value (addr_op1
, insn
);
5821 addr
= gen_rtx_PLUS (Pmode
, addr_op0
, reg
);
5828 else if (CONSTANT_P (addr
))
5829 addr
= frv_ifcvt_load_value (addr
, insn
);
5834 if (addr
== NULL_RTX
)
5837 else if (XEXP (mem
, 0) != addr
)
5838 return change_address (mem
, mode
, addr
);
5845 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5846 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5849 single_set_pattern (rtx pattern
)
5854 if (GET_CODE (pattern
) == COND_EXEC
)
5855 pattern
= COND_EXEC_CODE (pattern
);
5857 if (GET_CODE (pattern
) == SET
)
5860 else if (GET_CODE (pattern
) == PARALLEL
)
5862 for (i
= 0, set
= 0; i
< XVECLEN (pattern
, 0); i
++)
5864 rtx sub
= XVECEXP (pattern
, 0, i
);
5866 switch (GET_CODE (sub
))
5890 /* A C expression to modify the code described by the conditional if
5891 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5892 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5893 insn cannot be converted to be executed conditionally. */
5896 frv_ifcvt_modify_insn (ce_if_block
*ce_info
,
5900 rtx orig_ce_pattern
= pattern
;
5906 gcc_assert (GET_CODE (pattern
) == COND_EXEC
);
5908 test
= COND_EXEC_TEST (pattern
);
5909 if (GET_CODE (test
) == AND
)
5911 rtx cr
= frv_ifcvt
.cr_reg
;
5914 op0
= XEXP (test
, 0);
5915 if (! rtx_equal_p (cr
, XEXP (op0
, 0)))
5918 op1
= XEXP (test
, 1);
5919 test_reg
= XEXP (op1
, 0);
5920 if (GET_CODE (test_reg
) != REG
)
5923 /* Is this the first nested if block in this sequence? If so, generate
5924 an andcr or andncr. */
5925 if (! frv_ifcvt
.last_nested_if_cr
)
5929 frv_ifcvt
.last_nested_if_cr
= test_reg
;
5930 if (GET_CODE (op0
) == NE
)
5931 and_op
= gen_andcr (test_reg
, cr
, test_reg
);
5933 and_op
= gen_andncr (test_reg
, cr
, test_reg
);
5935 frv_ifcvt_add_insn (and_op
, insn
, TRUE
);
5938 /* If this isn't the first statement in the nested if sequence, see if we
5939 are dealing with the same register. */
5940 else if (! rtx_equal_p (test_reg
, frv_ifcvt
.last_nested_if_cr
))
5943 COND_EXEC_TEST (pattern
) = test
= op1
;
5946 /* If this isn't a nested if, reset state variables. */
5949 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5952 set
= single_set_pattern (pattern
);
5955 rtx dest
= SET_DEST (set
);
5956 rtx src
= SET_SRC (set
);
5957 machine_mode mode
= GET_MODE (dest
);
5959 /* Check for normal binary operators. */
5960 if (mode
== SImode
&& ARITHMETIC_P (src
))
5962 op0
= XEXP (src
, 0);
5963 op1
= XEXP (src
, 1);
5965 if (integer_register_operand (op0
, SImode
) && CONSTANT_P (op1
))
5967 op1
= frv_ifcvt_load_value (op1
, insn
);
5969 COND_EXEC_CODE (pattern
)
5970 = gen_rtx_SET (VOIDmode
, dest
, gen_rtx_fmt_ee (GET_CODE (src
),
5978 /* For multiply by a constant, we need to handle the sign extending
5979 correctly. Add a USE of the value after the multiply to prevent flow
5980 from cratering because only one register out of the two were used. */
5981 else if (mode
== DImode
&& GET_CODE (src
) == MULT
)
5983 op0
= XEXP (src
, 0);
5984 op1
= XEXP (src
, 1);
5985 if (GET_CODE (op0
) == SIGN_EXTEND
&& GET_CODE (op1
) == CONST_INT
)
5987 op1
= frv_ifcvt_load_value (op1
, insn
);
5990 op1
= gen_rtx_SIGN_EXTEND (DImode
, op1
);
5991 COND_EXEC_CODE (pattern
)
5992 = gen_rtx_SET (VOIDmode
, dest
,
5993 gen_rtx_MULT (DImode
, op0
, op1
));
5999 frv_ifcvt_add_insn (gen_use (dest
), insn
, FALSE
);
6002 /* If we are just loading a constant created for a nested conditional
6003 execution statement, just load the constant without any conditional
6004 execution, since we know that the constant will not interfere with any
6006 else if (frv_ifcvt
.scratch_insns_bitmap
6007 && bitmap_bit_p (frv_ifcvt
.scratch_insns_bitmap
,
6009 && REG_P (SET_DEST (set
))
6010 /* We must not unconditionally set a scratch reg chosen
6011 for a nested if-converted block if its incoming
6012 value from the TEST block (or the result of the THEN
6013 branch) could/should propagate to the JOIN block.
6014 It suffices to test whether the register is live at
6015 the JOIN point: if it's live there, we can infer
6016 that we set it in the former JOIN block of the
6017 nested if-converted block (otherwise it wouldn't
6018 have been available as a scratch register), and it
6019 is either propagated through or set in the other
6020 conditional block. It's probably not worth trying
6021 to catch the latter case, and it could actually
6022 limit scheduling of the combined block quite
6025 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->join_bb
),
6026 REGNO (SET_DEST (set
))))
6027 /* Similarly, we must not unconditionally set a reg
6028 used as scratch in the THEN branch if the same reg
6029 is live in the ELSE branch. */
6030 && (! ce_info
->else_bb
6031 || BLOCK_FOR_INSN (insn
) == ce_info
->else_bb
6032 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->else_bb
),
6033 REGNO (SET_DEST (set
))))))
6036 else if (mode
== QImode
|| mode
== HImode
|| mode
== SImode
6039 int changed_p
= FALSE
;
6041 /* Check for just loading up a constant */
6042 if (CONSTANT_P (src
) && integer_register_operand (dest
, mode
))
6044 src
= frv_ifcvt_load_value (src
, insn
);
6051 /* See if we need to fix up stores */
6052 if (GET_CODE (dest
) == MEM
)
6054 rtx new_mem
= frv_ifcvt_rewrite_mem (dest
, mode
, insn
);
6059 else if (new_mem
!= dest
)
6066 /* See if we need to fix up loads */
6067 if (GET_CODE (src
) == MEM
)
6069 rtx new_mem
= frv_ifcvt_rewrite_mem (src
, mode
, insn
);
6074 else if (new_mem
!= src
)
6081 /* If either src or destination changed, redo SET. */
6083 COND_EXEC_CODE (pattern
) = gen_rtx_SET (VOIDmode
, dest
, src
);
6086 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6087 rewriting the CC register to be the same as the paired CC/CR register
6089 else if (mode
== CC_CCRmode
&& COMPARISON_P (src
))
6091 int regno
= REGNO (XEXP (src
, 0));
6094 if (ce_info
->pass
> 1
6095 && regno
!= (int)REGNO (frv_ifcvt
.nested_cc_reg
)
6096 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, regno
))
6098 src
= gen_rtx_fmt_ee (GET_CODE (src
),
6100 frv_ifcvt
.nested_cc_reg
,
6104 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, test
, src
, const0_rtx
);
6105 pattern
= gen_rtx_SET (VOIDmode
, dest
, if_else
);
6108 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6109 else if (ce_info
->pass
> 1
6110 && GET_CODE (dest
) == REG
6111 && CC_P (REGNO (dest
))
6112 && REGNO (dest
) != REGNO (frv_ifcvt
.nested_cc_reg
)
6113 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
,
6115 && GET_CODE (src
) == COMPARE
)
6117 PUT_MODE (frv_ifcvt
.nested_cc_reg
, GET_MODE (dest
));
6118 COND_EXEC_CODE (pattern
)
6119 = gen_rtx_SET (VOIDmode
, frv_ifcvt
.nested_cc_reg
, copy_rtx (src
));
6123 if (TARGET_DEBUG_COND_EXEC
)
6125 rtx orig_pattern
= PATTERN (insn
);
6127 PATTERN (insn
) = pattern
;
6129 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6133 PATTERN (insn
) = orig_pattern
;
6139 if (TARGET_DEBUG_COND_EXEC
)
6141 rtx orig_pattern
= PATTERN (insn
);
6143 PATTERN (insn
) = orig_ce_pattern
;
6145 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6149 PATTERN (insn
) = orig_pattern
;
6156 /* A C expression to perform any final machine dependent modifications in
6157 converting code to conditional execution in the code described by the
6158 conditional if information CE_INFO. */
6161 frv_ifcvt_modify_final (ce_if_block
*ce_info ATTRIBUTE_UNUSED
)
6165 rtx p
= frv_ifcvt
.added_insns_list
;
6168 /* Loop inserting the check insns. The last check insn is the first test,
6169 and is the appropriate place to insert constants. */
6174 rtx check_and_insert_insns
= XEXP (p
, 0);
6177 check_insn
= XEXP (check_and_insert_insns
, 0);
6178 existing_insn
= XEXP (check_and_insert_insns
, 1);
6181 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6182 the existing insn, otherwise it is to be inserted AFTER. */
6183 if (check_and_insert_insns
->jump
)
6185 emit_insn_before (check_insn
, existing_insn
);
6186 check_and_insert_insns
->jump
= 0;
6189 emit_insn_after (check_insn
, existing_insn
);
6191 free_EXPR_LIST_node (check_and_insert_insns
);
6192 free_EXPR_LIST_node (old_p
);
6194 while (p
!= NULL_RTX
);
6196 /* Load up any constants needed into temp gprs */
6197 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6199 rtx insn
= emit_insn_before (frv_ifcvt
.scratch_regs
[i
], existing_insn
);
6200 if (! frv_ifcvt
.scratch_insns_bitmap
)
6201 frv_ifcvt
.scratch_insns_bitmap
= BITMAP_ALLOC (NULL
);
6202 bitmap_set_bit (frv_ifcvt
.scratch_insns_bitmap
, INSN_UID (insn
));
6203 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6206 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6207 frv_ifcvt
.cur_scratch_regs
= 0;
6211 /* A C expression to cancel any machine dependent modifications in converting
6212 code to conditional execution in the code described by the conditional if
6213 information CE_INFO. */
6216 frv_ifcvt_modify_cancel (ce_if_block
*ce_info ATTRIBUTE_UNUSED
)
6219 rtx p
= frv_ifcvt
.added_insns_list
;
6221 /* Loop freeing up the EXPR_LIST's allocated. */
6222 while (p
!= NULL_RTX
)
6224 rtx check_and_jump
= XEXP (p
, 0);
6228 free_EXPR_LIST_node (check_and_jump
);
6229 free_EXPR_LIST_node (old_p
);
6232 /* Release any temporary gprs allocated. */
6233 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6234 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6236 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6237 frv_ifcvt
.cur_scratch_regs
= 0;
6241 /* A C expression for the size in bytes of the trampoline, as an integer.
6245 setlo #0, <static_chain>
6247 sethi #0, <static_chain>
6248 jmpl @(gr0,<jmp_reg>) */
6251 frv_trampoline_size (void)
6254 /* Allocate room for the function descriptor and the lddi
6257 return 5 /* instructions */ * 4 /* instruction size. */;
6261 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6262 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6263 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6264 should be passed to the function when it is called.
6269 setlo #0, <static_chain>
6271 sethi #0, <static_chain>
6272 jmpl @(gr0,<jmp_reg>) */
6275 frv_trampoline_init (rtx m_tramp
, tree fndecl
, rtx static_chain
)
6277 rtx addr
= XEXP (m_tramp
, 0);
6278 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6279 rtx sc_reg
= force_reg (Pmode
, static_chain
);
6281 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
6282 LCT_NORMAL
, VOIDmode
, 4,
6284 GEN_INT (frv_trampoline_size ()), SImode
,
6290 /* Many machines have some registers that cannot be copied directly to or from
6291 memory or even from other types of registers. An example is the `MQ'
6292 register, which on most machines, can only be copied to or from general
6293 registers, but not memory. Some machines allow copying all registers to and
6294 from memory, but require a scratch register for stores to some memory
6295 locations (e.g., those with symbolic address on the RT, and those with
6296 certain symbolic address on the SPARC when compiling PIC). In some cases,
6297 both an intermediate and a scratch register are required.
6299 You should define these macros to indicate to the reload phase that it may
6300 need to allocate at least one register for a reload in addition to the
6301 register to contain the data. Specifically, if copying X to a register
6302 RCLASS in MODE requires an intermediate register, you should define
6303 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6304 whose registers can be used as intermediate registers or scratch registers.
6306 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6307 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6308 largest register class required. If the requirements for input and output
6309 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6310 instead of defining both macros identically.
6312 The values returned by these macros are often `GENERAL_REGS'. Return
6313 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6314 to or from a register of RCLASS in MODE without requiring a scratch register.
6315 Do not define this macro if it would always return `NO_REGS'.
6317 If a scratch register is required (either with or without an intermediate
6318 register), you should define patterns for `reload_inM' or `reload_outM', as
6319 required.. These patterns, which will normally be implemented with a
6320 `define_expand', should be similar to the `movM' patterns, except that
6321 operand 2 is the scratch register.
6323 Define constraints for the reload register and scratch register that contain
6324 a single register class. If the original reload register (whose class is
6325 RCLASS) can meet the constraint given in the pattern, the value returned by
6326 these macros is used for the class of the scratch register. Otherwise, two
6327 additional reload registers are required. Their classes are obtained from
6328 the constraints in the insn pattern.
6330 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6331 either be in a hard register or in memory. Use `true_regnum' to find out;
6332 it will return -1 if the pseudo is in memory and the hard register number if
6333 it is in a register.
6335 These macros should not be used in the case where a particular class of
6336 registers can only be copied to memory and not to another class of
6337 registers. In that case, secondary reload registers are not needed and
6338 would not be helpful. Instead, a stack location must be used to perform the
6339 copy and the `movM' pattern should use memory as an intermediate storage.
6340 This case often occurs between floating-point and general registers. */
6343 frv_secondary_reload_class (enum reg_class rclass
,
6344 machine_mode mode ATTRIBUTE_UNUSED
,
6355 /* Accumulators/Accumulator guard registers need to go through floating
6360 if (x
&& GET_CODE (x
) == REG
)
6362 int regno
= REGNO (x
);
6364 if (ACC_P (regno
) || ACCG_P (regno
))
6369 /* Nonzero constants should be loaded into an FPR through a GPR. */
6371 if (x
&& CONSTANT_P (x
) && !ZERO_P (x
))
6377 /* All of these types need gpr registers. */
6389 /* The accumulators need fpr registers. */
6399 /* This hook exists to catch the case where secondary_reload_class() is
6400 called from init_reg_autoinc() in regclass.c - before the reload optabs
6401 have been initialised. */
6404 frv_secondary_reload (bool in_p
, rtx x
, reg_class_t reload_class_i
,
6405 machine_mode reload_mode
,
6406 secondary_reload_info
* sri
)
6408 enum reg_class rclass
= NO_REGS
;
6409 enum reg_class reload_class
= (enum reg_class
) reload_class_i
;
6411 if (sri
->prev_sri
&& sri
->prev_sri
->t_icode
!= CODE_FOR_nothing
)
6413 sri
->icode
= sri
->prev_sri
->t_icode
;
6417 rclass
= frv_secondary_reload_class (reload_class
, reload_mode
, x
);
6419 if (rclass
!= NO_REGS
)
6421 enum insn_code icode
6422 = direct_optab_handler (in_p
? reload_in_optab
: reload_out_optab
,
6426 /* This happens when then the reload_[in|out]_optabs have
6427 not been initialised. */
6428 sri
->t_icode
= CODE_FOR_nothing
;
6433 /* Fall back to the default secondary reload handler. */
6434 return default_secondary_reload (in_p
, x
, reload_class
, reload_mode
, sri
);
6438 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6441 frv_class_likely_spilled_p (reg_class_t rclass
)
6451 case FDPIC_FPTR_REGS
:
6471 /* An expression for the alignment of a structure field FIELD if the
6472 alignment computed in the usual way is COMPUTED. GCC uses this
6473 value instead of the value in `BIGGEST_ALIGNMENT' or
6474 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6476 /* The definition type of the bit field data is either char, short, long or
6477 long long. The maximum bit size is the number of bits of its own type.
6479 The bit field data is assigned to a storage unit that has an adequate size
6480 for bit field data retention and is located at the smallest address.
6482 Consecutive bit field data are packed at consecutive bits having the same
6483 storage unit, with regard to the type, beginning with the MSB and continuing
6486 If a field to be assigned lies over a bit field type boundary, its
6487 assignment is completed by aligning it with a boundary suitable for the
6490 When a bit field having a bit length of 0 is declared, it is forcibly
6491 assigned to the next storage unit.
6504 &x 00000000 00000000 00000000 00000000
6507 &x+4 00000000 00000000 00000000 00000000
6510 &x+8 00000000 00000000 00000000 00000000
6513 &x+12 00000000 00000000 00000000 00000000
6519 frv_adjust_field_align (tree field
, int computed
)
6521 /* Make sure that the bitfield is not wider than the type. */
6522 if (DECL_BIT_FIELD (field
)
6523 && !DECL_ARTIFICIAL (field
))
6525 tree parent
= DECL_CONTEXT (field
);
6526 tree prev
= NULL_TREE
;
6529 for (cur
= TYPE_FIELDS (parent
); cur
&& cur
!= field
; cur
= DECL_CHAIN (cur
))
6531 if (TREE_CODE (cur
) != FIELD_DECL
)
6539 /* If this isn't a :0 field and if the previous element is a bitfield
6540 also, see if the type is different, if so, we will need to align the
6541 bit-field to the next boundary. */
6543 && ! DECL_PACKED (field
)
6544 && ! integer_zerop (DECL_SIZE (field
))
6545 && DECL_BIT_FIELD_TYPE (field
) != DECL_BIT_FIELD_TYPE (prev
))
6547 int prev_align
= TYPE_ALIGN (TREE_TYPE (prev
));
6548 int cur_align
= TYPE_ALIGN (TREE_TYPE (field
));
6549 computed
= (prev_align
> cur_align
) ? prev_align
: cur_align
;
6557 /* A C expression that is nonzero if it is permissible to store a value of mode
6558 MODE in hard register number REGNO (or in several registers starting with
6559 that one). For a machine where all registers are equivalent, a suitable
6562 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6564 It is not necessary for this macro to check for the numbers of fixed
6565 registers, because the allocation mechanism considers them to be always
6568 On some machines, double-precision values must be kept in even/odd register
6569 pairs. The way to implement that is to define this macro to reject odd
6570 register numbers for such modes.
6572 The minimum requirement for a mode to be OK in a register is that the
6573 `movMODE' instruction pattern support moves between the register and any
6574 other hard register for which the mode is OK; and that moving a value into
6575 the register and back out not alter it.
6577 Since the same instruction used to move `SImode' will work for all narrower
6578 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6579 to distinguish between these modes, provided you define patterns `movhi',
6580 etc., to take advantage of this. This is useful because of the interaction
6581 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6582 all integer modes to be tieable.
6584 Many machines have special registers for floating point arithmetic. Often
6585 people assume that floating point machine modes are allowed only in floating
6586 point registers. This is not true. Any registers that can hold integers
6587 can safely *hold* a floating point machine mode, whether or not floating
6588 arithmetic can be done on it in those registers. Integer move instructions
6589 can be used to move the values.
6591 On some machines, though, the converse is true: fixed-point machine modes
6592 may not go in floating registers. This is true if the floating registers
6593 normalize any value stored in them, because storing a non-floating value
6594 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6595 fixed-point machine modes in floating registers. But if the floating
6596 registers do not automatically normalize, if you can store any bit pattern
6597 in one and retrieve it unchanged without a trap, then any machine mode may
6598 go in a floating register, so you can define this macro to say so.
6600 The primary significance of special floating registers is rather that they
6601 are the registers acceptable in floating point arithmetic instructions.
6602 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6603 writing the proper constraints for those instructions.
6605 On some machines, the floating registers are especially slow to access, so
6606 that it is better to store a value in a stack frame than in such a register
6607 if floating point arithmetic is not being done. As long as the floating
6608 registers are not in class `GENERAL_REGS', they will not be used unless some
6609 pattern's constraint asks for one. */
6612 frv_hard_regno_mode_ok (int regno
, machine_mode mode
)
6622 return ICC_P (regno
) || GPR_P (regno
);
6625 return CR_P (regno
) || GPR_P (regno
);
6628 return FCC_P (regno
) || GPR_P (regno
);
6634 /* Set BASE to the first register in REGNO's class. Set MASK to the
6635 bits that must be clear in (REGNO - BASE) for the register to be
6637 if (INTEGRAL_MODE_P (mode
) || FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
6641 /* ACCGs store one byte. Two-byte quantities must start in
6642 even-numbered registers, four-byte ones in registers whose
6643 numbers are divisible by four, and so on. */
6645 mask
= GET_MODE_SIZE (mode
) - 1;
6649 /* The other registers store one word. */
6650 if (GPR_P (regno
) || regno
== AP_FIRST
)
6653 else if (FPR_P (regno
))
6656 else if (ACC_P (regno
))
6659 else if (SPR_P (regno
))
6660 return mode
== SImode
;
6662 /* Fill in the table. */
6666 /* Anything smaller than an SI is OK in any word-sized register. */
6667 if (GET_MODE_SIZE (mode
) < 4)
6670 mask
= (GET_MODE_SIZE (mode
) / 4) - 1;
6672 return (((regno
- base
) & mask
) == 0);
6679 /* A C expression for the number of consecutive hard registers, starting at
6680 register number REGNO, required to hold a value of mode MODE.
6682 On a machine where all registers are exactly one word, a suitable definition
6685 #define HARD_REGNO_NREGS(REGNO, MODE) \
6686 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6687 / UNITS_PER_WORD)) */
6689 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6690 that we can build the appropriate instructions to properly reload the
6691 values. Also, make the byte-sized accumulator guards use one guard
6695 frv_hard_regno_nregs (int regno
, machine_mode mode
)
6698 return GET_MODE_SIZE (mode
);
6700 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6704 /* A C expression for the maximum number of consecutive registers of
6705 class RCLASS needed to hold a value of mode MODE.
6707 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6708 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6709 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6711 This macro helps control the handling of multiple-word values in
6714 This declaration is required. */
6717 frv_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
6719 if (rclass
== ACCG_REGS
)
6720 /* An N-byte value requires N accumulator guards. */
6721 return GET_MODE_SIZE (mode
);
6723 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6727 /* A C expression that is nonzero if X is a legitimate constant for an
6728 immediate operand on the target machine. You can assume that X satisfies
6729 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6730 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6733 frv_legitimate_constant_p (machine_mode mode
, rtx x
)
6735 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6736 means that the move expanders will be expected to deal with most
6737 kinds of constant, regardless of what we return here.
6739 However, among its other duties, frv_legitimate_constant_p decides whether
6740 a constant can be entered into reg_equiv_constant[]. If we return true,
6741 reload can create new instances of the constant whenever it likes.
6743 The idea is therefore to accept as many constants as possible (to give
6744 reload more freedom) while rejecting constants that can only be created
6745 at certain times. In particular, anything with a symbolic component will
6746 require use of the pseudo FDPIC register, which is only available before
6749 return LEGITIMATE_PIC_OPERAND_P (x
);
6751 /* All of the integer constants are ok. */
6752 if (GET_CODE (x
) != CONST_DOUBLE
)
6755 /* double integer constants are ok. */
6756 if (GET_MODE (x
) == VOIDmode
|| mode
== DImode
)
6759 /* 0 is always ok. */
6760 if (x
== CONST0_RTX (mode
))
6763 /* If floating point is just emulated, allow any constant, since it will be
6764 constructed in the GPRs. */
6765 if (!TARGET_HAS_FPRS
)
6768 if (mode
== DFmode
&& !TARGET_DOUBLE
)
6771 /* Otherwise store the constant away and do a load. */
6775 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6776 CC_NZ for comparisons against zero in which a single Z or N flag test
6777 is enough, CC_UNS for other unsigned comparisons, and CC for other
6778 signed comparisons. */
6781 frv_select_cc_mode (enum rtx_code code
, rtx x
, rtx y
)
6783 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6792 return y
== const0_rtx
? CC_NZmode
: CCmode
;
6798 return y
== const0_rtx
? CC_NZmode
: CC_UNSmode
;
6806 /* Worker function for TARGET_REGISTER_MOVE_COST. */
6808 #define HIGH_COST 40
6809 #define MEDIUM_COST 3
6813 frv_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
6814 reg_class_t from
, reg_class_t to
)
6827 case FDPIC_FPTR_REGS
:
6828 case FDPIC_CALL_REGS
:
6841 case FDPIC_FPTR_REGS
:
6842 case FDPIC_CALL_REGS
:
6867 case FDPIC_FPTR_REGS
:
6868 case FDPIC_CALL_REGS
:
6892 case FDPIC_FPTR_REGS
:
6893 case FDPIC_CALL_REGS
:
6914 /* Worker function for TARGET_MEMORY_MOVE_COST. */
6917 frv_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
6918 reg_class_t rclass ATTRIBUTE_UNUSED
,
6919 bool in ATTRIBUTE_UNUSED
)
6925 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6926 use ".picptr" to generate safe relocations for PIC code. We also
6927 need a fixup entry for aligned (non-debugging) code. */
6930 frv_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
6932 if ((flag_pic
|| TARGET_FDPIC
) && size
== UNITS_PER_WORD
)
6934 if (GET_CODE (value
) == CONST
6935 || GET_CODE (value
) == SYMBOL_REF
6936 || GET_CODE (value
) == LABEL_REF
)
6938 if (TARGET_FDPIC
&& GET_CODE (value
) == SYMBOL_REF
6939 && SYMBOL_REF_FUNCTION_P (value
))
6941 fputs ("\t.picptr\tfuncdesc(", asm_out_file
);
6942 output_addr_const (asm_out_file
, value
);
6943 fputs (")\n", asm_out_file
);
6946 else if (TARGET_FDPIC
&& GET_CODE (value
) == CONST
6947 && frv_function_symbol_referenced_p (value
))
6949 if (aligned_p
&& !TARGET_FDPIC
)
6951 static int label_num
= 0;
6955 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", label_num
++);
6956 p
= (* targetm
.strip_name_encoding
) (buf
);
6958 fprintf (asm_out_file
, "%s:\n", p
);
6959 fprintf (asm_out_file
, "%s\n", FIXUP_SECTION_ASM_OP
);
6960 fprintf (asm_out_file
, "\t.picptr\t%s\n", p
);
6961 fprintf (asm_out_file
, "\t.previous\n");
6963 assemble_integer_with_op ("\t.picptr\t", value
);
6968 /* We've set the unaligned SI op to NULL, so we always have to
6969 handle the unaligned case here. */
6970 assemble_integer_with_op ("\t.4byte\t", value
);
6974 return default_assemble_integer (value
, size
, aligned_p
);
6977 /* Function to set up the backend function structure. */
6979 static struct machine_function
*
6980 frv_init_machine_status (void)
6982 return ggc_cleared_alloc
<machine_function
> ();
6985 /* Implement TARGET_SCHED_ISSUE_RATE. */
6988 frv_issue_rate (void)
6993 switch (frv_cpu_type
)
6997 case FRV_CPU_SIMPLE
:
7005 case FRV_CPU_GENERIC
:
7007 case FRV_CPU_TOMCAT
:
7015 /* Return the value of INSN's acc_group attribute. */
7018 frv_acc_group (rtx insn
)
7020 /* This distinction only applies to the FR550 packing constraints. */
7021 if (frv_cpu_type
== FRV_CPU_FR550
)
7023 subrtx_iterator::array_type array
;
7024 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
7027 unsigned int regno
= REGNO (*iter
);
7028 /* If REGNO refers to an accumulator, return ACC_GROUP_ODD if
7029 the bit 2 of the register number is set and ACC_GROUP_EVEN if
7032 return (regno
- ACC_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
7034 return (regno
- ACCG_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
7037 return ACC_GROUP_NONE
;
7040 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7041 INSN will try to claim first. Since this value depends only on the
7042 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7045 frv_insn_unit (rtx_insn
*insn
)
7047 enum attr_type type
;
7049 type
= get_attr_type (insn
);
7050 if (frv_type_to_unit
[type
] == ARRAY_SIZE (frv_unit_codes
))
7052 /* We haven't seen this type of instruction before. */
7056 /* Issue the instruction on its own to see which unit it prefers. */
7057 state
= alloca (state_size ());
7058 state_reset (state
);
7059 state_transition (state
, insn
);
7061 /* Find out which unit was taken. */
7062 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_codes
); unit
++)
7063 if (cpu_unit_reservation_p (state
, frv_unit_codes
[unit
]))
7066 gcc_assert (unit
!= ARRAY_SIZE (frv_unit_codes
));
7068 frv_type_to_unit
[type
] = unit
;
7070 return frv_type_to_unit
[type
];
7073 /* Return true if INSN issues to a branch unit. */
7076 frv_issues_to_branch_unit_p (rtx_insn
*insn
)
7078 return frv_unit_groups
[frv_insn_unit (insn
)] == GROUP_B
;
7081 /* The instructions in the packet, partitioned into groups. */
7082 struct frv_packet_group
{
7083 /* How many instructions in the packet belong to this group. */
7084 unsigned int num_insns
;
7086 /* A list of the instructions that belong to this group, in the order
7087 they appear in the rtl stream. */
7088 rtx_insn
*insns
[ARRAY_SIZE (frv_unit_codes
)];
7090 /* The contents of INSNS after they have been sorted into the correct
7091 assembly-language order. Element X issues to unit X. The list may
7092 contain extra nops. */
7093 rtx_insn
*sorted
[ARRAY_SIZE (frv_unit_codes
)];
7095 /* The member of frv_nops[] to use in sorted[]. */
7099 /* The current state of the packing pass, implemented by frv_pack_insns. */
7101 /* The state of the pipeline DFA. */
7104 /* Which hardware registers are set within the current packet,
7105 and the conditions under which they are set. */
7106 regstate_t regstate
[FIRST_PSEUDO_REGISTER
];
7108 /* The memory locations that have been modified so far in this
7109 packet. MEM is the memref and COND is the regstate_t condition
7110 under which it is set. */
7116 /* The number of valid entries in MEMS. The value is larger than
7117 ARRAY_SIZE (mems) if there were too many mems to record. */
7118 unsigned int num_mems
;
7120 /* The maximum number of instructions that can be packed together. */
7121 unsigned int issue_rate
;
7123 /* The instructions in the packet, partitioned into groups. */
7124 struct frv_packet_group groups
[NUM_GROUPS
];
7126 /* The instructions that make up the current packet. */
7127 rtx_insn
*insns
[ARRAY_SIZE (frv_unit_codes
)];
7128 unsigned int num_insns
;
7131 /* Return the regstate_t flags for the given COND_EXEC condition.
7132 Abort if the condition isn't in the right form. */
7135 frv_cond_flags (rtx cond
)
7137 gcc_assert ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
7138 && GET_CODE (XEXP (cond
, 0)) == REG
7139 && CR_P (REGNO (XEXP (cond
, 0)))
7140 && XEXP (cond
, 1) == const0_rtx
);
7141 return ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
7142 | (GET_CODE (cond
) == NE
7144 : REGSTATE_IF_FALSE
));
7148 /* Return true if something accessed under condition COND2 can
7149 conflict with something written under condition COND1. */
7152 frv_regstate_conflict_p (regstate_t cond1
, regstate_t cond2
)
7154 /* If either reference was unconditional, we have a conflict. */
7155 if ((cond1
& REGSTATE_IF_EITHER
) == 0
7156 || (cond2
& REGSTATE_IF_EITHER
) == 0)
7159 /* The references might conflict if they were controlled by
7161 if ((cond1
& REGSTATE_CC_MASK
) != (cond2
& REGSTATE_CC_MASK
))
7164 /* They definitely conflict if they are controlled by the
7166 if ((cond1
& cond2
& REGSTATE_IF_EITHER
) != 0)
7173 /* Return true if an instruction with pattern PAT depends on an
7174 instruction in the current packet. COND describes the condition
7175 under which PAT might be set or used. */
7178 frv_registers_conflict_p_1 (rtx pat
, regstate_t cond
)
7180 subrtx_var_iterator::array_type array
;
7181 FOR_EACH_SUBRTX_VAR (iter
, array
, pat
, NONCONST
)
7184 if (GET_CODE (x
) == REG
)
7187 FOR_EACH_REGNO (regno
, x
)
7188 if ((frv_packet
.regstate
[regno
] & REGSTATE_MODIFIED
) != 0)
7189 if (frv_regstate_conflict_p (frv_packet
.regstate
[regno
], cond
))
7192 else if (GET_CODE (x
) == MEM
)
7194 /* If we ran out of memory slots, assume a conflict. */
7195 if (frv_packet
.num_mems
> ARRAY_SIZE (frv_packet
.mems
))
7198 /* Check for output or true dependencies with earlier MEMs. */
7199 for (unsigned int i
= 0; i
< frv_packet
.num_mems
; i
++)
7200 if (frv_regstate_conflict_p (frv_packet
.mems
[i
].cond
, cond
))
7202 if (true_dependence (frv_packet
.mems
[i
].mem
, VOIDmode
, x
))
7205 if (output_dependence (frv_packet
.mems
[i
].mem
, x
))
7210 /* The return values of calls aren't significant: they describe
7211 the effect of the call as a whole, not of the insn itself. */
7212 else if (GET_CODE (x
) == SET
&& GET_CODE (SET_SRC (x
)) == CALL
)
7213 iter
.substitute (SET_SRC (x
));
7219 /* Return true if something in X might depend on an instruction
7220 in the current packet. */
7223 frv_registers_conflict_p (rtx x
)
7228 if (GET_CODE (x
) == COND_EXEC
)
7230 if (frv_registers_conflict_p_1 (XEXP (x
, 0), flags
))
7233 flags
|= frv_cond_flags (XEXP (x
, 0));
7236 return frv_registers_conflict_p_1 (x
, flags
);
7240 /* A note_stores callback. DATA points to the regstate_t condition
7241 under which X is modified. Update FRV_PACKET accordingly. */
7244 frv_registers_update_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7248 if (GET_CODE (x
) == REG
)
7249 FOR_EACH_REGNO (regno
, x
)
7250 frv_packet
.regstate
[regno
] |= *(regstate_t
*) data
;
7252 if (GET_CODE (x
) == MEM
)
7254 if (frv_packet
.num_mems
< ARRAY_SIZE (frv_packet
.mems
))
7256 frv_packet
.mems
[frv_packet
.num_mems
].mem
= x
;
7257 frv_packet
.mems
[frv_packet
.num_mems
].cond
= *(regstate_t
*) data
;
7259 frv_packet
.num_mems
++;
7264 /* Update the register state information for an instruction whose
7268 frv_registers_update (rtx x
)
7272 flags
= REGSTATE_MODIFIED
;
7273 if (GET_CODE (x
) == COND_EXEC
)
7275 flags
|= frv_cond_flags (XEXP (x
, 0));
7278 note_stores (x
, frv_registers_update_1
, &flags
);
7282 /* Initialize frv_packet for the start of a new packet. */
7285 frv_start_packet (void)
7287 enum frv_insn_group group
;
7289 memset (frv_packet
.regstate
, 0, sizeof (frv_packet
.regstate
));
7290 frv_packet
.num_mems
= 0;
7291 frv_packet
.num_insns
= 0;
7292 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7293 group
= (enum frv_insn_group
) (group
+ 1))
7294 frv_packet
.groups
[group
].num_insns
= 0;
7298 /* Likewise for the start of a new basic block. */
7301 frv_start_packet_block (void)
7303 state_reset (frv_packet
.dfa_state
);
7304 frv_start_packet ();
7308 /* Finish the current packet, if any, and start a new one. Call
7309 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7312 frv_finish_packet (void (*handle_packet
) (void))
7314 if (frv_packet
.num_insns
> 0)
7317 state_transition (frv_packet
.dfa_state
, 0);
7318 frv_start_packet ();
7323 /* Return true if INSN can be added to the current packet. Update
7324 the DFA state on success. */
7327 frv_pack_insn_p (rtx_insn
*insn
)
7329 /* See if the packet is already as long as it can be. */
7330 if (frv_packet
.num_insns
== frv_packet
.issue_rate
)
7333 /* If the scheduler thought that an instruction should start a packet,
7334 it's usually a good idea to believe it. It knows much more about
7335 the latencies than we do.
7337 There are some exceptions though:
7339 - Conditional instructions are scheduled on the assumption that
7340 they will be executed. This is usually a good thing, since it
7341 tends to avoid unnecessary stalls in the conditional code.
7342 But we want to pack conditional instructions as tightly as
7343 possible, in order to optimize the case where they aren't
7346 - The scheduler will always put branches on their own, even
7347 if there's no real dependency.
7349 - There's no point putting a call in its own packet unless
7351 if (frv_packet
.num_insns
> 0
7352 && NONJUMP_INSN_P (insn
)
7353 && GET_MODE (insn
) == TImode
7354 && GET_CODE (PATTERN (insn
)) != COND_EXEC
)
7357 /* Check for register conflicts. Don't do this for setlo since any
7358 conflict will be with the partnering sethi, with which it can
7360 if (get_attr_type (insn
) != TYPE_SETLO
)
7361 if (frv_registers_conflict_p (PATTERN (insn
)))
7364 return state_transition (frv_packet
.dfa_state
, insn
) < 0;
7368 /* Add instruction INSN to the current packet. */
7371 frv_add_insn_to_packet (rtx_insn
*insn
)
7373 struct frv_packet_group
*packet_group
;
7375 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7376 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7377 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7379 frv_registers_update (PATTERN (insn
));
7383 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7384 packet ends in a branch or call, insert the nop before it, otherwise
7388 frv_insert_nop_in_packet (rtx_insn
*insn
)
7390 struct frv_packet_group
*packet_group
;
7393 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7394 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
7395 if (! NONJUMP_INSN_P (last
))
7397 insn
= emit_insn_before (PATTERN (insn
), last
);
7398 frv_packet
.insns
[frv_packet
.num_insns
- 1] = insn
;
7399 frv_packet
.insns
[frv_packet
.num_insns
++] = last
;
7403 insn
= emit_insn_after (PATTERN (insn
), last
);
7404 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7406 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7410 /* If packing is enabled, divide the instructions into packets and
7411 return true. Call HANDLE_PACKET for each complete packet. */
7414 frv_for_each_packet (void (*handle_packet
) (void))
7416 rtx_insn
*insn
, *next_insn
;
7418 frv_packet
.issue_rate
= frv_issue_rate ();
7420 /* Early exit if we don't want to pack insns. */
7422 || !flag_schedule_insns_after_reload
7423 || !TARGET_VLIW_BRANCH
7424 || frv_packet
.issue_rate
== 1)
7427 /* Set up the initial packing state. */
7429 frv_packet
.dfa_state
= alloca (state_size ());
7431 frv_start_packet_block ();
7432 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
7437 code
= GET_CODE (insn
);
7438 next_insn
= NEXT_INSN (insn
);
7440 if (code
== CODE_LABEL
)
7442 frv_finish_packet (handle_packet
);
7443 frv_start_packet_block ();
7447 switch (GET_CODE (PATTERN (insn
)))
7454 /* Calls mustn't be packed on a TOMCAT. */
7455 if (CALL_P (insn
) && frv_cpu_type
== FRV_CPU_TOMCAT
)
7456 frv_finish_packet (handle_packet
);
7458 /* Since the last instruction in a packet determines the EH
7459 region, any exception-throwing instruction must come at
7460 the end of reordered packet. Insns that issue to a
7461 branch unit are bound to come last; for others it's
7462 too hard to predict. */
7463 eh_insn_p
= (find_reg_note (insn
, REG_EH_REGION
, NULL
) != NULL
);
7464 if (eh_insn_p
&& !frv_issues_to_branch_unit_p (insn
))
7465 frv_finish_packet (handle_packet
);
7467 /* Finish the current packet if we can't add INSN to it.
7468 Simulate cycles until INSN is ready to issue. */
7469 if (!frv_pack_insn_p (insn
))
7471 frv_finish_packet (handle_packet
);
7472 while (!frv_pack_insn_p (insn
))
7473 state_transition (frv_packet
.dfa_state
, 0);
7476 /* Add the instruction to the packet. */
7477 frv_add_insn_to_packet (insn
);
7479 /* Calls and jumps end a packet, as do insns that throw
7481 if (code
== CALL_INSN
|| code
== JUMP_INSN
|| eh_insn_p
)
7482 frv_finish_packet (handle_packet
);
7486 frv_finish_packet (handle_packet
);
7491 /* Subroutine of frv_sort_insn_group. We are trying to sort
7492 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7493 language order. We have already picked a new position for
7494 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7495 These instructions will occupy elements [0, LOWER_SLOT) and
7496 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7497 the DFA state after issuing these instructions.
7499 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7500 of the unused instructions. Return true if one such permutation gives
7501 a valid ordering, leaving the successful permutation in sorted[].
7502 Do not modify sorted[] until a valid permutation is found. */
7505 frv_sort_insn_group_1 (enum frv_insn_group group
,
7506 unsigned int lower_slot
, unsigned int upper_slot
,
7507 unsigned int issued
, unsigned int num_insns
,
7510 struct frv_packet_group
*packet_group
;
7516 /* Early success if we've filled all the slots. */
7517 if (lower_slot
== upper_slot
)
7520 packet_group
= &frv_packet
.groups
[group
];
7521 dfa_size
= state_size ();
7522 test_state
= alloca (dfa_size
);
7524 /* Try issuing each unused instruction. */
7525 for (i
= num_insns
- 1; i
+ 1 != 0; i
--)
7526 if (~issued
& (1 << i
))
7528 insn
= packet_group
->sorted
[i
];
7529 memcpy (test_state
, state
, dfa_size
);
7530 if (state_transition (test_state
, insn
) < 0
7531 && cpu_unit_reservation_p (test_state
,
7532 NTH_UNIT (group
, upper_slot
- 1))
7533 && frv_sort_insn_group_1 (group
, lower_slot
, upper_slot
- 1,
7534 issued
| (1 << i
), num_insns
,
7537 packet_group
->sorted
[upper_slot
- 1] = insn
;
7545 /* Compare two instructions by their frv_insn_unit. */
7548 frv_compare_insns (const void *first
, const void *second
)
7550 rtx_insn
* const *insn1
= (rtx_insn
* const *) first
;
7551 rtx_insn
* const *insn2
= (rtx_insn
* const *) second
;
7552 return frv_insn_unit (*insn1
) - frv_insn_unit (*insn2
);
7555 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7556 and sort it into assembly language order. See frv.md for a description of
7560 frv_sort_insn_group (enum frv_insn_group group
)
7562 struct frv_packet_group
*packet_group
;
7563 unsigned int first
, i
, nop
, max_unit
, num_slots
;
7564 state_t state
, test_state
;
7567 packet_group
= &frv_packet
.groups
[group
];
7569 /* Assume no nop is needed. */
7570 packet_group
->nop
= 0;
7572 if (packet_group
->num_insns
== 0)
7575 /* Copy insns[] to sorted[]. */
7576 memcpy (packet_group
->sorted
, packet_group
->insns
,
7577 sizeof (rtx
) * packet_group
->num_insns
);
7579 /* Sort sorted[] by the unit that each insn tries to take first. */
7580 if (packet_group
->num_insns
> 1)
7581 qsort (packet_group
->sorted
, packet_group
->num_insns
,
7582 sizeof (rtx
), frv_compare_insns
);
7584 /* That's always enough for branch and control insns. */
7585 if (group
== GROUP_B
|| group
== GROUP_C
)
7588 dfa_size
= state_size ();
7589 state
= alloca (dfa_size
);
7590 test_state
= alloca (dfa_size
);
7592 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7593 consecutively and such that the DFA takes unit X when sorted[X]
7594 is added. Set STATE to the new DFA state. */
7595 state_reset (test_state
);
7596 for (first
= 0; first
< packet_group
->num_insns
; first
++)
7598 memcpy (state
, test_state
, dfa_size
);
7599 if (state_transition (test_state
, packet_group
->sorted
[first
]) >= 0
7600 || !cpu_unit_reservation_p (test_state
, NTH_UNIT (group
, first
)))
7604 /* If all the instructions issued in ascending order, we're done. */
7605 if (first
== packet_group
->num_insns
)
7608 /* Add nops to the end of sorted[] and try each permutation until
7609 we find one that works. */
7610 for (nop
= 0; nop
< frv_num_nops
; nop
++)
7612 max_unit
= frv_insn_unit (frv_nops
[nop
]);
7613 if (frv_unit_groups
[max_unit
] == group
)
7615 packet_group
->nop
= frv_nops
[nop
];
7616 num_slots
= UNIT_NUMBER (max_unit
) + 1;
7617 for (i
= packet_group
->num_insns
; i
< num_slots
; i
++)
7618 packet_group
->sorted
[i
] = frv_nops
[nop
];
7619 if (frv_sort_insn_group_1 (group
, first
, num_slots
,
7620 (1 << first
) - 1, num_slots
, state
))
7627 /* Sort the current packet into assembly-language order. Set packing
7628 flags as appropriate. */
7631 frv_reorder_packet (void)
7633 unsigned int cursor
[NUM_GROUPS
];
7634 rtx insns
[ARRAY_SIZE (frv_unit_groups
)];
7635 unsigned int unit
, to
, from
;
7636 enum frv_insn_group group
;
7637 struct frv_packet_group
*packet_group
;
7639 /* First sort each group individually. */
7640 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7641 group
= (enum frv_insn_group
) (group
+ 1))
7644 frv_sort_insn_group (group
);
7647 /* Go through the unit template and try add an instruction from
7648 that unit's group. */
7650 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_groups
); unit
++)
7652 group
= frv_unit_groups
[unit
];
7653 packet_group
= &frv_packet
.groups
[group
];
7654 if (cursor
[group
] < packet_group
->num_insns
)
7656 /* frv_reorg should have added nops for us. */
7657 gcc_assert (packet_group
->sorted
[cursor
[group
]]
7658 != packet_group
->nop
);
7659 insns
[to
++] = packet_group
->sorted
[cursor
[group
]++];
7663 gcc_assert (to
== frv_packet
.num_insns
);
7665 /* Clear the last instruction's packing flag, thus marking the end of
7666 a packet. Reorder the other instructions relative to it. */
7667 CLEAR_PACKING_FLAG (insns
[to
- 1]);
7668 for (from
= 0; from
< to
- 1; from
++)
7670 remove_insn (insns
[from
]);
7671 add_insn_before (insns
[from
], insns
[to
- 1], NULL
);
7672 SET_PACKING_FLAG (insns
[from
]);
7677 /* Divide instructions into packets. Reorder the contents of each
7678 packet so that they are in the correct assembly-language order.
7680 Since this pass can change the raw meaning of the rtl stream, it must
7681 only be called at the last minute, just before the instructions are
7685 frv_pack_insns (void)
7687 if (frv_for_each_packet (frv_reorder_packet
))
7688 frv_insn_packing_flag
= 0;
7690 frv_insn_packing_flag
= -1;
7693 /* See whether we need to add nops to group GROUP in order to
7694 make a valid packet. */
7697 frv_fill_unused_units (enum frv_insn_group group
)
7699 unsigned int non_nops
, nops
, i
;
7700 struct frv_packet_group
*packet_group
;
7702 packet_group
= &frv_packet
.groups
[group
];
7704 /* Sort the instructions into assembly-language order.
7705 Use nops to fill slots that are otherwise unused. */
7706 frv_sort_insn_group (group
);
7708 /* See how many nops are needed before the final useful instruction. */
7710 for (non_nops
= 0; non_nops
< packet_group
->num_insns
; non_nops
++)
7711 while (packet_group
->sorted
[i
++] == packet_group
->nop
)
7714 /* Insert that many nops into the instruction stream. */
7716 frv_insert_nop_in_packet (packet_group
->nop
);
7719 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7722 frv_same_doubleword_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7724 if (io1
->const_address
!= 0 && io2
->const_address
!= 0)
7725 return io1
->const_address
== io2
->const_address
;
7727 if (io1
->var_address
!= 0 && io2
->var_address
!= 0)
7728 return rtx_equal_p (io1
->var_address
, io2
->var_address
);
7733 /* Return true if operations IO1 and IO2 are guaranteed to complete
7737 frv_io_fixed_order_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7739 /* The order of writes is always preserved. */
7740 if (io1
->type
== FRV_IO_WRITE
&& io2
->type
== FRV_IO_WRITE
)
7743 /* The order of reads isn't preserved. */
7744 if (io1
->type
!= FRV_IO_WRITE
&& io2
->type
!= FRV_IO_WRITE
)
7747 /* One operation is a write and the other is (or could be) a read.
7748 The order is only guaranteed if the accesses are to the same
7750 return frv_same_doubleword_p (io1
, io2
);
7753 /* Generalize I/O operation X so that it covers both X and Y. */
7756 frv_io_union (struct frv_io
*x
, const struct frv_io
*y
)
7758 if (x
->type
!= y
->type
)
7759 x
->type
= FRV_IO_UNKNOWN
;
7760 if (!frv_same_doubleword_p (x
, y
))
7762 x
->const_address
= 0;
7767 /* Fill IO with information about the load or store associated with
7768 membar instruction INSN. */
7771 frv_extract_membar (struct frv_io
*io
, rtx_insn
*insn
)
7773 extract_insn (insn
);
7774 io
->type
= (enum frv_io_type
) INTVAL (recog_data
.operand
[2]);
7775 io
->const_address
= INTVAL (recog_data
.operand
[1]);
7776 io
->var_address
= XEXP (recog_data
.operand
[0], 0);
7779 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7780 if X is a register and *DATA depends on X. */
7783 frv_io_check_address (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7785 rtx
*other
= (rtx
*) data
;
7787 if (REG_P (x
) && *other
!= 0 && reg_overlap_mentioned_p (x
, *other
))
7791 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7792 Remove every modified register from the set. */
7795 frv_io_handle_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7797 HARD_REG_SET
*set
= (HARD_REG_SET
*) data
;
7801 FOR_EACH_REGNO (regno
, x
)
7802 CLEAR_HARD_REG_BIT (*set
, regno
);
7805 /* A note_uses callback that adds all registers in *X to hard register
7809 frv_io_handle_use (rtx
*x
, void *data
)
7811 find_all_hard_regs (*x
, (HARD_REG_SET
*) data
);
7814 /* Go through block BB looking for membars to remove. There are two
7815 cases where intra-block analysis is enough:
7817 - a membar is redundant if it occurs between two consecutive I/O
7818 operations and if those operations are guaranteed to complete
7821 - a membar for a __builtin_read is redundant if the result is
7822 used before the next I/O operation is issued.
7824 If the last membar in the block could not be removed, and there
7825 are guaranteed to be no I/O operations between that membar and
7826 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7829 Describe the block's first I/O operation in *NEXT_IO. Describe
7830 an unknown operation if the block doesn't do any I/O. */
7833 frv_optimize_membar_local (basic_block bb
, struct frv_io
*next_io
,
7834 rtx_insn
**last_membar
)
7836 HARD_REG_SET used_regs
;
7837 rtx next_membar
, set
;
7841 /* NEXT_IO is the next I/O operation to be performed after the current
7842 instruction. It starts off as being an unknown operation. */
7843 memset (next_io
, 0, sizeof (*next_io
));
7845 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7846 next_is_end_p
= true;
7848 /* If the current instruction is a __builtin_read or __builtin_write,
7849 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7850 is null if the membar has already been deleted.
7852 Note that the initialization here should only be needed to
7853 suppress warnings. */
7856 /* USED_REGS is the set of registers that are used before the
7857 next I/O instruction. */
7858 CLEAR_HARD_REG_SET (used_regs
);
7860 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
); insn
= PREV_INSN (insn
))
7863 /* We can't predict what a call will do to volatile memory. */
7864 memset (next_io
, 0, sizeof (struct frv_io
));
7865 next_is_end_p
= false;
7866 CLEAR_HARD_REG_SET (used_regs
);
7868 else if (INSN_P (insn
))
7869 switch (recog_memoized (insn
))
7871 case CODE_FOR_optional_membar_qi
:
7872 case CODE_FOR_optional_membar_hi
:
7873 case CODE_FOR_optional_membar_si
:
7874 case CODE_FOR_optional_membar_di
:
7878 /* Local information isn't enough to decide whether this
7879 membar is needed. Stash it away for later. */
7880 *last_membar
= insn
;
7881 frv_extract_membar (next_io
, insn
);
7882 next_is_end_p
= false;
7886 /* Check whether the I/O operation before INSN could be
7887 reordered with one described by NEXT_IO. If it can't,
7888 INSN will not be needed. */
7889 struct frv_io prev_io
;
7891 frv_extract_membar (&prev_io
, insn
);
7892 if (frv_io_fixed_order_p (&prev_io
, next_io
))
7896 ";; [Local] Removing membar %d since order"
7897 " of accesses is guaranteed\n",
7898 INSN_UID (next_membar
));
7900 insn
= NEXT_INSN (insn
);
7901 delete_insn (next_membar
);
7909 /* Invalidate NEXT_IO's address if it depends on something that
7910 is clobbered by INSN. */
7911 if (next_io
->var_address
)
7912 note_stores (PATTERN (insn
), frv_io_check_address
,
7913 &next_io
->var_address
);
7915 /* If the next membar is associated with a __builtin_read,
7916 see if INSN reads from that address. If it does, and if
7917 the destination register is used before the next I/O access,
7918 there is no need for the membar. */
7919 set
= PATTERN (insn
);
7920 if (next_io
->type
== FRV_IO_READ
7921 && next_io
->var_address
!= 0
7923 && GET_CODE (set
) == SET
7924 && GET_CODE (SET_DEST (set
)) == REG
7925 && TEST_HARD_REG_BIT (used_regs
, REGNO (SET_DEST (set
))))
7929 src
= SET_SRC (set
);
7930 if (GET_CODE (src
) == ZERO_EXTEND
)
7931 src
= XEXP (src
, 0);
7933 if (GET_CODE (src
) == MEM
7934 && rtx_equal_p (XEXP (src
, 0), next_io
->var_address
))
7938 ";; [Local] Removing membar %d since the target"
7939 " of %d is used before the I/O operation\n",
7940 INSN_UID (next_membar
), INSN_UID (insn
));
7942 if (next_membar
== *last_membar
)
7945 delete_insn (next_membar
);
7950 /* If INSN has volatile references, forget about any registers
7951 that are used after it. Otherwise forget about uses that
7952 are (or might be) defined by INSN. */
7953 if (volatile_refs_p (PATTERN (insn
)))
7954 CLEAR_HARD_REG_SET (used_regs
);
7956 note_stores (PATTERN (insn
), frv_io_handle_set
, &used_regs
);
7958 note_uses (&PATTERN (insn
), frv_io_handle_use
, &used_regs
);
7963 /* See if MEMBAR, the last membar instruction in BB, can be removed.
7964 FIRST_IO[X] describes the first operation performed by basic block X. */
7967 frv_optimize_membar_global (basic_block bb
, struct frv_io
*first_io
,
7970 struct frv_io this_io
, next_io
;
7974 /* We need to keep the membar if there is an edge to the exit block. */
7975 FOR_EACH_EDGE (succ
, ei
, bb
->succs
)
7976 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
7977 if (succ
->dest
== EXIT_BLOCK_PTR_FOR_FN (cfun
))
7980 /* Work out the union of all successor blocks. */
7981 ei
= ei_start (bb
->succs
);
7982 ei_cond (ei
, &succ
);
7983 /* next_io = first_io[bb->succ->dest->index]; */
7984 next_io
= first_io
[succ
->dest
->index
];
7985 ei
= ei_start (bb
->succs
);
7986 if (ei_cond (ei
, &succ
))
7988 for (ei_next (&ei
); ei_cond (ei
, &succ
); ei_next (&ei
))
7989 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
7990 frv_io_union (&next_io
, &first_io
[succ
->dest
->index
]);
7995 frv_extract_membar (&this_io
, membar
);
7996 if (frv_io_fixed_order_p (&this_io
, &next_io
))
8000 ";; [Global] Removing membar %d since order of accesses"
8001 " is guaranteed\n", INSN_UID (membar
));
8003 delete_insn (membar
);
8007 /* Remove redundant membars from the current function. */
8010 frv_optimize_membar (void)
8013 struct frv_io
*first_io
;
8014 rtx_insn
**last_membar
;
8016 compute_bb_for_insn ();
8017 first_io
= XCNEWVEC (struct frv_io
, last_basic_block_for_fn (cfun
));
8018 last_membar
= XCNEWVEC (rtx_insn
*, last_basic_block_for_fn (cfun
));
8020 FOR_EACH_BB_FN (bb
, cfun
)
8021 frv_optimize_membar_local (bb
, &first_io
[bb
->index
],
8022 &last_membar
[bb
->index
]);
8024 FOR_EACH_BB_FN (bb
, cfun
)
8025 if (last_membar
[bb
->index
] != 0)
8026 frv_optimize_membar_global (bb
, first_io
, last_membar
[bb
->index
]);
8032 /* Used by frv_reorg to keep track of the current packet's address. */
8033 static unsigned int frv_packet_address
;
8035 /* If the current packet falls through to a label, try to pad the packet
8036 with nops in order to fit the label's alignment requirements. */
8039 frv_align_label (void)
8041 unsigned int alignment
, target
, nop
;
8042 rtx_insn
*x
, *last
, *barrier
, *label
;
8044 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8045 maximum alignment of that packet, LABEL to the last label between
8046 the packets, and BARRIER to the last barrier. */
8047 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8048 label
= barrier
= 0;
8050 for (x
= NEXT_INSN (last
); x
!= 0 && !INSN_P (x
); x
= NEXT_INSN (x
))
8054 unsigned int subalign
= 1 << label_to_alignment (x
);
8055 alignment
= MAX (alignment
, subalign
);
8062 /* If -malign-labels, and the packet falls through to an unaligned
8063 label, try introducing a nop to align that label to 8 bytes. */
8064 if (TARGET_ALIGN_LABELS
8067 && frv_packet
.num_insns
< frv_packet
.issue_rate
)
8068 alignment
= MAX (alignment
, 8);
8070 /* Advance the address to the end of the current packet. */
8071 frv_packet_address
+= frv_packet
.num_insns
* 4;
8073 /* Work out the target address, after alignment. */
8074 target
= (frv_packet_address
+ alignment
- 1) & -alignment
;
8076 /* If the packet falls through to the label, try to find an efficient
8077 padding sequence. */
8080 /* First try adding nops to the current packet. */
8081 for (nop
= 0; nop
< frv_num_nops
; nop
++)
8082 while (frv_packet_address
< target
&& frv_pack_insn_p (frv_nops
[nop
]))
8084 frv_insert_nop_in_packet (frv_nops
[nop
]);
8085 frv_packet_address
+= 4;
8088 /* If we still haven't reached the target, add some new packets that
8089 contain only nops. If there are two types of nop, insert an
8090 alternating sequence of frv_nops[0] and frv_nops[1], which will
8091 lead to packets like:
8098 etc. Just emit frv_nops[0] if that's the only nop we have. */
8099 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8101 while (frv_packet_address
< target
)
8103 last
= emit_insn_after (PATTERN (frv_nops
[nop
]), last
);
8104 frv_packet_address
+= 4;
8105 if (frv_num_nops
> 1)
8110 frv_packet_address
= target
;
8113 /* Subroutine of frv_reorg, called after each packet has been constructed
8117 frv_reorg_packet (void)
8119 frv_fill_unused_units (GROUP_I
);
8120 frv_fill_unused_units (GROUP_FM
);
8124 /* Add an instruction with pattern NOP to frv_nops[]. */
8127 frv_register_nop (rtx nop
)
8129 rtx_insn
*nop_insn
= make_insn_raw (nop
);
8130 SET_NEXT_INSN (nop_insn
) = 0;
8131 SET_PREV_INSN (nop_insn
) = 0;
8132 frv_nops
[frv_num_nops
++] = nop_insn
;
8135 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8136 into packets and check whether we need to insert nops in order to
8137 fulfill the processor's issue requirements. Also, if the user has
8138 requested a certain alignment for a label, try to meet that alignment
8139 by inserting nops in the previous packet. */
8144 if (optimize
> 0 && TARGET_OPTIMIZE_MEMBAR
&& cfun
->machine
->has_membar_p
)
8145 frv_optimize_membar ();
8148 frv_register_nop (gen_nop ());
8150 frv_register_nop (gen_mnop ());
8151 if (TARGET_HARD_FLOAT
)
8152 frv_register_nop (gen_fnop ());
8154 /* Estimate the length of each branch. Although this may change after
8155 we've inserted nops, it will only do so in big functions. */
8156 shorten_branches (get_insns ());
8158 frv_packet_address
= 0;
8159 frv_for_each_packet (frv_reorg_packet
);
8162 #define def_builtin(name, type, code) \
8163 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8165 struct builtin_description
8167 enum insn_code icode
;
8169 enum frv_builtins code
;
8170 enum rtx_code comparison
;
8174 /* Media intrinsics that take a single, constant argument. */
8176 static struct builtin_description bdesc_set
[] =
8178 { CODE_FOR_mhdsets
, "__MHDSETS", FRV_BUILTIN_MHDSETS
, UNKNOWN
, 0 }
8181 /* Media intrinsics that take just one argument. */
8183 static struct builtin_description bdesc_1arg
[] =
8185 { CODE_FOR_mnot
, "__MNOT", FRV_BUILTIN_MNOT
, UNKNOWN
, 0 },
8186 { CODE_FOR_munpackh
, "__MUNPACKH", FRV_BUILTIN_MUNPACKH
, UNKNOWN
, 0 },
8187 { CODE_FOR_mbtoh
, "__MBTOH", FRV_BUILTIN_MBTOH
, UNKNOWN
, 0 },
8188 { CODE_FOR_mhtob
, "__MHTOB", FRV_BUILTIN_MHTOB
, UNKNOWN
, 0},
8189 { CODE_FOR_mabshs
, "__MABSHS", FRV_BUILTIN_MABSHS
, UNKNOWN
, 0 },
8190 { CODE_FOR_scutss
, "__SCUTSS", FRV_BUILTIN_SCUTSS
, UNKNOWN
, 0 }
8193 /* Media intrinsics that take two arguments. */
8195 static struct builtin_description bdesc_2arg
[] =
8197 { CODE_FOR_mand
, "__MAND", FRV_BUILTIN_MAND
, UNKNOWN
, 0},
8198 { CODE_FOR_mor
, "__MOR", FRV_BUILTIN_MOR
, UNKNOWN
, 0},
8199 { CODE_FOR_mxor
, "__MXOR", FRV_BUILTIN_MXOR
, UNKNOWN
, 0},
8200 { CODE_FOR_maveh
, "__MAVEH", FRV_BUILTIN_MAVEH
, UNKNOWN
, 0},
8201 { CODE_FOR_msaths
, "__MSATHS", FRV_BUILTIN_MSATHS
, UNKNOWN
, 0},
8202 { CODE_FOR_msathu
, "__MSATHU", FRV_BUILTIN_MSATHU
, UNKNOWN
, 0},
8203 { CODE_FOR_maddhss
, "__MADDHSS", FRV_BUILTIN_MADDHSS
, UNKNOWN
, 0},
8204 { CODE_FOR_maddhus
, "__MADDHUS", FRV_BUILTIN_MADDHUS
, UNKNOWN
, 0},
8205 { CODE_FOR_msubhss
, "__MSUBHSS", FRV_BUILTIN_MSUBHSS
, UNKNOWN
, 0},
8206 { CODE_FOR_msubhus
, "__MSUBHUS", FRV_BUILTIN_MSUBHUS
, UNKNOWN
, 0},
8207 { CODE_FOR_mqaddhss
, "__MQADDHSS", FRV_BUILTIN_MQADDHSS
, UNKNOWN
, 0},
8208 { CODE_FOR_mqaddhus
, "__MQADDHUS", FRV_BUILTIN_MQADDHUS
, UNKNOWN
, 0},
8209 { CODE_FOR_mqsubhss
, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS
, UNKNOWN
, 0},
8210 { CODE_FOR_mqsubhus
, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS
, UNKNOWN
, 0},
8211 { CODE_FOR_mpackh
, "__MPACKH", FRV_BUILTIN_MPACKH
, UNKNOWN
, 0},
8212 { CODE_FOR_mcop1
, "__Mcop1", FRV_BUILTIN_MCOP1
, UNKNOWN
, 0},
8213 { CODE_FOR_mcop2
, "__Mcop2", FRV_BUILTIN_MCOP2
, UNKNOWN
, 0},
8214 { CODE_FOR_mwcut
, "__MWCUT", FRV_BUILTIN_MWCUT
, UNKNOWN
, 0},
8215 { CODE_FOR_mqsaths
, "__MQSATHS", FRV_BUILTIN_MQSATHS
, UNKNOWN
, 0},
8216 { CODE_FOR_mqlclrhs
, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS
, UNKNOWN
, 0},
8217 { CODE_FOR_mqlmths
, "__MQLMTHS", FRV_BUILTIN_MQLMTHS
, UNKNOWN
, 0},
8218 { CODE_FOR_smul
, "__SMUL", FRV_BUILTIN_SMUL
, UNKNOWN
, 0},
8219 { CODE_FOR_umul
, "__UMUL", FRV_BUILTIN_UMUL
, UNKNOWN
, 0},
8220 { CODE_FOR_addss
, "__ADDSS", FRV_BUILTIN_ADDSS
, UNKNOWN
, 0},
8221 { CODE_FOR_subss
, "__SUBSS", FRV_BUILTIN_SUBSS
, UNKNOWN
, 0},
8222 { CODE_FOR_slass
, "__SLASS", FRV_BUILTIN_SLASS
, UNKNOWN
, 0},
8223 { CODE_FOR_scan
, "__SCAN", FRV_BUILTIN_SCAN
, UNKNOWN
, 0}
8226 /* Integer intrinsics that take two arguments and have no return value. */
8228 static struct builtin_description bdesc_int_void2arg
[] =
8230 { CODE_FOR_smass
, "__SMASS", FRV_BUILTIN_SMASS
, UNKNOWN
, 0},
8231 { CODE_FOR_smsss
, "__SMSSS", FRV_BUILTIN_SMSSS
, UNKNOWN
, 0},
8232 { CODE_FOR_smu
, "__SMU", FRV_BUILTIN_SMU
, UNKNOWN
, 0}
8235 static struct builtin_description bdesc_prefetches
[] =
8237 { CODE_FOR_frv_prefetch0
, "__data_prefetch0", FRV_BUILTIN_PREFETCH0
, UNKNOWN
,
8239 { CODE_FOR_frv_prefetch
, "__data_prefetch", FRV_BUILTIN_PREFETCH
, UNKNOWN
, 0}
8242 /* Media intrinsics that take two arguments, the first being an ACC number. */
8244 static struct builtin_description bdesc_cut
[] =
8246 { CODE_FOR_mcut
, "__MCUT", FRV_BUILTIN_MCUT
, UNKNOWN
, 0},
8247 { CODE_FOR_mcutss
, "__MCUTSS", FRV_BUILTIN_MCUTSS
, UNKNOWN
, 0},
8248 { CODE_FOR_mdcutssi
, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI
, UNKNOWN
, 0}
8251 /* Two-argument media intrinsics with an immediate second argument. */
8253 static struct builtin_description bdesc_2argimm
[] =
8255 { CODE_FOR_mrotli
, "__MROTLI", FRV_BUILTIN_MROTLI
, UNKNOWN
, 0},
8256 { CODE_FOR_mrotri
, "__MROTRI", FRV_BUILTIN_MROTRI
, UNKNOWN
, 0},
8257 { CODE_FOR_msllhi
, "__MSLLHI", FRV_BUILTIN_MSLLHI
, UNKNOWN
, 0},
8258 { CODE_FOR_msrlhi
, "__MSRLHI", FRV_BUILTIN_MSRLHI
, UNKNOWN
, 0},
8259 { CODE_FOR_msrahi
, "__MSRAHI", FRV_BUILTIN_MSRAHI
, UNKNOWN
, 0},
8260 { CODE_FOR_mexpdhw
, "__MEXPDHW", FRV_BUILTIN_MEXPDHW
, UNKNOWN
, 0},
8261 { CODE_FOR_mexpdhd
, "__MEXPDHD", FRV_BUILTIN_MEXPDHD
, UNKNOWN
, 0},
8262 { CODE_FOR_mdrotli
, "__MDROTLI", FRV_BUILTIN_MDROTLI
, UNKNOWN
, 0},
8263 { CODE_FOR_mcplhi
, "__MCPLHI", FRV_BUILTIN_MCPLHI
, UNKNOWN
, 0},
8264 { CODE_FOR_mcpli
, "__MCPLI", FRV_BUILTIN_MCPLI
, UNKNOWN
, 0},
8265 { CODE_FOR_mhsetlos
, "__MHSETLOS", FRV_BUILTIN_MHSETLOS
, UNKNOWN
, 0},
8266 { CODE_FOR_mhsetloh
, "__MHSETLOH", FRV_BUILTIN_MHSETLOH
, UNKNOWN
, 0},
8267 { CODE_FOR_mhsethis
, "__MHSETHIS", FRV_BUILTIN_MHSETHIS
, UNKNOWN
, 0},
8268 { CODE_FOR_mhsethih
, "__MHSETHIH", FRV_BUILTIN_MHSETHIH
, UNKNOWN
, 0},
8269 { CODE_FOR_mhdseth
, "__MHDSETH", FRV_BUILTIN_MHDSETH
, UNKNOWN
, 0},
8270 { CODE_FOR_mqsllhi
, "__MQSLLHI", FRV_BUILTIN_MQSLLHI
, UNKNOWN
, 0},
8271 { CODE_FOR_mqsrahi
, "__MQSRAHI", FRV_BUILTIN_MQSRAHI
, UNKNOWN
, 0}
8274 /* Media intrinsics that take two arguments and return void, the first argument
8275 being a pointer to 4 words in memory. */
8277 static struct builtin_description bdesc_void2arg
[] =
8279 { CODE_FOR_mdunpackh
, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH
, UNKNOWN
, 0},
8280 { CODE_FOR_mbtohe
, "__MBTOHE", FRV_BUILTIN_MBTOHE
, UNKNOWN
, 0},
8283 /* Media intrinsics that take three arguments, the first being a const_int that
8284 denotes an accumulator, and that return void. */
8286 static struct builtin_description bdesc_void3arg
[] =
8288 { CODE_FOR_mcpxrs
, "__MCPXRS", FRV_BUILTIN_MCPXRS
, UNKNOWN
, 0},
8289 { CODE_FOR_mcpxru
, "__MCPXRU", FRV_BUILTIN_MCPXRU
, UNKNOWN
, 0},
8290 { CODE_FOR_mcpxis
, "__MCPXIS", FRV_BUILTIN_MCPXIS
, UNKNOWN
, 0},
8291 { CODE_FOR_mcpxiu
, "__MCPXIU", FRV_BUILTIN_MCPXIU
, UNKNOWN
, 0},
8292 { CODE_FOR_mmulhs
, "__MMULHS", FRV_BUILTIN_MMULHS
, UNKNOWN
, 0},
8293 { CODE_FOR_mmulhu
, "__MMULHU", FRV_BUILTIN_MMULHU
, UNKNOWN
, 0},
8294 { CODE_FOR_mmulxhs
, "__MMULXHS", FRV_BUILTIN_MMULXHS
, UNKNOWN
, 0},
8295 { CODE_FOR_mmulxhu
, "__MMULXHU", FRV_BUILTIN_MMULXHU
, UNKNOWN
, 0},
8296 { CODE_FOR_mmachs
, "__MMACHS", FRV_BUILTIN_MMACHS
, UNKNOWN
, 0},
8297 { CODE_FOR_mmachu
, "__MMACHU", FRV_BUILTIN_MMACHU
, UNKNOWN
, 0},
8298 { CODE_FOR_mmrdhs
, "__MMRDHS", FRV_BUILTIN_MMRDHS
, UNKNOWN
, 0},
8299 { CODE_FOR_mmrdhu
, "__MMRDHU", FRV_BUILTIN_MMRDHU
, UNKNOWN
, 0},
8300 { CODE_FOR_mqcpxrs
, "__MQCPXRS", FRV_BUILTIN_MQCPXRS
, UNKNOWN
, 0},
8301 { CODE_FOR_mqcpxru
, "__MQCPXRU", FRV_BUILTIN_MQCPXRU
, UNKNOWN
, 0},
8302 { CODE_FOR_mqcpxis
, "__MQCPXIS", FRV_BUILTIN_MQCPXIS
, UNKNOWN
, 0},
8303 { CODE_FOR_mqcpxiu
, "__MQCPXIU", FRV_BUILTIN_MQCPXIU
, UNKNOWN
, 0},
8304 { CODE_FOR_mqmulhs
, "__MQMULHS", FRV_BUILTIN_MQMULHS
, UNKNOWN
, 0},
8305 { CODE_FOR_mqmulhu
, "__MQMULHU", FRV_BUILTIN_MQMULHU
, UNKNOWN
, 0},
8306 { CODE_FOR_mqmulxhs
, "__MQMULXHS", FRV_BUILTIN_MQMULXHS
, UNKNOWN
, 0},
8307 { CODE_FOR_mqmulxhu
, "__MQMULXHU", FRV_BUILTIN_MQMULXHU
, UNKNOWN
, 0},
8308 { CODE_FOR_mqmachs
, "__MQMACHS", FRV_BUILTIN_MQMACHS
, UNKNOWN
, 0},
8309 { CODE_FOR_mqmachu
, "__MQMACHU", FRV_BUILTIN_MQMACHU
, UNKNOWN
, 0},
8310 { CODE_FOR_mqxmachs
, "__MQXMACHS", FRV_BUILTIN_MQXMACHS
, UNKNOWN
, 0},
8311 { CODE_FOR_mqxmacxhs
, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS
, UNKNOWN
, 0},
8312 { CODE_FOR_mqmacxhs
, "__MQMACXHS", FRV_BUILTIN_MQMACXHS
, UNKNOWN
, 0}
8315 /* Media intrinsics that take two accumulator numbers as argument and
8318 static struct builtin_description bdesc_voidacc
[] =
8320 { CODE_FOR_maddaccs
, "__MADDACCS", FRV_BUILTIN_MADDACCS
, UNKNOWN
, 0},
8321 { CODE_FOR_msubaccs
, "__MSUBACCS", FRV_BUILTIN_MSUBACCS
, UNKNOWN
, 0},
8322 { CODE_FOR_masaccs
, "__MASACCS", FRV_BUILTIN_MASACCS
, UNKNOWN
, 0},
8323 { CODE_FOR_mdaddaccs
, "__MDADDACCS", FRV_BUILTIN_MDADDACCS
, UNKNOWN
, 0},
8324 { CODE_FOR_mdsubaccs
, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS
, UNKNOWN
, 0},
8325 { CODE_FOR_mdasaccs
, "__MDASACCS", FRV_BUILTIN_MDASACCS
, UNKNOWN
, 0}
8328 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8329 a normal move and the ICODE is for the membar. */
8331 static struct builtin_description bdesc_loads
[] =
8333 { CODE_FOR_optional_membar_qi
, "__builtin_read8",
8334 FRV_BUILTIN_READ8
, UNKNOWN
, 0},
8335 { CODE_FOR_optional_membar_hi
, "__builtin_read16",
8336 FRV_BUILTIN_READ16
, UNKNOWN
, 0},
8337 { CODE_FOR_optional_membar_si
, "__builtin_read32",
8338 FRV_BUILTIN_READ32
, UNKNOWN
, 0},
8339 { CODE_FOR_optional_membar_di
, "__builtin_read64",
8340 FRV_BUILTIN_READ64
, UNKNOWN
, 0}
8343 /* Likewise stores. */
8345 static struct builtin_description bdesc_stores
[] =
8347 { CODE_FOR_optional_membar_qi
, "__builtin_write8",
8348 FRV_BUILTIN_WRITE8
, UNKNOWN
, 0},
8349 { CODE_FOR_optional_membar_hi
, "__builtin_write16",
8350 FRV_BUILTIN_WRITE16
, UNKNOWN
, 0},
8351 { CODE_FOR_optional_membar_si
, "__builtin_write32",
8352 FRV_BUILTIN_WRITE32
, UNKNOWN
, 0},
8353 { CODE_FOR_optional_membar_di
, "__builtin_write64",
8354 FRV_BUILTIN_WRITE64
, UNKNOWN
, 0},
8357 /* Initialize media builtins. */
8360 frv_init_builtins (void)
8362 tree accumulator
= integer_type_node
;
8363 tree integer
= integer_type_node
;
8364 tree voidt
= void_type_node
;
8365 tree uhalf
= short_unsigned_type_node
;
8366 tree sword1
= long_integer_type_node
;
8367 tree uword1
= long_unsigned_type_node
;
8368 tree sword2
= long_long_integer_type_node
;
8369 tree uword2
= long_long_unsigned_type_node
;
8370 tree uword4
= build_pointer_type (uword1
);
8371 tree vptr
= build_pointer_type (build_type_variant (void_type_node
, 0, 1));
8372 tree ubyte
= unsigned_char_type_node
;
8373 tree iacc
= integer_type_node
;
8375 #define UNARY(RET, T1) \
8376 build_function_type_list (RET, T1, NULL_TREE)
8378 #define BINARY(RET, T1, T2) \
8379 build_function_type_list (RET, T1, T2, NULL_TREE)
8381 #define TRINARY(RET, T1, T2, T3) \
8382 build_function_type_list (RET, T1, T2, T3, NULL_TREE)
8384 #define QUAD(RET, T1, T2, T3, T4) \
8385 build_function_type_list (RET, T1, T2, T3, T4, NULL_TREE)
8387 tree void_ftype_void
= build_function_type_list (voidt
, NULL_TREE
);
8389 tree void_ftype_acc
= UNARY (voidt
, accumulator
);
8390 tree void_ftype_uw4_uw1
= BINARY (voidt
, uword4
, uword1
);
8391 tree void_ftype_uw4_uw2
= BINARY (voidt
, uword4
, uword2
);
8392 tree void_ftype_acc_uw1
= BINARY (voidt
, accumulator
, uword1
);
8393 tree void_ftype_acc_acc
= BINARY (voidt
, accumulator
, accumulator
);
8394 tree void_ftype_acc_uw1_uw1
= TRINARY (voidt
, accumulator
, uword1
, uword1
);
8395 tree void_ftype_acc_sw1_sw1
= TRINARY (voidt
, accumulator
, sword1
, sword1
);
8396 tree void_ftype_acc_uw2_uw2
= TRINARY (voidt
, accumulator
, uword2
, uword2
);
8397 tree void_ftype_acc_sw2_sw2
= TRINARY (voidt
, accumulator
, sword2
, sword2
);
8399 tree uw1_ftype_uw1
= UNARY (uword1
, uword1
);
8400 tree uw1_ftype_sw1
= UNARY (uword1
, sword1
);
8401 tree uw1_ftype_uw2
= UNARY (uword1
, uword2
);
8402 tree uw1_ftype_acc
= UNARY (uword1
, accumulator
);
8403 tree uw1_ftype_uh_uh
= BINARY (uword1
, uhalf
, uhalf
);
8404 tree uw1_ftype_uw1_uw1
= BINARY (uword1
, uword1
, uword1
);
8405 tree uw1_ftype_uw1_int
= BINARY (uword1
, uword1
, integer
);
8406 tree uw1_ftype_acc_uw1
= BINARY (uword1
, accumulator
, uword1
);
8407 tree uw1_ftype_acc_sw1
= BINARY (uword1
, accumulator
, sword1
);
8408 tree uw1_ftype_uw2_uw1
= BINARY (uword1
, uword2
, uword1
);
8409 tree uw1_ftype_uw2_int
= BINARY (uword1
, uword2
, integer
);
8411 tree sw1_ftype_int
= UNARY (sword1
, integer
);
8412 tree sw1_ftype_sw1_sw1
= BINARY (sword1
, sword1
, sword1
);
8413 tree sw1_ftype_sw1_int
= BINARY (sword1
, sword1
, integer
);
8415 tree uw2_ftype_uw1
= UNARY (uword2
, uword1
);
8416 tree uw2_ftype_uw1_int
= BINARY (uword2
, uword1
, integer
);
8417 tree uw2_ftype_uw2_uw2
= BINARY (uword2
, uword2
, uword2
);
8418 tree uw2_ftype_uw2_int
= BINARY (uword2
, uword2
, integer
);
8419 tree uw2_ftype_acc_int
= BINARY (uword2
, accumulator
, integer
);
8420 tree uw2_ftype_uh_uh_uh_uh
= QUAD (uword2
, uhalf
, uhalf
, uhalf
, uhalf
);
8422 tree sw2_ftype_sw2_sw2
= BINARY (sword2
, sword2
, sword2
);
8423 tree sw2_ftype_sw2_int
= BINARY (sword2
, sword2
, integer
);
8424 tree uw2_ftype_uw1_uw1
= BINARY (uword2
, uword1
, uword1
);
8425 tree sw2_ftype_sw1_sw1
= BINARY (sword2
, sword1
, sword1
);
8426 tree void_ftype_sw1_sw1
= BINARY (voidt
, sword1
, sword1
);
8427 tree void_ftype_iacc_sw2
= BINARY (voidt
, iacc
, sword2
);
8428 tree void_ftype_iacc_sw1
= BINARY (voidt
, iacc
, sword1
);
8429 tree sw1_ftype_sw1
= UNARY (sword1
, sword1
);
8430 tree sw2_ftype_iacc
= UNARY (sword2
, iacc
);
8431 tree sw1_ftype_iacc
= UNARY (sword1
, iacc
);
8432 tree void_ftype_ptr
= UNARY (voidt
, const_ptr_type_node
);
8433 tree uw1_ftype_vptr
= UNARY (uword1
, vptr
);
8434 tree uw2_ftype_vptr
= UNARY (uword2
, vptr
);
8435 tree void_ftype_vptr_ub
= BINARY (voidt
, vptr
, ubyte
);
8436 tree void_ftype_vptr_uh
= BINARY (voidt
, vptr
, uhalf
);
8437 tree void_ftype_vptr_uw1
= BINARY (voidt
, vptr
, uword1
);
8438 tree void_ftype_vptr_uw2
= BINARY (voidt
, vptr
, uword2
);
8440 def_builtin ("__MAND", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAND
);
8441 def_builtin ("__MOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MOR
);
8442 def_builtin ("__MXOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MXOR
);
8443 def_builtin ("__MNOT", uw1_ftype_uw1
, FRV_BUILTIN_MNOT
);
8444 def_builtin ("__MROTLI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTLI
);
8445 def_builtin ("__MROTRI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTRI
);
8446 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1
, FRV_BUILTIN_MWCUT
);
8447 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAVEH
);
8448 def_builtin ("__MSLLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSLLHI
);
8449 def_builtin ("__MSRLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSRLHI
);
8450 def_builtin ("__MSRAHI", sw1_ftype_sw1_int
, FRV_BUILTIN_MSRAHI
);
8451 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSATHS
);
8452 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSATHU
);
8453 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MADDHSS
);
8454 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MADDHUS
);
8455 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSUBHSS
);
8456 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSUBHUS
);
8457 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULHS
);
8458 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULHU
);
8459 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULXHS
);
8460 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULXHU
);
8461 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMACHS
);
8462 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMACHU
);
8463 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMRDHS
);
8464 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMRDHU
);
8465 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQADDHSS
);
8466 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQADDHUS
);
8467 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSUBHSS
);
8468 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQSUBHUS
);
8469 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULHS
);
8470 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULHU
);
8471 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULXHS
);
8472 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULXHU
);
8473 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACHS
);
8474 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMACHU
);
8475 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXRS
);
8476 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXRU
);
8477 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXIS
);
8478 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXIU
);
8479 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXRS
);
8480 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXRU
);
8481 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXIS
);
8482 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXIU
);
8483 def_builtin ("__MCUT", uw1_ftype_acc_uw1
, FRV_BUILTIN_MCUT
);
8484 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1
, FRV_BUILTIN_MCUTSS
);
8485 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int
, FRV_BUILTIN_MEXPDHW
);
8486 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int
, FRV_BUILTIN_MEXPDHD
);
8487 def_builtin ("__MPACKH", uw1_ftype_uh_uh
, FRV_BUILTIN_MPACKH
);
8488 def_builtin ("__MUNPACKH", uw2_ftype_uw1
, FRV_BUILTIN_MUNPACKH
);
8489 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh
, FRV_BUILTIN_MDPACKH
);
8490 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2
, FRV_BUILTIN_MDUNPACKH
);
8491 def_builtin ("__MBTOH", uw2_ftype_uw1
, FRV_BUILTIN_MBTOH
);
8492 def_builtin ("__MHTOB", uw1_ftype_uw2
, FRV_BUILTIN_MHTOB
);
8493 def_builtin ("__MBTOHE", void_ftype_uw4_uw1
, FRV_BUILTIN_MBTOHE
);
8494 def_builtin ("__MCLRACC", void_ftype_acc
, FRV_BUILTIN_MCLRACC
);
8495 def_builtin ("__MCLRACCA", void_ftype_void
, FRV_BUILTIN_MCLRACCA
);
8496 def_builtin ("__MRDACC", uw1_ftype_acc
, FRV_BUILTIN_MRDACC
);
8497 def_builtin ("__MRDACCG", uw1_ftype_acc
, FRV_BUILTIN_MRDACCG
);
8498 def_builtin ("__MWTACC", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACC
);
8499 def_builtin ("__MWTACCG", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACCG
);
8500 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP1
);
8501 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP2
);
8502 def_builtin ("__MTRAP", void_ftype_void
, FRV_BUILTIN_MTRAP
);
8503 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACHS
);
8504 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACXHS
);
8505 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACXHS
);
8506 def_builtin ("__MADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MADDACCS
);
8507 def_builtin ("__MSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MSUBACCS
);
8508 def_builtin ("__MASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MASACCS
);
8509 def_builtin ("__MDADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDADDACCS
);
8510 def_builtin ("__MDSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDSUBACCS
);
8511 def_builtin ("__MDASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDASACCS
);
8512 def_builtin ("__MABSHS", uw1_ftype_sw1
, FRV_BUILTIN_MABSHS
);
8513 def_builtin ("__MDROTLI", uw2_ftype_uw2_int
, FRV_BUILTIN_MDROTLI
);
8514 def_builtin ("__MCPLHI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLHI
);
8515 def_builtin ("__MCPLI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLI
);
8516 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int
, FRV_BUILTIN_MDCUTSSI
);
8517 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSATHS
);
8518 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETLOS
);
8519 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETHIS
);
8520 def_builtin ("__MHDSETS", sw1_ftype_int
, FRV_BUILTIN_MHDSETS
);
8521 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETLOH
);
8522 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETHIH
);
8523 def_builtin ("__MHDSETH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHDSETH
);
8524 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLCLRHS
);
8525 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLMTHS
);
8526 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int
, FRV_BUILTIN_MQSLLHI
);
8527 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int
, FRV_BUILTIN_MQSRAHI
);
8528 def_builtin ("__SMUL", sw2_ftype_sw1_sw1
, FRV_BUILTIN_SMUL
);
8529 def_builtin ("__UMUL", uw2_ftype_uw1_uw1
, FRV_BUILTIN_UMUL
);
8530 def_builtin ("__SMASS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMASS
);
8531 def_builtin ("__SMSSS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMSSS
);
8532 def_builtin ("__SMU", void_ftype_sw1_sw1
, FRV_BUILTIN_SMU
);
8533 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_ADDSS
);
8534 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SUBSS
);
8535 def_builtin ("__SLASS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SLASS
);
8536 def_builtin ("__SCAN", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SCAN
);
8537 def_builtin ("__SCUTSS", sw1_ftype_sw1
, FRV_BUILTIN_SCUTSS
);
8538 def_builtin ("__IACCreadll", sw2_ftype_iacc
, FRV_BUILTIN_IACCreadll
);
8539 def_builtin ("__IACCreadl", sw1_ftype_iacc
, FRV_BUILTIN_IACCreadl
);
8540 def_builtin ("__IACCsetll", void_ftype_iacc_sw2
, FRV_BUILTIN_IACCsetll
);
8541 def_builtin ("__IACCsetl", void_ftype_iacc_sw1
, FRV_BUILTIN_IACCsetl
);
8542 def_builtin ("__data_prefetch0", void_ftype_ptr
, FRV_BUILTIN_PREFETCH0
);
8543 def_builtin ("__data_prefetch", void_ftype_ptr
, FRV_BUILTIN_PREFETCH
);
8544 def_builtin ("__builtin_read8", uw1_ftype_vptr
, FRV_BUILTIN_READ8
);
8545 def_builtin ("__builtin_read16", uw1_ftype_vptr
, FRV_BUILTIN_READ16
);
8546 def_builtin ("__builtin_read32", uw1_ftype_vptr
, FRV_BUILTIN_READ32
);
8547 def_builtin ("__builtin_read64", uw2_ftype_vptr
, FRV_BUILTIN_READ64
);
8549 def_builtin ("__builtin_write8", void_ftype_vptr_ub
, FRV_BUILTIN_WRITE8
);
8550 def_builtin ("__builtin_write16", void_ftype_vptr_uh
, FRV_BUILTIN_WRITE16
);
8551 def_builtin ("__builtin_write32", void_ftype_vptr_uw1
, FRV_BUILTIN_WRITE32
);
8552 def_builtin ("__builtin_write64", void_ftype_vptr_uw2
, FRV_BUILTIN_WRITE64
);
8560 /* Set the names for various arithmetic operations according to the
8563 frv_init_libfuncs (void)
8565 set_optab_libfunc (smod_optab
, SImode
, "__modi");
8566 set_optab_libfunc (umod_optab
, SImode
, "__umodi");
8568 set_optab_libfunc (add_optab
, DImode
, "__addll");
8569 set_optab_libfunc (sub_optab
, DImode
, "__subll");
8570 set_optab_libfunc (smul_optab
, DImode
, "__mulll");
8571 set_optab_libfunc (sdiv_optab
, DImode
, "__divll");
8572 set_optab_libfunc (smod_optab
, DImode
, "__modll");
8573 set_optab_libfunc (umod_optab
, DImode
, "__umodll");
8574 set_optab_libfunc (and_optab
, DImode
, "__andll");
8575 set_optab_libfunc (ior_optab
, DImode
, "__orll");
8576 set_optab_libfunc (xor_optab
, DImode
, "__xorll");
8577 set_optab_libfunc (one_cmpl_optab
, DImode
, "__notll");
8579 set_optab_libfunc (add_optab
, SFmode
, "__addf");
8580 set_optab_libfunc (sub_optab
, SFmode
, "__subf");
8581 set_optab_libfunc (smul_optab
, SFmode
, "__mulf");
8582 set_optab_libfunc (sdiv_optab
, SFmode
, "__divf");
8584 set_optab_libfunc (add_optab
, DFmode
, "__addd");
8585 set_optab_libfunc (sub_optab
, DFmode
, "__subd");
8586 set_optab_libfunc (smul_optab
, DFmode
, "__muld");
8587 set_optab_libfunc (sdiv_optab
, DFmode
, "__divd");
8589 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__ftod");
8590 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__dtof");
8592 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__ftoi");
8593 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
8594 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__dtoi");
8595 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
8597 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__ftoui");
8598 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
8599 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__dtoui");
8600 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
8602 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__itof");
8603 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__lltof");
8604 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__itod");
8605 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__lltod");
8608 /* Convert an integer constant to an accumulator register. ICODE is the
8609 code of the target instruction, OPNUM is the number of the
8610 accumulator operand and OPVAL is the constant integer. Try both
8611 ACC and ACCG registers; only report an error if neither fit the
8615 frv_int_to_acc (enum insn_code icode
, int opnum
, rtx opval
)
8620 /* ACCs and ACCGs are implicit global registers if media intrinsics
8621 are being used. We set up this lazily to avoid creating lots of
8622 unnecessary call_insn rtl in non-media code. */
8623 for (i
= 0; i
<= ACC_MASK
; i
++)
8624 if ((i
& ACC_MASK
) == i
)
8625 global_regs
[i
+ ACC_FIRST
] = global_regs
[i
+ ACCG_FIRST
] = 1;
8627 if (GET_CODE (opval
) != CONST_INT
)
8629 error ("accumulator is not a constant integer");
8632 if ((INTVAL (opval
) & ~ACC_MASK
) != 0)
8634 error ("accumulator number is out of bounds");
8638 reg
= gen_rtx_REG (insn_data
[icode
].operand
[opnum
].mode
,
8639 ACC_FIRST
+ INTVAL (opval
));
8640 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8641 SET_REGNO (reg
, ACCG_FIRST
+ INTVAL (opval
));
8643 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8645 error ("inappropriate accumulator for %qs", insn_data
[icode
].name
);
8651 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8655 frv_matching_accg_mode (machine_mode mode
)
8673 /* Given that a __builtin_read or __builtin_write function is accessing
8674 address ADDRESS, return the value that should be used as operand 1
8678 frv_io_address_cookie (rtx address
)
8680 return (GET_CODE (address
) == CONST_INT
8681 ? GEN_INT (INTVAL (address
) / 8 * 8)
8685 /* Return the accumulator guard that should be paired with accumulator
8686 register ACC. The mode of the returned register is in the same
8687 class as ACC, but is four times smaller. */
8690 frv_matching_accg_for_acc (rtx acc
)
8692 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc
)),
8693 REGNO (acc
) - ACC_FIRST
+ ACCG_FIRST
);
8696 /* Read the requested argument from the call EXP given by INDEX.
8697 Return the value as an rtx. */
8700 frv_read_argument (tree exp
, unsigned int index
)
8702 return expand_normal (CALL_EXPR_ARG (exp
, index
));
8705 /* Like frv_read_argument, but interpret the argument as the number
8706 of an IACC register and return a (reg:MODE ...) rtx for it. */
8709 frv_read_iacc_argument (machine_mode mode
, tree call
,
8715 op
= frv_read_argument (call
, index
);
8716 if (GET_CODE (op
) != CONST_INT
8718 || INTVAL (op
) > IACC_LAST
- IACC_FIRST
8719 || ((INTVAL (op
) * 4) & (GET_MODE_SIZE (mode
) - 1)) != 0)
8721 error ("invalid IACC argument");
8725 /* IACCs are implicit global registers. We set up this lazily to
8726 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8728 regno
= INTVAL (op
) + IACC_FIRST
;
8729 for (i
= 0; i
< HARD_REGNO_NREGS (regno
, mode
); i
++)
8730 global_regs
[regno
+ i
] = 1;
8732 return gen_rtx_REG (mode
, regno
);
8735 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8736 The instruction should require a constant operand of some sort. The
8737 function prints an error if OPVAL is not valid. */
8740 frv_check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
8742 if (GET_CODE (opval
) != CONST_INT
)
8744 error ("%qs expects a constant argument", insn_data
[icode
].name
);
8747 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
8749 error ("constant argument out of range for %qs", insn_data
[icode
].name
);
8755 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8756 if it's not null, has the right mode, and satisfies operand 0's
8760 frv_legitimize_target (enum insn_code icode
, rtx target
)
8762 machine_mode mode
= insn_data
[icode
].operand
[0].mode
;
8765 || GET_MODE (target
) != mode
8766 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
8767 return gen_reg_rtx (mode
);
8772 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8773 check whether ARG satisfies the operand's constraints. If it doesn't,
8774 copy ARG to a temporary register and return that. Otherwise return ARG
8778 frv_legitimize_argument (enum insn_code icode
, int opnum
, rtx arg
)
8780 machine_mode mode
= insn_data
[icode
].operand
[opnum
].mode
;
8782 if ((*insn_data
[icode
].operand
[opnum
].predicate
) (arg
, mode
))
8785 return copy_to_mode_reg (mode
, arg
);
8788 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8791 frv_volatile_memref (machine_mode mode
, rtx arg
)
8795 mem
= gen_rtx_MEM (mode
, memory_address (mode
, arg
));
8796 MEM_VOLATILE_P (mem
) = 1;
8800 /* Expand builtins that take a single, constant argument. At the moment,
8801 only MHDSETS falls into this category. */
8804 frv_expand_set_builtin (enum insn_code icode
, tree call
, rtx target
)
8807 rtx op0
= frv_read_argument (call
, 0);
8809 if (! frv_check_constant_argument (icode
, 1, op0
))
8812 target
= frv_legitimize_target (icode
, target
);
8813 pat
= GEN_FCN (icode
) (target
, op0
);
8821 /* Expand builtins that take one operand. */
8824 frv_expand_unop_builtin (enum insn_code icode
, tree call
, rtx target
)
8827 rtx op0
= frv_read_argument (call
, 0);
8829 target
= frv_legitimize_target (icode
, target
);
8830 op0
= frv_legitimize_argument (icode
, 1, op0
);
8831 pat
= GEN_FCN (icode
) (target
, op0
);
8839 /* Expand builtins that take two operands. */
8842 frv_expand_binop_builtin (enum insn_code icode
, tree call
, rtx target
)
8845 rtx op0
= frv_read_argument (call
, 0);
8846 rtx op1
= frv_read_argument (call
, 1);
8848 target
= frv_legitimize_target (icode
, target
);
8849 op0
= frv_legitimize_argument (icode
, 1, op0
);
8850 op1
= frv_legitimize_argument (icode
, 2, op1
);
8851 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8859 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8863 frv_expand_cut_builtin (enum insn_code icode
, tree call
, rtx target
)
8866 rtx op0
= frv_read_argument (call
, 0);
8867 rtx op1
= frv_read_argument (call
, 1);
8870 target
= frv_legitimize_target (icode
, target
);
8871 op0
= frv_int_to_acc (icode
, 1, op0
);
8875 if (icode
== CODE_FOR_mdcutssi
|| GET_CODE (op1
) == CONST_INT
)
8877 if (! frv_check_constant_argument (icode
, 2, op1
))
8881 op1
= frv_legitimize_argument (icode
, 2, op1
);
8883 op2
= frv_matching_accg_for_acc (op0
);
8884 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
8892 /* Expand builtins that take two operands and the second is immediate. */
8895 frv_expand_binopimm_builtin (enum insn_code icode
, tree call
, rtx target
)
8898 rtx op0
= frv_read_argument (call
, 0);
8899 rtx op1
= frv_read_argument (call
, 1);
8901 if (! frv_check_constant_argument (icode
, 2, op1
))
8904 target
= frv_legitimize_target (icode
, target
);
8905 op0
= frv_legitimize_argument (icode
, 1, op0
);
8906 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8914 /* Expand builtins that take two operands, the first operand being a pointer to
8915 ints and return void. */
8918 frv_expand_voidbinop_builtin (enum insn_code icode
, tree call
)
8921 rtx op0
= frv_read_argument (call
, 0);
8922 rtx op1
= frv_read_argument (call
, 1);
8923 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
8926 if (GET_CODE (op0
) != MEM
)
8930 if (! offsettable_address_p (0, mode0
, op0
))
8932 reg
= gen_reg_rtx (Pmode
);
8933 emit_insn (gen_rtx_SET (VOIDmode
, reg
, op0
));
8936 op0
= gen_rtx_MEM (SImode
, reg
);
8939 addr
= XEXP (op0
, 0);
8940 if (! offsettable_address_p (0, mode0
, addr
))
8941 addr
= copy_to_mode_reg (Pmode
, op0
);
8943 op0
= change_address (op0
, V4SImode
, addr
);
8944 op1
= frv_legitimize_argument (icode
, 1, op1
);
8945 pat
= GEN_FCN (icode
) (op0
, op1
);
8953 /* Expand builtins that take two long operands and return void. */
8956 frv_expand_int_void2arg (enum insn_code icode
, tree call
)
8959 rtx op0
= frv_read_argument (call
, 0);
8960 rtx op1
= frv_read_argument (call
, 1);
8962 op0
= frv_legitimize_argument (icode
, 1, op0
);
8963 op1
= frv_legitimize_argument (icode
, 1, op1
);
8964 pat
= GEN_FCN (icode
) (op0
, op1
);
8972 /* Expand prefetch builtins. These take a single address as argument. */
8975 frv_expand_prefetches (enum insn_code icode
, tree call
)
8978 rtx op0
= frv_read_argument (call
, 0);
8980 pat
= GEN_FCN (icode
) (force_reg (Pmode
, op0
));
8988 /* Expand builtins that take three operands and return void. The first
8989 argument must be a constant that describes a pair or quad accumulators. A
8990 fourth argument is created that is the accumulator guard register that
8991 corresponds to the accumulator. */
8994 frv_expand_voidtriop_builtin (enum insn_code icode
, tree call
)
8997 rtx op0
= frv_read_argument (call
, 0);
8998 rtx op1
= frv_read_argument (call
, 1);
8999 rtx op2
= frv_read_argument (call
, 2);
9002 op0
= frv_int_to_acc (icode
, 0, op0
);
9006 op1
= frv_legitimize_argument (icode
, 1, op1
);
9007 op2
= frv_legitimize_argument (icode
, 2, op2
);
9008 op3
= frv_matching_accg_for_acc (op0
);
9009 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9017 /* Expand builtins that perform accumulator-to-accumulator operations.
9018 These builtins take two accumulator numbers as argument and return
9022 frv_expand_voidaccop_builtin (enum insn_code icode
, tree call
)
9025 rtx op0
= frv_read_argument (call
, 0);
9026 rtx op1
= frv_read_argument (call
, 1);
9030 op0
= frv_int_to_acc (icode
, 0, op0
);
9034 op1
= frv_int_to_acc (icode
, 1, op1
);
9038 op2
= frv_matching_accg_for_acc (op0
);
9039 op3
= frv_matching_accg_for_acc (op1
);
9040 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9048 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9049 membar and TARGET_MODE is the mode that the loaded value should have. */
9052 frv_expand_load_builtin (enum insn_code icode
, machine_mode target_mode
,
9053 tree call
, rtx target
)
9055 rtx op0
= frv_read_argument (call
, 0);
9056 rtx cookie
= frv_io_address_cookie (op0
);
9058 if (target
== 0 || !REG_P (target
))
9059 target
= gen_reg_rtx (target_mode
);
9060 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9061 convert_move (target
, op0
, 1);
9062 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_READ
)));
9063 cfun
->machine
->has_membar_p
= 1;
9067 /* Likewise __builtin_write* functions. */
9070 frv_expand_store_builtin (enum insn_code icode
, tree call
)
9072 rtx op0
= frv_read_argument (call
, 0);
9073 rtx op1
= frv_read_argument (call
, 1);
9074 rtx cookie
= frv_io_address_cookie (op0
);
9076 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9077 convert_move (op0
, force_reg (insn_data
[icode
].operand
[0].mode
, op1
), 1);
9078 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_WRITE
)));
9079 cfun
->machine
->has_membar_p
= 1;
9083 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9084 each argument forms one word of the two double-word input registers.
9085 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9086 to put the return value. */
9089 frv_expand_mdpackh_builtin (tree call
, rtx target
)
9091 enum insn_code icode
= CODE_FOR_mdpackh
;
9093 rtx arg1
= frv_read_argument (call
, 0);
9094 rtx arg2
= frv_read_argument (call
, 1);
9095 rtx arg3
= frv_read_argument (call
, 2);
9096 rtx arg4
= frv_read_argument (call
, 3);
9098 target
= frv_legitimize_target (icode
, target
);
9099 op0
= gen_reg_rtx (DImode
);
9100 op1
= gen_reg_rtx (DImode
);
9102 /* The high half of each word is not explicitly initialized, so indicate
9103 that the input operands are not live before this point. */
9107 /* Move each argument into the low half of its associated input word. */
9108 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 2), arg1
);
9109 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 6), arg2
);
9110 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 2), arg3
);
9111 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 6), arg4
);
9113 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9121 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9122 number as argument. */
9125 frv_expand_mclracc_builtin (tree call
)
9127 enum insn_code icode
= CODE_FOR_mclracc
;
9129 rtx op0
= frv_read_argument (call
, 0);
9131 op0
= frv_int_to_acc (icode
, 0, op0
);
9135 pat
= GEN_FCN (icode
) (op0
);
9142 /* Expand builtins that take no arguments. */
9145 frv_expand_noargs_builtin (enum insn_code icode
)
9147 rtx pat
= GEN_FCN (icode
) (const0_rtx
);
9154 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9155 number or accumulator guard number as argument and return an SI integer. */
9158 frv_expand_mrdacc_builtin (enum insn_code icode
, tree call
)
9161 rtx target
= gen_reg_rtx (SImode
);
9162 rtx op0
= frv_read_argument (call
, 0);
9164 op0
= frv_int_to_acc (icode
, 1, op0
);
9168 pat
= GEN_FCN (icode
) (target
, op0
);
9176 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9177 accumulator guard as their first argument and an SImode value as their
9181 frv_expand_mwtacc_builtin (enum insn_code icode
, tree call
)
9184 rtx op0
= frv_read_argument (call
, 0);
9185 rtx op1
= frv_read_argument (call
, 1);
9187 op0
= frv_int_to_acc (icode
, 0, op0
);
9191 op1
= frv_legitimize_argument (icode
, 1, op1
);
9192 pat
= GEN_FCN (icode
) (op0
, op1
);
9199 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9200 to move DImode values into and out of IACC0. */
9203 frv_split_iacc_move (rtx dest
, rtx src
)
9208 inner
= GET_MODE (dest
);
9209 for (i
= 0; i
< GET_MODE_SIZE (inner
); i
+= GET_MODE_SIZE (SImode
))
9210 emit_move_insn (simplify_gen_subreg (SImode
, dest
, inner
, i
),
9211 simplify_gen_subreg (SImode
, src
, inner
, i
));
9214 /* Expand builtins. */
9217 frv_expand_builtin (tree exp
,
9219 rtx subtarget ATTRIBUTE_UNUSED
,
9220 machine_mode mode ATTRIBUTE_UNUSED
,
9221 int ignore ATTRIBUTE_UNUSED
)
9223 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9224 unsigned fcode
= (unsigned)DECL_FUNCTION_CODE (fndecl
);
9226 struct builtin_description
*d
;
9228 if (fcode
< FRV_BUILTIN_FIRST_NONMEDIA
&& !TARGET_MEDIA
)
9230 error ("media functions are not available unless -mmedia is used");
9236 case FRV_BUILTIN_MCOP1
:
9237 case FRV_BUILTIN_MCOP2
:
9238 case FRV_BUILTIN_MDUNPACKH
:
9239 case FRV_BUILTIN_MBTOHE
:
9240 if (! TARGET_MEDIA_REV1
)
9242 error ("this media function is only available on the fr500");
9247 case FRV_BUILTIN_MQXMACHS
:
9248 case FRV_BUILTIN_MQXMACXHS
:
9249 case FRV_BUILTIN_MQMACXHS
:
9250 case FRV_BUILTIN_MADDACCS
:
9251 case FRV_BUILTIN_MSUBACCS
:
9252 case FRV_BUILTIN_MASACCS
:
9253 case FRV_BUILTIN_MDADDACCS
:
9254 case FRV_BUILTIN_MDSUBACCS
:
9255 case FRV_BUILTIN_MDASACCS
:
9256 case FRV_BUILTIN_MABSHS
:
9257 case FRV_BUILTIN_MDROTLI
:
9258 case FRV_BUILTIN_MCPLHI
:
9259 case FRV_BUILTIN_MCPLI
:
9260 case FRV_BUILTIN_MDCUTSSI
:
9261 case FRV_BUILTIN_MQSATHS
:
9262 case FRV_BUILTIN_MHSETLOS
:
9263 case FRV_BUILTIN_MHSETLOH
:
9264 case FRV_BUILTIN_MHSETHIS
:
9265 case FRV_BUILTIN_MHSETHIH
:
9266 case FRV_BUILTIN_MHDSETS
:
9267 case FRV_BUILTIN_MHDSETH
:
9268 if (! TARGET_MEDIA_REV2
)
9270 error ("this media function is only available on the fr400"
9276 case FRV_BUILTIN_SMASS
:
9277 case FRV_BUILTIN_SMSSS
:
9278 case FRV_BUILTIN_SMU
:
9279 case FRV_BUILTIN_ADDSS
:
9280 case FRV_BUILTIN_SUBSS
:
9281 case FRV_BUILTIN_SLASS
:
9282 case FRV_BUILTIN_SCUTSS
:
9283 case FRV_BUILTIN_IACCreadll
:
9284 case FRV_BUILTIN_IACCreadl
:
9285 case FRV_BUILTIN_IACCsetll
:
9286 case FRV_BUILTIN_IACCsetl
:
9287 if (!TARGET_FR405_BUILTINS
)
9289 error ("this builtin function is only available"
9290 " on the fr405 and fr450");
9295 case FRV_BUILTIN_PREFETCH
:
9296 if (!TARGET_FR500_FR550_BUILTINS
)
9298 error ("this builtin function is only available on the fr500"
9304 case FRV_BUILTIN_MQLCLRHS
:
9305 case FRV_BUILTIN_MQLMTHS
:
9306 case FRV_BUILTIN_MQSLLHI
:
9307 case FRV_BUILTIN_MQSRAHI
:
9308 if (!TARGET_MEDIA_FR450
)
9310 error ("this builtin function is only available on the fr450");
9319 /* Expand unique builtins. */
9323 case FRV_BUILTIN_MTRAP
:
9324 return frv_expand_noargs_builtin (CODE_FOR_mtrap
);
9326 case FRV_BUILTIN_MCLRACC
:
9327 return frv_expand_mclracc_builtin (exp
);
9329 case FRV_BUILTIN_MCLRACCA
:
9331 return frv_expand_noargs_builtin (CODE_FOR_mclracca8
);
9333 return frv_expand_noargs_builtin (CODE_FOR_mclracca4
);
9335 case FRV_BUILTIN_MRDACC
:
9336 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc
, exp
);
9338 case FRV_BUILTIN_MRDACCG
:
9339 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg
, exp
);
9341 case FRV_BUILTIN_MWTACC
:
9342 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc
, exp
);
9344 case FRV_BUILTIN_MWTACCG
:
9345 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg
, exp
);
9347 case FRV_BUILTIN_MDPACKH
:
9348 return frv_expand_mdpackh_builtin (exp
, target
);
9350 case FRV_BUILTIN_IACCreadll
:
9352 rtx src
= frv_read_iacc_argument (DImode
, exp
, 0);
9353 if (target
== 0 || !REG_P (target
))
9354 target
= gen_reg_rtx (DImode
);
9355 frv_split_iacc_move (target
, src
);
9359 case FRV_BUILTIN_IACCreadl
:
9360 return frv_read_iacc_argument (SImode
, exp
, 0);
9362 case FRV_BUILTIN_IACCsetll
:
9364 rtx dest
= frv_read_iacc_argument (DImode
, exp
, 0);
9365 rtx src
= frv_read_argument (exp
, 1);
9366 frv_split_iacc_move (dest
, force_reg (DImode
, src
));
9370 case FRV_BUILTIN_IACCsetl
:
9372 rtx dest
= frv_read_iacc_argument (SImode
, exp
, 0);
9373 rtx src
= frv_read_argument (exp
, 1);
9374 emit_move_insn (dest
, force_reg (SImode
, src
));
9382 /* Expand groups of builtins. */
9384 for (i
= 0, d
= bdesc_set
; i
< ARRAY_SIZE (bdesc_set
); i
++, d
++)
9385 if (d
->code
== fcode
)
9386 return frv_expand_set_builtin (d
->icode
, exp
, target
);
9388 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9389 if (d
->code
== fcode
)
9390 return frv_expand_unop_builtin (d
->icode
, exp
, target
);
9392 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9393 if (d
->code
== fcode
)
9394 return frv_expand_binop_builtin (d
->icode
, exp
, target
);
9396 for (i
= 0, d
= bdesc_cut
; i
< ARRAY_SIZE (bdesc_cut
); i
++, d
++)
9397 if (d
->code
== fcode
)
9398 return frv_expand_cut_builtin (d
->icode
, exp
, target
);
9400 for (i
= 0, d
= bdesc_2argimm
; i
< ARRAY_SIZE (bdesc_2argimm
); i
++, d
++)
9401 if (d
->code
== fcode
)
9402 return frv_expand_binopimm_builtin (d
->icode
, exp
, target
);
9404 for (i
= 0, d
= bdesc_void2arg
; i
< ARRAY_SIZE (bdesc_void2arg
); i
++, d
++)
9405 if (d
->code
== fcode
)
9406 return frv_expand_voidbinop_builtin (d
->icode
, exp
);
9408 for (i
= 0, d
= bdesc_void3arg
; i
< ARRAY_SIZE (bdesc_void3arg
); i
++, d
++)
9409 if (d
->code
== fcode
)
9410 return frv_expand_voidtriop_builtin (d
->icode
, exp
);
9412 for (i
= 0, d
= bdesc_voidacc
; i
< ARRAY_SIZE (bdesc_voidacc
); i
++, d
++)
9413 if (d
->code
== fcode
)
9414 return frv_expand_voidaccop_builtin (d
->icode
, exp
);
9416 for (i
= 0, d
= bdesc_int_void2arg
;
9417 i
< ARRAY_SIZE (bdesc_int_void2arg
); i
++, d
++)
9418 if (d
->code
== fcode
)
9419 return frv_expand_int_void2arg (d
->icode
, exp
);
9421 for (i
= 0, d
= bdesc_prefetches
;
9422 i
< ARRAY_SIZE (bdesc_prefetches
); i
++, d
++)
9423 if (d
->code
== fcode
)
9424 return frv_expand_prefetches (d
->icode
, exp
);
9426 for (i
= 0, d
= bdesc_loads
; i
< ARRAY_SIZE (bdesc_loads
); i
++, d
++)
9427 if (d
->code
== fcode
)
9428 return frv_expand_load_builtin (d
->icode
, TYPE_MODE (TREE_TYPE (exp
)),
9431 for (i
= 0, d
= bdesc_stores
; i
< ARRAY_SIZE (bdesc_stores
); i
++, d
++)
9432 if (d
->code
== fcode
)
9433 return frv_expand_store_builtin (d
->icode
, exp
);
9439 frv_in_small_data_p (const_tree decl
)
9442 const char *section_name
;
9444 /* Don't apply the -G flag to internal compiler structures. We
9445 should leave such structures in the main data section, partly
9446 for efficiency and partly because the size of some of them
9447 (such as C++ typeinfos) is not known until later. */
9448 if (TREE_CODE (decl
) != VAR_DECL
|| DECL_ARTIFICIAL (decl
))
9451 /* If we already know which section the decl should be in, see if
9452 it's a small data section. */
9453 section_name
= DECL_SECTION_NAME (decl
);
9456 if (frv_string_begins_with (section_name
, ".sdata"))
9458 if (frv_string_begins_with (section_name
, ".sbss"))
9463 size
= int_size_in_bytes (TREE_TYPE (decl
));
9464 if (size
> 0 && size
<= g_switch_value
)
9471 frv_rtx_costs (rtx x
,
9472 int code ATTRIBUTE_UNUSED
,
9473 int outer_code ATTRIBUTE_UNUSED
,
9474 int opno ATTRIBUTE_UNUSED
,
9476 bool speed ATTRIBUTE_UNUSED
)
9478 if (outer_code
== MEM
)
9480 /* Don't differentiate between memory addresses. All the ones
9481 we accept have equal cost. */
9482 *total
= COSTS_N_INSNS (0);
9489 /* Make 12-bit integers really cheap. */
9490 if (IN_RANGE (INTVAL (x
), -2048, 2047))
9501 *total
= COSTS_N_INSNS (2);
9515 if (GET_MODE (x
) == SImode
)
9516 *total
= COSTS_N_INSNS (1);
9517 else if (GET_MODE (x
) == DImode
)
9518 *total
= COSTS_N_INSNS (2);
9520 *total
= COSTS_N_INSNS (3);
9524 if (GET_MODE (x
) == SImode
)
9525 *total
= COSTS_N_INSNS (2);
9527 *total
= COSTS_N_INSNS (6); /* guess */
9534 *total
= COSTS_N_INSNS (18);
9538 *total
= COSTS_N_INSNS (3);
9547 frv_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9549 switch_to_section (ctors_section
);
9550 assemble_align (POINTER_SIZE
);
9553 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9558 assemble_integer_with_op ("\t.picptr\t", symbol
);
9562 frv_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9564 switch_to_section (dtors_section
);
9565 assemble_align (POINTER_SIZE
);
9568 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9573 assemble_integer_with_op ("\t.picptr\t", symbol
);
9576 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9579 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
9580 int incoming ATTRIBUTE_UNUSED
)
9582 return gen_rtx_REG (Pmode
, FRV_STRUCT_VALUE_REGNUM
);
9585 #define TLS_BIAS (2048 - 16)
9587 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9588 We need to emit DTP-relative relocations. */
9591 frv_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
9593 gcc_assert (size
== 4);
9594 fputs ("\t.picptr\ttlsmoff(", file
);
9595 /* We want the unbiased TLS offset, so add the bias to the
9596 expression, such that the implicit biasing cancels out. */
9597 output_addr_const (file
, plus_constant (Pmode
, x
, TLS_BIAS
));