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1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
68 #ifndef CHECK_STACK_LIMIT
69 #define CHECK_STACK_LIMIT (-1)
70 #endif
72 /* Return index of given mode in mult and division cost tables. */
73 #define MODE_INDEX(mode) \
74 ((mode) == QImode ? 0 \
75 : (mode) == HImode ? 1 \
76 : (mode) == SImode ? 2 \
77 : (mode) == DImode ? 3 \
78 : 4)
80 /* Processor costs (relative to an add) */
81 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
82 #define COSTS_N_BYTES(N) ((N) * 2)
84 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
86 const
109 in QImode, HImode and SImode.
110 Relative to reg-reg move (2). */
114 in SFmode, DFmode and XFmode */
116 in SFmode, DFmode and XFmode */
119 in SImode and DImode */
121 in SImode and DImode */
124 in SImode, DImode and TImode */
126 in SImode, DImode and TImode */
154 };
156 /* Processor costs (relative to an add) */
157 static const
180 in QImode, HImode and SImode.
181 Relative to reg-reg move (2). */
185 in SFmode, DFmode and XFmode */
187 in SFmode, DFmode and XFmode */
190 in SImode and DImode */
192 in SImode and DImode */
195 in SImode, DImode and TImode */
197 in SImode, DImode and TImode */
211 DUMMY_STRINGOP_ALGS},
213 DUMMY_STRINGOP_ALGS},
225 };
227 static const
250 in QImode, HImode and SImode.
251 Relative to reg-reg move (2). */
255 in SFmode, DFmode and XFmode */
257 in SFmode, DFmode and XFmode */
260 in SImode and DImode */
262 in SImode and DImode */
265 in SImode, DImode and TImode */
267 in SImode, DImode and TImode */
270 shared for code and data, so 4kB is
271 not really precise. */
283 DUMMY_STRINGOP_ALGS},
285 DUMMY_STRINGOP_ALGS},
297 };
299 static const
322 in QImode, HImode and SImode.
323 Relative to reg-reg move (2). */
327 in SFmode, DFmode and XFmode */
329 in SFmode, DFmode and XFmode */
332 in SImode and DImode */
334 in SImode and DImode */
337 in SImode, DImode and TImode */
339 in SImode, DImode and TImode */
353 DUMMY_STRINGOP_ALGS},
355 DUMMY_STRINGOP_ALGS},
367 };
369 static const
392 in QImode, HImode and SImode.
393 Relative to reg-reg move (2). */
397 in SFmode, DFmode and XFmode */
399 in SFmode, DFmode and XFmode */
402 in SImode and DImode */
404 in SImode and DImode */
407 in SImode, DImode and TImode */
409 in SImode, DImode and TImode */
422 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
423 (we ensure the alignment). For small blocks inline loop is still a
424 noticeable win, for bigger blocks either rep movsl or rep movsb is
425 way to go. Rep movsb has apparently more expensive startup time in CPU,
426 but after 4K the difference is down in the noise. */
430 DUMMY_STRINGOP_ALGS},
434 DUMMY_STRINGOP_ALGS},
446 };
448 static const
471 in QImode, HImode and SImode.
472 Relative to reg-reg move (2). */
476 in SFmode, DFmode and XFmode */
478 in SFmode, DFmode and XFmode */
482 in SImode and DImode */
484 in SImode and DImode */
487 in SImode, DImode and TImode */
489 in SImode, DImode and TImode */
503 DUMMY_STRINGOP_ALGS},
505 DUMMY_STRINGOP_ALGS},
517 };
519 static const
542 in QImode, HImode and SImode.
543 Relative to reg-reg move (2). */
547 in SFmode, DFmode and XFmode */
549 in SFmode, DFmode and XFmode */
552 in SImode and DImode */
554 in SImode and DImode */
557 in SImode, DImode and TImode */
559 in SImode, DImode and TImode */
563 have integrated l2 cache, but
564 optimizing for k6 is not important
565 enough to worry about that. */
576 DUMMY_STRINGOP_ALGS},
578 DUMMY_STRINGOP_ALGS},
590 };
592 static const
615 in QImode, HImode and SImode.
616 Relative to reg-reg move (2). */
620 in SFmode, DFmode and XFmode */
622 in SFmode, DFmode and XFmode */
625 in SImode and DImode */
627 in SImode and DImode */
630 in SImode, DImode and TImode */
632 in SImode, DImode and TImode */
645 /* For some reason, Athlon deals better with REP prefix (relative to loops)
646 compared to K8. Alignment becomes important after 8 bytes for memcpy and
647 128 bytes for memset. */
649 DUMMY_STRINGOP_ALGS},
651 DUMMY_STRINGOP_ALGS},
663 };
665 static const
688 in QImode, HImode and SImode.
689 Relative to reg-reg move (2). */
693 in SFmode, DFmode and XFmode */
695 in SFmode, DFmode and XFmode */
698 in SImode and DImode */
700 in SImode and DImode */
703 in SImode, DImode and TImode */
705 in SImode, DImode and TImode */
710 /* New AMD processors never drop prefetches; if they cannot be performed
711 immediately, they are queued. We set number of simultaneous prefetches
712 to a large constant to reflect this (it probably is not a good idea not
713 to limit number of prefetches at all, as their execution also takes some
714 time). */
723 /* K8 has optimized REP instruction for medium sized blocks, but for very
724 small blocks it is better to use loop. For large blocks, libcall can
725 do nontemporary accesses and beat inline considerably. */
745 };
769 in QImode, HImode and SImode.
770 Relative to reg-reg move (2). */
774 in SFmode, DFmode and XFmode */
776 in SFmode, DFmode and XFmode */
779 in SImode and DImode */
781 in SImode and DImode */
784 in SImode, DImode and TImode */
786 in SImode, DImode and TImode */
788 /* On K8:
789 MOVD reg64, xmmreg Double FSTORE 4
790 MOVD reg32, xmmreg Double FSTORE 4
791 On AMDFAM10:
792 MOVD reg64, xmmreg Double FADD 3
793 1/1 1/1
794 MOVD reg32, xmmreg Double FADD 3
795 1/1 1/1 */
799 /* New AMD processors never drop prefetches; if they cannot be performed
800 immediately, they are queued. We set number of simultaneous prefetches
801 to a large constant to reflect this (it probably is not a good idea not
802 to limit number of prefetches at all, as their execution also takes some
803 time). */
813 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
814 very small blocks it is better to use loop. For large blocks, libcall can
815 do nontemporary accesses and beat inline considerably. */
835 };
859 in QImode, HImode and SImode.
860 Relative to reg-reg move (2). */
864 in SFmode, DFmode and XFmode */
866 in SFmode, DFmode and XFmode */
869 in SImode and DImode */
871 in SImode and DImode */
874 in SImode, DImode and TImode */
876 in SImode, DImode and TImode */
878 /* On K8:
879 MOVD reg64, xmmreg Double FSTORE 4
880 MOVD reg32, xmmreg Double FSTORE 4
881 On AMDFAM10:
882 MOVD reg64, xmmreg Double FADD 3
883 1/1 1/1
884 MOVD reg32, xmmreg Double FADD 3
885 1/1 1/1 */
889 /* New AMD processors never drop prefetches; if they cannot be performed
890 immediately, they are queued. We set number of simultaneous prefetches
891 to a large constant to reflect this (it probably is not a good idea not
892 to limit number of prefetches at all, as their execution also takes some
893 time). */
903 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
904 very small blocks it is better to use loop. For large blocks, libcall
905 can do nontemporary accesses and beat inline considerably. */
925 };
949 in QImode, HImode and SImode.
950 Relative to reg-reg move (2). */
954 in SFmode, DFmode and XFmode */
956 in SFmode, DFmode and XFmode */
959 in SImode and DImode */
961 in SImode and DImode */
964 in SImode, DImode and TImode */
966 in SImode, DImode and TImode */
968 /* On K8:
969 MOVD reg64, xmmreg Double FSTORE 4
970 MOVD reg32, xmmreg Double FSTORE 4
971 On AMDFAM10:
972 MOVD reg64, xmmreg Double FADD 3
973 1/1 1/1
974 MOVD reg32, xmmreg Double FADD 3
975 1/1 1/1 */
979 /* New AMD processors never drop prefetches; if they cannot be performed
980 immediately, they are queued. We set number of simultaneous prefetches
981 to a large constant to reflect this (it probably is not a good idea not
982 to limit number of prefetches at all, as their execution also takes some
983 time). */
993 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
994 very small blocks it is better to use loop. For large blocks, libcall
995 can do nontemporary accesses and beat inline considerably. */
1015 };
1039 in QImode, HImode and SImode.
1040 Relative to reg-reg move (2). */
1044 in SFmode, DFmode and XFmode */
1046 in SFmode, DFmode and XFmode */
1049 in SImode and DImode */
1051 in SImode and DImode */
1054 in SImode, DImode and TImode */
1056 in SImode, DImode and TImode */
1061 /* New AMD processors never drop prefetches; if they cannot be performed
1062 immediately, they are queued. We set number of simultaneous prefetches
1063 to a large constant to reflect this (it probably is not a good idea not
1064 to limit number of prefetches at all, as their execution also takes some
1065 time). */
1075 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1076 very small blocks it is better to use loop. For large blocks, libcall
1077 can do nontemporary accesses and beat inline considerably. */
1097 };
1121 in QImode, HImode and SImode.
1122 Relative to reg-reg move (2). */
1126 in SFmode, DFmode and XFmode */
1128 in SFmode, DFmode and XFmode */
1131 in SImode and DImode */
1133 in SImode and DImode */
1136 in SImode, DImode and TImode */
1138 in SImode, DImode and TImode */
1140 /* On K8:
1141 MOVD reg64, xmmreg Double FSTORE 4
1142 MOVD reg32, xmmreg Double FSTORE 4
1143 On AMDFAM10:
1144 MOVD reg64, xmmreg Double FADD 3
1145 1/1 1/1
1146 MOVD reg32, xmmreg Double FADD 3
1147 1/1 1/1 */
1160 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1161 very small blocks it is better to use loop. For large blocks, libcall can
1162 do nontemporary accesses and beat inline considerably. */
1182 };
1206 in QImode, HImode and SImode.
1207 Relative to reg-reg move (2). */
1211 in SFmode, DFmode and XFmode */
1213 in SFmode, DFmode and XFmode */
1216 in SImode and DImode */
1218 in SImode and DImode */
1221 in SImode, DImode and TImode */
1223 in SImode, DImode and TImode */
1225 /* On K8:
1226 MOVD reg64, xmmreg Double FSTORE 4
1227 MOVD reg32, xmmreg Double FSTORE 4
1228 On AMDFAM10:
1229 MOVD reg64, xmmreg Double FADD 3
1230 1/1 1/1
1231 MOVD reg32, xmmreg Double FADD 3
1232 1/1 1/1 */
1264 };
1266 static const
1289 in QImode, HImode and SImode.
1290 Relative to reg-reg move (2). */
1294 in SFmode, DFmode and XFmode */
1296 in SFmode, DFmode and XFmode */
1299 in SImode and DImode */
1301 in SImode and DImode */
1304 in SImode, DImode and TImode */
1306 in SImode, DImode and TImode */
1320 DUMMY_STRINGOP_ALGS},
1323 DUMMY_STRINGOP_ALGS},
1335 };
1337 static const
1360 in QImode, HImode and SImode.
1361 Relative to reg-reg move (2). */
1365 in SFmode, DFmode and XFmode */
1367 in SFmode, DFmode and XFmode */
1370 in SImode and DImode */
1372 in SImode and DImode */
1375 in SImode, DImode and TImode */
1377 in SImode, DImode and TImode */
1408 };
1410 static const
1433 in QImode, HImode and SImode.
1434 Relative to reg-reg move (2). */
1438 in SFmode, DFmode and XFmode */
1440 in SFmode, DFmode and XFmode */
1443 in SImode and DImode */
1445 in SImode and DImode */
1448 in SImode, DImode and TImode */
1450 in SImode, DImode and TImode */
1481 };
1483 /* Generic64 should produce code tuned for Nocona and K8. */
1484 static const
1487 /* On all chips taken into consideration lea is 2 cycles and more. With
1488 this cost however our current implementation of synth_mult results in
1489 use of unnecessary temporary registers causing regression on several
1490 SPECfp benchmarks. */
1511 in QImode, HImode and SImode.
1512 Relative to reg-reg move (2). */
1516 in SFmode, DFmode and XFmode */
1518 in SFmode, DFmode and XFmode */
1521 in SImode and DImode */
1523 in SImode and DImode */
1526 in SImode, DImode and TImode */
1528 in SImode, DImode and TImode */
1534 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1535 value is increased to perhaps more appropriate value of 5. */
1560 };
1562 /* core_cost should produce code tuned for Core familly of CPUs. */
1563 static const
1566 /* On all chips taken into consideration lea is 2 cycles and more. With
1567 this cost however our current implementation of synth_mult results in
1568 use of unnecessary temporary registers causing regression on several
1569 SPECfp benchmarks. */
1590 in QImode, HImode and SImode.
1591 Relative to reg-reg move (2). */
1595 in SFmode, DFmode and XFmode */
1597 in SFmode, DFmode and XFmode */
1600 in SImode and DImode */
1602 in SImode and DImode */
1605 in SImode, DImode and TImode */
1607 in SImode, DImode and TImode */
1613 /* FIXME perhaps more appropriate value is 5. */
1641 };
1643 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1644 Athlon and K8. */
1645 static const
1668 in QImode, HImode and SImode.
1669 Relative to reg-reg move (2). */
1673 in SFmode, DFmode and XFmode */
1675 in SFmode, DFmode and XFmode */
1678 in SImode and DImode */
1680 in SImode and DImode */
1683 in SImode, DImode and TImode */
1685 in SImode, DImode and TImode */
1700 DUMMY_STRINGOP_ALGS},
1703 DUMMY_STRINGOP_ALGS},
1715 };
1717 /* Set by -mtune. */
1720 /* Set by -mtune or -Os. */
1723 /* Processor feature/optimization bitmasks. */
1724 #define m_386 (1<<PROCESSOR_I386)
1725 #define m_486 (1<<PROCESSOR_I486)
1726 #define m_PENT (1<<PROCESSOR_PENTIUM)
1727 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1728 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1729 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1730 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
1731 #define m_CORE2 (1<<PROCESSOR_CORE2)
1732 #define m_COREI7 (1<<PROCESSOR_COREI7)
1733 #define m_HASWELL (1<<PROCESSOR_HASWELL)
1734 #define m_CORE_ALL (m_CORE2 | m_COREI7 | m_HASWELL)
1735 #define m_ATOM (1<<PROCESSOR_ATOM)
1737 #define m_GEODE (1<<PROCESSOR_GEODE)
1738 #define m_K6 (1<<PROCESSOR_K6)
1739 #define m_K6_GEODE (m_K6 | m_GEODE)
1740 #define m_K8 (1<<PROCESSOR_K8)
1741 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1742 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1743 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1744 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1745 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
1746 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
1747 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1748 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
1749 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3)
1750 #define m_BTVER (m_BTVER1 | m_BTVER2)
1751 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
1753 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1754 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1756 /* Generic instruction choice should be common subset of supported CPUs
1757 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1758 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1760 /* Feature tests against the various tunings. */
1763 /* Feature tests against the various tunings used to create ix86_tune_features
1764 based on the processor mask. */
1766 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1767 negatively, so enabling for Generic64 seems like good code size
1768 tradeoff. We can't enable it for 32bit generic because it does not
1769 work well with PPro base chips. */
1772 /* X86_TUNE_PUSH_MEMORY */
1775 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1778 /* X86_TUNE_UNROLL_STRLEN */
1781 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1782 on simulation result. But after P4 was made, no performance benefit
1783 was observed with branch hints. It also increases the code size.
1784 As a result, icc never generates branch hints. */
1787 /* X86_TUNE_DOUBLE_WITH_ADD */
1790 /* X86_TUNE_USE_SAHF */
1791 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC,
1793 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1794 partial dependencies. */
1797 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1798 register stalls on Generic32 compilation setting as well. However
1799 in current implementation the partial register stalls are not eliminated
1800 very well - they can be introduced via subregs synthesized by combine
1801 and can happen in caller/callee saving sequences. Because this option
1802 pays back little on PPro based chips and is in conflict with partial reg
1803 dependencies used by Athlon/P4 based chips, it is better to leave it off
1804 for generic32 for now. */
1805 m_PPRO,
1807 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1810 /* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
1811 * on 16-bit immediate moves into memory on Core2 and Corei7. */
1814 /* X86_TUNE_USE_HIMODE_FIOP */
1817 /* X86_TUNE_USE_SIMODE_FIOP */
1820 /* X86_TUNE_USE_MOV0 */
1821 m_K6,
1823 /* X86_TUNE_USE_CLTD */
1826 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1827 m_PENT4,
1829 /* X86_TUNE_SPLIT_LONG_MOVES */
1830 m_PPRO,
1832 /* X86_TUNE_READ_MODIFY_WRITE */
1835 /* X86_TUNE_READ_MODIFY */
1838 /* X86_TUNE_PROMOTE_QIMODE */
1841 /* X86_TUNE_FAST_PREFIX */
1844 /* X86_TUNE_SINGLE_STRINGOP */
1847 /* X86_TUNE_QIMODE_MATH */
1850 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1851 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1852 might be considered for Generic32 if our scheme for avoiding partial
1853 stalls was more effective. */
1856 /* X86_TUNE_PROMOTE_QI_REGS */
1859 /* X86_TUNE_PROMOTE_HI_REGS */
1860 m_PPRO,
1862 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
1863 over esp addition. */
1866 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
1867 over esp addition. */
1868 m_PENT,
1870 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
1871 over esp subtraction. */
1874 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
1875 over esp subtraction. */
1878 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1879 for DFmode copies */
1882 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1885 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1886 conflict here in between PPro/Pentium4 based chips that thread 128bit
1887 SSE registers as single units versus K8 based chips that divide SSE
1888 registers to two 64bit halves. This knob promotes all store destinations
1889 to be 128bit to allow register renaming on 128bit SSE units, but usually
1890 results in one extra microop on 64bit SSE units. Experimental results
1891 shows that disabling this option on P4 brings over 20% SPECfp regression,
1892 while enabling it on K8 brings roughly 2.4% regression that can be partly
1893 masked by careful scheduling of moves. */
1896 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1899 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1902 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1903 m_BDVER ,
1905 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1906 are resolved on SSE register parts instead of whole registers, so we may
1907 maintain just lower part of scalar values in proper format leaving the
1908 upper part undefined. */
1909 m_ATHLON_K8,
1911 /* X86_TUNE_SSE_TYPELESS_STORES */
1912 m_AMD_MULTIPLE,
1914 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1917 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1920 /* X86_TUNE_PROLOGUE_USING_MOVE */
1923 /* X86_TUNE_EPILOGUE_USING_MOVE */
1926 /* X86_TUNE_SHIFT1 */
1929 /* X86_TUNE_USE_FFREEP */
1930 m_AMD_MULTIPLE,
1932 /* X86_TUNE_INTER_UNIT_MOVES */
1935 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1938 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1939 than 4 branch instructions in the 16 byte window. */
1942 /* X86_TUNE_SCHEDULE */
1945 /* X86_TUNE_USE_BT */
1948 /* X86_TUNE_USE_INCDEC */
1951 /* X86_TUNE_PAD_RETURNS */
1954 /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
1955 m_ATOM,
1957 /* X86_TUNE_EXT_80387_CONSTANTS */
1960 /* X86_TUNE_AVOID_VECTOR_DECODE */
1963 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1964 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1967 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1968 vector path on AMD machines. */
1971 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1972 machines. */
1975 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1976 than a MOV. */
1977 m_PENT,
1979 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1980 but one byte longer. */
1981 m_PENT,
1983 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1984 operand that cannot be represented using a modRM byte. The XOR
1985 replacement is long decoded, so this split helps here as well. */
1986 m_K6,
1988 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1989 from FP to FP. */
1992 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1993 from integer to FP. */
1994 m_AMDFAM10,
1996 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1997 with a subsequent conditional jump instruction into a single
1998 compare-and-branch uop. */
1999 m_BDVER,
2001 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
2002 will impact LEA instruction selection. */
2003 m_ATOM,
2005 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
2006 instructions. */
2009 /* X86_SOFTARE_PREFETCHING_BENEFICIAL: Enable software prefetching
2010 at -O3. For the moment, the prefetching seems badly tuned for Intel
2011 chips. */
2014 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
2015 the auto-vectorizer. */
2018 /* X86_TUNE_REASSOC_INT_TO_PARALLEL: Try to produce parallel computations
2019 during reassociation of integer computation. */
2020 m_ATOM,
2022 /* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
2023 during reassociation of fp computation. */
2024 m_ATOM,
2026 /* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
2027 regs instead of memory. */
2028 m_CORE_ALL,
2030 /* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
2031 a conditional move. */
2032 m_ATOM
2033 };
2035 /* Feature tests against the various architecture variations. */
2038 /* Feature tests against the various architecture variations, used to create
2039 ix86_arch_features based on the processor mask. */
2041 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2044 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2047 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2050 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2053 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2055 };
2057 static const unsigned int x86_accumulate_outgoing_args
2060 static const unsigned int x86_arch_always_fancy_math_387
2063 static const unsigned int x86_avx256_split_unaligned_load
2066 static const unsigned int x86_avx256_split_unaligned_store
2069 /* In case the average insn count for single function invocation is
2070 lower than this constant, emit fast (but longer) prologue and
2071 epilogue code. */
2072 #define FAST_PROLOGUE_INSN_COUNT 20
2074 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2079 /* Array of the smallest class containing reg number REGNO, indexed by
2080 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2083 {
2084 /* ax, dx, cx, bx */
2086 /* si, di, bp, sp */
2088 /* FP registers */
2091 /* arg pointer */
2092 NON_Q_REGS,
2093 /* flags, fpsr, fpcr, frame */
2095 /* SSE registers */
2098 /* MMX registers */
2101 /* REX registers */
2104 /* SSE REX registers */
2107 };
2109 /* The "default" register map used in 32bit mode. */
2112 {
2120 };
2122 /* The "default" register map used in 64bit mode. */
2125 {
2133 };
2135 /* Define the register numbers to be used in Dwarf debugging information.
2136 The SVR4 reference port C compiler uses the following register numbers
2137 in its Dwarf output code:
2138 0 for %eax (gcc regno = 0)
2139 1 for %ecx (gcc regno = 2)
2140 2 for %edx (gcc regno = 1)
2141 3 for %ebx (gcc regno = 3)
2142 4 for %esp (gcc regno = 7)
2143 5 for %ebp (gcc regno = 6)
2144 6 for %esi (gcc regno = 4)
2145 7 for %edi (gcc regno = 5)
2146 The following three DWARF register numbers are never generated by
2147 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2148 believes these numbers have these meanings.
2149 8 for %eip (no gcc equivalent)
2150 9 for %eflags (gcc regno = 17)
2151 10 for %trapno (no gcc equivalent)
2152 It is not at all clear how we should number the FP stack registers
2153 for the x86 architecture. If the version of SDB on x86/svr4 were
2154 a bit less brain dead with respect to floating-point then we would
2155 have a precedent to follow with respect to DWARF register numbers
2156 for x86 FP registers, but the SDB on x86/svr4 is so completely
2157 broken with respect to FP registers that it is hardly worth thinking
2158 of it as something to strive for compatibility with.
2159 The version of x86/svr4 SDB I have at the moment does (partially)
2160 seem to believe that DWARF register number 11 is associated with
2161 the x86 register %st(0), but that's about all. Higher DWARF
2162 register numbers don't seem to be associated with anything in
2163 particular, and even for DWARF regno 11, SDB only seems to under-
2164 stand that it should say that a variable lives in %st(0) (when
2165 asked via an `=' command) if we said it was in DWARF regno 11,
2166 but SDB still prints garbage when asked for the value of the
2167 variable in question (via a `/' command).
2168 (Also note that the labels SDB prints for various FP stack regs
2169 when doing an `x' command are all wrong.)
2170 Note that these problems generally don't affect the native SVR4
2171 C compiler because it doesn't allow the use of -O with -g and
2172 because when it is *not* optimizing, it allocates a memory
2173 location for each floating-point variable, and the memory
2174 location is what gets described in the DWARF AT_location
2175 attribute for the variable in question.
2176 Regardless of the severe mental illness of the x86/svr4 SDB, we
2177 do something sensible here and we use the following DWARF
2178 register numbers. Note that these are all stack-top-relative
2179 numbers.
2180 11 for %st(0) (gcc regno = 8)
2181 12 for %st(1) (gcc regno = 9)
2182 13 for %st(2) (gcc regno = 10)
2183 14 for %st(3) (gcc regno = 11)
2184 15 for %st(4) (gcc regno = 12)
2185 16 for %st(5) (gcc regno = 13)
2186 17 for %st(6) (gcc regno = 14)
2187 18 for %st(7) (gcc regno = 15)
2188 */
2190 {
2198 };
2200 /* Define parameter passing and return registers. */
2203 {
2205 };
2208 {
2210 };
2213 {
2215 };
2217 /* Define the structure for the machine field in struct function. */
2222 rtx rtl;
2224 };
2226 /* Structure describing stack frame layout.
2227 Stack grows downward:
2229 [arguments]
2230 <- ARG_POINTER
2231 saved pc
2233 saved static chain if ix86_static_chain_on_stack
2235 saved frame pointer if frame_pointer_needed
2236 <- HARD_FRAME_POINTER
2237 [saved regs]
2238 <- regs_save_offset
2239 [padding0]
2241 [saved SSE regs]
2242 <- sse_regs_save_offset
2243 [padding1] |
2244 | <- FRAME_POINTER
2245 [va_arg registers] |
2246 |
2247 [frame] |
2248 |
2249 [padding2] | = to_allocate
2250 <- STACK_POINTER
2251 */
2252 struct ix86_frame
2253 {
2260 /* The offsets relative to ARG_POINTER. */
2261 HOST_WIDE_INT frame_pointer_offset;
2262 HOST_WIDE_INT hard_frame_pointer_offset;
2263 HOST_WIDE_INT stack_pointer_offset;
2264 HOST_WIDE_INT hfp_save_offset;
2265 HOST_WIDE_INT reg_save_offset;
2266 HOST_WIDE_INT sse_reg_save_offset;
2268 /* When save_regs_using_mov is set, emit prologue using
2269 move instead of push instructions. */
2271 };
2273 /* Which cpu are we scheduling for. */
2276 /* Which cpu are we optimizing for. */
2279 /* Which instruction set architecture to use. */
2282 /* True if processor has SSE prefetch instruction. */
2285 /* -mstackrealign option */
2302 /* Preferred alignment for stack boundary in bits. */
2305 /* Alignment for incoming stack boundary in bits specified at
2306 command line. */
2309 /* Default alignment for incoming stack boundary in bits. */
2312 /* Alignment for incoming stack boundary in bits. */
2315 /* Calling abi specific va_list type nodes. */
2319 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2323 /* Fence to use after loop using movnt. */
2324 tree x86_mfence;
2326 /* Register class used for passing given 64bit part of the argument.
2327 These represent classes as documented by the PS ABI, with the exception
2328 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2329 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2331 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2332 whenever possible (upper half does contain padding). */
2333 enum x86_64_reg_class
2334 {
2335 X86_64_NO_CLASS,
2336 X86_64_INTEGER_CLASS,
2337 X86_64_INTEGERSI_CLASS,
2338 X86_64_SSE_CLASS,
2339 X86_64_SSESF_CLASS,
2340 X86_64_SSEDF_CLASS,
2341 X86_64_SSEUP_CLASS,
2342 X86_64_X87_CLASS,
2343 X86_64_X87UP_CLASS,
2344 X86_64_COMPLEX_X87_CLASS,
2345 X86_64_MEMORY_CLASS
2346 };
2348 #define MAX_CLASSES 4
2350 /* Table of constants used by fldpi, fldln2, etc.... */
2354 \f
2359 const_tree);
2371 enum ix86_function_specific_strings
2372 {
2373 IX86_FUNCTION_SPECIFIC_ARCH,
2374 IX86_FUNCTION_SPECIFIC_TUNE,
2375 IX86_FUNCTION_SPECIFIC_MAX
2376 };
2394 \f
2395 #ifndef SUBTARGET32_DEFAULT_CPU
2397 #endif
2399 /* Whether -mtune= or -march= were specified */
2403 /* Vectorization library interface and handlers. */
2409 /* Processor target table, indexed by processor number */
2410 struct ptt
2411 {
2418 };
2421 {
2432 /* Core 2 */
2434 /* Core i7 */
2436 /* Core avx2 */
2447 };
2450 {
2479 "btver2"
2480 };
2481 \f
2482 static bool
2484 {
2486 }
2488 static unsigned int
2490 {
2493 /* vzeroupper instructions are inserted immediately after reload to
2494 account for possible spills from 256bit registers. The pass
2495 reuses mode switching infrastructure by re-running mode insertion
2496 pass, so disable entities that have already been processed. */
2502 /* Call optimize_mode_switching. */
2505 }
2508 {
2509 {
2510 RTL_PASS,
2525 }
2526 };
2528 /* Return true if a red-zone is in use. */
2532 {
2534 }
2535 \f
2536 /* Return a string that documents the current -m options. The caller is
2537 responsible for freeing the string. */
2543 {
2544 struct ix86_target_opts
2545 {
2548 };
2550 /* This table is ordered so that options like -msse4.2 that imply
2551 preceding options while match those first. */
2553 {
2589 };
2591 /* Flag options. */
2593 {
2621 };
2638 /* Add -march= option. */
2640 {
2643 }
2645 /* Add -mtune= option. */
2647 {
2650 }
2652 /* Add -m32/-m64/-mx32. */
2654 {
2657 else
2659 isa &= ~ (OPTION_MASK_ISA_64BIT
2660 | OPTION_MASK_ABI_64
2662 }
2663 else
2667 /* Pick out the options in isa options. */
2669 {
2671 {
2674 }
2675 }
2678 {
2681 isa);
2682 }
2684 /* Add flag options. */
2686 {
2688 {
2691 }
2692 }
2695 {
2698 }
2700 /* Add -fpmath= option. */
2702 {
2705 {
2720 }
2721 }
2723 /* Any options? */
2729 /* Size the string. */
2733 {
2738 }
2740 /* Build the string. */
2745 {
2752 {
2754 line_len++;
2757 {
2761 }
2762 }
2766 {
2770 }
2771 }
2777 }
2779 /* Return true, if profiling code should be emitted before
2780 prologue. Otherwise it returns false.
2781 Note: For x86 with "hotfix" it is sorried. */
2782 static bool
2784 {
2786 }
2788 /* Function that is callable from the debugger to print the current
2789 options. */
2790 void
2792 {
2798 {
2801 }
2802 else
2806 }
2807 \f
2808 /* Override various settings based on options. If MAIN_ARGS_P, the
2809 options are from the command line, otherwise they are from
2810 attributes. */
2812 static void
2814 {
2822 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
2823 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
2824 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
2825 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
2826 #define PTA_AES (HOST_WIDE_INT_1 << 4)
2827 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
2828 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
2829 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
2830 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
2831 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
2832 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
2833 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
2834 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
2835 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
2836 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
2837 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
2838 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
2839 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
2840 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
2841 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
2842 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
2843 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
2844 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
2845 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
2846 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
2847 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
2848 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
2849 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
2850 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
2851 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
2852 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
2853 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
2854 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
2855 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
2856 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
2857 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
2858 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
2859 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
2860 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
2861 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
2863 /* if this reaches 64, need to widen struct pta flags below */
2865 static struct pta
2866 {
2871 }
2873 {
3003 PTA_64BIT
3005 };
3007 /* -mrecip options. */
3008 static struct
3009 {
3012 }
3014 {
3021 };
3025 /* Set up prefix/suffix so the error messages refer to either the command
3026 line argument, or the attribute(target). */
3028 {
3032 }
3033 else
3034 {
3038 }
3040 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3041 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3044 #ifdef TARGET_BI_ARCH
3045 else
3046 {
3047 #if TARGET_BI_ARCH == 1
3048 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3049 is on and OPTION_MASK_ABI_X32 is off. We turn off
3050 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3051 -mx32. */
3054 #else
3055 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3056 on and OPTION_MASK_ABI_64 is off. We turn off
3057 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3058 -m64. */
3061 #endif
3062 }
3063 #endif
3066 {
3067 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3068 OPTION_MASK_ABI_64 for TARGET_X32. */
3071 }
3073 {
3074 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3075 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3078 }
3080 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3081 SUBTARGET_OVERRIDE_OPTIONS;
3082 #endif
3084 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3085 SUBSUBTARGET_OVERRIDE_OPTIONS;
3086 #endif
3088 /* -fPIC is the default for x86_64. */
3092 /* Need to check -mtune=generic first. */
3094 {
3097 /* As special support for cross compilers we read -mtune=native
3098 as -mtune=generic. With native compilers we won't see the
3099 -mtune=native, as it was changed by the driver. */
3101 {
3104 else
3106 }
3107 /* If this call is for setting the option attribute, allow the
3108 generic32/generic64 that was previously set. */
3112 ;
3120 }
3121 else
3122 {
3126 {
3129 }
3131 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3132 need to use a sensible tune option. */
3136 {
3139 else
3141 }
3142 }
3145 {
3146 /* rep; movq isn't available in 32-bit code. */
3149 }
3153 else
3157 {
3163 }
3164 else
3171 {
3173 {
3217 {
3220 }
3228 }
3229 }
3230 else
3231 {
3232 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3233 use of rip-relative addressing. This eliminates fixups that
3234 would otherwise be needed if this object is to be placed in a
3235 DLL, and is essentially just as efficient as direct addressing. */
3242 else
3244 }
3246 {
3249 }
3256 {
3259 /* Default cpu tuning to the architecture. */
3384 }
3399 {
3403 {
3405 {
3407 {
3415 }
3416 else
3419 }
3420 }
3421 else
3422 {
3423 /* Adjust tuning when compiling for 32-bit ABI. */
3425 {
3433 }
3434 }
3435 /* Intel CPUs have always interpreted SSE prefetch instructions as
3436 NOPs; so, we can enable SSE prefetch instructions even when
3437 -mtune (rather than -march) points us to a processor that has them.
3438 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3439 higher processors. */
3444 }
3454 #ifndef USE_IX86_FRAME_POINTER
3455 #define USE_IX86_FRAME_POINTER 0
3456 #endif
3458 #ifndef USE_X86_64_FRAME_POINTER
3459 #define USE_X86_64_FRAME_POINTER 0
3460 #endif
3462 /* Set the default values for switches whose default depends on TARGET_64BIT
3463 in case they weren't overwritten by command line options. */
3465 {
3472 }
3473 else
3474 {
3481 }
3486 else
3489 /* Arrange to set up i386_stack_locals for all functions. */
3492 /* Validate -mregparm= value. */
3494 {
3498 {
3502 }
3503 }
3507 /* Default align_* from the processor table. */
3509 {
3512 }
3514 {
3517 }
3519 {
3521 }
3523 /* Provide default for -mbranch-cost= value. */
3528 {
3531 /* Enable by default the SSE and MMX builtins. Do allow the user to
3532 explicitly disable any of these. In particular, disabling SSE and
3533 MMX for kernel code is extremely useful. */
3535 ix86_isa_flags
3541 }
3542 else
3543 {
3547 ix86_isa_flags
3550 /* i386 ABI does not specify red zone. It still makes sense to use it
3551 when programmer takes care to stack from being destroyed. */
3554 }
3556 /* Keep nonleaf frame pointers. */
3562 /* If we're doing fast math, we don't care about comparison order
3563 wrt NaNs. This lets us use a shorter comparison sequence. */
3567 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3568 since the insns won't need emulation. */
3572 /* Likewise, if the target doesn't have a 387, or we've specified
3573 software floating point, don't use 387 inline intrinsics. */
3577 /* Turn on MMX builtins for -msse. */
3581 /* Enable SSE prefetch. */
3585 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3589 /* Turn on lzcnt instruction for -mabm. */
3593 /* Validate -mpreferred-stack-boundary= value or default it to
3594 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3597 {
3603 {
3607 else
3610 }
3611 else
3612 ix86_preferred_stack_boundary
3614 }
3616 /* Set the default value for -mstackrealign. */
3622 /* Validate -mincoming-stack-boundary= value or default it to
3623 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3626 {
3631 else
3632 {
3633 ix86_user_incoming_stack_boundary
3635 ix86_incoming_stack_boundary
3637 }
3638 }
3640 /* Accept -msseregparm only if at least SSE support is enabled. */
3646 {
3648 {
3650 {
3653 }
3655 {
3658 }
3659 }
3660 }
3661 else
3664 /* If the i387 is disabled, then do not return values in it. */
3668 /* Use external vectorized library in vectorizing intrinsics. */
3671 {
3682 }
3690 /* ??? Unwind info is not correct around the CFG unless either a frame
3691 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3692 unwind info generation to be aware of the CFG and propagating states
3693 around edges. */
3696 && flag_omit_frame_pointer
3698 {
3704 }
3706 /* If stack probes are required, the space used for large function
3707 arguments on the stack must also be probed, so enable
3708 -maccumulate-outgoing-args so this happens in the prologue. */
3711 {
3716 }
3718 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3719 {
3725 }
3727 /* When scheduling description is not available, disable scheduler pass
3728 so it won't slow down the compilation and make x87 code slower. */
3749 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3751 && HAVE_prefetch
3756 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3757 can be optimized to ap = __builtin_next_arg (0). */
3762 {
3765 {
3768 ix86_gen_tls_local_dynamic_base_64
3770 }
3771 else
3772 {
3775 ix86_gen_tls_local_dynamic_base_64
3777 }
3778 }
3779 else
3780 {
3783 }
3786 {
3795 }
3796 else
3797 {
3806 }
3808 #ifdef USE_IX86_CLD
3809 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3812 #endif
3815 {
3820 }
3822 {
3826 }
3828 {
3829 #if defined(PROFILE_BEFORE_PROLOGUE)
3831 #else
3833 #endif
3834 }
3837 {
3838 /* When not optimize for size, enable vzeroupper optimization for
3839 TARGET_AVX with -fexpensive-optimizations and split 32-byte
3840 AVX unaligned load/store. */
3842 {
3852 /* Enable 128-bit AVX instruction generation
3853 for the auto-vectorizer. */
3857 }
3858 }
3859 else
3860 {
3861 /* Disable vzeroupper pass if TARGET_AVX is disabled. */
3863 }
3866 {
3873 {
3876 {
3878 q++;
3879 }
3880 else
3885 else
3886 {
3889 {
3892 }
3895 {
3899 }
3900 }
3905 else
3907 }
3908 }
3915 /* Default long double to 64-bit for Bionic. */
3920 /* Save the initial options in case the user does function specific
3921 options. */
3923 target_option_default_node = target_option_current_node
3925 }
3927 /* Implement the TARGET_OPTION_OVERRIDE hook. */
3929 static void
3931 {
3932 static struct register_pass_info insert_vzeroupper_info
3935 };
3940 /* This needs to be done at start up. It's convenient to do it here. */
3942 }
3944 /* Update register usage after having seen the compiler flags. */
3946 static void
3948 {
3952 /* The PIC register, if it exists, is fixed. */
3957 /* For 32-bit targets, squash the REX registers. */
3959 {
3964 }
3966 /* See the definition of CALL_USED_REGISTERS in i386.h. */
3974 {
3975 /* Set/reset conditionally defined registers from
3976 CALL_USED_REGISTERS initializer. */
3980 /* Calculate registers of CLOBBERED_REGS register set
3981 as call used registers from GENERAL_REGS register set. */
3985 }
3987 /* If MMX is disabled, squash the registers. */
3993 /* If SSE is disabled, squash the registers. */
3999 /* If the FPU is disabled, squash the registers. */
4004 }
4006 \f
4007 /* Save the current options */
4009 static void
4011 {
4022 /* The fields are char but the variables are not; make sure the
4023 values fit in the fields. */
4028 }
4030 /* Restore the current options */
4032 static void
4034 {
4050 /* Recreate the arch feature tests if the arch changed */
4052 {
4057 }
4059 /* Recreate the tune optimization tests */
4061 {
4066 }
4067 }
4069 /* Print the current options */
4071 static void
4074 {
4096 {
4099 }
4100 }
4102 \f
4103 /* Inner function to process the attribute((target(...))), take an argument and
4104 set the current options from the argument. If we have a list, recursively go
4105 over the list. */
4107 static bool
4110 {
4114 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4115 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4116 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4117 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4118 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4120 enum ix86_opt_type
4121 {
4122 ix86_opt_unknown,
4123 ix86_opt_yes,
4124 ix86_opt_no,
4125 ix86_opt_str,
4126 ix86_opt_enum,
4127 ix86_opt_isa
4128 };
4130 static const struct
4131 {
4138 /* isa options */
4175 /* enum options */
4178 /* string options */
4182 /* flag options */
4184 OPT_mcld,
4185 MASK_CLD),
4188 OPT_mfancy_math_387,
4189 MASK_NO_FANCY_MATH_387),
4192 OPT_mieee_fp,
4193 MASK_IEEE_FP),
4196 OPT_minline_all_stringops,
4197 MASK_INLINE_ALL_STRINGOPS),
4200 OPT_minline_stringops_dynamically,
4201 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4204 OPT_mno_align_stringops,
4205 MASK_NO_ALIGN_STRINGOPS),
4208 OPT_mrecip,
4209 MASK_RECIP),
4211 };
4213 /* If this is a list, recurse to get the options. */
4215 {
4225 }
4228 {
4231 }
4233 /* Handle multiple arguments separated by commas. */
4237 {
4251 {
4255 }
4256 else
4257 {
4260 }
4262 /* Recognize no-xxx. */
4264 {
4268 }
4269 else
4272 /* Find the option. */
4276 {
4284 {
4289 }
4290 }
4292 /* Process the option. */
4294 {
4297 }
4300 {
4306 }
4309 {
4315 else
4317 }
4320 {
4322 {
4325 }
4326 else
4328 }
4331 {
4339 global_dc);
4340 else
4341 {
4344 }
4345 }
4347 else
4349 }
4352 }
4354 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4356 tree
4358 {
4373 /* Process each of the options on the chain. */
4378 /* If the changed options are different from the default, rerun
4379 ix86_option_override_internal, and then save the options away.
4380 The string options are are attribute options, and will be undone
4381 when we copy the save structure. */
4387 {
4388 /* If we are using the default tune= or arch=, undo the string assigned,
4389 and use the default. */
4400 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4404 {
4407 }
4409 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4412 /* Add any builtin functions with the new isa if any. */
4415 /* Save the current options unless we are validating options for
4416 #pragma. */
4423 /* Free up memory allocated to hold the strings */
4426 }
4429 }
4431 /* Hook to validate attribute((target("string"))). */
4433 static bool
4436 tree args,
4438 {
4442 /* attribute((target("default"))) does nothing, beyond
4443 affecting multi-versioning. */
4454 /* If the function changed the optimization levels as well as setting target
4455 options, start with the optimizations specified. */
4460 /* The target attributes may also change some optimization flags, so update
4461 the optimization options if necessary. */
4470 {
4475 }
4484 }
4486 \f
4487 /* Hook to determine if one function can safely inline another. */
4489 static bool
4491 {
4496 /* If callee has no option attributes, then it is ok to inline. */
4500 /* If caller has no option attributes, but callee does then it is not ok to
4501 inline. */
4505 else
4506 {
4510 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4511 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4512 function. */
4517 /* See if we have the same non-isa options. */
4521 /* See if arch, tune, etc. are the same. */
4534 else
4536 }
4539 }
4541 \f
4542 /* Remember the last target of ix86_set_current_function. */
4545 /* Establish appropriate back-end context for processing the function
4546 FNDECL. The argument might be NULL to indicate processing at top
4547 level, outside of any function scope. */
4548 static void
4550 {
4551 /* Only change the context if the function changes. This hook is called
4552 several times in the course of compiling a function, and we don't want to
4553 slow things down too much or call target_reinit when it isn't safe. */
4555 {
4556 tree old_tree = (ix86_previous_fndecl
4560 tree new_tree = (fndecl
4566 ;
4569 {
4573 }
4576 {
4582 }
4583 }
4584 }
4586 \f
4587 /* Return true if this goes in large data/bss. */
4589 static bool
4591 {
4595 /* Functions are never large data. */
4600 {
4606 }
4607 else
4608 {
4611 /* If this is an incomplete type with size 0, then we can't put it
4612 in data because it might be too big when completed. */
4615 }
4618 }
4620 /* Switch to the appropriate section for output of DECL.
4621 DECL is either a `VAR_DECL' node or a constant of some sort.
4622 RELOC indicates whether forming the initial value of DECL requires
4623 link-time relocations. */
4626 ATTRIBUTE_UNUSED;
4631 {
4634 {
4638 {
4672 /* We don't split these for medium model. Place them into
4673 default sections and hope for best. */
4675 }
4677 {
4678 /* We might get called with string constants, but get_named_section
4679 doesn't like them as they are not DECLs. Also, we need to set
4680 flags in that case. */
4684 }
4685 }
4687 }
4689 /* Build up a unique section name, expressed as a
4690 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4691 RELOC indicates whether the initial value of EXP requires
4692 link-time relocations. */
4694 static void ATTRIBUTE_UNUSED
4696 {
4699 {
4701 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4705 {
4729 /* We don't split these for medium model. Place them into
4730 default sections and hope for best. */
4732 }
4734 {
4741 /* If we're using one_only, then there needs to be a .gnu.linkonce
4742 prefix to the section name. */
4749 }
4750 }
4752 }
4754 #ifdef COMMON_ASM_OP
4755 /* This says how to output assembler code to declare an
4756 uninitialized external linkage data object.
4758 For medium model x86-64 we need to use .largecomm opcode for
4759 large objects. */
4760 void
4764 {
4768 else
4773 }
4774 #endif
4776 /* Utility function for targets to use in implementing
4777 ASM_OUTPUT_ALIGNED_BSS. */
4779 void
4783 {
4787 else
4790 #ifdef ASM_DECLARE_OBJECT_NAME
4793 #else
4794 /* Standard thing is just output label for the object. */
4798 }
4799 \f
4800 /* Decide whether we must probe the stack before any space allocation
4801 on this target. It's essentially TARGET_STACK_PROBE except when
4802 -fstack-check causes the stack to be already probed differently. */
4804 bool
4806 {
4807 /* Do not probe the stack twice if static stack checking is enabled. */
4812 }
4813 \f
4814 /* Decide whether we can make a sibling call to a function. DECL is the
4815 declaration of the function being targeted by the call and EXP is the
4816 CALL_EXPR representing the call. */
4818 static bool
4820 {
4824 /* If we are generating position-independent code, we cannot sibcall
4825 optimize any indirect call, or a direct call to a global function,
4826 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
4828 && !TARGET_64BIT
4829 && flag_pic
4833 /* If we need to align the outgoing stack, then sibcalling would
4834 unalign the stack, which may break the called function. */
4840 {
4843 }
4844 else
4845 {
4846 /* We're looking at the CALL_EXPR, we need the type of the function. */
4851 }
4853 /* Check that the return value locations are the same. Like
4854 if we are returning floats on the 80387 register stack, we cannot
4855 make a sibcall from a function that doesn't return a float to a
4856 function that does or, conversely, from a function that does return
4857 a float to a function that doesn't; the necessary stack adjustment
4858 would not be executed. This is also the place we notice
4859 differences in the return value ABI. Note that it is ok for one
4860 of the functions to have void return type as long as the return
4861 value of the other is passed in a register. */
4866 {
4869 }
4871 ;
4876 {
4877 /* The SYSV ABI has more call-clobbered registers;
4878 disallow sibcalls from MS to SYSV. */
4882 }
4883 else
4884 {
4885 /* If this call is indirect, we'll need to be able to use a
4886 call-clobbered register for the address of the target function.
4887 Make sure that all such registers are not used for passing
4888 parameters. Note that DLLIMPORT functions are indirect. */
4891 {
4893 {
4894 /* ??? Need to count the actual number of registers to be used,
4895 not the possible number of registers. Fix later. */
4897 }
4898 }
4899 }
4901 /* Otherwise okay. That also includes certain types of indirect calls. */
4903 }
4905 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
4906 and "sseregparm" calling convention attributes;
4907 arguments as in struct attribute_spec.handler. */
4909 static tree
4911 tree args,
4914 {
4919 {
4921 name);
4924 }
4926 /* Can combine regparm with all attributes but fastcall, and thiscall. */
4928 {
4929 tree cst;
4932 {
4934 }
4937 {
4939 }
4943 {
4946 name);
4948 }
4950 {
4954 }
4957 }
4960 {
4961 /* Do not warn when emulating the MS ABI. */
4966 name);
4969 }
4971 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4973 {
4975 {
4977 }
4979 {
4981 }
4983 {
4985 }
4987 {
4989 }
4990 }
4992 /* Can combine stdcall with fastcall (redundant), regparm and
4993 sseregparm. */
4995 {
4997 {
4999 }
5001 {
5003 }
5005 {
5007 }
5008 }
5010 /* Can combine cdecl with regparm and sseregparm. */
5012 {
5014 {
5016 }
5018 {
5020 }
5022 {
5024 }
5025 }
5027 {
5030 name);
5032 {
5034 }
5036 {
5038 }
5040 {
5042 }
5043 }
5045 /* Can combine sseregparm with all attributes. */
5048 }
5050 /* The transactional memory builtins are implicitly regparm or fastcall
5051 depending on the ABI. Override the generic do-nothing attribute that
5052 these builtins were declared with, and replace it with one of the two
5053 attributes that we expect elsewhere. */
5055 static tree
5057 tree args ATTRIBUTE_UNUSED,
5060 {
5061 tree alt;
5063 /* In no case do we want to add the placeholder attribute. */
5066 /* The 64-bit ABI is unchanged for transactional memory. */
5070 /* ??? Is there a better way to validate 32-bit windows? We have
5071 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5074 else
5075 {
5078 }
5082 }
5084 /* This function determines from TYPE the calling-convention. */
5086 unsigned int
5088 {
5091 tree attrs;
5098 {
5108 /* Regparam isn't allowed for thiscall and fastcall. */
5110 {
5115 }
5119 }
5126 || is_stdarg
5132 }
5134 /* Return 0 if the attributes for two types are incompatible, 1 if they
5135 are compatible, and 2 if they are nearly compatible (which causes a
5136 warning to be generated). */
5138 static int
5140 {
5156 }
5157 \f
5158 /* Return the regparm value for a function with the indicated TYPE and DECL.
5159 DECL may be NULL when calling function indirectly
5160 or considering a libcall. */
5162 static int
5164 {
5165 tree attr;
5176 {
5179 {
5182 }
5183 }
5189 /* Use register calling convention for local functions when possible. */
5192 && optimize
5194 {
5195 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5198 {
5201 /* Make sure no regparm register is taken by a
5202 fixed register variable. */
5207 /* We don't want to use regparm(3) for nested functions as
5208 these use a static chain pointer in the third argument. */
5212 /* In 32-bit mode save a register for the split stack. */
5216 /* Each fixed register usage increases register pressure,
5217 so less registers should be used for argument passing.
5218 This functionality can be overriden by an explicit
5219 regparm value. */
5222 globals++;
5224 local_regparm
5229 }
5230 }
5233 }
5235 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5236 DFmode (2) arguments in SSE registers for a function with the
5237 indicated TYPE and DECL. DECL may be NULL when calling function
5238 indirectly or considering a libcall. Otherwise return 0. */
5240 static int
5242 {
5245 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5246 by the sseregparm attribute. */
5249 {
5251 {
5253 {
5257 else
5260 }
5262 }
5265 }
5267 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5268 (and DFmode for SSE2) arguments in SSE registers. */
5271 {
5272 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5276 }
5279 }
5281 /* Return true if EAX is live at the start of the function. Used by
5282 ix86_expand_prologue to determine if we need special help before
5283 calling allocate_stack_worker. */
5285 static bool
5287 {
5288 /* Cheat. Don't bother working forward from ix86_function_regparm
5289 to the function type to whether an actual argument is located in
5290 eax. Instead just look at cfg info, which is still close enough
5291 to correct at this point. This gives false positives for broken
5292 functions that might use uninitialized data that happens to be
5293 allocated in eax, but who cares? */
5295 }
5297 static bool
5299 {
5300 tree attr;
5303 {
5309 /* For 32-bit MS-ABI the default is to keep aggregate
5310 return pointer. */
5313 }
5315 }
5317 /* Value is the number of bytes of arguments automatically
5318 popped when returning from a subroutine call.
5319 FUNDECL is the declaration node of the function (as a tree),
5320 FUNTYPE is the data type of the function (as a tree),
5321 or for a library call it is an identifier node for the subroutine name.
5322 SIZE is the number of bytes of arguments passed on the stack.
5324 On the 80386, the RTD insn may be used to pop them if the number
5325 of args is fixed, but if the number is variable then the caller
5326 must pop them all. RTD can't be used for library calls now
5327 because the library is compiled with the Unix compiler.
5328 Use of RTD is a selectable option, since it is incompatible with
5329 standard Unix calling sequences. If the option is not selected,
5330 the caller must always pop the args.
5332 The attribute stdcall is equivalent to RTD on a per module basis. */
5334 static int
5336 {
5339 /* None of the 64-bit ABIs pop arguments. */
5350 /* Lose any fake structure return argument if it is passed on the stack. */
5353 {
5357 }
5360 }
5362 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5364 static bool
5366 {
5367 /* Check operand constraints in case hard registers were propagated
5368 into insn pattern. This check prevents combine pass from
5369 generating insn patterns with invalid hard register operands.
5370 These invalid insns can eventually confuse reload to error out
5371 with a spill failure. See also PRs 46829 and 46843. */
5373 {
5380 {
5388 /* A unary operator may be accepted by the predicate, but it
5389 is irrelevant for matching constraints. */
5394 {
5402 }
5409 /* Operand has no constraints, anything is OK. */
5413 {
5416 && operands_match_p
5420 {
5423 }
5424 }
5428 }
5429 }
5432 }
5433 \f
5434 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5436 static unsigned HOST_WIDE_INT
5438 {
5440 }
5441 \f
5442 /* Argument support functions. */
5444 /* Return true when register may be used to pass function parameters. */
5445 bool
5447 {
5452 {
5456 else
5462 }
5465 {
5468 }
5469 else
5470 {
5474 }
5476 /* TODO: The function should depend on current function ABI but
5477 builtins.c would need updating then. Therefore we use the
5478 default ABI. */
5480 /* RAX is used as hidden argument to va_arg functions. */
5486 else
5493 }
5495 /* Return if we do not know how to pass TYPE solely in registers. */
5497 static bool
5499 {
5503 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5504 The layout_type routine is crafty and tries to trick us into passing
5505 currently unsupported vector types on the stack by using TImode. */
5508 }
5510 /* It returns the size, in bytes, of the area reserved for arguments passed
5511 in registers for the function represented by fndecl dependent to the used
5512 abi format. */
5513 int
5515 {
5519 else
5524 }
5526 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5527 call abi used. */
5528 enum calling_abi
5530 {
5532 {
5535 {
5538 }
5542 }
5544 }
5546 static bool
5548 {
5550 {
5554 else
5556 }
5558 }
5560 static enum calling_abi
5562 {
5566 }
5568 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5569 call abi used. */
5570 enum calling_abi
5572 {
5576 }
5578 /* Write the extra assembler code needed to declare a function properly. */
5580 void
5582 tree decl)
5583 {
5587 {
5593 }
5595 #ifdef SUBTARGET_ASM_UNWIND_INIT
5597 #endif
5601 /* Output magic byte marker, if hot-patch attribute is set. */
5603 {
5605 {
5606 /* leaq [%rsp + 0], %rsp */
5609 }
5610 else
5611 {
5612 /* movl.s %edi, %edi
5613 push %ebp
5614 movl.s %esp, %ebp */
5617 }
5618 }
5619 }
5621 /* regclass.c */
5624 /* Implementation of call abi switching target hook. Specific to FNDECL
5625 the specific call register sets are set. See also
5626 ix86_conditional_register_usage for more details. */
5627 void
5629 {
5632 else
5634 }
5636 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
5637 expensive re-initialization of init_regs each time we switch function context
5638 since this is needed only during RTL expansion. */
5639 static void
5641 {
5645 }
5647 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5648 for a call to a function whose data type is FNTYPE.
5649 For a library call, FNTYPE is 0. */
5651 void
5655 tree fndecl,
5657 {
5663 {
5666 }
5667 else
5668 {
5671 }
5675 /* Set up the number of registers to use for passing arguments. */
5682 {
5684 ? X86_64_REGPARM_MAX
5686 }
5688 {
5691 {
5693 ? X86_64_SSE_REGPARM_MAX
5695 }
5696 }
5703 /* Because type might mismatch in between caller and callee, we need to
5704 use actual type of function for local calls.
5705 FIXME: cgraph_analyze can be told to actually record if function uses
5706 va_start so for local functions maybe_vaarg can be made aggressive
5707 helping K&R code.
5708 FIXME: once typesytem is fixed, we won't need this code anymore. */
5716 {
5717 /* If there are variable arguments, then we won't pass anything
5718 in registers in 32-bit mode. */
5720 {
5728 }
5730 /* Use ecx and edx registers if function has fastcall attribute,
5731 else look for regparm information. */
5733 {
5736 {
5739 }
5741 {
5744 }
5745 else
5747 }
5749 /* Set up the number of SSE registers used for passing SFmode
5750 and DFmode arguments. Warn for mismatching ABI. */
5752 }
5753 }
5755 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5756 But in the case of vector types, it is some vector mode.
5758 When we have only some of our vector isa extensions enabled, then there
5759 are some modes for which vector_mode_supported_p is false. For these
5760 modes, the generic vector support in gcc will choose some non-vector mode
5761 in order to implement the type. By computing the natural mode, we'll
5762 select the proper ABI location for the operand and not depend on whatever
5763 the middle-end decides to do with these vector types.
5765 The midde-end can't deal with the vector types > 16 bytes. In this
5766 case, we return the original mode and warn ABI change if CUM isn't
5767 NULL. */
5769 static enum machine_mode
5771 {
5775 {
5778 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5780 {
5785 else
5788 /* Get the mode which has this inner mode and number of units. */
5792 {
5794 {
5798 && !warnedavx
5800 {
5804 }
5806 }
5808 {
5812 && !warnedsse
5814 {
5818 }
5820 }
5821 else
5823 }
5826 }
5827 }
5830 }
5832 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5833 this may not agree with the mode that the type system has chosen for the
5834 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5835 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5837 static rtx
5840 {
5841 rtx tmp;
5845 else
5846 {
5850 }
5853 }
5855 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5856 of this code is to classify each 8bytes of incoming argument by the register
5857 class and assign registers accordingly. */
5859 /* Return the union class of CLASS1 and CLASS2.
5860 See the x86-64 PS ABI for details. */
5862 static enum x86_64_reg_class
5864 {
5865 /* Rule #1: If both classes are equal, this is the resulting class. */
5869 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5870 the other class. */
5876 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5880 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5888 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5889 MEMORY is used. */
5898 /* Rule #6: Otherwise class SSE is used. */
5900 }
5902 /* Classify the argument of type TYPE and mode MODE.
5903 CLASSES will be filled by the register class used to pass each word
5904 of the operand. The number of words is returned. In case the parameter
5905 should be passed in memory, 0 is returned. As a special case for zero
5906 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5908 BIT_OFFSET is used internally for handling records and specifies offset
5909 of the offset in bits modulo 256 to avoid overflow cases.
5911 See the x86-64 PS ABI for details.
5912 */
5914 static int
5917 {
5918 HOST_WIDE_INT bytes =
5920 int words
5923 /* Variable sized entities are always passed/returned in memory. */
5931 /* Special case check for pointer to shared, on 64-bit target. */
5935 {
5938 }
5941 {
5943 tree field;
5946 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5953 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5954 signalize memory class, so handle it as special case. */
5956 {
5959 }
5961 /* Classify each field of record and merge classes. */
5963 {
5965 /* And now merge the fields of structure. */
5967 {
5969 {
5975 /* Bitfields are always classified as integer. Handle them
5976 early, since later code would consider them to be
5977 misaligned integers. */
5979 {
5988 }
5989 else
5990 {
5995 /* Flexible array member is ignored. */
6002 {
6006 {
6009 "the ABI of passing struct with"
6010 " a flexible array member has"
6012 }
6014 }
6016 subclasses,
6026 }
6027 }
6028 }
6032 /* Arrays are handled as small records. */
6033 {
6040 /* The partial classes are now full classes. */
6051 }
6054 /* Unions are similar to RECORD_TYPE but offset is always 0.
6055 */
6057 {
6059 {
6067 bit_offset);
6072 }
6073 }
6078 }
6081 {
6082 /* When size > 16 bytes, if the first one isn't
6083 X86_64_SSE_CLASS or any other ones aren't
6084 X86_64_SSEUP_CLASS, everything should be passed in
6085 memory. */
6092 }
6094 /* Final merger cleanup. */
6096 {
6097 /* If one class is MEMORY, everything should be passed in
6098 memory. */
6102 /* The X86_64_SSEUP_CLASS should be always preceded by
6103 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6107 {
6108 /* The first one should never be X86_64_SSEUP_CLASS. */
6111 }
6113 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6114 everything should be passed in memory. */
6117 {
6120 /* The first one should never be X86_64_X87UP_CLASS. */
6123 {
6126 "the ABI of passing union with long double"
6128 }
6130 }
6131 }
6133 }
6135 /* Compute alignment needed. We align all types to natural boundaries with
6136 exception of XFmode that is aligned to 64bits. */
6138 {
6147 /* Misaligned fields are always returned in memory. */
6150 }
6152 /* for V1xx modes, just use the base mode */
6157 /* Classification of atomic types. */
6159 {
6175 {
6179 {
6182 }
6184 {
6187 }
6189 {
6193 }
6195 {
6198 }
6199 else
6201 }
6208 /* OImode shouldn't be used directly. */
6215 else
6233 else
6234 {
6238 {
6241 "the ABI of passing structure with complex float"
6243 }
6246 }
6255 /* This modes is larger than 16 bytes. */
6298 else
6302 }
6303 }
6305 /* Examine the argument and return set number of register required in each
6306 class. Return 0 iff parameter should be passed in memory. */
6307 static int
6310 {
6320 {
6342 }
6344 }
6346 /* Construct container for the argument used by GCC interface. See
6347 FUNCTION_ARG for the detailed description. */
6349 static rtx
6353 {
6354 /* The following variables hold the static issued_error state. */
6368 rtx ret;
6379 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6380 some less clueful developer tries to use floating-point anyway. */
6382 {
6384 {
6386 {
6389 }
6390 }
6392 {
6395 }
6397 }
6399 /* Likewise, error if the ABI requires us to return values in the
6400 x87 registers and the user specified -mno-80387. */
6406 {
6408 {
6411 }
6413 }
6415 /* First construct simple cases. Avoid SCmode, since we want to use
6416 single register to pass this type. */
6419 {
6434 /* Zero sized array, struct or class. */
6438 }
6465 /* Otherwise figure out the entries of the PARALLEL. */
6467 {
6471 {
6476 /* Merge TImodes on aligned occasions here too. */
6478 tmpmode
6482 else
6484 /* We've requested 24 bytes we
6485 don't have mode for. Use DImode. */
6492 intreg++;
6500 sse_regno++;
6508 sse_regno++;
6513 {
6519 {
6521 i++;
6522 }
6523 else
6536 }
6542 sse_regno++;
6546 }
6547 }
6549 /* Empty aligned struct, union or class. */
6557 }
6559 /* Update the data in CUM to advance over an argument of mode MODE
6560 and data type TYPE. (TYPE is null for libcalls where that information
6561 may not be available.) */
6563 static void
6566 HOST_WIDE_INT words)
6567 {
6569 {
6576 /* FALLTHRU */
6587 {
6590 }
6594 /* OImode shouldn't be used directly. */
6603 /* FALLTHRU */
6619 {
6624 {
6627 }
6628 }
6638 {
6643 {
6646 }
6647 }
6649 }
6650 }
6652 static void
6655 {
6658 /* Unnamed 256bit vector mode parameters are passed on stack. */
6664 {
6669 }
6670 else
6671 {
6675 }
6676 }
6678 static void
6680 HOST_WIDE_INT words)
6681 {
6682 /* Otherwise, this should be passed indirect. */
6687 {
6690 }
6691 }
6693 /* Update the data in CUM to advance over an argument of mode MODE and
6694 data type TYPE. (TYPE is null for libcalls where that information
6695 may not be available.) */
6697 static void
6700 {
6706 else
6717 else
6719 }
6721 /* Define where to put the arguments to a function.
6722 Value is zero to push the argument on the stack,
6723 or a hard register in which to store the argument.
6725 MODE is the argument's machine mode.
6726 TYPE is the data type of the argument (as a tree).
6727 This is null for libcalls where that information may
6728 not be available.
6729 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6730 the preceding args and about the function being called.
6731 NAMED is nonzero if this argument is a named parameter
6732 (otherwise it is an extra parameter matching an ellipsis). */
6734 static rtx
6738 {
6741 /* Avoid the AL settings for the Unix64 ABI. */
6746 {
6753 /* FALLTHRU */
6759 {
6762 /* Fastcall allocates the first two DWORD (SImode) or
6763 smaller arguments to ECX and EDX if it isn't an
6764 aggregate type . */
6766 {
6772 /* ECX not EAX is the first allocated register. */
6775 }
6777 }
6786 /* FALLTHRU */
6788 /* In 32bit, we pass TImode in xmm registers. */
6796 {
6798 {
6802 }
6806 }
6810 /* OImode shouldn't be used directly. */
6820 {
6824 }
6834 {
6836 {
6840 }
6844 }
6846 }
6849 }
6851 static rtx
6854 {
6855 /* Handle a hidden AL argument containing number of registers
6856 for varargs x86-64 functions. */
6860 ? X86_64_SSE_REGPARM_MAX
6865 {
6875 /* Unnamed 256bit vector mode parameters are passed on stack. */
6879 }
6885 }
6887 static rtx
6890 HOST_WIDE_INT bytes)
6891 {
6894 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6895 We use value of -2 to specify that current function call is MSABI. */
6899 /* If we've run out of registers, it goes on the stack. */
6905 /* Only floating point modes are passed in anything but integer regs. */
6907 {
6910 else
6911 {
6914 /* Unnamed floating parameters are passed in both the
6915 SSE and integer registers. */
6921 }
6922 }
6923 /* Handle aggregated types passed in register. */
6925 {
6930 }
6933 }
6935 /* Return where to put the arguments to a function.
6936 Return zero to push the argument on the stack, or a hard register in which to store the argument.
6938 MODE is the argument's machine mode. TYPE is the data type of the
6939 argument. It is null for libcalls where that information may not be
6940 available. CUM gives information about the preceding args and about
6941 the function being called. NAMED is nonzero if this argument is a
6942 named parameter (otherwise it is an extra parameter matching an
6943 ellipsis). */
6945 static rtx
6948 {
6952 rtx arg;
6956 else
6960 /* To simplify the code below, represent vector types with a vector mode
6961 even if MMX/SSE are not active. */
6969 else
6973 }
6975 /* A C expression that indicates when an argument must be passed by
6976 reference. If nonzero for an argument, a copy of that argument is
6977 made in memory and a pointer to the argument is passed instead of
6978 the argument itself. The pointer is passed in whatever way is
6979 appropriate for passing a pointer to that type. */
6981 static bool
6985 {
6988 /* See Windows x64 Software Convention. */
6990 {
6993 {
6994 /* Arrays are passed by reference. */
6999 {
7000 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7001 are passed by reference. */
7003 }
7004 }
7006 /* __m128 is passed by reference. */
7012 }
7013 }
7018 }
7020 /* Return true when TYPE should be 128bit aligned for 32bit argument
7021 passing ABI. XXX: This function is obsolete and is only used for
7022 checking psABI compatibility with previous versions of GCC. */
7024 static bool
7026 {
7038 {
7039 /* Walk the aggregates recursively. */
7041 {
7045 {
7046 tree field;
7048 /* Walk all the structure fields. */
7050 {
7054 }
7056 }
7059 /* Just for use if some languages passes arrays by value. */
7066 }
7067 }
7069 }
7071 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7072 XXX: This function is obsolete and is only used for checking psABI
7073 compatibility with previous versions of GCC. */
7075 static unsigned int
7078 {
7079 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7080 natural boundaries. */
7082 {
7083 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7084 make an exception for SSE modes since these require 128bit
7085 alignment.
7087 The handling here differs from field_alignment. ICC aligns MMX
7088 arguments to 4 byte boundaries, while structure fields are aligned
7089 to 8 byte boundaries. */
7091 {
7094 }
7095 else
7096 {
7099 }
7100 }
7104 }
7106 /* Return true when TYPE should be 128bit aligned for 32bit argument
7107 passing ABI. */
7109 static bool
7111 {
7121 {
7122 /* Walk the aggregates recursively. */
7124 {
7128 {
7129 tree field;
7131 /* Walk all the structure fields. */
7133 field;
7135 {
7139 }
7141 }
7144 /* Just for use if some languages passes arrays by value. */
7151 }
7152 }
7153 else
7157 }
7159 /* Gives the alignment boundary, in bits, of an argument with the
7160 specified mode and type. */
7162 static unsigned int
7164 {
7167 {
7168 /* Since the main variant type is used for call, we convert it to
7169 the main variant type. */
7172 }
7173 else
7177 else
7178 {
7183 {
7184 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7186 {
7189 }
7195 }
7198 && !warned
7200 saved_align))
7201 {
7204 "The ABI for passing parameters with %d-byte"
7207 }
7208 }
7211 }
7213 /* Return true if N is a possible register number of function value. */
7215 static bool
7217 {
7219 {
7224 /* TODO: The function should depend on current function ABI but
7225 builtins.c would need updating then. Therefore we use the
7226 default ABI. */
7238 }
7241 }
7243 /* Define how to find the value returned by a function.
7244 VALTYPE is the data type of the value (as a tree).
7245 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7246 otherwise, FUNC is 0. */
7248 static rtx
7251 {
7254 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7255 we normally prevent this case when mmx is not available. However
7256 some ABIs may require the result to be returned like DImode. */
7260 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7261 we prevent this case when sse is not available. However some ABIs
7262 may require the result to be returned like integer TImode. */
7267 /* 32-byte vector modes in %ymm0. */
7271 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7274 else
7275 /* Most things go in %eax. */
7278 /* Override FP return register with %xmm0 for local functions when
7279 SSE math is enabled or for functions with sseregparm attribute. */
7281 {
7286 }
7288 /* OImode shouldn't be used directly. */
7292 }
7294 static rtx
7296 const_tree valtype)
7297 {
7298 rtx ret;
7300 /* Handle libcalls, which don't provide a type node. */
7302 {
7306 {
7325 }
7328 }
7331 {
7332 /* Pointers are always returned in word_mode. */
7334 }
7340 /* For zero sized structures, construct_container returns NULL, but we
7341 need to keep rest of compiler happy by returning meaningful value. */
7346 }
7348 static rtx
7350 const_tree valtype)
7351 {
7355 {
7357 {
7376 }
7377 }
7379 }
7381 static rtx
7384 {
7396 else
7398 }
7400 static rtx
7403 {
7409 }
7411 /* Pointer function arguments and return values are promoted to
7412 word_mode. */
7414 static enum machine_mode
7418 {
7420 {
7422 {
7425 }
7428 }
7430 for_return);
7431 }
7433 /* Return true if a structure, union or array with MODE containing FIELD
7434 should be accessed using BLKmode. */
7436 static bool
7438 {
7439 /* Union with XFmode must be in BLKmode. */
7443 }
7445 rtx
7447 {
7449 }
7451 /* Return true iff type is returned in memory. */
7453 static bool ATTRIBUTE_UNUSED
7455 {
7456 HOST_WIDE_INT size;
7467 {
7468 /* User-created vectors small enough to fit in EAX. */
7472 /* MMX/3dNow values are returned in MM0,
7473 except when it doesn't exits or the ABI prescribes otherwise. */
7477 /* SSE values are returned in XMM0, except when it doesn't exist. */
7481 /* AVX values are returned in YMM0, except when it doesn't exist. */
7484 }
7492 /* OImode shouldn't be used directly. */
7496 }
7498 static bool ATTRIBUTE_UNUSED
7500 {
7503 }
7505 static bool ATTRIBUTE_UNUSED
7507 {
7510 /* __m128 is returned in xmm0. */
7517 /* Otherwise, the size must be exactly in [1248]. */
7519 }
7521 static bool
7523 {
7524 #ifdef SUBTARGET_RETURN_IN_MEMORY
7526 #else
7530 {
7533 else
7535 }
7536 else
7538 #endif
7539 }
7541 /* When returning SSE vector types, we have a choice of either
7542 (1) being abi incompatible with a -march switch, or
7543 (2) generating an error.
7544 Given no good solution, I think the safest thing is one warning.
7545 The user won't be able to use -Werror, but....
7547 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7548 called in response to actually generating a caller or callee that
7549 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7550 via aggregate_value_p for general type probing from tree-ssa. */
7552 static rtx
7554 {
7558 {
7559 /* Look at the return type of the function, not the function type. */
7563 {
7566 {
7570 }
7571 }
7574 {
7576 {
7580 }
7581 }
7582 }
7585 }
7587 \f
7588 /* Create the va_list data type. */
7590 /* Returns the calling convention specific va_list date type.
7591 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7593 static tree
7595 {
7598 /* For i386 we use plain pointer to argument area. */
7608 unsigned_type_node);
7611 unsigned_type_node);
7614 ptr_type_node);
7617 ptr_type_node);
7636 /* The correct type is an array type of one element. */
7638 }
7640 /* Setup the builtin va_list data type and for 64-bit the additional
7641 calling convention specific va_list data types. */
7643 static tree
7645 {
7648 /* Initialize abi specific va_list builtin types. */
7650 {
7651 tree t;
7653 {
7658 }
7659 else
7660 {
7665 }
7667 {
7672 }
7673 else
7674 {
7679 }
7680 }
7683 }
7685 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7687 static void
7689 {
7691 alias_set_type set;
7694 /* GPR size of varargs save area. */
7697 else
7700 /* FPR size of varargs save area. We don't need it if we don't pass
7701 anything in SSE registers. */
7704 else
7718 {
7726 }
7729 {
7733 /* Now emit code to save SSE registers. The AX parameter contains number
7734 of SSE parameter registers used to call this function, though all we
7735 actually check here is the zero/non-zero status. */
7740 label));
7742 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7743 we used movdqa (i.e. TImode) instead? Perhaps even better would
7744 be if we could determine the real mode of the data, via a hook
7745 into pass_stdarg. Ignore all that for now. */
7755 {
7764 }
7767 }
7768 }
7770 static void
7772 {
7776 /* Reset to zero, as there might be a sysv vaarg used
7777 before. */
7782 {
7793 }
7794 }
7796 static void
7800 {
7802 CUMULATIVE_ARGS next_cum;
7803 tree fntype;
7805 /* This argument doesn't appear to be used anymore. Which is good,
7806 because the old code here didn't suppress rtl generation. */
7814 /* For varargs, we do not want to skip the dummy va_dcl argument.
7815 For stdargs, we do want to skip the last named argument. */
7823 else
7825 }
7827 /* Checks if TYPE is of kind va_list char *. */
7829 static bool
7831 {
7832 tree canonic;
7834 /* For 32-bit it is always true. */
7840 }
7842 /* Implement va_start. */
7844 static void
7846 {
7850 tree type;
7851 rtx ovf_rtx;
7855 {
7858 /* When we are splitting the stack, we can't refer to the stack
7859 arguments using internal_arg_pointer, because they may be on
7860 the old stack. The split stack prologue will arrange to
7861 leave a pointer to the old stack arguments in a scratch
7862 register, which we here copy to a pseudo-register. The split
7863 stack prologue can't set the pseudo-register directly because
7864 it (the prologue) runs before any registers have been saved. */
7868 {
7882 }
7883 }
7885 /* Only 64bit target needs something special. */
7887 {
7890 else
7891 {
7900 }
7902 }
7911 /* The following should be folded into the MEM_REF offset. */
7921 /* Count number of gp and fp argument registers used. */
7927 {
7933 }
7936 {
7942 }
7944 /* Find the overflow area. */
7948 else
7958 {
7959 /* Find the register save area.
7960 Prologue of the function save it right above stack frame. */
7968 }
7969 }
7971 /* Implement va_arg. */
7973 static tree
7976 {
7983 rtx container;
7985 tree ptrtype;
7989 /* Only 64bit target needs something special. */
8013 {
8020 /* Unnamed 256bit vector mode parameters are passed on stack. */
8022 {
8025 }
8033 }
8035 /* Pull the value out of the saved registers. */
8040 {
8054 /* In case we are passing structure, verify that it is consecutive block
8055 on the register save area. If not we need to do moves. */
8057 {
8058 /* Verify that all registers are strictly consecutive */
8060 {
8064 {
8069 }
8070 }
8071 else
8072 {
8076 {
8081 }
8082 }
8083 }
8085 {
8088 }
8089 else
8090 {
8093 }
8095 /* First ensure that we fit completely in registers. */
8097 {
8104 }
8106 {
8114 }
8116 /* Compute index to start of area used for integer regs. */
8118 {
8119 /* int_addr = gpr + sav; */
8122 }
8124 {
8125 /* sse_addr = fpr + sav; */
8128 }
8130 {
8134 /* addr = &temp; */
8139 {
8143 tree piece_type;
8144 tree addr_type;
8145 tree daddr_type;
8154 {
8159 }
8163 else
8170 {
8173 }
8174 else
8175 {
8178 }
8185 {
8190 }
8191 else
8192 {
8193 tree copy
8198 }
8200 }
8201 }
8204 {
8208 }
8211 {
8215 }
8220 }
8222 /* ... otherwise out of the overflow area. */
8224 /* When we align parameter on stack for caller, if the parameter
8225 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8226 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8227 here with caller. */
8232 /* Care for on-stack alignment if needed. */
8235 else
8236 {
8241 }
8258 }
8259 \f
8260 /* Return true if OPNUM's MEM should be matched
8261 in movabs* patterns. */
8263 bool
8265 {
8277 }
8278 \f
8279 /* Initialize the table of extra 80387 mathematical constants. */
8281 static void
8283 {
8285 {
8291 };
8295 {
8297 /* Ensure each constant is rounded to XFmode precision. */
8300 }
8303 }
8305 /* Return non-zero if the constant is something that
8306 can be loaded with a special instruction. */
8308 int
8310 {
8313 REAL_VALUE_TYPE r;
8325 /* For XFmode constants, try to find a special 80387 instruction when
8326 optimizing for size or on those CPUs that benefit from them. */
8329 {
8338 }
8340 /* Load of the constant -0.0 or -1.0 will be split as
8341 fldz;fchs or fld1;fchs sequence. */
8348 }
8350 /* Return the opcode of the special instruction to be used to load
8351 the constant X. */
8355 {
8357 {
8377 }
8378 }
8380 /* Return the CONST_DOUBLE representing the 80387 constant that is
8381 loaded by the specified special instruction. The argument IDX
8382 matches the return value from standard_80387_constant_p. */
8384 rtx
8386 {
8393 {
8404 }
8407 XFmode);
8408 }
8410 /* Return 1 if X is all 0s and 2 if x is all 1s
8411 in supported SSE/AVX vector mode. */
8413 int
8415 {
8422 {
8437 }
8440 }
8442 /* Return the opcode of the special instruction to be used to load
8443 the constant X. */
8447 {
8449 {
8452 {
8469 }
8474 else
8479 }
8481 }
8483 /* Returns true if OP contains a symbol reference */
8485 bool
8487 {
8496 {
8498 {
8504 }
8508 }
8511 }
8513 /* Return true if it is appropriate to emit `ret' instructions in the
8514 body of a function. Do this only if the epilogue is simple, needing a
8515 couple of insns. Prior to reloading, we can't tell how many registers
8516 must be saved, so return false then. Return false if there is no frame
8517 marker to de-allocate. */
8519 bool
8521 {
8527 /* Don't allow more than 32k pop, since that's all we can do
8528 with one instruction. */
8535 }
8536 \f
8537 /* Value should be nonzero if functions must have frame pointers.
8538 Zero means the frame pointer need not be set up (and parms may
8539 be accessed via the stack pointer) in functions that seem suitable. */
8541 static bool
8543 {
8544 /* If we accessed previous frames, then the generated code expects
8545 to be able to access the saved ebp value in our frame. */
8549 /* Several x86 os'es need a frame pointer for other reasons,
8550 usually pertaining to setjmp. */
8554 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
8558 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
8559 allocation is 4GB. */
8563 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8564 turns off the frame pointer by default. Turn it back on now if
8565 we've not got a leaf function. */
8575 }
8577 /* Record that the current function accesses previous call frames. */
8579 void
8581 {
8583 }
8584 \f
8585 #ifndef USE_HIDDEN_LINKONCE
8586 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
8587 # define USE_HIDDEN_LINKONCE 1
8588 # else
8589 # define USE_HIDDEN_LINKONCE 0
8590 # endif
8591 #endif
8595 /* Fills in the label name that should be used for a pc thunk for
8596 the given register. */
8598 static void
8600 {
8605 else
8607 }
8610 /* This function generates code for -fpic that loads %ebx with
8611 the return address of the caller and then returns. */
8613 static void
8615 {
8620 {
8622 tree decl;
8638 #if TARGET_MACHO
8640 {
8649 }
8650 else
8651 #endif
8653 {
8664 }
8665 else
8666 {
8669 }
8675 /* Make sure unwind info is emitted for the thunk if needed. */
8678 /* Pad stack IP move with 4 instructions (two NOPs count
8679 as one instruction). */
8681 {
8686 }
8697 }
8701 }
8703 /* Emit code for the SET_GOT patterns. */
8707 {
8713 {
8714 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8719 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8720 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8721 an unadorned address. */
8726 }
8731 {
8736 #if TARGET_MACHO
8737 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8738 is what will be referenced by the Mach-O PIC subsystem. */
8741 #endif
8745 }
8746 else
8747 {
8755 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8756 is what will be referenced by the Mach-O PIC subsystem. */
8757 #if TARGET_MACHO
8760 else
8763 #endif
8764 }
8770 }
8772 /* Generate an "push" pattern for input ARG. */
8774 static rtx
8776 {
8789 stack_pointer_rtx)),
8790 arg);
8791 }
8793 /* Generate an "pop" pattern for input ARG. */
8795 static rtx
8797 {
8802 arg,
8805 stack_pointer_rtx)));
8806 }
8808 /* Return >= 0 if there is an unused call-clobbered register available
8809 for the entire function. */
8811 static unsigned int
8813 {
8817 {
8819 /* Can't use the same register for both PIC and DRAP. */
8822 else
8827 }
8830 }
8832 /* Return TRUE if we need to save REGNO. */
8834 static bool
8836 {
8846 {
8849 {
8855 }
8856 }
8865 }
8867 /* Return number of saved general prupose registers. */
8869 static int
8871 {
8877 nregs ++;
8879 }
8881 /* Return number of saved SSE registrers. */
8883 static int
8885 {
8893 nregs ++;
8895 }
8897 /* Given FROM and TO register numbers, say whether this elimination is
8898 allowed. If stack alignment is needed, we can only replace argument
8899 pointer with hard frame pointer, or replace frame pointer with stack
8900 pointer. Otherwise, frame pointer elimination is automatically
8901 handled and all other eliminations are valid. */
8903 static bool
8905 {
8911 else
8913 }
8915 /* Return the offset between two registers, one to be eliminated, and the other
8916 its replacement, at the start of a routine. */
8918 HOST_WIDE_INT
8920 {
8929 else
8930 {
8938 }
8939 }
8941 /* In a dynamically-aligned function, we can't know the offset from
8942 stack pointer to frame pointer, so we must ensure that setjmp
8943 eliminates fp against the hard fp (%ebp) rather than trying to
8944 index from %esp up to the top of the frame across a gap that is
8945 of unknown (at compile-time) size. */
8946 static rtx
8948 {
8950 }
8952 /* When using -fsplit-stack, the allocation routines set a field in
8953 the TCB to the bottom of the stack plus this much space, measured
8954 in bytes. */
8956 #define SPLIT_STACK_AVAILABLE 256
8958 /* Fill structure ix86_frame about frame of currently computed function. */
8960 static void
8962 {
8964 HOST_WIDE_INT offset;
8967 HOST_WIDE_INT to_allocate;
8975 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
8976 function prologues and leaf. */
8980 {
8985 }
8991 /* For SEH we have to limit the amount of code movement into the prologue.
8992 At present we do this via a BLOCKAGE, at which point there's very little
8993 scheduling that can be done, which means that there's very little point
8994 in doing anything except PUSHs. */
8998 /* During reload iteration the amount of registers saved can change.
8999 Recompute the value as needed. Do not recompute when amount of registers
9000 didn't change as reload does multiple calls to the function and does not
9001 expect the decision to change within single iteration. */
9004 {
9010 /* The fast prologue uses move instead of push to save registers. This
9011 is significantly longer, but also executes faster as modern hardware
9012 can execute the moves in parallel, but can't do that for push/pop.
9014 Be careful about choosing what prologue to emit: When function takes
9015 many instructions to execute we may use slow version as well as in
9016 case function is known to be outside hot spot (this is known with
9017 feedback only). Weight the size of function by number of registers
9018 to save as it is cheap to use one or two push instructions but very
9019 slow to use many of them. */
9023 || (flag_branch_probabilities
9026 else
9029 }
9031 frame->save_regs_using_mov
9033 /* If static stack checking is enabled and done with probes,
9034 the registers need to be saved before allocating the frame. */
9037 /* Skip return address. */
9040 /* Skip pushed static chain. */
9044 /* Skip saved base pointer. */
9049 /* The traditional frame pointer location is at the top of the frame. */
9052 /* Register save area */
9056 /* On SEH target, registers are pushed just before the frame pointer
9057 location. */
9061 /* Align and set SSE register save area. */
9063 {
9064 /* The only ABI that has saved SSE registers (Win64) also has a
9065 16-byte aligned default stack, and thus we don't need to be
9066 within the re-aligned local stack frame to save them. */
9070 }
9073 /* The re-aligned stack starts here. Values before this point are not
9074 directly comparable with values below this point. In order to make
9075 sure that no value happens to be the same before and after, force
9076 the alignment computation below to add a non-zero value. */
9080 /* Va-arg area */
9084 /* Align start of frame for local function. */
9093 /* Frame pointer points here. */
9098 /* Add outgoing arguments area. Can be skipped if we eliminated
9099 all the function calls as dead code.
9100 Skipping is however impossible when function calls alloca. Alloca
9101 expander assumes that last crtl->outgoing_args_size
9102 of stack frame are unused. */
9106 {
9109 }
9110 else
9113 /* Align stack boundary. Only needed if we're calling another function
9114 or using alloca. */
9119 /* We've reached end of stack frame. */
9122 /* Size prologue needs to allocate. */
9133 {
9139 }
9140 else
9144 /* The SEH frame pointer location is near the bottom of the frame.
9145 This is enforced by the fact that the difference between the
9146 stack pointer and the frame pointer is limited to 240 bytes in
9147 the unwind data structure. */
9149 {
9150 HOST_WIDE_INT diff;
9152 /* If we can leave the frame pointer where it is, do so. Also, returns
9153 the establisher frame for __builtin_frame_address (0). */
9158 {
9159 /* Ideally we'd determine what portion of the local stack frame
9160 (within the constraint of the lowest 240) is most heavily used.
9161 But without that complication, simply bias the frame pointer
9162 by 128 bytes so as to maximize the amount of the local stack
9163 frame that is addressable with 8-bit offsets. */
9165 }
9166 }
9167 }
9169 /* This is semi-inlined memory_address_length, but simplified
9170 since we know that we're always dealing with reg+offset, and
9171 to avoid having to create and discard all that rtl. */
9175 {
9179 {
9180 /* EBP and R13 cannot be encoded without an offset. */
9182 }
9186 /* ESP and R12 must be encoded with a SIB byte. */
9188 len++;
9191 }
9193 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9194 The valid base registers are taken from CFUN->MACHINE->FS. */
9196 static rtx
9198 {
9204 {
9205 /* Choose the base register most likely to allow the most scheduling
9206 opportunities. Generally FP is valid throughout the function,
9207 while DRAP must be reloaded within the epilogue. But choose either
9208 over the SP due to increased encoding size. */
9211 {
9214 }
9216 {
9219 }
9221 {
9224 }
9225 }
9226 else
9227 {
9228 HOST_WIDE_INT toffset;
9231 /* Choose the base register with the smallest address encoding.
9232 With a tie, choose FP > DRAP > SP. */
9234 {
9238 }
9240 {
9244 {
9248 }
9249 }
9251 {
9255 {
9259 }
9260 }
9261 }
9265 }
9267 /* Emit code to save registers in the prologue. */
9269 static void
9271 {
9273 rtx insn;
9277 {
9280 }
9281 }
9283 /* Emit a single register save at CFA - CFA_OFFSET. */
9285 static void
9287 HOST_WIDE_INT cfa_offset)
9288 {
9296 /* For SSE saves, we need to indicate the 128-bit alignment. */
9307 /* When saving registers into a re-aligned local stack frame, avoid
9308 any tricky guessing by dwarf2out. */
9310 {
9314 {
9315 /* A bit of a hack. We force the DRAP register to be saved in
9316 the re-aligned stack frame, which provides us with a copy
9317 of the CFA that will last past the prologue. Install it. */
9323 }
9324 else
9325 {
9326 /* The frame pointer is a stable reference within the
9327 aligned frame. Use it. */
9334 }
9335 }
9337 /* The memory may not be relative to the current CFA register,
9338 which means that we may need to generate a new pattern for
9339 use by the unwind info. */
9341 {
9346 }
9347 }
9349 /* Emit code to save registers using MOV insns.
9350 First register is stored at CFA - CFA_OFFSET. */
9351 static void
9353 {
9358 {
9361 }
9362 }
9364 /* Emit code to save SSE registers using MOV insns.
9365 First register is stored at CFA - CFA_OFFSET. */
9366 static void
9368 {
9373 {
9376 }
9377 }
9381 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9382 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9383 Don't add the note if the previously saved value will be left untouched
9384 within stack red-zone till return, as unwinders can find the same value
9385 in the register and on the stack. */
9387 static void
9389 {
9395 {
9398 }
9399 else
9400 queued_cfa_restores
9402 }
9404 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9406 static void
9408 {
9409 rtx last;
9413 ;
9418 }
9420 /* Expand prologue or epilogue stack adjustment.
9421 The pattern exist to put a dependency on all ebp-based memory accesses.
9422 STYLE should be negative if instructions should be marked as frame related,
9423 zero if %r11 register is live and cannot be freely used and positive
9424 otherwise. */
9426 static void
9429 {
9431 rtx insn;
9438 else
9439 {
9440 rtx tmp;
9441 /* r11 is used by indirect sibcall return as well, set before the
9442 epilogue and used after the epilogue. */
9445 else
9446 {
9450 }
9456 }
9463 {
9464 rtx r;
9474 }
9476 {
9479 {
9483 }
9484 }
9487 {
9492 {
9495 }
9497 {
9500 }
9501 else
9502 {
9503 /* Else there are two possibilities: SP itself, which we set
9504 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9505 taken care of this by hand along the eh_return path. */
9508 }
9512 }
9513 }
9515 /* Find an available register to be used as dynamic realign argument
9516 pointer regsiter. Such a register will be written in prologue and
9517 used in begin of body, so it must not be
9518 1. parameter passing register.
9519 2. GOT pointer.
9520 We reuse static-chain register if it is available. Otherwise, we
9521 use DI for i386 and R13 for x86-64. We chose R13 since it has
9522 shorter encoding.
9524 Return: the regno of chosen register. */
9526 static unsigned int
9528 {
9532 {
9533 /* Use R13 for nested function or function need static chain.
9534 Since function with tail call may use any caller-saved
9535 registers in epilogue, DRAP must not use caller-saved
9536 register in such case. */
9541 }
9542 else
9543 {
9544 /* Use DI for nested function or function need static chain.
9545 Since function with tail call may use any caller-saved
9546 registers in epilogue, DRAP must not use caller-saved
9547 register in such case. */
9551 /* Reuse static chain register if it isn't used for parameter
9552 passing. */
9554 {
9558 }
9560 }
9561 }
9563 /* Return minimum incoming stack alignment. */
9565 static unsigned int
9567 {
9570 /* Prefer the one specified at command line. */
9573 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9574 if -mstackrealign is used, it isn't used for sibcall check and
9575 estimated stack alignment is 128bit. */
9577 && !TARGET_64BIT
9578 && ix86_force_align_arg_pointer
9581 else
9584 /* Incoming stack alignment can be changed on individual functions
9585 via force_align_arg_pointer attribute. We use the smallest
9586 incoming stack boundary. */
9592 /* The incoming stack frame has to be aligned at least at
9593 parm_stack_boundary. */
9597 /* Stack at entrance of main is aligned by runtime. We use the
9598 smallest incoming stack boundary. */
9606 }
9608 /* Update incoming stack boundary and estimated stack alignment. */
9610 static void
9612 {
9613 ix86_incoming_stack_boundary
9616 /* x86_64 vararg needs 16byte stack alignment for register save
9617 area. */
9622 }
9624 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9625 needed or an rtx for DRAP otherwise. */
9627 static rtx
9629 {
9634 {
9635 /* Assign DRAP to vDRAP and returns vDRAP */
9637 rtx drap_vreg;
9638 rtx arg_ptr;
9651 {
9654 }
9656 }
9657 else
9659 }
9661 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9663 static rtx
9665 {
9667 }
9670 rtx reg;
9672 };
9674 /* Return a short-lived scratch register for use on function entry.
9675 In 32-bit mode, it is valid only after the registers are saved
9676 in the prologue. This register must be released by means of
9677 release_scratch_register_on_entry once it is dead. */
9679 static void
9681 {
9687 {
9688 /* We always use R11 in 64-bit mode. */
9690 }
9691 else
9692 {
9694 bool fastcall_p
9696 bool thiscall_p
9700 int drap_regno
9703 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9704 for the static chain register. */
9708 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
9709 for the static chain register. */
9714 /* ecx is the static chain register. */
9716 && !static_chain_p
9721 /* esi is the static chain register. */
9727 else
9728 {
9731 }
9732 }
9736 {
9739 }
9740 }
9742 /* Release a scratch register obtained from the preceding function. */
9744 static void
9746 {
9748 {
9752 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9758 }
9759 }
9761 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9763 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9765 static void
9767 {
9768 /* We skip the probe for the first interval + a small dope of 4 words and
9769 probe that many bytes past the specified size to maintain a protection
9770 area at the botton of the stack. */
9774 /* See if we have a constant small number of probes to generate. If so,
9775 that's the easy case. The run-time loop is made up of 11 insns in the
9776 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9777 for n # of intervals. */
9779 {
9783 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9784 values of N from 1 until it exceeds SIZE. If only one probe is
9785 needed, this will not generate any code. Then adjust and probe
9786 to PROBE_INTERVAL + SIZE. */
9788 {
9790 {
9793 }
9794 else
9801 }
9805 else
9813 /* Adjust back to account for the additional first interval. */
9817 }
9819 /* Otherwise, do the same as above, but in a loop. Note that we must be
9820 extra careful with variables wrapping around because we might be at
9821 the very top (or the very bottom) of the address space and we have
9822 to be able to handle this case properly; in particular, we use an
9823 equality test for the loop condition. */
9824 else
9825 {
9826 HOST_WIDE_INT rounded_size;
9832 /* Step 1: round SIZE to the previous multiple of the interval. */
9837 /* Step 2: compute initial and final value of the loop counter. */
9839 /* SP = SP_0 + PROBE_INTERVAL. */
9844 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
9848 stack_pointer_rtx)));
9851 /* Step 3: the loop
9853 while (SP != LAST_ADDR)
9854 {
9855 SP = SP + PROBE_INTERVAL
9856 probe at SP
9857 }
9859 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
9860 values of N from 1 until it is equal to ROUNDED_SIZE. */
9865 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
9866 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
9869 {
9874 }
9876 /* Adjust back to account for the additional first interval. */
9882 }
9886 /* Even if the stack pointer isn't the CFA register, we need to correctly
9887 describe the adjustments made to it, in particular differentiate the
9888 frame-related ones from the frame-unrelated ones. */
9890 {
9903 }
9905 /* Make sure nothing is scheduled before we are done. */
9907 }
9909 /* Adjust the stack pointer up to REG while probing it. */
9913 {
9923 /* Jump to END_LAB if SP == LAST_ADDR. */
9931 /* SP = SP + PROBE_INTERVAL. */
9935 /* Probe at SP. */
9946 }
9948 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
9949 inclusive. These are offsets from the current stack pointer. */
9951 static void
9953 {
9954 /* See if we have a constant small number of probes to generate. If so,
9955 that's the easy case. The run-time loop is made up of 7 insns in the
9956 generic case while the compile-time loop is made up of n insns for n #
9957 of intervals. */
9959 {
9960 HOST_WIDE_INT i;
9962 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
9963 it exceeds SIZE. If only one probe is needed, this will not
9964 generate any code. Then probe at FIRST + SIZE. */
9971 }
9973 /* Otherwise, do the same as above, but in a loop. Note that we must be
9974 extra careful with variables wrapping around because we might be at
9975 the very top (or the very bottom) of the address space and we have
9976 to be able to handle this case properly; in particular, we use an
9977 equality test for the loop condition. */
9978 else
9979 {
9986 /* Step 1: round SIZE to the previous multiple of the interval. */
9991 /* Step 2: compute initial and final value of the loop counter. */
9993 /* TEST_OFFSET = FIRST. */
9996 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10000 /* Step 3: the loop
10002 while (TEST_ADDR != LAST_ADDR)
10003 {
10004 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10005 probe at TEST_ADDR
10006 }
10008 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10009 until it is equal to ROUNDED_SIZE. */
10014 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10015 that SIZE is equal to ROUNDED_SIZE. */
10020 stack_pointer_rtx,
10025 }
10027 /* Make sure nothing is scheduled before we are done. */
10029 }
10031 /* Probe a range of stack addresses from REG to END, inclusive. These are
10032 offsets from the current stack pointer. */
10036 {
10046 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10054 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10058 /* Probe at TEST_ADDR. */
10071 }
10073 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10074 to be generated in correct form. */
10075 static void
10077 {
10078 /* Check if stack realign is really needed after reload, and
10079 stores result in cfun */
10080 unsigned int incoming_stack_boundary
10089 {
10090 /* After stack_realign_needed is finalized, we can't no longer
10091 change it. */
10094 }
10096 /* If the only reason for frame_pointer_needed is that we conservatively
10097 assumed stack realignment might be needed, but in the end nothing that
10098 needed the stack alignment had been spilled, clear frame_pointer_needed
10099 and say we don't need stack realignment. */
10102 && frame_pointer_needed
10104 && flag_omit_frame_pointer
10106 && !ix86_current_function_calls_tls_descriptor
10115 {
10117 basic_block bb;
10124 HARD_FRAME_POINTER_REGNUM);
10126 {
10127 rtx insn;
10131 set_up_by_prologue))
10132 {
10136 }
10137 }
10151 }
10155 }
10157 /* Expand the prologue into a bunch of separate insns. */
10159 void
10161 {
10166 HOST_WIDE_INT allocate;
10172 /* DRAP should not coexist with stack_realign_fp */
10177 /* Initialize CFA state for before the prologue. */
10181 /* Track SP offset to the CFA. We continue tracking this after we've
10182 swapped the CFA register away from SP. In the case of re-alignment
10183 this is fudged; we're interested to offsets within the local frame. */
10190 {
10191 /* We should have already generated an error for any use of
10192 ms_hook on a nested function. */
10195 /* Check if profiling is active and we shall use profiling before
10196 prologue variant. If so sorry. */
10201 /* In ix86_asm_output_function_label we emitted:
10202 8b ff movl.s %edi,%edi
10203 55 push %ebp
10204 8b ec movl.s %esp,%ebp
10206 This matches the hookable function prologue in Win32 API
10207 functions in Microsoft Windows XP Service Pack 2 and newer.
10208 Wine uses this to enable Windows apps to hook the Win32 API
10209 functions provided by Wine.
10211 What that means is that we've already set up the frame pointer. */
10215 {
10218 /* We've decided to use the frame pointer already set up.
10219 Describe this to the unwinder by pretending that both
10220 push and mov insns happen right here.
10222 Putting the unwind info here at the end of the ms_hook
10223 is done so that we can make absolutely certain we get
10224 the required byte sequence at the start of the function,
10225 rather than relying on an assembler that can produce
10226 the exact encoding required.
10228 However it does mean (in the unpatched case) that we have
10229 a 1 insn window where the asynchronous unwind info is
10230 incorrect. However, if we placed the unwind info at
10231 its correct location we would have incorrect unwind info
10232 in the patched case. Which is probably all moot since
10233 I don't expect Wine generates dwarf2 unwind info for the
10234 system libraries that use this feature. */
10240 stack_pointer_rtx);
10248 /* Note that gen_push incremented m->fs.cfa_offset, even
10249 though we didn't emit the push insn here. */
10253 }
10254 else
10255 {
10256 /* The frame pointer is not needed so pop %ebp again.
10257 This leaves us with a pristine state. */
10259 }
10260 }
10262 /* The first insn of a function that accepts its static chain on the
10263 stack is to push the register that would be filled in by a direct
10264 call. This insn will be skipped by the trampoline. */
10266 {
10270 /* We don't want to interpret this push insn as a register save,
10271 only as a stack adjustment. The real copy of the register as
10272 a save will be done later, if needed. */
10277 }
10279 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10280 of DRAP is needed and stack realignment is really needed after reload */
10282 {
10285 /* Only need to push parameter pointer reg if it is caller saved. */
10287 {
10288 /* Push arg pointer reg */
10291 }
10293 /* Grab the argument pointer. */
10300 /* Align the stack. */
10302 stack_pointer_rtx,
10306 /* Replicate the return address on the stack so that return
10307 address can be reached via (argp - 1) slot. This is needed
10308 to implement macro RETURN_ADDR_RTX and intrinsic function
10309 expand_builtin_return_addr etc. */
10315 /* For the purposes of frame and register save area addressing,
10316 we've started over with a new frame. */
10319 }
10325 {
10326 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10327 slower on all targets. Also sdb doesn't like it. */
10331 /* Push registers now, before setting the frame pointer
10332 on SEH target. */
10334 && TARGET_SEH
10336 {
10340 }
10343 {
10351 }
10352 }
10355 {
10356 /* If saving registers via PUSH, do so now. */
10358 {
10362 }
10364 /* When using red zone we may start register saving before allocating
10365 the stack frame saving one cycle of the prologue. However, avoid
10366 doing this if we have to probe the stack; at least on x86_64 the
10367 stack probe can turn into a call that clobbers a red zone location. */
10369 && (! TARGET_STACK_PROBE
10371 {
10374 }
10375 }
10378 {
10382 /* The computation of the size of the re-aligned stack frame means
10383 that we must allocate the size of the register save area before
10384 performing the actual alignment. Otherwise we cannot guarantee
10385 that there's enough storage above the realignment point. */
10392 /* Align the stack. */
10394 stack_pointer_rtx,
10397 /* For the purposes of register save area addressing, the stack
10398 pointer is no longer valid. As for the value of sp_offset,
10399 see ix86_compute_frame_layout, which we need to match in order
10400 to pass verification of stack_pointer_offset at the end. */
10403 }
10408 {
10409 /* We start to count from ARG_POINTER. */
10412 /* If it was realigned, take into account the fake frame. */
10414 {
10421 /* This over-estimates by 1 minimal-stack-alignment-unit but
10422 mitigates that by counting in the new return address slot. */
10423 current_function_dynamic_stack_size
10425 }
10428 }
10430 /* On SEH target with very large frame size, allocate an area to save
10431 SSE registers (as the very large allocation won't be described). */
10435 {
10436 HOST_WIDE_INT sse_size =
10441 /* No need to do stack checking as the area will be immediately
10442 written. */
10449 }
10451 /* The stack has already been decremented by the instruction calling us
10452 so probe if the size is non-negative to preserve the protection area. */
10454 {
10455 /* We expect the registers to be saved when probes are used. */
10459 {
10462 }
10463 else
10464 {
10472 else
10474 }
10475 }
10478 ;
10481 {
10485 }
10486 else
10487 {
10500 /* Note that SEH directives need to continue tracking the stack
10501 pointer even after the frame pointer has been set up. */
10503 {
10507 {
10511 }
10512 }
10515 {
10520 {
10524 }
10525 }
10530 /* Use the fact that AX still contains ALLOCATE. */
10532 ? gen_pro_epilogue_adjust_stack_di_sub
10539 {
10547 }
10551 {
10558 }
10560 {
10565 }
10566 }
10569 /* If we havn't already set up the frame pointer, do so now. */
10571 {
10583 }
10594 {
10601 }
10604 {
10606 {
10608 {
10618 label));
10622 }
10623 else
10625 }
10626 else
10627 {
10631 }
10632 }
10634 /* In the pic_reg_used case, make sure that the got load isn't deleted
10635 when mcount needs it. Blockage to avoid call movement across mcount
10636 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10637 note. */
10642 {
10643 /* vDRAP is setup but after reload it turns out stack realign
10644 isn't necessary, here we will emit prologue to setup DRAP
10645 without stack realign adjustment */
10648 }
10650 /* Prevent instructions from being scheduled into register save push
10651 sequence when access to the redzone area is done through frame pointer.
10652 The offset between the frame pointer and the stack pointer is calculated
10653 relative to the value of the stack pointer at the end of the function
10654 prologue, and moving instructions that access redzone area via frame
10655 pointer inside push sequence violates this assumption. */
10659 /* Emit cld instruction if stringops are used in the function. */
10663 /* SEH requires that the prologue end within 256 bytes of the start of
10664 the function. Prevent instruction schedules that would extend that.
10665 Further, prevent alloca modifications to the stack pointer from being
10666 combined with prologue modifications. */
10669 }
10671 /* Emit code to restore REG using a POP insn. */
10673 static void
10675 {
10684 {
10685 /* Previously we'd represented the CFA as an expression
10686 like *(%ebp - 8). We've just popped that value from
10687 the stack, which means we need to reset the CFA to
10688 the drap register. This will remain until we restore
10689 the stack pointer. */
10693 /* This means that the DRAP register is valid for addressing too. */
10696 }
10699 {
10706 }
10708 /* When the frame pointer is the CFA, and we pop it, we are
10709 swapping back to the stack pointer as the CFA. This happens
10710 for stack frames that don't allocate other data, so we assume
10711 the stack pointer is now pointing at the return address, i.e.
10712 the function entry state, which makes the offset be 1 word. */
10714 {
10717 {
10725 }
10726 }
10727 }
10729 /* Emit code to restore saved registers using POP insns. */
10731 static void
10733 {
10739 }
10741 /* Emit code and notes for the LEAVE instruction. */
10743 static void
10745 {
10757 {
10765 }
10768 }
10770 /* Emit code to restore saved registers using MOV insns.
10771 First register is restored from CFA - CFA_OFFSET. */
10772 static void
10775 {
10781 {
10790 {
10791 /* Previously we'd represented the CFA as an expression
10792 like *(%ebp - 8). We've just popped that value from
10793 the stack, which means we need to reset the CFA to
10794 the drap register. This will remain until we restore
10795 the stack pointer. */
10799 /* This means that the DRAP register is valid for addressing. */
10801 }
10802 else
10806 }
10807 }
10809 /* Emit code to restore saved registers using MOV insns.
10810 First register is restored from CFA - CFA_OFFSET. */
10811 static void
10814 {
10819 {
10821 rtx mem;
10831 }
10832 }
10834 /* Restore function stack, frame, and registers. */
10836 void
10838 {
10854 /* The FP must be valid if the frame pointer is present. */
10859 /* We must have *some* valid pointer to the stack frame. */
10862 /* The DRAP is never valid at this point. */
10865 /* See the comment about red zone and frame
10866 pointer usage in ix86_expand_prologue. */
10873 /* Determine the CFA offset of the end of the red-zone. */
10876 {
10877 /* The red-zone begins below the return address. */
10880 /* When the register save area is in the aligned portion of
10881 the stack, determine the maximum runtime displacement that
10882 matches up with the aligned frame. */
10886 }
10888 /* Special care must be taken for the normal return case of a function
10889 using eh_return: the eax and edx registers are marked as saved, but
10890 not restored along this path. Adjust the save location to match. */
10894 /* EH_RETURN requires the use of moves to function properly. */
10897 /* SEH requires the use of pops to identify the epilogue. */
10900 /* If we're only restoring one register and sp is not valid then
10901 using a move instruction to restore the register since it's
10902 less work than reloading sp and popping the register. */
10915 && TARGET_USE_LEAVE
10919 else
10923 {
10924 /* Ensure that the entire register save area is addressable via
10925 the stack pointer, if we will restore via sp. */
10930 {
10934 style,
10936 }
10937 }
10939 /* If there are any SSE registers to restore, then we have to do it
10940 via moves, since there's obviously no pop for SSE regs. */
10946 {
10947 rtx t;
10952 /* eh_return epilogues need %ecx added to the stack pointer. */
10954 {
10957 /* Stack align doesn't work with eh_return. */
10959 /* Neither does regparm nested functions. */
10963 {
10971 /* Note that we use SA as a temporary CFA, as the return
10972 address is at the proper place relative to it. We
10973 pretend this happens at the FP restore insn because
10974 prior to this insn the FP would be stored at the wrong
10975 offset relative to SA, and after this insn we have no
10976 other reasonable register to use for the CFA. We don't
10977 bother resetting the CFA to the SP for the duration of
10978 the return insn. */
10991 }
10992 else
10993 {
11001 {
11005 UNITS_PER_WORD));
11007 }
11008 }
11011 }
11012 }
11013 else
11014 {
11015 /* SEH requires that the function end with (1) a stack adjustment
11016 if necessary, (2) a sequence of pops, and (3) a return or
11017 jump instruction. Prevent insns from the function body from
11018 being scheduled into this sequence. */
11020 {
11021 /* Prevent a catch region from being adjacent to the standard
11022 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11023 several other flags that would be interesting to test are
11024 not yet set up. */
11027 else
11029 }
11031 /* First step is to deallocate the stack frame so that we can
11032 pop the registers. Also do it on SEH target for very large
11033 frame as the emitted instructions aren't allowed by the ABI in
11034 epilogues. */
11036 || (TARGET_SEH
11039 {
11044 }
11046 {
11050 style,
11052 }
11055 }
11057 /* If we used a stack pointer and haven't already got rid of it,
11058 then do so now. */
11060 {
11061 /* If the stack pointer is valid and pointing at the frame
11062 pointer store address, then we only need a pop. */
11065 /* Leave results in shorter dependency chains on CPUs that are
11066 able to grok it fast. */
11071 else
11072 {
11074 hard_frame_pointer_rtx,
11077 }
11078 }
11081 {
11083 rtx insn;
11109 }
11111 /* At this point the stack pointer must be valid, and we must have
11112 restored all of the registers. We may not have deallocated the
11113 entire stack frame. We've delayed this until now because it may
11114 be possible to merge the local stack deallocation with the
11115 deallocation forced by ix86_static_chain_on_stack. */
11120 {
11124 }
11125 else
11128 /* Sibcall epilogues don't want a return instruction. */
11130 {
11133 }
11136 {
11139 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11140 address, do explicit add, and jump indirectly to the caller. */
11143 {
11145 rtx insn;
11147 /* There is no "pascal" calling convention in any 64bit ABI. */
11163 }
11164 else
11166 }
11167 else
11170 /* Restore the state back to the state from the prologue,
11171 so that it's correct for the next epilogue. */
11173 }
11175 /* Reset from the function's potential modifications. */
11177 static void
11179 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11180 {
11183 #if TARGET_MACHO
11184 /* Mach-O doesn't support labels at the end of objects, so if
11185 it looks like we might want one, insert a NOP. */
11186 {
11192 {
11193 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11194 notes only, instead set their CODE_LABEL_NUMBER to -1,
11195 otherwise there would be code generation differences
11196 in between -g and -g0. */
11200 }
11210 }
11211 #endif
11213 }
11215 /* Return a scratch register to use in the split stack prologue. The
11216 split stack prologue is used for -fsplit-stack. It is the first
11217 instructions in the function, even before the regular prologue.
11218 The scratch register can be any caller-saved register which is not
11219 used for parameters or for the static chain. */
11221 static unsigned int
11223 {
11226 else
11227 {
11240 {
11242 {
11246 }
11248 }
11250 {
11254 }
11256 {
11259 else
11260 {
11262 {
11266 }
11268 }
11269 }
11270 else
11271 {
11272 /* FIXME: We could make this work by pushing a register
11273 around the addition and comparison. */
11276 }
11277 }
11278 }
11280 /* A SYMBOL_REF for the function which allocates new stackspace for
11281 -fsplit-stack. */
11285 /* A SYMBOL_REF for the more stack function when using the large
11286 model. */
11290 /* Handle -fsplit-stack. These are the first instructions in the
11291 function, even before the regular prologue. */
11293 void
11295 {
11297 HOST_WIDE_INT allocate;
11302 rtx fn;
11310 /* This is the label we will branch to if we have enough stack
11311 space. We expect the basic block reordering pass to reverse this
11312 branch if optimizing, so that we branch in the unlikely case. */
11315 /* We need to compare the stack pointer minus the frame size with
11316 the stack boundary in the TCB. The stack boundary always gives
11317 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11318 can compare directly. Otherwise we need to do an addition. */
11321 UNSPEC_STACK_CHECK);
11326 else
11327 {
11329 rtx offset;
11331 /* We need a scratch register to hold the stack pointer minus
11332 the required frame size. Since this is the very start of the
11333 function, the scratch register can be any caller-saved
11334 register which is not used for parameters. */
11341 {
11342 /* We don't use ix86_gen_add3 in this case because it will
11343 want to split to lea, but when not optimizing the insn
11344 will not be split after this point. */
11347 offset)));
11348 }
11349 else
11350 {
11353 stack_pointer_rtx));
11354 }
11356 }
11362 /* Mark the jump as very likely to be taken. */
11370 /* Get more stack space. We pass in the desired stack space and the
11371 size of the arguments to copy to the new stack. In 32-bit mode
11372 we push the parameters; __morestack will return on a new stack
11373 anyhow. In 64-bit mode we pass the parameters in r10 and
11374 r11. */
11379 {
11385 /* If this function uses a static chain, it will be in %r10.
11386 Preserve it across the call to __morestack. */
11388 {
11389 rtx rax;
11394 }
11397 {
11398 HOST_WIDE_INT argval;
11401 /* When using the large model we need to load the address
11402 into a register, and we've run out of registers. So we
11403 switch to a different calling convention, and we call a
11404 different function: __morestack_large. We pass the
11405 argument size in the upper 32 bits of r10 and pass the
11406 frame size in the lower 32 bits. */
11411 split_stack_fn_large =
11415 {
11425 UNSPEC_GOT);
11431 }
11432 else
11439 }
11440 else
11441 {
11445 }
11448 }
11449 else
11450 {
11453 }
11459 /* In order to make call/return prediction work right, we now need
11460 to execute a return instruction. See
11461 libgcc/config/i386/morestack.S for the details on how this works.
11463 For flow purposes gcc must not see this as a return
11464 instruction--we need control flow to continue at the subsequent
11465 label. Therefore, we use an unspec. */
11469 /* If we are in 64-bit mode and this function uses a static chain,
11470 we saved %r10 in %rax before calling _morestack. */
11475 /* If this function calls va_start, we need to store a pointer to
11476 the arguments on the old stack, because they may not have been
11477 all copied to the new stack. At this point the old stack can be
11478 found at the frame pointer value used by __morestack, because
11479 __morestack has set that up before calling back to us. Here we
11480 store that pointer in a scratch register, and in
11481 ix86_expand_prologue we store the scratch register in a stack
11482 slot. */
11484 {
11486 rtx frame_reg;
11493 /* 64-bit:
11494 fp -> old fp value
11495 return address within this function
11496 return address of caller of this function
11497 stack arguments
11498 So we add three words to get to the stack arguments.
11500 32-bit:
11501 fp -> old fp value
11502 return address within this function
11503 first argument to __morestack
11504 second argument to __morestack
11505 return address of caller of this function
11506 stack arguments
11507 So we add five words to get to the stack arguments.
11508 */
11519 }
11524 /* If this function calls va_start, we now have to set the scratch
11525 register for the case where we do not call __morestack. In this
11526 case we need to set it based on the stack pointer. */
11528 {
11535 }
11536 }
11538 /* We may have to tell the dataflow pass that the split stack prologue
11539 is initializing a scratch register. */
11541 static void
11543 {
11545 {
11548 }
11549 }
11550 \f
11551 /* Determine if op is suitable SUBREG RTX for address. */
11553 static bool
11555 {
11566 /* Don't allow SUBREGs that span more than a word. It can lead to spill
11567 failures when the register is one word out of a two word structure. */
11571 /* Allow only SUBREGs of non-eliminable hard registers. */
11573 }
11575 /* Extract the parts of an RTL expression that is a valid memory address
11576 for an instruction. Return 0 if the structure of the address is
11577 grossly off. Return -1 if the address contains ASHIFT, so it is not
11578 strictly valid, but still used for computing length of lea instruction. */
11580 int
11582 {
11587 rtx tmp;
11591 /* Allow zero-extended SImode addresses,
11592 they will be emitted with addr32 prefix. */
11594 {
11597 {
11601 }
11604 {
11611 }
11612 }
11614 /* Allow SImode subregs of DImode addresses,
11615 they will be emitted with addr32 prefix. */
11617 {
11620 {
11624 }
11625 }
11630 {
11633 else
11635 }
11637 {
11642 do
11643 {
11648 }
11655 {
11658 {
11683 /* FALLTHRU */
11687 && TARGET_TLS_DIRECT_SEG_REFS
11690 else
11697 /* FALLTHRU */
11704 else
11719 }
11720 }
11721 }
11723 {
11726 }
11728 {
11729 /* We're called for lea too, which implements ashift on occasion. */
11739 }
11741 {
11745 /* Constant addresses are sign extended to 64bit, we have to
11746 prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */
11752 }
11753 else
11757 {
11759 ;
11762 ;
11763 else
11765 }
11767 /* Address override works only on the (%reg) part of %fs:(%reg). */
11773 /* Extract the integral value of scale. */
11775 {
11779 }
11784 /* Avoid useless 0 displacement. */
11788 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11793 {
11794 rtx tmp;
11797 }
11799 /* Special case: %ebp cannot be encoded as a base without a displacement.
11800 Similarly %r13. */
11802 && base_reg
11811 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11812 Avoid this by transforming to [%esi+0].
11813 Reload calls address legitimization without cfun defined, so we need
11814 to test cfun for being non-NULL. */
11820 /* Special case: encode reg+reg instead of reg*2. */
11824 /* Special case: scaling cannot be encoded without base or displacement. */
11835 }
11836 \f
11837 /* Return cost of the memory address x.
11838 For i386, it is better to use a complex address than let gcc copy
11839 the address into a reg and make a new pseudo. But not if the address
11840 requires to two regs - that would mean more pseudos with longer
11841 lifetimes. */
11842 static int
11844 addr_space_t as ATTRIBUTE_UNUSED,
11846 {
11858 /* Attempt to minimize number of registers in the address. */
11864 cost++;
11871 cost++;
11873 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
11874 since it's predecode logic can't detect the length of instructions
11875 and it degenerates to vector decoded. Increase cost of such
11876 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
11877 to split such addresses or even refuse such addresses at all.
11879 Following addressing modes are affected:
11880 [base+scale*index]
11881 [scale*index+disp]
11882 [base+index]
11884 The first and last case may be avoidable by explicitly coding the zero in
11885 memory address, but I don't have AMD-K6 machine handy to check this
11886 theory. */
11895 }
11896 \f
11897 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
11898 this is used for to form addresses to local data when -fPIC is in
11899 use. */
11901 static bool
11903 {
11906 }
11908 /* Determine if a given RTX is a valid constant. We already know this
11909 satisfies CONSTANT_P. */
11911 static bool
11913 {
11915 {
11920 {
11924 }
11929 /* Only some unspecs are valid as "constants". */
11932 {
11948 }
11950 /* We must have drilled down to a symbol. */
11955 /* FALLTHRU */
11958 /* TLS symbols are never valid. */
11962 /* DLLIMPORT symbols are never valid. */
11967 #if TARGET_MACHO
11968 /* mdynamic-no-pic */
11971 #endif
11987 }
11989 /* Otherwise we handle everything else in the move patterns. */
11991 }
11993 /* Determine if it's legal to put X into the constant pool. This
11994 is not possible for the address of thread-local symbols, which
11995 is checked above. */
11997 static bool
11999 {
12000 /* We can always put integral constants and vectors in memory. */
12002 {
12010 }
12012 }
12015 /* Nonzero if the constant value X is a legitimate general operand
12016 when generating PIC code. It is given that flag_pic is on and
12017 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12019 bool
12021 {
12022 rtx inner;
12025 {
12032 /* Only some unspecs are valid as "constants". */
12035 {
12048 }
12049 /* FALLTHRU */
12057 }
12058 }
12060 /* Determine if a given CONST RTX is a valid memory displacement
12061 in PIC mode. */
12063 bool
12065 {
12068 /* In 64bit mode we can allow direct addresses of symbols and labels
12069 when they are not dynamic symbols. */
12071 {
12075 {
12099 /* FALLTHRU */
12102 /* TLS references should always be enclosed in UNSPEC. */
12112 }
12113 }
12119 {
12120 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12121 of GOT tables. We should not need these anyway. */
12133 }
12137 {
12142 }
12151 {
12155 /* We need to check for both symbols and labels because VxWorks loads
12156 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12157 details. */
12161 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12162 While ABI specify also 32bit relocation but we don't produce it in
12163 small PIC model at all. */
12185 }
12188 }
12190 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12191 replace the input X, or the original X if no replacement is called for.
12192 The output parameter *WIN is 1 if the calling macro should goto WIN,
12193 0 if it should not. */
12195 bool
12200 {
12201 /* Reload can generate:
12203 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12204 (reg:DI 97))
12205 (reg:DI 2 cx))
12207 This RTX is rejected from ix86_legitimate_address_p due to
12208 non-strictness of base register 97. Following this rejection,
12209 reload pushes all three components into separate registers,
12210 creating invalid memory address RTX.
12212 Following code reloads only the invalid part of the
12213 memory address RTX. */
12219 {
12225 {
12230 }
12234 {
12239 }
12243 }
12246 }
12248 /* Recognizes RTL expressions that are valid memory addresses for an
12249 instruction. The MODE argument is the machine mode for the MEM
12250 expression that wants to use this address.
12252 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12253 convert common non-canonical forms to canonical form so that they will
12254 be recognized. */
12256 static bool
12259 {
12262 HOST_WIDE_INT scale;
12265 /* Decomposition failed. */
12273 /* Validate base register. */
12275 {
12276 rtx reg;
12282 else
12283 /* Base is not a register. */
12291 /* Base is not valid. */
12293 }
12295 /* Validate index register. */
12297 {
12298 rtx reg;
12304 else
12305 /* Index is not a register. */
12313 /* Index is not valid. */
12315 }
12317 /* Index and base should have the same mode. */
12322 /* Validate scale factor. */
12324 {
12326 /* Scale without index. */
12330 /* Scale is not a valid multiplier. */
12332 }
12334 /* Validate displacement. */
12336 {
12341 {
12342 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12343 used. While ABI specify also 32bit relocations, we don't produce
12344 them at all and use IP relative instead. */
12351 /* 64bit address unspec. */
12371 /* Invalid address unspec. */
12373 }
12376 && (flag_pic
12377 || (TARGET_MACHO
12378 #if TARGET_MACHO
12379 && MACHOPIC_INDIRECT
12381 #endif
12382 )))
12383 {
12385 is_legitimate_pic:
12387 {
12388 /* foo@dtpoff(%rX) is ok. */
12395 /* Non-constant pic memory reference. */
12397 }
12400 /* Displacement is an invalid pic construct. */
12402 #if TARGET_MACHO
12405 /* displacment must be referenced via non_lazy_pointer */
12407 #endif
12409 /* This code used to verify that a symbolic pic displacement
12410 includes the pic_offset_table_rtx register.
12412 While this is good idea, unfortunately these constructs may
12413 be created by "adds using lea" optimization for incorrect
12414 code like:
12416 int a;
12417 int foo(int i)
12418 {
12419 return *(&a+i);
12420 }
12422 This code is nonsensical, but results in addressing
12423 GOT table with pic_offset_table_rtx base. We can't
12424 just refuse it easily, since it gets matched by
12425 "addsi3" pattern, that later gets split to lea in the
12426 case output register differs from input. While this
12427 can be handled by separate addsi pattern for this case
12428 that never results in lea, this seems to be easier and
12429 correct fix for crash to disable this test. */
12430 }
12437 /* Displacement is not constant. */
12441 /* Displacement is out of range. */
12443 }
12445 /* Everything looks valid. */
12447 }
12449 /* Determine if a given RTX is a valid constant address. */
12451 bool
12453 {
12455 }
12456 \f
12457 /* Return a unique alias set for the GOT. */
12459 static alias_set_type
12461 {
12466 }
12468 /* Return a legitimate reference for ORIG (an address) using the
12469 register REG. If REG is 0, a new pseudo is generated.
12471 There are two types of references that must be handled:
12473 1. Global data references must load the address from the GOT, via
12474 the PIC reg. An insn is emitted to do this load, and the reg is
12475 returned.
12477 2. Static data references, constant pool addresses, and code labels
12478 compute the address as an offset from the GOT, whose base is in
12479 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12480 differentiate them from global data objects. The returned
12481 address is the PIC reg + an unspec constant.
12483 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12484 reg also appears in the address. */
12486 static rtx
12488 {
12492 #if TARGET_MACHO
12494 {
12497 /* Use the generic Mach-O PIC machinery. */
12499 }
12500 #endif
12507 {
12508 rtx tmpreg;
12509 /* This symbol may be referenced via a displacement from the PIC
12510 base address (@GOTOFF). */
12517 {
12519 UNSPEC_GOTOFF);
12521 }
12522 else
12527 else
12532 {
12536 }
12538 }
12540 {
12541 /* This symbol may be referenced via a displacement from the PIC
12542 base address (@GOTOFF). */
12549 {
12551 UNSPEC_GOTOFF);
12553 }
12554 else
12560 {
12563 }
12564 }
12566 /* We can't use @GOTOFF for text labels on VxWorks;
12567 see gotoff_operand. */
12569 {
12571 {
12577 {
12580 }
12581 }
12583 /* For x64 PE-COFF there is no GOT table. So we use address
12584 directly. */
12586 {
12594 }
12596 {
12604 /* Use directly gen_movsi, otherwise the address is loaded
12605 into register for CSE. We don't want to CSE this addresses,
12606 instead we CSE addresses from the GOT table, so skip this. */
12609 }
12610 else
12611 {
12612 /* This symbol must be referenced via a load from the
12613 Global Offset Table (@GOT). */
12629 }
12630 }
12631 else
12632 {
12635 {
12637 {
12640 }
12641 else
12643 }
12645 {
12648 /* We must match stuff we generate before. Assume the only
12649 unspecs that can get here are ours. Not that we could do
12650 anything with them anyway.... */
12656 }
12658 {
12661 /* Check first to see if this is a constant offset from a @GOTOFF
12662 symbol reference. */
12665 {
12667 {
12671 UNSPEC_GOTOFF);
12677 {
12680 }
12681 }
12682 else
12683 {
12686 {
12690 }
12691 }
12692 }
12693 else
12694 {
12697 new_rtx
12701 {
12704 {
12707 new_rtx
12709 }
12710 else
12712 }
12713 else
12714 {
12717 {
12720 }
12722 }
12723 }
12724 }
12725 }
12727 }
12728 \f
12729 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12731 static rtx
12733 {
12737 {
12742 }
12748 }
12750 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12754 static rtx
12756 {
12758 {
12764 }
12767 }
12769 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
12773 rtx
12775 {
12777 {
12778 ix86_tls_module_base_symbol
12783 }
12786 }
12788 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
12789 false if we expect this to be used for a memory address and true if
12790 we expect to load the address into a register. */
12792 static rtx
12794 {
12801 {
12806 {
12809 else
12810 {
12813 }
12814 }
12817 {
12820 else
12830 }
12831 else
12832 {
12836 {
12838 rtx insns;
12841 emit_call_insn
12851 }
12852 else
12854 }
12861 {
12864 else
12865 {
12868 }
12869 }
12872 {
12877 else
12883 }
12884 else
12885 {
12889 {
12894 emit_call_insn
12899 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
12900 share the LD_BASE result with other LD model accesses. */
12902 UNSPEC_TLS_LD_BASE);
12906 }
12907 else
12909 }
12917 {
12924 }
12929 {
12931 {
12932 /* The Sun linker took the AMD64 TLS spec literally
12933 and can only handle %rax as destination of the
12934 initial executable code sequence. */
12939 }
12941 /* Generate DImode references to avoid %fs:(%reg32)
12942 problems and linker IE->LE relaxation bug. */
12946 }
12948 {
12953 }
12955 {
12959 }
12960 else
12961 {
12964 }
12974 {
12979 }
12980 else
12981 {
12985 }
12995 {
12999 }
13000 else
13001 {
13005 }
13010 }
13013 }
13015 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13016 to symbol DECL. */
13019 htab_t dllimport_map;
13021 static tree
13023 {
13030 tree to;
13031 rtx rtl;
13075 }
13077 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13078 true if we require the result be a register. */
13080 static rtx
13082 {
13083 tree imp_decl;
13084 rtx x;
13093 }
13095 /* Try machine-dependent ways of modifying an illegitimate address
13096 to be legitimate. If we find one, return the new, valid address.
13097 This macro is used in only one place: `memory_address' in explow.c.
13099 OLDX is the address as it was before break_out_memory_refs was called.
13100 In some cases it is useful to look at this to decide what needs to be done.
13102 It is always safe for this macro to do nothing. It exists to recognize
13103 opportunities to optimize the output.
13105 For the 80386, we handle X+REG by loading X into a register R and
13106 using R+REG. R will go in a general reg and indexing will be used.
13107 However, if REG is a broken-out memory address or multiplication,
13108 nothing needs to be done because REG can certainly go in a general reg.
13110 When -fpic is used, special handling is needed for symbolic references.
13111 See comments by legitimize_pic_address in i386.c for details. */
13113 static rtx
13116 {
13127 {
13131 }
13134 {
13141 {
13144 }
13145 }
13150 #if TARGET_MACHO
13153 #endif
13155 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13159 {
13164 }
13167 {
13168 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13173 {
13179 }
13184 {
13190 }
13192 /* Put multiply first if it isn't already. */
13194 {
13199 }
13201 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13202 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13203 created by virtual register instantiation, register elimination, and
13204 similar optimizations. */
13206 {
13212 }
13214 /* Canonicalize
13215 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13216 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13221 {
13222 rtx constant;
13226 {
13229 }
13231 {
13234 }
13235 else
13239 {
13246 }
13247 }
13253 {
13256 }
13259 {
13262 }
13270 {
13273 }
13279 {
13283 {
13286 }
13290 }
13293 {
13297 {
13300 }
13304 }
13305 }
13308 }
13309 \f
13310 /* Print an integer constant expression in assembler syntax. Addition
13311 and subtraction are the only arithmetic that may appear in these
13312 expressions. FILE is the stdio stream to write to, X is the rtx, and
13313 CODE is the operand print code from the output string. */
13315 static void
13317 {
13321 {
13330 else
13331 {
13334 /* Mark the decl as referenced so that cgraph will
13335 output the function. */
13339 #if TARGET_MACHO
13343 #endif
13345 }
13353 /* FALLTHRU */
13364 /* This used to output parentheses around the expression,
13365 but that does not work on the 386 (either ATT or BSD assembler). */
13371 {
13372 /* We can use %d if the number is <32 bits and positive. */
13377 else
13379 }
13380 else
13381 /* We can't handle floating point constants;
13382 TARGET_PRINT_OPERAND must handle them. */
13387 /* Some assemblers need integer constants to appear first. */
13389 {
13393 }
13394 else
13395 {
13400 }
13415 {
13419 }
13424 {
13443 /* FIXME: This might be @TPOFF in Sun ld too. */
13452 else
13462 else
13468 #if TARGET_MACHO
13473 #endif
13477 }
13482 }
13483 }
13485 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13486 We need to emit DTP-relative relocations. */
13488 static void ATTRIBUTE_UNUSED
13490 {
13495 {
13503 }
13504 }
13506 /* Return true if X is a representation of the PIC register. This copes
13507 with calls from ix86_find_base_term, where the register might have
13508 been replaced by a cselib value. */
13510 static bool
13512 {
13516 else
13518 }
13520 /* Helper function for ix86_delegitimize_address.
13521 Attempt to delegitimize TLS local-exec accesses. */
13523 static rtx
13525 {
13550 {
13555 }
13561 }
13563 /* In the name of slightly smaller debug output, and to cater to
13564 general assembler lossage, recognize PIC+GOTOFF and turn it back
13565 into a direct symbol reference.
13567 On Darwin, this is necessary to avoid a crash, because Darwin
13568 has a different PIC label for each routine but the DWARF debugging
13569 information is not associated with any particular routine, so it's
13570 necessary to remove references to the PIC label from RTL stored by
13571 the DWARF output code. */
13573 static rtx
13575 {
13577 /* addend is NULL or some rtx if x is something+GOTOFF where
13578 something doesn't include the PIC register. */
13580 /* reg_addend is NULL or a multiple of some register. */
13582 /* const_addend is NULL or a const_int. */
13584 /* This is the result, or NULL. */
13593 {
13600 {
13606 }
13615 {
13620 }
13622 }
13629 /* %ebx + GOT/GOTOFF */
13630 ;
13632 {
13633 /* %ebx + %reg * scale + GOT/GOTOFF */
13639 else
13640 {
13643 }
13644 }
13645 else
13651 {
13654 }
13673 {
13674 /* If the rest of original X doesn't involve the PIC register, add
13675 addend and subtract pic_offset_table_rtx. This can happen e.g.
13676 for code like:
13677 leal (%ebx, %ecx, 4), %ecx
13678 ...
13679 movl foo@GOTOFF(%ecx), %edx
13680 in which case we return (%ecx - %ebx) + foo. */
13683 pic_offset_table_rtx),
13684 result);
13685 else
13687 }
13689 {
13693 }
13695 }
13697 /* If X is a machine specific address (i.e. a symbol or label being
13698 referenced as a displacement from the GOT implemented using an
13699 UNSPEC), then return the base term. Otherwise return X. */
13701 rtx
13703 {
13704 rtx term;
13707 {
13721 }
13724 }
13725 \f
13726 static void
13729 {
13733 {
13736 }
13741 {
13744 {
13763 }
13767 {
13786 }
13793 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
13794 Those same assemblers have the same but opposite lossage on cmov. */
13799 else
13804 {
13817 }
13825 {
13838 }
13841 /* ??? As above. */
13850 /* ??? As above. */
13855 else
13866 }
13868 }
13870 /* Print the name of register X to FILE based on its machine mode and number.
13871 If CODE is 'w', pretend the mode is HImode.
13872 If CODE is 'b', pretend the mode is QImode.
13873 If CODE is 'k', pretend the mode is SImode.
13874 If CODE is 'q', pretend the mode is DImode.
13875 If CODE is 'x', pretend the mode is V4SFmode.
13876 If CODE is 't', pretend the mode is V8SFmode.
13877 If CODE is 'h', pretend the reg is the 'high' byte register.
13878 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
13879 If CODE is 'd', duplicate the operand for AVX instruction.
13880 */
13882 void
13884 {
13893 {
13897 }
13922 else
13925 /* Irritatingly, AMD extended registers use different naming convention
13926 from the normal registers: "r%d[bwd]" */
13928 {
13933 {
13947 /* no suffix */
13952 }
13954 }
13958 {
13961 {
13964 }
13965 /* FALLTHRU */
13971 /* FALLTHRU */
13974 normal:
13989 {
13994 }
13998 }
14002 {
14005 else
14007 }
14008 }
14010 /* Locate some local-dynamic symbol still in use by this function
14011 so that we can print its name in some tls_local_dynamic_base
14012 pattern. */
14014 static int
14016 {
14021 {
14024 }
14027 }
14031 {
14032 rtx insn;
14043 }
14045 /* Meaning of CODE:
14046 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14047 C -- print opcode suffix for set/cmov insn.
14048 c -- like C, but print reversed condition
14049 F,f -- likewise, but for floating-point.
14050 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14051 otherwise nothing
14052 R -- print the prefix for register names.
14053 z -- print the opcode suffix for the size of the current operand.
14054 Z -- likewise, with special suffixes for x87 instructions.
14055 * -- print a star (in certain assembler syntax)
14056 A -- print an absolute memory reference.
14057 E -- print address with DImode register names if TARGET_64BIT.
14058 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14059 s -- print a shift double count, followed by the assemblers argument
14060 delimiter.
14061 b -- print the QImode name of the register for the indicated operand.
14062 %b0 would print %al if operands[0] is reg 0.
14063 w -- likewise, print the HImode name of the register.
14064 k -- likewise, print the SImode name of the register.
14065 q -- likewise, print the DImode name of the register.
14066 x -- likewise, print the V4SFmode name of the register.
14067 t -- likewise, print the V8SFmode name of the register.
14068 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14069 y -- print "st(0)" instead of "st" as a register.
14070 d -- print duplicated register operand for AVX instruction.
14071 D -- print condition for SSE cmp instruction.
14072 P -- if PIC, print an @PLT suffix.
14073 p -- print raw symbol name.
14074 X -- don't print any sort of PIC '@' suffix for a symbol.
14075 & -- print some in-use local-dynamic symbol name.
14076 H -- print a memory address offset by 8; used for sse high-parts
14077 Y -- print condition for XOP pcom* instruction.
14078 + -- print a branch hint as 'cs' or 'ds' prefix
14079 ; -- print a semicolon (after prefixes due to bug in older gas).
14080 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14081 @ -- print a segment register of thread base pointer load
14082 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14083 */
14085 void
14087 {
14089 {
14091 {
14094 {
14100 /* Intel syntax. For absolute addresses, registers should not
14101 be surrounded by braces. */
14103 {
14108 }
14113 }
14119 /* Wrap address in an UNSPEC to declare special handling. */
14157 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14162 {
14176 output_operand_lossage
14179 }
14182 #endif
14187 {
14188 /* Opcodes don't get size suffixes if using Intel opcodes. */
14193 {
14211 output_operand_lossage
14214 }
14215 }
14218 warning
14220 /* FALLTHRU */
14223 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14228 {
14230 {
14232 #ifdef HAVE_AS_IX86_FILDS
14234 #endif
14242 #ifdef HAVE_AS_IX86_FILDQ
14244 #else
14246 #endif
14251 }
14252 }
14254 {
14255 /* 387 opcodes don't get size suffixes
14256 if the operands are registers. */
14261 {
14277 }
14278 }
14279 else
14280 {
14281 output_operand_lossage
14284 }
14286 output_operand_lossage
14306 {
14309 }
14314 {
14365 }
14369 /* Little bit of braindamage here. The SSE compare instructions
14370 does use completely different names for the comparisons that the
14371 fp conditional moves. */
14373 {
14376 {
14379 }
14385 {
14388 }
14394 {
14397 }
14406 {
14409 }
14415 {
14418 }
14424 {
14427 }
14438 }
14443 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14446 #endif
14451 {
14455 }
14459 file);
14464 {
14468 }
14469 /* It doesn't actually matter what mode we use here, as we're
14470 only going to use this for printing. */
14478 #ifdef HAVE_AS_IX86_HLE
14480 #else
14482 #endif
14484 #ifdef HAVE_AS_IX86_HLE
14486 #else
14488 #endif
14489 /* We do not want to print value of the operand. */
14498 {
14503 else
14506 }
14509 {
14510 rtx x;
14519 {
14524 {
14526 bool cputaken
14529 /* Emit hints only in the case default branch prediction
14530 heuristics would fail. */
14532 {
14533 /* We use 3e (DS) prefix for taken branches and
14534 2e (CS) prefix for not taken branches. */
14537 else
14539 }
14540 }
14541 }
14543 }
14546 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14548 #endif
14555 /* The kernel uses a different segment register for performance
14556 reasons; a system call would not have to trash the userspace
14557 segment register, which would be expensive. */
14560 else
14575 }
14576 }
14582 {
14583 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14586 {
14589 {
14598 else
14604 }
14606 /* Check for explicit size override (codes 'b', 'w', 'k',
14607 'q' and 'x') */
14621 }
14624 /* Avoid (%rip) for call operands. */
14630 else
14632 }
14635 {
14636 REAL_VALUE_TYPE r;
14644 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14648 else
14650 }
14653 {
14654 REAL_VALUE_TYPE r;
14663 }
14665 /* These float cases don't actually occur as immediate operands. */
14667 {
14672 }
14674 else
14675 {
14676 /* We have patterns that allow zero sets of memory, for instance.
14677 In 64-bit mode, we should probably support all 8-byte vectors,
14678 since we can in fact encode that into an immediate. */
14680 {
14683 }
14686 {
14688 {
14691 }
14694 {
14697 else
14699 }
14700 }
14705 else
14707 }
14708 }
14710 static bool
14712 {
14715 }
14716 \f
14717 /* Print a memory operand whose address is ADDR. */
14719 static void
14721 {
14730 {
14737 }
14739 {
14743 }
14744 else
14755 {
14766 }
14768 /* Use one byte shorter RIP relative addressing for 64bit mode. */
14770 {
14782 }
14784 {
14785 /* Displacement only requires special attention. */
14788 {
14792 }
14795 else
14797 }
14798 else
14799 {
14800 /* Print SImode register names to force addr32 prefix. */
14802 {
14803 #ifdef ENABLE_CHECKING
14806 {
14817 }
14818 #endif
14821 }
14823 && TARGET_X32
14824 && disp
14827 {
14828 /* X32 runs in 64-bit mode, where displacement, DISP, in
14829 address DISP(%r64), is encoded as 32-bit immediate sign-
14830 extended from 32-bit to 64-bit. For -0x40000300(%r64),
14831 address is %r64 + 0xffffffffbffffd00. When %r64 <
14832 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
14833 which is invalid for x32. The correct address is %r64
14834 - 0x40000300 == 0xf7ffdd64. To properly encode
14835 -0x40000300(%r64) for x32, we zero-extend negative
14836 displacement by forcing addr32 prefix which truncates
14837 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
14838 zero-extend all negative displacements, including -1(%rsp).
14839 However, for small negative displacements, sign-extension
14840 won't cause overflow. We only zero-extend negative
14841 displacements if they < -16*1024*1024, which is also used
14842 to check legitimate address displacements for PIC. */
14844 }
14847 {
14849 {
14854 else
14856 }
14862 {
14867 }
14869 }
14870 else
14871 {
14875 {
14876 /* Pull out the offset of a symbol; print any symbol itself. */
14880 {
14884 }
14892 else
14894 }
14898 {
14901 {
14905 }
14906 }
14909 else
14913 {
14918 }
14920 }
14921 }
14922 }
14924 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
14926 static bool
14928 {
14929 rtx op;
14936 {
14939 /* FIXME: This might be @TPOFF in Sun ld. */
14950 else
14962 else
14969 #if TARGET_MACHO
14975 #endif
14978 {
14983 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
14985 #else
14987 #endif
14990 }
14995 }
14998 }
14999 \f
15000 /* Split one or more double-mode RTL references into pairs of half-mode
15001 references. The RTL can be REG, offsettable MEM, integer constant, or
15002 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
15003 split and "num" is its length. lo_half and hi_half are output arrays
15004 that parallel "operands". */
15006 void
15009 {
15014 {
15023 }
15028 {
15031 /* simplify_subreg refuse to split volatile memory addresses,
15032 but we still have to handle it. */
15034 {
15037 }
15038 else
15039 {
15046 }
15047 }
15048 }
15049 \f
15050 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15051 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15052 is the expression of the binary operation. The output may either be
15053 emitted here, or returned to the caller, like all output_* functions.
15055 There is no guarantee that the operands are the same mode, as they
15056 might be within FLOAT or FLOAT_EXTEND expressions. */
15058 #ifndef SYSV386_COMPAT
15059 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15060 wants to fix the assemblers because that causes incompatibility
15061 with gcc. No-one wants to fix gcc because that causes
15062 incompatibility with assemblers... You can use the option of
15063 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15064 #define SYSV386_COMPAT 1
15065 #endif
15069 {
15075 #ifdef ENABLE_CHECKING
15076 /* Even if we do not want to check the inputs, this documents input
15077 constraints. Which helps in understanding the following code. */
15087 else
15089 #endif
15092 {
15097 else
15106 else
15115 else
15124 else
15131 }
15134 {
15136 {
15140 else
15142 }
15143 else
15144 {
15148 else
15150 }
15152 }
15156 {
15160 {
15164 }
15166 /* know operands[0] == operands[1]. */
15169 {
15172 }
15175 {
15177 /* How is it that we are storing to a dead operand[2]?
15178 Well, presumably operands[1] is dead too. We can't
15179 store the result to st(0) as st(0) gets popped on this
15180 instruction. Instead store to operands[2] (which I
15181 think has to be st(1)). st(1) will be popped later.
15182 gcc <= 2.8.1 didn't have this check and generated
15183 assembly code that the Unixware assembler rejected. */
15185 else
15188 }
15192 else
15199 {
15202 }
15205 {
15208 }
15211 {
15212 #if SYSV386_COMPAT
15213 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15214 derived assemblers, confusingly reverse the direction of
15215 the operation for fsub{r} and fdiv{r} when the
15216 destination register is not st(0). The Intel assembler
15217 doesn't have this brain damage. Read !SYSV386_COMPAT to
15218 figure out what the hardware really does. */
15221 else
15223 #else
15225 /* As above for fmul/fadd, we can't store to st(0). */
15227 else
15229 #endif
15231 }
15234 {
15235 #if SYSV386_COMPAT
15238 else
15240 #else
15243 else
15245 #endif
15247 }
15250 {
15253 else
15256 }
15258 {
15259 #if SYSV386_COMPAT
15261 #else
15263 #endif
15264 }
15265 else
15266 {
15267 #if SYSV386_COMPAT
15269 #else
15271 #endif
15272 }
15277 }
15281 }
15283 /* Check if a 256bit AVX register is referenced inside of EXP. */
15285 static int
15287 {
15298 }
15300 /* Return needed mode for entity in optimize_mode_switching pass. */
15302 static int
15304 {
15306 {
15307 rtx link;
15309 /* Needed mode is set to AVX_U128_CLEAN if there are
15310 no 256bit modes used in function arguments. */
15312 link;
15314 {
15316 {
15321 }
15322 }
15325 }
15327 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
15328 changes state only when a 256bit register is written to, but we need
15329 to prevent the compiler from moving optimal insertion point above
15330 eventual read from 256bit register. */
15335 }
15337 /* Return mode that i387 must be switched into
15338 prior to the execution of insn. */
15340 static int
15342 {
15345 /* The mode UNINITIALIZED is used to store control word after a
15346 function call or ASM pattern. The mode ANY specify that function
15347 has no requirements on the control word and make no changes in the
15348 bits we are interested in. */
15362 {
15385 }
15388 }
15390 /* Return mode that entity must be switched into
15391 prior to the execution of insn. */
15393 int
15395 {
15397 {
15407 }
15409 }
15411 /* Check if a 256bit AVX register is referenced in stores. */
15413 static void
15415 {
15417 {
15420 }
15421 }
15423 /* Calculate mode of upper 128bit AVX registers after the insn. */
15425 static int
15427 {
15434 /* We know that state is clean after CALL insn if there are no
15435 256bit registers used in the function return register. */
15437 {
15442 }
15444 /* Otherwise, return current mode. Remember that if insn
15445 references AVX 256bit registers, the mode was already changed
15446 to DIRTY from MODE_NEEDED. */
15448 }
15450 /* Return the mode that an insn results in. */
15452 int
15454 {
15456 {
15466 }
15467 }
15469 static int
15471 {
15472 tree arg;
15474 /* Entry mode is set to AVX_U128_DIRTY if there are
15475 256bit modes used in function arguments. */
15478 {
15483 }
15486 }
15488 /* Return a mode that ENTITY is assumed to be
15489 switched to at function entry. */
15491 int
15493 {
15495 {
15505 }
15506 }
15508 static int
15510 {
15513 /* Exit mode is set to AVX_U128_DIRTY if there are
15514 256bit modes used in the function return register. */
15519 }
15521 /* Return a mode that ENTITY is assumed to be
15522 switched to at function exit. */
15524 int
15526 {
15528 {
15538 }
15539 }
15541 /* Output code to initialize control word copies used by trunc?f?i and
15542 rounding patterns. CURRENT_MODE is set to current control word,
15543 while NEW_MODE is set to new control word. */
15545 static void
15547 {
15549 rtx new_mode;
15560 {
15562 {
15564 /* round toward zero (truncate) */
15570 /* round down toward -oo */
15577 /* round up toward +oo */
15584 /* mask precision exception for nearbyint() */
15591 }
15592 }
15593 else
15594 {
15596 {
15598 /* round toward zero (truncate) */
15604 /* round down toward -oo */
15610 /* round up toward +oo */
15616 /* mask precision exception for nearbyint() */
15623 }
15624 }
15630 }
15632 /* Emit vzeroupper. */
15634 void
15636 {
15639 /* Cancel automatic vzeroupper insertion if there are
15640 live call-saved SSE registers at the insertion point. */
15652 }
15654 /* Generate one or more insns to set ENTITY to MODE. */
15656 void
15658 {
15660 {
15675 }
15676 }
15678 /* Output code for INSN to convert a float to a signed int. OPERANDS
15679 are the insn operands. The output may be [HSD]Imode and the input
15680 operand may be [SDX]Fmode. */
15684 {
15689 /* Jump through a hoop or two for DImode, since the hardware has no
15690 non-popping instruction. We used to do this a different way, but
15691 that was somewhat fragile and broke with post-reload splitters. */
15701 else
15702 {
15707 else
15711 }
15714 }
15716 /* Output code for x87 ffreep insn. The OPNO argument, which may only
15717 have the values zero or one, indicates the ffreep insn's operand
15718 from the OPERANDS array. */
15722 {
15724 #ifdef HAVE_AS_IX86_FFREEP
15726 #else
15727 {
15737 }
15738 #endif
15741 }
15744 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
15745 should be used. UNORDERED_P is true when fucom should be used. */
15749 {
15755 {
15758 }
15759 else
15760 {
15763 }
15766 {
15770 else
15772 else
15775 else
15777 }
15784 {
15786 {
15789 }
15790 else
15792 }
15795 && stack_top_dies
15798 {
15799 /* If both the top of the 387 stack dies, and the other operand
15800 is also a stack register that dies, then this must be a
15801 `fcompp' float compare */
15804 {
15805 /* There is no double popping fcomi variant. Fortunately,
15806 eflags is immune from the fstp's cc clobbering. */
15809 else
15812 }
15813 else
15814 {
15817 else
15819 }
15820 }
15821 else
15822 {
15823 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
15826 {
15834 NULL,
15835 NULL,
15842 NULL,
15843 NULL,
15844 NULL,
15845 NULL
15846 };
15861 }
15862 }
15864 void
15866 {
15869 #ifdef ASM_QUAD
15872 #else
15874 #endif
15877 }
15879 void
15881 {
15884 #ifdef ASM_QUAD
15887 #else
15889 #endif
15890 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
15896 #if TARGET_MACHO
15898 {
15902 }
15903 #endif
15904 else
15907 }
15908 \f
15909 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
15910 for the target. */
15912 void
15914 {
15915 rtx tmp;
15917 /* We play register width games, which are only valid after reload. */
15920 /* Avoid HImode and its attendant prefix byte. */
15925 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
15927 {
15930 }
15933 }
15935 /* X is an unchanging MEM. If it is a constant pool reference, return
15936 the constant pool rtx, else NULL. */
15938 rtx
15940 {
15947 }
15949 void
15951 {
15959 {
15962 {
15968 }
15972 }
15976 {
15989 {
15996 }
15997 }
16001 {
16003 {
16004 #if TARGET_MACHO
16005 /* dynamic-no-pic */
16007 {
16008 rtx temp = ((reload_in_progress
16016 }
16018 {
16022 }
16025 else
16026 {
16034 }
16035 /* dynamic-no-pic */
16036 #endif
16037 }
16038 else
16039 {
16043 {
16049 }
16050 }
16051 }
16052 else
16053 {
16064 /* Force large constants in 64bit compilation into register
16065 to get them CSEed. */
16077 {
16078 /* If we are loading a floating point constant to a register,
16079 force the value to memory now, since we'll get better code
16080 out the back end. */
16084 {
16089 }
16090 }
16091 }
16094 }
16096 void
16098 {
16102 /* Force constants other than zero into memory. We do not know how
16103 the instructions used to build constants modify the upper 64 bits
16104 of the register, once we have that information we may be able
16105 to handle some of them more efficiently. */
16114 /* We need to check memory alignment for SSE mode since attribute
16115 can make operands unaligned. */
16120 {
16123 /* ix86_expand_vector_move_misalign() does not like constants ... */
16129 /* ... nor both arguments in memory. */
16137 }
16139 /* Make operand1 a register if it isn't already. */
16143 {
16146 }
16149 }
16151 /* Split 32-byte AVX unaligned load and store if needed. */
16153 static void
16155 {
16156 rtx m;
16163 {
16184 }
16187 {
16189 {
16196 }
16197 else
16199 }
16201 {
16203 {
16208 }
16209 else
16211 }
16212 else
16214 }
16216 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16217 straight to ix86_expand_vector_move. */
16218 /* Code generation for scalar reg-reg moves of single and double precision data:
16219 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16220 movaps reg, reg
16221 else
16222 movss reg, reg
16223 if (x86_sse_partial_reg_dependency == true)
16224 movapd reg, reg
16225 else
16226 movsd reg, reg
16228 Code generation for scalar loads of double precision data:
16229 if (x86_sse_split_regs == true)
16230 movlpd mem, reg (gas syntax)
16231 else
16232 movsd mem, reg
16234 Code generation for unaligned packed loads of single precision data
16235 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
16236 if (x86_sse_unaligned_move_optimal)
16237 movups mem, reg
16239 if (x86_sse_partial_reg_dependency == true)
16240 {
16241 xorps reg, reg
16242 movlps mem, reg
16243 movhps mem+8, reg
16244 }
16245 else
16246 {
16247 movlps mem, reg
16248 movhps mem+8, reg
16249 }
16251 Code generation for unaligned packed loads of double precision data
16252 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
16253 if (x86_sse_unaligned_move_optimal)
16254 movupd mem, reg
16256 if (x86_sse_split_regs == true)
16257 {
16258 movlpd mem, reg
16259 movhpd mem+8, reg
16260 }
16261 else
16262 {
16263 movsd mem, reg
16264 movhpd mem+8, reg
16265 }
16266 */
16268 void
16270 {
16278 {
16280 {
16285 /* FALLTHRU */
16293 }
16296 }
16299 {
16300 /* ??? If we have typed data, then it would appear that using
16301 movdqu is the only way to get unaligned data loaded with
16302 integer type. */
16304 {
16307 /* We will eventually emit movups based on insn attributes. */
16309 }
16311 {
16312 rtx zero;
16315 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16316 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16318 {
16319 /* We will eventually emit movups based on insn attributes. */
16322 }
16324 /* When SSE registers are split into halves, we can avoid
16325 writing to the top half twice. */
16327 {
16330 }
16331 else
16332 {
16333 /* ??? Not sure about the best option for the Intel chips.
16334 The following would seem to satisfy; the register is
16335 entirely cleared, breaking the dependency chain. We
16336 then store to the upper half, with a dependency depth
16337 of one. A rumor has it that Intel recommends two movsd
16338 followed by an unpacklpd, but this is unconfirmed. And
16339 given that the dependency depth of the unpacklpd would
16340 still be one, I'm not sure why this would be better. */
16342 }
16348 }
16349 else
16350 {
16352 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16353 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16355 {
16360 }
16364 else
16374 }
16375 }
16377 {
16379 {
16382 /* We will eventually emit movups based on insn attributes. */
16384 }
16386 {
16388 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16389 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16391 /* We will eventually emit movups based on insn attributes. */
16393 else
16394 {
16399 }
16400 }
16401 else
16402 {
16407 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16408 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16410 {
16413 }
16414 else
16415 {
16420 }
16421 }
16422 }
16423 else
16425 }
16427 /* Expand a push in MODE. This is some mode for which we do not support
16428 proper push instructions, at least from the registers that we expect
16429 the value to live in. */
16431 void
16433 {
16434 rtx tmp;
16444 /* When we push an operand onto stack, it has to be aligned at least
16445 at the function argument boundary. However since we don't have
16446 the argument type, we can't determine the actual argument
16447 boundary. */
16449 }
16451 /* Helper function of ix86_fixup_binary_operands to canonicalize
16452 operand order. Returns true if the operands should be swapped. */
16454 static bool
16456 rtx operands[])
16457 {
16462 /* If the operation is not commutative, we can't do anything. */
16466 /* Highest priority is that src1 should match dst. */
16472 /* Next highest priority is that immediate constants come second. */
16478 /* Lowest priority is that memory references should come second. */
16485 }
16488 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
16489 destination to use for the operation. If different from the true
16490 destination in operands[0], a copy operation will be required. */
16492 rtx
16494 rtx operands[])
16495 {
16500 /* Canonicalize operand order. */
16502 {
16503 rtx temp;
16505 /* It is invalid to swap operands of different modes. */
16511 }
16513 /* Both source operands cannot be in memory. */
16515 {
16516 /* Optimization: Only read from memory once. */
16518 {
16521 }
16522 else
16524 }
16526 /* If the destination is memory, and we do not have matching source
16527 operands, do things in registers. */
16531 /* Source 1 cannot be a constant. */
16535 /* Source 1 cannot be a non-matching memory. */
16539 /* Improve address combine. */
16548 }
16550 /* Similarly, but assume that the destination has already been
16551 set up properly. */
16553 void
16556 {
16559 }
16561 /* Attempt to expand a binary operator. Make the expansion closer to the
16562 actual machine, then just general_operand, which will allow 3 separate
16563 memory references (one output, two input) in a single insn. */
16565 void
16567 rtx operands[])
16568 {
16575 /* Emit the instruction. */
16579 {
16580 /* Reload doesn't know about the flags register, and doesn't know that
16581 it doesn't want to clobber it. We can only do this with PLUS. */
16584 }
16588 {
16589 /* This is going to be an LEA; avoid splitting it later. */
16591 }
16592 else
16593 {
16596 }
16598 /* Fix up the destination if needed. */
16601 }
16603 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
16604 the given OPERANDS. */
16606 void
16608 rtx operands[])
16609 {
16612 {
16615 }
16617 {
16620 }
16621 /* Optimize (__m128i) d | (__m128i) e and similar code
16622 when d and e are float vectors into float vector logical
16623 insn. In C/C++ without using intrinsics there is no other way
16624 to express vector logical operation on float vectors than
16625 to cast them temporarily to integer vectors. */
16627 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16636 {
16637 rtx dst;
16639 {
16646 {
16649 }
16650 else
16651 {
16656 }
16667 }
16668 }
16677 }
16679 /* Return TRUE or FALSE depending on whether the binary operator meets the
16680 appropriate constraints. */
16682 bool
16685 {
16690 /* Both source operands cannot be in memory. */
16694 /* Canonicalize operand order for commutative operators. */
16696 {
16700 }
16702 /* If the destination is memory, we must have a matching source operand. */
16706 /* Source 1 cannot be a constant. */
16710 /* Source 1 cannot be a non-matching memory. */
16712 /* Support "andhi/andsi/anddi" as a zero-extending move. */
16720 }
16722 /* Attempt to expand a unary operator. Make the expansion closer to the
16723 actual machine, then just general_operand, which will allow 2 separate
16724 memory references (one output, one input) in a single insn. */
16726 void
16728 rtx operands[])
16729 {
16736 /* If the destination is memory, and we do not have matching source
16737 operands, do things in registers. */
16740 {
16743 else
16745 }
16747 /* When source operand is memory, destination must match. */
16751 /* Emit the instruction. */
16755 {
16756 /* Reload doesn't know about the flags register, and doesn't know that
16757 it doesn't want to clobber it. */
16760 }
16761 else
16762 {
16765 }
16767 /* Fix up the destination if needed. */
16770 }
16772 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
16773 divisor are within the range [0-255]. */
16775 void
16778 {
16787 {
16800 }
16807 /* Use 8bit unsigned divimod if dividend and divisor are within
16808 the range [0-255]. */
16817 pc_rtx);
16822 /* Generate original signed/unsigned divimod. */
16827 /* Branch to the end. */
16831 /* Generate 8bit unsigned divide. */
16833 /* Don't use operands[0] for result of 8bit divide since not all
16834 registers support QImode ZERO_EXTRACT. */
16841 {
16844 }
16845 else
16846 {
16849 }
16851 /* Extract remainder from AH. */
16855 else
16856 {
16857 /* Need a new scratch register since the old one has result
16858 of 8bit divide. */
16862 }
16865 /* Zero extend quotient from AL. */
16871 }
16873 #define LEA_MAX_STALL (3)
16874 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
16876 /* Increase given DISTANCE in half-cycles according to
16877 dependencies between PREV and NEXT instructions.
16878 Add 1 half-cycle if there is no dependency and
16879 go to next cycle if there is some dependecy. */
16881 static unsigned int
16883 {
16900 }
16902 /* Function checks if instruction INSN defines register number
16903 REGNO1 or REGNO2. */
16905 static bool
16907 rtx insn)
16908 {
16916 {
16918 }
16921 }
16923 /* Function checks if instruction INSN uses register number
16924 REGNO as a part of address expression. */
16926 static bool
16928 {
16936 }
16938 /* Search backward for non-agu definition of register number REGNO1
16939 or register number REGNO2 in basic block starting from instruction
16940 START up to head of basic block or instruction INSN.
16942 Function puts true value into *FOUND var if definition was found
16943 and false otherwise.
16945 Distance in half-cycles between START and found instruction or head
16946 of BB is added to DISTANCE and returned. */
16948 static int
16952 {
16962 {
16964 {
16967 {
16970 {
16973 }
16974 }
16977 }
16982 }
16985 }
16987 /* Search backward for non-agu definition of register number REGNO1
16988 or register number REGNO2 in INSN's basic block until
16989 1. Pass LEA_SEARCH_THRESHOLD instructions, or
16990 2. Reach neighbour BBs boundary, or
16991 3. Reach agu definition.
16992 Returns the distance between the non-agu definition point and INSN.
16993 If no definition point, returns -1. */
16995 static int
16997 rtx insn)
16998 {
17009 {
17010 edge e;
17011 edge_iterator ei;
17016 {
17019 }
17025 else
17026 {
17031 {
17032 int bb_dist
17038 {
17045 }
17046 }
17049 }
17050 }
17052 /* get_attr_type may modify recog data. We want to make sure
17053 that recog data is valid for instruction INSN, on which
17054 distance_non_agu_define is called. INSN is unchanged here. */
17061 }
17063 /* Return the distance in half-cycles between INSN and the next
17064 insn that uses register number REGNO in memory address added
17065 to DISTANCE. Return -1 if REGNO0 is set.
17067 Put true value into *FOUND if register usage was found and
17068 false otherwise.
17069 Put true value into *REDEFINED if register redefinition was
17070 found and false otherwise. */
17072 static int
17076 {
17087 {
17089 {
17092 {
17093 /* Return DISTANCE if OP0 is used in memory
17094 address in NEXT. */
17097 }
17100 {
17101 /* Return -1 if OP0 is set in NEXT. */
17104 }
17107 }
17113 }
17116 }
17118 /* Return the distance between INSN and the next insn that uses
17119 register number REGNO0 in memory address. Return -1 if no such
17120 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17122 static int
17124 {
17136 {
17137 edge e;
17138 edge_iterator ei;
17143 {
17146 }
17152 else
17153 {
17159 {
17160 int bb_dist
17165 {
17172 }
17173 }
17176 }
17177 }
17183 }
17185 /* Define this macro to tune LEA priority vs ADD, it take effect when
17186 there is a dilemma of choicing LEA or ADD
17187 Negative value: ADD is more preferred than LEA
17188 Zero: Netrual
17189 Positive value: LEA is more preferred than ADD*/
17190 #define IX86_LEA_PRIORITY 0
17192 /* Return true if usage of lea INSN has performance advantage
17193 over a sequence of instructions. Instructions sequence has
17194 SPLIT_COST cycles higher latency than lea latency. */
17196 static bool
17199 {
17206 {
17207 /* If there is no non AGU operand definition, no AGU
17208 operand usage and split cost is 0 then both lea
17209 and non lea variants have same priority. Currently
17210 we prefer lea for 64 bit code and non lea on 32 bit
17211 code. */
17214 else
17216 }
17218 /* With longer definitions distance lea is more preferable.
17219 Here we change it to take into account splitting cost and
17220 lea priority. */
17223 /* If there is no use in memory addess then we just check
17224 that split cost exceeds AGU stall. */
17228 /* If this insn has both backward non-agu dependence and forward
17229 agu dependence, the one with short distance takes effect. */
17231 }
17233 /* Return true if it is legal to clobber flags by INSN and
17234 false otherwise. */
17236 static bool
17238 {
17241 bitmap live;
17244 {
17246 {
17253 }
17259 }
17263 }
17265 /* Return true if we need to split op0 = op1 + op2 into a sequence of
17266 move and add to avoid AGU stalls. */
17268 bool
17270 {
17273 /* Check if we need to optimize. */
17277 /* Check it is correct to split here. */
17285 /* We need to split only adds with non destructive
17286 destination operand. */
17289 else
17291 }
17293 /* Return true if we should emit lea instruction instead of mov
17294 instruction. */
17296 bool
17298 {
17301 /* Check if we need to optimize. */
17305 /* Use lea for reg to reg moves only. */
17313 }
17315 /* Return true if we need to split lea into a sequence of
17316 instructions to avoid AGU stalls. */
17318 bool
17320 {
17326 /* Check we need to optimize. */
17330 /* Check it is correct to split here. */
17337 /* There should be at least two components in the address. */
17342 /* We should not split into add if non legitimate pic
17343 operand is used as displacement. */
17358 /* Compute how many cycles we will add to execution time
17359 if split lea into a sequence of instructions. */
17361 {
17362 /* Have to use mov instruction if non desctructive
17363 destination form is used. */
17367 /* Have to add index to base if both exist. */
17371 /* Have to use shift and adds if scale is 2 or greater. */
17373 {
17378 else
17380 }
17382 /* Have to use add instruction with immediate if
17383 disp is non zero. */
17387 /* Subtract the price of lea. */
17389 }
17392 }
17394 /* Emit x86 binary operand CODE in mode MODE, where the first operand
17395 matches destination. RTX includes clobber of FLAGS_REG. */
17397 static void
17400 {
17407 }
17409 /* Return true if regno1 def is nearest to the insn. */
17411 static bool
17413 {
17420 {
17422 {
17425 }
17431 }
17433 /* None of the regs is defined in the bb. */
17435 }
17437 /* Split lea instructions into a sequence of instructions
17438 which are executed on ALU to avoid AGU stalls.
17439 It is assumed that it is allowed to clobber flags register
17440 at lea position. */
17442 void
17444 {
17460 {
17463 }
17466 {
17469 }
17475 {
17476 /* Case r1 = r1 + ... */
17478 {
17479 /* If we have a case r1 = r1 + C * r1 then we
17480 should use multiplication which is very
17481 expensive. Assume cost model is wrong if we
17482 have such case here. */
17487 }
17488 else
17489 {
17490 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
17494 /* Use shift for scaling. */
17503 }
17504 }
17506 {
17509 }
17510 else
17511 {
17513 {
17516 }
17518 {
17521 }
17522 else
17523 {
17528 else
17529 {
17530 rtx tmp1;
17532 /* Find better operand for SET instruction, depending
17533 on which definition is farther from the insn. */
17536 else
17546 }
17549 }
17553 }
17554 }
17556 /* Return true if it is ok to optimize an ADD operation to LEA
17557 operation to avoid flag register consumation. For most processors,
17558 ADD is faster than LEA. For the processors like ATOM, if the
17559 destination register of LEA holds an actual address which will be
17560 used soon, LEA is better and otherwise ADD is better. */
17562 bool
17564 {
17569 /* If a = b + c, (a!=b && a!=c), must use lea form. */
17577 }
17579 /* Return true if destination reg of SET_BODY is shift count of
17580 USE_BODY. */
17582 static bool
17584 {
17585 rtx set_dest;
17586 rtx shift_rtx;
17589 /* Retrieve destination of SET_BODY. */
17591 {
17600 use_body))
17605 }
17607 /* Retrieve shift count of USE_BODY. */
17609 {
17621 }
17629 {
17632 /* Return true if shift count is dest of SET_BODY. */
17634 {
17635 /* Add check since it can be invoked before register
17636 allocation in pre-reload schedule. */
17642 }
17643 }
17646 }
17648 /* Return true if destination reg of SET_INSN is shift count of
17649 USE_INSN. */
17651 bool
17653 {
17656 }
17658 /* Return TRUE or FALSE depending on whether the unary operator meets the
17659 appropriate constraints. */
17661 bool
17665 {
17666 /* If one of operands is memory, source and destination must match. */
17672 }
17674 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
17675 are ok, keeping in mind the possible movddup alternative. */
17677 bool
17679 {
17685 }
17687 /* Post-reload splitter for converting an SF or DFmode value in an
17688 SSE register into an unsigned SImode. */
17690 void
17692 {
17703 /* Load up the value into the low element. We must ensure that the other
17704 elements are valid floats -- zero is the easiest such value. */
17706 {
17709 else
17711 }
17712 else
17713 {
17718 else
17720 }
17740 else
17745 }
17747 /* Convert an unsigned DImode value into a DFmode, using only SSE.
17748 Expects the 64-bit DImode to be supplied in a pair of integral
17749 registers. Requires SSE2; will use SSE3 if available. For x86_32,
17750 -mfpmath=sse, !optimize_size only. */
17752 void
17754 {
17758 rtx x;
17764 {
17767 }
17768 else
17769 {
17773 }
17781 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
17784 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
17785 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
17786 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
17787 (0x1.0p84 + double(fp_value_hi_xmm)).
17788 Note these exponents differ by 32. */
17792 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
17793 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
17802 /* Add the upper and lower DFmode values together. */
17805 else
17806 {
17810 }
17813 }
17815 /* Not used, but eases macroization of patterns. */
17816 void
17818 rtx input ATTRIBUTE_UNUSED)
17819 {
17821 }
17823 /* Convert an unsigned SImode value into a DFmode. Only currently used
17824 for SSE, but applicable anywhere. */
17826 void
17828 {
17829 REAL_VALUE_TYPE TWO31r;
17844 }
17846 /* Convert a signed DImode value into a DFmode. Only used for SSE in
17847 32-bit mode; otherwise we have a direct convert instruction. */
17849 void
17851 {
17852 REAL_VALUE_TYPE TWO32r;
17870 }
17872 /* Convert an unsigned SImode value into a SFmode, using only SSE.
17873 For x86_32, -mfpmath=sse, !optimize_size only. */
17874 void
17876 {
17877 REAL_VALUE_TYPE ONE16r;
17896 }
17898 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
17899 a vector of unsigned ints VAL to vector of floats TARGET. */
17901 void
17903 {
17905 REAL_VALUE_TYPE TWO16r;
17912 else
17917 OPTAB_DIRECT);
17928 OPTAB_DIRECT);
17930 OPTAB_DIRECT);
17933 }
17935 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
17936 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
17937 This is done by doing just signed conversion if < 0x1p31, and otherwise by
17938 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
17940 rtx
17942 {
17943 REAL_VALUE_TYPE TWO31r;
17958 {
17964 }
17973 OPTAB_DIRECT);
17974 else
17975 {
17981 OPTAB_DIRECT);
17982 }
17985 }
17987 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
17988 then replicate the value for all elements of the vector
17989 register. */
17991 rtx
17993 {
17995 rtvec v;
17999 {
18026 }
18027 }
18029 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18030 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18031 for an SSE register. If VECT is true, then replicate the mask for
18032 all elements of the vector register. If INVERT is true, then create
18033 a mask excluding the sign bit. */
18035 rtx
18037 {
18041 rtx v;
18042 rtx mask;
18044 /* Find the sign bit, sign extended to 2*HWI. */
18046 {
18066 else
18074 {
18077 }
18078 else
18079 {
18080 rtvec vec;
18086 {
18089 }
18090 else
18100 }
18105 }
18110 /* Force this value into the low part of a fp vector constant. */
18119 }
18121 /* Generate code for floating point ABS or NEG. */
18123 void
18125 rtx operands[])
18126 {
18137 {
18143 }
18145 /* NEG and ABS performed with SSE use bitwise mask operations.
18146 Create the appropriate mask now. */
18149 else
18159 {
18161 rtvec par;
18166 else
18167 {
18170 }
18172 }
18173 else
18175 }
18177 /* Expand a copysign operation. Special case operand 0 being a constant. */
18179 void
18181 {
18195 else
18199 {
18206 {
18209 else
18210 {
18214 }
18215 }
18225 else
18229 }
18230 else
18231 {
18241 else
18245 }
18246 }
18248 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
18249 be a constant, and so has already been expanded into a vector constant. */
18251 void
18253 {
18269 {
18272 }
18273 }
18275 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
18276 so we have to do two masks. */
18278 void
18280 {
18295 {
18296 /* Shouldn't happen often (it's useless, obviously), but when it does
18297 we'd generate incorrect code if we continue below. */
18300 }
18303 {
18314 }
18315 else
18316 {
18318 {
18320 }
18322 {
18326 }
18330 {
18333 }
18335 {
18340 }
18342 }
18346 }
18348 /* Return TRUE or FALSE depending on whether the first SET in INSN
18349 has source and destination with matching CC modes, and that the
18350 CC mode is at least as constrained as REQ_MODE. */
18352 bool
18354 {
18355 rtx set;
18366 {
18376 /* FALLTHRU */
18380 /* FALLTHRU */
18384 /* FALLTHRU */
18398 }
18401 }
18403 /* Generate insn patterns to do an integer compare of OPERANDS. */
18405 static rtx
18407 {
18414 /* This is very simple, but making the interface the same as in the
18415 FP case makes the rest of the code easier. */
18419 /* Return the test that should be put into the flags user, i.e.
18420 the bcc, scc, or cmov instruction. */
18422 }
18424 /* Figure out whether to use ordered or unordered fp comparisons.
18425 Return the appropriate mode to use. */
18427 enum machine_mode
18429 {
18430 /* ??? In order to make all comparisons reversible, we do all comparisons
18431 non-trapping when compiling for IEEE. Once gcc is able to distinguish
18432 all forms trapping and nontrapping comparisons, we can make inequality
18433 comparisons trapping again, since it results in better code when using
18434 FCOM based compares. */
18436 }
18438 enum machine_mode
18440 {
18444 {
18447 }
18450 {
18451 /* Only zero flag is needed. */
18455 /* Codes needing carry flag. */
18458 /* Detect overflow checks. They need just the carry flag. */
18462 else
18466 /* Detect overflow checks. They need just the carry flag. */
18470 else
18472 /* Codes possibly doable only with sign flag when
18473 comparing against zero. */
18478 else
18479 /* For other cases Carry flag is not required. */
18481 /* Codes doable only with sign flag when comparing
18482 against zero, but we miss jump instruction for it
18483 so we need to use relational tests against overflow
18484 that thus needs to be zero. */
18489 else
18491 /* strcmp pattern do (use flags) and combine may ask us for proper
18492 mode. */
18497 }
18498 }
18500 /* Return the fixed registers used for condition codes. */
18502 static bool
18504 {
18508 }
18510 /* If two condition code modes are compatible, return a condition code
18511 mode which is compatible with both. Otherwise, return
18512 VOIDmode. */
18514 static enum machine_mode
18516 {
18533 {
18547 {
18561 }
18565 /* These are only compatible with themselves, which we already
18566 checked above. */
18568 }
18569 }
18572 /* Return a comparison we can do and that it is equivalent to
18573 swap_condition (code) apart possibly from orderedness.
18574 But, never change orderedness if TARGET_IEEE_FP, returning
18575 UNKNOWN in that case if necessary. */
18577 static enum rtx_code
18579 {
18581 {
18592 }
18593 }
18595 /* Return cost of comparison CODE using the best strategy for performance.
18596 All following functions do use number of instructions as a cost metrics.
18597 In future this should be tweaked to compute bytes for optimize_size and
18598 take into account performance of various instructions on various CPUs. */
18600 static int
18602 {
18605 /* The cost of code using bit-twiddling on %ah. */
18607 {
18630 }
18633 {
18640 }
18641 }
18643 /* Return strategy to use for floating-point. We assume that fcomi is always
18644 preferrable where available, since that is also true when looking at size
18645 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
18647 enum ix86_fpcmp_strategy
18649 {
18650 /* Do fcomi/sahf based test when profitable. */
18659 }
18661 /* Swap, force into registers, or otherwise massage the two operands
18662 to a fp comparison. The operands are updated in place; the new
18663 comparison code is returned. */
18665 static enum rtx_code
18667 {
18673 /* All of the unordered compare instructions only work on registers.
18674 The same is true of the fcomi compare instructions. The XFmode
18675 compare instructions require registers except when comparing
18676 against zero or when converting operand 1 from fixed point to
18677 floating point. */
18686 {
18689 }
18690 else
18691 {
18692 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
18693 things around if they appear profitable, otherwise force op0
18694 into a register. */
18700 {
18703 {
18704 rtx tmp;
18707 }
18708 }
18714 {
18719 {
18722 }
18723 else
18725 }
18726 }
18728 /* Try to rearrange the comparison to make it cheaper. */
18732 {
18733 rtx tmp;
18738 }
18743 }
18745 /* Convert comparison codes we use to represent FP comparison to integer
18746 code that will result in proper branch. Return UNKNOWN if no such code
18747 is available. */
18749 enum rtx_code
18751 {
18753 {
18776 }
18777 }
18779 /* Generate insn patterns to do a floating point compare of OPERANDS. */
18781 static rtx
18783 {
18790 /* Do fcomi/sahf based test when profitable. */
18792 {
18797 tmp);
18805 tmp);
18814 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
18821 /* In the unordered case, we have to check C2 for NaN's, which
18822 doesn't happen to work out to anything nice combination-wise.
18823 So do some bit twiddling on the value we've got in AH to come
18824 up with an appropriate set of condition codes. */
18828 {
18832 {
18835 }
18836 else
18837 {
18843 }
18848 {
18853 }
18854 else
18855 {
18858 }
18863 {
18866 }
18867 else
18868 {
18872 }
18877 {
18883 }
18884 else
18885 {
18888 }
18893 {
18898 }
18899 else
18900 {
18903 }
18908 {
18913 }
18914 else
18915 {
18918 }
18932 }
18937 }
18939 /* Return the test that should be put into the flags user, i.e.
18940 the bcc, scc, or cmov instruction. */
18943 const0_rtx);
18944 }
18946 static rtx
18948 {
18949 rtx ret;
18955 {
18958 }
18959 else
18963 }
18965 void
18967 {
18969 rtx tmp;
18972 {
18979 simple:
18983 pc_rtx);
18991 /* Expand DImode branch into multiple compare+branch. */
18992 {
18998 {
19001 }
19008 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
19009 avoid two branches. This costs one extra insn, so disable when
19010 optimizing for size. */
19015 {
19033 }
19035 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19036 op1 is a constant and the low word is zero, then we can just
19037 examine the high word. Similarly for low word -1 and
19038 less-or-equal-than or greater-than. */
19042 {
19045 {
19048 }
19052 {
19055 }
19059 }
19061 /* Otherwise, we need two or three jumps. */
19070 {
19084 }
19086 /*
19087 * a < b =>
19088 * if (hi(a) < hi(b)) goto true;
19089 * if (hi(a) > hi(b)) goto false;
19090 * if (lo(a) < lo(b)) goto true;
19091 * false:
19092 */
19104 }
19109 }
19110 }
19112 /* Split branch based on floating point condition. */
19113 void
19116 {
19117 rtx condition;
19118 rtx i;
19121 {
19126 }
19129 tmp);
19131 /* Remove pushed operand from stack. */
19141 }
19143 void
19145 {
19146 rtx ret;
19153 }
19155 /* Expand comparison setting or clearing carry flag. Return true when
19156 successful and set pop for the operation. */
19157 static bool
19159 {
19163 /* Do not handle double-mode compares that go through special path. */
19168 {
19173 /* Shortcut: following common codes never translate
19174 into carry flag compares. */
19179 /* These comparisons require zero flag; swap operands so they won't. */
19182 {
19187 }
19189 /* Try to expand the comparison and verify that we end up with
19190 carry flag based comparison. This fails to be true only when
19191 we decide to expand comparison using arithmetic that is not
19192 too common scenario. */
19201 else
19210 }
19216 {
19221 /* Convert a==0 into (unsigned)a<1. */
19230 /* Convert a>b into b<a or a>=b-1. */
19234 {
19236 /* Bail out on overflow. We still can swap operands but that
19237 would force loading of the constant into register. */
19242 }
19243 else
19244 {
19249 }
19252 /* Convert a>=0 into (unsigned)a<0x80000000. */
19270 }
19271 /* Swapping operands may cause constant to appear as first operand. */
19273 {
19277 }
19281 }
19283 bool
19285 {
19309 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
19310 HImode insns, we'd be swallowed in word prefix ops. */
19316 {
19320 HOST_WIDE_INT diff;
19323 /* Sign bit compares are better done using shifts than we do by using
19324 sbb. */
19327 {
19328 /* Detect overlap between destination and compare sources. */
19332 {
19333 rtx flags;
19342 {
19344 compare_code
19346 }
19348 /* To simplify rest of code, restrict to the GEU case. */
19350 {
19356 }
19357 else
19358 {
19361 reverse_condition_maybe_unordered
19363 else
19366 }
19375 else
19378 }
19379 else
19380 {
19383 else
19384 {
19389 }
19391 }
19394 {
19395 /*
19396 * cmpl op0,op1
19397 * sbbl dest,dest
19398 * [addl dest, ct]
19399 *
19400 * Size 5 - 8.
19401 */
19406 }
19408 {
19409 /*
19410 * cmpl op0,op1
19411 * sbbl dest,dest
19412 * orl $ct, dest
19413 *
19414 * Size 8.
19415 */
19419 }
19421 {
19422 /*
19423 * cmpl op0,op1
19424 * sbbl dest,dest
19425 * notl dest
19426 * [addl dest, cf]
19427 *
19428 * Size 8 - 11.
19429 */
19435 }
19436 else
19437 {
19438 /*
19439 * cmpl op0,op1
19440 * sbbl dest,dest
19441 * [notl dest]
19442 * andl cf - ct, dest
19443 * [addl dest, ct]
19444 *
19445 * Size 8 - 11.
19446 */
19449 {
19453 }
19463 }
19469 }
19472 {
19475 HOST_WIDE_INT tmp;
19480 {
19483 /* We may be reversing unordered compare to normal compare, that
19484 is not valid in general (we may convert non-trapping condition
19485 to trapping one), however on i386 we currently emit all
19486 comparisons unordered. */
19489 }
19490 else
19491 {
19494 }
19495 }
19500 {
19505 {
19510 }
19511 }
19513 /* Optimize dest = (op0 < 0) ? -1 : cf. */
19517 {
19518 /* If lea code below could be used, only optimize
19519 if it results in a 2 insn sequence. */
19525 {
19526 /*
19527 * notl op1 (if necessary)
19528 * sarl $31, op1
19529 * orl cf, op1
19530 */
19532 {
19536 }
19547 }
19548 }
19556 {
19557 /*
19558 * xorl dest,dest
19559 * cmpl op1,op2
19560 * setcc dest
19561 * lea cf(dest*(ct-cf)),dest
19562 *
19563 * Size 14.
19564 *
19565 * This also catches the degenerate setcc-only case.
19566 */
19568 rtx tmp;
19574 /* On x86_64 the lea instruction operates on Pmode, so we need
19575 to get arithmetics done in proper mode to match. */
19578 else
19579 {
19580 rtx out1;
19583 nops++;
19585 {
19587 nops++;
19588 }
19589 }
19591 {
19593 nops++;
19594 }
19596 {
19599 else
19601 }
19606 }
19608 /*
19609 * General case: Jumpful:
19610 * xorl dest,dest cmpl op1, op2
19611 * cmpl op1, op2 movl ct, dest
19612 * setcc dest jcc 1f
19613 * decl dest movl cf, dest
19614 * andl (cf-ct),dest 1:
19615 * addl ct,dest
19616 *
19617 * Size 20. Size 14.
19618 *
19619 * This is reasonably steep, but branch mispredict costs are
19620 * high on modern cpus, so consider failing only if optimizing
19621 * for space.
19622 */
19627 {
19629 {
19636 {
19639 /* We may be reversing unordered compare to normal compare,
19640 that is not valid in general (we may convert non-trapping
19641 condition to trapping one), however on i386 we currently
19642 emit all comparisons unordered. */
19644 }
19645 else
19646 {
19650 }
19651 }
19654 {
19655 /* notl op1 (if needed)
19656 sarl $31, op1
19657 andl (cf-ct), op1
19658 addl ct, op1
19660 For x < 0 (resp. x <= -1) there will be no notl,
19661 so if possible swap the constants to get rid of the
19662 complement.
19663 True/false will be -1/0 while code below (store flag
19664 followed by decrement) is 0/-1, so the constants need
19665 to be exchanged once more. */
19668 {
19671 }
19672 else
19673 {
19677 }
19680 }
19681 else
19682 {
19686 constm1_rtx,
19688 }
19700 }
19701 }
19704 {
19705 /* Try a few things more with specific constants and a variable. */
19707 optab op;
19713 /* If one of the two operands is an interesting constant, load a
19714 constant with the above and mask it in with a logical operation. */
19717 {
19723 else
19725 }
19727 {
19733 else
19735 }
19736 else
19743 /* Recurse to get the constant loaded. */
19747 /* Mask in the interesting variable. */
19749 OPTAB_WIDEN);
19754 }
19756 /*
19757 * For comparison with above,
19758 *
19759 * movl cf,dest
19760 * movl ct,tmp
19761 * cmpl op1,op2
19762 * cmovcc tmp,dest
19763 *
19764 * Size 15.
19765 */
19787 }
19789 /* Swap, force into registers, or otherwise massage the two operands
19790 to an sse comparison with a mask result. Thus we differ a bit from
19791 ix86_prepare_fp_compare_args which expects to produce a flags result.
19793 The DEST operand exists to help determine whether to commute commutative
19794 operators. The POP0/POP1 operands are updated in place. The new
19795 comparison code is returned, or UNKNOWN if not implementable. */
19797 static enum rtx_code
19800 {
19801 rtx tmp;
19804 {
19807 /* AVX supports all the needed comparisons. */
19810 /* We have no LTGT as an operator. We could implement it with
19811 NE & ORDERED, but this requires an extra temporary. It's
19812 not clear that it's worth it. */
19819 /* These are supported directly. */
19826 /* AVX has 3 operand comparisons, no need to swap anything. */
19829 /* For commutative operators, try to canonicalize the destination
19830 operand to be first in the comparison - this helps reload to
19831 avoid extra moves. */
19834 /* FALLTHRU */
19840 /* These are not supported directly before AVX, and furthermore
19841 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
19842 comparison operands to transform into something that is
19843 supported. */
19852 }
19855 }
19857 /* Detect conditional moves that exactly match min/max operational
19858 semantics. Note that this is IEEE safe, as long as we don't
19859 interchange the operands.
19861 Returns FALSE if this conditional move doesn't match a MIN/MAX,
19862 and TRUE if the operation is successful and instructions are emitted. */
19864 static bool
19867 {
19870 rtx tmp;
19873 ;
19875 {
19879 }
19880 else
19887 else
19892 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
19893 but MODE may be a vector mode and thus not appropriate. */
19895 {
19897 rtvec v;
19902 }
19903 else
19904 {
19907 }
19911 }
19913 /* Expand an sse vector comparison. Return the register with the result. */
19915 static rtx
19918 {
19921 rtx x;
19934 {
19937 }
19938 else
19942 }
19944 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
19945 operations. This is used for both scalar and vector conditional moves. */
19947 static void
19949 {
19955 {
19957 }
19959 {
19963 }
19965 {
19970 }
19972 {
19976 }
19978 {
19986 op_true,
19987 op_false)));
19988 }
19989 else
19990 {
19999 {
20013 {
20019 }
20034 {
20040 }
20044 }
20048 else
20049 {
20055 else
20067 }
20068 }
20069 }
20071 /* Expand a floating-point conditional move. Return true if successful. */
20073 bool
20075 {
20083 {
20086 /* Since we've no cmove for sse registers, don't force bad register
20087 allocation just to gain access to it. Deny movcc when the
20088 comparison mode doesn't match the move mode. */
20107 }
20114 /* The floating point conditional move instructions don't directly
20115 support conditions resulting from a signed integer comparison. */
20119 {
20124 }
20131 }
20133 /* Expand a floating-point vector conditional move; a vcond operation
20134 rather than a movcc operation. */
20136 bool
20138 {
20140 rtx cmp;
20145 {
20146 rtx temp;
20148 {
20165 }
20167 OPTAB_DIRECT);
20170 }
20180 }
20182 /* Expand a signed/unsigned integral vector conditional move. */
20184 bool
20186 {
20196 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
20197 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
20206 {
20210 {
20216 }
20219 {
20225 }
20226 }
20235 /* XOP supports all of the comparisons on all 128-bit vector int types. */
20239 ;
20240 else
20241 {
20242 /* Canonicalize the comparison to EQ, GT, GTU. */
20244 {
20261 /* FALLTHRU */
20271 }
20273 /* Only SSE4.1/SSE4.2 supports V2DImode. */
20275 {
20277 {
20279 /* SSE4.1 supports EQ. */
20286 /* SSE4.2 supports GT/GTU. */
20293 }
20294 }
20296 /* Unsigned parallel compare is not supported by the hardware.
20297 Play some tricks to turn this into a signed comparison
20298 against 0. */
20300 {
20304 {
20309 {
20314 {
20321 }
20322 /* Subtract (-(INT MAX) - 1) from both operands to make
20323 them signed. */
20334 }
20341 /* Perform a parallel unsigned saturating subtraction. */
20354 }
20355 }
20356 }
20358 /* Allow the comparison to be done in one mode, but the movcc to
20359 happen in another mode. */
20361 {
20364 }
20365 else
20366 {
20372 }
20377 }
20379 /* Expand a variable vector permutation. */
20381 void
20383 {
20394 /* Number of elements in the vector. */
20400 {
20402 {
20403 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
20404 an constant shuffle operand. With a tiny bit of effort we can
20405 use VPERMD instead. A re-interpretation stall for V4DFmode is
20406 unfortunate but there's no avoiding it.
20407 Similarly for V16HImode we don't have instructions for variable
20408 shuffling, while for V32QImode we can use after preparing suitable
20409 masks vpshufb; vpshufb; vpermq; vpor. */
20412 {
20416 }
20417 else
20418 {
20422 }
20425 /* Replicate the low bits of the V4DImode mask into V8SImode:
20426 mask = { A B C D }
20427 t1 = { A A B B C C D D }. */
20435 else
20438 /* Multiply the shuffle indicies by two. */
20440 OPTAB_DIRECT);
20442 /* Add one to the odd shuffle indicies:
20443 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
20445 {
20448 }
20452 OPTAB_DIRECT);
20454 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
20459 }
20462 {
20464 /* The VPERMD and VPERMPS instructions already properly ignore
20465 the high bits of the shuffle elements. No need for us to
20466 perform an AND ourselves. */
20469 else
20470 {
20476 }
20483 else
20484 {
20490 }
20494 /* By combining the two 128-bit input vectors into one 256-bit
20495 input vector, we can use VPERMD and VPERMPS for the full
20496 two-operand shuffle. */
20528 /* From mask create two adjusted masks, which contain the same
20529 bits as mask in the low 7 bits of each vector element.
20530 The first mask will have the most significant bit clear
20531 if it requests element from the same 128-bit lane
20532 and MSB set if it requests element from the other 128-bit lane.
20533 The second mask will have the opposite values of the MSB,
20534 and additionally will have its 128-bit lanes swapped.
20535 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
20536 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
20537 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
20538 stands for other 12 bytes. */
20539 /* The bit whether element is from the same lane or the other
20540 lane is bit 4, so shift it up by 3 to the MSB position. */
20544 /* Clear MSB bits from the mask just in case it had them set. */
20546 /* After this t1 will have MSB set for elements from other lane. */
20548 /* Clear bits other than MSB. */
20550 /* Or in the lower bits from mask into t3. */
20552 /* And invert MSB bits in t1, so MSB is set for elements from the same
20553 lane. */
20555 /* Swap 128-bit lanes in t3. */
20560 /* And or in the lower bits from mask into t1. */
20563 {
20564 /* Each of these shuffles will put 0s in places where
20565 element from the other 128-bit lane is needed, otherwise
20566 will shuffle in the requested value. */
20569 /* For t3 the 128-bit lanes are swapped again. */
20574 /* And oring both together leads to the result. */
20577 }
20580 /* Similarly to the above one_operand_shuffle code,
20581 just for repeated twice for each operand. merge_two:
20582 code will merge the two results together. */
20604 }
20605 }
20608 {
20609 /* The XOP VPPERM insn supports three inputs. By ignoring the
20610 one_operand_shuffle special case, we avoid creating another
20611 set of constant vectors in memory. */
20614 /* mask = mask & {2*w-1, ...} */
20616 }
20617 else
20618 {
20619 /* mask = mask & {w-1, ...} */
20621 }
20629 /* For non-QImode operations, convert the word permutation control
20630 into a byte permutation control. */
20632 {
20637 /* Convert mask to vector of chars. */
20640 /* Replicate each of the input bytes into byte positions:
20641 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
20642 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
20643 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
20650 else
20653 /* Convert it into the byte positions by doing
20654 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
20660 }
20662 /* The actual shuffle operations all operate on V16QImode. */
20668 {
20670 }
20672 {
20674 }
20675 else
20676 {
20680 /* Shuffle the two input vectors independently. */
20686 merge_two:
20687 /* Then merge them together. The key is whether any given control
20688 element contained a bit set that indicates the second word. */
20692 {
20693 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
20694 more shuffle to convert the V2DI input mask into a V4SI
20695 input mask. At which point the masking that expand_int_vcond
20696 will work as desired. */
20704 }
20721 }
20722 }
20724 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
20725 true if we should do zero extension, else sign extension. HIGH_P is
20726 true if we want the N/2 high elements, else the low elements. */
20728 void
20730 {
20732 rtx tmp;
20735 {
20741 {
20745 else
20748 extract
20754 else
20757 extract
20763 else
20766 extract
20772 else
20778 else
20784 else
20789 }
20792 {
20795 }
20797 {
20798 /* Shift higher 8 bytes to lower 8 bytes. */
20803 }
20804 else
20808 }
20809 else
20810 {
20814 {
20818 else
20824 else
20830 else
20835 }
20839 else
20844 }
20845 }
20847 /* Expand conditional increment or decrement using adb/sbb instructions.
20848 The default case using setcc followed by the conditional move can be
20849 done by generic code. */
20850 bool
20852 {
20854 rtx flags;
20856 rtx compare_op;
20874 {
20877 }
20880 {
20884 reverse_condition_maybe_unordered
20886 else
20888 }
20892 /* Construct either adc or sbb insn. */
20894 {
20896 {
20911 }
20912 }
20913 else
20914 {
20916 {
20931 }
20932 }
20936 }
20939 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
20940 but works for floating pointer parameters and nonoffsetable memories.
20941 For pushes, it returns just stack offsets; the values will be saved
20942 in the right order. Maximally three parts are generated. */
20944 static int
20946 {
20951 else
20957 /* Optimize constant pool reference to immediates. This is used by fp
20958 moves, that force all constants to memory to allow combining. */
20960 {
20964 }
20967 {
20968 /* The only non-offsetable memories we handle are pushes. */
20977 }
20980 {
20982 /* Caution: if we looked through a constant pool memory above,
20983 the operand may actually have a different mode now. That's
20984 ok, since we want to pun this all the way back to an integer. */
20988 }
20991 {
20994 else
20995 {
20999 {
21003 }
21005 {
21010 }
21012 {
21013 REAL_VALUE_TYPE r;
21018 {
21025 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
21026 long double may not be 80-bit. */
21035 }
21038 }
21039 else
21041 }
21042 }
21043 else
21044 {
21048 {
21051 {
21055 }
21057 {
21061 }
21063 {
21064 REAL_VALUE_TYPE r;
21070 /* Do not use shift by 32 to avoid warning on 32bit systems. */
21073 = gen_int_mode
21076 DImode);
21077 else
21084 = gen_int_mode
21087 DImode);
21088 else
21090 }
21091 else
21093 }
21094 }
21097 }
21099 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
21100 Return false when normal moves are needed; true when all required
21101 insns have been emitted. Operands 2-4 contain the input values
21102 int the correct order; operands 5-7 contain the output values. */
21104 void
21106 {
21114 /* The DFmode expanders may ask us to move double.
21115 For 64bit target this is single move. By hiding the fact
21116 here we simplify i386.md splitters. */
21118 {
21119 /* Optimize constant pool reference to immediates. This is used by
21120 fp moves, that force all constants to memory to allow combining. */
21127 {
21130 }
21131 else
21136 }
21138 /* The only non-offsettable memory we handle is push. */
21141 else
21148 /* When emitting push, take care for source operands on the stack. */
21151 {
21154 /* Compensate for the stack decrement by 4. */
21159 /* src_base refers to the stack pointer and is
21160 automatically decreased by emitted push. */
21164 }
21166 /* We need to do copy in the right order in case an address register
21167 of the source overlaps the destination. */
21169 {
21170 rtx tmp;
21173 {
21177 collisions++;
21178 }
21180 /* Collision in the middle part can be handled by reordering. */
21182 {
21185 }
21189 {
21191 {
21194 }
21195 else
21196 {
21199 }
21200 }
21202 /* If there are more collisions, we can't handle it by reordering.
21203 Do an lea to the last part and use only one colliding move. */
21205 {
21206 rtx base;
21212 /* Handle the case when the last part isn't valid for lea.
21213 Happens in 64-bit mode storing the 12-byte XFmode. */
21220 {
21223 }
21224 }
21225 }
21228 {
21230 {
21232 {
21237 }
21239 {
21242 }
21243 }
21244 else
21245 {
21246 /* In 64bit mode we don't have 32bit push available. In case this is
21247 register, it is OK - we will just use larger counterpart. We also
21248 retype memory - these comes from attempt to avoid REX prefix on
21249 moving of second half of TFmode value. */
21251 {
21253 {
21264 }
21268 }
21269 }
21273 }
21275 /* Choose correct order to not overwrite the source before it is copied. */
21285 {
21287 {
21290 }
21291 }
21292 else
21293 {
21295 {
21298 }
21299 }
21301 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
21303 {
21312 }
21318 }
21320 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
21321 left shift by a constant, either using a single shift or
21322 a sequence of add instructions. */
21324 static void
21326 {
21332 {
21336 }
21337 else
21338 {
21341 }
21342 }
21344 void
21346 {
21355 {
21360 {
21366 }
21367 else
21368 {
21376 }
21378 }
21385 {
21386 /* Assuming we've chosen a QImode capable registers, then 1 << N
21387 can be done with two 32/64-bit shifts, no branches, no cmoves. */
21389 {
21405 }
21407 /* Otherwise, we can get the same results by manually performing
21408 a bit extract operation on bit 5/6, and then performing the two
21409 shifts. The two methods of getting 0/1 into low/high are exactly
21410 the same size. Avoiding the shift in the bit extract case helps
21411 pentium4 a bit; no one else seems to care much either way. */
21412 else
21413 {
21418 HOST_WIDE_INT bits;
21419 rtx x;
21422 {
21428 }
21429 else
21430 {
21436 }
21440 else
21448 }
21453 }
21456 {
21457 /* For -1 << N, we can avoid the shld instruction, because we
21458 know that we're shifting 0...31/63 ones into a -1. */
21462 else
21464 }
21465 else
21466 {
21474 }
21479 {
21485 }
21486 else
21487 {
21492 }
21493 }
21495 void
21497 {
21507 {
21512 {
21518 }
21520 {
21529 }
21530 else
21531 {
21539 }
21540 }
21541 else
21542 {
21554 {
21562 scratch));
21563 }
21564 else
21565 {
21570 }
21571 }
21572 }
21574 void
21576 {
21586 {
21591 {
21598 }
21599 else
21600 {
21608 }
21609 }
21610 else
21611 {
21623 {
21629 scratch));
21630 }
21631 else
21632 {
21637 }
21638 }
21639 }
21641 /* Predict just emitted jump instruction to be taken with probability PROB. */
21642 static void
21644 {
21648 }
21650 /* Helper function for the string operations below. Dest VARIABLE whether
21651 it is aligned to VALUE bytes. If true, jump to the label. */
21652 static rtx
21654 {
21659 else
21665 else
21668 }
21670 /* Adjust COUNTER by the VALUE. */
21671 static void
21673 {
21678 }
21680 /* Zero extend possibly SImode EXP to Pmode register. */
21681 rtx
21683 {
21685 }
21687 /* Divide COUNTREG by SCALE. */
21688 static rtx
21690 {
21691 rtx sc;
21703 }
21705 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
21706 DImode for constant loop counts. */
21708 static enum machine_mode
21710 {
21718 }
21720 /* When SRCPTR is non-NULL, output simple loop to move memory
21721 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
21722 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
21723 equivalent loop to set memory by VALUE (supposed to be in MODE).
21725 The size is rounded down to whole number of chunk size moved at once.
21726 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
21729 static void
21734 {
21739 rtx size;
21740 rtx x_addr;
21741 rtx y_addr;
21750 /* Those two should combine. */
21752 {
21756 }
21766 {
21770 /* When unrolling for chips that reorder memory reads and writes,
21771 we can save registers by using single temporary.
21772 Also using 4 temporaries is overkill in 32bit mode. */
21774 {
21776 {
21778 {
21779 destmem =
21781 srcmem =
21783 }
21785 }
21786 }
21787 else
21788 {
21792 {
21795 {
21796 srcmem =
21798 }
21800 }
21802 {
21804 {
21805 destmem =
21807 }
21809 }
21810 }
21811 }
21812 else
21814 {
21816 destmem =
21819 }
21829 {
21835 else
21837 }
21838 else
21846 {
21851 }
21853 }
21855 /* Output "rep; mov" instruction.
21856 Arguments have same meaning as for previous function */
21857 static void
21860 rtx count,
21862 {
21863 rtx destexp;
21864 rtx srcexp;
21865 rtx countreg;
21866 HOST_WIDE_INT rounded_count;
21868 /* If the size is known, it is shorter to use rep movs. */
21879 {
21886 }
21887 else
21888 {
21891 }
21893 {
21900 }
21901 else
21902 {
21907 }
21910 }
21912 /* Output "rep; stos" instruction.
21913 Arguments have same meaning as for previous function */
21914 static void
21917 rtx orig_value)
21918 {
21919 rtx destexp;
21920 rtx countreg;
21921 HOST_WIDE_INT rounded_count;
21928 {
21932 }
21933 else
21936 {
21941 }
21945 }
21947 static void
21950 {
21954 }
21956 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
21957 static void
21960 {
21963 {
21968 {
21970 {
21973 }
21974 else
21977 }
21979 {
21982 else
21983 {
21986 }
21988 }
21990 {
21993 }
21995 {
21998 }
22000 {
22003 }
22005 }
22007 {
22013 }
22015 /* When there are stringops, we can cheaply increase dest and src pointers.
22016 Otherwise we save code size by maintaining offset (zero is readily
22017 available from preceding rep operation) and using x86 addressing modes.
22018 */
22020 {
22022 {
22029 }
22031 {
22038 }
22040 {
22047 }
22048 }
22049 else
22050 {
22052 rtx tmp;
22055 {
22066 }
22068 {
22081 }
22083 {
22092 }
22093 }
22094 }
22096 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22097 static void
22100 {
22101 count =
22107 }
22109 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22110 static void
22112 {
22113 rtx dest;
22116 {
22121 {
22123 {
22128 }
22129 else
22132 }
22134 {
22136 {
22139 }
22140 else
22141 {
22146 }
22148 }
22150 {
22154 }
22156 {
22160 }
22162 {
22166 }
22168 }
22170 {
22173 }
22175 {
22178 {
22182 }
22183 else
22184 {
22190 }
22193 }
22195 {
22198 {
22201 }
22202 else
22203 {
22207 }
22210 }
22212 {
22218 }
22220 {
22226 }
22228 {
22234 }
22235 }
22237 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
22238 DESIRED_ALIGNMENT. */
22239 static void
22243 {
22245 {
22253 }
22255 {
22263 }
22265 {
22273 }
22275 }
22277 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
22278 ALIGN_BYTES is how many bytes need to be copied. */
22279 static rtx
22282 {
22291 {
22296 }
22298 {
22309 }
22311 {
22317 {
22325 }
22328 }
22334 {
22346 }
22353 }
22355 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
22356 DESIRED_ALIGNMENT. */
22357 static void
22360 {
22362 {
22369 }
22371 {
22378 }
22380 {
22387 }
22389 }
22391 /* Set enough from DST to align DST known to by aligned by ALIGN to
22392 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
22393 static rtx
22396 {
22400 {
22405 }
22407 {
22414 }
22416 {
22423 }
22430 }
22432 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
22433 static enum stringop_alg
22436 {
22439 /* Algorithms using the rep prefix want at least edi and ecx;
22440 additionally, memset wants eax and memcpy wants esi. Don't
22441 consider such algorithms if the user has appropriated those
22442 registers for their own purposes. */
22444 || (memset
22448 #define ALG_USABLE_P(alg) (rep_prefix_usable \
22449 || (alg != rep_prefix_1_byte \
22450 && alg != rep_prefix_4_byte \
22451 && alg != rep_prefix_8_byte))
22454 /* Even if the string operation call is cold, we still might spend a lot
22455 of time processing large blocks. */
22460 else
22468 else
22472 /* rep; movq or rep; movl is the smallest variant. */
22474 {
22477 else
22479 }
22480 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
22481 */
22485 {
22489 {
22490 /* We get here if the algorithms that were not libcall-based
22491 were rep-prefix based and we are unable to use rep prefixes
22492 based on global register usage. Break out of the loop and
22493 use the heuristic below. */
22497 {
22502 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
22503 last non-libcall inline algorithm. */
22505 {
22506 /* When the current size is best to be copied by a libcall,
22507 but we are still forced to inline, run the heuristic below
22508 that will pick code for medium sized blocks. */
22512 }
22514 {
22517 }
22518 }
22519 }
22521 }
22522 /* When asked to inline the call anyway, try to pick meaningful choice.
22523 We look for maximal size of block that is faster to copy by hand and
22524 take blocks of at most of that size guessing that average size will
22525 be roughly half of the block.
22527 If this turns out to be bad, we might simply specify the preferred
22528 choice in ix86_costs. */
22531 {
22538 {
22545 }
22546 /* If there aren't any usable algorithms, then recursing on
22547 smaller sizes isn't going to find anything. Just return the
22548 simple byte-at-a-time copy loop. */
22550 {
22551 /* Pick something reasonable. */
22555 }
22564 }
22566 #undef ALG_USABLE_P
22567 }
22569 /* Decide on alignment. We know that the operand is already aligned to ALIGN
22570 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
22571 static int
22575 {
22578 {
22589 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22590 copying whole cacheline at once. */
22593 else
22597 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22598 copying whole cacheline at once. */
22601 else
22609 }
22618 }
22620 /* Return the smallest power of 2 greater than VAL. */
22621 static int
22623 {
22628 }
22630 /* Expand string move (memcpy) operation. Use i386 string operations
22631 when profitable. expand_setmem contains similar code. The code
22632 depends upon architecture, block size and alignment, but always has
22633 the same overall structure:
22635 1) Prologue guard: Conditional that jumps up to epilogues for small
22636 blocks that can be handled by epilogue alone. This is faster
22637 but also needed for correctness, since prologue assume the block
22638 is larger than the desired alignment.
22640 Optional dynamic check for size and libcall for large
22641 blocks is emitted here too, with -minline-stringops-dynamically.
22643 2) Prologue: copy first few bytes in order to get destination
22644 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
22645 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
22646 copied. We emit either a jump tree on power of two sized
22647 blocks, or a byte loop.
22649 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
22650 with specified algorithm.
22652 4) Epilogue: code copying tail of the block that is too small to be
22653 handled by main body (or up to size guarded by prologue guard). */
22655 bool
22658 {
22659 rtx destreg;
22660 rtx srcreg;
22662 rtx tmp;
22676 /* i386 can do misaligned access on reasonably increased cost. */
22680 /* ALIGN is the minimum of destination and source alignment, but we care here
22681 just about destination alignment. */
22690 /* Make sure we don't need to care about overflow later on. */
22694 /* Step 0: Decide on preferred algorithm, desired alignment and
22695 size of chunks to be copied by main loop. */
22711 {
22736 }
22740 /* Step 1: Prologue guard. */
22742 /* Alignment code needs count to be in register. */
22744 {
22747 {
22748 align_bytes
22752 else
22754 }
22757 }
22760 /* Ensure that alignment prologue won't copy past end of block. */
22762 {
22764 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
22765 Make sure it is power of 2. */
22769 {
22771 {
22772 /* If main algorithm works on QImode, no epilogue is needed.
22773 For small sizes just don't align anything. */
22776 else
22778 }
22779 }
22780 else
22781 {
22788 else
22790 }
22791 }
22793 /* Emit code to decide on runtime whether library call or inline should be
22794 used. */
22796 {
22798 {
22800 {
22804 }
22805 }
22806 else
22807 {
22816 }
22817 }
22819 /* Step 2: Alignment prologue. */
22822 {
22824 {
22825 /* Except for the first move in epilogue, we no longer know
22826 constant offset in aliasing info. It don't seems to worth
22827 the pain to maintain it for the first move, so throw away
22828 the info early. */
22832 desired_align);
22833 }
22834 else
22835 {
22836 /* If we know how many bytes need to be stored before dst is
22837 sufficiently aligned, maintain aliasing info accurately. */
22843 }
22849 {
22850 /* It is possible that we copied enough so the main loop will not
22851 execute. */
22861 else
22863 }
22864 }
22866 {
22871 }
22875 /* Step 3: Main loop. */
22878 {
22891 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
22892 registers for 4 temporaries anyway. */
22895 expected_size);
22899 DImode);
22903 SImode);
22907 QImode);
22909 }
22910 /* Adjust properly the offset of src and dest memory for aliasing. */
22912 {
22917 }
22918 else
22919 {
22922 }
22924 /* Step 4: Epilogue to copy the remaining bytes. */
22925 epilogue:
22927 {
22928 /* When the main loop is done, COUNT_EXP might hold original count,
22929 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
22930 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
22931 bytes. Compensate if needed. */
22934 {
22935 tmp =
22938 OPTAB_DIRECT);
22941 }
22944 }
22948 epilogue_size_needed);
22952 }
22954 /* Helper function for memcpy. For QImode value 0xXY produce
22955 0xXYXYXYXY of wide specified by MODE. This is essentially
22956 a * 0x10101010, but we can do slightly better than
22957 synth_mult by unwinding the sequence by hand on CPUs with
22958 slow multiply. */
22959 static rtx
22961 {
22963 rtx tmp;
22970 {
22978 }
22987 nops--;
22992 {
22996 OPTAB_DIRECT);
22997 }
22998 else
22999 {
23005 else
23007 else
23008 {
23011 reg =
23013 }
23023 }
23024 }
23026 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
23027 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
23028 alignment from ALIGN to DESIRED_ALIGN. */
23029 static rtx
23031 {
23032 rtx promoted_val;
23041 else
23045 }
23047 /* Expand string clear operation (bzero). Use i386 string operations when
23048 profitable. See expand_movmem comment for explanation of individual
23049 steps performed. */
23050 bool
23053 {
23054 rtx destreg;
23056 rtx tmp;
23072 /* i386 can do misaligned access on reasonably increased cost. */
23081 /* Make sure we don't need to care about overflow later on. */
23085 /* Step 0: Decide on preferred algorithm, desired alignment and
23086 size of chunks to be copied by main loop. */
23101 {
23126 }
23129 /* Step 1: Prologue guard. */
23131 /* Alignment code needs count to be in register. */
23133 {
23136 {
23137 align_bytes
23141 else
23143 }
23145 {
23150 }
23151 }
23152 /* Do the cheap promotion to allow better CSE across the
23153 main loop and epilogue (ie one load of the big constant in the
23154 front of all code. */
23158 /* Ensure that alignment prologue won't copy past end of block. */
23160 {
23162 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
23163 Make sure it is power of 2. */
23166 /* To improve performance of small blocks, we jump around the VAL
23167 promoting mode. This mean that if the promoted VAL is not constant,
23168 we might not use it in the epilogue and have to use byte
23169 loop variant. */
23173 {
23175 {
23176 /* If main algorithm works on QImode, no epilogue is needed.
23177 For small sizes just don't align anything. */
23180 else
23182 }
23183 }
23184 else
23185 {
23192 else
23194 }
23195 }
23197 {
23206 }
23208 /* Step 2: Alignment prologue. */
23210 /* Do the expensive promotion once we branched off the small blocks. */
23217 {
23219 {
23220 /* Except for the first move in epilogue, we no longer know
23221 constant offset in aliasing info. It don't seems to worth
23222 the pain to maintain it for the first move, so throw away
23223 the info early. */
23226 desired_align);
23227 }
23228 else
23229 {
23230 /* If we know how many bytes need to be stored before dst is
23231 sufficiently aligned, maintain aliasing info accurately. */
23237 }
23243 {
23244 /* It is possible that we copied enough so the main loop will not
23245 execute. */
23255 else
23257 }
23258 }
23260 {
23266 }
23270 /* Step 3: Main loop. */
23273 {
23301 }
23302 /* Adjust properly the offset of src and dest memory for aliasing. */
23306 else
23309 /* Step 4: Epilogue to copy the remaining bytes. */
23312 {
23313 /* When the main loop is done, COUNT_EXP might hold original count,
23314 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23315 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23316 bytes. Compensate if needed. */
23319 {
23320 tmp =
23323 OPTAB_DIRECT);
23326 }
23329 }
23330 epilogue:
23332 {
23335 epilogue_size_needed);
23336 else
23338 epilogue_size_needed);
23339 }
23343 }
23345 /* Expand the appropriate insns for doing strlen if not just doing
23346 repnz; scasb
23348 out = result, initialized with the start address
23349 align_rtx = alignment of the address.
23350 scratch = scratch register, initialized with the startaddress when
23351 not aligned, otherwise undefined
23353 This is just the body. It needs the initializations mentioned above and
23354 some address computing at the end. These things are done in i386.md. */
23356 static void
23358 {
23360 rtx tmp;
23365 rtx mem;
23368 rtx cmp;
23374 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
23376 /* Is there a known alignment and is it less than 4? */
23378 {
23381 /* Is there a known alignment and is it not 2? */
23383 {
23387 /* Leave just the 3 lower bits. */
23397 }
23398 else
23399 {
23400 /* Since the alignment is 2, we have to check 2 or 0 bytes;
23401 check if is aligned to 4 - byte. */
23408 }
23412 /* Now compare the bytes. */
23414 /* Compare the first n unaligned byte on a byte per byte basis. */
23418 /* Increment the address. */
23421 /* Not needed with an alignment of 2 */
23423 {
23427 end_0_label);
23432 }
23435 end_0_label);
23438 }
23440 /* Generate loop to check 4 bytes at a time. It is not a good idea to
23441 align this loop. It gives only huge programs, but does not help to
23442 speed up. */
23449 /* This formula yields a nonzero result iff one of the bytes is zero.
23450 This saves three branches inside loop and many cycles. */
23458 align_4_label);
23461 {
23467 /* If zero is not in the first two bytes, move two bytes forward. */
23473 reg,
23474 tmpreg)));
23475 /* Emit lea manually to avoid clobbering of flags. */
23483 reg2,
23484 out)));
23485 }
23486 else
23487 {
23489 /* Is zero in the first two bytes? */
23496 pc_rtx);
23500 /* Not in the first two. Move two bytes forward. */
23506 }
23508 /* Avoid branch in fixing the byte. */
23516 }
23518 /* Expand strlen. */
23520 bool
23522 {
23525 /* The generic case of strlen expander is long. Avoid it's
23526 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
23529 && !TARGET_INLINE_ALL_STRINGOPS
23539 {
23540 /* Well it seems that some optimizer does not combine a call like
23541 foo(strlen(bar), strlen(bar));
23542 when the move and the subtraction is done here. It does calculate
23543 the length just once when these instructions are done inside of
23544 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
23545 often used and I use one fewer register for the lifetime of
23546 output_strlen_unroll() this is better. */
23552 /* strlensi_unroll_1 returns the address of the zero at the end of
23553 the string, like memchr(), so compute the length by subtracting
23554 the start address. */
23556 }
23557 else
23558 {
23559 rtx unspec;
23561 /* Can't use this if the user has appropriated eax, ecx, or edi. */
23574 /* If .md starts supporting :P, this can be done in .md. */
23580 }
23582 }
23584 /* For given symbol (function) construct code to compute address of it's PLT
23585 entry in large x86-64 PIC model. */
23586 static rtx
23588 {
23601 }
23603 rtx
23605 rtx callarg2,
23607 {
23608 /* We need to represent that SI and DI registers are clobbered
23609 by SYSV calls. */
23615 };
23625 {
23626 #if TARGET_MACHO
23629 #endif
23630 }
23631 else
23632 {
23633 /* Static functions and indirect calls don't need the pic register. */
23638 }
23641 {
23645 }
23655 {
23658 }
23667 {
23671 }
23675 {
23679 UNSPEC_MS_TO_SYSV_CALL);
23687 }
23696 }
23698 /* Output the assembly for a call instruction. */
23702 {
23708 {
23711 /* SEH epilogue detection requires the indirect branch case
23712 to include REX.W. */
23715 else
23720 }
23722 /* SEH unwinding can require an extra nop to be emitted in several
23723 circumstances. Determine if we have one of those. */
23725 {
23726 rtx i;
23729 {
23730 /* If we get to another real insn, we don't need the nop. */
23734 /* If we get to the epilogue note, prevent a catch region from
23735 being adjacent to the standard epilogue sequence. If non-
23736 call-exceptions, we'll have done this during epilogue emission. */
23738 && !flag_non_call_exceptions
23740 {
23743 }
23744 }
23746 /* If we didn't find a real insn following the call, prevent the
23747 unwinder from looking into the next function. */
23750 }
23754 else
23763 }
23764 \f
23765 /* Clear stack slot assignments remembered from previous functions.
23766 This is called from INIT_EXPANDERS once before RTL is emitted for each
23767 function. */
23771 {
23779 }
23781 /* Return a MEM corresponding to a stack slot with mode MODE.
23782 Allocate a new slot if necessary.
23784 The RTL for a function can have several slots available: N is
23785 which slot to use. */
23787 rtx
23789 {
23806 }
23808 static void
23810 {
23816 }
23817 \f
23818 /* Calculate the length of the memory address in the instruction encoding.
23819 Includes addr32 prefix, does not include the one-byte modrm, opcode,
23820 or other prefixes. We never generate addr32 prefix for LEA insn. */
23822 int
23824 {
23841 /* If this is not LEA instruction, add the length of addr32 prefix. */
23846 len++;
23860 /* Rule of thumb:
23861 - esp as the base always wants an index,
23862 - ebp as the base always wants a displacement,
23863 - r12 as the base always wants an index,
23864 - r13 as the base always wants a displacement. */
23866 /* Register Indirect. */
23868 {
23869 /* esp (for its index) and ebp (for its displacement) need
23870 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
23871 code. */
23878 len++;
23879 }
23881 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
23882 is not disp32, but disp32(%rip), so for disp32
23883 SIB byte is needed, unless print_operand_address
23884 optimizes it into disp32(%rip) or (%rip) is implied
23885 by UNSPEC. */
23887 {
23890 {
23906 len++;
23907 }
23908 }
23909 else
23910 {
23911 /* Find the length of the displacement constant. */
23913 {
23916 else
23918 }
23919 /* ebp always wants a displacement. Similarly r13. */
23921 len++;
23923 /* An index requires the two-byte modrm form.... */
23925 /* ...like esp (or r12), which always wants an index. */
23929 len++;
23930 }
23933 }
23935 /* Compute default value for "length_immediate" attribute. When SHORTFORM
23936 is set, expect that insn have 8bit immediate alternative. */
23937 int
23939 {
23945 {
23950 {
23953 {
23965 }
23967 {
23970 }
23971 }
23973 {
23983 /* Immediates for DImode instructions are encoded
23984 as 32bit sign extended values. */
23990 }
23991 }
23993 }
23995 /* Compute default value for "length_address" attribute. */
23996 int
23998 {
24002 {
24013 }
24018 {
24021 {
24026 constraints++;
24029 ;
24030 /* Skip ignored operands. */
24033 }
24035 }
24037 }
24039 /* Compute default value for "length_vex" attribute. It includes
24040 2 or 3 byte VEX prefix and 1 opcode byte. */
24042 int
24044 {
24047 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
24048 byte VEX prefix. */
24052 /* We can always use 2 byte VEX prefix in 32bit. */
24060 {
24061 /* REX.W bit uses 3 byte VEX prefix. */
24065 }
24066 else
24067 {
24068 /* REX.X or REX.B bits use 3 byte VEX prefix. */
24072 }
24075 }
24076 \f
24077 /* Return the maximum number of instructions a cpu can issue. */
24079 static int
24081 {
24083 {
24109 }
24110 }
24112 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
24113 by DEP_INSN and nothing set by DEP_INSN. */
24115 static bool
24117 {
24120 /* Simplify the test for uninteresting insns. */
24128 {
24131 }
24136 {
24139 }
24140 else
24146 /* This test is true if the dependent insn reads the flags but
24147 not any other potentially set register. */
24155 }
24157 /* Return true iff USE_INSN has a memory address with operands set by
24158 SET_INSN. */
24160 bool
24162 {
24167 {
24170 }
24172 }
24174 static int
24176 {
24182 /* Anti and output dependencies have zero cost on all CPUs. */
24188 /* If we can't recognize the insns, we can't really do anything. */
24196 {
24198 /* Address Generation Interlock adds a cycle of latency. */
24200 {
24211 }
24215 /* ??? Compares pair with jump/setcc. */
24219 /* Floating point stores require value to be ready one cycle earlier. */
24229 /* INT->FP conversion is expensive. */
24233 /* There is one cycle extra latency between an FP op and a store. */
24241 /* Show ability of reorder buffer to hide latency of load by executing
24242 in parallel with previous instruction in case
24243 previous instruction is not needed to compute the address. */
24246 {
24247 /* Claim moves to take one cycle, as core can issue one load
24248 at time and the next load can start cycle later. */
24253 cost--;
24254 }
24260 /* The esp dependency is resolved before the instruction is really
24261 finished. */
24266 /* INT->FP conversion is expensive. */
24270 /* Show ability of reorder buffer to hide latency of load by executing
24271 in parallel with previous instruction in case
24272 previous instruction is not needed to compute the address. */
24275 {
24276 /* Claim moves to take one cycle, as core can issue one load
24277 at time and the next load can start cycle later. */
24283 else
24285 }
24301 /* Show ability of reorder buffer to hide latency of load by executing
24302 in parallel with previous instruction in case
24303 previous instruction is not needed to compute the address. */
24306 {
24310 /* Because of the difference between the length of integer and
24311 floating unit pipeline preparation stages, the memory operands
24312 for floating point are cheaper.
24314 ??? For Athlon it the difference is most probably 2. */
24317 else
24322 else
24324 }
24328 }
24331 }
24333 /* How many alternative schedules to try. This should be as wide as the
24334 scheduling freedom in the DFA, but no wider. Making this value too
24335 large results extra work for the scheduler. */
24337 static int
24339 {
24341 {
24353 /* Generally, we want haifa-sched:max_issue() to look ahead as far
24354 as many instructions can be executed on a cycle, i.e.,
24355 issue_rate. I wonder why tuning for many CPUs does not do this. */
24358 /* Don't use lookahead for pre-reload schedule to save compile time. */
24363 }
24364 }
24366 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
24367 execution. It is applied if
24368 (1) IMUL instruction is on the top of list;
24369 (2) There exists the only producer of independent IMUL instruction in
24370 ready list;
24371 (3) Put found producer on the top of ready list.
24372 Returns issue rate. */
24374 static int
24377 {
24382 sd_iterator_def sd_it;
24383 dep_t dep;
24386 /* Set up issue rate. */
24389 /* Do reodering for Atom only. */
24392 /* Do not perform ready list reodering for pre-reload schedule pass. */
24395 /* Nothing to do if ready list contains only 1 instruction. */
24399 /* Check that IMUL instruction is on the top of ready list. */
24412 /* Search for producer of independent IMUL instruction. */
24414 {
24418 /* Skip IMUL instruction. */
24428 {
24429 rtx con;
24440 {
24441 sd_iterator_def sd_it1;
24442 dep_t dep1;
24443 /* Check if there is no other dependee for IMUL. */
24446 {
24447 rtx pro;
24453 }
24456 }
24457 }
24460 }
24468 /* Put IMUL producer (ready[index]) at the top of ready list. */
24475 }
24477 static bool
24480 /* Returns true if lhs of insn is HW function argument register and set up
24481 is_spilled to true if it is likely spilled HW register. */
24482 static bool
24484 {
24485 rtx dst;
24489 /* Call instructions are not movable, ignore it. */
24500 {
24501 /* Is it likely spilled HW register? */
24506 }
24508 }
24510 /* Add output dependencies for chain of function adjacent arguments if only
24511 there is a move to likely spilled HW register. Return first argument
24512 if at least one dependence was added or NULL otherwise. */
24513 static rtx
24515 {
24516 rtx insn;
24523 /* Find nearest to call argument passing instruction. */
24525 {
24534 }
24538 {
24545 {
24548 }
24550 {
24551 /* Add output depdendence between two function arguments if chain
24552 of output arguments contains likely spilled HW registers. */
24556 }
24557 else
24559 }
24563 }
24565 /* Add output or anti dependency from insn to first_arg to restrict its code
24566 motion. */
24567 static void
24569 {
24570 rtx set;
24571 rtx tmp;
24578 {
24579 /* Add output dependency to the first function argument. */
24582 }
24583 /* Add anti dependency. */
24585 }
24587 /* Avoid cross block motion of function argument through adding dependency
24588 from the first non-jump instruction in bb. */
24589 static void
24591 {
24595 {
24597 {
24600 {
24603 }
24604 }
24608 }
24609 }
24611 /* Hook for pre-reload schedule - avoid motion of function arguments
24612 passed in likely spilled HW registers. */
24613 static void
24615 {
24616 rtx insn;
24624 {
24627 {
24628 /* Add dependee for first argument to predecessors if only
24629 region contains more than one block. */
24633 /* Skip trivial regions and region head blocks that can have
24634 predecessors outside of region. */
24636 {
24637 edge e;
24638 edge_iterator ei;
24639 /* Assume that region is SCC, i.e. all immediate predecessors
24640 of non-head block are in the same region. */
24642 {
24643 /* Avoid creating of loop-carried dependencies through
24644 using topological odering in region. */
24647 }
24648 }
24652 }
24653 }
24656 }
24658 /* Hook for pre-reload schedule - set priority of moves from likely spilled
24659 HW registers to maximum, to schedule them at soon as possible. These are
24660 moves from function argument registers at the top of the function entry
24661 and moves from function return value registers after call. */
24662 static int
24664 {
24665 rtx set;
24675 {
24682 }
24685 }
24687 /* Model decoder of Core 2/i7.
24688 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
24689 track the instruction fetch block boundaries and make sure that long
24690 (9+ bytes) instructions are assigned to D0. */
24692 /* Maximum length of an insn that can be handled by
24693 a secondary decoder unit. '8' for Core 2/i7. */
24696 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
24697 '16' for Core 2/i7. */
24700 /* Maximum number of instructions decoder can handle per cycle.
24701 '6' for Core 2/i7. */
24705 ix86_first_cycle_multipass_data_t;
24707 const_ix86_first_cycle_multipass_data_t;
24709 /* A variable to store target state across calls to max_issue within
24710 one cycle. */
24714 /* Initialize DATA. */
24715 static void
24717 {
24718 ix86_first_cycle_multipass_data_t data
24725 }
24727 /* Advancing the cycle; reset ifetch block counts. */
24728 static void
24730 {
24737 }
24741 /* Filter out insns from ready_try that the core will not be able to issue
24742 on current cycle due to decoder. */
24743 static void
24744 core2i7_first_cycle_multipass_filter_ready_try
24747 {
24749 {
24750 rtx insn;
24760 (!first_cycle_insn_p
24762 /* ... or it would not fit into the ifetch block ... */
24764 /* ... or the decoder is full already ... */
24766 /* ... mask the insn out. */
24767 {
24772 }
24773 }
24774 }
24776 /* Prepare for a new round of multipass lookahead scheduling. */
24777 static void
24780 {
24781 ix86_first_cycle_multipass_data_t data
24783 const_ix86_first_cycle_multipass_data_t prev_data
24786 /* Restore the state from the end of the previous round. */
24790 /* Filter instructions that cannot be issued on current cycle due to
24791 decoder restrictions. */
24793 first_cycle_insn_p);
24794 }
24796 /* INSN is being issued in current solution. Account for its impact on
24797 the decoder model. */
24798 static void
24801 {
24802 ix86_first_cycle_multipass_data_t data
24804 const_ix86_first_cycle_multipass_data_t prev_data
24814 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
24816 {
24819 }
24821 {
24825 }
24828 /* Filter out insns from ready_try that the core will not be able to issue
24829 on current cycle due to decoder. */
24832 }
24834 /* Revert the effect on ready_try. */
24835 static void
24839 {
24840 const_ix86_first_cycle_multipass_data_t data
24843 sbitmap_iterator sbi;
24847 {
24849 }
24850 }
24852 /* Save the result of multipass lookahead scheduling for the next round. */
24853 static void
24855 {
24856 const_ix86_first_cycle_multipass_data_t data
24858 ix86_first_cycle_multipass_data_t next_data
24862 {
24865 }
24866 }
24868 /* Deallocate target data. */
24869 static void
24871 {
24872 ix86_first_cycle_multipass_data_t data
24876 {
24880 }
24881 }
24883 /* Prepare for scheduling pass. */
24884 static void
24888 {
24889 /* Install scheduling hooks for current CPU. Some of these hooks are used
24890 in time-critical parts of the scheduler, so we only set them up when
24891 they are actually used. */
24893 {
24897 /* Do not perform multipass scheduling for pre-reload schedule
24898 to save compile time. */
24900 {
24916 /* Set decoder parameters. */
24921 }
24922 /* ... Fall through ... */
24932 }
24933 }
24935 \f
24936 /* Compute the alignment given to a constant that is being placed in memory.
24937 EXP is the constant and ALIGN is the alignment that the object would
24938 ordinarily have.
24939 The value of this function is used instead of that alignment to align
24940 the object. */
24942 int
24944 {
24947 {
24952 }
24958 }
24960 /* Compute the alignment for a static variable.
24961 TYPE is the data type, and ALIGN is the alignment that
24962 the object would ordinarily have. The value of this function is used
24963 instead of that alignment to align the object. */
24965 int
24967 {
24978 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
24979 to 16byte boundary. */
24981 {
24988 }
24991 {
24996 }
24998 {
25005 }
25010 {
25015 }
25018 {
25023 }
25026 }
25028 /* Compute the alignment for a local variable or a stack slot. EXP is
25029 the data type or decl itself, MODE is the widest mode available and
25030 ALIGN is the alignment that the object would ordinarily have. The
25031 value of this macro is used instead of that alignment to align the
25032 object. */
25034 unsigned int
25037 {
25041 {
25044 }
25045 else
25046 {
25049 }
25051 /* Don't do dynamic stack realignment for long long objects with
25052 -mpreferred-stack-boundary=2. */
25061 /* If TYPE is NULL, we are allocating a stack slot for caller-save
25062 register in MODE. We will return the largest alignment of XF
25063 and DF. */
25065 {
25069 }
25071 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25072 to 16byte boundary. Exact wording is:
25074 An array uses the same alignment as its elements, except that a local or
25075 global array variable of length at least 16 bytes or
25076 a C99 variable-length array variable always has alignment of at least 16 bytes.
25078 This was added to allow use of aligned SSE instructions at arrays. This
25079 rule is meant for static storage (where compiler can not do the analysis
25080 by itself). We follow it for automatic variables only when convenient.
25081 We fully control everything in the function compiled and functions from
25082 other unit can not rely on the alignment.
25084 Exclude va_list type. It is the common case of local array where
25085 we can not benefit from the alignment. */
25088 {
25098 }
25100 {
25105 }
25107 {
25113 }
25118 {
25123 }
25126 {
25132 }
25134 }
25136 /* Compute the minimum required alignment for dynamic stack realignment
25137 purposes for a local variable, parameter or a stack slot. EXP is
25138 the data type or decl itself, MODE is its mode and ALIGN is the
25139 alignment that the object would ordinarily have. */
25141 unsigned int
25144 {
25148 {
25151 }
25152 else
25153 {
25156 }
25161 /* Don't do dynamic stack realignment for long long objects with
25162 -mpreferred-stack-boundary=2. */
25169 }
25170 \f
25171 /* Find a location for the static chain incoming to a nested function.
25172 This is a register, unless all free registers are used by arguments. */
25174 static rtx
25176 {
25183 {
25184 /* We always use R10 in 64-bit mode. */
25186 }
25187 else
25188 {
25189 tree fntype;
25192 /* By default in 32-bit mode we use ECX to pass the static chain. */
25198 {
25199 /* Fastcall functions use ecx/edx for arguments, which leaves
25200 us with EAX for the static chain.
25201 Thiscall functions use ecx for arguments, which also
25202 leaves us with EAX for the static chain. */
25204 }
25206 {
25207 /* Thiscall functions use ecx for arguments, which leaves
25208 us with EAX and EDX for the static chain.
25209 We are using for abi-compatibility EAX. */
25211 }
25213 {
25214 /* For regparm 3, we have no free call-clobbered registers in
25215 which to store the static chain. In order to implement this,
25216 we have the trampoline push the static chain to the stack.
25217 However, we can't push a value below the return address when
25218 we call the nested function directly, so we have to use an
25219 alternate entry point. For this we use ESI, and have the
25220 alternate entry point push ESI, so that things appear the
25221 same once we're executing the nested function. */
25223 {
25229 }
25231 }
25232 }
25235 }
25237 /* Emit RTL insns to initialize the variable parts of a trampoline.
25238 FNDECL is the decl of the target address; M_TRAMP is a MEM for
25239 the trampoline, and CHAIN_VALUE is an RTX for the static chain
25240 to be passed to the target function. */
25242 static void
25244 {
25252 {
25255 /* Load the function address to r11. Try to load address using
25256 the shorter movl instead of movabs. We may want to support
25257 movq for kernel mode, but kernel does not use trampolines at
25258 the moment. FNADDR is a 32bit address and may not be in
25259 DImode when ptr_mode == SImode. Always use movl in this
25260 case. */
25263 {
25272 }
25273 else
25274 {
25281 }
25283 /* Load static chain using movabs to r10. Use the shorter movl
25284 instead of movabs when ptr_mode == SImode. */
25286 {
25289 }
25290 else
25291 {
25294 }
25303 /* Jump to r11; the last (unused) byte is a nop, only there to
25304 pad the write out to a single 32-bit store. */
25308 }
25309 else
25310 {
25313 /* Depending on the static chain location, either load a register
25314 with a constant, or push the constant to the stack. All of the
25315 instructions are the same size. */
25318 {
25320 {
25327 }
25328 }
25329 else
25344 /* Compute offset from the end of the jmp to the target function.
25345 In the case in which the trampoline stores the static chain on
25346 the stack, we need to skip the first insn which pushes the
25347 (call-saved) register static chain; this push is 1 byte. */
25354 }
25358 #ifdef HAVE_ENABLE_EXECUTE_STACK
25359 #ifdef CHECK_EXECUTE_STACK_ENABLED
25361 #endif
25364 #endif
25365 }
25366 \f
25367 /* The following file contains several enumerations and data structures
25368 built from the definitions in i386-builtin-types.def. */
25372 /* Table for the ix86 builtin non-function types. */
25375 /* Retrieve an element from the above table, building some of
25376 the types lazily. */
25378 static tree
25380 {
25392 {
25400 }
25401 else
25402 {
25408 else
25416 }
25420 }
25422 /* Table for the ix86 builtin function types. */
25425 /* Retrieve an element from the above table, building some of
25426 the types lazily. */
25428 static tree
25430 {
25431 tree type;
25440 {
25448 {
25451 }
25454 }
25455 else
25456 {
25462 }
25466 }
25469 /* Codes for all the SSE/MMX builtins. */
25470 enum ix86_builtins
25471 {
25472 IX86_BUILTIN_ADDPS,
25473 IX86_BUILTIN_ADDSS,
25474 IX86_BUILTIN_DIVPS,
25475 IX86_BUILTIN_DIVSS,
25476 IX86_BUILTIN_MULPS,
25477 IX86_BUILTIN_MULSS,
25478 IX86_BUILTIN_SUBPS,
25479 IX86_BUILTIN_SUBSS,
25481 IX86_BUILTIN_CMPEQPS,
25482 IX86_BUILTIN_CMPLTPS,
25483 IX86_BUILTIN_CMPLEPS,
25484 IX86_BUILTIN_CMPGTPS,
25485 IX86_BUILTIN_CMPGEPS,
25486 IX86_BUILTIN_CMPNEQPS,
25487 IX86_BUILTIN_CMPNLTPS,
25488 IX86_BUILTIN_CMPNLEPS,
25489 IX86_BUILTIN_CMPNGTPS,
25490 IX86_BUILTIN_CMPNGEPS,
25491 IX86_BUILTIN_CMPORDPS,
25492 IX86_BUILTIN_CMPUNORDPS,
25493 IX86_BUILTIN_CMPEQSS,
25494 IX86_BUILTIN_CMPLTSS,
25495 IX86_BUILTIN_CMPLESS,
25496 IX86_BUILTIN_CMPNEQSS,
25497 IX86_BUILTIN_CMPNLTSS,
25498 IX86_BUILTIN_CMPNLESS,
25499 IX86_BUILTIN_CMPNGTSS,
25500 IX86_BUILTIN_CMPNGESS,
25501 IX86_BUILTIN_CMPORDSS,
25502 IX86_BUILTIN_CMPUNORDSS,
25504 IX86_BUILTIN_COMIEQSS,
25505 IX86_BUILTIN_COMILTSS,
25506 IX86_BUILTIN_COMILESS,
25507 IX86_BUILTIN_COMIGTSS,
25508 IX86_BUILTIN_COMIGESS,
25509 IX86_BUILTIN_COMINEQSS,
25510 IX86_BUILTIN_UCOMIEQSS,
25511 IX86_BUILTIN_UCOMILTSS,
25512 IX86_BUILTIN_UCOMILESS,
25513 IX86_BUILTIN_UCOMIGTSS,
25514 IX86_BUILTIN_UCOMIGESS,
25515 IX86_BUILTIN_UCOMINEQSS,
25517 IX86_BUILTIN_CVTPI2PS,
25518 IX86_BUILTIN_CVTPS2PI,
25519 IX86_BUILTIN_CVTSI2SS,
25520 IX86_BUILTIN_CVTSI642SS,
25521 IX86_BUILTIN_CVTSS2SI,
25522 IX86_BUILTIN_CVTSS2SI64,
25523 IX86_BUILTIN_CVTTPS2PI,
25524 IX86_BUILTIN_CVTTSS2SI,
25525 IX86_BUILTIN_CVTTSS2SI64,
25527 IX86_BUILTIN_MAXPS,
25528 IX86_BUILTIN_MAXSS,
25529 IX86_BUILTIN_MINPS,
25530 IX86_BUILTIN_MINSS,
25532 IX86_BUILTIN_LOADUPS,
25533 IX86_BUILTIN_STOREUPS,
25534 IX86_BUILTIN_MOVSS,
25536 IX86_BUILTIN_MOVHLPS,
25537 IX86_BUILTIN_MOVLHPS,
25538 IX86_BUILTIN_LOADHPS,
25539 IX86_BUILTIN_LOADLPS,
25540 IX86_BUILTIN_STOREHPS,
25541 IX86_BUILTIN_STORELPS,
25543 IX86_BUILTIN_MASKMOVQ,
25544 IX86_BUILTIN_MOVMSKPS,
25545 IX86_BUILTIN_PMOVMSKB,
25547 IX86_BUILTIN_MOVNTPS,
25548 IX86_BUILTIN_MOVNTQ,
25550 IX86_BUILTIN_LOADDQU,
25551 IX86_BUILTIN_STOREDQU,
25553 IX86_BUILTIN_PACKSSWB,
25554 IX86_BUILTIN_PACKSSDW,
25555 IX86_BUILTIN_PACKUSWB,
25557 IX86_BUILTIN_PADDB,
25558 IX86_BUILTIN_PADDW,
25559 IX86_BUILTIN_PADDD,
25560 IX86_BUILTIN_PADDQ,
25561 IX86_BUILTIN_PADDSB,
25562 IX86_BUILTIN_PADDSW,
25563 IX86_BUILTIN_PADDUSB,
25564 IX86_BUILTIN_PADDUSW,
25565 IX86_BUILTIN_PSUBB,
25566 IX86_BUILTIN_PSUBW,
25567 IX86_BUILTIN_PSUBD,
25568 IX86_BUILTIN_PSUBQ,
25569 IX86_BUILTIN_PSUBSB,
25570 IX86_BUILTIN_PSUBSW,
25571 IX86_BUILTIN_PSUBUSB,
25572 IX86_BUILTIN_PSUBUSW,
25574 IX86_BUILTIN_PAND,
25575 IX86_BUILTIN_PANDN,
25576 IX86_BUILTIN_POR,
25577 IX86_BUILTIN_PXOR,
25579 IX86_BUILTIN_PAVGB,
25580 IX86_BUILTIN_PAVGW,
25582 IX86_BUILTIN_PCMPEQB,
25583 IX86_BUILTIN_PCMPEQW,
25584 IX86_BUILTIN_PCMPEQD,
25585 IX86_BUILTIN_PCMPGTB,
25586 IX86_BUILTIN_PCMPGTW,
25587 IX86_BUILTIN_PCMPGTD,
25589 IX86_BUILTIN_PMADDWD,
25591 IX86_BUILTIN_PMAXSW,
25592 IX86_BUILTIN_PMAXUB,
25593 IX86_BUILTIN_PMINSW,
25594 IX86_BUILTIN_PMINUB,
25596 IX86_BUILTIN_PMULHUW,
25597 IX86_BUILTIN_PMULHW,
25598 IX86_BUILTIN_PMULLW,
25600 IX86_BUILTIN_PSADBW,
25601 IX86_BUILTIN_PSHUFW,
25603 IX86_BUILTIN_PSLLW,
25604 IX86_BUILTIN_PSLLD,
25605 IX86_BUILTIN_PSLLQ,
25606 IX86_BUILTIN_PSRAW,
25607 IX86_BUILTIN_PSRAD,
25608 IX86_BUILTIN_PSRLW,
25609 IX86_BUILTIN_PSRLD,
25610 IX86_BUILTIN_PSRLQ,
25611 IX86_BUILTIN_PSLLWI,
25612 IX86_BUILTIN_PSLLDI,
25613 IX86_BUILTIN_PSLLQI,
25614 IX86_BUILTIN_PSRAWI,
25615 IX86_BUILTIN_PSRADI,
25616 IX86_BUILTIN_PSRLWI,
25617 IX86_BUILTIN_PSRLDI,
25618 IX86_BUILTIN_PSRLQI,
25620 IX86_BUILTIN_PUNPCKHBW,
25621 IX86_BUILTIN_PUNPCKHWD,
25622 IX86_BUILTIN_PUNPCKHDQ,
25623 IX86_BUILTIN_PUNPCKLBW,
25624 IX86_BUILTIN_PUNPCKLWD,
25625 IX86_BUILTIN_PUNPCKLDQ,
25627 IX86_BUILTIN_SHUFPS,
25629 IX86_BUILTIN_RCPPS,
25630 IX86_BUILTIN_RCPSS,
25631 IX86_BUILTIN_RSQRTPS,
25632 IX86_BUILTIN_RSQRTPS_NR,
25633 IX86_BUILTIN_RSQRTSS,
25634 IX86_BUILTIN_RSQRTF,
25635 IX86_BUILTIN_SQRTPS,
25636 IX86_BUILTIN_SQRTPS_NR,
25637 IX86_BUILTIN_SQRTSS,
25639 IX86_BUILTIN_UNPCKHPS,
25640 IX86_BUILTIN_UNPCKLPS,
25642 IX86_BUILTIN_ANDPS,
25643 IX86_BUILTIN_ANDNPS,
25644 IX86_BUILTIN_ORPS,
25645 IX86_BUILTIN_XORPS,
25647 IX86_BUILTIN_EMMS,
25648 IX86_BUILTIN_LDMXCSR,
25649 IX86_BUILTIN_STMXCSR,
25650 IX86_BUILTIN_SFENCE,
25652 IX86_BUILTIN_FXSAVE,
25653 IX86_BUILTIN_FXRSTOR,
25654 IX86_BUILTIN_FXSAVE64,
25655 IX86_BUILTIN_FXRSTOR64,
25657 IX86_BUILTIN_XSAVE,
25658 IX86_BUILTIN_XRSTOR,
25659 IX86_BUILTIN_XSAVE64,
25660 IX86_BUILTIN_XRSTOR64,
25662 IX86_BUILTIN_XSAVEOPT,
25663 IX86_BUILTIN_XSAVEOPT64,
25665 /* 3DNow! Original */
25666 IX86_BUILTIN_FEMMS,
25667 IX86_BUILTIN_PAVGUSB,
25668 IX86_BUILTIN_PF2ID,
25669 IX86_BUILTIN_PFACC,
25670 IX86_BUILTIN_PFADD,
25671 IX86_BUILTIN_PFCMPEQ,
25672 IX86_BUILTIN_PFCMPGE,
25673 IX86_BUILTIN_PFCMPGT,
25674 IX86_BUILTIN_PFMAX,
25675 IX86_BUILTIN_PFMIN,
25676 IX86_BUILTIN_PFMUL,
25677 IX86_BUILTIN_PFRCP,
25678 IX86_BUILTIN_PFRCPIT1,
25679 IX86_BUILTIN_PFRCPIT2,
25680 IX86_BUILTIN_PFRSQIT1,
25681 IX86_BUILTIN_PFRSQRT,
25682 IX86_BUILTIN_PFSUB,
25683 IX86_BUILTIN_PFSUBR,
25684 IX86_BUILTIN_PI2FD,
25685 IX86_BUILTIN_PMULHRW,
25687 /* 3DNow! Athlon Extensions */
25688 IX86_BUILTIN_PF2IW,
25689 IX86_BUILTIN_PFNACC,
25690 IX86_BUILTIN_PFPNACC,
25691 IX86_BUILTIN_PI2FW,
25692 IX86_BUILTIN_PSWAPDSI,
25693 IX86_BUILTIN_PSWAPDSF,
25695 /* SSE2 */
25696 IX86_BUILTIN_ADDPD,
25697 IX86_BUILTIN_ADDSD,
25698 IX86_BUILTIN_DIVPD,
25699 IX86_BUILTIN_DIVSD,
25700 IX86_BUILTIN_MULPD,
25701 IX86_BUILTIN_MULSD,
25702 IX86_BUILTIN_SUBPD,
25703 IX86_BUILTIN_SUBSD,
25705 IX86_BUILTIN_CMPEQPD,
25706 IX86_BUILTIN_CMPLTPD,
25707 IX86_BUILTIN_CMPLEPD,
25708 IX86_BUILTIN_CMPGTPD,
25709 IX86_BUILTIN_CMPGEPD,
25710 IX86_BUILTIN_CMPNEQPD,
25711 IX86_BUILTIN_CMPNLTPD,
25712 IX86_BUILTIN_CMPNLEPD,
25713 IX86_BUILTIN_CMPNGTPD,
25714 IX86_BUILTIN_CMPNGEPD,
25715 IX86_BUILTIN_CMPORDPD,
25716 IX86_BUILTIN_CMPUNORDPD,
25717 IX86_BUILTIN_CMPEQSD,
25718 IX86_BUILTIN_CMPLTSD,
25719 IX86_BUILTIN_CMPLESD,
25720 IX86_BUILTIN_CMPNEQSD,
25721 IX86_BUILTIN_CMPNLTSD,
25722 IX86_BUILTIN_CMPNLESD,
25723 IX86_BUILTIN_CMPORDSD,
25724 IX86_BUILTIN_CMPUNORDSD,
25726 IX86_BUILTIN_COMIEQSD,
25727 IX86_BUILTIN_COMILTSD,
25728 IX86_BUILTIN_COMILESD,
25729 IX86_BUILTIN_COMIGTSD,
25730 IX86_BUILTIN_COMIGESD,
25731 IX86_BUILTIN_COMINEQSD,
25732 IX86_BUILTIN_UCOMIEQSD,
25733 IX86_BUILTIN_UCOMILTSD,
25734 IX86_BUILTIN_UCOMILESD,
25735 IX86_BUILTIN_UCOMIGTSD,
25736 IX86_BUILTIN_UCOMIGESD,
25737 IX86_BUILTIN_UCOMINEQSD,
25739 IX86_BUILTIN_MAXPD,
25740 IX86_BUILTIN_MAXSD,
25741 IX86_BUILTIN_MINPD,
25742 IX86_BUILTIN_MINSD,
25744 IX86_BUILTIN_ANDPD,
25745 IX86_BUILTIN_ANDNPD,
25746 IX86_BUILTIN_ORPD,
25747 IX86_BUILTIN_XORPD,
25749 IX86_BUILTIN_SQRTPD,
25750 IX86_BUILTIN_SQRTSD,
25752 IX86_BUILTIN_UNPCKHPD,
25753 IX86_BUILTIN_UNPCKLPD,
25755 IX86_BUILTIN_SHUFPD,
25757 IX86_BUILTIN_LOADUPD,
25758 IX86_BUILTIN_STOREUPD,
25759 IX86_BUILTIN_MOVSD,
25761 IX86_BUILTIN_LOADHPD,
25762 IX86_BUILTIN_LOADLPD,
25764 IX86_BUILTIN_CVTDQ2PD,
25765 IX86_BUILTIN_CVTDQ2PS,
25767 IX86_BUILTIN_CVTPD2DQ,
25768 IX86_BUILTIN_CVTPD2PI,
25769 IX86_BUILTIN_CVTPD2PS,
25770 IX86_BUILTIN_CVTTPD2DQ,
25771 IX86_BUILTIN_CVTTPD2PI,
25773 IX86_BUILTIN_CVTPI2PD,
25774 IX86_BUILTIN_CVTSI2SD,
25775 IX86_BUILTIN_CVTSI642SD,
25777 IX86_BUILTIN_CVTSD2SI,
25778 IX86_BUILTIN_CVTSD2SI64,
25779 IX86_BUILTIN_CVTSD2SS,
25780 IX86_BUILTIN_CVTSS2SD,
25781 IX86_BUILTIN_CVTTSD2SI,
25782 IX86_BUILTIN_CVTTSD2SI64,
25784 IX86_BUILTIN_CVTPS2DQ,
25785 IX86_BUILTIN_CVTPS2PD,
25786 IX86_BUILTIN_CVTTPS2DQ,
25788 IX86_BUILTIN_MOVNTI,
25789 IX86_BUILTIN_MOVNTI64,
25790 IX86_BUILTIN_MOVNTPD,
25791 IX86_BUILTIN_MOVNTDQ,
25793 IX86_BUILTIN_MOVQ128,
25795 /* SSE2 MMX */
25796 IX86_BUILTIN_MASKMOVDQU,
25797 IX86_BUILTIN_MOVMSKPD,
25798 IX86_BUILTIN_PMOVMSKB128,
25800 IX86_BUILTIN_PACKSSWB128,
25801 IX86_BUILTIN_PACKSSDW128,
25802 IX86_BUILTIN_PACKUSWB128,
25804 IX86_BUILTIN_PADDB128,
25805 IX86_BUILTIN_PADDW128,
25806 IX86_BUILTIN_PADDD128,
25807 IX86_BUILTIN_PADDQ128,
25808 IX86_BUILTIN_PADDSB128,
25809 IX86_BUILTIN_PADDSW128,
25810 IX86_BUILTIN_PADDUSB128,
25811 IX86_BUILTIN_PADDUSW128,
25812 IX86_BUILTIN_PSUBB128,
25813 IX86_BUILTIN_PSUBW128,
25814 IX86_BUILTIN_PSUBD128,
25815 IX86_BUILTIN_PSUBQ128,
25816 IX86_BUILTIN_PSUBSB128,
25817 IX86_BUILTIN_PSUBSW128,
25818 IX86_BUILTIN_PSUBUSB128,
25819 IX86_BUILTIN_PSUBUSW128,
25821 IX86_BUILTIN_PAND128,
25822 IX86_BUILTIN_PANDN128,
25823 IX86_BUILTIN_POR128,
25824 IX86_BUILTIN_PXOR128,
25826 IX86_BUILTIN_PAVGB128,
25827 IX86_BUILTIN_PAVGW128,
25829 IX86_BUILTIN_PCMPEQB128,
25830 IX86_BUILTIN_PCMPEQW128,
25831 IX86_BUILTIN_PCMPEQD128,
25832 IX86_BUILTIN_PCMPGTB128,
25833 IX86_BUILTIN_PCMPGTW128,
25834 IX86_BUILTIN_PCMPGTD128,
25836 IX86_BUILTIN_PMADDWD128,
25838 IX86_BUILTIN_PMAXSW128,
25839 IX86_BUILTIN_PMAXUB128,
25840 IX86_BUILTIN_PMINSW128,
25841 IX86_BUILTIN_PMINUB128,
25843 IX86_BUILTIN_PMULUDQ,
25844 IX86_BUILTIN_PMULUDQ128,
25845 IX86_BUILTIN_PMULHUW128,
25846 IX86_BUILTIN_PMULHW128,
25847 IX86_BUILTIN_PMULLW128,
25849 IX86_BUILTIN_PSADBW128,
25850 IX86_BUILTIN_PSHUFHW,
25851 IX86_BUILTIN_PSHUFLW,
25852 IX86_BUILTIN_PSHUFD,
25854 IX86_BUILTIN_PSLLDQI128,
25855 IX86_BUILTIN_PSLLWI128,
25856 IX86_BUILTIN_PSLLDI128,
25857 IX86_BUILTIN_PSLLQI128,
25858 IX86_BUILTIN_PSRAWI128,
25859 IX86_BUILTIN_PSRADI128,
25860 IX86_BUILTIN_PSRLDQI128,
25861 IX86_BUILTIN_PSRLWI128,
25862 IX86_BUILTIN_PSRLDI128,
25863 IX86_BUILTIN_PSRLQI128,
25865 IX86_BUILTIN_PSLLDQ128,
25866 IX86_BUILTIN_PSLLW128,
25867 IX86_BUILTIN_PSLLD128,
25868 IX86_BUILTIN_PSLLQ128,
25869 IX86_BUILTIN_PSRAW128,
25870 IX86_BUILTIN_PSRAD128,
25871 IX86_BUILTIN_PSRLW128,
25872 IX86_BUILTIN_PSRLD128,
25873 IX86_BUILTIN_PSRLQ128,
25875 IX86_BUILTIN_PUNPCKHBW128,
25876 IX86_BUILTIN_PUNPCKHWD128,
25877 IX86_BUILTIN_PUNPCKHDQ128,
25878 IX86_BUILTIN_PUNPCKHQDQ128,
25879 IX86_BUILTIN_PUNPCKLBW128,
25880 IX86_BUILTIN_PUNPCKLWD128,
25881 IX86_BUILTIN_PUNPCKLDQ128,
25882 IX86_BUILTIN_PUNPCKLQDQ128,
25884 IX86_BUILTIN_CLFLUSH,
25885 IX86_BUILTIN_MFENCE,
25886 IX86_BUILTIN_LFENCE,
25887 IX86_BUILTIN_PAUSE,
25889 IX86_BUILTIN_BSRSI,
25890 IX86_BUILTIN_BSRDI,
25891 IX86_BUILTIN_RDPMC,
25892 IX86_BUILTIN_RDTSC,
25893 IX86_BUILTIN_RDTSCP,
25894 IX86_BUILTIN_ROLQI,
25895 IX86_BUILTIN_ROLHI,
25896 IX86_BUILTIN_RORQI,
25897 IX86_BUILTIN_RORHI,
25899 /* SSE3. */
25900 IX86_BUILTIN_ADDSUBPS,
25901 IX86_BUILTIN_HADDPS,
25902 IX86_BUILTIN_HSUBPS,
25903 IX86_BUILTIN_MOVSHDUP,
25904 IX86_BUILTIN_MOVSLDUP,
25905 IX86_BUILTIN_ADDSUBPD,
25906 IX86_BUILTIN_HADDPD,
25907 IX86_BUILTIN_HSUBPD,
25908 IX86_BUILTIN_LDDQU,
25910 IX86_BUILTIN_MONITOR,
25911 IX86_BUILTIN_MWAIT,
25913 /* SSSE3. */
25914 IX86_BUILTIN_PHADDW,
25915 IX86_BUILTIN_PHADDD,
25916 IX86_BUILTIN_PHADDSW,
25917 IX86_BUILTIN_PHSUBW,
25918 IX86_BUILTIN_PHSUBD,
25919 IX86_BUILTIN_PHSUBSW,
25920 IX86_BUILTIN_PMADDUBSW,
25921 IX86_BUILTIN_PMULHRSW,
25922 IX86_BUILTIN_PSHUFB,
25923 IX86_BUILTIN_PSIGNB,
25924 IX86_BUILTIN_PSIGNW,
25925 IX86_BUILTIN_PSIGND,
25926 IX86_BUILTIN_PALIGNR,
25927 IX86_BUILTIN_PABSB,
25928 IX86_BUILTIN_PABSW,
25929 IX86_BUILTIN_PABSD,
25931 IX86_BUILTIN_PHADDW128,
25932 IX86_BUILTIN_PHADDD128,
25933 IX86_BUILTIN_PHADDSW128,
25934 IX86_BUILTIN_PHSUBW128,
25935 IX86_BUILTIN_PHSUBD128,
25936 IX86_BUILTIN_PHSUBSW128,
25937 IX86_BUILTIN_PMADDUBSW128,
25938 IX86_BUILTIN_PMULHRSW128,
25939 IX86_BUILTIN_PSHUFB128,
25940 IX86_BUILTIN_PSIGNB128,
25941 IX86_BUILTIN_PSIGNW128,
25942 IX86_BUILTIN_PSIGND128,
25943 IX86_BUILTIN_PALIGNR128,
25944 IX86_BUILTIN_PABSB128,
25945 IX86_BUILTIN_PABSW128,
25946 IX86_BUILTIN_PABSD128,
25948 /* AMDFAM10 - SSE4A New Instructions. */
25949 IX86_BUILTIN_MOVNTSD,
25950 IX86_BUILTIN_MOVNTSS,
25951 IX86_BUILTIN_EXTRQI,
25952 IX86_BUILTIN_EXTRQ,
25953 IX86_BUILTIN_INSERTQI,
25954 IX86_BUILTIN_INSERTQ,
25956 /* SSE4.1. */
25957 IX86_BUILTIN_BLENDPD,
25958 IX86_BUILTIN_BLENDPS,
25959 IX86_BUILTIN_BLENDVPD,
25960 IX86_BUILTIN_BLENDVPS,
25961 IX86_BUILTIN_PBLENDVB128,
25962 IX86_BUILTIN_PBLENDW128,
25964 IX86_BUILTIN_DPPD,
25965 IX86_BUILTIN_DPPS,
25967 IX86_BUILTIN_INSERTPS128,
25969 IX86_BUILTIN_MOVNTDQA,
25970 IX86_BUILTIN_MPSADBW128,
25971 IX86_BUILTIN_PACKUSDW128,
25972 IX86_BUILTIN_PCMPEQQ,
25973 IX86_BUILTIN_PHMINPOSUW128,
25975 IX86_BUILTIN_PMAXSB128,
25976 IX86_BUILTIN_PMAXSD128,
25977 IX86_BUILTIN_PMAXUD128,
25978 IX86_BUILTIN_PMAXUW128,
25980 IX86_BUILTIN_PMINSB128,
25981 IX86_BUILTIN_PMINSD128,
25982 IX86_BUILTIN_PMINUD128,
25983 IX86_BUILTIN_PMINUW128,
25985 IX86_BUILTIN_PMOVSXBW128,
25986 IX86_BUILTIN_PMOVSXBD128,
25987 IX86_BUILTIN_PMOVSXBQ128,
25988 IX86_BUILTIN_PMOVSXWD128,
25989 IX86_BUILTIN_PMOVSXWQ128,
25990 IX86_BUILTIN_PMOVSXDQ128,
25992 IX86_BUILTIN_PMOVZXBW128,
25993 IX86_BUILTIN_PMOVZXBD128,
25994 IX86_BUILTIN_PMOVZXBQ128,
25995 IX86_BUILTIN_PMOVZXWD128,
25996 IX86_BUILTIN_PMOVZXWQ128,
25997 IX86_BUILTIN_PMOVZXDQ128,
25999 IX86_BUILTIN_PMULDQ128,
26000 IX86_BUILTIN_PMULLD128,
26002 IX86_BUILTIN_ROUNDSD,
26003 IX86_BUILTIN_ROUNDSS,
26005 IX86_BUILTIN_ROUNDPD,
26006 IX86_BUILTIN_ROUNDPS,
26008 IX86_BUILTIN_FLOORPD,
26009 IX86_BUILTIN_CEILPD,
26010 IX86_BUILTIN_TRUNCPD,
26011 IX86_BUILTIN_RINTPD,
26012 IX86_BUILTIN_ROUNDPD_AZ,
26014 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
26015 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
26016 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
26018 IX86_BUILTIN_FLOORPS,
26019 IX86_BUILTIN_CEILPS,
26020 IX86_BUILTIN_TRUNCPS,
26021 IX86_BUILTIN_RINTPS,
26022 IX86_BUILTIN_ROUNDPS_AZ,
26024 IX86_BUILTIN_FLOORPS_SFIX,
26025 IX86_BUILTIN_CEILPS_SFIX,
26026 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
26028 IX86_BUILTIN_PTESTZ,
26029 IX86_BUILTIN_PTESTC,
26030 IX86_BUILTIN_PTESTNZC,
26032 IX86_BUILTIN_VEC_INIT_V2SI,
26033 IX86_BUILTIN_VEC_INIT_V4HI,
26034 IX86_BUILTIN_VEC_INIT_V8QI,
26035 IX86_BUILTIN_VEC_EXT_V2DF,
26036 IX86_BUILTIN_VEC_EXT_V2DI,
26037 IX86_BUILTIN_VEC_EXT_V4SF,
26038 IX86_BUILTIN_VEC_EXT_V4SI,
26039 IX86_BUILTIN_VEC_EXT_V8HI,
26040 IX86_BUILTIN_VEC_EXT_V2SI,
26041 IX86_BUILTIN_VEC_EXT_V4HI,
26042 IX86_BUILTIN_VEC_EXT_V16QI,
26043 IX86_BUILTIN_VEC_SET_V2DI,
26044 IX86_BUILTIN_VEC_SET_V4SF,
26045 IX86_BUILTIN_VEC_SET_V4SI,
26046 IX86_BUILTIN_VEC_SET_V8HI,
26047 IX86_BUILTIN_VEC_SET_V4HI,
26048 IX86_BUILTIN_VEC_SET_V16QI,
26050 IX86_BUILTIN_VEC_PACK_SFIX,
26051 IX86_BUILTIN_VEC_PACK_SFIX256,
26053 /* SSE4.2. */
26054 IX86_BUILTIN_CRC32QI,
26055 IX86_BUILTIN_CRC32HI,
26056 IX86_BUILTIN_CRC32SI,
26057 IX86_BUILTIN_CRC32DI,
26059 IX86_BUILTIN_PCMPESTRI128,
26060 IX86_BUILTIN_PCMPESTRM128,
26061 IX86_BUILTIN_PCMPESTRA128,
26062 IX86_BUILTIN_PCMPESTRC128,
26063 IX86_BUILTIN_PCMPESTRO128,
26064 IX86_BUILTIN_PCMPESTRS128,
26065 IX86_BUILTIN_PCMPESTRZ128,
26066 IX86_BUILTIN_PCMPISTRI128,
26067 IX86_BUILTIN_PCMPISTRM128,
26068 IX86_BUILTIN_PCMPISTRA128,
26069 IX86_BUILTIN_PCMPISTRC128,
26070 IX86_BUILTIN_PCMPISTRO128,
26071 IX86_BUILTIN_PCMPISTRS128,
26072 IX86_BUILTIN_PCMPISTRZ128,
26074 IX86_BUILTIN_PCMPGTQ,
26076 /* AES instructions */
26077 IX86_BUILTIN_AESENC128,
26078 IX86_BUILTIN_AESENCLAST128,
26079 IX86_BUILTIN_AESDEC128,
26080 IX86_BUILTIN_AESDECLAST128,
26081 IX86_BUILTIN_AESIMC128,
26082 IX86_BUILTIN_AESKEYGENASSIST128,
26084 /* PCLMUL instruction */
26085 IX86_BUILTIN_PCLMULQDQ128,
26087 /* AVX */
26088 IX86_BUILTIN_ADDPD256,
26089 IX86_BUILTIN_ADDPS256,
26090 IX86_BUILTIN_ADDSUBPD256,
26091 IX86_BUILTIN_ADDSUBPS256,
26092 IX86_BUILTIN_ANDPD256,
26093 IX86_BUILTIN_ANDPS256,
26094 IX86_BUILTIN_ANDNPD256,
26095 IX86_BUILTIN_ANDNPS256,
26096 IX86_BUILTIN_BLENDPD256,
26097 IX86_BUILTIN_BLENDPS256,
26098 IX86_BUILTIN_BLENDVPD256,
26099 IX86_BUILTIN_BLENDVPS256,
26100 IX86_BUILTIN_DIVPD256,
26101 IX86_BUILTIN_DIVPS256,
26102 IX86_BUILTIN_DPPS256,
26103 IX86_BUILTIN_HADDPD256,
26104 IX86_BUILTIN_HADDPS256,
26105 IX86_BUILTIN_HSUBPD256,
26106 IX86_BUILTIN_HSUBPS256,
26107 IX86_BUILTIN_MAXPD256,
26108 IX86_BUILTIN_MAXPS256,
26109 IX86_BUILTIN_MINPD256,
26110 IX86_BUILTIN_MINPS256,
26111 IX86_BUILTIN_MULPD256,
26112 IX86_BUILTIN_MULPS256,
26113 IX86_BUILTIN_ORPD256,
26114 IX86_BUILTIN_ORPS256,
26115 IX86_BUILTIN_SHUFPD256,
26116 IX86_BUILTIN_SHUFPS256,
26117 IX86_BUILTIN_SUBPD256,
26118 IX86_BUILTIN_SUBPS256,
26119 IX86_BUILTIN_XORPD256,
26120 IX86_BUILTIN_XORPS256,
26121 IX86_BUILTIN_CMPSD,
26122 IX86_BUILTIN_CMPSS,
26123 IX86_BUILTIN_CMPPD,
26124 IX86_BUILTIN_CMPPS,
26125 IX86_BUILTIN_CMPPD256,
26126 IX86_BUILTIN_CMPPS256,
26127 IX86_BUILTIN_CVTDQ2PD256,
26128 IX86_BUILTIN_CVTDQ2PS256,
26129 IX86_BUILTIN_CVTPD2PS256,
26130 IX86_BUILTIN_CVTPS2DQ256,
26131 IX86_BUILTIN_CVTPS2PD256,
26132 IX86_BUILTIN_CVTTPD2DQ256,
26133 IX86_BUILTIN_CVTPD2DQ256,
26134 IX86_BUILTIN_CVTTPS2DQ256,
26135 IX86_BUILTIN_EXTRACTF128PD256,
26136 IX86_BUILTIN_EXTRACTF128PS256,
26137 IX86_BUILTIN_EXTRACTF128SI256,
26138 IX86_BUILTIN_VZEROALL,
26139 IX86_BUILTIN_VZEROUPPER,
26140 IX86_BUILTIN_VPERMILVARPD,
26141 IX86_BUILTIN_VPERMILVARPS,
26142 IX86_BUILTIN_VPERMILVARPD256,
26143 IX86_BUILTIN_VPERMILVARPS256,
26144 IX86_BUILTIN_VPERMILPD,
26145 IX86_BUILTIN_VPERMILPS,
26146 IX86_BUILTIN_VPERMILPD256,
26147 IX86_BUILTIN_VPERMILPS256,
26148 IX86_BUILTIN_VPERMIL2PD,
26149 IX86_BUILTIN_VPERMIL2PS,
26150 IX86_BUILTIN_VPERMIL2PD256,
26151 IX86_BUILTIN_VPERMIL2PS256,
26152 IX86_BUILTIN_VPERM2F128PD256,
26153 IX86_BUILTIN_VPERM2F128PS256,
26154 IX86_BUILTIN_VPERM2F128SI256,
26155 IX86_BUILTIN_VBROADCASTSS,
26156 IX86_BUILTIN_VBROADCASTSD256,
26157 IX86_BUILTIN_VBROADCASTSS256,
26158 IX86_BUILTIN_VBROADCASTPD256,
26159 IX86_BUILTIN_VBROADCASTPS256,
26160 IX86_BUILTIN_VINSERTF128PD256,
26161 IX86_BUILTIN_VINSERTF128PS256,
26162 IX86_BUILTIN_VINSERTF128SI256,
26163 IX86_BUILTIN_LOADUPD256,
26164 IX86_BUILTIN_LOADUPS256,
26165 IX86_BUILTIN_STOREUPD256,
26166 IX86_BUILTIN_STOREUPS256,
26167 IX86_BUILTIN_LDDQU256,
26168 IX86_BUILTIN_MOVNTDQ256,
26169 IX86_BUILTIN_MOVNTPD256,
26170 IX86_BUILTIN_MOVNTPS256,
26171 IX86_BUILTIN_LOADDQU256,
26172 IX86_BUILTIN_STOREDQU256,
26173 IX86_BUILTIN_MASKLOADPD,
26174 IX86_BUILTIN_MASKLOADPS,
26175 IX86_BUILTIN_MASKSTOREPD,
26176 IX86_BUILTIN_MASKSTOREPS,
26177 IX86_BUILTIN_MASKLOADPD256,
26178 IX86_BUILTIN_MASKLOADPS256,
26179 IX86_BUILTIN_MASKSTOREPD256,
26180 IX86_BUILTIN_MASKSTOREPS256,
26181 IX86_BUILTIN_MOVSHDUP256,
26182 IX86_BUILTIN_MOVSLDUP256,
26183 IX86_BUILTIN_MOVDDUP256,
26185 IX86_BUILTIN_SQRTPD256,
26186 IX86_BUILTIN_SQRTPS256,
26187 IX86_BUILTIN_SQRTPS_NR256,
26188 IX86_BUILTIN_RSQRTPS256,
26189 IX86_BUILTIN_RSQRTPS_NR256,
26191 IX86_BUILTIN_RCPPS256,
26193 IX86_BUILTIN_ROUNDPD256,
26194 IX86_BUILTIN_ROUNDPS256,
26196 IX86_BUILTIN_FLOORPD256,
26197 IX86_BUILTIN_CEILPD256,
26198 IX86_BUILTIN_TRUNCPD256,
26199 IX86_BUILTIN_RINTPD256,
26200 IX86_BUILTIN_ROUNDPD_AZ256,
26202 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
26203 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
26204 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
26206 IX86_BUILTIN_FLOORPS256,
26207 IX86_BUILTIN_CEILPS256,
26208 IX86_BUILTIN_TRUNCPS256,
26209 IX86_BUILTIN_RINTPS256,
26210 IX86_BUILTIN_ROUNDPS_AZ256,
26212 IX86_BUILTIN_FLOORPS_SFIX256,
26213 IX86_BUILTIN_CEILPS_SFIX256,
26214 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
26216 IX86_BUILTIN_UNPCKHPD256,
26217 IX86_BUILTIN_UNPCKLPD256,
26218 IX86_BUILTIN_UNPCKHPS256,
26219 IX86_BUILTIN_UNPCKLPS256,
26221 IX86_BUILTIN_SI256_SI,
26222 IX86_BUILTIN_PS256_PS,
26223 IX86_BUILTIN_PD256_PD,
26224 IX86_BUILTIN_SI_SI256,
26225 IX86_BUILTIN_PS_PS256,
26226 IX86_BUILTIN_PD_PD256,
26228 IX86_BUILTIN_VTESTZPD,
26229 IX86_BUILTIN_VTESTCPD,
26230 IX86_BUILTIN_VTESTNZCPD,
26231 IX86_BUILTIN_VTESTZPS,
26232 IX86_BUILTIN_VTESTCPS,
26233 IX86_BUILTIN_VTESTNZCPS,
26234 IX86_BUILTIN_VTESTZPD256,
26235 IX86_BUILTIN_VTESTCPD256,
26236 IX86_BUILTIN_VTESTNZCPD256,
26237 IX86_BUILTIN_VTESTZPS256,
26238 IX86_BUILTIN_VTESTCPS256,
26239 IX86_BUILTIN_VTESTNZCPS256,
26240 IX86_BUILTIN_PTESTZ256,
26241 IX86_BUILTIN_PTESTC256,
26242 IX86_BUILTIN_PTESTNZC256,
26244 IX86_BUILTIN_MOVMSKPD256,
26245 IX86_BUILTIN_MOVMSKPS256,
26247 /* AVX2 */
26248 IX86_BUILTIN_MPSADBW256,
26249 IX86_BUILTIN_PABSB256,
26250 IX86_BUILTIN_PABSW256,
26251 IX86_BUILTIN_PABSD256,
26252 IX86_BUILTIN_PACKSSDW256,
26253 IX86_BUILTIN_PACKSSWB256,
26254 IX86_BUILTIN_PACKUSDW256,
26255 IX86_BUILTIN_PACKUSWB256,
26256 IX86_BUILTIN_PADDB256,
26257 IX86_BUILTIN_PADDW256,
26258 IX86_BUILTIN_PADDD256,
26259 IX86_BUILTIN_PADDQ256,
26260 IX86_BUILTIN_PADDSB256,
26261 IX86_BUILTIN_PADDSW256,
26262 IX86_BUILTIN_PADDUSB256,
26263 IX86_BUILTIN_PADDUSW256,
26264 IX86_BUILTIN_PALIGNR256,
26265 IX86_BUILTIN_AND256I,
26266 IX86_BUILTIN_ANDNOT256I,
26267 IX86_BUILTIN_PAVGB256,
26268 IX86_BUILTIN_PAVGW256,
26269 IX86_BUILTIN_PBLENDVB256,
26270 IX86_BUILTIN_PBLENDVW256,
26271 IX86_BUILTIN_PCMPEQB256,
26272 IX86_BUILTIN_PCMPEQW256,
26273 IX86_BUILTIN_PCMPEQD256,
26274 IX86_BUILTIN_PCMPEQQ256,
26275 IX86_BUILTIN_PCMPGTB256,
26276 IX86_BUILTIN_PCMPGTW256,
26277 IX86_BUILTIN_PCMPGTD256,
26278 IX86_BUILTIN_PCMPGTQ256,
26279 IX86_BUILTIN_PHADDW256,
26280 IX86_BUILTIN_PHADDD256,
26281 IX86_BUILTIN_PHADDSW256,
26282 IX86_BUILTIN_PHSUBW256,
26283 IX86_BUILTIN_PHSUBD256,
26284 IX86_BUILTIN_PHSUBSW256,
26285 IX86_BUILTIN_PMADDUBSW256,
26286 IX86_BUILTIN_PMADDWD256,
26287 IX86_BUILTIN_PMAXSB256,
26288 IX86_BUILTIN_PMAXSW256,
26289 IX86_BUILTIN_PMAXSD256,
26290 IX86_BUILTIN_PMAXUB256,
26291 IX86_BUILTIN_PMAXUW256,
26292 IX86_BUILTIN_PMAXUD256,
26293 IX86_BUILTIN_PMINSB256,
26294 IX86_BUILTIN_PMINSW256,
26295 IX86_BUILTIN_PMINSD256,
26296 IX86_BUILTIN_PMINUB256,
26297 IX86_BUILTIN_PMINUW256,
26298 IX86_BUILTIN_PMINUD256,
26299 IX86_BUILTIN_PMOVMSKB256,
26300 IX86_BUILTIN_PMOVSXBW256,
26301 IX86_BUILTIN_PMOVSXBD256,
26302 IX86_BUILTIN_PMOVSXBQ256,
26303 IX86_BUILTIN_PMOVSXWD256,
26304 IX86_BUILTIN_PMOVSXWQ256,
26305 IX86_BUILTIN_PMOVSXDQ256,
26306 IX86_BUILTIN_PMOVZXBW256,
26307 IX86_BUILTIN_PMOVZXBD256,
26308 IX86_BUILTIN_PMOVZXBQ256,
26309 IX86_BUILTIN_PMOVZXWD256,
26310 IX86_BUILTIN_PMOVZXWQ256,
26311 IX86_BUILTIN_PMOVZXDQ256,
26312 IX86_BUILTIN_PMULDQ256,
26313 IX86_BUILTIN_PMULHRSW256,
26314 IX86_BUILTIN_PMULHUW256,
26315 IX86_BUILTIN_PMULHW256,
26316 IX86_BUILTIN_PMULLW256,
26317 IX86_BUILTIN_PMULLD256,
26318 IX86_BUILTIN_PMULUDQ256,
26319 IX86_BUILTIN_POR256,
26320 IX86_BUILTIN_PSADBW256,
26321 IX86_BUILTIN_PSHUFB256,
26322 IX86_BUILTIN_PSHUFD256,
26323 IX86_BUILTIN_PSHUFHW256,
26324 IX86_BUILTIN_PSHUFLW256,
26325 IX86_BUILTIN_PSIGNB256,
26326 IX86_BUILTIN_PSIGNW256,
26327 IX86_BUILTIN_PSIGND256,
26328 IX86_BUILTIN_PSLLDQI256,
26329 IX86_BUILTIN_PSLLWI256,
26330 IX86_BUILTIN_PSLLW256,
26331 IX86_BUILTIN_PSLLDI256,
26332 IX86_BUILTIN_PSLLD256,
26333 IX86_BUILTIN_PSLLQI256,
26334 IX86_BUILTIN_PSLLQ256,
26335 IX86_BUILTIN_PSRAWI256,
26336 IX86_BUILTIN_PSRAW256,
26337 IX86_BUILTIN_PSRADI256,
26338 IX86_BUILTIN_PSRAD256,
26339 IX86_BUILTIN_PSRLDQI256,
26340 IX86_BUILTIN_PSRLWI256,
26341 IX86_BUILTIN_PSRLW256,
26342 IX86_BUILTIN_PSRLDI256,
26343 IX86_BUILTIN_PSRLD256,
26344 IX86_BUILTIN_PSRLQI256,
26345 IX86_BUILTIN_PSRLQ256,
26346 IX86_BUILTIN_PSUBB256,
26347 IX86_BUILTIN_PSUBW256,
26348 IX86_BUILTIN_PSUBD256,
26349 IX86_BUILTIN_PSUBQ256,
26350 IX86_BUILTIN_PSUBSB256,
26351 IX86_BUILTIN_PSUBSW256,
26352 IX86_BUILTIN_PSUBUSB256,
26353 IX86_BUILTIN_PSUBUSW256,
26354 IX86_BUILTIN_PUNPCKHBW256,
26355 IX86_BUILTIN_PUNPCKHWD256,
26356 IX86_BUILTIN_PUNPCKHDQ256,
26357 IX86_BUILTIN_PUNPCKHQDQ256,
26358 IX86_BUILTIN_PUNPCKLBW256,
26359 IX86_BUILTIN_PUNPCKLWD256,
26360 IX86_BUILTIN_PUNPCKLDQ256,
26361 IX86_BUILTIN_PUNPCKLQDQ256,
26362 IX86_BUILTIN_PXOR256,
26363 IX86_BUILTIN_MOVNTDQA256,
26364 IX86_BUILTIN_VBROADCASTSS_PS,
26365 IX86_BUILTIN_VBROADCASTSS_PS256,
26366 IX86_BUILTIN_VBROADCASTSD_PD256,
26367 IX86_BUILTIN_VBROADCASTSI256,
26368 IX86_BUILTIN_PBLENDD256,
26369 IX86_BUILTIN_PBLENDD128,
26370 IX86_BUILTIN_PBROADCASTB256,
26371 IX86_BUILTIN_PBROADCASTW256,
26372 IX86_BUILTIN_PBROADCASTD256,
26373 IX86_BUILTIN_PBROADCASTQ256,
26374 IX86_BUILTIN_PBROADCASTB128,
26375 IX86_BUILTIN_PBROADCASTW128,
26376 IX86_BUILTIN_PBROADCASTD128,
26377 IX86_BUILTIN_PBROADCASTQ128,
26378 IX86_BUILTIN_VPERMVARSI256,
26379 IX86_BUILTIN_VPERMDF256,
26380 IX86_BUILTIN_VPERMVARSF256,
26381 IX86_BUILTIN_VPERMDI256,
26382 IX86_BUILTIN_VPERMTI256,
26383 IX86_BUILTIN_VEXTRACT128I256,
26384 IX86_BUILTIN_VINSERT128I256,
26385 IX86_BUILTIN_MASKLOADD,
26386 IX86_BUILTIN_MASKLOADQ,
26387 IX86_BUILTIN_MASKLOADD256,
26388 IX86_BUILTIN_MASKLOADQ256,
26389 IX86_BUILTIN_MASKSTORED,
26390 IX86_BUILTIN_MASKSTOREQ,
26391 IX86_BUILTIN_MASKSTORED256,
26392 IX86_BUILTIN_MASKSTOREQ256,
26393 IX86_BUILTIN_PSLLVV4DI,
26394 IX86_BUILTIN_PSLLVV2DI,
26395 IX86_BUILTIN_PSLLVV8SI,
26396 IX86_BUILTIN_PSLLVV4SI,
26397 IX86_BUILTIN_PSRAVV8SI,
26398 IX86_BUILTIN_PSRAVV4SI,
26399 IX86_BUILTIN_PSRLVV4DI,
26400 IX86_BUILTIN_PSRLVV2DI,
26401 IX86_BUILTIN_PSRLVV8SI,
26402 IX86_BUILTIN_PSRLVV4SI,
26404 IX86_BUILTIN_GATHERSIV2DF,
26405 IX86_BUILTIN_GATHERSIV4DF,
26406 IX86_BUILTIN_GATHERDIV2DF,
26407 IX86_BUILTIN_GATHERDIV4DF,
26408 IX86_BUILTIN_GATHERSIV4SF,
26409 IX86_BUILTIN_GATHERSIV8SF,
26410 IX86_BUILTIN_GATHERDIV4SF,
26411 IX86_BUILTIN_GATHERDIV8SF,
26412 IX86_BUILTIN_GATHERSIV2DI,
26413 IX86_BUILTIN_GATHERSIV4DI,
26414 IX86_BUILTIN_GATHERDIV2DI,
26415 IX86_BUILTIN_GATHERDIV4DI,
26416 IX86_BUILTIN_GATHERSIV4SI,
26417 IX86_BUILTIN_GATHERSIV8SI,
26418 IX86_BUILTIN_GATHERDIV4SI,
26419 IX86_BUILTIN_GATHERDIV8SI,
26421 /* Alternate 4 element gather for the vectorizer where
26422 all operands are 32-byte wide. */
26423 IX86_BUILTIN_GATHERALTSIV4DF,
26424 IX86_BUILTIN_GATHERALTDIV8SF,
26425 IX86_BUILTIN_GATHERALTSIV4DI,
26426 IX86_BUILTIN_GATHERALTDIV8SI,
26428 /* TFmode support builtins. */
26429 IX86_BUILTIN_INFQ,
26430 IX86_BUILTIN_HUGE_VALQ,
26431 IX86_BUILTIN_FABSQ,
26432 IX86_BUILTIN_COPYSIGNQ,
26434 /* Vectorizer support builtins. */
26435 IX86_BUILTIN_CPYSGNPS,
26436 IX86_BUILTIN_CPYSGNPD,
26437 IX86_BUILTIN_CPYSGNPS256,
26438 IX86_BUILTIN_CPYSGNPD256,
26440 /* FMA4 instructions. */
26441 IX86_BUILTIN_VFMADDSS,
26442 IX86_BUILTIN_VFMADDSD,
26443 IX86_BUILTIN_VFMADDPS,
26444 IX86_BUILTIN_VFMADDPD,
26445 IX86_BUILTIN_VFMADDPS256,
26446 IX86_BUILTIN_VFMADDPD256,
26447 IX86_BUILTIN_VFMADDSUBPS,
26448 IX86_BUILTIN_VFMADDSUBPD,
26449 IX86_BUILTIN_VFMADDSUBPS256,
26450 IX86_BUILTIN_VFMADDSUBPD256,
26452 /* FMA3 instructions. */
26453 IX86_BUILTIN_VFMADDSS3,
26454 IX86_BUILTIN_VFMADDSD3,
26456 /* XOP instructions. */
26457 IX86_BUILTIN_VPCMOV,
26458 IX86_BUILTIN_VPCMOV_V2DI,
26459 IX86_BUILTIN_VPCMOV_V4SI,
26460 IX86_BUILTIN_VPCMOV_V8HI,
26461 IX86_BUILTIN_VPCMOV_V16QI,
26462 IX86_BUILTIN_VPCMOV_V4SF,
26463 IX86_BUILTIN_VPCMOV_V2DF,
26464 IX86_BUILTIN_VPCMOV256,
26465 IX86_BUILTIN_VPCMOV_V4DI256,
26466 IX86_BUILTIN_VPCMOV_V8SI256,
26467 IX86_BUILTIN_VPCMOV_V16HI256,
26468 IX86_BUILTIN_VPCMOV_V32QI256,
26469 IX86_BUILTIN_VPCMOV_V8SF256,
26470 IX86_BUILTIN_VPCMOV_V4DF256,
26472 IX86_BUILTIN_VPPERM,
26474 IX86_BUILTIN_VPMACSSWW,
26475 IX86_BUILTIN_VPMACSWW,
26476 IX86_BUILTIN_VPMACSSWD,
26477 IX86_BUILTIN_VPMACSWD,
26478 IX86_BUILTIN_VPMACSSDD,
26479 IX86_BUILTIN_VPMACSDD,
26480 IX86_BUILTIN_VPMACSSDQL,
26481 IX86_BUILTIN_VPMACSSDQH,
26482 IX86_BUILTIN_VPMACSDQL,
26483 IX86_BUILTIN_VPMACSDQH,
26484 IX86_BUILTIN_VPMADCSSWD,
26485 IX86_BUILTIN_VPMADCSWD,
26487 IX86_BUILTIN_VPHADDBW,
26488 IX86_BUILTIN_VPHADDBD,
26489 IX86_BUILTIN_VPHADDBQ,
26490 IX86_BUILTIN_VPHADDWD,
26491 IX86_BUILTIN_VPHADDWQ,
26492 IX86_BUILTIN_VPHADDDQ,
26493 IX86_BUILTIN_VPHADDUBW,
26494 IX86_BUILTIN_VPHADDUBD,
26495 IX86_BUILTIN_VPHADDUBQ,
26496 IX86_BUILTIN_VPHADDUWD,
26497 IX86_BUILTIN_VPHADDUWQ,
26498 IX86_BUILTIN_VPHADDUDQ,
26499 IX86_BUILTIN_VPHSUBBW,
26500 IX86_BUILTIN_VPHSUBWD,
26501 IX86_BUILTIN_VPHSUBDQ,
26503 IX86_BUILTIN_VPROTB,
26504 IX86_BUILTIN_VPROTW,
26505 IX86_BUILTIN_VPROTD,
26506 IX86_BUILTIN_VPROTQ,
26507 IX86_BUILTIN_VPROTB_IMM,
26508 IX86_BUILTIN_VPROTW_IMM,
26509 IX86_BUILTIN_VPROTD_IMM,
26510 IX86_BUILTIN_VPROTQ_IMM,
26512 IX86_BUILTIN_VPSHLB,
26513 IX86_BUILTIN_VPSHLW,
26514 IX86_BUILTIN_VPSHLD,
26515 IX86_BUILTIN_VPSHLQ,
26516 IX86_BUILTIN_VPSHAB,
26517 IX86_BUILTIN_VPSHAW,
26518 IX86_BUILTIN_VPSHAD,
26519 IX86_BUILTIN_VPSHAQ,
26521 IX86_BUILTIN_VFRCZSS,
26522 IX86_BUILTIN_VFRCZSD,
26523 IX86_BUILTIN_VFRCZPS,
26524 IX86_BUILTIN_VFRCZPD,
26525 IX86_BUILTIN_VFRCZPS256,
26526 IX86_BUILTIN_VFRCZPD256,
26528 IX86_BUILTIN_VPCOMEQUB,
26529 IX86_BUILTIN_VPCOMNEUB,
26530 IX86_BUILTIN_VPCOMLTUB,
26531 IX86_BUILTIN_VPCOMLEUB,
26532 IX86_BUILTIN_VPCOMGTUB,
26533 IX86_BUILTIN_VPCOMGEUB,
26534 IX86_BUILTIN_VPCOMFALSEUB,
26535 IX86_BUILTIN_VPCOMTRUEUB,
26537 IX86_BUILTIN_VPCOMEQUW,
26538 IX86_BUILTIN_VPCOMNEUW,
26539 IX86_BUILTIN_VPCOMLTUW,
26540 IX86_BUILTIN_VPCOMLEUW,
26541 IX86_BUILTIN_VPCOMGTUW,
26542 IX86_BUILTIN_VPCOMGEUW,
26543 IX86_BUILTIN_VPCOMFALSEUW,
26544 IX86_BUILTIN_VPCOMTRUEUW,
26546 IX86_BUILTIN_VPCOMEQUD,
26547 IX86_BUILTIN_VPCOMNEUD,
26548 IX86_BUILTIN_VPCOMLTUD,
26549 IX86_BUILTIN_VPCOMLEUD,
26550 IX86_BUILTIN_VPCOMGTUD,
26551 IX86_BUILTIN_VPCOMGEUD,
26552 IX86_BUILTIN_VPCOMFALSEUD,
26553 IX86_BUILTIN_VPCOMTRUEUD,
26555 IX86_BUILTIN_VPCOMEQUQ,
26556 IX86_BUILTIN_VPCOMNEUQ,
26557 IX86_BUILTIN_VPCOMLTUQ,
26558 IX86_BUILTIN_VPCOMLEUQ,
26559 IX86_BUILTIN_VPCOMGTUQ,
26560 IX86_BUILTIN_VPCOMGEUQ,
26561 IX86_BUILTIN_VPCOMFALSEUQ,
26562 IX86_BUILTIN_VPCOMTRUEUQ,
26564 IX86_BUILTIN_VPCOMEQB,
26565 IX86_BUILTIN_VPCOMNEB,
26566 IX86_BUILTIN_VPCOMLTB,
26567 IX86_BUILTIN_VPCOMLEB,
26568 IX86_BUILTIN_VPCOMGTB,
26569 IX86_BUILTIN_VPCOMGEB,
26570 IX86_BUILTIN_VPCOMFALSEB,
26571 IX86_BUILTIN_VPCOMTRUEB,
26573 IX86_BUILTIN_VPCOMEQW,
26574 IX86_BUILTIN_VPCOMNEW,
26575 IX86_BUILTIN_VPCOMLTW,
26576 IX86_BUILTIN_VPCOMLEW,
26577 IX86_BUILTIN_VPCOMGTW,
26578 IX86_BUILTIN_VPCOMGEW,
26579 IX86_BUILTIN_VPCOMFALSEW,
26580 IX86_BUILTIN_VPCOMTRUEW,
26582 IX86_BUILTIN_VPCOMEQD,
26583 IX86_BUILTIN_VPCOMNED,
26584 IX86_BUILTIN_VPCOMLTD,
26585 IX86_BUILTIN_VPCOMLED,
26586 IX86_BUILTIN_VPCOMGTD,
26587 IX86_BUILTIN_VPCOMGED,
26588 IX86_BUILTIN_VPCOMFALSED,
26589 IX86_BUILTIN_VPCOMTRUED,
26591 IX86_BUILTIN_VPCOMEQQ,
26592 IX86_BUILTIN_VPCOMNEQ,
26593 IX86_BUILTIN_VPCOMLTQ,
26594 IX86_BUILTIN_VPCOMLEQ,
26595 IX86_BUILTIN_VPCOMGTQ,
26596 IX86_BUILTIN_VPCOMGEQ,
26597 IX86_BUILTIN_VPCOMFALSEQ,
26598 IX86_BUILTIN_VPCOMTRUEQ,
26600 /* LWP instructions. */
26601 IX86_BUILTIN_LLWPCB,
26602 IX86_BUILTIN_SLWPCB,
26603 IX86_BUILTIN_LWPVAL32,
26604 IX86_BUILTIN_LWPVAL64,
26605 IX86_BUILTIN_LWPINS32,
26606 IX86_BUILTIN_LWPINS64,
26608 IX86_BUILTIN_CLZS,
26610 /* RTM */
26611 IX86_BUILTIN_XBEGIN,
26612 IX86_BUILTIN_XEND,
26613 IX86_BUILTIN_XABORT,
26614 IX86_BUILTIN_XTEST,
26616 /* BMI instructions. */
26617 IX86_BUILTIN_BEXTR32,
26618 IX86_BUILTIN_BEXTR64,
26619 IX86_BUILTIN_CTZS,
26621 /* TBM instructions. */
26622 IX86_BUILTIN_BEXTRI32,
26623 IX86_BUILTIN_BEXTRI64,
26625 /* BMI2 instructions. */
26626 IX86_BUILTIN_BZHI32,
26627 IX86_BUILTIN_BZHI64,
26628 IX86_BUILTIN_PDEP32,
26629 IX86_BUILTIN_PDEP64,
26630 IX86_BUILTIN_PEXT32,
26631 IX86_BUILTIN_PEXT64,
26633 /* ADX instructions. */
26634 IX86_BUILTIN_ADDCARRYX32,
26635 IX86_BUILTIN_ADDCARRYX64,
26637 /* FSGSBASE instructions. */
26638 IX86_BUILTIN_RDFSBASE32,
26639 IX86_BUILTIN_RDFSBASE64,
26640 IX86_BUILTIN_RDGSBASE32,
26641 IX86_BUILTIN_RDGSBASE64,
26642 IX86_BUILTIN_WRFSBASE32,
26643 IX86_BUILTIN_WRFSBASE64,
26644 IX86_BUILTIN_WRGSBASE32,
26645 IX86_BUILTIN_WRGSBASE64,
26647 /* RDRND instructions. */
26648 IX86_BUILTIN_RDRAND16_STEP,
26649 IX86_BUILTIN_RDRAND32_STEP,
26650 IX86_BUILTIN_RDRAND64_STEP,
26652 /* RDSEED instructions. */
26653 IX86_BUILTIN_RDSEED16_STEP,
26654 IX86_BUILTIN_RDSEED32_STEP,
26655 IX86_BUILTIN_RDSEED64_STEP,
26657 /* F16C instructions. */
26658 IX86_BUILTIN_CVTPH2PS,
26659 IX86_BUILTIN_CVTPH2PS256,
26660 IX86_BUILTIN_CVTPS2PH,
26661 IX86_BUILTIN_CVTPS2PH256,
26663 /* CFString built-in for darwin */
26664 IX86_BUILTIN_CFSTRING,
26666 /* Builtins to get CPU type and supported features. */
26667 IX86_BUILTIN_CPU_INIT,
26668 IX86_BUILTIN_CPU_IS,
26669 IX86_BUILTIN_CPU_SUPPORTS,
26671 IX86_BUILTIN_MAX
26672 };
26674 /* Table for the ix86 builtin decls. */
26677 /* Table of all of the builtin functions that are possible with different ISA's
26678 but are waiting to be built until a function is declared to use that
26679 ISA. */
26686 };
26691 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
26692 of which isa_flags to use in the ix86_builtins_isa array. Stores the
26693 function decl in the ix86_builtins array. Returns the function decl or
26694 NULL_TREE, if the builtin was not added.
26696 If the front end has a special hook for builtin functions, delay adding
26697 builtin functions that aren't in the current ISA until the ISA is changed
26698 with function specific optimization. Doing so, can save about 300K for the
26699 default compiler. When the builtin is expanded, check at that time whether
26700 it is valid.
26702 If the front end doesn't have a special hook, record all builtins, even if
26703 it isn't an instruction set in the current ISA in case the user uses
26704 function specific options for a different ISA, so that we don't get scope
26705 errors if a builtin is added in the middle of a function scope. */
26711 {
26715 {
26724 {
26730 }
26731 else
26732 {
26738 }
26739 }
26742 }
26744 /* Like def_builtin, but also marks the function decl "const". */
26749 {
26753 else
26757 }
26759 /* Add any new builtin functions for a given ISA that may not have been
26760 declared. This saves a bit of space compared to adding all of the
26761 declarations to the tree, even if we didn't use them. */
26763 static void
26765 {
26769 {
26772 {
26775 /* Don't define the builtin again. */
26781 NULL_TREE);
26786 }
26787 }
26788 }
26790 /* Bits for builtin_description.flag. */
26792 /* Set when we don't support the comparison natively, and should
26793 swap_comparison in order to support it. */
26794 #define BUILTIN_DESC_SWAP_OPERANDS 1
26796 struct builtin_description
26797 {
26804 };
26807 {
26808 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
26809 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
26810 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
26811 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
26812 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
26813 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
26814 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
26815 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
26816 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
26817 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
26818 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
26819 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
26820 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
26821 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
26822 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
26823 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
26824 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
26825 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
26826 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
26827 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
26828 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
26829 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
26830 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
26831 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
26832 };
26835 {
26836 /* SSE4.2 */
26837 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
26838 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
26839 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
26840 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
26841 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
26842 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
26843 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
26844 };
26847 {
26848 /* SSE4.2 */
26849 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
26850 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
26851 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
26852 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
26853 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
26854 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
26855 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
26856 };
26858 /* Special builtins with variable number of arguments. */
26860 {
26861 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
26862 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
26863 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
26865 /* MMX */
26866 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26868 /* 3DNow! */
26869 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26871 /* FXSR, XSAVE and XSAVEOPT */
26872 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
26873 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
26874 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26875 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26876 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26878 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26879 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26880 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26881 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26882 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26884 /* SSE */
26885 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26886 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26887 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26889 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26890 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26891 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26892 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26894 /* SSE or 3DNow!A */
26895 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26896 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
26898 /* SSE2 */
26899 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26900 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26901 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26902 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
26903 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26904 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
26905 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
26906 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
26907 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
26908 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26910 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26911 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26913 /* SSE3 */
26914 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26916 /* SSE4.1 */
26917 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
26919 /* SSE4A */
26920 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26921 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26923 /* AVX */
26924 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
26925 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
26927 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26928 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26929 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26930 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
26931 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
26933 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26934 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26935 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26936 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26937 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26938 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
26939 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26941 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
26942 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26943 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26945 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
26946 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
26947 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
26948 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
26949 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
26950 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
26951 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
26952 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
26954 /* AVX2 */
26955 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
26956 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
26957 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
26958 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
26959 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
26960 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
26961 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
26962 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
26963 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
26965 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
26966 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
26967 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
26968 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
26969 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
26970 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
26972 /* FSGSBASE */
26973 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26974 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26975 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26976 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26977 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26978 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26979 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26980 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26982 /* RTM */
26983 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26984 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
26985 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
26986 };
26988 /* Builtins with variable number of arguments. */
26990 {
26991 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
26992 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
26993 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
26994 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26995 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26996 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26997 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26999 /* MMX */
27000 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27001 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27002 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27003 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27004 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27005 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27007 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27008 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27009 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27010 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27011 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27012 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27013 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27014 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27016 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27017 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27019 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27020 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27021 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27022 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27024 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27025 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27026 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27027 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27028 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27029 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27031 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27032 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27033 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27034 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27035 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
27036 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
27038 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27039 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
27040 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27042 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
27044 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27045 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27046 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27047 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27048 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27049 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27051 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27052 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27053 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27054 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27055 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27056 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27058 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27059 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27060 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27061 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27063 /* 3DNow! */
27064 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27065 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27066 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27067 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27069 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27070 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27071 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27072 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27073 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27074 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27075 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27076 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27077 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27078 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27079 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27080 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27081 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27082 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27083 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27085 /* 3DNow!A */
27086 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27087 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27088 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27089 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27090 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27091 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27093 /* SSE */
27094 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
27095 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27096 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27097 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27098 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27099 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27100 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27101 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27102 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27103 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27104 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27105 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27107 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27109 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27110 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27111 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27112 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27113 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27114 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27115 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27116 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27118 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27119 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27120 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27121 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27122 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27123 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27124 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27125 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27126 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27127 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27128 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
27129 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27130 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27131 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27132 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27133 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27134 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27135 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27136 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27137 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27138 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27139 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27141 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27142 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27143 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27144 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27146 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27147 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27148 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27149 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27151 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27153 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27154 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27155 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27156 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27157 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27159 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
27160 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
27161 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
27163 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
27165 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27166 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27167 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27169 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
27170 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
27172 /* SSE MMX or 3Dnow!A */
27173 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27174 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27175 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27177 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27178 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27179 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27180 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27182 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
27183 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
27185 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
27187 /* SSE2 */
27188 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
27191 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
27192 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27193 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
27194 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
27196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27197 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27198 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
27199 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27200 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27202 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
27204 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27205 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27206 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27207 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27209 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27210 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
27211 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27213 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27214 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27215 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27216 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27217 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27226 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
27227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27232 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27233 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27234 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27235 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27236 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27237 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27238 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27239 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27240 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27241 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27243 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27244 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27245 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27246 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27248 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27249 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27250 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27251 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27253 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27255 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27256 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27257 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27259 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27261 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27262 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27263 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27264 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27265 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27266 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27267 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27268 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27271 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27272 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27273 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27274 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27275 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27276 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27277 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27279 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27280 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
27282 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27283 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27284 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27285 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27287 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27288 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27290 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27291 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27292 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27293 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27294 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27295 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27297 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27298 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27299 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27300 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27302 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27303 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27304 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27305 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27306 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27307 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27308 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27309 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27312 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27313 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27315 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
27318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
27319 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
27323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
27324 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
27325 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
27326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
27328 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27329 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27330 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27331 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27332 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27333 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27334 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27337 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27338 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27339 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27340 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27341 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27342 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27344 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27345 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27346 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27347 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27349 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
27350 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27351 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27353 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
27355 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27357 /* SSE2 MMX */
27358 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27359 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27361 /* SSE3 */
27362 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
27363 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27365 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27366 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27367 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27368 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27369 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27370 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27372 /* SSSE3 */
27373 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27374 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
27375 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27376 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
27377 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27378 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27380 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27381 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27382 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27383 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27384 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27385 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27386 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27387 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27388 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27389 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27390 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27391 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27392 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
27393 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
27394 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27395 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27396 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27397 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27398 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27399 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27400 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27401 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27402 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27403 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27405 /* SSSE3. */
27406 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
27407 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
27409 /* SSE4.1 */
27410 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27411 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27412 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
27413 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
27414 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27415 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27416 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27417 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
27418 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
27419 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
27421 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27422 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27423 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27424 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27425 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27426 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27427 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27428 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27429 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27430 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27431 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27432 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27433 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27435 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27436 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27437 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27438 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27439 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27440 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27441 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27442 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27443 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27444 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27445 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27446 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27448 /* SSE4.1 */
27449 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27450 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27451 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27452 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27454 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
27455 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
27456 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
27457 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
27459 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27460 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27462 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27463 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27465 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
27466 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
27467 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
27468 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
27470 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
27471 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
27473 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27474 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27476 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27477 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27478 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27480 /* SSE4.2 */
27481 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27482 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
27483 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
27484 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27485 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27487 /* SSE4A */
27488 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
27489 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
27490 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
27491 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27493 /* AES */
27494 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
27495 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27497 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27498 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27499 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27500 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27502 /* PCLMUL */
27503 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
27505 /* AVX */
27506 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27507 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27508 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27509 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27510 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27511 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27512 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27513 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27514 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27515 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27516 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27517 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27518 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27519 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27520 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27521 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27522 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27523 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27524 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27525 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27526 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27527 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27528 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27529 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27530 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27531 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27533 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
27534 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
27535 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
27536 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27538 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27539 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27540 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
27541 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
27542 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27543 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27544 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27545 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27546 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27547 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27548 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27549 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27550 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27551 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
27552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
27553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
27554 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
27555 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
27556 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
27557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
27559 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27560 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27561 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27562 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27563 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27564 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27566 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
27570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
27571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
27573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27575 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27577 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27579 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27581 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27588 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
27589 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
27590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
27591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
27593 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27594 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27596 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27597 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27599 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
27600 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
27601 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
27602 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
27604 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
27605 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
27607 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27608 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27610 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27611 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27612 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27613 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27615 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27616 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27617 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27618 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
27619 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
27620 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
27622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27625 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27626 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27628 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27631 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27632 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27633 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27634 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27635 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27636 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27638 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
27639 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
27641 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27642 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27644 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27646 /* AVX2 */
27647 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
27648 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
27649 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
27650 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
27651 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27652 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27653 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27654 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27655 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27656 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27657 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27658 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27659 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27660 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27661 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27662 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27663 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
27664 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27665 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27666 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27667 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27668 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
27669 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
27670 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27671 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27672 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27673 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27674 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27675 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27676 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27677 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27678 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27679 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27680 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27681 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27682 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27683 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27684 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27685 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
27686 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27687 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27688 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27689 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27690 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27691 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27692 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27693 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27694 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27695 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27696 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27697 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27698 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
27699 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27700 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27701 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27702 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27703 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27704 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27705 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27706 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27707 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27708 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27709 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27710 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27711 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27712 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27713 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27714 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27715 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27716 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27717 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27718 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27719 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27720 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27721 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
27722 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27723 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27724 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27725 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27726 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27727 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27728 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27729 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27730 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27731 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27732 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27733 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27734 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27735 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27736 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27737 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27738 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27739 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27740 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27741 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27742 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27743 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27744 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27745 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27746 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27747 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27748 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27749 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27750 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27751 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27752 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27753 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27754 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27755 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27756 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27757 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27758 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27759 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27760 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27761 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27762 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27763 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27764 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27765 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27766 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
27767 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27768 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
27769 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
27770 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27771 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27772 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27773 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27774 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27775 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27776 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27777 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27778 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27779 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
27780 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
27781 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
27782 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
27783 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27784 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27785 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27786 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27787 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27788 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27789 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27790 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27791 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27792 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27794 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27796 /* BMI */
27797 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27798 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27799 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27801 /* TBM */
27802 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27803 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27805 /* F16C */
27806 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
27807 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
27808 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
27809 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
27811 /* BMI2 */
27812 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27813 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27814 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27815 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27816 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27817 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27818 };
27820 /* FMA4 and XOP. */
27821 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
27822 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
27823 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
27824 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
27825 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
27826 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
27827 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
27828 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
27829 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
27830 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
27831 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
27832 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
27833 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
27834 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
27835 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
27836 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
27837 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
27838 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
27839 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
27840 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
27841 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
27842 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
27843 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
27844 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
27845 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
27846 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
27847 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
27848 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
27849 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
27850 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
27851 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
27852 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
27853 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
27854 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
27855 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
27856 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
27857 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
27858 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
27859 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
27860 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
27861 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
27862 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
27863 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
27864 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
27865 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
27866 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
27867 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
27868 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
27869 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
27870 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
27871 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
27872 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
27875 {
27916 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
27917 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
27918 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
27919 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
27920 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
27921 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
27922 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
27924 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27925 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27926 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
27927 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
27928 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
27929 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
27930 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
27932 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
27934 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27935 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27936 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27937 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27938 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27939 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27940 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27941 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27942 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27943 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27944 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27945 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27947 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27948 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
27949 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
27950 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
27951 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
27952 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
27953 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
27954 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
27955 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27956 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
27957 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
27958 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
27959 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27960 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
27961 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
27962 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
27964 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
27965 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
27966 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
27967 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
27968 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
27969 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
27971 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27972 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27973 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27974 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27975 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27976 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27977 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27978 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27979 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27980 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27981 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27982 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27983 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27984 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27985 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27987 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
27988 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27989 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27990 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
27991 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
27992 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
27993 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
27995 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
27996 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27997 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27998 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
27999 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
28000 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
28001 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
28003 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
28004 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
28005 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
28006 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
28007 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
28008 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
28009 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
28011 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28012 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28013 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28014 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
28015 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
28016 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
28017 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
28019 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
28020 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28021 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28022 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
28023 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
28024 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
28025 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
28027 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
28028 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28029 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28030 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
28031 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
28032 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
28033 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
28035 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
28036 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28037 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28038 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
28039 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
28040 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
28041 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
28043 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28044 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28045 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28046 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
28047 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
28048 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
28049 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
28051 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28052 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28053 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28054 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28055 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28056 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28057 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28058 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28060 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28061 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28062 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28063 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28064 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28065 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28066 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28067 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28069 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
28070 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
28071 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
28072 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
28074 };
28075 \f
28076 /* TM vector builtins. */
28078 /* Reuse the existing x86-specific `struct builtin_description' cause
28079 we're lazy. Add casts to make them fit. */
28081 {
28082 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28083 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28084 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28085 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28086 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28087 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28088 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28090 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28091 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28092 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28093 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28094 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28095 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28096 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28098 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28099 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28100 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28101 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28102 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28103 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28104 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28106 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
28107 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
28108 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
28109 };
28111 /* TM callbacks. */
28113 /* Return the builtin decl needed to load a vector of TYPE. */
28115 static tree
28117 {
28119 {
28121 {
28128 }
28129 }
28131 }
28133 /* Return the builtin decl needed to store a vector of TYPE. */
28135 static tree
28137 {
28139 {
28141 {
28148 }
28149 }
28151 }
28152 \f
28153 /* Initialize the transactional memory vector load/store builtins. */
28155 static void
28157 {
28161 tree decl;
28168 /* If there are no builtins defined, we must be compiling in a
28169 language without trans-mem support. */
28173 /* Use whatever attributes a normal TM load has. */
28177 /* Use whatever attributes a normal TM store has. */
28181 /* Use whatever attributes a normal TM log has. */
28189 {
28193 {
28201 {
28204 }
28206 {
28209 }
28210 else
28211 {
28214 }
28216 /* The builtin without the prefix for
28217 calling it directly. */
28219 attrs);
28220 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
28221 set the TYPE_ATTRIBUTES. */
28225 }
28226 }
28227 }
28229 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
28230 in the current target ISA to allow the user to compile particular modules
28231 with different target specific options that differ from the command line
28232 options. */
28233 static void
28235 {
28240 /* Add all special builtins with variable number of operands. */
28244 {
28250 }
28252 /* Add all builtins with variable number of operands. */
28256 {
28262 }
28264 /* pcmpestr[im] insns. */
28268 {
28271 else
28274 }
28276 /* pcmpistr[im] insns. */
28280 {
28283 else
28286 }
28288 /* comi/ucomi insns. */
28290 {
28293 else
28296 }
28298 /* SSE */
28304 /* SSE or 3DNow!A */
28307 IX86_BUILTIN_MASKMOVQ);
28309 /* SSE2 */
28318 /* SSE3. */
28324 /* AES */
28338 /* PCLMUL */
28342 /* RDRND */
28349 IX86_BUILTIN_RDRAND64_STEP);
28351 /* AVX2 */
28353 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
28354 IX86_BUILTIN_GATHERSIV2DF);
28357 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
28358 IX86_BUILTIN_GATHERSIV4DF);
28361 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
28362 IX86_BUILTIN_GATHERDIV2DF);
28365 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
28366 IX86_BUILTIN_GATHERDIV4DF);
28369 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
28370 IX86_BUILTIN_GATHERSIV4SF);
28373 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
28374 IX86_BUILTIN_GATHERSIV8SF);
28377 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
28378 IX86_BUILTIN_GATHERDIV4SF);
28381 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
28382 IX86_BUILTIN_GATHERDIV8SF);
28385 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
28386 IX86_BUILTIN_GATHERSIV2DI);
28389 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
28390 IX86_BUILTIN_GATHERSIV4DI);
28393 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
28394 IX86_BUILTIN_GATHERDIV2DI);
28397 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
28398 IX86_BUILTIN_GATHERDIV4DI);
28401 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
28402 IX86_BUILTIN_GATHERSIV4SI);
28405 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
28406 IX86_BUILTIN_GATHERSIV8SI);
28409 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
28410 IX86_BUILTIN_GATHERDIV4SI);
28413 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
28414 IX86_BUILTIN_GATHERDIV8SI);
28417 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
28418 IX86_BUILTIN_GATHERALTSIV4DF);
28421 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
28422 IX86_BUILTIN_GATHERALTDIV8SF);
28425 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
28426 IX86_BUILTIN_GATHERALTSIV4DI);
28429 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
28430 IX86_BUILTIN_GATHERALTDIV8SI);
28432 /* RTM. */
28436 /* MMX access to the vec_init patterns. */
28441 V4HI_FTYPE_HI_HI_HI_HI,
28442 IX86_BUILTIN_VEC_INIT_V4HI);
28445 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
28446 IX86_BUILTIN_VEC_INIT_V8QI);
28448 /* Access to the vec_extract patterns. */
28470 /* Access to the vec_set patterns. */
28491 /* RDSEED */
28500 /* ADCX */
28505 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
28506 IX86_BUILTIN_ADDCARRYX64);
28508 /* Add FMA4 multi-arg argument instructions */
28510 {
28516 }
28517 }
28519 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
28520 to return a pointer to VERSION_DECL if the outcome of the expression
28521 formed by PREDICATE_CHAIN is true. This function will be called during
28522 version dispatch to decide which function version to execute. It returns
28523 the basic block at the end, to which more conditions can be added. */
28525 static basic_block
28528 {
28529 gimple return_stmt;
28531 gimple convert_stmt;
28532 gimple call_cond_stmt;
28533 gimple if_else_stmt;
28539 gimple_seq gseq;
28556 {
28564 }
28567 {
28582 else
28583 {
28584 gimple assign_stmt;
28585 /* Use MIN_EXPR to check if any integer is zero?.
28586 and_expr_var = min_expr <cond_var, and_expr_var> */
28594 }
28595 }
28598 integer_zero_node,
28628 }
28630 /* This parses the attribute arguments to target in DECL and determines
28631 the right builtin to use to match the platform specification.
28632 It returns the priority value for this version decl. If PREDICATE_LIST
28633 is not NULL, it stores the list of cpu features that need to be checked
28634 before dispatching this function. */
28636 static unsigned int
28638 {
28639 tree attrs;
28641 tree target_node;
28648 /* Priority of i386 features, greater value is higher priority. This is
28649 used to decide the order in which function dispatch must happen. For
28650 instance, a version specialized for SSE4.2 should be checked for dispatch
28651 before a version for SSE3, as SSE4.2 implies SSE3. */
28652 enum feature_priority
28653 {
28655 P_MMX,
28656 P_SSE,
28657 P_SSE2,
28658 P_SSE3,
28659 P_SSSE3,
28660 P_PROC_SSSE3,
28661 P_SSE4_a,
28662 P_PROC_SSE4_a,
28663 P_SSE4_1,
28664 P_SSE4_2,
28665 P_PROC_SSE4_2,
28666 P_POPCNT,
28667 P_AVX,
28668 P_AVX2,
28669 P_FMA,
28670 P_PROC_FMA
28671 };
28675 /* These are the target attribute strings for which a dispatcher is
28676 available, from fold_builtin_cpu. */
28678 static struct _feature_list
28679 {
28682 }
28684 {
28695 };
28698 static unsigned int NUM_FEATURES
28715 /* Handle arch= if specified. For priority, set it to be 1 more than
28716 the best instruction set the processor can handle. For instance, if
28717 there is a version for atom and a version for ssse3 (the highest ISA
28718 priority for atom), the atom version must be checked for dispatch
28719 before the ssse3 version. */
28721 {
28730 {
28732 {
28757 }
28758 }
28763 {
28767 }
28770 {
28772 /* For a C string literal the length includes the trailing NULL. */
28775 predicate_chain);
28776 }
28777 }
28779 /* Process feature name. */
28786 {
28787 /* Do not process "arch=" */
28789 {
28792 }
28794 {
28796 {
28798 {
28803 predicate_chain);
28804 }
28805 /* Find the maximum priority feature. */
28810 }
28811 }
28813 {
28817 }
28819 }
28823 {
28826 attrs_str);
28828 }
28830 {
28833 }
28836 }
28838 /* This compares the priority of target features in function DECL1
28839 and DECL2. It returns positive value if DECL1 is higher priority,
28840 negative value if DECL2 is higher priority and 0 if they are the
28841 same. */
28843 static int
28845 {
28856 }
28858 /* V1 and V2 point to function versions with different priorities
28859 based on the target ISA. This function compares their priorities. */
28861 static int
28863 {
28865 {
28866 tree version_decl;
28867 tree predicate_chain;
28874 }
28876 /* This function generates the dispatch function for
28877 multi-versioned functions. DISPATCH_DECL is the function which will
28878 contain the dispatch logic. FNDECLS are the function choices for
28879 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
28880 in DISPATCH_DECL in which the dispatch code is generated. */
28882 static int
28886 {
28887 tree default_decl;
28888 gimple ifunc_cpu_init_stmt;
28889 gimple_seq gseq;
28891 tree ele;
28897 struct _function_version_info
28898 {
28899 tree version_decl;
28900 tree predicate_chain;
28908 /*fndecls_p is actually a vector. */
28911 /* At least one more version other than the default. */
28918 /* The first version in the vector is the default decl. */
28924 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
28925 constructors, so explicity call __builtin_cpu_init here. */
28936 {
28940 /* Get attribute string, parse it and find the right predicate decl.
28941 The predicate function could be a lengthy combination of many
28942 features, like arch-type and various isa-variants. */
28949 actual_versions++;
28953 }
28955 /* Sort the versions according to descending order of dispatch priority. The
28956 priority is based on the ISA. This is not a perfect solution. There
28957 could still be ambiguity. If more than one function version is suitable
28958 to execute, which one should be dispatched? In future, allow the user
28959 to specify a dispatch priority next to the version. */
28969 /* dispatch default version at the end. */
28975 }
28977 /* Comparator function to be used in qsort routine to sort attribute
28978 specification strings to "target". */
28980 static int
28982 {
28986 }
28988 /* ARGLIST is the argument to target attribute. This function tokenizes
28989 the comma separated arguments, sorts them and returns a string which
28990 is a unique identifier for the comma separated arguments. It also
28991 replaces non-identifier characters "=,-" with "_". */
28995 {
28996 tree arg;
29005 {
29010 argnum++;
29013 argnum++;
29014 }
29019 {
29025 }
29027 /* Replace "=,-" with "_". */
29040 {
29042 i++;
29044 }
29051 {
29056 }
29061 }
29063 /* This function changes the assembler name for functions that are
29064 versions. If DECL is a function version and has a "target"
29065 attribute, it appends the attribute string to its assembler name. */
29067 static tree
29069 {
29070 tree version_attr;
29078 "Function versions cannot be marked as gnu_inline,"
29088 /* target attribute string is NULL for default functions. */
29093 version_string
29104 /* Allow assembler name to be modified if already set. */
29112 }
29114 /* This function returns true if FN1 and FN2 are versions of the same function,
29115 that is, the target strings of the function decls are different. This assumes
29116 that FN1 and FN2 have the same signature. */
29118 static bool
29120 {
29132 /* At least one function decl should have the target attribute specified. */
29136 /* Diagnose missing target attribute if one of the decls is already
29137 multi-versioned. */
29139 {
29141 {
29143 {
29148 }
29151 fn2);
29154 /* Prevent diagnosing of the same error multiple times. */
29159 }
29161 }
29166 /* The sorted target strings must be different for fn1 and fn2
29167 to be versions. */
29170 else
29177 }
29179 static tree
29181 {
29182 /* For function version, add the target suffix to the assembler name. */
29186 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
29188 #endif
29191 }
29193 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
29194 is true, append the full path name of the source file. */
29198 {
29206 /* Get a unique name that can be used globally without any chances
29207 of collision at link time. */
29217 /* Use '.' to concatenate names as it is demangler friendly. */
29220 suffix);
29221 else
29225 }
29227 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29229 /* Make a dispatcher declaration for the multi-versioned function DECL.
29230 Calls to DECL function will be replaced with calls to the dispatcher
29231 by the front-end. Return the decl created. */
29233 static tree
29235 {
29236 tree func_decl;
29256 /* Mark this func as external, the resolver will flip it again if
29257 it gets generated. */
29259 /* This will be of type IFUNCs have to be externally visible. */
29263 }
29265 #endif
29267 /* Returns true if decl is multi-versioned and DECL is the default function,
29268 that is it is not tagged with target specific optimization. */
29270 static bool
29272 {
29281 }
29283 /* Make a dispatcher declaration for the multi-versioned function DECL.
29284 Calls to DECL function will be replaced with calls to the dispatcher
29285 by the front-end. Returns the decl of the dispatcher function. */
29287 static tree
29289 {
29298 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29302 #endif
29317 /* Find the default version and make it the first node. */
29319 /* Go to the beginnig of the chain. */
29324 {
29329 }
29331 /* If there is no default node, just return NULL. */
29335 /* Make default info the first node. */
29337 {
29344 }
29348 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29349 /* Right now, the dispatching is done via ifunc. */
29355 dispatcher_version_info
29360 /* Set the dispatcher for all the versions. */
29363 {
29366 }
29367 #else
29369 "multiversioning needs ifunc which is not supported "
29371 #endif
29373 }
29375 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
29376 it to CHAIN. */
29378 static tree
29380 {
29381 tree attr_name;
29382 tree attr_arg_name;
29383 tree attr_args;
29384 tree attr;
29391 }
29393 /* Make the resolver function decl to dispatch the versions of
29394 a multi-versioned function, DEFAULT_DECL. Create an
29395 empty basic block in the resolver and store the pointer in
29396 EMPTY_BB. Return the decl of the resolver function. */
29398 static tree
29402 {
29407 /* IFUNC's have to be globally visible. So, if the default_decl is
29408 not, then the name of the IFUNC should be made unique. */
29412 /* Append the filename to the resolver function if the versions are
29413 not externally visible. This is because the resolver function has
29414 to be externally visible for the loader to find it. So, appending
29415 the filename will prevent conflicts with a resolver function from
29416 another module which is based on the same version name. */
29419 /* The resolver function should return a (void *). */
29430 /* IFUNC resolvers have to be externally visible. */
29434 /* Resolver is not external, body is generated. */
29444 {
29445 /* In this case, each translation unit with a call to this
29446 versioned function will put out a resolver. Ensure it
29447 is comdat to keep just one copy. */
29450 }
29451 /* Build result decl and add to function_decl. */
29467 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
29471 /* Create the alias for dispatch to resolver here. */
29472 /*cgraph_create_function_alias (dispatch_decl, decl);*/
29476 }
29478 /* Generate the dispatching code body to dispatch multi-versioned function
29479 DECL. The target hook is called to process the "target" attributes and
29480 provide the code to dispatch the right function at run-time. NODE points
29481 to the dispatcher decl whose body will be created. */
29483 static tree
29485 {
29486 tree resolver_decl;
29487 basic_block empty_bb;
29489 tree default_ver_decl;
29505 /* The first version in the chain corresponds to the default version. */
29508 /* node is going to be an alias, so remove the finalized bit. */
29522 {
29524 /* Check for virtual functions here again, as by this time it should
29525 have been determined if this function needs a vtable index or
29526 not. This happens for methods in derived classes that override
29527 virtual methods in base classes but are not explicitly marked as
29528 virtual. */
29533 }
29540 }
29541 /* This builds the processor_model struct type defined in
29542 libgcc/config/i386/cpuinfo.c */
29544 static tree
29546 {
29553 /* The first 3 fields are unsigned int. */
29555 {
29561 }
29563 /* The last field is an array of unsigned integers of size one. */
29574 }
29576 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
29578 static tree
29580 {
29581 tree new_decl;
29584 VAR_DECL,
29586 type);
29599 }
29601 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
29602 into an integer defined in libgcc/config/i386/cpuinfo.c */
29604 static tree
29606 {
29612 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
29613 enum processor_features
29614 {
29616 F_MMX,
29617 F_POPCNT,
29618 F_SSE,
29619 F_SSE2,
29620 F_SSE3,
29621 F_SSSE3,
29622 F_SSE4_1,
29623 F_SSE4_2,
29624 F_AVX,
29625 F_AVX2,
29626 F_MAX
29627 };
29629 /* These are the values for vendor types and cpu types and subtypes
29630 in cpuinfo.c. Cpu types and subtypes should be subtracted by
29631 the corresponding start value. */
29632 enum processor_model
29633 {
29635 M_AMD,
29636 M_CPU_TYPE_START,
29637 M_INTEL_ATOM,
29638 M_INTEL_CORE2,
29639 M_INTEL_COREI7,
29640 M_AMDFAM10H,
29641 M_AMDFAM15H,
29642 M_CPU_SUBTYPE_START,
29643 M_INTEL_COREI7_NEHALEM,
29644 M_INTEL_COREI7_WESTMERE,
29645 M_INTEL_COREI7_SANDYBRIDGE,
29646 M_AMDFAM10H_BARCELONA,
29647 M_AMDFAM10H_SHANGHAI,
29648 M_AMDFAM10H_ISTANBUL,
29649 M_AMDFAM15H_BDVER1,
29650 M_AMDFAM15H_BDVER2,
29651 M_AMDFAM15H_BDVER3
29652 };
29654 static struct _arch_names_table
29655 {
29658 }
29660 {
29677 };
29679 static struct _isa_names_table
29680 {
29683 }
29685 {
29697 };
29708 {
29709 /* *args must be a expr that can contain other EXPRS leading to a
29710 STRING_CST. */
29712 {
29715 }
29717 }
29722 {
29723 tree ref;
29724 tree field;
29725 tree final;
29728 unsigned int NUM_ARCH_NAMES
29737 {
29741 }
29746 /* CPU types are stored in the next field. */
29749 {
29752 }
29754 /* CPU subtypes are stored in the next field. */
29756 {
29759 }
29761 /* Get the appropriate field in __cpu_model. */
29765 /* Check the value. */
29769 }
29771 {
29772 tree ref;
29773 tree array_elt;
29774 tree field;
29775 tree final;
29778 unsigned int NUM_ISA_NAMES
29787 {
29791 }
29794 /* Get the last field, which is __cpu_features. */
29798 /* Get the appropriate field: __cpu_model.__cpu_features */
29802 /* Access the 0th element of __cpu_features array. */
29807 /* Return __cpu_model.__cpu_features[0] & field_val */
29811 }
29813 }
29815 static tree
29818 {
29820 {
29825 {
29828 }
29829 }
29831 #ifdef SUBTARGET_FOLD_BUILTIN
29833 #endif
29836 }
29838 /* Make builtins to detect cpu type and features supported. NAME is
29839 the builtin name, CODE is the builtin code, and FTYPE is the function
29840 type of the builtin. */
29842 static void
29845 {
29846 tree decl;
29847 tree type;
29855 }
29857 /* Make builtins to get CPU type and features supported. The created
29858 builtins are :
29860 __builtin_cpu_init (), to detect cpu type and features,
29861 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
29862 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
29863 */
29865 static void
29867 {
29874 }
29876 /* Internal method for ix86_init_builtins. */
29878 static void
29880 {
29892 sysv_va_ref =
29895 fnvoid_va_end_ms =
29897 fnvoid_va_start_ms =
29899 fnvoid_va_end_sysv =
29901 fnvoid_va_start_sysv =
29903 NULL_TREE);
29904 fnvoid_va_copy_ms =
29906 NULL_TREE);
29907 fnvoid_va_copy_sysv =
29923 }
29925 static void
29927 {
29930 /* The __float80 type. */
29933 {
29934 /* The __float80 type. */
29939 }
29942 /* The __float128 type. */
29948 /* This macro is built by i386-builtin-types.awk. */
29949 DEFINE_BUILTIN_PRIMITIVE_TYPES;
29950 }
29952 static void
29954 {
29955 tree t;
29959 /* Builtins to get CPU type and features. */
29962 /* TFmode support builtins. */
29968 /* We will expand them to normal call if SSE isn't available since
29969 they are used by libgcc. */
29988 #ifdef SUBTARGET_INIT_BUILTINS
29989 SUBTARGET_INIT_BUILTINS;
29990 #endif
29991 }
29993 /* Return the ix86 builtin for CODE. */
29995 static tree
29997 {
30002 }
30004 /* Errors in the source file can cause expand_expr to return const0_rtx
30005 where we expect a vector. To avoid crashing, use one of the vector
30006 clear instructions. */
30007 static rtx
30009 {
30013 }
30015 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
30017 static rtx
30019 {
30020 rtx pat;
30040 {
30044 }
30058 }
30060 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
30062 static rtx
30066 {
30067 rtx pat;
30075 rtx op;
30082 {
30162 }
30172 {
30179 {
30181 {
30184 {
30202 xop_rotl:
30204 {
30207 gcc_checking_assert
30209 }
30210 else
30211 {
30212 gcc_checking_assert
30223 }
30227 }
30228 }
30229 }
30230 else
30231 {
30232 non_constant:
30236 /* If we aren't optimizing, only allow one memory operand to be
30237 generated. */
30239 num_memory++;
30247 }
30251 }
30254 {
30265 else
30266 {
30272 }
30285 }
30292 }
30294 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
30295 insns with vec_merge. */
30297 static rtx
30299 rtx target)
30300 {
30301 rtx pat;
30328 }
30330 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
30332 static rtx
30335 {
30336 rtx pat;
30341 rtx op2;
30352 /* Swap operands if we have a comparison that isn't available in
30353 hardware. */
30355 {
30360 }
30380 }
30382 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
30384 static rtx
30386 rtx target)
30387 {
30388 rtx pat;
30402 /* Swap operands if we have a comparison that isn't available in
30403 hardware. */
30405 {
30409 }
30430 const0_rtx)));
30433 }
30435 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
30437 static rtx
30439 rtx target)
30440 {
30441 rtx pat;
30466 }
30468 static rtx
30471 {
30472 rtx pat;
30477 rtx op2;
30504 }
30506 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
30508 static rtx
30510 rtx target)
30511 {
30512 rtx pat;
30545 const0_rtx)));
30548 }
30550 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
30552 static rtx
30555 {
30556 rtx pat;
30594 {
30597 }
30600 {
30609 }
30611 {
30620 }
30621 else
30622 {
30629 }
30637 {
30642 emit_insn
30646 FLAGS_REG),
30647 const0_rtx)));
30649 }
30650 else
30652 }
30655 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
30657 static rtx
30660 {
30661 rtx pat;
30689 {
30692 }
30695 {
30704 }
30706 {
30715 }
30716 else
30717 {
30724 }
30732 {
30737 emit_insn
30741 FLAGS_REG),
30742 const0_rtx)));
30744 }
30745 else
30747 }
30749 /* Subroutine of ix86_expand_builtin to take care of insns with
30750 variable number of operands. */
30752 static rtx
30755 {
30760 struct
30761 {
30762 rtx op;
30774 {
31053 }
31058 {
31061 }
31064 {
31071 }
31072 else
31073 {
31076 }
31079 {
31086 {
31087 /* SIMD shift insns take either an 8-bit immediate or
31088 register as count. But builtin functions take int as
31089 count. If count doesn't match, we put it in register. */
31091 {
31095 }
31096 }
31098 {
31101 {
31155 {
31158 {
31161 }
31167 }
31169 }
31170 }
31171 else
31172 {
31176 /* If we aren't optimizing, only allow one memory operand to
31177 be generated. */
31179 num_memory++;
31182 {
31185 }
31186 else
31187 {
31190 }
31191 }
31195 }
31198 {
31215 }
31222 }
31224 /* Subroutine of ix86_expand_builtin to take care of special insns
31225 with variable number of operands. */
31227 static rtx
31230 {
31231 tree arg;
31234 struct
31235 {
31236 rtx op;
31246 {
31294 /* Reserve memory operand for target. */
31325 /* Reserve memory operand for target. */
31339 }
31344 {
31349 {
31352 }
31353 else
31356 }
31357 else
31358 {
31365 }
31368 {
31377 {
31379 {
31385 else
31388 }
31389 }
31390 else
31391 {
31393 {
31394 /* This must be the memory operand. */
31399 }
31400 else
31401 {
31402 /* This must be register. */
31409 }
31410 }
31414 }
31417 {
31432 }
31438 }
31440 /* Return the integer constant in ARG. Constrain it to be in the range
31441 of the subparts of VEC_TYPE; issue an error if not. */
31443 static int
31445 {
31450 {
31453 }
31456 }
31458 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31459 ix86_expand_vector_init. We DO have language-level syntax for this, in
31460 the form of (type){ init-list }. Except that since we can't place emms
31461 instructions from inside the compiler, we can't allow the use of MMX
31462 registers unless the user explicitly asks for it. So we do *not* define
31463 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
31464 we have builtins invoked by mmintrin.h that gives us license to emit
31465 these sorts of instructions. */
31467 static rtx
31469 {
31479 {
31482 }
31489 }
31491 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31492 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
31493 had a language-level syntax for referencing vector elements. */
31495 static rtx
31497 {
31501 rtx op0;
31521 }
31523 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31524 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
31525 a language-level syntax for referencing vector elements. */
31527 static rtx
31529 {
31553 /* OP0 is the source of these builtin functions and shouldn't be
31554 modified. Create a copy, use it and return it as target. */
31560 }
31562 /* Expand an expression EXP that calls a built-in function,
31563 with result going to TARGET if that's convenient
31564 (and in mode MODE if that's convenient).
31565 SUBTARGET may be used as the target for computing one of EXP's operands.
31566 IGNORE is nonzero if the value is to be ignored. */
31568 static rtx
31572 {
31582 /* For CPU builtins that can be folded, fold first and expand the fold. */
31584 {
31586 {
31587 /* Make it call __cpu_indicator_init in libgcc. */
31593 }
31596 {
31601 }
31602 }
31604 /* Determine whether the builtin function is available under the current ISA.
31605 Originally the builtin was not created if it wasn't applicable to the
31606 current ISA based on the command line switches. With function specific
31607 options, we need to check in the context of the function making the call
31608 whether it is supported. */
31611 {
31617 else
31618 {
31622 }
31624 }
31627 {
31631 ? CODE_FOR_mmx_maskmovq
31633 /* Note the arg order is different from the operand order. */
31734 {
31735 REAL_VALUE_TYPE inf;
31736 rtx tmp;
31748 }
31758 {
31764 insn = (TARGET_64BIT
31768 }
31770 {
31771 insn = (TARGET_64BIT
31775 }
31776 else
31777 {
31780 insn = (TARGET_64BIT
31788 {
31791 }
31793 }
31799 {
31804 }
31814 {
31829 }
31835 {
31838 }
31858 {
31861 }
31867 {
31871 {
31892 }
31897 }
31898 else
31899 {
31901 {
31913 }
31915 }
31945 ? CODE_FOR_tbm_bextri_si
31948 {
31951 }
31952 else
31953 {
31962 }
31978 rdrand_step:
31985 {
31988 }
31994 /* Emit SImode conditional move. */
31996 {
31999 }
32002 else
32009 const0_rtx);
32028 rdseed_step:
32035 {
32038 }
32044 const0_rtx);
32062 addcarryx:
32070 /* Generate CF from input operand. */
32075 /* Gen ADCX instruction to compute X+Y+CF. */
32090 /* Store the result. */
32093 {
32096 }
32099 /* Return current CF value. */
32168 gather_gen:
32179 /* Note the arg order is different from the operand order. */
32188 else
32193 {
32199 }
32202 {
32207 else
32217 }
32219 /* Force memory operand only with base register here. But we
32220 don't want to do it on memory operand for other builtin
32221 functions. */
32233 {
32236 }
32238 /* Optimize. If mask is known to have all high bits set,
32239 replace op0 with pc_rtx to signal that the instruction
32240 overwrites the whole destination and doesn't use its
32241 previous contents. */
32243 {
32245 {
32248 {
32252 negative++;
32255 negative++;
32256 }
32259 }
32261 {
32262 /* Recognize also when mask is like:
32263 __v2df src = _mm_setzero_pd ();
32264 __v2df mask = _mm_cmpeq_pd (src, src);
32265 or
32266 __v8sf src = _mm256_setzero_ps ();
32267 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
32268 as that is a cheaper way to load all ones into
32269 a register than having to load a constant from
32270 memory. */
32273 {
32278 {
32285 /* FALLTHRU */
32295 }
32296 }
32297 }
32298 }
32307 {
32314 else
32316 }
32317 else
32328 {
32331 }
32337 }
32350 {
32354 /* Emit a normal call if SSE isn't available. */
32358 }
32383 }
32385 /* Returns a function decl for a vectorized version of the builtin function
32386 with builtin function code FN and the result vector type TYPE, or NULL_TREE
32387 if it is not available. */
32389 static tree
32391 tree type_in)
32392 {
32408 {
32411 {
32416 }
32421 {
32426 }
32432 /* The round insn does not trap on denormals. */
32437 {
32442 }
32448 /* The round insn does not trap on denormals. */
32453 {
32458 }
32464 /* The round insn does not trap on denormals. */
32469 {
32474 }
32480 /* The round insn does not trap on denormals. */
32485 {
32490 }
32497 {
32502 }
32509 {
32514 }
32520 /* The round insn does not trap on denormals. */
32525 {
32530 }
32536 /* The round insn does not trap on denormals. */
32541 {
32546 }
32551 {
32556 }
32561 {
32566 }
32570 /* The round insn does not trap on denormals. */
32575 {
32580 }
32584 /* The round insn does not trap on denormals. */
32589 {
32594 }
32598 /* The round insn does not trap on denormals. */
32603 {
32608 }
32612 /* The round insn does not trap on denormals. */
32617 {
32622 }
32626 /* The round insn does not trap on denormals. */
32631 {
32636 }
32640 /* The round insn does not trap on denormals. */
32645 {
32650 }
32654 /* The round insn does not trap on denormals. */
32659 {
32664 }
32668 /* The round insn does not trap on denormals. */
32673 {
32678 }
32682 /* The round insn does not trap on denormals. */
32687 {
32692 }
32696 /* The round insn does not trap on denormals. */
32701 {
32706 }
32711 {
32716 }
32721 {
32726 }
32731 }
32733 /* Dispatch to a handler for a vectorization library. */
32736 type_in);
32739 }
32741 /* Handler for an SVML-style interface to
32742 a library with vectorized intrinsics. */
32744 static tree
32746 {
32754 /* The SVML is suitable for unsafe math only. */
32767 {
32814 }
32823 {
32826 }
32827 else
32830 /* Convert to uppercase. */
32835 args;
32837 arity++;
32841 else
32844 /* Build a function declaration for the vectorized function. */
32853 }
32855 /* Handler for an ACML-style interface to
32856 a library with vectorized intrinsics. */
32858 static tree
32860 {
32868 /* The ACML is 64bits only and suitable for unsafe math only as
32869 it does not correctly support parts of IEEE with the required
32870 precision such as denormals. */
32884 {
32914 }
32921 args;
32923 arity++;
32927 else
32930 /* Build a function declaration for the vectorized function. */
32939 }
32941 /* Returns a decl of a function that implements gather load with
32942 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
32943 Return NULL_TREE if it is not available. */
32945 static tree
32948 {
32964 /* v*gather* insn sign extends index to pointer mode. */
32976 {
33003 }
33006 }
33008 /* Returns a code for a target-specific builtin that implements
33009 reciprocal of the function, or NULL_TREE if not available. */
33011 static tree
33014 {
33021 /* Machine dependent builtins. */
33023 {
33024 /* Vectorized version of sqrt to rsqrt conversion. */
33033 }
33034 else
33035 /* Normal builtins. */
33037 {
33038 /* Sqrt to rsqrt conversion. */
33044 }
33045 }
33046 \f
33047 /* Helper for avx_vpermilps256_operand et al. This is also used by
33048 the expansion functions to turn the parallel back into a mask.
33049 The return value is 0 for no match and the imm8+1 for a match. */
33051 int
33053 {
33061 /* Validate that all of the elements are constants, and not totally
33062 out of range. Copy the data into an integral array to make the
33063 subsequent checks easier. */
33065 {
33075 }
33078 {
33080 /* In the 256-bit DFmode case, we can only move elements within
33081 a 128-bit lane. */
33083 {
33087 }
33089 {
33093 }
33097 /* In the 256-bit SFmode case, we have full freedom of movement
33098 within the low 128-bit lane, but the high 128-bit lane must
33099 mirror the exact same pattern. */
33104 /* FALLTHRU */
33108 /* In the 128-bit case, we've full freedom in the placement of
33109 the elements from the source operand. */
33116 }
33118 /* Make sure success has a non-zero value by adding one. */
33120 }
33122 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
33123 the expansion functions to turn the parallel back into a mask.
33124 The return value is 0 for no match and the imm8+1 for a match. */
33126 int
33128 {
33136 /* Validate that all of the elements are constants, and not totally
33137 out of range. Copy the data into an integral array to make the
33138 subsequent checks easier. */
33140 {
33150 }
33152 /* Validate that the halves of the permute are halves. */
33160 /* Reconstruct the mask. */
33162 {
33168 }
33170 /* Make sure success has a non-zero value by adding one. */
33172 }
33173 \f
33174 /* Store OPERAND to the memory after reload is completed. This means
33175 that we can't easily use assign_stack_local. */
33176 rtx
33178 {
33179 rtx result;
33183 {
33186 stack_pointer_rtx,
33189 }
33191 {
33193 {
33197 /* FALLTHRU */
33203 stack_pointer_rtx)),
33204 operand));
33208 }
33210 }
33211 else
33212 {
33214 {
33216 {
33223 stack_pointer_rtx)),
33229 stack_pointer_rtx)),
33231 }
33234 /* Store HImodes as SImodes. */
33236 /* FALLTHRU */
33242 stack_pointer_rtx)),
33243 operand));
33247 }
33249 }
33251 }
33253 /* Free operand from the memory. */
33254 void
33256 {
33258 {
33263 else
33265 /* Use LEA to deallocate stack space. In peephole2 it will be converted
33266 to pop or add instruction if registers are available. */
33270 }
33271 }
33273 /* Return a register priority for hard reg REGNO. */
33274 static int
33276 {
33277 /* ebp and r13 as the base always wants a displacement, r12 as the
33278 base always wants an index. So discourage their usage in an
33279 address. */
33284 /* New x86-64 int registers result in bigger code size. Discourage
33285 them. */
33288 /* New x86-64 SSE registers result in bigger code size. Discourage
33289 them. */
33292 /* Usage of AX register results in smaller code. Prefer it. */
33296 }
33298 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
33300 Put float CONST_DOUBLE in the constant pool instead of fp regs.
33301 QImode must go into class Q_REGS.
33302 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
33303 movdf to do mem-to-mem moves through integer regs. */
33305 static reg_class_t
33307 {
33310 /* We're only allowed to return a subclass of CLASS. Many of the
33311 following checks fail for NO_REGS, so eliminate that early. */
33315 /* All classes can load zeros. */
33319 /* Force constants into memory if we are loading a (nonzero) constant into
33320 an MMX or SSE register. This is because there are no MMX/SSE instructions
33321 to load from a constant. */
33326 /* Prefer SSE regs only, if we can use them for math. */
33330 /* Floating-point constants need more complex checks. */
33332 {
33333 /* General regs can load everything. */
33337 /* Floats can load 0 and 1 plus some others. Note that we eliminated
33338 zero above. We only want to wind up preferring 80387 registers if
33339 we plan on doing computation with them. */
33342 {
33343 /* Limit class to non-sse. */
33352 }
33355 }
33357 /* Generally when we see PLUS here, it's the function invariant
33358 (plus soft-fp const_int). Which can only be computed into general
33359 regs. */
33363 /* QImode constants are easy to load, but non-constant QImode data
33364 must go into Q_REGS. */
33366 {
33372 }
33375 }
33377 /* Discourage putting floating-point values in SSE registers unless
33378 SSE math is being used, and likewise for the 387 registers. */
33379 static reg_class_t
33381 {
33384 /* Restrict the output reload class to the register bank that we are doing
33385 math on. If we would like not to return a subset of CLASS, reject this
33386 alternative: if reload cannot do this, it will still use its choice. */
33392 {
33397 else
33399 }
33402 }
33404 static reg_class_t
33407 {
33408 /* Double-word spills from general registers to non-offsettable memory
33409 references (zero-extended addresses) require special handling. */
33415 {
33417 ? CODE_FOR_reload_noff_load
33419 /* Add the cost of moving address to a temporary. */
33423 }
33425 /* QImode spills from non-QI registers require
33426 intermediate register on 32bit targets. */
33435 {
33440 else
33446 /* Return Q_REGS if the operand is in memory. */
33449 }
33451 /* This condition handles corner case where an expression involving
33452 pointers gets vectorized. We're trying to use the address of a
33453 stack slot as a vector initializer.
33455 (set (reg:V2DI 74 [ vect_cst_.2 ])
33456 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
33458 Eventually frame gets turned into sp+offset like this:
33460 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33461 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33462 (const_int 392 [0x188]))))
33464 That later gets turned into:
33466 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33467 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33468 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
33470 We'll have the following reload recorded:
33472 Reload 0: reload_in (DI) =
33473 (plus:DI (reg/f:DI 7 sp)
33474 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
33475 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33476 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
33477 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
33478 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33479 reload_reg_rtx: (reg:V2DI 22 xmm1)
33481 Which isn't going to work since SSE instructions can't handle scalar
33482 additions. Returning GENERAL_REGS forces the addition into integer
33483 register and reload can handle subsequent reloads without problems. */
33491 }
33493 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
33495 static bool
33497 {
33499 {
33514 }
33517 }
33519 /* If we are copying between general and FP registers, we need a memory
33520 location. The same is true for SSE and MMX registers.
33522 To optimize register_move_cost performance, allow inline variant.
33524 The macro can't work reliably when one of the CLASSES is class containing
33525 registers from multiple units (SSE, MMX, integer). We avoid this by never
33526 combining those units in single alternative in the machine description.
33527 Ensure that this constraint holds to avoid unexpected surprises.
33529 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
33530 enforce these sanity checks. */
33535 {
33542 {
33545 }
33550 /* ??? This is a lie. We do have moves between mmx/general, and for
33551 mmx/sse2. But by saying we need secondary memory we discourage the
33552 register allocator from using the mmx registers unless needed. */
33557 {
33558 /* SSE1 doesn't have any direct moves from other classes. */
33562 /* If the target says that inter-unit moves are more expensive
33563 than moving through memory, then don't generate them. */
33567 /* Between SSE and general, we have moves no larger than word size. */
33570 }
33573 }
33575 bool
33578 {
33580 }
33582 /* Implement the TARGET_CLASS_MAX_NREGS hook.
33584 On the 80386, this is the size of MODE in words,
33585 except in the FP regs, where a single reg is always enough. */
33587 static unsigned char
33589 {
33591 {
33596 else
33598 }
33599 else
33600 {
33603 else
33605 }
33606 }
33608 /* Return true if the registers in CLASS cannot represent the change from
33609 modes FROM to TO. */
33611 bool
33614 {
33618 /* x87 registers can't do subreg at all, as all values are reformatted
33619 to extended precision. */
33624 {
33625 /* Vector registers do not support QI or HImode loads. If we don't
33626 disallow a change to these modes, reload will assume it's ok to
33627 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
33628 the vec_dupv4hi pattern. */
33632 /* Vector registers do not support subreg with nonzero offsets, which
33633 are otherwise valid for integer registers. Since we can't see
33634 whether we have a nonzero offset from here, prohibit all
33635 nonparadoxical subregs changing size. */
33638 }
33641 }
33643 /* Return the cost of moving data of mode M between a
33644 register and memory. A value of 2 is the default; this cost is
33645 relative to those in `REGISTER_MOVE_COST'.
33647 This function is used extensively by register_move_cost that is used to
33648 build tables at startup. Make it inline in this case.
33649 When IN is 2, return maximum of in and out move cost.
33651 If moving between registers and memory is more expensive than
33652 between two registers, you should define this macro to express the
33653 relative cost.
33655 Model also increased moving costs of QImode registers in non
33656 Q_REGS classes.
33657 */
33661 {
33664 {
33667 {
33679 }
33683 }
33685 {
33688 {
33700 }
33704 }
33706 {
33709 {
33718 }
33722 }
33724 {
33727 {
33733 else
33738 }
33739 else
33740 {
33745 else
33747 }
33754 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
33761 else
33765 }
33766 }
33768 static int
33771 {
33773 }
33776 /* Return the cost of moving data from a register in class CLASS1 to
33777 one in class CLASS2.
33779 It is not required that the cost always equal 2 when FROM is the same as TO;
33780 on some machines it is expensive to move between registers if they are not
33781 general registers. */
33783 static int
33785 reg_class_t class2_i)
33786 {
33790 /* In case we require secondary memory, compute cost of the store followed
33791 by load. In order to avoid bad register allocation choices, we need
33792 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
33795 {
33801 /* In case of copying from general_purpose_register we may emit multiple
33802 stores followed by single load causing memory size mismatch stall.
33803 Count this as arbitrarily high cost of 20. */
33808 /* In the case of FP/MMX moves, the registers actually overlap, and we
33809 have to switch modes in order to treat them differently. */
33815 }
33817 /* Moves between SSE/MMX and integer unit are expensive. */
33821 /* ??? By keeping returned value relatively high, we limit the number
33822 of moves between integer and MMX/SSE registers for all targets.
33823 Additionally, high value prevents problem with x86_modes_tieable_p(),
33824 where integer modes in MMX/SSE registers are not tieable
33825 because of missing QImode and HImode moves to, from or between
33826 MMX/SSE registers. */
33836 }
33838 /* Return TRUE if hard register REGNO can hold a value of machine-mode
33839 MODE. */
33841 bool
33843 {
33844 /* Flags and only flags can only hold CCmode values. */
33854 {
33855 /* We implement the move patterns for all vector modes into and
33856 out of SSE registers, even when no operation instructions
33857 are available. OImode move is available only when AVX is
33858 enabled. */
33865 }
33867 {
33868 /* We implement the move patterns for 3DNOW modes even in MMX mode,
33869 so if the register is available at all, then we can move data of
33870 the given mode into or out of it. */
33873 }
33876 {
33877 /* Take care for QImode values - they can be in non-QI regs,
33878 but then they do cause partial register stalls. */
33884 }
33885 /* We handle both integer and floats in the general purpose registers. */
33892 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
33893 on to use that value in smaller contexts, this can easily force a
33894 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
33895 supporting DImode, allow it. */
33900 }
33902 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
33903 tieable integer mode. */
33905 static bool
33907 {
33909 {
33922 }
33923 }
33925 /* Return true if MODE1 is accessible in a register that can hold MODE2
33926 without copying. That is, all register classes that can hold MODE2
33927 can also hold MODE1. */
33929 bool
33931 {
33939 /* MODE2 being XFmode implies fp stack or general regs, which means we
33940 can tie any smaller floating point modes to it. Note that we do not
33941 tie this with TFmode. */
33945 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
33946 that we can tie it with SFmode. */
33950 /* If MODE2 is only appropriate for an SSE register, then tie with
33951 any other mode acceptable to SSE registers. */
33961 /* If MODE2 is appropriate for an MMX register, then tie
33962 with any other mode acceptable to MMX registers. */
33969 }
33971 /* Return the cost of moving between two registers of mode MODE. */
33973 static int
33975 {
33979 {
34010 }
34012 /* Return the cost of moving between two registers of mode MODE,
34013 assuming that the move will be in pieces of at most UNITS bytes. */
34015 }
34017 /* Compute a (partial) cost for rtx X. Return true if the complete
34018 cost has been computed, and false if subexpressions should be
34019 scanned. In either case, *TOTAL contains the cost result. */
34021 static bool
34024 {
34031 {
34035 {
34038 }
34050 && (!TARGET_64BIT
34055 else
34061 {
34064 }
34066 {
34076 }
34078 {
34081 {
34090 }
34091 }
34092 /* Fall back to (MEM (SYMBOL_REF)), since that's where
34093 it'll probably end up. Add a penalty for size. */
34100 /* The zero extensions is often completely free on x86_64, so make
34101 it as cheap as possible. */
34107 else
34119 {
34122 {
34125 }
34128 {
34131 }
34132 }
34133 /* FALLTHRU */
34140 {
34141 /* ??? Should be SSE vector operation cost. */
34142 /* At least for published AMD latencies, this really is the same
34143 as the latency for a simple fpu operation like fabs. */
34144 /* V*QImode is emulated with 1-11 insns. */
34146 {
34149 {
34150 /* For XOP we use vpshab, which requires a broadcast of the
34151 value to the variable shift insn. For constants this
34152 means a V16Q const in mem; even when we can perform the
34153 shift with one insn set the cost to prefer paddb. */
34155 {
34160 }
34162 }
34166 }
34167 else
34169 }
34171 {
34173 {
34176 else
34178 }
34179 else
34180 {
34183 else
34185 }
34186 }
34187 else
34188 {
34191 else
34193 }
34197 {
34198 rtx sub;
34203 /* ??? SSE scalar/vector cost should be used here. */
34204 /* ??? Bald assumption that fma has the same cost as fmul. */
34208 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
34219 }
34223 {
34224 /* ??? SSE scalar cost should be used here. */
34227 }
34229 {
34232 }
34234 {
34235 /* ??? SSE vector cost should be used here. */
34238 }
34240 {
34241 /* V*QImode is emulated with 7-13 insns. */
34243 {
34250 }
34251 /* V*DImode is emulated with 5-8 insns. */
34253 {
34256 else
34258 }
34259 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
34260 insns, including two PMULUDQ. */
34263 else
34266 }
34267 else
34268 {
34273 {
34276 nbits++;
34277 }
34278 else
34279 /* This is arbitrary. */
34282 /* Compute costs correctly for widening multiplication. */
34286 {
34293 {
34297 else
34299 }
34303 }
34311 }
34318 /* ??? SSE cost should be used here. */
34323 /* ??? SSE vector cost should be used here. */
34325 else
34332 {
34337 {
34340 {
34348 }
34349 }
34352 {
34355 {
34361 }
34362 }
34364 {
34372 }
34373 }
34374 /* FALLTHRU */
34378 {
34379 /* ??? SSE cost should be used here. */
34382 }
34384 {
34387 }
34389 {
34390 /* ??? SSE vector cost should be used here. */
34393 }
34394 /* FALLTHRU */
34401 {
34408 }
34409 /* FALLTHRU */
34413 {
34414 /* ??? SSE cost should be used here. */
34417 }
34419 {
34422 }
34424 {
34425 /* ??? SSE vector cost should be used here. */
34428 }
34429 /* FALLTHRU */
34433 {
34434 /* ??? Should be SSE vector operation cost. */
34435 /* At least for published AMD latencies, this really is the same
34436 as the latency for a simple fpu operation like fabs. */
34438 }
34441 else
34450 {
34451 /* This kind of construct is implemented using test[bwl].
34452 Treat it as if we had an AND. */
34457 }
34467 /* ??? SSE cost should be used here. */
34472 /* ??? SSE vector cost should be used here. */
34478 /* ??? SSE cost should be used here. */
34483 /* ??? SSE vector cost should be used here. */
34496 /* ??? Assume all of these vector manipulation patterns are
34497 recognizable. In which case they all pretty much have the
34498 same cost. */
34504 }
34505 }
34507 #if TARGET_MACHO
34511 /* Given a symbol name and its associated stub, write out the
34512 definition of the stub. */
34514 void
34516 {
34521 /* For 64-bit we shouldn't get here. */
34524 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
34541 else
34548 {
34550 }
34552 {
34553 /* PIC stub. */
34554 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34560 }
34561 else
34564 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
34565 it needs no stub-binding-helper. */
34572 {
34575 }
34576 else
34581 /* N.B. Keep the correspondence of these
34582 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
34583 old-pic/new-pic/non-pic stubs; altering this will break
34584 compatibility with existing dylibs. */
34586 {
34587 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34589 }
34590 else
34591 /* 16-byte -mdynamic-no-pic stub. */
34597 }
34600 /* Order the registers for register allocator. */
34602 void
34604 {
34608 /* First allocate the local general purpose registers. */
34613 /* Global general purpose registers. */
34618 /* x87 registers come first in case we are doing FP math
34619 using them. */
34624 /* SSE registers. */
34630 /* x87 registers. */
34638 /* Initialize the rest of array as we do not allocate some registers
34639 at all. */
34642 }
34644 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
34645 in struct attribute_spec handler. */
34646 static tree
34648 tree args,
34651 {
34656 {
34658 name);
34661 }
34663 {
34665 name);
34668 }
34670 {
34671 tree cst;
34675 {
34678 name);
34680 }
34683 {
34686 name);
34688 }
34691 }
34694 }
34696 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
34697 struct attribute_spec.handler. */
34698 static tree
34700 tree args ATTRIBUTE_UNUSED,
34702 {
34707 {
34709 name);
34712 }
34714 /* Can combine regparm with all attributes but fastcall. */
34716 {
34718 {
34720 }
34723 }
34725 {
34727 {
34729 }
34732 }
34735 }
34737 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
34738 struct attribute_spec.handler. */
34739 static tree
34741 tree args ATTRIBUTE_UNUSED,
34743 {
34746 {
34749 }
34750 else
34754 {
34756 name);
34758 }
34764 {
34766 name);
34768 }
34771 }
34773 static tree
34775 tree args ATTRIBUTE_UNUSED,
34777 {
34779 {
34781 name);
34783 }
34785 }
34787 static bool
34789 {
34793 }
34795 /* Returns an expression indicating where the this parameter is
34796 located on entry to the FUNCTION. */
34798 static rtx
34800 {
34806 {
34811 else
34814 }
34819 {
34826 {
34831 }
34832 else
34833 {
34836 {
34842 }
34843 }
34845 }
34849 }
34851 /* Determine whether x86_output_mi_thunk can succeed. */
34853 static bool
34855 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
34857 {
34858 /* 64-bit can handle anything. */
34862 /* For 32-bit, everything's fine if we have one free register. */
34866 /* Need a free register for vcall_offset. */
34870 /* Need a free register for GOT references. */
34874 /* Otherwise ok. */
34876 }
34878 /* Output the assembler code for a thunk function. THUNK_DECL is the
34879 declaration for the thunk function itself, FUNCTION is the decl for
34880 the target function. DELTA is an immediate constant offset to be
34881 added to THIS. If VCALL_OFFSET is nonzero, the word at
34882 *(*this + vcall_offset) should be added to THIS. */
34884 static void
34888 {
34895 else
34896 {
34902 else
34904 }
34908 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
34909 pull it in now and let DELTA benefit. */
34913 {
34914 /* Put the this parameter into %eax. */
34917 }
34918 else
34921 /* Adjust the this parameter by a fixed constant. */
34923 {
34928 {
34930 {
34934 }
34935 }
34938 }
34940 /* Adjust the this parameter by a value stored in the vtable. */
34942 {
34952 /* Adjust the this parameter. */
34956 {
34960 }
34967 vcall_mem));
34968 else
34970 }
34972 /* If necessary, drop THIS back to its stack slot. */
34978 {
34981 ;
34982 else
34983 {
34987 }
34988 }
34989 else
34990 {
34992 ;
34993 #if TARGET_MACHO
34995 {
34998 }
35000 else
35001 {
35008 }
35009 }
35011 /* Our sibling call patterns do not allow memories, because we have no
35012 predicate that can distinguish between frame and non-frame memory.
35013 For our purposes here, we can get away with (ab)using a jump pattern,
35014 because we're going to do no optimization. */
35017 else
35018 {
35024 {
35030 }
35036 }
35039 /* Emit just enough of rest_of_compilation to get the insns emitted.
35040 Note that use_thunk calls assemble_start_function et al. */
35046 }
35048 static void
35050 {
35052 #if TARGET_MACHO
35054 #endif
35061 }
35063 int
35065 {
35077 }
35079 /* Output assembler code to FILE to increment profiler label # LABELNO
35080 for profiling a function entry. */
35081 void
35083 {
35088 {
35089 #ifndef NO_PROFILE_COUNTERS
35091 #endif
35095 else
35097 }
35099 {
35100 #ifndef NO_PROFILE_COUNTERS
35103 #endif
35105 }
35106 else
35107 {
35108 #ifndef NO_PROFILE_COUNTERS
35111 #endif
35113 }
35114 }
35116 /* We don't have exact information about the insn sizes, but we may assume
35117 quite safely that we are informed about all 1 byte insns and memory
35118 address sizes. This is enough to eliminate unnecessary padding in
35119 99% of cases. */
35121 static int
35123 {
35129 /* Discard alignments we've emit and jump instructions. */
35136 /* Important case - calls are always 5 bytes.
35137 It is common to have many calls in the row. */
35146 /* For normal instructions we rely on get_attr_length being exact,
35147 with a few exceptions. */
35149 {
35153 {
35163 /* Otherwise trust get_attr_length. */
35165 }
35170 }
35173 else
35175 }
35177 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35179 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
35180 window. */
35182 static void
35184 {
35189 /* Look for all minimal intervals of instructions containing 4 jumps.
35190 The intervals are bounded by START and INSN. NBYTES is the total
35191 size of instructions in the interval including INSN and not including
35192 START. When the NBYTES is smaller than 16 bytes, it is possible
35193 that the end of START and INSN ends up in the same 16byte page.
35195 The smallest offset in the page INSN can start is the case where START
35196 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
35197 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
35198 */
35200 {
35204 {
35210 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
35211 already in the current 16 byte page, because otherwise
35212 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
35213 bytes to reach 16 byte boundary. */
35221 {
35223 {
35230 else
35233 }
35234 }
35236 }
35247 njumps++;
35248 else
35252 {
35259 else
35262 }
35269 {
35276 }
35277 }
35278 }
35279 #endif
35281 /* AMD Athlon works faster
35282 when RET is not destination of conditional jump or directly preceded
35283 by other jump instruction. We avoid the penalty by inserting NOP just
35284 before the RET instructions in such cases. */
35285 static void
35287 {
35288 edge e;
35289 edge_iterator ei;
35292 {
35295 rtx prev;
35305 {
35306 edge e;
35307 edge_iterator ei;
35313 }
35315 {
35321 /* Empty functions get branch mispredict even when
35322 the jump destination is not visible to us. */
35325 }
35327 {
35330 }
35331 }
35332 }
35334 /* Count the minimum number of instructions in BB. Return 4 if the
35335 number of instructions >= 4. */
35337 static int
35339 {
35340 rtx insn;
35343 /* Count number of instructions in this block. Return 4 if the number
35344 of instructions >= 4. */
35346 {
35347 /* Only happen in exit blocks. */
35355 {
35356 insn_count++;
35359 }
35360 }
35363 }
35366 /* Count the minimum number of instructions in code path in BB.
35367 Return 4 if the number of instructions >= 4. */
35369 static int
35371 {
35372 edge e;
35373 edge_iterator ei;
35376 /* Only bother counting instructions along paths with no
35377 more than 2 basic blocks between entry and exit. Given
35378 that BB has an edge to exit, determine if a predecessor
35379 of BB has an edge from entry. If so, compute the number
35380 of instructions in the predecessor block. If there
35381 happen to be multiple such blocks, compute the minimum. */
35384 {
35385 edge prev_e;
35386 edge_iterator prev_ei;
35389 {
35392 }
35394 {
35396 {
35401 }
35402 }
35403 }
35409 }
35411 /* Pad short function to 4 instructions. */
35413 static void
35415 {
35416 edge e;
35417 edge_iterator ei;
35420 {
35423 {
35426 /* Pad short function. */
35428 {
35431 /* Find epilogue. */
35440 /* Two NOPs count as one instruction. */
35443 }
35444 }
35445 }
35446 }
35448 /* Implement machine specific optimizations. We implement padding of returns
35449 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
35450 static void
35452 {
35453 /* We are freeing block_for_insn in the toplev to keep compatibility
35454 with old MDEP_REORGS that are not CFG based. Recompute it now. */
35458 {
35463 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35466 #endif
35467 }
35468 }
35470 /* Return nonzero when QImode register that must be represented via REX prefix
35471 is used. */
35472 bool
35474 {
35482 }
35484 /* Return nonzero when P points to register encoded via REX prefix.
35485 Called via for_each_rtx. */
35486 static int
35488 {
35494 }
35496 /* Return true when INSN mentions register that must be encoded using REX
35497 prefix. */
35498 bool
35500 {
35503 }
35505 /* If profitable, negate (without causing overflow) integer constant
35506 of mode MODE at location LOC. Return true in this case. */
35507 bool
35509 {
35510 HOST_WIDE_INT val;
35516 {
35518 /* DImode x86_64 constants must fit in 32 bits. */
35531 }
35533 /* Avoid overflows. */
35539 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
35540 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
35543 {
35546 }
35549 }
35551 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
35552 optabs would emit if we didn't have TFmode patterns. */
35554 void
35556 {
35590 }
35591 \f
35592 /* AVX2 does support 32-byte integer vector operations,
35593 thus the longest vector we are faced with is V32QImode. */
35594 #define MAX_VECT_LEN 32
35596 struct expand_vec_perm_d
35597 {
35604 };
35610 /* Get a vector mode of the same size as the original but with elements
35611 twice as wide. This is only guaranteed to apply to integral vectors. */
35615 {
35616 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
35621 }
35623 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35624 with all elements equal to VAR. Return true if successful. */
35626 static bool
35629 {
35633 {
35638 /* FALLTHRU */
35648 {
35651 /* First attempt to recognize VAL as-is. */
35655 {
35656 rtx seq;
35657 /* If that fails, force VAL into a register. */
35668 }
35669 }
35676 {
35677 rtx x;
35684 }
35694 {
35698 permute:
35706 /* Extend to SImode using a paradoxical SUBREG. */
35710 /* Insert the SImode value as low element of a V4SImode vector. */
35718 }
35726 widen:
35727 /* Replicate the value once into the next wider mode and recurse. */
35728 {
35730 rtx x;
35746 }
35750 {
35759 }
35764 }
35765 }
35767 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35768 whose ONE_VAR element is VAR, and other elements are zero. Return true
35769 if successful. */
35771 static bool
35774 {
35776 rtx new_target;
35781 {
35783 /* For SSE4.1, we normally use vector set. But if the second
35784 element is zero and inter-unit moves are OK, we use movq
35785 instead. */
35786 use_vector_set = (TARGET_64BIT
35787 && TARGET_SSE4_1
35788 && !(TARGET_INTER_UNIT_MOVES
35810 /* Use ix86_expand_vector_set in 64bit mode only. */
35815 }
35818 {
35823 }
35826 {
35831 /* FALLTHRU */
35846 else
35853 {
35854 /* We need to shuffle the value to the correct position, so
35855 create a new pseudo to store the intermediate result. */
35857 /* With SSE2, we can use the integer shuffle insns. */
35859 {
35861 const1_rtx,
35868 }
35870 /* Otherwise convert the intermediate result to V4SFmode and
35871 use the SSE1 shuffle instructions. */
35873 {
35876 }
35877 else
35881 const1_rtx,
35890 }
35905 widen:
35909 /* Zero extend the variable element to SImode and recurse. */
35922 }
35923 }
35925 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35926 consisting of the values in VALS. It is known that all elements
35927 except ONE_VAR are constants. Return true if successful. */
35929 static bool
35932 {
35942 {
35947 /* For the two element vectors, it's just as easy to use
35948 the general case. */
35952 /* Use ix86_expand_vector_set in 64bit mode only. */
35974 widen:
35975 /* There's no way to set one QImode entry easily. Combine
35976 the variable value with its adjacent constant value, and
35977 promote to an HImode set. */
35980 {
35985 }
35986 else
35987 {
35990 }
36004 }
36009 }
36011 /* A subroutine of ix86_expand_vector_init_general. Use vector
36012 concatenate to handle the most general case: all values variable,
36013 and none identical. */
36015 static void
36018 {
36021 rtvec v;
36025 {
36028 {
36061 }
36074 {
36089 }
36094 {
36105 }
36108 half:
36109 /* FIXME: We process inputs backward to help RA. PR 36222. */
36113 {
36118 }
36122 {
36125 {
36129 }
36132 }
36133 else
36139 }
36140 }
36142 /* A subroutine of ix86_expand_vector_init_general. Use vector
36143 interleave to handle the most general case: all values variable,
36144 and none identical. */
36146 static void
36149 {
36158 {
36179 }
36182 {
36183 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
36187 /* Insert the SImode value as low element of V4SImode vector. */
36191 op0),
36193 const1_rtx);
36196 /* Cast the V4SImode vector back to a vector in orignal mode. */
36200 /* Load even elements into the second positon. */
36204 const1_rtx));
36206 /* Cast vector to FIRST_IMODE vector. */
36209 }
36211 /* Interleave low FIRST_IMODE vectors. */
36213 {
36217 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
36220 }
36222 /* Interleave low SECOND_IMODE vectors. */
36224 {
36227 {
36232 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
36233 vector. */
36236 }
36239 /* FALLTHRU */
36246 /* Cast the SECOND_IMODE vector back to a vector on original
36247 mode. */
36254 }
36255 }
36257 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
36258 all values variable, and none identical. */
36260 static void
36263 {
36269 {
36274 /* FALLTHRU */
36298 half:
36315 /* FALLTHRU */
36321 /* Don't use ix86_expand_vector_init_interleave if we can't
36322 move from GPR to SSE register directly. */
36338 }
36340 {
36352 {
36356 {
36362 else
36363 {
36368 }
36369 }
36372 }
36377 {
36383 }
36385 {
36391 }
36392 else
36394 }
36395 }
36397 /* Initialize vector TARGET via VALS. Suppress the use of MMX
36398 instructions unless MMX_OK is true. */
36400 void
36402 {
36409 rtx x;
36412 {
36422 }
36424 /* Constants are best loaded from the constant pool. */
36426 {
36429 }
36431 /* If all values are identical, broadcast the value. */
36437 /* Values where only one field is non-constant are best loaded from
36438 the pool and overwritten via move later. */
36440 {
36444 one_var))
36449 }
36452 }
36454 void
36456 {
36461 rtx tmp;
36463 = {
36470 };
36472 = {
36479 };
36483 {
36487 {
36492 else
36496 }
36508 else
36514 {
36517 /* For the two element vectors, we implement a VEC_CONCAT with
36518 the extraction of the other element. */
36525 else
36530 }
36539 {
36545 /* tmp = target = A B C D */
36547 /* target = A A B B */
36549 /* target = X A B B */
36551 /* target = A X C D */
36558 /* tmp = target = A B C D */
36560 /* tmp = X B C D */
36562 /* target = A B X D */
36569 /* tmp = target = A B C D */
36571 /* tmp = X B C D */
36573 /* target = A B X D */
36581 }
36589 /* Element 0 handled by vec_merge below. */
36591 {
36594 }
36597 {
36598 /* With SSE2, use integer shuffles to swap element 0 and ELT,
36599 store into element 0, then shuffle them back. */
36616 }
36617 else
36618 {
36619 /* For SSE1, we have to reuse the V4SF code. */
36622 }
36675 half:
36676 /* Compute offset. */
36682 /* Extract the half. */
36686 /* Put val in tmp at elt. */
36689 /* Put it back. */
36695 }
36698 {
36702 }
36703 else
36704 {
36713 }
36714 }
36716 void
36718 {
36722 rtx tmp;
36725 {
36730 /* FALLTHRU */
36743 {
36763 }
36775 {
36777 {
36797 }
36801 }
36802 else
36803 {
36804 /* For SSE1, we have to reuse the V4SF code. */
36808 }
36824 {
36828 else
36832 }
36837 {
36841 else
36845 }
36850 {
36854 else
36858 }
36863 {
36867 else
36871 }
36876 {
36880 else
36884 }
36889 {
36893 else
36897 }
36901 /* ??? Could extract the appropriate HImode element and shift. */
36904 }
36907 {
36911 /* Let the rtl optimizers know about the zero extension performed. */
36913 {
36916 }
36919 }
36920 else
36921 {
36928 }
36929 }
36931 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
36932 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
36933 The upper bits of DEST are undefined, though they shouldn't cause
36934 exceptions (some bits from src or all zeros are ok). */
36936 static void
36938 {
36939 rtx tem;
36941 {
36945 else
36963 else
36970 else
36981 const1_rtx);
36982 else
36989 }
36991 }
36993 /* Expand a vector reduction. FN is the binary pattern to reduce;
36994 DEST is the destination; IN is the input vector. */
36996 void
36998 {
37003 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
37007 {
37010 }
37015 {
37020 else
37024 }
37025 }
37026 \f
37027 /* Target hook for scalar_mode_supported_p. */
37028 static bool
37030 {
37035 else
37037 }
37039 /* Implements target hook vector_mode_supported_p. */
37040 static bool
37042 {
37054 }
37056 /* Target hook for c_mode_for_suffix. */
37057 static enum machine_mode
37059 {
37066 }
37068 /* Worker function for TARGET_MD_ASM_CLOBBERS.
37070 We do this in the new i386 backend to maintain source compatibility
37071 with the old cc0-based compiler. */
37073 static tree
37075 tree inputs ATTRIBUTE_UNUSED,
37076 tree clobbers)
37077 {
37079 clobbers);
37081 clobbers);
37083 }
37085 /* Implements target vector targetm.asm.encode_section_info. */
37087 static void ATTRIBUTE_UNUSED
37089 {
37096 }
37098 /* Worker function for REVERSE_CONDITION. */
37100 enum rtx_code
37102 {
37106 }
37108 /* Output code to perform an x87 FP register move, from OPERANDS[1]
37109 to OPERANDS[0]. */
37113 {
37115 {
37118 {
37122 }
37126 }
37128 {
37132 else
37133 {
37134 /* There is no non-popping store to memory for XFmode.
37135 So if we need one, follow the store with a load. */
37138 else
37140 }
37141 }
37142 else
37144 }
37146 /* Output code to perform a conditional jump to LABEL, if C2 flag in
37147 FP status register is set. */
37149 void
37151 {
37153 rtx temp;
37158 {
37163 }
37164 else
37165 {
37170 }
37174 pc_rtx);
37179 }
37181 /* Output code to perform a log1p XFmode calculation. */
37184 {
37190 rtx test;
37196 XFmode));
37210 }
37212 /* Emit code for round calculation. */
37214 {
37221 rtx insn;
37226 {
37238 }
37241 {
37262 }
37270 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
37272 /* scratch = fxam(op1) */
37275 UNSPEC_FXAM)));
37276 /* e1 = fabs(op1) */
37279 /* e2 = e1 + 0.5 */
37284 /* res = floor(e2) */
37286 {
37291 }
37292 else
37296 {
37299 {
37306 UNSPEC_TRUNC_NOOP)));
37307 }
37323 }
37325 /* flags = signbit(a) */
37328 /* if (flags) then res = -res */
37332 pc_rtx);
37343 }
37345 /* Output code to perform a Newton-Rhapson approximation of a single precision
37346 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
37349 {
37357 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
37361 /* x0 = rcp(b) estimate */
37364 UNSPEC_RCP)));
37365 /* e0 = x0 * b */
37369 /* e0 = x0 * e0 */
37373 /* e1 = x0 + x0 */
37377 /* x1 = e1 - e0 */
37381 /* res = a * x1 */
37384 }
37386 /* Output code to perform a Newton-Rhapson approximation of a
37387 single precision floating point [reciprocal] square root. */
37391 {
37393 REAL_VALUE_TYPE r;
37408 {
37411 }
37413 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
37414 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
37418 /* x0 = rsqrt(a) estimate */
37421 UNSPEC_RSQRT)));
37423 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
37425 {
37437 }
37439 /* e0 = x0 * a */
37442 /* e1 = e0 * x0 */
37446 /* e2 = e1 - 3. */
37453 /* e3 = -.5 * x0 */
37456 else
37457 /* e3 = -.5 * e0 */
37460 /* ret = e2 * e3 */
37463 }
37465 #ifdef TARGET_SOLARIS
37466 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
37468 static void
37470 tree decl)
37471 {
37472 /* With Binutils 2.15, the "@unwind" marker must be specified on
37473 every occurrence of the ".eh_frame" section, not just the first
37474 one. */
37477 {
37481 }
37483 #ifndef USE_GAS
37485 {
37488 }
37489 #endif
37492 }
37495 /* Return the mangling of TYPE if it is an extended fundamental type. */
37499 {
37507 {
37509 /* __float128 is "g". */
37512 /* "long double" or __float80 is "e". */
37516 }
37517 }
37519 /* For 32-bit code we can save PIC register setup by using
37520 __stack_chk_fail_local hidden function instead of calling
37521 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
37522 register, so it is better to call __stack_chk_fail directly. */
37524 static tree ATTRIBUTE_UNUSED
37526 {
37527 return TARGET_64BIT
37530 }
37532 /* Select a format to encode pointers in exception handling data. CODE
37533 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
37534 true if the symbol may be affected by dynamic relocations.
37536 ??? All x86 object file formats are capable of representing this.
37537 After all, the relocation needed is the same as for the call insn.
37538 Whether or not a particular assembler allows us to enter such, I
37539 guess we'll have to see. */
37540 int
37542 {
37544 {
37551 }
37556 }
37557 \f
37558 /* Expand copysign from SIGN to the positive value ABS_VALUE
37559 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
37560 the sign-bit. */
37561 static void
37563 {
37567 {
37574 else
37579 {
37580 /* We need to generate a scalar mode mask in this case. */
37585 }
37586 }
37587 else
37593 }
37595 /* Expand fabs (OP0) and return a new rtx that holds the result. The
37596 mask for masking out the sign-bit is stored in *SMASK, if that is
37597 non-null. */
37598 static rtx
37600 {
37609 else
37613 {
37614 /* We need to generate a scalar mode mask in this case. */
37619 }
37627 }
37629 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
37630 swapping the operands if SWAP_OPERANDS is true. The expanded
37631 code is a forward jump to a newly created label in case the
37632 comparison is true. The generated label rtx is returned. */
37633 static rtx
37636 {
37640 {
37644 }
37657 }
37659 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
37660 using comparison code CODE. Operands are swapped for the comparison if
37661 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
37662 static rtx
37665 {
37671 {
37675 }
37682 }
37684 /* Generate and return a rtx of mode MODE for 2**n where n is the number
37685 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
37686 static rtx
37688 {
37689 REAL_VALUE_TYPE TWO52r;
37690 rtx TWO52;
37697 }
37699 /* Expand SSE sequence for computing lround from OP1 storing
37700 into OP0. */
37701 void
37703 {
37704 /* C code for the stuff we're doing below:
37705 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
37706 return (long)tmp;
37707 */
37711 rtx adj;
37713 /* load nextafter (0.5, 0.0) */
37718 /* adj = copysign (0.5, op1) */
37722 /* adj = op1 + adj */
37725 /* op0 = (imode)adj */
37727 }
37729 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
37730 into OPERAND0. */
37731 void
37733 {
37734 /* C code for the stuff we're doing below (for do_floor):
37735 xi = (long)op1;
37736 xi -= (double)xi > op1 ? 1 : 0;
37737 return xi;
37738 */
37743 /* reg = (long)op1 */
37747 /* freg = (double)reg */
37751 /* ireg = (freg > op1) ? ireg - 1 : ireg */
37762 }
37764 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
37765 result in OPERAND0. */
37766 void
37768 {
37769 /* C code for the stuff we're doing below:
37770 xa = fabs (operand1);
37771 if (!isless (xa, 2**52))
37772 return operand1;
37773 xa = xa + 2**52 - 2**52;
37774 return copysign (xa, operand1);
37775 */
37782 /* xa = abs (operand1) */
37785 /* if (!isless (xa, TWO52)) goto label; */
37798 }
37800 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37801 into OPERAND0. */
37802 void
37804 {
37805 /* C code for the stuff we expand below.
37806 double xa = fabs (x), x2;
37807 if (!isless (xa, TWO52))
37808 return x;
37809 xa = xa + TWO52 - TWO52;
37810 x2 = copysign (xa, x);
37811 Compensate. Floor:
37812 if (x2 > x)
37813 x2 -= 1;
37814 Compensate. Ceil:
37815 if (x2 < x)
37816 x2 -= -1;
37817 return x2;
37818 */
37824 /* Temporary for holding the result, initialized to the input
37825 operand to ease control flow. */
37829 /* xa = abs (operand1) */
37832 /* if (!isless (xa, TWO52)) goto label; */
37835 /* xa = xa + TWO52 - TWO52; */
37839 /* xa = copysign (xa, operand1) */
37842 /* generate 1.0 or -1.0 */
37847 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37851 /* We always need to subtract here to preserve signed zero. */
37860 }
37862 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37863 into OPERAND0. */
37864 void
37866 {
37867 /* C code for the stuff we expand below.
37868 double xa = fabs (x), x2;
37869 if (!isless (xa, TWO52))
37870 return x;
37871 x2 = (double)(long)x;
37872 Compensate. Floor:
37873 if (x2 > x)
37874 x2 -= 1;
37875 Compensate. Ceil:
37876 if (x2 < x)
37877 x2 += 1;
37878 if (HONOR_SIGNED_ZEROS (mode))
37879 return copysign (x2, x);
37880 return x2;
37881 */
37887 /* Temporary for holding the result, initialized to the input
37888 operand to ease control flow. */
37892 /* xa = abs (operand1) */
37895 /* if (!isless (xa, TWO52)) goto label; */
37898 /* xa = (double)(long)x */
37903 /* generate 1.0 */
37906 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37921 }
37923 /* Expand SSE sequence for computing round from OPERAND1 storing
37924 into OPERAND0. Sequence that works without relying on DImode truncation
37925 via cvttsd2siq that is only available on 64bit targets. */
37926 void
37928 {
37929 /* C code for the stuff we expand below.
37930 double xa = fabs (x), xa2, x2;
37931 if (!isless (xa, TWO52))
37932 return x;
37933 Using the absolute value and copying back sign makes
37934 -0.0 -> -0.0 correct.
37935 xa2 = xa + TWO52 - TWO52;
37936 Compensate.
37937 dxa = xa2 - xa;
37938 if (dxa <= -0.5)
37939 xa2 += 1;
37940 else if (dxa > 0.5)
37941 xa2 -= 1;
37942 x2 = copysign (xa2, x);
37943 return x2;
37944 */
37950 /* Temporary for holding the result, initialized to the input
37951 operand to ease control flow. */
37955 /* xa = abs (operand1) */
37958 /* if (!isless (xa, TWO52)) goto label; */
37961 /* xa2 = xa + TWO52 - TWO52; */
37965 /* dxa = xa2 - xa; */
37968 /* generate 0.5, 1.0 and -0.5 */
37974 /* Compensate. */
37976 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
37981 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
37987 /* res = copysign (xa2, operand1) */
37994 }
37996 /* Expand SSE sequence for computing trunc from OPERAND1 storing
37997 into OPERAND0. */
37998 void
38000 {
38001 /* C code for SSE variant we expand below.
38002 double xa = fabs (x), x2;
38003 if (!isless (xa, TWO52))
38004 return x;
38005 x2 = (double)(long)x;
38006 if (HONOR_SIGNED_ZEROS (mode))
38007 return copysign (x2, x);
38008 return x2;
38009 */
38015 /* Temporary for holding the result, initialized to the input
38016 operand to ease control flow. */
38020 /* xa = abs (operand1) */
38023 /* if (!isless (xa, TWO52)) goto label; */
38026 /* x = (double)(long)x */
38038 }
38040 /* Expand SSE sequence for computing trunc from OPERAND1 storing
38041 into OPERAND0. */
38042 void
38044 {
38048 /* C code for SSE variant we expand below.
38049 double xa = fabs (x), x2;
38050 if (!isless (xa, TWO52))
38051 return x;
38052 xa2 = xa + TWO52 - TWO52;
38053 Compensate:
38054 if (xa2 > xa)
38055 xa2 -= 1.0;
38056 x2 = copysign (xa2, x);
38057 return x2;
38058 */
38062 /* Temporary for holding the result, initialized to the input
38063 operand to ease control flow. */
38067 /* xa = abs (operand1) */
38070 /* if (!isless (xa, TWO52)) goto label; */
38073 /* res = xa + TWO52 - TWO52; */
38078 /* generate 1.0 */
38081 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
38089 /* res = copysign (res, operand1) */
38096 }
38098 /* Expand SSE sequence for computing round from OPERAND1 storing
38099 into OPERAND0. */
38100 void
38102 {
38103 /* C code for the stuff we're doing below:
38104 double xa = fabs (x);
38105 if (!isless (xa, TWO52))
38106 return x;
38107 xa = (double)(long)(xa + nextafter (0.5, 0.0));
38108 return copysign (xa, x);
38109 */
38115 /* Temporary for holding the result, initialized to the input
38116 operand to ease control flow. */
38124 /* load nextafter (0.5, 0.0) */
38129 /* xa = xa + 0.5 */
38133 /* xa = (double)(int64_t)xa */
38138 /* res = copysign (xa, operand1) */
38145 }
38147 /* Expand SSE sequence for computing round
38148 from OP1 storing into OP0 using sse4 round insn. */
38149 void
38151 {
38160 {
38171 }
38173 /* round (a) = trunc (a + copysign (0.5, a)) */
38175 /* load nextafter (0.5, 0.0) */
38181 /* e1 = copysign (0.5, op1) */
38185 /* e2 = op1 + e1 */
38188 /* res = trunc (e2) */
38193 }
38194 \f
38196 /* Table of valid machine attributes. */
38198 {
38199 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
38200 affects_type_identity } */
38201 /* Stdcall attribute says callee is responsible for popping arguments
38202 if they are not variable. */
38205 /* Fastcall attribute says callee is responsible for popping arguments
38206 if they are not variable. */
38209 /* Thiscall attribute says callee is responsible for popping arguments
38210 if they are not variable. */
38213 /* Cdecl attribute says the callee is a normal C declaration */
38216 /* Regparm attribute specifies how many integer arguments are to be
38217 passed in registers. */
38220 /* Sseregparm attribute says we are using x86_64 calling conventions
38221 for FP arguments. */
38224 /* The transactional memory builtins are implicitly regparm or fastcall
38225 depending on the ABI. Override the generic do-nothing attribute that
38226 these builtins were declared with. */
38229 /* force_align_arg_pointer says this function realigns the stack at entry. */
38232 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
38237 #endif
38242 #ifdef SUBTARGET_ATTRIBUTE_TABLE
38243 SUBTARGET_ATTRIBUTE_TABLE,
38244 #endif
38245 /* ms_abi and sysv_abi calling convention function attributes. */
38252 /* End element. */
38254 };
38256 /* Implement targetm.vectorize.builtin_vectorization_cost. */
38257 static int
38259 tree vectype,
38261 {
38265 {
38310 }
38311 }
38313 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
38314 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
38315 insn every time. */
38319 /* Initialize vselect_insn. */
38321 static void
38323 {
38325 rtx x;
38336 }
38338 /* Construct (set target (vec_select op0 (parallel perm))) and
38339 return true if that's a valid instruction in the active ISA. */
38341 static bool
38344 {
38370 }
38372 /* Similar, but generate a vec_concat from op0 and op1 as well. */
38374 static bool
38378 {
38380 rtx x;
38395 }
38397 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38398 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
38400 static bool
38402 {
38411 ;
38413 ;
38415 ;
38416 else
38419 /* This is a blend, not a permute. Elements must stay in their
38420 respective lanes. */
38422 {
38426 }
38431 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
38432 decision should be extracted elsewhere, so that we only try that
38433 sequence once all budget==3 options have been tried. */
38440 {
38464 /* See if bytes move in pairs so we can use pblendw with
38465 an immediate argument, rather than pblendvb with a vector
38466 argument. */
38469 {
38470 use_pblendvb:
38474 finish_pblendvb:
38480 else
38483 }
38488 /* FALLTHRU */
38490 do_subreg:
38497 /* See if bytes move in pairs. If not, vpblendvb must be used. */
38501 /* See if bytes move in quadruplets. If yes, vpblendd
38502 with immediate can be used. */
38507 {
38508 /* See if bytes move the same in both lanes. If yes,
38509 vpblendw with immediate can be used. */
38514 /* Use vpblendw. */
38519 }
38521 /* Use vpblendd. */
38528 /* See if words move in pairs. If yes, vpblendd can be used. */
38533 {
38534 /* See if words move the same in both lanes. If not,
38535 vpblendvb must be used. */
38538 {
38539 /* Use vpblendvb. */
38549 }
38551 /* Use vpblendw. */
38555 }
38557 /* Use vpblendd. */
38564 /* Use vpblendd. */
38572 }
38574 /* This matches five different patterns with the different modes. */
38580 }
38582 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38583 in terms of the variable form of vpermilps.
38585 Note that we will have already failed the immediate input vpermilps,
38586 which requires that the high and low part shuffle be identical; the
38587 variable form doesn't require that. */
38589 static bool
38591 {
38598 /* We can only permute within the 128-bit lane. */
38600 {
38604 }
38610 {
38613 /* Within each 128-bit lane, the elements of op0 are numbered
38614 from 0 and the elements of op1 are numbered from 4. */
38621 }
38628 }
38630 /* Return true if permutation D can be performed as VMODE permutation
38631 instead. */
38633 static bool
38635 {
38650 else
38656 }
38658 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38659 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
38661 static bool
38663 {
38672 {
38674 {
38677 {
38681 /* Use vperm2i128 insn. The pattern uses
38682 V4DImode instead of V2TImode. */
38691 }
38693 }
38694 }
38695 else
38696 {
38698 {
38701 }
38703 {
38707 /* V4DImode should be already handled through
38708 expand_vselect by vpermq instruction. */
38715 {
38716 /* First see if vpermq can be used for
38717 V8SImode/V16HImode/V32QImode. */
38719 {
38727 }
38729 /* Next see if vpermd can be used. */
38732 }
38733 /* Or if vpermps can be used. */
38738 {
38739 /* vpshufb only works intra lanes, it is not
38740 possible to shuffle bytes in between the lanes. */
38744 }
38745 }
38746 else
38748 }
38756 else
38757 {
38763 else
38767 {
38771 }
38772 }
38781 {
38788 else
38790 }
38791 else
38792 {
38795 }
38798 }
38800 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
38801 in a single instruction. */
38803 static bool
38805 {
38809 /* Check plain VEC_SELECT first, because AVX has instructions that could
38810 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
38811 input where SEL+CONCAT may not. */
38813 {
38819 {
38825 }
38828 {
38832 }
38834 {
38835 /* Use vpbroadcast{b,w,d}. */
38838 {
38857 /* For other modes prefer other shuffles this function creates. */
38859 }
38861 {
38865 }
38866 }
38871 /* There are plenty of patterns in sse.md that are written for
38872 SEL+CONCAT and are not replicated for a single op. Perhaps
38873 that should be changed, to avoid the nastiness here. */
38875 /* Recognize interleave style patterns, which means incrementing
38876 every other permutation operand. */
38878 {
38881 }
38886 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
38888 {
38890 {
38895 }
38900 }
38901 }
38903 /* Finally, try the fully general two operand permute. */
38908 /* Recognize interleave style patterns with reversed operands. */
38910 {
38912 {
38916 else
38919 }
38924 }
38926 /* Try the SSE4.1 blend variable merge instructions. */
38930 /* Try one of the AVX vpermil variable permutations. */
38934 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
38935 vpshufb, vpermd, vpermps or vpermq variable permutation. */
38940 }
38942 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38943 in terms of a pair of pshuflw + pshufhw instructions. */
38945 static bool
38947 {
38955 /* The two permutations only operate in 64-bit lanes. */
38966 /* Emit the pshuflw. */
38973 /* Emit the pshufhw. */
38981 }
38983 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
38984 the permutation using the SSSE3 palignr instruction. This succeeds
38985 when all of the elements in PERM fit within one vector and we merely
38986 need to shift them down so that a single vector permutation has a
38987 chance to succeed. */
38989 static bool
38991 {
38995 rtx shift;
38997 /* Even with AVX, palignr only operates on 128-bit vectors. */
39003 {
39009 }
39013 /* Given that we have SSSE3, we know we'll be able to implement the
39014 single operand permutation after the palignr with pshufb. */
39028 {
39033 }
39035 /* Test for the degenerate case where the alignment by itself
39036 produces the desired permutation. */
39044 }
39048 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39049 a two vector permutation into a single vector permutation by using
39050 an interleave operation to merge the vectors. */
39052 static bool
39054 {
39059 rtx seq;
39063 {
39066 }
39068 {
39071 /* For 32-byte modes allow even d->one_operand_p.
39072 The lack of cross-lane shuffling in some instructions
39073 might prevent a single insn shuffle. */
39076 /* If expand_vec_perm_interleave3 can expand this into
39077 a 3 insn sequence, give up and let it be expanded as
39078 3 insn sequence. While that is one insn longer,
39079 it doesn't need a memory operand and in the common
39080 case that both interleave low and high permutations
39081 with the same operands are adjacent needs 4 insns
39082 for both after CSE. */
39085 }
39086 else
39089 /* Examine from whence the elements come. */
39098 {
39101 /* Split the two input vectors into 4 halves. */
39107 /* If the elements from the low halves use interleave low, and similarly
39108 for interleave high. If the elements are from mis-matched halves, we
39109 can use shufps for V4SF/V4SI or do a DImode shuffle. */
39111 {
39112 /* punpckl* */
39114 {
39119 }
39122 }
39124 {
39125 /* punpckh* */
39127 {
39132 }
39135 }
39137 {
39138 /* shufps */
39140 {
39145 }
39147 {
39148 /* shufpd */
39153 }
39154 }
39156 {
39157 /* shufps */
39159 {
39164 }
39166 {
39167 /* shufpd */
39172 }
39173 }
39174 else
39176 }
39177 else
39178 {
39183 /* Split the two input vectors into 8 quarters. */
39189 {
39192 }
39195 {
39199 }
39201 {
39204 }
39207 {
39209 {
39210 /* Attempt to increase the likelihood that dfinal
39211 shuffle will be intra-lane. */
39215 }
39217 /* vperm2f128 or vperm2i128. */
39219 {
39224 }
39229 {
39233 {
39236 }
39237 }
39238 }
39243 {
39244 /* vpunpckl* */
39246 {
39255 }
39256 }
39259 {
39260 /* vpunpckh* */
39262 {
39271 }
39272 }
39273 else
39275 }
39277 /* Use the remapping array set up above to move the elements from their
39278 swizzled locations into their final destinations. */
39281 {
39284 /* If same_halves is true, both halves of the remapped vector are the
39285 same. Avoid cross-lane accesses if possible. */
39287 {
39290 }
39291 else
39293 }
39299 /* Test if the final remap can be done with a single insn. For V4SFmode or
39300 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
39313 {
39317 }
39324 }
39326 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39327 a single vector cross-lane permutation into vpermq followed
39328 by any of the single insn permutations. */
39330 static bool
39332 {
39346 {
39349 }
39352 {
39357 }
39370 {
39377 }
39384 {
39389 ;
39392 else
39394 }
39403 }
39405 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
39406 a vector permutation using two instructions, vperm2f128 resp.
39407 vperm2i128 followed by any single in-lane permutation. */
39409 static bool
39411 {
39425 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
39426 immediate. For perm < 16 the second permutation uses
39427 d->op0 as first operand, for perm >= 16 it uses d->op1
39428 as first operand. The second operand is the result of
39429 vperm2[fi]128. */
39431 {
39432 /* Ignore permutations which do not move anything cross-lane. */
39434 {
39435 /* The second shuffle for e.g. V4DFmode has
39436 0123 and ABCD operands.
39437 Ignore AB23, as 23 is already in the second lane
39438 of the first operand. */
39440 /* And 01CD, as 01 is in the first lane of the first
39441 operand. */
39443 /* And 4567, as then the vperm2[fi]128 doesn't change
39444 anything on the original 4567 second operand. */
39446 }
39447 else
39448 {
39449 /* The second shuffle for e.g. V4DFmode has
39450 4567 and ABCD operands.
39451 Ignore AB67, as 67 is already in the second lane
39452 of the first operand. */
39454 /* And 45CD, as 45 is in the first lane of the first
39455 operand. */
39457 /* And 0123, as then the vperm2[fi]128 doesn't change
39458 anything on the original 0123 first operand. */
39460 }
39463 {
39469 else
39471 }
39474 {
39478 }
39479 else
39483 {
39487 /* Found a usable second shuffle. dfirst will be
39488 vperm2f128 on d->op0 and d->op1. */
39499 /* And dsecond is some single insn shuffle, taking
39500 d->op0 and result of vperm2f128 (if perm < 16) or
39501 d->op1 and result of vperm2f128 (otherwise). */
39510 }
39512 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
39515 }
39518 }
39520 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39521 a two vector permutation using 2 intra-lane interleave insns
39522 and cross-lane shuffle for 32-byte vectors. */
39524 static bool
39526 {
39533 ;
39535 ;
39536 else
39551 {
39555 else
39561 else
39567 else
39573 else
39579 else
39585 else
39590 }
39594 }
39596 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
39597 a single vector permutation using a single intra-lane vector
39598 permutation, vperm2f128 swapping the lanes and vblend* insn blending
39599 the non-swapped and swapped vectors together. */
39601 static bool
39603 {
39606 rtx seq;
39611 || TARGET_AVX2
39620 {
39627 }
39662 }
39664 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
39665 permutation using two vperm2f128, followed by a vshufpd insn blending
39666 the two vectors together. */
39668 static bool
39670 {
39713 }
39715 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
39716 permutation with two pshufb insns and an ior. We should have already
39717 failed all two instruction sequences. */
39719 static bool
39721 {
39732 /* Generate two permutation masks. If the required element is within
39733 the given vector it is shuffled into the proper lane. If the required
39734 element is in the other vector, force a zero into the lane by setting
39735 bit 7 in the permutation mask. */
39738 {
39745 {
39748 }
39749 }
39769 }
39771 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
39772 with two vpshufb insns, vpermq and vpor. We should have already failed
39773 all two or three instruction sequences. */
39775 static bool
39777 {
39792 /* Generate two permutation masks. If the required element is within
39793 the same lane, it is shuffled in. If the required element from the
39794 other lane, force a zero by setting bit 7 in the permutation mask.
39795 In the other mask the mask has non-negative elements if element
39796 is requested from the other lane, but also moved to the other lane,
39797 so that the result of vpshufb can have the two V2TImode halves
39798 swapped. */
39801 {
39806 {
39809 }
39810 }
39819 /* Swap the 128-byte lanes of h into hp. */
39823 const1_rtx));
39836 }
39838 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
39839 and extract-odd permutations of two V32QImode and V16QImode operand
39840 with two vpshufb insns, vpor and vpermq. We should have already
39841 failed all two or three instruction sequences. */
39843 static bool
39845 {
39864 /* Generate two permutation masks. In the first permutation mask
39865 the first quarter will contain indexes for the first half
39866 of the op0, the second quarter will contain bit 7 set, third quarter
39867 will contain indexes for the second half of the op0 and the
39868 last quarter bit 7 set. In the second permutation mask
39869 the first quarter will contain bit 7 set, the second quarter
39870 indexes for the first half of the op1, the third quarter bit 7 set
39871 and last quarter indexes for the second half of the op1.
39872 I.e. the first mask e.g. for V32QImode extract even will be:
39873 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
39874 (all values masked with 0xf except for -128) and second mask
39875 for extract even will be
39876 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
39879 {
39885 {
39888 }
39889 }
39908 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
39915 }
39917 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
39918 and extract-odd permutations. */
39920 static bool
39922 {
39926 {
39931 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
39935 /* Now an unpck[lh]pd will produce the result required. */
39938 else
39944 {
39951 /* Shuffle within the 128-bit lanes to produce:
39952 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
39956 /* Shuffle the lanes around to produce:
39957 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
39961 /* Shuffle within the 128-bit lanes to produce:
39962 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
39965 /* Shuffle within the 128-bit lanes to produce:
39966 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
39969 /* Shuffle the lanes around to produce:
39970 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
39973 }
39980 /* These are always directly implementable by expand_vec_perm_1. */
39986 else
39987 {
39988 /* We need 2*log2(N)-1 operations to achieve odd/even
39989 with interleave. */
39998 else
40001 }
40007 else
40008 {
40020 else
40023 }
40032 {
40039 }
40044 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
40048 /* Now an vpunpck[lh]qdq will produce the result required. */
40051 else
40058 {
40065 }
40070 /* Shuffle the lanes around into
40071 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
40081 /* Swap the 2nd and 3rd position in each lane into
40082 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
40088 /* Now an vpunpck[lh]qdq will produce
40089 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
40094 else
40103 }
40106 }
40108 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40109 extract-even and extract-odd permutations. */
40111 static bool
40113 {
40125 }
40127 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
40128 permutations. We assume that expand_vec_perm_1 has already failed. */
40130 static bool
40132 {
40140 {
40143 /* These are special-cased in sse.md so that we can optionally
40144 use the vbroadcast instruction. They expand to two insns
40145 if the input happens to be in a register. */
40152 /* These are always implementable using standard shuffle patterns. */
40157 /* These can be implemented via interleave. We save one insn by
40158 stopping once we have promoted to V4SImode and then use pshufd. */
40159 do
40160 {
40161 rtx dest;
40167 {
40171 }
40178 }
40191 /* For AVX2 broadcasts of the first element vpbroadcast* or
40192 vpermq should be used by expand_vec_perm_1. */
40198 }
40199 }
40201 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40202 broadcast permutations. */
40204 static bool
40206 {
40218 }
40220 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
40221 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
40222 all the shorter instruction sequences. */
40224 static bool
40226 {
40242 /* Generate 4 permutation masks. If the required element is within
40243 the same lane, it is shuffled in. If the required element from the
40244 other lane, force a zero by setting bit 7 in the permutation mask.
40245 In the other mask the mask has non-negative elements if element
40246 is requested from the other lane, but also moved to the other lane,
40247 so that the result of vpshufb can have the two V2TImode halves
40248 swapped. */
40251 {
40256 }
40262 {
40270 }
40273 {
40275 {
40278 }
40285 }
40287 /* Swap the 128-byte lanes of h[X]. */
40289 {
40295 const1_rtx));
40297 }
40300 {
40302 {
40305 }
40311 }
40314 {
40316 {
40320 }
40323 }
40329 }
40331 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
40332 With all of the interface bits taken care of, perform the expansion
40333 in D and return true on success. */
40335 static bool
40337 {
40338 /* Try a single instruction expansion. */
40342 /* Try sequences of two instructions. */
40362 /* Try sequences of three instructions. */
40376 /* Try sequences of four instructions. */
40384 /* ??? Look for narrow permutations whose element orderings would
40385 allow the promotion to a wider mode. */
40387 /* ??? Look for sequences of interleave or a wider permute that place
40388 the data into the correct lanes for a half-vector shuffle like
40389 pshuf[lh]w or vpermilps. */
40391 /* ??? Look for sequences of interleave that produce the desired results.
40392 The combinatorics of punpck[lh] get pretty ugly... */
40397 /* Even longer sequences. */
40402 }
40404 /* If a permutation only uses one operand, make it clear. Returns true
40405 if the permutation references both operands. */
40407 static bool
40409 {
40417 {
40423 {
40426 }
40427 /* The elements of PERM do not suggest that only the first operand
40428 is used, but both operands are identical. Allow easier matching
40429 of the permutation by folding the permutation into the single
40430 input vector. */
40431 /* FALLTHRU */
40442 }
40445 }
40447 bool
40449 {
40454 rtx sel;
40471 {
40476 }
40483 /* If the selector says both arguments are needed, but the operands are the
40484 same, the above tried to expand with one_operand_p and flattened selector.
40485 If that didn't work, retry without one_operand_p; we succeeded with that
40486 during testing. */
40488 {
40492 }
40495 }
40497 /* Implement targetm.vectorize.vec_perm_const_ok. */
40499 static bool
40502 {
40511 /* Given sufficient ISA support we can just return true here
40512 for selected vector modes. */
40514 {
40515 /* All implementable with a single vpperm insn. */
40518 /* All implementable with 2 pshufb + 1 ior. */
40521 /* All implementable with shufpd or unpck[lh]pd. */
40524 }
40526 /* Extract the values from the vector CST into the permutation
40527 array in D. */
40530 {
40534 }
40536 /* For all elements from second vector, fold the elements to first. */
40541 /* Check whether the mask can be applied to the vector type. */
40544 /* Implementable with shufps or pshufd. */
40548 /* Otherwise we have to go through the motions and see if we can
40549 figure out how to generate the requested permutation. */
40560 }
40562 void
40564 {
40579 /* We'll either be able to implement the permutation directly... */
40583 /* ... or we use the special-case patterns. */
40585 }
40587 static void
40589 {
40604 {
40607 }
40609 /* Note that for AVX this isn't one instruction. */
40612 }
40615 /* Expand a vector operation CODE for a V*QImode in terms of the
40616 same operation on V*HImode. */
40618 void
40620 {
40632 {
40645 }
40649 {
40651 /* Unpack data such that we've got a source byte in each low byte of
40652 each word. We don't care what goes into the high byte of each word.
40653 Rather than trying to get zero in there, most convenient is to let
40654 it be a copy of the low byte. */
40659 /* FALLTHRU */
40671 /* FALLTHRU */
40681 }
40683 /* Perform the operation. */
40690 /* Merge the data back into the right place. */
40700 {
40701 /* For SSE2, we used an full interleave, so the desired
40702 results are in the even elements. */
40705 }
40706 else
40707 {
40708 /* For AVX, the interleave used above was not cross-lane. So the
40709 extraction is evens but with the second and third quarter swapped.
40710 Happily, that is even one insn shorter than even extraction. */
40713 }
40720 }
40722 void
40725 {
40728 rtx x;
40730 /* We only play even/odd games with vectors of SImode. */
40733 /* If we're looking for the odd results, shift those members down to
40734 the even slots. For some cpus this is faster than a PSHUFD. */
40736 {
40738 {
40742 }
40751 }
40754 {
40757 else
40759 }
40764 else
40765 {
40768 /* The easiest way to implement this without PMULDQ is to go through
40769 the motions as if we are performing a full 64-bit multiply. With
40770 the exception that we need to do less shuffling of the elements. */
40772 /* Compute the sign-extension, aka highparts, of the two operands. */
40778 /* Multiply LO(A) * HI(B), and vice-versa. */
40784 /* Multiply LO(A) * LO(B). */
40788 /* Combine and shift the highparts into place. */
40793 /* Combine high and low parts. */
40796 }
40798 }
40800 void
40803 {
40809 {
40814 {
40815 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
40816 shuffle the elements once so that all elements are in the right
40817 place for immediate use: { A C B D }. */
40822 }
40823 else
40824 {
40825 /* Put the elements into place for the multiply. */
40829 }
40834 /* Shuffle the elements between the lanes. After this we
40835 have { A B E F | C D G H } for each operand. */
40845 /* Shuffle the elements within the lanes. After this we
40846 have { A A B B | C C D D } or { E E F F | G G H H }. */
40882 }
40883 }
40885 void
40887 {
40897 /* Move the results in element 2 down to element 1; we don't care
40898 what goes in elements 2 and 3. Then we can merge the parts
40899 back together with an interleave.
40901 Note that two other sequences were tried:
40902 (1) Use interleaves at the start instead of psrldq, which allows
40903 us to use a single shufps to merge things back at the end.
40904 (2) Use shufps here to combine the two vectors, then pshufd to
40905 put the elements in the correct order.
40906 In both cases the cost of the reformatting stall was too high
40907 and the overall sequence slower. */
40916 }
40918 void
40920 {
40925 {
40926 /* op1: A,B,C,D, op2: E,F,G,H */
40935 /* t1: B,A,D,C */
40942 /* t2: (B*E),(A*F),(D*G),(C*H) */
40945 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
40948 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
40951 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
40953 }
40954 else
40955 {
40960 {
40963 }
40965 {
40968 }
40969 else
40973 /* Multiply low parts. */
40977 /* Shift input vectors right 32 bits so we can multiply high parts. */
40982 /* Multiply high parts by low parts. */
40988 /* Combine and shift the highparts back. */
40992 /* Combine high and low parts. */
40994 }
40998 }
41000 /* Expand an insert into a vector register through pinsr insn.
41001 Return true if successful. */
41003 bool
41005 {
41013 {
41016 }
41022 {
41027 {
41034 {
41066 }
41075 }
41079 }
41080 }
41081 \f
41082 /* This function returns the calling abi specific va_list type node.
41083 It returns the FNDECL specific va_list type. */
41085 static tree
41087 {
41094 else
41096 }
41098 /* Returns the canonical va_list type specified by TYPE. If there
41099 is no valid TYPE provided, it return NULL_TREE. */
41101 static tree
41103 {
41106 /* Resolve references and pointers to va_list type. */
41115 {
41120 {
41121 /* If va_list is an array type, the argument may have decayed
41122 to a pointer type, e.g. by being passed to another function.
41123 In that case, unwrap both types so that we can compare the
41124 underlying records. */
41127 {
41130 }
41131 }
41138 {
41139 /* If va_list is an array type, the argument may have decayed
41140 to a pointer type, e.g. by being passed to another function.
41141 In that case, unwrap both types so that we can compare the
41142 underlying records. */
41145 {
41148 }
41149 }
41156 {
41157 /* If va_list is an array type, the argument may have decayed
41158 to a pointer type, e.g. by being passed to another function.
41159 In that case, unwrap both types so that we can compare the
41160 underlying records. */
41163 {
41166 }
41167 }
41171 }
41173 }
41175 /* Iterate through the target-specific builtin types for va_list.
41176 IDX denotes the iterator, *PTREE is set to the result type of
41177 the va_list builtin, and *PNAME to its internal type.
41178 Returns zero if there is no element for this index, otherwise
41179 IDX should be increased upon the next call.
41180 Note, do not iterate a base builtin's name like __builtin_va_list.
41181 Used from c_common_nodes_and_builtins. */
41183 static int
41185 {
41187 {
41189 {
41202 }
41203 }
41206 }
41208 #undef TARGET_SCHED_DISPATCH
41209 #define TARGET_SCHED_DISPATCH has_dispatch
41210 #undef TARGET_SCHED_DISPATCH_DO
41211 #define TARGET_SCHED_DISPATCH_DO do_dispatch
41212 #undef TARGET_SCHED_REASSOCIATION_WIDTH
41213 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
41214 #undef TARGET_SCHED_REORDER
41215 #define TARGET_SCHED_REORDER ix86_sched_reorder
41216 #undef TARGET_SCHED_ADJUST_PRIORITY
41217 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
41218 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
41219 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ix86_dependencies_evaluation_hook
41221 /* The size of the dispatch window is the total number of bytes of
41222 object code allowed in a window. */
41223 #define DISPATCH_WINDOW_SIZE 16
41225 /* Number of dispatch windows considered for scheduling. */
41226 #define MAX_DISPATCH_WINDOWS 3
41228 /* Maximum number of instructions in a window. */
41229 #define MAX_INSN 4
41231 /* Maximum number of immediate operands in a window. */
41232 #define MAX_IMM 4
41234 /* Maximum number of immediate bits allowed in a window. */
41235 #define MAX_IMM_SIZE 128
41237 /* Maximum number of 32 bit immediates allowed in a window. */
41238 #define MAX_IMM_32 4
41240 /* Maximum number of 64 bit immediates allowed in a window. */
41241 #define MAX_IMM_64 2
41243 /* Maximum total of loads or prefetches allowed in a window. */
41244 #define MAX_LOAD 2
41246 /* Maximum total of stores allowed in a window. */
41247 #define MAX_STORE 1
41249 #undef BIG
41250 #define BIG 100
41253 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
41256 disp_load,
41257 disp_store,
41258 disp_load_store,
41259 disp_prefetch,
41260 disp_imm,
41261 disp_imm_32,
41262 disp_imm_64,
41263 disp_branch,
41264 disp_cmp,
41265 disp_jcc,
41266 disp_last
41267 };
41269 /* Number of allowable groups in a dispatch window. It is an array
41270 indexed by dispatch_group enum. 100 is used as a big number,
41271 because the number of these kind of operations does not have any
41272 effect in dispatch window, but we need them for other reasons in
41273 the table. */
41276 };
41282 };
41284 /* Instruction path. */
41290 last_path
41291 };
41293 /* sched_insn_info defines a window to the instructions scheduled in
41294 the basic block. It contains a pointer to the insn_info table and
41295 the instruction scheduled.
41297 Windows are allocated for each basic block and are linked
41298 together. */
41300 rtx insn;
41307 /* Linked list of dispatch windows. This is a two way list of
41308 dispatch windows of a basic block. It contains information about
41309 the number of uops in the window and the total number of
41310 instructions and of bytes in the object code for this dispatch
41311 window. */
41329 /* Immediate valuse used in an insn. */
41331 {
41340 /* Get dispatch group of insn. */
41342 static enum dispatch_group
41344 {
41360 }
41362 /* Return true if insn is a compare instruction. */
41364 static bool
41366 {
41374 }
41376 /* Return true if a dispatch violation encountered. */
41378 static bool
41380 {
41384 }
41386 /* Return true if insn is a branch instruction. */
41388 static bool
41390 {
41392 }
41394 /* Return true if insn is a prefetch instruction. */
41396 static bool
41398 {
41400 }
41402 /* This function initializes a dispatch window and the list container holding a
41403 pointer to the window. */
41405 static void
41407 {
41413 else
41431 {
41437 }
41439 }
41441 /* This function allocates and initializes a dispatch window and the
41442 list container holding a pointer to the window. */
41446 {
41451 }
41453 /* This routine initializes the dispatch scheduling information. It
41454 initiates building dispatch scheduler tables and constructs the
41455 first dispatch window. */
41457 static void
41459 {
41460 /* Allocate a dispatch list and a window. */
41465 }
41467 /* This function returns true if a branch is detected. End of a basic block
41468 does not have to be a branch, but here we assume only branches end a
41469 window. */
41471 static bool
41473 {
41475 }
41477 /* This function is called when the end of a window processing is reached. */
41479 static void
41481 {
41484 {
41489 }
41491 }
41493 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
41494 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
41495 for 48 bytes of instructions. Note that these windows are not dispatch
41496 windows that their sizes are DISPATCH_WINDOW_SIZE. */
41500 {
41502 {
41507 }
41513 }
41515 /* Increment the number of immediate operands of an instruction. */
41517 static int
41519 {
41524 {
41531 else
41542 {
41545 }
41550 }
41553 }
41555 /* Compute number of immediate operands of an instruction. */
41557 static void
41559 {
41562 }
41564 /* Return total size of immediate operands of an instruction along with number
41565 of corresponding immediate-operands. It initializes its parameters to zero
41566 befor calling FIND_CONSTANT.
41567 INSN is the input instruction. IMM is the total of immediates.
41568 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
41569 bit immediates. */
41571 static int
41573 {
41581 }
41583 /* This function indicates if an operand of an instruction is an
41584 immediate. */
41586 static bool
41588 {
41597 }
41599 /* Return single or double path for instructions. */
41601 static enum insn_path
41603 {
41613 }
41615 /* Return insn dispatch group. */
41617 static enum dispatch_group
41619 {
41637 }
41639 /* Count number of GROUP restricted instructions in a dispatch
41640 window WINDOW_LIST. */
41642 static int
41644 {
41655 {
41674 }
41687 }
41689 /* This function returns true if insn satisfies dispatch rules on the
41690 last window scheduled. */
41692 static bool
41694 {
41702 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
41703 instructions should be given the lowest priority in the
41704 scheduling process in Haifa scheduler to make sure they will be
41705 scheduled in the same dispatch window as the reference to them. */
41709 /* Check nonrestricted. */
41713 /* Get last dispatch window. */
41718 {
41723 /* Window 1 is full. Go for next window. */
41725 }
41732 /* See if it fits in the first window. */
41734 {
41735 /* The first widow should have only single and double path
41736 uops. */
41742 }
41744 }
41746 /* Add an instruction INSN with NUM_UOPS micro-operations to the
41747 dispatch window WINDOW_LIST. */
41749 static void
41751 {
41769 /* Initialize window with new instruction. */
41790 {
41793 }
41794 }
41796 /* Adds a scheduled instruction, INSN, to the current dispatch window.
41797 If the total bytes of instructions or the number of instructions in
41798 the window exceed allowable, it allocates a new window. */
41800 static void
41802 {
41825 /* Get the last dispatch window. */
41833 else
41836 /* If current window is full, get a new window.
41837 Window number zero is full, if MAX_INSN uops are scheduled in it.
41838 Window number one is full, if window zero's bytes plus window
41839 one's bytes is 32, or if the bytes of the new instruction added
41840 to the total makes it greater than 48, or it has already MAX_INSN
41841 instructions in it. */
41850 {
41853 }
41856 {
41860 {
41863 }
41864 }
41866 {
41871 {
41874 }
41877 }
41878 else
41882 {
41883 /* End of basic block is reached do end-basic-block process. */
41886 }
41887 }
41889 /* Print the dispatch window, WINDOW_NUM, to FILE. */
41891 DEBUG_FUNCTION static void
41893 {
41899 else
41913 {
41916 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
41922 }
41923 }
41925 /* Print to stdout a dispatch window. */
41927 DEBUG_FUNCTION void
41929 {
41931 }
41933 /* Print INSN dispatch information to FILE. */
41935 DEBUG_FUNCTION static void
41937 {
41960 }
41962 /* Print to STDERR the status of the ready list with respect to
41963 dispatch windows. */
41965 DEBUG_FUNCTION void
41967 {
41975 }
41977 /* This routine is the driver of the dispatch scheduler. */
41979 static void
41981 {
41986 }
41988 /* Return TRUE if Dispatch Scheduling is supported. */
41990 static bool
41992 {
41996 {
42012 }
42015 }
42017 /* Implementation of reassociation_width target hook used by
42018 reassoc phase to identify parallelism level in reassociated
42019 tree. Statements tree_code is passed in OPC. Arguments type
42020 is passed in MODE.
42022 Currently parallel reassociation is enabled for Atom
42023 processors only and we set reassociation width to be 2
42024 because Atom may issue up to 2 instructions per cycle.
42026 Return value should be fixed if parallel reassociation is
42027 enabled for other processors. */
42029 static int
42032 {
42041 }
42043 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
42044 place emms and femms instructions. */
42046 static enum machine_mode
42048 {
42053 {
42066 else
42076 /* FALLTHRU */
42080 }
42081 }
42083 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
42084 vectors. */
42086 static unsigned int
42088 {
42090 }
42092 \f
42094 /* Return class of registers which could be used for pseudo of MODE
42095 and of class RCLASS for spilling instead of memory. Return NO_REGS
42096 if it is not possible or non-profitable. */
42097 static reg_class_t
42099 {
42105 }
42107 /* Implement targetm.vectorize.init_cost. */
42111 {
42115 }
42117 /* Implement targetm.vectorize.add_stmt_cost. */
42119 static unsigned
42123 {
42128 {
42132 /* Statements in an inner loop relative to the loop being
42133 vectorized are weighted more heavily. The value here is
42134 arbitrary and could potentially be improved with analysis. */
42140 }
42143 }
42145 /* Implement targetm.vectorize.finish_cost. */
42147 static void
42150 {
42155 }
42157 /* Implement targetm.vectorize.destroy_cost_data. */
42159 static void
42161 {
42163 }
42165 /* Validate target specific memory model bits in VAL. */
42167 static unsigned HOST_WIDE_INT
42169 {
42176 {
42180 }
42183 {
42187 }
42189 {
42193 }
42195 }
42197 /* Initialize the GCC target structure. */
42198 #undef TARGET_RETURN_IN_MEMORY
42199 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
42201 #undef TARGET_LEGITIMIZE_ADDRESS
42202 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
42204 #undef TARGET_ATTRIBUTE_TABLE
42205 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
42206 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42207 # undef TARGET_MERGE_DECL_ATTRIBUTES
42208 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
42209 #endif
42211 #undef TARGET_COMP_TYPE_ATTRIBUTES
42212 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
42214 #undef TARGET_INIT_BUILTINS
42215 #define TARGET_INIT_BUILTINS ix86_init_builtins
42216 #undef TARGET_BUILTIN_DECL
42217 #define TARGET_BUILTIN_DECL ix86_builtin_decl
42218 #undef TARGET_EXPAND_BUILTIN
42219 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
42221 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
42222 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
42223 ix86_builtin_vectorized_function
42225 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
42226 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
42228 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
42229 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
42231 #undef TARGET_VECTORIZE_BUILTIN_GATHER
42232 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
42234 #undef TARGET_BUILTIN_RECIPROCAL
42235 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
42237 #undef TARGET_ASM_FUNCTION_EPILOGUE
42238 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
42240 #undef TARGET_ENCODE_SECTION_INFO
42241 #ifndef SUBTARGET_ENCODE_SECTION_INFO
42242 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
42243 #else
42244 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
42245 #endif
42247 #undef TARGET_ASM_OPEN_PAREN
42249 #undef TARGET_ASM_CLOSE_PAREN
42252 #undef TARGET_ASM_BYTE_OP
42253 #define TARGET_ASM_BYTE_OP ASM_BYTE
42255 #undef TARGET_ASM_ALIGNED_HI_OP
42256 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
42257 #undef TARGET_ASM_ALIGNED_SI_OP
42258 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
42259 #ifdef ASM_QUAD
42260 #undef TARGET_ASM_ALIGNED_DI_OP
42261 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
42262 #endif
42264 #undef TARGET_PROFILE_BEFORE_PROLOGUE
42265 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
42267 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
42268 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
42270 #undef TARGET_ASM_UNALIGNED_HI_OP
42271 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
42272 #undef TARGET_ASM_UNALIGNED_SI_OP
42273 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
42274 #undef TARGET_ASM_UNALIGNED_DI_OP
42275 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
42277 #undef TARGET_PRINT_OPERAND
42278 #define TARGET_PRINT_OPERAND ix86_print_operand
42279 #undef TARGET_PRINT_OPERAND_ADDRESS
42280 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
42281 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
42282 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
42283 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
42284 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
42286 #undef TARGET_SCHED_INIT_GLOBAL
42287 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
42288 #undef TARGET_SCHED_ADJUST_COST
42289 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
42290 #undef TARGET_SCHED_ISSUE_RATE
42291 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
42292 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
42293 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
42294 ia32_multipass_dfa_lookahead
42296 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
42297 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
42299 #undef TARGET_MEMMODEL_CHECK
42300 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
42302 #ifdef HAVE_AS_TLS
42303 #undef TARGET_HAVE_TLS
42304 #define TARGET_HAVE_TLS true
42305 #endif
42306 #undef TARGET_CANNOT_FORCE_CONST_MEM
42307 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
42308 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
42309 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
42311 #undef TARGET_DELEGITIMIZE_ADDRESS
42312 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
42314 #undef TARGET_MS_BITFIELD_LAYOUT_P
42315 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
42317 #if TARGET_MACHO
42318 #undef TARGET_BINDS_LOCAL_P
42319 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
42320 #endif
42321 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42322 #undef TARGET_BINDS_LOCAL_P
42323 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
42324 #endif
42326 #undef TARGET_ASM_OUTPUT_MI_THUNK
42327 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
42328 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
42329 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
42331 #undef TARGET_ASM_FILE_START
42332 #define TARGET_ASM_FILE_START x86_file_start
42334 #undef TARGET_OPTION_OVERRIDE
42335 #define TARGET_OPTION_OVERRIDE ix86_option_override
42337 #undef TARGET_REGISTER_MOVE_COST
42338 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
42339 #undef TARGET_MEMORY_MOVE_COST
42340 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
42341 #undef TARGET_RTX_COSTS
42342 #define TARGET_RTX_COSTS ix86_rtx_costs
42343 #undef TARGET_ADDRESS_COST
42344 #define TARGET_ADDRESS_COST ix86_address_cost
42346 #undef TARGET_FIXED_CONDITION_CODE_REGS
42347 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
42348 #undef TARGET_CC_MODES_COMPATIBLE
42349 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
42351 #undef TARGET_MACHINE_DEPENDENT_REORG
42352 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
42354 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
42355 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
42357 #undef TARGET_BUILD_BUILTIN_VA_LIST
42358 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
42360 #undef TARGET_FOLD_BUILTIN
42361 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
42363 #undef TARGET_COMPARE_VERSION_PRIORITY
42364 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
42366 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
42367 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
42368 ix86_generate_version_dispatcher_body
42370 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
42371 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
42372 ix86_get_function_versions_dispatcher
42374 #undef TARGET_ENUM_VA_LIST_P
42375 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
42377 #undef TARGET_FN_ABI_VA_LIST
42378 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
42380 #undef TARGET_CANONICAL_VA_LIST_TYPE
42381 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
42383 #undef TARGET_EXPAND_BUILTIN_VA_START
42384 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
42386 #undef TARGET_MD_ASM_CLOBBERS
42387 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
42389 #undef TARGET_PROMOTE_PROTOTYPES
42390 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
42391 #undef TARGET_STRUCT_VALUE_RTX
42392 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
42393 #undef TARGET_SETUP_INCOMING_VARARGS
42394 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
42395 #undef TARGET_MUST_PASS_IN_STACK
42396 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
42397 #undef TARGET_FUNCTION_ARG_ADVANCE
42398 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
42399 #undef TARGET_FUNCTION_ARG
42400 #define TARGET_FUNCTION_ARG ix86_function_arg
42401 #undef TARGET_FUNCTION_ARG_BOUNDARY
42402 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
42403 #undef TARGET_PASS_BY_REFERENCE
42404 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
42405 #undef TARGET_INTERNAL_ARG_POINTER
42406 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
42407 #undef TARGET_UPDATE_STACK_BOUNDARY
42408 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
42409 #undef TARGET_GET_DRAP_RTX
42410 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
42411 #undef TARGET_STRICT_ARGUMENT_NAMING
42412 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
42413 #undef TARGET_STATIC_CHAIN
42414 #define TARGET_STATIC_CHAIN ix86_static_chain
42415 #undef TARGET_TRAMPOLINE_INIT
42416 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
42417 #undef TARGET_RETURN_POPS_ARGS
42418 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
42420 #undef TARGET_LEGITIMATE_COMBINED_INSN
42421 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
42423 #undef TARGET_ASAN_SHADOW_OFFSET
42424 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
42426 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
42427 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
42429 #undef TARGET_SCALAR_MODE_SUPPORTED_P
42430 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
42432 #undef TARGET_VECTOR_MODE_SUPPORTED_P
42433 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
42435 #undef TARGET_C_MODE_FOR_SUFFIX
42436 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
42438 #ifdef HAVE_AS_TLS
42439 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
42440 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
42441 #endif
42443 #ifdef SUBTARGET_INSERT_ATTRIBUTES
42444 #undef TARGET_INSERT_ATTRIBUTES
42445 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
42446 #endif
42448 #undef TARGET_MANGLE_TYPE
42449 #define TARGET_MANGLE_TYPE ix86_mangle_type
42451 #if !TARGET_MACHO
42452 #undef TARGET_STACK_PROTECT_FAIL
42453 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
42454 #endif
42456 #undef TARGET_FUNCTION_VALUE
42457 #define TARGET_FUNCTION_VALUE ix86_function_value
42459 #undef TARGET_FUNCTION_VALUE_REGNO_P
42460 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
42462 #undef TARGET_PROMOTE_FUNCTION_MODE
42463 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
42465 #undef TARGET_MEMBER_TYPE_FORCES_BLK
42466 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
42468 #undef TARGET_INSTANTIATE_DECLS
42469 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
42471 #undef TARGET_SECONDARY_RELOAD
42472 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
42474 #undef TARGET_CLASS_MAX_NREGS
42475 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
42477 #undef TARGET_PREFERRED_RELOAD_CLASS
42478 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
42479 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
42480 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
42481 #undef TARGET_CLASS_LIKELY_SPILLED_P
42482 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
42484 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
42485 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
42486 ix86_builtin_vectorization_cost
42487 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
42488 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
42489 ix86_vectorize_vec_perm_const_ok
42490 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
42491 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
42492 ix86_preferred_simd_mode
42493 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
42494 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
42495 ix86_autovectorize_vector_sizes
42496 #undef TARGET_VECTORIZE_INIT_COST
42497 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
42498 #undef TARGET_VECTORIZE_ADD_STMT_COST
42499 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
42500 #undef TARGET_VECTORIZE_FINISH_COST
42501 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
42502 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
42503 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
42505 #undef TARGET_SET_CURRENT_FUNCTION
42506 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
42508 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
42509 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
42511 #undef TARGET_OPTION_SAVE
42512 #define TARGET_OPTION_SAVE ix86_function_specific_save
42514 #undef TARGET_OPTION_RESTORE
42515 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
42517 #undef TARGET_OPTION_PRINT
42518 #define TARGET_OPTION_PRINT ix86_function_specific_print
42520 #undef TARGET_OPTION_FUNCTION_VERSIONS
42521 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
42523 #undef TARGET_CAN_INLINE_P
42524 #define TARGET_CAN_INLINE_P ix86_can_inline_p
42526 #undef TARGET_EXPAND_TO_RTL_HOOK
42527 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
42529 #undef TARGET_LEGITIMATE_ADDRESS_P
42530 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
42532 #undef TARGET_LRA_P
42533 #define TARGET_LRA_P hook_bool_void_true
42535 #undef TARGET_REGISTER_PRIORITY
42536 #define TARGET_REGISTER_PRIORITY ix86_register_priority
42538 #undef TARGET_LEGITIMATE_CONSTANT_P
42539 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
42541 #undef TARGET_FRAME_POINTER_REQUIRED
42542 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
42544 #undef TARGET_CAN_ELIMINATE
42545 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
42547 #undef TARGET_EXTRA_LIVE_ON_ENTRY
42548 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
42550 #undef TARGET_ASM_CODE_END
42551 #define TARGET_ASM_CODE_END ix86_code_end
42553 #undef TARGET_CONDITIONAL_REGISTER_USAGE
42554 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
42556 #if TARGET_MACHO
42557 #undef TARGET_INIT_LIBFUNCS
42558 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
42559 #endif
42561 #undef TARGET_SPILL_CLASS
42562 #define TARGET_SPILL_CLASS ix86_spill_class
42565 \f