| blob | 1e58e9d781912eb1eb764720a3baed96eec5f88c |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
70 /* This file should be included last. */
73 /* Defined for convenience. */
74 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
76 /* Classifies an address.
78 ADDRESS_REG_IMM
79 A simple base register plus immediate offset.
81 ADDRESS_REG_WB
82 A base register indexed by immediate offset with writeback.
84 ADDRESS_REG_REG
85 A base register indexed by (optionally scaled) register.
87 ADDRESS_REG_UXTW
88 A base register indexed by (optionally scaled) zero-extended register.
90 ADDRESS_REG_SXTW
91 A base register indexed by (optionally scaled) sign-extended register.
93 ADDRESS_LO_SUM
94 A LO_SUM rtx with a base register and "LO12" symbol relocation.
96 ADDRESS_SYMBOLIC:
97 A constant symbolic address, in pc-relative literal pool. */
100 ADDRESS_REG_IMM,
101 ADDRESS_REG_WB,
102 ADDRESS_REG_REG,
103 ADDRESS_REG_UXTW,
104 ADDRESS_REG_SXTW,
105 ADDRESS_LO_SUM,
106 ADDRESS_SYMBOLIC
107 };
111 rtx base;
112 rtx offset;
115 };
117 struct simd_immediate_info
118 {
119 rtx value;
124 };
126 /* The current code model. */
129 #ifdef HAVE_AS_TLS
130 #undef TARGET_HAVE_TLS
131 #define TARGET_HAVE_TLS 1
132 #endif
136 const_tree,
147 const_tree type,
151 /* Major revision number of the ARM Architecture implemented by the target. */
154 /* The processor for which instructions should be scheduled. */
157 /* Mask to specify which instruction scheduling options should be used. */
160 /* Global flag for PC relative loads. */
163 /* Support for command line parsing of boolean flags in the tuning
164 structures. */
165 struct aarch64_flag_desc
166 {
169 };
171 #define AARCH64_FUSION_PAIR(name, internal_name) \
172 { name, AARCH64_FUSE_##internal_name },
174 {
179 };
181 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
182 { name, AARCH64_EXTRA_TUNE_##internal_name },
184 {
189 };
191 /* Tuning parameters. */
194 {
195 {
200 },
207 };
210 {
211 {
216 },
223 };
226 {
227 {
232 },
239 };
242 {
243 {
248 },
255 };
258 {
259 {
264 },
271 };
274 {
275 {
280 },
287 };
290 {
292 /* Avoid the use of slow int<->fp moves for spilling by setting
293 their cost higher than memmov_cost. */
297 };
300 {
302 /* Avoid the use of slow int<->fp moves for spilling by setting
303 their cost higher than memmov_cost. */
307 };
310 {
312 /* Avoid the use of slow int<->fp moves for spilling by setting
313 their cost higher than memmov_cost. */
317 };
320 {
322 /* Avoid the use of slow int<->fp moves for spilling by setting
323 their cost higher than memmov_cost (actual, 4 and 9). */
327 };
330 {
335 };
338 {
340 /* Avoid the use of slow int<->fp moves for spilling by setting
341 their cost higher than memmov_cost. */
345 };
348 {
350 /* Avoid the use of int<->fp moves for spilling. */
354 };
357 {
359 /* Avoid the use of int<->fp moves for spilling. */
363 };
365 /* Generic costs for vector insn classes. */
367 {
383 };
385 /* ThunderX costs for vector insn classes. */
387 {
403 };
405 /* Generic costs for vector insn classes. */
407 {
423 };
426 {
442 };
444 /* Generic costs for vector insn classes. */
446 {
462 };
464 /* Costs for vector insn classes for Vulcan. */
466 {
482 };
484 /* Generic costs for branch instructions. */
486 {
489 };
491 /* Branch costs for Cortex-A57. */
493 {
496 };
498 /* Branch costs for Vulcan. */
500 {
503 };
505 /* Generic approximation modes. */
507 {
510 AARCH64_APPROX_NONE /* recip_sqrt */
511 };
513 /* Approximation modes for Exynos M1. */
515 {
518 AARCH64_APPROX_ALL /* recip_sqrt */
519 };
521 /* Approximation modes for X-Gene 1. */
523 {
526 AARCH64_APPROX_ALL /* recip_sqrt */
527 };
530 {
552 };
555 {
578 };
581 {
604 };
607 {
630 };
633 {
656 };
659 {
682 };
685 {
707 };
710 {
732 };
735 {
757 };
760 {
783 };
786 {
808 };
810 /* Support for fine-grained override of the tuning structures. */
811 struct aarch64_tuning_override_function
812 {
815 };
820 static const struct aarch64_tuning_override_function
821 aarch64_tuning_override_functions[] =
822 {
826 };
828 /* A processor implementing AArch64. */
829 struct processor
830 {
838 };
840 /* Architectures implementing AArch64. */
842 {
843 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
844 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
847 };
849 /* Processor cores implementing AArch64. */
851 {
852 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
853 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
854 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
855 FLAGS, &COSTS##_tunings},
860 };
863 /* Target specification. These are populated by the -march, -mtune, -mcpu
864 handling code or by target attributes. */
869 /* The current tuning set. */
872 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
874 /* An ISA extension in the co-processor and main instruction set space. */
875 struct aarch64_option_extension
876 {
880 };
883 {
887 }
888 aarch64_cc;
890 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
892 /* The condition codes of the processor, and the inverse function. */
894 {
897 };
899 /* Generate code to enable conditional branches in functions over 1 MiB. */
903 {
920 }
922 void
924 {
928 else
930 }
932 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
933 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
934 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
935 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
936 cost (in this case the best class is the lowest cost one). Using ALL_REGS
937 irrespectively of its cost results in bad allocations with many redundant
938 int<->FP moves which are expensive on various cores.
939 To avoid this we don't allow ALL_REGS as the allocno class, but force a
940 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
941 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
942 Otherwise set the allocno class depending on the mode.
943 The result of this is that it is no longer inefficient to have a higher
944 memory move cost than the register move cost.
945 */
947 static reg_class_t
949 reg_class_t best_class)
950 {
961 }
963 static unsigned int
965 {
969 }
971 static int
974 {
982 }
984 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
985 unsigned
987 {
995 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
996 equivalent DWARF register. */
998 }
1000 /* Return TRUE if MODE is any of the large INT modes. */
1001 static bool
1003 {
1005 }
1007 /* Return TRUE if MODE is any of the vector modes. */
1008 static bool
1010 {
1013 }
1015 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1016 static bool
1019 {
1027 }
1029 /* Implement HARD_REGNO_NREGS. */
1031 int
1033 {
1035 {
1041 }
1043 }
1045 /* Implement HARD_REGNO_MODE_OK. */
1047 int
1049 {
1054 /* The purpose of comparing with ptr_mode is to support the
1055 global register variable associated with the stack pointer
1056 register via the syntax of asm ("wsp") in ILP32. */
1066 {
1068 return
1070 else
1072 }
1075 }
1077 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1078 machine_mode
1080 machine_mode mode)
1081 {
1082 /* Handle modes that fit within single registers. */
1084 {
1087 else
1089 }
1090 /* Fall back to generic for multi-reg and very large modes. */
1091 else
1093 }
1095 /* Return true if calls to DECL should be treated as
1096 long-calls (ie called via a register). */
1097 static bool
1099 {
1101 }
1103 /* Return true if calls to symbol-ref SYM should be treated as
1104 long-calls (ie called via a register). */
1105 bool
1107 {
1109 }
1111 /* Return true if calls to symbol-ref SYM should not go through
1112 plt stubs. */
1114 bool
1116 {
1120 && decl
1121 && (!flag_plt
1127 }
1129 /* Return true if the offsets to a zero/sign-extract operation
1130 represent an expression that matches an extend operation. The
1131 operands represent the paramters from
1133 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1134 bool
1136 rtx extract_imm)
1137 {
1154 }
1156 /* Emit an insn that's a simple single-set. Both the operands must be
1157 known to be valid. */
1160 {
1162 }
1164 /* X and Y are two things to compare using CODE. Emit the compare insn and
1165 return the rtx for register 0 in the proper mode. */
1166 rtx
1168 {
1174 }
1176 /* Build the SYMBOL_REF for __tls_get_addr. */
1180 rtx
1182 {
1186 }
1188 /* Return the TLS model to use for ADDR. */
1190 static enum tls_model
1192 {
1197 {
1201 }
1206 }
1208 /* We'll allow lo_sum's in addresses in our legitimate addresses
1209 so that combine would take care of combining addresses where
1210 necessary, but for generation purposes, we'll generate the address
1211 as :
1212 RTL Absolute
1213 tmp = hi (symbol_ref); adrp x1, foo
1214 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1215 nop
1217 PIC TLS
1218 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1219 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1220 bl __tls_get_addr
1221 nop
1223 Load TLS symbol, depending on TLS mechanism and TLS access model.
1225 Global Dynamic - Traditional TLS:
1226 adrp tmp, :tlsgd:imm
1227 add dest, tmp, #:tlsgd_lo12:imm
1228 bl __tls_get_addr
1230 Global Dynamic - TLS Descriptors:
1231 adrp dest, :tlsdesc:imm
1232 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1233 add dest, dest, #:tlsdesc_lo12:imm
1234 blr tmp
1235 mrs tp, tpidr_el0
1236 add dest, dest, tp
1238 Initial Exec:
1239 mrs tp, tpidr_el0
1240 adrp tmp, :gottprel:imm
1241 ldr dest, [tmp, #:gottprel_lo12:imm]
1242 add dest, dest, tp
1244 Local Exec:
1245 mrs tp, tpidr_el0
1246 add t0, tp, #:tprel_hi12:imm, lsl #12
1247 add t0, t0, #:tprel_lo12_nc:imm
1248 */
1250 static void
1253 {
1255 {
1257 {
1258 /* In ILP32, the mode of dest can be either SImode or DImode. */
1270 }
1277 {
1280 rtx insn;
1281 rtx mem;
1283 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1284 here before rtl expand. Tree IVOPT will generate rtl pattern to
1285 decide rtx costs, in which case pic_offset_table_rtx is not
1286 initialized. For that case no need to generate the first adrp
1287 instruction as the final cost for global variable access is
1288 one instruction. */
1290 {
1291 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1292 using the page base as GOT base, the first page may be wasted,
1293 in the worst scenario, there is only 28K space for GOT).
1295 The generate instruction sequence for accessing global variable
1296 is:
1298 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1300 Only one instruction needed. But we must initialize
1301 pic_offset_table_rtx properly. We generate initialize insn for
1302 every global access, and allow CSE to remove all redundant.
1304 The final instruction sequences will look like the following
1305 for multiply global variables access.
1307 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1309 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1310 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1311 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1312 ... */
1321 }
1324 {
1327 else
1331 }
1332 else
1333 {
1338 }
1340 /* The operand is expected to be MEM. Whenever the related insn
1341 pattern changed, above code which calculate mem should be
1342 updated. */
1348 }
1351 {
1352 /* In ILP32, the mode of dest can be either SImode or DImode,
1353 while the got entry is always of SImode size. The mode of
1354 dest depends on how dest is used: if dest is assigned to a
1355 pointer (e.g. in the memory), it has SImode; it may have
1356 DImode if dest is dereferenced to access the memeory.
1357 This is why we have to handle three different ldr_got_small
1358 patterns here (two patterns for ILP32). */
1360 rtx insn;
1361 rtx mem;
1370 {
1373 else
1377 }
1378 else
1379 {
1384 }
1391 }
1394 {
1402 else
1410 }
1413 {
1416 rtx tp;
1420 /* In ILP32, the got entry is always of SImode size. Unlike
1421 small GOT, the dest is fixed at reg 0. */
1424 else
1434 }
1437 {
1438 /* In ILP32, the mode of dest can be either SImode or DImode,
1439 while the got entry is always of SImode size. The mode of
1440 dest depends on how dest is used: if dest is assigned to a
1441 pointer (e.g. in the memory), it has SImode; it may have
1442 DImode if dest is dereferenced to access the memeory.
1443 This is why we have to handle three different tlsie_small
1444 patterns here (two patterns for ILP32). */
1450 {
1453 else
1454 {
1457 }
1458 }
1459 else
1460 {
1463 }
1468 }
1474 {
1482 {
1505 }
1509 }
1516 {
1521 {
1524 else
1525 {
1528 }
1529 }
1530 else
1531 {
1534 }
1538 }
1542 }
1543 }
1545 /* Emit a move from SRC to DEST. Assume that the move expanders can
1546 handle all moves if !can_create_pseudo_p (). The distinction is
1547 important because, unlike emit_move_insn, the move expanders know
1548 how to force Pmode objects into the constant pool even when the
1549 constant pool address is not itself legitimate. */
1550 static rtx
1552 {
1556 }
1558 /* Split a 128-bit move operation into two 64-bit move operations,
1559 taking care to handle partial overlap of register to register
1560 copies. Special cases are needed when moving between GP regs and
1561 FP regs. SRC can be a register, constant or memory; DST a register
1562 or memory. If either operand is memory it must not have any side
1563 effects. */
1564 void
1566 {
1577 {
1581 /* Handle FP <-> GP regs. */
1583 {
1588 {
1591 }
1592 else
1593 {
1596 }
1598 }
1600 {
1605 {
1608 }
1609 else
1610 {
1613 }
1615 }
1616 }
1623 /* At most one pairing may overlap. */
1625 {
1628 }
1629 else
1630 {
1633 }
1634 }
1636 bool
1638 {
1641 }
1643 /* Split a complex SIMD combine. */
1645 void
1647 {
1654 {
1658 {
1682 }
1686 }
1687 }
1689 /* Split a complex SIMD move. */
1691 void
1693 {
1700 {
1706 {
1730 }
1734 }
1735 }
1737 bool
1740 {
1744 }
1747 static rtx
1749 {
1752 else
1753 {
1756 }
1757 }
1760 static rtx
1762 {
1764 {
1765 rtx high;
1766 /* Load the full offset into a register. This
1767 might be improvable in the future. */
1773 }
1775 }
1777 static int
1779 machine_mode mode)
1780 {
1789 {
1793 }
1796 {
1798 {
1803 else
1806 }
1808 }
1810 /* Remaining cases are all for DImode. */
1819 {
1820 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1821 For a 64-bit bitmask try whether changing 16 bits to all ones or
1822 zeroes creates a valid bitmask. To check any repeated bitmask,
1823 try using 16 bits from the other 32-bit half of val. */
1826 {
1837 }
1839 {
1841 {
1845 }
1847 }
1848 }
1850 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1851 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1852 otherwise skip zero bits. */
1864 {
1870 num_insns ++;
1871 }
1874 }
1877 void
1879 {
1884 /* Check on what type of symbol it is. */
1888 {
1892 /* If we have (const (plus symbol offset)), separate out the offset
1893 before we start classifying the symbol. */
1898 {
1902 {
1908 }
1913 /* If we aren't generating PC relative literals, then
1914 we need to expand the literal pool access carefully.
1915 This is something that needs to be done in a number
1916 of places, so could well live as a separate function. */
1918 {
1923 }
1940 {
1946 }
1947 /* FALLTHRU */
1960 }
1961 }
1964 {
1967 else
1968 {
1972 }
1975 }
1978 }
1980 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
1981 temporary value if necessary. FRAME_RELATED_P should be true if
1982 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
1983 to the generated instructions. If SCRATCHREG is known to hold
1984 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
1985 immediate again.
1987 Since this function may be used to adjust the stack pointer, we must
1988 ensure that it cannot cause transient stack deallocation (for example
1989 by first incrementing SP and then decrementing when adjusting by a
1990 large immediate). */
1992 static void
1996 {
2004 /* Single instruction adjustment. */
2006 {
2010 }
2012 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
2013 Only do this if mdelta is not a 16-bit move as adjusting using a move
2014 is better. */
2016 {
2025 }
2027 /* Emit a move immediate if required and an addition/subtraction. */
2034 {
2038 }
2039 }
2043 HOST_WIDE_INT delta)
2044 {
2046 }
2050 {
2053 }
2057 {
2060 }
2062 static bool
2064 tree exp ATTRIBUTE_UNUSED)
2065 {
2066 /* Currently, always true. */
2068 }
2070 /* Implement TARGET_PASS_BY_REFERENCE. */
2072 static bool
2074 machine_mode mode,
2075 const_tree type,
2077 {
2078 HOST_WIDE_INT size;
2079 machine_mode dummymode;
2082 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2086 /* Aggregates are passed by reference based on their size. */
2088 {
2090 }
2092 /* Variable sized arguments are always returned by reference. */
2096 /* Can this be a candidate to be passed in fp/simd register(s)? */
2099 NULL))
2102 /* Arguments which are variable sized or larger than 2 registers are
2103 passed by reference unless they are a homogenous floating point
2104 aggregate. */
2106 }
2108 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2109 static bool
2111 {
2112 machine_mode dummy_mode;
2115 /* Never happens in little-endian mode. */
2119 /* Only composite types smaller than or equal to 16 bytes can
2120 be potentially returned in registers. */
2126 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2127 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2128 is always passed/returned in the least significant bits of fp/simd
2129 register(s). */
2135 }
2137 /* Implement TARGET_FUNCTION_VALUE.
2138 Define how to find the value returned by a function. */
2140 static rtx
2143 {
2144 machine_mode mode;
2147 machine_mode ag_mode;
2154 {
2158 {
2161 }
2162 }
2166 {
2168 {
2171 }
2172 else
2173 {
2175 rtx par;
2179 {
2184 }
2186 }
2187 }
2188 else
2190 }
2192 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2193 Return true if REGNO is the number of a hard register in which the values
2194 of called function may come back. */
2196 static bool
2198 {
2199 /* Maximum of 16 bytes can be returned in the general registers. Examples
2200 of 16-byte return values are: 128-bit integers and 16-byte small
2201 structures (excluding homogeneous floating-point aggregates). */
2205 /* Up to four fp/simd registers can return a function value, e.g. a
2206 homogeneous floating-point aggregate having four members. */
2211 }
2213 /* Implement TARGET_RETURN_IN_MEMORY.
2215 If the type T of the result of a function is such that
2216 void func (T arg)
2217 would require that arg be passed as a value in a register (or set of
2218 registers) according to the parameter passing rules, then the result
2219 is returned in the same registers as would be used for such an
2220 argument. */
2222 static bool
2224 {
2225 HOST_WIDE_INT size;
2226 machine_mode ag_mode;
2232 /* Simple scalar types always returned in registers. */
2236 type,
2239 NULL))
2242 /* Types larger than 2 registers returned in memory. */
2245 }
2247 static bool
2250 {
2253 type,
2255 nregs,
2256 NULL);
2257 }
2259 struct aarch64_fn_arg_alignment
2260 {
2261 /* Alignment for FIELD_DECLs in function arguments. */
2263 /* Alignment for decls other than FIELD_DECLs in function arguments. */
2265 };
2267 /* Given MODE and TYPE of a function argument, return a pair of alignments in
2268 bits. The idea is to suppress any stronger alignment requested by
2269 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2270 This is a helper function for local use only. */
2272 static struct aarch64_fn_arg_alignment
2274 {
2280 {
2283 }
2291 {
2294 }
2297 {
2300 }
2303 {
2306 else
2308 }
2311 }
2313 /* Layout a function argument according to the AAPCS64 rules. The rule
2314 numbers refer to the rule numbers in the AAPCS64. */
2316 static void
2318 const_tree type,
2320 {
2324 HOST_WIDE_INT size;
2326 /* We need to do this once per argument. */
2332 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2333 size
2335 UNITS_PER_WORD);
2339 mode,
2340 type,
2343 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2344 The following code thus handles passing by SIMD/FP registers first. */
2348 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2349 and homogenous short-vector aggregates (HVA). */
2351 {
2356 {
2359 {
2362 }
2363 else
2364 {
2365 rtx par;
2369 {
2372 tmp = gen_rtx_EXPR_LIST
2376 }
2378 }
2380 }
2381 else
2382 {
2383 /* C.3 NSRN is set to 8. */
2386 }
2387 }
2392 /* C6 - C9. though the sign and zero extension semantics are
2393 handled elsewhere. This is the case where the argument fits
2394 entirely general registers. */
2396 {
2400 /* C.8 if the argument has an alignment of 16 then the NGRN is
2401 rounded up to the next even number. */
2403 {
2404 struct aarch64_fn_arg_alignment aa
2407 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
2408 comparisons are there because for > 16 * BITS_PER_UNIT
2409 alignment nregs should be > 2 and therefore it should be
2410 passed by reference rather than value. */
2413 && warn_psabi
2416 "parameter passing for argument of type %qT "
2419 {
2422 }
2423 }
2425 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2426 A reg is still generated for it, but the caller should be smart
2427 enough not to use it. */
2430 else
2431 {
2432 rtx par;
2437 {
2442 }
2444 }
2448 }
2450 /* C.11 */
2453 /* The argument is passed on stack; record the needed number of words for
2454 this argument and align the total size if necessary. */
2455 on_stack:
2457 struct aarch64_fn_arg_alignment aa
2464 }
2466 /* Implement TARGET_FUNCTION_ARG. */
2468 static rtx
2471 {
2480 }
2482 void
2484 const_tree fntype ATTRIBUTE_UNUSED,
2485 rtx libname ATTRIBUTE_UNUSED,
2486 const_tree fndecl ATTRIBUTE_UNUSED,
2488 {
2502 {
2509 }
2511 }
2513 static void
2515 machine_mode mode,
2516 const_tree type,
2518 {
2521 {
2531 }
2532 }
2534 bool
2536 {
2539 }
2541 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2542 PARM_BOUNDARY bits of alignment, but will be given anything up
2543 to STACK_BOUNDARY bits if the type requires it. This makes sure
2544 that both before and after the layout of each argument, the Next
2545 Stacked Argument Address (NSAA) will have a minimum alignment of
2546 8 bytes. */
2548 static unsigned int
2550 {
2551 struct aarch64_fn_arg_alignment aa
2554 aa.warn_alignment
2562 }
2564 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2566 Return true if an argument passed on the stack should be padded upwards,
2567 i.e. if the least-significant byte of the stack slot has useful data.
2569 Small aggregate types are placed in the lowest memory address.
2571 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2573 bool
2575 {
2576 /* On little-endian targets, the least significant byte of every stack
2577 argument is passed at the lowest byte address of the stack slot. */
2581 /* Otherwise, integral, floating-point and pointer types are padded downward:
2582 the least significant byte of a stack argument is passed at the highest
2583 byte address of the stack slot. */
2590 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2592 }
2594 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2596 It specifies padding for the last (may also be the only)
2597 element of a block move between registers and memory. If
2598 assuming the block is in the memory, padding upward means that
2599 the last element is padded after its highest significant byte,
2600 while in downward padding, the last element is padded at the
2601 its least significant byte side.
2603 Small aggregates and small complex types are always padded
2604 upwards.
2606 We don't need to worry about homogeneous floating-point or
2607 short-vector aggregates; their move is not affected by the
2608 padding direction determined here. Regardless of endianness,
2609 each element of such an aggregate is put in the least
2610 significant bits of a fp/simd register.
2612 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2613 register has useful data, and return the opposite if the most
2614 significant byte does. */
2616 bool
2619 {
2621 /* Small composite types are always padded upward. */
2623 {
2628 }
2630 /* Otherwise, use the default padding. */
2632 }
2634 static machine_mode
2636 {
2638 }
2640 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2642 /* We use the 12-bit shifted immediate arithmetic instructions so values
2643 must be multiple of (1 << 12), i.e. 4096. */
2644 #define ARITH_FACTOR 4096
2646 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2647 #error Cannot use simple address calculation for stack probing
2648 #endif
2650 /* The pair of scratch registers used for stack probing. */
2651 #define PROBE_STACK_FIRST_REG 9
2652 #define PROBE_STACK_SECOND_REG 10
2654 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2655 inclusive. These are offsets from the current stack pointer. */
2657 static void
2659 {
2662 /* See the same assertion on PROBE_INTERVAL above. */
2665 /* See if we have a constant small number of probes to generate. If so,
2666 that's the easy case. */
2668 {
2675 }
2677 /* The run-time loop is made up of 8 insns in the generic case while the
2678 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2680 {
2685 stack_pointer_rtx,
2689 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2690 it exceeds SIZE. If only two probes are needed, this will not
2691 generate any code. Then probe at FIRST + SIZE. */
2693 {
2697 }
2701 {
2706 }
2707 else
2709 }
2711 /* Otherwise, do the same as above, but in a loop. Note that we must be
2712 extra careful with variables wrapping around because we might be at
2713 the very top (or the very bottom) of the address space and we have
2714 to be able to handle this case properly; in particular, we use an
2715 equality test for the loop condition. */
2716 else
2717 {
2720 /* Step 1: round SIZE to the previous multiple of the interval. */
2725 /* Step 2: compute initial and final value of the loop counter. */
2727 /* TEST_ADDR = SP + FIRST. */
2731 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2737 /* Step 3: the loop
2739 do
2740 {
2741 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2742 probe at TEST_ADDR
2743 }
2744 while (TEST_ADDR != LAST_ADDR)
2746 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2747 until it is equal to ROUNDED_SIZE. */
2752 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2753 that SIZE is equal to ROUNDED_SIZE. */
2756 {
2760 {
2765 }
2766 else
2768 }
2769 }
2771 /* Make sure nothing is scheduled before we are done. */
2773 }
2775 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2776 absolute addresses. */
2780 {
2787 /* Loop. */
2790 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2795 /* Probe at TEST_ADDR. */
2798 /* Test if TEST_ADDR == LAST_ADDR. */
2802 /* Branch. */
2808 }
2810 static bool
2812 {
2813 /* In aarch64_override_options_after_change
2814 flag_omit_leaf_frame_pointer turns off the frame pointer by
2815 default. Turn it back on now if we've not got a leaf
2816 function. */
2821 /* Force a frame pointer for EH returns so the return address is at FP+8. */
2826 }
2828 /* Mark the registers that need to be saved by the callee and calculate
2829 the size of the callee-saved registers area and frame record (both FP
2830 and LR may be omitted). */
2831 static void
2833 {
2840 #define SLOT_NOT_REQUIRED (-2)
2841 #define SLOT_REQUIRED (-1)
2846 /* First mark all the registers that really need to be saved... */
2853 /* ... that includes the eh data registers (if needed)... */
2859 /* ... and any callee saved register that dataflow says is live. */
2869 {
2872 }
2875 {
2876 /* FP and LR are placed in the linkage record. */
2882 }
2884 /* Now assign stack slots for them. */
2887 {
2894 }
2902 {
2903 /* If there is an alignment gap between integer and fp callee-saves,
2904 allocate the last fp register to it if possible. */
2906 {
2909 }
2918 }
2924 HOST_WIDE_INT varargs_and_saved_regs_size
2951 {
2952 /* Simple, small frame with no outgoing arguments:
2953 stp reg1, reg2, [sp, -frame_size]!
2954 stp reg3, reg4, [sp, 16] */
2956 }
2961 {
2962 /* Frame with small outgoing arguments:
2963 sub sp, sp, frame_size
2964 stp reg1, reg2, [sp, outgoing_args_size]
2965 stp reg3, reg4, [sp, outgoing_args_size + 16] */
2969 }
2971 {
2972 /* Frame with large outgoing arguments but a small local area:
2973 stp reg1, reg2, [sp, -hard_fp_offset]!
2974 stp reg3, reg4, [sp, 16]
2975 sub sp, sp, outgoing_args_size */
2979 }
2982 {
2983 /* Frame with large local area and outgoing arguments (this pushes the
2984 callee-saves first, followed by the locals and outgoing area):
2985 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
2986 stp reg3, reg4, [sp, 16]
2987 sub sp, sp, frame_size - varargs_and_saved_regs_size */
2993 }
2994 else
2995 {
2996 /* Frame with large local area and outgoing arguments using frame pointer:
2997 sub sp, sp, hard_fp_offset
2998 stp x29, x30, [sp, 0]
2999 add x29, sp, 0
3000 stp reg3, reg4, [sp, 16]
3001 sub sp, sp, outgoing_args_size */
3005 }
3008 }
3010 /* Return true if the register REGNO is saved on entry to
3011 the current function. */
3013 static bool
3015 {
3017 }
3019 /* Return the next register up from REGNO up to LIMIT for the callee
3020 to save. */
3022 static unsigned
3024 {
3026 regno ++;
3028 }
3030 /* Push the register number REGNO of mode MODE to the stack with write-back
3031 adjusting the stack by ADJUSTMENT. */
3033 static void
3035 HOST_WIDE_INT adjustment)
3036 {
3047 }
3049 /* Generate and return an instruction to store the pair of registers
3050 REG and REG2 of mode MODE to location BASE with write-back adjusting
3051 the stack location BASE by ADJUSTMENT. */
3053 static rtx
3055 HOST_WIDE_INT adjustment)
3056 {
3058 {
3069 }
3070 }
3072 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3073 stack pointer by ADJUSTMENT. */
3075 static void
3077 {
3092 }
3094 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3095 adjusting it by ADJUSTMENT afterwards. */
3097 static rtx
3099 HOST_WIDE_INT adjustment)
3100 {
3102 {
3111 }
3112 }
3114 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3115 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3116 into CFI_OPS. */
3118 static void
3121 {
3128 {
3132 }
3133 else
3134 {
3139 }
3140 }
3142 /* Generate and return a store pair instruction of mode MODE to store
3143 register REG1 to MEM1 and register REG2 to MEM2. */
3145 static rtx
3147 rtx reg2)
3148 {
3150 {
3159 }
3160 }
3162 /* Generate and regurn a load pair isntruction of mode MODE to load register
3163 REG1 from MEM1 and register REG2 from MEM2. */
3165 static rtx
3167 rtx mem2)
3168 {
3170 {
3179 }
3180 }
3182 /* Return TRUE if return address signing should be enabled for the current
3183 function, otherwise return FALSE. */
3185 bool
3187 {
3188 /* This function should only be called after frame laid out. */
3191 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
3192 if it's LR is pushed onto stack. */
3196 }
3198 /* Emit code to save the callee-saved registers from register number START
3199 to LIMIT to the stack at the location starting at offset START_OFFSET,
3200 skipping any write-back candidates if SKIP_WB is true. */
3202 static void
3205 {
3215 {
3217 HOST_WIDE_INT offset;
3230 offset));
3239 {
3241 rtx mem2;
3245 offset));
3247 reg2));
3249 /* The first part of a frame-related parallel insn is
3250 always assumed to be relevant to the frame
3251 calculations; subsequent parts, are only
3252 frame-related if explicitly marked. */
3255 }
3256 else
3260 }
3261 }
3263 /* Emit code to restore the callee registers of mode MODE from register
3264 number START up to and including LIMIT. Restore from the stack offset
3265 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3266 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3268 static void
3272 {
3278 HOST_WIDE_INT offset;
3283 {
3304 {
3306 rtx mem2;
3314 }
3315 else
3318 }
3319 }
3323 HOST_WIDE_INT offset)
3324 {
3326 }
3330 {
3334 }
3336 bool
3338 {
3342 }
3344 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
3346 static sbitmap
3348 {
3354 /* The registers we need saved to the frame. */
3357 {
3362 /* Check that we can access the stack slot of the register with one
3363 direct load with no adjustments needed. */
3366 }
3368 /* Don't mess with the hard frame pointer. */
3374 /* If aarch64_layout_frame has chosen registers to store/restore with
3375 writeback don't interfere with them to avoid having to output explicit
3376 stack adjustment instructions. */
3386 }
3388 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
3390 static sbitmap
3392 {
3400 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
3409 }
3411 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
3412 Nothing to do for aarch64. */
3414 static void
3416 {
3417 }
3419 /* Return the next set bit in BMP from START onwards. Return the total number
3420 of bits in BMP if no set bit is found at or after START. */
3422 static unsigned int
3424 {
3435 }
3437 /* Do the work for aarch64_emit_prologue_components and
3438 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
3439 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
3440 for these components or the epilogue sequence. That is, it determines
3441 whether we should emit stores or loads and what kind of CFA notes to attach
3442 to the insns. Otherwise the logic for the two sequences is very
3443 similar. */
3445 static void
3447 {
3449 ? HARD_FRAME_POINTER_REGNUM
3457 {
3458 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
3459 so DFmode for the vector registers is enough. */
3471 /* No more registers to handle after REGNO.
3472 Emit a single save/restore and exit. */
3474 {
3479 else
3482 }
3485 /* The next register is not of the same class or its offset is not
3486 mergeable with the current one into a pair. */
3491 {
3496 else
3501 }
3503 /* REGNO2 can be saved/restored in a pair with REGNO. */
3515 else
3520 {
3523 }
3524 else
3525 {
3528 }
3531 }
3532 }
3534 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
3536 static void
3538 {
3540 }
3542 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
3544 static void
3546 {
3548 }
3550 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
3552 static void
3554 {
3558 }
3560 /* AArch64 stack frames generated by this compiler look like:
3562 +-------------------------------+
3563 | |
3564 | incoming stack arguments |
3565 | |
3566 +-------------------------------+
3567 | | <-- incoming stack pointer (aligned)
3568 | callee-allocated save area |
3569 | for register varargs |
3570 | |
3571 +-------------------------------+
3572 | local variables | <-- frame_pointer_rtx
3573 | |
3574 +-------------------------------+
3575 | padding0 | \
3576 +-------------------------------+ |
3577 | callee-saved registers | | frame.saved_regs_size
3578 +-------------------------------+ |
3579 | LR' | |
3580 +-------------------------------+ |
3581 | FP' | / <- hard_frame_pointer_rtx (aligned)
3582 +-------------------------------+
3583 | dynamic allocation |
3584 +-------------------------------+
3585 | padding |
3586 +-------------------------------+
3587 | outgoing stack arguments | <-- arg_pointer
3588 | |
3589 +-------------------------------+
3590 | | <-- stack_pointer_rtx (aligned)
3592 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3593 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3594 unchanged. */
3596 /* Generate the prologue instructions for entry into a function.
3597 Establish the stack frame by decreasing the stack pointer with a
3598 properly calculated size and, if necessary, create a frame record
3599 filled with the values of LR and previous frame pointer. The
3600 current FP is also set up if it is in use. */
3602 void
3604 {
3616 /* Sign return address for functions. */
3618 {
3622 }
3628 {
3630 {
3634 }
3637 }
3645 {
3650 stack_pointer_rtx,
3654 }
3661 }
3663 /* Return TRUE if we can use a simple_return insn.
3665 This function checks whether the callee saved stack is empty, which
3666 means no restore actions are need. The pro_and_epilogue will use
3667 this to check whether shrink-wrapping opt is feasible. */
3669 bool
3671 {
3681 }
3683 /* Generate the epilogue instructions for returning from a function.
3684 This is almost exactly the reverse of the prolog sequence, except
3685 that we need to insert barriers to avoid scheduling loads that read
3686 from a deallocated stack, and we optimize the unwind records by
3687 emitting them all together if possible. */
3688 void
3690 {
3702 /* We need to add memory barrier to prevent read from deallocated stack. */
3706 /* Emit a barrier to prevent loads from a deallocated stack. */
3709 {
3712 }
3714 /* Restore the stack pointer from the frame pointer if it may not
3715 be the same as the stack pointer. */
3717 {
3719 hard_frame_pointer_rtx,
3721 /* If writeback is used when restoring callee-saves, the CFA
3722 is restored on the instruction doing the writeback. */
3724 }
3725 else
3740 {
3741 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3747 }
3752 {
3753 /* Emit delayed restores and reset the CFA to be SP. */
3758 }
3760 /* We prefer to emit the combined return/authenticate instruction RETAA,
3761 however there are three cases in which we must instead emit an explicit
3762 authentication instruction.
3764 1) Sibcalls don't return in a normal way, so if we're about to call one
3765 we must authenticate.
3767 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
3768 generating code for !TARGET_ARMV8_3 we can't use it and must
3769 explicitly authenticate.
3771 3) On an eh_return path we make extra stack adjustments to update the
3772 canonical frame address to be the exception handler's CFA. We want
3773 to authenticate using the CFA of the function which calls eh_return.
3774 */
3777 {
3781 }
3783 /* Stack adjustment for exception handler. */
3785 {
3786 /* We need to unwind the stack by the offset computed by
3787 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3788 to be SP; letting the CFA move during this adjustment
3789 is just as correct as retaining the CFA from the body
3790 of the function. Therefore, do nothing special. */
3792 }
3797 }
3799 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
3800 normally or return to a previous frame after unwinding.
3802 An EH return uses a single shared return sequence. The epilogue is
3803 exactly like a normal epilogue except that it has an extra input
3804 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
3805 that must be applied after the frame has been destroyed. An extra label
3806 is inserted before the epilogue which initializes this register to zero,
3807 and this is the entry point for a normal return.
3809 An actual EH return updates the return address, initializes the stack
3810 adjustment and jumps directly into the epilogue (bypassing the zeroing
3811 of the adjustment). Since the return address is typically saved on the
3812 stack when a function makes a call, the saved LR must be updated outside
3813 the epilogue.
3815 This poses problems as the store is generated well before the epilogue,
3816 so the offset of LR is not known yet. Also optimizations will remove the
3817 store as it appears dead, even after the epilogue is generated (as the
3818 base or offset for loading LR is different in many cases).
3820 To avoid these problems this implementation forces the frame pointer
3821 in eh_return functions so that the location of LR is fixed and known early.
3822 It also marks the store volatile, so no optimization is permitted to
3823 remove the store. */
3824 rtx
3826 {
3830 /* Mark the store volatile, so no optimization is permitted to remove it. */
3833 }
3835 /* Output code to add DELTA to the first argument, and then jump
3836 to FUNCTION. Used for C++ multiple inheritance. */
3837 static void
3839 HOST_WIDE_INT delta,
3840 HOST_WIDE_INT vcall_offset,
3841 tree function)
3842 {
3843 /* The this pointer is always in x0. Note that this differs from
3844 Arm where the this pointer maybe bumped to r1 if r0 is required
3845 to return a pointer to an aggregate. On AArch64 a result value
3846 pointer will be in x8. */
3856 else
3857 {
3866 {
3870 else
3872 }
3876 else
3883 else
3884 {
3886 Pmode);
3888 }
3892 else
3898 }
3900 /* Generate a tail call to the target function. */
3902 {
3905 }
3917 /* Stop pretending to be a post-reload pass. */
3919 }
3921 static bool
3923 {
3928 {
3932 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3933 TLS offsets, not real symbol references. */
3936 }
3938 }
3941 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3942 a left shift of 0 or 12 bits. */
3943 bool
3945 {
3948 );
3949 }
3952 /* Return true if val is an immediate that can be loaded into a
3953 register by a MOVZ instruction. */
3954 static bool
3956 {
3958 {
3962 }
3963 else
3964 {
3965 /* Ignore sign extension. */
3967 }
3970 }
3972 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
3975 {
3981 };
3984 /* Return true if val is a valid bitmask immediate. */
3986 bool
3988 {
3992 /* Check for a single sequence of one bits and return quickly if so.
3993 The special cases of all ones and all zeroes returns false. */
4000 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
4004 /* Invert if the immediate doesn't start with a zero bit - this means we
4005 only need to search for sequences of one bits. */
4009 /* Find the first set bit and set tmp to val with the first sequence of one
4010 bits removed. Return success if there is a single sequence of ones. */
4017 /* Find the next set bit and compute the difference in bit position. */
4022 /* Check the bit position difference is a power of 2, and that the first
4023 sequence of one bits fits within 'bits' bits. */
4027 /* Check the sequence of one bits is repeated 64/bits times. */
4029 }
4031 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
4032 Assumed precondition: VAL_IN Is not zero. */
4034 unsigned HOST_WIDE_INT
4036 {
4043 }
4045 /* Create constant where bits outside of lowest bit set to highest bit set
4046 are set to 1. */
4048 unsigned HOST_WIDE_INT
4050 {
4052 }
4054 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
4056 bool
4058 {
4068 }
4070 /* Return true if val is an immediate that can be loaded into a
4071 register in a single instruction. */
4072 bool
4074 {
4078 }
4080 static bool
4082 {
4090 {
4094 else
4095 /* Avoid generating a 64-bit relocation in ILP32; leave
4096 to aarch64_expand_mov_immediate to handle it properly. */
4098 }
4101 }
4103 /* Implement TARGET_CASE_VALUES_THRESHOLD.
4104 The expansion for a table switch is quite expensive due to the number
4105 of instructions, the table lookup and hard to predict indirect jump.
4106 When optimizing for speed, and -O3 enabled, use the per-core tuning if
4107 set, otherwise use tables for > 16 cases as a tradeoff between size and
4108 performance. When optimizing for size, use the default setting. */
4110 static unsigned int
4112 {
4113 /* Use the specified limit for the number of cases before using jump
4114 tables at higher optimization levels. */
4118 else
4120 }
4122 /* Return true if register REGNO is a valid index register.
4123 STRICT_P is true if REG_OK_STRICT is in effect. */
4125 bool
4127 {
4129 {
4137 }
4139 }
4141 /* Return true if register REGNO is a valid base register for mode MODE.
4142 STRICT_P is true if REG_OK_STRICT is in effect. */
4144 bool
4146 {
4148 {
4156 }
4158 /* The fake registers will be eliminated to either the stack or
4159 hard frame pointer, both of which are usually valid base registers.
4160 Reload deals with the cases where the eliminated form isn't valid. */
4165 }
4167 /* Return true if X is a valid base register for mode MODE.
4168 STRICT_P is true if REG_OK_STRICT is in effect. */
4170 static bool
4172 {
4177 }
4179 /* Return true if address offset is a valid index. If it is, fill in INFO
4180 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
4182 static bool
4185 {
4187 rtx index;
4190 /* (reg:P) */
4193 {
4197 }
4198 /* (sign_extend:DI (reg:SI)) */
4203 {
4208 }
4209 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
4216 {
4221 }
4222 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
4229 {
4234 }
4235 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
4242 {
4250 }
4251 /* (and:DI (mult:DI (reg:DI) (const_int scale))
4252 (const_int 0xffffffff<<shift)) */
4259 {
4265 }
4266 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
4273 {
4281 }
4282 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
4283 (const_int 0xffffffff<<shift)) */
4290 {
4296 }
4297 /* (mult:P (reg:P) (const_int scale)) */
4302 {
4306 }
4307 /* (ashift:P (reg:P) (const_int shift)) */
4312 {
4316 }
4317 else
4328 {
4333 }
4336 }
4338 /* Return true if MODE is one of the modes for which we
4339 support LDP/STP operations. */
4341 static bool
4343 {
4348 }
4350 /* Return true if REGNO is a virtual pointer register, or an eliminable
4351 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
4352 include stack_pointer or hard_frame_pointer. */
4353 static bool
4355 {
4360 }
4362 /* Return true if X is a valid address for machine mode MODE. If it is,
4363 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
4364 effect. OUTER_CODE is PARALLEL for a load/store pair. */
4366 static bool
4370 {
4374 /* On BE, we use load/store pair for all large int mode load/stores.
4375 TI/TFmode may also use a load/store pair. */
4379 || (BYTES_BIG_ENDIAN
4383 !load_store_pair_p
4387 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4388 REG addressing. */
4394 {
4410 {
4416 }
4421 {
4428 /* TImode and TFmode values are allowed in both pairs of X
4429 registers and individual Q registers. The available
4430 address modes are:
4431 X,X: 7-bit signed scaled offset
4432 Q: 9-bit signed offset
4433 We conservatively require an offset representable in either mode.
4434 When performing the check for pairs of X registers i.e. LDP/STP
4435 pass down DImode since that is the natural size of the LDP/STP
4436 instruction memory accesses. */
4442 /* A 7bit offset check because OImode will emit a ldp/stp
4443 instruction (only big endian will get here).
4444 For ldp/stp instructions, the offset is scaled for the size of a
4445 single element of the pair. */
4449 /* Three 9/12 bit offsets checks because CImode will emit three
4450 ldr/str instructions (only big endian will get here). */
4457 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4458 instructions (only big endian will get here). */
4467 else
4470 }
4473 {
4474 /* Look for base + (scaled/extended) index register. */
4477 {
4480 }
4483 {
4486 }
4487 }
4508 {
4509 HOST_WIDE_INT offset;
4513 /* TImode and TFmode values are allowed in both pairs of X
4514 registers and individual Q registers. The available
4515 address modes are:
4516 X,X: 7-bit signed scaled offset
4517 Q: 9-bit signed offset
4518 We conservatively require an offset representable in either mode.
4519 */
4527 else
4529 }
4535 /* load literal: pc-relative constant pool entry. Only supported
4536 for SI mode or larger. */
4540 {
4548 }
4557 {
4562 {
4563 /* The symbol and offset must be aligned to the access size. */
4570 {
4574 }
4580 else
4589 }
4590 }
4595 }
4596 }
4598 bool
4600 {
4601 rtx offset;
4605 }
4607 /* Classify the base of symbolic expression X. */
4609 enum aarch64_symbol_type
4611 {
4612 rtx offset;
4616 }
4619 /* Return TRUE if X is a legitimate address for accessing memory in
4620 mode MODE. */
4621 static bool
4623 {
4627 }
4629 /* Return TRUE if X is a legitimate address for accessing memory in
4630 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4631 pair operation. */
4632 bool
4635 {
4639 }
4641 /* Split an out-of-range address displacement into a base and offset.
4642 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4643 to increase opportunities for sharing the base address of different sizes.
4644 For unaligned accesses and TI/TF mode use the signed 9-bit range. */
4645 static bool
4647 {
4658 }
4660 /* Return TRUE if rtx X is immediate constant 0.0 */
4661 bool
4663 {
4670 }
4672 /* Return the fixed registers used for condition codes. */
4674 static bool
4676 {
4680 }
4682 /* Emit call insn with PAT and do aarch64-specific handling. */
4684 void
4686 {
4692 }
4694 machine_mode
4696 {
4697 /* All floating point compares return CCFP if it is an equality
4698 comparison, and CCFPE otherwise. */
4700 {
4702 {
4723 }
4724 }
4726 /* Equality comparisons of short modes against zero can be performed
4727 using the TST instruction with the appropriate bitmask. */
4733 /* Similarly, comparisons of zero_extends from shorter modes can
4734 be performed using an ANDS with an immediate mask. */
4750 /* A compare with a shifted operand. Because of canonicalization,
4751 the comparison will have to be swapped when we emit the assembly
4752 code. */
4760 /* Similarly for a negated operand, but we can only do this for
4761 equalities. */
4768 /* A test for unsigned overflow. */
4775 /* For everything else, return CCmode. */
4777 }
4779 static int
4782 int
4784 {
4791 }
4793 static int
4795 {
4797 {
4801 {
4815 }
4820 {
4832 }
4837 {
4849 }
4854 {
4860 }
4865 {
4869 }
4874 {
4878 }
4883 }
4886 }
4888 bool
4890 HOST_WIDE_INT minval,
4891 HOST_WIDE_INT maxval)
4892 {
4893 HOST_WIDE_INT firstval;
4910 }
4912 bool
4914 {
4916 }
4919 /* N Z C V. */
4920 #define AARCH64_CC_V 1
4921 #define AARCH64_CC_C (1 << 1)
4922 #define AARCH64_CC_Z (1 << 2)
4923 #define AARCH64_CC_N (1 << 3)
4925 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
4927 {
4944 };
4946 static void
4948 {
4950 {
4951 /* An integer or symbol address without a preceding # sign. */
4954 {
4966 {
4969 }
4970 /* Fall through. */
4974 }
4978 /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
4979 {
4984 {
4987 }
4990 {
5003 }
5004 }
5008 {
5011 /* Print N such that 2^N == X. */
5013 {
5016 }
5019 }
5023 /* Print the number of non-zero bits in X (a const_int). */
5025 {
5028 }
5034 /* Print the higher numbered register of a pair (TImode) of regs. */
5036 {
5039 }
5046 {
5048 /* Print a condition (eq, ne, etc) or its inverse. */
5050 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
5052 {
5056 }
5059 {
5062 }
5069 }
5077 /* Print a scalar FP/SIMD register name. */
5079 {
5080 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5082 }
5090 /* Print the first FP/SIMD register name in a list. */
5092 {
5093 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5095 }
5100 /* Print a scalar FP/SIMD register name + 1. */
5102 {
5103 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5105 }
5110 /* Print bottom 16 bits of integer constant in hex. */
5112 {
5115 }
5121 /* Print a general register name or the zero register (32-bit or
5122 64-bit). */
5125 {
5128 }
5131 {
5134 }
5137 {
5140 }
5142 /* Fall through */
5145 /* Print a normal operand, if it's a general register, then we
5146 assume DImode. */
5148 {
5151 }
5154 {
5175 {
5178 HOST_WIDE_INT_MIN,
5179 HOST_WIDE_INT_MAX));
5181 }
5183 {
5185 }
5186 else
5191 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
5192 be getting CONST_DOUBLEs holding integers. */
5195 {
5198 }
5200 {
5201 #define buf_size 20
5209 #undef buf_size
5210 }
5216 }
5224 {
5251 }
5257 {
5292 }
5299 {
5305 }
5310 {
5311 HOST_WIDE_INT cond_code;
5312 /* Print nzcv. */
5315 {
5318 }
5323 }
5329 }
5330 }
5332 static void
5334 {
5339 {
5343 else
5352 else
5361 else
5370 else
5377 {
5404 }
5415 }
5418 }
5420 bool
5422 {
5429 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5430 referencing instruction, but they are constant offsets, not
5431 symbols. */
5437 {
5439 {
5445 }
5448 }
5451 }
5453 /* Implement REGNO_REG_CLASS. */
5455 enum reg_class
5457 {
5472 }
5474 static rtx
5476 {
5477 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5478 where mask is selected by alignment and size of the offset.
5479 We try to pick as large a range for the offset as possible to
5480 maximize the chance of a CSE. However, for aligned addresses
5481 we limit the range to 4k so that structures with different sized
5482 elements are likely to use the same base. We need to be careful
5483 not to split a CONST for some forms of address expression, otherwise
5484 it will generate sub-optimal code. */
5487 {
5493 {
5497 /* Force any scaling into a temp for CSE. */
5501 /* Let the pointer register be in op0. */
5505 /* If the pointer is virtual or frame related, then we know that
5506 virtual register instantiation or register elimination is going
5507 to apply a second constant. We want the two constants folded
5508 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5510 {
5514 }
5516 /* Otherwise, in order to encourage CSE (and thence loop strength
5517 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5521 }
5523 /* Does it look like we'll need a 16-byte load/store-pair operation? */
5524 HOST_WIDE_INT base_offset;
5527 /* For offsets aren't a multiple of the access size, the limit is
5528 -256...255. */
5530 {
5533 /* BLKmode typically uses LDP of X-registers. */
5536 }
5537 /* Small negative offsets are supported. */
5542 /* Use 12-bit offset by access size. */
5543 else
5547 {
5551 }
5552 }
5555 }
5557 /* Return the reload icode required for a constant pool in mode. */
5558 static enum insn_code
5560 {
5562 {
5598 }
5601 }
5602 static reg_class_t
5604 reg_class_t rclass,
5605 machine_mode mode,
5607 {
5609 /* If we have to disable direct literal pool loads and stores because the
5610 function is too big, then we need a scratch register. */
5615 {
5618 }
5620 /* Without the TARGET_SIMD instructions we cannot move a Q register
5621 to a Q register directly. We need a scratch. */
5625 {
5631 }
5633 /* A TFmode or TImode memory access should be handled via an FP_REGS
5634 because AArch64 has richer addressing modes for LDR/STR instructions
5635 than LDP/STP instructions. */
5644 }
5646 static bool
5648 {
5649 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5650 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5653 {
5665 }
5666 else
5667 {
5668 /* If we decided that we didn't need a leaf frame pointer but then used
5669 LR in the function, then we'll want a frame pointer after all, so
5670 prevent this elimination to ensure a frame pointer is used. */
5672 && flag_omit_leaf_frame_pointer
5675 }
5678 }
5680 HOST_WIDE_INT
5682 {
5686 {
5693 }
5696 {
5700 }
5703 }
5705 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5706 previous frame. */
5708 rtx
5710 {
5714 }
5717 static void
5719 {
5721 {
5724 }
5725 else
5726 {
5729 }
5734 }
5736 static void
5738 {
5742 /* Don't need to copy the trailing D-words, we fill those in below. */
5754 /* XXX We should really define a "clear_cache" pattern and use
5755 gen_clear_cache(). */
5760 ptr_mode);
5761 }
5763 static unsigned char
5765 {
5767 {
5774 return
5786 }
5788 }
5790 static reg_class_t
5792 {
5797 {
5803 }
5805 /* If it's an integer immediate that MOVI can't handle, then
5806 FP_REGS is not an option, so we return NO_REGS instead. */
5811 /* Register eliminiation can result in a request for
5812 SP+constant->FP_REGS. We cannot support such operations which
5813 use SP as source and an FP_REG as destination, so reject out
5814 right now. */
5816 {
5819 /* Look through a possible SUBREG introduced by ILP32. */
5825 POINTER_REGS));
5827 }
5830 }
5832 void
5834 {
5836 }
5838 static void
5840 {
5843 else
5844 {
5846 /* While priority is known to be in range [0, 65535], so 18 bytes
5847 would be enough, the compiler might not know that. To avoid
5848 -Wformat-truncation false positive, use a larger size. */
5855 }
5856 }
5858 static void
5860 {
5863 else
5864 {
5866 /* While priority is known to be in range [0, 65535], so 18 bytes
5867 would be enough, the compiler might not know that. To avoid
5868 -Wformat-truncation false positive, use a larger size. */
5875 }
5876 }
5880 {
5886 {
5887 {
5890 },
5891 {
5894 },
5895 {
5898 },
5899 /* We assume that DImode is only generated when not optimizing and
5900 that we don't really need 64-bit address offsets. That would
5901 imply an object file with 8GB of code in a single function! */
5902 {
5905 }
5906 };
5914 /* Need to implement table size reduction, by chaning the code below. */
5924 }
5927 /* Return size in bits of an arithmetic operand which is shifted/scaled and
5928 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
5929 operator. */
5931 int
5933 {
5935 {
5938 {
5942 }
5943 }
5945 }
5947 /* Constant pools are per function only when PC relative
5948 literal loads are true or we are in the large memory
5949 model. */
5953 {
5956 }
5958 static bool
5960 {
5961 /* Fixme:: In an ideal world this would work similar
5962 to the logic in aarch64_select_rtx_section but this
5963 breaks bootstrap in gcc go. For now we workaround
5964 this by returning false here. */
5966 }
5968 /* Select appropriate section for constants depending
5969 on where we place literal pools. */
5973 rtx x,
5975 {
5980 }
5982 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
5983 void
5985 HOST_WIDE_INT offset)
5986 {
5987 /* When using per-function literal pools, we must ensure that any code
5988 section is aligned to the minimal instruction length, lest we get
5989 errors from the assembler re "unaligned instructions". */
5992 }
5994 /* Costs. */
5996 /* Helper function for rtx cost calculation. Strip a shift expression
5997 from X. Returns the inner operand if successful, or the original
5998 expression on failure. */
5999 static rtx
6001 {
6004 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
6005 we can convert both to ROR during final output. */
6020 }
6022 /* Helper function for rtx cost calculation. Strip an extend
6023 expression from X. Returns the inner operand if successful, or the
6024 original expression on failure. We deal with a number of possible
6025 canonicalization variations here. */
6026 static rtx
6028 {
6031 /* Zero and sign extraction of a widened value. */
6039 /* It can also be represented (for zero-extend) as an AND with an
6040 immediate. */
6049 /* Now handle extended register, as this may also have an optional
6050 left shift by 1..4. */
6064 }
6066 /* Return true iff CODE is a shift supported in combination
6067 with arithmetic instructions. */
6069 static bool
6071 {
6073 }
6075 /* Helper function for rtx cost calculation. Calculate the cost of
6076 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
6077 Return the calculated cost of the expression, recursing manually in to
6078 operands where needed. */
6080 static int
6082 {
6098 /* Integer multiply/fma. */
6100 {
6101 /* The multiply will be canonicalized as a shift, cost it as such. */
6105 {
6109 {
6111 {
6113 /* ARITH + shift-by-register. */
6116 /* ARITH + extended register. We don't have a cost field
6117 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
6119 else
6120 /* ARITH + shift-by-immediate. */
6122 }
6123 else
6124 /* LSL (immediate). */
6127 }
6128 /* Strip extends as we will have costed them in the case above. */
6135 }
6137 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
6138 compound and let the below cases handle it. After all, MNEG is a
6139 special-case alias of MSUB. */
6141 {
6144 }
6146 /* Integer multiplies or FMAs have zero/sign extending variants. */
6151 {
6156 {
6158 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
6160 else
6161 /* MUL/SMULL/UMULL. */
6163 }
6166 }
6168 /* This is either an integer multiply or a MADD. In both cases
6169 we want to recurse and cost the operands. */
6174 {
6176 /* MADD/MSUB. */
6178 else
6179 /* MUL. */
6181 }
6184 }
6185 else
6186 {
6188 {
6189 /* Floating-point FMA/FMUL can also support negations of the
6190 operands, unless the rounding mode is upward or downward in
6191 which case FNMUL is different than FMUL with operand negation. */
6195 {
6200 }
6203 /* FMADD/FNMADD/FNMSUB/FMSUB. */
6205 else
6206 /* FMUL/FNMUL. */
6208 }
6213 }
6214 }
6216 static int
6218 machine_mode mode,
6219 addr_space_t as ATTRIBUTE_UNUSED,
6221 {
6229 {
6231 {
6232 /* This is a CONST or SYMBOL ref which will be split
6233 in a different way depending on the code model in use.
6234 Cost it through the generic infrastructure. */
6236 /* Divide through by the cost of one instruction to
6237 bring it to the same units as the address costs. */
6239 /* The cost is then the cost of preparing the address,
6240 followed by an immediate (possibly 0) offset. */
6242 }
6243 else
6244 {
6245 /* This is most likely a jump table from a case
6246 statement. */
6248 }
6249 }
6252 {
6264 else
6283 }
6287 {
6288 /* For the sake of calculating the cost of the shifted register
6289 component, we can treat same sized modes in the same way. */
6291 {
6304 /* We can't tell, or this is a 128-bit vector. */
6308 }
6309 }
6312 }
6314 /* Return the cost of a branch. If SPEED_P is true then the compiler is
6315 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
6316 to be taken. */
6318 int
6320 {
6321 /* When optimizing for speed, use the cost of unpredictable branches. */
6327 else
6329 }
6331 /* Return true if the RTX X in mode MODE is a zero or sign extract
6332 usable in an ADD or SUB (extended register) instruction. */
6333 static bool
6335 {
6336 /* Catch add with a sign extract.
6337 This is add_<optab><mode>_multp2. */
6340 {
6351 op1))
6352 {
6354 }
6355 }
6356 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6357 No shift. */
6363 }
6365 static bool
6367 {
6369 {
6381 }
6382 }
6384 /* Return true iff X is an rtx that will match an extr instruction
6385 i.e. as described in the *extr<mode>5_insn family of patterns.
6386 OP0 and OP1 will be set to the operands of the shifts involved
6387 on success and will be NULL_RTX otherwise. */
6389 static bool
6391 {
6406 {
6407 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6419 {
6423 }
6424 }
6427 }
6429 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6430 storing it in *COST. Result is true if the total cost of the operation
6431 has now been calculated. */
6432 static bool
6434 {
6435 rtx inner;
6436 rtx comparator;
6440 {
6444 }
6445 else
6446 {
6450 }
6453 {
6454 /* Conditional branch. */
6457 else
6458 {
6460 {
6462 {
6463 /* TBZ/TBNZ/CBZ/CBNZ. */
6465 /* TBZ/TBNZ. */
6468 else
6469 /* CBZ/CBNZ. */
6473 }
6474 }
6476 {
6477 /* TBZ/TBNZ. */
6480 }
6481 }
6482 }
6484 {
6485 /* CCMP. */
6487 {
6488 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6492 {
6499 else
6501 }
6503 }
6505 /* It's a conditional operation based on the status flags,
6506 so it must be some flavor of CSEL. */
6508 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6514 {
6515 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6518 }
6523 }
6525 /* We don't know what this is, cost all operands. */
6527 }
6529 /* Check whether X is a bitfield operation of the form shift + extend that
6530 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6531 operand to which the bitfield operation is applied. Otherwise return
6532 NULL_RTX. */
6534 static rtx
6536 {
6550 {
6568 }
6571 }
6573 /* Return true if the mask and a shift amount from an RTX of the form
6574 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6575 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6577 bool
6579 {
6584 }
6586 /* Calculate the cost of calculating X, storing it in *COST. Result
6587 is true if the total cost of the operation has now been calculated. */
6588 static bool
6591 {
6597 /* By default, assume that everything has equivalent cost to the
6598 cheapest instruction. Any additional costs are applied as a delta
6599 above this default. */
6603 {
6605 /* The cost depends entirely on the operands to SET. */
6611 {
6614 {
6628 }
6637 /* Fall through. */
6639 /* The cost is one per vector-register copied. */
6641 {
6645 }
6646 /* const0_rtx is in general free, but we will use an
6647 instruction to set a register to 0. */
6649 {
6650 /* The cost is 1 per register copied. */
6654 }
6655 else
6656 /* Cost is just the cost of the RHS of the set. */
6662 /* Bit-field insertion. Strip any redundant widening of
6663 the RHS to meet the width of the target. */
6674 {
6675 /* MOV immediate is assumed to always be cheap. */
6677 }
6678 else
6679 {
6680 /* BFM. */
6684 }
6689 /* We can't make sense of this, assume default cost. */
6692 }
6696 /* If an instruction can incorporate a constant within the
6697 instruction, the instruction's expression avoids calling
6698 rtx_cost() on the constant. If rtx_cost() is called on a
6699 constant, then it is usually because the constant must be
6700 moved into a register by one or more instructions.
6702 The exception is constant 0, which can be expressed
6703 as XZR/WZR and is therefore free. The exception to this is
6704 if we have (set (reg) (const0_rtx)) in which case we must cost
6705 the move. However, we can catch that when we cost the SET, so
6706 we don't need to consider that here. */
6709 else
6710 {
6711 /* To an approximation, building any other constant is
6712 proportionally expensive to the number of instructions
6713 required to build that constant. This is true whether we
6714 are compiling for SPEED or otherwise. */
6717 }
6722 {
6723 /* mov[df,sf]_aarch64. */
6725 /* FMOV (scalar immediate). */
6728 {
6729 /* This will be a load from memory. */
6732 else
6734 }
6735 else
6736 /* Otherwise this is +0.0. We get this using MOVI d0, #0
6737 or MOV v0.s[0], wzr - neither of which are modeled by the
6738 cost tables. Just use the default cost. */
6739 {
6740 }
6741 }
6747 {
6748 /* For loads we want the base cost of a load, plus an
6749 approximation for the additional cost of the addressing
6750 mode. */
6764 }
6772 {
6774 {
6775 /* FNEG. */
6777 }
6779 }
6782 {
6785 {
6786 /* CSETM. */
6789 }
6791 /* Cost this as SUB wzr, X. */
6795 }
6798 {
6799 /* Support (neg(fma...)) as a single instruction only if
6800 sign of zeros is unimportant. This matches the decision
6801 making in aarch64.md. */
6803 {
6804 /* FNMADD. */
6807 }
6809 {
6810 /* FNMUL. */
6813 }
6815 /* FNEG. */
6818 }
6825 {
6828 else
6830 }
6840 {
6844 }
6847 {
6848 /* TODO: A write to the CC flags possibly costs extra, this
6849 needs encoding in the cost tables. */
6852 /* ANDS. */
6854 {
6857 }
6860 {
6861 /* ADDS (and CMN alias). */
6864 }
6867 {
6868 /* SUBS. */
6871 }
6876 {
6877 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
6878 Handle it here directly rather than going to cost_logic
6879 since we know the immediate generated for the TST is valid
6880 so we can avoid creating an intermediate rtx for it only
6881 for costing purposes. */
6888 }
6891 {
6892 /* CMN. */
6899 }
6901 /* CMP.
6903 Compare can freely swap the order of operands, and
6904 canonicalization puts the more complex operation first.
6905 But the integer MINUS logic expects the shift/extend
6906 operation in op1. */
6909 {
6912 }
6914 }
6917 {
6918 /* FCMP. */
6923 {
6925 /* FCMP supports constant 0.0 for no extra cost. */
6927 }
6929 }
6932 {
6933 /* Vector compare. */
6938 {
6939 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
6940 cost. */
6942 }
6944 }
6948 {
6952 cost_minus:
6955 /* Detect valid immediates. */
6961 {
6963 /* SUB(S) (immediate). */
6966 }
6968 /* Look for SUB (extended register). */
6970 {
6978 }
6982 /* Cost this as an FMA-alike operation. */
6986 {
6989 speed);
6991 }
6996 {
6998 {
6999 /* Vector SUB. */
7001 }
7003 {
7004 /* SUB(S). */
7006 }
7008 {
7009 /* FSUB. */
7011 }
7012 }
7014 }
7017 {
7018 rtx new_op0;
7023 cost_plus:
7026 {
7027 /* CSINC. */
7031 }
7036 {
7040 /* ADD (immediate). */
7043 }
7047 /* Look for ADD (extended register). */
7049 {
7057 }
7059 /* Strip any extend, leave shifts behind as we will
7060 cost them through mult_cost. */
7065 {
7067 speed);
7069 }
7074 {
7076 {
7077 /* Vector ADD. */
7079 }
7081 {
7082 /* ADD. */
7084 }
7086 {
7087 /* FADD. */
7089 }
7090 }
7092 }
7098 {
7101 else
7103 }
7108 {
7112 {
7115 else
7117 }
7119 }
7122 {
7129 }
7130 /* Fall through. */
7133 cost_logic:
7138 {
7142 }
7150 {
7151 /* This is a UBFM/SBFM. */
7156 }
7159 {
7161 {
7162 /* We have a mask + shift version of a UBFIZ
7163 i.e. the *andim_ashift<mode>_bfiz pattern. */
7167 {
7174 }
7176 {
7177 /* We possibly get the immediate for free, this is not
7178 modelled. */
7184 }
7185 }
7186 else
7187 {
7190 /* Handle ORN, EON, or BIC. */
7196 /* If we had a shift on op0 then this is a logical-shift-
7197 by-register/immediate operation. Otherwise, this is just
7198 a logical operation. */
7200 {
7202 {
7203 /* Shift by immediate. */
7206 else
7208 }
7209 else
7211 }
7213 /* In both cases we want to cost both operands. */
7218 }
7219 }
7227 {
7228 /* Vector NOT. */
7231 }
7233 /* MVN-shifted-reg. */
7235 {
7242 }
7243 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
7244 Handle the second form here taking care that 'a' in the above can
7245 be a shift. */
7247 {
7256 {
7259 else
7261 }
7264 }
7265 /* MVN. */
7274 /* If a value is written in SI mode, then zero extended to DI
7275 mode, the operation will in general be free as a write to
7276 a 'w' register implicitly zeroes the upper bits of an 'x'
7277 register. However, if this is
7279 (set (reg) (zero_extend (reg)))
7281 we must cost the explicit register move. */
7285 {
7288 /* If OP_COST is non-zero, then the cost of the zero extend
7289 is effectively the cost of the inner operation. Otherwise
7290 we have a MOV instruction and we take the cost from the MOV
7291 itself. This is true independently of whether we are
7292 optimizing for space or time. */
7297 }
7299 {
7300 /* All loads can zero extend to any size for free. */
7303 }
7307 {
7312 }
7315 {
7317 {
7318 /* UMOV. */
7320 }
7321 else
7322 {
7323 /* We generate an AND instead of UXTB/UXTH. */
7325 }
7326 }
7331 {
7332 /* LDRSH. */
7334 {
7341 }
7343 }
7347 {
7352 }
7355 {
7358 else
7360 }
7368 {
7370 {
7372 {
7373 /* Vector shift (immediate). */
7375 }
7376 else
7377 {
7378 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
7379 aliases. */
7381 }
7382 }
7384 /* We can incorporate zero/sign extend for free. */
7391 }
7392 else
7393 {
7395 {
7397 {
7398 /* Vector shift (register). */
7400 }
7401 else
7402 {
7403 /* LSLV. */
7405 }
7406 }
7408 }
7418 {
7419 /* ASR (immediate) and friends. */
7421 {
7424 else
7426 }
7430 }
7431 else
7432 {
7434 /* ASR (register) and friends. */
7436 {
7439 else
7441 }
7443 }
7449 {
7450 /* LDR. */
7453 }
7456 {
7457 /* ADRP, followed by ADD. */
7461 }
7464 {
7465 /* ADR. */
7468 }
7471 {
7472 /* One extra load instruction, after accessing the GOT. */
7476 }
7481 /* ADRP/ADD (immediate). */
7488 /* UBFX/SBFX. */
7490 {
7493 else
7495 }
7497 /* We can trust that the immediates used will be correct (there
7498 are no by-register forms), so we need only cost op0. */
7504 /* aarch64_rtx_mult_cost always handles recursion to its
7505 operands. */
7509 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7510 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7511 an unconditional negate. This case should only ever be reached through
7512 the set_smod_pow2_cheap check in expmed.c. */
7516 {
7517 /* We expand to 4 instructions. Reset the baseline. */
7525 }
7527 /* Fall-through. */
7530 {
7542 }
7549 {
7553 /* There is no integer SQRT, so only DIV and UDIV can get
7554 here. */
7556 else
7558 }
7584 {
7587 else
7589 }
7591 /* FMSUB, FNMADD, and FNMSUB are free. */
7598 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7599 and the by-element operand as operand 0. */
7603 /* Catch vector-by-element operations. The by-element operand can
7604 either be (vec_duplicate (vec_select (x))) or just
7605 (vec_select (x)), depending on whether we are multiplying by
7606 a vector or a scalar.
7608 Canonicalization is not very good in these cases, FMA4 will put the
7609 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7620 /* If the remaining parameters are not registers,
7621 get the cost to put them into registers. */
7635 {
7637 {
7638 /*Vector truncate. */
7640 }
7641 else
7643 }
7648 {
7650 {
7651 /*Vector conversion. */
7653 }
7654 else
7656 }
7662 /* Strip the rounding part. They will all be implemented
7663 by the fcvt* family of instructions anyway. */
7665 {
7674 }
7677 {
7680 else
7682 }
7684 /* We can combine fmul by a power of 2 followed by a fcvt into a single
7685 fixed-point fcvt. */
7690 {
7694 }
7701 {
7702 /* ABS (vector). */
7705 }
7707 {
7710 /* FABD, which is analogous to FADD. */
7712 {
7719 }
7720 /* Simple FABS is analogous to FNEG. */
7723 }
7724 else
7725 {
7726 /* Integer ABS will either be split to
7727 two arithmetic instructions, or will be an ABS
7728 (scalar), which we don't model. */
7732 }
7738 {
7741 else
7742 {
7743 /* FMAXNM/FMINNM/FMAX/FMIN.
7744 TODO: This may not be accurate for all implementations, but
7745 we do not model this in the cost tables. */
7747 }
7748 }
7752 /* The floating point round to integer frint* instructions. */
7754 {
7759 }
7762 {
7767 }
7772 /* Decompose <su>muldi3_highpart. */
7774 mode == DImode
7775 /* (lshiftrt:TI */
7778 /* (mult:TI */
7780 /* (ANY_EXTEND:TI (reg:DI))
7781 (ANY_EXTEND:TI (reg:DI))) */
7788 /* (const_int 64) */
7791 {
7792 /* UMULH/SMULH. */
7800 }
7802 /* Fall through. */
7805 }
7813 }
7815 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
7816 calculated for X. This cost is stored in *COST. Returns true
7817 if the total cost of X was calculated. */
7818 static bool
7821 {
7826 {
7831 }
7834 }
7836 static int
7839 {
7845 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
7852 /* Moving between GPR and stack cost is the same as GP2GP. */
7857 /* To/From the stack register, we move via the gprs. */
7863 {
7864 /* 128-bit operations on general registers require 2 instructions. */
7872 /* When AdvSIMD instructions are disabled it is not possible to move
7873 a 128-bit value directly between Q registers. This is handled in
7874 secondary reload. A general register is used as a scratch to move
7875 the upper DI value and the lower DI value is moved directly,
7876 hence the cost is the sum of three moves. */
7881 }
7891 }
7893 static int
7895 reg_class_t rclass ATTRIBUTE_UNUSED,
7897 {
7899 }
7901 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
7902 to optimize 1.0/sqrt. */
7904 static bool
7906 {
7908 && flag_unsafe_math_optimizations
7912 }
7914 /* Function to decide when to use the approximate reciprocal square root
7915 builtin. */
7917 static tree
7919 {
7925 }
7929 /* Select reciprocal square root initial estimate insn depending on machine
7930 mode. */
7932 static rsqrte_type
7934 {
7936 {
7943 }
7944 }
7948 /* Select reciprocal square root series step insn depending on machine mode. */
7950 static rsqrts_type
7952 {
7954 {
7961 }
7962 }
7964 /* Emit instruction sequence to compute either the approximate square root
7965 or its approximate reciprocal, depending on the flag RECP, and return
7966 whether the sequence was emitted or not. */
7968 bool
7970 {
7976 machine_mode mmsk = mode_for_vector
7980 && (flag_mlow_precision_sqrt
7984 && (flag_mrecip_low_precision_sqrt
7989 || flag_trapping_math
7990 || !flag_unsafe_math_optimizations
7997 /* When calculating the approximate square root, compare the argument with
7998 0.0 and create a mask. */
8002 /* Estimate the approximate reciprocal square root. */
8006 /* Iterate over the series twice for SF and thrice for DF. */
8009 /* Optionally iterate over the series once less for faster performance
8010 while sacrificing the accuracy. */
8013 iterations--;
8015 /* Iterate over the series to calculate the approximate reciprocal square
8016 root. */
8019 {
8027 }
8030 {
8031 /* Qualify the approximate reciprocal square root when the argument is
8032 0.0 by squashing the intermediary result to 0.0. */
8038 /* Calculate the approximate square root. */
8040 }
8042 /* Finalize the approximation. */
8046 }
8050 /* Select reciprocal initial estimate insn depending on machine mode. */
8052 static recpe_type
8054 {
8056 {
8063 }
8064 }
8068 /* Select reciprocal series step insn depending on machine mode. */
8070 static recps_type
8072 {
8074 {
8081 }
8082 }
8084 /* Emit the instruction sequence to compute the approximation for the division
8085 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
8087 bool
8089 {
8100 || flag_trapping_math
8101 || !flag_unsafe_math_optimizations
8106 /* Estimate the approximate reciprocal. */
8110 /* Iterate over the series twice for SF and thrice for DF. */
8113 /* Optionally iterate over the series once less for faster performance,
8114 while sacrificing the accuracy. */
8116 iterations--;
8118 /* Iterate over the series to calculate the approximate reciprocal. */
8121 {
8126 }
8129 {
8130 /* As the approximate reciprocal of DEN is already calculated, only
8131 calculate the approximate division when NUM is not 1.0. */
8134 }
8136 /* Finalize the approximation. */
8139 }
8141 /* Return the number of instructions that can be issued per cycle. */
8142 static int
8144 {
8146 }
8148 static int
8150 {
8154 }
8157 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
8158 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
8159 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
8161 static int
8164 {
8166 }
8169 /* Vectorizer cost model target hooks. */
8171 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8172 static int
8174 tree vectype,
8176 {
8185 {
8234 }
8235 }
8237 /* Implement targetm.vectorize.add_stmt_cost. */
8238 static unsigned
8242 {
8247 {
8252 /* Statements in an inner loop relative to the loop being
8253 vectorized are weighted more heavily. The value here is
8254 arbitrary and could potentially be improved with analysis. */
8260 }
8263 }
8267 /* Parse the TO_PARSE string and put the architecture struct that it
8268 selects into RES and the architectural features into ISA_FLAGS.
8269 Return an aarch64_parse_opt_result describing the parse result.
8270 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
8272 static enum aarch64_parse_opt_result
8275 {
8287 else
8294 /* Loop through the list of supported ARCHes to find a match. */
8296 {
8298 {
8302 {
8303 /* TO_PARSE string contains at least one extension. */
8304 enum aarch64_parse_opt_result ext_res
8309 }
8310 /* Extension parsing was successful. Confirm the result
8311 arch and ISA flags. */
8315 }
8316 }
8318 /* ARCH name not found in list. */
8320 }
8322 /* Parse the TO_PARSE string and put the result tuning in RES and the
8323 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
8324 describing the parse result. If there is an error parsing, RES and
8325 ISA_FLAGS are left unchanged. */
8327 static enum aarch64_parse_opt_result
8330 {
8342 else
8349 /* Loop through the list of supported CPUs to find a match. */
8351 {
8353 {
8358 {
8359 /* TO_PARSE string contains at least one extension. */
8360 enum aarch64_parse_opt_result ext_res
8365 }
8366 /* Extension parsing was successfull. Confirm the result
8367 cpu and ISA flags. */
8371 }
8372 }
8374 /* CPU name not found in list. */
8376 }
8378 /* Parse the TO_PARSE string and put the cpu it selects into RES.
8379 Return an aarch64_parse_opt_result describing the parse result.
8380 If the parsing fails the RES does not change. */
8382 static enum aarch64_parse_opt_result
8384 {
8390 /* Loop through the list of supported CPUs to find a match. */
8392 {
8394 {
8397 }
8398 }
8400 /* CPU name not found in list. */
8402 }
8404 /* Parse TOKEN, which has length LENGTH to see if it is an option
8405 described in FLAG. If it is, return the index bit for that fusion type.
8406 If not, error (printing OPTION_NAME) and return zero. */
8408 static unsigned int
8413 {
8415 {
8419 }
8423 }
8425 /* Parse OPTION which is a comma-separated list of flags to enable.
8426 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8427 default state we inherit from the CPU tuning structures. OPTION_NAME
8428 gives the top-level option we are parsing in the -moverride string,
8429 for use in error messages. */
8431 static unsigned int
8436 {
8443 {
8446 token_length,
8447 flags,
8448 option_name);
8449 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8450 in the token stream, reset the supported operations. So:
8452 adrp+add.cmp+branch.none.adrp+add
8454 would have the result of turning on only adrp+add fusion. */
8460 }
8462 /* We ended with a comma, print something. */
8464 {
8467 }
8469 /* We still have one more token to parse. */
8472 token_length,
8473 flags,
8474 option_name);
8480 }
8482 /* Support for overriding instruction fusion. */
8484 static void
8487 {
8489 aarch64_fusible_pairs,
8492 }
8494 /* Support for overriding other tuning flags. */
8496 static void
8499 {
8500 tune->extra_tuning_flags
8502 aarch64_tuning_flags,
8505 }
8507 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8508 we understand. If it is, extract the option string and handoff to
8509 the appropriate function. */
8511 void
8515 {
8521 {
8524 }
8526 /* Get the length of the option name. */
8528 /* Skip the '=' to get to the option string. */
8529 option_part++;
8532 {
8534 {
8537 }
8538 }
8542 }
8544 /* A checking mechanism for the implementation of the tls size. */
8546 static void
8548 {
8553 {
8555 /* Both the default and maximum TLS size allowed under tiny is 1M which
8556 needs two instructions to address, so we clamp the size to 24. */
8561 /* The maximum TLS size allowed under small is 4G. */
8566 /* The maximum TLS size allowed under large is 16E.
8567 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8573 }
8576 }
8578 /* Parse STRING looking for options in the format:
8579 string :: option:string
8580 option :: name=substring
8581 name :: {a-z}
8582 substring :: defined by option. */
8584 static void
8587 {
8598 {
8600 /* Make this substring look like a string. */
8604 }
8606 /* One last option to parse. */
8609 }
8612 static void
8614 {
8615 /* The logic here is that if we are disabling all frame pointer generation
8616 then we do not need to disable leaf frame pointer generation as a
8617 separate operation. But if we are *only* disabling leaf frame pointer
8618 generation then we set flag_omit_frame_pointer to true, but in
8619 aarch64_frame_pointer_required we return false only for leaf functions.
8621 PR 70044: We have to be careful about being called multiple times for the
8622 same function. Once we have decided to set flag_omit_frame_pointer just
8623 so that we can omit leaf frame pointers, we must then not interpret a
8624 second call as meaning that all frame pointer generation should be
8625 omitted. We do this by setting flag_omit_frame_pointer to a special,
8626 non-zero value. */
8635 /* If not optimizing for size, set the default
8636 alignment to what the target wants. */
8638 {
8645 }
8647 /* We default to no pc-relative literal loads. */
8651 /* If -mpc-relative-literal-loads is set on the command line, this
8652 implies that the user asked for PC relative literal loads. */
8656 /* This is PR70113. When building the Linux kernel with
8657 CONFIG_ARM64_ERRATUM_843419, support for relocations
8658 R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
8659 removed from the kernel to avoid loading objects with possibly
8660 offending sequences. Without -mpc-relative-literal-loads we would
8661 generate such relocations, preventing the kernel build from
8662 succeeding. */
8667 /* In the tiny memory model it makes no sense to disallow PC relative
8668 literal pool loads. */
8673 /* When enabling the lower precision Newton series for the square root, also
8674 enable it for the reciprocal square root, since the latter is an
8675 intermediary step for the former. */
8678 }
8680 /* 'Unpack' up the internal tuning structs and update the options
8681 in OPTS. The caller must have set up selected_tune and selected_arch
8682 as all the other target-specific codegen decisions are
8683 derived from them. */
8685 void
8687 {
8690 /* Make a copy of the tuning parameters attached to the core, which
8691 we may later overwrite. */
8699 /* This target defaults to strict volatile bitfields. */
8708 {
8720 }
8722 /* We don't mind passing in global_options_set here as we don't use
8723 the *options_set structs anyway. */
8725 queue_depth,
8729 /* Set the L1 cache line size. */
8737 }
8739 /* Print a hint with a suggestion for a core or architecture name that
8740 most closely resembles what the user passed in STR. ARCH is true if
8741 the user is asking for an architecture name. ARCH is false if the user
8742 is asking for a core name. */
8744 static void
8746 {
8757 }
8759 /* Print a hint with a suggestion for a core name that most closely resembles
8760 what the user passed in STR. */
8764 {
8766 }
8768 /* Print a hint with a suggestion for an architecture name that most closely
8769 resembles what the user passed in STR. */
8773 {
8775 }
8777 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
8778 specified in STR and throw errors if appropriate. Put the results if
8779 they are valid in RES and ISA_FLAGS. Return whether the option is
8780 valid. */
8782 static bool
8785 {
8786 enum aarch64_parse_opt_result parse_res
8793 {
8806 }
8809 }
8811 /* Validate a command-line -march option. Parse the arch and extensions
8812 (if any) specified in STR and throw errors if appropriate. Put the
8813 results, if they are valid, in RES and ISA_FLAGS. Return whether the
8814 option is valid. */
8816 static bool
8819 {
8820 enum aarch64_parse_opt_result parse_res
8827 {
8840 }
8843 }
8845 /* Validate a command-line -mtune option. Parse the cpu
8846 specified in STR and throw errors if appropriate. Put the
8847 result, if it is valid, in RES. Return whether the option is
8848 valid. */
8850 static bool
8852 {
8853 enum aarch64_parse_opt_result parse_res
8860 {
8870 }
8872 }
8874 /* Return the CPU corresponding to the enum CPU.
8875 If it doesn't specify a cpu, return the default. */
8879 {
8883 /* The & 0x3f is to extract the bottom 6 bits that encode the
8884 default cpu as selected by the --with-cpu GCC configure option
8885 in config.gcc.
8886 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
8887 flags mechanism should be reworked to make it more sane. */
8889 }
8891 /* Return the architecture corresponding to the enum ARCH.
8892 If it doesn't specify a valid architecture, return the default. */
8896 {
8903 }
8905 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
8906 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
8907 tuning structs. In particular it must set selected_tune and
8908 aarch64_isa_flags that define the available ISA features and tuning
8909 decisions. It must also set selected_arch as this will be used to
8910 output the .arch asm tags for each function. */
8912 static void
8914 {
8927 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
8928 If either of -march or -mtune is given, they override their
8929 respective component of -mcpu. */
8941 /* If the user did not specify a processor, choose the default
8942 one for them. This will be the CPU set during configuration using
8943 --with-cpu, otherwise it is "generic". */
8945 {
8947 {
8951 }
8952 else
8953 {
8954 /* Get default configure-time CPU. */
8957 }
8961 }
8962 /* If both -mcpu and -march are specified check that they are architecturally
8963 compatible, warn if they're not and prefer the -march ISA flags. */
8965 {
8967 {
8971 }
8976 }
8977 else
8978 {
8979 /* -mcpu but no -march. */
8986 }
8988 /* Set the arch as well as we will need it when outputing
8989 the .arch directive in assembly. */
8991 {
8994 }
8999 #ifndef HAVE_AS_MABI_OPTION
9000 /* The compiler may have been configured with 2.23.* binutils, which does
9001 not have support for ILP32. */
9004 #endif
9009 /* Make sure we properly set up the explicit options. */
9020 /* Save these options as the default ones in case we push and pop them later
9021 while processing functions with potential target attributes. */
9022 target_option_default_node = target_option_current_node
9024 }
9026 /* Implement targetm.override_options_after_change. */
9028 static void
9030 {
9032 }
9036 {
9040 }
9042 void
9044 {
9046 }
9048 /* A checking mechanism for the implementation of the various code models. */
9049 static void
9051 {
9053 {
9055 {
9060 #ifdef HAVE_AS_SMALL_PIC_RELOCS
9062 ? AARCH64_CMODEL_SMALL_PIC
9064 #else
9066 #endif
9074 }
9075 }
9076 else
9078 }
9080 /* Implement TARGET_OPTION_SAVE. */
9082 static void
9084 {
9086 }
9088 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
9089 using the information saved in PTR. */
9091 static void
9093 {
9101 }
9103 /* Implement TARGET_OPTION_PRINT. */
9105 static void
9107 {
9118 }
9122 void
9124 {
9126 }
9128 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9129 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
9130 make sure optab availability predicates are recomputed when necessary. */
9132 void
9134 {
9139 else
9141 }
9143 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
9144 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
9145 of the function, if such exists. This function may be called multiple
9146 times on a single function so use aarch64_previous_fndecl to avoid
9147 setting up identical state. */
9149 static void
9151 {
9155 tree old_tree = (aarch64_previous_fndecl
9161 /* If current function has no attributes but the previous one did,
9162 use the default node. */
9166 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
9167 the default have been handled by aarch64_save_restore_target_globals from
9168 aarch64_pragma_target_parse. */
9174 /* First set the target options. */
9178 }
9180 /* Enum describing the various ways we can handle attributes.
9181 In many cases we can reuse the generic option handling machinery. */
9183 enum aarch64_attr_opt_type
9184 {
9188 aarch64_attr_custom /* Attribute requires a custom handling function. */
9189 };
9191 /* All the information needed to handle a target attribute.
9192 NAME is the name of the attribute.
9193 ATTR_TYPE specifies the type of behavior of the attribute as described
9194 in the definition of enum aarch64_attr_opt_type.
9195 ALLOW_NEG is true if the attribute supports a "no-" form.
9196 HANDLER is the function that takes the attribute string and whether
9197 it is a pragma or attribute and handles the option. It is needed only
9198 when the ATTR_TYPE is aarch64_attr_custom.
9199 OPT_NUM is the enum specifying the option that the attribute modifies.
9200 This is needed for attributes that mirror the behavior of a command-line
9201 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
9202 aarch64_attr_enum. */
9204 struct aarch64_attribute_info
9205 {
9211 };
9213 /* Handle the ARCH_STR argument to the arch= target attribute.
9214 PRAGMA_OR_ATTR is used in potential error messages. */
9216 static bool
9218 {
9220 enum aarch64_parse_opt_result parse_res
9224 {
9229 }
9232 {
9246 }
9249 }
9251 /* Handle the argument CPU_STR to the cpu= target attribute.
9252 PRAGMA_OR_ATTR is used in potential error messages. */
9254 static bool
9256 {
9258 enum aarch64_parse_opt_result parse_res
9262 {
9270 }
9273 {
9287 }
9290 }
9292 /* Handle the argument STR to the tune= target attribute.
9293 PRAGMA_OR_ATTR is used in potential error messages. */
9295 static bool
9297 {
9299 enum aarch64_parse_opt_result parse_res
9303 {
9308 }
9311 {
9318 }
9321 }
9323 /* Parse an architecture extensions target attribute string specified in STR.
9324 For example "+fp+nosimd". Show any errors if needed. Return TRUE
9325 if successful. Update aarch64_isa_flags to reflect the ISA features
9326 modified.
9327 PRAGMA_OR_ATTR is used in potential error messages. */
9329 static bool
9331 {
9335 /* We allow "+nothing" in the beginning to clear out all architectural
9336 features if the user wants to handpick specific features. */
9338 {
9341 }
9346 {
9349 }
9352 {
9365 }
9368 }
9370 /* The target attributes that we support. On top of these we also support just
9371 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
9372 handled explicitly in aarch64_process_one_target_attr. */
9375 {
9377 OPT_mgeneral_regs_only },
9379 OPT_mfix_cortex_a53_835769 },
9381 OPT_mfix_cortex_a53_843419 },
9385 OPT_momit_leaf_frame_pointer },
9388 OPT_march_ },
9391 OPT_mtune_ },
9393 OPT_msign_return_address_ },
9395 };
9397 /* Parse ARG_STR which contains the definition of one target attribute.
9398 Show appropriate errors if any or return true if the attribute is valid.
9399 PRAGMA_OR_ATTR holds the string to use in error messages about whether
9400 we're processing a target attribute or pragma. */
9402 static bool
9404 {
9410 {
9413 }
9418 /* Skip leading whitespace. */
9420 str_to_check++;
9422 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9423 It is easier to detect and handle it explicitly here rather than going
9424 through the machinery for the rest of the target attributes in this
9425 function. */
9430 {
9433 }
9436 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9437 and point ARG to "foo". */
9439 {
9441 arg++;
9442 }
9446 {
9447 /* If the names don't match up, or the user has given an argument
9448 to an attribute that doesn't accept one, or didn't give an argument
9449 to an attribute that expects one, fail to match. */
9458 {
9462 }
9464 /* If the name matches but the attribute does not allow "no-" versions
9465 then we can't match. */
9467 {
9471 }
9474 {
9475 /* Has a custom handler registered.
9476 For example, cpu=, arch=, tune=. */
9483 /* Either set or unset a boolean option. */
9485 {
9493 }
9494 /* Set or unset a bit in the target_flags. aarch64_handle_option
9495 should know what mask to apply given the option number. */
9497 {
9499 /* We only need to specify the option number.
9500 aarch64_handle_option will know which mask to apply. */
9506 }
9507 /* Use the option setting machinery to set an option to an enum. */
9509 {
9516 {
9519 global_dc);
9520 }
9521 else
9522 {
9525 }
9527 }
9530 }
9531 }
9533 /* If we reached here we either have found an attribute and validated
9534 it or didn't match any. If we matched an attribute but its arguments
9535 were malformed we will have returned false already. */
9537 }
9539 /* Count how many times the character C appears in
9540 NULL-terminated string STR. */
9542 static unsigned int
9544 {
9547 {
9549 res++;
9551 str++;
9552 }
9555 }
9557 /* Parse the tree in ARGS that contains the target attribute information
9558 and update the global target options space. PRAGMA_OR_ATTR is a string
9559 to be used in error messages, specifying whether this is processing
9560 a target attribute or a target pragma. */
9562 bool
9564 {
9566 {
9567 do
9568 {
9571 {
9574 }
9579 }
9582 {
9585 }
9592 {
9595 }
9597 /* Used to catch empty spaces between commas i.e.
9598 attribute ((target ("attr1,,attr2"))). */
9601 /* Handle multiple target attributes separated by ','. */
9606 {
9607 num_attrs++;
9609 {
9612 }
9615 }
9618 {
9622 }
9625 }
9627 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9628 process attribute ((target ("..."))). */
9630 static bool
9632 {
9635 tree old_optimize;
9639 /* If what we're processing is the current pragma string then the
9640 target option node is already stored in target_option_current_node
9641 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
9642 having to re-parse the string. This is especially useful to keep
9643 arm_neon.h compile times down since that header contains a lot
9644 of intrinsics enclosed in pragmas. */
9646 {
9649 }
9655 /* If the function changed the optimization levels as well as setting
9656 target options, start with the optimizations specified. */
9661 /* Save the current target options to restore at the end. */
9664 /* If fndecl already has some target attributes applied to it, unpack
9665 them so that we add this attribute on top of them, rather than
9666 overwriting them. */
9668 {
9674 }
9675 else
9682 /* Set up any additional state. */
9684 {
9686 /* Initialize SIMD builtins if we haven't already.
9687 Set current_target_pragma to NULL for the duration so that
9688 the builtin initialization code doesn't try to tag the functions
9689 being built with the attributes specified by any current pragma, thus
9690 going into an infinite recursion. */
9692 {
9697 }
9699 }
9700 else
9706 {
9711 }
9719 }
9721 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
9722 tri-bool options (yes, no, don't care) and the default value is
9723 DEF, determine whether to reject inlining. */
9725 static bool
9728 {
9729 /* If the callee doesn't care, always allow inlining. */
9733 /* If the caller doesn't care, always allow inlining. */
9737 /* Otherwise, allow inlining if either the callee and caller values
9738 agree, or if the callee is using the default value. */
9740 }
9742 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
9743 to inline CALLEE into CALLER based on target-specific info.
9744 Make sure that the caller and callee have compatible architectural
9745 features. Then go through the other possible target attributes
9746 and see if they can block inlining. Try not to reject always_inline
9747 callees unless they are incompatible architecturally. */
9749 static bool
9751 {
9755 /* If callee has no option attributes, then it is ok to inline. */
9766 /* Callee's ISA flags should be a subset of the caller's. */
9771 /* Allow non-strict aligned functions inlining into strict
9772 aligned ones. */
9782 /* If the architectural features match up and the callee is always_inline
9783 then the other attributes don't matter. */
9795 /* Honour explicit requests to workaround errata. */
9808 /* If the user explicitly specified -momit-leaf-frame-pointer for the
9809 caller and calle and they don't match up, reject inlining. */
9816 /* If the callee has specific tuning overrides, respect them. */
9821 /* If the user specified tuning override strings for the
9822 caller and callee and they don't match up, reject inlining.
9823 We just do a string compare here, we don't analyze the meaning
9824 of the string, as it would be too costly for little gain. */
9832 }
9834 /* Return true if SYMBOL_REF X binds locally. */
9836 static bool
9838 {
9842 }
9844 /* Return true if SYMBOL_REF X is thread local */
9845 static bool
9847 {
9855 }
9857 /* Classify a TLS symbol into one of the TLS kinds. */
9858 enum aarch64_symbol_type
9860 {
9864 {
9871 {
9877 }
9888 else
9897 }
9898 }
9900 /* Return the method that should be used to access SYMBOL_REF or
9901 LABEL_REF X. */
9903 enum aarch64_symbol_type
9905 {
9907 {
9909 {
9924 }
9925 }
9928 {
9933 {
9935 /* When we retrieve symbol + offset address, we have to make sure
9936 the offset does not cause overflow of the final address. But
9937 we have no way of knowing the address of symbol at compile time
9938 so we can't accurately say if the distance between the PC and
9939 symbol + offset is outside the addressible range of +/-1M in the
9940 TINY code model. So we rely on images not being greater than
9941 1M and cap the offset at 1M and anything beyond 1M will have to
9942 be loaded using an alternative mechanism. Furthermore if the
9943 symbol is a weak reference to something that isn't known to
9944 resolve to a symbol in this module, then force to memory. */
9952 /* Same reasoning as the tiny code model, but the offset cap here is
9953 4G. */
9974 /* This is alright even in PIC code as the constant
9975 pool reference is always PC relative and within
9976 the same translation unit. */
9979 else
9984 }
9985 }
9987 /* By default push everything into the constant pool. */
9989 }
9991 bool
9993 {
9995 }
9997 bool
9999 {
10007 }
10009 /* Return true if X holds either a quarter-precision or
10010 floating-point +0.0 constant. */
10011 static bool
10013 {
10020 /* We only handle moving 0.0 to a TFmode register. */
10025 }
10027 static bool
10029 {
10030 /* Do not allow vector struct mode constants. We could support
10031 0 and -1 easily, but they need support in aarch64-simd.md. */
10035 /* This could probably go away because
10036 we now decompose CONST_INTs according to expand_mov_immediate. */
10047 }
10049 rtx
10051 {
10057 /* Can return in any reg. */
10060 }
10062 /* On AAPCS systems, this is the "struct __va_list". */
10065 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
10066 Return the type to use as __builtin_va_list.
10068 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
10070 struct __va_list
10071 {
10072 void *__stack;
10073 void *__gr_top;
10074 void *__vr_top;
10075 int __gr_offs;
10076 int __vr_offs;
10077 }; */
10079 static tree
10081 {
10082 tree va_list_name;
10085 /* Create the type. */
10087 /* Give it the required name. */
10089 TYPE_DECL,
10091 va_list_type);
10096 /* Create the fields. */
10099 ptr_type_node);
10102 ptr_type_node);
10105 ptr_type_node);
10108 integer_type_node);
10111 integer_type_node);
10113 /* Tell tree-stdarg pass about our internal offset fields.
10114 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
10115 purpose to identify whether the code is updating va_list internal
10116 offset fields through irregular way. */
10138 /* Compute its layout. */
10142 }
10144 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
10145 static void
10147 {
10151 tree t;
10165 {
10168 }
10177 NULL_TREE);
10179 NULL_TREE);
10181 NULL_TREE);
10183 NULL_TREE);
10185 NULL_TREE);
10187 /* Emit code to initialize STACK, which points to the next varargs stack
10188 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
10189 by named arguments. STACK is 8-byte aligned. */
10196 /* Emit code to initialize GRTOP, the top of the GR save area.
10197 virtual_incoming_args_rtx should have been 16 byte aligned. */
10202 /* Emit code to initialize VRTOP, the top of the VR save area.
10203 This address is gr_save_area_bytes below GRTOP, rounded
10204 down to the next 16-byte boundary. */
10214 /* Emit code to initialize GROFF, the offset from GRTOP of the
10215 next GPR argument. */
10220 /* Likewise emit code to initialize VROFF, the offset from FTOP
10221 of the next VR argument. */
10225 }
10227 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
10229 static tree
10232 {
10233 tree addr;
10239 machine_mode mode;
10261 struct aarch64_fn_arg_alignment aa
10268 type,
10272 {
10273 /* TYPE passed in fp/simd registers. */
10285 {
10288 }
10291 {
10293 }
10294 }
10295 else
10296 {
10297 /* TYPE passed in general registers. */
10310 {
10312 }
10313 }
10315 /* Get a local temporary for the field value. */
10318 /* Emit code to branch if off >= 0. */
10324 {
10325 /* Emit: offs = (offs + 15) & -16. */
10331 }
10332 else
10335 /* Update ap.__[g|v]r_offs */
10340 /* String up. */
10344 /* [cond2] if (ap.__[g|v]r_offs > 0) */
10349 /* String up: make sure the assignment happens before the use. */
10353 /* Prepare the trees handling the argument that is passed on the stack;
10354 the top level node will store in ON_STACK. */
10357 {
10358 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
10366 }
10367 else
10369 /* Advance ap.__stack */
10377 /* String up roundup and advance. */
10380 /* String up with arg */
10382 /* Big-endianness related address adjustment. */
10385 {
10389 }
10394 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10404 {
10405 /* type ha; // treat as "struct {ftype field[n];}"
10406 ... [computing offs]
10407 for (i = 0; i <nregs; ++i, offs += 16)
10408 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10409 return ha; */
10413 /* Declare a local variable. */
10417 /* Establish the base type. */
10419 {
10438 {
10442 }
10446 }
10448 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10456 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10458 {
10468 }
10472 }
10482 }
10484 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10486 static void
10490 {
10492 CUMULATIVE_ARGS local_cum;
10496 /* The caller has advanced CUM up to, but not beyond, the last named
10497 argument. Advance a local copy of CUM past the last "real" named
10498 argument, to find out how many registers are left over. */
10502 /* Found out how many registers we need to save.
10503 Honor tree-stdvar analysis results. */
10512 {
10515 }
10518 {
10520 {
10523 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10531 }
10533 {
10534 /* We can't use move_block_from_reg, because it will use
10535 the wrong mode, storing D regs only. */
10539 /* Set OFF to the offset from virtual_incoming_args_rtx of
10540 the first vector register. The VR save area lies below
10541 the GR one, and is aligned to 16 bytes. */
10548 {
10556 }
10557 }
10558 }
10560 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10561 any complication of having crtl->args.pretend_args_size changed. */
10566 }
10568 static void
10570 {
10573 {
10575 {
10578 }
10579 }
10580 }
10582 /* Walk down the type tree of TYPE counting consecutive base elements.
10583 If *MODEP is VOIDmode, then set it to the first valid floating point
10584 type. If a non-floating point type is found, or if a floating point
10585 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10586 otherwise return the count in the sub-tree. */
10587 static int
10589 {
10590 machine_mode mode;
10591 HOST_WIDE_INT size;
10594 {
10624 /* Use V2SImode and V4SImode as representatives of all 64-bit
10625 and 128-bit vector types. */
10628 {
10637 }
10642 /* Vector modes are considered to be opaque: two vectors are
10643 equivalent for the purposes of being homogeneous aggregates
10644 if they are the same size. */
10651 {
10655 /* Can't handle incomplete types nor sizes that are not
10656 fixed. */
10663 || !index
10674 /* There must be no padding. */
10679 }
10682 {
10685 tree field;
10687 /* Can't handle incomplete types nor sizes that are not
10688 fixed. */
10694 {
10702 }
10704 /* There must be no padding. */
10709 }
10713 {
10714 /* These aren't very interesting except in a degenerate case. */
10717 tree field;
10719 /* Can't handle incomplete types nor sizes that are not
10720 fixed. */
10726 {
10734 }
10736 /* There must be no padding. */
10741 }
10745 }
10748 }
10750 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
10751 type as described in AAPCS64 \S 4.1.2.
10753 See the comment above aarch64_composite_type_p for the notes on MODE. */
10755 static bool
10757 machine_mode mode)
10758 {
10768 }
10770 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
10771 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
10772 array types. The C99 floating-point complex types are also considered
10773 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
10774 types, which are GCC extensions and out of the scope of AAPCS64, are
10775 treated as composite types here as well.
10777 Note that MODE itself is not sufficient in determining whether a type
10778 is such a composite type or not. This is because
10779 stor-layout.c:compute_record_mode may have already changed the MODE
10780 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
10781 structure with only one field may have its MODE set to the mode of the
10782 field. Also an integer mode whose size matches the size of the
10783 RECORD_TYPE type may be used to substitute the original mode
10784 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
10785 solely relied on. */
10787 static bool
10789 machine_mode mode)
10790 {
10803 }
10805 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
10806 shall be passed or returned in simd/fp register(s) (providing these
10807 parameter passing registers are available).
10809 Upon successful return, *COUNT returns the number of needed registers,
10810 *BASE_MODE returns the mode of the individual register and when IS_HAF
10811 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
10812 floating-point aggregate or a homogeneous short-vector aggregate. */
10814 static bool
10816 const_tree type,
10820 {
10828 {
10831 }
10833 {
10837 }
10839 {
10843 {
10846 }
10847 else
10849 }
10850 else
10855 }
10857 /* Implement TARGET_STRUCT_VALUE_RTX. */
10859 static rtx
10862 {
10864 }
10866 /* Implements target hook vector_mode_supported_p. */
10867 static bool
10869 {
10881 }
10883 /* Return appropriate SIMD container
10884 for MODE within a vector of WIDTH bits. */
10885 static machine_mode
10887 {
10890 {
10893 {
10910 }
10911 else
10913 {
10926 }
10927 }
10929 }
10931 /* Return 128-bit container as the preferred SIMD mode for MODE. */
10932 static machine_mode
10934 {
10936 }
10938 /* Return the bitmask of possible vector sizes for the vectorizer
10939 to iterate over. */
10940 static unsigned int
10942 {
10944 }
10946 /* Implement TARGET_MANGLE_TYPE. */
10950 {
10951 /* The AArch64 ABI documents say that "__va_list" has to be
10952 managled as if it is in the "std" namespace. */
10956 /* Half-precision float. */
10960 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
10961 builtin types. */
10965 /* Use the default mangling. */
10967 }
10969 /* Find the first rtx_insn before insn that will generate an assembly
10970 instruction. */
10974 {
10978 do
10979 {
10981 }
10985 }
10987 static bool
10989 {
10991 /* A number of these may be AArch32 only. */
10996 };
10999 {
11002 }
11005 }
11007 /* Check if there is a register dependency between a load and the insn
11008 for which we hold recog_data. */
11010 static bool
11012 {
11013 rtx load_reg;
11023 {
11029 }
11031 }
11034 /* When working around the Cortex-A53 erratum 835769,
11035 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
11036 instruction and has a preceding memory instruction such that a NOP
11037 should be inserted between them. */
11039 bool
11041 {
11044 rtx body;
11057 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
11058 Restore recog state to INSN to avoid state corruption. */
11066 /* If the previous insn is a memory op and there is no dependency between
11067 it and the DImode madd, emit a NOP between them. If body is NULL then we
11068 have a complex memory operation, probably a load/store pair.
11069 Be conservative for now and emit a NOP. */
11076 }
11079 /* Implement FINAL_PRESCAN_INSN. */
11081 void
11083 {
11086 }
11089 /* Return the equivalent letter for size. */
11090 static char
11092 {
11094 {
11100 }
11101 }
11103 /* Return true iff x is a uniform vector of floating-point
11104 constants, and the constant can be represented in
11105 quarter-precision form. Note, as aarch64_float_const_representable
11106 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
11107 static bool
11109 {
11110 rtx elt;
11114 }
11116 /* Return true for valid and false for invalid. */
11117 bool
11120 {
11121 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
11122 matches = 1; \
11123 for (i = 0; i < idx; i += (STRIDE)) \
11124 if (!(TEST)) \
11125 matches = 0; \
11126 if (matches) \
11127 { \
11128 immtype = (CLASS); \
11129 elsize = (ELSIZE); \
11130 eshift = (SHIFT); \
11131 emvn = (NEG); \
11132 break; \
11133 }
11143 {
11149 {
11154 }
11157 }
11159 /* Splat vector constant out into a byte vector. */
11161 {
11162 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
11163 it must be laid out in the vector register in reverse order. */
11171 {
11174 }
11176 }
11178 /* Sanity check. */
11181 do
11182 {
11231 }
11238 {
11248 /* Un-invert bytes of recognized vector, if necessary. */
11254 {
11255 /* FIXME: Broken on 32-bit H_W_I hosts. */
11264 }
11265 else
11266 {
11270 /* Construct 'abcdefgh' because the assembler cannot handle
11271 generic constants. */
11276 }
11277 }
11280 #undef CHECK
11281 }
11283 /* Check of immediate shift constants are within range. */
11284 bool
11286 {
11290 else
11292 }
11294 /* Return true if X is a uniform vector where all elements
11295 are either the floating-point constant 0.0 or the
11296 integer constant 0. */
11297 bool
11299 {
11301 }
11304 /* Return the bitmask CONST_INT to select the bits required by a zero extract
11305 operation of width WIDTH at bit position POS. */
11307 rtx
11309 {
11313 unsigned HOST_WIDE_INT mask
11316 }
11318 bool
11320 {
11325 {
11330 }
11333 }
11335 bool
11337 {
11350 }
11352 /* Return a const_int vector of VAL. */
11353 rtx
11355 {
11366 }
11368 /* Check OP is a legal scalar immediate for the MOVI instruction. */
11370 bool
11372 {
11373 machine_mode vmode;
11379 }
11381 /* Construct and return a PARALLEL RTX vector with elements numbering the
11382 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
11383 the vector - from the perspective of the architecture. This does not
11384 line up with GCC's perspective on lane numbers, so we end up with
11385 different masks depending on our target endian-ness. The diagram
11386 below may help. We must draw the distinction when building masks
11387 which select one half of the vector. An instruction selecting
11388 architectural low-lanes for a big-endian target, must be described using
11389 a mask selecting GCC high-lanes.
11391 Big-Endian Little-Endian
11393 GCC 0 1 2 3 3 2 1 0
11394 | x | x | x | x | | x | x | x | x |
11395 Architecture 3 2 1 0 3 2 1 0
11397 Low Mask: { 2, 3 } { 0, 1 }
11398 High Mask: { 0, 1 } { 2, 3 }
11399 */
11401 rtx
11403 {
11409 rtx t1;
11414 else
11422 }
11424 /* Check OP for validity as a PARALLEL RTX vector with elements
11425 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11426 from the perspective of the architecture. See the diagram above
11427 aarch64_simd_vect_par_cnst_half for more details. */
11429 bool
11432 {
11445 {
11452 }
11454 }
11456 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11457 HIGH (exclusive). */
11458 void
11460 const_tree exp)
11461 {
11462 HOST_WIDE_INT lane;
11467 {
11470 else
11472 }
11473 }
11475 /* Return TRUE if OP is a valid vector addressing mode. */
11476 bool
11478 {
11481 }
11483 /* Emit a register copy from operand to operand, taking care not to
11484 early-clobber source registers in the process.
11486 COUNT is the number of components into which the copy needs to be
11487 decomposed. */
11488 void
11491 {
11501 else
11505 }
11507 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11508 one of VSTRUCT modes: OI, CI, or XI. */
11509 int
11511 {
11513 }
11515 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11516 alignment of a vector to 128 bits. */
11517 static HOST_WIDE_INT
11519 {
11522 }
11524 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11525 static bool
11527 {
11531 /* We guarantee alignment for vectors up to 128-bits. */
11536 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11538 }
11540 /* Return true if the vector misalignment factor is supported by the
11541 target. */
11542 static bool
11546 {
11548 {
11549 /* Return if movmisalign pattern is not supported for this mode. */
11554 {
11555 /* Misalignment factor is unknown at compile time but we know
11556 it's word aligned. */
11558 {
11563 }
11565 }
11566 }
11568 is_packed);
11569 }
11571 /* If VALS is a vector constant that can be loaded into a register
11572 using DUP, generate instructions to do so and return an RTX to
11573 assign to the register. Otherwise return NULL_RTX. */
11574 static rtx
11576 {
11579 rtx x;
11584 /* We can load this constant by using DUP and a constant in a
11585 single ARM register. This will be cheaper than a vector
11586 load. */
11589 }
11592 /* Generate code to load VALS, which is a PARALLEL containing only
11593 constants (for vec_init) or CONST_VECTOR, efficiently into a
11594 register. Returns an RTX to copy into the register, or NULL_RTX
11595 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11596 static rtx
11598 {
11600 rtx const_dup;
11609 {
11610 /* A CONST_VECTOR must contain only CONST_INTs and
11611 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11612 Only store valid constants in a CONST_VECTOR. */
11614 {
11617 n_const++;
11618 }
11621 }
11622 else
11627 /* Load using MOVI/MVNI. */
11630 /* Loaded using DUP. */
11633 /* Load from constant pool. We can not take advantage of single-cycle
11634 LD1 because we need a PC-relative addressing mode. */
11636 else
11637 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11638 We can not construct an initializer. */
11640 }
11642 /* Expand a vector initialisation sequence, such that TARGET is
11643 initialised to contain VALS. */
11645 void
11647 {
11650 /* The number of vector elements. */
11652 /* The number of vector elements which are not constant. */
11655 /* The first element of vals. */
11659 /* Count the number of variable elements to initialise. */
11661 {
11665 else
11669 }
11671 /* No variable elements, hand off to aarch64_simd_make_constant which knows
11672 how best to handle this. */
11674 {
11677 {
11680 }
11681 }
11683 /* Splat a single non-constant element if we can. */
11685 {
11689 }
11691 /* Initialise a vector which is part-variable. We want to first try
11692 to build those lanes which are constant in the most efficient way we
11693 can. */
11695 {
11698 /* Load constant part of vector. We really don't care what goes into the
11699 parts we will overwrite, but we're more likely to be able to load the
11700 constant efficiently if it has fewer, larger, repeating parts
11701 (see aarch64_simd_valid_immediate). */
11703 {
11709 {
11710 /* Look in the copied vector, as more elements are const. */
11713 {
11716 }
11717 }
11719 }
11721 }
11723 /* Insert the variable lanes directly. */
11729 {
11735 }
11736 }
11738 static unsigned HOST_WIDE_INT
11740 {
11741 return
11742 (!SHIFT_COUNT_TRUNCATED
11745 }
11747 /* Select a format to encode pointers in exception handling data. */
11748 int
11750 {
11753 {
11759 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
11760 for everything. */
11764 /* No assumptions here. 8-byte relocs required. */
11767 }
11769 }
11771 /* The last .arch and .tune assembly strings that we printed. */
11775 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
11776 by the function fndecl. */
11778 void
11780 tree fndecl)
11781 {
11787 else
11798 /* Only update the assembler .arch string if it is distinct from the last
11799 such string we printed. */
11802 {
11805 }
11807 /* Print the cpu name we're tuning for in the comments, might be
11808 useful to readers of the generated asm. Do it only when it changes
11809 from function to function and verbose assembly is requested. */
11814 {
11818 }
11820 /* Don't forget the type directive for ELF. */
11823 }
11825 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
11827 static void
11829 {
11846 }
11848 /* Emit load exclusive. */
11850 static void
11853 {
11857 {
11864 }
11867 }
11869 /* Emit store exclusive. */
11871 static void
11874 {
11878 {
11885 }
11888 }
11890 /* Mark the previous jump instruction as unlikely. */
11892 static void
11894 {
11899 }
11901 /* Expand a compare and swap pattern. */
11903 void
11905 {
11910 gen_cas_fn gen;
11912 {
11913 gen_aarch64_compare_and_swapqi,
11914 gen_aarch64_compare_and_swaphi,
11915 gen_aarch64_compare_and_swapsi,
11916 gen_aarch64_compare_and_swapdi
11917 };
11919 {
11920 gen_aarch64_compare_and_swapqi_lse,
11921 gen_aarch64_compare_and_swaphi_lse,
11922 gen_aarch64_compare_and_swapsi_lse,
11923 gen_aarch64_compare_and_swapdi_lse
11924 };
11937 /* Normally the succ memory model must be stronger than fail, but in the
11938 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
11939 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
11946 {
11949 /* For short modes, we're going to perform the comparison in SImode,
11950 so do the zero-extension now. */
11954 /* Fall through. */
11958 /* Force the value into a register if needed. */
11965 }
11968 {
11975 }
11978 else
11989 }
11991 /* Test whether the target supports using a atomic load-operate instruction.
11992 CODE is the operation and AFTER is TRUE if the data in memory after the
11993 operation should be returned and FALSE if the data before the operation
11994 should be returned. Returns FALSE if the operation isn't supported by the
11995 architecture. */
11997 bool
11999 {
12004 {
12014 }
12015 }
12017 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
12018 sequence implementing an atomic operation. */
12020 static void
12022 {
12029 {
12031 }
12032 }
12034 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
12035 for the data in memory. EXPECTED is the value expected to be in memory.
12036 DESIRED is the value to store to memory. MEM is the memory location. MODEL
12037 is the memory ordering to use. */
12039 void
12042 rtx model)
12043 {
12045 machine_mode mode;
12050 {
12057 }
12059 /* Move the expected value into the CAS destination register. */
12062 /* Emit the CAS. */
12065 /* Compare the expected value with the value loaded by the CAS, to establish
12066 whether the swap was made. */
12068 }
12070 /* Split a compare and swap pattern. */
12072 void
12074 {
12076 machine_mode mode;
12081 rtx model_rtx;
12095 {
12098 }
12101 /* The initial load can be relaxed for a __sync operation since a final
12102 barrier will be emitted to stop code hoisting. */
12106 else
12118 {
12123 }
12124 else
12125 {
12129 }
12133 /* Emit any final barrier needed for a __sync operation. */
12136 }
12138 /* Emit a BIC instruction. */
12140 static void
12142 {
12147 {
12152 }
12155 }
12157 /* Emit an atomic swap. */
12159 static void
12162 {
12166 {
12173 }
12176 }
12178 /* Operations supported by aarch64_emit_atomic_load_op. */
12180 enum aarch64_atomic_load_op_code
12181 {
12185 AARCH64_LDOP_BIC /* A & ~B */
12186 };
12188 /* Emit an atomic load-operate. */
12190 static void
12194 {
12197 {
12198 gen_aarch64_atomic_loadaddqi,
12199 gen_aarch64_atomic_loadaddhi,
12200 gen_aarch64_atomic_loadaddsi,
12201 gen_aarch64_atomic_loadadddi
12202 };
12204 {
12205 gen_aarch64_atomic_loadeorqi,
12206 gen_aarch64_atomic_loadeorhi,
12207 gen_aarch64_atomic_loadeorsi,
12208 gen_aarch64_atomic_loadeordi
12209 };
12211 {
12212 gen_aarch64_atomic_loadsetqi,
12213 gen_aarch64_atomic_loadsethi,
12214 gen_aarch64_atomic_loadsetsi,
12215 gen_aarch64_atomic_loadsetdi
12216 };
12218 {
12219 gen_aarch64_atomic_loadclrqi,
12220 gen_aarch64_atomic_loadclrhi,
12221 gen_aarch64_atomic_loadclrsi,
12222 gen_aarch64_atomic_loadclrdi
12223 };
12224 aarch64_atomic_load_op_fn gen;
12228 {
12235 }
12238 {
12245 }
12248 }
12250 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
12251 location to store the data read from memory. OUT_RESULT is the location to
12252 store the result of the operation. MEM is the memory location to read and
12253 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
12254 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
12255 be NULL. */
12257 void
12260 {
12264 aarch64_atomic_load_op_code ldop_code;
12265 rtx src;
12266 rtx x;
12274 /* Make sure the value is in a register, putting it into a destination
12275 register if it needs to be manipulated. */
12278 {
12281 }
12282 else
12286 /* Preprocess the data for the operation as necessary. If the operation is
12287 a SET then emit a swap instruction and finish. */
12289 {
12295 /* Negate the value and treat it as a PLUS. */
12296 {
12297 rtx neg_src;
12299 /* Resize the value if necessary. */
12308 }
12309 /* Fall-through. */
12323 {
12324 rtx not_src;
12326 /* Resize the value if necessary. */
12335 }
12340 /* The operation can't be done with atomic instructions. */
12342 }
12346 /* If necessary, calculate the data in memory after the update by redoing the
12347 operation from values in registers. */
12352 {
12356 }
12361 {
12377 }
12382 }
12384 /* Split an atomic operation. */
12386 void
12389 {
12395 rtx x;
12397 /* Split the atomic operation into a sequence. */
12405 else
12409 /* The initial load can be relaxed for a __sync operation since a final
12410 barrier will be emitted to stop code hoisting. */
12414 else
12418 {
12432 {
12435 }
12436 /* Fall through. */
12442 }
12452 /* Emit any final barrier needed for a __sync operation. */
12455 }
12457 static void
12459 {
12460 /* Half-precision float operations. The compiler handles all operations
12461 with NULL libfuncs by converting to SFmode. */
12463 /* Conversions. */
12467 /* Arithmetic. */
12474 /* Comparisons. */
12482 }
12484 /* Target hook for c_mode_for_suffix. */
12485 static machine_mode
12487 {
12492 }
12494 /* We can only represent floating point constants which will fit in
12495 "quarter-precision" values. These values are characterised by
12496 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12497 by:
12499 (-1)^s * (n/16) * 2^r
12501 Where:
12502 's' is the sign bit.
12503 'n' is an integer in the range 16 <= n <= 31.
12504 'r' is an integer in the range -3 <= r <= 4. */
12506 /* Return true iff X can be represented by a quarter-precision
12507 floating point immediate operand X. Note, we cannot represent 0.0. */
12508 bool
12510 {
12511 /* This represents our current view of how many bits
12512 make up the mantissa. */
12522 /* We don't support HFmode constants yet. */
12528 /* We cannot represent infinities, NaNs or +/-zero. We won't
12529 know if we have +zero until we analyse the mantissa, but we
12530 can reject the other invalid values. */
12535 /* Extract exponent. */
12539 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12540 highest (sign) bit, with a fixed binary point at bit point_pos.
12541 m1 holds the low part of the mantissa, m2 the high part.
12542 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12543 bits for the mantissa, this can fail (low bits will be lost). */
12547 /* If the low part of the mantissa has bits set we cannot represent
12548 the value. */
12551 /* We have rejected the lower HOST_WIDE_INT, so update our
12552 understanding of how many bits lie in the mantissa and
12553 look only at the high HOST_WIDE_INT. */
12557 /* We can only represent values with a mantissa of the form 1.xxxx. */
12562 /* Having filtered unrepresentable values, we may now remove all
12563 but the highest 5 bits. */
12566 /* We cannot represent the value 0.0, so reject it. This is handled
12567 elsewhere. */
12571 /* Then, as bit 4 is always set, we can mask it off, leaving
12572 the mantissa in the range [0, 15]. */
12576 /* GCC internally does not use IEEE754-like encoding (where normalized
12577 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
12578 Our mantissa values are shifted 4 places to the left relative to
12579 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
12580 by 5 places to correct for GCC's representation. */
12584 }
12588 machine_mode mode,
12590 {
12600 /* This will return true to show const_vector is legal for use as either
12601 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
12602 also update INFO to show how the immediate should be generated. */
12611 {
12613 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
12614 move immediate path. */
12617 else
12618 {
12627 else
12631 }
12632 }
12645 else
12649 }
12653 machine_mode mode)
12654 {
12655 machine_mode vmode;
12661 }
12663 /* Split operands into moves from op[1] + op[2] into op[0]. */
12665 void
12667 {
12678 {
12679 /* No-op move. Can't split to nothing; emit something. */
12682 }
12684 /* Preserve register attributes for variable tracking. */
12689 /* Special case of reversed high/low parts. */
12692 {
12696 }
12698 {
12699 /* Try to avoid unnecessary moves if part of the result
12700 is in the right place already. */
12705 }
12706 else
12707 {
12712 }
12713 }
12715 /* vec_perm support. */
12717 #define MAX_VECT_LEN 16
12719 struct expand_vec_perm_d
12720 {
12723 machine_mode vmode;
12727 };
12729 /* Generate a variable permutation. */
12731 static void
12733 {
12744 {
12746 {
12747 /* Expand the argument to a V16QI mode by duplicating it. */
12751 }
12752 else
12753 {
12755 }
12756 }
12757 else
12758 {
12759 rtx pair;
12762 {
12766 }
12767 else
12768 {
12772 }
12773 }
12774 }
12776 void
12778 {
12782 rtx mask;
12784 /* The TBL instruction does not use a modulo index, so we must take care
12785 of that ourselves. */
12790 /* For big-endian, we also need to reverse the index within the vector
12791 (but not which vector). */
12793 {
12794 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
12799 }
12801 }
12803 /* Recognize patterns suitable for the TRN instructions. */
12804 static bool
12806 {
12815 /* Note that these are little-endian tests.
12816 We correct for big-endian later. */
12821 else
12826 {
12831 }
12833 /* Success! */
12840 {
12843 }
12847 {
12849 {
12864 }
12865 }
12866 else
12867 {
12869 {
12884 }
12885 }
12889 }
12891 /* Recognize patterns suitable for the UZP instructions. */
12892 static bool
12894 {
12903 /* Note that these are little-endian tests.
12904 We correct for big-endian later. */
12909 else
12914 {
12918 }
12920 /* Success! */
12927 {
12930 }
12934 {
12936 {
12951 }
12952 }
12953 else
12954 {
12956 {
12971 }
12972 }
12976 }
12978 /* Recognize patterns suitable for the ZIP instructions. */
12979 static bool
12981 {
12990 /* Note that these are little-endian tests.
12991 We correct for big-endian later. */
12994 /* Do Nothing. */
12995 ;
12998 else
13003 {
13010 }
13012 /* Success! */
13019 {
13022 }
13026 {
13028 {
13043 }
13044 }
13045 else
13046 {
13048 {
13063 }
13064 }
13068 }
13070 /* Recognize patterns for the EXT insn. */
13072 static bool
13074 {
13077 rtx offset;
13081 /* Check if the extracted indices are increasing by one. */
13083 {
13086 {
13087 /* We'll pass the same vector in twice, so allow indices to wrap. */
13089 }
13092 }
13095 {
13110 }
13112 /* Success! */
13116 /* The case where (location == 0) is a no-op for both big- and little-endian,
13117 and is removed by the mid-end at optimization levels -O1 and higher. */
13120 {
13121 /* After setup, we want the high elements of the first vector (stored
13122 at the LSB end of the register), and the low elements of the second
13123 vector (stored at the MSB end of the register). So swap. */
13125 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
13127 }
13132 }
13134 /* Recognize patterns for the REV insns. */
13136 static bool
13138 {
13147 {
13150 {
13155 }
13159 {
13166 }
13170 {
13183 }
13187 }
13191 {
13192 /* This is guaranteed to be true as the value of diff
13193 is 7, 3, 1 and we should have enough elements in the
13194 queue to generate this. Getting a vector mask with a
13195 value of diff other than these values implies that
13196 something is wrong by the time we get here. */
13200 }
13202 /* Success! */
13208 }
13210 static bool
13212 {
13215 rtx in0;
13218 rtx lane;
13222 {
13225 }
13227 /* The generic preparation in aarch64_expand_vec_perm_const_1
13228 swaps the operand order and the permute indices if it finds
13229 d->perm[0] to be in the second operand. Thus, we can always
13230 use d->op0 and need not do any extra arithmetic to get the
13231 correct lane number. */
13236 {
13251 }
13255 }
13257 static bool
13259 {
13267 /* Generic code will try constant permutation twice. Once with the
13268 original mode and again with the elements lowered to QImode.
13269 So wait and don't do the selector expansion ourselves. */
13274 {
13277 /* If big-endian and two vectors we end up with a weird mixed-endian
13278 mode on NEON. Reverse the index within each word but not the word
13279 itself. */
13282 }
13288 }
13290 static bool
13292 {
13293 /* The pattern matching functions above are written to look for a small
13294 number to begin the sequence (0, 1, N/2). If we begin with an index
13295 from the second operand, we can swap the operands. */
13297 {
13305 }
13308 {
13322 }
13324 }
13326 /* Expand a vec_perm_const pattern. */
13328 bool
13330 {
13344 {
13349 }
13352 {
13361 /* The elements of PERM do not suggest that only the first operand
13362 is used, but both operands are identical. Allow easier matching
13363 of the permutation by folding the permutation into the single
13364 input vector. */
13365 /* Fall Through. */
13377 }
13380 }
13382 static bool
13385 {
13395 /* Calculate whether all elements are in one vector. */
13397 {
13401 }
13403 /* If all elements are from the second vector, reindex as if from the
13404 first vector. */
13409 /* Check whether the mask can be applied to a single vector. */
13422 }
13424 rtx
13426 {
13427 /* We have to reverse each vector because we dont have
13428 a permuted load that can reverse-load according to ABI rules. */
13429 rtx mask;
13443 }
13445 /* Implement MODES_TIEABLE_P. In principle we should always return true.
13446 However due to issues with register allocation it is preferable to avoid
13447 tieing integer scalar and FP scalar modes. Executing integer operations
13448 in general registers is better than treating them as scalar vector
13449 operations. This reduces latency and avoids redundant int<->FP moves.
13450 So tie modes if they are either the same class, or vector modes with
13451 other vector modes, vector structs or any scalar mode.
13452 */
13454 bool
13456 {
13460 /* We specifically want to allow elements of "structure" modes to
13461 be tieable to the structure. This more general condition allows
13462 other rarer situations too. */
13466 /* Also allow any scalar modes with vectors. */
13472 }
13474 /* Return a new RTX holding the result of moving POINTER forward by
13475 AMOUNT bytes. */
13477 static rtx
13479 {
13484 }
13486 /* Return a new RTX holding the result of moving POINTER forward by the
13487 size of the mode it points to. */
13489 static rtx
13491 {
13495 }
13497 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13498 MODE bytes. */
13500 static void
13502 machine_mode mode)
13503 {
13506 /* "Cast" the pointers to the correct mode. */
13509 /* Emit the memcpy. */
13512 /* Move the pointers forward. */
13515 }
13517 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13518 we succeed, otherwise return false. */
13520 bool
13522 {
13526 rtx base;
13529 /* When optimizing for size, give a better estimate of the length of a
13530 memcpy call, but use the default otherwise. */
13533 /* We can't do anything smart if the amount to copy is not constant. */
13539 /* Try to keep the number of instructions low. For cases below 16 bytes we
13540 need to make at most two moves. For cases above 16 bytes it will be one
13541 move for each 16 byte chunk, then at most two additional moves. */
13551 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
13552 1-byte chunk. */
13554 {
13556 {
13559 }
13565 }
13567 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
13568 4-byte chunk, partially overlapping with the previously copied chunk. */
13570 {
13574 {
13580 }
13582 }
13584 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
13585 them, then (if applicable) an 8-byte chunk. */
13587 {
13589 {
13592 }
13593 else
13594 {
13597 }
13598 }
13600 /* Finish the final bytes of the copy. We can always do this in one
13601 instruction. We either copy the exact amount we need, or partially
13602 overlap with the previous chunk we copied and copy 8-bytes. */
13611 else
13612 {
13614 {
13618 }
13619 else
13620 {
13626 }
13627 }
13630 }
13632 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
13633 SImode stores. Handle the case when the constant has identical
13634 bottom and top halves. This is beneficial when the two stores can be
13635 merged into an STP and we avoid synthesising potentially expensive
13636 immediates twice. Return true if such a split is possible. */
13638 bool
13640 {
13649 unsigned int orig_cost
13651 unsigned int lo_cost
13654 /* We want to transform:
13655 MOV x1, 49370
13656 MOVK x1, 0x140, lsl 16
13657 MOVK x1, 0xc0da, lsl 32
13658 MOVK x1, 0x140, lsl 48
13659 STR x1, [x0]
13660 into:
13661 MOV w1, 49370
13662 MOVK w1, 0x140, lsl 16
13663 STP w1, w1, [x0]
13664 So we want to perform this only when we save two instructions
13665 or more. When optimizing for size, however, accept any code size
13666 savings we can. */
13681 /* Don't emit an explicit store pair as this may not be always profitable.
13682 Let the sched-fusion logic decide whether to merge them. */
13687 }
13689 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
13691 static unsigned HOST_WIDE_INT
13693 {
13695 }
13697 static bool
13702 {
13703 /* STORE_BY_PIECES can be used when copying a constant string, but
13704 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
13705 For now we always fail this and let the move_by_pieces code copy
13706 the string from read-only memory. */
13711 }
13713 static rtx
13716 {
13720 insn_code icode;
13731 {
13759 }
13764 {
13767 }
13776 {
13779 }
13785 }
13787 static rtx
13790 {
13794 insn_code icode;
13806 {
13834 }
13839 {
13842 }
13850 {
13855 }
13866 {
13869 }
13875 }
13877 #undef TARGET_GEN_CCMP_FIRST
13878 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
13880 #undef TARGET_GEN_CCMP_NEXT
13881 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
13883 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
13884 instruction fusion of some sort. */
13886 static bool
13888 {
13890 }
13893 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
13894 should be kept together during scheduling. */
13896 static bool
13898 {
13899 rtx set_dest;
13902 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
13909 {
13910 /* We are trying to match:
13911 prev (mov) == (set (reg r0) (const_int imm16))
13912 curr (movk) == (set (zero_extract (reg r0)
13913 (const_int 16)
13914 (const_int 16))
13915 (const_int imm16_1)) */
13927 {
13929 }
13930 }
13933 {
13935 /* We're trying to match:
13936 prev (adrp) == (set (reg r1)
13937 (high (symbol_ref ("SYM"))))
13938 curr (add) == (set (reg r0)
13939 (lo_sum (reg r1)
13940 (symbol_ref ("SYM"))))
13941 Note that r0 need not necessarily be the same as r1, especially
13942 during pre-regalloc scheduling. */
13946 {
13954 }
13955 }
13958 {
13960 /* We're trying to match:
13961 prev (movk) == (set (zero_extract (reg r0)
13962 (const_int 16)
13963 (const_int 32))
13964 (const_int imm16_1))
13965 curr (movk) == (set (zero_extract (reg r0)
13966 (const_int 16)
13967 (const_int 48))
13968 (const_int imm16_2)) */
13984 }
13986 {
13987 /* We're trying to match:
13988 prev (adrp) == (set (reg r0)
13989 (high (symbol_ref ("SYM"))))
13990 curr (ldr) == (set (reg r1)
13991 (mem (lo_sum (reg r0)
13992 (symbol_ref ("SYM")))))
13993 or
13994 curr (ldr) == (set (reg r1)
13995 (zero_extend (mem
13996 (lo_sum (reg r0)
13997 (symbol_ref ("SYM")))))) */
14000 {
14013 }
14014 }
14022 {
14025 /* FIXME: this misses some which is considered simple arthematic
14026 instructions for ThunderX. Simple shifts are missed here. */
14032 }
14035 }
14037 /* Return true iff the instruction fusion described by OP is enabled. */
14039 bool
14041 {
14043 }
14045 /* If MEM is in the form of [base+offset], extract the two parts
14046 of address and set to BASE and OFFSET, otherwise return false
14047 after clearing BASE and OFFSET. */
14049 bool
14051 {
14052 rtx addr;
14059 {
14063 }
14067 {
14071 }
14077 }
14079 /* Types for scheduling fusion. */
14080 enum sched_fusion_type
14081 {
14083 SCHED_FUSION_LD_SIGN_EXTEND,
14084 SCHED_FUSION_LD_ZERO_EXTEND,
14085 SCHED_FUSION_LD,
14086 SCHED_FUSION_ST,
14087 SCHED_FUSION_NUM
14088 };
14090 /* If INSN is a load or store of address in the form of [base+offset],
14091 extract the two parts and set to BASE and OFFSET. Return scheduling
14092 fusion type this INSN is. */
14094 static enum sched_fusion_type
14096 {
14114 {
14119 }
14121 {
14126 }
14131 {
14134 }
14135 else
14142 }
14144 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
14146 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
14147 and PRI are only calculated for these instructions. For other instruction,
14148 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
14149 type instruction fusion can be added by returning different priorities.
14151 It's important that irrelevant instructions get the largest FUSION_PRI. */
14153 static void
14156 {
14166 {
14170 }
14172 /* Set FUSION_PRI according to fusion type and base register. */
14175 /* Calculate PRI. */
14178 /* INSN with smaller offset goes first. */
14182 else
14187 }
14189 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
14190 Adjust priority of sha1h instructions so they are scheduled before
14191 other SHA1 instructions. */
14193 static int
14195 {
14199 {
14204 }
14207 }
14209 /* Given OPERANDS of consecutive load/store, check if we can merge
14210 them into ldp/stp. LOAD is true if they are load instructions.
14211 MODE is the mode of memory operands. */
14213 bool
14216 {
14222 {
14230 }
14231 else
14232 {
14237 }
14239 /* The mems cannot be volatile. */
14243 /* If we have SImode and slow unaligned ldp,
14244 check the alignment to be at least 8 byte. */
14248 && !optimize_size
14252 /* Check if the addresses are in the form of [base+offset]. */
14260 /* Check if the bases are same. */
14267 /* Check if the offsets are consecutive. */
14271 /* Check if the addresses are clobbered by load. */
14273 {
14277 /* In increasing order, the last load can clobber the address. */
14280 }
14284 else
14289 else
14292 /* Check if the registers are of same class. */
14297 }
14299 /* Given OPERANDS of consecutive load/store, check if we can merge
14300 them into ldp/stp by adjusting the offset. LOAD is true if they
14301 are load instructions. MODE is the mode of memory operands.
14303 Given below consecutive stores:
14305 str w1, [xb, 0x100]
14306 str w1, [xb, 0x104]
14307 str w1, [xb, 0x108]
14308 str w1, [xb, 0x10c]
14310 Though the offsets are out of the range supported by stp, we can
14311 still pair them after adjusting the offset, like:
14313 add scratch, xb, 0x100
14314 stp w1, w1, [scratch]
14315 stp w1, w1, [scratch, 0x8]
14317 The peephole patterns detecting this opportunity should guarantee
14318 the scratch register is avaliable. */
14320 bool
14323 {
14330 {
14343 }
14344 else
14345 {
14354 }
14355 /* Skip if memory operand is by itslef valid for ldp/stp. */
14359 /* The mems cannot be volatile. */
14364 /* Check if the addresses are in the form of [base+offset]. */
14378 /* Check if the bases are same. */
14389 /* Check if the offsets are consecutive. */
14398 /* Check if the addresses are clobbered by load. */
14400 {
14406 /* In increasing order, the last load can clobber the address. */
14409 }
14411 /* If we have SImode and slow unaligned ldp,
14412 check the alignment to be at least 8 byte. */
14416 && !optimize_size
14422 else
14427 else
14432 else
14437 else
14440 /* Check if the registers are of same class. */
14445 }
14447 /* Given OPERANDS of consecutive load/store, this function pairs them
14448 into ldp/stp after adjusting the offset. It depends on the fact
14449 that addresses of load/store instructions are in increasing order.
14450 MODE is the mode of memory operands. CODE is the rtl operator
14451 which should be applied to all memory operands, it's SIGN_EXTEND,
14452 ZERO_EXTEND or UNKNOWN. */
14454 bool
14457 {
14463 {
14468 }
14469 else
14470 {
14476 }
14481 /* Adjust offset thus it can fit in ldp/stp instruction. */
14489 /* Further adjust to make sure all offsets are OK. */
14491 {
14494 }
14496 /* Make sure the adjustment can be done with ADD/SUB instructions. */
14501 {
14504 }
14506 /* Create new memory references. */
14510 /* Check if the adjusted address is OK for ldp/stp. */
14529 {
14534 }
14536 {
14541 }
14544 {
14549 }
14550 else
14551 {
14556 }
14558 /* Emit adjusting instruction. */
14560 /* Emit ldp/stp instructions. */
14568 }
14570 /* Return 1 if pseudo register should be created and used to hold
14571 GOT address for PIC code. */
14573 bool
14575 {
14577 }
14579 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
14581 static int
14583 {
14585 {
14592 }
14595 }
14598 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
14599 return the log2 of that value. Otherwise return -1. */
14601 int
14603 {
14618 }
14620 /* If X is a vector of equal CONST_DOUBLE values and that value is
14621 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
14623 int
14625 {
14641 }
14643 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
14644 to float.
14646 __fp16 always promotes through this hook.
14647 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
14648 through the generic excess precision logic rather than here. */
14650 static tree
14652 {
14658 }
14660 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
14662 static bool
14664 optimization_type opt_type)
14665 {
14667 {
14673 }
14674 }
14676 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
14677 if MODE is HFmode, and punt to the generic implementation otherwise. */
14679 static bool
14681 {
14685 }
14687 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
14688 if MODE is HFmode, and punt to the generic implementation otherwise. */
14690 static bool
14692 {
14696 }
14698 /* Set the value of FLT_EVAL_METHOD.
14699 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
14701 0: evaluate all operations and constants, whose semantic type has at
14702 most the range and precision of type float, to the range and
14703 precision of float; evaluate all other operations and constants to
14704 the range and precision of the semantic type;
14706 N, where _FloatN is a supported interchange floating type
14707 evaluate all operations and constants, whose semantic type has at
14708 most the range and precision of _FloatN type, to the range and
14709 precision of the _FloatN type; evaluate all other operations and
14710 constants to the range and precision of the semantic type;
14712 If we have the ARMv8.2-A extensions then we support _Float16 in native
14713 precision, so we should set this to 16. Otherwise, we support the type,
14714 but want to evaluate expressions in float precision, so set this to
14715 0. */
14717 static enum flt_eval_method
14719 {
14721 {
14724 /* We can calculate either in 16-bit range and precision or
14725 32-bit range and precision. Make that decision based on whether
14726 we have native support for the ARMv8.2-A 16-bit floating-point
14727 instructions or not. */
14729 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
14735 }
14737 }
14739 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
14740 scheduled for speculative execution. Reject the long-running division
14741 and square-root instructions. */
14743 static bool
14745 {
14747 {
14765 }
14766 }
14768 /* Target-specific selftests. */
14770 #if CHECKING_P
14774 /* Selftest for the RTL loader.
14775 Verify that the RTL loader copes with a dump from
14776 print_rtx_function. This is essentially just a test that class
14777 function_reader can handle a real dump, but it also verifies
14778 that lookup_reg_by_dump_name correctly handles hard regs.
14779 The presence of hard reg names in the dump means that the test is
14780 target-specific, hence it is in this file. */
14782 static void
14784 {
14796 /* Verify crtl->return_rtx. */
14800 }
14802 /* Run all target-specific selftests. */
14804 static void
14806 {
14808 }
14814 #undef TARGET_ADDRESS_COST
14815 #define TARGET_ADDRESS_COST aarch64_address_cost
14817 /* This hook will determines whether unnamed bitfields affect the alignment
14818 of the containing structure. The hook returns true if the structure
14819 should inherit the alignment requirements of an unnamed bitfield's
14820 type. */
14821 #undef TARGET_ALIGN_ANON_BITFIELD
14822 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
14824 #undef TARGET_ASM_ALIGNED_DI_OP
14827 #undef TARGET_ASM_ALIGNED_HI_OP
14830 #undef TARGET_ASM_ALIGNED_SI_OP
14833 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
14834 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
14835 hook_bool_const_tree_hwi_hwi_const_tree_true
14837 #undef TARGET_ASM_FILE_START
14838 #define TARGET_ASM_FILE_START aarch64_start_file
14840 #undef TARGET_ASM_OUTPUT_MI_THUNK
14841 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
14843 #undef TARGET_ASM_SELECT_RTX_SECTION
14844 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
14846 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
14847 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
14849 #undef TARGET_BUILD_BUILTIN_VA_LIST
14850 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
14852 #undef TARGET_CALLEE_COPIES
14853 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
14855 #undef TARGET_CAN_ELIMINATE
14856 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
14858 #undef TARGET_CAN_INLINE_P
14859 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
14861 #undef TARGET_CANNOT_FORCE_CONST_MEM
14862 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
14864 #undef TARGET_CASE_VALUES_THRESHOLD
14865 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
14867 #undef TARGET_CONDITIONAL_REGISTER_USAGE
14868 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
14870 /* Only the least significant bit is used for initialization guard
14871 variables. */
14872 #undef TARGET_CXX_GUARD_MASK_BIT
14873 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
14875 #undef TARGET_C_MODE_FOR_SUFFIX
14876 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
14878 #ifdef TARGET_BIG_ENDIAN_DEFAULT
14879 #undef TARGET_DEFAULT_TARGET_FLAGS
14880 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
14881 #endif
14883 #undef TARGET_CLASS_MAX_NREGS
14884 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
14886 #undef TARGET_BUILTIN_DECL
14887 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
14889 #undef TARGET_BUILTIN_RECIPROCAL
14890 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
14892 #undef TARGET_C_EXCESS_PRECISION
14893 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
14895 #undef TARGET_EXPAND_BUILTIN
14896 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
14898 #undef TARGET_EXPAND_BUILTIN_VA_START
14899 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
14901 #undef TARGET_FOLD_BUILTIN
14902 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
14904 #undef TARGET_FUNCTION_ARG
14905 #define TARGET_FUNCTION_ARG aarch64_function_arg
14907 #undef TARGET_FUNCTION_ARG_ADVANCE
14908 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
14910 #undef TARGET_FUNCTION_ARG_BOUNDARY
14911 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
14913 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
14914 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
14916 #undef TARGET_FUNCTION_VALUE
14917 #define TARGET_FUNCTION_VALUE aarch64_function_value
14919 #undef TARGET_FUNCTION_VALUE_REGNO_P
14920 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
14922 #undef TARGET_FRAME_POINTER_REQUIRED
14923 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
14925 #undef TARGET_GIMPLE_FOLD_BUILTIN
14926 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
14928 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
14929 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
14931 #undef TARGET_INIT_BUILTINS
14932 #define TARGET_INIT_BUILTINS aarch64_init_builtins
14934 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
14935 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
14936 aarch64_ira_change_pseudo_allocno_class
14938 #undef TARGET_LEGITIMATE_ADDRESS_P
14939 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
14941 #undef TARGET_LEGITIMATE_CONSTANT_P
14942 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
14944 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
14945 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
14946 aarch64_legitimize_address_displacement
14948 #undef TARGET_LIBGCC_CMP_RETURN_MODE
14949 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
14951 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
14952 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
14953 aarch64_libgcc_floating_mode_supported_p
14955 #undef TARGET_MANGLE_TYPE
14956 #define TARGET_MANGLE_TYPE aarch64_mangle_type
14958 #undef TARGET_MEMORY_MOVE_COST
14959 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
14961 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
14962 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
14964 #undef TARGET_MUST_PASS_IN_STACK
14965 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
14967 /* This target hook should return true if accesses to volatile bitfields
14968 should use the narrowest mode possible. It should return false if these
14969 accesses should use the bitfield container type. */
14970 #undef TARGET_NARROW_VOLATILE_BITFIELD
14971 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
14973 #undef TARGET_OPTION_OVERRIDE
14974 #define TARGET_OPTION_OVERRIDE aarch64_override_options
14976 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
14977 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
14978 aarch64_override_options_after_change
14980 #undef TARGET_OPTION_SAVE
14981 #define TARGET_OPTION_SAVE aarch64_option_save
14983 #undef TARGET_OPTION_RESTORE
14984 #define TARGET_OPTION_RESTORE aarch64_option_restore
14986 #undef TARGET_OPTION_PRINT
14987 #define TARGET_OPTION_PRINT aarch64_option_print
14989 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
14990 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
14992 #undef TARGET_SET_CURRENT_FUNCTION
14993 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
14995 #undef TARGET_PASS_BY_REFERENCE
14996 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
14998 #undef TARGET_PREFERRED_RELOAD_CLASS
14999 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
15001 #undef TARGET_SCHED_REASSOCIATION_WIDTH
15002 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
15004 #undef TARGET_PROMOTED_TYPE
15005 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
15007 #undef TARGET_SECONDARY_RELOAD
15008 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
15010 #undef TARGET_SHIFT_TRUNCATION_MASK
15011 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
15013 #undef TARGET_SETUP_INCOMING_VARARGS
15014 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
15016 #undef TARGET_STRUCT_VALUE_RTX
15017 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
15019 #undef TARGET_REGISTER_MOVE_COST
15020 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
15022 #undef TARGET_RETURN_IN_MEMORY
15023 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
15025 #undef TARGET_RETURN_IN_MSB
15026 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
15028 #undef TARGET_RTX_COSTS
15029 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
15031 #undef TARGET_SCALAR_MODE_SUPPORTED_P
15032 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
15034 #undef TARGET_SCHED_ISSUE_RATE
15035 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
15037 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
15038 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
15039 aarch64_sched_first_cycle_multipass_dfa_lookahead
15041 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
15042 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
15043 aarch64_first_cycle_multipass_dfa_lookahead_guard
15045 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
15046 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
15047 aarch64_get_separate_components
15049 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
15050 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
15051 aarch64_components_for_bb
15053 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
15054 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
15055 aarch64_disqualify_components
15057 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
15058 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
15059 aarch64_emit_prologue_components
15061 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
15062 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
15063 aarch64_emit_epilogue_components
15065 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
15066 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
15067 aarch64_set_handled_components
15069 #undef TARGET_TRAMPOLINE_INIT
15070 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
15072 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
15073 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
15075 #undef TARGET_VECTOR_MODE_SUPPORTED_P
15076 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
15078 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
15079 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
15080 aarch64_builtin_support_vector_misalignment
15082 #undef TARGET_ARRAY_MODE_SUPPORTED_P
15083 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
15085 #undef TARGET_VECTORIZE_ADD_STMT_COST
15086 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
15088 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
15089 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
15090 aarch64_builtin_vectorization_cost
15092 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
15093 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
15095 #undef TARGET_VECTORIZE_BUILTINS
15096 #define TARGET_VECTORIZE_BUILTINS
15098 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
15099 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
15100 aarch64_builtin_vectorized_function
15102 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
15103 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
15104 aarch64_autovectorize_vector_sizes
15106 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
15107 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
15108 aarch64_atomic_assign_expand_fenv
15110 /* Section anchor support. */
15112 #undef TARGET_MIN_ANCHOR_OFFSET
15113 #define TARGET_MIN_ANCHOR_OFFSET -256
15115 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
15116 byte offset; we can do much more for larger data types, but have no way
15117 to determine the size of the access. We assume accesses are aligned. */
15118 #undef TARGET_MAX_ANCHOR_OFFSET
15119 #define TARGET_MAX_ANCHOR_OFFSET 4095
15121 #undef TARGET_VECTOR_ALIGNMENT
15122 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
15124 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
15125 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
15126 aarch64_simd_vector_alignment_reachable
15128 /* vec_perm support. */
15130 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
15131 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
15132 aarch64_vectorize_vec_perm_const_ok
15134 #undef TARGET_INIT_LIBFUNCS
15135 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
15137 #undef TARGET_FIXED_CONDITION_CODE_REGS
15138 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
15140 #undef TARGET_FLAGS_REGNUM
15141 #define TARGET_FLAGS_REGNUM CC_REGNUM
15143 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
15144 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
15146 #undef TARGET_ASAN_SHADOW_OFFSET
15147 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
15149 #undef TARGET_LEGITIMIZE_ADDRESS
15150 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
15152 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
15153 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
15154 aarch64_use_by_pieces_infrastructure_p
15156 #undef TARGET_SCHED_CAN_SPECULATE_INSN
15157 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
15159 #undef TARGET_CAN_USE_DOLOOP_P
15160 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
15162 #undef TARGET_SCHED_ADJUST_PRIORITY
15163 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
15165 #undef TARGET_SCHED_MACRO_FUSION_P
15166 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
15168 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
15169 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
15171 #undef TARGET_SCHED_FUSION_PRIORITY
15172 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
15174 #undef TARGET_UNSPEC_MAY_TRAP_P
15175 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
15177 #undef TARGET_USE_PSEUDO_PIC_REG
15178 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
15180 #undef TARGET_PRINT_OPERAND
15181 #define TARGET_PRINT_OPERAND aarch64_print_operand
15183 #undef TARGET_PRINT_OPERAND_ADDRESS
15184 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
15186 #undef TARGET_OPTAB_SUPPORTED_P
15187 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
15189 #undef TARGET_OMIT_STRUCT_RETURN_REG
15190 #define TARGET_OMIT_STRUCT_RETURN_REG true
15192 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
15193 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
15194 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
15196 #if CHECKING_P
15197 #undef TARGET_RUN_TARGET_SELFTESTS
15198 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests