1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2020 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with modified_between_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
95 #include "stor-layout.h"
97 #include "cfgcleanup.h"
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
100 #include "insn-attr.h"
101 #include "rtlhooks-def.h"
103 #include "tree-pass.h"
104 #include "valtrack.h"
105 #include "rtl-iter.h"
106 #include "print-rtl.h"
107 #include "function-abi.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts
;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges
;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras
;
121 /* Number of instructions combined in this function. */
123 static int combine_successes
;
125 /* Totals over entire compilation. */
127 static int total_attempts
, total_merges
, total_extras
, total_successes
;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
136 static rtx_insn
*i2mod
;
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs
;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs
;
146 struct reg_stat_type
{
147 /* Record last point of death of (hard or pseudo) register n. */
148 rtx_insn
*last_death
;
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick
;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
216 char last_set_sign_bit_copies
;
217 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid
;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies
;
239 unsigned HOST_WIDE_INT nonzero_bits
;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label
;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
256 static vec
<reg_stat_type
> reg_stat
;
258 /* One plus the highest pseudo for which we track REG_N_SETS.
259 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
260 but during combine_split_insns new pseudos can be created. As we don't have
261 updated DF information in that case, it is hard to initialize the array
262 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
263 so instead of growing the arrays, just assume all newly created pseudos
264 during combine might be set multiple times. */
266 static unsigned int reg_n_sets_max
;
268 /* Record the luid of the last insn that invalidated memory
269 (anything that writes memory, and subroutine calls, but not pushes). */
271 static int mem_last_set
;
273 /* Record the luid of the last CALL_INSN
274 so we can tell whether a potential combination crosses any calls. */
276 static int last_call_luid
;
278 /* When `subst' is called, this is the insn that is being modified
279 (by combining in a previous insn). The PATTERN of this insn
280 is still the old pattern partially modified and it should not be
281 looked at, but this may be used to examine the successors of the insn
282 to judge whether a simplification is valid. */
284 static rtx_insn
*subst_insn
;
286 /* This is the lowest LUID that `subst' is currently dealing with.
287 get_last_value will not return a value if the register was set at or
288 after this LUID. If not for this mechanism, we could get confused if
289 I2 or I1 in try_combine were an insn that used the old value of a register
290 to obtain a new value. In that case, we might erroneously get the
291 new value of the register when we wanted the old one. */
293 static int subst_low_luid
;
295 /* This contains any hard registers that are used in newpat; reg_dead_at_p
296 must consider all these registers to be always live. */
298 static HARD_REG_SET newpat_used_regs
;
300 /* This is an insn to which a LOG_LINKS entry has been added. If this
301 insn is the earlier than I2 or I3, combine should rescan starting at
304 static rtx_insn
*added_links_insn
;
306 /* And similarly, for notes. */
308 static rtx_insn
*added_notes_insn
;
310 /* Basic block in which we are performing combines. */
311 static basic_block this_basic_block
;
312 static bool optimize_this_for_speed_p
;
315 /* Length of the currently allocated uid_insn_cost array. */
317 static int max_uid_known
;
319 /* The following array records the insn_cost for every insn
320 in the instruction stream. */
322 static int *uid_insn_cost
;
324 /* The following array records the LOG_LINKS for every insn in the
325 instruction stream as struct insn_link pointers. */
330 struct insn_link
*next
;
333 static struct insn_link
**uid_log_links
;
336 insn_uid_check (const_rtx insn
)
338 int uid
= INSN_UID (insn
);
339 gcc_checking_assert (uid
<= max_uid_known
);
343 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
344 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
346 #define FOR_EACH_LOG_LINK(L, INSN) \
347 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
349 /* Links for LOG_LINKS are allocated from this obstack. */
351 static struct obstack insn_link_obstack
;
353 /* Allocate a link. */
355 static inline struct insn_link
*
356 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
359 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
360 sizeof (struct insn_link
));
367 /* Incremented for each basic block. */
369 static int label_tick
;
371 /* Reset to label_tick for each extended basic block in scanning order. */
373 static int label_tick_ebb_start
;
375 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
376 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
378 static scalar_int_mode nonzero_bits_mode
;
380 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
381 be safely used. It is zero while computing them and after combine has
382 completed. This former test prevents propagating values based on
383 previously set values, which can be incorrect if a variable is modified
386 static int nonzero_sign_valid
;
389 /* Record one modification to rtl structure
390 to be undone by storing old_contents into *where. */
392 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
398 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
399 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
402 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
403 num_undo says how many are currently recorded.
405 other_insn is nonzero if we have modified some other insn in the process
406 of working on subst_insn. It must be verified too. */
412 rtx_insn
*other_insn
;
415 static struct undobuf undobuf
;
417 /* Number of times the pseudo being substituted for
418 was found and replaced. */
420 static int n_occurrences
;
422 static rtx
reg_nonzero_bits_for_combine (const_rtx
, scalar_int_mode
,
424 unsigned HOST_WIDE_INT
*);
425 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, scalar_int_mode
,
428 static void do_SUBST (rtx
*, rtx
);
429 static void do_SUBST_INT (int *, int);
430 static void init_reg_last (void);
431 static void setup_incoming_promotions (rtx_insn
*);
432 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
433 static int cant_combine_insn_p (rtx_insn
*);
434 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
435 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
436 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
437 static int contains_muldiv (rtx
);
438 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
440 static void undo_all (void);
441 static void undo_commit (void);
442 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
443 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
444 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
445 static rtx
simplify_if_then_else (rtx
);
446 static rtx
simplify_set (rtx
);
447 static rtx
simplify_logical (rtx
);
448 static rtx
expand_compound_operation (rtx
);
449 static const_rtx
expand_field_assignment (const_rtx
);
450 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
451 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
452 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
453 unsigned HOST_WIDE_INT
*);
454 static rtx
canon_reg_for_combine (rtx
, rtx
);
455 static rtx
force_int_to_mode (rtx
, scalar_int_mode
, scalar_int_mode
,
456 scalar_int_mode
, unsigned HOST_WIDE_INT
, int);
457 static rtx
force_to_mode (rtx
, machine_mode
,
458 unsigned HOST_WIDE_INT
, int);
459 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
460 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
461 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
462 static rtx
make_field_assignment (rtx
);
463 static rtx
apply_distributive_law (rtx
);
464 static rtx
distribute_and_simplify_rtx (rtx
, int);
465 static rtx
simplify_and_const_int_1 (scalar_int_mode
, rtx
,
466 unsigned HOST_WIDE_INT
);
467 static rtx
simplify_and_const_int (rtx
, scalar_int_mode
, rtx
,
468 unsigned HOST_WIDE_INT
);
469 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
470 HOST_WIDE_INT
, machine_mode
, int *);
471 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
472 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
474 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
475 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
476 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
478 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
479 static void update_table_tick (rtx
);
480 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
481 static void check_promoted_subreg (rtx_insn
*, rtx
);
482 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
483 static void record_dead_and_set_regs (rtx_insn
*);
484 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
485 static rtx
get_last_value (const_rtx
);
486 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
487 static int reg_dead_at_p (rtx
, rtx_insn
*);
488 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
489 static int reg_bitfield_target_p (rtx
, rtx
);
490 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
491 static void distribute_links (struct insn_link
*);
492 static void mark_used_regs_combine (rtx
);
493 static void record_promoted_value (rtx_insn
*, rtx
);
494 static bool unmentioned_reg_p (rtx
, rtx
);
495 static void record_truncated_values (rtx
*, void *);
496 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
497 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
500 /* It is not safe to use ordinary gen_lowpart in combine.
501 See comments in gen_lowpart_for_combine. */
502 #undef RTL_HOOKS_GEN_LOWPART
503 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
505 /* Our implementation of gen_lowpart never emits a new pseudo. */
506 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
507 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
509 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
510 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
512 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
513 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
515 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
516 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
518 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
521 /* Convenience wrapper for the canonicalize_comparison target hook.
522 Target hooks cannot use enum rtx_code. */
524 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
525 bool op0_preserve_value
)
527 int code_int
= (int)*code
;
528 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
529 *code
= (enum rtx_code
)code_int
;
532 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
533 PATTERN cannot be split. Otherwise, it returns an insn sequence.
534 This is a wrapper around split_insns which ensures that the
535 reg_stat vector is made larger if the splitter creates a new
539 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
544 ret
= split_insns (pattern
, insn
);
545 nregs
= max_reg_num ();
546 if (nregs
> reg_stat
.length ())
547 reg_stat
.safe_grow_cleared (nregs
, true);
551 /* This is used by find_single_use to locate an rtx in LOC that
552 contains exactly one use of DEST, which is typically either a REG
553 or CC0. It returns a pointer to the innermost rtx expression
554 containing DEST. Appearances of DEST that are being used to
555 totally replace it are not counted. */
558 find_single_use_1 (rtx dest
, rtx
*loc
)
561 enum rtx_code code
= GET_CODE (x
);
577 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
578 of a REG that occupies all of the REG, the insn uses DEST if
579 it is mentioned in the destination or the source. Otherwise, we
580 need just check the source. */
581 if (GET_CODE (SET_DEST (x
)) != CC0
582 && GET_CODE (SET_DEST (x
)) != PC
583 && !REG_P (SET_DEST (x
))
584 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
585 && REG_P (SUBREG_REG (SET_DEST (x
)))
586 && !read_modify_subreg_p (SET_DEST (x
))))
589 return find_single_use_1 (dest
, &SET_SRC (x
));
593 return find_single_use_1 (dest
, &XEXP (x
, 0));
599 /* If it wasn't one of the common cases above, check each expression and
600 vector of this code. Look for a unique usage of DEST. */
602 fmt
= GET_RTX_FORMAT (code
);
603 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
607 if (dest
== XEXP (x
, i
)
608 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
609 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
612 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
615 result
= this_result
;
616 else if (this_result
)
617 /* Duplicate usage. */
620 else if (fmt
[i
] == 'E')
624 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
626 if (XVECEXP (x
, i
, j
) == dest
628 && REG_P (XVECEXP (x
, i
, j
))
629 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
632 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
635 result
= this_result
;
636 else if (this_result
)
646 /* See if DEST, produced in INSN, is used only a single time in the
647 sequel. If so, return a pointer to the innermost rtx expression in which
650 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
652 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
653 care about REG_DEAD notes or LOG_LINKS.
655 Otherwise, we find the single use by finding an insn that has a
656 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
657 only referenced once in that insn, we know that it must be the first
658 and last insn referencing DEST. */
661 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
666 struct insn_link
*link
;
670 next
= NEXT_INSN (insn
);
672 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
675 result
= find_single_use_1 (dest
, &PATTERN (next
));
684 bb
= BLOCK_FOR_INSN (insn
);
685 for (next
= NEXT_INSN (insn
);
686 next
&& BLOCK_FOR_INSN (next
) == bb
;
687 next
= NEXT_INSN (next
))
688 if (NONDEBUG_INSN_P (next
) && dead_or_set_p (next
, dest
))
690 FOR_EACH_LOG_LINK (link
, next
)
691 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
696 result
= find_single_use_1 (dest
, &PATTERN (next
));
706 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
707 insn. The substitution can be undone by undo_all. If INTO is already
708 set to NEWVAL, do not record this change. Because computing NEWVAL might
709 also call SUBST, we have to compute it before we put anything into
713 do_SUBST (rtx
*into
, rtx newval
)
718 if (oldval
== newval
)
721 /* We'd like to catch as many invalid transformations here as
722 possible. Unfortunately, there are way too many mode changes
723 that are perfectly valid, so we'd waste too much effort for
724 little gain doing the checks here. Focus on catching invalid
725 transformations involving integer constants. */
726 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
727 && CONST_INT_P (newval
))
729 /* Sanity check that we're replacing oldval with a CONST_INT
730 that is a valid sign-extension for the original mode. */
731 gcc_assert (INTVAL (newval
)
732 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
734 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
735 CONST_INT is not valid, because after the replacement, the
736 original mode would be gone. Unfortunately, we can't tell
737 when do_SUBST is called to replace the operand thereof, so we
738 perform this test on oldval instead, checking whether an
739 invalid replacement took place before we got here. */
740 gcc_assert (!(GET_CODE (oldval
) == SUBREG
741 && CONST_INT_P (SUBREG_REG (oldval
))));
742 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
743 && CONST_INT_P (XEXP (oldval
, 0))));
747 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
749 buf
= XNEW (struct undo
);
751 buf
->kind
= UNDO_RTX
;
753 buf
->old_contents
.r
= oldval
;
756 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
759 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
761 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
762 for the value of a HOST_WIDE_INT value (including CONST_INT) is
766 do_SUBST_INT (int *into
, int newval
)
771 if (oldval
== newval
)
775 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
777 buf
= XNEW (struct undo
);
779 buf
->kind
= UNDO_INT
;
781 buf
->old_contents
.i
= oldval
;
784 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
787 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
789 /* Similar to SUBST, but just substitute the mode. This is used when
790 changing the mode of a pseudo-register, so that any other
791 references to the entry in the regno_reg_rtx array will change as
795 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
798 machine_mode oldval
= GET_MODE (*into
);
800 if (oldval
== newval
)
804 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
806 buf
= XNEW (struct undo
);
808 buf
->kind
= UNDO_MODE
;
810 buf
->old_contents
.m
= oldval
;
811 adjust_reg_mode (*into
, newval
);
813 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
816 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
818 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
821 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
824 struct insn_link
* oldval
= *into
;
826 if (oldval
== newval
)
830 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
832 buf
= XNEW (struct undo
);
834 buf
->kind
= UNDO_LINKS
;
836 buf
->old_contents
.l
= oldval
;
839 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
842 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
844 /* Subroutine of try_combine. Determine whether the replacement patterns
845 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
846 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
847 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
848 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
849 of all the instructions can be estimated and the replacements are more
850 expensive than the original sequence. */
853 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
854 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
856 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
857 int new_i2_cost
, new_i3_cost
;
858 int old_cost
, new_cost
;
860 /* Lookup the original insn_costs. */
861 i2_cost
= INSN_COST (i2
);
862 i3_cost
= INSN_COST (i3
);
866 i1_cost
= INSN_COST (i1
);
869 i0_cost
= INSN_COST (i0
);
870 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
871 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
875 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
876 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
882 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
883 i1_cost
= i0_cost
= 0;
886 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
888 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
892 /* Calculate the replacement insn_costs. */
893 rtx tmp
= PATTERN (i3
);
894 PATTERN (i3
) = newpat
;
895 int tmpi
= INSN_CODE (i3
);
897 new_i3_cost
= insn_cost (i3
, optimize_this_for_speed_p
);
899 INSN_CODE (i3
) = tmpi
;
903 PATTERN (i2
) = newi2pat
;
904 tmpi
= INSN_CODE (i2
);
906 new_i2_cost
= insn_cost (i2
, optimize_this_for_speed_p
);
908 INSN_CODE (i2
) = tmpi
;
909 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
910 ? new_i2_cost
+ new_i3_cost
: 0;
914 new_cost
= new_i3_cost
;
918 if (undobuf
.other_insn
)
920 int old_other_cost
, new_other_cost
;
922 old_other_cost
= INSN_COST (undobuf
.other_insn
);
923 tmp
= PATTERN (undobuf
.other_insn
);
924 PATTERN (undobuf
.other_insn
) = newotherpat
;
925 tmpi
= INSN_CODE (undobuf
.other_insn
);
926 INSN_CODE (undobuf
.other_insn
) = -1;
927 new_other_cost
= insn_cost (undobuf
.other_insn
,
928 optimize_this_for_speed_p
);
929 PATTERN (undobuf
.other_insn
) = tmp
;
930 INSN_CODE (undobuf
.other_insn
) = tmpi
;
931 if (old_other_cost
> 0 && new_other_cost
> 0)
933 old_cost
+= old_other_cost
;
934 new_cost
+= new_other_cost
;
940 /* Disallow this combination if both new_cost and old_cost are greater than
941 zero, and new_cost is greater than old cost. */
942 int reject
= old_cost
> 0 && new_cost
> old_cost
;
946 fprintf (dump_file
, "%s combination of insns ",
947 reject
? "rejecting" : "allowing");
949 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
950 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
951 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
952 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
954 fprintf (dump_file
, "original costs ");
956 fprintf (dump_file
, "%d + ", i0_cost
);
957 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
958 fprintf (dump_file
, "%d + ", i1_cost
);
959 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
962 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
963 new_i2_cost
, new_i3_cost
, new_cost
);
965 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
971 /* Update the uid_insn_cost array with the replacement costs. */
972 INSN_COST (i2
) = new_i2_cost
;
973 INSN_COST (i3
) = new_i3_cost
;
985 /* Delete any insns that copy a register to itself.
986 Return true if the CFG was changed. */
989 delete_noop_moves (void)
991 rtx_insn
*insn
, *next
;
994 bool edges_deleted
= false;
996 FOR_EACH_BB_FN (bb
, cfun
)
998 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
1000 next
= NEXT_INSN (insn
);
1001 if (INSN_P (insn
) && noop_move_p (insn
))
1004 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
1006 edges_deleted
|= delete_insn_and_edges (insn
);
1011 return edges_deleted
;
1015 /* Return false if we do not want to (or cannot) combine DEF. */
1017 can_combine_def_p (df_ref def
)
1019 /* Do not consider if it is pre/post modification in MEM. */
1020 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1023 unsigned int regno
= DF_REF_REGNO (def
);
1025 /* Do not combine frame pointer adjustments. */
1026 if ((regno
== FRAME_POINTER_REGNUM
1027 && (!reload_completed
|| frame_pointer_needed
))
1028 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1029 && regno
== HARD_FRAME_POINTER_REGNUM
1030 && (!reload_completed
|| frame_pointer_needed
))
1031 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1032 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1038 /* Return false if we do not want to (or cannot) combine USE. */
1040 can_combine_use_p (df_ref use
)
1042 /* Do not consider the usage of the stack pointer by function call. */
1043 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1049 /* Fill in log links field for all insns. */
1052 create_log_links (void)
1055 rtx_insn
**next_use
;
1059 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1061 /* Pass through each block from the end, recording the uses of each
1062 register and establishing log links when def is encountered.
1063 Note that we do not clear next_use array in order to save time,
1064 so we have to test whether the use is in the same basic block as def.
1066 There are a few cases below when we do not consider the definition or
1067 usage -- these are taken from original flow.c did. Don't ask me why it is
1068 done this way; I don't know and if it works, I don't want to know. */
1070 FOR_EACH_BB_FN (bb
, cfun
)
1072 FOR_BB_INSNS_REVERSE (bb
, insn
)
1074 if (!NONDEBUG_INSN_P (insn
))
1077 /* Log links are created only once. */
1078 gcc_assert (!LOG_LINKS (insn
));
1080 FOR_EACH_INSN_DEF (def
, insn
)
1082 unsigned int regno
= DF_REF_REGNO (def
);
1085 if (!next_use
[regno
])
1088 if (!can_combine_def_p (def
))
1091 use_insn
= next_use
[regno
];
1092 next_use
[regno
] = NULL
;
1094 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1099 We don't build a LOG_LINK for hard registers contained
1100 in ASM_OPERANDs. If these registers get replaced,
1101 we might wind up changing the semantics of the insn,
1102 even if reload can make what appear to be valid
1103 assignments later. */
1104 if (regno
< FIRST_PSEUDO_REGISTER
1105 && asm_noperands (PATTERN (use_insn
)) >= 0)
1108 /* Don't add duplicate links between instructions. */
1109 struct insn_link
*links
;
1110 FOR_EACH_LOG_LINK (links
, use_insn
)
1111 if (insn
== links
->insn
&& regno
== links
->regno
)
1115 LOG_LINKS (use_insn
)
1116 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1119 FOR_EACH_INSN_USE (use
, insn
)
1120 if (can_combine_use_p (use
))
1121 next_use
[DF_REF_REGNO (use
)] = insn
;
1128 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1129 true if we found a LOG_LINK that proves that A feeds B. This only works
1130 if there are no instructions between A and B which could have a link
1131 depending on A, since in that case we would not record a link for B.
1132 We also check the implicit dependency created by a cc0 setter/user
1136 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1138 struct insn_link
*links
;
1139 FOR_EACH_LOG_LINK (links
, b
)
1140 if (links
->insn
== a
)
1142 if (HAVE_cc0
&& sets_cc0_p (a
))
1147 /* Main entry point for combiner. F is the first insn of the function.
1148 NREGS is the first unused pseudo-reg number.
1150 Return nonzero if the CFG was changed (e.g. if the combiner has
1151 turned an indirect jump instruction into a direct jump). */
1153 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1155 rtx_insn
*insn
, *next
;
1157 struct insn_link
*links
, *nextlinks
;
1159 basic_block last_bb
;
1161 int new_direct_jump_p
= 0;
1163 for (first
= f
; first
&& !NONDEBUG_INSN_P (first
); )
1164 first
= NEXT_INSN (first
);
1168 combine_attempts
= 0;
1171 combine_successes
= 0;
1173 rtl_hooks
= combine_rtl_hooks
;
1175 reg_stat
.safe_grow_cleared (nregs
, true);
1177 init_recog_no_volatile ();
1179 /* Allocate array for insn info. */
1180 max_uid_known
= get_max_uid ();
1181 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1182 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1183 gcc_obstack_init (&insn_link_obstack
);
1185 nonzero_bits_mode
= int_mode_for_size (HOST_BITS_PER_WIDE_INT
, 0).require ();
1187 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1188 problems when, for example, we have j <<= 1 in a loop. */
1190 nonzero_sign_valid
= 0;
1191 label_tick
= label_tick_ebb_start
= 1;
1193 /* Scan all SETs and see if we can deduce anything about what
1194 bits are known to be zero for some registers and how many copies
1195 of the sign bit are known to exist for those registers.
1197 Also set any known values so that we can use it while searching
1198 for what bits are known to be set. */
1200 setup_incoming_promotions (first
);
1201 /* Allow the entry block and the first block to fall into the same EBB.
1202 Conceptually the incoming promotions are assigned to the entry block. */
1203 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1205 create_log_links ();
1206 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1208 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1213 if (!single_pred_p (this_basic_block
)
1214 || single_pred (this_basic_block
) != last_bb
)
1215 label_tick_ebb_start
= label_tick
;
1216 last_bb
= this_basic_block
;
1218 FOR_BB_INSNS (this_basic_block
, insn
)
1219 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1223 subst_low_luid
= DF_INSN_LUID (insn
);
1226 note_stores (insn
, set_nonzero_bits_and_sign_copies
, insn
);
1227 record_dead_and_set_regs (insn
);
1230 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1231 if (REG_NOTE_KIND (links
) == REG_INC
)
1232 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1235 /* Record the current insn_cost of this instruction. */
1236 INSN_COST (insn
) = insn_cost (insn
, optimize_this_for_speed_p
);
1239 fprintf (dump_file
, "insn_cost %d for ", INSN_COST (insn
));
1240 dump_insn_slim (dump_file
, insn
);
1245 nonzero_sign_valid
= 1;
1247 /* Now scan all the insns in forward order. */
1248 label_tick
= label_tick_ebb_start
= 1;
1250 setup_incoming_promotions (first
);
1251 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1252 int max_combine
= param_max_combine_insns
;
1254 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1256 rtx_insn
*last_combined_insn
= NULL
;
1258 /* Ignore instruction combination in basic blocks that are going to
1259 be removed as unreachable anyway. See PR82386. */
1260 if (EDGE_COUNT (this_basic_block
->preds
) == 0)
1263 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1268 if (!single_pred_p (this_basic_block
)
1269 || single_pred (this_basic_block
) != last_bb
)
1270 label_tick_ebb_start
= label_tick
;
1271 last_bb
= this_basic_block
;
1273 rtl_profile_for_bb (this_basic_block
);
1274 for (insn
= BB_HEAD (this_basic_block
);
1275 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1276 insn
= next
? next
: NEXT_INSN (insn
))
1279 if (!NONDEBUG_INSN_P (insn
))
1282 while (last_combined_insn
1283 && (!NONDEBUG_INSN_P (last_combined_insn
)
1284 || last_combined_insn
->deleted ()))
1285 last_combined_insn
= PREV_INSN (last_combined_insn
);
1286 if (last_combined_insn
== NULL_RTX
1287 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1288 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1289 last_combined_insn
= insn
;
1291 /* See if we know about function return values before this
1292 insn based upon SUBREG flags. */
1293 check_promoted_subreg (insn
, PATTERN (insn
));
1295 /* See if we can find hardregs and subreg of pseudos in
1296 narrower modes. This could help turning TRUNCATEs
1298 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1300 /* Try this insn with each insn it links back to. */
1302 FOR_EACH_LOG_LINK (links
, insn
)
1303 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1304 NULL
, &new_direct_jump_p
,
1305 last_combined_insn
)) != 0)
1307 statistics_counter_event (cfun
, "two-insn combine", 1);
1311 /* Try each sequence of three linked insns ending with this one. */
1313 if (max_combine
>= 3)
1314 FOR_EACH_LOG_LINK (links
, insn
)
1316 rtx_insn
*link
= links
->insn
;
1318 /* If the linked insn has been replaced by a note, then there
1319 is no point in pursuing this chain any further. */
1323 FOR_EACH_LOG_LINK (nextlinks
, link
)
1324 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1325 NULL
, &new_direct_jump_p
,
1326 last_combined_insn
)) != 0)
1328 statistics_counter_event (cfun
, "three-insn combine", 1);
1333 /* Try to combine a jump insn that uses CC0
1334 with a preceding insn that sets CC0, and maybe with its
1335 logical predecessor as well.
1336 This is how we make decrement-and-branch insns.
1337 We need this special code because data flow connections
1338 via CC0 do not get entered in LOG_LINKS. */
1342 && (prev
= prev_nonnote_insn (insn
)) != 0
1343 && NONJUMP_INSN_P (prev
)
1344 && sets_cc0_p (PATTERN (prev
)))
1346 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1348 last_combined_insn
)) != 0)
1351 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1352 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1353 NULL
, &new_direct_jump_p
,
1354 last_combined_insn
)) != 0)
1358 /* Do the same for an insn that explicitly references CC0. */
1359 if (HAVE_cc0
&& NONJUMP_INSN_P (insn
)
1360 && (prev
= prev_nonnote_insn (insn
)) != 0
1361 && NONJUMP_INSN_P (prev
)
1362 && sets_cc0_p (PATTERN (prev
))
1363 && GET_CODE (PATTERN (insn
)) == SET
1364 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1366 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1368 last_combined_insn
)) != 0)
1371 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1372 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1373 NULL
, &new_direct_jump_p
,
1374 last_combined_insn
)) != 0)
1378 /* Finally, see if any of the insns that this insn links to
1379 explicitly references CC0. If so, try this insn, that insn,
1380 and its predecessor if it sets CC0. */
1383 FOR_EACH_LOG_LINK (links
, insn
)
1384 if (NONJUMP_INSN_P (links
->insn
)
1385 && GET_CODE (PATTERN (links
->insn
)) == SET
1386 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1387 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1388 && NONJUMP_INSN_P (prev
)
1389 && sets_cc0_p (PATTERN (prev
))
1390 && (next
= try_combine (insn
, links
->insn
,
1391 prev
, NULL
, &new_direct_jump_p
,
1392 last_combined_insn
)) != 0)
1396 /* Try combining an insn with two different insns whose results it
1398 if (max_combine
>= 3)
1399 FOR_EACH_LOG_LINK (links
, insn
)
1400 for (nextlinks
= links
->next
; nextlinks
;
1401 nextlinks
= nextlinks
->next
)
1402 if ((next
= try_combine (insn
, links
->insn
,
1403 nextlinks
->insn
, NULL
,
1405 last_combined_insn
)) != 0)
1408 statistics_counter_event (cfun
, "three-insn combine", 1);
1412 /* Try four-instruction combinations. */
1413 if (max_combine
>= 4)
1414 FOR_EACH_LOG_LINK (links
, insn
)
1416 struct insn_link
*next1
;
1417 rtx_insn
*link
= links
->insn
;
1419 /* If the linked insn has been replaced by a note, then there
1420 is no point in pursuing this chain any further. */
1424 FOR_EACH_LOG_LINK (next1
, link
)
1426 rtx_insn
*link1
= next1
->insn
;
1429 /* I0 -> I1 -> I2 -> I3. */
1430 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1431 if ((next
= try_combine (insn
, link
, link1
,
1434 last_combined_insn
)) != 0)
1436 statistics_counter_event (cfun
, "four-insn combine", 1);
1439 /* I0, I1 -> I2, I2 -> I3. */
1440 for (nextlinks
= next1
->next
; nextlinks
;
1441 nextlinks
= nextlinks
->next
)
1442 if ((next
= try_combine (insn
, link
, link1
,
1445 last_combined_insn
)) != 0)
1447 statistics_counter_event (cfun
, "four-insn combine", 1);
1452 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1454 rtx_insn
*link1
= next1
->insn
;
1457 /* I0 -> I2; I1, I2 -> I3. */
1458 FOR_EACH_LOG_LINK (nextlinks
, link
)
1459 if ((next
= try_combine (insn
, link
, link1
,
1462 last_combined_insn
)) != 0)
1464 statistics_counter_event (cfun
, "four-insn combine", 1);
1467 /* I0 -> I1; I1, I2 -> I3. */
1468 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1469 if ((next
= try_combine (insn
, link
, link1
,
1472 last_combined_insn
)) != 0)
1474 statistics_counter_event (cfun
, "four-insn combine", 1);
1480 /* Try this insn with each REG_EQUAL note it links back to. */
1481 FOR_EACH_LOG_LINK (links
, insn
)
1484 rtx_insn
*temp
= links
->insn
;
1485 if ((set
= single_set (temp
)) != 0
1486 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1487 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1488 && ! side_effects_p (SET_SRC (set
))
1489 /* Avoid using a register that may already been marked
1490 dead by an earlier instruction. */
1491 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1492 && (GET_MODE (note
) == VOIDmode
1493 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1494 : (GET_MODE (SET_DEST (set
)) == GET_MODE (note
)
1495 && (GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1496 || (GET_MODE (XEXP (SET_DEST (set
), 0))
1497 == GET_MODE (note
))))))
1499 /* Temporarily replace the set's source with the
1500 contents of the REG_EQUAL note. The insn will
1501 be deleted or recognized by try_combine. */
1502 rtx orig_src
= SET_SRC (set
);
1503 rtx orig_dest
= SET_DEST (set
);
1504 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
)
1505 SET_DEST (set
) = XEXP (SET_DEST (set
), 0);
1506 SET_SRC (set
) = note
;
1508 i2mod_old_rhs
= copy_rtx (orig_src
);
1509 i2mod_new_rhs
= copy_rtx (note
);
1510 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1512 last_combined_insn
);
1516 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1519 SET_SRC (set
) = orig_src
;
1520 SET_DEST (set
) = orig_dest
;
1525 record_dead_and_set_regs (insn
);
1532 default_rtl_profile ();
1534 new_direct_jump_p
|= purge_all_dead_edges ();
1535 new_direct_jump_p
|= delete_noop_moves ();
1538 obstack_free (&insn_link_obstack
, NULL
);
1539 free (uid_log_links
);
1540 free (uid_insn_cost
);
1541 reg_stat
.release ();
1544 struct undo
*undo
, *next
;
1545 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1553 total_attempts
+= combine_attempts
;
1554 total_merges
+= combine_merges
;
1555 total_extras
+= combine_extras
;
1556 total_successes
+= combine_successes
;
1558 nonzero_sign_valid
= 0;
1559 rtl_hooks
= general_rtl_hooks
;
1561 /* Make recognizer allow volatile MEMs again. */
1564 return new_direct_jump_p
;
1567 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1570 init_reg_last (void)
1575 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1576 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1579 /* Set up any promoted values for incoming argument registers. */
1582 setup_incoming_promotions (rtx_insn
*first
)
1585 bool strictly_local
= false;
1587 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1588 arg
= DECL_CHAIN (arg
))
1590 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1592 machine_mode mode1
, mode2
, mode3
, mode4
;
1594 /* Only continue if the incoming argument is in a register. */
1598 /* Determine, if possible, whether all call sites of the current
1599 function lie within the current compilation unit. (This does
1600 take into account the exporting of a function via taking its
1601 address, and so forth.) */
1603 = cgraph_node::local_info_node (current_function_decl
)->local
;
1605 /* The mode and signedness of the argument before any promotions happen
1606 (equal to the mode of the pseudo holding it at that stage). */
1607 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1608 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1610 /* The mode and signedness of the argument after any source language and
1611 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1612 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1613 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1615 /* The mode and signedness of the argument as it is actually passed,
1616 see assign_parm_setup_reg in function.c. */
1617 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1618 TREE_TYPE (cfun
->decl
), 0);
1620 /* The mode of the register in which the argument is being passed. */
1621 mode4
= GET_MODE (reg
);
1623 /* Eliminate sign extensions in the callee when:
1624 (a) A mode promotion has occurred; */
1627 /* (b) The mode of the register is the same as the mode of
1628 the argument as it is passed; */
1631 /* (c) There's no language level extension; */
1634 /* (c.1) All callers are from the current compilation unit. If that's
1635 the case we don't have to rely on an ABI, we only have to know
1636 what we're generating right now, and we know that we will do the
1637 mode1 to mode2 promotion with the given sign. */
1638 else if (!strictly_local
)
1640 /* (c.2) The combination of the two promotions is useful. This is
1641 true when the signs match, or if the first promotion is unsigned.
1642 In the later case, (sign_extend (zero_extend x)) is the same as
1643 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1649 /* Record that the value was promoted from mode1 to mode3,
1650 so that any sign extension at the head of the current
1651 function may be eliminated. */
1652 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1653 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1654 record_value_for_reg (reg
, first
, x
);
1658 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1659 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1660 because some machines (maybe most) will actually do the sign-extension and
1661 this is the conservative approach.
1663 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1667 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1669 scalar_int_mode int_mode
;
1670 if (CONST_INT_P (src
)
1671 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1672 && GET_MODE_PRECISION (int_mode
) < prec
1674 && val_signbit_known_set_p (int_mode
, INTVAL (src
)))
1675 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (int_mode
));
1680 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1684 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1687 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1688 unsigned HOST_WIDE_INT bits
= 0;
1689 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1690 unsigned int num
= 0;
1693 reg_equal
= XEXP (reg_equal_note
, 0);
1695 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
1697 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1699 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1702 /* Don't call nonzero_bits if it cannot change anything. */
1703 if (rsp
->nonzero_bits
!= HOST_WIDE_INT_M1U
)
1705 machine_mode mode
= GET_MODE (x
);
1706 if (GET_MODE_CLASS (mode
) == MODE_INT
1707 && HWI_COMPUTABLE_MODE_P (mode
))
1708 mode
= nonzero_bits_mode
;
1709 bits
= nonzero_bits (src
, mode
);
1710 if (reg_equal
&& bits
)
1711 bits
&= nonzero_bits (reg_equal
, mode
);
1712 rsp
->nonzero_bits
|= bits
;
1715 /* Don't call num_sign_bit_copies if it cannot change anything. */
1716 if (rsp
->sign_bit_copies
!= 1)
1718 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1719 if (reg_equal
&& maybe_ne (num
, GET_MODE_PRECISION (GET_MODE (x
))))
1721 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1722 if (num
== 0 || numeq
> num
)
1725 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1726 rsp
->sign_bit_copies
= num
;
1730 /* Called via note_stores. If X is a pseudo that is narrower than
1731 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1733 If we are setting only a portion of X and we can't figure out what
1734 portion, assume all bits will be used since we don't know what will
1737 Similarly, set how many bits of X are known to be copies of the sign bit
1738 at all locations in the function. This is the smallest number implied
1742 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1744 rtx_insn
*insn
= (rtx_insn
*) data
;
1745 scalar_int_mode mode
;
1748 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1749 /* If this register is undefined at the start of the file, we can't
1750 say what its contents were. */
1751 && ! REGNO_REG_SET_P
1752 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1753 && is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
)
1754 && HWI_COMPUTABLE_MODE_P (mode
))
1756 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1758 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1760 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1761 rsp
->sign_bit_copies
= 1;
1765 /* If this register is being initialized using itself, and the
1766 register is uninitialized in this basic block, and there are
1767 no LOG_LINKS which set the register, then part of the
1768 register is uninitialized. In that case we can't assume
1769 anything about the number of nonzero bits.
1771 ??? We could do better if we checked this in
1772 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1773 could avoid making assumptions about the insn which initially
1774 sets the register, while still using the information in other
1775 insns. We would have to be careful to check every insn
1776 involved in the combination. */
1779 && reg_referenced_p (x
, PATTERN (insn
))
1780 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1783 struct insn_link
*link
;
1785 FOR_EACH_LOG_LINK (link
, insn
)
1786 if (dead_or_set_p (link
->insn
, x
))
1790 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1791 rsp
->sign_bit_copies
= 1;
1796 /* If this is a complex assignment, see if we can convert it into a
1797 simple assignment. */
1798 set
= expand_field_assignment (set
);
1800 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1801 set what we know about X. */
1803 if (SET_DEST (set
) == x
1804 || (paradoxical_subreg_p (SET_DEST (set
))
1805 && SUBREG_REG (SET_DEST (set
)) == x
))
1806 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1809 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1810 rsp
->sign_bit_copies
= 1;
1815 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1816 optionally insns that were previously combined into I3 or that will be
1817 combined into the merger of INSN and I3. The order is PRED, PRED2,
1818 INSN, SUCC, SUCC2, I3.
1820 Return 0 if the combination is not allowed for any reason.
1822 If the combination is allowed, *PDEST will be set to the single
1823 destination of INSN and *PSRC to the single source, and this function
1827 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1828 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1829 rtx
*pdest
, rtx
*psrc
)
1836 bool all_adjacent
= true;
1837 int (*is_volatile_p
) (const_rtx
);
1843 if (next_active_insn (succ2
) != i3
)
1844 all_adjacent
= false;
1845 if (next_active_insn (succ
) != succ2
)
1846 all_adjacent
= false;
1848 else if (next_active_insn (succ
) != i3
)
1849 all_adjacent
= false;
1850 if (next_active_insn (insn
) != succ
)
1851 all_adjacent
= false;
1853 else if (next_active_insn (insn
) != i3
)
1854 all_adjacent
= false;
1856 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1857 or a PARALLEL consisting of such a SET and CLOBBERs.
1859 If INSN has CLOBBER parallel parts, ignore them for our processing.
1860 By definition, these happen during the execution of the insn. When it
1861 is merged with another insn, all bets are off. If they are, in fact,
1862 needed and aren't also supplied in I3, they may be added by
1863 recog_for_combine. Otherwise, it won't match.
1865 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1868 Get the source and destination of INSN. If more than one, can't
1871 if (GET_CODE (PATTERN (insn
)) == SET
)
1872 set
= PATTERN (insn
);
1873 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1874 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1876 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1878 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1880 switch (GET_CODE (elt
))
1882 /* This is important to combine floating point insns
1883 for the SH4 port. */
1885 /* Combining an isolated USE doesn't make sense.
1886 We depend here on combinable_i3pat to reject them. */
1887 /* The code below this loop only verifies that the inputs of
1888 the SET in INSN do not change. We call reg_set_between_p
1889 to verify that the REG in the USE does not change between
1891 If the USE in INSN was for a pseudo register, the matching
1892 insn pattern will likely match any register; combining this
1893 with any other USE would only be safe if we knew that the
1894 used registers have identical values, or if there was
1895 something to tell them apart, e.g. different modes. For
1896 now, we forgo such complicated tests and simply disallow
1897 combining of USES of pseudo registers with any other USE. */
1898 if (REG_P (XEXP (elt
, 0))
1899 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1901 rtx i3pat
= PATTERN (i3
);
1902 int i
= XVECLEN (i3pat
, 0) - 1;
1903 unsigned int regno
= REGNO (XEXP (elt
, 0));
1907 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1909 if (GET_CODE (i3elt
) == USE
1910 && REG_P (XEXP (i3elt
, 0))
1911 && (REGNO (XEXP (i3elt
, 0)) == regno
1912 ? reg_set_between_p (XEXP (elt
, 0),
1913 PREV_INSN (insn
), i3
)
1914 : regno
>= FIRST_PSEUDO_REGISTER
))
1921 /* We can ignore CLOBBERs. */
1926 /* Ignore SETs whose result isn't used but not those that
1927 have side-effects. */
1928 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1929 && insn_nothrow_p (insn
)
1930 && !side_effects_p (elt
))
1933 /* If we have already found a SET, this is a second one and
1934 so we cannot combine with this insn. */
1942 /* Anything else means we can't combine. */
1948 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1949 so don't do anything with it. */
1950 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1959 /* The simplification in expand_field_assignment may call back to
1960 get_last_value, so set safe guard here. */
1961 subst_low_luid
= DF_INSN_LUID (insn
);
1963 set
= expand_field_assignment (set
);
1964 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1966 /* Do not eliminate user-specified register if it is in an
1967 asm input because we may break the register asm usage defined
1968 in GCC manual if allow to do so.
1969 Be aware that this may cover more cases than we expect but this
1970 should be harmless. */
1971 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1972 && extract_asm_operands (PATTERN (i3
)))
1975 /* Don't eliminate a store in the stack pointer. */
1976 if (dest
== stack_pointer_rtx
1977 /* Don't combine with an insn that sets a register to itself if it has
1978 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1979 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1980 /* Can't merge an ASM_OPERANDS. */
1981 || GET_CODE (src
) == ASM_OPERANDS
1982 /* Can't merge a function call. */
1983 || GET_CODE (src
) == CALL
1984 /* Don't eliminate a function call argument. */
1986 && (find_reg_fusage (i3
, USE
, dest
)
1988 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1989 && global_regs
[REGNO (dest
)])))
1990 /* Don't substitute into an incremented register. */
1991 || FIND_REG_INC_NOTE (i3
, dest
)
1992 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1993 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1994 /* Don't substitute into a non-local goto, this confuses CFG. */
1995 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1996 /* Make sure that DEST is not used after INSN but before SUCC, or
1997 after SUCC and before SUCC2, or after SUCC2 but before I3. */
2000 && (reg_used_between_p (dest
, succ2
, i3
)
2001 || reg_used_between_p (dest
, succ
, succ2
)))
2002 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))
2003 || (!succ2
&& !succ
&& reg_used_between_p (dest
, insn
, i3
))
2005 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
2006 that case SUCC is not in the insn stream, so use SUCC2
2007 instead for this test. */
2008 && reg_used_between_p (dest
, insn
,
2010 && INSN_UID (succ
) == INSN_UID (succ2
)
2012 /* Make sure that the value that is to be substituted for the register
2013 does not use any registers whose values alter in between. However,
2014 If the insns are adjacent, a use can't cross a set even though we
2015 think it might (this can happen for a sequence of insns each setting
2016 the same destination; last_set of that register might point to
2017 a NOTE). If INSN has a REG_EQUIV note, the register is always
2018 equivalent to the memory so the substitution is valid even if there
2019 are intervening stores. Also, don't move a volatile asm or
2020 UNSPEC_VOLATILE across any other insns. */
2023 || ! find_reg_note (insn
, REG_EQUIV
, src
))
2024 && modified_between_p (src
, insn
, i3
))
2025 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
2026 || GET_CODE (src
) == UNSPEC_VOLATILE
))
2027 /* Don't combine across a CALL_INSN, because that would possibly
2028 change whether the life span of some REGs crosses calls or not,
2029 and it is a pain to update that information.
2030 Exception: if source is a constant, moving it later can't hurt.
2031 Accept that as a special case. */
2032 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
2035 /* DEST must either be a REG or CC0. */
2038 /* If register alignment is being enforced for multi-word items in all
2039 cases except for parameters, it is possible to have a register copy
2040 insn referencing a hard register that is not allowed to contain the
2041 mode being copied and which would not be valid as an operand of most
2042 insns. Eliminate this problem by not combining with such an insn.
2044 Also, on some machines we don't want to extend the life of a hard
2048 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
2049 && !targetm
.hard_regno_mode_ok (REGNO (dest
), GET_MODE (dest
)))
2050 /* Don't extend the life of a hard register unless it is
2051 user variable (if we have few registers) or it can't
2052 fit into the desired register (meaning something special
2054 Also avoid substituting a return register into I3, because
2055 reload can't handle a conflict with constraints of other
2057 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2058 && !targetm
.hard_regno_mode_ok (REGNO (src
),
2062 else if (GET_CODE (dest
) != CC0
)
2066 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2067 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2068 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2070 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2072 /* If the clobber represents an earlyclobber operand, we must not
2073 substitute an expression containing the clobbered register.
2074 As we do not analyze the constraint strings here, we have to
2075 make the conservative assumption. However, if the register is
2076 a fixed hard reg, the clobber cannot represent any operand;
2077 we leave it up to the machine description to either accept or
2078 reject use-and-clobber patterns. */
2080 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2081 || !fixed_regs
[REGNO (reg
)])
2082 if (reg_overlap_mentioned_p (reg
, src
))
2086 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2087 or not), reject, unless nothing volatile comes between it and I3 */
2089 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2091 /* Make sure neither succ nor succ2 contains a volatile reference. */
2092 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2094 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2096 /* We'll check insns between INSN and I3 below. */
2099 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2100 to be an explicit register variable, and was chosen for a reason. */
2102 if (GET_CODE (src
) == ASM_OPERANDS
2103 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2106 /* If INSN contains volatile references (specifically volatile MEMs),
2107 we cannot combine across any other volatile references.
2108 Even if INSN doesn't contain volatile references, any intervening
2109 volatile insn might affect machine state. */
2111 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2115 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2116 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2119 /* If INSN contains an autoincrement or autodecrement, make sure that
2120 register is not used between there and I3, and not already used in
2121 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2122 Also insist that I3 not be a jump if using LRA; if it were one
2123 and the incremented register were spilled, we would lose.
2124 Reload handles this correctly. */
2127 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2128 if (REG_NOTE_KIND (link
) == REG_INC
2129 && ((JUMP_P (i3
) && targetm
.lra_p ())
2130 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2131 || (pred
!= NULL_RTX
2132 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2133 || (pred2
!= NULL_RTX
2134 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2135 || (succ
!= NULL_RTX
2136 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2137 || (succ2
!= NULL_RTX
2138 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2139 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2142 /* Don't combine an insn that follows a CC0-setting insn.
2143 An insn that uses CC0 must not be separated from the one that sets it.
2144 We do, however, allow I2 to follow a CC0-setting insn if that insn
2145 is passed as I1; in that case it will be deleted also.
2146 We also allow combining in this case if all the insns are adjacent
2147 because that would leave the two CC0 insns adjacent as well.
2148 It would be more logical to test whether CC0 occurs inside I1 or I2,
2149 but that would be much slower, and this ought to be equivalent. */
2153 p
= prev_nonnote_insn (insn
);
2154 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2159 /* If we get here, we have passed all the tests and the combination is
2168 /* LOC is the location within I3 that contains its pattern or the component
2169 of a PARALLEL of the pattern. We validate that it is valid for combining.
2171 One problem is if I3 modifies its output, as opposed to replacing it
2172 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2173 doing so would produce an insn that is not equivalent to the original insns.
2177 (set (reg:DI 101) (reg:DI 100))
2178 (set (subreg:SI (reg:DI 101) 0) <foo>)
2180 This is NOT equivalent to:
2182 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2183 (set (reg:DI 101) (reg:DI 100))])
2185 Not only does this modify 100 (in which case it might still be valid
2186 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2188 We can also run into a problem if I2 sets a register that I1
2189 uses and I1 gets directly substituted into I3 (not via I2). In that
2190 case, we would be getting the wrong value of I2DEST into I3, so we
2191 must reject the combination. This case occurs when I2 and I1 both
2192 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2193 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2194 of a SET must prevent combination from occurring. The same situation
2195 can occur for I0, in which case I0_NOT_IN_SRC is set.
2197 Before doing the above check, we first try to expand a field assignment
2198 into a set of logical operations.
2200 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2201 we place a register that is both set and used within I3. If more than one
2202 such register is detected, we fail.
2204 Return 1 if the combination is valid, zero otherwise. */
2207 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2208 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2212 if (GET_CODE (x
) == SET
)
2215 rtx dest
= SET_DEST (set
);
2216 rtx src
= SET_SRC (set
);
2217 rtx inner_dest
= dest
;
2220 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2221 || GET_CODE (inner_dest
) == SUBREG
2222 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2223 inner_dest
= XEXP (inner_dest
, 0);
2225 /* Check for the case where I3 modifies its output, as discussed
2226 above. We don't want to prevent pseudos from being combined
2227 into the address of a MEM, so only prevent the combination if
2228 i1 or i2 set the same MEM. */
2229 if ((inner_dest
!= dest
&&
2230 (!MEM_P (inner_dest
)
2231 || rtx_equal_p (i2dest
, inner_dest
)
2232 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2233 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2234 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2235 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2236 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2238 /* This is the same test done in can_combine_p except we can't test
2239 all_adjacent; we don't have to, since this instruction will stay
2240 in place, thus we are not considering increasing the lifetime of
2243 Also, if this insn sets a function argument, combining it with
2244 something that might need a spill could clobber a previous
2245 function argument; the all_adjacent test in can_combine_p also
2246 checks this; here, we do a more specific test for this case. */
2248 || (REG_P (inner_dest
)
2249 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2250 && !targetm
.hard_regno_mode_ok (REGNO (inner_dest
),
2251 GET_MODE (inner_dest
)))
2252 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2253 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2256 /* If DEST is used in I3, it is being killed in this insn, so
2257 record that for later. We have to consider paradoxical
2258 subregs here, since they kill the whole register, but we
2259 ignore partial subregs, STRICT_LOW_PART, etc.
2260 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2261 STACK_POINTER_REGNUM, since these are always considered to be
2262 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2264 if (GET_CODE (subdest
) == SUBREG
&& !partial_subreg_p (subdest
))
2265 subdest
= SUBREG_REG (subdest
);
2268 && reg_referenced_p (subdest
, PATTERN (i3
))
2269 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2270 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2271 || REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
)
2272 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2273 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2274 || ! fixed_regs
[REGNO (subdest
)]))
2275 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2277 if (*pi3dest_killed
)
2280 *pi3dest_killed
= subdest
;
2284 else if (GET_CODE (x
) == PARALLEL
)
2288 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2289 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2290 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2297 /* Return 1 if X is an arithmetic expression that contains a multiplication
2298 and division. We don't count multiplications by powers of two here. */
2301 contains_muldiv (rtx x
)
2303 switch (GET_CODE (x
))
2305 case MOD
: case DIV
: case UMOD
: case UDIV
:
2309 return ! (CONST_INT_P (XEXP (x
, 1))
2310 && pow2p_hwi (UINTVAL (XEXP (x
, 1))));
2313 return contains_muldiv (XEXP (x
, 0))
2314 || contains_muldiv (XEXP (x
, 1));
2317 return contains_muldiv (XEXP (x
, 0));
2323 /* Determine whether INSN can be used in a combination. Return nonzero if
2324 not. This is used in try_combine to detect early some cases where we
2325 can't perform combinations. */
2328 cant_combine_insn_p (rtx_insn
*insn
)
2333 /* If this isn't really an insn, we can't do anything.
2334 This can occur when flow deletes an insn that it has merged into an
2335 auto-increment address. */
2336 if (!NONDEBUG_INSN_P (insn
))
2339 /* Never combine loads and stores involving hard regs that are likely
2340 to be spilled. The register allocator can usually handle such
2341 reg-reg moves by tying. If we allow the combiner to make
2342 substitutions of likely-spilled regs, reload might die.
2343 As an exception, we allow combinations involving fixed regs; these are
2344 not available to the register allocator so there's no risk involved. */
2346 set
= single_set (insn
);
2349 src
= SET_SRC (set
);
2350 dest
= SET_DEST (set
);
2351 if (GET_CODE (src
) == SUBREG
)
2352 src
= SUBREG_REG (src
);
2353 if (GET_CODE (dest
) == SUBREG
)
2354 dest
= SUBREG_REG (dest
);
2355 if (REG_P (src
) && REG_P (dest
)
2356 && ((HARD_REGISTER_P (src
)
2357 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2358 #ifdef LEAF_REGISTERS
2359 && ! LEAF_REGISTERS
[REGNO (src
)])
2363 || (HARD_REGISTER_P (dest
)
2364 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2365 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2371 struct likely_spilled_retval_info
2373 unsigned regno
, nregs
;
2377 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2378 hard registers that are known to be written to / clobbered in full. */
2380 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2382 struct likely_spilled_retval_info
*const info
=
2383 (struct likely_spilled_retval_info
*) data
;
2384 unsigned regno
, nregs
;
2387 if (!REG_P (XEXP (set
, 0)))
2390 if (regno
>= info
->regno
+ info
->nregs
)
2392 nregs
= REG_NREGS (x
);
2393 if (regno
+ nregs
<= info
->regno
)
2395 new_mask
= (2U << (nregs
- 1)) - 1;
2396 if (regno
< info
->regno
)
2397 new_mask
>>= info
->regno
- regno
;
2399 new_mask
<<= regno
- info
->regno
;
2400 info
->mask
&= ~new_mask
;
2403 /* Return nonzero iff part of the return value is live during INSN, and
2404 it is likely spilled. This can happen when more than one insn is needed
2405 to copy the return value, e.g. when we consider to combine into the
2406 second copy insn for a complex value. */
2409 likely_spilled_retval_p (rtx_insn
*insn
)
2411 rtx_insn
*use
= BB_END (this_basic_block
);
2414 unsigned regno
, nregs
;
2415 /* We assume here that no machine mode needs more than
2416 32 hard registers when the value overlaps with a register
2417 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2419 struct likely_spilled_retval_info info
;
2421 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2423 reg
= XEXP (PATTERN (use
), 0);
2424 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2426 regno
= REGNO (reg
);
2427 nregs
= REG_NREGS (reg
);
2430 mask
= (2U << (nregs
- 1)) - 1;
2432 /* Disregard parts of the return value that are set later. */
2436 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2438 note_stores (p
, likely_spilled_retval_1
, &info
);
2441 /* Check if any of the (probably) live return value registers is
2446 if ((mask
& 1 << nregs
)
2447 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2453 /* Adjust INSN after we made a change to its destination.
2455 Changing the destination can invalidate notes that say something about
2456 the results of the insn and a LOG_LINK pointing to the insn. */
2459 adjust_for_new_dest (rtx_insn
*insn
)
2461 /* For notes, be conservative and simply remove them. */
2462 remove_reg_equal_equiv_notes (insn
, true);
2464 /* The new insn will have a destination that was previously the destination
2465 of an insn just above it. Call distribute_links to make a LOG_LINK from
2466 the next use of that destination. */
2468 rtx set
= single_set (insn
);
2471 rtx reg
= SET_DEST (set
);
2473 while (GET_CODE (reg
) == ZERO_EXTRACT
2474 || GET_CODE (reg
) == STRICT_LOW_PART
2475 || GET_CODE (reg
) == SUBREG
)
2476 reg
= XEXP (reg
, 0);
2477 gcc_assert (REG_P (reg
));
2479 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2481 df_insn_rescan (insn
);
2484 /* Return TRUE if combine can reuse reg X in mode MODE.
2485 ADDED_SETS is nonzero if the original set is still required. */
2487 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2494 /* Don't change between modes with different underlying register sizes,
2495 since this could lead to invalid subregs. */
2496 if (maybe_ne (REGMODE_NATURAL_SIZE (mode
),
2497 REGMODE_NATURAL_SIZE (GET_MODE (x
))))
2501 /* Allow hard registers if the new mode is legal, and occupies no more
2502 registers than the old mode. */
2503 if (regno
< FIRST_PSEUDO_REGISTER
)
2504 return (targetm
.hard_regno_mode_ok (regno
, mode
)
2505 && REG_NREGS (x
) >= hard_regno_nregs (regno
, mode
));
2507 /* Or a pseudo that is only used once. */
2508 return (regno
< reg_n_sets_max
2509 && REG_N_SETS (regno
) == 1
2511 && !REG_USERVAR_P (x
));
2515 /* Check whether X, the destination of a set, refers to part of
2516 the register specified by REG. */
2519 reg_subword_p (rtx x
, rtx reg
)
2521 /* Check that reg is an integer mode register. */
2522 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2525 if (GET_CODE (x
) == STRICT_LOW_PART
2526 || GET_CODE (x
) == ZERO_EXTRACT
)
2529 return GET_CODE (x
) == SUBREG
2530 && SUBREG_REG (x
) == reg
2531 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2534 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2535 Note that the INSN should be deleted *after* removing dead edges, so
2536 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2537 but not for a (set (pc) (label_ref FOO)). */
2540 update_cfg_for_uncondjump (rtx_insn
*insn
)
2542 basic_block bb
= BLOCK_FOR_INSN (insn
);
2543 gcc_assert (BB_END (bb
) == insn
);
2545 purge_dead_edges (bb
);
2548 if (EDGE_COUNT (bb
->succs
) == 1)
2552 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2554 /* Remove barriers from the footer if there are any. */
2555 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2556 if (BARRIER_P (insn
))
2558 if (PREV_INSN (insn
))
2559 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2561 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2562 if (NEXT_INSN (insn
))
2563 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2565 else if (LABEL_P (insn
))
2570 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2571 by an arbitrary number of CLOBBERs. */
2573 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2575 if (GET_CODE (pat
) != PARALLEL
)
2578 int len
= XVECLEN (pat
, 0);
2583 for (i
= 0; i
< n
; i
++)
2584 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2585 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2587 for ( ; i
< len
; i
++)
2588 switch (GET_CODE (XVECEXP (pat
, 0, i
)))
2591 if (XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
2600 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2601 CLOBBERs), can be split into individual SETs in that order, without
2602 changing semantics. */
2604 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2606 if (!insn_nothrow_p (insn
))
2609 rtx pat
= PATTERN (insn
);
2612 for (i
= 0; i
< n
; i
++)
2614 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2617 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2619 for (j
= i
+ 1; j
< n
; j
++)
2620 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2627 /* Return whether X is just a single_set, with the source
2628 a general_operand. */
2630 is_just_move (rtx_insn
*x
)
2632 rtx set
= single_set (x
);
2636 return general_operand (SET_SRC (set
), VOIDmode
);
2639 /* Callback function to count autoincs. */
2642 count_auto_inc (rtx
, rtx
, rtx
, rtx
, rtx
, void *arg
)
2649 /* Try to combine the insns I0, I1 and I2 into I3.
2650 Here I0, I1 and I2 appear earlier than I3.
2651 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2654 If we are combining more than two insns and the resulting insn is not
2655 recognized, try splitting it into two insns. If that happens, I2 and I3
2656 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2657 Otherwise, I0, I1 and I2 are pseudo-deleted.
2659 Return 0 if the combination does not work. Then nothing is changed.
2660 If we did the combination, return the insn at which combine should
2663 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2664 new direct jump instruction.
2666 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2667 been I3 passed to an earlier try_combine within the same basic
2671 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2672 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2674 /* New patterns for I3 and I2, respectively. */
2675 rtx newpat
, newi2pat
= 0;
2676 rtvec newpat_vec_with_clobbers
= 0;
2677 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2678 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2680 int added_sets_0
, added_sets_1
, added_sets_2
;
2681 /* Total number of SETs to put into I3. */
2683 /* Nonzero if I2's or I1's body now appears in I3. */
2684 int i2_is_used
= 0, i1_is_used
= 0;
2685 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2686 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2687 /* Contains I3 if the destination of I3 is used in its source, which means
2688 that the old life of I3 is being killed. If that usage is placed into
2689 I2 and not in I3, a REG_DEAD note must be made. */
2690 rtx i3dest_killed
= 0;
2691 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2692 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2693 /* Copy of SET_SRC of I1 and I0, if needed. */
2694 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2695 /* Set if I2DEST was reused as a scratch register. */
2696 bool i2scratch
= false;
2697 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2698 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2699 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2700 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2701 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2702 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2703 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2704 /* Notes that must be added to REG_NOTES in I3 and I2. */
2705 rtx new_i3_notes
, new_i2_notes
;
2706 /* Notes that we substituted I3 into I2 instead of the normal case. */
2707 int i3_subst_into_i2
= 0;
2708 /* Notes that I1, I2 or I3 is a MULT operation. */
2712 int changed_i3_dest
= 0;
2713 bool i2_was_move
= false, i3_was_move
= false;
2717 rtx_insn
*temp_insn
;
2719 struct insn_link
*link
;
2721 rtx new_other_notes
;
2723 scalar_int_mode dest_mode
, temp_mode
;
2725 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2727 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2730 /* Only try four-insn combinations when there's high likelihood of
2731 success. Look for simple insns, such as loads of constants or
2732 binary operations involving a constant. */
2740 if (!flag_expensive_optimizations
)
2743 for (i
= 0; i
< 4; i
++)
2745 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2746 rtx set
= single_set (insn
);
2750 src
= SET_SRC (set
);
2751 if (CONSTANT_P (src
))
2756 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2758 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2759 || GET_CODE (src
) == LSHIFTRT
)
2763 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2764 are likely manipulating its value. Ideally we'll be able to combine
2765 all four insns into a bitfield insertion of some kind.
2767 Note the source in I0 might be inside a sign/zero extension and the
2768 memory modes in I0 and I3 might be different. So extract the address
2769 from the destination of I3 and search for it in the source of I0.
2771 In the event that there's a match but the source/dest do not actually
2772 refer to the same memory, the worst that happens is we try some
2773 combinations that we wouldn't have otherwise. */
2774 if ((set0
= single_set (i0
))
2775 /* Ensure the source of SET0 is a MEM, possibly buried inside
2777 && (GET_CODE (SET_SRC (set0
)) == MEM
2778 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2779 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2780 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2781 && (set3
= single_set (i3
))
2782 /* Ensure the destination of SET3 is a MEM. */
2783 && GET_CODE (SET_DEST (set3
)) == MEM
2784 /* Would it be better to extract the base address for the MEM
2785 in SET3 and look for that? I don't have cases where it matters
2786 but I could envision such cases. */
2787 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2790 if (ngood
< 2 && nshift
< 2)
2794 /* Exit early if one of the insns involved can't be used for
2797 || (i1
&& CALL_P (i1
))
2798 || (i0
&& CALL_P (i0
))
2799 || cant_combine_insn_p (i3
)
2800 || cant_combine_insn_p (i2
)
2801 || (i1
&& cant_combine_insn_p (i1
))
2802 || (i0
&& cant_combine_insn_p (i0
))
2803 || likely_spilled_retval_p (i3
))
2807 undobuf
.other_insn
= 0;
2809 /* Reset the hard register usage information. */
2810 CLEAR_HARD_REG_SET (newpat_used_regs
);
2812 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2815 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2816 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2818 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2819 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2821 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2822 INSN_UID (i2
), INSN_UID (i3
));
2825 dump_insn_slim (dump_file
, i0
);
2827 dump_insn_slim (dump_file
, i1
);
2828 dump_insn_slim (dump_file
, i2
);
2829 dump_insn_slim (dump_file
, i3
);
2832 /* If multiple insns feed into one of I2 or I3, they can be in any
2833 order. To simplify the code below, reorder them in sequence. */
2834 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2836 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2838 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2841 added_links_insn
= 0;
2842 added_notes_insn
= 0;
2844 /* First check for one important special case that the code below will
2845 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2846 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2847 we may be able to replace that destination with the destination of I3.
2848 This occurs in the common code where we compute both a quotient and
2849 remainder into a structure, in which case we want to do the computation
2850 directly into the structure to avoid register-register copies.
2852 Note that this case handles both multiple sets in I2 and also cases
2853 where I2 has a number of CLOBBERs inside the PARALLEL.
2855 We make very conservative checks below and only try to handle the
2856 most common cases of this. For example, we only handle the case
2857 where I2 and I3 are adjacent to avoid making difficult register
2860 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2861 && REG_P (SET_SRC (PATTERN (i3
)))
2862 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2863 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2864 && GET_CODE (PATTERN (i2
)) == PARALLEL
2865 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2866 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2867 below would need to check what is inside (and reg_overlap_mentioned_p
2868 doesn't support those codes anyway). Don't allow those destinations;
2869 the resulting insn isn't likely to be recognized anyway. */
2870 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2871 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2872 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2873 SET_DEST (PATTERN (i3
)))
2874 && next_active_insn (i2
) == i3
)
2876 rtx p2
= PATTERN (i2
);
2878 /* Make sure that the destination of I3,
2879 which we are going to substitute into one output of I2,
2880 is not used within another output of I2. We must avoid making this:
2881 (parallel [(set (mem (reg 69)) ...)
2882 (set (reg 69) ...)])
2883 which is not well-defined as to order of actions.
2884 (Besides, reload can't handle output reloads for this.)
2886 The problem can also happen if the dest of I3 is a memory ref,
2887 if another dest in I2 is an indirect memory ref.
2889 Neither can this PARALLEL be an asm. We do not allow combining
2890 that usually (see can_combine_p), so do not here either. */
2892 for (i
= 0; ok
&& i
< XVECLEN (p2
, 0); i
++)
2894 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2895 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2896 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2897 SET_DEST (XVECEXP (p2
, 0, i
))))
2899 else if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2900 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2905 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2906 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2907 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2912 subst_low_luid
= DF_INSN_LUID (i2
);
2914 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2915 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2916 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2917 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2919 /* Replace the dest in I2 with our dest and make the resulting
2920 insn the new pattern for I3. Then skip to where we validate
2921 the pattern. Everything was set up above. */
2922 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2924 i3_subst_into_i2
= 1;
2925 goto validate_replacement
;
2929 /* If I2 is setting a pseudo to a constant and I3 is setting some
2930 sub-part of it to another constant, merge them by making a new
2933 && (temp_expr
= single_set (i2
)) != 0
2934 && is_a
<scalar_int_mode
> (GET_MODE (SET_DEST (temp_expr
)), &temp_mode
)
2935 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2936 && GET_CODE (PATTERN (i3
)) == SET
2937 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2938 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2940 rtx dest
= SET_DEST (PATTERN (i3
));
2941 rtx temp_dest
= SET_DEST (temp_expr
);
2945 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2947 if (CONST_INT_P (XEXP (dest
, 1))
2948 && CONST_INT_P (XEXP (dest
, 2))
2949 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (dest
, 0)),
2952 width
= INTVAL (XEXP (dest
, 1));
2953 offset
= INTVAL (XEXP (dest
, 2));
2954 dest
= XEXP (dest
, 0);
2955 if (BITS_BIG_ENDIAN
)
2956 offset
= GET_MODE_PRECISION (dest_mode
) - width
- offset
;
2961 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2962 dest
= XEXP (dest
, 0);
2963 if (is_a
<scalar_int_mode
> (GET_MODE (dest
), &dest_mode
))
2965 width
= GET_MODE_PRECISION (dest_mode
);
2972 /* If this is the low part, we're done. */
2973 if (subreg_lowpart_p (dest
))
2975 /* Handle the case where inner is twice the size of outer. */
2976 else if (GET_MODE_PRECISION (temp_mode
)
2977 == 2 * GET_MODE_PRECISION (dest_mode
))
2978 offset
+= GET_MODE_PRECISION (dest_mode
);
2979 /* Otherwise give up for now. */
2986 rtx inner
= SET_SRC (PATTERN (i3
));
2987 rtx outer
= SET_SRC (temp_expr
);
2989 wide_int o
= wi::insert (rtx_mode_t (outer
, temp_mode
),
2990 rtx_mode_t (inner
, dest_mode
),
2995 subst_low_luid
= DF_INSN_LUID (i2
);
2996 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2998 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
3000 /* Replace the source in I2 with the new constant and make the
3001 resulting insn the new pattern for I3. Then skip to where we
3002 validate the pattern. Everything was set up above. */
3003 SUBST (SET_SRC (temp_expr
),
3004 immed_wide_int_const (o
, temp_mode
));
3006 newpat
= PATTERN (i2
);
3008 /* The dest of I3 has been replaced with the dest of I2. */
3009 changed_i3_dest
= 1;
3010 goto validate_replacement
;
3014 /* If we have no I1 and I2 looks like:
3015 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
3017 make up a dummy I1 that is
3020 (set (reg:CC X) (compare:CC Y (const_int 0)))
3022 (We can ignore any trailing CLOBBERs.)
3024 This undoes a previous combination and allows us to match a branch-and-
3027 if (!HAVE_cc0
&& i1
== 0
3028 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
3029 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
3031 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
3032 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
3033 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
3034 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
3035 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
3036 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
3038 /* We make I1 with the same INSN_UID as I2. This gives it
3039 the same DF_INSN_LUID for value tracking. Our fake I1 will
3040 never appear in the insn stream so giving it the same INSN_UID
3041 as I2 will not cause a problem. */
3043 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
3044 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
3046 INSN_UID (i1
) = INSN_UID (i2
);
3048 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
3049 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
3050 SET_DEST (PATTERN (i1
)));
3051 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
3052 SUBST_LINK (LOG_LINKS (i2
),
3053 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
3056 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3057 make those two SETs separate I1 and I2 insns, and make an I0 that is
3059 if (!HAVE_cc0
&& i0
== 0
3060 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
3061 && can_split_parallel_of_n_reg_sets (i2
, 2)
3062 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
3063 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
)
3064 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
3065 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
3067 /* If there is no I1, there is no I0 either. */
3070 /* We make I1 with the same INSN_UID as I2. This gives it
3071 the same DF_INSN_LUID for value tracking. Our fake I1 will
3072 never appear in the insn stream so giving it the same INSN_UID
3073 as I2 will not cause a problem. */
3075 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
3076 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
3078 INSN_UID (i1
) = INSN_UID (i2
);
3080 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
3083 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
3084 if (!can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
))
3086 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
3087 fprintf (dump_file
, "Can't combine i2 into i3\n");
3091 if (i1
&& !can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
, &i1dest
, &i1src
))
3093 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
3094 fprintf (dump_file
, "Can't combine i1 into i3\n");
3098 if (i0
&& !can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
, &i0dest
, &i0src
))
3100 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
3101 fprintf (dump_file
, "Can't combine i0 into i3\n");
3106 /* Record whether i2 and i3 are trivial moves. */
3107 i2_was_move
= is_just_move (i2
);
3108 i3_was_move
= is_just_move (i3
);
3110 /* Record whether I2DEST is used in I2SRC and similarly for the other
3111 cases. Knowing this will help in register status updating below. */
3112 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
3113 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
3114 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
3115 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
3116 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
3117 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
3118 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
3119 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
3120 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
3122 /* For the earlier insns, determine which of the subsequent ones they
3124 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3125 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3126 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3127 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3128 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3130 /* Ensure that I3's pattern can be the destination of combines. */
3131 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3132 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3133 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3134 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3141 /* See if any of the insns is a MULT operation. Unless one is, we will
3142 reject a combination that is, since it must be slower. Be conservative
3144 if (GET_CODE (i2src
) == MULT
3145 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3146 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3147 || (GET_CODE (PATTERN (i3
)) == SET
3148 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3151 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3152 We used to do this EXCEPT in one case: I3 has a post-inc in an
3153 output operand. However, that exception can give rise to insns like
3155 which is a famous insn on the PDP-11 where the value of r3 used as the
3156 source was model-dependent. Avoid this sort of thing. */
3159 if (!(GET_CODE (PATTERN (i3
)) == SET
3160 && REG_P (SET_SRC (PATTERN (i3
)))
3161 && MEM_P (SET_DEST (PATTERN (i3
)))
3162 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3163 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3164 /* It's not the exception. */
3169 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3170 if (REG_NOTE_KIND (link
) == REG_INC
3171 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3173 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3180 /* See if the SETs in I1 or I2 need to be kept around in the merged
3181 instruction: whenever the value set there is still needed past I3.
3182 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3184 For the SET in I1, we have two cases: if I1 and I2 independently feed
3185 into I3, the set in I1 needs to be kept around unless I1DEST dies
3186 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3187 in I1 needs to be kept around unless I1DEST dies or is set in either
3188 I2 or I3. The same considerations apply to I0. */
3190 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3193 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3194 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3199 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3200 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3201 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3202 && dead_or_set_p (i2
, i0dest
)));
3206 /* We are about to copy insns for the case where they need to be kept
3207 around. Check that they can be copied in the merged instruction. */
3209 if (targetm
.cannot_copy_insn_p
3210 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3211 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3212 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3218 /* Count how many auto_inc expressions there were in the original insns;
3219 we need to have the same number in the resulting patterns. */
3222 for_each_inc_dec (PATTERN (i0
), count_auto_inc
, &n_auto_inc
);
3224 for_each_inc_dec (PATTERN (i1
), count_auto_inc
, &n_auto_inc
);
3225 for_each_inc_dec (PATTERN (i2
), count_auto_inc
, &n_auto_inc
);
3226 for_each_inc_dec (PATTERN (i3
), count_auto_inc
, &n_auto_inc
);
3228 /* If the set in I2 needs to be kept around, we must make a copy of
3229 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3230 PATTERN (I2), we are only substituting for the original I1DEST, not into
3231 an already-substituted copy. This also prevents making self-referential
3232 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3237 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3238 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3240 i2pat
= copy_rtx (PATTERN (i2
));
3245 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3246 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3248 i1pat
= copy_rtx (PATTERN (i1
));
3253 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3254 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3256 i0pat
= copy_rtx (PATTERN (i0
));
3261 /* Substitute in the latest insn for the regs set by the earlier ones. */
3263 maxreg
= max_reg_num ();
3267 /* Many machines that don't use CC0 have insns that can both perform an
3268 arithmetic operation and set the condition code. These operations will
3269 be represented as a PARALLEL with the first element of the vector
3270 being a COMPARE of an arithmetic operation with the constant zero.
3271 The second element of the vector will set some pseudo to the result
3272 of the same arithmetic operation. If we simplify the COMPARE, we won't
3273 match such a pattern and so will generate an extra insn. Here we test
3274 for this case, where both the comparison and the operation result are
3275 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3276 I2SRC. Later we will make the PARALLEL that contains I2. */
3278 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3279 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3280 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3281 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3284 rtx
*cc_use_loc
= NULL
;
3285 rtx_insn
*cc_use_insn
= NULL
;
3286 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3287 machine_mode compare_mode
, orig_compare_mode
;
3288 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3289 scalar_int_mode mode
;
3291 newpat
= PATTERN (i3
);
3292 newpat_dest
= SET_DEST (newpat
);
3293 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3295 if (undobuf
.other_insn
== 0
3296 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3299 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3300 if (is_a
<scalar_int_mode
> (GET_MODE (i2dest
), &mode
))
3301 compare_code
= simplify_compare_const (compare_code
, mode
,
3303 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3306 /* Do the rest only if op1 is const0_rtx, which may be the
3307 result of simplification. */
3308 if (op1
== const0_rtx
)
3310 /* If a single use of the CC is found, prepare to modify it
3311 when SELECT_CC_MODE returns a new CC-class mode, or when
3312 the above simplify_compare_const() returned a new comparison
3313 operator. undobuf.other_insn is assigned the CC use insn
3314 when modifying it. */
3317 #ifdef SELECT_CC_MODE
3318 machine_mode new_mode
3319 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3320 if (new_mode
!= orig_compare_mode
3321 && can_change_dest_mode (SET_DEST (newpat
),
3322 added_sets_2
, new_mode
))
3324 unsigned int regno
= REGNO (newpat_dest
);
3325 compare_mode
= new_mode
;
3326 if (regno
< FIRST_PSEUDO_REGISTER
)
3327 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3330 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3331 newpat_dest
= regno_reg_rtx
[regno
];
3335 /* Cases for modifying the CC-using comparison. */
3336 if (compare_code
!= orig_compare_code
3337 /* ??? Do we need to verify the zero rtx? */
3338 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3340 /* Replace cc_use_loc with entire new RTX. */
3342 gen_rtx_fmt_ee (compare_code
, GET_MODE (*cc_use_loc
),
3343 newpat_dest
, const0_rtx
));
3344 undobuf
.other_insn
= cc_use_insn
;
3346 else if (compare_mode
!= orig_compare_mode
)
3348 /* Just replace the CC reg with a new mode. */
3349 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3350 undobuf
.other_insn
= cc_use_insn
;
3354 /* Now we modify the current newpat:
3355 First, SET_DEST(newpat) is updated if the CC mode has been
3356 altered. For targets without SELECT_CC_MODE, this should be
3358 if (compare_mode
!= orig_compare_mode
)
3359 SUBST (SET_DEST (newpat
), newpat_dest
);
3360 /* This is always done to propagate i2src into newpat. */
3361 SUBST (SET_SRC (newpat
),
3362 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3363 /* Create new version of i2pat if needed; the below PARALLEL
3364 creation needs this to work correctly. */
3365 if (! rtx_equal_p (i2src
, op0
))
3366 i2pat
= gen_rtx_SET (i2dest
, op0
);
3371 if (i2_is_used
== 0)
3373 /* It is possible that the source of I2 or I1 may be performing
3374 an unneeded operation, such as a ZERO_EXTEND of something
3375 that is known to have the high part zero. Handle that case
3376 by letting subst look at the inner insns.
3378 Another way to do this would be to have a function that tries
3379 to simplify a single insn instead of merging two or more
3380 insns. We don't do this because of the potential of infinite
3381 loops and because of the potential extra memory required.
3382 However, doing it the way we are is a bit of a kludge and
3383 doesn't catch all cases.
3385 But only do this if -fexpensive-optimizations since it slows
3386 things down and doesn't usually win.
3388 This is not done in the COMPARE case above because the
3389 unmodified I2PAT is used in the PARALLEL and so a pattern
3390 with a modified I2SRC would not match. */
3392 if (flag_expensive_optimizations
)
3394 /* Pass pc_rtx so no substitutions are done, just
3398 subst_low_luid
= DF_INSN_LUID (i1
);
3399 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3402 subst_low_luid
= DF_INSN_LUID (i2
);
3403 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3406 n_occurrences
= 0; /* `subst' counts here */
3407 subst_low_luid
= DF_INSN_LUID (i2
);
3409 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3410 copy of I2SRC each time we substitute it, in order to avoid creating
3411 self-referential RTL when we will be substituting I1SRC for I1DEST
3412 later. Likewise if I0 feeds into I2, either directly or indirectly
3413 through I1, and I0DEST is in I0SRC. */
3414 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3415 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3416 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3417 && i0dest_in_i0src
));
3420 /* Record whether I2's body now appears within I3's body. */
3421 i2_is_used
= n_occurrences
;
3424 /* If we already got a failure, don't try to do more. Otherwise, try to
3425 substitute I1 if we have it. */
3427 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3429 /* Before we can do this substitution, we must redo the test done
3430 above (see detailed comments there) that ensures I1DEST isn't
3431 mentioned in any SETs in NEWPAT that are field assignments. */
3432 if (!combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3440 subst_low_luid
= DF_INSN_LUID (i1
);
3442 /* If the following substitution will modify I1SRC, make a copy of it
3443 for the case where it is substituted for I1DEST in I2PAT later. */
3444 if (added_sets_2
&& i1_feeds_i2_n
)
3445 i1src_copy
= copy_rtx (i1src
);
3447 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3448 copy of I1SRC each time we substitute it, in order to avoid creating
3449 self-referential RTL when we will be substituting I0SRC for I0DEST
3451 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3452 i0_feeds_i1_n
&& i0dest_in_i0src
);
3455 /* Record whether I1's body now appears within I3's body. */
3456 i1_is_used
= n_occurrences
;
3459 /* Likewise for I0 if we have it. */
3461 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3463 if (!combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3470 /* If the following substitution will modify I0SRC, make a copy of it
3471 for the case where it is substituted for I0DEST in I1PAT later. */
3472 if (added_sets_1
&& i0_feeds_i1_n
)
3473 i0src_copy
= copy_rtx (i0src
);
3474 /* And a copy for I0DEST in I2PAT substitution. */
3475 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3476 || (i0_feeds_i2_n
)))
3477 i0src_copy2
= copy_rtx (i0src
);
3480 subst_low_luid
= DF_INSN_LUID (i0
);
3481 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3487 int new_n_auto_inc
= 0;
3488 for_each_inc_dec (newpat
, count_auto_inc
, &new_n_auto_inc
);
3490 if (n_auto_inc
!= new_n_auto_inc
)
3492 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
3493 fprintf (dump_file
, "Number of auto_inc expressions changed\n");
3499 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3500 to count all the ways that I2SRC and I1SRC can be used. */
3501 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3502 && i2_is_used
+ added_sets_2
> 1)
3503 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3504 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3506 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3507 && (n_occurrences
+ added_sets_0
3508 + (added_sets_1
&& i0_feeds_i1_n
)
3509 + (added_sets_2
&& i0_feeds_i2_n
)
3511 /* Fail if we tried to make a new register. */
3512 || max_reg_num () != maxreg
3513 /* Fail if we couldn't do something and have a CLOBBER. */
3514 || GET_CODE (newpat
) == CLOBBER
3515 /* Fail if this new pattern is a MULT and we didn't have one before
3516 at the outer level. */
3517 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3524 /* If the actions of the earlier insns must be kept
3525 in addition to substituting them into the latest one,
3526 we must make a new PARALLEL for the latest insn
3527 to hold additional the SETs. */
3529 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3531 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3534 if (GET_CODE (newpat
) == PARALLEL
)
3536 rtvec old
= XVEC (newpat
, 0);
3537 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3538 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3539 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3540 sizeof (old
->elem
[0]) * old
->num_elem
);
3545 total_sets
= 1 + extra_sets
;
3546 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3547 XVECEXP (newpat
, 0, 0) = old
;
3551 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3557 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3559 XVECEXP (newpat
, 0, --total_sets
) = t
;
3565 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3566 i0_feeds_i1_n
&& i0dest_in_i0src
);
3567 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3568 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3570 XVECEXP (newpat
, 0, --total_sets
) = t
;
3574 validate_replacement
:
3576 /* Note which hard regs this insn has as inputs. */
3577 mark_used_regs_combine (newpat
);
3579 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3580 consider splitting this pattern, we might need these clobbers. */
3581 if (i1
&& GET_CODE (newpat
) == PARALLEL
3582 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3584 int len
= XVECLEN (newpat
, 0);
3586 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3587 for (i
= 0; i
< len
; i
++)
3588 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3591 /* We have recognized nothing yet. */
3592 insn_code_number
= -1;
3594 /* See if this is a PARALLEL of two SETs where one SET's destination is
3595 a register that is unused and this isn't marked as an instruction that
3596 might trap in an EH region. In that case, we just need the other SET.
3597 We prefer this over the PARALLEL.
3599 This can occur when simplifying a divmod insn. We *must* test for this
3600 case here because the code below that splits two independent SETs doesn't
3601 handle this case correctly when it updates the register status.
3603 It's pointless doing this if we originally had two sets, one from
3604 i3, and one from i2. Combining then splitting the parallel results
3605 in the original i2 again plus an invalid insn (which we delete).
3606 The net effect is only to move instructions around, which makes
3607 debug info less accurate.
3609 If the remaining SET came from I2 its destination should not be used
3610 between I2 and I3. See PR82024. */
3612 if (!(added_sets_2
&& i1
== 0)
3613 && is_parallel_of_n_reg_sets (newpat
, 2)
3614 && asm_noperands (newpat
) < 0)
3616 rtx set0
= XVECEXP (newpat
, 0, 0);
3617 rtx set1
= XVECEXP (newpat
, 0, 1);
3618 rtx oldpat
= newpat
;
3620 if (((REG_P (SET_DEST (set1
))
3621 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3622 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3623 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3624 && insn_nothrow_p (i3
)
3625 && !side_effects_p (SET_SRC (set1
)))
3628 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3631 else if (((REG_P (SET_DEST (set0
))
3632 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3633 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3634 && find_reg_note (i3
, REG_UNUSED
,
3635 SUBREG_REG (SET_DEST (set0
)))))
3636 && insn_nothrow_p (i3
)
3637 && !side_effects_p (SET_SRC (set0
)))
3639 rtx dest
= SET_DEST (set1
);
3640 if (GET_CODE (dest
) == SUBREG
)
3641 dest
= SUBREG_REG (dest
);
3642 if (!reg_used_between_p (dest
, i2
, i3
))
3645 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3647 if (insn_code_number
>= 0)
3648 changed_i3_dest
= 1;
3652 if (insn_code_number
< 0)
3656 /* Is the result of combination a valid instruction? */
3657 if (insn_code_number
< 0)
3658 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3660 /* If we were combining three insns and the result is a simple SET
3661 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3662 insns. There are two ways to do this. It can be split using a
3663 machine-specific method (like when you have an addition of a large
3664 constant) or by combine in the function find_split_point. */
3666 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3667 && asm_noperands (newpat
) < 0)
3669 rtx parallel
, *split
;
3670 rtx_insn
*m_split_insn
;
3672 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3673 use I2DEST as a scratch register will help. In the latter case,
3674 convert I2DEST to the mode of the source of NEWPAT if we can. */
3676 m_split_insn
= combine_split_insns (newpat
, i3
);
3678 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3679 inputs of NEWPAT. */
3681 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3682 possible to try that as a scratch reg. This would require adding
3683 more code to make it work though. */
3685 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3687 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3689 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3690 (temporarily, until we are committed to this instruction
3691 combination) does not work: for example, any call to nonzero_bits
3692 on the register (from a splitter in the MD file, for example)
3693 will get the old information, which is invalid.
3695 Since nowadays we can create registers during combine just fine,
3696 we should just create a new one here, not reuse i2dest. */
3698 /* First try to split using the original register as a
3699 scratch register. */
3700 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3701 gen_rtvec (2, newpat
,
3702 gen_rtx_CLOBBER (VOIDmode
,
3704 m_split_insn
= combine_split_insns (parallel
, i3
);
3706 /* If that didn't work, try changing the mode of I2DEST if
3708 if (m_split_insn
== 0
3709 && new_mode
!= GET_MODE (i2dest
)
3710 && new_mode
!= VOIDmode
3711 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3713 machine_mode old_mode
= GET_MODE (i2dest
);
3716 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3717 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3720 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3721 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3724 parallel
= (gen_rtx_PARALLEL
3726 gen_rtvec (2, newpat
,
3727 gen_rtx_CLOBBER (VOIDmode
,
3729 m_split_insn
= combine_split_insns (parallel
, i3
);
3731 if (m_split_insn
== 0
3732 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3736 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3737 buf
= undobuf
.undos
;
3738 undobuf
.undos
= buf
->next
;
3739 buf
->next
= undobuf
.frees
;
3740 undobuf
.frees
= buf
;
3744 i2scratch
= m_split_insn
!= 0;
3747 /* If recog_for_combine has discarded clobbers, try to use them
3748 again for the split. */
3749 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3751 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3752 m_split_insn
= combine_split_insns (parallel
, i3
);
3755 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3757 rtx m_split_pat
= PATTERN (m_split_insn
);
3758 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3759 if (insn_code_number
>= 0)
3760 newpat
= m_split_pat
;
3762 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3763 && (next_nonnote_nondebug_insn (i2
) == i3
3764 || !modified_between_p (PATTERN (m_split_insn
), i2
, i3
)))
3767 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3768 newi2pat
= PATTERN (m_split_insn
);
3770 i3set
= single_set (NEXT_INSN (m_split_insn
));
3771 i2set
= single_set (m_split_insn
);
3773 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3775 /* If I2 or I3 has multiple SETs, we won't know how to track
3776 register status, so don't use these insns. If I2's destination
3777 is used between I2 and I3, we also can't use these insns. */
3779 if (i2_code_number
>= 0 && i2set
&& i3set
3780 && (next_nonnote_nondebug_insn (i2
) == i3
3781 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3782 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3784 if (insn_code_number
>= 0)
3787 /* It is possible that both insns now set the destination of I3.
3788 If so, we must show an extra use of it. */
3790 if (insn_code_number
>= 0)
3792 rtx new_i3_dest
= SET_DEST (i3set
);
3793 rtx new_i2_dest
= SET_DEST (i2set
);
3795 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3796 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3797 || GET_CODE (new_i3_dest
) == SUBREG
)
3798 new_i3_dest
= XEXP (new_i3_dest
, 0);
3800 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3801 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3802 || GET_CODE (new_i2_dest
) == SUBREG
)
3803 new_i2_dest
= XEXP (new_i2_dest
, 0);
3805 if (REG_P (new_i3_dest
)
3806 && REG_P (new_i2_dest
)
3807 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3808 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3809 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3813 /* If we can split it and use I2DEST, go ahead and see if that
3814 helps things be recognized. Verify that none of the registers
3815 are set between I2 and I3. */
3816 if (insn_code_number
< 0
3817 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3818 && (!HAVE_cc0
|| REG_P (i2dest
))
3819 /* We need I2DEST in the proper mode. If it is a hard register
3820 or the only use of a pseudo, we can change its mode.
3821 Make sure we don't change a hard register to have a mode that
3822 isn't valid for it, or change the number of registers. */
3823 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3824 || GET_MODE (*split
) == VOIDmode
3825 || can_change_dest_mode (i2dest
, added_sets_2
,
3827 && (next_nonnote_nondebug_insn (i2
) == i3
3828 || !modified_between_p (*split
, i2
, i3
))
3829 /* We can't overwrite I2DEST if its value is still used by
3831 && ! reg_referenced_p (i2dest
, newpat
))
3833 rtx newdest
= i2dest
;
3834 enum rtx_code split_code
= GET_CODE (*split
);
3835 machine_mode split_mode
= GET_MODE (*split
);
3836 bool subst_done
= false;
3837 newi2pat
= NULL_RTX
;
3841 /* *SPLIT may be part of I2SRC, so make sure we have the
3842 original expression around for later debug processing.
3843 We should not need I2SRC any more in other cases. */
3844 if (MAY_HAVE_DEBUG_BIND_INSNS
)
3845 i2src
= copy_rtx (i2src
);
3849 /* Get NEWDEST as a register in the proper mode. We have already
3850 validated that we can do this. */
3851 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3853 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3854 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3857 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3858 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3862 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3863 an ASHIFT. This can occur if it was inside a PLUS and hence
3864 appeared to be a memory address. This is a kludge. */
3865 if (split_code
== MULT
3866 && CONST_INT_P (XEXP (*split
, 1))
3867 && INTVAL (XEXP (*split
, 1)) > 0
3868 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3870 rtx i_rtx
= gen_int_shift_amount (split_mode
, i
);
3871 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3872 XEXP (*split
, 0), i_rtx
));
3873 /* Update split_code because we may not have a multiply
3875 split_code
= GET_CODE (*split
);
3878 /* Similarly for (plus (mult FOO (const_int pow2))). */
3879 if (split_code
== PLUS
3880 && GET_CODE (XEXP (*split
, 0)) == MULT
3881 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3882 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3883 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3885 rtx nsplit
= XEXP (*split
, 0);
3886 rtx i_rtx
= gen_int_shift_amount (GET_MODE (nsplit
), i
);
3887 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3890 /* Update split_code because we may not have a multiply
3892 split_code
= GET_CODE (*split
);
3895 #ifdef INSN_SCHEDULING
3896 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3897 be written as a ZERO_EXTEND. */
3898 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3900 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3901 what it really is. */
3902 if (load_extend_op (GET_MODE (SUBREG_REG (*split
)))
3904 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3905 SUBREG_REG (*split
)));
3907 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3908 SUBREG_REG (*split
)));
3912 /* Attempt to split binary operators using arithmetic identities. */
3913 if (BINARY_P (SET_SRC (newpat
))
3914 && split_mode
== GET_MODE (SET_SRC (newpat
))
3915 && ! side_effects_p (SET_SRC (newpat
)))
3917 rtx setsrc
= SET_SRC (newpat
);
3918 machine_mode mode
= GET_MODE (setsrc
);
3919 enum rtx_code code
= GET_CODE (setsrc
);
3920 rtx src_op0
= XEXP (setsrc
, 0);
3921 rtx src_op1
= XEXP (setsrc
, 1);
3923 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3924 if (rtx_equal_p (src_op0
, src_op1
))
3926 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3927 SUBST (XEXP (setsrc
, 0), newdest
);
3928 SUBST (XEXP (setsrc
, 1), newdest
);
3931 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3932 else if ((code
== PLUS
|| code
== MULT
)
3933 && GET_CODE (src_op0
) == code
3934 && GET_CODE (XEXP (src_op0
, 0)) == code
3935 && (INTEGRAL_MODE_P (mode
)
3936 || (FLOAT_MODE_P (mode
)
3937 && flag_unsafe_math_optimizations
)))
3939 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3940 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3941 rtx r
= XEXP (src_op0
, 1);
3944 /* Split both "((X op Y) op X) op Y" and
3945 "((X op Y) op Y) op X" as "T op T" where T is
3947 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3948 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3950 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3951 SUBST (XEXP (setsrc
, 0), newdest
);
3952 SUBST (XEXP (setsrc
, 1), newdest
);
3955 /* Split "((X op X) op Y) op Y)" as "T op T" where
3957 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3959 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3960 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3961 SUBST (XEXP (setsrc
, 0), newdest
);
3962 SUBST (XEXP (setsrc
, 1), newdest
);
3970 newi2pat
= gen_rtx_SET (newdest
, *split
);
3971 SUBST (*split
, newdest
);
3974 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3976 /* recog_for_combine might have added CLOBBERs to newi2pat.
3977 Make sure NEWPAT does not depend on the clobbered regs. */
3978 if (GET_CODE (newi2pat
) == PARALLEL
)
3979 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3980 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3982 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3983 if (reg_overlap_mentioned_p (reg
, newpat
))
3990 /* If the split point was a MULT and we didn't have one before,
3991 don't use one now. */
3992 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3993 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3997 /* Check for a case where we loaded from memory in a narrow mode and
3998 then sign extended it, but we need both registers. In that case,
3999 we have a PARALLEL with both loads from the same memory location.
4000 We can split this into a load from memory followed by a register-register
4001 copy. This saves at least one insn, more if register allocation can
4004 We cannot do this if the destination of the first assignment is a
4005 condition code register or cc0. We eliminate this case by making sure
4006 the SET_DEST and SET_SRC have the same mode.
4008 We cannot do this if the destination of the second assignment is
4009 a register that we have already assumed is zero-extended. Similarly
4010 for a SUBREG of such a register. */
4012 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
4013 && GET_CODE (newpat
) == PARALLEL
4014 && XVECLEN (newpat
, 0) == 2
4015 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
4016 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
4017 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
4018 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
4019 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
4020 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
4021 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
4022 && !modified_between_p (SET_SRC (XVECEXP (newpat
, 0, 1)), i2
, i3
)
4023 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
4024 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
4025 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
4027 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
4028 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
4030 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
4032 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
4033 != GET_MODE_MASK (word_mode
))))
4034 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
4035 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
4037 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
4038 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
4040 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
4042 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
4043 != GET_MODE_MASK (word_mode
)))))
4044 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
4045 SET_SRC (XVECEXP (newpat
, 0, 1)))
4046 && ! find_reg_note (i3
, REG_UNUSED
,
4047 SET_DEST (XVECEXP (newpat
, 0, 0))))
4051 newi2pat
= XVECEXP (newpat
, 0, 0);
4052 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
4053 newpat
= XVECEXP (newpat
, 0, 1);
4054 SUBST (SET_SRC (newpat
),
4055 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
4056 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
4058 if (i2_code_number
>= 0)
4059 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4061 if (insn_code_number
>= 0)
4065 /* Similarly, check for a case where we have a PARALLEL of two independent
4066 SETs but we started with three insns. In this case, we can do the sets
4067 as two separate insns. This case occurs when some SET allows two
4068 other insns to combine, but the destination of that SET is still live.
4070 Also do this if we started with two insns and (at least) one of the
4071 resulting sets is a noop; this noop will be deleted later.
4073 Also do this if we started with two insns neither of which was a simple
4076 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
4077 && GET_CODE (newpat
) == PARALLEL
4078 && XVECLEN (newpat
, 0) == 2
4079 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
4080 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
4082 || set_noop_p (XVECEXP (newpat
, 0, 0))
4083 || set_noop_p (XVECEXP (newpat
, 0, 1))
4084 || (!i2_was_move
&& !i3_was_move
))
4085 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
4086 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
4087 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
4088 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
4089 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
4090 XVECEXP (newpat
, 0, 0))
4091 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
4092 XVECEXP (newpat
, 0, 1))
4093 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
4094 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
4096 rtx set0
= XVECEXP (newpat
, 0, 0);
4097 rtx set1
= XVECEXP (newpat
, 0, 1);
4099 /* Normally, it doesn't matter which of the two is done first,
4100 but the one that references cc0 can't be the second, and
4101 one which uses any regs/memory set in between i2 and i3 can't
4102 be first. The PARALLEL might also have been pre-existing in i3,
4103 so we need to make sure that we won't wrongly hoist a SET to i2
4104 that would conflict with a death note present in there, or would
4105 have its dest modified between i2 and i3. */
4106 if (!modified_between_p (SET_SRC (set1
), i2
, i3
)
4107 && !(REG_P (SET_DEST (set1
))
4108 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
4109 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
4110 && find_reg_note (i2
, REG_DEAD
,
4111 SUBREG_REG (SET_DEST (set1
))))
4112 && !modified_between_p (SET_DEST (set1
), i2
, i3
)
4113 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
4114 /* If I3 is a jump, ensure that set0 is a jump so that
4115 we do not create invalid RTL. */
4116 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
4122 else if (!modified_between_p (SET_SRC (set0
), i2
, i3
)
4123 && !(REG_P (SET_DEST (set0
))
4124 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
4125 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
4126 && find_reg_note (i2
, REG_DEAD
,
4127 SUBREG_REG (SET_DEST (set0
))))
4128 && !modified_between_p (SET_DEST (set0
), i2
, i3
)
4129 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
4130 /* If I3 is a jump, ensure that set1 is a jump so that
4131 we do not create invalid RTL. */
4132 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
4144 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
4146 if (i2_code_number
>= 0)
4148 /* recog_for_combine might have added CLOBBERs to newi2pat.
4149 Make sure NEWPAT does not depend on the clobbered regs. */
4150 if (GET_CODE (newi2pat
) == PARALLEL
)
4152 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
4153 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
4155 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
4156 if (reg_overlap_mentioned_p (reg
, newpat
))
4164 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4166 if (insn_code_number
>= 0)
4171 /* If it still isn't recognized, fail and change things back the way they
4173 if ((insn_code_number
< 0
4174 /* Is the result a reasonable ASM_OPERANDS? */
4175 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4181 /* If we had to change another insn, make sure it is valid also. */
4182 if (undobuf
.other_insn
)
4184 CLEAR_HARD_REG_SET (newpat_used_regs
);
4186 other_pat
= PATTERN (undobuf
.other_insn
);
4187 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4190 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4197 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4198 they are adjacent to each other or not. */
4201 rtx_insn
*p
= prev_nonnote_insn (i3
);
4202 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4203 && sets_cc0_p (newi2pat
))
4210 /* Only allow this combination if insn_cost reports that the
4211 replacement instructions are cheaper than the originals. */
4212 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4218 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4222 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4223 if (undo
->kind
== UNDO_MODE
)
4225 rtx reg
= *undo
->where
.r
;
4226 machine_mode new_mode
= GET_MODE (reg
);
4227 machine_mode old_mode
= undo
->old_contents
.m
;
4229 /* Temporarily revert mode back. */
4230 adjust_reg_mode (reg
, old_mode
);
4232 if (reg
== i2dest
&& i2scratch
)
4234 /* If we used i2dest as a scratch register with a
4235 different mode, substitute it for the original
4236 i2src while its original mode is temporarily
4237 restored, and then clear i2scratch so that we don't
4238 do it again later. */
4239 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4242 /* Put back the new mode. */
4243 adjust_reg_mode (reg
, new_mode
);
4247 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4248 rtx_insn
*first
, *last
;
4253 last
= last_combined_insn
;
4258 last
= undobuf
.other_insn
;
4260 if (DF_INSN_LUID (last
)
4261 < DF_INSN_LUID (last_combined_insn
))
4262 last
= last_combined_insn
;
4265 /* We're dealing with a reg that changed mode but not
4266 meaning, so we want to turn it into a subreg for
4267 the new mode. However, because of REG sharing and
4268 because its mode had already changed, we have to do
4269 it in two steps. First, replace any debug uses of
4270 reg, with its original mode temporarily restored,
4271 with this copy we have created; then, replace the
4272 copy with the SUBREG of the original shared reg,
4273 once again changed to the new mode. */
4274 propagate_for_debug (first
, last
, reg
, tempreg
,
4276 adjust_reg_mode (reg
, new_mode
);
4277 propagate_for_debug (first
, last
, tempreg
,
4278 lowpart_subreg (old_mode
, reg
, new_mode
),
4284 /* If we will be able to accept this, we have made a
4285 change to the destination of I3. This requires us to
4286 do a few adjustments. */
4288 if (changed_i3_dest
)
4290 PATTERN (i3
) = newpat
;
4291 adjust_for_new_dest (i3
);
4294 /* We now know that we can do this combination. Merge the insns and
4295 update the status of registers and LOG_LINKS. */
4297 if (undobuf
.other_insn
)
4301 PATTERN (undobuf
.other_insn
) = other_pat
;
4303 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4304 ensure that they are still valid. Then add any non-duplicate
4305 notes added by recog_for_combine. */
4306 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4308 next
= XEXP (note
, 1);
4310 if ((REG_NOTE_KIND (note
) == REG_DEAD
4311 && !reg_referenced_p (XEXP (note
, 0),
4312 PATTERN (undobuf
.other_insn
)))
4313 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4314 && !reg_set_p (XEXP (note
, 0),
4315 PATTERN (undobuf
.other_insn
)))
4316 /* Simply drop equal note since it may be no longer valid
4317 for other_insn. It may be possible to record that CC
4318 register is changed and only discard those notes, but
4319 in practice it's unnecessary complication and doesn't
4320 give any meaningful improvement.
4323 || REG_NOTE_KIND (note
) == REG_EQUAL
4324 || REG_NOTE_KIND (note
) == REG_EQUIV
)
4325 remove_note (undobuf
.other_insn
, note
);
4328 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4329 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4335 /* I3 now uses what used to be its destination and which is now
4336 I2's destination. This requires us to do a few adjustments. */
4337 PATTERN (i3
) = newpat
;
4338 adjust_for_new_dest (i3
);
4341 if (swap_i2i3
|| split_i2i3
)
4343 /* We might need a LOG_LINK from I3 to I2. But then we used to
4344 have one, so we still will.
4346 However, some later insn might be using I2's dest and have
4347 a LOG_LINK pointing at I3. We should change it to point at
4350 /* newi2pat is usually a SET here; however, recog_for_combine might
4351 have added some clobbers. */
4353 if (GET_CODE (x
) == PARALLEL
)
4354 x
= XVECEXP (newi2pat
, 0, 0);
4356 if (REG_P (SET_DEST (x
))
4357 || (GET_CODE (SET_DEST (x
)) == SUBREG
4358 && REG_P (SUBREG_REG (SET_DEST (x
)))))
4360 unsigned int regno
= reg_or_subregno (SET_DEST (x
));
4363 for (rtx_insn
*insn
= NEXT_INSN (i3
);
4366 && NONDEBUG_INSN_P (insn
)
4367 && BLOCK_FOR_INSN (insn
) == this_basic_block
;
4368 insn
= NEXT_INSN (insn
))
4370 struct insn_link
*link
;
4371 FOR_EACH_LOG_LINK (link
, insn
)
4372 if (link
->insn
== i3
&& link
->regno
== regno
)
4383 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4384 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4387 /* Compute which registers we expect to eliminate. newi2pat may be setting
4388 either i3dest or i2dest, so we must check it. */
4389 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4390 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4393 /* For i1, we need to compute both local elimination and global
4394 elimination information with respect to newi2pat because i1dest
4395 may be the same as i3dest, in which case newi2pat may be setting
4396 i1dest. Global information is used when distributing REG_DEAD
4397 note for i2 and i3, in which case it does matter if newi2pat sets
4400 Local information is used when distributing REG_DEAD note for i1,
4401 in which case it doesn't matter if newi2pat sets i1dest or not.
4402 See PR62151, if we have four insns combination:
4404 i1: r1 <- i1src (using r0)
4406 i2: r0 <- i2src (using r1)
4407 i3: r3 <- i3src (using r0)
4409 From i1's point of view, r0 is eliminated, no matter if it is set
4410 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4411 should be discarded.
4413 Note local information only affects cases in forms like "I1->I2->I3",
4414 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4415 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4417 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4420 rtx elim_i1
= (local_elim_i1
== 0
4421 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4423 /* Same case as i1. */
4424 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4426 rtx elim_i0
= (local_elim_i0
== 0
4427 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4430 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4432 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4433 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4435 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4437 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4439 /* Ensure that we do not have something that should not be shared but
4440 occurs multiple times in the new insns. Check this by first
4441 resetting all the `used' flags and then copying anything is shared. */
4443 reset_used_flags (i3notes
);
4444 reset_used_flags (i2notes
);
4445 reset_used_flags (i1notes
);
4446 reset_used_flags (i0notes
);
4447 reset_used_flags (newpat
);
4448 reset_used_flags (newi2pat
);
4449 if (undobuf
.other_insn
)
4450 reset_used_flags (PATTERN (undobuf
.other_insn
));
4452 i3notes
= copy_rtx_if_shared (i3notes
);
4453 i2notes
= copy_rtx_if_shared (i2notes
);
4454 i1notes
= copy_rtx_if_shared (i1notes
);
4455 i0notes
= copy_rtx_if_shared (i0notes
);
4456 newpat
= copy_rtx_if_shared (newpat
);
4457 newi2pat
= copy_rtx_if_shared (newi2pat
);
4458 if (undobuf
.other_insn
)
4459 reset_used_flags (PATTERN (undobuf
.other_insn
));
4461 INSN_CODE (i3
) = insn_code_number
;
4462 PATTERN (i3
) = newpat
;
4464 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4466 for (rtx link
= CALL_INSN_FUNCTION_USAGE (i3
); link
;
4467 link
= XEXP (link
, 1))
4471 /* I2SRC must still be meaningful at this point. Some
4472 splitting operations can invalidate I2SRC, but those
4473 operations do not apply to calls. */
4475 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4479 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4482 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4487 if (undobuf
.other_insn
)
4488 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4490 /* We had one special case above where I2 had more than one set and
4491 we replaced a destination of one of those sets with the destination
4492 of I3. In that case, we have to update LOG_LINKS of insns later
4493 in this basic block. Note that this (expensive) case is rare.
4495 Also, in this case, we must pretend that all REG_NOTEs for I2
4496 actually came from I3, so that REG_UNUSED notes from I2 will be
4497 properly handled. */
4499 if (i3_subst_into_i2
)
4501 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4502 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4503 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4504 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4505 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4506 && ! find_reg_note (i2
, REG_UNUSED
,
4507 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4508 for (temp_insn
= NEXT_INSN (i2
);
4510 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4511 || BB_HEAD (this_basic_block
) != temp_insn
);
4512 temp_insn
= NEXT_INSN (temp_insn
))
4513 if (temp_insn
!= i3
&& NONDEBUG_INSN_P (temp_insn
))
4514 FOR_EACH_LOG_LINK (link
, temp_insn
)
4515 if (link
->insn
== i2
)
4521 while (XEXP (link
, 1))
4522 link
= XEXP (link
, 1);
4523 XEXP (link
, 1) = i2notes
;
4530 LOG_LINKS (i3
) = NULL
;
4532 LOG_LINKS (i2
) = NULL
;
4537 if (MAY_HAVE_DEBUG_BIND_INSNS
&& i2scratch
)
4538 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4540 INSN_CODE (i2
) = i2_code_number
;
4541 PATTERN (i2
) = newi2pat
;
4545 if (MAY_HAVE_DEBUG_BIND_INSNS
&& i2src
)
4546 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4548 SET_INSN_DELETED (i2
);
4553 LOG_LINKS (i1
) = NULL
;
4555 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4556 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4558 SET_INSN_DELETED (i1
);
4563 LOG_LINKS (i0
) = NULL
;
4565 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4566 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4568 SET_INSN_DELETED (i0
);
4571 /* Get death notes for everything that is now used in either I3 or
4572 I2 and used to die in a previous insn. If we built two new
4573 patterns, move from I1 to I2 then I2 to I3 so that we get the
4574 proper movement on registers that I2 modifies. */
4577 from_luid
= DF_INSN_LUID (i0
);
4579 from_luid
= DF_INSN_LUID (i1
);
4581 from_luid
= DF_INSN_LUID (i2
);
4583 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4584 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4586 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4588 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4589 elim_i2
, elim_i1
, elim_i0
);
4591 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4592 elim_i2
, elim_i1
, elim_i0
);
4594 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4595 elim_i2
, local_elim_i1
, local_elim_i0
);
4597 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4598 elim_i2
, elim_i1
, local_elim_i0
);
4600 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4601 elim_i2
, elim_i1
, elim_i0
);
4603 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4604 know these are REG_UNUSED and want them to go to the desired insn,
4605 so we always pass it as i3. */
4607 if (newi2pat
&& new_i2_notes
)
4608 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4612 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4615 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4616 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4617 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4618 in that case, it might delete I2. Similarly for I2 and I1.
4619 Show an additional death due to the REG_DEAD note we make here. If
4620 we discard it in distribute_notes, we will decrement it again. */
4624 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4625 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4626 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4629 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4630 elim_i2
, elim_i1
, elim_i0
);
4633 if (i2dest_in_i2src
)
4635 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4636 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4637 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4638 NULL_RTX
, NULL_RTX
);
4640 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4641 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4644 if (i1dest_in_i1src
)
4646 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4647 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4648 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4649 NULL_RTX
, NULL_RTX
);
4651 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4652 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4655 if (i0dest_in_i0src
)
4657 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4658 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4659 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4660 NULL_RTX
, NULL_RTX
);
4662 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4663 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4666 distribute_links (i3links
);
4667 distribute_links (i2links
);
4668 distribute_links (i1links
);
4669 distribute_links (i0links
);
4673 struct insn_link
*link
;
4674 rtx_insn
*i2_insn
= 0;
4675 rtx i2_val
= 0, set
;
4677 /* The insn that used to set this register doesn't exist, and
4678 this life of the register may not exist either. See if one of
4679 I3's links points to an insn that sets I2DEST. If it does,
4680 that is now the last known value for I2DEST. If we don't update
4681 this and I2 set the register to a value that depended on its old
4682 contents, we will get confused. If this insn is used, thing
4683 will be set correctly in combine_instructions. */
4684 FOR_EACH_LOG_LINK (link
, i3
)
4685 if ((set
= single_set (link
->insn
)) != 0
4686 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4687 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4689 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4691 /* If the reg formerly set in I2 died only once and that was in I3,
4692 zero its use count so it won't make `reload' do any work. */
4694 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4695 && ! i2dest_in_i2src
4696 && REGNO (i2dest
) < reg_n_sets_max
)
4697 INC_REG_N_SETS (REGNO (i2dest
), -1);
4700 if (i1
&& REG_P (i1dest
))
4702 struct insn_link
*link
;
4703 rtx_insn
*i1_insn
= 0;
4704 rtx i1_val
= 0, set
;
4706 FOR_EACH_LOG_LINK (link
, i3
)
4707 if ((set
= single_set (link
->insn
)) != 0
4708 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4709 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4711 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4714 && ! i1dest_in_i1src
4715 && REGNO (i1dest
) < reg_n_sets_max
)
4716 INC_REG_N_SETS (REGNO (i1dest
), -1);
4719 if (i0
&& REG_P (i0dest
))
4721 struct insn_link
*link
;
4722 rtx_insn
*i0_insn
= 0;
4723 rtx i0_val
= 0, set
;
4725 FOR_EACH_LOG_LINK (link
, i3
)
4726 if ((set
= single_set (link
->insn
)) != 0
4727 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4728 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4730 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4733 && ! i0dest_in_i0src
4734 && REGNO (i0dest
) < reg_n_sets_max
)
4735 INC_REG_N_SETS (REGNO (i0dest
), -1);
4738 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4739 been made to this insn. The order is important, because newi2pat
4740 can affect nonzero_bits of newpat. */
4742 note_pattern_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4743 note_pattern_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4746 if (undobuf
.other_insn
!= NULL_RTX
)
4750 fprintf (dump_file
, "modifying other_insn ");
4751 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4753 df_insn_rescan (undobuf
.other_insn
);
4756 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4760 fprintf (dump_file
, "modifying insn i0 ");
4761 dump_insn_slim (dump_file
, i0
);
4763 df_insn_rescan (i0
);
4766 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4770 fprintf (dump_file
, "modifying insn i1 ");
4771 dump_insn_slim (dump_file
, i1
);
4773 df_insn_rescan (i1
);
4776 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4780 fprintf (dump_file
, "modifying insn i2 ");
4781 dump_insn_slim (dump_file
, i2
);
4783 df_insn_rescan (i2
);
4786 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4790 fprintf (dump_file
, "modifying insn i3 ");
4791 dump_insn_slim (dump_file
, i3
);
4793 df_insn_rescan (i3
);
4796 /* Set new_direct_jump_p if a new return or simple jump instruction
4797 has been created. Adjust the CFG accordingly. */
4798 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4800 *new_direct_jump_p
= 1;
4801 mark_jump_label (PATTERN (i3
), i3
, 0);
4802 update_cfg_for_uncondjump (i3
);
4805 if (undobuf
.other_insn
!= NULL_RTX
4806 && (returnjump_p (undobuf
.other_insn
)
4807 || any_uncondjump_p (undobuf
.other_insn
)))
4809 *new_direct_jump_p
= 1;
4810 update_cfg_for_uncondjump (undobuf
.other_insn
);
4813 if (GET_CODE (PATTERN (i3
)) == TRAP_IF
4814 && XEXP (PATTERN (i3
), 0) == const1_rtx
)
4816 basic_block bb
= BLOCK_FOR_INSN (i3
);
4818 remove_edge (split_block (bb
, i3
));
4819 emit_barrier_after_bb (bb
);
4820 *new_direct_jump_p
= 1;
4823 if (undobuf
.other_insn
4824 && GET_CODE (PATTERN (undobuf
.other_insn
)) == TRAP_IF
4825 && XEXP (PATTERN (undobuf
.other_insn
), 0) == const1_rtx
)
4827 basic_block bb
= BLOCK_FOR_INSN (undobuf
.other_insn
);
4829 remove_edge (split_block (bb
, undobuf
.other_insn
));
4830 emit_barrier_after_bb (bb
);
4831 *new_direct_jump_p
= 1;
4834 /* A noop might also need cleaning up of CFG, if it comes from the
4835 simplification of a jump. */
4837 && GET_CODE (newpat
) == SET
4838 && SET_SRC (newpat
) == pc_rtx
4839 && SET_DEST (newpat
) == pc_rtx
)
4841 *new_direct_jump_p
= 1;
4842 update_cfg_for_uncondjump (i3
);
4845 if (undobuf
.other_insn
!= NULL_RTX
4846 && JUMP_P (undobuf
.other_insn
)
4847 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4848 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4849 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4851 *new_direct_jump_p
= 1;
4852 update_cfg_for_uncondjump (undobuf
.other_insn
);
4855 combine_successes
++;
4858 rtx_insn
*ret
= newi2pat
? i2
: i3
;
4859 if (added_links_insn
&& DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (ret
))
4860 ret
= added_links_insn
;
4861 if (added_notes_insn
&& DF_INSN_LUID (added_notes_insn
) < DF_INSN_LUID (ret
))
4862 ret
= added_notes_insn
;
4867 /* Get a marker for undoing to the current state. */
4870 get_undo_marker (void)
4872 return undobuf
.undos
;
4875 /* Undo the modifications up to the marker. */
4878 undo_to_marker (void *marker
)
4880 struct undo
*undo
, *next
;
4882 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4890 *undo
->where
.r
= undo
->old_contents
.r
;
4893 *undo
->where
.i
= undo
->old_contents
.i
;
4896 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4899 *undo
->where
.l
= undo
->old_contents
.l
;
4905 undo
->next
= undobuf
.frees
;
4906 undobuf
.frees
= undo
;
4909 undobuf
.undos
= (struct undo
*) marker
;
4912 /* Undo all the modifications recorded in undobuf. */
4920 /* We've committed to accepting the changes we made. Move all
4921 of the undos to the free list. */
4926 struct undo
*undo
, *next
;
4928 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4931 undo
->next
= undobuf
.frees
;
4932 undobuf
.frees
= undo
;
4937 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4938 where we have an arithmetic expression and return that point. LOC will
4941 try_combine will call this function to see if an insn can be split into
4945 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4948 enum rtx_code code
= GET_CODE (x
);
4950 unsigned HOST_WIDE_INT len
= 0;
4951 HOST_WIDE_INT pos
= 0;
4953 rtx inner
= NULL_RTX
;
4954 scalar_int_mode mode
, inner_mode
;
4956 /* First special-case some codes. */
4960 #ifdef INSN_SCHEDULING
4961 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4963 if (MEM_P (SUBREG_REG (x
)))
4966 return find_split_point (&SUBREG_REG (x
), insn
, false);
4969 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4970 using LO_SUM and HIGH. */
4971 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4972 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4974 machine_mode address_mode
= get_address_mode (x
);
4977 gen_rtx_LO_SUM (address_mode
,
4978 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4980 return &XEXP (XEXP (x
, 0), 0);
4983 /* If we have a PLUS whose second operand is a constant and the
4984 address is not valid, perhaps we can split it up using
4985 the machine-specific way to split large constants. We use
4986 the first pseudo-reg (one of the virtual regs) as a placeholder;
4987 it will not remain in the result. */
4988 if (GET_CODE (XEXP (x
, 0)) == PLUS
4989 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4990 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4991 MEM_ADDR_SPACE (x
)))
4993 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4994 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4997 /* This should have produced two insns, each of which sets our
4998 placeholder. If the source of the second is a valid address,
4999 we can put both sources together and make a split point
5003 && NEXT_INSN (seq
) != NULL_RTX
5004 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
5005 && NONJUMP_INSN_P (seq
)
5006 && GET_CODE (PATTERN (seq
)) == SET
5007 && SET_DEST (PATTERN (seq
)) == reg
5008 && ! reg_mentioned_p (reg
,
5009 SET_SRC (PATTERN (seq
)))
5010 && NONJUMP_INSN_P (NEXT_INSN (seq
))
5011 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
5012 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
5013 && memory_address_addr_space_p
5014 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
5015 MEM_ADDR_SPACE (x
)))
5017 rtx src1
= SET_SRC (PATTERN (seq
));
5018 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
5020 /* Replace the placeholder in SRC2 with SRC1. If we can
5021 find where in SRC2 it was placed, that can become our
5022 split point and we can replace this address with SRC2.
5023 Just try two obvious places. */
5025 src2
= replace_rtx (src2
, reg
, src1
);
5027 if (XEXP (src2
, 0) == src1
)
5028 split
= &XEXP (src2
, 0);
5029 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
5030 && XEXP (XEXP (src2
, 0), 0) == src1
)
5031 split
= &XEXP (XEXP (src2
, 0), 0);
5035 SUBST (XEXP (x
, 0), src2
);
5040 /* If that didn't work and we have a nested plus, like:
5041 ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
5042 is valid address, try to split (REG1 * CONST1). */
5043 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
5044 && !OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 0))
5045 && OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5046 && ! (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SUBREG
5047 && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x
, 0),
5050 rtx tem
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
5051 XEXP (XEXP (XEXP (x
, 0), 0), 0) = reg
;
5052 if (memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
5053 MEM_ADDR_SPACE (x
)))
5055 XEXP (XEXP (XEXP (x
, 0), 0), 0) = tem
;
5056 return &XEXP (XEXP (XEXP (x
, 0), 0), 0);
5058 XEXP (XEXP (XEXP (x
, 0), 0), 0) = tem
;
5060 else if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
5061 && OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 0))
5062 && !OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5063 && ! (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == SUBREG
5064 && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x
, 0),
5067 rtx tem
= XEXP (XEXP (XEXP (x
, 0), 0), 1);
5068 XEXP (XEXP (XEXP (x
, 0), 0), 1) = reg
;
5069 if (memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
5070 MEM_ADDR_SPACE (x
)))
5072 XEXP (XEXP (XEXP (x
, 0), 0), 1) = tem
;
5073 return &XEXP (XEXP (XEXP (x
, 0), 0), 1);
5075 XEXP (XEXP (XEXP (x
, 0), 0), 1) = tem
;
5078 /* If that didn't work, perhaps the first operand is complex and
5079 needs to be computed separately, so make a split point there.
5080 This will occur on machines that just support REG + CONST
5081 and have a constant moved through some previous computation. */
5082 if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
5083 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
5084 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
5085 return &XEXP (XEXP (x
, 0), 0);
5088 /* If we have a PLUS whose first operand is complex, try computing it
5089 separately by making a split there. */
5090 if (GET_CODE (XEXP (x
, 0)) == PLUS
5091 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
5093 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
5094 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
5095 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
5096 return &XEXP (XEXP (x
, 0), 0);
5100 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
5101 ZERO_EXTRACT, the most likely reason why this doesn't match is that
5102 we need to put the operand into a register. So split at that
5105 if (SET_DEST (x
) == cc0_rtx
5106 && GET_CODE (SET_SRC (x
)) != COMPARE
5107 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
5108 && !OBJECT_P (SET_SRC (x
))
5109 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
5110 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
5111 return &SET_SRC (x
);
5113 /* See if we can split SET_SRC as it stands. */
5114 split
= find_split_point (&SET_SRC (x
), insn
, true);
5115 if (split
&& split
!= &SET_SRC (x
))
5118 /* See if we can split SET_DEST as it stands. */
5119 split
= find_split_point (&SET_DEST (x
), insn
, false);
5120 if (split
&& split
!= &SET_DEST (x
))
5123 /* See if this is a bitfield assignment with everything constant. If
5124 so, this is an IOR of an AND, so split it into that. */
5125 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5126 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (SET_DEST (x
), 0)),
5128 && HWI_COMPUTABLE_MODE_P (inner_mode
)
5129 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
5130 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
5131 && CONST_INT_P (SET_SRC (x
))
5132 && ((INTVAL (XEXP (SET_DEST (x
), 1))
5133 + INTVAL (XEXP (SET_DEST (x
), 2)))
5134 <= GET_MODE_PRECISION (inner_mode
))
5135 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
5137 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
5138 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
5139 rtx dest
= XEXP (SET_DEST (x
), 0);
5140 unsigned HOST_WIDE_INT mask
= (HOST_WIDE_INT_1U
<< len
) - 1;
5141 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
)) & mask
;
5144 if (BITS_BIG_ENDIAN
)
5145 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
5147 or_mask
= gen_int_mode (src
<< pos
, inner_mode
);
5150 simplify_gen_binary (IOR
, inner_mode
, dest
, or_mask
));
5153 rtx negmask
= gen_int_mode (~(mask
<< pos
), inner_mode
);
5155 simplify_gen_binary (IOR
, inner_mode
,
5156 simplify_gen_binary (AND
, inner_mode
,
5161 SUBST (SET_DEST (x
), dest
);
5163 split
= find_split_point (&SET_SRC (x
), insn
, true);
5164 if (split
&& split
!= &SET_SRC (x
))
5168 /* Otherwise, see if this is an operation that we can split into two.
5169 If so, try to split that. */
5170 code
= GET_CODE (SET_SRC (x
));
5175 /* If we are AND'ing with a large constant that is only a single
5176 bit and the result is only being used in a context where we
5177 need to know if it is zero or nonzero, replace it with a bit
5178 extraction. This will avoid the large constant, which might
5179 have taken more than one insn to make. If the constant were
5180 not a valid argument to the AND but took only one insn to make,
5181 this is no worse, but if it took more than one insn, it will
5184 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5185 && REG_P (XEXP (SET_SRC (x
), 0))
5186 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
5187 && REG_P (SET_DEST (x
))
5188 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
5189 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
5190 && XEXP (*split
, 0) == SET_DEST (x
)
5191 && XEXP (*split
, 1) == const0_rtx
)
5193 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
5194 XEXP (SET_SRC (x
), 0),
5195 pos
, NULL_RTX
, 1, 1, 0, 0);
5196 if (extraction
!= 0)
5198 SUBST (SET_SRC (x
), extraction
);
5199 return find_split_point (loc
, insn
, false);
5205 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5206 is known to be on, this can be converted into a NEG of a shift. */
5207 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
5208 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
5209 && ((pos
= exact_log2 (nonzero_bits (XEXP (SET_SRC (x
), 0),
5210 GET_MODE (XEXP (SET_SRC (x
),
5213 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
5214 rtx pos_rtx
= gen_int_shift_amount (mode
, pos
);
5217 gen_rtx_LSHIFTRT (mode
,
5218 XEXP (SET_SRC (x
), 0),
5221 split
= find_split_point (&SET_SRC (x
), insn
, true);
5222 if (split
&& split
!= &SET_SRC (x
))
5228 inner
= XEXP (SET_SRC (x
), 0);
5230 /* We can't optimize if either mode is a partial integer
5231 mode as we don't know how many bits are significant
5233 if (!is_int_mode (GET_MODE (inner
), &inner_mode
)
5234 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5238 len
= GET_MODE_PRECISION (inner_mode
);
5244 if (is_a
<scalar_int_mode
> (GET_MODE (XEXP (SET_SRC (x
), 0)),
5246 && CONST_INT_P (XEXP (SET_SRC (x
), 1))
5247 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5249 inner
= XEXP (SET_SRC (x
), 0);
5250 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5251 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5253 if (BITS_BIG_ENDIAN
)
5254 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
5255 unsignedp
= (code
== ZERO_EXTRACT
);
5264 && known_subrange_p (pos
, len
,
5265 0, GET_MODE_PRECISION (GET_MODE (inner
)))
5266 && is_a
<scalar_int_mode
> (GET_MODE (SET_SRC (x
)), &mode
))
5268 /* For unsigned, we have a choice of a shift followed by an
5269 AND or two shifts. Use two shifts for field sizes where the
5270 constant might be too large. We assume here that we can
5271 always at least get 8-bit constants in an AND insn, which is
5272 true for every current RISC. */
5274 if (unsignedp
&& len
<= 8)
5276 unsigned HOST_WIDE_INT mask
5277 = (HOST_WIDE_INT_1U
<< len
) - 1;
5278 rtx pos_rtx
= gen_int_shift_amount (mode
, pos
);
5282 (mode
, gen_lowpart (mode
, inner
), pos_rtx
),
5283 gen_int_mode (mask
, mode
)));
5285 split
= find_split_point (&SET_SRC (x
), insn
, true);
5286 if (split
&& split
!= &SET_SRC (x
))
5291 int left_bits
= GET_MODE_PRECISION (mode
) - len
- pos
;
5292 int right_bits
= GET_MODE_PRECISION (mode
) - len
;
5295 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5296 gen_rtx_ASHIFT (mode
,
5297 gen_lowpart (mode
, inner
),
5298 gen_int_shift_amount (mode
, left_bits
)),
5299 gen_int_shift_amount (mode
, right_bits
)));
5301 split
= find_split_point (&SET_SRC (x
), insn
, true);
5302 if (split
&& split
!= &SET_SRC (x
))
5307 /* See if this is a simple operation with a constant as the second
5308 operand. It might be that this constant is out of range and hence
5309 could be used as a split point. */
5310 if (BINARY_P (SET_SRC (x
))
5311 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5312 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5313 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5314 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5315 return &XEXP (SET_SRC (x
), 1);
5317 /* Finally, see if this is a simple operation with its first operand
5318 not in a register. The operation might require this operand in a
5319 register, so return it as a split point. We can always do this
5320 because if the first operand were another operation, we would have
5321 already found it as a split point. */
5322 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5323 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5324 return &XEXP (SET_SRC (x
), 0);
5330 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5331 it is better to write this as (not (ior A B)) so we can split it.
5332 Similarly for IOR. */
5333 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5336 gen_rtx_NOT (GET_MODE (x
),
5337 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5339 XEXP (XEXP (x
, 0), 0),
5340 XEXP (XEXP (x
, 1), 0))));
5341 return find_split_point (loc
, insn
, set_src
);
5344 /* Many RISC machines have a large set of logical insns. If the
5345 second operand is a NOT, put it first so we will try to split the
5346 other operand first. */
5347 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5349 rtx tem
= XEXP (x
, 0);
5350 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5351 SUBST (XEXP (x
, 1), tem
);
5357 /* Canonicalization can produce (minus A (mult B C)), where C is a
5358 constant. It may be better to try splitting (plus (mult B -C) A)
5359 instead if this isn't a multiply by a power of two. */
5360 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5361 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5362 && !pow2p_hwi (INTVAL (XEXP (XEXP (x
, 1), 1))))
5364 machine_mode mode
= GET_MODE (x
);
5365 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5366 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5367 SUBST (*loc
, gen_rtx_PLUS (mode
,
5369 XEXP (XEXP (x
, 1), 0),
5370 gen_int_mode (other_int
,
5373 return find_split_point (loc
, insn
, set_src
);
5376 /* Split at a multiply-accumulate instruction. However if this is
5377 the SET_SRC, we likely do not have such an instruction and it's
5378 worthless to try this split. */
5380 && (GET_CODE (XEXP (x
, 0)) == MULT
5381 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5382 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5389 /* Otherwise, select our actions depending on our rtx class. */
5390 switch (GET_RTX_CLASS (code
))
5392 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5394 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5399 case RTX_COMM_ARITH
:
5401 case RTX_COMM_COMPARE
:
5402 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5407 /* Some machines have (and (shift ...) ...) insns. If X is not
5408 an AND, but XEXP (X, 0) is, use it as our split point. */
5409 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5410 return &XEXP (x
, 0);
5412 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5418 /* Otherwise, we don't have a split point. */
5423 /* Throughout X, replace FROM with TO, and return the result.
5424 The result is TO if X is FROM;
5425 otherwise the result is X, but its contents may have been modified.
5426 If they were modified, a record was made in undobuf so that
5427 undo_all will (among other things) return X to its original state.
5429 If the number of changes necessary is too much to record to undo,
5430 the excess changes are not made, so the result is invalid.
5431 The changes already made can still be undone.
5432 undobuf.num_undo is incremented for such changes, so by testing that
5433 the caller can tell whether the result is valid.
5435 `n_occurrences' is incremented each time FROM is replaced.
5437 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5439 IN_COND is nonzero if we are at the top level of a condition.
5441 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5442 by copying if `n_occurrences' is nonzero. */
5445 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5447 enum rtx_code code
= GET_CODE (x
);
5448 machine_mode op0_mode
= VOIDmode
;
5453 /* Two expressions are equal if they are identical copies of a shared
5454 RTX or if they are both registers with the same register number
5457 #define COMBINE_RTX_EQUAL_P(X,Y) \
5459 || (REG_P (X) && REG_P (Y) \
5460 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5462 /* Do not substitute into clobbers of regs -- this will never result in
5464 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5467 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5470 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5473 /* If X and FROM are the same register but different modes, they
5474 will not have been seen as equal above. However, the log links code
5475 will make a LOG_LINKS entry for that case. If we do nothing, we
5476 will try to rerecognize our original insn and, when it succeeds,
5477 we will delete the feeding insn, which is incorrect.
5479 So force this insn not to match in this (rare) case. */
5480 if (! in_dest
&& code
== REG
&& REG_P (from
)
5481 && reg_overlap_mentioned_p (x
, from
))
5482 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5484 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5485 of which may contain things that can be combined. */
5486 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5489 /* It is possible to have a subexpression appear twice in the insn.
5490 Suppose that FROM is a register that appears within TO.
5491 Then, after that subexpression has been scanned once by `subst',
5492 the second time it is scanned, TO may be found. If we were
5493 to scan TO here, we would find FROM within it and create a
5494 self-referent rtl structure which is completely wrong. */
5495 if (COMBINE_RTX_EQUAL_P (x
, to
))
5498 /* Parallel asm_operands need special attention because all of the
5499 inputs are shared across the arms. Furthermore, unsharing the
5500 rtl results in recognition failures. Failure to handle this case
5501 specially can result in circular rtl.
5503 Solve this by doing a normal pass across the first entry of the
5504 parallel, and only processing the SET_DESTs of the subsequent
5507 if (code
== PARALLEL
5508 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5509 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5511 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5513 /* If this substitution failed, this whole thing fails. */
5514 if (GET_CODE (new_rtx
) == CLOBBER
5515 && XEXP (new_rtx
, 0) == const0_rtx
)
5518 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5520 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5522 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5525 && GET_CODE (dest
) != CC0
5526 && GET_CODE (dest
) != PC
)
5528 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5530 /* If this substitution failed, this whole thing fails. */
5531 if (GET_CODE (new_rtx
) == CLOBBER
5532 && XEXP (new_rtx
, 0) == const0_rtx
)
5535 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5541 len
= GET_RTX_LENGTH (code
);
5542 fmt
= GET_RTX_FORMAT (code
);
5544 /* We don't need to process a SET_DEST that is a register, CC0,
5545 or PC, so set up to skip this common case. All other cases
5546 where we want to suppress replacing something inside a
5547 SET_SRC are handled via the IN_DEST operand. */
5549 && (REG_P (SET_DEST (x
))
5550 || GET_CODE (SET_DEST (x
)) == CC0
5551 || GET_CODE (SET_DEST (x
)) == PC
))
5554 /* Trying to simplify the operands of a widening MULT is not likely
5555 to create RTL matching a machine insn. */
5557 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5558 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
5559 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
5560 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
5561 && REG_P (XEXP (XEXP (x
, 0), 0))
5562 && REG_P (XEXP (XEXP (x
, 1), 0))
5567 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5570 op0_mode
= GET_MODE (XEXP (x
, 0));
5572 for (i
= 0; i
< len
; i
++)
5577 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5579 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5581 new_rtx
= (unique_copy
&& n_occurrences
5582 ? copy_rtx (to
) : to
);
5587 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5590 /* If this substitution failed, this whole thing
5592 if (GET_CODE (new_rtx
) == CLOBBER
5593 && XEXP (new_rtx
, 0) == const0_rtx
)
5597 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5600 else if (fmt
[i
] == 'e')
5602 /* If this is a register being set, ignore it. */
5603 new_rtx
= XEXP (x
, i
);
5606 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5608 || code
== STRICT_LOW_PART
))
5611 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5613 /* In general, don't install a subreg involving two
5614 modes not tieable. It can worsen register
5615 allocation, and can even make invalid reload
5616 insns, since the reg inside may need to be copied
5617 from in the outside mode, and that may be invalid
5618 if it is an fp reg copied in integer mode.
5620 We allow two exceptions to this: It is valid if
5621 it is inside another SUBREG and the mode of that
5622 SUBREG and the mode of the inside of TO is
5623 tieable and it is valid if X is a SET that copies
5626 if (GET_CODE (to
) == SUBREG
5627 && !targetm
.modes_tieable_p (GET_MODE (to
),
5628 GET_MODE (SUBREG_REG (to
)))
5629 && ! (code
== SUBREG
5630 && (targetm
.modes_tieable_p
5631 (GET_MODE (x
), GET_MODE (SUBREG_REG (to
)))))
5635 && XEXP (x
, 0) == cc0_rtx
))))
5636 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5640 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5641 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5644 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5646 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5650 /* If we are in a SET_DEST, suppress most cases unless we
5651 have gone inside a MEM, in which case we want to
5652 simplify the address. We assume here that things that
5653 are actually part of the destination have their inner
5654 parts in the first expression. This is true for SUBREG,
5655 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5656 things aside from REG and MEM that should appear in a
5658 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5660 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5661 || code
== ZERO_EXTRACT
))
5664 code
== IF_THEN_ELSE
&& i
== 0,
5667 /* If we found that we will have to reject this combination,
5668 indicate that by returning the CLOBBER ourselves, rather than
5669 an expression containing it. This will speed things up as
5670 well as prevent accidents where two CLOBBERs are considered
5671 to be equal, thus producing an incorrect simplification. */
5673 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5676 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5678 machine_mode mode
= GET_MODE (x
);
5680 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5681 GET_MODE (SUBREG_REG (x
)),
5684 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5686 else if (CONST_SCALAR_INT_P (new_rtx
)
5687 && (GET_CODE (x
) == ZERO_EXTEND
5688 || GET_CODE (x
) == SIGN_EXTEND
5689 || GET_CODE (x
) == FLOAT
5690 || GET_CODE (x
) == UNSIGNED_FLOAT
))
5692 x
= simplify_unary_operation (GET_CODE (x
), GET_MODE (x
),
5694 GET_MODE (XEXP (x
, 0)));
5696 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5699 SUBST (XEXP (x
, i
), new_rtx
);
5704 /* Check if we are loading something from the constant pool via float
5705 extension; in this case we would undo compress_float_constant
5706 optimization and degenerate constant load to an immediate value. */
5707 if (GET_CODE (x
) == FLOAT_EXTEND
5708 && MEM_P (XEXP (x
, 0))
5709 && MEM_READONLY_P (XEXP (x
, 0)))
5711 rtx tmp
= avoid_constant_pool_reference (x
);
5716 /* Try to simplify X. If the simplification changed the code, it is likely
5717 that further simplification will help, so loop, but limit the number
5718 of repetitions that will be performed. */
5720 for (i
= 0; i
< 4; i
++)
5722 /* If X is sufficiently simple, don't bother trying to do anything
5724 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5725 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5727 if (GET_CODE (x
) == code
)
5730 code
= GET_CODE (x
);
5732 /* We no longer know the original mode of operand 0 since we
5733 have changed the form of X) */
5734 op0_mode
= VOIDmode
;
5740 /* If X is a commutative operation whose operands are not in the canonical
5741 order, use substitutions to swap them. */
5744 maybe_swap_commutative_operands (rtx x
)
5746 if (COMMUTATIVE_ARITH_P (x
)
5747 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5749 rtx temp
= XEXP (x
, 0);
5750 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5751 SUBST (XEXP (x
, 1), temp
);
5755 /* Simplify X, a piece of RTL. We just operate on the expression at the
5756 outer level; call `subst' to simplify recursively. Return the new
5759 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5760 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5764 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5767 enum rtx_code code
= GET_CODE (x
);
5768 machine_mode mode
= GET_MODE (x
);
5769 scalar_int_mode int_mode
;
5773 /* If this is a commutative operation, put a constant last and a complex
5774 expression first. We don't need to do this for comparisons here. */
5775 maybe_swap_commutative_operands (x
);
5777 /* Try to fold this expression in case we have constants that weren't
5780 switch (GET_RTX_CLASS (code
))
5783 if (op0_mode
== VOIDmode
)
5784 op0_mode
= GET_MODE (XEXP (x
, 0));
5785 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5788 case RTX_COMM_COMPARE
:
5790 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5791 if (cmp_mode
== VOIDmode
)
5793 cmp_mode
= GET_MODE (XEXP (x
, 1));
5794 if (cmp_mode
== VOIDmode
)
5795 cmp_mode
= op0_mode
;
5797 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5798 XEXP (x
, 0), XEXP (x
, 1));
5801 case RTX_COMM_ARITH
:
5803 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5805 case RTX_BITFIELD_OPS
:
5807 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5808 XEXP (x
, 1), XEXP (x
, 2));
5817 code
= GET_CODE (temp
);
5818 op0_mode
= VOIDmode
;
5819 mode
= GET_MODE (temp
);
5822 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5823 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5824 things. Check for cases where both arms are testing the same
5827 Don't do anything if all operands are very simple. */
5830 && ((!OBJECT_P (XEXP (x
, 0))
5831 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5832 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5833 || (!OBJECT_P (XEXP (x
, 1))
5834 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5835 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5837 && (!OBJECT_P (XEXP (x
, 0))
5838 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5839 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5841 rtx cond
, true_rtx
, false_rtx
;
5843 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5845 /* If everything is a comparison, what we have is highly unlikely
5846 to be simpler, so don't use it. */
5847 && ! (COMPARISON_P (x
)
5848 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
)))
5849 /* Similarly, if we end up with one of the expressions the same
5850 as the original, it is certainly not simpler. */
5851 && ! rtx_equal_p (x
, true_rtx
)
5852 && ! rtx_equal_p (x
, false_rtx
))
5854 rtx cop1
= const0_rtx
;
5855 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5857 if (cond_code
== NE
&& COMPARISON_P (cond
))
5860 /* Simplify the alternative arms; this may collapse the true and
5861 false arms to store-flag values. Be careful to use copy_rtx
5862 here since true_rtx or false_rtx might share RTL with x as a
5863 result of the if_then_else_cond call above. */
5864 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5865 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5867 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5868 is unlikely to be simpler. */
5869 if (general_operand (true_rtx
, VOIDmode
)
5870 && general_operand (false_rtx
, VOIDmode
))
5872 enum rtx_code reversed
;
5874 /* Restarting if we generate a store-flag expression will cause
5875 us to loop. Just drop through in this case. */
5877 /* If the result values are STORE_FLAG_VALUE and zero, we can
5878 just make the comparison operation. */
5879 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5880 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5882 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5883 && ((reversed
= reversed_comparison_code_parts
5884 (cond_code
, cond
, cop1
, NULL
))
5886 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5889 /* Likewise, we can make the negate of a comparison operation
5890 if the result values are - STORE_FLAG_VALUE and zero. */
5891 else if (CONST_INT_P (true_rtx
)
5892 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5893 && false_rtx
== const0_rtx
)
5894 x
= simplify_gen_unary (NEG
, mode
,
5895 simplify_gen_relational (cond_code
,
5899 else if (CONST_INT_P (false_rtx
)
5900 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5901 && true_rtx
== const0_rtx
5902 && ((reversed
= reversed_comparison_code_parts
5903 (cond_code
, cond
, cop1
, NULL
))
5905 x
= simplify_gen_unary (NEG
, mode
,
5906 simplify_gen_relational (reversed
,
5911 code
= GET_CODE (x
);
5912 op0_mode
= VOIDmode
;
5917 /* First see if we can apply the inverse distributive law. */
5918 if (code
== PLUS
|| code
== MINUS
5919 || code
== AND
|| code
== IOR
|| code
== XOR
)
5921 x
= apply_distributive_law (x
);
5922 code
= GET_CODE (x
);
5923 op0_mode
= VOIDmode
;
5926 /* If CODE is an associative operation not otherwise handled, see if we
5927 can associate some operands. This can win if they are constants or
5928 if they are logically related (i.e. (a & b) & a). */
5929 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5930 || code
== AND
|| code
== IOR
|| code
== XOR
5931 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5932 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5933 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5935 if (GET_CODE (XEXP (x
, 0)) == code
)
5937 rtx other
= XEXP (XEXP (x
, 0), 0);
5938 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5939 rtx inner_op1
= XEXP (x
, 1);
5942 /* Make sure we pass the constant operand if any as the second
5943 one if this is a commutative operation. */
5944 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5945 std::swap (inner_op0
, inner_op1
);
5946 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5947 : code
== DIV
? MULT
5949 mode
, inner_op0
, inner_op1
);
5951 /* For commutative operations, try the other pair if that one
5953 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5955 other
= XEXP (XEXP (x
, 0), 1);
5956 inner
= simplify_binary_operation (code
, mode
,
5957 XEXP (XEXP (x
, 0), 0),
5962 return simplify_gen_binary (code
, mode
, other
, inner
);
5966 /* A little bit of algebraic simplification here. */
5970 /* Ensure that our address has any ASHIFTs converted to MULT in case
5971 address-recognizing predicates are called later. */
5972 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5973 SUBST (XEXP (x
, 0), temp
);
5977 if (op0_mode
== VOIDmode
)
5978 op0_mode
= GET_MODE (SUBREG_REG (x
));
5980 /* See if this can be moved to simplify_subreg. */
5981 if (CONSTANT_P (SUBREG_REG (x
))
5982 && known_eq (subreg_lowpart_offset (mode
, op0_mode
), SUBREG_BYTE (x
))
5983 /* Don't call gen_lowpart if the inner mode
5984 is VOIDmode and we cannot simplify it, as SUBREG without
5985 inner mode is invalid. */
5986 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5987 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5988 return gen_lowpart (mode
, SUBREG_REG (x
));
5990 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5994 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5999 /* If op is known to have all lower bits zero, the result is zero. */
6000 scalar_int_mode int_mode
, int_op0_mode
;
6002 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6003 && is_a
<scalar_int_mode
> (op0_mode
, &int_op0_mode
)
6004 && (GET_MODE_PRECISION (int_mode
)
6005 < GET_MODE_PRECISION (int_op0_mode
))
6006 && known_eq (subreg_lowpart_offset (int_mode
, int_op0_mode
),
6008 && HWI_COMPUTABLE_MODE_P (int_op0_mode
)
6009 && ((nonzero_bits (SUBREG_REG (x
), int_op0_mode
)
6010 & GET_MODE_MASK (int_mode
)) == 0)
6011 && !side_effects_p (SUBREG_REG (x
)))
6012 return CONST0_RTX (int_mode
);
6015 /* Don't change the mode of the MEM if that would change the meaning
6017 if (MEM_P (SUBREG_REG (x
))
6018 && (MEM_VOLATILE_P (SUBREG_REG (x
))
6019 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
6020 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
6021 return gen_rtx_CLOBBER (mode
, const0_rtx
);
6023 /* Note that we cannot do any narrowing for non-constants since
6024 we might have been counting on using the fact that some bits were
6025 zero. We now do this in the SET. */
6030 temp
= expand_compound_operation (XEXP (x
, 0));
6032 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
6033 replaced by (lshiftrt X C). This will convert
6034 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
6036 if (GET_CODE (temp
) == ASHIFTRT
6037 && CONST_INT_P (XEXP (temp
, 1))
6038 && INTVAL (XEXP (temp
, 1)) == GET_MODE_UNIT_PRECISION (mode
) - 1)
6039 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
6040 INTVAL (XEXP (temp
, 1)));
6042 /* If X has only a single bit that might be nonzero, say, bit I, convert
6043 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
6044 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
6045 (sign_extract X 1 Y). But only do this if TEMP isn't a register
6046 or a SUBREG of one since we'd be making the expression more
6047 complex if it was just a register. */
6050 && ! (GET_CODE (temp
) == SUBREG
6051 && REG_P (SUBREG_REG (temp
)))
6052 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6053 && (i
= exact_log2 (nonzero_bits (temp
, int_mode
))) >= 0)
6055 rtx temp1
= simplify_shift_const
6056 (NULL_RTX
, ASHIFTRT
, int_mode
,
6057 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
, temp
,
6058 GET_MODE_PRECISION (int_mode
) - 1 - i
),
6059 GET_MODE_PRECISION (int_mode
) - 1 - i
);
6061 /* If all we did was surround TEMP with the two shifts, we
6062 haven't improved anything, so don't use it. Otherwise,
6063 we are better off with TEMP1. */
6064 if (GET_CODE (temp1
) != ASHIFTRT
6065 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
6066 || XEXP (XEXP (temp1
, 0), 0) != temp
)
6072 /* We can't handle truncation to a partial integer mode here
6073 because we don't know the real bitsize of the partial
6075 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
6078 if (HWI_COMPUTABLE_MODE_P (mode
))
6080 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
6081 GET_MODE_MASK (mode
), 0));
6083 /* We can truncate a constant value and return it. */
6086 if (poly_int_rtx_p (XEXP (x
, 0), &c
))
6087 return gen_int_mode (c
, mode
);
6090 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
6091 whose value is a comparison can be replaced with a subreg if
6092 STORE_FLAG_VALUE permits. */
6093 if (HWI_COMPUTABLE_MODE_P (mode
)
6094 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
6095 && (temp
= get_last_value (XEXP (x
, 0)))
6096 && COMPARISON_P (temp
))
6097 return gen_lowpart (mode
, XEXP (x
, 0));
6101 /* (const (const X)) can become (const X). Do it this way rather than
6102 returning the inner CONST since CONST can be shared with a
6104 if (GET_CODE (XEXP (x
, 0)) == CONST
)
6105 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
6109 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6110 can add in an offset. find_split_point will split this address up
6111 again if it doesn't match. */
6112 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
6113 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
6118 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6119 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6120 bit-field and can be replaced by either a sign_extend or a
6121 sign_extract. The `and' may be a zero_extend and the two
6122 <c>, -<c> constants may be reversed. */
6123 if (GET_CODE (XEXP (x
, 0)) == XOR
6124 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6125 && CONST_INT_P (XEXP (x
, 1))
6126 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
6127 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
6128 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
6129 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
6130 && HWI_COMPUTABLE_MODE_P (int_mode
)
6131 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
6132 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6133 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6134 == (HOST_WIDE_INT_1U
<< (i
+ 1)) - 1))
6135 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
6136 && known_eq ((GET_MODE_PRECISION
6137 (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))),
6138 (unsigned int) i
+ 1))))
6139 return simplify_shift_const
6140 (NULL_RTX
, ASHIFTRT
, int_mode
,
6141 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6142 XEXP (XEXP (XEXP (x
, 0), 0), 0),
6143 GET_MODE_PRECISION (int_mode
) - (i
+ 1)),
6144 GET_MODE_PRECISION (int_mode
) - (i
+ 1));
6146 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6147 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6148 the bitsize of the mode - 1. This allows simplification of
6149 "a = (b & 8) == 0;" */
6150 if (XEXP (x
, 1) == constm1_rtx
6151 && !REG_P (XEXP (x
, 0))
6152 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
6153 && REG_P (SUBREG_REG (XEXP (x
, 0))))
6154 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6155 && nonzero_bits (XEXP (x
, 0), int_mode
) == 1)
6156 return simplify_shift_const
6157 (NULL_RTX
, ASHIFTRT
, int_mode
,
6158 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6159 gen_rtx_XOR (int_mode
, XEXP (x
, 0),
6161 GET_MODE_PRECISION (int_mode
) - 1),
6162 GET_MODE_PRECISION (int_mode
) - 1);
6164 /* If we are adding two things that have no bits in common, convert
6165 the addition into an IOR. This will often be further simplified,
6166 for example in cases like ((a & 1) + (a & 2)), which can
6169 if (HWI_COMPUTABLE_MODE_P (mode
)
6170 && (nonzero_bits (XEXP (x
, 0), mode
)
6171 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
6173 /* Try to simplify the expression further. */
6174 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
6175 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
6177 /* If we could, great. If not, do not go ahead with the IOR
6178 replacement, since PLUS appears in many special purpose
6179 address arithmetic instructions. */
6180 if (GET_CODE (temp
) != CLOBBER
6181 && (GET_CODE (temp
) != IOR
6182 || ((XEXP (temp
, 0) != XEXP (x
, 0)
6183 || XEXP (temp
, 1) != XEXP (x
, 1))
6184 && (XEXP (temp
, 0) != XEXP (x
, 1)
6185 || XEXP (temp
, 1) != XEXP (x
, 0)))))
6189 /* Canonicalize x + x into x << 1. */
6190 if (GET_MODE_CLASS (mode
) == MODE_INT
6191 && rtx_equal_p (XEXP (x
, 0), XEXP (x
, 1))
6192 && !side_effects_p (XEXP (x
, 0)))
6193 return simplify_gen_binary (ASHIFT
, mode
, XEXP (x
, 0), const1_rtx
);
6198 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6199 (and <foo> (const_int pow2-1)) */
6200 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
6201 && GET_CODE (XEXP (x
, 1)) == AND
6202 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
6203 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x
, 1), 1)))
6204 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
6205 return simplify_and_const_int (NULL_RTX
, int_mode
, XEXP (x
, 0),
6206 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
6210 /* If we have (mult (plus A B) C), apply the distributive law and then
6211 the inverse distributive law to see if things simplify. This
6212 occurs mostly in addresses, often when unrolling loops. */
6214 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
6216 rtx result
= distribute_and_simplify_rtx (x
, 0);
6221 /* Try simplify a*(b/c) as (a*b)/c. */
6222 if (FLOAT_MODE_P (mode
) && flag_associative_math
6223 && GET_CODE (XEXP (x
, 0)) == DIV
)
6225 rtx tem
= simplify_binary_operation (MULT
, mode
,
6226 XEXP (XEXP (x
, 0), 0),
6229 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
6234 /* If this is a divide by a power of two, treat it as a shift if
6235 its first operand is a shift. */
6236 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
6237 && CONST_INT_P (XEXP (x
, 1))
6238 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
6239 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
6240 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6241 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
6242 || GET_CODE (XEXP (x
, 0)) == ROTATE
6243 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
6244 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, int_mode
,
6249 case GT
: case GTU
: case GE
: case GEU
:
6250 case LT
: case LTU
: case LE
: case LEU
:
6251 case UNEQ
: case LTGT
:
6252 case UNGT
: case UNGE
:
6253 case UNLT
: case UNLE
:
6254 case UNORDERED
: case ORDERED
:
6255 /* If the first operand is a condition code, we can't do anything
6257 if (GET_CODE (XEXP (x
, 0)) == COMPARE
6258 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
6259 && ! CC0_P (XEXP (x
, 0))))
6261 rtx op0
= XEXP (x
, 0);
6262 rtx op1
= XEXP (x
, 1);
6263 enum rtx_code new_code
;
6265 if (GET_CODE (op0
) == COMPARE
)
6266 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
6268 /* Simplify our comparison, if possible. */
6269 new_code
= simplify_comparison (code
, &op0
, &op1
);
6271 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6272 if only the low-order bit is possibly nonzero in X (such as when
6273 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6274 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6275 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6278 Remove any ZERO_EXTRACT we made when thinking this was a
6279 comparison. It may now be simpler to use, e.g., an AND. If a
6280 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6281 the call to make_compound_operation in the SET case.
6283 Don't apply these optimizations if the caller would
6284 prefer a comparison rather than a value.
6285 E.g., for the condition in an IF_THEN_ELSE most targets need
6286 an explicit comparison. */
6291 else if (STORE_FLAG_VALUE
== 1
6293 && is_int_mode (mode
, &int_mode
)
6294 && op1
== const0_rtx
6295 && int_mode
== GET_MODE (op0
)
6296 && nonzero_bits (op0
, int_mode
) == 1)
6297 return gen_lowpart (int_mode
,
6298 expand_compound_operation (op0
));
6300 else if (STORE_FLAG_VALUE
== 1
6302 && is_int_mode (mode
, &int_mode
)
6303 && op1
== const0_rtx
6304 && int_mode
== GET_MODE (op0
)
6305 && (num_sign_bit_copies (op0
, int_mode
)
6306 == GET_MODE_PRECISION (int_mode
)))
6308 op0
= expand_compound_operation (op0
);
6309 return simplify_gen_unary (NEG
, int_mode
,
6310 gen_lowpart (int_mode
, op0
),
6314 else if (STORE_FLAG_VALUE
== 1
6316 && is_int_mode (mode
, &int_mode
)
6317 && op1
== const0_rtx
6318 && int_mode
== GET_MODE (op0
)
6319 && nonzero_bits (op0
, int_mode
) == 1)
6321 op0
= expand_compound_operation (op0
);
6322 return simplify_gen_binary (XOR
, int_mode
,
6323 gen_lowpart (int_mode
, op0
),
6327 else if (STORE_FLAG_VALUE
== 1
6329 && is_int_mode (mode
, &int_mode
)
6330 && op1
== const0_rtx
6331 && int_mode
== GET_MODE (op0
)
6332 && (num_sign_bit_copies (op0
, int_mode
)
6333 == GET_MODE_PRECISION (int_mode
)))
6335 op0
= expand_compound_operation (op0
);
6336 return plus_constant (int_mode
, gen_lowpart (int_mode
, op0
), 1);
6339 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6344 else if (STORE_FLAG_VALUE
== -1
6346 && is_int_mode (mode
, &int_mode
)
6347 && op1
== const0_rtx
6348 && int_mode
== GET_MODE (op0
)
6349 && (num_sign_bit_copies (op0
, int_mode
)
6350 == GET_MODE_PRECISION (int_mode
)))
6351 return gen_lowpart (int_mode
, expand_compound_operation (op0
));
6353 else if (STORE_FLAG_VALUE
== -1
6355 && is_int_mode (mode
, &int_mode
)
6356 && op1
== const0_rtx
6357 && int_mode
== GET_MODE (op0
)
6358 && nonzero_bits (op0
, int_mode
) == 1)
6360 op0
= expand_compound_operation (op0
);
6361 return simplify_gen_unary (NEG
, int_mode
,
6362 gen_lowpart (int_mode
, op0
),
6366 else if (STORE_FLAG_VALUE
== -1
6368 && is_int_mode (mode
, &int_mode
)
6369 && op1
== const0_rtx
6370 && int_mode
== GET_MODE (op0
)
6371 && (num_sign_bit_copies (op0
, int_mode
)
6372 == GET_MODE_PRECISION (int_mode
)))
6374 op0
= expand_compound_operation (op0
);
6375 return simplify_gen_unary (NOT
, int_mode
,
6376 gen_lowpart (int_mode
, op0
),
6380 /* If X is 0/1, (eq X 0) is X-1. */
6381 else if (STORE_FLAG_VALUE
== -1
6383 && is_int_mode (mode
, &int_mode
)
6384 && op1
== const0_rtx
6385 && int_mode
== GET_MODE (op0
)
6386 && nonzero_bits (op0
, int_mode
) == 1)
6388 op0
= expand_compound_operation (op0
);
6389 return plus_constant (int_mode
, gen_lowpart (int_mode
, op0
), -1);
6392 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6393 one bit that might be nonzero, we can convert (ne x 0) to
6394 (ashift x c) where C puts the bit in the sign bit. Remove any
6395 AND with STORE_FLAG_VALUE when we are done, since we are only
6396 going to test the sign bit. */
6398 && is_int_mode (mode
, &int_mode
)
6399 && HWI_COMPUTABLE_MODE_P (int_mode
)
6400 && val_signbit_p (int_mode
, STORE_FLAG_VALUE
)
6401 && op1
== const0_rtx
6402 && int_mode
== GET_MODE (op0
)
6403 && (i
= exact_log2 (nonzero_bits (op0
, int_mode
))) >= 0)
6405 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6406 expand_compound_operation (op0
),
6407 GET_MODE_PRECISION (int_mode
) - 1 - i
);
6408 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6414 /* If the code changed, return a whole new comparison.
6415 We also need to avoid using SUBST in cases where
6416 simplify_comparison has widened a comparison with a CONST_INT,
6417 since in that case the wider CONST_INT may fail the sanity
6418 checks in do_SUBST. */
6419 if (new_code
!= code
6420 || (CONST_INT_P (op1
)
6421 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6422 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6423 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6425 /* Otherwise, keep this operation, but maybe change its operands.
6426 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6427 SUBST (XEXP (x
, 0), op0
);
6428 SUBST (XEXP (x
, 1), op1
);
6433 return simplify_if_then_else (x
);
6439 /* If we are processing SET_DEST, we are done. */
6443 return expand_compound_operation (x
);
6446 return simplify_set (x
);
6450 return simplify_logical (x
);
6457 /* If this is a shift by a constant amount, simplify it. */
6458 if (CONST_INT_P (XEXP (x
, 1)))
6459 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6460 INTVAL (XEXP (x
, 1)));
6462 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6464 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6466 << exact_log2 (GET_MODE_UNIT_BITSIZE
6479 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6482 simplify_if_then_else (rtx x
)
6484 machine_mode mode
= GET_MODE (x
);
6485 rtx cond
= XEXP (x
, 0);
6486 rtx true_rtx
= XEXP (x
, 1);
6487 rtx false_rtx
= XEXP (x
, 2);
6488 enum rtx_code true_code
= GET_CODE (cond
);
6489 int comparison_p
= COMPARISON_P (cond
);
6492 enum rtx_code false_code
;
6494 scalar_int_mode int_mode
, inner_mode
;
6496 /* Simplify storing of the truth value. */
6497 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6498 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6499 XEXP (cond
, 0), XEXP (cond
, 1));
6501 /* Also when the truth value has to be reversed. */
6503 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6504 && (reversed
= reversed_comparison (cond
, mode
)))
6507 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6508 in it is being compared against certain values. Get the true and false
6509 comparisons and see if that says anything about the value of each arm. */
6512 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6514 && REG_P (XEXP (cond
, 0)))
6517 rtx from
= XEXP (cond
, 0);
6518 rtx true_val
= XEXP (cond
, 1);
6519 rtx false_val
= true_val
;
6522 /* If FALSE_CODE is EQ, swap the codes and arms. */
6524 if (false_code
== EQ
)
6526 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6527 std::swap (true_rtx
, false_rtx
);
6530 scalar_int_mode from_mode
;
6531 if (is_a
<scalar_int_mode
> (GET_MODE (from
), &from_mode
))
6533 /* If we are comparing against zero and the expression being
6534 tested has only a single bit that might be nonzero, that is
6535 its value when it is not equal to zero. Similarly if it is
6536 known to be -1 or 0. */
6538 && true_val
== const0_rtx
6539 && pow2p_hwi (nzb
= nonzero_bits (from
, from_mode
)))
6542 false_val
= gen_int_mode (nzb
, from_mode
);
6544 else if (true_code
== EQ
6545 && true_val
== const0_rtx
6546 && (num_sign_bit_copies (from
, from_mode
)
6547 == GET_MODE_PRECISION (from_mode
)))
6550 false_val
= constm1_rtx
;
6554 /* Now simplify an arm if we know the value of the register in the
6555 branch and it is used in the arm. Be careful due to the potential
6556 of locally-shared RTL. */
6558 if (reg_mentioned_p (from
, true_rtx
))
6559 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6561 pc_rtx
, pc_rtx
, 0, 0, 0);
6562 if (reg_mentioned_p (from
, false_rtx
))
6563 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6565 pc_rtx
, pc_rtx
, 0, 0, 0);
6567 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6568 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6570 true_rtx
= XEXP (x
, 1);
6571 false_rtx
= XEXP (x
, 2);
6572 true_code
= GET_CODE (cond
);
6575 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6576 reversed, do so to avoid needing two sets of patterns for
6577 subtract-and-branch insns. Similarly if we have a constant in the true
6578 arm, the false arm is the same as the first operand of the comparison, or
6579 the false arm is more complicated than the true arm. */
6582 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6583 && (true_rtx
== pc_rtx
6584 || (CONSTANT_P (true_rtx
)
6585 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6586 || true_rtx
== const0_rtx
6587 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6588 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6589 && !OBJECT_P (false_rtx
))
6590 || reg_mentioned_p (true_rtx
, false_rtx
)
6591 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6593 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6594 SUBST (XEXP (x
, 1), false_rtx
);
6595 SUBST (XEXP (x
, 2), true_rtx
);
6597 std::swap (true_rtx
, false_rtx
);
6600 /* It is possible that the conditional has been simplified out. */
6601 true_code
= GET_CODE (cond
);
6602 comparison_p
= COMPARISON_P (cond
);
6605 /* If the two arms are identical, we don't need the comparison. */
6607 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6610 /* Convert a == b ? b : a to "a". */
6611 if (true_code
== EQ
&& ! side_effects_p (cond
)
6612 && !HONOR_NANS (mode
)
6613 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6614 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6616 else if (true_code
== NE
&& ! side_effects_p (cond
)
6617 && !HONOR_NANS (mode
)
6618 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6619 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6622 /* Look for cases where we have (abs x) or (neg (abs X)). */
6624 if (GET_MODE_CLASS (mode
) == MODE_INT
6626 && XEXP (cond
, 1) == const0_rtx
6627 && GET_CODE (false_rtx
) == NEG
6628 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6629 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6630 && ! side_effects_p (true_rtx
))
6635 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6639 simplify_gen_unary (NEG
, mode
,
6640 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6646 /* Look for MIN or MAX. */
6648 if ((! FLOAT_MODE_P (mode
)
6649 || (flag_unsafe_math_optimizations
6650 && !HONOR_NANS (mode
)
6651 && !HONOR_SIGNED_ZEROS (mode
)))
6653 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6654 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6655 && ! side_effects_p (cond
))
6660 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6663 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6666 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6669 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6674 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6675 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6676 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6677 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6678 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6679 neither 1 or -1, but it isn't worth checking for. */
6681 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6683 && is_int_mode (mode
, &int_mode
)
6684 && ! side_effects_p (x
))
6686 rtx t
= make_compound_operation (true_rtx
, SET
);
6687 rtx f
= make_compound_operation (false_rtx
, SET
);
6688 rtx cond_op0
= XEXP (cond
, 0);
6689 rtx cond_op1
= XEXP (cond
, 1);
6690 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6691 scalar_int_mode m
= int_mode
;
6692 rtx z
= 0, c1
= NULL_RTX
;
6694 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6695 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6696 || GET_CODE (t
) == ASHIFT
6697 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6698 && rtx_equal_p (XEXP (t
, 0), f
))
6699 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6701 /* If an identity-zero op is commutative, check whether there
6702 would be a match if we swapped the operands. */
6703 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6704 || GET_CODE (t
) == XOR
)
6705 && rtx_equal_p (XEXP (t
, 1), f
))
6706 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6707 else if (GET_CODE (t
) == SIGN_EXTEND
6708 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6709 && (GET_CODE (XEXP (t
, 0)) == PLUS
6710 || GET_CODE (XEXP (t
, 0)) == MINUS
6711 || GET_CODE (XEXP (t
, 0)) == IOR
6712 || GET_CODE (XEXP (t
, 0)) == XOR
6713 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6714 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6715 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6716 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6717 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6718 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6719 && (num_sign_bit_copies (f
, GET_MODE (f
))
6721 (GET_MODE_PRECISION (int_mode
)
6722 - GET_MODE_PRECISION (inner_mode
))))
6724 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6725 extend_op
= SIGN_EXTEND
;
6728 else if (GET_CODE (t
) == SIGN_EXTEND
6729 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6730 && (GET_CODE (XEXP (t
, 0)) == PLUS
6731 || GET_CODE (XEXP (t
, 0)) == IOR
6732 || GET_CODE (XEXP (t
, 0)) == XOR
)
6733 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6734 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6735 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6736 && (num_sign_bit_copies (f
, GET_MODE (f
))
6738 (GET_MODE_PRECISION (int_mode
)
6739 - GET_MODE_PRECISION (inner_mode
))))
6741 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6742 extend_op
= SIGN_EXTEND
;
6745 else if (GET_CODE (t
) == ZERO_EXTEND
6746 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6747 && (GET_CODE (XEXP (t
, 0)) == PLUS
6748 || GET_CODE (XEXP (t
, 0)) == MINUS
6749 || GET_CODE (XEXP (t
, 0)) == IOR
6750 || GET_CODE (XEXP (t
, 0)) == XOR
6751 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6752 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6753 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6754 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6755 && HWI_COMPUTABLE_MODE_P (int_mode
)
6756 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6757 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6758 && ((nonzero_bits (f
, GET_MODE (f
))
6759 & ~GET_MODE_MASK (inner_mode
))
6762 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6763 extend_op
= ZERO_EXTEND
;
6766 else if (GET_CODE (t
) == ZERO_EXTEND
6767 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6768 && (GET_CODE (XEXP (t
, 0)) == PLUS
6769 || GET_CODE (XEXP (t
, 0)) == IOR
6770 || GET_CODE (XEXP (t
, 0)) == XOR
)
6771 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6772 && HWI_COMPUTABLE_MODE_P (int_mode
)
6773 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6774 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6775 && ((nonzero_bits (f
, GET_MODE (f
))
6776 & ~GET_MODE_MASK (inner_mode
))
6779 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6780 extend_op
= ZERO_EXTEND
;
6786 machine_mode cm
= m
;
6787 if ((op
== ASHIFT
|| op
== LSHIFTRT
|| op
== ASHIFTRT
)
6788 && GET_MODE (c1
) != VOIDmode
)
6790 temp
= subst (simplify_gen_relational (true_code
, cm
, VOIDmode
,
6791 cond_op0
, cond_op1
),
6792 pc_rtx
, pc_rtx
, 0, 0, 0);
6793 temp
= simplify_gen_binary (MULT
, cm
, temp
,
6794 simplify_gen_binary (MULT
, cm
, c1
,
6796 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6797 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6799 if (extend_op
!= UNKNOWN
)
6800 temp
= simplify_gen_unary (extend_op
, int_mode
, temp
, m
);
6806 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6807 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6808 negation of a single bit, we can convert this operation to a shift. We
6809 can actually do this more generally, but it doesn't seem worth it. */
6812 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6813 && XEXP (cond
, 1) == const0_rtx
6814 && false_rtx
== const0_rtx
6815 && CONST_INT_P (true_rtx
)
6816 && ((nonzero_bits (XEXP (cond
, 0), int_mode
) == 1
6817 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6818 || ((num_sign_bit_copies (XEXP (cond
, 0), int_mode
)
6819 == GET_MODE_PRECISION (int_mode
))
6820 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6822 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6823 gen_lowpart (int_mode
, XEXP (cond
, 0)), i
);
6825 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6826 non-zero bit in A is C1. */
6827 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6828 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6829 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6830 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (cond
, 0)), &inner_mode
)
6831 && (UINTVAL (true_rtx
) & GET_MODE_MASK (int_mode
))
6832 == nonzero_bits (XEXP (cond
, 0), inner_mode
)
6833 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (int_mode
))) >= 0)
6835 rtx val
= XEXP (cond
, 0);
6836 if (inner_mode
== int_mode
)
6838 else if (GET_MODE_PRECISION (inner_mode
) < GET_MODE_PRECISION (int_mode
))
6839 return simplify_gen_unary (ZERO_EXTEND
, int_mode
, val
, inner_mode
);
6845 /* Simplify X, a SET expression. Return the new expression. */
6848 simplify_set (rtx x
)
6850 rtx src
= SET_SRC (x
);
6851 rtx dest
= SET_DEST (x
);
6853 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6854 rtx_insn
*other_insn
;
6856 scalar_int_mode int_mode
;
6858 /* (set (pc) (return)) gets written as (return). */
6859 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6862 /* Now that we know for sure which bits of SRC we are using, see if we can
6863 simplify the expression for the object knowing that we only need the
6866 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6868 src
= force_to_mode (src
, mode
, HOST_WIDE_INT_M1U
, 0);
6869 SUBST (SET_SRC (x
), src
);
6872 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6873 the comparison result and try to simplify it unless we already have used
6874 undobuf.other_insn. */
6875 if ((GET_MODE_CLASS (mode
) == MODE_CC
6876 || GET_CODE (src
) == COMPARE
6878 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6879 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6880 && COMPARISON_P (*cc_use
)
6881 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6883 enum rtx_code old_code
= GET_CODE (*cc_use
);
6884 enum rtx_code new_code
;
6886 int other_changed
= 0;
6887 rtx inner_compare
= NULL_RTX
;
6888 machine_mode compare_mode
= GET_MODE (dest
);
6890 if (GET_CODE (src
) == COMPARE
)
6892 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6893 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6895 inner_compare
= op0
;
6896 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6900 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6902 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6905 new_code
= old_code
;
6906 else if (!CONSTANT_P (tmp
))
6908 new_code
= GET_CODE (tmp
);
6909 op0
= XEXP (tmp
, 0);
6910 op1
= XEXP (tmp
, 1);
6914 rtx pat
= PATTERN (other_insn
);
6915 undobuf
.other_insn
= other_insn
;
6916 SUBST (*cc_use
, tmp
);
6918 /* Attempt to simplify CC user. */
6919 if (GET_CODE (pat
) == SET
)
6921 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6922 if (new_rtx
!= NULL_RTX
)
6923 SUBST (SET_SRC (pat
), new_rtx
);
6926 /* Convert X into a no-op move. */
6927 SUBST (SET_DEST (x
), pc_rtx
);
6928 SUBST (SET_SRC (x
), pc_rtx
);
6932 /* Simplify our comparison, if possible. */
6933 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6935 #ifdef SELECT_CC_MODE
6936 /* If this machine has CC modes other than CCmode, check to see if we
6937 need to use a different CC mode here. */
6938 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6939 compare_mode
= GET_MODE (op0
);
6940 else if (inner_compare
6941 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6942 && new_code
== old_code
6943 && op0
== XEXP (inner_compare
, 0)
6944 && op1
== XEXP (inner_compare
, 1))
6945 compare_mode
= GET_MODE (inner_compare
);
6947 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6949 /* If the mode changed, we have to change SET_DEST, the mode in the
6950 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6951 a hard register, just build new versions with the proper mode. If it
6952 is a pseudo, we lose unless it is only time we set the pseudo, in
6953 which case we can safely change its mode. */
6954 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6956 if (can_change_dest_mode (dest
, 0, compare_mode
))
6958 unsigned int regno
= REGNO (dest
);
6961 if (regno
< FIRST_PSEUDO_REGISTER
)
6962 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6965 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6966 new_dest
= regno_reg_rtx
[regno
];
6969 SUBST (SET_DEST (x
), new_dest
);
6970 SUBST (XEXP (*cc_use
, 0), new_dest
);
6976 #endif /* SELECT_CC_MODE */
6978 /* If the code changed, we have to build a new comparison in
6979 undobuf.other_insn. */
6980 if (new_code
!= old_code
)
6982 int other_changed_previously
= other_changed
;
6983 unsigned HOST_WIDE_INT mask
;
6984 rtx old_cc_use
= *cc_use
;
6986 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6990 /* If the only change we made was to change an EQ into an NE or
6991 vice versa, OP0 has only one bit that might be nonzero, and OP1
6992 is zero, check if changing the user of the condition code will
6993 produce a valid insn. If it won't, we can keep the original code
6994 in that insn by surrounding our operation with an XOR. */
6996 if (((old_code
== NE
&& new_code
== EQ
)
6997 || (old_code
== EQ
&& new_code
== NE
))
6998 && ! other_changed_previously
&& op1
== const0_rtx
6999 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
7000 && pow2p_hwi (mask
= nonzero_bits (op0
, GET_MODE (op0
))))
7002 rtx pat
= PATTERN (other_insn
), note
= 0;
7004 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
7005 && ! check_asm_operands (pat
)))
7007 *cc_use
= old_cc_use
;
7010 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
7018 undobuf
.other_insn
= other_insn
;
7020 /* Don't generate a compare of a CC with 0, just use that CC. */
7021 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
7023 SUBST (SET_SRC (x
), op0
);
7026 /* Otherwise, if we didn't previously have the same COMPARE we
7027 want, create it from scratch. */
7028 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
7029 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
7031 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
7037 /* Get SET_SRC in a form where we have placed back any
7038 compound expressions. Then do the checks below. */
7039 src
= make_compound_operation (src
, SET
);
7040 SUBST (SET_SRC (x
), src
);
7043 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
7044 and X being a REG or (subreg (reg)), we may be able to convert this to
7045 (set (subreg:m2 x) (op)).
7047 We can always do this if M1 is narrower than M2 because that means that
7048 we only care about the low bits of the result.
7050 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
7051 perform a narrower operation than requested since the high-order bits will
7052 be undefined. On machine where it is defined, this transformation is safe
7053 as long as M1 and M2 have the same number of words. */
7055 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
7056 && !OBJECT_P (SUBREG_REG (src
))
7057 && (known_equal_after_align_up
7058 (GET_MODE_SIZE (GET_MODE (src
)),
7059 GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))),
7061 && (WORD_REGISTER_OPERATIONS
|| !paradoxical_subreg_p (src
))
7062 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
7063 && !REG_CAN_CHANGE_MODE_P (REGNO (dest
),
7064 GET_MODE (SUBREG_REG (src
)),
7067 || (GET_CODE (dest
) == SUBREG
7068 && REG_P (SUBREG_REG (dest
)))))
7070 SUBST (SET_DEST (x
),
7071 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
7073 SUBST (SET_SRC (x
), SUBREG_REG (src
));
7075 src
= SET_SRC (x
), dest
= SET_DEST (x
);
7078 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
7081 && partial_subreg_p (src
)
7082 && subreg_lowpart_p (src
))
7084 rtx inner
= SUBREG_REG (src
);
7085 machine_mode inner_mode
= GET_MODE (inner
);
7087 /* Here we make sure that we don't have a sign bit on. */
7088 if (val_signbit_known_clear_p (GET_MODE (src
),
7089 nonzero_bits (inner
, inner_mode
)))
7091 SUBST (SET_SRC (x
), inner
);
7096 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
7097 would require a paradoxical subreg. Replace the subreg with a
7098 zero_extend to avoid the reload that would otherwise be required.
7099 Don't do this unless we have a scalar integer mode, otherwise the
7100 transformation is incorrect. */
7102 enum rtx_code extend_op
;
7103 if (paradoxical_subreg_p (src
)
7104 && MEM_P (SUBREG_REG (src
))
7105 && SCALAR_INT_MODE_P (GET_MODE (src
))
7106 && (extend_op
= load_extend_op (GET_MODE (SUBREG_REG (src
)))) != UNKNOWN
)
7109 gen_rtx_fmt_e (extend_op
, GET_MODE (src
), SUBREG_REG (src
)));
7114 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7115 are comparing an item known to be 0 or -1 against 0, use a logical
7116 operation instead. Check for one of the arms being an IOR of the other
7117 arm with some value. We compute three terms to be IOR'ed together. In
7118 practice, at most two will be nonzero. Then we do the IOR's. */
7120 if (GET_CODE (dest
) != PC
7121 && GET_CODE (src
) == IF_THEN_ELSE
7122 && is_int_mode (GET_MODE (src
), &int_mode
)
7123 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
7124 && XEXP (XEXP (src
, 0), 1) == const0_rtx
7125 && int_mode
== GET_MODE (XEXP (XEXP (src
, 0), 0))
7126 && (!HAVE_conditional_move
7127 || ! can_conditionally_move_p (int_mode
))
7128 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0), int_mode
)
7129 == GET_MODE_PRECISION (int_mode
))
7130 && ! side_effects_p (src
))
7132 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
7133 ? XEXP (src
, 1) : XEXP (src
, 2));
7134 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
7135 ? XEXP (src
, 2) : XEXP (src
, 1));
7136 rtx term1
= const0_rtx
, term2
, term3
;
7138 if (GET_CODE (true_rtx
) == IOR
7139 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
7140 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
7141 else if (GET_CODE (true_rtx
) == IOR
7142 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
7143 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
7144 else if (GET_CODE (false_rtx
) == IOR
7145 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
7146 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
7147 else if (GET_CODE (false_rtx
) == IOR
7148 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
7149 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
7151 term2
= simplify_gen_binary (AND
, int_mode
,
7152 XEXP (XEXP (src
, 0), 0), true_rtx
);
7153 term3
= simplify_gen_binary (AND
, int_mode
,
7154 simplify_gen_unary (NOT
, int_mode
,
7155 XEXP (XEXP (src
, 0), 0),
7160 simplify_gen_binary (IOR
, int_mode
,
7161 simplify_gen_binary (IOR
, int_mode
,
7168 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7169 whole thing fail. */
7170 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
7172 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
7175 /* Convert this into a field assignment operation, if possible. */
7176 return make_field_assignment (x
);
7179 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7183 simplify_logical (rtx x
)
7185 rtx op0
= XEXP (x
, 0);
7186 rtx op1
= XEXP (x
, 1);
7187 scalar_int_mode mode
;
7189 switch (GET_CODE (x
))
7192 /* We can call simplify_and_const_int only if we don't lose
7193 any (sign) bits when converting INTVAL (op1) to
7194 "unsigned HOST_WIDE_INT". */
7195 if (is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
)
7196 && CONST_INT_P (op1
)
7197 && (HWI_COMPUTABLE_MODE_P (mode
)
7198 || INTVAL (op1
) > 0))
7200 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
7201 if (GET_CODE (x
) != AND
)
7208 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7209 apply the distributive law and then the inverse distributive
7210 law to see if things simplify. */
7211 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
7213 rtx result
= distribute_and_simplify_rtx (x
, 0);
7217 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
7219 rtx result
= distribute_and_simplify_rtx (x
, 1);
7226 /* If we have (ior (and A B) C), apply the distributive law and then
7227 the inverse distributive law to see if things simplify. */
7229 if (GET_CODE (op0
) == AND
)
7231 rtx result
= distribute_and_simplify_rtx (x
, 0);
7236 if (GET_CODE (op1
) == AND
)
7238 rtx result
= distribute_and_simplify_rtx (x
, 1);
7251 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7252 operations" because they can be replaced with two more basic operations.
7253 ZERO_EXTEND is also considered "compound" because it can be replaced with
7254 an AND operation, which is simpler, though only one operation.
7256 The function expand_compound_operation is called with an rtx expression
7257 and will convert it to the appropriate shifts and AND operations,
7258 simplifying at each stage.
7260 The function make_compound_operation is called to convert an expression
7261 consisting of shifts and ANDs into the equivalent compound expression.
7262 It is the inverse of this function, loosely speaking. */
7265 expand_compound_operation (rtx x
)
7267 unsigned HOST_WIDE_INT pos
= 0, len
;
7269 unsigned int modewidth
;
7271 scalar_int_mode inner_mode
;
7273 switch (GET_CODE (x
))
7279 /* We can't necessarily use a const_int for a multiword mode;
7280 it depends on implicitly extending the value.
7281 Since we don't know the right way to extend it,
7282 we can't tell whether the implicit way is right.
7284 Even for a mode that is no wider than a const_int,
7285 we can't win, because we need to sign extend one of its bits through
7286 the rest of it, and we don't know which bit. */
7287 if (CONST_INT_P (XEXP (x
, 0)))
7290 /* Reject modes that aren't scalar integers because turning vector
7291 or complex modes into shifts causes problems. */
7292 if (!is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
7295 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7296 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7297 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7298 reloaded. If not for that, MEM's would very rarely be safe.
7300 Reject modes bigger than a word, because we might not be able
7301 to reference a two-register group starting with an arbitrary register
7302 (and currently gen_lowpart might crash for a SUBREG). */
7304 if (GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7307 len
= GET_MODE_PRECISION (inner_mode
);
7308 /* If the inner object has VOIDmode (the only way this can happen
7309 is if it is an ASM_OPERANDS), we can't do anything since we don't
7310 know how much masking to do. */
7322 /* If the operand is a CLOBBER, just return it. */
7323 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7326 if (!CONST_INT_P (XEXP (x
, 1))
7327 || !CONST_INT_P (XEXP (x
, 2)))
7330 /* Reject modes that aren't scalar integers because turning vector
7331 or complex modes into shifts causes problems. */
7332 if (!is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
7335 len
= INTVAL (XEXP (x
, 1));
7336 pos
= INTVAL (XEXP (x
, 2));
7338 /* This should stay within the object being extracted, fail otherwise. */
7339 if (len
+ pos
> GET_MODE_PRECISION (inner_mode
))
7342 if (BITS_BIG_ENDIAN
)
7343 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
7351 /* We've rejected non-scalar operations by now. */
7352 scalar_int_mode mode
= as_a
<scalar_int_mode
> (GET_MODE (x
));
7354 /* Convert sign extension to zero extension, if we know that the high
7355 bit is not set, as this is easier to optimize. It will be converted
7356 back to cheaper alternative in make_extraction. */
7357 if (GET_CODE (x
) == SIGN_EXTEND
7358 && HWI_COMPUTABLE_MODE_P (mode
)
7359 && ((nonzero_bits (XEXP (x
, 0), inner_mode
)
7360 & ~(((unsigned HOST_WIDE_INT
) GET_MODE_MASK (inner_mode
)) >> 1))
7363 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, XEXP (x
, 0));
7364 rtx temp2
= expand_compound_operation (temp
);
7366 /* Make sure this is a profitable operation. */
7367 if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7368 > set_src_cost (temp2
, mode
, optimize_this_for_speed_p
))
7370 else if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7371 > set_src_cost (temp
, mode
, optimize_this_for_speed_p
))
7377 /* We can optimize some special cases of ZERO_EXTEND. */
7378 if (GET_CODE (x
) == ZERO_EXTEND
)
7380 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7381 know that the last value didn't have any inappropriate bits
7383 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7384 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
7385 && HWI_COMPUTABLE_MODE_P (mode
)
7386 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
)
7387 & ~GET_MODE_MASK (inner_mode
)) == 0)
7388 return XEXP (XEXP (x
, 0), 0);
7390 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7391 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7392 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
7393 && subreg_lowpart_p (XEXP (x
, 0))
7394 && HWI_COMPUTABLE_MODE_P (mode
)
7395 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), mode
)
7396 & ~GET_MODE_MASK (inner_mode
)) == 0)
7397 return SUBREG_REG (XEXP (x
, 0));
7399 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7400 is a comparison and STORE_FLAG_VALUE permits. This is like
7401 the first case, but it works even when MODE is larger
7402 than HOST_WIDE_INT. */
7403 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7404 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
7405 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7406 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
7407 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (inner_mode
)) == 0)
7408 return XEXP (XEXP (x
, 0), 0);
7410 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7411 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7412 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
7413 && subreg_lowpart_p (XEXP (x
, 0))
7414 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7415 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
7416 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (inner_mode
)) == 0)
7417 return SUBREG_REG (XEXP (x
, 0));
7421 /* If we reach here, we want to return a pair of shifts. The inner
7422 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7423 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7424 logical depending on the value of UNSIGNEDP.
7426 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7427 converted into an AND of a shift.
7429 We must check for the case where the left shift would have a negative
7430 count. This can happen in a case like (x >> 31) & 255 on machines
7431 that can't shift by a constant. On those machines, we would first
7432 combine the shift with the AND to produce a variable-position
7433 extraction. Then the constant of 31 would be substituted in
7434 to produce such a position. */
7436 modewidth
= GET_MODE_PRECISION (mode
);
7437 if (modewidth
>= pos
+ len
)
7439 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7440 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7442 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7443 tem
, modewidth
- pos
- len
);
7444 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7445 mode
, tem
, modewidth
- len
);
7447 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7448 tem
= simplify_and_const_int (NULL_RTX
, mode
,
7449 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7452 (HOST_WIDE_INT_1U
<< len
) - 1);
7454 /* Any other cases we can't handle. */
7457 /* If we couldn't do this for some reason, return the original
7459 if (GET_CODE (tem
) == CLOBBER
)
7465 /* X is a SET which contains an assignment of one object into
7466 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7467 or certain SUBREGS). If possible, convert it into a series of
7470 We half-heartedly support variable positions, but do not at all
7471 support variable lengths. */
7474 expand_field_assignment (const_rtx x
)
7477 rtx pos
; /* Always counts from low bit. */
7479 rtx mask
, cleared
, masked
;
7480 scalar_int_mode compute_mode
;
7482 /* Loop until we find something we can't simplify. */
7485 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7486 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7488 rtx x0
= XEXP (SET_DEST (x
), 0);
7489 if (!GET_MODE_PRECISION (GET_MODE (x0
)).is_constant (&len
))
7491 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7492 pos
= gen_int_mode (subreg_lsb (XEXP (SET_DEST (x
), 0)),
7495 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7496 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7498 inner
= XEXP (SET_DEST (x
), 0);
7499 if (!GET_MODE_PRECISION (GET_MODE (inner
)).is_constant (&inner_len
))
7502 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7503 pos
= XEXP (SET_DEST (x
), 2);
7505 /* A constant position should stay within the width of INNER. */
7506 if (CONST_INT_P (pos
) && INTVAL (pos
) + len
> inner_len
)
7509 if (BITS_BIG_ENDIAN
)
7511 if (CONST_INT_P (pos
))
7512 pos
= GEN_INT (inner_len
- len
- INTVAL (pos
));
7513 else if (GET_CODE (pos
) == MINUS
7514 && CONST_INT_P (XEXP (pos
, 1))
7515 && INTVAL (XEXP (pos
, 1)) == inner_len
- len
)
7516 /* If position is ADJUST - X, new position is X. */
7517 pos
= XEXP (pos
, 0);
7519 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7520 gen_int_mode (inner_len
- len
,
7526 /* If the destination is a subreg that overwrites the whole of the inner
7527 register, we can move the subreg to the source. */
7528 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7529 /* We need SUBREGs to compute nonzero_bits properly. */
7530 && nonzero_sign_valid
7531 && !read_modify_subreg_p (SET_DEST (x
)))
7533 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7535 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7542 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7543 inner
= SUBREG_REG (inner
);
7545 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7546 if (!is_a
<scalar_int_mode
> (GET_MODE (inner
), &compute_mode
))
7548 /* Don't do anything for vector or complex integral types. */
7549 if (! FLOAT_MODE_P (GET_MODE (inner
)))
7552 /* Try to find an integral mode to pun with. */
7553 if (!int_mode_for_size (GET_MODE_BITSIZE (GET_MODE (inner
)), 0)
7554 .exists (&compute_mode
))
7557 inner
= gen_lowpart (compute_mode
, inner
);
7560 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7561 if (len
>= HOST_BITS_PER_WIDE_INT
)
7564 /* Don't try to compute in too wide unsupported modes. */
7565 if (!targetm
.scalar_mode_supported_p (compute_mode
))
7568 /* Now compute the equivalent expression. Make a copy of INNER
7569 for the SET_DEST in case it is a MEM into which we will substitute;
7570 we don't want shared RTL in that case. */
7571 mask
= gen_int_mode ((HOST_WIDE_INT_1U
<< len
) - 1,
7573 cleared
= simplify_gen_binary (AND
, compute_mode
,
7574 simplify_gen_unary (NOT
, compute_mode
,
7575 simplify_gen_binary (ASHIFT
,
7580 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7581 simplify_gen_binary (
7583 gen_lowpart (compute_mode
, SET_SRC (x
)),
7587 x
= gen_rtx_SET (copy_rtx (inner
),
7588 simplify_gen_binary (IOR
, compute_mode
,
7595 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7596 it is an RTX that represents the (variable) starting position; otherwise,
7597 POS is the (constant) starting bit position. Both are counted from the LSB.
7599 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7601 IN_DEST is nonzero if this is a reference in the destination of a SET.
7602 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7603 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7606 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7607 ZERO_EXTRACT should be built even for bits starting at bit 0.
7609 MODE is the desired mode of the result (if IN_DEST == 0).
7611 The result is an RTX for the extraction or NULL_RTX if the target
7615 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7616 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7617 int in_dest
, int in_compare
)
7619 /* This mode describes the size of the storage area
7620 to fetch the overall value from. Within that, we
7621 ignore the POS lowest bits, etc. */
7622 machine_mode is_mode
= GET_MODE (inner
);
7623 machine_mode inner_mode
;
7624 scalar_int_mode wanted_inner_mode
;
7625 scalar_int_mode wanted_inner_reg_mode
= word_mode
;
7626 scalar_int_mode pos_mode
= word_mode
;
7627 machine_mode extraction_mode
= word_mode
;
7629 rtx orig_pos_rtx
= pos_rtx
;
7630 HOST_WIDE_INT orig_pos
;
7632 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7633 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7635 if (GET_CODE (inner
) == SUBREG
7636 && subreg_lowpart_p (inner
)
7637 && (paradoxical_subreg_p (inner
)
7638 /* If trying or potentionally trying to extract
7639 bits outside of is_mode, don't look through
7640 non-paradoxical SUBREGs. See PR82192. */
7641 || (pos_rtx
== NULL_RTX
7642 && known_le (pos
+ len
, GET_MODE_PRECISION (is_mode
)))))
7644 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7645 consider just the QI as the memory to extract from.
7646 The subreg adds or removes high bits; its mode is
7647 irrelevant to the meaning of this extraction,
7648 since POS and LEN count from the lsb. */
7649 if (MEM_P (SUBREG_REG (inner
)))
7650 is_mode
= GET_MODE (SUBREG_REG (inner
));
7651 inner
= SUBREG_REG (inner
);
7653 else if (GET_CODE (inner
) == ASHIFT
7654 && CONST_INT_P (XEXP (inner
, 1))
7655 && pos_rtx
== 0 && pos
== 0
7656 && len
> UINTVAL (XEXP (inner
, 1)))
7658 /* We're extracting the least significant bits of an rtx
7659 (ashift X (const_int C)), where LEN > C. Extract the
7660 least significant (LEN - C) bits of X, giving an rtx
7661 whose mode is MODE, then shift it left C times. */
7662 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7663 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7664 unsignedp
, in_dest
, in_compare
);
7666 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7668 else if (GET_CODE (inner
) == TRUNCATE
7669 /* If trying or potentionally trying to extract
7670 bits outside of is_mode, don't look through
7671 TRUNCATE. See PR82192. */
7672 && pos_rtx
== NULL_RTX
7673 && known_le (pos
+ len
, GET_MODE_PRECISION (is_mode
)))
7674 inner
= XEXP (inner
, 0);
7676 inner_mode
= GET_MODE (inner
);
7678 /* See if this can be done without an extraction. We never can if the
7679 width of the field is not the same as that of some integer mode. For
7680 registers, we can only avoid the extraction if the position is at the
7681 low-order bit and this is either not in the destination or we have the
7682 appropriate STRICT_LOW_PART operation available.
7684 For MEM, we can avoid an extract if the field starts on an appropriate
7685 boundary and we can change the mode of the memory reference. */
7687 scalar_int_mode tmode
;
7688 if (int_mode_for_size (len
, 1).exists (&tmode
)
7689 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7691 && (pos
== 0 || REG_P (inner
))
7692 && (inner_mode
== tmode
7694 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7695 || reg_truncated_to_mode (tmode
, inner
))
7698 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7699 || (MEM_P (inner
) && pos_rtx
== 0
7701 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7702 : BITS_PER_UNIT
)) == 0
7703 /* We can't do this if we are widening INNER_MODE (it
7704 may not be aligned, for one thing). */
7705 && !paradoxical_subreg_p (tmode
, inner_mode
)
7706 && known_le (pos
+ len
, GET_MODE_PRECISION (is_mode
))
7707 && (inner_mode
== tmode
7708 || (! mode_dependent_address_p (XEXP (inner
, 0),
7709 MEM_ADDR_SPACE (inner
))
7710 && ! MEM_VOLATILE_P (inner
))))))
7712 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7713 field. If the original and current mode are the same, we need not
7714 adjust the offset. Otherwise, we do if bytes big endian.
7716 If INNER is not a MEM, get a piece consisting of just the field
7717 of interest (in this case POS % BITS_PER_WORD must be 0). */
7723 /* POS counts from lsb, but make OFFSET count in memory order. */
7724 if (BYTES_BIG_ENDIAN
)
7725 offset
= bits_to_bytes_round_down (GET_MODE_PRECISION (is_mode
)
7728 offset
= pos
/ BITS_PER_UNIT
;
7730 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7732 else if (REG_P (inner
))
7734 if (tmode
!= inner_mode
)
7736 /* We can't call gen_lowpart in a DEST since we
7737 always want a SUBREG (see below) and it would sometimes
7738 return a new hard register. */
7742 = subreg_offset_from_lsb (tmode
, inner_mode
, pos
);
7744 /* Avoid creating invalid subregs, for example when
7745 simplifying (x>>32)&255. */
7746 if (!validate_subreg (tmode
, inner_mode
, inner
, offset
))
7749 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, offset
);
7752 new_rtx
= gen_lowpart (tmode
, inner
);
7758 new_rtx
= force_to_mode (inner
, tmode
,
7759 len
>= HOST_BITS_PER_WIDE_INT
7761 : (HOST_WIDE_INT_1U
<< len
) - 1, 0);
7763 /* If this extraction is going into the destination of a SET,
7764 make a STRICT_LOW_PART unless we made a MEM. */
7767 return (MEM_P (new_rtx
) ? new_rtx
7768 : (GET_CODE (new_rtx
) != SUBREG
7769 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7770 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7775 if (CONST_SCALAR_INT_P (new_rtx
))
7776 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7777 mode
, new_rtx
, tmode
);
7779 /* If we know that no extraneous bits are set, and that the high
7780 bit is not set, convert the extraction to the cheaper of
7781 sign and zero extension, that are equivalent in these cases. */
7782 if (flag_expensive_optimizations
7783 && (HWI_COMPUTABLE_MODE_P (tmode
)
7784 && ((nonzero_bits (new_rtx
, tmode
)
7785 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7788 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7789 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7791 /* Prefer ZERO_EXTENSION, since it gives more information to
7793 if (set_src_cost (temp
, mode
, optimize_this_for_speed_p
)
7794 <= set_src_cost (temp1
, mode
, optimize_this_for_speed_p
))
7799 /* Otherwise, sign- or zero-extend unless we already are in the
7802 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7806 /* Unless this is a COMPARE or we have a funny memory reference,
7807 don't do anything with zero-extending field extracts starting at
7808 the low-order bit since they are simple AND operations. */
7809 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7810 && ! in_compare
&& unsignedp
)
7813 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7814 if the position is not a constant and the length is not 1. In all
7815 other cases, we would only be going outside our object in cases when
7816 an original shift would have been undefined. */
7818 && ((pos_rtx
== 0 && maybe_gt (pos
+ len
, GET_MODE_PRECISION (is_mode
)))
7819 || (pos_rtx
!= 0 && len
!= 1)))
7822 enum extraction_pattern pattern
= (in_dest
? EP_insv
7823 : unsignedp
? EP_extzv
: EP_extv
);
7825 /* If INNER is not from memory, we want it to have the mode of a register
7826 extraction pattern's structure operand, or word_mode if there is no
7827 such pattern. The same applies to extraction_mode and pos_mode
7828 and their respective operands.
7830 For memory, assume that the desired extraction_mode and pos_mode
7831 are the same as for a register operation, since at present we don't
7832 have named patterns for aligned memory structures. */
7833 class extraction_insn insn
;
7834 unsigned int inner_size
;
7835 if (GET_MODE_BITSIZE (inner_mode
).is_constant (&inner_size
)
7836 && get_best_reg_extraction_insn (&insn
, pattern
, inner_size
, mode
))
7838 wanted_inner_reg_mode
= insn
.struct_mode
.require ();
7839 pos_mode
= insn
.pos_mode
;
7840 extraction_mode
= insn
.field_mode
;
7843 /* Never narrow an object, since that might not be safe. */
7845 if (mode
!= VOIDmode
7846 && partial_subreg_p (extraction_mode
, mode
))
7847 extraction_mode
= mode
;
7849 /* Punt if len is too large for extraction_mode. */
7850 if (maybe_gt (len
, GET_MODE_PRECISION (extraction_mode
)))
7854 wanted_inner_mode
= wanted_inner_reg_mode
;
7857 /* Be careful not to go beyond the extracted object and maintain the
7858 natural alignment of the memory. */
7859 wanted_inner_mode
= smallest_int_mode_for_size (len
);
7860 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7861 > GET_MODE_BITSIZE (wanted_inner_mode
))
7862 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
).require ();
7867 if (BITS_BIG_ENDIAN
)
7869 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7870 BITS_BIG_ENDIAN style. If position is constant, compute new
7871 position. Otherwise, build subtraction.
7872 Note that POS is relative to the mode of the original argument.
7873 If it's a MEM we need to recompute POS relative to that.
7874 However, if we're extracting from (or inserting into) a register,
7875 we want to recompute POS relative to wanted_inner_mode. */
7878 width
= GET_MODE_BITSIZE (wanted_inner_mode
);
7879 else if (!GET_MODE_BITSIZE (is_mode
).is_constant (&width
))
7883 pos
= width
- len
- pos
;
7886 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7887 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7889 /* POS may be less than 0 now, but we check for that below.
7890 Note that it can only be less than 0 if !MEM_P (inner). */
7893 /* If INNER has a wider mode, and this is a constant extraction, try to
7894 make it smaller and adjust the byte to point to the byte containing
7896 if (wanted_inner_mode
!= VOIDmode
7897 && inner_mode
!= wanted_inner_mode
7899 && partial_subreg_p (wanted_inner_mode
, is_mode
)
7901 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7902 && ! MEM_VOLATILE_P (inner
))
7904 poly_int64 offset
= 0;
7906 /* The computations below will be correct if the machine is big
7907 endian in both bits and bytes or little endian in bits and bytes.
7908 If it is mixed, we must adjust. */
7910 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7911 adjust OFFSET to compensate. */
7912 if (BYTES_BIG_ENDIAN
7913 && paradoxical_subreg_p (is_mode
, inner_mode
))
7914 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7916 /* We can now move to the desired byte. */
7917 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7918 * GET_MODE_SIZE (wanted_inner_mode
);
7919 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7921 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7922 && is_mode
!= wanted_inner_mode
)
7923 offset
= (GET_MODE_SIZE (is_mode
)
7924 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7926 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7929 /* If INNER is not memory, get it into the proper mode. If we are changing
7930 its mode, POS must be a constant and smaller than the size of the new
7932 else if (!MEM_P (inner
))
7934 /* On the LHS, don't create paradoxical subregs implicitely truncating
7935 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7937 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7941 if (GET_MODE (inner
) != wanted_inner_mode
7943 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7949 inner
= force_to_mode (inner
, wanted_inner_mode
,
7951 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7953 : (((HOST_WIDE_INT_1U
<< len
) - 1)
7958 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7959 have to zero extend. Otherwise, we can just use a SUBREG.
7961 We dealt with constant rtxes earlier, so pos_rtx cannot
7962 have VOIDmode at this point. */
7964 && (GET_MODE_SIZE (pos_mode
)
7965 > GET_MODE_SIZE (as_a
<scalar_int_mode
> (GET_MODE (pos_rtx
)))))
7967 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7968 GET_MODE (pos_rtx
));
7970 /* If we know that no extraneous bits are set, and that the high
7971 bit is not set, convert extraction to cheaper one - either
7972 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7974 if (flag_expensive_optimizations
7975 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7976 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7977 & ~(((unsigned HOST_WIDE_INT
)
7978 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7982 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7983 GET_MODE (pos_rtx
));
7985 /* Prefer ZERO_EXTENSION, since it gives more information to
7987 if (set_src_cost (temp1
, pos_mode
, optimize_this_for_speed_p
)
7988 < set_src_cost (temp
, pos_mode
, optimize_this_for_speed_p
))
7994 /* Make POS_RTX unless we already have it and it is correct. If we don't
7995 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7997 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7998 pos_rtx
= orig_pos_rtx
;
8000 else if (pos_rtx
== 0)
8001 pos_rtx
= GEN_INT (pos
);
8003 /* Make the required operation. See if we can use existing rtx. */
8004 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
8005 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
8007 new_rtx
= gen_lowpart (mode
, new_rtx
);
8012 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
8013 can be commuted with any other operations in X. Return X without
8014 that shift if so. */
8017 extract_left_shift (scalar_int_mode mode
, rtx x
, int count
)
8019 enum rtx_code code
= GET_CODE (x
);
8025 /* This is the shift itself. If it is wide enough, we will return
8026 either the value being shifted if the shift count is equal to
8027 COUNT or a shift for the difference. */
8028 if (CONST_INT_P (XEXP (x
, 1))
8029 && INTVAL (XEXP (x
, 1)) >= count
)
8030 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
8031 INTVAL (XEXP (x
, 1)) - count
);
8035 if ((tem
= extract_left_shift (mode
, XEXP (x
, 0), count
)) != 0)
8036 return simplify_gen_unary (code
, mode
, tem
, mode
);
8040 case PLUS
: case IOR
: case XOR
: case AND
:
8041 /* If we can safely shift this constant and we find the inner shift,
8042 make a new operation. */
8043 if (CONST_INT_P (XEXP (x
, 1))
8044 && (UINTVAL (XEXP (x
, 1))
8045 & (((HOST_WIDE_INT_1U
<< count
)) - 1)) == 0
8046 && (tem
= extract_left_shift (mode
, XEXP (x
, 0), count
)) != 0)
8048 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
8049 return simplify_gen_binary (code
, mode
, tem
,
8050 gen_int_mode (val
, mode
));
8061 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
8062 level of the expression and MODE is its mode. IN_CODE is as for
8063 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
8064 that should be used when recursing on operands of *X_PTR.
8066 There are two possible actions:
8068 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
8069 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
8071 - Return a new rtx, which the caller returns directly. */
8074 make_compound_operation_int (scalar_int_mode mode
, rtx
*x_ptr
,
8075 enum rtx_code in_code
,
8076 enum rtx_code
*next_code_ptr
)
8079 enum rtx_code next_code
= *next_code_ptr
;
8080 enum rtx_code code
= GET_CODE (x
);
8081 int mode_width
= GET_MODE_PRECISION (mode
);
8086 scalar_int_mode inner_mode
;
8087 bool equality_comparison
= false;
8091 equality_comparison
= true;
8095 /* Process depending on the code of this operation. If NEW is set
8096 nonzero, it will be returned. */
8101 /* Convert shifts by constants into multiplications if inside
8103 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
8104 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8105 && INTVAL (XEXP (x
, 1)) >= 0)
8107 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
8108 HOST_WIDE_INT multval
= HOST_WIDE_INT_1
<< count
;
8110 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8111 if (GET_CODE (new_rtx
) == NEG
)
8113 new_rtx
= XEXP (new_rtx
, 0);
8116 multval
= trunc_int_for_mode (multval
, mode
);
8117 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
8124 lhs
= make_compound_operation (lhs
, next_code
);
8125 rhs
= make_compound_operation (rhs
, next_code
);
8126 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
)
8128 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
8130 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
8132 else if (GET_CODE (lhs
) == MULT
8133 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
8135 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
8136 simplify_gen_unary (NEG
, mode
,
8139 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
8143 SUBST (XEXP (x
, 0), lhs
);
8144 SUBST (XEXP (x
, 1), rhs
);
8146 maybe_swap_commutative_operands (x
);
8152 lhs
= make_compound_operation (lhs
, next_code
);
8153 rhs
= make_compound_operation (rhs
, next_code
);
8154 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
)
8156 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
8158 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8160 else if (GET_CODE (rhs
) == MULT
8161 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
8163 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
8164 simplify_gen_unary (NEG
, mode
,
8167 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8171 SUBST (XEXP (x
, 0), lhs
);
8172 SUBST (XEXP (x
, 1), rhs
);
8177 /* If the second operand is not a constant, we can't do anything
8179 if (!CONST_INT_P (XEXP (x
, 1)))
8182 /* If the constant is a power of two minus one and the first operand
8183 is a logical right shift, make an extraction. */
8184 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8185 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8187 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8188 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1),
8189 i
, 1, 0, in_code
== COMPARE
);
8192 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8193 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
8194 && subreg_lowpart_p (XEXP (x
, 0))
8195 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (XEXP (x
, 0))),
8197 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
8198 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8200 rtx inner_x0
= SUBREG_REG (XEXP (x
, 0));
8201 new_rtx
= make_compound_operation (XEXP (inner_x0
, 0), next_code
);
8202 new_rtx
= make_extraction (inner_mode
, new_rtx
, 0,
8204 i
, 1, 0, in_code
== COMPARE
);
8206 /* If we narrowed the mode when dropping the subreg, then we lose. */
8207 if (GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (mode
))
8210 /* If that didn't give anything, see if the AND simplifies on
8212 if (!new_rtx
&& i
>= 0)
8214 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8215 new_rtx
= make_extraction (mode
, new_rtx
, 0, NULL_RTX
, i
, 1,
8216 0, in_code
== COMPARE
);
8219 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8220 else if ((GET_CODE (XEXP (x
, 0)) == XOR
8221 || GET_CODE (XEXP (x
, 0)) == IOR
)
8222 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
8223 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
8224 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8226 /* Apply the distributive law, and then try to make extractions. */
8227 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
8228 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
8230 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
8232 new_rtx
= make_compound_operation (new_rtx
, in_code
);
8235 /* If we are have (and (rotate X C) M) and C is larger than the number
8236 of bits in M, this is an extraction. */
8238 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
8239 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8240 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
8241 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
8243 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8244 new_rtx
= make_extraction (mode
, new_rtx
,
8245 (GET_MODE_PRECISION (mode
)
8246 - INTVAL (XEXP (XEXP (x
, 0), 1))),
8247 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8250 /* On machines without logical shifts, if the operand of the AND is
8251 a logical shift and our mask turns off all the propagated sign
8252 bits, we can replace the logical shift with an arithmetic shift. */
8253 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8254 && !have_insn_for (LSHIFTRT
, mode
)
8255 && have_insn_for (ASHIFTRT
, mode
)
8256 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8257 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8258 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8259 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8261 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8263 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
8264 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
8266 gen_rtx_ASHIFTRT (mode
,
8267 make_compound_operation (XEXP (XEXP (x
,
8271 XEXP (XEXP (x
, 0), 1)));
8274 /* If the constant is one less than a power of two, this might be
8275 representable by an extraction even if no shift is present.
8276 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8277 we are in a COMPARE. */
8278 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8279 new_rtx
= make_extraction (mode
,
8280 make_compound_operation (XEXP (x
, 0),
8282 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8284 /* If we are in a comparison and this is an AND with a power of two,
8285 convert this into the appropriate bit extract. */
8286 else if (in_code
== COMPARE
8287 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
8288 && (equality_comparison
|| i
< GET_MODE_PRECISION (mode
) - 1))
8289 new_rtx
= make_extraction (mode
,
8290 make_compound_operation (XEXP (x
, 0),
8292 i
, NULL_RTX
, 1, 1, 0, 1);
8294 /* If the one operand is a paradoxical subreg of a register or memory and
8295 the constant (limited to the smaller mode) has only zero bits where
8296 the sub expression has known zero bits, this can be expressed as
8298 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
)
8302 sub
= XEXP (XEXP (x
, 0), 0);
8303 machine_mode sub_mode
= GET_MODE (sub
);
8305 if ((REG_P (sub
) || MEM_P (sub
))
8306 && GET_MODE_PRECISION (sub_mode
).is_constant (&sub_width
)
8307 && sub_width
< mode_width
)
8309 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (sub_mode
);
8310 unsigned HOST_WIDE_INT mask
;
8312 /* original AND constant with all the known zero bits set */
8313 mask
= UINTVAL (XEXP (x
, 1)) | (~nonzero_bits (sub
, sub_mode
));
8314 if ((mask
& mode_mask
) == mode_mask
)
8316 new_rtx
= make_compound_operation (sub
, next_code
);
8317 new_rtx
= make_extraction (mode
, new_rtx
, 0, 0, sub_width
,
8318 1, 0, in_code
== COMPARE
);
8326 /* If the sign bit is known to be zero, replace this with an
8327 arithmetic shift. */
8328 if (have_insn_for (ASHIFTRT
, mode
)
8329 && ! have_insn_for (LSHIFTRT
, mode
)
8330 && mode_width
<= HOST_BITS_PER_WIDE_INT
8331 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
8333 new_rtx
= gen_rtx_ASHIFTRT (mode
,
8334 make_compound_operation (XEXP (x
, 0),
8346 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8347 this is a SIGN_EXTRACT. */
8348 if (CONST_INT_P (rhs
)
8349 && GET_CODE (lhs
) == ASHIFT
8350 && CONST_INT_P (XEXP (lhs
, 1))
8351 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8352 && INTVAL (XEXP (lhs
, 1)) >= 0
8353 && INTVAL (rhs
) < mode_width
)
8355 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8356 new_rtx
= make_extraction (mode
, new_rtx
,
8357 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8358 NULL_RTX
, mode_width
- INTVAL (rhs
),
8359 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8363 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8364 If so, try to merge the shifts into a SIGN_EXTEND. We could
8365 also do this for some cases of SIGN_EXTRACT, but it doesn't
8366 seem worth the effort; the case checked for occurs on Alpha. */
8369 && ! (GET_CODE (lhs
) == SUBREG
8370 && (OBJECT_P (SUBREG_REG (lhs
))))
8371 && CONST_INT_P (rhs
)
8372 && INTVAL (rhs
) >= 0
8373 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8374 && INTVAL (rhs
) < mode_width
8375 && (new_rtx
= extract_left_shift (mode
, lhs
, INTVAL (rhs
))) != 0)
8376 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
,
8378 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8379 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8384 /* Call ourselves recursively on the inner expression. If we are
8385 narrowing the object and it has a different RTL code from
8386 what it originally did, do this SUBREG as a force_to_mode. */
8388 rtx inner
= SUBREG_REG (x
), simplified
;
8389 enum rtx_code subreg_code
= in_code
;
8391 /* If the SUBREG is masking of a logical right shift,
8392 make an extraction. */
8393 if (GET_CODE (inner
) == LSHIFTRT
8394 && is_a
<scalar_int_mode
> (GET_MODE (inner
), &inner_mode
)
8395 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (inner_mode
)
8396 && CONST_INT_P (XEXP (inner
, 1))
8397 && UINTVAL (XEXP (inner
, 1)) < GET_MODE_PRECISION (inner_mode
)
8398 && subreg_lowpart_p (x
))
8400 new_rtx
= make_compound_operation (XEXP (inner
, 0), next_code
);
8401 int width
= GET_MODE_PRECISION (inner_mode
)
8402 - INTVAL (XEXP (inner
, 1));
8403 if (width
> mode_width
)
8405 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (inner
, 1),
8406 width
, 1, 0, in_code
== COMPARE
);
8410 /* If in_code is COMPARE, it isn't always safe to pass it through
8411 to the recursive make_compound_operation call. */
8412 if (subreg_code
== COMPARE
8413 && (!subreg_lowpart_p (x
)
8414 || GET_CODE (inner
) == SUBREG
8415 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8416 is (const_int 0), rather than
8417 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8418 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8419 for non-equality comparisons against 0 is not equivalent
8420 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8421 || (GET_CODE (inner
) == AND
8422 && CONST_INT_P (XEXP (inner
, 1))
8423 && partial_subreg_p (x
)
8424 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8425 >= GET_MODE_BITSIZE (mode
) - 1)))
8428 tem
= make_compound_operation (inner
, subreg_code
);
8431 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8435 if (GET_CODE (tem
) != GET_CODE (inner
)
8436 && partial_subreg_p (x
)
8437 && subreg_lowpart_p (x
))
8440 = force_to_mode (tem
, mode
, HOST_WIDE_INT_M1U
, 0);
8442 /* If we have something other than a SUBREG, we might have
8443 done an expansion, so rerun ourselves. */
8444 if (GET_CODE (newer
) != SUBREG
)
8445 newer
= make_compound_operation (newer
, in_code
);
8447 /* force_to_mode can expand compounds. If it just re-expanded
8448 the compound, use gen_lowpart to convert to the desired
8450 if (rtx_equal_p (newer
, x
)
8451 /* Likewise if it re-expanded the compound only partially.
8452 This happens for SUBREG of ZERO_EXTRACT if they extract
8453 the same number of bits. */
8454 || (GET_CODE (newer
) == SUBREG
8455 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8456 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8457 && GET_CODE (inner
) == AND
8458 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8459 return gen_lowpart (GET_MODE (x
), tem
);
8474 *x_ptr
= gen_lowpart (mode
, new_rtx
);
8475 *next_code_ptr
= next_code
;
8479 /* Look at the expression rooted at X. Look for expressions
8480 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8481 Form these expressions.
8483 Return the new rtx, usually just X.
8485 Also, for machines like the VAX that don't have logical shift insns,
8486 try to convert logical to arithmetic shift operations in cases where
8487 they are equivalent. This undoes the canonicalizations to logical
8488 shifts done elsewhere.
8490 We try, as much as possible, to re-use rtl expressions to save memory.
8492 IN_CODE says what kind of expression we are processing. Normally, it is
8493 SET. In a memory address it is MEM. When processing the arguments of
8494 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8495 precisely it is an equality comparison against zero. */
8498 make_compound_operation (rtx x
, enum rtx_code in_code
)
8500 enum rtx_code code
= GET_CODE (x
);
8503 enum rtx_code next_code
;
8506 /* Select the code to be used in recursive calls. Once we are inside an
8507 address, we stay there. If we have a comparison, set to COMPARE,
8508 but once inside, go back to our default of SET. */
8510 next_code
= (code
== MEM
? MEM
8511 : ((code
== COMPARE
|| COMPARISON_P (x
))
8512 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
8513 : in_code
== COMPARE
|| in_code
== EQ
? SET
: in_code
);
8515 scalar_int_mode mode
;
8516 if (is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
))
8518 rtx new_rtx
= make_compound_operation_int (mode
, &x
, in_code
,
8522 code
= GET_CODE (x
);
8525 /* Now recursively process each operand of this operation. We need to
8526 handle ZERO_EXTEND specially so that we don't lose track of the
8528 if (code
== ZERO_EXTEND
)
8530 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8531 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8532 new_rtx
, GET_MODE (XEXP (x
, 0)));
8535 SUBST (XEXP (x
, 0), new_rtx
);
8539 fmt
= GET_RTX_FORMAT (code
);
8540 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8543 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8544 SUBST (XEXP (x
, i
), new_rtx
);
8546 else if (fmt
[i
] == 'E')
8547 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8549 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8550 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8553 maybe_swap_commutative_operands (x
);
8557 /* Given M see if it is a value that would select a field of bits
8558 within an item, but not the entire word. Return -1 if not.
8559 Otherwise, return the starting position of the field, where 0 is the
8562 *PLEN is set to the length of the field. */
8565 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8567 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8568 int pos
= m
? ctz_hwi (m
) : -1;
8572 /* Now shift off the low-order zero bits and see if we have a
8573 power of two minus 1. */
8574 len
= exact_log2 ((m
>> pos
) + 1);
8583 /* If X refers to a register that equals REG in value, replace these
8584 references with REG. */
8586 canon_reg_for_combine (rtx x
, rtx reg
)
8593 enum rtx_code code
= GET_CODE (x
);
8594 switch (GET_RTX_CLASS (code
))
8597 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8598 if (op0
!= XEXP (x
, 0))
8599 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8604 case RTX_COMM_ARITH
:
8605 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8606 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8607 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8608 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8612 case RTX_COMM_COMPARE
:
8613 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8614 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8615 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8616 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8617 GET_MODE (op0
), op0
, op1
);
8621 case RTX_BITFIELD_OPS
:
8622 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8623 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8624 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8625 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8626 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8627 GET_MODE (op0
), op0
, op1
, op2
);
8633 if (rtx_equal_p (get_last_value (reg
), x
)
8634 || rtx_equal_p (reg
, get_last_value (x
)))
8643 fmt
= GET_RTX_FORMAT (code
);
8645 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8648 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8649 if (op
!= XEXP (x
, i
))
8659 else if (fmt
[i
] == 'E')
8662 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8664 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8665 if (op
!= XVECEXP (x
, i
, j
))
8672 XVECEXP (x
, i
, j
) = op
;
8683 /* Return X converted to MODE. If the value is already truncated to
8684 MODE we can just return a subreg even though in the general case we
8685 would need an explicit truncation. */
8688 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8690 if (!CONST_INT_P (x
)
8691 && partial_subreg_p (mode
, GET_MODE (x
))
8692 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8693 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8695 /* Bit-cast X into an integer mode. */
8696 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8697 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)).require (), x
);
8698 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
).require (),
8702 return gen_lowpart (mode
, x
);
8705 /* See if X can be simplified knowing that we will only refer to it in
8706 MODE and will only refer to those bits that are nonzero in MASK.
8707 If other bits are being computed or if masking operations are done
8708 that select a superset of the bits in MASK, they can sometimes be
8711 Return a possibly simplified expression, but always convert X to
8712 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8714 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8715 are all off in X. This is used when X will be complemented, by either
8716 NOT, NEG, or XOR. */
8719 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8722 enum rtx_code code
= GET_CODE (x
);
8723 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8724 machine_mode op_mode
;
8725 unsigned HOST_WIDE_INT nonzero
;
8727 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8728 code below will do the wrong thing since the mode of such an
8729 expression is VOIDmode.
8731 Also do nothing if X is a CLOBBER; this can happen if X was
8732 the return value from a call to gen_lowpart. */
8733 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8736 /* We want to perform the operation in its present mode unless we know
8737 that the operation is valid in MODE, in which case we do the operation
8739 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8740 && have_insn_for (code
, mode
))
8741 ? mode
: GET_MODE (x
));
8743 /* It is not valid to do a right-shift in a narrower mode
8744 than the one it came in with. */
8745 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8746 && partial_subreg_p (mode
, GET_MODE (x
)))
8747 op_mode
= GET_MODE (x
);
8749 /* Truncate MASK to fit OP_MODE. */
8751 mask
&= GET_MODE_MASK (op_mode
);
8753 /* Determine what bits of X are guaranteed to be (non)zero. */
8754 nonzero
= nonzero_bits (x
, mode
);
8756 /* If none of the bits in X are needed, return a zero. */
8757 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8760 /* If X is a CONST_INT, return a new one. Do this here since the
8761 test below will fail. */
8762 if (CONST_INT_P (x
))
8764 if (SCALAR_INT_MODE_P (mode
))
8765 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8768 x
= GEN_INT (INTVAL (x
) & mask
);
8769 return gen_lowpart_common (mode
, x
);
8773 /* If X is narrower than MODE and we want all the bits in X's mode, just
8774 get X in the proper mode. */
8775 if (paradoxical_subreg_p (mode
, GET_MODE (x
))
8776 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8777 return gen_lowpart (mode
, x
);
8779 /* We can ignore the effect of a SUBREG if it narrows the mode or
8780 if the constant masks to zero all the bits the mode doesn't have. */
8781 if (GET_CODE (x
) == SUBREG
8782 && subreg_lowpart_p (x
)
8783 && (partial_subreg_p (x
)
8785 & GET_MODE_MASK (GET_MODE (x
))
8786 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))) == 0))
8787 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8789 scalar_int_mode int_mode
, xmode
;
8790 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
8791 && is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
8792 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8794 return force_int_to_mode (x
, int_mode
, xmode
,
8795 as_a
<scalar_int_mode
> (op_mode
),
8798 return gen_lowpart_or_truncate (mode
, x
);
8801 /* Subroutine of force_to_mode that handles cases in which both X and
8802 the result are scalar integers. MODE is the mode of the result,
8803 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8804 is preferred for simplified versions of X. The other arguments
8805 are as for force_to_mode. */
8808 force_int_to_mode (rtx x
, scalar_int_mode mode
, scalar_int_mode xmode
,
8809 scalar_int_mode op_mode
, unsigned HOST_WIDE_INT mask
,
8812 enum rtx_code code
= GET_CODE (x
);
8813 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8814 unsigned HOST_WIDE_INT fuller_mask
;
8816 poly_int64 const_op0
;
8818 /* When we have an arithmetic operation, or a shift whose count we
8819 do not know, we need to assume that all bits up to the highest-order
8820 bit in MASK will be needed. This is how we form such a mask. */
8821 if (mask
& (HOST_WIDE_INT_1U
<< (HOST_BITS_PER_WIDE_INT
- 1)))
8822 fuller_mask
= HOST_WIDE_INT_M1U
;
8824 fuller_mask
= ((HOST_WIDE_INT_1U
<< (floor_log2 (mask
) + 1))
8830 /* If X is a (clobber (const_int)), return it since we know we are
8831 generating something that won't match. */
8838 x
= expand_compound_operation (x
);
8839 if (GET_CODE (x
) != code
)
8840 return force_to_mode (x
, mode
, mask
, next_select
);
8844 /* Similarly for a truncate. */
8845 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8848 /* If this is an AND with a constant, convert it into an AND
8849 whose constant is the AND of that constant with MASK. If it
8850 remains an AND of MASK, delete it since it is redundant. */
8852 if (CONST_INT_P (XEXP (x
, 1)))
8854 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8855 mask
& INTVAL (XEXP (x
, 1)));
8858 /* If X is still an AND, see if it is an AND with a mask that
8859 is just some low-order bits. If so, and it is MASK, we don't
8862 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8863 && (INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (xmode
)) == mask
)
8866 /* If it remains an AND, try making another AND with the bits
8867 in the mode mask that aren't in MASK turned on. If the
8868 constant in the AND is wide enough, this might make a
8869 cheaper constant. */
8871 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8872 && GET_MODE_MASK (xmode
) != mask
8873 && HWI_COMPUTABLE_MODE_P (xmode
))
8875 unsigned HOST_WIDE_INT cval
8876 = UINTVAL (XEXP (x
, 1)) | (GET_MODE_MASK (xmode
) & ~mask
);
8879 y
= simplify_gen_binary (AND
, xmode
, XEXP (x
, 0),
8880 gen_int_mode (cval
, xmode
));
8881 if (set_src_cost (y
, xmode
, optimize_this_for_speed_p
)
8882 < set_src_cost (x
, xmode
, optimize_this_for_speed_p
))
8892 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8893 low-order bits (as in an alignment operation) and FOO is already
8894 aligned to that boundary, mask C1 to that boundary as well.
8895 This may eliminate that PLUS and, later, the AND. */
8898 unsigned int width
= GET_MODE_PRECISION (mode
);
8899 unsigned HOST_WIDE_INT smask
= mask
;
8901 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8902 number, sign extend it. */
8904 if (width
< HOST_BITS_PER_WIDE_INT
8905 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8906 smask
|= HOST_WIDE_INT_M1U
<< width
;
8908 if (CONST_INT_P (XEXP (x
, 1))
8909 && pow2p_hwi (- smask
)
8910 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8911 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8912 return force_to_mode (plus_constant (xmode
, XEXP (x
, 0),
8913 (INTVAL (XEXP (x
, 1)) & smask
)),
8914 mode
, smask
, next_select
);
8920 /* Substituting into the operands of a widening MULT is not likely to
8921 create RTL matching a machine insn. */
8923 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8924 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
8925 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
8926 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
8927 && REG_P (XEXP (XEXP (x
, 0), 0))
8928 && REG_P (XEXP (XEXP (x
, 1), 0)))
8929 return gen_lowpart_or_truncate (mode
, x
);
8931 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8932 most significant bit in MASK since carries from those bits will
8933 affect the bits we are interested in. */
8938 /* If X is (minus C Y) where C's least set bit is larger than any bit
8939 in the mask, then we may replace with (neg Y). */
8940 if (poly_int_rtx_p (XEXP (x
, 0), &const_op0
)
8941 && known_alignment (poly_uint64 (const_op0
)) > mask
)
8943 x
= simplify_gen_unary (NEG
, xmode
, XEXP (x
, 1), xmode
);
8944 return force_to_mode (x
, mode
, mask
, next_select
);
8947 /* Similarly, if C contains every bit in the fuller_mask, then we may
8948 replace with (not Y). */
8949 if (CONST_INT_P (XEXP (x
, 0))
8950 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8952 x
= simplify_gen_unary (NOT
, xmode
, XEXP (x
, 1), xmode
);
8953 return force_to_mode (x
, mode
, mask
, next_select
);
8961 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8962 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8963 operation which may be a bitfield extraction. Ensure that the
8964 constant we form is not wider than the mode of X. */
8966 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8967 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8968 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8969 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8970 && CONST_INT_P (XEXP (x
, 1))
8971 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8972 + floor_log2 (INTVAL (XEXP (x
, 1))))
8973 < GET_MODE_PRECISION (xmode
))
8974 && (UINTVAL (XEXP (x
, 1))
8975 & ~nonzero_bits (XEXP (x
, 0), xmode
)) == 0)
8977 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8978 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8980 temp
= simplify_gen_binary (GET_CODE (x
), xmode
,
8981 XEXP (XEXP (x
, 0), 0), temp
);
8982 x
= simplify_gen_binary (LSHIFTRT
, xmode
, temp
,
8983 XEXP (XEXP (x
, 0), 1));
8984 return force_to_mode (x
, mode
, mask
, next_select
);
8988 /* For most binary operations, just propagate into the operation and
8989 change the mode if we have an operation of that mode. */
8991 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8992 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8994 /* If we ended up truncating both operands, truncate the result of the
8995 operation instead. */
8996 if (GET_CODE (op0
) == TRUNCATE
8997 && GET_CODE (op1
) == TRUNCATE
)
8999 op0
= XEXP (op0
, 0);
9000 op1
= XEXP (op1
, 0);
9003 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
9004 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
9006 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
9008 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
9014 /* For left shifts, do the same, but just for the first operand.
9015 However, we cannot do anything with shifts where we cannot
9016 guarantee that the counts are smaller than the size of the mode
9017 because such a count will have a different meaning in a
9020 if (! (CONST_INT_P (XEXP (x
, 1))
9021 && INTVAL (XEXP (x
, 1)) >= 0
9022 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
9023 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
9024 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
9025 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
9028 /* If the shift count is a constant and we can do arithmetic in
9029 the mode of the shift, refine which bits we need. Otherwise, use the
9030 conservative form of the mask. */
9031 if (CONST_INT_P (XEXP (x
, 1))
9032 && INTVAL (XEXP (x
, 1)) >= 0
9033 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
9034 && HWI_COMPUTABLE_MODE_P (op_mode
))
9035 mask
>>= INTVAL (XEXP (x
, 1));
9039 op0
= gen_lowpart_or_truncate (op_mode
,
9040 force_to_mode (XEXP (x
, 0), mode
,
9041 mask
, next_select
));
9043 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0))
9045 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
9051 /* Here we can only do something if the shift count is a constant,
9052 this shift constant is valid for the host, and we can do arithmetic
9055 if (CONST_INT_P (XEXP (x
, 1))
9056 && INTVAL (XEXP (x
, 1)) >= 0
9057 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
9058 && HWI_COMPUTABLE_MODE_P (op_mode
))
9060 rtx inner
= XEXP (x
, 0);
9061 unsigned HOST_WIDE_INT inner_mask
;
9063 /* Select the mask of the bits we need for the shift operand. */
9064 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
9066 /* We can only change the mode of the shift if we can do arithmetic
9067 in the mode of the shift and INNER_MASK is no wider than the
9068 width of X's mode. */
9069 if ((inner_mask
& ~GET_MODE_MASK (xmode
)) != 0)
9072 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
9074 if (xmode
!= op_mode
|| inner
!= XEXP (x
, 0))
9076 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
9081 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9082 shift and AND produces only copies of the sign bit (C2 is one less
9083 than a power of two), we can do this with just a shift. */
9085 if (GET_CODE (x
) == LSHIFTRT
9086 && CONST_INT_P (XEXP (x
, 1))
9087 /* The shift puts one of the sign bit copies in the least significant
9089 && ((INTVAL (XEXP (x
, 1))
9090 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
9091 >= GET_MODE_PRECISION (xmode
))
9092 && pow2p_hwi (mask
+ 1)
9093 /* Number of bits left after the shift must be more than the mask
9095 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
9096 <= GET_MODE_PRECISION (xmode
))
9097 /* Must be more sign bit copies than the mask needs. */
9098 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
9099 >= exact_log2 (mask
+ 1)))
9101 int nbits
= GET_MODE_PRECISION (xmode
) - exact_log2 (mask
+ 1);
9102 x
= simplify_gen_binary (LSHIFTRT
, xmode
, XEXP (x
, 0),
9103 gen_int_shift_amount (xmode
, nbits
));
9108 /* If we are just looking for the sign bit, we don't need this shift at
9109 all, even if it has a variable count. */
9110 if (val_signbit_p (xmode
, mask
))
9111 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
9113 /* If this is a shift by a constant, get a mask that contains those bits
9114 that are not copies of the sign bit. We then have two cases: If
9115 MASK only includes those bits, this can be a logical shift, which may
9116 allow simplifications. If MASK is a single-bit field not within
9117 those bits, we are requesting a copy of the sign bit and hence can
9118 shift the sign bit to the appropriate location. */
9120 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
9121 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
9123 unsigned HOST_WIDE_INT nonzero
;
9126 /* If the considered data is wider than HOST_WIDE_INT, we can't
9127 represent a mask for all its bits in a single scalar.
9128 But we only care about the lower bits, so calculate these. */
9130 if (GET_MODE_PRECISION (xmode
) > HOST_BITS_PER_WIDE_INT
)
9132 nonzero
= HOST_WIDE_INT_M1U
;
9134 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9135 is the number of bits a full-width mask would have set.
9136 We need only shift if these are fewer than nonzero can
9137 hold. If not, we must keep all bits set in nonzero. */
9139 if (GET_MODE_PRECISION (xmode
) - INTVAL (XEXP (x
, 1))
9140 < HOST_BITS_PER_WIDE_INT
)
9141 nonzero
>>= INTVAL (XEXP (x
, 1))
9142 + HOST_BITS_PER_WIDE_INT
9143 - GET_MODE_PRECISION (xmode
);
9147 nonzero
= GET_MODE_MASK (xmode
);
9148 nonzero
>>= INTVAL (XEXP (x
, 1));
9151 if ((mask
& ~nonzero
) == 0)
9153 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, xmode
,
9154 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
9155 if (GET_CODE (x
) != ASHIFTRT
)
9156 return force_to_mode (x
, mode
, mask
, next_select
);
9159 else if ((i
= exact_log2 (mask
)) >= 0)
9161 x
= simplify_shift_const
9162 (NULL_RTX
, LSHIFTRT
, xmode
, XEXP (x
, 0),
9163 GET_MODE_PRECISION (xmode
) - 1 - i
);
9165 if (GET_CODE (x
) != ASHIFTRT
)
9166 return force_to_mode (x
, mode
, mask
, next_select
);
9170 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9171 even if the shift count isn't a constant. */
9173 x
= simplify_gen_binary (LSHIFTRT
, xmode
, XEXP (x
, 0), XEXP (x
, 1));
9177 /* If this is a zero- or sign-extension operation that just affects bits
9178 we don't care about, remove it. Be sure the call above returned
9179 something that is still a shift. */
9181 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
9182 && CONST_INT_P (XEXP (x
, 1))
9183 && INTVAL (XEXP (x
, 1)) >= 0
9184 && (INTVAL (XEXP (x
, 1))
9185 <= GET_MODE_PRECISION (xmode
) - (floor_log2 (mask
) + 1))
9186 && GET_CODE (XEXP (x
, 0)) == ASHIFT
9187 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
9188 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
9195 /* If the shift count is constant and we can do computations
9196 in the mode of X, compute where the bits we care about are.
9197 Otherwise, we can't do anything. Don't change the mode of
9198 the shift or propagate MODE into the shift, though. */
9199 if (CONST_INT_P (XEXP (x
, 1))
9200 && INTVAL (XEXP (x
, 1)) >= 0)
9202 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
9203 xmode
, gen_int_mode (mask
, xmode
),
9205 if (temp
&& CONST_INT_P (temp
))
9206 x
= simplify_gen_binary (code
, xmode
,
9207 force_to_mode (XEXP (x
, 0), xmode
,
9208 INTVAL (temp
), next_select
),
9214 /* If we just want the low-order bit, the NEG isn't needed since it
9215 won't change the low-order bit. */
9217 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
9219 /* We need any bits less significant than the most significant bit in
9220 MASK since carries from those bits will affect the bits we are
9226 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9227 same as the XOR case above. Ensure that the constant we form is not
9228 wider than the mode of X. */
9230 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
9231 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
9232 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
9233 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
9234 < GET_MODE_PRECISION (xmode
))
9235 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
9237 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)), xmode
);
9238 temp
= simplify_gen_binary (XOR
, xmode
, XEXP (XEXP (x
, 0), 0), temp
);
9239 x
= simplify_gen_binary (LSHIFTRT
, xmode
,
9240 temp
, XEXP (XEXP (x
, 0), 1));
9242 return force_to_mode (x
, mode
, mask
, next_select
);
9245 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9246 use the full mask inside the NOT. */
9250 op0
= gen_lowpart_or_truncate (op_mode
,
9251 force_to_mode (XEXP (x
, 0), mode
, mask
,
9253 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0))
9255 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
9261 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9262 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9263 which is equal to STORE_FLAG_VALUE. */
9264 if ((mask
& ~STORE_FLAG_VALUE
) == 0
9265 && XEXP (x
, 1) == const0_rtx
9266 && GET_MODE (XEXP (x
, 0)) == mode
9267 && pow2p_hwi (nonzero_bits (XEXP (x
, 0), mode
))
9268 && (nonzero_bits (XEXP (x
, 0), mode
)
9269 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
9270 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
9275 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9276 written in a narrower mode. We play it safe and do not do so. */
9278 op0
= gen_lowpart_or_truncate (xmode
,
9279 force_to_mode (XEXP (x
, 1), mode
,
9280 mask
, next_select
));
9281 op1
= gen_lowpart_or_truncate (xmode
,
9282 force_to_mode (XEXP (x
, 2), mode
,
9283 mask
, next_select
));
9284 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
9285 x
= simplify_gen_ternary (IF_THEN_ELSE
, xmode
,
9286 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
9294 /* Ensure we return a value of the proper mode. */
9295 return gen_lowpart_or_truncate (mode
, x
);
9298 /* Return nonzero if X is an expression that has one of two values depending on
9299 whether some other value is zero or nonzero. In that case, we return the
9300 value that is being tested, *PTRUE is set to the value if the rtx being
9301 returned has a nonzero value, and *PFALSE is set to the other alternative.
9303 If we return zero, we set *PTRUE and *PFALSE to X. */
9306 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
9308 machine_mode mode
= GET_MODE (x
);
9309 enum rtx_code code
= GET_CODE (x
);
9310 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
9311 unsigned HOST_WIDE_INT nz
;
9312 scalar_int_mode int_mode
;
9314 /* If we are comparing a value against zero, we are done. */
9315 if ((code
== NE
|| code
== EQ
)
9316 && XEXP (x
, 1) == const0_rtx
)
9318 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
9319 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
9323 /* If this is a unary operation whose operand has one of two values, apply
9324 our opcode to compute those values. */
9325 else if (UNARY_P (x
)
9326 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
9328 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
9329 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
9330 GET_MODE (XEXP (x
, 0)));
9334 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9335 make can't possibly match and would suppress other optimizations. */
9336 else if (code
== COMPARE
)
9339 /* If this is a binary operation, see if either side has only one of two
9340 values. If either one does or if both do and they are conditional on
9341 the same value, compute the new true and false values. */
9342 else if (BINARY_P (x
))
9344 rtx op0
= XEXP (x
, 0);
9345 rtx op1
= XEXP (x
, 1);
9346 cond0
= if_then_else_cond (op0
, &true0
, &false0
);
9347 cond1
= if_then_else_cond (op1
, &true1
, &false1
);
9349 if ((cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
))
9350 && (REG_P (op0
) || REG_P (op1
)))
9352 /* Try to enable a simplification by undoing work done by
9353 if_then_else_cond if it converted a REG into something more
9358 true0
= false0
= op0
;
9363 true1
= false1
= op1
;
9367 if ((cond0
!= 0 || cond1
!= 0)
9368 && ! (cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
)))
9370 /* If if_then_else_cond returned zero, then true/false are the
9371 same rtl. We must copy one of them to prevent invalid rtl
9374 true0
= copy_rtx (true0
);
9375 else if (cond1
== 0)
9376 true1
= copy_rtx (true1
);
9378 if (COMPARISON_P (x
))
9380 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
9382 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
9387 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
9388 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
9391 return cond0
? cond0
: cond1
;
9394 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9395 operands is zero when the other is nonzero, and vice-versa,
9396 and STORE_FLAG_VALUE is 1 or -1. */
9398 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9399 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
9401 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9403 rtx op0
= XEXP (XEXP (x
, 0), 1);
9404 rtx op1
= XEXP (XEXP (x
, 1), 1);
9406 cond0
= XEXP (XEXP (x
, 0), 0);
9407 cond1
= XEXP (XEXP (x
, 1), 0);
9409 if (COMPARISON_P (cond0
)
9410 && COMPARISON_P (cond1
)
9411 && SCALAR_INT_MODE_P (mode
)
9412 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9413 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9414 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9415 || ((swap_condition (GET_CODE (cond0
))
9416 == reversed_comparison_code (cond1
, NULL
))
9417 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9418 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9419 && ! side_effects_p (x
))
9421 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
9422 *pfalse
= simplify_gen_binary (MULT
, mode
,
9424 ? simplify_gen_unary (NEG
, mode
,
9432 /* Similarly for MULT, AND and UMIN, except that for these the result
9434 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9435 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
9436 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9438 cond0
= XEXP (XEXP (x
, 0), 0);
9439 cond1
= XEXP (XEXP (x
, 1), 0);
9441 if (COMPARISON_P (cond0
)
9442 && COMPARISON_P (cond1
)
9443 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9444 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9445 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9446 || ((swap_condition (GET_CODE (cond0
))
9447 == reversed_comparison_code (cond1
, NULL
))
9448 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9449 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9450 && ! side_effects_p (x
))
9452 *ptrue
= *pfalse
= const0_rtx
;
9458 else if (code
== IF_THEN_ELSE
)
9460 /* If we have IF_THEN_ELSE already, extract the condition and
9461 canonicalize it if it is NE or EQ. */
9462 cond0
= XEXP (x
, 0);
9463 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9464 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9465 return XEXP (cond0
, 0);
9466 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9468 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9469 return XEXP (cond0
, 0);
9475 /* If X is a SUBREG, we can narrow both the true and false values
9476 if the inner expression, if there is a condition. */
9477 else if (code
== SUBREG
9478 && (cond0
= if_then_else_cond (SUBREG_REG (x
), &true0
,
9481 true0
= simplify_gen_subreg (mode
, true0
,
9482 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9483 false0
= simplify_gen_subreg (mode
, false0
,
9484 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9485 if (true0
&& false0
)
9493 /* If X is a constant, this isn't special and will cause confusions
9494 if we treat it as such. Likewise if it is equivalent to a constant. */
9495 else if (CONSTANT_P (x
)
9496 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9499 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9500 will be least confusing to the rest of the compiler. */
9501 else if (mode
== BImode
)
9503 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9507 /* If X is known to be either 0 or -1, those are the true and
9508 false values when testing X. */
9509 else if (x
== constm1_rtx
|| x
== const0_rtx
9510 || (is_a
<scalar_int_mode
> (mode
, &int_mode
)
9511 && (num_sign_bit_copies (x
, int_mode
)
9512 == GET_MODE_PRECISION (int_mode
))))
9514 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9518 /* Likewise for 0 or a single bit. */
9519 else if (HWI_COMPUTABLE_MODE_P (mode
)
9520 && pow2p_hwi (nz
= nonzero_bits (x
, mode
)))
9522 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9526 /* Otherwise fail; show no condition with true and false values the same. */
9527 *ptrue
= *pfalse
= x
;
9531 /* Return the value of expression X given the fact that condition COND
9532 is known to be true when applied to REG as its first operand and VAL
9533 as its second. X is known to not be shared and so can be modified in
9536 We only handle the simplest cases, and specifically those cases that
9537 arise with IF_THEN_ELSE expressions. */
9540 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9542 enum rtx_code code
= GET_CODE (x
);
9546 if (side_effects_p (x
))
9549 /* If either operand of the condition is a floating point value,
9550 then we have to avoid collapsing an EQ comparison. */
9552 && rtx_equal_p (x
, reg
)
9553 && ! FLOAT_MODE_P (GET_MODE (x
))
9554 && ! FLOAT_MODE_P (GET_MODE (val
)))
9557 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9560 /* If X is (abs REG) and we know something about REG's relationship
9561 with zero, we may be able to simplify this. */
9563 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9566 case GE
: case GT
: case EQ
:
9569 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9571 GET_MODE (XEXP (x
, 0)));
9576 /* The only other cases we handle are MIN, MAX, and comparisons if the
9577 operands are the same as REG and VAL. */
9579 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9581 if (rtx_equal_p (XEXP (x
, 0), val
))
9583 std::swap (val
, reg
);
9584 cond
= swap_condition (cond
);
9587 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9589 if (COMPARISON_P (x
))
9591 if (comparison_dominates_p (cond
, code
))
9592 return VECTOR_MODE_P (GET_MODE (x
)) ? x
: const_true_rtx
;
9594 code
= reversed_comparison_code (x
, NULL
);
9596 && comparison_dominates_p (cond
, code
))
9597 return CONST0_RTX (GET_MODE (x
));
9601 else if (code
== SMAX
|| code
== SMIN
9602 || code
== UMIN
|| code
== UMAX
)
9604 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9606 /* Do not reverse the condition when it is NE or EQ.
9607 This is because we cannot conclude anything about
9608 the value of 'SMAX (x, y)' when x is not equal to y,
9609 but we can when x equals y. */
9610 if ((code
== SMAX
|| code
== UMAX
)
9611 && ! (cond
== EQ
|| cond
== NE
))
9612 cond
= reverse_condition (cond
);
9617 return unsignedp
? x
: XEXP (x
, 1);
9619 return unsignedp
? x
: XEXP (x
, 0);
9621 return unsignedp
? XEXP (x
, 1) : x
;
9623 return unsignedp
? XEXP (x
, 0) : x
;
9630 else if (code
== SUBREG
)
9632 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9633 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9635 if (SUBREG_REG (x
) != r
)
9637 /* We must simplify subreg here, before we lose track of the
9638 original inner_mode. */
9639 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9640 inner_mode
, SUBREG_BYTE (x
));
9644 SUBST (SUBREG_REG (x
), r
);
9649 /* We don't have to handle SIGN_EXTEND here, because even in the
9650 case of replacing something with a modeless CONST_INT, a
9651 CONST_INT is already (supposed to be) a valid sign extension for
9652 its narrower mode, which implies it's already properly
9653 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9654 story is different. */
9655 else if (code
== ZERO_EXTEND
)
9657 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9658 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9660 if (XEXP (x
, 0) != r
)
9662 /* We must simplify the zero_extend here, before we lose
9663 track of the original inner_mode. */
9664 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9669 SUBST (XEXP (x
, 0), r
);
9675 fmt
= GET_RTX_FORMAT (code
);
9676 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9679 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9680 else if (fmt
[i
] == 'E')
9681 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9682 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9689 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9690 assignment as a field assignment. */
9693 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9695 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9697 if (paradoxical_subreg_p (GET_MODE (x
), GET_MODE (y
)))
9699 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9701 x
= adjust_address_nv (x
, GET_MODE (y
),
9702 byte_lowpart_offset (GET_MODE (y
),
9706 if (x
== y
|| rtx_equal_p (x
, y
))
9709 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9712 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9713 Note that all SUBREGs of MEM are paradoxical; otherwise they
9714 would have been rewritten. */
9715 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9716 && MEM_P (SUBREG_REG (y
))
9717 && rtx_equal_p (SUBREG_REG (y
),
9718 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9721 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9722 && MEM_P (SUBREG_REG (x
))
9723 && rtx_equal_p (SUBREG_REG (x
),
9724 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9727 /* We used to see if get_last_value of X and Y were the same but that's
9728 not correct. In one direction, we'll cause the assignment to have
9729 the wrong destination and in the case, we'll import a register into this
9730 insn that might have already have been dead. So fail if none of the
9731 above cases are true. */
9735 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9736 Return that assignment if so.
9738 We only handle the most common cases. */
9741 make_field_assignment (rtx x
)
9743 rtx dest
= SET_DEST (x
);
9744 rtx src
= SET_SRC (x
);
9749 unsigned HOST_WIDE_INT len
;
9752 /* All the rules in this function are specific to scalar integers. */
9753 scalar_int_mode mode
;
9754 if (!is_a
<scalar_int_mode
> (GET_MODE (dest
), &mode
))
9757 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9758 a clear of a one-bit field. We will have changed it to
9759 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9762 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9763 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9764 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9765 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9767 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9770 return gen_rtx_SET (assign
, const0_rtx
);
9774 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9775 && subreg_lowpart_p (XEXP (src
, 0))
9776 && partial_subreg_p (XEXP (src
, 0))
9777 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9778 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9779 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9780 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9782 assign
= make_extraction (VOIDmode
, dest
, 0,
9783 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9786 return gen_rtx_SET (assign
, const0_rtx
);
9790 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9792 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9793 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9794 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9796 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9799 return gen_rtx_SET (assign
, const1_rtx
);
9803 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9804 SRC is an AND with all bits of that field set, then we can discard
9806 if (GET_CODE (dest
) == ZERO_EXTRACT
9807 && CONST_INT_P (XEXP (dest
, 1))
9808 && GET_CODE (src
) == AND
9809 && CONST_INT_P (XEXP (src
, 1)))
9811 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9812 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9813 unsigned HOST_WIDE_INT ze_mask
;
9815 if (width
>= HOST_BITS_PER_WIDE_INT
)
9818 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9820 /* Complete overlap. We can remove the source AND. */
9821 if ((and_mask
& ze_mask
) == ze_mask
)
9822 return gen_rtx_SET (dest
, XEXP (src
, 0));
9824 /* Partial overlap. We can reduce the source AND. */
9825 if ((and_mask
& ze_mask
) != and_mask
)
9827 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9828 gen_int_mode (and_mask
& ze_mask
, mode
));
9829 return gen_rtx_SET (dest
, src
);
9833 /* The other case we handle is assignments into a constant-position
9834 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9835 a mask that has all one bits except for a group of zero bits and
9836 OTHER is known to have zeros where C1 has ones, this is such an
9837 assignment. Compute the position and length from C1. Shift OTHER
9838 to the appropriate position, force it to the required mode, and
9839 make the extraction. Check for the AND in both operands. */
9841 /* One or more SUBREGs might obscure the constant-position field
9842 assignment. The first one we are likely to encounter is an outer
9843 narrowing SUBREG, which we can just strip for the purposes of
9844 identifying the constant-field assignment. */
9845 scalar_int_mode src_mode
= mode
;
9846 if (GET_CODE (src
) == SUBREG
9847 && subreg_lowpart_p (src
)
9848 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (src
)), &src_mode
))
9849 src
= SUBREG_REG (src
);
9851 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9854 rhs
= expand_compound_operation (XEXP (src
, 0));
9855 lhs
= expand_compound_operation (XEXP (src
, 1));
9857 if (GET_CODE (rhs
) == AND
9858 && CONST_INT_P (XEXP (rhs
, 1))
9859 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9860 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9861 /* The second SUBREG that might get in the way is a paradoxical
9862 SUBREG around the first operand of the AND. We want to
9863 pretend the operand is as wide as the destination here. We
9864 do this by adjusting the MEM to wider mode for the sole
9865 purpose of the call to rtx_equal_for_field_assignment_p. Also
9866 note this trick only works for MEMs. */
9867 else if (GET_CODE (rhs
) == AND
9868 && paradoxical_subreg_p (XEXP (rhs
, 0))
9869 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9870 && CONST_INT_P (XEXP (rhs
, 1))
9871 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9873 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9874 else if (GET_CODE (lhs
) == AND
9875 && CONST_INT_P (XEXP (lhs
, 1))
9876 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9877 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9878 /* The second SUBREG that might get in the way is a paradoxical
9879 SUBREG around the first operand of the AND. We want to
9880 pretend the operand is as wide as the destination here. We
9881 do this by adjusting the MEM to wider mode for the sole
9882 purpose of the call to rtx_equal_for_field_assignment_p. Also
9883 note this trick only works for MEMs. */
9884 else if (GET_CODE (lhs
) == AND
9885 && paradoxical_subreg_p (XEXP (lhs
, 0))
9886 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9887 && CONST_INT_P (XEXP (lhs
, 1))
9888 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9890 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9894 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (mode
), &len
);
9896 || pos
+ len
> GET_MODE_PRECISION (mode
)
9897 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
9898 || (c1
& nonzero_bits (other
, mode
)) != 0)
9901 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9905 /* The mode to use for the source is the mode of the assignment, or of
9906 what is inside a possible STRICT_LOW_PART. */
9907 machine_mode new_mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9908 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9910 /* Shift OTHER right POS places and make it the source, restricting it
9911 to the proper length and mode. */
9913 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9914 src_mode
, other
, pos
),
9916 src
= force_to_mode (src
, new_mode
,
9917 len
>= HOST_BITS_PER_WIDE_INT
9919 : (HOST_WIDE_INT_1U
<< len
) - 1,
9922 /* If SRC is masked by an AND that does not make a difference in
9923 the value being stored, strip it. */
9924 if (GET_CODE (assign
) == ZERO_EXTRACT
9925 && CONST_INT_P (XEXP (assign
, 1))
9926 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9927 && GET_CODE (src
) == AND
9928 && CONST_INT_P (XEXP (src
, 1))
9929 && UINTVAL (XEXP (src
, 1))
9930 == (HOST_WIDE_INT_1U
<< INTVAL (XEXP (assign
, 1))) - 1)
9931 src
= XEXP (src
, 0);
9933 return gen_rtx_SET (assign
, src
);
9936 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9940 apply_distributive_law (rtx x
)
9942 enum rtx_code code
= GET_CODE (x
);
9943 enum rtx_code inner_code
;
9944 rtx lhs
, rhs
, other
;
9947 /* Distributivity is not true for floating point as it can change the
9948 value. So we don't do it unless -funsafe-math-optimizations. */
9949 if (FLOAT_MODE_P (GET_MODE (x
))
9950 && ! flag_unsafe_math_optimizations
)
9953 /* The outer operation can only be one of the following: */
9954 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9955 && code
!= PLUS
&& code
!= MINUS
)
9961 /* If either operand is a primitive we can't do anything, so get out
9963 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9966 lhs
= expand_compound_operation (lhs
);
9967 rhs
= expand_compound_operation (rhs
);
9968 inner_code
= GET_CODE (lhs
);
9969 if (inner_code
!= GET_CODE (rhs
))
9972 /* See if the inner and outer operations distribute. */
9979 /* These all distribute except over PLUS. */
9980 if (code
== PLUS
|| code
== MINUS
)
9985 if (code
!= PLUS
&& code
!= MINUS
)
9990 /* This is also a multiply, so it distributes over everything. */
9993 /* This used to handle SUBREG, but this turned out to be counter-
9994 productive, since (subreg (op ...)) usually is not handled by
9995 insn patterns, and this "optimization" therefore transformed
9996 recognizable patterns into unrecognizable ones. Therefore the
9997 SUBREG case was removed from here.
9999 It is possible that distributing SUBREG over arithmetic operations
10000 leads to an intermediate result than can then be optimized further,
10001 e.g. by moving the outer SUBREG to the other side of a SET as done
10002 in simplify_set. This seems to have been the original intent of
10003 handling SUBREGs here.
10005 However, with current GCC this does not appear to actually happen,
10006 at least on major platforms. If some case is found where removing
10007 the SUBREG case here prevents follow-on optimizations, distributing
10008 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
10014 /* Set LHS and RHS to the inner operands (A and B in the example
10015 above) and set OTHER to the common operand (C in the example).
10016 There is only one way to do this unless the inner operation is
10018 if (COMMUTATIVE_ARITH_P (lhs
)
10019 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
10020 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
10021 else if (COMMUTATIVE_ARITH_P (lhs
)
10022 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
10023 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
10024 else if (COMMUTATIVE_ARITH_P (lhs
)
10025 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
10026 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
10027 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
10028 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
10032 /* Form the new inner operation, seeing if it simplifies first. */
10033 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
10035 /* There is one exception to the general way of distributing:
10036 (a | c) ^ (b | c) -> (a ^ b) & ~c */
10037 if (code
== XOR
&& inner_code
== IOR
)
10040 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
10043 /* We may be able to continuing distributing the result, so call
10044 ourselves recursively on the inner operation before forming the
10045 outer operation, which we return. */
10046 return simplify_gen_binary (inner_code
, GET_MODE (x
),
10047 apply_distributive_law (tem
), other
);
10050 /* See if X is of the form (* (+ A B) C), and if so convert to
10051 (+ (* A C) (* B C)) and try to simplify.
10053 Most of the time, this results in no change. However, if some of
10054 the operands are the same or inverses of each other, simplifications
10057 For example, (and (ior A B) (not B)) can occur as the result of
10058 expanding a bit field assignment. When we apply the distributive
10059 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
10060 which then simplifies to (and (A (not B))).
10062 Note that no checks happen on the validity of applying the inverse
10063 distributive law. This is pointless since we can do it in the
10064 few places where this routine is called.
10066 N is the index of the term that is decomposed (the arithmetic operation,
10067 i.e. (+ A B) in the first example above). !N is the index of the term that
10068 is distributed, i.e. of C in the first example above. */
10070 distribute_and_simplify_rtx (rtx x
, int n
)
10073 enum rtx_code outer_code
, inner_code
;
10074 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
10076 /* Distributivity is not true for floating point as it can change the
10077 value. So we don't do it unless -funsafe-math-optimizations. */
10078 if (FLOAT_MODE_P (GET_MODE (x
))
10079 && ! flag_unsafe_math_optimizations
)
10082 decomposed
= XEXP (x
, n
);
10083 if (!ARITHMETIC_P (decomposed
))
10086 mode
= GET_MODE (x
);
10087 outer_code
= GET_CODE (x
);
10088 distributed
= XEXP (x
, !n
);
10090 inner_code
= GET_CODE (decomposed
);
10091 inner_op0
= XEXP (decomposed
, 0);
10092 inner_op1
= XEXP (decomposed
, 1);
10094 /* Special case (and (xor B C) (not A)), which is equivalent to
10095 (xor (ior A B) (ior A C)) */
10096 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
10098 distributed
= XEXP (distributed
, 0);
10104 /* Distribute the second term. */
10105 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
10106 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
10110 /* Distribute the first term. */
10111 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
10112 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
10115 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
10116 new_op0
, new_op1
));
10117 if (GET_CODE (tmp
) != outer_code
10118 && (set_src_cost (tmp
, mode
, optimize_this_for_speed_p
)
10119 < set_src_cost (x
, mode
, optimize_this_for_speed_p
)))
10125 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10126 in MODE. Return an equivalent form, if different from (and VAROP
10127 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10130 simplify_and_const_int_1 (scalar_int_mode mode
, rtx varop
,
10131 unsigned HOST_WIDE_INT constop
)
10133 unsigned HOST_WIDE_INT nonzero
;
10134 unsigned HOST_WIDE_INT orig_constop
;
10138 orig_varop
= varop
;
10139 orig_constop
= constop
;
10140 if (GET_CODE (varop
) == CLOBBER
)
10143 /* Simplify VAROP knowing that we will be only looking at some of the
10146 Note by passing in CONSTOP, we guarantee that the bits not set in
10147 CONSTOP are not significant and will never be examined. We must
10148 ensure that is the case by explicitly masking out those bits
10149 before returning. */
10150 varop
= force_to_mode (varop
, mode
, constop
, 0);
10152 /* If VAROP is a CLOBBER, we will fail so return it. */
10153 if (GET_CODE (varop
) == CLOBBER
)
10156 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10157 to VAROP and return the new constant. */
10158 if (CONST_INT_P (varop
))
10159 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
10161 /* See what bits may be nonzero in VAROP. Unlike the general case of
10162 a call to nonzero_bits, here we don't care about bits outside
10165 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
10167 /* Turn off all bits in the constant that are known to already be zero.
10168 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10169 which is tested below. */
10171 constop
&= nonzero
;
10173 /* If we don't have any bits left, return zero. */
10177 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10178 a power of two, we can replace this with an ASHIFT. */
10179 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
10180 && (i
= exact_log2 (constop
)) >= 0)
10181 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
10183 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10184 or XOR, then try to apply the distributive law. This may eliminate
10185 operations if either branch can be simplified because of the AND.
10186 It may also make some cases more complex, but those cases probably
10187 won't match a pattern either with or without this. */
10189 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
10191 scalar_int_mode varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10195 apply_distributive_law
10196 (simplify_gen_binary (GET_CODE (varop
), varop_mode
,
10197 simplify_and_const_int (NULL_RTX
, varop_mode
,
10200 simplify_and_const_int (NULL_RTX
, varop_mode
,
10205 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10206 the AND and see if one of the operands simplifies to zero. If so, we
10207 may eliminate it. */
10209 if (GET_CODE (varop
) == PLUS
10210 && pow2p_hwi (constop
+ 1))
10214 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
10215 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
10216 if (o0
== const0_rtx
)
10218 if (o1
== const0_rtx
)
10222 /* Make a SUBREG if necessary. If we can't make it, fail. */
10223 varop
= gen_lowpart (mode
, varop
);
10224 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10227 /* If we are only masking insignificant bits, return VAROP. */
10228 if (constop
== nonzero
)
10231 if (varop
== orig_varop
&& constop
== orig_constop
)
10234 /* Otherwise, return an AND. */
10235 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
10239 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10242 Return an equivalent form, if different from X. Otherwise, return X. If
10243 X is zero, we are to always construct the equivalent form. */
10246 simplify_and_const_int (rtx x
, scalar_int_mode mode
, rtx varop
,
10247 unsigned HOST_WIDE_INT constop
)
10249 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
10254 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
10255 gen_int_mode (constop
, mode
));
10256 if (GET_MODE (x
) != mode
)
10257 x
= gen_lowpart (mode
, x
);
10261 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10262 We don't care about bits outside of those defined in MODE.
10263 We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10265 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10266 a shift, AND, or zero_extract, we can do better. */
10269 reg_nonzero_bits_for_combine (const_rtx x
, scalar_int_mode xmode
,
10270 scalar_int_mode mode
,
10271 unsigned HOST_WIDE_INT
*nonzero
)
10274 reg_stat_type
*rsp
;
10276 /* If X is a register whose nonzero bits value is current, use it.
10277 Otherwise, if X is a register whose value we can find, use that
10278 value. Otherwise, use the previously-computed global nonzero bits
10279 for this register. */
10281 rsp
= ®_stat
[REGNO (x
)];
10282 if (rsp
->last_set_value
!= 0
10283 && (rsp
->last_set_mode
== mode
10284 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10285 && GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
10286 && GET_MODE_CLASS (mode
) == MODE_INT
))
10287 && ((rsp
->last_set_label
>= label_tick_ebb_start
10288 && rsp
->last_set_label
< label_tick
)
10289 || (rsp
->last_set_label
== label_tick
10290 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10291 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10292 && REGNO (x
) < reg_n_sets_max
10293 && REG_N_SETS (REGNO (x
)) == 1
10294 && !REGNO_REG_SET_P
10295 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10298 /* Note that, even if the precision of last_set_mode is lower than that
10299 of mode, record_value_for_reg invoked nonzero_bits on the register
10300 with nonzero_bits_mode (because last_set_mode is necessarily integral
10301 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10302 are all valid, hence in mode too since nonzero_bits_mode is defined
10303 to the largest HWI_COMPUTABLE_MODE_P mode. */
10304 *nonzero
&= rsp
->last_set_nonzero_bits
;
10308 tem
= get_last_value (x
);
10311 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
10312 tem
= sign_extend_short_imm (tem
, xmode
, GET_MODE_PRECISION (mode
));
10317 if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
10319 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
10321 if (GET_MODE_PRECISION (xmode
) < GET_MODE_PRECISION (mode
))
10322 /* We don't know anything about the upper bits. */
10323 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (xmode
);
10331 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10332 end of X that are known to be equal to the sign bit. X will be used
10333 in mode MODE; the returned value will always be between 1 and the
10334 number of bits in MODE. */
10337 reg_num_sign_bit_copies_for_combine (const_rtx x
, scalar_int_mode xmode
,
10338 scalar_int_mode mode
,
10339 unsigned int *result
)
10342 reg_stat_type
*rsp
;
10344 rsp
= ®_stat
[REGNO (x
)];
10345 if (rsp
->last_set_value
!= 0
10346 && rsp
->last_set_mode
== mode
10347 && ((rsp
->last_set_label
>= label_tick_ebb_start
10348 && rsp
->last_set_label
< label_tick
)
10349 || (rsp
->last_set_label
== label_tick
10350 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10351 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10352 && REGNO (x
) < reg_n_sets_max
10353 && REG_N_SETS (REGNO (x
)) == 1
10354 && !REGNO_REG_SET_P
10355 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10358 *result
= rsp
->last_set_sign_bit_copies
;
10362 tem
= get_last_value (x
);
10366 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
10367 && GET_MODE_PRECISION (xmode
) == GET_MODE_PRECISION (mode
))
10368 *result
= rsp
->sign_bit_copies
;
10373 /* Return the number of "extended" bits there are in X, when interpreted
10374 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10375 unsigned quantities, this is the number of high-order zero bits.
10376 For signed quantities, this is the number of copies of the sign bit
10377 minus 1. In both case, this function returns the number of "spare"
10378 bits. For example, if two quantities for which this function returns
10379 at least 1 are added, the addition is known not to overflow.
10381 This function will always return 0 unless called during combine, which
10382 implies that it must be called from a define_split. */
10385 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
10387 if (nonzero_sign_valid
== 0)
10390 scalar_int_mode int_mode
;
10392 ? (is_a
<scalar_int_mode
> (mode
, &int_mode
)
10393 && HWI_COMPUTABLE_MODE_P (int_mode
)
10394 ? (unsigned int) (GET_MODE_PRECISION (int_mode
) - 1
10395 - floor_log2 (nonzero_bits (x
, int_mode
)))
10397 : num_sign_bit_copies (x
, mode
) - 1);
10400 /* This function is called from `simplify_shift_const' to merge two
10401 outer operations. Specifically, we have already found that we need
10402 to perform operation *POP0 with constant *PCONST0 at the outermost
10403 position. We would now like to also perform OP1 with constant CONST1
10404 (with *POP0 being done last).
10406 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10407 the resulting operation. *PCOMP_P is set to 1 if we would need to
10408 complement the innermost operand, otherwise it is unchanged.
10410 MODE is the mode in which the operation will be done. No bits outside
10411 the width of this mode matter. It is assumed that the width of this mode
10412 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10414 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10415 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10416 result is simply *PCONST0.
10418 If the resulting operation cannot be expressed as one operation, we
10419 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10422 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
10424 enum rtx_code op0
= *pop0
;
10425 HOST_WIDE_INT const0
= *pconst0
;
10427 const0
&= GET_MODE_MASK (mode
);
10428 const1
&= GET_MODE_MASK (mode
);
10430 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10434 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10437 if (op1
== UNKNOWN
|| op0
== SET
)
10440 else if (op0
== UNKNOWN
)
10441 op0
= op1
, const0
= const1
;
10443 else if (op0
== op1
)
10467 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10468 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10471 /* If the two constants aren't the same, we can't do anything. The
10472 remaining six cases can all be done. */
10473 else if (const0
!= const1
)
10481 /* (a & b) | b == b */
10483 else /* op1 == XOR */
10484 /* (a ^ b) | b == a | b */
10490 /* (a & b) ^ b == (~a) & b */
10491 op0
= AND
, *pcomp_p
= 1;
10492 else /* op1 == IOR */
10493 /* (a | b) ^ b == a & ~b */
10494 op0
= AND
, const0
= ~const0
;
10499 /* (a | b) & b == b */
10501 else /* op1 == XOR */
10502 /* (a ^ b) & b) == (~a) & b */
10509 /* Check for NO-OP cases. */
10510 const0
&= GET_MODE_MASK (mode
);
10512 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10514 else if (const0
== 0 && op0
== AND
)
10516 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10522 /* ??? Slightly redundant with the above mask, but not entirely.
10523 Moving this above means we'd have to sign-extend the mode mask
10524 for the final test. */
10525 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10526 *pconst0
= trunc_int_for_mode (const0
, mode
);
10531 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10532 the shift in. The original shift operation CODE is performed on OP in
10533 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10534 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10535 result of the shift is subject to operation OUTER_CODE with operand
10538 static scalar_int_mode
10539 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10540 scalar_int_mode orig_mode
, scalar_int_mode mode
,
10541 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10543 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10545 /* In general we can't perform in wider mode for right shift and rotate. */
10549 /* We can still widen if the bits brought in from the left are identical
10550 to the sign bit of ORIG_MODE. */
10551 if (num_sign_bit_copies (op
, mode
)
10552 > (unsigned) (GET_MODE_PRECISION (mode
)
10553 - GET_MODE_PRECISION (orig_mode
)))
10558 /* Similarly here but with zero bits. */
10559 if (HWI_COMPUTABLE_MODE_P (mode
)
10560 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10563 /* We can also widen if the bits brought in will be masked off. This
10564 operation is performed in ORIG_MODE. */
10565 if (outer_code
== AND
)
10567 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10570 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10579 gcc_unreachable ();
10586 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10587 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10588 if we cannot simplify it. Otherwise, return a simplified value.
10590 The shift is normally computed in the widest mode we find in VAROP, as
10591 long as it isn't a different number of words than RESULT_MODE. Exceptions
10592 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10595 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10596 rtx varop
, int orig_count
)
10598 enum rtx_code orig_code
= code
;
10599 rtx orig_varop
= varop
;
10601 machine_mode mode
= result_mode
;
10602 machine_mode shift_mode
;
10603 scalar_int_mode tmode
, inner_mode
, int_mode
, int_varop_mode
, int_result_mode
;
10604 /* We form (outer_op (code varop count) (outer_const)). */
10605 enum rtx_code outer_op
= UNKNOWN
;
10606 HOST_WIDE_INT outer_const
= 0;
10607 int complement_p
= 0;
10610 /* Make sure and truncate the "natural" shift on the way in. We don't
10611 want to do this inside the loop as it makes it more difficult to
10613 if (SHIFT_COUNT_TRUNCATED
)
10614 orig_count
&= GET_MODE_UNIT_BITSIZE (mode
) - 1;
10616 /* If we were given an invalid count, don't do anything except exactly
10617 what was requested. */
10619 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_UNIT_PRECISION (mode
))
10622 count
= orig_count
;
10624 /* Unless one of the branches of the `if' in this loop does a `continue',
10625 we will `break' the loop after the `if'. */
10629 /* If we have an operand of (clobber (const_int 0)), fail. */
10630 if (GET_CODE (varop
) == CLOBBER
)
10633 /* Convert ROTATERT to ROTATE. */
10634 if (code
== ROTATERT
)
10636 unsigned int bitsize
= GET_MODE_UNIT_PRECISION (result_mode
);
10638 count
= bitsize
- count
;
10641 shift_mode
= result_mode
;
10642 if (shift_mode
!= mode
)
10644 /* We only change the modes of scalar shifts. */
10645 int_mode
= as_a
<scalar_int_mode
> (mode
);
10646 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10647 shift_mode
= try_widen_shift_mode (code
, varop
, count
,
10648 int_result_mode
, int_mode
,
10649 outer_op
, outer_const
);
10652 scalar_int_mode shift_unit_mode
10653 = as_a
<scalar_int_mode
> (GET_MODE_INNER (shift_mode
));
10655 /* Handle cases where the count is greater than the size of the mode
10656 minus 1. For ASHIFT, use the size minus one as the count (this can
10657 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10658 take the count modulo the size. For other shifts, the result is
10661 Since these shifts are being produced by the compiler by combining
10662 multiple operations, each of which are defined, we know what the
10663 result is supposed to be. */
10665 if (count
> (GET_MODE_PRECISION (shift_unit_mode
) - 1))
10667 if (code
== ASHIFTRT
)
10668 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10669 else if (code
== ROTATE
|| code
== ROTATERT
)
10670 count
%= GET_MODE_PRECISION (shift_unit_mode
);
10673 /* We can't simply return zero because there may be an
10675 varop
= const0_rtx
;
10681 /* If we discovered we had to complement VAROP, leave. Making a NOT
10682 here would cause an infinite loop. */
10686 if (shift_mode
== shift_unit_mode
)
10688 /* An arithmetic right shift of a quantity known to be -1 or 0
10690 if (code
== ASHIFTRT
10691 && (num_sign_bit_copies (varop
, shift_unit_mode
)
10692 == GET_MODE_PRECISION (shift_unit_mode
)))
10698 /* If we are doing an arithmetic right shift and discarding all but
10699 the sign bit copies, this is equivalent to doing a shift by the
10700 bitsize minus one. Convert it into that shift because it will
10701 often allow other simplifications. */
10703 if (code
== ASHIFTRT
10704 && (count
+ num_sign_bit_copies (varop
, shift_unit_mode
)
10705 >= GET_MODE_PRECISION (shift_unit_mode
)))
10706 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10708 /* We simplify the tests below and elsewhere by converting
10709 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10710 `make_compound_operation' will convert it to an ASHIFTRT for
10711 those machines (such as VAX) that don't have an LSHIFTRT. */
10712 if (code
== ASHIFTRT
10713 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10714 && val_signbit_known_clear_p (shift_unit_mode
,
10715 nonzero_bits (varop
,
10719 if (((code
== LSHIFTRT
10720 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10721 && !(nonzero_bits (varop
, shift_unit_mode
) >> count
))
10723 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10724 && !((nonzero_bits (varop
, shift_unit_mode
) << count
)
10725 & GET_MODE_MASK (shift_unit_mode
))))
10726 && !side_effects_p (varop
))
10727 varop
= const0_rtx
;
10730 switch (GET_CODE (varop
))
10736 new_rtx
= expand_compound_operation (varop
);
10737 if (new_rtx
!= varop
)
10745 /* The following rules apply only to scalars. */
10746 if (shift_mode
!= shift_unit_mode
)
10748 int_mode
= as_a
<scalar_int_mode
> (mode
);
10750 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10751 minus the width of a smaller mode, we can do this with a
10752 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10753 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10754 && ! mode_dependent_address_p (XEXP (varop
, 0),
10755 MEM_ADDR_SPACE (varop
))
10756 && ! MEM_VOLATILE_P (varop
)
10757 && (int_mode_for_size (GET_MODE_BITSIZE (int_mode
) - count
, 1)
10760 new_rtx
= adjust_address_nv (varop
, tmode
,
10761 BYTES_BIG_ENDIAN
? 0
10762 : count
/ BITS_PER_UNIT
);
10764 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10765 : ZERO_EXTEND
, int_mode
, new_rtx
);
10772 /* The following rules apply only to scalars. */
10773 if (shift_mode
!= shift_unit_mode
)
10775 int_mode
= as_a
<scalar_int_mode
> (mode
);
10776 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10778 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10779 the same number of words as what we've seen so far. Then store
10780 the widest mode in MODE. */
10781 if (subreg_lowpart_p (varop
)
10782 && is_int_mode (GET_MODE (SUBREG_REG (varop
)), &inner_mode
)
10783 && GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (int_varop_mode
)
10784 && (CEIL (GET_MODE_SIZE (inner_mode
), UNITS_PER_WORD
)
10785 == CEIL (GET_MODE_SIZE (int_mode
), UNITS_PER_WORD
))
10786 && GET_MODE_CLASS (int_varop_mode
) == MODE_INT
)
10788 varop
= SUBREG_REG (varop
);
10789 if (GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (int_mode
))
10796 /* Some machines use MULT instead of ASHIFT because MULT
10797 is cheaper. But it is still better on those machines to
10798 merge two shifts into one. */
10799 if (CONST_INT_P (XEXP (varop
, 1))
10800 && (log2
= exact_log2 (UINTVAL (XEXP (varop
, 1)))) >= 0)
10802 rtx log2_rtx
= gen_int_shift_amount (GET_MODE (varop
), log2
);
10803 varop
= simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10804 XEXP (varop
, 0), log2_rtx
);
10810 /* Similar, for when divides are cheaper. */
10811 if (CONST_INT_P (XEXP (varop
, 1))
10812 && (log2
= exact_log2 (UINTVAL (XEXP (varop
, 1)))) >= 0)
10814 rtx log2_rtx
= gen_int_shift_amount (GET_MODE (varop
), log2
);
10815 varop
= simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10816 XEXP (varop
, 0), log2_rtx
);
10822 /* If we are extracting just the sign bit of an arithmetic
10823 right shift, that shift is not needed. However, the sign
10824 bit of a wider mode may be different from what would be
10825 interpreted as the sign bit in a narrower mode, so, if
10826 the result is narrower, don't discard the shift. */
10827 if (code
== LSHIFTRT
10828 && count
== (GET_MODE_UNIT_BITSIZE (result_mode
) - 1)
10829 && (GET_MODE_UNIT_BITSIZE (result_mode
)
10830 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop
))))
10832 varop
= XEXP (varop
, 0);
10841 /* The following rules apply only to scalars. */
10842 if (shift_mode
!= shift_unit_mode
)
10844 int_mode
= as_a
<scalar_int_mode
> (mode
);
10845 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10846 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10848 /* Here we have two nested shifts. The result is usually the
10849 AND of a new shift with a mask. We compute the result below. */
10850 if (CONST_INT_P (XEXP (varop
, 1))
10851 && INTVAL (XEXP (varop
, 1)) >= 0
10852 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (int_varop_mode
)
10853 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
10854 && HWI_COMPUTABLE_MODE_P (int_mode
))
10856 enum rtx_code first_code
= GET_CODE (varop
);
10857 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10858 unsigned HOST_WIDE_INT mask
;
10861 /* We have one common special case. We can't do any merging if
10862 the inner code is an ASHIFTRT of a smaller mode. However, if
10863 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10864 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10865 we can convert it to
10866 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10867 This simplifies certain SIGN_EXTEND operations. */
10868 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10869 && count
== (GET_MODE_PRECISION (int_result_mode
)
10870 - GET_MODE_PRECISION (int_varop_mode
)))
10872 /* C3 has the low-order C1 bits zero. */
10874 mask
= GET_MODE_MASK (int_mode
)
10875 & ~((HOST_WIDE_INT_1U
<< first_count
) - 1);
10877 varop
= simplify_and_const_int (NULL_RTX
, int_result_mode
,
10878 XEXP (varop
, 0), mask
);
10879 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
,
10880 int_result_mode
, varop
, count
);
10881 count
= first_count
;
10886 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10887 than C1 high-order bits equal to the sign bit, we can convert
10888 this to either an ASHIFT or an ASHIFTRT depending on the
10891 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10893 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10894 && int_varop_mode
== shift_unit_mode
10895 && (num_sign_bit_copies (XEXP (varop
, 0), shift_unit_mode
)
10898 varop
= XEXP (varop
, 0);
10899 count
-= first_count
;
10909 /* There are some cases we can't do. If CODE is ASHIFTRT,
10910 we can only do this if FIRST_CODE is also ASHIFTRT.
10912 We can't do the case when CODE is ROTATE and FIRST_CODE is
10915 If the mode of this shift is not the mode of the outer shift,
10916 we can't do this if either shift is a right shift or ROTATE.
10918 Finally, we can't do any of these if the mode is too wide
10919 unless the codes are the same.
10921 Handle the case where the shift codes are the same
10924 if (code
== first_code
)
10926 if (int_varop_mode
!= int_result_mode
10927 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10928 || code
== ROTATE
))
10931 count
+= first_count
;
10932 varop
= XEXP (varop
, 0);
10936 if (code
== ASHIFTRT
10937 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10938 || GET_MODE_PRECISION (int_mode
) > HOST_BITS_PER_WIDE_INT
10939 || (int_varop_mode
!= int_result_mode
10940 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10941 || first_code
== ROTATE
10942 || code
== ROTATE
)))
10945 /* To compute the mask to apply after the shift, shift the
10946 nonzero bits of the inner shift the same way the
10947 outer shift will. */
10949 mask_rtx
= gen_int_mode (nonzero_bits (varop
, int_varop_mode
),
10951 rtx count_rtx
= gen_int_shift_amount (int_result_mode
, count
);
10953 = simplify_const_binary_operation (code
, int_result_mode
,
10954 mask_rtx
, count_rtx
);
10956 /* Give up if we can't compute an outer operation to use. */
10958 || !CONST_INT_P (mask_rtx
)
10959 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10961 int_result_mode
, &complement_p
))
10964 /* If the shifts are in the same direction, we add the
10965 counts. Otherwise, we subtract them. */
10966 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10967 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10968 count
+= first_count
;
10970 count
-= first_count
;
10972 /* If COUNT is positive, the new shift is usually CODE,
10973 except for the two exceptions below, in which case it is
10974 FIRST_CODE. If the count is negative, FIRST_CODE should
10977 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10978 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10980 else if (count
< 0)
10981 code
= first_code
, count
= -count
;
10983 varop
= XEXP (varop
, 0);
10987 /* If we have (A << B << C) for any shift, we can convert this to
10988 (A << C << B). This wins if A is a constant. Only try this if
10989 B is not a constant. */
10991 else if (GET_CODE (varop
) == code
10992 && CONST_INT_P (XEXP (varop
, 0))
10993 && !CONST_INT_P (XEXP (varop
, 1)))
10995 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10996 sure the result will be masked. See PR70222. */
10997 if (code
== LSHIFTRT
10998 && int_mode
!= int_result_mode
10999 && !merge_outer_ops (&outer_op
, &outer_const
, AND
,
11000 GET_MODE_MASK (int_result_mode
)
11001 >> orig_count
, int_result_mode
,
11004 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
11005 up outer sign extension (often left and right shift) is
11006 hardly more efficient than the original. See PR70429.
11007 Similarly punt for rotates with different modes.
11009 if ((code
== ASHIFTRT
|| code
== ROTATE
)
11010 && int_mode
!= int_result_mode
)
11013 rtx count_rtx
= gen_int_shift_amount (int_result_mode
, count
);
11014 rtx new_rtx
= simplify_const_binary_operation (code
, int_mode
,
11017 varop
= gen_rtx_fmt_ee (code
, int_mode
, new_rtx
, XEXP (varop
, 1));
11024 /* The following rules apply only to scalars. */
11025 if (shift_mode
!= shift_unit_mode
)
11028 /* Make this fit the case below. */
11029 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
11035 /* The following rules apply only to scalars. */
11036 if (shift_mode
!= shift_unit_mode
)
11038 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
11039 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11041 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
11042 with C the size of VAROP - 1 and the shift is logical if
11043 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11044 we have an (le X 0) operation. If we have an arithmetic shift
11045 and STORE_FLAG_VALUE is 1 or we have a logical shift with
11046 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
11048 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
11049 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
11050 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
11051 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
11052 && count
== (GET_MODE_PRECISION (int_varop_mode
) - 1)
11053 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
11056 varop
= gen_rtx_LE (int_varop_mode
, XEXP (varop
, 1),
11059 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
11060 varop
= gen_rtx_NEG (int_varop_mode
, varop
);
11065 /* If we have (shift (logical)), move the logical to the outside
11066 to allow it to possibly combine with another logical and the
11067 shift to combine with another shift. This also canonicalizes to
11068 what a ZERO_EXTRACT looks like. Also, some machines have
11069 (and (shift)) insns. */
11071 if (CONST_INT_P (XEXP (varop
, 1))
11072 /* We can't do this if we have (ashiftrt (xor)) and the
11073 constant has its sign bit set in shift_unit_mode with
11074 shift_unit_mode wider than result_mode. */
11075 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
11076 && int_result_mode
!= shift_unit_mode
11077 && trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
11078 shift_unit_mode
) < 0)
11079 && (new_rtx
= simplify_const_binary_operation
11080 (code
, int_result_mode
,
11081 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
11082 gen_int_shift_amount (int_result_mode
, count
))) != 0
11083 && CONST_INT_P (new_rtx
)
11084 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
11085 INTVAL (new_rtx
), int_result_mode
,
11088 varop
= XEXP (varop
, 0);
11092 /* If we can't do that, try to simplify the shift in each arm of the
11093 logical expression, make a new logical expression, and apply
11094 the inverse distributive law. This also can't be done for
11095 (ashiftrt (xor)) where we've widened the shift and the constant
11096 changes the sign bit. */
11097 if (CONST_INT_P (XEXP (varop
, 1))
11098 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
11099 && int_result_mode
!= shift_unit_mode
11100 && trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
11101 shift_unit_mode
) < 0))
11103 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_unit_mode
,
11104 XEXP (varop
, 0), count
);
11105 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_unit_mode
,
11106 XEXP (varop
, 1), count
);
11108 varop
= simplify_gen_binary (GET_CODE (varop
), shift_unit_mode
,
11110 varop
= apply_distributive_law (varop
);
11118 /* The following rules apply only to scalars. */
11119 if (shift_mode
!= shift_unit_mode
)
11121 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11123 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11124 says that the sign bit can be tested, FOO has mode MODE, C is
11125 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11126 that may be nonzero. */
11127 if (code
== LSHIFTRT
11128 && XEXP (varop
, 1) == const0_rtx
11129 && GET_MODE (XEXP (varop
, 0)) == int_result_mode
11130 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11131 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
11132 && STORE_FLAG_VALUE
== -1
11133 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1
11134 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
11135 int_result_mode
, &complement_p
))
11137 varop
= XEXP (varop
, 0);
11144 /* The following rules apply only to scalars. */
11145 if (shift_mode
!= shift_unit_mode
)
11147 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11149 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11150 than the number of bits in the mode is equivalent to A. */
11151 if (code
== LSHIFTRT
11152 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11153 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1)
11155 varop
= XEXP (varop
, 0);
11160 /* NEG commutes with ASHIFT since it is multiplication. Move the
11161 NEG outside to allow shifts to combine. */
11163 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0,
11164 int_result_mode
, &complement_p
))
11166 varop
= XEXP (varop
, 0);
11172 /* The following rules apply only to scalars. */
11173 if (shift_mode
!= shift_unit_mode
)
11175 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11177 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11178 is one less than the number of bits in the mode is
11179 equivalent to (xor A 1). */
11180 if (code
== LSHIFTRT
11181 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11182 && XEXP (varop
, 1) == constm1_rtx
11183 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1
11184 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
11185 int_result_mode
, &complement_p
))
11188 varop
= XEXP (varop
, 0);
11192 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11193 that might be nonzero in BAR are those being shifted out and those
11194 bits are known zero in FOO, we can replace the PLUS with FOO.
11195 Similarly in the other operand order. This code occurs when
11196 we are computing the size of a variable-size array. */
11198 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11199 && count
< HOST_BITS_PER_WIDE_INT
11200 && nonzero_bits (XEXP (varop
, 1), int_result_mode
) >> count
== 0
11201 && (nonzero_bits (XEXP (varop
, 1), int_result_mode
)
11202 & nonzero_bits (XEXP (varop
, 0), int_result_mode
)) == 0)
11204 varop
= XEXP (varop
, 0);
11207 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11208 && count
< HOST_BITS_PER_WIDE_INT
11209 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
11210 && (nonzero_bits (XEXP (varop
, 0), int_result_mode
)
11212 && (nonzero_bits (XEXP (varop
, 0), int_result_mode
)
11213 & nonzero_bits (XEXP (varop
, 1), int_result_mode
)) == 0)
11215 varop
= XEXP (varop
, 1);
11219 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11221 && CONST_INT_P (XEXP (varop
, 1))
11222 && (new_rtx
= simplify_const_binary_operation
11223 (ASHIFT
, int_result_mode
,
11224 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
11225 gen_int_shift_amount (int_result_mode
, count
))) != 0
11226 && CONST_INT_P (new_rtx
)
11227 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
11228 INTVAL (new_rtx
), int_result_mode
,
11231 varop
= XEXP (varop
, 0);
11235 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11236 signbit', and attempt to change the PLUS to an XOR and move it to
11237 the outer operation as is done above in the AND/IOR/XOR case
11238 leg for shift(logical). See details in logical handling above
11239 for reasoning in doing so. */
11240 if (code
== LSHIFTRT
11241 && CONST_INT_P (XEXP (varop
, 1))
11242 && mode_signbit_p (int_result_mode
, XEXP (varop
, 1))
11243 && (new_rtx
= simplify_const_binary_operation
11244 (code
, int_result_mode
,
11245 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
11246 gen_int_shift_amount (int_result_mode
, count
))) != 0
11247 && CONST_INT_P (new_rtx
)
11248 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
11249 INTVAL (new_rtx
), int_result_mode
,
11252 varop
= XEXP (varop
, 0);
11259 /* The following rules apply only to scalars. */
11260 if (shift_mode
!= shift_unit_mode
)
11262 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
11264 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11265 with C the size of VAROP - 1 and the shift is logical if
11266 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11267 we have a (gt X 0) operation. If the shift is arithmetic with
11268 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11269 we have a (neg (gt X 0)) operation. */
11271 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
11272 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
11273 && count
== (GET_MODE_PRECISION (int_varop_mode
) - 1)
11274 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
11275 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11276 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
11277 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
11280 varop
= gen_rtx_GT (int_varop_mode
, XEXP (varop
, 1),
11283 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
11284 varop
= gen_rtx_NEG (int_varop_mode
, varop
);
11291 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11292 if the truncate does not affect the value. */
11293 if (code
== LSHIFTRT
11294 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
11295 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11296 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
11297 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop
, 0)))
11298 - GET_MODE_UNIT_PRECISION (GET_MODE (varop
)))))
11300 rtx varop_inner
= XEXP (varop
, 0);
11301 int new_count
= count
+ INTVAL (XEXP (varop_inner
, 1));
11302 rtx new_count_rtx
= gen_int_shift_amount (GET_MODE (varop_inner
),
11304 varop_inner
= gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
11305 XEXP (varop_inner
, 0),
11307 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
11320 shift_mode
= result_mode
;
11321 if (shift_mode
!= mode
)
11323 /* We only change the modes of scalar shifts. */
11324 int_mode
= as_a
<scalar_int_mode
> (mode
);
11325 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11326 shift_mode
= try_widen_shift_mode (code
, varop
, count
, int_result_mode
,
11327 int_mode
, outer_op
, outer_const
);
11330 /* We have now finished analyzing the shift. The result should be
11331 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11332 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11333 to the result of the shift. OUTER_CONST is the relevant constant,
11334 but we must turn off all bits turned off in the shift. */
11336 if (outer_op
== UNKNOWN
11337 && orig_code
== code
&& orig_count
== count
11338 && varop
== orig_varop
11339 && shift_mode
== GET_MODE (varop
))
11342 /* Make a SUBREG if necessary. If we can't make it, fail. */
11343 varop
= gen_lowpart (shift_mode
, varop
);
11344 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
11347 /* If we have an outer operation and we just made a shift, it is
11348 possible that we could have simplified the shift were it not
11349 for the outer operation. So try to do the simplification
11352 if (outer_op
!= UNKNOWN
)
11353 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
11358 x
= simplify_gen_binary (code
, shift_mode
, varop
,
11359 gen_int_shift_amount (shift_mode
, count
));
11361 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11362 turn off all the bits that the shift would have turned off. */
11363 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
11364 /* We only change the modes of scalar shifts. */
11365 x
= simplify_and_const_int (NULL_RTX
, as_a
<scalar_int_mode
> (shift_mode
),
11366 x
, GET_MODE_MASK (result_mode
) >> orig_count
);
11368 /* Do the remainder of the processing in RESULT_MODE. */
11369 x
= gen_lowpart_or_truncate (result_mode
, x
);
11371 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11374 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
11376 if (outer_op
!= UNKNOWN
)
11378 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11380 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
11381 && GET_MODE_PRECISION (int_result_mode
) < HOST_BITS_PER_WIDE_INT
)
11382 outer_const
= trunc_int_for_mode (outer_const
, int_result_mode
);
11384 if (outer_op
== AND
)
11385 x
= simplify_and_const_int (NULL_RTX
, int_result_mode
, x
, outer_const
);
11386 else if (outer_op
== SET
)
11388 /* This means that we have determined that the result is
11389 equivalent to a constant. This should be rare. */
11390 if (!side_effects_p (x
))
11391 x
= GEN_INT (outer_const
);
11393 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
11394 x
= simplify_gen_unary (outer_op
, int_result_mode
, x
, int_result_mode
);
11396 x
= simplify_gen_binary (outer_op
, int_result_mode
, x
,
11397 GEN_INT (outer_const
));
11403 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11404 The result of the shift is RESULT_MODE. If we cannot simplify it,
11405 return X or, if it is NULL, synthesize the expression with
11406 simplify_gen_binary. Otherwise, return a simplified value.
11408 The shift is normally computed in the widest mode we find in VAROP, as
11409 long as it isn't a different number of words than RESULT_MODE. Exceptions
11410 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11413 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
11414 rtx varop
, int count
)
11416 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
11421 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
,
11422 gen_int_shift_amount (GET_MODE (varop
), count
));
11423 if (GET_MODE (x
) != result_mode
)
11424 x
= gen_lowpart (result_mode
, x
);
11429 /* A subroutine of recog_for_combine. See there for arguments and
11433 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11435 rtx pat
= *pnewpat
;
11436 rtx pat_without_clobbers
;
11437 int insn_code_number
;
11438 int num_clobbers_to_add
= 0;
11440 rtx notes
= NULL_RTX
;
11441 rtx old_notes
, old_pat
;
11444 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11445 we use to indicate that something didn't match. If we find such a
11446 thing, force rejection. */
11447 if (GET_CODE (pat
) == PARALLEL
)
11448 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
11449 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
11450 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
11453 old_pat
= PATTERN (insn
);
11454 old_notes
= REG_NOTES (insn
);
11455 PATTERN (insn
) = pat
;
11456 REG_NOTES (insn
) = NULL_RTX
;
11458 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11459 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11461 if (insn_code_number
< 0)
11462 fputs ("Failed to match this instruction:\n", dump_file
);
11464 fputs ("Successfully matched this instruction:\n", dump_file
);
11465 print_rtl_single (dump_file
, pat
);
11468 /* If it isn't, there is the possibility that we previously had an insn
11469 that clobbered some register as a side effect, but the combined
11470 insn doesn't need to do that. So try once more without the clobbers
11471 unless this represents an ASM insn. */
11473 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
11474 && GET_CODE (pat
) == PARALLEL
)
11478 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
11479 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
11482 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
11486 SUBST_INT (XVECLEN (pat
, 0), pos
);
11489 pat
= XVECEXP (pat
, 0, 0);
11491 PATTERN (insn
) = pat
;
11492 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11493 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11495 if (insn_code_number
< 0)
11496 fputs ("Failed to match this instruction:\n", dump_file
);
11498 fputs ("Successfully matched this instruction:\n", dump_file
);
11499 print_rtl_single (dump_file
, pat
);
11503 pat_without_clobbers
= pat
;
11505 PATTERN (insn
) = old_pat
;
11506 REG_NOTES (insn
) = old_notes
;
11508 /* Recognize all noop sets, these will be killed by followup pass. */
11509 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
11510 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
11512 /* If we had any clobbers to add, make a new pattern than contains
11513 them. Then check to make sure that all of them are dead. */
11514 if (num_clobbers_to_add
)
11516 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
11517 rtvec_alloc (GET_CODE (pat
) == PARALLEL
11518 ? (XVECLEN (pat
, 0)
11519 + num_clobbers_to_add
)
11520 : num_clobbers_to_add
+ 1));
11522 if (GET_CODE (pat
) == PARALLEL
)
11523 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11524 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
11526 XVECEXP (newpat
, 0, 0) = pat
;
11528 add_clobbers (newpat
, insn_code_number
);
11530 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
11531 i
< XVECLEN (newpat
, 0); i
++)
11533 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
11534 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
11536 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
11538 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
11539 notes
= alloc_reg_note (REG_UNUSED
,
11540 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11546 if (insn_code_number
>= 0
11547 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11549 old_pat
= PATTERN (insn
);
11550 old_notes
= REG_NOTES (insn
);
11551 old_icode
= INSN_CODE (insn
);
11552 PATTERN (insn
) = pat
;
11553 REG_NOTES (insn
) = notes
;
11554 INSN_CODE (insn
) = insn_code_number
;
11556 /* Allow targets to reject combined insn. */
11557 if (!targetm
.legitimate_combined_insn (insn
))
11559 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11560 fputs ("Instruction not appropriate for target.",
11563 /* Callers expect recog_for_combine to strip
11564 clobbers from the pattern on failure. */
11565 pat
= pat_without_clobbers
;
11568 insn_code_number
= -1;
11571 PATTERN (insn
) = old_pat
;
11572 REG_NOTES (insn
) = old_notes
;
11573 INSN_CODE (insn
) = old_icode
;
11579 return insn_code_number
;
11582 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11583 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11584 Return whether anything was so changed. */
11587 change_zero_ext (rtx pat
)
11589 bool changed
= false;
11590 rtx
*src
= &SET_SRC (pat
);
11592 subrtx_ptr_iterator::array_type array
;
11593 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11596 scalar_int_mode mode
, inner_mode
;
11597 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
))
11601 if (GET_CODE (x
) == ZERO_EXTRACT
11602 && CONST_INT_P (XEXP (x
, 1))
11603 && CONST_INT_P (XEXP (x
, 2))
11604 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
)
11605 && GET_MODE_PRECISION (inner_mode
) <= GET_MODE_PRECISION (mode
))
11607 size
= INTVAL (XEXP (x
, 1));
11609 int start
= INTVAL (XEXP (x
, 2));
11610 if (BITS_BIG_ENDIAN
)
11611 start
= GET_MODE_PRECISION (inner_mode
) - size
- start
;
11614 x
= gen_rtx_LSHIFTRT (inner_mode
, XEXP (x
, 0),
11615 gen_int_shift_amount (inner_mode
, start
));
11619 if (mode
!= inner_mode
)
11621 if (REG_P (x
) && HARD_REGISTER_P (x
)
11622 && !can_change_dest_mode (x
, 0, mode
))
11625 x
= gen_lowpart_SUBREG (mode
, x
);
11628 else if (GET_CODE (x
) == ZERO_EXTEND
11629 && GET_CODE (XEXP (x
, 0)) == SUBREG
11630 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x
, 0))))
11631 && !paradoxical_subreg_p (XEXP (x
, 0))
11632 && subreg_lowpart_p (XEXP (x
, 0)))
11634 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
11635 size
= GET_MODE_PRECISION (inner_mode
);
11636 x
= SUBREG_REG (XEXP (x
, 0));
11637 if (GET_MODE (x
) != mode
)
11639 if (REG_P (x
) && HARD_REGISTER_P (x
)
11640 && !can_change_dest_mode (x
, 0, mode
))
11643 x
= gen_lowpart_SUBREG (mode
, x
);
11646 else if (GET_CODE (x
) == ZERO_EXTEND
11647 && REG_P (XEXP (x
, 0))
11648 && HARD_REGISTER_P (XEXP (x
, 0))
11649 && can_change_dest_mode (XEXP (x
, 0), 0, mode
))
11651 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
11652 size
= GET_MODE_PRECISION (inner_mode
);
11653 x
= gen_rtx_REG (mode
, REGNO (XEXP (x
, 0)));
11658 if (!(GET_CODE (x
) == LSHIFTRT
11659 && CONST_INT_P (XEXP (x
, 1))
11660 && size
+ INTVAL (XEXP (x
, 1)) == GET_MODE_PRECISION (mode
)))
11662 wide_int mask
= wi::mask (size
, false, GET_MODE_PRECISION (mode
));
11663 x
= gen_rtx_AND (mode
, x
, immed_wide_int_const (mask
, mode
));
11671 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11672 maybe_swap_commutative_operands (**iter
);
11674 rtx
*dst
= &SET_DEST (pat
);
11675 scalar_int_mode mode
;
11676 if (GET_CODE (*dst
) == ZERO_EXTRACT
11677 && REG_P (XEXP (*dst
, 0))
11678 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (*dst
, 0)), &mode
)
11679 && CONST_INT_P (XEXP (*dst
, 1))
11680 && CONST_INT_P (XEXP (*dst
, 2)))
11682 rtx reg
= XEXP (*dst
, 0);
11683 int width
= INTVAL (XEXP (*dst
, 1));
11684 int offset
= INTVAL (XEXP (*dst
, 2));
11685 int reg_width
= GET_MODE_PRECISION (mode
);
11686 if (BITS_BIG_ENDIAN
)
11687 offset
= reg_width
- width
- offset
;
11690 wide_int mask
= wi::shifted_mask (offset
, width
, true, reg_width
);
11691 wide_int mask2
= wi::shifted_mask (offset
, width
, false, reg_width
);
11692 x
= gen_rtx_AND (mode
, reg
, immed_wide_int_const (mask
, mode
));
11694 y
= gen_rtx_ASHIFT (mode
, SET_SRC (pat
), GEN_INT (offset
));
11697 z
= gen_rtx_AND (mode
, y
, immed_wide_int_const (mask2
, mode
));
11698 w
= gen_rtx_IOR (mode
, x
, z
);
11699 SUBST (SET_DEST (pat
), reg
);
11700 SUBST (SET_SRC (pat
), w
);
11708 /* Like recog, but we receive the address of a pointer to a new pattern.
11709 We try to match the rtx that the pointer points to.
11710 If that fails, we may try to modify or replace the pattern,
11711 storing the replacement into the same pointer object.
11713 Modifications include deletion or addition of CLOBBERs. If the
11714 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11715 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11716 (and undo if that fails).
11718 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11719 the CLOBBERs are placed.
11721 The value is the final insn code from the pattern ultimately matched,
11725 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11727 rtx pat
= *pnewpat
;
11728 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11729 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11730 return insn_code_number
;
11732 void *marker
= get_undo_marker ();
11733 bool changed
= false;
11735 if (GET_CODE (pat
) == SET
)
11736 changed
= change_zero_ext (pat
);
11737 else if (GET_CODE (pat
) == PARALLEL
)
11740 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11742 rtx set
= XVECEXP (pat
, 0, i
);
11743 if (GET_CODE (set
) == SET
)
11744 changed
|= change_zero_ext (set
);
11750 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11752 if (insn_code_number
< 0)
11753 undo_to_marker (marker
);
11756 return insn_code_number
;
11759 /* Like gen_lowpart_general but for use by combine. In combine it
11760 is not possible to create any new pseudoregs. However, it is
11761 safe to create invalid memory addresses, because combine will
11762 try to recognize them and all they will do is make the combine
11765 If for some reason this cannot do its job, an rtx
11766 (clobber (const_int 0)) is returned.
11767 An insn containing that will not be recognized. */
11770 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11772 machine_mode imode
= GET_MODE (x
);
11775 if (omode
== imode
)
11778 /* We can only support MODE being wider than a word if X is a
11779 constant integer or has a mode the same size. */
11780 if (maybe_gt (GET_MODE_SIZE (omode
), UNITS_PER_WORD
)
11781 && ! (CONST_SCALAR_INT_P (x
)
11782 || known_eq (GET_MODE_SIZE (imode
), GET_MODE_SIZE (omode
))))
11785 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11786 won't know what to do. So we will strip off the SUBREG here and
11787 process normally. */
11788 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11790 x
= SUBREG_REG (x
);
11792 /* For use in case we fall down into the address adjustments
11793 further below, we need to adjust the known mode and size of
11794 x; imode and isize, since we just adjusted x. */
11795 imode
= GET_MODE (x
);
11797 if (imode
== omode
)
11801 result
= gen_lowpart_common (omode
, x
);
11808 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11810 if (MEM_VOLATILE_P (x
)
11811 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11814 /* If we want to refer to something bigger than the original memref,
11815 generate a paradoxical subreg instead. That will force a reload
11816 of the original memref X. */
11817 if (paradoxical_subreg_p (omode
, imode
))
11818 return gen_rtx_SUBREG (omode
, x
, 0);
11820 poly_int64 offset
= byte_lowpart_offset (omode
, imode
);
11821 return adjust_address_nv (x
, omode
, offset
);
11824 /* If X is a comparison operator, rewrite it in a new mode. This
11825 probably won't match, but may allow further simplifications. */
11826 else if (COMPARISON_P (x
)
11827 && SCALAR_INT_MODE_P (imode
)
11828 && SCALAR_INT_MODE_P (omode
))
11829 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11831 /* If we couldn't simplify X any other way, just enclose it in a
11832 SUBREG. Normally, this SUBREG won't match, but some patterns may
11833 include an explicit SUBREG or we may simplify it further in combine. */
11838 if (imode
== VOIDmode
)
11840 imode
= int_mode_for_mode (omode
).require ();
11841 x
= gen_lowpart_common (imode
, x
);
11845 res
= lowpart_subreg (omode
, x
, imode
);
11851 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11854 /* Try to simplify a comparison between OP0 and a constant OP1,
11855 where CODE is the comparison code that will be tested, into a
11856 (CODE OP0 const0_rtx) form.
11858 The result is a possibly different comparison code to use.
11859 *POP1 may be updated. */
11861 static enum rtx_code
11862 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11863 rtx op0
, rtx
*pop1
)
11865 scalar_int_mode int_mode
;
11866 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11868 /* Get the constant we are comparing against and turn off all bits
11869 not on in our mode. */
11870 if (mode
!= VOIDmode
)
11871 const_op
= trunc_int_for_mode (const_op
, mode
);
11873 /* If we are comparing against a constant power of two and the value
11874 being compared can only have that single bit nonzero (e.g., it was
11875 `and'ed with that bit), we can replace this with a comparison
11878 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11879 || code
== LT
|| code
== LTU
)
11880 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11881 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11882 && pow2p_hwi (const_op
& GET_MODE_MASK (int_mode
))
11883 && (nonzero_bits (op0
, int_mode
)
11884 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (int_mode
))))
11886 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11890 /* Similarly, if we are comparing a value known to be either -1 or
11891 0 with -1, change it to the opposite comparison against zero. */
11893 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11894 || code
== GEU
|| code
== LTU
)
11895 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11896 && num_sign_bit_copies (op0
, int_mode
) == GET_MODE_PRECISION (int_mode
))
11898 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11902 /* Do some canonicalizations based on the comparison code. We prefer
11903 comparisons against zero and then prefer equality comparisons.
11904 If we can reduce the size of a constant, we will do that too. */
11908 /* < C is equivalent to <= (C - 1) */
11913 /* ... fall through to LE case below. */
11914 gcc_fallthrough ();
11920 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11927 /* If we are doing a <= 0 comparison on a value known to have
11928 a zero sign bit, we can replace this with == 0. */
11929 else if (const_op
== 0
11930 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11931 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11932 && (nonzero_bits (op0
, int_mode
)
11933 & (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11939 /* >= C is equivalent to > (C - 1). */
11944 /* ... fall through to GT below. */
11945 gcc_fallthrough ();
11951 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11958 /* If we are doing a > 0 comparison on a value known to have
11959 a zero sign bit, we can replace this with != 0. */
11960 else if (const_op
== 0
11961 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11962 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11963 && (nonzero_bits (op0
, int_mode
)
11964 & (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11970 /* < C is equivalent to <= (C - 1). */
11975 /* ... fall through ... */
11976 gcc_fallthrough ();
11978 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11979 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11980 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11981 && ((unsigned HOST_WIDE_INT
) const_op
11982 == HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11992 /* unsigned <= 0 is equivalent to == 0 */
11995 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11996 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11997 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11998 && ((unsigned HOST_WIDE_INT
) const_op
11999 == ((HOST_WIDE_INT_1U
12000 << (GET_MODE_PRECISION (int_mode
) - 1)) - 1)))
12008 /* >= C is equivalent to > (C - 1). */
12013 /* ... fall through ... */
12014 gcc_fallthrough ();
12017 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
12018 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
12019 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
12020 && ((unsigned HOST_WIDE_INT
) const_op
12021 == HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
12031 /* unsigned > 0 is equivalent to != 0 */
12034 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
12035 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
12036 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
12037 && ((unsigned HOST_WIDE_INT
) const_op
12038 == (HOST_WIDE_INT_1U
12039 << (GET_MODE_PRECISION (int_mode
) - 1)) - 1))
12050 *pop1
= GEN_INT (const_op
);
12054 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
12055 comparison code that will be tested.
12057 The result is a possibly different comparison code to use. *POP0 and
12058 *POP1 may be updated.
12060 It is possible that we might detect that a comparison is either always
12061 true or always false. However, we do not perform general constant
12062 folding in combine, so this knowledge isn't useful. Such tautologies
12063 should have been detected earlier. Hence we ignore all such cases. */
12065 static enum rtx_code
12066 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
12072 scalar_int_mode mode
, inner_mode
, tmode
;
12073 opt_scalar_int_mode tmode_iter
;
12075 /* Try a few ways of applying the same transformation to both operands. */
12078 /* The test below this one won't handle SIGN_EXTENDs on these machines,
12079 so check specially. */
12080 if (!WORD_REGISTER_OPERATIONS
12081 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
12082 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
12083 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12084 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
12085 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
12086 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
12087 && is_a
<scalar_int_mode
> (GET_MODE (op0
), &mode
)
12088 && (is_a
<scalar_int_mode
>
12089 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))), &inner_mode
))
12090 && inner_mode
== GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0)))
12091 && CONST_INT_P (XEXP (op0
, 1))
12092 && XEXP (op0
, 1) == XEXP (op1
, 1)
12093 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12094 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
12095 && (INTVAL (XEXP (op0
, 1))
12096 == (GET_MODE_PRECISION (mode
)
12097 - GET_MODE_PRECISION (inner_mode
))))
12099 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
12100 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
12103 /* If both operands are the same constant shift, see if we can ignore the
12104 shift. We can if the shift is a rotate or if the bits shifted out of
12105 this shift are known to be zero for both inputs and if the type of
12106 comparison is compatible with the shift. */
12107 if (GET_CODE (op0
) == GET_CODE (op1
)
12108 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
12109 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
12110 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
12111 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
12112 || (GET_CODE (op0
) == ASHIFTRT
12113 && (code
!= GTU
&& code
!= LTU
12114 && code
!= GEU
&& code
!= LEU
)))
12115 && CONST_INT_P (XEXP (op0
, 1))
12116 && INTVAL (XEXP (op0
, 1)) >= 0
12117 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12118 && XEXP (op0
, 1) == XEXP (op1
, 1))
12120 machine_mode mode
= GET_MODE (op0
);
12121 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
12122 int shift_count
= INTVAL (XEXP (op0
, 1));
12124 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
12125 mask
&= (mask
>> shift_count
) << shift_count
;
12126 else if (GET_CODE (op0
) == ASHIFT
)
12127 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
12129 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
12130 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
12131 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
12136 /* If both operands are AND's of a paradoxical SUBREG by constant, the
12137 SUBREGs are of the same mode, and, in both cases, the AND would
12138 be redundant if the comparison was done in the narrower mode,
12139 do the comparison in the narrower mode (e.g., we are AND'ing with 1
12140 and the operand's possibly nonzero bits are 0xffffff01; in that case
12141 if we only care about QImode, we don't need the AND). This case
12142 occurs if the output mode of an scc insn is not SImode and
12143 STORE_FLAG_VALUE == 1 (e.g., the 386).
12145 Similarly, check for a case where the AND's are ZERO_EXTEND
12146 operations from some narrower mode even though a SUBREG is not
12149 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
12150 && CONST_INT_P (XEXP (op0
, 1))
12151 && CONST_INT_P (XEXP (op1
, 1)))
12153 rtx inner_op0
= XEXP (op0
, 0);
12154 rtx inner_op1
= XEXP (op1
, 0);
12155 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
12156 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
12159 if (paradoxical_subreg_p (inner_op0
)
12160 && GET_CODE (inner_op1
) == SUBREG
12161 && HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0
)))
12162 && (GET_MODE (SUBREG_REG (inner_op0
))
12163 == GET_MODE (SUBREG_REG (inner_op1
)))
12164 && ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
12165 GET_MODE (SUBREG_REG (inner_op0
)))) == 0
12166 && ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
12167 GET_MODE (SUBREG_REG (inner_op1
)))) == 0)
12169 op0
= SUBREG_REG (inner_op0
);
12170 op1
= SUBREG_REG (inner_op1
);
12172 /* The resulting comparison is always unsigned since we masked
12173 off the original sign bit. */
12174 code
= unsigned_condition (code
);
12180 FOR_EACH_MODE_UNTIL (tmode
,
12181 as_a
<scalar_int_mode
> (GET_MODE (op0
)))
12182 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
12184 op0
= gen_lowpart_or_truncate (tmode
, inner_op0
);
12185 op1
= gen_lowpart_or_truncate (tmode
, inner_op1
);
12186 code
= unsigned_condition (code
);
12195 /* If both operands are NOT, we can strip off the outer operation
12196 and adjust the comparison code for swapped operands; similarly for
12197 NEG, except that this must be an equality comparison. */
12198 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
12199 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
12200 && (code
== EQ
|| code
== NE
)))
12201 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
12207 /* If the first operand is a constant, swap the operands and adjust the
12208 comparison code appropriately, but don't do this if the second operand
12209 is already a constant integer. */
12210 if (swap_commutative_operands_p (op0
, op1
))
12212 std::swap (op0
, op1
);
12213 code
= swap_condition (code
);
12216 /* We now enter a loop during which we will try to simplify the comparison.
12217 For the most part, we only are concerned with comparisons with zero,
12218 but some things may really be comparisons with zero but not start
12219 out looking that way. */
12221 while (CONST_INT_P (op1
))
12223 machine_mode raw_mode
= GET_MODE (op0
);
12224 scalar_int_mode int_mode
;
12225 int equality_comparison_p
;
12226 int sign_bit_comparison_p
;
12227 int unsigned_comparison_p
;
12228 HOST_WIDE_INT const_op
;
12230 /* We only want to handle integral modes. This catches VOIDmode,
12231 CCmode, and the floating-point modes. An exception is that we
12232 can handle VOIDmode if OP0 is a COMPARE or a comparison
12235 if (GET_MODE_CLASS (raw_mode
) != MODE_INT
12236 && ! (raw_mode
== VOIDmode
12237 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
12240 /* Try to simplify the compare to constant, possibly changing the
12241 comparison op, and/or changing op1 to zero. */
12242 code
= simplify_compare_const (code
, raw_mode
, op0
, &op1
);
12243 const_op
= INTVAL (op1
);
12245 /* Compute some predicates to simplify code below. */
12247 equality_comparison_p
= (code
== EQ
|| code
== NE
);
12248 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
12249 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
12252 /* If this is a sign bit comparison and we can do arithmetic in
12253 MODE, say that we will only be needing the sign bit of OP0. */
12254 if (sign_bit_comparison_p
12255 && is_a
<scalar_int_mode
> (raw_mode
, &int_mode
)
12256 && HWI_COMPUTABLE_MODE_P (int_mode
))
12257 op0
= force_to_mode (op0
, int_mode
,
12259 << (GET_MODE_PRECISION (int_mode
) - 1),
12262 if (COMPARISON_P (op0
))
12264 /* We can't do anything if OP0 is a condition code value, rather
12265 than an actual data value. */
12267 || CC0_P (XEXP (op0
, 0))
12268 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
12271 /* Get the two operands being compared. */
12272 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
12273 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
12275 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
12277 /* Check for the cases where we simply want the result of the
12278 earlier test or the opposite of that result. */
12279 if (code
== NE
|| code
== EQ
12280 || (val_signbit_known_set_p (raw_mode
, STORE_FLAG_VALUE
)
12281 && (code
== LT
|| code
== GE
)))
12283 enum rtx_code new_code
;
12284 if (code
== LT
|| code
== NE
)
12285 new_code
= GET_CODE (op0
);
12287 new_code
= reversed_comparison_code (op0
, NULL
);
12289 if (new_code
!= UNKNOWN
)
12300 if (raw_mode
== VOIDmode
)
12302 scalar_int_mode mode
= as_a
<scalar_int_mode
> (raw_mode
);
12304 /* Now try cases based on the opcode of OP0. If none of the cases
12305 does a "continue", we exit this loop immediately after the
12308 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
12309 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
12310 switch (GET_CODE (op0
))
12313 /* If we are extracting a single bit from a variable position in
12314 a constant that has only a single bit set and are comparing it
12315 with zero, we can convert this into an equality comparison
12316 between the position and the location of the single bit. */
12317 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12318 have already reduced the shift count modulo the word size. */
12319 if (!SHIFT_COUNT_TRUNCATED
12320 && CONST_INT_P (XEXP (op0
, 0))
12321 && XEXP (op0
, 1) == const1_rtx
12322 && equality_comparison_p
&& const_op
== 0
12323 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
12325 if (BITS_BIG_ENDIAN
)
12326 i
= BITS_PER_WORD
- 1 - i
;
12328 op0
= XEXP (op0
, 2);
12332 /* Result is nonzero iff shift count is equal to I. */
12333 code
= reverse_condition (code
);
12340 tem
= expand_compound_operation (op0
);
12349 /* If testing for equality, we can take the NOT of the constant. */
12350 if (equality_comparison_p
12351 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
12353 op0
= XEXP (op0
, 0);
12358 /* If just looking at the sign bit, reverse the sense of the
12360 if (sign_bit_comparison_p
)
12362 op0
= XEXP (op0
, 0);
12363 code
= (code
== GE
? LT
: GE
);
12369 /* If testing for equality, we can take the NEG of the constant. */
12370 if (equality_comparison_p
12371 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
12373 op0
= XEXP (op0
, 0);
12378 /* The remaining cases only apply to comparisons with zero. */
12382 /* When X is ABS or is known positive,
12383 (neg X) is < 0 if and only if X != 0. */
12385 if (sign_bit_comparison_p
12386 && (GET_CODE (XEXP (op0
, 0)) == ABS
12387 || (mode_width
<= HOST_BITS_PER_WIDE_INT
12388 && (nonzero_bits (XEXP (op0
, 0), mode
)
12389 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12392 op0
= XEXP (op0
, 0);
12393 code
= (code
== LT
? NE
: EQ
);
12397 /* If we have NEG of something whose two high-order bits are the
12398 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12399 if (num_sign_bit_copies (op0
, mode
) >= 2)
12401 op0
= XEXP (op0
, 0);
12402 code
= swap_condition (code
);
12408 /* If we are testing equality and our count is a constant, we
12409 can perform the inverse operation on our RHS. */
12410 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12411 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
12412 op1
, XEXP (op0
, 1))) != 0)
12414 op0
= XEXP (op0
, 0);
12419 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12420 a particular bit. Convert it to an AND of a constant of that
12421 bit. This will be converted into a ZERO_EXTRACT. */
12422 if (const_op
== 0 && sign_bit_comparison_p
12423 && CONST_INT_P (XEXP (op0
, 1))
12424 && mode_width
<= HOST_BITS_PER_WIDE_INT
12425 && UINTVAL (XEXP (op0
, 1)) < mode_width
)
12427 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12430 - INTVAL (XEXP (op0
, 1)))));
12431 code
= (code
== LT
? NE
: EQ
);
12435 /* Fall through. */
12438 /* ABS is ignorable inside an equality comparison with zero. */
12439 if (const_op
== 0 && equality_comparison_p
)
12441 op0
= XEXP (op0
, 0);
12447 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12448 (compare FOO CONST) if CONST fits in FOO's mode and we
12449 are either testing inequality or have an unsigned
12450 comparison with ZERO_EXTEND or a signed comparison with
12451 SIGN_EXTEND. But don't do it if we don't have a compare
12452 insn of the given mode, since we'd have to revert it
12453 later on, and then we wouldn't know whether to sign- or
12455 if (is_int_mode (GET_MODE (XEXP (op0
, 0)), &mode
)
12456 && ! unsigned_comparison_p
12457 && HWI_COMPUTABLE_MODE_P (mode
)
12458 && trunc_int_for_mode (const_op
, mode
) == const_op
12459 && have_insn_for (COMPARE
, mode
))
12461 op0
= XEXP (op0
, 0);
12467 /* Check for the case where we are comparing A - C1 with C2, that is
12469 (subreg:MODE (plus (A) (-C1))) op (C2)
12471 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12472 comparison in the wider mode. One of the following two conditions
12473 must be true in order for this to be valid:
12475 1. The mode extension results in the same bit pattern being added
12476 on both sides and the comparison is equality or unsigned. As
12477 C2 has been truncated to fit in MODE, the pattern can only be
12480 2. The mode extension results in the sign bit being copied on
12483 The difficulty here is that we have predicates for A but not for
12484 (A - C1) so we need to check that C1 is within proper bounds so
12485 as to perturbate A as little as possible. */
12487 if (mode_width
<= HOST_BITS_PER_WIDE_INT
12488 && subreg_lowpart_p (op0
)
12489 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op0
)),
12491 && GET_MODE_PRECISION (inner_mode
) > mode_width
12492 && GET_CODE (SUBREG_REG (op0
)) == PLUS
12493 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
12495 rtx a
= XEXP (SUBREG_REG (op0
), 0);
12496 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
12499 && (unsigned HOST_WIDE_INT
) c1
12500 < HOST_WIDE_INT_1U
<< (mode_width
- 1)
12501 && (equality_comparison_p
|| unsigned_comparison_p
)
12502 /* (A - C1) zero-extends if it is positive and sign-extends
12503 if it is negative, C2 both zero- and sign-extends. */
12504 && (((nonzero_bits (a
, inner_mode
)
12505 & ~GET_MODE_MASK (mode
)) == 0
12507 /* (A - C1) sign-extends if it is positive and 1-extends
12508 if it is negative, C2 both sign- and 1-extends. */
12509 || (num_sign_bit_copies (a
, inner_mode
)
12510 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12513 || ((unsigned HOST_WIDE_INT
) c1
12514 < HOST_WIDE_INT_1U
<< (mode_width
- 2)
12515 /* (A - C1) always sign-extends, like C2. */
12516 && num_sign_bit_copies (a
, inner_mode
)
12517 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12518 - (mode_width
- 1))))
12520 op0
= SUBREG_REG (op0
);
12525 /* If the inner mode is narrower and we are extracting the low part,
12526 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12527 if (paradoxical_subreg_p (op0
))
12529 else if (subreg_lowpart_p (op0
)
12530 && GET_MODE_CLASS (mode
) == MODE_INT
12531 && is_int_mode (GET_MODE (SUBREG_REG (op0
)), &inner_mode
)
12532 && (code
== NE
|| code
== EQ
)
12533 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
12534 && !paradoxical_subreg_p (op0
)
12535 && (nonzero_bits (SUBREG_REG (op0
), inner_mode
)
12536 & ~GET_MODE_MASK (mode
)) == 0)
12538 /* Remove outer subregs that don't do anything. */
12539 tem
= gen_lowpart (inner_mode
, op1
);
12541 if ((nonzero_bits (tem
, inner_mode
)
12542 & ~GET_MODE_MASK (mode
)) == 0)
12544 op0
= SUBREG_REG (op0
);
12556 if (is_int_mode (GET_MODE (XEXP (op0
, 0)), &mode
)
12557 && (unsigned_comparison_p
|| equality_comparison_p
)
12558 && HWI_COMPUTABLE_MODE_P (mode
)
12559 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
12561 && have_insn_for (COMPARE
, mode
))
12563 op0
= XEXP (op0
, 0);
12569 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12570 this for equality comparisons due to pathological cases involving
12572 if (equality_comparison_p
12573 && (tem
= simplify_binary_operation (MINUS
, mode
,
12574 op1
, XEXP (op0
, 1))) != 0)
12576 op0
= XEXP (op0
, 0);
12581 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12582 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
12583 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
12585 op0
= XEXP (XEXP (op0
, 0), 0);
12586 code
= (code
== LT
? EQ
: NE
);
12592 /* We used to optimize signed comparisons against zero, but that
12593 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12594 arrive here as equality comparisons, or (GEU, LTU) are
12595 optimized away. No need to special-case them. */
12597 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12598 (eq B (minus A C)), whichever simplifies. We can only do
12599 this for equality comparisons due to pathological cases involving
12601 if (equality_comparison_p
12602 && (tem
= simplify_binary_operation (PLUS
, mode
,
12603 XEXP (op0
, 1), op1
)) != 0)
12605 op0
= XEXP (op0
, 0);
12610 if (equality_comparison_p
12611 && (tem
= simplify_binary_operation (MINUS
, mode
,
12612 XEXP (op0
, 0), op1
)) != 0)
12614 op0
= XEXP (op0
, 1);
12619 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12620 of bits in X minus 1, is one iff X > 0. */
12621 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
12622 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12623 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
12624 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12626 op0
= XEXP (op0
, 1);
12627 code
= (code
== GE
? LE
: GT
);
12633 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12634 if C is zero or B is a constant. */
12635 if (equality_comparison_p
12636 && (tem
= simplify_binary_operation (XOR
, mode
,
12637 XEXP (op0
, 1), op1
)) != 0)
12639 op0
= XEXP (op0
, 0);
12647 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12649 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12650 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12651 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12653 op0
= XEXP (op0
, 1);
12654 code
= (code
== GE
? GT
: LE
);
12660 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12661 will be converted to a ZERO_EXTRACT later. */
12662 if (const_op
== 0 && equality_comparison_p
12663 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12664 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12666 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12667 XEXP (XEXP (op0
, 0), 1));
12668 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12672 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12673 zero and X is a comparison and C1 and C2 describe only bits set
12674 in STORE_FLAG_VALUE, we can compare with X. */
12675 if (const_op
== 0 && equality_comparison_p
12676 && mode_width
<= HOST_BITS_PER_WIDE_INT
12677 && CONST_INT_P (XEXP (op0
, 1))
12678 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12679 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12680 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12681 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12683 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12684 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12685 if ((~STORE_FLAG_VALUE
& mask
) == 0
12686 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12687 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12688 && COMPARISON_P (tem
))))
12690 op0
= XEXP (XEXP (op0
, 0), 0);
12695 /* If we are doing an equality comparison of an AND of a bit equal
12696 to the sign bit, replace this with a LT or GE comparison of
12697 the underlying value. */
12698 if (equality_comparison_p
12700 && CONST_INT_P (XEXP (op0
, 1))
12701 && mode_width
<= HOST_BITS_PER_WIDE_INT
12702 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12703 == HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12705 op0
= XEXP (op0
, 0);
12706 code
= (code
== EQ
? GE
: LT
);
12710 /* If this AND operation is really a ZERO_EXTEND from a narrower
12711 mode, the constant fits within that mode, and this is either an
12712 equality or unsigned comparison, try to do this comparison in
12717 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12718 -> (ne:DI (reg:SI 4) (const_int 0))
12720 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12721 known to hold a value of the required mode the
12722 transformation is invalid. */
12723 if ((equality_comparison_p
|| unsigned_comparison_p
)
12724 && CONST_INT_P (XEXP (op0
, 1))
12725 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12726 & GET_MODE_MASK (mode
))
12728 && const_op
>> i
== 0
12729 && int_mode_for_size (i
, 1).exists (&tmode
))
12731 op0
= gen_lowpart_or_truncate (tmode
, XEXP (op0
, 0));
12735 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12736 fits in both M1 and M2 and the SUBREG is either paradoxical
12737 or represents the low part, permute the SUBREG and the AND
12739 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
12740 && CONST_INT_P (XEXP (op0
, 1)))
12742 unsigned HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
12743 /* Require an integral mode, to avoid creating something like
12745 if ((is_a
<scalar_int_mode
>
12746 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))), &tmode
))
12747 /* It is unsafe to commute the AND into the SUBREG if the
12748 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12749 not defined. As originally written the upper bits
12750 have a defined value due to the AND operation.
12751 However, if we commute the AND inside the SUBREG then
12752 they no longer have defined values and the meaning of
12753 the code has been changed.
12754 Also C1 should not change value in the smaller mode,
12755 see PR67028 (a positive C1 can become negative in the
12756 smaller mode, so that the AND does no longer mask the
12758 && ((WORD_REGISTER_OPERATIONS
12759 && mode_width
> GET_MODE_PRECISION (tmode
)
12760 && mode_width
<= BITS_PER_WORD
12761 && trunc_int_for_mode (c1
, tmode
) == (HOST_WIDE_INT
) c1
)
12762 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12763 && subreg_lowpart_p (XEXP (op0
, 0))))
12764 && mode_width
<= HOST_BITS_PER_WIDE_INT
12765 && HWI_COMPUTABLE_MODE_P (tmode
)
12766 && (c1
& ~mask
) == 0
12767 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12769 && c1
!= GET_MODE_MASK (tmode
))
12771 op0
= simplify_gen_binary (AND
, tmode
,
12772 SUBREG_REG (XEXP (op0
, 0)),
12773 gen_int_mode (c1
, tmode
));
12774 op0
= gen_lowpart (mode
, op0
);
12779 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12780 if (const_op
== 0 && equality_comparison_p
12781 && XEXP (op0
, 1) == const1_rtx
12782 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12784 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12785 XEXP (XEXP (op0
, 0), 0), 1);
12786 code
= (code
== NE
? EQ
: NE
);
12790 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12791 (eq (and (lshiftrt X) 1) 0).
12792 Also handle the case where (not X) is expressed using xor. */
12793 if (const_op
== 0 && equality_comparison_p
12794 && XEXP (op0
, 1) == const1_rtx
12795 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12797 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12798 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12800 if (GET_CODE (shift_op
) == NOT
12801 || (GET_CODE (shift_op
) == XOR
12802 && CONST_INT_P (XEXP (shift_op
, 1))
12803 && CONST_INT_P (shift_count
)
12804 && HWI_COMPUTABLE_MODE_P (mode
)
12805 && (UINTVAL (XEXP (shift_op
, 1))
12806 == HOST_WIDE_INT_1U
12807 << INTVAL (shift_count
))))
12810 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12811 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12812 code
= (code
== NE
? EQ
: NE
);
12819 /* If we have (compare (ashift FOO N) (const_int C)) and
12820 the high order N bits of FOO (N+1 if an inequality comparison)
12821 are known to be zero, we can do this by comparing FOO with C
12822 shifted right N bits so long as the low-order N bits of C are
12824 if (CONST_INT_P (XEXP (op0
, 1))
12825 && INTVAL (XEXP (op0
, 1)) >= 0
12826 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12827 < HOST_BITS_PER_WIDE_INT
)
12828 && (((unsigned HOST_WIDE_INT
) const_op
12829 & ((HOST_WIDE_INT_1U
<< INTVAL (XEXP (op0
, 1)))
12831 && mode_width
<= HOST_BITS_PER_WIDE_INT
12832 && (nonzero_bits (XEXP (op0
, 0), mode
)
12833 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12834 + ! equality_comparison_p
))) == 0)
12836 /* We must perform a logical shift, not an arithmetic one,
12837 as we want the top N bits of C to be zero. */
12838 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12840 temp
>>= INTVAL (XEXP (op0
, 1));
12841 op1
= gen_int_mode (temp
, mode
);
12842 op0
= XEXP (op0
, 0);
12846 /* If we are doing a sign bit comparison, it means we are testing
12847 a particular bit. Convert it to the appropriate AND. */
12848 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12849 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12851 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12854 - INTVAL (XEXP (op0
, 1)))));
12855 code
= (code
== LT
? NE
: EQ
);
12859 /* If this an equality comparison with zero and we are shifting
12860 the low bit to the sign bit, we can convert this to an AND of the
12862 if (const_op
== 0 && equality_comparison_p
12863 && CONST_INT_P (XEXP (op0
, 1))
12864 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12866 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12872 /* If this is an equality comparison with zero, we can do this
12873 as a logical shift, which might be much simpler. */
12874 if (equality_comparison_p
&& const_op
== 0
12875 && CONST_INT_P (XEXP (op0
, 1)))
12877 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12879 INTVAL (XEXP (op0
, 1)));
12883 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12884 do the comparison in a narrower mode. */
12885 if (! unsigned_comparison_p
12886 && CONST_INT_P (XEXP (op0
, 1))
12887 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12888 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12889 && (int_mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)), 1)
12891 && (((unsigned HOST_WIDE_INT
) const_op
12892 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12893 <= GET_MODE_MASK (tmode
)))
12895 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12899 /* Likewise if OP0 is a PLUS of a sign extension with a
12900 constant, which is usually represented with the PLUS
12901 between the shifts. */
12902 if (! unsigned_comparison_p
12903 && CONST_INT_P (XEXP (op0
, 1))
12904 && GET_CODE (XEXP (op0
, 0)) == PLUS
12905 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12906 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12907 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12908 && (int_mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)), 1)
12910 && (((unsigned HOST_WIDE_INT
) const_op
12911 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12912 <= GET_MODE_MASK (tmode
)))
12914 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12915 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12916 rtx new_const
= simplify_gen_binary (ASHIFTRT
, mode
,
12917 add_const
, XEXP (op0
, 1));
12919 op0
= simplify_gen_binary (PLUS
, tmode
,
12920 gen_lowpart (tmode
, inner
),
12927 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12928 the low order N bits of FOO are known to be zero, we can do this
12929 by comparing FOO with C shifted left N bits so long as no
12930 overflow occurs. Even if the low order N bits of FOO aren't known
12931 to be zero, if the comparison is >= or < we can use the same
12932 optimization and for > or <= by setting all the low
12933 order N bits in the comparison constant. */
12934 if (CONST_INT_P (XEXP (op0
, 1))
12935 && INTVAL (XEXP (op0
, 1)) > 0
12936 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12937 && mode_width
<= HOST_BITS_PER_WIDE_INT
12938 && (((unsigned HOST_WIDE_INT
) const_op
12939 + (GET_CODE (op0
) != LSHIFTRT
12940 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12943 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12945 unsigned HOST_WIDE_INT low_bits
12946 = (nonzero_bits (XEXP (op0
, 0), mode
)
12947 & ((HOST_WIDE_INT_1U
12948 << INTVAL (XEXP (op0
, 1))) - 1));
12949 if (low_bits
== 0 || !equality_comparison_p
)
12951 /* If the shift was logical, then we must make the condition
12953 if (GET_CODE (op0
) == LSHIFTRT
)
12954 code
= unsigned_condition (code
);
12956 const_op
= (unsigned HOST_WIDE_INT
) const_op
12957 << INTVAL (XEXP (op0
, 1));
12959 && (code
== GT
|| code
== GTU
12960 || code
== LE
|| code
== LEU
))
12962 |= ((HOST_WIDE_INT_1
<< INTVAL (XEXP (op0
, 1))) - 1);
12963 op1
= GEN_INT (const_op
);
12964 op0
= XEXP (op0
, 0);
12969 /* If we are using this shift to extract just the sign bit, we
12970 can replace this with an LT or GE comparison. */
12972 && (equality_comparison_p
|| sign_bit_comparison_p
)
12973 && CONST_INT_P (XEXP (op0
, 1))
12974 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12976 op0
= XEXP (op0
, 0);
12977 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12989 /* Now make any compound operations involved in this comparison. Then,
12990 check for an outmost SUBREG on OP0 that is not doing anything or is
12991 paradoxical. The latter transformation must only be performed when
12992 it is known that the "extra" bits will be the same in op0 and op1 or
12993 that they don't matter. There are three cases to consider:
12995 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12996 care bits and we can assume they have any convenient value. So
12997 making the transformation is safe.
12999 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
13000 In this case the upper bits of op0 are undefined. We should not make
13001 the simplification in that case as we do not know the contents of
13004 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
13005 In that case we know those bits are zeros or ones. We must also be
13006 sure that they are the same as the upper bits of op1.
13008 We can never remove a SUBREG for a non-equality comparison because
13009 the sign bit is in a different place in the underlying object. */
13011 rtx_code op0_mco_code
= SET
;
13012 if (op1
== const0_rtx
)
13013 op0_mco_code
= code
== NE
|| code
== EQ
? EQ
: COMPARE
;
13015 op0
= make_compound_operation (op0
, op0_mco_code
);
13016 op1
= make_compound_operation (op1
, SET
);
13018 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
13019 && is_int_mode (GET_MODE (op0
), &mode
)
13020 && is_int_mode (GET_MODE (SUBREG_REG (op0
)), &inner_mode
)
13021 && (code
== NE
|| code
== EQ
))
13023 if (paradoxical_subreg_p (op0
))
13025 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
13027 if (REG_P (SUBREG_REG (op0
)))
13029 op0
= SUBREG_REG (op0
);
13030 op1
= gen_lowpart (inner_mode
, op1
);
13033 else if (GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
13034 && (nonzero_bits (SUBREG_REG (op0
), inner_mode
)
13035 & ~GET_MODE_MASK (mode
)) == 0)
13037 tem
= gen_lowpart (inner_mode
, op1
);
13039 if ((nonzero_bits (tem
, inner_mode
) & ~GET_MODE_MASK (mode
)) == 0)
13040 op0
= SUBREG_REG (op0
), op1
= tem
;
13044 /* We now do the opposite procedure: Some machines don't have compare
13045 insns in all modes. If OP0's mode is an integer mode smaller than a
13046 word and we can't do a compare in that mode, see if there is a larger
13047 mode for which we can do the compare. There are a number of cases in
13048 which we can use the wider mode. */
13050 if (is_int_mode (GET_MODE (op0
), &mode
)
13051 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
13052 && ! have_insn_for (COMPARE
, mode
))
13053 FOR_EACH_WIDER_MODE (tmode_iter
, mode
)
13055 tmode
= tmode_iter
.require ();
13056 if (!HWI_COMPUTABLE_MODE_P (tmode
))
13058 if (have_insn_for (COMPARE
, tmode
))
13062 /* If this is a test for negative, we can make an explicit
13063 test of the sign bit. Test this first so we can use
13064 a paradoxical subreg to extend OP0. */
13066 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
13067 && HWI_COMPUTABLE_MODE_P (mode
))
13069 unsigned HOST_WIDE_INT sign
13070 = HOST_WIDE_INT_1U
<< (GET_MODE_BITSIZE (mode
) - 1);
13071 op0
= simplify_gen_binary (AND
, tmode
,
13072 gen_lowpart (tmode
, op0
),
13073 gen_int_mode (sign
, tmode
));
13074 code
= (code
== LT
) ? NE
: EQ
;
13078 /* If the only nonzero bits in OP0 and OP1 are those in the
13079 narrower mode and this is an equality or unsigned comparison,
13080 we can use the wider mode. Similarly for sign-extended
13081 values, in which case it is true for all comparisons. */
13082 zero_extended
= ((code
== EQ
|| code
== NE
13083 || code
== GEU
|| code
== GTU
13084 || code
== LEU
|| code
== LTU
)
13085 && (nonzero_bits (op0
, tmode
)
13086 & ~GET_MODE_MASK (mode
)) == 0
13087 && ((CONST_INT_P (op1
)
13088 || (nonzero_bits (op1
, tmode
)
13089 & ~GET_MODE_MASK (mode
)) == 0)));
13092 || ((num_sign_bit_copies (op0
, tmode
)
13093 > (unsigned int) (GET_MODE_PRECISION (tmode
)
13094 - GET_MODE_PRECISION (mode
)))
13095 && (num_sign_bit_copies (op1
, tmode
)
13096 > (unsigned int) (GET_MODE_PRECISION (tmode
)
13097 - GET_MODE_PRECISION (mode
)))))
13099 /* If OP0 is an AND and we don't have an AND in MODE either,
13100 make a new AND in the proper mode. */
13101 if (GET_CODE (op0
) == AND
13102 && !have_insn_for (AND
, mode
))
13103 op0
= simplify_gen_binary (AND
, tmode
,
13104 gen_lowpart (tmode
,
13106 gen_lowpart (tmode
,
13112 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
,
13114 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
,
13119 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
,
13121 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
,
13130 /* We may have changed the comparison operands. Re-canonicalize. */
13131 if (swap_commutative_operands_p (op0
, op1
))
13133 std::swap (op0
, op1
);
13134 code
= swap_condition (code
);
13137 /* If this machine only supports a subset of valid comparisons, see if we
13138 can convert an unsupported one into a supported one. */
13139 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
13147 /* Utility function for record_value_for_reg. Count number of
13152 enum rtx_code code
= GET_CODE (x
);
13156 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
13157 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
13159 rtx x0
= XEXP (x
, 0);
13160 rtx x1
= XEXP (x
, 1);
13163 return 1 + 2 * count_rtxs (x0
);
13165 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
13166 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
13167 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13168 return 2 + 2 * count_rtxs (x0
)
13169 + count_rtxs (x
== XEXP (x1
, 0)
13170 ? XEXP (x1
, 1) : XEXP (x1
, 0));
13172 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
13173 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
13174 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13175 return 2 + 2 * count_rtxs (x1
)
13176 + count_rtxs (x
== XEXP (x0
, 0)
13177 ? XEXP (x0
, 1) : XEXP (x0
, 0));
13180 fmt
= GET_RTX_FORMAT (code
);
13181 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13183 ret
+= count_rtxs (XEXP (x
, i
));
13184 else if (fmt
[i
] == 'E')
13185 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13186 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
13191 /* Utility function for following routine. Called when X is part of a value
13192 being stored into last_set_value. Sets last_set_table_tick
13193 for each register mentioned. Similar to mention_regs in cse.c */
13196 update_table_tick (rtx x
)
13198 enum rtx_code code
= GET_CODE (x
);
13199 const char *fmt
= GET_RTX_FORMAT (code
);
13204 unsigned int regno
= REGNO (x
);
13205 unsigned int endregno
= END_REGNO (x
);
13208 for (r
= regno
; r
< endregno
; r
++)
13210 reg_stat_type
*rsp
= ®_stat
[r
];
13211 rsp
->last_set_table_tick
= label_tick
;
13217 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13220 /* Check for identical subexpressions. If x contains
13221 identical subexpression we only have to traverse one of
13223 if (i
== 0 && ARITHMETIC_P (x
))
13225 /* Note that at this point x1 has already been
13227 rtx x0
= XEXP (x
, 0);
13228 rtx x1
= XEXP (x
, 1);
13230 /* If x0 and x1 are identical then there is no need to
13235 /* If x0 is identical to a subexpression of x1 then while
13236 processing x1, x0 has already been processed. Thus we
13237 are done with x. */
13238 if (ARITHMETIC_P (x1
)
13239 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13242 /* If x1 is identical to a subexpression of x0 then we
13243 still have to process the rest of x0. */
13244 if (ARITHMETIC_P (x0
)
13245 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13247 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
13252 update_table_tick (XEXP (x
, i
));
13254 else if (fmt
[i
] == 'E')
13255 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13256 update_table_tick (XVECEXP (x
, i
, j
));
13259 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13260 are saying that the register is clobbered and we no longer know its
13261 value. If INSN is zero, don't update reg_stat[].last_set; this is
13262 only permitted with VALUE also zero and is used to invalidate the
13266 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
13268 unsigned int regno
= REGNO (reg
);
13269 unsigned int endregno
= END_REGNO (reg
);
13271 reg_stat_type
*rsp
;
13273 /* If VALUE contains REG and we have a previous value for REG, substitute
13274 the previous value. */
13275 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
13279 /* Set things up so get_last_value is allowed to see anything set up to
13281 subst_low_luid
= DF_INSN_LUID (insn
);
13282 tem
= get_last_value (reg
);
13284 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13285 it isn't going to be useful and will take a lot of time to process,
13286 so just use the CLOBBER. */
13290 if (ARITHMETIC_P (tem
)
13291 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
13292 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
13293 tem
= XEXP (tem
, 0);
13294 else if (count_occurrences (value
, reg
, 1) >= 2)
13296 /* If there are two or more occurrences of REG in VALUE,
13297 prevent the value from growing too much. */
13298 if (count_rtxs (tem
) > param_max_last_value_rtl
)
13299 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
13302 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
13306 /* For each register modified, show we don't know its value, that
13307 we don't know about its bitwise content, that its value has been
13308 updated, and that we don't know the location of the death of the
13310 for (i
= regno
; i
< endregno
; i
++)
13312 rsp
= ®_stat
[i
];
13315 rsp
->last_set
= insn
;
13317 rsp
->last_set_value
= 0;
13318 rsp
->last_set_mode
= VOIDmode
;
13319 rsp
->last_set_nonzero_bits
= 0;
13320 rsp
->last_set_sign_bit_copies
= 0;
13321 rsp
->last_death
= 0;
13322 rsp
->truncated_to_mode
= VOIDmode
;
13325 /* Mark registers that are being referenced in this value. */
13327 update_table_tick (value
);
13329 /* Now update the status of each register being set.
13330 If someone is using this register in this block, set this register
13331 to invalid since we will get confused between the two lives in this
13332 basic block. This makes using this register always invalid. In cse, we
13333 scan the table to invalidate all entries using this register, but this
13334 is too much work for us. */
13336 for (i
= regno
; i
< endregno
; i
++)
13338 rsp
= ®_stat
[i
];
13339 rsp
->last_set_label
= label_tick
;
13341 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
13342 rsp
->last_set_invalid
= 1;
13344 rsp
->last_set_invalid
= 0;
13347 /* The value being assigned might refer to X (like in "x++;"). In that
13348 case, we must replace it with (clobber (const_int 0)) to prevent
13350 rsp
= ®_stat
[regno
];
13351 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
13353 value
= copy_rtx (value
);
13354 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
13358 /* For the main register being modified, update the value, the mode, the
13359 nonzero bits, and the number of sign bit copies. */
13361 rsp
->last_set_value
= value
;
13365 machine_mode mode
= GET_MODE (reg
);
13366 subst_low_luid
= DF_INSN_LUID (insn
);
13367 rsp
->last_set_mode
= mode
;
13368 if (GET_MODE_CLASS (mode
) == MODE_INT
13369 && HWI_COMPUTABLE_MODE_P (mode
))
13370 mode
= nonzero_bits_mode
;
13371 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
13372 rsp
->last_set_sign_bit_copies
13373 = num_sign_bit_copies (value
, GET_MODE (reg
));
13377 /* Called via note_stores from record_dead_and_set_regs to handle one
13378 SET or CLOBBER in an insn. DATA is the instruction in which the
13379 set is occurring. */
13382 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
13384 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
13386 if (GET_CODE (dest
) == SUBREG
)
13387 dest
= SUBREG_REG (dest
);
13389 if (!record_dead_insn
)
13392 record_value_for_reg (dest
, NULL
, NULL_RTX
);
13398 /* If we are setting the whole register, we know its value. Otherwise
13399 show that we don't know the value. We can handle a SUBREG if it's
13400 the low part, but we must be careful with paradoxical SUBREGs on
13401 RISC architectures because we cannot strip e.g. an extension around
13402 a load and record the naked load since the RTL middle-end considers
13403 that the upper bits are defined according to LOAD_EXTEND_OP. */
13404 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
13405 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
13406 else if (GET_CODE (setter
) == SET
13407 && GET_CODE (SET_DEST (setter
)) == SUBREG
13408 && SUBREG_REG (SET_DEST (setter
)) == dest
13409 && known_le (GET_MODE_PRECISION (GET_MODE (dest
)),
13411 && subreg_lowpart_p (SET_DEST (setter
)))
13412 record_value_for_reg (dest
, record_dead_insn
,
13413 WORD_REGISTER_OPERATIONS
13414 && word_register_operation_p (SET_SRC (setter
))
13415 && paradoxical_subreg_p (SET_DEST (setter
))
13417 : gen_lowpart (GET_MODE (dest
),
13418 SET_SRC (setter
)));
13420 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
13422 else if (MEM_P (dest
)
13423 /* Ignore pushes, they clobber nothing. */
13424 && ! push_operand (dest
, GET_MODE (dest
)))
13425 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
13428 /* Update the records of when each REG was most recently set or killed
13429 for the things done by INSN. This is the last thing done in processing
13430 INSN in the combiner loop.
13432 We update reg_stat[], in particular fields last_set, last_set_value,
13433 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13434 last_death, and also the similar information mem_last_set (which insn
13435 most recently modified memory) and last_call_luid (which insn was the
13436 most recent subroutine call). */
13439 record_dead_and_set_regs (rtx_insn
*insn
)
13444 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
13446 if (REG_NOTE_KIND (link
) == REG_DEAD
13447 && REG_P (XEXP (link
, 0)))
13449 unsigned int regno
= REGNO (XEXP (link
, 0));
13450 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
13452 for (i
= regno
; i
< endregno
; i
++)
13454 reg_stat_type
*rsp
;
13456 rsp
= ®_stat
[i
];
13457 rsp
->last_death
= insn
;
13460 else if (REG_NOTE_KIND (link
) == REG_INC
)
13461 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
13466 HARD_REG_SET callee_clobbers
13467 = insn_callee_abi (insn
).full_and_partial_reg_clobbers ();
13468 hard_reg_set_iterator hrsi
;
13469 EXECUTE_IF_SET_IN_HARD_REG_SET (callee_clobbers
, 0, i
, hrsi
)
13471 reg_stat_type
*rsp
;
13473 /* ??? We could try to preserve some information from the last
13474 set of register I if the call doesn't actually clobber
13475 (reg:last_set_mode I), which might be true for ABIs with
13476 partial clobbers. However, it would be difficult to
13477 update last_set_nonzero_bits and last_sign_bit_copies
13478 to account for the part of I that actually was clobbered.
13479 It wouldn't help much anyway, since we rarely see this
13480 situation before RA. */
13481 rsp
= ®_stat
[i
];
13482 rsp
->last_set_invalid
= 1;
13483 rsp
->last_set
= insn
;
13484 rsp
->last_set_value
= 0;
13485 rsp
->last_set_mode
= VOIDmode
;
13486 rsp
->last_set_nonzero_bits
= 0;
13487 rsp
->last_set_sign_bit_copies
= 0;
13488 rsp
->last_death
= 0;
13489 rsp
->truncated_to_mode
= VOIDmode
;
13492 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
13494 /* We can't combine into a call pattern. Remember, though, that
13495 the return value register is set at this LUID. We could
13496 still replace a register with the return value from the
13497 wrong subroutine call! */
13498 note_stores (insn
, record_dead_and_set_regs_1
, NULL_RTX
);
13501 note_stores (insn
, record_dead_and_set_regs_1
, insn
);
13504 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13505 register present in the SUBREG, so for each such SUBREG go back and
13506 adjust nonzero and sign bit information of the registers that are
13507 known to have some zero/sign bits set.
13509 This is needed because when combine blows the SUBREGs away, the
13510 information on zero/sign bits is lost and further combines can be
13511 missed because of that. */
13514 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
13516 struct insn_link
*links
;
13518 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
13519 machine_mode mode
= GET_MODE (subreg
);
13521 if (!HWI_COMPUTABLE_MODE_P (mode
))
13524 for (links
= LOG_LINKS (insn
); links
;)
13526 reg_stat_type
*rsp
;
13528 insn
= links
->insn
;
13529 set
= single_set (insn
);
13531 if (! set
|| !REG_P (SET_DEST (set
))
13532 || REGNO (SET_DEST (set
)) != regno
13533 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
13535 links
= links
->next
;
13539 rsp
= ®_stat
[regno
];
13540 if (rsp
->last_set
== insn
)
13542 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
13543 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
13546 if (REG_P (SET_SRC (set
)))
13548 regno
= REGNO (SET_SRC (set
));
13549 links
= LOG_LINKS (insn
);
13556 /* Check if X, a register, is known to contain a value already
13557 truncated to MODE. In this case we can use a subreg to refer to
13558 the truncated value even though in the generic case we would need
13559 an explicit truncation. */
13562 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
13564 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
13565 machine_mode truncated
= rsp
->truncated_to_mode
;
13568 || rsp
->truncation_label
< label_tick_ebb_start
)
13570 if (!partial_subreg_p (mode
, truncated
))
13572 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
13577 /* If X is a hard reg or a subreg record the mode that the register is
13578 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13579 able to turn a truncate into a subreg using this information. Return true
13580 if traversing X is complete. */
13583 record_truncated_value (rtx x
)
13585 machine_mode truncated_mode
;
13586 reg_stat_type
*rsp
;
13588 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
13590 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
13591 truncated_mode
= GET_MODE (x
);
13593 if (!partial_subreg_p (truncated_mode
, original_mode
))
13596 truncated_mode
= GET_MODE (x
);
13597 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
13600 x
= SUBREG_REG (x
);
13602 /* ??? For hard-regs we now record everything. We might be able to
13603 optimize this using last_set_mode. */
13604 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
13605 truncated_mode
= GET_MODE (x
);
13609 rsp
= ®_stat
[REGNO (x
)];
13610 if (rsp
->truncated_to_mode
== 0
13611 || rsp
->truncation_label
< label_tick_ebb_start
13612 || partial_subreg_p (truncated_mode
, rsp
->truncated_to_mode
))
13614 rsp
->truncated_to_mode
= truncated_mode
;
13615 rsp
->truncation_label
= label_tick
;
13621 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13622 the modes they are used in. This can help truning TRUNCATEs into
13626 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13628 subrtx_var_iterator::array_type array
;
13629 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
13630 if (record_truncated_value (*iter
))
13631 iter
.skip_subrtxes ();
13634 /* Scan X for promoted SUBREGs. For each one found,
13635 note what it implies to the registers used in it. */
13638 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
13640 if (GET_CODE (x
) == SUBREG
13641 && SUBREG_PROMOTED_VAR_P (x
)
13642 && REG_P (SUBREG_REG (x
)))
13643 record_promoted_value (insn
, x
);
13646 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
13649 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
13653 check_promoted_subreg (insn
, XEXP (x
, i
));
13657 if (XVEC (x
, i
) != 0)
13658 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13659 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
13665 /* Verify that all the registers and memory references mentioned in *LOC are
13666 still valid. *LOC was part of a value set in INSN when label_tick was
13667 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13668 the invalid references with (clobber (const_int 0)) and return 1. This
13669 replacement is useful because we often can get useful information about
13670 the form of a value (e.g., if it was produced by a shift that always
13671 produces -1 or 0) even though we don't know exactly what registers it
13672 was produced from. */
13675 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
13678 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13679 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13684 unsigned int regno
= REGNO (x
);
13685 unsigned int endregno
= END_REGNO (x
);
13688 for (j
= regno
; j
< endregno
; j
++)
13690 reg_stat_type
*rsp
= ®_stat
[j
];
13691 if (rsp
->last_set_invalid
13692 /* If this is a pseudo-register that was only set once and not
13693 live at the beginning of the function, it is always valid. */
13694 || (! (regno
>= FIRST_PSEUDO_REGISTER
13695 && regno
< reg_n_sets_max
13696 && REG_N_SETS (regno
) == 1
13697 && (!REGNO_REG_SET_P
13698 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13700 && rsp
->last_set_label
> tick
))
13703 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13710 /* If this is a memory reference, make sure that there were no stores after
13711 it that might have clobbered the value. We don't have alias info, so we
13712 assume any store invalidates it. Moreover, we only have local UIDs, so
13713 we also assume that there were stores in the intervening basic blocks. */
13714 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13715 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13718 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13722 for (i
= 0; i
< len
; i
++)
13726 /* Check for identical subexpressions. If x contains
13727 identical subexpression we only have to traverse one of
13729 if (i
== 1 && ARITHMETIC_P (x
))
13731 /* Note that at this point x0 has already been checked
13732 and found valid. */
13733 rtx x0
= XEXP (x
, 0);
13734 rtx x1
= XEXP (x
, 1);
13736 /* If x0 and x1 are identical then x is also valid. */
13740 /* If x1 is identical to a subexpression of x0 then
13741 while checking x0, x1 has already been checked. Thus
13742 it is valid and so as x. */
13743 if (ARITHMETIC_P (x0
)
13744 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13747 /* If x0 is identical to a subexpression of x1 then x is
13748 valid iff the rest of x1 is valid. */
13749 if (ARITHMETIC_P (x1
)
13750 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13752 get_last_value_validate (&XEXP (x1
,
13753 x0
== XEXP (x1
, 0) ? 1 : 0),
13754 insn
, tick
, replace
);
13757 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13761 else if (fmt
[i
] == 'E')
13762 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13763 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13764 insn
, tick
, replace
) == 0)
13768 /* If we haven't found a reason for it to be invalid, it is valid. */
13772 /* Get the last value assigned to X, if known. Some registers
13773 in the value may be replaced with (clobber (const_int 0)) if their value
13774 is known longer known reliably. */
13777 get_last_value (const_rtx x
)
13779 unsigned int regno
;
13781 reg_stat_type
*rsp
;
13783 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13784 then convert it to the desired mode. If this is a paradoxical SUBREG,
13785 we cannot predict what values the "extra" bits might have. */
13786 if (GET_CODE (x
) == SUBREG
13787 && subreg_lowpart_p (x
)
13788 && !paradoxical_subreg_p (x
)
13789 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13790 return gen_lowpart (GET_MODE (x
), value
);
13796 rsp
= ®_stat
[regno
];
13797 value
= rsp
->last_set_value
;
13799 /* If we don't have a value, or if it isn't for this basic block and
13800 it's either a hard register, set more than once, or it's a live
13801 at the beginning of the function, return 0.
13803 Because if it's not live at the beginning of the function then the reg
13804 is always set before being used (is never used without being set).
13805 And, if it's set only once, and it's always set before use, then all
13806 uses must have the same last value, even if it's not from this basic
13810 || (rsp
->last_set_label
< label_tick_ebb_start
13811 && (regno
< FIRST_PSEUDO_REGISTER
13812 || regno
>= reg_n_sets_max
13813 || REG_N_SETS (regno
) != 1
13815 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13818 /* If the value was set in a later insn than the ones we are processing,
13819 we can't use it even if the register was only set once. */
13820 if (rsp
->last_set_label
== label_tick
13821 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13824 /* If fewer bits were set than what we are asked for now, we cannot use
13826 if (maybe_lt (GET_MODE_PRECISION (rsp
->last_set_mode
),
13827 GET_MODE_PRECISION (GET_MODE (x
))))
13830 /* If the value has all its registers valid, return it. */
13831 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13834 /* Otherwise, make a copy and replace any invalid register with
13835 (clobber (const_int 0)). If that fails for some reason, return 0. */
13837 value
= copy_rtx (value
);
13838 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13844 /* Define three variables used for communication between the following
13847 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13848 static int reg_dead_flag
;
13851 /* Function called via note_stores from reg_dead_at_p.
13853 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13854 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13857 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13859 unsigned int regno
, endregno
;
13864 regno
= REGNO (dest
);
13865 endregno
= END_REGNO (dest
);
13866 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13867 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13870 /* Return nonzero if REG is known to be dead at INSN.
13872 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13873 referencing REG, it is dead. If we hit a SET referencing REG, it is
13874 live. Otherwise, see if it is live or dead at the start of the basic
13875 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13876 must be assumed to be always live. */
13879 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13884 /* Set variables for reg_dead_at_p_1. */
13885 reg_dead_regno
= REGNO (reg
);
13886 reg_dead_endregno
= END_REGNO (reg
);
13887 reg_dead_reg
= reg
;
13891 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13892 we allow the machine description to decide whether use-and-clobber
13893 patterns are OK. */
13894 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13896 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13897 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13901 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13902 beginning of basic block. */
13903 block
= BLOCK_FOR_INSN (insn
);
13908 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13911 note_stores (insn
, reg_dead_at_p_1
, NULL
);
13913 return reg_dead_flag
== 1 ? 1 : 0;
13915 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13919 if (insn
== BB_HEAD (block
))
13922 insn
= PREV_INSN (insn
);
13925 /* Look at live-in sets for the basic block that we were in. */
13926 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13927 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13933 /* Note hard registers in X that are used. */
13936 mark_used_regs_combine (rtx x
)
13938 RTX_CODE code
= GET_CODE (x
);
13939 unsigned int regno
;
13950 case ADDR_DIFF_VEC
:
13952 /* CC0 must die in the insn after it is set, so we don't need to take
13953 special note of it here. */
13958 /* If we are clobbering a MEM, mark any hard registers inside the
13959 address as used. */
13960 if (MEM_P (XEXP (x
, 0)))
13961 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13966 /* A hard reg in a wide mode may really be multiple registers.
13967 If so, mark all of them just like the first. */
13968 if (regno
< FIRST_PSEUDO_REGISTER
)
13970 /* None of this applies to the stack, frame or arg pointers. */
13971 if (regno
== STACK_POINTER_REGNUM
13972 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13973 && regno
== HARD_FRAME_POINTER_REGNUM
)
13974 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13975 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13976 || regno
== FRAME_POINTER_REGNUM
)
13979 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13985 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13987 rtx testreg
= SET_DEST (x
);
13989 while (GET_CODE (testreg
) == SUBREG
13990 || GET_CODE (testreg
) == ZERO_EXTRACT
13991 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13992 testreg
= XEXP (testreg
, 0);
13994 if (MEM_P (testreg
))
13995 mark_used_regs_combine (XEXP (testreg
, 0));
13997 mark_used_regs_combine (SET_SRC (x
));
14005 /* Recursively scan the operands of this expression. */
14008 const char *fmt
= GET_RTX_FORMAT (code
);
14010 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
14013 mark_used_regs_combine (XEXP (x
, i
));
14014 else if (fmt
[i
] == 'E')
14018 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
14019 mark_used_regs_combine (XVECEXP (x
, i
, j
));
14025 /* Remove register number REGNO from the dead registers list of INSN.
14027 Return the note used to record the death, if there was one. */
14030 remove_death (unsigned int regno
, rtx_insn
*insn
)
14032 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
14035 remove_note (insn
, note
);
14040 /* For each register (hardware or pseudo) used within expression X, if its
14041 death is in an instruction with luid between FROM_LUID (inclusive) and
14042 TO_INSN (exclusive), put a REG_DEAD note for that register in the
14043 list headed by PNOTES.
14045 That said, don't move registers killed by maybe_kill_insn.
14047 This is done when X is being merged by combination into TO_INSN. These
14048 notes will then be distributed as needed. */
14051 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
14056 enum rtx_code code
= GET_CODE (x
);
14060 unsigned int regno
= REGNO (x
);
14061 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
14063 /* If we do not know where the register died, it may still die between
14064 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
14065 if (!where_dead
|| DF_INSN_LUID (where_dead
) >= DF_INSN_LUID (to_insn
))
14067 rtx_insn
*insn
= prev_real_nondebug_insn (to_insn
);
14069 && BLOCK_FOR_INSN (insn
) == BLOCK_FOR_INSN (to_insn
)
14070 && DF_INSN_LUID (insn
) >= from_luid
)
14072 if (dead_or_set_regno_p (insn
, regno
))
14074 if (find_regno_note (insn
, REG_DEAD
, regno
))
14079 insn
= prev_real_nondebug_insn (insn
);
14083 /* Don't move the register if it gets killed in between from and to. */
14084 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
14085 && ! reg_referenced_p (x
, maybe_kill_insn
))
14089 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
14090 && DF_INSN_LUID (where_dead
) >= from_luid
14091 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
14093 rtx note
= remove_death (regno
, where_dead
);
14095 /* It is possible for the call above to return 0. This can occur
14096 when last_death points to I2 or I1 that we combined with.
14097 In that case make a new note.
14099 We must also check for the case where X is a hard register
14100 and NOTE is a death note for a range of hard registers
14101 including X. In that case, we must put REG_DEAD notes for
14102 the remaining registers in place of NOTE. */
14104 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
14105 && partial_subreg_p (GET_MODE (x
), GET_MODE (XEXP (note
, 0))))
14107 unsigned int deadregno
= REGNO (XEXP (note
, 0));
14108 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
14109 unsigned int ourend
= END_REGNO (x
);
14112 for (i
= deadregno
; i
< deadend
; i
++)
14113 if (i
< regno
|| i
>= ourend
)
14114 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
14117 /* If we didn't find any note, or if we found a REG_DEAD note that
14118 covers only part of the given reg, and we have a multi-reg hard
14119 register, then to be safe we must check for REG_DEAD notes
14120 for each register other than the first. They could have
14121 their own REG_DEAD notes lying around. */
14122 else if ((note
== 0
14124 && partial_subreg_p (GET_MODE (XEXP (note
, 0)),
14126 && regno
< FIRST_PSEUDO_REGISTER
14127 && REG_NREGS (x
) > 1)
14129 unsigned int ourend
= END_REGNO (x
);
14130 unsigned int i
, offset
;
14134 offset
= hard_regno_nregs (regno
, GET_MODE (XEXP (note
, 0)));
14138 for (i
= regno
+ offset
; i
< ourend
; i
++)
14139 move_deaths (regno_reg_rtx
[i
],
14140 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
14143 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
14145 XEXP (note
, 1) = *pnotes
;
14149 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
14155 else if (GET_CODE (x
) == SET
)
14157 rtx dest
= SET_DEST (x
);
14159 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14161 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14162 that accesses one word of a multi-word item, some
14163 piece of everything register in the expression is used by
14164 this insn, so remove any old death. */
14165 /* ??? So why do we test for equality of the sizes? */
14167 if (GET_CODE (dest
) == ZERO_EXTRACT
14168 || GET_CODE (dest
) == STRICT_LOW_PART
14169 || (GET_CODE (dest
) == SUBREG
14170 && !read_modify_subreg_p (dest
)))
14172 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14176 /* If this is some other SUBREG, we know it replaces the entire
14177 value, so use that as the destination. */
14178 if (GET_CODE (dest
) == SUBREG
)
14179 dest
= SUBREG_REG (dest
);
14181 /* If this is a MEM, adjust deaths of anything used in the address.
14182 For a REG (the only other possibility), the entire value is
14183 being replaced so the old value is not used in this insn. */
14186 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
14191 else if (GET_CODE (x
) == CLOBBER
)
14194 len
= GET_RTX_LENGTH (code
);
14195 fmt
= GET_RTX_FORMAT (code
);
14197 for (i
= 0; i
< len
; i
++)
14202 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
14203 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
14206 else if (fmt
[i
] == 'e')
14207 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14211 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14212 pattern of an insn. X must be a REG. */
14215 reg_bitfield_target_p (rtx x
, rtx body
)
14219 if (GET_CODE (body
) == SET
)
14221 rtx dest
= SET_DEST (body
);
14223 unsigned int regno
, tregno
, endregno
, endtregno
;
14225 if (GET_CODE (dest
) == ZERO_EXTRACT
)
14226 target
= XEXP (dest
, 0);
14227 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
14228 target
= SUBREG_REG (XEXP (dest
, 0));
14232 if (GET_CODE (target
) == SUBREG
)
14233 target
= SUBREG_REG (target
);
14235 if (!REG_P (target
))
14238 tregno
= REGNO (target
), regno
= REGNO (x
);
14239 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
14240 return target
== x
;
14242 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
14243 endregno
= end_hard_regno (GET_MODE (x
), regno
);
14245 return endregno
> tregno
&& regno
< endtregno
;
14248 else if (GET_CODE (body
) == PARALLEL
)
14249 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
14250 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
14256 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14257 as appropriate. I3 and I2 are the insns resulting from the combination
14258 insns including FROM (I2 may be zero).
14260 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14261 not need REG_DEAD notes because they are being substituted for. This
14262 saves searching in the most common cases.
14264 Each note in the list is either ignored or placed on some insns, depending
14265 on the type of note. */
14268 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
14269 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
14271 rtx note
, next_note
;
14273 rtx_insn
*tem_insn
;
14275 for (note
= notes
; note
; note
= next_note
)
14277 rtx_insn
*place
= 0, *place2
= 0;
14279 next_note
= XEXP (note
, 1);
14280 switch (REG_NOTE_KIND (note
))
14284 /* Doesn't matter much where we put this, as long as it's somewhere.
14285 It is preferable to keep these notes on branches, which is most
14286 likely to be i3. */
14290 case REG_NON_LOCAL_GOTO
:
14295 gcc_assert (i2
&& JUMP_P (i2
));
14300 case REG_EH_REGION
:
14301 /* These notes must remain with the call or trapping instruction. */
14304 else if (i2
&& CALL_P (i2
))
14308 gcc_assert (cfun
->can_throw_non_call_exceptions
);
14309 if (may_trap_p (i3
))
14311 else if (i2
&& may_trap_p (i2
))
14313 /* ??? Otherwise assume we've combined things such that we
14314 can now prove that the instructions can't trap. Drop the
14315 note in this case. */
14319 case REG_ARGS_SIZE
:
14320 /* ??? How to distribute between i3-i1. Assume i3 contains the
14321 entire adjustment. Assert i3 contains at least some adjust. */
14322 if (!noop_move_p (i3
))
14324 poly_int64 old_size
, args_size
= get_args_size (note
);
14325 /* fixup_args_size_notes looks at REG_NORETURN note,
14326 so ensure the note is placed there first. */
14330 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
14331 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
14335 XEXP (n
, 1) = REG_NOTES (i3
);
14336 REG_NOTES (i3
) = n
;
14340 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
14341 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14342 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14343 gcc_assert (maybe_ne (old_size
, args_size
)
14345 && !ACCUMULATE_OUTGOING_ARGS
14346 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
14353 case REG_CALL_DECL
:
14354 case REG_CALL_NOCF_CHECK
:
14355 /* These notes must remain with the call. It should not be
14356 possible for both I2 and I3 to be a call. */
14361 gcc_assert (i2
&& CALL_P (i2
));
14367 /* Any clobbers for i3 may still exist, and so we must process
14368 REG_UNUSED notes from that insn.
14370 Any clobbers from i2 or i1 can only exist if they were added by
14371 recog_for_combine. In that case, recog_for_combine created the
14372 necessary REG_UNUSED notes. Trying to keep any original
14373 REG_UNUSED notes from these insns can cause incorrect output
14374 if it is for the same register as the original i3 dest.
14375 In that case, we will notice that the register is set in i3,
14376 and then add a REG_UNUSED note for the destination of i3, which
14377 is wrong. However, it is possible to have REG_UNUSED notes from
14378 i2 or i1 for register which were both used and clobbered, so
14379 we keep notes from i2 or i1 if they will turn into REG_DEAD
14382 /* If this register is set or clobbered in I3, put the note there
14383 unless there is one already. */
14384 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
14386 if (from_insn
!= i3
)
14389 if (! (REG_P (XEXP (note
, 0))
14390 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
14391 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
14394 /* Otherwise, if this register is used by I3, then this register
14395 now dies here, so we must put a REG_DEAD note here unless there
14397 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
14398 && ! (REG_P (XEXP (note
, 0))
14399 ? find_regno_note (i3
, REG_DEAD
,
14400 REGNO (XEXP (note
, 0)))
14401 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
14403 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14407 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14408 but we can't tell which at this point. We must reset any
14409 expectations we had about the value that was previously
14410 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14411 and, if appropriate, restore its previous value, but we
14412 don't have enough information for that at this point. */
14415 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14417 /* Otherwise, if this register is now referenced in i2
14418 then the register used to be modified in one of the
14419 original insns. If it was i3 (say, in an unused
14420 parallel), it's now completely gone, so the note can
14421 be discarded. But if it was modified in i2, i1 or i0
14422 and we still reference it in i2, then we're
14423 referencing the previous value, and since the
14424 register was modified and REG_UNUSED, we know that
14425 the previous value is now dead. So, if we only
14426 reference the register in i2, we change the note to
14427 REG_DEAD, to reflect the previous value. However, if
14428 we're also setting or clobbering the register as
14429 scratch, we know (because the register was not
14430 referenced in i3) that it's unused, just as it was
14431 unused before, and we place the note in i2. */
14432 if (from_insn
!= i3
&& i2
&& INSN_P (i2
)
14433 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14435 if (!reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14436 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14437 if (! (REG_P (XEXP (note
, 0))
14438 ? find_regno_note (i2
, REG_NOTE_KIND (note
),
14439 REGNO (XEXP (note
, 0)))
14440 : find_reg_note (i2
, REG_NOTE_KIND (note
),
14451 /* These notes say something about results of an insn. We can
14452 only support them if they used to be on I3 in which case they
14453 remain on I3. Otherwise they are ignored.
14455 If the note refers to an expression that is not a constant, we
14456 must also ignore the note since we cannot tell whether the
14457 equivalence is still true. It might be possible to do
14458 slightly better than this (we only have a problem if I2DEST
14459 or I1DEST is present in the expression), but it doesn't
14460 seem worth the trouble. */
14462 if (from_insn
== i3
14463 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
14468 /* These notes say something about how a register is used. They must
14469 be present on any use of the register in I2 or I3. */
14470 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
14473 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
14482 case REG_LABEL_TARGET
:
14483 case REG_LABEL_OPERAND
:
14484 /* This can show up in several ways -- either directly in the
14485 pattern, or hidden off in the constant pool with (or without?)
14486 a REG_EQUAL note. */
14487 /* ??? Ignore the without-reg_equal-note problem for now. */
14488 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
14489 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
14490 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14491 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
14495 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
14496 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
14497 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14498 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
14506 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14507 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14509 if (place
&& JUMP_P (place
)
14510 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14511 && (JUMP_LABEL (place
) == NULL
14512 || JUMP_LABEL (place
) == XEXP (note
, 0)))
14514 rtx label
= JUMP_LABEL (place
);
14517 JUMP_LABEL (place
) = XEXP (note
, 0);
14518 else if (LABEL_P (label
))
14519 LABEL_NUSES (label
)--;
14522 if (place2
&& JUMP_P (place2
)
14523 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14524 && (JUMP_LABEL (place2
) == NULL
14525 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
14527 rtx label
= JUMP_LABEL (place2
);
14530 JUMP_LABEL (place2
) = XEXP (note
, 0);
14531 else if (LABEL_P (label
))
14532 LABEL_NUSES (label
)--;
14538 /* This note says something about the value of a register prior
14539 to the execution of an insn. It is too much trouble to see
14540 if the note is still correct in all situations. It is better
14541 to simply delete it. */
14545 /* If we replaced the right hand side of FROM_INSN with a
14546 REG_EQUAL note, the original use of the dying register
14547 will not have been combined into I3 and I2. In such cases,
14548 FROM_INSN is guaranteed to be the first of the combined
14549 instructions, so we simply need to search back before
14550 FROM_INSN for the previous use or set of this register,
14551 then alter the notes there appropriately.
14553 If the register is used as an input in I3, it dies there.
14554 Similarly for I2, if it is nonzero and adjacent to I3.
14556 If the register is not used as an input in either I3 or I2
14557 and it is not one of the registers we were supposed to eliminate,
14558 there are two possibilities. We might have a non-adjacent I2
14559 or we might have somehow eliminated an additional register
14560 from a computation. For example, we might have had A & B where
14561 we discover that B will always be zero. In this case we will
14562 eliminate the reference to A.
14564 In both cases, we must search to see if we can find a previous
14565 use of A and put the death note there. */
14568 && from_insn
== i2mod
14569 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
14570 tem_insn
= from_insn
;
14574 && CALL_P (from_insn
)
14575 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
14577 else if (i2
&& reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14579 /* If the new I2 sets the same register that is marked
14580 dead in the note, we do not in general know where to
14581 put the note. One important case we _can_ handle is
14582 when the note comes from I3. */
14583 if (from_insn
== i3
)
14588 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
14590 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
14591 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14593 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
14595 && reg_overlap_mentioned_p (XEXP (note
, 0),
14597 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
14598 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
14605 basic_block bb
= this_basic_block
;
14607 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
14609 if (!NONDEBUG_INSN_P (tem_insn
))
14611 if (tem_insn
== BB_HEAD (bb
))
14616 /* If the register is being set at TEM_INSN, see if that is all
14617 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14618 into a REG_UNUSED note instead. Don't delete sets to
14619 global register vars. */
14620 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
14621 || !global_regs
[REGNO (XEXP (note
, 0))])
14622 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
14624 rtx set
= single_set (tem_insn
);
14625 rtx inner_dest
= 0;
14626 rtx_insn
*cc0_setter
= NULL
;
14629 for (inner_dest
= SET_DEST (set
);
14630 (GET_CODE (inner_dest
) == STRICT_LOW_PART
14631 || GET_CODE (inner_dest
) == SUBREG
14632 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
14633 inner_dest
= XEXP (inner_dest
, 0))
14636 /* Verify that it was the set, and not a clobber that
14637 modified the register.
14639 CC0 targets must be careful to maintain setter/user
14640 pairs. If we cannot delete the setter due to side
14641 effects, mark the user with an UNUSED note instead
14644 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
14645 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
14647 || (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
14648 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
14649 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))))
14651 /* Move the notes and links of TEM_INSN elsewhere.
14652 This might delete other dead insns recursively.
14653 First set the pattern to something that won't use
14655 rtx old_notes
= REG_NOTES (tem_insn
);
14657 PATTERN (tem_insn
) = pc_rtx
;
14658 REG_NOTES (tem_insn
) = NULL
;
14660 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
14661 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14662 distribute_links (LOG_LINKS (tem_insn
));
14664 unsigned int regno
= REGNO (XEXP (note
, 0));
14665 reg_stat_type
*rsp
= ®_stat
[regno
];
14666 if (rsp
->last_set
== tem_insn
)
14667 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14669 SET_INSN_DELETED (tem_insn
);
14670 if (tem_insn
== i2
)
14673 /* Delete the setter too. */
14676 PATTERN (cc0_setter
) = pc_rtx
;
14677 old_notes
= REG_NOTES (cc0_setter
);
14678 REG_NOTES (cc0_setter
) = NULL
;
14680 distribute_notes (old_notes
, cc0_setter
,
14682 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14683 distribute_links (LOG_LINKS (cc0_setter
));
14685 SET_INSN_DELETED (cc0_setter
);
14686 if (cc0_setter
== i2
)
14692 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14694 /* If there isn't already a REG_UNUSED note, put one
14695 here. Do not place a REG_DEAD note, even if
14696 the register is also used here; that would not
14697 match the algorithm used in lifetime analysis
14698 and can cause the consistency check in the
14699 scheduler to fail. */
14700 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14701 REGNO (XEXP (note
, 0))))
14706 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14707 || (CALL_P (tem_insn
)
14708 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14712 /* If we are doing a 3->2 combination, and we have a
14713 register which formerly died in i3 and was not used
14714 by i2, which now no longer dies in i3 and is used in
14715 i2 but does not die in i2, and place is between i2
14716 and i3, then we may need to move a link from place to
14718 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14720 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14721 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14723 struct insn_link
*links
= LOG_LINKS (place
);
14724 LOG_LINKS (place
) = NULL
;
14725 distribute_links (links
);
14730 if (tem_insn
== BB_HEAD (bb
))
14736 /* If the register is set or already dead at PLACE, we needn't do
14737 anything with this note if it is still a REG_DEAD note.
14738 We check here if it is set at all, not if is it totally replaced,
14739 which is what `dead_or_set_p' checks, so also check for it being
14742 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14744 unsigned int regno
= REGNO (XEXP (note
, 0));
14745 reg_stat_type
*rsp
= ®_stat
[regno
];
14747 if (dead_or_set_p (place
, XEXP (note
, 0))
14748 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14750 /* Unless the register previously died in PLACE, clear
14751 last_death. [I no longer understand why this is
14753 if (rsp
->last_death
!= place
)
14754 rsp
->last_death
= 0;
14758 rsp
->last_death
= place
;
14760 /* If this is a death note for a hard reg that is occupying
14761 multiple registers, ensure that we are still using all
14762 parts of the object. If we find a piece of the object
14763 that is unused, we must arrange for an appropriate REG_DEAD
14764 note to be added for it. However, we can't just emit a USE
14765 and tag the note to it, since the register might actually
14766 be dead; so we recourse, and the recursive call then finds
14767 the previous insn that used this register. */
14769 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14771 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14772 bool all_used
= true;
14775 for (i
= regno
; i
< endregno
; i
++)
14776 if ((! refers_to_regno_p (i
, PATTERN (place
))
14777 && ! find_regno_fusage (place
, USE
, i
))
14778 || dead_or_set_regno_p (place
, i
))
14786 /* Put only REG_DEAD notes for pieces that are
14787 not already dead or set. */
14789 for (i
= regno
; i
< endregno
;
14790 i
+= hard_regno_nregs (i
, reg_raw_mode
[i
]))
14792 rtx piece
= regno_reg_rtx
[i
];
14793 basic_block bb
= this_basic_block
;
14795 if (! dead_or_set_p (place
, piece
)
14796 && ! reg_bitfield_target_p (piece
,
14799 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14802 distribute_notes (new_note
, place
, place
,
14803 NULL
, NULL_RTX
, NULL_RTX
,
14806 else if (! refers_to_regno_p (i
, PATTERN (place
))
14807 && ! find_regno_fusage (place
, USE
, i
))
14808 for (tem_insn
= PREV_INSN (place
); ;
14809 tem_insn
= PREV_INSN (tem_insn
))
14811 if (!NONDEBUG_INSN_P (tem_insn
))
14813 if (tem_insn
== BB_HEAD (bb
))
14817 if (dead_or_set_p (tem_insn
, piece
)
14818 || reg_bitfield_target_p (piece
,
14819 PATTERN (tem_insn
)))
14821 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14834 /* Any other notes should not be present at this point in the
14836 gcc_unreachable ();
14841 XEXP (note
, 1) = REG_NOTES (place
);
14842 REG_NOTES (place
) = note
;
14844 /* Set added_notes_insn to the earliest insn we added a note to. */
14845 if (added_notes_insn
== 0
14846 || DF_INSN_LUID (added_notes_insn
) > DF_INSN_LUID (place
))
14847 added_notes_insn
= place
;
14852 add_shallow_copy_of_reg_note (place2
, note
);
14854 /* Set added_notes_insn to the earliest insn we added a note to. */
14855 if (added_notes_insn
== 0
14856 || DF_INSN_LUID (added_notes_insn
) > DF_INSN_LUID (place2
))
14857 added_notes_insn
= place2
;
14862 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14863 I3, I2, and I1 to new locations. This is also called to add a link
14864 pointing at I3 when I3's destination is changed. */
14867 distribute_links (struct insn_link
*links
)
14869 struct insn_link
*link
, *next_link
;
14871 for (link
= links
; link
; link
= next_link
)
14873 rtx_insn
*place
= 0;
14877 next_link
= link
->next
;
14879 /* If the insn that this link points to is a NOTE, ignore it. */
14880 if (NOTE_P (link
->insn
))
14884 rtx pat
= PATTERN (link
->insn
);
14885 if (GET_CODE (pat
) == SET
)
14887 else if (GET_CODE (pat
) == PARALLEL
)
14890 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14892 set
= XVECEXP (pat
, 0, i
);
14893 if (GET_CODE (set
) != SET
)
14896 reg
= SET_DEST (set
);
14897 while (GET_CODE (reg
) == ZERO_EXTRACT
14898 || GET_CODE (reg
) == STRICT_LOW_PART
14899 || GET_CODE (reg
) == SUBREG
)
14900 reg
= XEXP (reg
, 0);
14905 if (REGNO (reg
) == link
->regno
)
14908 if (i
== XVECLEN (pat
, 0))
14914 reg
= SET_DEST (set
);
14916 while (GET_CODE (reg
) == ZERO_EXTRACT
14917 || GET_CODE (reg
) == STRICT_LOW_PART
14918 || GET_CODE (reg
) == SUBREG
)
14919 reg
= XEXP (reg
, 0);
14924 /* A LOG_LINK is defined as being placed on the first insn that uses
14925 a register and points to the insn that sets the register. Start
14926 searching at the next insn after the target of the link and stop
14927 when we reach a set of the register or the end of the basic block.
14929 Note that this correctly handles the link that used to point from
14930 I3 to I2. Also note that not much searching is typically done here
14931 since most links don't point very far away. */
14933 for (insn
= NEXT_INSN (link
->insn
);
14934 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14935 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14936 insn
= NEXT_INSN (insn
))
14937 if (DEBUG_INSN_P (insn
))
14939 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14941 if (reg_referenced_p (reg
, PATTERN (insn
)))
14945 else if (CALL_P (insn
)
14946 && find_reg_fusage (insn
, USE
, reg
))
14951 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14954 /* If we found a place to put the link, place it there unless there
14955 is already a link to the same insn as LINK at that point. */
14959 struct insn_link
*link2
;
14961 FOR_EACH_LOG_LINK (link2
, place
)
14962 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14967 link
->next
= LOG_LINKS (place
);
14968 LOG_LINKS (place
) = link
;
14970 /* Set added_links_insn to the earliest insn we added a
14972 if (added_links_insn
== 0
14973 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14974 added_links_insn
= place
;
14980 /* Check for any register or memory mentioned in EQUIV that is not
14981 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14982 of EXPR where some registers may have been replaced by constants. */
14985 unmentioned_reg_p (rtx equiv
, rtx expr
)
14987 subrtx_iterator::array_type array
;
14988 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14990 const_rtx x
= *iter
;
14991 if ((REG_P (x
) || MEM_P (x
))
14992 && !reg_mentioned_p (x
, expr
))
14998 DEBUG_FUNCTION
void
14999 dump_combine_stats (FILE *file
)
15003 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
15004 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
15008 dump_combine_total_stats (FILE *file
)
15012 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
15013 total_attempts
, total_merges
, total_extras
, total_successes
);
15016 /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
15017 the reg-to-reg copy can usefully combine with later instructions, but we
15018 do not want to combine the hard reg into later instructions, for that
15019 restricts register allocation. */
15021 make_more_copies (void)
15025 FOR_EACH_BB_FN (bb
, cfun
)
15029 FOR_BB_INSNS (bb
, insn
)
15031 if (!NONDEBUG_INSN_P (insn
))
15034 rtx set
= single_set (insn
);
15038 rtx dest
= SET_DEST (set
);
15039 if (!(REG_P (dest
) && !HARD_REGISTER_P (dest
)))
15042 rtx src
= SET_SRC (set
);
15043 if (!(REG_P (src
) && HARD_REGISTER_P (src
)))
15045 if (TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
)))
15048 rtx new_reg
= gen_reg_rtx (GET_MODE (dest
));
15049 rtx_insn
*new_insn
= gen_move_insn (new_reg
, src
);
15050 SET_SRC (set
) = new_reg
;
15051 emit_insn_before (new_insn
, insn
);
15052 df_insn_rescan (insn
);
15057 /* Try combining insns through substitution. */
15058 static unsigned int
15059 rest_of_handle_combine (void)
15061 make_more_copies ();
15063 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
15064 df_note_add_problem ();
15067 regstat_init_n_sets_and_refs ();
15068 reg_n_sets_max
= max_reg_num ();
15070 int rebuild_jump_labels_after_combine
15071 = combine_instructions (get_insns (), max_reg_num ());
15073 /* Combining insns may have turned an indirect jump into a
15074 direct jump. Rebuild the JUMP_LABEL fields of jumping
15076 if (rebuild_jump_labels_after_combine
)
15078 if (dom_info_available_p (CDI_DOMINATORS
))
15079 free_dominance_info (CDI_DOMINATORS
);
15080 timevar_push (TV_JUMP
);
15081 rebuild_jump_labels (get_insns ());
15083 timevar_pop (TV_JUMP
);
15086 regstat_free_n_sets_and_refs ();
15092 const pass_data pass_data_combine
=
15094 RTL_PASS
, /* type */
15095 "combine", /* name */
15096 OPTGROUP_NONE
, /* optinfo_flags */
15097 TV_COMBINE
, /* tv_id */
15098 PROP_cfglayout
, /* properties_required */
15099 0, /* properties_provided */
15100 0, /* properties_destroyed */
15101 0, /* todo_flags_start */
15102 TODO_df_finish
, /* todo_flags_finish */
15105 class pass_combine
: public rtl_opt_pass
15108 pass_combine (gcc::context
*ctxt
)
15109 : rtl_opt_pass (pass_data_combine
, ctxt
)
15112 /* opt_pass methods: */
15113 virtual bool gate (function
*) { return (optimize
> 0); }
15114 virtual unsigned int execute (function
*)
15116 return rest_of_handle_combine ();
15119 }; // class pass_combine
15121 } // anon namespace
15124 make_pass_combine (gcc::context
*ctxt
)
15126 return new pass_combine (ctxt
);