| blob | ca615e5693cdb86a39ba5b4a0bb175d1fb311017 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; REGNOS
27 ;;
29 (define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
52 ;;
53 ;; UNSPEC usage
54 ;;
56 (define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
63 (UNSPEC_FCTIWZ 10)
64 (UNSPEC_FRIM 11)
65 (UNSPEC_FRIN 12)
66 (UNSPEC_FRIP 13)
67 (UNSPEC_FRIZ 14)
68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
70 (UNSPEC_TLSGD 17)
71 (UNSPEC_TLSLD 18)
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
74 (UNSPEC_TLSDTPREL 21)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
78 (UNSPEC_TLSTPREL 25)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
82 (UNSPEC_TLSTLS 29)
83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
85 (UNSPEC_STFIWX 32)
86 (UNSPEC_POPCNTB 33)
87 (UNSPEC_FRES 34)
88 (UNSPEC_SP_SET 35)
89 (UNSPEC_SP_TEST 36)
90 (UNSPEC_SYNC 37)
91 (UNSPEC_LWSYNC 38)
92 (UNSPEC_ISYNC 39)
93 (UNSPEC_SYNC_OP 40)
94 (UNSPEC_ATOMIC 41)
95 (UNSPEC_CMPXCHG 42)
96 (UNSPEC_XCHG 43)
97 (UNSPEC_AND 44)
98 (UNSPEC_DLMZB 45)
99 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47)
101 (UNSPEC_RSQRT 48)
102 ])
104 ;;
105 ;; UNSPEC_VOLATILE usage
106 ;;
108 (define_constants
109 [(UNSPECV_BLOCK 0)
110 (UNSPECV_LL 1) ; load-locked
111 (UNSPECV_SC 2) ; store-conditional
112 (UNSPECV_EH_RR 9) ; eh_reg_restore
113 ])
114 \f
115 ;; Define an insn type attribute. This is used in function unit delay
116 ;; computations.
117 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
118 (const_string "integer"))
120 ;; Length (in bytes).
121 ; '(pc)' in the following doesn't include the instruction itself; it is
122 ; calculated as if the instruction had zero size.
123 (define_attr "length" ""
124 (if_then_else (eq_attr "type" "branch")
125 (if_then_else (and (ge (minus (match_dup 0) (pc))
126 (const_int -32768))
127 (lt (minus (match_dup 0) (pc))
128 (const_int 32764)))
129 (const_int 4)
130 (const_int 8))
131 (const_int 4)))
133 ;; Processor type -- this attribute must exactly match the processor_type
134 ;; enumeration in rs6000.h.
136 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,cell"
137 (const (symbol_ref "rs6000_cpu_attr")))
140 ;; If this instruction is microcoded on the CELL processor
141 ; The default for load and stores is conditional
142 ; The default for load extended and the recorded instructions is always microcoded
143 (define_attr "cell_micro" "not,conditional,always"
144 (if_then_else (ior (ior (eq_attr "type" "load")
145 (eq_attr "type" "store"))
146 (ior (eq_attr "type" "fpload")
147 (eq_attr "type" "fpstore")))
148 (const_string "conditional")
149 (if_then_else (ior (eq_attr "type" "load_ext")
150 (ior (eq_attr "type" "compare")
151 (eq_attr "type" "delayed_compare")))
152 (const_string "always")
153 (const_string "not"))))
156 (automata_option "ndfa")
158 (include "rios1.md")
159 (include "rios2.md")
160 (include "rs64.md")
161 (include "mpc.md")
162 (include "40x.md")
163 (include "440.md")
164 (include "603.md")
165 (include "6xx.md")
166 (include "7xx.md")
167 (include "7450.md")
168 (include "8540.md")
169 (include "e300c2c3.md")
170 (include "e500mc.md")
171 (include "power4.md")
172 (include "power5.md")
173 (include "power6.md")
174 (include "cell.md")
176 (include "predicates.md")
177 (include "constraints.md")
179 (include "darwin.md")
181 \f
182 ;; Mode iterators
184 ; This mode iterator allows :GPR to be used to indicate the allowable size
185 ; of whole values in GPRs.
186 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
188 ; Any supported integer mode.
189 (define_mode_iterator INT [QI HI SI DI TI])
191 ; Any supported integer mode that fits in one register.
192 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
194 ; extend modes for DImode
195 (define_mode_iterator QHSI [QI HI SI])
197 ; SImode or DImode, even if DImode doesn't fit in GPRs.
198 (define_mode_iterator SDI [SI DI])
200 ; The size of a pointer. Also, the size of the value that a record-condition
201 ; (one with a '.') will compare.
202 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
204 ; Any hardware-supported floating-point mode
205 (define_mode_iterator FP [
206 (SF "TARGET_HARD_FLOAT
207 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
208 (DF "TARGET_HARD_FLOAT
209 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
210 (TF "!TARGET_IEEEQUAD
211 && TARGET_HARD_FLOAT
212 && (TARGET_FPRS || TARGET_E500_DOUBLE)
213 && TARGET_LONG_DOUBLE_128")
214 (DD "TARGET_DFP")
215 (TD "TARGET_DFP")])
217 ; Various instructions that come in SI and DI forms.
218 ; A generic w/d attribute, for things like cmpw/cmpd.
219 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
221 ; DImode bits
222 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
224 \f
225 ;; Start with fixed-point load and store insns. Here we put only the more
226 ;; complex forms. Basic data transfer is done later.
228 (define_expand "zero_extend<mode>di2"
229 [(set (match_operand:DI 0 "gpc_reg_operand" "")
230 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
231 "TARGET_POWERPC64"
232 "")
234 (define_insn "*zero_extend<mode>di2_internal1"
235 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
236 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
237 "TARGET_POWERPC64"
238 "@
239 l<wd>z%U1%X1 %0,%1
240 rldicl %0,%1,0,<dbits>"
241 [(set_attr "type" "load,*")])
243 (define_insn "*zero_extend<mode>di2_internal2"
244 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
245 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
246 (const_int 0)))
247 (clobber (match_scratch:DI 2 "=r,r"))]
248 "TARGET_64BIT"
249 "@
250 rldicl. %2,%1,0,<dbits>
251 #"
252 [(set_attr "type" "compare")
253 (set_attr "length" "4,8")])
255 (define_split
256 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
257 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
258 (const_int 0)))
259 (clobber (match_scratch:DI 2 ""))]
260 "TARGET_POWERPC64 && reload_completed"
261 [(set (match_dup 2)
262 (zero_extend:DI (match_dup 1)))
263 (set (match_dup 0)
264 (compare:CC (match_dup 2)
265 (const_int 0)))]
266 "")
268 (define_insn "*zero_extend<mode>di2_internal3"
269 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
270 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
271 (const_int 0)))
272 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
273 (zero_extend:DI (match_dup 1)))]
274 "TARGET_64BIT"
275 "@
276 rldicl. %0,%1,0,<dbits>
277 #"
278 [(set_attr "type" "compare")
279 (set_attr "length" "4,8")])
281 (define_split
282 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
283 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
284 (const_int 0)))
285 (set (match_operand:DI 0 "gpc_reg_operand" "")
286 (zero_extend:DI (match_dup 1)))]
287 "TARGET_POWERPC64 && reload_completed"
288 [(set (match_dup 0)
289 (zero_extend:DI (match_dup 1)))
290 (set (match_dup 2)
291 (compare:CC (match_dup 0)
292 (const_int 0)))]
293 "")
295 (define_insn "extendqidi2"
296 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
297 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
298 "TARGET_POWERPC64"
299 "extsb %0,%1"
300 [(set_attr "type" "exts")])
302 (define_insn ""
303 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
304 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
305 (const_int 0)))
306 (clobber (match_scratch:DI 2 "=r,r"))]
307 "TARGET_64BIT"
308 "@
309 extsb. %2,%1
310 #"
311 [(set_attr "type" "compare")
312 (set_attr "length" "4,8")])
314 (define_split
315 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
316 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
317 (const_int 0)))
318 (clobber (match_scratch:DI 2 ""))]
319 "TARGET_POWERPC64 && reload_completed"
320 [(set (match_dup 2)
321 (sign_extend:DI (match_dup 1)))
322 (set (match_dup 0)
323 (compare:CC (match_dup 2)
324 (const_int 0)))]
325 "")
327 (define_insn ""
328 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
329 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
330 (const_int 0)))
331 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
332 (sign_extend:DI (match_dup 1)))]
333 "TARGET_64BIT"
334 "@
335 extsb. %0,%1
336 #"
337 [(set_attr "type" "compare")
338 (set_attr "length" "4,8")])
340 (define_split
341 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
342 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
343 (const_int 0)))
344 (set (match_operand:DI 0 "gpc_reg_operand" "")
345 (sign_extend:DI (match_dup 1)))]
346 "TARGET_POWERPC64 && reload_completed"
347 [(set (match_dup 0)
348 (sign_extend:DI (match_dup 1)))
349 (set (match_dup 2)
350 (compare:CC (match_dup 0)
351 (const_int 0)))]
352 "")
354 (define_expand "extendhidi2"
355 [(set (match_operand:DI 0 "gpc_reg_operand" "")
356 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
357 "TARGET_POWERPC64"
358 "")
360 (define_insn ""
361 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
362 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
363 "TARGET_POWERPC64"
364 "@
365 lha%U1%X1 %0,%1
366 extsh %0,%1"
367 [(set_attr "type" "load_ext,exts")])
369 (define_insn ""
370 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
371 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
372 (const_int 0)))
373 (clobber (match_scratch:DI 2 "=r,r"))]
374 "TARGET_64BIT"
375 "@
376 extsh. %2,%1
377 #"
378 [(set_attr "type" "compare")
379 (set_attr "length" "4,8")])
381 (define_split
382 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
383 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
384 (const_int 0)))
385 (clobber (match_scratch:DI 2 ""))]
386 "TARGET_POWERPC64 && reload_completed"
387 [(set (match_dup 2)
388 (sign_extend:DI (match_dup 1)))
389 (set (match_dup 0)
390 (compare:CC (match_dup 2)
391 (const_int 0)))]
392 "")
394 (define_insn ""
395 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
396 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
397 (const_int 0)))
398 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
399 (sign_extend:DI (match_dup 1)))]
400 "TARGET_64BIT"
401 "@
402 extsh. %0,%1
403 #"
404 [(set_attr "type" "compare")
405 (set_attr "length" "4,8")])
407 (define_split
408 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
409 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
410 (const_int 0)))
411 (set (match_operand:DI 0 "gpc_reg_operand" "")
412 (sign_extend:DI (match_dup 1)))]
413 "TARGET_POWERPC64 && reload_completed"
414 [(set (match_dup 0)
415 (sign_extend:DI (match_dup 1)))
416 (set (match_dup 2)
417 (compare:CC (match_dup 0)
418 (const_int 0)))]
419 "")
421 (define_expand "extendsidi2"
422 [(set (match_operand:DI 0 "gpc_reg_operand" "")
423 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
424 "TARGET_POWERPC64"
425 "")
427 (define_insn ""
428 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
429 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
430 "TARGET_POWERPC64"
431 "@
432 lwa%U1%X1 %0,%1
433 extsw %0,%1"
434 [(set_attr "type" "load_ext,exts")])
436 (define_insn ""
437 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
438 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
439 (const_int 0)))
440 (clobber (match_scratch:DI 2 "=r,r"))]
441 "TARGET_64BIT"
442 "@
443 extsw. %2,%1
444 #"
445 [(set_attr "type" "compare")
446 (set_attr "length" "4,8")])
448 (define_split
449 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
450 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
451 (const_int 0)))
452 (clobber (match_scratch:DI 2 ""))]
453 "TARGET_POWERPC64 && reload_completed"
454 [(set (match_dup 2)
455 (sign_extend:DI (match_dup 1)))
456 (set (match_dup 0)
457 (compare:CC (match_dup 2)
458 (const_int 0)))]
459 "")
461 (define_insn ""
462 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
463 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
464 (const_int 0)))
465 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
466 (sign_extend:DI (match_dup 1)))]
467 "TARGET_64BIT"
468 "@
469 extsw. %0,%1
470 #"
471 [(set_attr "type" "compare")
472 (set_attr "length" "4,8")])
474 (define_split
475 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
476 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
477 (const_int 0)))
478 (set (match_operand:DI 0 "gpc_reg_operand" "")
479 (sign_extend:DI (match_dup 1)))]
480 "TARGET_POWERPC64 && reload_completed"
481 [(set (match_dup 0)
482 (sign_extend:DI (match_dup 1)))
483 (set (match_dup 2)
484 (compare:CC (match_dup 0)
485 (const_int 0)))]
486 "")
488 (define_expand "zero_extendqisi2"
489 [(set (match_operand:SI 0 "gpc_reg_operand" "")
490 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
491 ""
492 "")
494 (define_insn ""
495 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
496 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
497 ""
498 "@
499 lbz%U1%X1 %0,%1
500 {rlinm|rlwinm} %0,%1,0,0xff"
501 [(set_attr "type" "load,*")])
503 (define_insn ""
504 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
505 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
506 (const_int 0)))
507 (clobber (match_scratch:SI 2 "=r,r"))]
508 ""
509 "@
510 {andil.|andi.} %2,%1,0xff
511 #"
512 [(set_attr "type" "compare")
513 (set_attr "length" "4,8")])
515 (define_split
516 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
517 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
518 (const_int 0)))
519 (clobber (match_scratch:SI 2 ""))]
520 "reload_completed"
521 [(set (match_dup 2)
522 (zero_extend:SI (match_dup 1)))
523 (set (match_dup 0)
524 (compare:CC (match_dup 2)
525 (const_int 0)))]
526 "")
528 (define_insn ""
529 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
530 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
531 (const_int 0)))
532 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
533 (zero_extend:SI (match_dup 1)))]
534 ""
535 "@
536 {andil.|andi.} %0,%1,0xff
537 #"
538 [(set_attr "type" "compare")
539 (set_attr "length" "4,8")])
541 (define_split
542 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
543 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
544 (const_int 0)))
545 (set (match_operand:SI 0 "gpc_reg_operand" "")
546 (zero_extend:SI (match_dup 1)))]
547 "reload_completed"
548 [(set (match_dup 0)
549 (zero_extend:SI (match_dup 1)))
550 (set (match_dup 2)
551 (compare:CC (match_dup 0)
552 (const_int 0)))]
553 "")
555 (define_expand "extendqisi2"
556 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
557 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
558 ""
559 "
560 {
561 if (TARGET_POWERPC)
562 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
563 else if (TARGET_POWER)
564 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
565 else
566 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
567 DONE;
568 }")
570 (define_insn "extendqisi2_ppc"
571 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
572 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
573 "TARGET_POWERPC"
574 "extsb %0,%1"
575 [(set_attr "type" "exts")])
577 (define_insn ""
578 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
579 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
580 (const_int 0)))
581 (clobber (match_scratch:SI 2 "=r,r"))]
582 "TARGET_POWERPC"
583 "@
584 extsb. %2,%1
585 #"
586 [(set_attr "type" "compare")
587 (set_attr "length" "4,8")])
589 (define_split
590 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
591 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
592 (const_int 0)))
593 (clobber (match_scratch:SI 2 ""))]
594 "TARGET_POWERPC && reload_completed"
595 [(set (match_dup 2)
596 (sign_extend:SI (match_dup 1)))
597 (set (match_dup 0)
598 (compare:CC (match_dup 2)
599 (const_int 0)))]
600 "")
602 (define_insn ""
603 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
604 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
605 (const_int 0)))
606 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
607 (sign_extend:SI (match_dup 1)))]
608 "TARGET_POWERPC"
609 "@
610 extsb. %0,%1
611 #"
612 [(set_attr "type" "compare")
613 (set_attr "length" "4,8")])
615 (define_split
616 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
617 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
618 (const_int 0)))
619 (set (match_operand:SI 0 "gpc_reg_operand" "")
620 (sign_extend:SI (match_dup 1)))]
621 "TARGET_POWERPC && reload_completed"
622 [(set (match_dup 0)
623 (sign_extend:SI (match_dup 1)))
624 (set (match_dup 2)
625 (compare:CC (match_dup 0)
626 (const_int 0)))]
627 "")
629 (define_expand "extendqisi2_power"
630 [(parallel [(set (match_dup 2)
631 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
632 (const_int 24)))
633 (clobber (scratch:SI))])
634 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
635 (ashiftrt:SI (match_dup 2)
636 (const_int 24)))
637 (clobber (scratch:SI))])]
638 "TARGET_POWER"
639 "
640 { operands[1] = gen_lowpart (SImode, operands[1]);
641 operands[2] = gen_reg_rtx (SImode); }")
643 (define_expand "extendqisi2_no_power"
644 [(set (match_dup 2)
645 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
646 (const_int 24)))
647 (set (match_operand:SI 0 "gpc_reg_operand" "")
648 (ashiftrt:SI (match_dup 2)
649 (const_int 24)))]
650 "! TARGET_POWER && ! TARGET_POWERPC"
651 "
652 { operands[1] = gen_lowpart (SImode, operands[1]);
653 operands[2] = gen_reg_rtx (SImode); }")
655 (define_expand "zero_extendqihi2"
656 [(set (match_operand:HI 0 "gpc_reg_operand" "")
657 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
658 ""
659 "")
661 (define_insn ""
662 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
663 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
664 ""
665 "@
666 lbz%U1%X1 %0,%1
667 {rlinm|rlwinm} %0,%1,0,0xff"
668 [(set_attr "type" "load,*")])
670 (define_insn ""
671 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
672 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
673 (const_int 0)))
674 (clobber (match_scratch:HI 2 "=r,r"))]
675 ""
676 "@
677 {andil.|andi.} %2,%1,0xff
678 #"
679 [(set_attr "type" "compare")
680 (set_attr "length" "4,8")])
682 (define_split
683 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
684 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
685 (const_int 0)))
686 (clobber (match_scratch:HI 2 ""))]
687 "reload_completed"
688 [(set (match_dup 2)
689 (zero_extend:HI (match_dup 1)))
690 (set (match_dup 0)
691 (compare:CC (match_dup 2)
692 (const_int 0)))]
693 "")
695 (define_insn ""
696 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
697 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
698 (const_int 0)))
699 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
700 (zero_extend:HI (match_dup 1)))]
701 ""
702 "@
703 {andil.|andi.} %0,%1,0xff
704 #"
705 [(set_attr "type" "compare")
706 (set_attr "length" "4,8")])
708 (define_split
709 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
710 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
711 (const_int 0)))
712 (set (match_operand:HI 0 "gpc_reg_operand" "")
713 (zero_extend:HI (match_dup 1)))]
714 "reload_completed"
715 [(set (match_dup 0)
716 (zero_extend:HI (match_dup 1)))
717 (set (match_dup 2)
718 (compare:CC (match_dup 0)
719 (const_int 0)))]
720 "")
722 (define_expand "extendqihi2"
723 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
724 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
725 ""
726 "
727 {
728 if (TARGET_POWERPC)
729 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
730 else if (TARGET_POWER)
731 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
732 else
733 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
734 DONE;
735 }")
737 (define_insn "extendqihi2_ppc"
738 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
739 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
740 "TARGET_POWERPC"
741 "extsb %0,%1"
742 [(set_attr "type" "exts")])
744 (define_insn ""
745 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
746 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
747 (const_int 0)))
748 (clobber (match_scratch:HI 2 "=r,r"))]
749 "TARGET_POWERPC"
750 "@
751 extsb. %2,%1
752 #"
753 [(set_attr "type" "compare")
754 (set_attr "length" "4,8")])
756 (define_split
757 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
758 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
759 (const_int 0)))
760 (clobber (match_scratch:HI 2 ""))]
761 "TARGET_POWERPC && reload_completed"
762 [(set (match_dup 2)
763 (sign_extend:HI (match_dup 1)))
764 (set (match_dup 0)
765 (compare:CC (match_dup 2)
766 (const_int 0)))]
767 "")
769 (define_insn ""
770 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
771 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
772 (const_int 0)))
773 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
774 (sign_extend:HI (match_dup 1)))]
775 "TARGET_POWERPC"
776 "@
777 extsb. %0,%1
778 #"
779 [(set_attr "type" "compare")
780 (set_attr "length" "4,8")])
782 (define_split
783 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
784 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
785 (const_int 0)))
786 (set (match_operand:HI 0 "gpc_reg_operand" "")
787 (sign_extend:HI (match_dup 1)))]
788 "TARGET_POWERPC && reload_completed"
789 [(set (match_dup 0)
790 (sign_extend:HI (match_dup 1)))
791 (set (match_dup 2)
792 (compare:CC (match_dup 0)
793 (const_int 0)))]
794 "")
796 (define_expand "extendqihi2_power"
797 [(parallel [(set (match_dup 2)
798 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
799 (const_int 24)))
800 (clobber (scratch:SI))])
801 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
802 (ashiftrt:SI (match_dup 2)
803 (const_int 24)))
804 (clobber (scratch:SI))])]
805 "TARGET_POWER"
806 "
807 { operands[0] = gen_lowpart (SImode, operands[0]);
808 operands[1] = gen_lowpart (SImode, operands[1]);
809 operands[2] = gen_reg_rtx (SImode); }")
811 (define_expand "extendqihi2_no_power"
812 [(set (match_dup 2)
813 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
814 (const_int 24)))
815 (set (match_operand:HI 0 "gpc_reg_operand" "")
816 (ashiftrt:SI (match_dup 2)
817 (const_int 24)))]
818 "! TARGET_POWER && ! TARGET_POWERPC"
819 "
820 { operands[0] = gen_lowpart (SImode, operands[0]);
821 operands[1] = gen_lowpart (SImode, operands[1]);
822 operands[2] = gen_reg_rtx (SImode); }")
824 (define_expand "zero_extendhisi2"
825 [(set (match_operand:SI 0 "gpc_reg_operand" "")
826 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
827 ""
828 "")
830 (define_insn ""
831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
832 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
833 ""
834 "@
835 lhz%U1%X1 %0,%1
836 {rlinm|rlwinm} %0,%1,0,0xffff"
837 [(set_attr "type" "load,*")])
839 (define_insn ""
840 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
841 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
842 (const_int 0)))
843 (clobber (match_scratch:SI 2 "=r,r"))]
844 ""
845 "@
846 {andil.|andi.} %2,%1,0xffff
847 #"
848 [(set_attr "type" "compare")
849 (set_attr "length" "4,8")])
851 (define_split
852 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
853 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
854 (const_int 0)))
855 (clobber (match_scratch:SI 2 ""))]
856 "reload_completed"
857 [(set (match_dup 2)
858 (zero_extend:SI (match_dup 1)))
859 (set (match_dup 0)
860 (compare:CC (match_dup 2)
861 (const_int 0)))]
862 "")
864 (define_insn ""
865 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
866 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
867 (const_int 0)))
868 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
869 (zero_extend:SI (match_dup 1)))]
870 ""
871 "@
872 {andil.|andi.} %0,%1,0xffff
873 #"
874 [(set_attr "type" "compare")
875 (set_attr "length" "4,8")])
877 (define_split
878 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
879 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
880 (const_int 0)))
881 (set (match_operand:SI 0 "gpc_reg_operand" "")
882 (zero_extend:SI (match_dup 1)))]
883 "reload_completed"
884 [(set (match_dup 0)
885 (zero_extend:SI (match_dup 1)))
886 (set (match_dup 2)
887 (compare:CC (match_dup 0)
888 (const_int 0)))]
889 "")
891 (define_expand "extendhisi2"
892 [(set (match_operand:SI 0 "gpc_reg_operand" "")
893 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
894 ""
895 "")
897 (define_insn ""
898 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
899 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
900 ""
901 "@
902 lha%U1%X1 %0,%1
903 {exts|extsh} %0,%1"
904 [(set_attr "type" "load_ext,exts")])
906 (define_insn ""
907 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
908 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
909 (const_int 0)))
910 (clobber (match_scratch:SI 2 "=r,r"))]
911 ""
912 "@
913 {exts.|extsh.} %2,%1
914 #"
915 [(set_attr "type" "compare")
916 (set_attr "length" "4,8")])
918 (define_split
919 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
920 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
921 (const_int 0)))
922 (clobber (match_scratch:SI 2 ""))]
923 "reload_completed"
924 [(set (match_dup 2)
925 (sign_extend:SI (match_dup 1)))
926 (set (match_dup 0)
927 (compare:CC (match_dup 2)
928 (const_int 0)))]
929 "")
931 (define_insn ""
932 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
933 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
934 (const_int 0)))
935 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
936 (sign_extend:SI (match_dup 1)))]
937 ""
938 "@
939 {exts.|extsh.} %0,%1
940 #"
941 [(set_attr "type" "compare")
942 (set_attr "length" "4,8")])
943 \f
944 ;; IBM 405, 440 and 464 half-word multiplication operations.
946 (define_insn "*macchwc"
947 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
948 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
949 (match_operand:SI 2 "gpc_reg_operand" "r")
950 (const_int 16))
951 (sign_extend:SI
952 (match_operand:HI 1 "gpc_reg_operand" "r")))
953 (match_operand:SI 4 "gpc_reg_operand" "0"))
954 (const_int 0)))
955 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
956 (plus:SI (mult:SI (ashiftrt:SI
957 (match_dup 2)
958 (const_int 16))
959 (sign_extend:SI
960 (match_dup 1)))
961 (match_dup 4)))]
962 "TARGET_MULHW"
963 "macchw. %0, %1, %2"
964 [(set_attr "type" "imul3")])
966 (define_insn "*macchw"
967 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
968 (plus:SI (mult:SI (ashiftrt:SI
969 (match_operand:SI 2 "gpc_reg_operand" "r")
970 (const_int 16))
971 (sign_extend:SI
972 (match_operand:HI 1 "gpc_reg_operand" "r")))
973 (match_operand:SI 3 "gpc_reg_operand" "0")))]
974 "TARGET_MULHW"
975 "macchw %0, %1, %2"
976 [(set_attr "type" "imul3")])
978 (define_insn "*macchwuc"
979 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
980 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
981 (match_operand:SI 2 "gpc_reg_operand" "r")
982 (const_int 16))
983 (zero_extend:SI
984 (match_operand:HI 1 "gpc_reg_operand" "r")))
985 (match_operand:SI 4 "gpc_reg_operand" "0"))
986 (const_int 0)))
987 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
988 (plus:SI (mult:SI (lshiftrt:SI
989 (match_dup 2)
990 (const_int 16))
991 (zero_extend:SI
992 (match_dup 1)))
993 (match_dup 4)))]
994 "TARGET_MULHW"
995 "macchwu. %0, %1, %2"
996 [(set_attr "type" "imul3")])
998 (define_insn "*macchwu"
999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1000 (plus:SI (mult:SI (lshiftrt:SI
1001 (match_operand:SI 2 "gpc_reg_operand" "r")
1002 (const_int 16))
1003 (zero_extend:SI
1004 (match_operand:HI 1 "gpc_reg_operand" "r")))
1005 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1006 "TARGET_MULHW"
1007 "macchwu %0, %1, %2"
1008 [(set_attr "type" "imul3")])
1010 (define_insn "*machhwc"
1011 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1012 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1013 (match_operand:SI 1 "gpc_reg_operand" "%r")
1014 (const_int 16))
1015 (ashiftrt:SI
1016 (match_operand:SI 2 "gpc_reg_operand" "r")
1017 (const_int 16)))
1018 (match_operand:SI 4 "gpc_reg_operand" "0"))
1019 (const_int 0)))
1020 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1021 (plus:SI (mult:SI (ashiftrt:SI
1022 (match_dup 1)
1023 (const_int 16))
1024 (ashiftrt:SI
1025 (match_dup 2)
1026 (const_int 16)))
1027 (match_dup 4)))]
1028 "TARGET_MULHW"
1029 "machhw. %0, %1, %2"
1030 [(set_attr "type" "imul3")])
1032 (define_insn "*machhw"
1033 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1034 (plus:SI (mult:SI (ashiftrt:SI
1035 (match_operand:SI 1 "gpc_reg_operand" "%r")
1036 (const_int 16))
1037 (ashiftrt:SI
1038 (match_operand:SI 2 "gpc_reg_operand" "r")
1039 (const_int 16)))
1040 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1041 "TARGET_MULHW"
1042 "machhw %0, %1, %2"
1043 [(set_attr "type" "imul3")])
1045 (define_insn "*machhwuc"
1046 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1047 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1048 (match_operand:SI 1 "gpc_reg_operand" "%r")
1049 (const_int 16))
1050 (lshiftrt:SI
1051 (match_operand:SI 2 "gpc_reg_operand" "r")
1052 (const_int 16)))
1053 (match_operand:SI 4 "gpc_reg_operand" "0"))
1054 (const_int 0)))
1055 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1056 (plus:SI (mult:SI (lshiftrt:SI
1057 (match_dup 1)
1058 (const_int 16))
1059 (lshiftrt:SI
1060 (match_dup 2)
1061 (const_int 16)))
1062 (match_dup 4)))]
1063 "TARGET_MULHW"
1064 "machhwu. %0, %1, %2"
1065 [(set_attr "type" "imul3")])
1067 (define_insn "*machhwu"
1068 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1069 (plus:SI (mult:SI (lshiftrt:SI
1070 (match_operand:SI 1 "gpc_reg_operand" "%r")
1071 (const_int 16))
1072 (lshiftrt:SI
1073 (match_operand:SI 2 "gpc_reg_operand" "r")
1074 (const_int 16)))
1075 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1076 "TARGET_MULHW"
1077 "machhwu %0, %1, %2"
1078 [(set_attr "type" "imul3")])
1080 (define_insn "*maclhwc"
1081 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1082 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1083 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1084 (sign_extend:SI
1085 (match_operand:HI 2 "gpc_reg_operand" "r")))
1086 (match_operand:SI 4 "gpc_reg_operand" "0"))
1087 (const_int 0)))
1088 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1089 (plus:SI (mult:SI (sign_extend:SI
1090 (match_dup 1))
1091 (sign_extend:SI
1092 (match_dup 2)))
1093 (match_dup 4)))]
1094 "TARGET_MULHW"
1095 "maclhw. %0, %1, %2"
1096 [(set_attr "type" "imul3")])
1098 (define_insn "*maclhw"
1099 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1100 (plus:SI (mult:SI (sign_extend:SI
1101 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1102 (sign_extend:SI
1103 (match_operand:HI 2 "gpc_reg_operand" "r")))
1104 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1105 "TARGET_MULHW"
1106 "maclhw %0, %1, %2"
1107 [(set_attr "type" "imul3")])
1109 (define_insn "*maclhwuc"
1110 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1111 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1112 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1113 (zero_extend:SI
1114 (match_operand:HI 2 "gpc_reg_operand" "r")))
1115 (match_operand:SI 4 "gpc_reg_operand" "0"))
1116 (const_int 0)))
1117 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1118 (plus:SI (mult:SI (zero_extend:SI
1119 (match_dup 1))
1120 (zero_extend:SI
1121 (match_dup 2)))
1122 (match_dup 4)))]
1123 "TARGET_MULHW"
1124 "maclhwu. %0, %1, %2"
1125 [(set_attr "type" "imul3")])
1127 (define_insn "*maclhwu"
1128 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1129 (plus:SI (mult:SI (zero_extend:SI
1130 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1131 (zero_extend:SI
1132 (match_operand:HI 2 "gpc_reg_operand" "r")))
1133 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1134 "TARGET_MULHW"
1135 "maclhwu %0, %1, %2"
1136 [(set_attr "type" "imul3")])
1138 (define_insn "*nmacchwc"
1139 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1140 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1141 (mult:SI (ashiftrt:SI
1142 (match_operand:SI 2 "gpc_reg_operand" "r")
1143 (const_int 16))
1144 (sign_extend:SI
1145 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1146 (const_int 0)))
1147 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1148 (minus:SI (match_dup 4)
1149 (mult:SI (ashiftrt:SI
1150 (match_dup 2)
1151 (const_int 16))
1152 (sign_extend:SI
1153 (match_dup 1)))))]
1154 "TARGET_MULHW"
1155 "nmacchw. %0, %1, %2"
1156 [(set_attr "type" "imul3")])
1158 (define_insn "*nmacchw"
1159 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1160 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1161 (mult:SI (ashiftrt:SI
1162 (match_operand:SI 2 "gpc_reg_operand" "r")
1163 (const_int 16))
1164 (sign_extend:SI
1165 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1166 "TARGET_MULHW"
1167 "nmacchw %0, %1, %2"
1168 [(set_attr "type" "imul3")])
1170 (define_insn "*nmachhwc"
1171 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1172 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1173 (mult:SI (ashiftrt:SI
1174 (match_operand:SI 1 "gpc_reg_operand" "%r")
1175 (const_int 16))
1176 (ashiftrt:SI
1177 (match_operand:SI 2 "gpc_reg_operand" "r")
1178 (const_int 16))))
1179 (const_int 0)))
1180 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1181 (minus:SI (match_dup 4)
1182 (mult:SI (ashiftrt:SI
1183 (match_dup 1)
1184 (const_int 16))
1185 (ashiftrt:SI
1186 (match_dup 2)
1187 (const_int 16)))))]
1188 "TARGET_MULHW"
1189 "nmachhw. %0, %1, %2"
1190 [(set_attr "type" "imul3")])
1192 (define_insn "*nmachhw"
1193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1194 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1195 (mult:SI (ashiftrt:SI
1196 (match_operand:SI 1 "gpc_reg_operand" "%r")
1197 (const_int 16))
1198 (ashiftrt:SI
1199 (match_operand:SI 2 "gpc_reg_operand" "r")
1200 (const_int 16)))))]
1201 "TARGET_MULHW"
1202 "nmachhw %0, %1, %2"
1203 [(set_attr "type" "imul3")])
1205 (define_insn "*nmaclhwc"
1206 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1207 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1208 (mult:SI (sign_extend:SI
1209 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1210 (sign_extend:SI
1211 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1212 (const_int 0)))
1213 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1214 (minus:SI (match_dup 4)
1215 (mult:SI (sign_extend:SI
1216 (match_dup 1))
1217 (sign_extend:SI
1218 (match_dup 2)))))]
1219 "TARGET_MULHW"
1220 "nmaclhw. %0, %1, %2"
1221 [(set_attr "type" "imul3")])
1223 (define_insn "*nmaclhw"
1224 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1225 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1226 (mult:SI (sign_extend:SI
1227 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1228 (sign_extend:SI
1229 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1230 "TARGET_MULHW"
1231 "nmaclhw %0, %1, %2"
1232 [(set_attr "type" "imul3")])
1234 (define_insn "*mulchwc"
1235 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1236 (compare:CC (mult:SI (ashiftrt:SI
1237 (match_operand:SI 2 "gpc_reg_operand" "r")
1238 (const_int 16))
1239 (sign_extend:SI
1240 (match_operand:HI 1 "gpc_reg_operand" "r")))
1241 (const_int 0)))
1242 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1243 (mult:SI (ashiftrt:SI
1244 (match_dup 2)
1245 (const_int 16))
1246 (sign_extend:SI
1247 (match_dup 1))))]
1248 "TARGET_MULHW"
1249 "mulchw. %0, %1, %2"
1250 [(set_attr "type" "imul3")])
1252 (define_insn "*mulchw"
1253 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1254 (mult:SI (ashiftrt:SI
1255 (match_operand:SI 2 "gpc_reg_operand" "r")
1256 (const_int 16))
1257 (sign_extend:SI
1258 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1259 "TARGET_MULHW"
1260 "mulchw %0, %1, %2"
1261 [(set_attr "type" "imul3")])
1263 (define_insn "*mulchwuc"
1264 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1265 (compare:CC (mult:SI (lshiftrt:SI
1266 (match_operand:SI 2 "gpc_reg_operand" "r")
1267 (const_int 16))
1268 (zero_extend:SI
1269 (match_operand:HI 1 "gpc_reg_operand" "r")))
1270 (const_int 0)))
1271 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1272 (mult:SI (lshiftrt:SI
1273 (match_dup 2)
1274 (const_int 16))
1275 (zero_extend:SI
1276 (match_dup 1))))]
1277 "TARGET_MULHW"
1278 "mulchwu. %0, %1, %2"
1279 [(set_attr "type" "imul3")])
1281 (define_insn "*mulchwu"
1282 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1283 (mult:SI (lshiftrt:SI
1284 (match_operand:SI 2 "gpc_reg_operand" "r")
1285 (const_int 16))
1286 (zero_extend:SI
1287 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1288 "TARGET_MULHW"
1289 "mulchwu %0, %1, %2"
1290 [(set_attr "type" "imul3")])
1292 (define_insn "*mulhhwc"
1293 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1294 (compare:CC (mult:SI (ashiftrt:SI
1295 (match_operand:SI 1 "gpc_reg_operand" "%r")
1296 (const_int 16))
1297 (ashiftrt:SI
1298 (match_operand:SI 2 "gpc_reg_operand" "r")
1299 (const_int 16)))
1300 (const_int 0)))
1301 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1302 (mult:SI (ashiftrt:SI
1303 (match_dup 1)
1304 (const_int 16))
1305 (ashiftrt:SI
1306 (match_dup 2)
1307 (const_int 16))))]
1308 "TARGET_MULHW"
1309 "mulhhw. %0, %1, %2"
1310 [(set_attr "type" "imul3")])
1312 (define_insn "*mulhhw"
1313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1314 (mult:SI (ashiftrt:SI
1315 (match_operand:SI 1 "gpc_reg_operand" "%r")
1316 (const_int 16))
1317 (ashiftrt:SI
1318 (match_operand:SI 2 "gpc_reg_operand" "r")
1319 (const_int 16))))]
1320 "TARGET_MULHW"
1321 "mulhhw %0, %1, %2"
1322 [(set_attr "type" "imul3")])
1324 (define_insn "*mulhhwuc"
1325 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1326 (compare:CC (mult:SI (lshiftrt:SI
1327 (match_operand:SI 1 "gpc_reg_operand" "%r")
1328 (const_int 16))
1329 (lshiftrt:SI
1330 (match_operand:SI 2 "gpc_reg_operand" "r")
1331 (const_int 16)))
1332 (const_int 0)))
1333 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1334 (mult:SI (lshiftrt:SI
1335 (match_dup 1)
1336 (const_int 16))
1337 (lshiftrt:SI
1338 (match_dup 2)
1339 (const_int 16))))]
1340 "TARGET_MULHW"
1341 "mulhhwu. %0, %1, %2"
1342 [(set_attr "type" "imul3")])
1344 (define_insn "*mulhhwu"
1345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1346 (mult:SI (lshiftrt:SI
1347 (match_operand:SI 1 "gpc_reg_operand" "%r")
1348 (const_int 16))
1349 (lshiftrt:SI
1350 (match_operand:SI 2 "gpc_reg_operand" "r")
1351 (const_int 16))))]
1352 "TARGET_MULHW"
1353 "mulhhwu %0, %1, %2"
1354 [(set_attr "type" "imul3")])
1356 (define_insn "*mullhwc"
1357 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1358 (compare:CC (mult:SI (sign_extend:SI
1359 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1360 (sign_extend:SI
1361 (match_operand:HI 2 "gpc_reg_operand" "r")))
1362 (const_int 0)))
1363 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1364 (mult:SI (sign_extend:SI
1365 (match_dup 1))
1366 (sign_extend:SI
1367 (match_dup 2))))]
1368 "TARGET_MULHW"
1369 "mullhw. %0, %1, %2"
1370 [(set_attr "type" "imul3")])
1372 (define_insn "*mullhw"
1373 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1374 (mult:SI (sign_extend:SI
1375 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1376 (sign_extend:SI
1377 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1378 "TARGET_MULHW"
1379 "mullhw %0, %1, %2"
1380 [(set_attr "type" "imul3")])
1382 (define_insn "*mullhwuc"
1383 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1384 (compare:CC (mult:SI (zero_extend:SI
1385 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1386 (zero_extend:SI
1387 (match_operand:HI 2 "gpc_reg_operand" "r")))
1388 (const_int 0)))
1389 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1390 (mult:SI (zero_extend:SI
1391 (match_dup 1))
1392 (zero_extend:SI
1393 (match_dup 2))))]
1394 "TARGET_MULHW"
1395 "mullhwu. %0, %1, %2"
1396 [(set_attr "type" "imul3")])
1398 (define_insn "*mullhwu"
1399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1400 (mult:SI (zero_extend:SI
1401 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1402 (zero_extend:SI
1403 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1404 "TARGET_MULHW"
1405 "mullhwu %0, %1, %2"
1406 [(set_attr "type" "imul3")])
1407 \f
1408 ;; IBM 405, 440 and 464 string-search dlmzb instruction support.
1409 (define_insn "dlmzb"
1410 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1411 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1412 (match_operand:SI 2 "gpc_reg_operand" "r")]
1413 UNSPEC_DLMZB_CR))
1414 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1415 (unspec:SI [(match_dup 1)
1416 (match_dup 2)]
1417 UNSPEC_DLMZB))]
1418 "TARGET_DLMZB"
1419 "dlmzb. %0, %1, %2")
1421 (define_expand "strlensi"
1422 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1423 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1424 (match_operand:QI 2 "const_int_operand" "")
1425 (match_operand 3 "const_int_operand" "")]
1426 UNSPEC_DLMZB_STRLEN))
1427 (clobber (match_scratch:CC 4 "=x"))]
1428 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1429 {
1430 rtx result = operands[0];
1431 rtx src = operands[1];
1432 rtx search_char = operands[2];
1433 rtx align = operands[3];
1434 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1435 rtx loop_label, end_label, mem, cr0, cond;
1436 if (search_char != const0_rtx
1437 || GET_CODE (align) != CONST_INT
1438 || INTVAL (align) < 8)
1439 FAIL;
1440 word1 = gen_reg_rtx (SImode);
1441 word2 = gen_reg_rtx (SImode);
1442 scratch_dlmzb = gen_reg_rtx (SImode);
1443 scratch_string = gen_reg_rtx (Pmode);
1444 loop_label = gen_label_rtx ();
1445 end_label = gen_label_rtx ();
1446 addr = force_reg (Pmode, XEXP (src, 0));
1447 emit_move_insn (scratch_string, addr);
1448 emit_label (loop_label);
1449 mem = change_address (src, SImode, scratch_string);
1450 emit_move_insn (word1, mem);
1451 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1452 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1453 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1454 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1455 emit_jump_insn (gen_rtx_SET (VOIDmode,
1456 pc_rtx,
1457 gen_rtx_IF_THEN_ELSE (VOIDmode,
1458 cond,
1459 gen_rtx_LABEL_REF
1460 (VOIDmode,
1461 end_label),
1462 pc_rtx)));
1463 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1464 emit_jump_insn (gen_rtx_SET (VOIDmode,
1465 pc_rtx,
1466 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1467 emit_barrier ();
1468 emit_label (end_label);
1469 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1470 emit_insn (gen_subsi3 (result, scratch_string, addr));
1471 emit_insn (gen_subsi3 (result, result, const1_rtx));
1472 DONE;
1473 })
1474 \f
1475 (define_split
1476 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1477 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1478 (const_int 0)))
1479 (set (match_operand:SI 0 "gpc_reg_operand" "")
1480 (sign_extend:SI (match_dup 1)))]
1481 "reload_completed"
1482 [(set (match_dup 0)
1483 (sign_extend:SI (match_dup 1)))
1484 (set (match_dup 2)
1485 (compare:CC (match_dup 0)
1486 (const_int 0)))]
1487 "")
1489 ;; Fixed-point arithmetic insns.
1491 (define_expand "add<mode>3"
1492 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1493 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1494 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1495 ""
1496 {
1497 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1498 {
1499 if (non_short_cint_operand (operands[2], DImode))
1500 FAIL;
1501 }
1502 else if (GET_CODE (operands[2]) == CONST_INT
1503 && ! add_operand (operands[2], <MODE>mode))
1504 {
1505 rtx tmp = ((!can_create_pseudo_p ()
1506 || rtx_equal_p (operands[0], operands[1]))
1507 ? operands[0] : gen_reg_rtx (<MODE>mode));
1509 HOST_WIDE_INT val = INTVAL (operands[2]);
1510 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1511 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1513 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1514 FAIL;
1516 /* The ordering here is important for the prolog expander.
1517 When space is allocated from the stack, adding 'low' first may
1518 produce a temporary deallocation (which would be bad). */
1519 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1520 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1521 DONE;
1522 }
1523 })
1525 ;; Discourage ai/addic because of carry but provide it in an alternative
1526 ;; allowing register zero as source.
1527 (define_insn "*add<mode>3_internal1"
1528 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1529 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1530 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1531 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1532 "@
1533 {cax|add} %0,%1,%2
1534 {cal %0,%2(%1)|addi %0,%1,%2}
1535 {ai|addic} %0,%1,%2
1536 {cau|addis} %0,%1,%v2"
1537 [(set_attr "length" "4,4,4,4")])
1539 (define_insn "addsi3_high"
1540 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1541 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1542 (high:SI (match_operand 2 "" ""))))]
1543 "TARGET_MACHO && !TARGET_64BIT"
1544 "{cau|addis} %0,%1,ha16(%2)"
1545 [(set_attr "length" "4")])
1547 (define_insn "*add<mode>3_internal2"
1548 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1549 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1550 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1551 (const_int 0)))
1552 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1553 ""
1554 "@
1555 {cax.|add.} %3,%1,%2
1556 {ai.|addic.} %3,%1,%2
1557 #
1558 #"
1559 [(set_attr "type" "fast_compare,compare,compare,compare")
1560 (set_attr "length" "4,4,8,8")])
1562 (define_split
1563 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1564 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1565 (match_operand:GPR 2 "reg_or_short_operand" ""))
1566 (const_int 0)))
1567 (clobber (match_scratch:GPR 3 ""))]
1568 "reload_completed"
1569 [(set (match_dup 3)
1570 (plus:GPR (match_dup 1)
1571 (match_dup 2)))
1572 (set (match_dup 0)
1573 (compare:CC (match_dup 3)
1574 (const_int 0)))]
1575 "")
1577 (define_insn "*add<mode>3_internal3"
1578 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1579 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1580 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1581 (const_int 0)))
1582 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1583 (plus:P (match_dup 1)
1584 (match_dup 2)))]
1585 ""
1586 "@
1587 {cax.|add.} %0,%1,%2
1588 {ai.|addic.} %0,%1,%2
1589 #
1590 #"
1591 [(set_attr "type" "fast_compare,compare,compare,compare")
1592 (set_attr "length" "4,4,8,8")])
1594 (define_split
1595 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1596 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1597 (match_operand:P 2 "reg_or_short_operand" ""))
1598 (const_int 0)))
1599 (set (match_operand:P 0 "gpc_reg_operand" "")
1600 (plus:P (match_dup 1) (match_dup 2)))]
1601 "reload_completed"
1602 [(set (match_dup 0)
1603 (plus:P (match_dup 1)
1604 (match_dup 2)))
1605 (set (match_dup 3)
1606 (compare:CC (match_dup 0)
1607 (const_int 0)))]
1608 "")
1610 ;; Split an add that we can't do in one insn into two insns, each of which
1611 ;; does one 16-bit part. This is used by combine. Note that the low-order
1612 ;; add should be last in case the result gets used in an address.
1614 (define_split
1615 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1616 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1617 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1618 ""
1619 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1620 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1621 {
1622 HOST_WIDE_INT val = INTVAL (operands[2]);
1623 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1624 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1626 operands[4] = GEN_INT (low);
1627 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1628 operands[3] = GEN_INT (rest);
1629 else if (can_create_pseudo_p ())
1630 {
1631 operands[3] = gen_reg_rtx (DImode);
1632 emit_move_insn (operands[3], operands[2]);
1633 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1634 DONE;
1635 }
1636 else
1637 FAIL;
1638 })
1640 (define_insn "one_cmpl<mode>2"
1641 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1642 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1643 ""
1644 "nor %0,%1,%1")
1646 (define_insn ""
1647 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1648 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1649 (const_int 0)))
1650 (clobber (match_scratch:P 2 "=r,r"))]
1651 ""
1652 "@
1653 nor. %2,%1,%1
1654 #"
1655 [(set_attr "type" "compare")
1656 (set_attr "length" "4,8")])
1658 (define_split
1659 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1660 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1661 (const_int 0)))
1662 (clobber (match_scratch:P 2 ""))]
1663 "reload_completed"
1664 [(set (match_dup 2)
1665 (not:P (match_dup 1)))
1666 (set (match_dup 0)
1667 (compare:CC (match_dup 2)
1668 (const_int 0)))]
1669 "")
1671 (define_insn ""
1672 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1673 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1674 (const_int 0)))
1675 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1676 (not:P (match_dup 1)))]
1677 ""
1678 "@
1679 nor. %0,%1,%1
1680 #"
1681 [(set_attr "type" "compare")
1682 (set_attr "length" "4,8")])
1684 (define_split
1685 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1686 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1687 (const_int 0)))
1688 (set (match_operand:P 0 "gpc_reg_operand" "")
1689 (not:P (match_dup 1)))]
1690 "reload_completed"
1691 [(set (match_dup 0)
1692 (not:P (match_dup 1)))
1693 (set (match_dup 2)
1694 (compare:CC (match_dup 0)
1695 (const_int 0)))]
1696 "")
1698 (define_insn ""
1699 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1700 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1701 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1702 "! TARGET_POWERPC"
1703 "{sf%I1|subf%I1c} %0,%2,%1")
1705 (define_insn ""
1706 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1707 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1708 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1709 "TARGET_POWERPC"
1710 "@
1711 subf %0,%2,%1
1712 subfic %0,%2,%1")
1714 (define_insn ""
1715 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1716 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1717 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1718 (const_int 0)))
1719 (clobber (match_scratch:SI 3 "=r,r"))]
1720 "! TARGET_POWERPC"
1721 "@
1722 {sf.|subfc.} %3,%2,%1
1723 #"
1724 [(set_attr "type" "compare")
1725 (set_attr "length" "4,8")])
1727 (define_insn ""
1728 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1729 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1730 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1731 (const_int 0)))
1732 (clobber (match_scratch:P 3 "=r,r"))]
1733 "TARGET_POWERPC"
1734 "@
1735 subf. %3,%2,%1
1736 #"
1737 [(set_attr "type" "fast_compare")
1738 (set_attr "length" "4,8")])
1740 (define_split
1741 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1742 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1743 (match_operand:P 2 "gpc_reg_operand" ""))
1744 (const_int 0)))
1745 (clobber (match_scratch:P 3 ""))]
1746 "reload_completed"
1747 [(set (match_dup 3)
1748 (minus:P (match_dup 1)
1749 (match_dup 2)))
1750 (set (match_dup 0)
1751 (compare:CC (match_dup 3)
1752 (const_int 0)))]
1753 "")
1755 (define_insn ""
1756 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1757 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1758 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1759 (const_int 0)))
1760 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1761 (minus:SI (match_dup 1) (match_dup 2)))]
1762 "! TARGET_POWERPC"
1763 "@
1764 {sf.|subfc.} %0,%2,%1
1765 #"
1766 [(set_attr "type" "compare")
1767 (set_attr "length" "4,8")])
1769 (define_insn ""
1770 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1771 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1772 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1773 (const_int 0)))
1774 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1775 (minus:P (match_dup 1)
1776 (match_dup 2)))]
1777 "TARGET_POWERPC"
1778 "@
1779 subf. %0,%2,%1
1780 #"
1781 [(set_attr "type" "fast_compare")
1782 (set_attr "length" "4,8")])
1784 (define_split
1785 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1786 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1787 (match_operand:P 2 "gpc_reg_operand" ""))
1788 (const_int 0)))
1789 (set (match_operand:P 0 "gpc_reg_operand" "")
1790 (minus:P (match_dup 1)
1791 (match_dup 2)))]
1792 "reload_completed"
1793 [(set (match_dup 0)
1794 (minus:P (match_dup 1)
1795 (match_dup 2)))
1796 (set (match_dup 3)
1797 (compare:CC (match_dup 0)
1798 (const_int 0)))]
1799 "")
1801 (define_expand "sub<mode>3"
1802 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1803 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1804 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1805 ""
1806 "
1807 {
1808 if (GET_CODE (operands[2]) == CONST_INT)
1809 {
1810 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1811 negate_rtx (<MODE>mode, operands[2])));
1812 DONE;
1813 }
1814 }")
1816 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1817 ;; instruction and some auxiliary computations. Then we just have a single
1818 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1819 ;; combine.
1821 (define_expand "sminsi3"
1822 [(set (match_dup 3)
1823 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1824 (match_operand:SI 2 "reg_or_short_operand" ""))
1825 (const_int 0)
1826 (minus:SI (match_dup 2) (match_dup 1))))
1827 (set (match_operand:SI 0 "gpc_reg_operand" "")
1828 (minus:SI (match_dup 2) (match_dup 3)))]
1829 "TARGET_POWER || TARGET_ISEL"
1830 "
1831 {
1832 if (TARGET_ISEL)
1833 {
1834 operands[2] = force_reg (SImode, operands[2]);
1835 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1836 DONE;
1837 }
1839 operands[3] = gen_reg_rtx (SImode);
1840 }")
1842 (define_split
1843 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1844 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1845 (match_operand:SI 2 "reg_or_short_operand" "")))
1846 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1847 "TARGET_POWER"
1848 [(set (match_dup 3)
1849 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1850 (const_int 0)
1851 (minus:SI (match_dup 2) (match_dup 1))))
1852 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1853 "")
1855 (define_expand "smaxsi3"
1856 [(set (match_dup 3)
1857 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1858 (match_operand:SI 2 "reg_or_short_operand" ""))
1859 (const_int 0)
1860 (minus:SI (match_dup 2) (match_dup 1))))
1861 (set (match_operand:SI 0 "gpc_reg_operand" "")
1862 (plus:SI (match_dup 3) (match_dup 1)))]
1863 "TARGET_POWER || TARGET_ISEL"
1864 "
1865 {
1866 if (TARGET_ISEL)
1867 {
1868 operands[2] = force_reg (SImode, operands[2]);
1869 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1870 DONE;
1871 }
1872 operands[3] = gen_reg_rtx (SImode);
1873 }")
1875 (define_split
1876 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1877 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1878 (match_operand:SI 2 "reg_or_short_operand" "")))
1879 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1880 "TARGET_POWER"
1881 [(set (match_dup 3)
1882 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1883 (const_int 0)
1884 (minus:SI (match_dup 2) (match_dup 1))))
1885 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1886 "")
1888 (define_expand "uminsi3"
1889 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1890 (match_dup 5)))
1891 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1892 (match_dup 5)))
1893 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1894 (const_int 0)
1895 (minus:SI (match_dup 4) (match_dup 3))))
1896 (set (match_operand:SI 0 "gpc_reg_operand" "")
1897 (minus:SI (match_dup 2) (match_dup 3)))]
1898 "TARGET_POWER || TARGET_ISEL"
1899 "
1900 {
1901 if (TARGET_ISEL)
1902 {
1903 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1904 DONE;
1905 }
1906 operands[3] = gen_reg_rtx (SImode);
1907 operands[4] = gen_reg_rtx (SImode);
1908 operands[5] = GEN_INT (-2147483647 - 1);
1909 }")
1911 (define_expand "umaxsi3"
1912 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1913 (match_dup 5)))
1914 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1915 (match_dup 5)))
1916 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1917 (const_int 0)
1918 (minus:SI (match_dup 4) (match_dup 3))))
1919 (set (match_operand:SI 0 "gpc_reg_operand" "")
1920 (plus:SI (match_dup 3) (match_dup 1)))]
1921 "TARGET_POWER || TARGET_ISEL"
1922 "
1923 {
1924 if (TARGET_ISEL)
1925 {
1926 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1927 DONE;
1928 }
1929 operands[3] = gen_reg_rtx (SImode);
1930 operands[4] = gen_reg_rtx (SImode);
1931 operands[5] = GEN_INT (-2147483647 - 1);
1932 }")
1934 (define_insn ""
1935 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1936 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1937 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1938 (const_int 0)
1939 (minus:SI (match_dup 2) (match_dup 1))))]
1940 "TARGET_POWER"
1941 "doz%I2 %0,%1,%2")
1943 (define_insn ""
1944 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1945 (compare:CC
1946 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1947 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1948 (const_int 0)
1949 (minus:SI (match_dup 2) (match_dup 1)))
1950 (const_int 0)))
1951 (clobber (match_scratch:SI 3 "=r,r"))]
1952 "TARGET_POWER"
1953 "@
1954 doz%I2. %3,%1,%2
1955 #"
1956 [(set_attr "type" "delayed_compare")
1957 (set_attr "length" "4,8")])
1959 (define_split
1960 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1961 (compare:CC
1962 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1963 (match_operand:SI 2 "reg_or_short_operand" ""))
1964 (const_int 0)
1965 (minus:SI (match_dup 2) (match_dup 1)))
1966 (const_int 0)))
1967 (clobber (match_scratch:SI 3 ""))]
1968 "TARGET_POWER && reload_completed"
1969 [(set (match_dup 3)
1970 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1971 (const_int 0)
1972 (minus:SI (match_dup 2) (match_dup 1))))
1973 (set (match_dup 0)
1974 (compare:CC (match_dup 3)
1975 (const_int 0)))]
1976 "")
1978 (define_insn ""
1979 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1980 (compare:CC
1981 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1982 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1983 (const_int 0)
1984 (minus:SI (match_dup 2) (match_dup 1)))
1985 (const_int 0)))
1986 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1987 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1988 (const_int 0)
1989 (minus:SI (match_dup 2) (match_dup 1))))]
1990 "TARGET_POWER"
1991 "@
1992 doz%I2. %0,%1,%2
1993 #"
1994 [(set_attr "type" "delayed_compare")
1995 (set_attr "length" "4,8")])
1997 (define_split
1998 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1999 (compare:CC
2000 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2001 (match_operand:SI 2 "reg_or_short_operand" ""))
2002 (const_int 0)
2003 (minus:SI (match_dup 2) (match_dup 1)))
2004 (const_int 0)))
2005 (set (match_operand:SI 0 "gpc_reg_operand" "")
2006 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2007 (const_int 0)
2008 (minus:SI (match_dup 2) (match_dup 1))))]
2009 "TARGET_POWER && reload_completed"
2010 [(set (match_dup 0)
2011 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2012 (const_int 0)
2013 (minus:SI (match_dup 2) (match_dup 1))))
2014 (set (match_dup 3)
2015 (compare:CC (match_dup 0)
2016 (const_int 0)))]
2017 "")
2019 ;; We don't need abs with condition code because such comparisons should
2020 ;; never be done.
2021 (define_expand "abssi2"
2022 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2023 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2024 ""
2025 "
2026 {
2027 if (TARGET_ISEL)
2028 {
2029 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2030 DONE;
2031 }
2032 else if (! TARGET_POWER)
2033 {
2034 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2035 DONE;
2036 }
2037 }")
2039 (define_insn "*abssi2_power"
2040 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2041 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2042 "TARGET_POWER"
2043 "abs %0,%1")
2045 (define_insn_and_split "abssi2_isel"
2046 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2047 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2048 (clobber (match_scratch:SI 2 "=&b"))
2049 (clobber (match_scratch:CC 3 "=y"))]
2050 "TARGET_ISEL"
2051 "#"
2052 "&& reload_completed"
2053 [(set (match_dup 2) (neg:SI (match_dup 1)))
2054 (set (match_dup 3)
2055 (compare:CC (match_dup 1)
2056 (const_int 0)))
2057 (set (match_dup 0)
2058 (if_then_else:SI (ge (match_dup 3)
2059 (const_int 0))
2060 (match_dup 1)
2061 (match_dup 2)))]
2062 "")
2064 (define_insn_and_split "abssi2_nopower"
2065 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2066 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2067 (clobber (match_scratch:SI 2 "=&r,&r"))]
2068 "! TARGET_POWER && ! TARGET_ISEL"
2069 "#"
2070 "&& reload_completed"
2071 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2072 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2073 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2074 "")
2076 (define_insn "*nabs_power"
2077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2078 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2079 "TARGET_POWER"
2080 "nabs %0,%1")
2082 (define_insn_and_split "*nabs_nopower"
2083 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2084 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2085 (clobber (match_scratch:SI 2 "=&r,&r"))]
2086 "! TARGET_POWER"
2087 "#"
2088 "&& reload_completed"
2089 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2090 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2091 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2092 "")
2094 (define_expand "neg<mode>2"
2095 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2096 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2097 ""
2098 "")
2100 (define_insn "*neg<mode>2_internal"
2101 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2102 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2103 ""
2104 "neg %0,%1")
2106 (define_insn ""
2107 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2108 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2109 (const_int 0)))
2110 (clobber (match_scratch:P 2 "=r,r"))]
2111 ""
2112 "@
2113 neg. %2,%1
2114 #"
2115 [(set_attr "type" "fast_compare")
2116 (set_attr "length" "4,8")])
2118 (define_split
2119 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2120 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2121 (const_int 0)))
2122 (clobber (match_scratch:P 2 ""))]
2123 "reload_completed"
2124 [(set (match_dup 2)
2125 (neg:P (match_dup 1)))
2126 (set (match_dup 0)
2127 (compare:CC (match_dup 2)
2128 (const_int 0)))]
2129 "")
2131 (define_insn ""
2132 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2133 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2134 (const_int 0)))
2135 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2136 (neg:P (match_dup 1)))]
2137 ""
2138 "@
2139 neg. %0,%1
2140 #"
2141 [(set_attr "type" "fast_compare")
2142 (set_attr "length" "4,8")])
2144 (define_split
2145 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2146 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2147 (const_int 0)))
2148 (set (match_operand:P 0 "gpc_reg_operand" "")
2149 (neg:P (match_dup 1)))]
2150 "reload_completed"
2151 [(set (match_dup 0)
2152 (neg:P (match_dup 1)))
2153 (set (match_dup 2)
2154 (compare:CC (match_dup 0)
2155 (const_int 0)))]
2156 "")
2158 (define_insn "clz<mode>2"
2159 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2160 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2161 ""
2162 "{cntlz|cntlz<wd>} %0,%1"
2163 [(set_attr "type" "cntlz")])
2165 (define_expand "ctz<mode>2"
2166 [(set (match_dup 2)
2167 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2168 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2169 (match_dup 2)))
2170 (clobber (scratch:CC))])
2171 (set (match_dup 4) (clz:GPR (match_dup 3)))
2172 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2173 (minus:GPR (match_dup 5) (match_dup 4)))]
2174 ""
2175 {
2176 operands[2] = gen_reg_rtx (<MODE>mode);
2177 operands[3] = gen_reg_rtx (<MODE>mode);
2178 operands[4] = gen_reg_rtx (<MODE>mode);
2179 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2180 })
2182 (define_expand "ffs<mode>2"
2183 [(set (match_dup 2)
2184 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2185 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2186 (match_dup 2)))
2187 (clobber (scratch:CC))])
2188 (set (match_dup 4) (clz:GPR (match_dup 3)))
2189 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2190 (minus:GPR (match_dup 5) (match_dup 4)))]
2191 ""
2192 {
2193 operands[2] = gen_reg_rtx (<MODE>mode);
2194 operands[3] = gen_reg_rtx (<MODE>mode);
2195 operands[4] = gen_reg_rtx (<MODE>mode);
2196 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2197 })
2199 (define_insn "popcntb<mode>2"
2200 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2201 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2202 UNSPEC_POPCNTB))]
2203 "TARGET_POPCNTB"
2204 "popcntb %0,%1")
2206 (define_expand "popcount<mode>2"
2207 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2208 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2209 "TARGET_POPCNTB"
2210 {
2211 rs6000_emit_popcount (operands[0], operands[1]);
2212 DONE;
2213 })
2215 (define_expand "parity<mode>2"
2216 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2217 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2218 "TARGET_POPCNTB"
2219 {
2220 rs6000_emit_parity (operands[0], operands[1]);
2221 DONE;
2222 })
2224 (define_insn "bswapsi2"
2225 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2226 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2227 ""
2228 "@
2229 {lbrx|lwbrx} %0,%y1
2230 {stbrx|stwbrx} %1,%y0
2231 #"
2232 [(set_attr "length" "4,4,12")])
2234 (define_split
2235 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2236 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2237 "reload_completed"
2238 [(set (match_dup 0)
2239 (rotate:SI (match_dup 1) (const_int 8)))
2240 (set (zero_extract:SI (match_dup 0)
2241 (const_int 8)
2242 (const_int 0))
2243 (match_dup 1))
2244 (set (zero_extract:SI (match_dup 0)
2245 (const_int 8)
2246 (const_int 16))
2247 (rotate:SI (match_dup 1)
2248 (const_int 16)))]
2249 "")
2251 (define_expand "mulsi3"
2252 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2253 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2254 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2255 ""
2256 "
2257 {
2258 if (TARGET_POWER)
2259 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2260 else
2261 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2262 DONE;
2263 }")
2265 (define_insn "mulsi3_mq"
2266 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2267 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2268 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2269 (clobber (match_scratch:SI 3 "=q,q"))]
2270 "TARGET_POWER"
2271 "@
2272 {muls|mullw} %0,%1,%2
2273 {muli|mulli} %0,%1,%2"
2274 [(set (attr "type")
2275 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2276 (const_string "imul3")
2277 (match_operand:SI 2 "short_cint_operand" "")
2278 (const_string "imul2")]
2279 (const_string "imul")))])
2281 (define_insn "mulsi3_no_mq"
2282 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2283 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2284 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2285 "! TARGET_POWER"
2286 "@
2287 {muls|mullw} %0,%1,%2
2288 {muli|mulli} %0,%1,%2"
2289 [(set (attr "type")
2290 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2291 (const_string "imul3")
2292 (match_operand:SI 2 "short_cint_operand" "")
2293 (const_string "imul2")]
2294 (const_string "imul")))])
2296 (define_insn "*mulsi3_mq_internal1"
2297 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2298 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2299 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2300 (const_int 0)))
2301 (clobber (match_scratch:SI 3 "=r,r"))
2302 (clobber (match_scratch:SI 4 "=q,q"))]
2303 "TARGET_POWER"
2304 "@
2305 {muls.|mullw.} %3,%1,%2
2306 #"
2307 [(set_attr "type" "imul_compare")
2308 (set_attr "length" "4,8")])
2310 (define_split
2311 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2312 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2313 (match_operand:SI 2 "gpc_reg_operand" ""))
2314 (const_int 0)))
2315 (clobber (match_scratch:SI 3 ""))
2316 (clobber (match_scratch:SI 4 ""))]
2317 "TARGET_POWER && reload_completed"
2318 [(parallel [(set (match_dup 3)
2319 (mult:SI (match_dup 1) (match_dup 2)))
2320 (clobber (match_dup 4))])
2321 (set (match_dup 0)
2322 (compare:CC (match_dup 3)
2323 (const_int 0)))]
2324 "")
2326 (define_insn "*mulsi3_no_mq_internal1"
2327 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2328 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2329 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2330 (const_int 0)))
2331 (clobber (match_scratch:SI 3 "=r,r"))]
2332 "! TARGET_POWER"
2333 "@
2334 {muls.|mullw.} %3,%1,%2
2335 #"
2336 [(set_attr "type" "imul_compare")
2337 (set_attr "length" "4,8")])
2339 (define_split
2340 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2341 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2342 (match_operand:SI 2 "gpc_reg_operand" ""))
2343 (const_int 0)))
2344 (clobber (match_scratch:SI 3 ""))]
2345 "! TARGET_POWER && reload_completed"
2346 [(set (match_dup 3)
2347 (mult:SI (match_dup 1) (match_dup 2)))
2348 (set (match_dup 0)
2349 (compare:CC (match_dup 3)
2350 (const_int 0)))]
2351 "")
2353 (define_insn "*mulsi3_mq_internal2"
2354 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2355 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2356 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2357 (const_int 0)))
2358 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2359 (mult:SI (match_dup 1) (match_dup 2)))
2360 (clobber (match_scratch:SI 4 "=q,q"))]
2361 "TARGET_POWER"
2362 "@
2363 {muls.|mullw.} %0,%1,%2
2364 #"
2365 [(set_attr "type" "imul_compare")
2366 (set_attr "length" "4,8")])
2368 (define_split
2369 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2370 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2371 (match_operand:SI 2 "gpc_reg_operand" ""))
2372 (const_int 0)))
2373 (set (match_operand:SI 0 "gpc_reg_operand" "")
2374 (mult:SI (match_dup 1) (match_dup 2)))
2375 (clobber (match_scratch:SI 4 ""))]
2376 "TARGET_POWER && reload_completed"
2377 [(parallel [(set (match_dup 0)
2378 (mult:SI (match_dup 1) (match_dup 2)))
2379 (clobber (match_dup 4))])
2380 (set (match_dup 3)
2381 (compare:CC (match_dup 0)
2382 (const_int 0)))]
2383 "")
2385 (define_insn "*mulsi3_no_mq_internal2"
2386 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2387 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2388 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2389 (const_int 0)))
2390 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2391 (mult:SI (match_dup 1) (match_dup 2)))]
2392 "! TARGET_POWER"
2393 "@
2394 {muls.|mullw.} %0,%1,%2
2395 #"
2396 [(set_attr "type" "imul_compare")
2397 (set_attr "length" "4,8")])
2399 (define_split
2400 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2401 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2402 (match_operand:SI 2 "gpc_reg_operand" ""))
2403 (const_int 0)))
2404 (set (match_operand:SI 0 "gpc_reg_operand" "")
2405 (mult:SI (match_dup 1) (match_dup 2)))]
2406 "! TARGET_POWER && reload_completed"
2407 [(set (match_dup 0)
2408 (mult:SI (match_dup 1) (match_dup 2)))
2409 (set (match_dup 3)
2410 (compare:CC (match_dup 0)
2411 (const_int 0)))]
2412 "")
2414 ;; Operand 1 is divided by operand 2; quotient goes to operand
2415 ;; 0 and remainder to operand 3.
2416 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2418 (define_expand "divmodsi4"
2419 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2420 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2421 (match_operand:SI 2 "gpc_reg_operand" "")))
2422 (set (match_operand:SI 3 "register_operand" "")
2423 (mod:SI (match_dup 1) (match_dup 2)))])]
2424 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2425 "
2426 {
2427 if (! TARGET_POWER && ! TARGET_POWERPC)
2428 {
2429 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2430 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2431 emit_insn (gen_divss_call ());
2432 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2433 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2434 DONE;
2435 }
2436 }")
2438 (define_insn "*divmodsi4_internal"
2439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2440 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2441 (match_operand:SI 2 "gpc_reg_operand" "r")))
2442 (set (match_operand:SI 3 "register_operand" "=q")
2443 (mod:SI (match_dup 1) (match_dup 2)))]
2444 "TARGET_POWER"
2445 "divs %0,%1,%2"
2446 [(set_attr "type" "idiv")])
2448 (define_expand "udiv<mode>3"
2449 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2450 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2451 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2452 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2453 "
2454 {
2455 if (! TARGET_POWER && ! TARGET_POWERPC)
2456 {
2457 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2458 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2459 emit_insn (gen_quous_call ());
2460 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2461 DONE;
2462 }
2463 else if (TARGET_POWER)
2464 {
2465 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2466 DONE;
2467 }
2468 }")
2470 (define_insn "udivsi3_mq"
2471 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2472 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2473 (match_operand:SI 2 "gpc_reg_operand" "r")))
2474 (clobber (match_scratch:SI 3 "=q"))]
2475 "TARGET_POWERPC && TARGET_POWER"
2476 "divwu %0,%1,%2"
2477 [(set_attr "type" "idiv")])
2479 (define_insn "*udivsi3_no_mq"
2480 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2481 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2482 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2483 "TARGET_POWERPC && ! TARGET_POWER"
2484 "div<wd>u %0,%1,%2"
2485 [(set (attr "type")
2486 (cond [(match_operand:SI 0 "" "")
2487 (const_string "idiv")]
2488 (const_string "ldiv")))])
2491 ;; For powers of two we can do srai/aze for divide and then adjust for
2492 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2493 ;; used; for PowerPC, force operands into register and do a normal divide;
2494 ;; for AIX common-mode, use quoss call on register operands.
2495 (define_expand "div<mode>3"
2496 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2497 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2498 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2499 ""
2500 "
2501 {
2502 if (GET_CODE (operands[2]) == CONST_INT
2503 && INTVAL (operands[2]) > 0
2504 && exact_log2 (INTVAL (operands[2])) >= 0)
2505 ;
2506 else if (TARGET_POWERPC)
2507 {
2508 operands[2] = force_reg (<MODE>mode, operands[2]);
2509 if (TARGET_POWER)
2510 {
2511 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2512 DONE;
2513 }
2514 }
2515 else if (TARGET_POWER)
2516 FAIL;
2517 else
2518 {
2519 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2520 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2521 emit_insn (gen_quoss_call ());
2522 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2523 DONE;
2524 }
2525 }")
2527 (define_insn "divsi3_mq"
2528 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2529 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2530 (match_operand:SI 2 "gpc_reg_operand" "r")))
2531 (clobber (match_scratch:SI 3 "=q"))]
2532 "TARGET_POWERPC && TARGET_POWER"
2533 "divw %0,%1,%2"
2534 [(set_attr "type" "idiv")])
2536 (define_insn "*div<mode>3_no_mq"
2537 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2538 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2539 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2540 "TARGET_POWERPC && ! TARGET_POWER"
2541 "div<wd> %0,%1,%2"
2542 [(set (attr "type")
2543 (cond [(match_operand:SI 0 "" "")
2544 (const_string "idiv")]
2545 (const_string "ldiv")))])
2547 (define_expand "mod<mode>3"
2548 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2549 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2550 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2551 ""
2552 "
2553 {
2554 int i;
2555 rtx temp1;
2556 rtx temp2;
2558 if (GET_CODE (operands[2]) != CONST_INT
2559 || INTVAL (operands[2]) <= 0
2560 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2561 FAIL;
2563 temp1 = gen_reg_rtx (<MODE>mode);
2564 temp2 = gen_reg_rtx (<MODE>mode);
2566 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2567 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2568 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2569 DONE;
2570 }")
2572 (define_insn ""
2573 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2574 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2575 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2576 ""
2577 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2578 [(set_attr "type" "two")
2579 (set_attr "length" "8")])
2581 (define_insn ""
2582 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2583 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2584 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2585 (const_int 0)))
2586 (clobber (match_scratch:P 3 "=r,r"))]
2587 ""
2588 "@
2589 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2590 #"
2591 [(set_attr "type" "compare")
2592 (set_attr "length" "8,12")])
2594 (define_split
2595 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2596 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2597 (match_operand:GPR 2 "exact_log2_cint_operand"
2598 ""))
2599 (const_int 0)))
2600 (clobber (match_scratch:GPR 3 ""))]
2601 "reload_completed"
2602 [(set (match_dup 3)
2603 (div:<MODE> (match_dup 1) (match_dup 2)))
2604 (set (match_dup 0)
2605 (compare:CC (match_dup 3)
2606 (const_int 0)))]
2607 "")
2609 (define_insn ""
2610 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2611 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2612 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2613 (const_int 0)))
2614 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2615 (div:P (match_dup 1) (match_dup 2)))]
2616 ""
2617 "@
2618 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2619 #"
2620 [(set_attr "type" "compare")
2621 (set_attr "length" "8,12")])
2623 (define_split
2624 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2625 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2626 (match_operand:GPR 2 "exact_log2_cint_operand"
2627 ""))
2628 (const_int 0)))
2629 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2630 (div:GPR (match_dup 1) (match_dup 2)))]
2631 "reload_completed"
2632 [(set (match_dup 0)
2633 (div:<MODE> (match_dup 1) (match_dup 2)))
2634 (set (match_dup 3)
2635 (compare:CC (match_dup 0)
2636 (const_int 0)))]
2637 "")
2639 (define_insn ""
2640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2641 (udiv:SI
2642 (plus:DI (ashift:DI
2643 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2644 (const_int 32))
2645 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2646 (match_operand:SI 3 "gpc_reg_operand" "r")))
2647 (set (match_operand:SI 2 "register_operand" "=*q")
2648 (umod:SI
2649 (plus:DI (ashift:DI
2650 (zero_extend:DI (match_dup 1)) (const_int 32))
2651 (zero_extend:DI (match_dup 4)))
2652 (match_dup 3)))]
2653 "TARGET_POWER"
2654 "div %0,%1,%3"
2655 [(set_attr "type" "idiv")])
2657 ;; To do unsigned divide we handle the cases of the divisor looking like a
2658 ;; negative number. If it is a constant that is less than 2**31, we don't
2659 ;; have to worry about the branches. So make a few subroutines here.
2660 ;;
2661 ;; First comes the normal case.
2662 (define_expand "udivmodsi4_normal"
2663 [(set (match_dup 4) (const_int 0))
2664 (parallel [(set (match_operand:SI 0 "" "")
2665 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2666 (const_int 32))
2667 (zero_extend:DI (match_operand:SI 1 "" "")))
2668 (match_operand:SI 2 "" "")))
2669 (set (match_operand:SI 3 "" "")
2670 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2671 (const_int 32))
2672 (zero_extend:DI (match_dup 1)))
2673 (match_dup 2)))])]
2674 "TARGET_POWER"
2675 "
2676 { operands[4] = gen_reg_rtx (SImode); }")
2678 ;; This handles the branches.
2679 (define_expand "udivmodsi4_tests"
2680 [(set (match_operand:SI 0 "" "") (const_int 0))
2681 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2682 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2683 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2684 (label_ref (match_operand:SI 4 "" "")) (pc)))
2685 (set (match_dup 0) (const_int 1))
2686 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2687 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2688 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2689 (label_ref (match_dup 4)) (pc)))]
2690 "TARGET_POWER"
2691 "
2692 { operands[5] = gen_reg_rtx (CCUNSmode);
2693 operands[6] = gen_reg_rtx (CCmode);
2694 }")
2696 (define_expand "udivmodsi4"
2697 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2698 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2699 (match_operand:SI 2 "reg_or_cint_operand" "")))
2700 (set (match_operand:SI 3 "gpc_reg_operand" "")
2701 (umod:SI (match_dup 1) (match_dup 2)))])]
2702 ""
2703 "
2704 {
2705 rtx label = 0;
2707 if (! TARGET_POWER)
2708 {
2709 if (! TARGET_POWERPC)
2710 {
2711 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2712 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2713 emit_insn (gen_divus_call ());
2714 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2715 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2716 DONE;
2717 }
2718 else
2719 FAIL;
2720 }
2722 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2723 {
2724 operands[2] = force_reg (SImode, operands[2]);
2725 label = gen_label_rtx ();
2726 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2727 operands[3], label));
2728 }
2729 else
2730 operands[2] = force_reg (SImode, operands[2]);
2732 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2733 operands[3]));
2734 if (label)
2735 emit_label (label);
2737 DONE;
2738 }")
2740 ;; AIX architecture-independent common-mode multiply (DImode),
2741 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2742 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2743 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2744 ;; assumed unused if generating common-mode, so ignore.
2745 (define_insn "mulh_call"
2746 [(set (reg:SI 3)
2747 (truncate:SI
2748 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2749 (sign_extend:DI (reg:SI 4)))
2750 (const_int 32))))
2751 (clobber (reg:SI LR_REGNO))]
2752 "! TARGET_POWER && ! TARGET_POWERPC"
2753 "bla __mulh"
2754 [(set_attr "type" "imul")])
2756 (define_insn "mull_call"
2757 [(set (reg:DI 3)
2758 (mult:DI (sign_extend:DI (reg:SI 3))
2759 (sign_extend:DI (reg:SI 4))))
2760 (clobber (reg:SI LR_REGNO))
2761 (clobber (reg:SI 0))]
2762 "! TARGET_POWER && ! TARGET_POWERPC"
2763 "bla __mull"
2764 [(set_attr "type" "imul")])
2766 (define_insn "divss_call"
2767 [(set (reg:SI 3)
2768 (div:SI (reg:SI 3) (reg:SI 4)))
2769 (set (reg:SI 4)
2770 (mod:SI (reg:SI 3) (reg:SI 4)))
2771 (clobber (reg:SI LR_REGNO))
2772 (clobber (reg:SI 0))]
2773 "! TARGET_POWER && ! TARGET_POWERPC"
2774 "bla __divss"
2775 [(set_attr "type" "idiv")])
2777 (define_insn "divus_call"
2778 [(set (reg:SI 3)
2779 (udiv:SI (reg:SI 3) (reg:SI 4)))
2780 (set (reg:SI 4)
2781 (umod:SI (reg:SI 3) (reg:SI 4)))
2782 (clobber (reg:SI LR_REGNO))
2783 (clobber (reg:SI 0))
2784 (clobber (match_scratch:CC 0 "=x"))
2785 (clobber (reg:CC CR1_REGNO))]
2786 "! TARGET_POWER && ! TARGET_POWERPC"
2787 "bla __divus"
2788 [(set_attr "type" "idiv")])
2790 (define_insn "quoss_call"
2791 [(set (reg:SI 3)
2792 (div:SI (reg:SI 3) (reg:SI 4)))
2793 (clobber (reg:SI LR_REGNO))]
2794 "! TARGET_POWER && ! TARGET_POWERPC"
2795 "bla __quoss"
2796 [(set_attr "type" "idiv")])
2798 (define_insn "quous_call"
2799 [(set (reg:SI 3)
2800 (udiv:SI (reg:SI 3) (reg:SI 4)))
2801 (clobber (reg:SI LR_REGNO))
2802 (clobber (reg:SI 0))
2803 (clobber (match_scratch:CC 0 "=x"))
2804 (clobber (reg:CC CR1_REGNO))]
2805 "! TARGET_POWER && ! TARGET_POWERPC"
2806 "bla __quous"
2807 [(set_attr "type" "idiv")])
2808 \f
2809 ;; Logical instructions
2810 ;; The logical instructions are mostly combined by using match_operator,
2811 ;; but the plain AND insns are somewhat different because there is no
2812 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2813 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2815 (define_insn "andsi3"
2816 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2817 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2818 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2819 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2820 ""
2821 "@
2822 and %0,%1,%2
2823 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2824 {andil.|andi.} %0,%1,%b2
2825 {andiu.|andis.} %0,%1,%u2"
2826 [(set_attr "type" "*,*,compare,compare")])
2828 ;; Note to set cr's other than cr0 we do the and immediate and then
2829 ;; the test again -- this avoids a mfcr which on the higher end
2830 ;; machines causes an execution serialization
2832 (define_insn "*andsi3_internal2"
2833 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2834 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2835 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2836 (const_int 0)))
2837 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2838 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2839 "TARGET_32BIT"
2840 "@
2841 and. %3,%1,%2
2842 {andil.|andi.} %3,%1,%b2
2843 {andiu.|andis.} %3,%1,%u2
2844 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2845 #
2846 #
2847 #
2848 #"
2849 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2850 (set_attr "length" "4,4,4,4,8,8,8,8")])
2852 (define_insn "*andsi3_internal3"
2853 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2854 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2855 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2856 (const_int 0)))
2857 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2858 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2859 "TARGET_64BIT"
2860 "@
2861 #
2862 {andil.|andi.} %3,%1,%b2
2863 {andiu.|andis.} %3,%1,%u2
2864 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2865 #
2866 #
2867 #
2868 #"
2869 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2870 (set_attr "length" "8,4,4,4,8,8,8,8")])
2872 (define_split
2873 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2874 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2875 (match_operand:GPR 2 "and_operand" ""))
2876 (const_int 0)))
2877 (clobber (match_scratch:GPR 3 ""))
2878 (clobber (match_scratch:CC 4 ""))]
2879 "reload_completed"
2880 [(parallel [(set (match_dup 3)
2881 (and:<MODE> (match_dup 1)
2882 (match_dup 2)))
2883 (clobber (match_dup 4))])
2884 (set (match_dup 0)
2885 (compare:CC (match_dup 3)
2886 (const_int 0)))]
2887 "")
2889 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2890 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2892 (define_split
2893 [(set (match_operand:CC 0 "cc_reg_operand" "")
2894 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2895 (match_operand:SI 2 "gpc_reg_operand" ""))
2896 (const_int 0)))
2897 (clobber (match_scratch:SI 3 ""))
2898 (clobber (match_scratch:CC 4 ""))]
2899 "TARGET_POWERPC64 && reload_completed"
2900 [(parallel [(set (match_dup 3)
2901 (and:SI (match_dup 1)
2902 (match_dup 2)))
2903 (clobber (match_dup 4))])
2904 (set (match_dup 0)
2905 (compare:CC (match_dup 3)
2906 (const_int 0)))]
2907 "")
2909 (define_insn "*andsi3_internal4"
2910 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2911 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2912 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2913 (const_int 0)))
2914 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2915 (and:SI (match_dup 1)
2916 (match_dup 2)))
2917 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2918 "TARGET_32BIT"
2919 "@
2920 and. %0,%1,%2
2921 {andil.|andi.} %0,%1,%b2
2922 {andiu.|andis.} %0,%1,%u2
2923 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2924 #
2925 #
2926 #
2927 #"
2928 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2929 (set_attr "length" "4,4,4,4,8,8,8,8")])
2931 (define_insn "*andsi3_internal5"
2932 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2933 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2934 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2935 (const_int 0)))
2936 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2937 (and:SI (match_dup 1)
2938 (match_dup 2)))
2939 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2940 "TARGET_64BIT"
2941 "@
2942 #
2943 {andil.|andi.} %0,%1,%b2
2944 {andiu.|andis.} %0,%1,%u2
2945 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2946 #
2947 #
2948 #
2949 #"
2950 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2951 (set_attr "length" "8,4,4,4,8,8,8,8")])
2953 (define_split
2954 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2955 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2956 (match_operand:SI 2 "and_operand" ""))
2957 (const_int 0)))
2958 (set (match_operand:SI 0 "gpc_reg_operand" "")
2959 (and:SI (match_dup 1)
2960 (match_dup 2)))
2961 (clobber (match_scratch:CC 4 ""))]
2962 "reload_completed"
2963 [(parallel [(set (match_dup 0)
2964 (and:SI (match_dup 1)
2965 (match_dup 2)))
2966 (clobber (match_dup 4))])
2967 (set (match_dup 3)
2968 (compare:CC (match_dup 0)
2969 (const_int 0)))]
2970 "")
2972 (define_split
2973 [(set (match_operand:CC 3 "cc_reg_operand" "")
2974 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2975 (match_operand:SI 2 "gpc_reg_operand" ""))
2976 (const_int 0)))
2977 (set (match_operand:SI 0 "gpc_reg_operand" "")
2978 (and:SI (match_dup 1)
2979 (match_dup 2)))
2980 (clobber (match_scratch:CC 4 ""))]
2981 "TARGET_POWERPC64 && reload_completed"
2982 [(parallel [(set (match_dup 0)
2983 (and:SI (match_dup 1)
2984 (match_dup 2)))
2985 (clobber (match_dup 4))])
2986 (set (match_dup 3)
2987 (compare:CC (match_dup 0)
2988 (const_int 0)))]
2989 "")
2991 ;; Handle the PowerPC64 rlwinm corner case
2993 (define_insn_and_split "*andsi3_internal6"
2994 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2995 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2996 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2997 "TARGET_POWERPC64"
2998 "#"
2999 "TARGET_POWERPC64"
3000 [(set (match_dup 0)
3001 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3002 (match_dup 4)))
3003 (set (match_dup 0)
3004 (rotate:SI (match_dup 0) (match_dup 5)))]
3005 "
3006 {
3007 int mb = extract_MB (operands[2]);
3008 int me = extract_ME (operands[2]);
3009 operands[3] = GEN_INT (me + 1);
3010 operands[5] = GEN_INT (32 - (me + 1));
3011 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3012 }"
3013 [(set_attr "length" "8")])
3015 (define_expand "iorsi3"
3016 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3017 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3018 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3019 ""
3020 "
3021 {
3022 if (GET_CODE (operands[2]) == CONST_INT
3023 && ! logical_operand (operands[2], SImode))
3024 {
3025 HOST_WIDE_INT value = INTVAL (operands[2]);
3026 rtx tmp = ((!can_create_pseudo_p ()
3027 || rtx_equal_p (operands[0], operands[1]))
3028 ? operands[0] : gen_reg_rtx (SImode));
3030 emit_insn (gen_iorsi3 (tmp, operands[1],
3031 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3032 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3033 DONE;
3034 }
3035 }")
3037 (define_expand "xorsi3"
3038 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3039 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3040 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3041 ""
3042 "
3043 {
3044 if (GET_CODE (operands[2]) == CONST_INT
3045 && ! logical_operand (operands[2], SImode))
3046 {
3047 HOST_WIDE_INT value = INTVAL (operands[2]);
3048 rtx tmp = ((!can_create_pseudo_p ()
3049 || rtx_equal_p (operands[0], operands[1]))
3050 ? operands[0] : gen_reg_rtx (SImode));
3052 emit_insn (gen_xorsi3 (tmp, operands[1],
3053 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3054 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3055 DONE;
3056 }
3057 }")
3059 (define_insn "*boolsi3_internal1"
3060 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3061 (match_operator:SI 3 "boolean_or_operator"
3062 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3063 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3064 ""
3065 "@
3066 %q3 %0,%1,%2
3067 {%q3il|%q3i} %0,%1,%b2
3068 {%q3iu|%q3is} %0,%1,%u2")
3070 (define_insn "*boolsi3_internal2"
3071 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3072 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3073 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3074 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3075 (const_int 0)))
3076 (clobber (match_scratch:SI 3 "=r,r"))]
3077 "TARGET_32BIT"
3078 "@
3079 %q4. %3,%1,%2
3080 #"
3081 [(set_attr "type" "compare")
3082 (set_attr "length" "4,8")])
3084 (define_split
3085 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3086 (compare:CC (match_operator:SI 4 "boolean_operator"
3087 [(match_operand:SI 1 "gpc_reg_operand" "")
3088 (match_operand:SI 2 "gpc_reg_operand" "")])
3089 (const_int 0)))
3090 (clobber (match_scratch:SI 3 ""))]
3091 "TARGET_32BIT && reload_completed"
3092 [(set (match_dup 3) (match_dup 4))
3093 (set (match_dup 0)
3094 (compare:CC (match_dup 3)
3095 (const_int 0)))]
3096 "")
3098 (define_insn "*boolsi3_internal3"
3099 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3100 (compare:CC (match_operator:SI 4 "boolean_operator"
3101 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3102 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3103 (const_int 0)))
3104 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3105 (match_dup 4))]
3106 "TARGET_32BIT"
3107 "@
3108 %q4. %0,%1,%2
3109 #"
3110 [(set_attr "type" "compare")
3111 (set_attr "length" "4,8")])
3113 (define_split
3114 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3115 (compare:CC (match_operator:SI 4 "boolean_operator"
3116 [(match_operand:SI 1 "gpc_reg_operand" "")
3117 (match_operand:SI 2 "gpc_reg_operand" "")])
3118 (const_int 0)))
3119 (set (match_operand:SI 0 "gpc_reg_operand" "")
3120 (match_dup 4))]
3121 "TARGET_32BIT && reload_completed"
3122 [(set (match_dup 0) (match_dup 4))
3123 (set (match_dup 3)
3124 (compare:CC (match_dup 0)
3125 (const_int 0)))]
3126 "")
3128 ;; Split a logical operation that we can't do in one insn into two insns,
3129 ;; each of which does one 16-bit part. This is used by combine.
3131 (define_split
3132 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3133 (match_operator:SI 3 "boolean_or_operator"
3134 [(match_operand:SI 1 "gpc_reg_operand" "")
3135 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3136 ""
3137 [(set (match_dup 0) (match_dup 4))
3138 (set (match_dup 0) (match_dup 5))]
3139 "
3140 {
3141 rtx i;
3142 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3143 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3144 operands[1], i);
3145 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3146 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3147 operands[0], i);
3148 }")
3150 (define_insn "*boolcsi3_internal1"
3151 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3152 (match_operator:SI 3 "boolean_operator"
3153 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3154 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3155 ""
3156 "%q3 %0,%2,%1")
3158 (define_insn "*boolcsi3_internal2"
3159 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3160 (compare:CC (match_operator:SI 4 "boolean_operator"
3161 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3162 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3163 (const_int 0)))
3164 (clobber (match_scratch:SI 3 "=r,r"))]
3165 "TARGET_32BIT"
3166 "@
3167 %q4. %3,%2,%1
3168 #"
3169 [(set_attr "type" "compare")
3170 (set_attr "length" "4,8")])
3172 (define_split
3173 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3174 (compare:CC (match_operator:SI 4 "boolean_operator"
3175 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3176 (match_operand:SI 2 "gpc_reg_operand" "")])
3177 (const_int 0)))
3178 (clobber (match_scratch:SI 3 ""))]
3179 "TARGET_32BIT && reload_completed"
3180 [(set (match_dup 3) (match_dup 4))
3181 (set (match_dup 0)
3182 (compare:CC (match_dup 3)
3183 (const_int 0)))]
3184 "")
3186 (define_insn "*boolcsi3_internal3"
3187 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3188 (compare:CC (match_operator:SI 4 "boolean_operator"
3189 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3190 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3191 (const_int 0)))
3192 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3193 (match_dup 4))]
3194 "TARGET_32BIT"
3195 "@
3196 %q4. %0,%2,%1
3197 #"
3198 [(set_attr "type" "compare")
3199 (set_attr "length" "4,8")])
3201 (define_split
3202 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3203 (compare:CC (match_operator:SI 4 "boolean_operator"
3204 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3205 (match_operand:SI 2 "gpc_reg_operand" "")])
3206 (const_int 0)))
3207 (set (match_operand:SI 0 "gpc_reg_operand" "")
3208 (match_dup 4))]
3209 "TARGET_32BIT && reload_completed"
3210 [(set (match_dup 0) (match_dup 4))
3211 (set (match_dup 3)
3212 (compare:CC (match_dup 0)
3213 (const_int 0)))]
3214 "")
3216 (define_insn "*boolccsi3_internal1"
3217 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3218 (match_operator:SI 3 "boolean_operator"
3219 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3220 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3221 ""
3222 "%q3 %0,%1,%2")
3224 (define_insn "*boolccsi3_internal2"
3225 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3226 (compare:CC (match_operator:SI 4 "boolean_operator"
3227 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3228 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3229 (const_int 0)))
3230 (clobber (match_scratch:SI 3 "=r,r"))]
3231 "TARGET_32BIT"
3232 "@
3233 %q4. %3,%1,%2
3234 #"
3235 [(set_attr "type" "compare")
3236 (set_attr "length" "4,8")])
3238 (define_split
3239 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3240 (compare:CC (match_operator:SI 4 "boolean_operator"
3241 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3242 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3243 (const_int 0)))
3244 (clobber (match_scratch:SI 3 ""))]
3245 "TARGET_32BIT && reload_completed"
3246 [(set (match_dup 3) (match_dup 4))
3247 (set (match_dup 0)
3248 (compare:CC (match_dup 3)
3249 (const_int 0)))]
3250 "")
3252 (define_insn "*boolccsi3_internal3"
3253 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3254 (compare:CC (match_operator:SI 4 "boolean_operator"
3255 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3256 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3257 (const_int 0)))
3258 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3259 (match_dup 4))]
3260 "TARGET_32BIT"
3261 "@
3262 %q4. %0,%1,%2
3263 #"
3264 [(set_attr "type" "compare")
3265 (set_attr "length" "4,8")])
3267 (define_split
3268 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3269 (compare:CC (match_operator:SI 4 "boolean_operator"
3270 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3271 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3272 (const_int 0)))
3273 (set (match_operand:SI 0 "gpc_reg_operand" "")
3274 (match_dup 4))]
3275 "TARGET_32BIT && reload_completed"
3276 [(set (match_dup 0) (match_dup 4))
3277 (set (match_dup 3)
3278 (compare:CC (match_dup 0)
3279 (const_int 0)))]
3280 "")
3282 ;; maskir insn. We need four forms because things might be in arbitrary
3283 ;; orders. Don't define forms that only set CR fields because these
3284 ;; would modify an input register.
3286 (define_insn "*maskir_internal1"
3287 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3288 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3289 (match_operand:SI 1 "gpc_reg_operand" "0"))
3290 (and:SI (match_dup 2)
3291 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3292 "TARGET_POWER"
3293 "maskir %0,%3,%2")
3295 (define_insn "*maskir_internal2"
3296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3297 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3298 (match_operand:SI 1 "gpc_reg_operand" "0"))
3299 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3300 (match_dup 2))))]
3301 "TARGET_POWER"
3302 "maskir %0,%3,%2")
3304 (define_insn "*maskir_internal3"
3305 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3306 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3307 (match_operand:SI 3 "gpc_reg_operand" "r"))
3308 (and:SI (not:SI (match_dup 2))
3309 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3310 "TARGET_POWER"
3311 "maskir %0,%3,%2")
3313 (define_insn "*maskir_internal4"
3314 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3315 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3316 (match_operand:SI 2 "gpc_reg_operand" "r"))
3317 (and:SI (not:SI (match_dup 2))
3318 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3319 "TARGET_POWER"
3320 "maskir %0,%3,%2")
3322 (define_insn "*maskir_internal5"
3323 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3324 (compare:CC
3325 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3326 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3327 (and:SI (match_dup 2)
3328 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3329 (const_int 0)))
3330 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3331 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3332 (and:SI (match_dup 2) (match_dup 3))))]
3333 "TARGET_POWER"
3334 "@
3335 maskir. %0,%3,%2
3336 #"
3337 [(set_attr "type" "compare")
3338 (set_attr "length" "4,8")])
3340 (define_split
3341 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3342 (compare:CC
3343 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3344 (match_operand:SI 1 "gpc_reg_operand" ""))
3345 (and:SI (match_dup 2)
3346 (match_operand:SI 3 "gpc_reg_operand" "")))
3347 (const_int 0)))
3348 (set (match_operand:SI 0 "gpc_reg_operand" "")
3349 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3350 (and:SI (match_dup 2) (match_dup 3))))]
3351 "TARGET_POWER && reload_completed"
3352 [(set (match_dup 0)
3353 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3354 (and:SI (match_dup 2) (match_dup 3))))
3355 (set (match_dup 4)
3356 (compare:CC (match_dup 0)
3357 (const_int 0)))]
3358 "")
3360 (define_insn "*maskir_internal6"
3361 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3362 (compare:CC
3363 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3364 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3365 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3366 (match_dup 2)))
3367 (const_int 0)))
3368 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3369 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3370 (and:SI (match_dup 3) (match_dup 2))))]
3371 "TARGET_POWER"
3372 "@
3373 maskir. %0,%3,%2
3374 #"
3375 [(set_attr "type" "compare")
3376 (set_attr "length" "4,8")])
3378 (define_split
3379 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3380 (compare:CC
3381 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3382 (match_operand:SI 1 "gpc_reg_operand" ""))
3383 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3384 (match_dup 2)))
3385 (const_int 0)))
3386 (set (match_operand:SI 0 "gpc_reg_operand" "")
3387 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3388 (and:SI (match_dup 3) (match_dup 2))))]
3389 "TARGET_POWER && reload_completed"
3390 [(set (match_dup 0)
3391 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3392 (and:SI (match_dup 3) (match_dup 2))))
3393 (set (match_dup 4)
3394 (compare:CC (match_dup 0)
3395 (const_int 0)))]
3396 "")
3398 (define_insn "*maskir_internal7"
3399 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3400 (compare:CC
3401 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3402 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3403 (and:SI (not:SI (match_dup 2))
3404 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3405 (const_int 0)))
3406 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3407 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3408 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3409 "TARGET_POWER"
3410 "@
3411 maskir. %0,%3,%2
3412 #"
3413 [(set_attr "type" "compare")
3414 (set_attr "length" "4,8")])
3416 (define_split
3417 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3418 (compare:CC
3419 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3420 (match_operand:SI 3 "gpc_reg_operand" ""))
3421 (and:SI (not:SI (match_dup 2))
3422 (match_operand:SI 1 "gpc_reg_operand" "")))
3423 (const_int 0)))
3424 (set (match_operand:SI 0 "gpc_reg_operand" "")
3425 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3426 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3427 "TARGET_POWER && reload_completed"
3428 [(set (match_dup 0)
3429 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3430 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3431 (set (match_dup 4)
3432 (compare:CC (match_dup 0)
3433 (const_int 0)))]
3434 "")
3436 (define_insn "*maskir_internal8"
3437 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3438 (compare:CC
3439 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3440 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3441 (and:SI (not:SI (match_dup 2))
3442 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3443 (const_int 0)))
3444 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3445 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3446 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3447 "TARGET_POWER"
3448 "@
3449 maskir. %0,%3,%2
3450 #"
3451 [(set_attr "type" "compare")
3452 (set_attr "length" "4,8")])
3454 (define_split
3455 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3456 (compare:CC
3457 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3458 (match_operand:SI 2 "gpc_reg_operand" ""))
3459 (and:SI (not:SI (match_dup 2))
3460 (match_operand:SI 1 "gpc_reg_operand" "")))
3461 (const_int 0)))
3462 (set (match_operand:SI 0 "gpc_reg_operand" "")
3463 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3464 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3465 "TARGET_POWER && reload_completed"
3466 [(set (match_dup 0)
3467 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3468 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3469 (set (match_dup 4)
3470 (compare:CC (match_dup 0)
3471 (const_int 0)))]
3472 "")
3473 \f
3474 ;; Rotate and shift insns, in all their variants. These support shifts,
3475 ;; field inserts and extracts, and various combinations thereof.
3476 (define_expand "insv"
3477 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3478 (match_operand:SI 1 "const_int_operand" "")
3479 (match_operand:SI 2 "const_int_operand" ""))
3480 (match_operand 3 "gpc_reg_operand" ""))]
3481 ""
3482 "
3483 {
3484 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3485 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3486 compiler if the address of the structure is taken later. Likewise, do
3487 not handle invalid E500 subregs. */
3488 if (GET_CODE (operands[0]) == SUBREG
3489 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3490 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3491 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3492 FAIL;
3494 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3495 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3496 else
3497 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3498 DONE;
3499 }")
3501 (define_insn "insvsi"
3502 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3503 (match_operand:SI 1 "const_int_operand" "i")
3504 (match_operand:SI 2 "const_int_operand" "i"))
3505 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3506 ""
3507 "*
3508 {
3509 int start = INTVAL (operands[2]) & 31;
3510 int size = INTVAL (operands[1]) & 31;
3512 operands[4] = GEN_INT (32 - start - size);
3513 operands[1] = GEN_INT (start + size - 1);
3514 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3515 }"
3516 [(set_attr "type" "insert_word")])
3518 (define_insn "*insvsi_internal1"
3519 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3520 (match_operand:SI 1 "const_int_operand" "i")
3521 (match_operand:SI 2 "const_int_operand" "i"))
3522 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3523 (match_operand:SI 4 "const_int_operand" "i")))]
3524 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3525 "*
3526 {
3527 int shift = INTVAL (operands[4]) & 31;
3528 int start = INTVAL (operands[2]) & 31;
3529 int size = INTVAL (operands[1]) & 31;
3531 operands[4] = GEN_INT (shift - start - size);
3532 operands[1] = GEN_INT (start + size - 1);
3533 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3534 }"
3535 [(set_attr "type" "insert_word")])
3537 (define_insn "*insvsi_internal2"
3538 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3539 (match_operand:SI 1 "const_int_operand" "i")
3540 (match_operand:SI 2 "const_int_operand" "i"))
3541 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3542 (match_operand:SI 4 "const_int_operand" "i")))]
3543 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3544 "*
3545 {
3546 int shift = INTVAL (operands[4]) & 31;
3547 int start = INTVAL (operands[2]) & 31;
3548 int size = INTVAL (operands[1]) & 31;
3550 operands[4] = GEN_INT (32 - shift - start - size);
3551 operands[1] = GEN_INT (start + size - 1);
3552 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3553 }"
3554 [(set_attr "type" "insert_word")])
3556 (define_insn "*insvsi_internal3"
3557 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3558 (match_operand:SI 1 "const_int_operand" "i")
3559 (match_operand:SI 2 "const_int_operand" "i"))
3560 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3561 (match_operand:SI 4 "const_int_operand" "i")))]
3562 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3563 "*
3564 {
3565 int shift = INTVAL (operands[4]) & 31;
3566 int start = INTVAL (operands[2]) & 31;
3567 int size = INTVAL (operands[1]) & 31;
3569 operands[4] = GEN_INT (32 - shift - start - size);
3570 operands[1] = GEN_INT (start + size - 1);
3571 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3572 }"
3573 [(set_attr "type" "insert_word")])
3575 (define_insn "*insvsi_internal4"
3576 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3577 (match_operand:SI 1 "const_int_operand" "i")
3578 (match_operand:SI 2 "const_int_operand" "i"))
3579 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3580 (match_operand:SI 4 "const_int_operand" "i")
3581 (match_operand:SI 5 "const_int_operand" "i")))]
3582 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3583 "*
3584 {
3585 int extract_start = INTVAL (operands[5]) & 31;
3586 int extract_size = INTVAL (operands[4]) & 31;
3587 int insert_start = INTVAL (operands[2]) & 31;
3588 int insert_size = INTVAL (operands[1]) & 31;
3590 /* Align extract field with insert field */
3591 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3592 operands[1] = GEN_INT (insert_start + insert_size - 1);
3593 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3594 }"
3595 [(set_attr "type" "insert_word")])
3597 ;; combine patterns for rlwimi
3598 (define_insn "*insvsi_internal5"
3599 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3600 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3601 (match_operand:SI 1 "mask_operand" "i"))
3602 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3603 (match_operand:SI 2 "const_int_operand" "i"))
3604 (match_operand:SI 5 "mask_operand" "i"))))]
3605 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3606 "*
3607 {
3608 int me = extract_ME(operands[5]);
3609 int mb = extract_MB(operands[5]);
3610 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3611 operands[2] = GEN_INT(mb);
3612 operands[1] = GEN_INT(me);
3613 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3614 }"
3615 [(set_attr "type" "insert_word")])
3617 (define_insn "*insvsi_internal6"
3618 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3619 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3620 (match_operand:SI 2 "const_int_operand" "i"))
3621 (match_operand:SI 5 "mask_operand" "i"))
3622 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3623 (match_operand:SI 1 "mask_operand" "i"))))]
3624 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3625 "*
3626 {
3627 int me = extract_ME(operands[5]);
3628 int mb = extract_MB(operands[5]);
3629 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3630 operands[2] = GEN_INT(mb);
3631 operands[1] = GEN_INT(me);
3632 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3633 }"
3634 [(set_attr "type" "insert_word")])
3636 (define_insn "insvdi"
3637 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3638 (match_operand:SI 1 "const_int_operand" "i")
3639 (match_operand:SI 2 "const_int_operand" "i"))
3640 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3641 "TARGET_POWERPC64"
3642 "*
3643 {
3644 int start = INTVAL (operands[2]) & 63;
3645 int size = INTVAL (operands[1]) & 63;
3647 operands[1] = GEN_INT (64 - start - size);
3648 return \"rldimi %0,%3,%H1,%H2\";
3649 }"
3650 [(set_attr "type" "insert_dword")])
3652 (define_insn "*insvdi_internal2"
3653 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3654 (match_operand:SI 1 "const_int_operand" "i")
3655 (match_operand:SI 2 "const_int_operand" "i"))
3656 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3657 (match_operand:SI 4 "const_int_operand" "i")))]
3658 "TARGET_POWERPC64
3659 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3660 "*
3661 {
3662 int shift = INTVAL (operands[4]) & 63;
3663 int start = (INTVAL (operands[2]) & 63) - 32;
3664 int size = INTVAL (operands[1]) & 63;
3666 operands[4] = GEN_INT (64 - shift - start - size);
3667 operands[2] = GEN_INT (start);
3668 operands[1] = GEN_INT (start + size - 1);
3669 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3670 }")
3672 (define_insn "*insvdi_internal3"
3673 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3674 (match_operand:SI 1 "const_int_operand" "i")
3675 (match_operand:SI 2 "const_int_operand" "i"))
3676 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3677 (match_operand:SI 4 "const_int_operand" "i")))]
3678 "TARGET_POWERPC64
3679 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3680 "*
3681 {
3682 int shift = INTVAL (operands[4]) & 63;
3683 int start = (INTVAL (operands[2]) & 63) - 32;
3684 int size = INTVAL (operands[1]) & 63;
3686 operands[4] = GEN_INT (64 - shift - start - size);
3687 operands[2] = GEN_INT (start);
3688 operands[1] = GEN_INT (start + size - 1);
3689 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3690 }")
3692 (define_expand "extzv"
3693 [(set (match_operand 0 "gpc_reg_operand" "")
3694 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3695 (match_operand:SI 2 "const_int_operand" "")
3696 (match_operand:SI 3 "const_int_operand" "")))]
3697 ""
3698 "
3699 {
3700 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3701 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3702 compiler if the address of the structure is taken later. */
3703 if (GET_CODE (operands[0]) == SUBREG
3704 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3705 FAIL;
3707 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3708 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3709 else
3710 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3711 DONE;
3712 }")
3714 (define_insn "extzvsi"
3715 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3716 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3717 (match_operand:SI 2 "const_int_operand" "i")
3718 (match_operand:SI 3 "const_int_operand" "i")))]
3719 ""
3720 "*
3721 {
3722 int start = INTVAL (operands[3]) & 31;
3723 int size = INTVAL (operands[2]) & 31;
3725 if (start + size >= 32)
3726 operands[3] = const0_rtx;
3727 else
3728 operands[3] = GEN_INT (start + size);
3729 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3730 }")
3732 (define_insn "*extzvsi_internal1"
3733 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3734 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3735 (match_operand:SI 2 "const_int_operand" "i,i")
3736 (match_operand:SI 3 "const_int_operand" "i,i"))
3737 (const_int 0)))
3738 (clobber (match_scratch:SI 4 "=r,r"))]
3739 ""
3740 "*
3741 {
3742 int start = INTVAL (operands[3]) & 31;
3743 int size = INTVAL (operands[2]) & 31;
3745 /* Force split for non-cc0 compare. */
3746 if (which_alternative == 1)
3747 return \"#\";
3749 /* If the bit-field being tested fits in the upper or lower half of a
3750 word, it is possible to use andiu. or andil. to test it. This is
3751 useful because the condition register set-use delay is smaller for
3752 andi[ul]. than for rlinm. This doesn't work when the starting bit
3753 position is 0 because the LT and GT bits may be set wrong. */
3755 if ((start > 0 && start + size <= 16) || start >= 16)
3756 {
3757 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3758 - (1 << (16 - (start & 15) - size))));
3759 if (start < 16)
3760 return \"{andiu.|andis.} %4,%1,%3\";
3761 else
3762 return \"{andil.|andi.} %4,%1,%3\";
3763 }
3765 if (start + size >= 32)
3766 operands[3] = const0_rtx;
3767 else
3768 operands[3] = GEN_INT (start + size);
3769 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3770 }"
3771 [(set_attr "type" "delayed_compare")
3772 (set_attr "length" "4,8")])
3774 (define_split
3775 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3776 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3777 (match_operand:SI 2 "const_int_operand" "")
3778 (match_operand:SI 3 "const_int_operand" ""))
3779 (const_int 0)))
3780 (clobber (match_scratch:SI 4 ""))]
3781 "reload_completed"
3782 [(set (match_dup 4)
3783 (zero_extract:SI (match_dup 1) (match_dup 2)
3784 (match_dup 3)))
3785 (set (match_dup 0)
3786 (compare:CC (match_dup 4)
3787 (const_int 0)))]
3788 "")
3790 (define_insn "*extzvsi_internal2"
3791 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3792 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3793 (match_operand:SI 2 "const_int_operand" "i,i")
3794 (match_operand:SI 3 "const_int_operand" "i,i"))
3795 (const_int 0)))
3796 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3797 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3798 ""
3799 "*
3800 {
3801 int start = INTVAL (operands[3]) & 31;
3802 int size = INTVAL (operands[2]) & 31;
3804 /* Force split for non-cc0 compare. */
3805 if (which_alternative == 1)
3806 return \"#\";
3808 /* Since we are using the output value, we can't ignore any need for
3809 a shift. The bit-field must end at the LSB. */
3810 if (start >= 16 && start + size == 32)
3811 {
3812 operands[3] = GEN_INT ((1 << size) - 1);
3813 return \"{andil.|andi.} %0,%1,%3\";
3814 }
3816 if (start + size >= 32)
3817 operands[3] = const0_rtx;
3818 else
3819 operands[3] = GEN_INT (start + size);
3820 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3821 }"
3822 [(set_attr "type" "delayed_compare")
3823 (set_attr "length" "4,8")])
3825 (define_split
3826 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3827 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3828 (match_operand:SI 2 "const_int_operand" "")
3829 (match_operand:SI 3 "const_int_operand" ""))
3830 (const_int 0)))
3831 (set (match_operand:SI 0 "gpc_reg_operand" "")
3832 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3833 "reload_completed"
3834 [(set (match_dup 0)
3835 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3836 (set (match_dup 4)
3837 (compare:CC (match_dup 0)
3838 (const_int 0)))]
3839 "")
3841 (define_insn "extzvdi"
3842 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3843 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3844 (match_operand:SI 2 "const_int_operand" "i")
3845 (match_operand:SI 3 "const_int_operand" "i")))]
3846 "TARGET_POWERPC64"
3847 "*
3848 {
3849 int start = INTVAL (operands[3]) & 63;
3850 int size = INTVAL (operands[2]) & 63;
3852 if (start + size >= 64)
3853 operands[3] = const0_rtx;
3854 else
3855 operands[3] = GEN_INT (start + size);
3856 operands[2] = GEN_INT (64 - size);
3857 return \"rldicl %0,%1,%3,%2\";
3858 }")
3860 (define_insn "*extzvdi_internal1"
3861 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3862 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3863 (match_operand:SI 2 "const_int_operand" "i")
3864 (match_operand:SI 3 "const_int_operand" "i"))
3865 (const_int 0)))
3866 (clobber (match_scratch:DI 4 "=r"))]
3867 "TARGET_64BIT"
3868 "*
3869 {
3870 int start = INTVAL (operands[3]) & 63;
3871 int size = INTVAL (operands[2]) & 63;
3873 if (start + size >= 64)
3874 operands[3] = const0_rtx;
3875 else
3876 operands[3] = GEN_INT (start + size);
3877 operands[2] = GEN_INT (64 - size);
3878 return \"rldicl. %4,%1,%3,%2\";
3879 }"
3880 [(set_attr "type" "compare")])
3882 (define_insn "*extzvdi_internal2"
3883 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3884 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3885 (match_operand:SI 2 "const_int_operand" "i")
3886 (match_operand:SI 3 "const_int_operand" "i"))
3887 (const_int 0)))
3888 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3889 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3890 "TARGET_64BIT"
3891 "*
3892 {
3893 int start = INTVAL (operands[3]) & 63;
3894 int size = INTVAL (operands[2]) & 63;
3896 if (start + size >= 64)
3897 operands[3] = const0_rtx;
3898 else
3899 operands[3] = GEN_INT (start + size);
3900 operands[2] = GEN_INT (64 - size);
3901 return \"rldicl. %0,%1,%3,%2\";
3902 }"
3903 [(set_attr "type" "compare")])
3905 (define_insn "rotlsi3"
3906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3907 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3908 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3909 ""
3910 "@
3911 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3912 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3913 [(set_attr "type" "var_shift_rotate,integer")])
3915 (define_insn "*rotlsi3_internal2"
3916 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3917 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3918 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3919 (const_int 0)))
3920 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3921 ""
3922 "@
3923 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3924 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3925 #
3926 #"
3927 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3928 (set_attr "length" "4,4,8,8")])
3930 (define_split
3931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3932 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3933 (match_operand:SI 2 "reg_or_cint_operand" ""))
3934 (const_int 0)))
3935 (clobber (match_scratch:SI 3 ""))]
3936 "reload_completed"
3937 [(set (match_dup 3)
3938 (rotate:SI (match_dup 1) (match_dup 2)))
3939 (set (match_dup 0)
3940 (compare:CC (match_dup 3)
3941 (const_int 0)))]
3942 "")
3944 (define_insn "*rotlsi3_internal3"
3945 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3946 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3947 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3948 (const_int 0)))
3949 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3950 (rotate:SI (match_dup 1) (match_dup 2)))]
3951 ""
3952 "@
3953 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3954 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3955 #
3956 #"
3957 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3958 (set_attr "length" "4,4,8,8")])
3960 (define_split
3961 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3962 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3963 (match_operand:SI 2 "reg_or_cint_operand" ""))
3964 (const_int 0)))
3965 (set (match_operand:SI 0 "gpc_reg_operand" "")
3966 (rotate:SI (match_dup 1) (match_dup 2)))]
3967 "reload_completed"
3968 [(set (match_dup 0)
3969 (rotate:SI (match_dup 1) (match_dup 2)))
3970 (set (match_dup 3)
3971 (compare:CC (match_dup 0)
3972 (const_int 0)))]
3973 "")
3975 (define_insn "*rotlsi3_internal4"
3976 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3977 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3978 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3979 (match_operand:SI 3 "mask_operand" "n,n")))]
3980 ""
3981 "@
3982 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3983 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3984 [(set_attr "type" "var_shift_rotate,integer")])
3986 (define_insn "*rotlsi3_internal5"
3987 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3988 (compare:CC (and:SI
3989 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3990 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3991 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3992 (const_int 0)))
3993 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3994 ""
3995 "@
3996 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3997 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3998 #
3999 #"
4000 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4001 (set_attr "length" "4,4,8,8")])
4003 (define_split
4004 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4005 (compare:CC (and:SI
4006 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4007 (match_operand:SI 2 "reg_or_cint_operand" ""))
4008 (match_operand:SI 3 "mask_operand" ""))
4009 (const_int 0)))
4010 (clobber (match_scratch:SI 4 ""))]
4011 "reload_completed"
4012 [(set (match_dup 4)
4013 (and:SI (rotate:SI (match_dup 1)
4014 (match_dup 2))
4015 (match_dup 3)))
4016 (set (match_dup 0)
4017 (compare:CC (match_dup 4)
4018 (const_int 0)))]
4019 "")
4021 (define_insn "*rotlsi3_internal6"
4022 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4023 (compare:CC (and:SI
4024 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4025 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4026 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4027 (const_int 0)))
4028 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4029 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4030 ""
4031 "@
4032 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4033 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4034 #
4035 #"
4036 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4037 (set_attr "length" "4,4,8,8")])
4039 (define_split
4040 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4041 (compare:CC (and:SI
4042 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4043 (match_operand:SI 2 "reg_or_cint_operand" ""))
4044 (match_operand:SI 3 "mask_operand" ""))
4045 (const_int 0)))
4046 (set (match_operand:SI 0 "gpc_reg_operand" "")
4047 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4048 "reload_completed"
4049 [(set (match_dup 0)
4050 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4051 (set (match_dup 4)
4052 (compare:CC (match_dup 0)
4053 (const_int 0)))]
4054 "")
4056 (define_insn "*rotlsi3_internal7"
4057 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4058 (zero_extend:SI
4059 (subreg:QI
4060 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4061 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4062 ""
4063 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
4065 (define_insn "*rotlsi3_internal8"
4066 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4067 (compare:CC (zero_extend:SI
4068 (subreg:QI
4069 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4070 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4071 (const_int 0)))
4072 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4073 ""
4074 "@
4075 {rlnm.|rlwnm.} %3,%1,%2,0xff
4076 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4077 #
4078 #"
4079 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4080 (set_attr "length" "4,4,8,8")])
4082 (define_split
4083 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4084 (compare:CC (zero_extend:SI
4085 (subreg:QI
4086 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4087 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4088 (const_int 0)))
4089 (clobber (match_scratch:SI 3 ""))]
4090 "reload_completed"
4091 [(set (match_dup 3)
4092 (zero_extend:SI (subreg:QI
4093 (rotate:SI (match_dup 1)
4094 (match_dup 2)) 0)))
4095 (set (match_dup 0)
4096 (compare:CC (match_dup 3)
4097 (const_int 0)))]
4098 "")
4100 (define_insn "*rotlsi3_internal9"
4101 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4102 (compare:CC (zero_extend:SI
4103 (subreg:QI
4104 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4105 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4106 (const_int 0)))
4107 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4108 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4109 ""
4110 "@
4111 {rlnm.|rlwnm.} %0,%1,%2,0xff
4112 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4113 #
4114 #"
4115 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4116 (set_attr "length" "4,4,8,8")])
4118 (define_split
4119 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4120 (compare:CC (zero_extend:SI
4121 (subreg:QI
4122 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4123 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4124 (const_int 0)))
4125 (set (match_operand:SI 0 "gpc_reg_operand" "")
4126 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4127 "reload_completed"
4128 [(set (match_dup 0)
4129 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4130 (set (match_dup 3)
4131 (compare:CC (match_dup 0)
4132 (const_int 0)))]
4133 "")
4135 (define_insn "*rotlsi3_internal10"
4136 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4137 (zero_extend:SI
4138 (subreg:HI
4139 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4140 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4141 ""
4142 "@
4143 {rlnm|rlwnm} %0,%1,%2,0xffff
4144 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4145 [(set_attr "type" "var_shift_rotate,integer")])
4148 (define_insn "*rotlsi3_internal11"
4149 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4150 (compare:CC (zero_extend:SI
4151 (subreg:HI
4152 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4153 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4154 (const_int 0)))
4155 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4156 ""
4157 "@
4158 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4159 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4160 #
4161 #"
4162 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4163 (set_attr "length" "4,4,8,8")])
4165 (define_split
4166 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4167 (compare:CC (zero_extend:SI
4168 (subreg:HI
4169 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4170 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4171 (const_int 0)))
4172 (clobber (match_scratch:SI 3 ""))]
4173 "reload_completed"
4174 [(set (match_dup 3)
4175 (zero_extend:SI (subreg:HI
4176 (rotate:SI (match_dup 1)
4177 (match_dup 2)) 0)))
4178 (set (match_dup 0)
4179 (compare:CC (match_dup 3)
4180 (const_int 0)))]
4181 "")
4183 (define_insn "*rotlsi3_internal12"
4184 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4185 (compare:CC (zero_extend:SI
4186 (subreg:HI
4187 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4188 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4189 (const_int 0)))
4190 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4191 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4192 ""
4193 "@
4194 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4195 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4196 #
4197 #"
4198 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4199 (set_attr "length" "4,4,8,8")])
4201 (define_split
4202 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4203 (compare:CC (zero_extend:SI
4204 (subreg:HI
4205 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4206 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4207 (const_int 0)))
4208 (set (match_operand:SI 0 "gpc_reg_operand" "")
4209 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4210 "reload_completed"
4211 [(set (match_dup 0)
4212 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4213 (set (match_dup 3)
4214 (compare:CC (match_dup 0)
4215 (const_int 0)))]
4216 "")
4218 ;; Note that we use "sle." instead of "sl." so that we can set
4219 ;; SHIFT_COUNT_TRUNCATED.
4221 (define_expand "ashlsi3"
4222 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4223 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4224 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4225 ""
4226 "
4227 {
4228 if (TARGET_POWER)
4229 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4230 else
4231 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4232 DONE;
4233 }")
4235 (define_insn "ashlsi3_power"
4236 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4237 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4238 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4239 (clobber (match_scratch:SI 3 "=q,X"))]
4240 "TARGET_POWER"
4241 "@
4242 sle %0,%1,%2
4243 {sli|slwi} %0,%1,%h2")
4245 (define_insn "ashlsi3_no_power"
4246 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4247 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4248 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4249 "! TARGET_POWER"
4250 "@
4251 {sl|slw} %0,%1,%2
4252 {sli|slwi} %0,%1,%h2"
4253 [(set_attr "type" "var_shift_rotate,shift")])
4255 (define_insn ""
4256 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4257 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4258 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4259 (const_int 0)))
4260 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4261 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4262 "TARGET_POWER"
4263 "@
4264 sle. %3,%1,%2
4265 {sli.|slwi.} %3,%1,%h2
4266 #
4267 #"
4268 [(set_attr "type" "delayed_compare")
4269 (set_attr "length" "4,4,8,8")])
4271 (define_split
4272 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4273 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4274 (match_operand:SI 2 "reg_or_cint_operand" ""))
4275 (const_int 0)))
4276 (clobber (match_scratch:SI 3 ""))
4277 (clobber (match_scratch:SI 4 ""))]
4278 "TARGET_POWER && reload_completed"
4279 [(parallel [(set (match_dup 3)
4280 (ashift:SI (match_dup 1) (match_dup 2)))
4281 (clobber (match_dup 4))])
4282 (set (match_dup 0)
4283 (compare:CC (match_dup 3)
4284 (const_int 0)))]
4285 "")
4287 (define_insn ""
4288 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4289 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4290 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4291 (const_int 0)))
4292 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4293 "! TARGET_POWER && TARGET_32BIT"
4294 "@
4295 {sl.|slw.} %3,%1,%2
4296 {sli.|slwi.} %3,%1,%h2
4297 #
4298 #"
4299 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4300 (set_attr "length" "4,4,8,8")])
4302 (define_split
4303 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4304 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4305 (match_operand:SI 2 "reg_or_cint_operand" ""))
4306 (const_int 0)))
4307 (clobber (match_scratch:SI 3 ""))]
4308 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4309 [(set (match_dup 3)
4310 (ashift:SI (match_dup 1) (match_dup 2)))
4311 (set (match_dup 0)
4312 (compare:CC (match_dup 3)
4313 (const_int 0)))]
4314 "")
4316 (define_insn ""
4317 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4318 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4319 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4320 (const_int 0)))
4321 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4322 (ashift:SI (match_dup 1) (match_dup 2)))
4323 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4324 "TARGET_POWER"
4325 "@
4326 sle. %0,%1,%2
4327 {sli.|slwi.} %0,%1,%h2
4328 #
4329 #"
4330 [(set_attr "type" "delayed_compare")
4331 (set_attr "length" "4,4,8,8")])
4333 (define_split
4334 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4335 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4336 (match_operand:SI 2 "reg_or_cint_operand" ""))
4337 (const_int 0)))
4338 (set (match_operand:SI 0 "gpc_reg_operand" "")
4339 (ashift:SI (match_dup 1) (match_dup 2)))
4340 (clobber (match_scratch:SI 4 ""))]
4341 "TARGET_POWER && reload_completed"
4342 [(parallel [(set (match_dup 0)
4343 (ashift:SI (match_dup 1) (match_dup 2)))
4344 (clobber (match_dup 4))])
4345 (set (match_dup 3)
4346 (compare:CC (match_dup 0)
4347 (const_int 0)))]
4348 "")
4350 (define_insn ""
4351 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4352 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4353 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4354 (const_int 0)))
4355 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4356 (ashift:SI (match_dup 1) (match_dup 2)))]
4357 "! TARGET_POWER && TARGET_32BIT"
4358 "@
4359 {sl.|slw.} %0,%1,%2
4360 {sli.|slwi.} %0,%1,%h2
4361 #
4362 #"
4363 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4364 (set_attr "length" "4,4,8,8")])
4366 (define_split
4367 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4368 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4369 (match_operand:SI 2 "reg_or_cint_operand" ""))
4370 (const_int 0)))
4371 (set (match_operand:SI 0 "gpc_reg_operand" "")
4372 (ashift:SI (match_dup 1) (match_dup 2)))]
4373 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4374 [(set (match_dup 0)
4375 (ashift:SI (match_dup 1) (match_dup 2)))
4376 (set (match_dup 3)
4377 (compare:CC (match_dup 0)
4378 (const_int 0)))]
4379 "")
4381 (define_insn "rlwinm"
4382 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4383 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4384 (match_operand:SI 2 "const_int_operand" "i"))
4385 (match_operand:SI 3 "mask_operand" "n")))]
4386 "includes_lshift_p (operands[2], operands[3])"
4387 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4389 (define_insn ""
4390 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4391 (compare:CC
4392 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4393 (match_operand:SI 2 "const_int_operand" "i,i"))
4394 (match_operand:SI 3 "mask_operand" "n,n"))
4395 (const_int 0)))
4396 (clobber (match_scratch:SI 4 "=r,r"))]
4397 "includes_lshift_p (operands[2], operands[3])"
4398 "@
4399 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4400 #"
4401 [(set_attr "type" "delayed_compare")
4402 (set_attr "length" "4,8")])
4404 (define_split
4405 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4406 (compare:CC
4407 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4408 (match_operand:SI 2 "const_int_operand" ""))
4409 (match_operand:SI 3 "mask_operand" ""))
4410 (const_int 0)))
4411 (clobber (match_scratch:SI 4 ""))]
4412 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4413 [(set (match_dup 4)
4414 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4415 (match_dup 3)))
4416 (set (match_dup 0)
4417 (compare:CC (match_dup 4)
4418 (const_int 0)))]
4419 "")
4421 (define_insn ""
4422 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4423 (compare:CC
4424 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4425 (match_operand:SI 2 "const_int_operand" "i,i"))
4426 (match_operand:SI 3 "mask_operand" "n,n"))
4427 (const_int 0)))
4428 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4429 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4430 "includes_lshift_p (operands[2], operands[3])"
4431 "@
4432 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4433 #"
4434 [(set_attr "type" "delayed_compare")
4435 (set_attr "length" "4,8")])
4437 (define_split
4438 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4439 (compare:CC
4440 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4441 (match_operand:SI 2 "const_int_operand" ""))
4442 (match_operand:SI 3 "mask_operand" ""))
4443 (const_int 0)))
4444 (set (match_operand:SI 0 "gpc_reg_operand" "")
4445 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4446 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4447 [(set (match_dup 0)
4448 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4449 (set (match_dup 4)
4450 (compare:CC (match_dup 0)
4451 (const_int 0)))]
4452 "")
4454 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4455 ;; "sli x,x,0".
4456 (define_expand "lshrsi3"
4457 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4458 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4459 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4460 ""
4461 "
4462 {
4463 if (TARGET_POWER)
4464 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4465 else
4466 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4467 DONE;
4468 }")
4470 (define_insn "lshrsi3_power"
4471 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4472 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4473 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4474 (clobber (match_scratch:SI 3 "=q,X,X"))]
4475 "TARGET_POWER"
4476 "@
4477 sre %0,%1,%2
4478 mr %0,%1
4479 {s%A2i|s%A2wi} %0,%1,%h2")
4481 (define_insn "lshrsi3_no_power"
4482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4483 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4484 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4485 "! TARGET_POWER"
4486 "@
4487 mr %0,%1
4488 {sr|srw} %0,%1,%2
4489 {sri|srwi} %0,%1,%h2"
4490 [(set_attr "type" "integer,var_shift_rotate,shift")])
4492 (define_insn ""
4493 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4494 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4495 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4496 (const_int 0)))
4497 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4498 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4499 "TARGET_POWER"
4500 "@
4501 sre. %3,%1,%2
4502 mr. %1,%1
4503 {s%A2i.|s%A2wi.} %3,%1,%h2
4504 #
4505 #
4506 #"
4507 [(set_attr "type" "delayed_compare")
4508 (set_attr "length" "4,4,4,8,8,8")])
4510 (define_split
4511 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4512 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4513 (match_operand:SI 2 "reg_or_cint_operand" ""))
4514 (const_int 0)))
4515 (clobber (match_scratch:SI 3 ""))
4516 (clobber (match_scratch:SI 4 ""))]
4517 "TARGET_POWER && reload_completed"
4518 [(parallel [(set (match_dup 3)
4519 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4520 (clobber (match_dup 4))])
4521 (set (match_dup 0)
4522 (compare:CC (match_dup 3)
4523 (const_int 0)))]
4524 "")
4526 (define_insn ""
4527 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4528 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4529 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4530 (const_int 0)))
4531 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4532 "! TARGET_POWER && TARGET_32BIT"
4533 "@
4534 mr. %1,%1
4535 {sr.|srw.} %3,%1,%2
4536 {sri.|srwi.} %3,%1,%h2
4537 #
4538 #
4539 #"
4540 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4541 (set_attr "length" "4,4,4,8,8,8")])
4543 (define_split
4544 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4545 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4546 (match_operand:SI 2 "reg_or_cint_operand" ""))
4547 (const_int 0)))
4548 (clobber (match_scratch:SI 3 ""))]
4549 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4550 [(set (match_dup 3)
4551 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4552 (set (match_dup 0)
4553 (compare:CC (match_dup 3)
4554 (const_int 0)))]
4555 "")
4557 (define_insn ""
4558 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4559 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4560 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4561 (const_int 0)))
4562 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4563 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4564 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4565 "TARGET_POWER"
4566 "@
4567 sre. %0,%1,%2
4568 mr. %0,%1
4569 {s%A2i.|s%A2wi.} %0,%1,%h2
4570 #
4571 #
4572 #"
4573 [(set_attr "type" "delayed_compare")
4574 (set_attr "length" "4,4,4,8,8,8")])
4576 (define_split
4577 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4578 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4579 (match_operand:SI 2 "reg_or_cint_operand" ""))
4580 (const_int 0)))
4581 (set (match_operand:SI 0 "gpc_reg_operand" "")
4582 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4583 (clobber (match_scratch:SI 4 ""))]
4584 "TARGET_POWER && reload_completed"
4585 [(parallel [(set (match_dup 0)
4586 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4587 (clobber (match_dup 4))])
4588 (set (match_dup 3)
4589 (compare:CC (match_dup 0)
4590 (const_int 0)))]
4591 "")
4593 (define_insn ""
4594 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4595 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4596 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4597 (const_int 0)))
4598 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4599 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4600 "! TARGET_POWER && TARGET_32BIT"
4601 "@
4602 mr. %0,%1
4603 {sr.|srw.} %0,%1,%2
4604 {sri.|srwi.} %0,%1,%h2
4605 #
4606 #
4607 #"
4608 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4609 (set_attr "length" "4,4,4,8,8,8")])
4611 (define_split
4612 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4613 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4614 (match_operand:SI 2 "reg_or_cint_operand" ""))
4615 (const_int 0)))
4616 (set (match_operand:SI 0 "gpc_reg_operand" "")
4617 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4618 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4619 [(set (match_dup 0)
4620 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4621 (set (match_dup 3)
4622 (compare:CC (match_dup 0)
4623 (const_int 0)))]
4624 "")
4626 (define_insn ""
4627 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4628 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4629 (match_operand:SI 2 "const_int_operand" "i"))
4630 (match_operand:SI 3 "mask_operand" "n")))]
4631 "includes_rshift_p (operands[2], operands[3])"
4632 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4634 (define_insn ""
4635 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4636 (compare:CC
4637 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4638 (match_operand:SI 2 "const_int_operand" "i,i"))
4639 (match_operand:SI 3 "mask_operand" "n,n"))
4640 (const_int 0)))
4641 (clobber (match_scratch:SI 4 "=r,r"))]
4642 "includes_rshift_p (operands[2], operands[3])"
4643 "@
4644 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4645 #"
4646 [(set_attr "type" "delayed_compare")
4647 (set_attr "length" "4,8")])
4649 (define_split
4650 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4651 (compare:CC
4652 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4653 (match_operand:SI 2 "const_int_operand" ""))
4654 (match_operand:SI 3 "mask_operand" ""))
4655 (const_int 0)))
4656 (clobber (match_scratch:SI 4 ""))]
4657 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4658 [(set (match_dup 4)
4659 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4660 (match_dup 3)))
4661 (set (match_dup 0)
4662 (compare:CC (match_dup 4)
4663 (const_int 0)))]
4664 "")
4666 (define_insn ""
4667 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4668 (compare:CC
4669 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4670 (match_operand:SI 2 "const_int_operand" "i,i"))
4671 (match_operand:SI 3 "mask_operand" "n,n"))
4672 (const_int 0)))
4673 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4674 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4675 "includes_rshift_p (operands[2], operands[3])"
4676 "@
4677 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4678 #"
4679 [(set_attr "type" "delayed_compare")
4680 (set_attr "length" "4,8")])
4682 (define_split
4683 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4684 (compare:CC
4685 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4686 (match_operand:SI 2 "const_int_operand" ""))
4687 (match_operand:SI 3 "mask_operand" ""))
4688 (const_int 0)))
4689 (set (match_operand:SI 0 "gpc_reg_operand" "")
4690 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4691 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4692 [(set (match_dup 0)
4693 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4694 (set (match_dup 4)
4695 (compare:CC (match_dup 0)
4696 (const_int 0)))]
4697 "")
4699 (define_insn ""
4700 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4701 (zero_extend:SI
4702 (subreg:QI
4703 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4704 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4705 "includes_rshift_p (operands[2], GEN_INT (255))"
4706 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4708 (define_insn ""
4709 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4710 (compare:CC
4711 (zero_extend:SI
4712 (subreg:QI
4713 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4714 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4715 (const_int 0)))
4716 (clobber (match_scratch:SI 3 "=r,r"))]
4717 "includes_rshift_p (operands[2], GEN_INT (255))"
4718 "@
4719 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4720 #"
4721 [(set_attr "type" "delayed_compare")
4722 (set_attr "length" "4,8")])
4724 (define_split
4725 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4726 (compare:CC
4727 (zero_extend:SI
4728 (subreg:QI
4729 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4730 (match_operand:SI 2 "const_int_operand" "")) 0))
4731 (const_int 0)))
4732 (clobber (match_scratch:SI 3 ""))]
4733 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4734 [(set (match_dup 3)
4735 (zero_extend:SI (subreg:QI
4736 (lshiftrt:SI (match_dup 1)
4737 (match_dup 2)) 0)))
4738 (set (match_dup 0)
4739 (compare:CC (match_dup 3)
4740 (const_int 0)))]
4741 "")
4743 (define_insn ""
4744 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4745 (compare:CC
4746 (zero_extend:SI
4747 (subreg:QI
4748 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4749 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4750 (const_int 0)))
4751 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4752 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4753 "includes_rshift_p (operands[2], GEN_INT (255))"
4754 "@
4755 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4756 #"
4757 [(set_attr "type" "delayed_compare")
4758 (set_attr "length" "4,8")])
4760 (define_split
4761 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4762 (compare:CC
4763 (zero_extend:SI
4764 (subreg:QI
4765 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4766 (match_operand:SI 2 "const_int_operand" "")) 0))
4767 (const_int 0)))
4768 (set (match_operand:SI 0 "gpc_reg_operand" "")
4769 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4770 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4771 [(set (match_dup 0)
4772 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4773 (set (match_dup 3)
4774 (compare:CC (match_dup 0)
4775 (const_int 0)))]
4776 "")
4778 (define_insn ""
4779 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4780 (zero_extend:SI
4781 (subreg:HI
4782 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4783 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4784 "includes_rshift_p (operands[2], GEN_INT (65535))"
4785 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4787 (define_insn ""
4788 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4789 (compare:CC
4790 (zero_extend:SI
4791 (subreg:HI
4792 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4793 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4794 (const_int 0)))
4795 (clobber (match_scratch:SI 3 "=r,r"))]
4796 "includes_rshift_p (operands[2], GEN_INT (65535))"
4797 "@
4798 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4799 #"
4800 [(set_attr "type" "delayed_compare")
4801 (set_attr "length" "4,8")])
4803 (define_split
4804 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4805 (compare:CC
4806 (zero_extend:SI
4807 (subreg:HI
4808 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4809 (match_operand:SI 2 "const_int_operand" "")) 0))
4810 (const_int 0)))
4811 (clobber (match_scratch:SI 3 ""))]
4812 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4813 [(set (match_dup 3)
4814 (zero_extend:SI (subreg:HI
4815 (lshiftrt:SI (match_dup 1)
4816 (match_dup 2)) 0)))
4817 (set (match_dup 0)
4818 (compare:CC (match_dup 3)
4819 (const_int 0)))]
4820 "")
4822 (define_insn ""
4823 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4824 (compare:CC
4825 (zero_extend:SI
4826 (subreg:HI
4827 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4828 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4829 (const_int 0)))
4830 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4831 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4832 "includes_rshift_p (operands[2], GEN_INT (65535))"
4833 "@
4834 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4835 #"
4836 [(set_attr "type" "delayed_compare")
4837 (set_attr "length" "4,8")])
4839 (define_split
4840 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4841 (compare:CC
4842 (zero_extend:SI
4843 (subreg:HI
4844 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4845 (match_operand:SI 2 "const_int_operand" "")) 0))
4846 (const_int 0)))
4847 (set (match_operand:SI 0 "gpc_reg_operand" "")
4848 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4849 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4850 [(set (match_dup 0)
4851 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4852 (set (match_dup 3)
4853 (compare:CC (match_dup 0)
4854 (const_int 0)))]
4855 "")
4857 (define_insn ""
4858 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4859 (const_int 1)
4860 (match_operand:SI 1 "gpc_reg_operand" "r"))
4861 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4862 (const_int 31)))]
4863 "TARGET_POWER"
4864 "rrib %0,%1,%2")
4866 (define_insn ""
4867 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4868 (const_int 1)
4869 (match_operand:SI 1 "gpc_reg_operand" "r"))
4870 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4871 (const_int 31)))]
4872 "TARGET_POWER"
4873 "rrib %0,%1,%2")
4875 (define_insn ""
4876 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4877 (const_int 1)
4878 (match_operand:SI 1 "gpc_reg_operand" "r"))
4879 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4880 (const_int 1)
4881 (const_int 0)))]
4882 "TARGET_POWER"
4883 "rrib %0,%1,%2")
4885 (define_expand "ashrsi3"
4886 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4887 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4888 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4889 ""
4890 "
4891 {
4892 if (TARGET_POWER)
4893 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4894 else
4895 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4896 DONE;
4897 }")
4899 (define_insn "ashrsi3_power"
4900 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4901 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4902 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4903 (clobber (match_scratch:SI 3 "=q,X"))]
4904 "TARGET_POWER"
4905 "@
4906 srea %0,%1,%2
4907 {srai|srawi} %0,%1,%h2"
4908 [(set_attr "type" "shift")])
4910 (define_insn "ashrsi3_no_power"
4911 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4912 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4913 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4914 "! TARGET_POWER"
4915 "@
4916 {sra|sraw} %0,%1,%2
4917 {srai|srawi} %0,%1,%h2"
4918 [(set_attr "type" "var_shift_rotate,shift")])
4920 (define_insn ""
4921 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4922 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4923 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4924 (const_int 0)))
4925 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4926 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4927 "TARGET_POWER"
4928 "@
4929 srea. %3,%1,%2
4930 {srai.|srawi.} %3,%1,%h2
4931 #
4932 #"
4933 [(set_attr "type" "delayed_compare")
4934 (set_attr "length" "4,4,8,8")])
4936 (define_split
4937 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4938 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4939 (match_operand:SI 2 "reg_or_cint_operand" ""))
4940 (const_int 0)))
4941 (clobber (match_scratch:SI 3 ""))
4942 (clobber (match_scratch:SI 4 ""))]
4943 "TARGET_POWER && reload_completed"
4944 [(parallel [(set (match_dup 3)
4945 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4946 (clobber (match_dup 4))])
4947 (set (match_dup 0)
4948 (compare:CC (match_dup 3)
4949 (const_int 0)))]
4950 "")
4952 (define_insn ""
4953 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4954 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4955 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4956 (const_int 0)))
4957 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4958 "! TARGET_POWER"
4959 "@
4960 {sra.|sraw.} %3,%1,%2
4961 {srai.|srawi.} %3,%1,%h2
4962 #
4963 #"
4964 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4965 (set_attr "length" "4,4,8,8")])
4967 (define_split
4968 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4969 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4970 (match_operand:SI 2 "reg_or_cint_operand" ""))
4971 (const_int 0)))
4972 (clobber (match_scratch:SI 3 ""))]
4973 "! TARGET_POWER && reload_completed"
4974 [(set (match_dup 3)
4975 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4976 (set (match_dup 0)
4977 (compare:CC (match_dup 3)
4978 (const_int 0)))]
4979 "")
4981 (define_insn ""
4982 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4983 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4984 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4985 (const_int 0)))
4986 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4987 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4988 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4989 "TARGET_POWER"
4990 "@
4991 srea. %0,%1,%2
4992 {srai.|srawi.} %0,%1,%h2
4993 #
4994 #"
4995 [(set_attr "type" "delayed_compare")
4996 (set_attr "length" "4,4,8,8")])
4998 (define_split
4999 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5000 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5001 (match_operand:SI 2 "reg_or_cint_operand" ""))
5002 (const_int 0)))
5003 (set (match_operand:SI 0 "gpc_reg_operand" "")
5004 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5005 (clobber (match_scratch:SI 4 ""))]
5006 "TARGET_POWER && reload_completed"
5007 [(parallel [(set (match_dup 0)
5008 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5009 (clobber (match_dup 4))])
5010 (set (match_dup 3)
5011 (compare:CC (match_dup 0)
5012 (const_int 0)))]
5013 "")
5015 (define_insn ""
5016 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5017 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5018 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5019 (const_int 0)))
5020 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5021 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5022 "! TARGET_POWER"
5023 "@
5024 {sra.|sraw.} %0,%1,%2
5025 {srai.|srawi.} %0,%1,%h2
5026 #
5027 #"
5028 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5029 (set_attr "length" "4,4,8,8")])
5030 \f
5031 (define_split
5032 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5033 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5034 (match_operand:SI 2 "reg_or_cint_operand" ""))
5035 (const_int 0)))
5036 (set (match_operand:SI 0 "gpc_reg_operand" "")
5037 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5038 "! TARGET_POWER && reload_completed"
5039 [(set (match_dup 0)
5040 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5041 (set (match_dup 3)
5042 (compare:CC (match_dup 0)
5043 (const_int 0)))]
5044 "")
5046 ;; Floating-point insns, excluding normal data motion.
5047 ;;
5048 ;; PowerPC has a full set of single-precision floating point instructions.
5049 ;;
5050 ;; For the POWER architecture, we pretend that we have both SFmode and
5051 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5052 ;; The only conversions we will do will be when storing to memory. In that
5053 ;; case, we will use the "frsp" instruction before storing.
5054 ;;
5055 ;; Note that when we store into a single-precision memory location, we need to
5056 ;; use the frsp insn first. If the register being stored isn't dead, we
5057 ;; need a scratch register for the frsp. But this is difficult when the store
5058 ;; is done by reload. It is not incorrect to do the frsp on the register in
5059 ;; this case, we just lose precision that we would have otherwise gotten but
5060 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5062 (define_expand "extendsfdf2"
5063 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5064 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5065 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5066 "")
5068 (define_insn_and_split "*extendsfdf2_fpr"
5069 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5070 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5071 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5072 "@
5073 #
5074 fmr %0,%1
5075 lfs%U1%X1 %0,%1"
5076 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5077 [(const_int 0)]
5078 {
5079 emit_note (NOTE_INSN_DELETED);
5080 DONE;
5081 }
5082 [(set_attr "type" "fp,fp,fpload")])
5084 (define_expand "truncdfsf2"
5085 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5086 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5087 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5088 "")
5090 (define_insn "*truncdfsf2_fpr"
5091 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5092 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5093 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5094 "frsp %0,%1"
5095 [(set_attr "type" "fp")])
5097 (define_insn "aux_truncdfsf2"
5098 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5099 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5100 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5101 "frsp %0,%1"
5102 [(set_attr "type" "fp")])
5104 (define_expand "negsf2"
5105 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5106 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5107 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5108 "")
5110 (define_insn "*negsf2"
5111 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5112 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5113 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5114 "fneg %0,%1"
5115 [(set_attr "type" "fp")])
5117 (define_expand "abssf2"
5118 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5119 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5120 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5121 "")
5123 (define_insn "*abssf2"
5124 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5125 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5126 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5127 "fabs %0,%1"
5128 [(set_attr "type" "fp")])
5130 (define_insn ""
5131 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5132 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5133 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5134 "fnabs %0,%1"
5135 [(set_attr "type" "fp")])
5137 (define_expand "addsf3"
5138 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5139 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5140 (match_operand:SF 2 "gpc_reg_operand" "")))]
5141 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5142 "")
5144 (define_insn ""
5145 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5146 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5147 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5148 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5149 "fadds %0,%1,%2"
5150 [(set_attr "type" "fp")])
5152 (define_insn ""
5153 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5154 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5155 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5156 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5157 "{fa|fadd} %0,%1,%2"
5158 [(set_attr "type" "fp")])
5160 (define_expand "subsf3"
5161 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5162 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5163 (match_operand:SF 2 "gpc_reg_operand" "")))]
5164 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5165 "")
5167 (define_insn ""
5168 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5169 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5170 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5171 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5172 "fsubs %0,%1,%2"
5173 [(set_attr "type" "fp")])
5175 (define_insn ""
5176 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5177 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5178 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5179 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5180 "{fs|fsub} %0,%1,%2"
5181 [(set_attr "type" "fp")])
5183 (define_expand "mulsf3"
5184 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5185 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5186 (match_operand:SF 2 "gpc_reg_operand" "")))]
5187 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5188 "")
5190 (define_insn ""
5191 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5192 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5193 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5194 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5195 "fmuls %0,%1,%2"
5196 [(set_attr "type" "fp")])
5198 (define_insn ""
5199 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5200 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5201 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5202 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5203 "{fm|fmul} %0,%1,%2"
5204 [(set_attr "type" "dmul")])
5206 (define_expand "divsf3"
5207 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5208 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5209 (match_operand:SF 2 "gpc_reg_operand" "")))]
5210 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5211 "")
5213 (define_insn ""
5214 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5215 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5216 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5217 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5218 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5219 "fdivs %0,%1,%2"
5220 [(set_attr "type" "sdiv")])
5222 (define_insn ""
5223 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5224 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5225 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5226 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5227 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5228 "{fd|fdiv} %0,%1,%2"
5229 [(set_attr "type" "ddiv")])
5231 (define_expand "recipsf3"
5232 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5233 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5234 (match_operand:SF 2 "gpc_reg_operand" "f")]
5235 UNSPEC_FRES))]
5236 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5237 && flag_finite_math_only && !flag_trapping_math"
5238 {
5239 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5240 DONE;
5241 })
5243 (define_insn "fres"
5244 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5245 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5246 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5247 "fres %0,%1"
5248 [(set_attr "type" "fp")])
5250 (define_insn ""
5251 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5252 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5253 (match_operand:SF 2 "gpc_reg_operand" "f"))
5254 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5255 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5256 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5257 "fmadds %0,%1,%2,%3"
5258 [(set_attr "type" "fp")])
5260 (define_insn ""
5261 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5262 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5263 (match_operand:SF 2 "gpc_reg_operand" "f"))
5264 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5265 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5266 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5267 "{fma|fmadd} %0,%1,%2,%3"
5268 [(set_attr "type" "dmul")])
5270 (define_insn ""
5271 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5272 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5273 (match_operand:SF 2 "gpc_reg_operand" "f"))
5274 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5275 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5276 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5277 "fmsubs %0,%1,%2,%3"
5278 [(set_attr "type" "fp")])
5280 (define_insn ""
5281 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5282 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5283 (match_operand:SF 2 "gpc_reg_operand" "f"))
5284 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5285 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5286 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5287 "{fms|fmsub} %0,%1,%2,%3"
5288 [(set_attr "type" "dmul")])
5290 (define_insn ""
5291 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5292 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5293 (match_operand:SF 2 "gpc_reg_operand" "f"))
5294 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5295 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5296 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5297 "fnmadds %0,%1,%2,%3"
5298 [(set_attr "type" "fp")])
5300 (define_insn ""
5301 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5302 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5303 (match_operand:SF 2 "gpc_reg_operand" "f"))
5304 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5305 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5306 && ! HONOR_SIGNED_ZEROS (SFmode)"
5307 "fnmadds %0,%1,%2,%3"
5308 [(set_attr "type" "fp")])
5310 (define_insn ""
5311 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5312 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5313 (match_operand:SF 2 "gpc_reg_operand" "f"))
5314 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5315 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5316 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5317 "{fnma|fnmadd} %0,%1,%2,%3"
5318 [(set_attr "type" "dmul")])
5320 (define_insn ""
5321 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5322 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5323 (match_operand:SF 2 "gpc_reg_operand" "f"))
5324 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5325 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5326 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5327 "{fnma|fnmadd} %0,%1,%2,%3"
5328 [(set_attr "type" "dmul")])
5330 (define_insn ""
5331 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5332 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5333 (match_operand:SF 2 "gpc_reg_operand" "f"))
5334 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5335 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5336 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5337 "fnmsubs %0,%1,%2,%3"
5338 [(set_attr "type" "fp")])
5340 (define_insn ""
5341 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5342 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5343 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5344 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5345 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5346 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5347 "fnmsubs %0,%1,%2,%3"
5348 [(set_attr "type" "fp")])
5350 (define_insn ""
5351 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5352 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5353 (match_operand:SF 2 "gpc_reg_operand" "f"))
5354 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5355 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5356 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5357 "{fnms|fnmsub} %0,%1,%2,%3"
5358 [(set_attr "type" "dmul")])
5360 (define_insn ""
5361 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5362 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5363 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5364 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5365 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5366 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5367 "{fnms|fnmsub} %0,%1,%2,%3"
5368 [(set_attr "type" "dmul")])
5370 (define_expand "sqrtsf2"
5371 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5372 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5373 "(TARGET_PPC_GPOPT || TARGET_POWER2)
5374 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5375 && !TARGET_SIMPLE_FPU"
5376 "")
5378 (define_insn ""
5379 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5380 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5381 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT
5382 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5383 "fsqrts %0,%1"
5384 [(set_attr "type" "ssqrt")])
5386 (define_insn ""
5387 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5388 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5389 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5390 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5391 "fsqrt %0,%1"
5392 [(set_attr "type" "dsqrt")])
5394 (define_expand "rsqrtsf2"
5395 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5396 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5397 UNSPEC_RSQRT))]
5398 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5399 && flag_finite_math_only && !flag_trapping_math"
5400 {
5401 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5402 DONE;
5403 })
5405 (define_insn "*rsqrt_internal1"
5406 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5407 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5408 UNSPEC_RSQRT))]
5409 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5410 "frsqrte %0,%1"
5411 [(set_attr "type" "fp")])
5413 (define_expand "copysignsf3"
5414 [(set (match_dup 3)
5415 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5416 (set (match_dup 4)
5417 (neg:SF (abs:SF (match_dup 1))))
5418 (set (match_operand:SF 0 "gpc_reg_operand" "")
5419 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5420 (match_dup 5))
5421 (match_dup 3)
5422 (match_dup 4)))]
5423 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5424 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5425 {
5426 operands[3] = gen_reg_rtx (SFmode);
5427 operands[4] = gen_reg_rtx (SFmode);
5428 operands[5] = CONST0_RTX (SFmode);
5429 })
5431 (define_expand "copysigndf3"
5432 [(set (match_dup 3)
5433 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5434 (set (match_dup 4)
5435 (neg:DF (abs:DF (match_dup 1))))
5436 (set (match_operand:DF 0 "gpc_reg_operand" "")
5437 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5438 (match_dup 5))
5439 (match_dup 3)
5440 (match_dup 4)))]
5441 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5442 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5443 {
5444 operands[3] = gen_reg_rtx (DFmode);
5445 operands[4] = gen_reg_rtx (DFmode);
5446 operands[5] = CONST0_RTX (DFmode);
5447 })
5449 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5450 ;; fsel instruction and some auxiliary computations. Then we just have a
5451 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5452 ;; combine.
5453 (define_expand "smaxsf3"
5454 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5455 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5456 (match_operand:SF 2 "gpc_reg_operand" ""))
5457 (match_dup 1)
5458 (match_dup 2)))]
5459 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5460 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5461 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5463 (define_expand "sminsf3"
5464 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5465 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5466 (match_operand:SF 2 "gpc_reg_operand" ""))
5467 (match_dup 2)
5468 (match_dup 1)))]
5469 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5470 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5471 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5473 (define_split
5474 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5475 (match_operator:SF 3 "min_max_operator"
5476 [(match_operand:SF 1 "gpc_reg_operand" "")
5477 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5478 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5479 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5480 [(const_int 0)]
5481 "
5482 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5483 operands[1], operands[2]);
5484 DONE;
5485 }")
5487 (define_expand "movsicc"
5488 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5489 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5490 (match_operand:SI 2 "gpc_reg_operand" "")
5491 (match_operand:SI 3 "gpc_reg_operand" "")))]
5492 "TARGET_ISEL"
5493 "
5494 {
5495 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5496 DONE;
5497 else
5498 FAIL;
5499 }")
5501 ;; We use the BASE_REGS for the isel input operands because, if rA is
5502 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5503 ;; because we may switch the operands and rB may end up being rA.
5504 ;;
5505 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5506 ;; leave out the mode in operand 4 and use one pattern, but reload can
5507 ;; change the mode underneath our feet and then gets confused trying
5508 ;; to reload the value.
5509 (define_insn "isel_signed"
5510 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5511 (if_then_else:SI
5512 (match_operator 1 "comparison_operator"
5513 [(match_operand:CC 4 "cc_reg_operand" "y")
5514 (const_int 0)])
5515 (match_operand:SI 2 "gpc_reg_operand" "b")
5516 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5517 "TARGET_ISEL"
5518 "*
5519 { return output_isel (operands); }"
5520 [(set_attr "length" "4")])
5522 (define_insn "isel_unsigned"
5523 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5524 (if_then_else:SI
5525 (match_operator 1 "comparison_operator"
5526 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5527 (const_int 0)])
5528 (match_operand:SI 2 "gpc_reg_operand" "b")
5529 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5530 "TARGET_ISEL"
5531 "*
5532 { return output_isel (operands); }"
5533 [(set_attr "length" "4")])
5535 (define_expand "movsfcc"
5536 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5537 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5538 (match_operand:SF 2 "gpc_reg_operand" "")
5539 (match_operand:SF 3 "gpc_reg_operand" "")))]
5540 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5541 "
5542 {
5543 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5544 DONE;
5545 else
5546 FAIL;
5547 }")
5549 (define_insn "*fselsfsf4"
5550 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5551 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5552 (match_operand:SF 4 "zero_fp_constant" "F"))
5553 (match_operand:SF 2 "gpc_reg_operand" "f")
5554 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5555 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5556 "fsel %0,%1,%2,%3"
5557 [(set_attr "type" "fp")])
5559 (define_insn "*fseldfsf4"
5560 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5561 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5562 (match_operand:DF 4 "zero_fp_constant" "F"))
5563 (match_operand:SF 2 "gpc_reg_operand" "f")
5564 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5565 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5566 "fsel %0,%1,%2,%3"
5567 [(set_attr "type" "fp")])
5569 (define_expand "negdf2"
5570 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5571 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5572 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5573 "")
5575 (define_insn "*negdf2_fpr"
5576 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5577 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5578 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5579 "fneg %0,%1"
5580 [(set_attr "type" "fp")])
5582 (define_expand "absdf2"
5583 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5584 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5585 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5586 "")
5588 (define_insn "*absdf2_fpr"
5589 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5590 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5591 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5592 "fabs %0,%1"
5593 [(set_attr "type" "fp")])
5595 (define_insn "*nabsdf2_fpr"
5596 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5597 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5598 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5599 "fnabs %0,%1"
5600 [(set_attr "type" "fp")])
5602 (define_expand "adddf3"
5603 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5604 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5605 (match_operand:DF 2 "gpc_reg_operand" "")))]
5606 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5607 "")
5609 (define_insn "*adddf3_fpr"
5610 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5611 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5612 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5613 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5614 "{fa|fadd} %0,%1,%2"
5615 [(set_attr "type" "fp")])
5617 (define_expand "subdf3"
5618 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5619 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5620 (match_operand:DF 2 "gpc_reg_operand" "")))]
5621 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5622 "")
5624 (define_insn "*subdf3_fpr"
5625 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5626 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5627 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5628 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5629 "{fs|fsub} %0,%1,%2"
5630 [(set_attr "type" "fp")])
5632 (define_expand "muldf3"
5633 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5634 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5635 (match_operand:DF 2 "gpc_reg_operand" "")))]
5636 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5637 "")
5639 (define_insn "*muldf3_fpr"
5640 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5641 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5642 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5643 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5644 "{fm|fmul} %0,%1,%2"
5645 [(set_attr "type" "dmul")])
5647 (define_expand "divdf3"
5648 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5649 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5650 (match_operand:DF 2 "gpc_reg_operand" "")))]
5651 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE) && !TARGET_SIMPLE_FPU"
5652 "")
5654 (define_insn "*divdf3_fpr"
5655 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5656 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5657 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5658 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU"
5659 "{fd|fdiv} %0,%1,%2"
5660 [(set_attr "type" "ddiv")])
5662 (define_expand "recipdf3"
5663 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5664 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")
5665 (match_operand:DF 2 "gpc_reg_operand" "f")]
5666 UNSPEC_FRES))]
5667 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
5668 && flag_finite_math_only && !flag_trapping_math"
5669 {
5670 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5671 DONE;
5672 })
5674 (define_insn "fred"
5675 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5676 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5677 "TARGET_POPCNTB && flag_finite_math_only"
5678 "fre %0,%1"
5679 [(set_attr "type" "fp")])
5681 (define_insn ""
5682 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5683 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5684 (match_operand:DF 2 "gpc_reg_operand" "f"))
5685 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5686 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
5687 "{fma|fmadd} %0,%1,%2,%3"
5688 [(set_attr "type" "dmul")])
5690 (define_insn ""
5691 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5692 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5693 (match_operand:DF 2 "gpc_reg_operand" "f"))
5694 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5695 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
5696 "{fms|fmsub} %0,%1,%2,%3"
5697 [(set_attr "type" "dmul")])
5699 (define_insn ""
5700 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5701 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5702 (match_operand:DF 2 "gpc_reg_operand" "f"))
5703 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5704 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5705 && HONOR_SIGNED_ZEROS (DFmode)"
5706 "{fnma|fnmadd} %0,%1,%2,%3"
5707 [(set_attr "type" "dmul")])
5709 (define_insn ""
5710 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5711 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5712 (match_operand:DF 2 "gpc_reg_operand" "f"))
5713 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5714 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5715 && ! HONOR_SIGNED_ZEROS (DFmode)"
5716 "{fnma|fnmadd} %0,%1,%2,%3"
5717 [(set_attr "type" "dmul")])
5719 (define_insn ""
5720 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5721 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5722 (match_operand:DF 2 "gpc_reg_operand" "f"))
5723 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5724 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5725 && HONOR_SIGNED_ZEROS (DFmode)"
5726 "{fnms|fnmsub} %0,%1,%2,%3"
5727 [(set_attr "type" "dmul")])
5729 (define_insn ""
5730 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5731 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5732 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5733 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5734 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5735 && ! HONOR_SIGNED_ZEROS (DFmode)"
5736 "{fnms|fnmsub} %0,%1,%2,%3"
5737 [(set_attr "type" "dmul")])
5739 (define_insn "sqrtdf2"
5740 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5741 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5742 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
5743 && TARGET_DOUBLE_FLOAT"
5744 "fsqrt %0,%1"
5745 [(set_attr "type" "dsqrt")])
5747 ;; The conditional move instructions allow us to perform max and min
5748 ;; operations even when
5750 (define_expand "smaxdf3"
5751 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5752 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5753 (match_operand:DF 2 "gpc_reg_operand" ""))
5754 (match_dup 1)
5755 (match_dup 2)))]
5756 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5757 && !flag_trapping_math"
5758 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5760 (define_expand "smindf3"
5761 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5762 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5763 (match_operand:DF 2 "gpc_reg_operand" ""))
5764 (match_dup 2)
5765 (match_dup 1)))]
5766 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5767 && !flag_trapping_math"
5768 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5770 (define_split
5771 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5772 (match_operator:DF 3 "min_max_operator"
5773 [(match_operand:DF 1 "gpc_reg_operand" "")
5774 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5775 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5776 && !flag_trapping_math"
5777 [(const_int 0)]
5778 "
5779 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5780 operands[1], operands[2]);
5781 DONE;
5782 }")
5784 (define_expand "movdfcc"
5785 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5786 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5787 (match_operand:DF 2 "gpc_reg_operand" "")
5788 (match_operand:DF 3 "gpc_reg_operand" "")))]
5789 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5790 "
5791 {
5792 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5793 DONE;
5794 else
5795 FAIL;
5796 }")
5798 (define_insn "*fseldfdf4"
5799 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5800 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5801 (match_operand:DF 4 "zero_fp_constant" "F"))
5802 (match_operand:DF 2 "gpc_reg_operand" "f")
5803 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5804 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5805 "fsel %0,%1,%2,%3"
5806 [(set_attr "type" "fp")])
5808 (define_insn "*fselsfdf4"
5809 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5810 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5811 (match_operand:SF 4 "zero_fp_constant" "F"))
5812 (match_operand:DF 2 "gpc_reg_operand" "f")
5813 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5814 "TARGET_PPC_GFXOPT"
5815 "fsel %0,%1,%2,%3"
5816 [(set_attr "type" "fp")])
5817 \f
5818 ;; Conversions to and from floating-point.
5820 (define_expand "fixuns_truncsfsi2"
5821 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5822 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5823 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5824 "")
5826 (define_expand "fix_truncsfsi2"
5827 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5828 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5829 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5830 "")
5832 ; For each of these conversions, there is a define_expand, a define_insn
5833 ; with a '#' template, and a define_split (with C code). The idea is
5834 ; to allow constant folding with the template of the define_insn,
5835 ; then to have the insns split later (between sched1 and final).
5837 (define_expand "floatsidf2"
5838 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5839 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5840 (use (match_dup 2))
5841 (use (match_dup 3))
5842 (clobber (match_dup 4))
5843 (clobber (match_dup 5))
5844 (clobber (match_dup 6))])]
5845 "TARGET_HARD_FLOAT
5846 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5847 "
5848 {
5849 if (TARGET_E500_DOUBLE)
5850 {
5851 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5852 DONE;
5853 }
5854 if (TARGET_POWERPC64)
5855 {
5856 rtx x = convert_to_mode (DImode, operands[1], 0);
5857 emit_insn (gen_floatdidf2 (operands[0], x));
5858 DONE;
5859 }
5861 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5862 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5863 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5864 operands[5] = gen_reg_rtx (DFmode);
5865 operands[6] = gen_reg_rtx (SImode);
5866 }")
5868 (define_insn_and_split "*floatsidf2_internal"
5869 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5870 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5871 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5872 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5873 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5874 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5875 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5876 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5877 "#"
5878 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5879 [(pc)]
5880 "
5881 {
5882 rtx lowword, highword;
5883 gcc_assert (MEM_P (operands[4]));
5884 highword = adjust_address (operands[4], SImode, 0);
5885 lowword = adjust_address (operands[4], SImode, 4);
5886 if (! WORDS_BIG_ENDIAN)
5887 {
5888 rtx tmp;
5889 tmp = highword; highword = lowword; lowword = tmp;
5890 }
5892 emit_insn (gen_xorsi3 (operands[6], operands[1],
5893 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5894 emit_move_insn (lowword, operands[6]);
5895 emit_move_insn (highword, operands[2]);
5896 emit_move_insn (operands[5], operands[4]);
5897 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5898 DONE;
5899 }"
5900 [(set_attr "length" "24")])
5902 (define_expand "floatunssisf2"
5903 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5904 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5905 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5906 "")
5908 (define_expand "floatunssidf2"
5909 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5910 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5911 (use (match_dup 2))
5912 (use (match_dup 3))
5913 (clobber (match_dup 4))
5914 (clobber (match_dup 5))])]
5915 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5916 "
5917 {
5918 if (TARGET_E500_DOUBLE)
5919 {
5920 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5921 DONE;
5922 }
5923 if (TARGET_POWERPC64)
5924 {
5925 rtx x = convert_to_mode (DImode, operands[1], 1);
5926 emit_insn (gen_floatdidf2 (operands[0], x));
5927 DONE;
5928 }
5930 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5931 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5932 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5933 operands[5] = gen_reg_rtx (DFmode);
5934 }")
5936 (define_insn_and_split "*floatunssidf2_internal"
5937 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5938 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5939 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5940 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5941 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5942 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5943 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5944 "#"
5945 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5946 [(pc)]
5947 "
5948 {
5949 rtx lowword, highword;
5950 gcc_assert (MEM_P (operands[4]));
5951 highword = adjust_address (operands[4], SImode, 0);
5952 lowword = adjust_address (operands[4], SImode, 4);
5953 if (! WORDS_BIG_ENDIAN)
5954 {
5955 rtx tmp;
5956 tmp = highword; highword = lowword; lowword = tmp;
5957 }
5959 emit_move_insn (lowword, operands[1]);
5960 emit_move_insn (highword, operands[2]);
5961 emit_move_insn (operands[5], operands[4]);
5962 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5963 DONE;
5964 }"
5965 [(set_attr "length" "20")])
5967 (define_expand "fix_truncdfsi2"
5968 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5969 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5970 (clobber (match_dup 2))
5971 (clobber (match_dup 3))])]
5972 "(TARGET_POWER2 || TARGET_POWERPC)
5973 && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5974 "
5975 {
5976 if (TARGET_E500_DOUBLE)
5977 {
5978 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5979 DONE;
5980 }
5981 operands[2] = gen_reg_rtx (DImode);
5982 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5983 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5984 {
5985 operands[3] = gen_reg_rtx (DImode);
5986 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5987 operands[2], operands[3]));
5988 DONE;
5989 }
5990 if (TARGET_PPC_GFXOPT)
5991 {
5992 rtx orig_dest = operands[0];
5993 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5994 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5995 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5996 operands[2]));
5997 if (operands[0] != orig_dest)
5998 emit_move_insn (orig_dest, operands[0]);
5999 DONE;
6000 }
6001 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
6002 }")
6004 (define_insn_and_split "*fix_truncdfsi2_internal"
6005 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6006 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6007 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6008 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6009 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6010 && TARGET_DOUBLE_FLOAT"
6011 "#"
6012 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
6013 [(pc)]
6014 "
6015 {
6016 rtx lowword;
6017 gcc_assert (MEM_P (operands[3]));
6018 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6020 emit_insn (gen_fctiwz (operands[2], operands[1]));
6021 emit_move_insn (operands[3], operands[2]);
6022 emit_move_insn (operands[0], lowword);
6023 DONE;
6024 }"
6025 [(set_attr "length" "16")])
6027 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6028 [(set (match_operand:SI 0 "memory_operand" "=Z")
6029 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6030 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
6031 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6032 && TARGET_DOUBLE_FLOAT
6033 && TARGET_PPC_GFXOPT"
6034 "#"
6035 "&& 1"
6036 [(pc)]
6037 "
6038 {
6039 emit_insn (gen_fctiwz (operands[2], operands[1]));
6040 emit_insn (gen_stfiwx (operands[0], operands[2]));
6041 DONE;
6042 }"
6043 [(set_attr "length" "16")])
6045 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6046 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6047 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6048 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6049 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6050 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6051 && TARGET_DOUBLE_FLOAT"
6052 "#"
6053 "&& 1"
6054 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6055 (set (match_dup 3) (match_dup 2))
6056 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6057 ""
6058 [(set_attr "length" "12")])
6060 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6061 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6062 ; because the first makes it clear that operand 0 is not live
6063 ; before the instruction.
6064 (define_insn "fctiwz"
6065 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
6066 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
6067 UNSPEC_FCTIWZ))]
6068 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6069 && TARGET_DOUBLE_FLOAT"
6070 "{fcirz|fctiwz} %0,%1"
6071 [(set_attr "type" "fp")])
6073 (define_insn "btruncdf2"
6074 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6075 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6076 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6077 "friz %0,%1"
6078 [(set_attr "type" "fp")])
6080 (define_insn "btruncsf2"
6081 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6082 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6083 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6084 "friz %0,%1"
6085 [(set_attr "type" "fp")])
6087 (define_insn "ceildf2"
6088 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6089 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6090 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6091 "frip %0,%1"
6092 [(set_attr "type" "fp")])
6094 (define_insn "ceilsf2"
6095 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6096 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6097 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6098 "frip %0,%1"
6099 [(set_attr "type" "fp")])
6101 (define_insn "floordf2"
6102 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6103 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6104 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6105 "frim %0,%1"
6106 [(set_attr "type" "fp")])
6108 (define_insn "floorsf2"
6109 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6110 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6111 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6112 "frim %0,%1"
6113 [(set_attr "type" "fp")])
6115 (define_insn "rounddf2"
6116 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6117 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6118 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6119 "frin %0,%1"
6120 [(set_attr "type" "fp")])
6122 (define_insn "roundsf2"
6123 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6124 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6125 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6126 "frin %0,%1"
6127 [(set_attr "type" "fp")])
6129 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6130 (define_insn "stfiwx"
6131 [(set (match_operand:SI 0 "memory_operand" "=Z")
6132 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6133 UNSPEC_STFIWX))]
6134 "TARGET_PPC_GFXOPT"
6135 "stfiwx %1,%y0"
6136 [(set_attr "type" "fpstore")])
6138 (define_expand "floatsisf2"
6139 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6140 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6141 "TARGET_HARD_FLOAT && (!TARGET_FPRS || TARGET_SINGLE_FPU)"
6142 "")
6144 (define_insn "floatdidf2"
6145 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6146 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))]
6147 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6148 "fcfid %0,%1"
6149 [(set_attr "type" "fp")])
6151 (define_insn "fix_truncdfdi2"
6152 [(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r")
6153 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
6154 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6155 "fctidz %0,%1"
6156 [(set_attr "type" "fp")])
6158 (define_expand "floatdisf2"
6159 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6160 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6161 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6162 "
6163 {
6164 rtx val = operands[1];
6165 if (!flag_unsafe_math_optimizations)
6166 {
6167 rtx label = gen_label_rtx ();
6168 val = gen_reg_rtx (DImode);
6169 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6170 emit_label (label);
6171 }
6172 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6173 DONE;
6174 }")
6176 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6177 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6178 ;; from double rounding.
6179 (define_insn_and_split "floatdisf2_internal1"
6180 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6181 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))
6182 (clobber (match_scratch:DF 2 "=f"))]
6183 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6184 "#"
6185 "&& reload_completed"
6186 [(set (match_dup 2)
6187 (float:DF (match_dup 1)))
6188 (set (match_dup 0)
6189 (float_truncate:SF (match_dup 2)))]
6190 "")
6192 ;; Twiddles bits to avoid double rounding.
6193 ;; Bits that might be truncated when converting to DFmode are replaced
6194 ;; by a bit that won't be lost at that stage, but is below the SFmode
6195 ;; rounding position.
6196 (define_expand "floatdisf2_internal2"
6197 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6198 (const_int 53)))
6199 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6200 (const_int 2047)))
6201 (clobber (scratch:CC))])
6202 (set (match_dup 3) (plus:DI (match_dup 3)
6203 (const_int 1)))
6204 (set (match_dup 0) (plus:DI (match_dup 0)
6205 (const_int 2047)))
6206 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6207 (const_int 2)))
6208 (set (match_dup 0) (ior:DI (match_dup 0)
6209 (match_dup 1)))
6210 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6211 (const_int -2048)))
6212 (clobber (scratch:CC))])
6213 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6214 (label_ref (match_operand:DI 2 "" ""))
6215 (pc)))
6216 (set (match_dup 0) (match_dup 1))]
6217 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6218 "
6219 {
6220 operands[3] = gen_reg_rtx (DImode);
6221 operands[4] = gen_reg_rtx (CCUNSmode);
6222 }")
6223 \f
6224 ;; Define the DImode operations that can be done in a small number
6225 ;; of instructions. The & constraints are to prevent the register
6226 ;; allocator from allocating registers that overlap with the inputs
6227 ;; (for example, having an input in 7,8 and an output in 6,7). We
6228 ;; also allow for the output being the same as one of the inputs.
6230 (define_insn "*adddi3_noppc64"
6231 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6232 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6233 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6234 "! TARGET_POWERPC64"
6235 "*
6236 {
6237 if (WORDS_BIG_ENDIAN)
6238 return (GET_CODE (operands[2])) != CONST_INT
6239 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6240 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6241 else
6242 return (GET_CODE (operands[2])) != CONST_INT
6243 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6244 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6245 }"
6246 [(set_attr "type" "two")
6247 (set_attr "length" "8")])
6249 (define_insn "*subdi3_noppc64"
6250 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6251 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6252 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6253 "! TARGET_POWERPC64"
6254 "*
6255 {
6256 if (WORDS_BIG_ENDIAN)
6257 return (GET_CODE (operands[1]) != CONST_INT)
6258 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6259 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6260 else
6261 return (GET_CODE (operands[1]) != CONST_INT)
6262 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6263 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6264 }"
6265 [(set_attr "type" "two")
6266 (set_attr "length" "8")])
6268 (define_insn "*negdi2_noppc64"
6269 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6270 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6271 "! TARGET_POWERPC64"
6272 "*
6273 {
6274 return (WORDS_BIG_ENDIAN)
6275 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6276 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6277 }"
6278 [(set_attr "type" "two")
6279 (set_attr "length" "8")])
6281 (define_expand "mulsidi3"
6282 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6283 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6284 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6285 "! TARGET_POWERPC64"
6286 "
6287 {
6288 if (! TARGET_POWER && ! TARGET_POWERPC)
6289 {
6290 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6291 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6292 emit_insn (gen_mull_call ());
6293 if (WORDS_BIG_ENDIAN)
6294 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6295 else
6296 {
6297 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6298 gen_rtx_REG (SImode, 3));
6299 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6300 gen_rtx_REG (SImode, 4));
6301 }
6302 DONE;
6303 }
6304 else if (TARGET_POWER)
6305 {
6306 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6307 DONE;
6308 }
6309 }")
6311 (define_insn "mulsidi3_mq"
6312 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6313 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6314 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6315 (clobber (match_scratch:SI 3 "=q"))]
6316 "TARGET_POWER"
6317 "mul %0,%1,%2\;mfmq %L0"
6318 [(set_attr "type" "imul")
6319 (set_attr "length" "8")])
6321 (define_insn "*mulsidi3_no_mq"
6322 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6323 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6324 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6325 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6326 "*
6327 {
6328 return (WORDS_BIG_ENDIAN)
6329 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6330 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6331 }"
6332 [(set_attr "type" "imul")
6333 (set_attr "length" "8")])
6335 (define_split
6336 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6337 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6338 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6339 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6340 [(set (match_dup 3)
6341 (truncate:SI
6342 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6343 (sign_extend:DI (match_dup 2)))
6344 (const_int 32))))
6345 (set (match_dup 4)
6346 (mult:SI (match_dup 1)
6347 (match_dup 2)))]
6348 "
6349 {
6350 int endian = (WORDS_BIG_ENDIAN == 0);
6351 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6352 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6353 }")
6355 (define_expand "umulsidi3"
6356 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6357 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6358 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6359 "TARGET_POWERPC && ! TARGET_POWERPC64"
6360 "
6361 {
6362 if (TARGET_POWER)
6363 {
6364 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6365 DONE;
6366 }
6367 }")
6369 (define_insn "umulsidi3_mq"
6370 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6371 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6372 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6373 (clobber (match_scratch:SI 3 "=q"))]
6374 "TARGET_POWERPC && TARGET_POWER"
6375 "*
6376 {
6377 return (WORDS_BIG_ENDIAN)
6378 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6379 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6380 }"
6381 [(set_attr "type" "imul")
6382 (set_attr "length" "8")])
6384 (define_insn "*umulsidi3_no_mq"
6385 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6386 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6387 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6388 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6389 "*
6390 {
6391 return (WORDS_BIG_ENDIAN)
6392 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6393 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6394 }"
6395 [(set_attr "type" "imul")
6396 (set_attr "length" "8")])
6398 (define_split
6399 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6400 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6401 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6402 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6403 [(set (match_dup 3)
6404 (truncate:SI
6405 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6406 (zero_extend:DI (match_dup 2)))
6407 (const_int 32))))
6408 (set (match_dup 4)
6409 (mult:SI (match_dup 1)
6410 (match_dup 2)))]
6411 "
6412 {
6413 int endian = (WORDS_BIG_ENDIAN == 0);
6414 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6415 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6416 }")
6418 (define_expand "smulsi3_highpart"
6419 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6420 (truncate:SI
6421 (lshiftrt:DI (mult:DI (sign_extend:DI
6422 (match_operand:SI 1 "gpc_reg_operand" ""))
6423 (sign_extend:DI
6424 (match_operand:SI 2 "gpc_reg_operand" "")))
6425 (const_int 32))))]
6426 ""
6427 "
6428 {
6429 if (! TARGET_POWER && ! TARGET_POWERPC)
6430 {
6431 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6432 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6433 emit_insn (gen_mulh_call ());
6434 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6435 DONE;
6436 }
6437 else if (TARGET_POWER)
6438 {
6439 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6440 DONE;
6441 }
6442 }")
6444 (define_insn "smulsi3_highpart_mq"
6445 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6446 (truncate:SI
6447 (lshiftrt:DI (mult:DI (sign_extend:DI
6448 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6449 (sign_extend:DI
6450 (match_operand:SI 2 "gpc_reg_operand" "r")))
6451 (const_int 32))))
6452 (clobber (match_scratch:SI 3 "=q"))]
6453 "TARGET_POWER"
6454 "mul %0,%1,%2"
6455 [(set_attr "type" "imul")])
6457 (define_insn "*smulsi3_highpart_no_mq"
6458 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6459 (truncate:SI
6460 (lshiftrt:DI (mult:DI (sign_extend:DI
6461 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6462 (sign_extend:DI
6463 (match_operand:SI 2 "gpc_reg_operand" "r")))
6464 (const_int 32))))]
6465 "TARGET_POWERPC && ! TARGET_POWER"
6466 "mulhw %0,%1,%2"
6467 [(set_attr "type" "imul")])
6469 (define_expand "umulsi3_highpart"
6470 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6471 (truncate:SI
6472 (lshiftrt:DI (mult:DI (zero_extend:DI
6473 (match_operand:SI 1 "gpc_reg_operand" ""))
6474 (zero_extend:DI
6475 (match_operand:SI 2 "gpc_reg_operand" "")))
6476 (const_int 32))))]
6477 "TARGET_POWERPC"
6478 "
6479 {
6480 if (TARGET_POWER)
6481 {
6482 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6483 DONE;
6484 }
6485 }")
6487 (define_insn "umulsi3_highpart_mq"
6488 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6489 (truncate:SI
6490 (lshiftrt:DI (mult:DI (zero_extend:DI
6491 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6492 (zero_extend:DI
6493 (match_operand:SI 2 "gpc_reg_operand" "r")))
6494 (const_int 32))))
6495 (clobber (match_scratch:SI 3 "=q"))]
6496 "TARGET_POWERPC && TARGET_POWER"
6497 "mulhwu %0,%1,%2"
6498 [(set_attr "type" "imul")])
6500 (define_insn "*umulsi3_highpart_no_mq"
6501 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6502 (truncate:SI
6503 (lshiftrt:DI (mult:DI (zero_extend:DI
6504 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6505 (zero_extend:DI
6506 (match_operand:SI 2 "gpc_reg_operand" "r")))
6507 (const_int 32))))]
6508 "TARGET_POWERPC && ! TARGET_POWER"
6509 "mulhwu %0,%1,%2"
6510 [(set_attr "type" "imul")])
6512 ;; If operands 0 and 2 are in the same register, we have a problem. But
6513 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6514 ;; why we have the strange constraints below.
6515 (define_insn "ashldi3_power"
6516 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6517 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6518 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6519 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6520 "TARGET_POWER"
6521 "@
6522 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6523 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6524 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6525 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6526 [(set_attr "length" "8")])
6528 (define_insn "lshrdi3_power"
6529 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6530 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6531 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6532 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6533 "TARGET_POWER"
6534 "@
6535 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6536 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6537 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6538 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6539 [(set_attr "length" "8")])
6541 ;; Shift by a variable amount is too complex to be worth open-coding. We
6542 ;; just handle shifts by constants.
6543 (define_insn "ashrdi3_power"
6544 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6545 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6546 (match_operand:SI 2 "const_int_operand" "M,i")))
6547 (clobber (match_scratch:SI 3 "=X,q"))]
6548 "TARGET_POWER"
6549 "@
6550 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6551 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6552 [(set_attr "type" "shift")
6553 (set_attr "length" "8")])
6555 (define_insn "ashrdi3_no_power"
6556 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6557 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6558 (match_operand:SI 2 "const_int_operand" "M,i")))]
6559 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6560 "@
6561 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6562 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6563 [(set_attr "type" "two,three")
6564 (set_attr "length" "8,12")])
6566 (define_insn "*ashrdisi3_noppc64"
6567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6568 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6569 (const_int 32)) 4))]
6570 "TARGET_32BIT && !TARGET_POWERPC64"
6571 "*
6572 {
6573 if (REGNO (operands[0]) == REGNO (operands[1]))
6574 return \"\";
6575 else
6576 return \"mr %0,%1\";
6577 }"
6578 [(set_attr "length" "4")])
6580 \f
6581 ;; PowerPC64 DImode operations.
6583 (define_insn_and_split "absdi2"
6584 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6585 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6586 (clobber (match_scratch:DI 2 "=&r,&r"))]
6587 "TARGET_POWERPC64"
6588 "#"
6589 "&& reload_completed"
6590 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6591 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6592 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6593 "")
6595 (define_insn_and_split "*nabsdi2"
6596 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6597 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6598 (clobber (match_scratch:DI 2 "=&r,&r"))]
6599 "TARGET_POWERPC64"
6600 "#"
6601 "&& reload_completed"
6602 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6603 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6604 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6605 "")
6607 (define_insn "muldi3"
6608 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6609 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6610 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6611 "TARGET_POWERPC64"
6612 "@
6613 mulld %0,%1,%2
6614 mulli %0,%1,%2"
6615 [(set (attr "type")
6616 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6617 (const_string "imul3")
6618 (match_operand:SI 2 "short_cint_operand" "")
6619 (const_string "imul2")]
6620 (const_string "lmul")))])
6622 (define_insn "*muldi3_internal1"
6623 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6624 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6625 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6626 (const_int 0)))
6627 (clobber (match_scratch:DI 3 "=r,r"))]
6628 "TARGET_POWERPC64"
6629 "@
6630 mulld. %3,%1,%2
6631 #"
6632 [(set_attr "type" "lmul_compare")
6633 (set_attr "length" "4,8")])
6635 (define_split
6636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6637 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6638 (match_operand:DI 2 "gpc_reg_operand" ""))
6639 (const_int 0)))
6640 (clobber (match_scratch:DI 3 ""))]
6641 "TARGET_POWERPC64 && reload_completed"
6642 [(set (match_dup 3)
6643 (mult:DI (match_dup 1) (match_dup 2)))
6644 (set (match_dup 0)
6645 (compare:CC (match_dup 3)
6646 (const_int 0)))]
6647 "")
6649 (define_insn "*muldi3_internal2"
6650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6651 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6652 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6653 (const_int 0)))
6654 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6655 (mult:DI (match_dup 1) (match_dup 2)))]
6656 "TARGET_POWERPC64"
6657 "@
6658 mulld. %0,%1,%2
6659 #"
6660 [(set_attr "type" "lmul_compare")
6661 (set_attr "length" "4,8")])
6663 (define_split
6664 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6665 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6666 (match_operand:DI 2 "gpc_reg_operand" ""))
6667 (const_int 0)))
6668 (set (match_operand:DI 0 "gpc_reg_operand" "")
6669 (mult:DI (match_dup 1) (match_dup 2)))]
6670 "TARGET_POWERPC64 && reload_completed"
6671 [(set (match_dup 0)
6672 (mult:DI (match_dup 1) (match_dup 2)))
6673 (set (match_dup 3)
6674 (compare:CC (match_dup 0)
6675 (const_int 0)))]
6676 "")
6678 (define_insn "smuldi3_highpart"
6679 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6680 (truncate:DI
6681 (lshiftrt:TI (mult:TI (sign_extend:TI
6682 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6683 (sign_extend:TI
6684 (match_operand:DI 2 "gpc_reg_operand" "r")))
6685 (const_int 64))))]
6686 "TARGET_POWERPC64"
6687 "mulhd %0,%1,%2"
6688 [(set_attr "type" "lmul")])
6690 (define_insn "umuldi3_highpart"
6691 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6692 (truncate:DI
6693 (lshiftrt:TI (mult:TI (zero_extend:TI
6694 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6695 (zero_extend:TI
6696 (match_operand:DI 2 "gpc_reg_operand" "r")))
6697 (const_int 64))))]
6698 "TARGET_POWERPC64"
6699 "mulhdu %0,%1,%2"
6700 [(set_attr "type" "lmul")])
6702 (define_insn "rotldi3"
6703 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6704 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6705 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6706 "TARGET_POWERPC64"
6707 "@
6708 rldcl %0,%1,%2,0
6709 rldicl %0,%1,%H2,0"
6710 [(set_attr "type" "var_shift_rotate,integer")])
6712 (define_insn "*rotldi3_internal2"
6713 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6714 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6715 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6716 (const_int 0)))
6717 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6718 "TARGET_64BIT"
6719 "@
6720 rldcl. %3,%1,%2,0
6721 rldicl. %3,%1,%H2,0
6722 #
6723 #"
6724 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6725 (set_attr "length" "4,4,8,8")])
6727 (define_split
6728 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6729 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6730 (match_operand:DI 2 "reg_or_cint_operand" ""))
6731 (const_int 0)))
6732 (clobber (match_scratch:DI 3 ""))]
6733 "TARGET_POWERPC64 && reload_completed"
6734 [(set (match_dup 3)
6735 (rotate:DI (match_dup 1) (match_dup 2)))
6736 (set (match_dup 0)
6737 (compare:CC (match_dup 3)
6738 (const_int 0)))]
6739 "")
6741 (define_insn "*rotldi3_internal3"
6742 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6743 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6744 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6745 (const_int 0)))
6746 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6747 (rotate:DI (match_dup 1) (match_dup 2)))]
6748 "TARGET_64BIT"
6749 "@
6750 rldcl. %0,%1,%2,0
6751 rldicl. %0,%1,%H2,0
6752 #
6753 #"
6754 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6755 (set_attr "length" "4,4,8,8")])
6757 (define_split
6758 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6759 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6760 (match_operand:DI 2 "reg_or_cint_operand" ""))
6761 (const_int 0)))
6762 (set (match_operand:DI 0 "gpc_reg_operand" "")
6763 (rotate:DI (match_dup 1) (match_dup 2)))]
6764 "TARGET_POWERPC64 && reload_completed"
6765 [(set (match_dup 0)
6766 (rotate:DI (match_dup 1) (match_dup 2)))
6767 (set (match_dup 3)
6768 (compare:CC (match_dup 0)
6769 (const_int 0)))]
6770 "")
6772 (define_insn "*rotldi3_internal4"
6773 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6774 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6775 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6776 (match_operand:DI 3 "mask64_operand" "n,n")))]
6777 "TARGET_POWERPC64"
6778 "@
6779 rldc%B3 %0,%1,%2,%S3
6780 rldic%B3 %0,%1,%H2,%S3"
6781 [(set_attr "type" "var_shift_rotate,integer")])
6783 (define_insn "*rotldi3_internal5"
6784 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6785 (compare:CC (and:DI
6786 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6787 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6788 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6789 (const_int 0)))
6790 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6791 "TARGET_64BIT"
6792 "@
6793 rldc%B3. %4,%1,%2,%S3
6794 rldic%B3. %4,%1,%H2,%S3
6795 #
6796 #"
6797 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6798 (set_attr "length" "4,4,8,8")])
6800 (define_split
6801 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6802 (compare:CC (and:DI
6803 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6804 (match_operand:DI 2 "reg_or_cint_operand" ""))
6805 (match_operand:DI 3 "mask64_operand" ""))
6806 (const_int 0)))
6807 (clobber (match_scratch:DI 4 ""))]
6808 "TARGET_POWERPC64 && reload_completed"
6809 [(set (match_dup 4)
6810 (and:DI (rotate:DI (match_dup 1)
6811 (match_dup 2))
6812 (match_dup 3)))
6813 (set (match_dup 0)
6814 (compare:CC (match_dup 4)
6815 (const_int 0)))]
6816 "")
6818 (define_insn "*rotldi3_internal6"
6819 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6820 (compare:CC (and:DI
6821 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6822 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6823 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6824 (const_int 0)))
6825 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6826 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6827 "TARGET_64BIT"
6828 "@
6829 rldc%B3. %0,%1,%2,%S3
6830 rldic%B3. %0,%1,%H2,%S3
6831 #
6832 #"
6833 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6834 (set_attr "length" "4,4,8,8")])
6836 (define_split
6837 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6838 (compare:CC (and:DI
6839 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6840 (match_operand:DI 2 "reg_or_cint_operand" ""))
6841 (match_operand:DI 3 "mask64_operand" ""))
6842 (const_int 0)))
6843 (set (match_operand:DI 0 "gpc_reg_operand" "")
6844 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6845 "TARGET_POWERPC64 && reload_completed"
6846 [(set (match_dup 0)
6847 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6848 (set (match_dup 4)
6849 (compare:CC (match_dup 0)
6850 (const_int 0)))]
6851 "")
6853 (define_insn "*rotldi3_internal7"
6854 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6855 (zero_extend:DI
6856 (subreg:QI
6857 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6858 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6859 "TARGET_POWERPC64"
6860 "@
6861 rldcl %0,%1,%2,56
6862 rldicl %0,%1,%H2,56"
6863 [(set_attr "type" "var_shift_rotate,integer")])
6865 (define_insn "*rotldi3_internal8"
6866 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6867 (compare:CC (zero_extend:DI
6868 (subreg:QI
6869 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6870 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6871 (const_int 0)))
6872 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6873 "TARGET_64BIT"
6874 "@
6875 rldcl. %3,%1,%2,56
6876 rldicl. %3,%1,%H2,56
6877 #
6878 #"
6879 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6880 (set_attr "length" "4,4,8,8")])
6882 (define_split
6883 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6884 (compare:CC (zero_extend:DI
6885 (subreg:QI
6886 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6887 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6888 (const_int 0)))
6889 (clobber (match_scratch:DI 3 ""))]
6890 "TARGET_POWERPC64 && reload_completed"
6891 [(set (match_dup 3)
6892 (zero_extend:DI (subreg:QI
6893 (rotate:DI (match_dup 1)
6894 (match_dup 2)) 0)))
6895 (set (match_dup 0)
6896 (compare:CC (match_dup 3)
6897 (const_int 0)))]
6898 "")
6900 (define_insn "*rotldi3_internal9"
6901 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6902 (compare:CC (zero_extend:DI
6903 (subreg:QI
6904 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6905 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6906 (const_int 0)))
6907 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6908 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6909 "TARGET_64BIT"
6910 "@
6911 rldcl. %0,%1,%2,56
6912 rldicl. %0,%1,%H2,56
6913 #
6914 #"
6915 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6916 (set_attr "length" "4,4,8,8")])
6918 (define_split
6919 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6920 (compare:CC (zero_extend:DI
6921 (subreg:QI
6922 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6923 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6924 (const_int 0)))
6925 (set (match_operand:DI 0 "gpc_reg_operand" "")
6926 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6927 "TARGET_POWERPC64 && reload_completed"
6928 [(set (match_dup 0)
6929 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6930 (set (match_dup 3)
6931 (compare:CC (match_dup 0)
6932 (const_int 0)))]
6933 "")
6935 (define_insn "*rotldi3_internal10"
6936 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6937 (zero_extend:DI
6938 (subreg:HI
6939 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6940 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6941 "TARGET_POWERPC64"
6942 "@
6943 rldcl %0,%1,%2,48
6944 rldicl %0,%1,%H2,48"
6945 [(set_attr "type" "var_shift_rotate,integer")])
6947 (define_insn "*rotldi3_internal11"
6948 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6949 (compare:CC (zero_extend:DI
6950 (subreg:HI
6951 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6952 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6953 (const_int 0)))
6954 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6955 "TARGET_64BIT"
6956 "@
6957 rldcl. %3,%1,%2,48
6958 rldicl. %3,%1,%H2,48
6959 #
6960 #"
6961 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6962 (set_attr "length" "4,4,8,8")])
6964 (define_split
6965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6966 (compare:CC (zero_extend:DI
6967 (subreg:HI
6968 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6969 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6970 (const_int 0)))
6971 (clobber (match_scratch:DI 3 ""))]
6972 "TARGET_POWERPC64 && reload_completed"
6973 [(set (match_dup 3)
6974 (zero_extend:DI (subreg:HI
6975 (rotate:DI (match_dup 1)
6976 (match_dup 2)) 0)))
6977 (set (match_dup 0)
6978 (compare:CC (match_dup 3)
6979 (const_int 0)))]
6980 "")
6982 (define_insn "*rotldi3_internal12"
6983 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6984 (compare:CC (zero_extend:DI
6985 (subreg:HI
6986 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6987 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6988 (const_int 0)))
6989 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6990 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6991 "TARGET_64BIT"
6992 "@
6993 rldcl. %0,%1,%2,48
6994 rldicl. %0,%1,%H2,48
6995 #
6996 #"
6997 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6998 (set_attr "length" "4,4,8,8")])
7000 (define_split
7001 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7002 (compare:CC (zero_extend:DI
7003 (subreg:HI
7004 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7005 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7006 (const_int 0)))
7007 (set (match_operand:DI 0 "gpc_reg_operand" "")
7008 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7009 "TARGET_POWERPC64 && reload_completed"
7010 [(set (match_dup 0)
7011 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7012 (set (match_dup 3)
7013 (compare:CC (match_dup 0)
7014 (const_int 0)))]
7015 "")
7017 (define_insn "*rotldi3_internal13"
7018 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7019 (zero_extend:DI
7020 (subreg:SI
7021 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7022 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7023 "TARGET_POWERPC64"
7024 "@
7025 rldcl %0,%1,%2,32
7026 rldicl %0,%1,%H2,32"
7027 [(set_attr "type" "var_shift_rotate,integer")])
7029 (define_insn "*rotldi3_internal14"
7030 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7031 (compare:CC (zero_extend:DI
7032 (subreg:SI
7033 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7034 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7035 (const_int 0)))
7036 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7037 "TARGET_64BIT"
7038 "@
7039 rldcl. %3,%1,%2,32
7040 rldicl. %3,%1,%H2,32
7041 #
7042 #"
7043 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7044 (set_attr "length" "4,4,8,8")])
7046 (define_split
7047 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7048 (compare:CC (zero_extend:DI
7049 (subreg:SI
7050 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7051 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7052 (const_int 0)))
7053 (clobber (match_scratch:DI 3 ""))]
7054 "TARGET_POWERPC64 && reload_completed"
7055 [(set (match_dup 3)
7056 (zero_extend:DI (subreg:SI
7057 (rotate:DI (match_dup 1)
7058 (match_dup 2)) 0)))
7059 (set (match_dup 0)
7060 (compare:CC (match_dup 3)
7061 (const_int 0)))]
7062 "")
7064 (define_insn "*rotldi3_internal15"
7065 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7066 (compare:CC (zero_extend:DI
7067 (subreg:SI
7068 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7069 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7070 (const_int 0)))
7071 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7072 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7073 "TARGET_64BIT"
7074 "@
7075 rldcl. %0,%1,%2,32
7076 rldicl. %0,%1,%H2,32
7077 #
7078 #"
7079 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7080 (set_attr "length" "4,4,8,8")])
7082 (define_split
7083 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7084 (compare:CC (zero_extend:DI
7085 (subreg:SI
7086 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7087 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7088 (const_int 0)))
7089 (set (match_operand:DI 0 "gpc_reg_operand" "")
7090 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7091 "TARGET_POWERPC64 && reload_completed"
7092 [(set (match_dup 0)
7093 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7094 (set (match_dup 3)
7095 (compare:CC (match_dup 0)
7096 (const_int 0)))]
7097 "")
7099 (define_expand "ashldi3"
7100 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7101 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7102 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7103 "TARGET_POWERPC64 || TARGET_POWER"
7104 "
7105 {
7106 if (TARGET_POWERPC64)
7107 ;
7108 else if (TARGET_POWER)
7109 {
7110 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7111 DONE;
7112 }
7113 else
7114 FAIL;
7115 }")
7117 (define_insn "*ashldi3_internal1"
7118 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7119 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7120 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7121 "TARGET_POWERPC64"
7122 "@
7123 sld %0,%1,%2
7124 sldi %0,%1,%H2"
7125 [(set_attr "type" "var_shift_rotate,shift")])
7127 (define_insn "*ashldi3_internal2"
7128 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7129 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7130 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7131 (const_int 0)))
7132 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7133 "TARGET_64BIT"
7134 "@
7135 sld. %3,%1,%2
7136 sldi. %3,%1,%H2
7137 #
7138 #"
7139 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7140 (set_attr "length" "4,4,8,8")])
7142 (define_split
7143 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7144 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7145 (match_operand:SI 2 "reg_or_cint_operand" ""))
7146 (const_int 0)))
7147 (clobber (match_scratch:DI 3 ""))]
7148 "TARGET_POWERPC64 && reload_completed"
7149 [(set (match_dup 3)
7150 (ashift:DI (match_dup 1) (match_dup 2)))
7151 (set (match_dup 0)
7152 (compare:CC (match_dup 3)
7153 (const_int 0)))]
7154 "")
7156 (define_insn "*ashldi3_internal3"
7157 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7158 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7159 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7160 (const_int 0)))
7161 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7162 (ashift:DI (match_dup 1) (match_dup 2)))]
7163 "TARGET_64BIT"
7164 "@
7165 sld. %0,%1,%2
7166 sldi. %0,%1,%H2
7167 #
7168 #"
7169 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7170 (set_attr "length" "4,4,8,8")])
7172 (define_split
7173 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7174 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7175 (match_operand:SI 2 "reg_or_cint_operand" ""))
7176 (const_int 0)))
7177 (set (match_operand:DI 0 "gpc_reg_operand" "")
7178 (ashift:DI (match_dup 1) (match_dup 2)))]
7179 "TARGET_POWERPC64 && reload_completed"
7180 [(set (match_dup 0)
7181 (ashift:DI (match_dup 1) (match_dup 2)))
7182 (set (match_dup 3)
7183 (compare:CC (match_dup 0)
7184 (const_int 0)))]
7185 "")
7187 (define_insn "*ashldi3_internal4"
7188 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7189 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7190 (match_operand:SI 2 "const_int_operand" "i"))
7191 (match_operand:DI 3 "const_int_operand" "n")))]
7192 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7193 "rldic %0,%1,%H2,%W3")
7195 (define_insn "ashldi3_internal5"
7196 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7197 (compare:CC
7198 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7199 (match_operand:SI 2 "const_int_operand" "i,i"))
7200 (match_operand:DI 3 "const_int_operand" "n,n"))
7201 (const_int 0)))
7202 (clobber (match_scratch:DI 4 "=r,r"))]
7203 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7204 "@
7205 rldic. %4,%1,%H2,%W3
7206 #"
7207 [(set_attr "type" "compare")
7208 (set_attr "length" "4,8")])
7210 (define_split
7211 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7212 (compare:CC
7213 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7214 (match_operand:SI 2 "const_int_operand" ""))
7215 (match_operand:DI 3 "const_int_operand" ""))
7216 (const_int 0)))
7217 (clobber (match_scratch:DI 4 ""))]
7218 "TARGET_POWERPC64 && reload_completed
7219 && includes_rldic_lshift_p (operands[2], operands[3])"
7220 [(set (match_dup 4)
7221 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7222 (match_dup 3)))
7223 (set (match_dup 0)
7224 (compare:CC (match_dup 4)
7225 (const_int 0)))]
7226 "")
7228 (define_insn "*ashldi3_internal6"
7229 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7230 (compare:CC
7231 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7232 (match_operand:SI 2 "const_int_operand" "i,i"))
7233 (match_operand:DI 3 "const_int_operand" "n,n"))
7234 (const_int 0)))
7235 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7236 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7237 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7238 "@
7239 rldic. %0,%1,%H2,%W3
7240 #"
7241 [(set_attr "type" "compare")
7242 (set_attr "length" "4,8")])
7244 (define_split
7245 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7246 (compare:CC
7247 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7248 (match_operand:SI 2 "const_int_operand" ""))
7249 (match_operand:DI 3 "const_int_operand" ""))
7250 (const_int 0)))
7251 (set (match_operand:DI 0 "gpc_reg_operand" "")
7252 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7253 "TARGET_POWERPC64 && reload_completed
7254 && includes_rldic_lshift_p (operands[2], operands[3])"
7255 [(set (match_dup 0)
7256 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7257 (match_dup 3)))
7258 (set (match_dup 4)
7259 (compare:CC (match_dup 0)
7260 (const_int 0)))]
7261 "")
7263 (define_insn "*ashldi3_internal7"
7264 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7265 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7266 (match_operand:SI 2 "const_int_operand" "i"))
7267 (match_operand:DI 3 "mask64_operand" "n")))]
7268 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7269 "rldicr %0,%1,%H2,%S3")
7271 (define_insn "ashldi3_internal8"
7272 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7273 (compare:CC
7274 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7275 (match_operand:SI 2 "const_int_operand" "i,i"))
7276 (match_operand:DI 3 "mask64_operand" "n,n"))
7277 (const_int 0)))
7278 (clobber (match_scratch:DI 4 "=r,r"))]
7279 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7280 "@
7281 rldicr. %4,%1,%H2,%S3
7282 #"
7283 [(set_attr "type" "compare")
7284 (set_attr "length" "4,8")])
7286 (define_split
7287 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7288 (compare:CC
7289 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7290 (match_operand:SI 2 "const_int_operand" ""))
7291 (match_operand:DI 3 "mask64_operand" ""))
7292 (const_int 0)))
7293 (clobber (match_scratch:DI 4 ""))]
7294 "TARGET_POWERPC64 && reload_completed
7295 && includes_rldicr_lshift_p (operands[2], operands[3])"
7296 [(set (match_dup 4)
7297 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7298 (match_dup 3)))
7299 (set (match_dup 0)
7300 (compare:CC (match_dup 4)
7301 (const_int 0)))]
7302 "")
7304 (define_insn "*ashldi3_internal9"
7305 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7306 (compare:CC
7307 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7308 (match_operand:SI 2 "const_int_operand" "i,i"))
7309 (match_operand:DI 3 "mask64_operand" "n,n"))
7310 (const_int 0)))
7311 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7312 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7313 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7314 "@
7315 rldicr. %0,%1,%H2,%S3
7316 #"
7317 [(set_attr "type" "compare")
7318 (set_attr "length" "4,8")])
7320 (define_split
7321 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7322 (compare:CC
7323 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7324 (match_operand:SI 2 "const_int_operand" ""))
7325 (match_operand:DI 3 "mask64_operand" ""))
7326 (const_int 0)))
7327 (set (match_operand:DI 0 "gpc_reg_operand" "")
7328 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7329 "TARGET_POWERPC64 && reload_completed
7330 && includes_rldicr_lshift_p (operands[2], operands[3])"
7331 [(set (match_dup 0)
7332 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7333 (match_dup 3)))
7334 (set (match_dup 4)
7335 (compare:CC (match_dup 0)
7336 (const_int 0)))]
7337 "")
7339 (define_expand "lshrdi3"
7340 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7341 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7342 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7343 "TARGET_POWERPC64 || TARGET_POWER"
7344 "
7345 {
7346 if (TARGET_POWERPC64)
7347 ;
7348 else if (TARGET_POWER)
7349 {
7350 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7351 DONE;
7352 }
7353 else
7354 FAIL;
7355 }")
7357 (define_insn "*lshrdi3_internal1"
7358 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7359 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7360 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7361 "TARGET_POWERPC64"
7362 "@
7363 srd %0,%1,%2
7364 srdi %0,%1,%H2"
7365 [(set_attr "type" "var_shift_rotate,shift")])
7367 (define_insn "*lshrdi3_internal2"
7368 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7369 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7370 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7371 (const_int 0)))
7372 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7373 "TARGET_64BIT "
7374 "@
7375 srd. %3,%1,%2
7376 srdi. %3,%1,%H2
7377 #
7378 #"
7379 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7380 (set_attr "length" "4,4,8,8")])
7382 (define_split
7383 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7384 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7385 (match_operand:SI 2 "reg_or_cint_operand" ""))
7386 (const_int 0)))
7387 (clobber (match_scratch:DI 3 ""))]
7388 "TARGET_POWERPC64 && reload_completed"
7389 [(set (match_dup 3)
7390 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7391 (set (match_dup 0)
7392 (compare:CC (match_dup 3)
7393 (const_int 0)))]
7394 "")
7396 (define_insn "*lshrdi3_internal3"
7397 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7398 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7399 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7400 (const_int 0)))
7401 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7402 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7403 "TARGET_64BIT"
7404 "@
7405 srd. %0,%1,%2
7406 srdi. %0,%1,%H2
7407 #
7408 #"
7409 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7410 (set_attr "length" "4,4,8,8")])
7412 (define_split
7413 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7414 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7415 (match_operand:SI 2 "reg_or_cint_operand" ""))
7416 (const_int 0)))
7417 (set (match_operand:DI 0 "gpc_reg_operand" "")
7418 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7419 "TARGET_POWERPC64 && reload_completed"
7420 [(set (match_dup 0)
7421 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7422 (set (match_dup 3)
7423 (compare:CC (match_dup 0)
7424 (const_int 0)))]
7425 "")
7427 (define_expand "ashrdi3"
7428 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7429 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7430 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7431 "WORDS_BIG_ENDIAN"
7432 "
7433 {
7434 if (TARGET_POWERPC64)
7435 ;
7436 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7437 {
7438 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7439 DONE;
7440 }
7441 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7442 && WORDS_BIG_ENDIAN)
7443 {
7444 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7445 DONE;
7446 }
7447 else
7448 FAIL;
7449 }")
7451 (define_insn "*ashrdi3_internal1"
7452 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7453 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7454 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7455 "TARGET_POWERPC64"
7456 "@
7457 srad %0,%1,%2
7458 sradi %0,%1,%H2"
7459 [(set_attr "type" "var_shift_rotate,shift")])
7461 (define_insn "*ashrdi3_internal2"
7462 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7463 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7464 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7465 (const_int 0)))
7466 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7467 "TARGET_64BIT"
7468 "@
7469 srad. %3,%1,%2
7470 sradi. %3,%1,%H2
7471 #
7472 #"
7473 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7474 (set_attr "length" "4,4,8,8")])
7476 (define_split
7477 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7478 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7479 (match_operand:SI 2 "reg_or_cint_operand" ""))
7480 (const_int 0)))
7481 (clobber (match_scratch:DI 3 ""))]
7482 "TARGET_POWERPC64 && reload_completed"
7483 [(set (match_dup 3)
7484 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7485 (set (match_dup 0)
7486 (compare:CC (match_dup 3)
7487 (const_int 0)))]
7488 "")
7490 (define_insn "*ashrdi3_internal3"
7491 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7492 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7493 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7494 (const_int 0)))
7495 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7496 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7497 "TARGET_64BIT"
7498 "@
7499 srad. %0,%1,%2
7500 sradi. %0,%1,%H2
7501 #
7502 #"
7503 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7504 (set_attr "length" "4,4,8,8")])
7506 (define_split
7507 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7508 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7509 (match_operand:SI 2 "reg_or_cint_operand" ""))
7510 (const_int 0)))
7511 (set (match_operand:DI 0 "gpc_reg_operand" "")
7512 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7513 "TARGET_POWERPC64 && reload_completed"
7514 [(set (match_dup 0)
7515 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7516 (set (match_dup 3)
7517 (compare:CC (match_dup 0)
7518 (const_int 0)))]
7519 "")
7521 (define_insn "anddi3"
7522 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7523 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7524 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7525 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7526 "TARGET_POWERPC64"
7527 "@
7528 and %0,%1,%2
7529 rldic%B2 %0,%1,0,%S2
7530 rlwinm %0,%1,0,%m2,%M2
7531 andi. %0,%1,%b2
7532 andis. %0,%1,%u2
7533 #"
7534 [(set_attr "type" "*,*,*,compare,compare,*")
7535 (set_attr "length" "4,4,4,4,4,8")])
7537 (define_split
7538 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7539 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7540 (match_operand:DI 2 "mask64_2_operand" "")))
7541 (clobber (match_scratch:CC 3 ""))]
7542 "TARGET_POWERPC64
7543 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7544 && !mask_operand (operands[2], DImode)
7545 && !mask64_operand (operands[2], DImode)"
7546 [(set (match_dup 0)
7547 (and:DI (rotate:DI (match_dup 1)
7548 (match_dup 4))
7549 (match_dup 5)))
7550 (set (match_dup 0)
7551 (and:DI (rotate:DI (match_dup 0)
7552 (match_dup 6))
7553 (match_dup 7)))]
7554 {
7555 build_mask64_2_operands (operands[2], &operands[4]);
7556 })
7558 (define_insn "*anddi3_internal2"
7559 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7560 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7561 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7562 (const_int 0)))
7563 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7564 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7565 "TARGET_64BIT"
7566 "@
7567 and. %3,%1,%2
7568 rldic%B2. %3,%1,0,%S2
7569 rlwinm. %3,%1,0,%m2,%M2
7570 andi. %3,%1,%b2
7571 andis. %3,%1,%u2
7572 #
7573 #
7574 #
7575 #
7576 #
7577 #
7578 #"
7579 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7580 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7582 (define_split
7583 [(set (match_operand:CC 0 "cc_reg_operand" "")
7584 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7585 (match_operand:DI 2 "mask64_2_operand" ""))
7586 (const_int 0)))
7587 (clobber (match_scratch:DI 3 ""))
7588 (clobber (match_scratch:CC 4 ""))]
7589 "TARGET_64BIT && reload_completed
7590 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7591 && !mask_operand (operands[2], DImode)
7592 && !mask64_operand (operands[2], DImode)"
7593 [(set (match_dup 3)
7594 (and:DI (rotate:DI (match_dup 1)
7595 (match_dup 5))
7596 (match_dup 6)))
7597 (parallel [(set (match_dup 0)
7598 (compare:CC (and:DI (rotate:DI (match_dup 3)
7599 (match_dup 7))
7600 (match_dup 8))
7601 (const_int 0)))
7602 (clobber (match_dup 3))])]
7603 "
7604 {
7605 build_mask64_2_operands (operands[2], &operands[5]);
7606 }")
7608 (define_insn "*anddi3_internal3"
7609 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7610 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7611 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7612 (const_int 0)))
7613 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7614 (and:DI (match_dup 1) (match_dup 2)))
7615 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7616 "TARGET_64BIT"
7617 "@
7618 and. %0,%1,%2
7619 rldic%B2. %0,%1,0,%S2
7620 rlwinm. %0,%1,0,%m2,%M2
7621 andi. %0,%1,%b2
7622 andis. %0,%1,%u2
7623 #
7624 #
7625 #
7626 #
7627 #
7628 #
7629 #"
7630 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7631 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7633 (define_split
7634 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7635 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7636 (match_operand:DI 2 "and64_2_operand" ""))
7637 (const_int 0)))
7638 (set (match_operand:DI 0 "gpc_reg_operand" "")
7639 (and:DI (match_dup 1) (match_dup 2)))
7640 (clobber (match_scratch:CC 4 ""))]
7641 "TARGET_64BIT && reload_completed"
7642 [(parallel [(set (match_dup 0)
7643 (and:DI (match_dup 1) (match_dup 2)))
7644 (clobber (match_dup 4))])
7645 (set (match_dup 3)
7646 (compare:CC (match_dup 0)
7647 (const_int 0)))]
7648 "")
7650 (define_split
7651 [(set (match_operand:CC 3 "cc_reg_operand" "")
7652 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7653 (match_operand:DI 2 "mask64_2_operand" ""))
7654 (const_int 0)))
7655 (set (match_operand:DI 0 "gpc_reg_operand" "")
7656 (and:DI (match_dup 1) (match_dup 2)))
7657 (clobber (match_scratch:CC 4 ""))]
7658 "TARGET_64BIT && reload_completed
7659 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7660 && !mask_operand (operands[2], DImode)
7661 && !mask64_operand (operands[2], DImode)"
7662 [(set (match_dup 0)
7663 (and:DI (rotate:DI (match_dup 1)
7664 (match_dup 5))
7665 (match_dup 6)))
7666 (parallel [(set (match_dup 3)
7667 (compare:CC (and:DI (rotate:DI (match_dup 0)
7668 (match_dup 7))
7669 (match_dup 8))
7670 (const_int 0)))
7671 (set (match_dup 0)
7672 (and:DI (rotate:DI (match_dup 0)
7673 (match_dup 7))
7674 (match_dup 8)))])]
7675 "
7676 {
7677 build_mask64_2_operands (operands[2], &operands[5]);
7678 }")
7680 (define_expand "iordi3"
7681 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7682 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7683 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7684 "TARGET_POWERPC64"
7685 "
7686 {
7687 if (non_logical_cint_operand (operands[2], DImode))
7688 {
7689 HOST_WIDE_INT value;
7690 rtx tmp = ((!can_create_pseudo_p ()
7691 || rtx_equal_p (operands[0], operands[1]))
7692 ? operands[0] : gen_reg_rtx (DImode));
7694 if (GET_CODE (operands[2]) == CONST_INT)
7695 {
7696 value = INTVAL (operands[2]);
7697 emit_insn (gen_iordi3 (tmp, operands[1],
7698 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7699 }
7700 else
7701 {
7702 value = CONST_DOUBLE_LOW (operands[2]);
7703 emit_insn (gen_iordi3 (tmp, operands[1],
7704 immed_double_const (value
7705 & (~ (HOST_WIDE_INT) 0xffff),
7706 0, DImode)));
7707 }
7709 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7710 DONE;
7711 }
7712 }")
7714 (define_expand "xordi3"
7715 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7716 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7717 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7718 "TARGET_POWERPC64"
7719 "
7720 {
7721 if (non_logical_cint_operand (operands[2], DImode))
7722 {
7723 HOST_WIDE_INT value;
7724 rtx tmp = ((!can_create_pseudo_p ()
7725 || rtx_equal_p (operands[0], operands[1]))
7726 ? operands[0] : gen_reg_rtx (DImode));
7728 if (GET_CODE (operands[2]) == CONST_INT)
7729 {
7730 value = INTVAL (operands[2]);
7731 emit_insn (gen_xordi3 (tmp, operands[1],
7732 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7733 }
7734 else
7735 {
7736 value = CONST_DOUBLE_LOW (operands[2]);
7737 emit_insn (gen_xordi3 (tmp, operands[1],
7738 immed_double_const (value
7739 & (~ (HOST_WIDE_INT) 0xffff),
7740 0, DImode)));
7741 }
7743 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7744 DONE;
7745 }
7746 }")
7748 (define_insn "*booldi3_internal1"
7749 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7750 (match_operator:DI 3 "boolean_or_operator"
7751 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7752 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7753 "TARGET_POWERPC64"
7754 "@
7755 %q3 %0,%1,%2
7756 %q3i %0,%1,%b2
7757 %q3is %0,%1,%u2")
7759 (define_insn "*booldi3_internal2"
7760 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7761 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7762 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7763 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7764 (const_int 0)))
7765 (clobber (match_scratch:DI 3 "=r,r"))]
7766 "TARGET_64BIT"
7767 "@
7768 %q4. %3,%1,%2
7769 #"
7770 [(set_attr "type" "compare")
7771 (set_attr "length" "4,8")])
7773 (define_split
7774 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7775 (compare:CC (match_operator:DI 4 "boolean_operator"
7776 [(match_operand:DI 1 "gpc_reg_operand" "")
7777 (match_operand:DI 2 "gpc_reg_operand" "")])
7778 (const_int 0)))
7779 (clobber (match_scratch:DI 3 ""))]
7780 "TARGET_POWERPC64 && reload_completed"
7781 [(set (match_dup 3) (match_dup 4))
7782 (set (match_dup 0)
7783 (compare:CC (match_dup 3)
7784 (const_int 0)))]
7785 "")
7787 (define_insn "*booldi3_internal3"
7788 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7789 (compare:CC (match_operator:DI 4 "boolean_operator"
7790 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7791 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7792 (const_int 0)))
7793 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7794 (match_dup 4))]
7795 "TARGET_64BIT"
7796 "@
7797 %q4. %0,%1,%2
7798 #"
7799 [(set_attr "type" "compare")
7800 (set_attr "length" "4,8")])
7802 (define_split
7803 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7804 (compare:CC (match_operator:DI 4 "boolean_operator"
7805 [(match_operand:DI 1 "gpc_reg_operand" "")
7806 (match_operand:DI 2 "gpc_reg_operand" "")])
7807 (const_int 0)))
7808 (set (match_operand:DI 0 "gpc_reg_operand" "")
7809 (match_dup 4))]
7810 "TARGET_POWERPC64 && reload_completed"
7811 [(set (match_dup 0) (match_dup 4))
7812 (set (match_dup 3)
7813 (compare:CC (match_dup 0)
7814 (const_int 0)))]
7815 "")
7817 ;; Split a logical operation that we can't do in one insn into two insns,
7818 ;; each of which does one 16-bit part. This is used by combine.
7820 (define_split
7821 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7822 (match_operator:DI 3 "boolean_or_operator"
7823 [(match_operand:DI 1 "gpc_reg_operand" "")
7824 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7825 "TARGET_POWERPC64"
7826 [(set (match_dup 0) (match_dup 4))
7827 (set (match_dup 0) (match_dup 5))]
7828 "
7829 {
7830 rtx i3,i4;
7832 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7833 {
7834 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7835 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7836 0, DImode);
7837 i4 = GEN_INT (value & 0xffff);
7838 }
7839 else
7840 {
7841 i3 = GEN_INT (INTVAL (operands[2])
7842 & (~ (HOST_WIDE_INT) 0xffff));
7843 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7844 }
7845 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7846 operands[1], i3);
7847 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7848 operands[0], i4);
7849 }")
7851 (define_insn "*boolcdi3_internal1"
7852 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7853 (match_operator:DI 3 "boolean_operator"
7854 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7855 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7856 "TARGET_POWERPC64"
7857 "%q3 %0,%2,%1")
7859 (define_insn "*boolcdi3_internal2"
7860 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7861 (compare:CC (match_operator:DI 4 "boolean_operator"
7862 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7863 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7864 (const_int 0)))
7865 (clobber (match_scratch:DI 3 "=r,r"))]
7866 "TARGET_64BIT"
7867 "@
7868 %q4. %3,%2,%1
7869 #"
7870 [(set_attr "type" "compare")
7871 (set_attr "length" "4,8")])
7873 (define_split
7874 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7875 (compare:CC (match_operator:DI 4 "boolean_operator"
7876 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7877 (match_operand:DI 2 "gpc_reg_operand" "")])
7878 (const_int 0)))
7879 (clobber (match_scratch:DI 3 ""))]
7880 "TARGET_POWERPC64 && reload_completed"
7881 [(set (match_dup 3) (match_dup 4))
7882 (set (match_dup 0)
7883 (compare:CC (match_dup 3)
7884 (const_int 0)))]
7885 "")
7887 (define_insn "*boolcdi3_internal3"
7888 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7889 (compare:CC (match_operator:DI 4 "boolean_operator"
7890 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7891 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7892 (const_int 0)))
7893 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7894 (match_dup 4))]
7895 "TARGET_64BIT"
7896 "@
7897 %q4. %0,%2,%1
7898 #"
7899 [(set_attr "type" "compare")
7900 (set_attr "length" "4,8")])
7902 (define_split
7903 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7904 (compare:CC (match_operator:DI 4 "boolean_operator"
7905 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7906 (match_operand:DI 2 "gpc_reg_operand" "")])
7907 (const_int 0)))
7908 (set (match_operand:DI 0 "gpc_reg_operand" "")
7909 (match_dup 4))]
7910 "TARGET_POWERPC64 && reload_completed"
7911 [(set (match_dup 0) (match_dup 4))
7912 (set (match_dup 3)
7913 (compare:CC (match_dup 0)
7914 (const_int 0)))]
7915 "")
7917 (define_insn "*boolccdi3_internal1"
7918 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7919 (match_operator:DI 3 "boolean_operator"
7920 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7921 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7922 "TARGET_POWERPC64"
7923 "%q3 %0,%1,%2")
7925 (define_insn "*boolccdi3_internal2"
7926 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7927 (compare:CC (match_operator:DI 4 "boolean_operator"
7928 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7929 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7930 (const_int 0)))
7931 (clobber (match_scratch:DI 3 "=r,r"))]
7932 "TARGET_64BIT"
7933 "@
7934 %q4. %3,%1,%2
7935 #"
7936 [(set_attr "type" "compare")
7937 (set_attr "length" "4,8")])
7939 (define_split
7940 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7941 (compare:CC (match_operator:DI 4 "boolean_operator"
7942 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7943 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7944 (const_int 0)))
7945 (clobber (match_scratch:DI 3 ""))]
7946 "TARGET_POWERPC64 && reload_completed"
7947 [(set (match_dup 3) (match_dup 4))
7948 (set (match_dup 0)
7949 (compare:CC (match_dup 3)
7950 (const_int 0)))]
7951 "")
7953 (define_insn "*boolccdi3_internal3"
7954 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7955 (compare:CC (match_operator:DI 4 "boolean_operator"
7956 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7957 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7958 (const_int 0)))
7959 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7960 (match_dup 4))]
7961 "TARGET_64BIT"
7962 "@
7963 %q4. %0,%1,%2
7964 #"
7965 [(set_attr "type" "compare")
7966 (set_attr "length" "4,8")])
7968 (define_split
7969 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7970 (compare:CC (match_operator:DI 4 "boolean_operator"
7971 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7972 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7973 (const_int 0)))
7974 (set (match_operand:DI 0 "gpc_reg_operand" "")
7975 (match_dup 4))]
7976 "TARGET_POWERPC64 && reload_completed"
7977 [(set (match_dup 0) (match_dup 4))
7978 (set (match_dup 3)
7979 (compare:CC (match_dup 0)
7980 (const_int 0)))]
7981 "")
7982 \f
7983 ;; Now define ways of moving data around.
7985 ;; Set up a register with a value from the GOT table
7987 (define_expand "movsi_got"
7988 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7989 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7990 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7991 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7992 "
7993 {
7994 if (GET_CODE (operands[1]) == CONST)
7995 {
7996 rtx offset = const0_rtx;
7997 HOST_WIDE_INT value;
7999 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8000 value = INTVAL (offset);
8001 if (value != 0)
8002 {
8003 rtx tmp = (!can_create_pseudo_p ()
8004 ? operands[0]
8005 : gen_reg_rtx (Pmode));
8006 emit_insn (gen_movsi_got (tmp, operands[1]));
8007 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8008 DONE;
8009 }
8010 }
8012 operands[2] = rs6000_got_register (operands[1]);
8013 }")
8015 (define_insn "*movsi_got_internal"
8016 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8017 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8018 (match_operand:SI 2 "gpc_reg_operand" "b")]
8019 UNSPEC_MOVSI_GOT))]
8020 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8021 "{l|lwz} %0,%a1@got(%2)"
8022 [(set_attr "type" "load")])
8024 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8025 ;; didn't get allocated to a hard register.
8026 (define_split
8027 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8028 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8029 (match_operand:SI 2 "memory_operand" "")]
8030 UNSPEC_MOVSI_GOT))]
8031 "DEFAULT_ABI == ABI_V4
8032 && flag_pic == 1
8033 && (reload_in_progress || reload_completed)"
8034 [(set (match_dup 0) (match_dup 2))
8035 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8036 UNSPEC_MOVSI_GOT))]
8037 "")
8039 ;; For SI, we special-case integers that can't be loaded in one insn. We
8040 ;; do the load 16-bits at a time. We could do this by loading from memory,
8041 ;; and this is even supposed to be faster, but it is simpler not to get
8042 ;; integers in the TOC.
8043 (define_insn "movsi_low"
8044 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8045 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8046 (match_operand 2 "" ""))))]
8047 "TARGET_MACHO && ! TARGET_64BIT"
8048 "{l|lwz} %0,lo16(%2)(%1)"
8049 [(set_attr "type" "load")
8050 (set_attr "length" "4")])
8052 (define_insn "*movsi_internal1"
8053 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8054 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8055 "gpc_reg_operand (operands[0], SImode)
8056 || gpc_reg_operand (operands[1], SImode)"
8057 "@
8058 mr %0,%1
8059 {cal|la} %0,%a1
8060 {l%U1%X1|lwz%U1%X1} %0,%1
8061 {st%U0%X0|stw%U0%X0} %1,%0
8062 {lil|li} %0,%1
8063 {liu|lis} %0,%v1
8064 #
8065 {cal|la} %0,%a1
8066 mf%1 %0
8067 mt%0 %1
8068 mt%0 %1
8069 mt%0 %1
8070 {cror 0,0,0|nop}"
8071 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8072 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8074 ;; Split a load of a large constant into the appropriate two-insn
8075 ;; sequence.
8077 (define_split
8078 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8079 (match_operand:SI 1 "const_int_operand" ""))]
8080 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8081 && (INTVAL (operands[1]) & 0xffff) != 0"
8082 [(set (match_dup 0)
8083 (match_dup 2))
8084 (set (match_dup 0)
8085 (ior:SI (match_dup 0)
8086 (match_dup 3)))]
8087 "
8088 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8090 if (tem == operands[0])
8091 DONE;
8092 else
8093 FAIL;
8094 }")
8096 (define_insn "*mov<mode>_internal2"
8097 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8098 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8099 (const_int 0)))
8100 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8101 ""
8102 "@
8103 {cmpi|cmp<wd>i} %2,%0,0
8104 mr. %0,%1
8105 #"
8106 [(set_attr "type" "cmp,compare,cmp")
8107 (set_attr "length" "4,4,8")])
8109 (define_split
8110 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8111 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8112 (const_int 0)))
8113 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8114 "reload_completed"
8115 [(set (match_dup 0) (match_dup 1))
8116 (set (match_dup 2)
8117 (compare:CC (match_dup 0)
8118 (const_int 0)))]
8119 "")
8120 \f
8121 (define_insn "*movhi_internal"
8122 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8123 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8124 "gpc_reg_operand (operands[0], HImode)
8125 || gpc_reg_operand (operands[1], HImode)"
8126 "@
8127 mr %0,%1
8128 lhz%U1%X1 %0,%1
8129 sth%U0%X0 %1,%0
8130 {lil|li} %0,%w1
8131 mf%1 %0
8132 mt%0 %1
8133 mt%0 %1
8134 {cror 0,0,0|nop}"
8135 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8137 (define_expand "mov<mode>"
8138 [(set (match_operand:INT 0 "general_operand" "")
8139 (match_operand:INT 1 "any_operand" ""))]
8140 ""
8141 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8143 (define_insn "*movqi_internal"
8144 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8145 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8146 "gpc_reg_operand (operands[0], QImode)
8147 || gpc_reg_operand (operands[1], QImode)"
8148 "@
8149 mr %0,%1
8150 lbz%U1%X1 %0,%1
8151 stb%U0%X0 %1,%0
8152 {lil|li} %0,%1
8153 mf%1 %0
8154 mt%0 %1
8155 mt%0 %1
8156 {cror 0,0,0|nop}"
8157 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8158 \f
8159 ;; Here is how to move condition codes around. When we store CC data in
8160 ;; an integer register or memory, we store just the high-order 4 bits.
8161 ;; This lets us not shift in the most common case of CR0.
8162 (define_expand "movcc"
8163 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8164 (match_operand:CC 1 "nonimmediate_operand" ""))]
8165 ""
8166 "")
8168 (define_insn "*movcc_internal1"
8169 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8170 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8171 "register_operand (operands[0], CCmode)
8172 || register_operand (operands[1], CCmode)"
8173 "@
8174 mcrf %0,%1
8175 mtcrf 128,%1
8176 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8177 crxor %0,%0,%0
8178 mfcr %0%Q1
8179 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8180 mr %0,%1
8181 {lil|li} %0,%1
8182 mf%1 %0
8183 mt%0 %1
8184 mt%0 %1
8185 {l%U1%X1|lwz%U1%X1} %0,%1
8186 {st%U0%U1|stw%U0%U1} %1,%0"
8187 [(set (attr "type")
8188 (cond [(eq_attr "alternative" "0,3")
8189 (const_string "cr_logical")
8190 (eq_attr "alternative" "1,2")
8191 (const_string "mtcr")
8192 (eq_attr "alternative" "6,7,9")
8193 (const_string "integer")
8194 (eq_attr "alternative" "8")
8195 (const_string "mfjmpr")
8196 (eq_attr "alternative" "10")
8197 (const_string "mtjmpr")
8198 (eq_attr "alternative" "11")
8199 (const_string "load")
8200 (eq_attr "alternative" "12")
8201 (const_string "store")
8202 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8203 (const_string "mfcrf")
8204 ]
8205 (const_string "mfcr")))
8206 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8207 \f
8208 ;; For floating-point, we normally deal with the floating-point registers
8209 ;; unless -msoft-float is used. The sole exception is that parameter passing
8210 ;; can produce floating-point values in fixed-point registers. Unless the
8211 ;; value is a simple constant or already in memory, we deal with this by
8212 ;; allocating memory and copying the value explicitly via that memory location.
8213 (define_expand "movsf"
8214 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8215 (match_operand:SF 1 "any_operand" ""))]
8216 ""
8217 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8219 (define_split
8220 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8221 (match_operand:SF 1 "const_double_operand" ""))]
8222 "reload_completed
8223 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8224 || (GET_CODE (operands[0]) == SUBREG
8225 && GET_CODE (SUBREG_REG (operands[0])) == REG
8226 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8227 [(set (match_dup 2) (match_dup 3))]
8228 "
8229 {
8230 long l;
8231 REAL_VALUE_TYPE rv;
8233 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8234 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8236 if (! TARGET_POWERPC64)
8237 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8238 else
8239 operands[2] = gen_lowpart (SImode, operands[0]);
8241 operands[3] = gen_int_mode (l, SImode);
8242 }")
8244 (define_insn "*movsf_hardfloat"
8245 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8246 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8247 "(gpc_reg_operand (operands[0], SFmode)
8248 || gpc_reg_operand (operands[1], SFmode))
8249 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8250 "@
8251 mr %0,%1
8252 {l%U1%X1|lwz%U1%X1} %0,%1
8253 {st%U0%X0|stw%U0%X0} %1,%0
8254 fmr %0,%1
8255 lfs%U1%X1 %0,%1
8256 stfs%U0%X0 %1,%0
8257 mt%0 %1
8258 mt%0 %1
8259 mf%1 %0
8260 {cror 0,0,0|nop}
8261 #
8262 #"
8263 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8264 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8266 (define_insn "*movsf_softfloat"
8267 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8268 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8269 "(gpc_reg_operand (operands[0], SFmode)
8270 || gpc_reg_operand (operands[1], SFmode))
8271 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8272 "@
8273 mr %0,%1
8274 mt%0 %1
8275 mt%0 %1
8276 mf%1 %0
8277 {l%U1%X1|lwz%U1%X1} %0,%1
8278 {st%U0%X0|stw%U0%X0} %1,%0
8279 {lil|li} %0,%1
8280 {liu|lis} %0,%v1
8281 {cal|la} %0,%a1
8282 #
8283 #
8284 {cror 0,0,0|nop}"
8285 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8286 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8288 \f
8289 (define_expand "movdf"
8290 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8291 (match_operand:DF 1 "any_operand" ""))]
8292 ""
8293 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8295 (define_split
8296 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8297 (match_operand:DF 1 "const_int_operand" ""))]
8298 "! TARGET_POWERPC64 && reload_completed
8299 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8300 || (GET_CODE (operands[0]) == SUBREG
8301 && GET_CODE (SUBREG_REG (operands[0])) == REG
8302 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8303 [(set (match_dup 2) (match_dup 4))
8304 (set (match_dup 3) (match_dup 1))]
8305 "
8306 {
8307 int endian = (WORDS_BIG_ENDIAN == 0);
8308 HOST_WIDE_INT value = INTVAL (operands[1]);
8310 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8311 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8312 #if HOST_BITS_PER_WIDE_INT == 32
8313 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8314 #else
8315 operands[4] = GEN_INT (value >> 32);
8316 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8317 #endif
8318 }")
8320 (define_split
8321 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8322 (match_operand:DF 1 "const_double_operand" ""))]
8323 "! TARGET_POWERPC64 && reload_completed
8324 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8325 || (GET_CODE (operands[0]) == SUBREG
8326 && GET_CODE (SUBREG_REG (operands[0])) == REG
8327 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8328 [(set (match_dup 2) (match_dup 4))
8329 (set (match_dup 3) (match_dup 5))]
8330 "
8331 {
8332 int endian = (WORDS_BIG_ENDIAN == 0);
8333 long l[2];
8334 REAL_VALUE_TYPE rv;
8336 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8337 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8339 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8340 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8341 operands[4] = gen_int_mode (l[endian], SImode);
8342 operands[5] = gen_int_mode (l[1 - endian], SImode);
8343 }")
8345 (define_split
8346 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8347 (match_operand:DF 1 "const_double_operand" ""))]
8348 "TARGET_POWERPC64 && reload_completed
8349 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8350 || (GET_CODE (operands[0]) == SUBREG
8351 && GET_CODE (SUBREG_REG (operands[0])) == REG
8352 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8353 [(set (match_dup 2) (match_dup 3))]
8354 "
8355 {
8356 int endian = (WORDS_BIG_ENDIAN == 0);
8357 long l[2];
8358 REAL_VALUE_TYPE rv;
8359 #if HOST_BITS_PER_WIDE_INT >= 64
8360 HOST_WIDE_INT val;
8361 #endif
8363 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8364 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8366 operands[2] = gen_lowpart (DImode, operands[0]);
8367 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8368 #if HOST_BITS_PER_WIDE_INT >= 64
8369 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8370 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8372 operands[3] = gen_int_mode (val, DImode);
8373 #else
8374 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8375 #endif
8376 }")
8378 ;; Don't have reload use general registers to load a constant. First,
8379 ;; it might not work if the output operand is the equivalent of
8380 ;; a non-offsettable memref, but also it is less efficient than loading
8381 ;; the constant into an FP register, since it will probably be used there.
8382 ;; The "??" is a kludge until we can figure out a more reasonable way
8383 ;; of handling these non-offsettable values.
8384 (define_insn "*movdf_hardfloat32"
8385 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8386 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8387 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8388 && (gpc_reg_operand (operands[0], DFmode)
8389 || gpc_reg_operand (operands[1], DFmode))"
8390 "*
8391 {
8392 switch (which_alternative)
8393 {
8394 default:
8395 gcc_unreachable ();
8396 case 0:
8397 /* We normally copy the low-numbered register first. However, if
8398 the first register operand 0 is the same as the second register
8399 of operand 1, we must copy in the opposite order. */
8400 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8401 return \"mr %L0,%L1\;mr %0,%1\";
8402 else
8403 return \"mr %0,%1\;mr %L0,%L1\";
8404 case 1:
8405 if (rs6000_offsettable_memref_p (operands[1])
8406 || (GET_CODE (operands[1]) == MEM
8407 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8408 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8409 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8410 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
8411 {
8412 /* If the low-address word is used in the address, we must load
8413 it last. Otherwise, load it first. Note that we cannot have
8414 auto-increment in that case since the address register is
8415 known to be dead. */
8416 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8417 operands[1], 0))
8418 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8419 else
8420 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8421 }
8422 else
8423 {
8424 rtx addreg;
8426 addreg = find_addr_reg (XEXP (operands[1], 0));
8427 if (refers_to_regno_p (REGNO (operands[0]),
8428 REGNO (operands[0]) + 1,
8429 operands[1], 0))
8430 {
8431 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8432 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8433 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8434 return \"{l%X1|lwz%X1} %0,%1\";
8435 }
8436 else
8437 {
8438 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
8439 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8440 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8441 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8442 return \"\";
8443 }
8444 }
8445 case 2:
8446 if (rs6000_offsettable_memref_p (operands[0])
8447 || (GET_CODE (operands[0]) == MEM
8448 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8449 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8450 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8451 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8452 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8453 else
8454 {
8455 rtx addreg;
8457 addreg = find_addr_reg (XEXP (operands[0], 0));
8458 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
8459 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8460 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
8461 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8462 return \"\";
8463 }
8464 case 3:
8465 return \"fmr %0,%1\";
8466 case 4:
8467 return \"lfd%U1%X1 %0,%1\";
8468 case 5:
8469 return \"stfd%U0%X0 %1,%0\";
8470 case 6:
8471 case 7:
8472 case 8:
8473 return \"#\";
8474 }
8475 }"
8476 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8477 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8479 (define_insn "*movdf_softfloat32"
8480 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8481 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8482 "! TARGET_POWERPC64
8483 && ((TARGET_FPRS && !TARGET_DOUBLE_FLOAT)
8484 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8485 && (gpc_reg_operand (operands[0], DFmode)
8486 || gpc_reg_operand (operands[1], DFmode))"
8487 "*
8488 {
8489 switch (which_alternative)
8490 {
8491 default:
8492 gcc_unreachable ();
8493 case 0:
8494 /* We normally copy the low-numbered register first. However, if
8495 the first register operand 0 is the same as the second register of
8496 operand 1, we must copy in the opposite order. */
8497 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8498 return \"mr %L0,%L1\;mr %0,%1\";
8499 else
8500 return \"mr %0,%1\;mr %L0,%L1\";
8501 case 1:
8502 /* If the low-address word is used in the address, we must load
8503 it last. Otherwise, load it first. Note that we cannot have
8504 auto-increment in that case since the address register is
8505 known to be dead. */
8506 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8507 operands[1], 0))
8508 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8509 else
8510 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8511 case 2:
8512 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8513 case 3:
8514 case 4:
8515 case 5:
8516 return \"#\";
8517 }
8518 }"
8519 [(set_attr "type" "two,load,store,*,*,*")
8520 (set_attr "length" "8,8,8,8,12,16")])
8522 ; ld/std require word-aligned displacements -> 'Y' constraint.
8523 ; List Y->r and r->Y before r->r for reload.
8524 (define_insn "*movdf_hardfloat64_mfpgpr"
8525 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8526 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8527 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8528 && TARGET_DOUBLE_FLOAT
8529 && (gpc_reg_operand (operands[0], DFmode)
8530 || gpc_reg_operand (operands[1], DFmode))"
8531 "@
8532 std%U0%X0 %1,%0
8533 ld%U1%X1 %0,%1
8534 mr %0,%1
8535 fmr %0,%1
8536 lfd%U1%X1 %0,%1
8537 stfd%U0%X0 %1,%0
8538 mt%0 %1
8539 mf%1 %0
8540 {cror 0,0,0|nop}
8541 #
8542 #
8543 #
8544 mftgpr %0,%1
8545 mffgpr %0,%1"
8546 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8547 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8549 ; ld/std require word-aligned displacements -> 'Y' constraint.
8550 ; List Y->r and r->Y before r->r for reload.
8551 (define_insn "*movdf_hardfloat64"
8552 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8553 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8554 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8555 && TARGET_DOUBLE_FLOAT
8556 && (gpc_reg_operand (operands[0], DFmode)
8557 || gpc_reg_operand (operands[1], DFmode))"
8558 "@
8559 std%U0%X0 %1,%0
8560 ld%U1%X1 %0,%1
8561 mr %0,%1
8562 fmr %0,%1
8563 lfd%U1%X1 %0,%1
8564 stfd%U0%X0 %1,%0
8565 mt%0 %1
8566 mf%1 %0
8567 {cror 0,0,0|nop}
8568 #
8569 #
8570 #"
8571 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8572 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8574 (define_insn "*movdf_softfloat64"
8575 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8576 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8577 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8578 && (gpc_reg_operand (operands[0], DFmode)
8579 || gpc_reg_operand (operands[1], DFmode))"
8580 "@
8581 ld%U1%X1 %0,%1
8582 std%U0%X0 %1,%0
8583 mr %0,%1
8584 mt%0 %1
8585 mf%1 %0
8586 #
8587 #
8588 #
8589 {cror 0,0,0|nop}"
8590 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8591 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8592 \f
8593 (define_expand "movtf"
8594 [(set (match_operand:TF 0 "general_operand" "")
8595 (match_operand:TF 1 "any_operand" ""))]
8596 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8597 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8599 ; It's important to list the o->f and f->o moves before f->f because
8600 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8601 ; which doesn't make progress. Likewise r->Y must be before r->r.
8602 (define_insn_and_split "*movtf_internal"
8603 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8604 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8605 "!TARGET_IEEEQUAD
8606 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8607 && (gpc_reg_operand (operands[0], TFmode)
8608 || gpc_reg_operand (operands[1], TFmode))"
8609 "#"
8610 "&& reload_completed"
8611 [(pc)]
8612 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8613 [(set_attr "length" "8,8,8,20,20,16")])
8615 (define_insn_and_split "*movtf_softfloat"
8616 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8617 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8618 "!TARGET_IEEEQUAD
8619 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8620 && (gpc_reg_operand (operands[0], TFmode)
8621 || gpc_reg_operand (operands[1], TFmode))"
8622 "#"
8623 "&& reload_completed"
8624 [(pc)]
8625 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8626 [(set_attr "length" "20,20,16")])
8628 (define_expand "extenddftf2"
8629 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8630 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8631 "!TARGET_IEEEQUAD
8632 && TARGET_HARD_FLOAT
8633 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8634 && TARGET_LONG_DOUBLE_128"
8635 {
8636 if (TARGET_E500_DOUBLE)
8637 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8638 else
8639 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8640 DONE;
8641 })
8643 (define_expand "extenddftf2_fprs"
8644 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8645 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8646 (use (match_dup 2))])]
8647 "!TARGET_IEEEQUAD
8648 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8649 && TARGET_LONG_DOUBLE_128"
8650 {
8651 operands[2] = CONST0_RTX (DFmode);
8652 /* Generate GOT reference early for SVR4 PIC. */
8653 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8654 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8655 })
8657 (define_insn_and_split "*extenddftf2_internal"
8658 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8659 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8660 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8661 "!TARGET_IEEEQUAD
8662 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8663 && TARGET_LONG_DOUBLE_128"
8664 "#"
8665 "&& reload_completed"
8666 [(pc)]
8667 {
8668 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8669 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8670 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8671 operands[1]);
8672 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8673 operands[2]);
8674 DONE;
8675 })
8677 (define_expand "extendsftf2"
8678 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8679 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8680 "!TARGET_IEEEQUAD
8681 && TARGET_HARD_FLOAT
8682 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8683 && TARGET_LONG_DOUBLE_128"
8684 {
8685 rtx tmp = gen_reg_rtx (DFmode);
8686 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8687 emit_insn (gen_extenddftf2 (operands[0], tmp));
8688 DONE;
8689 })
8691 (define_expand "trunctfdf2"
8692 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8693 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8694 "!TARGET_IEEEQUAD
8695 && TARGET_HARD_FLOAT
8696 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8697 && TARGET_LONG_DOUBLE_128"
8698 "")
8700 (define_insn_and_split "trunctfdf2_internal1"
8701 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8702 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8703 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8704 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8705 "@
8706 #
8707 fmr %0,%1"
8708 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8709 [(const_int 0)]
8710 {
8711 emit_note (NOTE_INSN_DELETED);
8712 DONE;
8713 }
8714 [(set_attr "type" "fp")])
8716 (define_insn "trunctfdf2_internal2"
8717 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8718 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8719 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8720 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8721 && TARGET_LONG_DOUBLE_128"
8722 "fadd %0,%1,%L1"
8723 [(set_attr "type" "fp")])
8725 (define_expand "trunctfsf2"
8726 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8727 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8728 "!TARGET_IEEEQUAD
8729 && TARGET_HARD_FLOAT
8730 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8731 && TARGET_LONG_DOUBLE_128"
8732 {
8733 if (TARGET_E500_DOUBLE)
8734 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8735 else
8736 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8737 DONE;
8738 })
8740 (define_insn_and_split "trunctfsf2_fprs"
8741 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8742 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8743 (clobber (match_scratch:DF 2 "=f"))]
8744 "!TARGET_IEEEQUAD
8745 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8746 && TARGET_LONG_DOUBLE_128"
8747 "#"
8748 "&& reload_completed"
8749 [(set (match_dup 2)
8750 (float_truncate:DF (match_dup 1)))
8751 (set (match_dup 0)
8752 (float_truncate:SF (match_dup 2)))]
8753 "")
8755 (define_expand "floatsitf2"
8756 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8757 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8758 "!TARGET_IEEEQUAD
8759 && TARGET_HARD_FLOAT
8760 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8761 && TARGET_LONG_DOUBLE_128"
8762 {
8763 rtx tmp = gen_reg_rtx (DFmode);
8764 expand_float (tmp, operands[1], false);
8765 emit_insn (gen_extenddftf2 (operands[0], tmp));
8766 DONE;
8767 })
8769 ; fadd, but rounding towards zero.
8770 ; This is probably not the optimal code sequence.
8771 (define_insn "fix_trunc_helper"
8772 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8773 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8774 UNSPEC_FIX_TRUNC_TF))
8775 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8776 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8777 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8778 [(set_attr "type" "fp")
8779 (set_attr "length" "20")])
8781 (define_expand "fix_trunctfsi2"
8782 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8783 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8784 "!TARGET_IEEEQUAD
8785 && (TARGET_POWER2 || TARGET_POWERPC)
8786 && TARGET_HARD_FLOAT
8787 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8788 && TARGET_LONG_DOUBLE_128"
8789 {
8790 if (TARGET_E500_DOUBLE)
8791 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8792 else
8793 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8794 DONE;
8795 })
8797 (define_expand "fix_trunctfsi2_fprs"
8798 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8799 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8800 (clobber (match_dup 2))
8801 (clobber (match_dup 3))
8802 (clobber (match_dup 4))
8803 (clobber (match_dup 5))])]
8804 "!TARGET_IEEEQUAD
8805 && (TARGET_POWER2 || TARGET_POWERPC)
8806 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8807 {
8808 operands[2] = gen_reg_rtx (DFmode);
8809 operands[3] = gen_reg_rtx (DFmode);
8810 operands[4] = gen_reg_rtx (DImode);
8811 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8812 })
8814 (define_insn_and_split "*fix_trunctfsi2_internal"
8815 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8816 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8817 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8818 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8819 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8820 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8821 "!TARGET_IEEEQUAD
8822 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8823 "#"
8824 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
8825 [(pc)]
8826 {
8827 rtx lowword;
8828 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8830 gcc_assert (MEM_P (operands[5]));
8831 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8833 emit_insn (gen_fctiwz (operands[4], operands[2]));
8834 emit_move_insn (operands[5], operands[4]);
8835 emit_move_insn (operands[0], lowword);
8836 DONE;
8837 })
8839 (define_expand "negtf2"
8840 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8841 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8842 "!TARGET_IEEEQUAD
8843 && TARGET_HARD_FLOAT
8844 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8845 && TARGET_LONG_DOUBLE_128"
8846 "")
8848 (define_insn "negtf2_internal"
8849 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8850 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8851 "!TARGET_IEEEQUAD
8852 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8853 "*
8854 {
8855 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8856 return \"fneg %L0,%L1\;fneg %0,%1\";
8857 else
8858 return \"fneg %0,%1\;fneg %L0,%L1\";
8859 }"
8860 [(set_attr "type" "fp")
8861 (set_attr "length" "8")])
8863 (define_expand "abstf2"
8864 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8865 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8866 "!TARGET_IEEEQUAD
8867 && TARGET_HARD_FLOAT
8868 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8869 && TARGET_LONG_DOUBLE_128"
8870 "
8871 {
8872 rtx label = gen_label_rtx ();
8873 if (TARGET_E500_DOUBLE)
8874 {
8875 if (flag_unsafe_math_optimizations)
8876 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8877 else
8878 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8879 }
8880 else
8881 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8882 emit_label (label);
8883 DONE;
8884 }")
8886 (define_expand "abstf2_internal"
8887 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8888 (match_operand:TF 1 "gpc_reg_operand" ""))
8889 (set (match_dup 3) (match_dup 5))
8890 (set (match_dup 5) (abs:DF (match_dup 5)))
8891 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8892 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8893 (label_ref (match_operand 2 "" ""))
8894 (pc)))
8895 (set (match_dup 6) (neg:DF (match_dup 6)))]
8896 "!TARGET_IEEEQUAD
8897 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8898 && TARGET_LONG_DOUBLE_128"
8899 "
8900 {
8901 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8902 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8903 operands[3] = gen_reg_rtx (DFmode);
8904 operands[4] = gen_reg_rtx (CCFPmode);
8905 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8906 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8907 }")
8908 \f
8909 ;; Next come the multi-word integer load and store and the load and store
8910 ;; multiple insns.
8912 ; List r->r after r->"o<>", otherwise reload will try to reload a
8913 ; non-offsettable address by using r->r which won't make progress.
8914 (define_insn "*movdi_internal32"
8915 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8916 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8917 "! TARGET_POWERPC64
8918 && (gpc_reg_operand (operands[0], DImode)
8919 || gpc_reg_operand (operands[1], DImode))"
8920 "@
8921 #
8922 #
8923 #
8924 fmr %0,%1
8925 lfd%U1%X1 %0,%1
8926 stfd%U0%X0 %1,%0
8927 #"
8928 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8930 (define_split
8931 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8932 (match_operand:DI 1 "const_int_operand" ""))]
8933 "! TARGET_POWERPC64 && reload_completed"
8934 [(set (match_dup 2) (match_dup 4))
8935 (set (match_dup 3) (match_dup 1))]
8936 "
8937 {
8938 HOST_WIDE_INT value = INTVAL (operands[1]);
8939 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8940 DImode);
8941 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8942 DImode);
8943 #if HOST_BITS_PER_WIDE_INT == 32
8944 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8945 #else
8946 operands[4] = GEN_INT (value >> 32);
8947 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8948 #endif
8949 }")
8951 (define_split
8952 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
8953 (match_operand:DI 1 "input_operand" ""))]
8954 "reload_completed && !TARGET_POWERPC64
8955 && gpr_or_gpr_p (operands[0], operands[1])"
8956 [(pc)]
8957 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8959 (define_insn "*movdi_mfpgpr"
8960 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8961 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8962 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8963 && (gpc_reg_operand (operands[0], DImode)
8964 || gpc_reg_operand (operands[1], DImode))"
8965 "@
8966 mr %0,%1
8967 ld%U1%X1 %0,%1
8968 std%U0%X0 %1,%0
8969 li %0,%1
8970 lis %0,%v1
8971 #
8972 {cal|la} %0,%a1
8973 fmr %0,%1
8974 lfd%U1%X1 %0,%1
8975 stfd%U0%X0 %1,%0
8976 mf%1 %0
8977 mt%0 %1
8978 {cror 0,0,0|nop}
8979 mftgpr %0,%1
8980 mffgpr %0,%1"
8981 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8982 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8984 (define_insn "*movdi_internal64"
8985 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8986 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8987 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
8988 && (gpc_reg_operand (operands[0], DImode)
8989 || gpc_reg_operand (operands[1], DImode))"
8990 "@
8991 mr %0,%1
8992 ld%U1%X1 %0,%1
8993 std%U0%X0 %1,%0
8994 li %0,%1
8995 lis %0,%v1
8996 #
8997 {cal|la} %0,%a1
8998 fmr %0,%1
8999 lfd%U1%X1 %0,%1
9000 stfd%U0%X0 %1,%0
9001 mf%1 %0
9002 mt%0 %1
9003 {cror 0,0,0|nop}"
9004 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9005 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9007 ;; immediate value valid for a single instruction hiding in a const_double
9008 (define_insn ""
9009 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9010 (match_operand:DI 1 "const_double_operand" "F"))]
9011 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9012 && GET_CODE (operands[1]) == CONST_DOUBLE
9013 && num_insns_constant (operands[1], DImode) == 1"
9014 "*
9015 {
9016 return ((unsigned HOST_WIDE_INT)
9017 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9018 ? \"li %0,%1\" : \"lis %0,%v1\";
9019 }")
9021 ;; Generate all one-bits and clear left or right.
9022 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9023 (define_split
9024 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9025 (match_operand:DI 1 "mask64_operand" ""))]
9026 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9027 [(set (match_dup 0) (const_int -1))
9028 (set (match_dup 0)
9029 (and:DI (rotate:DI (match_dup 0)
9030 (const_int 0))
9031 (match_dup 1)))]
9032 "")
9034 ;; Split a load of a large constant into the appropriate five-instruction
9035 ;; sequence. Handle anything in a constant number of insns.
9036 ;; When non-easy constants can go in the TOC, this should use
9037 ;; easy_fp_constant predicate.
9038 (define_split
9039 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9040 (match_operand:DI 1 "const_int_operand" ""))]
9041 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9042 [(set (match_dup 0) (match_dup 2))
9043 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9044 "
9045 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9047 if (tem == operands[0])
9048 DONE;
9049 else
9050 FAIL;
9051 }")
9053 (define_split
9054 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9055 (match_operand:DI 1 "const_double_operand" ""))]
9056 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9057 [(set (match_dup 0) (match_dup 2))
9058 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9059 "
9060 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9062 if (tem == operands[0])
9063 DONE;
9064 else
9065 FAIL;
9066 }")
9067 \f
9068 ;; TImode is similar, except that we usually want to compute the address into
9069 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9070 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9072 ;; We say that MQ is clobbered in the last alternative because the first
9073 ;; alternative would never get used otherwise since it would need a reload
9074 ;; while the 2nd alternative would not. We put memory cases first so they
9075 ;; are preferred. Otherwise, we'd try to reload the output instead of
9076 ;; giving the SCRATCH mq.
9078 (define_insn "*movti_power"
9079 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9080 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9081 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9082 "TARGET_POWER && ! TARGET_POWERPC64
9083 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9084 "*
9085 {
9086 switch (which_alternative)
9087 {
9088 default:
9089 gcc_unreachable ();
9091 case 0:
9092 if (TARGET_STRING)
9093 return \"{stsi|stswi} %1,%P0,16\";
9094 case 1:
9095 case 2:
9096 return \"#\";
9097 case 3:
9098 /* If the address is not used in the output, we can use lsi. Otherwise,
9099 fall through to generating four loads. */
9100 if (TARGET_STRING
9101 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9102 return \"{lsi|lswi} %0,%P1,16\";
9103 /* ... fall through ... */
9104 case 4:
9105 case 5:
9106 return \"#\";
9107 }
9108 }"
9109 [(set_attr "type" "store,store,*,load,load,*")])
9111 (define_insn "*movti_string"
9112 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9113 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9114 "! TARGET_POWER && ! TARGET_POWERPC64
9115 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9116 "*
9117 {
9118 switch (which_alternative)
9119 {
9120 default:
9121 gcc_unreachable ();
9122 case 0:
9123 if (TARGET_STRING)
9124 return \"{stsi|stswi} %1,%P0,16\";
9125 case 1:
9126 case 2:
9127 return \"#\";
9128 case 3:
9129 /* If the address is not used in the output, we can use lsi. Otherwise,
9130 fall through to generating four loads. */
9131 if (TARGET_STRING
9132 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9133 return \"{lsi|lswi} %0,%P1,16\";
9134 /* ... fall through ... */
9135 case 4:
9136 case 5:
9137 return \"#\";
9138 }
9139 }"
9140 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
9142 (define_insn "*movti_ppc64"
9143 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9144 (match_operand:TI 1 "input_operand" "r,r,m"))]
9145 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9146 || gpc_reg_operand (operands[1], TImode))"
9147 "#"
9148 [(set_attr "type" "*,load,store")])
9150 (define_split
9151 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9152 (match_operand:TI 1 "const_double_operand" ""))]
9153 "TARGET_POWERPC64"
9154 [(set (match_dup 2) (match_dup 4))
9155 (set (match_dup 3) (match_dup 5))]
9156 "
9157 {
9158 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9159 TImode);
9160 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9161 TImode);
9162 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9163 {
9164 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9165 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9166 }
9167 else if (GET_CODE (operands[1]) == CONST_INT)
9168 {
9169 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9170 operands[5] = operands[1];
9171 }
9172 else
9173 FAIL;
9174 }")
9176 (define_split
9177 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9178 (match_operand:TI 1 "input_operand" ""))]
9179 "reload_completed
9180 && gpr_or_gpr_p (operands[0], operands[1])"
9181 [(pc)]
9182 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9183 \f
9184 (define_expand "load_multiple"
9185 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9186 (match_operand:SI 1 "" ""))
9187 (use (match_operand:SI 2 "" ""))])]
9188 "TARGET_STRING && !TARGET_POWERPC64"
9189 "
9190 {
9191 int regno;
9192 int count;
9193 rtx op1;
9194 int i;
9196 /* Support only loading a constant number of fixed-point registers from
9197 memory and only bother with this if more than two; the machine
9198 doesn't support more than eight. */
9199 if (GET_CODE (operands[2]) != CONST_INT
9200 || INTVAL (operands[2]) <= 2
9201 || INTVAL (operands[2]) > 8
9202 || GET_CODE (operands[1]) != MEM
9203 || GET_CODE (operands[0]) != REG
9204 || REGNO (operands[0]) >= 32)
9205 FAIL;
9207 count = INTVAL (operands[2]);
9208 regno = REGNO (operands[0]);
9210 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9211 op1 = replace_equiv_address (operands[1],
9212 force_reg (SImode, XEXP (operands[1], 0)));
9214 for (i = 0; i < count; i++)
9215 XVECEXP (operands[3], 0, i)
9216 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9217 adjust_address_nv (op1, SImode, i * 4));
9218 }")
9220 (define_insn "*ldmsi8"
9221 [(match_parallel 0 "load_multiple_operation"
9222 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9223 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9224 (set (match_operand:SI 3 "gpc_reg_operand" "")
9225 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9226 (set (match_operand:SI 4 "gpc_reg_operand" "")
9227 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9228 (set (match_operand:SI 5 "gpc_reg_operand" "")
9229 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9230 (set (match_operand:SI 6 "gpc_reg_operand" "")
9231 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9232 (set (match_operand:SI 7 "gpc_reg_operand" "")
9233 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9234 (set (match_operand:SI 8 "gpc_reg_operand" "")
9235 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9236 (set (match_operand:SI 9 "gpc_reg_operand" "")
9237 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9238 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9239 "*
9240 { return rs6000_output_load_multiple (operands); }"
9241 [(set_attr "type" "load_ux")
9242 (set_attr "length" "32")])
9244 (define_insn "*ldmsi7"
9245 [(match_parallel 0 "load_multiple_operation"
9246 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9247 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9248 (set (match_operand:SI 3 "gpc_reg_operand" "")
9249 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9250 (set (match_operand:SI 4 "gpc_reg_operand" "")
9251 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9252 (set (match_operand:SI 5 "gpc_reg_operand" "")
9253 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9254 (set (match_operand:SI 6 "gpc_reg_operand" "")
9255 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9256 (set (match_operand:SI 7 "gpc_reg_operand" "")
9257 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9258 (set (match_operand:SI 8 "gpc_reg_operand" "")
9259 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9260 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9261 "*
9262 { return rs6000_output_load_multiple (operands); }"
9263 [(set_attr "type" "load_ux")
9264 (set_attr "length" "32")])
9266 (define_insn "*ldmsi6"
9267 [(match_parallel 0 "load_multiple_operation"
9268 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9269 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9270 (set (match_operand:SI 3 "gpc_reg_operand" "")
9271 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9272 (set (match_operand:SI 4 "gpc_reg_operand" "")
9273 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9274 (set (match_operand:SI 5 "gpc_reg_operand" "")
9275 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9276 (set (match_operand:SI 6 "gpc_reg_operand" "")
9277 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9278 (set (match_operand:SI 7 "gpc_reg_operand" "")
9279 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9280 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9281 "*
9282 { return rs6000_output_load_multiple (operands); }"
9283 [(set_attr "type" "load_ux")
9284 (set_attr "length" "32")])
9286 (define_insn "*ldmsi5"
9287 [(match_parallel 0 "load_multiple_operation"
9288 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9289 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9290 (set (match_operand:SI 3 "gpc_reg_operand" "")
9291 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9292 (set (match_operand:SI 4 "gpc_reg_operand" "")
9293 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9294 (set (match_operand:SI 5 "gpc_reg_operand" "")
9295 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9296 (set (match_operand:SI 6 "gpc_reg_operand" "")
9297 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9298 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9299 "*
9300 { return rs6000_output_load_multiple (operands); }"
9301 [(set_attr "type" "load_ux")
9302 (set_attr "length" "32")])
9304 (define_insn "*ldmsi4"
9305 [(match_parallel 0 "load_multiple_operation"
9306 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9307 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9308 (set (match_operand:SI 3 "gpc_reg_operand" "")
9309 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9310 (set (match_operand:SI 4 "gpc_reg_operand" "")
9311 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9312 (set (match_operand:SI 5 "gpc_reg_operand" "")
9313 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9314 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9315 "*
9316 { return rs6000_output_load_multiple (operands); }"
9317 [(set_attr "type" "load_ux")
9318 (set_attr "length" "32")])
9320 (define_insn "*ldmsi3"
9321 [(match_parallel 0 "load_multiple_operation"
9322 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9323 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9324 (set (match_operand:SI 3 "gpc_reg_operand" "")
9325 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9326 (set (match_operand:SI 4 "gpc_reg_operand" "")
9327 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9328 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9329 "*
9330 { return rs6000_output_load_multiple (operands); }"
9331 [(set_attr "type" "load_ux")
9332 (set_attr "length" "32")])
9334 (define_expand "store_multiple"
9335 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9336 (match_operand:SI 1 "" ""))
9337 (clobber (scratch:SI))
9338 (use (match_operand:SI 2 "" ""))])]
9339 "TARGET_STRING && !TARGET_POWERPC64"
9340 "
9341 {
9342 int regno;
9343 int count;
9344 rtx to;
9345 rtx op0;
9346 int i;
9348 /* Support only storing a constant number of fixed-point registers to
9349 memory and only bother with this if more than two; the machine
9350 doesn't support more than eight. */
9351 if (GET_CODE (operands[2]) != CONST_INT
9352 || INTVAL (operands[2]) <= 2
9353 || INTVAL (operands[2]) > 8
9354 || GET_CODE (operands[0]) != MEM
9355 || GET_CODE (operands[1]) != REG
9356 || REGNO (operands[1]) >= 32)
9357 FAIL;
9359 count = INTVAL (operands[2]);
9360 regno = REGNO (operands[1]);
9362 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9363 to = force_reg (SImode, XEXP (operands[0], 0));
9364 op0 = replace_equiv_address (operands[0], to);
9366 XVECEXP (operands[3], 0, 0)
9367 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9368 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9369 gen_rtx_SCRATCH (SImode));
9371 for (i = 1; i < count; i++)
9372 XVECEXP (operands[3], 0, i + 1)
9373 = gen_rtx_SET (VOIDmode,
9374 adjust_address_nv (op0, SImode, i * 4),
9375 gen_rtx_REG (SImode, regno + i));
9376 }")
9378 (define_insn "*stmsi8"
9379 [(match_parallel 0 "store_multiple_operation"
9380 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9381 (match_operand:SI 2 "gpc_reg_operand" "r"))
9382 (clobber (match_scratch:SI 3 "=X"))
9383 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9384 (match_operand:SI 4 "gpc_reg_operand" "r"))
9385 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9386 (match_operand:SI 5 "gpc_reg_operand" "r"))
9387 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9388 (match_operand:SI 6 "gpc_reg_operand" "r"))
9389 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9390 (match_operand:SI 7 "gpc_reg_operand" "r"))
9391 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9392 (match_operand:SI 8 "gpc_reg_operand" "r"))
9393 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9394 (match_operand:SI 9 "gpc_reg_operand" "r"))
9395 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9396 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9397 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9398 "{stsi|stswi} %2,%1,%O0"
9399 [(set_attr "type" "store_ux")])
9401 (define_insn "*stmsi7"
9402 [(match_parallel 0 "store_multiple_operation"
9403 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9404 (match_operand:SI 2 "gpc_reg_operand" "r"))
9405 (clobber (match_scratch:SI 3 "=X"))
9406 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9407 (match_operand:SI 4 "gpc_reg_operand" "r"))
9408 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9409 (match_operand:SI 5 "gpc_reg_operand" "r"))
9410 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9411 (match_operand:SI 6 "gpc_reg_operand" "r"))
9412 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9413 (match_operand:SI 7 "gpc_reg_operand" "r"))
9414 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9415 (match_operand:SI 8 "gpc_reg_operand" "r"))
9416 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9417 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9418 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9419 "{stsi|stswi} %2,%1,%O0"
9420 [(set_attr "type" "store_ux")])
9422 (define_insn "*stmsi6"
9423 [(match_parallel 0 "store_multiple_operation"
9424 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9425 (match_operand:SI 2 "gpc_reg_operand" "r"))
9426 (clobber (match_scratch:SI 3 "=X"))
9427 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9428 (match_operand:SI 4 "gpc_reg_operand" "r"))
9429 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9430 (match_operand:SI 5 "gpc_reg_operand" "r"))
9431 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9432 (match_operand:SI 6 "gpc_reg_operand" "r"))
9433 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9434 (match_operand:SI 7 "gpc_reg_operand" "r"))
9435 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9436 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9437 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9438 "{stsi|stswi} %2,%1,%O0"
9439 [(set_attr "type" "store_ux")])
9441 (define_insn "*stmsi5"
9442 [(match_parallel 0 "store_multiple_operation"
9443 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9444 (match_operand:SI 2 "gpc_reg_operand" "r"))
9445 (clobber (match_scratch:SI 3 "=X"))
9446 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9447 (match_operand:SI 4 "gpc_reg_operand" "r"))
9448 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9449 (match_operand:SI 5 "gpc_reg_operand" "r"))
9450 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9451 (match_operand:SI 6 "gpc_reg_operand" "r"))
9452 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9453 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9454 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9455 "{stsi|stswi} %2,%1,%O0"
9456 [(set_attr "type" "store_ux")])
9458 (define_insn "*stmsi4"
9459 [(match_parallel 0 "store_multiple_operation"
9460 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9461 (match_operand:SI 2 "gpc_reg_operand" "r"))
9462 (clobber (match_scratch:SI 3 "=X"))
9463 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9464 (match_operand:SI 4 "gpc_reg_operand" "r"))
9465 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9466 (match_operand:SI 5 "gpc_reg_operand" "r"))
9467 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9468 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9469 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9470 "{stsi|stswi} %2,%1,%O0"
9471 [(set_attr "type" "store_ux")])
9473 (define_insn "*stmsi3"
9474 [(match_parallel 0 "store_multiple_operation"
9475 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9476 (match_operand:SI 2 "gpc_reg_operand" "r"))
9477 (clobber (match_scratch:SI 3 "=X"))
9478 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9479 (match_operand:SI 4 "gpc_reg_operand" "r"))
9480 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9481 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9482 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9483 "{stsi|stswi} %2,%1,%O0"
9484 [(set_attr "type" "store_ux")])
9486 (define_insn "*stmsi8_power"
9487 [(match_parallel 0 "store_multiple_operation"
9488 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9489 (match_operand:SI 2 "gpc_reg_operand" "r"))
9490 (clobber (match_scratch:SI 3 "=q"))
9491 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9492 (match_operand:SI 4 "gpc_reg_operand" "r"))
9493 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9494 (match_operand:SI 5 "gpc_reg_operand" "r"))
9495 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9496 (match_operand:SI 6 "gpc_reg_operand" "r"))
9497 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9498 (match_operand:SI 7 "gpc_reg_operand" "r"))
9499 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9500 (match_operand:SI 8 "gpc_reg_operand" "r"))
9501 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9502 (match_operand:SI 9 "gpc_reg_operand" "r"))
9503 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9504 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9505 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9506 "{stsi|stswi} %2,%1,%O0"
9507 [(set_attr "type" "store_ux")])
9509 (define_insn "*stmsi7_power"
9510 [(match_parallel 0 "store_multiple_operation"
9511 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9512 (match_operand:SI 2 "gpc_reg_operand" "r"))
9513 (clobber (match_scratch:SI 3 "=q"))
9514 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9515 (match_operand:SI 4 "gpc_reg_operand" "r"))
9516 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9517 (match_operand:SI 5 "gpc_reg_operand" "r"))
9518 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9519 (match_operand:SI 6 "gpc_reg_operand" "r"))
9520 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9521 (match_operand:SI 7 "gpc_reg_operand" "r"))
9522 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9523 (match_operand:SI 8 "gpc_reg_operand" "r"))
9524 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9525 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9526 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9527 "{stsi|stswi} %2,%1,%O0"
9528 [(set_attr "type" "store_ux")])
9530 (define_insn "*stmsi6_power"
9531 [(match_parallel 0 "store_multiple_operation"
9532 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9533 (match_operand:SI 2 "gpc_reg_operand" "r"))
9534 (clobber (match_scratch:SI 3 "=q"))
9535 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9536 (match_operand:SI 4 "gpc_reg_operand" "r"))
9537 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9538 (match_operand:SI 5 "gpc_reg_operand" "r"))
9539 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9540 (match_operand:SI 6 "gpc_reg_operand" "r"))
9541 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9542 (match_operand:SI 7 "gpc_reg_operand" "r"))
9543 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9544 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9545 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9546 "{stsi|stswi} %2,%1,%O0"
9547 [(set_attr "type" "store_ux")])
9549 (define_insn "*stmsi5_power"
9550 [(match_parallel 0 "store_multiple_operation"
9551 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9552 (match_operand:SI 2 "gpc_reg_operand" "r"))
9553 (clobber (match_scratch:SI 3 "=q"))
9554 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9555 (match_operand:SI 4 "gpc_reg_operand" "r"))
9556 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9557 (match_operand:SI 5 "gpc_reg_operand" "r"))
9558 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9559 (match_operand:SI 6 "gpc_reg_operand" "r"))
9560 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9561 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9562 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9563 "{stsi|stswi} %2,%1,%O0"
9564 [(set_attr "type" "store_ux")])
9566 (define_insn "*stmsi4_power"
9567 [(match_parallel 0 "store_multiple_operation"
9568 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9569 (match_operand:SI 2 "gpc_reg_operand" "r"))
9570 (clobber (match_scratch:SI 3 "=q"))
9571 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9572 (match_operand:SI 4 "gpc_reg_operand" "r"))
9573 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9574 (match_operand:SI 5 "gpc_reg_operand" "r"))
9575 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9576 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9577 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9578 "{stsi|stswi} %2,%1,%O0"
9579 [(set_attr "type" "store_ux")])
9581 (define_insn "*stmsi3_power"
9582 [(match_parallel 0 "store_multiple_operation"
9583 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9584 (match_operand:SI 2 "gpc_reg_operand" "r"))
9585 (clobber (match_scratch:SI 3 "=q"))
9586 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9587 (match_operand:SI 4 "gpc_reg_operand" "r"))
9588 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9589 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9590 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9591 "{stsi|stswi} %2,%1,%O0"
9592 [(set_attr "type" "store_ux")])
9593 \f
9594 (define_expand "setmemsi"
9595 [(parallel [(set (match_operand:BLK 0 "" "")
9596 (match_operand 2 "const_int_operand" ""))
9597 (use (match_operand:SI 1 "" ""))
9598 (use (match_operand:SI 3 "" ""))])]
9599 ""
9600 "
9601 {
9602 /* If value to set is not zero, use the library routine. */
9603 if (operands[2] != const0_rtx)
9604 FAIL;
9606 if (expand_block_clear (operands))
9607 DONE;
9608 else
9609 FAIL;
9610 }")
9612 ;; String/block move insn.
9613 ;; Argument 0 is the destination
9614 ;; Argument 1 is the source
9615 ;; Argument 2 is the length
9616 ;; Argument 3 is the alignment
9618 (define_expand "movmemsi"
9619 [(parallel [(set (match_operand:BLK 0 "" "")
9620 (match_operand:BLK 1 "" ""))
9621 (use (match_operand:SI 2 "" ""))
9622 (use (match_operand:SI 3 "" ""))])]
9623 ""
9624 "
9625 {
9626 if (expand_block_move (operands))
9627 DONE;
9628 else
9629 FAIL;
9630 }")
9632 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9633 ;; register allocator doesn't have a clue about allocating 8 word registers.
9634 ;; rD/rS = r5 is preferred, efficient form.
9635 (define_expand "movmemsi_8reg"
9636 [(parallel [(set (match_operand 0 "" "")
9637 (match_operand 1 "" ""))
9638 (use (match_operand 2 "" ""))
9639 (use (match_operand 3 "" ""))
9640 (clobber (reg:SI 5))
9641 (clobber (reg:SI 6))
9642 (clobber (reg:SI 7))
9643 (clobber (reg:SI 8))
9644 (clobber (reg:SI 9))
9645 (clobber (reg:SI 10))
9646 (clobber (reg:SI 11))
9647 (clobber (reg:SI 12))
9648 (clobber (match_scratch:SI 4 ""))])]
9649 "TARGET_STRING"
9650 "")
9652 (define_insn ""
9653 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9654 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9655 (use (match_operand:SI 2 "immediate_operand" "i"))
9656 (use (match_operand:SI 3 "immediate_operand" "i"))
9657 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9658 (clobber (reg:SI 6))
9659 (clobber (reg:SI 7))
9660 (clobber (reg:SI 8))
9661 (clobber (reg:SI 9))
9662 (clobber (reg:SI 10))
9663 (clobber (reg:SI 11))
9664 (clobber (reg:SI 12))
9665 (clobber (match_scratch:SI 5 "=q"))]
9666 "TARGET_STRING && TARGET_POWER
9667 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9668 || INTVAL (operands[2]) == 0)
9669 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9670 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9671 && REGNO (operands[4]) == 5"
9672 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9673 [(set_attr "type" "store_ux")
9674 (set_attr "length" "8")])
9676 (define_insn ""
9677 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9678 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9679 (use (match_operand:SI 2 "immediate_operand" "i"))
9680 (use (match_operand:SI 3 "immediate_operand" "i"))
9681 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9682 (clobber (reg:SI 6))
9683 (clobber (reg:SI 7))
9684 (clobber (reg:SI 8))
9685 (clobber (reg:SI 9))
9686 (clobber (reg:SI 10))
9687 (clobber (reg:SI 11))
9688 (clobber (reg:SI 12))
9689 (clobber (match_scratch:SI 5 "=X"))]
9690 "TARGET_STRING && ! TARGET_POWER
9691 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9692 || INTVAL (operands[2]) == 0)
9693 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9694 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9695 && REGNO (operands[4]) == 5"
9696 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9697 [(set_attr "type" "store_ux")
9698 (set_attr "length" "8")])
9700 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9701 ;; register allocator doesn't have a clue about allocating 6 word registers.
9702 ;; rD/rS = r5 is preferred, efficient form.
9703 (define_expand "movmemsi_6reg"
9704 [(parallel [(set (match_operand 0 "" "")
9705 (match_operand 1 "" ""))
9706 (use (match_operand 2 "" ""))
9707 (use (match_operand 3 "" ""))
9708 (clobber (reg:SI 5))
9709 (clobber (reg:SI 6))
9710 (clobber (reg:SI 7))
9711 (clobber (reg:SI 8))
9712 (clobber (reg:SI 9))
9713 (clobber (reg:SI 10))
9714 (clobber (match_scratch:SI 4 ""))])]
9715 "TARGET_STRING"
9716 "")
9718 (define_insn ""
9719 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9720 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9721 (use (match_operand:SI 2 "immediate_operand" "i"))
9722 (use (match_operand:SI 3 "immediate_operand" "i"))
9723 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9724 (clobber (reg:SI 6))
9725 (clobber (reg:SI 7))
9726 (clobber (reg:SI 8))
9727 (clobber (reg:SI 9))
9728 (clobber (reg:SI 10))
9729 (clobber (match_scratch:SI 5 "=q"))]
9730 "TARGET_STRING && TARGET_POWER
9731 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9732 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9733 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9734 && REGNO (operands[4]) == 5"
9735 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9736 [(set_attr "type" "store_ux")
9737 (set_attr "length" "8")])
9739 (define_insn ""
9740 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9741 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9742 (use (match_operand:SI 2 "immediate_operand" "i"))
9743 (use (match_operand:SI 3 "immediate_operand" "i"))
9744 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9745 (clobber (reg:SI 6))
9746 (clobber (reg:SI 7))
9747 (clobber (reg:SI 8))
9748 (clobber (reg:SI 9))
9749 (clobber (reg:SI 10))
9750 (clobber (match_scratch:SI 5 "=X"))]
9751 "TARGET_STRING && ! TARGET_POWER
9752 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9753 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9754 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9755 && REGNO (operands[4]) == 5"
9756 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9757 [(set_attr "type" "store_ux")
9758 (set_attr "length" "8")])
9760 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9761 ;; problems with TImode.
9762 ;; rD/rS = r5 is preferred, efficient form.
9763 (define_expand "movmemsi_4reg"
9764 [(parallel [(set (match_operand 0 "" "")
9765 (match_operand 1 "" ""))
9766 (use (match_operand 2 "" ""))
9767 (use (match_operand 3 "" ""))
9768 (clobber (reg:SI 5))
9769 (clobber (reg:SI 6))
9770 (clobber (reg:SI 7))
9771 (clobber (reg:SI 8))
9772 (clobber (match_scratch:SI 4 ""))])]
9773 "TARGET_STRING"
9774 "")
9776 (define_insn ""
9777 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9778 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9779 (use (match_operand:SI 2 "immediate_operand" "i"))
9780 (use (match_operand:SI 3 "immediate_operand" "i"))
9781 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9782 (clobber (reg:SI 6))
9783 (clobber (reg:SI 7))
9784 (clobber (reg:SI 8))
9785 (clobber (match_scratch:SI 5 "=q"))]
9786 "TARGET_STRING && TARGET_POWER
9787 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9788 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9789 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9790 && REGNO (operands[4]) == 5"
9791 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9792 [(set_attr "type" "store_ux")
9793 (set_attr "length" "8")])
9795 (define_insn ""
9796 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9797 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9798 (use (match_operand:SI 2 "immediate_operand" "i"))
9799 (use (match_operand:SI 3 "immediate_operand" "i"))
9800 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9801 (clobber (reg:SI 6))
9802 (clobber (reg:SI 7))
9803 (clobber (reg:SI 8))
9804 (clobber (match_scratch:SI 5 "=X"))]
9805 "TARGET_STRING && ! TARGET_POWER
9806 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9807 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9808 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9809 && REGNO (operands[4]) == 5"
9810 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9811 [(set_attr "type" "store_ux")
9812 (set_attr "length" "8")])
9814 ;; Move up to 8 bytes at a time.
9815 (define_expand "movmemsi_2reg"
9816 [(parallel [(set (match_operand 0 "" "")
9817 (match_operand 1 "" ""))
9818 (use (match_operand 2 "" ""))
9819 (use (match_operand 3 "" ""))
9820 (clobber (match_scratch:DI 4 ""))
9821 (clobber (match_scratch:SI 5 ""))])]
9822 "TARGET_STRING && ! TARGET_POWERPC64"
9823 "")
9825 (define_insn ""
9826 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9827 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9828 (use (match_operand:SI 2 "immediate_operand" "i"))
9829 (use (match_operand:SI 3 "immediate_operand" "i"))
9830 (clobber (match_scratch:DI 4 "=&r"))
9831 (clobber (match_scratch:SI 5 "=q"))]
9832 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9833 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9834 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9835 [(set_attr "type" "store_ux")
9836 (set_attr "length" "8")])
9838 (define_insn ""
9839 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9840 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9841 (use (match_operand:SI 2 "immediate_operand" "i"))
9842 (use (match_operand:SI 3 "immediate_operand" "i"))
9843 (clobber (match_scratch:DI 4 "=&r"))
9844 (clobber (match_scratch:SI 5 "=X"))]
9845 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9846 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9847 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9848 [(set_attr "type" "store_ux")
9849 (set_attr "length" "8")])
9851 ;; Move up to 4 bytes at a time.
9852 (define_expand "movmemsi_1reg"
9853 [(parallel [(set (match_operand 0 "" "")
9854 (match_operand 1 "" ""))
9855 (use (match_operand 2 "" ""))
9856 (use (match_operand 3 "" ""))
9857 (clobber (match_scratch:SI 4 ""))
9858 (clobber (match_scratch:SI 5 ""))])]
9859 "TARGET_STRING"
9860 "")
9862 (define_insn ""
9863 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9864 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9865 (use (match_operand:SI 2 "immediate_operand" "i"))
9866 (use (match_operand:SI 3 "immediate_operand" "i"))
9867 (clobber (match_scratch:SI 4 "=&r"))
9868 (clobber (match_scratch:SI 5 "=q"))]
9869 "TARGET_STRING && TARGET_POWER
9870 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9871 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9872 [(set_attr "type" "store_ux")
9873 (set_attr "length" "8")])
9875 (define_insn ""
9876 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9877 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9878 (use (match_operand:SI 2 "immediate_operand" "i"))
9879 (use (match_operand:SI 3 "immediate_operand" "i"))
9880 (clobber (match_scratch:SI 4 "=&r"))
9881 (clobber (match_scratch:SI 5 "=X"))]
9882 "TARGET_STRING && ! TARGET_POWER
9883 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9884 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9885 [(set_attr "type" "store_ux")
9886 (set_attr "length" "8")])
9887 \f
9888 ;; Define insns that do load or store with update. Some of these we can
9889 ;; get by using pre-decrement or pre-increment, but the hardware can also
9890 ;; do cases where the increment is not the size of the object.
9891 ;;
9892 ;; In all these cases, we use operands 0 and 1 for the register being
9893 ;; incremented because those are the operands that local-alloc will
9894 ;; tie and these are the pair most likely to be tieable (and the ones
9895 ;; that will benefit the most).
9897 (define_insn "*movdi_update1"
9898 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9899 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9900 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9901 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9902 (plus:DI (match_dup 1) (match_dup 2)))]
9903 "TARGET_POWERPC64 && TARGET_UPDATE"
9904 "@
9905 ldux %3,%0,%2
9906 ldu %3,%2(%0)"
9907 [(set_attr "type" "load_ux,load_u")])
9909 (define_insn "movdi_<mode>_update"
9910 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9911 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9912 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9913 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9914 (plus:P (match_dup 1) (match_dup 2)))]
9915 "TARGET_POWERPC64 && TARGET_UPDATE"
9916 "@
9917 stdux %3,%0,%2
9918 stdu %3,%2(%0)"
9919 [(set_attr "type" "store_ux,store_u")])
9921 (define_insn "*movsi_update1"
9922 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9923 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9924 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9925 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9926 (plus:SI (match_dup 1) (match_dup 2)))]
9927 "TARGET_UPDATE"
9928 "@
9929 {lux|lwzux} %3,%0,%2
9930 {lu|lwzu} %3,%2(%0)"
9931 [(set_attr "type" "load_ux,load_u")])
9933 (define_insn "*movsi_update2"
9934 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9935 (sign_extend:DI
9936 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9937 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9938 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9939 (plus:DI (match_dup 1) (match_dup 2)))]
9940 "TARGET_POWERPC64"
9941 "lwaux %3,%0,%2"
9942 [(set_attr "type" "load_ext_ux")])
9944 (define_insn "movsi_update"
9945 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9946 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9947 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9948 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9949 (plus:SI (match_dup 1) (match_dup 2)))]
9950 "TARGET_UPDATE"
9951 "@
9952 {stux|stwux} %3,%0,%2
9953 {stu|stwu} %3,%2(%0)"
9954 [(set_attr "type" "store_ux,store_u")])
9956 (define_insn "*movhi_update1"
9957 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9958 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9959 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9960 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9961 (plus:SI (match_dup 1) (match_dup 2)))]
9962 "TARGET_UPDATE"
9963 "@
9964 lhzux %3,%0,%2
9965 lhzu %3,%2(%0)"
9966 [(set_attr "type" "load_ux,load_u")])
9968 (define_insn "*movhi_update2"
9969 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9970 (zero_extend:SI
9971 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9972 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9973 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9974 (plus:SI (match_dup 1) (match_dup 2)))]
9975 "TARGET_UPDATE"
9976 "@
9977 lhzux %3,%0,%2
9978 lhzu %3,%2(%0)"
9979 [(set_attr "type" "load_ux,load_u")])
9981 (define_insn "*movhi_update3"
9982 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9983 (sign_extend:SI
9984 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9985 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9986 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9987 (plus:SI (match_dup 1) (match_dup 2)))]
9988 "TARGET_UPDATE"
9989 "@
9990 lhaux %3,%0,%2
9991 lhau %3,%2(%0)"
9992 [(set_attr "type" "load_ext_ux,load_ext_u")])
9994 (define_insn "*movhi_update4"
9995 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9996 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9997 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9998 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9999 (plus:SI (match_dup 1) (match_dup 2)))]
10000 "TARGET_UPDATE"
10001 "@
10002 sthux %3,%0,%2
10003 sthu %3,%2(%0)"
10004 [(set_attr "type" "store_ux,store_u")])
10006 (define_insn "*movqi_update1"
10007 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10008 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10009 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10010 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10011 (plus:SI (match_dup 1) (match_dup 2)))]
10012 "TARGET_UPDATE"
10013 "@
10014 lbzux %3,%0,%2
10015 lbzu %3,%2(%0)"
10016 [(set_attr "type" "load_ux,load_u")])
10018 (define_insn "*movqi_update2"
10019 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10020 (zero_extend:SI
10021 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10022 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10023 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10024 (plus:SI (match_dup 1) (match_dup 2)))]
10025 "TARGET_UPDATE"
10026 "@
10027 lbzux %3,%0,%2
10028 lbzu %3,%2(%0)"
10029 [(set_attr "type" "load_ux,load_u")])
10031 (define_insn "*movqi_update3"
10032 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10033 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10034 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10035 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10036 (plus:SI (match_dup 1) (match_dup 2)))]
10037 "TARGET_UPDATE"
10038 "@
10039 stbux %3,%0,%2
10040 stbu %3,%2(%0)"
10041 [(set_attr "type" "store_ux,store_u")])
10043 (define_insn "*movsf_update1"
10044 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10045 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10046 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10047 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10048 (plus:SI (match_dup 1) (match_dup 2)))]
10049 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE"
10050 "@
10051 lfsux %3,%0,%2
10052 lfsu %3,%2(%0)"
10053 [(set_attr "type" "fpload_ux,fpload_u")])
10055 (define_insn "*movsf_update2"
10056 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10057 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10058 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10059 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10060 (plus:SI (match_dup 1) (match_dup 2)))]
10061 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE"
10062 "@
10063 stfsux %3,%0,%2
10064 stfsu %3,%2(%0)"
10065 [(set_attr "type" "fpstore_ux,fpstore_u")])
10067 (define_insn "*movsf_update3"
10068 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10069 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10070 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10071 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10072 (plus:SI (match_dup 1) (match_dup 2)))]
10073 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10074 "@
10075 {lux|lwzux} %3,%0,%2
10076 {lu|lwzu} %3,%2(%0)"
10077 [(set_attr "type" "load_ux,load_u")])
10079 (define_insn "*movsf_update4"
10080 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10081 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10082 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10083 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10084 (plus:SI (match_dup 1) (match_dup 2)))]
10085 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10086 "@
10087 {stux|stwux} %3,%0,%2
10088 {stu|stwu} %3,%2(%0)"
10089 [(set_attr "type" "store_ux,store_u")])
10091 (define_insn "*movdf_update1"
10092 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10093 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10094 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10095 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10096 (plus:SI (match_dup 1) (match_dup 2)))]
10097 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE"
10098 "@
10099 lfdux %3,%0,%2
10100 lfdu %3,%2(%0)"
10101 [(set_attr "type" "fpload_ux,fpload_u")])
10103 (define_insn "*movdf_update2"
10104 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10105 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10106 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10107 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10108 (plus:SI (match_dup 1) (match_dup 2)))]
10109 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE"
10110 "@
10111 stfdux %3,%0,%2
10112 stfdu %3,%2(%0)"
10113 [(set_attr "type" "fpstore_ux,fpstore_u")])
10115 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10117 (define_insn "*lfq_power2"
10118 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10119 (match_operand:V2DF 1 "memory_operand" ""))]
10120 "TARGET_POWER2
10121 && TARGET_HARD_FLOAT && TARGET_FPRS"
10122 "lfq%U1%X1 %0,%1")
10124 (define_peephole2
10125 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10126 (match_operand:DF 1 "memory_operand" ""))
10127 (set (match_operand:DF 2 "gpc_reg_operand" "")
10128 (match_operand:DF 3 "memory_operand" ""))]
10129 "TARGET_POWER2
10130 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10131 && registers_ok_for_quad_peep (operands[0], operands[2])
10132 && mems_ok_for_quad_peep (operands[1], operands[3])"
10133 [(set (match_dup 0)
10134 (match_dup 1))]
10135 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10136 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10138 (define_insn "*stfq_power2"
10139 [(set (match_operand:V2DF 0 "memory_operand" "")
10140 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10141 "TARGET_POWER2
10142 && TARGET_HARD_FLOAT && TARGET_FPRS"
10143 "stfq%U0%X0 %1,%0")
10146 (define_peephole2
10147 [(set (match_operand:DF 0 "memory_operand" "")
10148 (match_operand:DF 1 "gpc_reg_operand" ""))
10149 (set (match_operand:DF 2 "memory_operand" "")
10150 (match_operand:DF 3 "gpc_reg_operand" ""))]
10151 "TARGET_POWER2
10152 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10153 && registers_ok_for_quad_peep (operands[1], operands[3])
10154 && mems_ok_for_quad_peep (operands[0], operands[2])"
10155 [(set (match_dup 0)
10156 (match_dup 1))]
10157 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10158 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10160 ;; After inserting conditional returns we can sometimes have
10161 ;; unnecessary register moves. Unfortunately we cannot have a
10162 ;; modeless peephole here, because some single SImode sets have early
10163 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10164 ;; sequences, using get_attr_length here will smash the operands
10165 ;; array. Neither is there an early_cobbler_p predicate.
10166 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10167 (define_peephole2
10168 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10169 (match_operand:DF 1 "any_operand" ""))
10170 (set (match_operand:DF 2 "gpc_reg_operand" "")
10171 (match_dup 0))]
10172 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10173 && peep2_reg_dead_p (2, operands[0])"
10174 [(set (match_dup 2) (match_dup 1))])
10176 (define_peephole2
10177 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10178 (match_operand:SF 1 "any_operand" ""))
10179 (set (match_operand:SF 2 "gpc_reg_operand" "")
10180 (match_dup 0))]
10181 "peep2_reg_dead_p (2, operands[0])"
10182 [(set (match_dup 2) (match_dup 1))])
10184 \f
10185 ;; TLS support.
10187 ;; Mode attributes for different ABIs.
10188 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10189 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10190 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10191 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10193 (define_insn "tls_gd_aix<TLSmode:tls_abi_suffix>"
10194 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10195 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10196 (match_operand 4 "" "g")))
10197 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10198 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10199 UNSPEC_TLSGD)
10200 (clobber (reg:SI LR_REGNO))]
10201 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10202 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
10203 [(set_attr "type" "two")
10204 (set_attr "length" "12")])
10206 (define_insn "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10207 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10208 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10209 (match_operand 4 "" "g")))
10210 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10211 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10212 UNSPEC_TLSGD)
10213 (clobber (reg:SI LR_REGNO))]
10214 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10215 {
10216 if (flag_pic)
10217 {
10218 if (TARGET_SECURE_PLT && flag_pic == 2)
10219 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10220 else
10221 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10222 }
10223 else
10224 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10225 }
10226 [(set_attr "type" "two")
10227 (set_attr "length" "8")])
10229 (define_insn "tls_ld_aix<TLSmode:tls_abi_suffix>"
10230 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10231 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10232 (match_operand 3 "" "g")))
10233 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10234 UNSPEC_TLSLD)
10235 (clobber (reg:SI LR_REGNO))]
10236 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10237 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
10238 [(set_attr "length" "12")])
10240 (define_insn "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10241 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10242 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10243 (match_operand 3 "" "g")))
10244 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10245 UNSPEC_TLSLD)
10246 (clobber (reg:SI LR_REGNO))]
10247 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10248 {
10249 if (flag_pic)
10250 {
10251 if (TARGET_SECURE_PLT && flag_pic == 2)
10252 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10253 else
10254 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10255 }
10256 else
10257 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10258 }
10259 [(set_attr "length" "8")])
10261 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10262 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10263 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10264 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10265 UNSPEC_TLSDTPREL))]
10266 "HAVE_AS_TLS"
10267 "addi %0,%1,%2@dtprel")
10269 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10270 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10271 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10272 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10273 UNSPEC_TLSDTPRELHA))]
10274 "HAVE_AS_TLS"
10275 "addis %0,%1,%2@dtprel@ha")
10277 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10278 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10279 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10280 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10281 UNSPEC_TLSDTPRELLO))]
10282 "HAVE_AS_TLS"
10283 "addi %0,%1,%2@dtprel@l")
10285 (define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10286 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10287 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10288 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10289 UNSPEC_TLSGOTDTPREL))]
10290 "HAVE_AS_TLS"
10291 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
10293 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10294 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10295 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10296 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10297 UNSPEC_TLSTPREL))]
10298 "HAVE_AS_TLS"
10299 "addi %0,%1,%2@tprel")
10301 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10302 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10303 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10304 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10305 UNSPEC_TLSTPRELHA))]
10306 "HAVE_AS_TLS"
10307 "addis %0,%1,%2@tprel@ha")
10309 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10310 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10311 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10312 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10313 UNSPEC_TLSTPRELLO))]
10314 "HAVE_AS_TLS"
10315 "addi %0,%1,%2@tprel@l")
10317 ;; "b" output constraint here and on tls_tls input to support linker tls
10318 ;; optimization. The linker may edit the instructions emitted by a
10319 ;; tls_got_tprel/tls_tls pair to addis,addi.
10320 (define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10321 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10322 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10323 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10324 UNSPEC_TLSGOTTPREL))]
10325 "HAVE_AS_TLS"
10326 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
10328 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10329 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10330 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10331 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10332 UNSPEC_TLSTLS))]
10333 "HAVE_AS_TLS"
10334 "add %0,%1,%2@tls")
10336 \f
10337 ;; Next come insns related to the calling sequence.
10338 ;;
10339 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10340 ;; We move the back-chain and decrement the stack pointer.
10342 (define_expand "allocate_stack"
10343 [(set (match_operand 0 "gpc_reg_operand" "")
10344 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10345 (set (reg 1)
10346 (minus (reg 1) (match_dup 1)))]
10347 ""
10348 "
10349 { rtx chain = gen_reg_rtx (Pmode);
10350 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10351 rtx neg_op0;
10353 emit_move_insn (chain, stack_bot);
10355 /* Check stack bounds if necessary. */
10356 if (crtl->limit_stack)
10357 {
10358 rtx available;
10359 available = expand_binop (Pmode, sub_optab,
10360 stack_pointer_rtx, stack_limit_rtx,
10361 NULL_RTX, 1, OPTAB_WIDEN);
10362 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10363 }
10365 if (GET_CODE (operands[1]) != CONST_INT
10366 || INTVAL (operands[1]) < -32767
10367 || INTVAL (operands[1]) > 32768)
10368 {
10369 neg_op0 = gen_reg_rtx (Pmode);
10370 if (TARGET_32BIT)
10371 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10372 else
10373 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10374 }
10375 else
10376 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10378 if (TARGET_UPDATE)
10379 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10380 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10382 else
10383 {
10384 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10385 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10386 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10387 }
10389 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10390 DONE;
10391 }")
10393 ;; These patterns say how to save and restore the stack pointer. We need not
10394 ;; save the stack pointer at function level since we are careful to
10395 ;; preserve the backchain. At block level, we have to restore the backchain
10396 ;; when we restore the stack pointer.
10397 ;;
10398 ;; For nonlocal gotos, we must save both the stack pointer and its
10399 ;; backchain and restore both. Note that in the nonlocal case, the
10400 ;; save area is a memory location.
10402 (define_expand "save_stack_function"
10403 [(match_operand 0 "any_operand" "")
10404 (match_operand 1 "any_operand" "")]
10405 ""
10406 "DONE;")
10408 (define_expand "restore_stack_function"
10409 [(match_operand 0 "any_operand" "")
10410 (match_operand 1 "any_operand" "")]
10411 ""
10412 "DONE;")
10414 ;; Adjust stack pointer (op0) to a new value (op1).
10415 ;; First copy old stack backchain to new location, and ensure that the
10416 ;; scheduler won't reorder the sp assignment before the backchain write.
10417 (define_expand "restore_stack_block"
10418 [(set (match_dup 2) (match_dup 3))
10419 (set (match_dup 4) (match_dup 2))
10420 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10421 (set (match_operand 0 "register_operand" "")
10422 (match_operand 1 "register_operand" ""))]
10423 ""
10424 "
10425 {
10426 operands[1] = force_reg (Pmode, operands[1]);
10427 operands[2] = gen_reg_rtx (Pmode);
10428 operands[3] = gen_frame_mem (Pmode, operands[0]);
10429 operands[4] = gen_frame_mem (Pmode, operands[1]);
10430 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10431 }")
10433 (define_expand "save_stack_nonlocal"
10434 [(set (match_dup 3) (match_dup 4))
10435 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10436 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10437 ""
10438 "
10439 {
10440 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10442 /* Copy the backchain to the first word, sp to the second. */
10443 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10444 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10445 operands[3] = gen_reg_rtx (Pmode);
10446 operands[4] = gen_frame_mem (Pmode, operands[1]);
10447 }")
10449 (define_expand "restore_stack_nonlocal"
10450 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10451 (set (match_dup 3) (match_dup 4))
10452 (set (match_dup 5) (match_dup 2))
10453 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10454 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10455 ""
10456 "
10457 {
10458 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10460 /* Restore the backchain from the first word, sp from the second. */
10461 operands[2] = gen_reg_rtx (Pmode);
10462 operands[3] = gen_reg_rtx (Pmode);
10463 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10464 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10465 operands[5] = gen_frame_mem (Pmode, operands[3]);
10466 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10467 }")
10468 \f
10469 ;; TOC register handling.
10471 ;; Code to initialize the TOC register...
10473 (define_insn "load_toc_aix_si"
10474 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10475 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10476 (use (reg:SI 2))])]
10477 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10478 "*
10479 {
10480 char buf[30];
10481 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10482 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10483 operands[2] = gen_rtx_REG (Pmode, 2);
10484 return \"{l|lwz} %0,%1(%2)\";
10485 }"
10486 [(set_attr "type" "load")])
10488 (define_insn "load_toc_aix_di"
10489 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10490 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10491 (use (reg:DI 2))])]
10492 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10493 "*
10494 {
10495 char buf[30];
10496 #ifdef TARGET_RELOCATABLE
10497 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10498 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10499 #else
10500 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10501 #endif
10502 if (TARGET_ELF)
10503 strcat (buf, \"@toc\");
10504 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10505 operands[2] = gen_rtx_REG (Pmode, 2);
10506 return \"ld %0,%1(%2)\";
10507 }"
10508 [(set_attr "type" "load")])
10510 (define_insn "load_toc_v4_pic_si"
10511 [(set (reg:SI LR_REGNO)
10512 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10513 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10514 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10515 [(set_attr "type" "branch")
10516 (set_attr "length" "4")])
10518 (define_insn "load_toc_v4_PIC_1"
10519 [(set (reg:SI LR_REGNO)
10520 (match_operand:SI 0 "immediate_operand" "s"))
10521 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10522 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10523 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10524 "bcl 20,31,%0\\n%0:"
10525 [(set_attr "type" "branch")
10526 (set_attr "length" "4")])
10528 (define_insn "load_toc_v4_PIC_1b"
10529 [(set (reg:SI LR_REGNO)
10530 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
10531 UNSPEC_TOCPTR))]
10532 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10533 "bcl 20,31,$+8\\n\\t.long %0-$"
10534 [(set_attr "type" "branch")
10535 (set_attr "length" "8")])
10537 (define_insn "load_toc_v4_PIC_2"
10538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10539 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10540 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10541 (match_operand:SI 3 "immediate_operand" "s")))))]
10542 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10543 "{l|lwz} %0,%2-%3(%1)"
10544 [(set_attr "type" "load")])
10546 (define_insn "load_toc_v4_PIC_3b"
10547 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10548 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10549 (high:SI
10550 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10551 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10552 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10553 "{cau|addis} %0,%1,%2-%3@ha")
10555 (define_insn "load_toc_v4_PIC_3c"
10556 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10557 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10558 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10559 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10560 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10561 "{cal|addi} %0,%1,%2-%3@l")
10563 ;; If the TOC is shared over a translation unit, as happens with all
10564 ;; the kinds of PIC that we support, we need to restore the TOC
10565 ;; pointer only when jumping over units of translation.
10566 ;; On Darwin, we need to reload the picbase.
10568 (define_expand "builtin_setjmp_receiver"
10569 [(use (label_ref (match_operand 0 "" "")))]
10570 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10571 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10572 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10573 "
10574 {
10575 #if TARGET_MACHO
10576 if (DEFAULT_ABI == ABI_DARWIN)
10577 {
10578 const char *picbase = machopic_function_base_name ();
10579 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10580 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10581 rtx tmplabrtx;
10582 char tmplab[20];
10584 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10585 CODE_LABEL_NUMBER (operands[0]));
10586 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10588 emit_insn (gen_load_macho_picbase (tmplabrtx));
10589 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10590 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10591 }
10592 else
10593 #endif
10594 rs6000_emit_load_toc_table (FALSE);
10595 DONE;
10596 }")
10598 ;; Elf specific ways of loading addresses for non-PIC code.
10599 ;; The output of this could be r0, but we make a very strong
10600 ;; preference for a base register because it will usually
10601 ;; be needed there.
10602 (define_insn "elf_high"
10603 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10604 (high:SI (match_operand 1 "" "")))]
10605 "TARGET_ELF && ! TARGET_64BIT"
10606 "{liu|lis} %0,%1@ha")
10608 (define_insn "elf_low"
10609 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10610 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10611 (match_operand 2 "" "")))]
10612 "TARGET_ELF && ! TARGET_64BIT"
10613 "@
10614 {cal|la} %0,%2@l(%1)
10615 {ai|addic} %0,%1,%K2")
10616 \f
10617 ;; A function pointer under AIX is a pointer to a data area whose first word
10618 ;; contains the actual address of the function, whose second word contains a
10619 ;; pointer to its TOC, and whose third word contains a value to place in the
10620 ;; static chain register (r11). Note that if we load the static chain, our
10621 ;; "trampoline" need not have any executable code.
10623 (define_expand "call_indirect_aix32"
10624 [(set (match_dup 2)
10625 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10626 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10627 (reg:SI 2))
10628 (set (reg:SI 2)
10629 (mem:SI (plus:SI (match_dup 0)
10630 (const_int 4))))
10631 (set (reg:SI 11)
10632 (mem:SI (plus:SI (match_dup 0)
10633 (const_int 8))))
10634 (parallel [(call (mem:SI (match_dup 2))
10635 (match_operand 1 "" ""))
10636 (use (reg:SI 2))
10637 (use (reg:SI 11))
10638 (set (reg:SI 2)
10639 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10640 (clobber (reg:SI LR_REGNO))])]
10641 "TARGET_32BIT"
10642 "
10643 { operands[2] = gen_reg_rtx (SImode); }")
10645 (define_expand "call_indirect_aix64"
10646 [(set (match_dup 2)
10647 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10648 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10649 (reg:DI 2))
10650 (set (reg:DI 2)
10651 (mem:DI (plus:DI (match_dup 0)
10652 (const_int 8))))
10653 (set (reg:DI 11)
10654 (mem:DI (plus:DI (match_dup 0)
10655 (const_int 16))))
10656 (parallel [(call (mem:SI (match_dup 2))
10657 (match_operand 1 "" ""))
10658 (use (reg:DI 2))
10659 (use (reg:DI 11))
10660 (set (reg:DI 2)
10661 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10662 (clobber (reg:SI LR_REGNO))])]
10663 "TARGET_64BIT"
10664 "
10665 { operands[2] = gen_reg_rtx (DImode); }")
10667 (define_expand "call_value_indirect_aix32"
10668 [(set (match_dup 3)
10669 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10670 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10671 (reg:SI 2))
10672 (set (reg:SI 2)
10673 (mem:SI (plus:SI (match_dup 1)
10674 (const_int 4))))
10675 (set (reg:SI 11)
10676 (mem:SI (plus:SI (match_dup 1)
10677 (const_int 8))))
10678 (parallel [(set (match_operand 0 "" "")
10679 (call (mem:SI (match_dup 3))
10680 (match_operand 2 "" "")))
10681 (use (reg:SI 2))
10682 (use (reg:SI 11))
10683 (set (reg:SI 2)
10684 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10685 (clobber (reg:SI LR_REGNO))])]
10686 "TARGET_32BIT"
10687 "
10688 { operands[3] = gen_reg_rtx (SImode); }")
10690 (define_expand "call_value_indirect_aix64"
10691 [(set (match_dup 3)
10692 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10693 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10694 (reg:DI 2))
10695 (set (reg:DI 2)
10696 (mem:DI (plus:DI (match_dup 1)
10697 (const_int 8))))
10698 (set (reg:DI 11)
10699 (mem:DI (plus:DI (match_dup 1)
10700 (const_int 16))))
10701 (parallel [(set (match_operand 0 "" "")
10702 (call (mem:SI (match_dup 3))
10703 (match_operand 2 "" "")))
10704 (use (reg:DI 2))
10705 (use (reg:DI 11))
10706 (set (reg:DI 2)
10707 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10708 (clobber (reg:SI LR_REGNO))])]
10709 "TARGET_64BIT"
10710 "
10711 { operands[3] = gen_reg_rtx (DImode); }")
10713 ;; Now the definitions for the call and call_value insns
10714 (define_expand "call"
10715 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10716 (match_operand 1 "" ""))
10717 (use (match_operand 2 "" ""))
10718 (clobber (reg:SI LR_REGNO))])]
10719 ""
10720 "
10721 {
10722 #if TARGET_MACHO
10723 if (MACHOPIC_INDIRECT)
10724 operands[0] = machopic_indirect_call_target (operands[0]);
10725 #endif
10727 gcc_assert (GET_CODE (operands[0]) == MEM);
10728 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10730 operands[0] = XEXP (operands[0], 0);
10732 if (GET_CODE (operands[0]) != SYMBOL_REF
10733 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10734 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10735 {
10736 if (INTVAL (operands[2]) & CALL_LONG)
10737 operands[0] = rs6000_longcall_ref (operands[0]);
10739 switch (DEFAULT_ABI)
10740 {
10741 case ABI_V4:
10742 case ABI_DARWIN:
10743 operands[0] = force_reg (Pmode, operands[0]);
10744 break;
10746 case ABI_AIX:
10747 /* AIX function pointers are really pointers to a three word
10748 area. */
10749 emit_call_insn (TARGET_32BIT
10750 ? gen_call_indirect_aix32 (force_reg (SImode,
10751 operands[0]),
10752 operands[1])
10753 : gen_call_indirect_aix64 (force_reg (DImode,
10754 operands[0]),
10755 operands[1]));
10756 DONE;
10758 default:
10759 gcc_unreachable ();
10760 }
10761 }
10762 }")
10764 (define_expand "call_value"
10765 [(parallel [(set (match_operand 0 "" "")
10766 (call (mem:SI (match_operand 1 "address_operand" ""))
10767 (match_operand 2 "" "")))
10768 (use (match_operand 3 "" ""))
10769 (clobber (reg:SI LR_REGNO))])]
10770 ""
10771 "
10772 {
10773 #if TARGET_MACHO
10774 if (MACHOPIC_INDIRECT)
10775 operands[1] = machopic_indirect_call_target (operands[1]);
10776 #endif
10778 gcc_assert (GET_CODE (operands[1]) == MEM);
10779 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10781 operands[1] = XEXP (operands[1], 0);
10783 if (GET_CODE (operands[1]) != SYMBOL_REF
10784 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10785 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10786 {
10787 if (INTVAL (operands[3]) & CALL_LONG)
10788 operands[1] = rs6000_longcall_ref (operands[1]);
10790 switch (DEFAULT_ABI)
10791 {
10792 case ABI_V4:
10793 case ABI_DARWIN:
10794 operands[1] = force_reg (Pmode, operands[1]);
10795 break;
10797 case ABI_AIX:
10798 /* AIX function pointers are really pointers to a three word
10799 area. */
10800 emit_call_insn (TARGET_32BIT
10801 ? gen_call_value_indirect_aix32 (operands[0],
10802 force_reg (SImode,
10803 operands[1]),
10804 operands[2])
10805 : gen_call_value_indirect_aix64 (operands[0],
10806 force_reg (DImode,
10807 operands[1]),
10808 operands[2]));
10809 DONE;
10811 default:
10812 gcc_unreachable ();
10813 }
10814 }
10815 }")
10817 ;; Call to function in current module. No TOC pointer reload needed.
10818 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10819 ;; either the function was not prototyped, or it was prototyped as a
10820 ;; variable argument function. It is > 0 if FP registers were passed
10821 ;; and < 0 if they were not.
10823 (define_insn "*call_local32"
10824 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10825 (match_operand 1 "" "g,g"))
10826 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10827 (clobber (reg:SI LR_REGNO))]
10828 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10829 "*
10830 {
10831 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10832 output_asm_insn (\"crxor 6,6,6\", operands);
10834 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10835 output_asm_insn (\"creqv 6,6,6\", operands);
10837 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10838 }"
10839 [(set_attr "type" "branch")
10840 (set_attr "length" "4,8")])
10842 (define_insn "*call_local64"
10843 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10844 (match_operand 1 "" "g,g"))
10845 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10846 (clobber (reg:SI LR_REGNO))]
10847 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10848 "*
10849 {
10850 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10851 output_asm_insn (\"crxor 6,6,6\", operands);
10853 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10854 output_asm_insn (\"creqv 6,6,6\", operands);
10856 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10857 }"
10858 [(set_attr "type" "branch")
10859 (set_attr "length" "4,8")])
10861 (define_insn "*call_value_local32"
10862 [(set (match_operand 0 "" "")
10863 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10864 (match_operand 2 "" "g,g")))
10865 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10866 (clobber (reg:SI LR_REGNO))]
10867 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10868 "*
10869 {
10870 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10871 output_asm_insn (\"crxor 6,6,6\", operands);
10873 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10874 output_asm_insn (\"creqv 6,6,6\", operands);
10876 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10877 }"
10878 [(set_attr "type" "branch")
10879 (set_attr "length" "4,8")])
10882 (define_insn "*call_value_local64"
10883 [(set (match_operand 0 "" "")
10884 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10885 (match_operand 2 "" "g,g")))
10886 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10887 (clobber (reg:SI LR_REGNO))]
10888 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10889 "*
10890 {
10891 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10892 output_asm_insn (\"crxor 6,6,6\", operands);
10894 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10895 output_asm_insn (\"creqv 6,6,6\", operands);
10897 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10898 }"
10899 [(set_attr "type" "branch")
10900 (set_attr "length" "4,8")])
10902 ;; Call to function which may be in another module. Restore the TOC
10903 ;; pointer (r2) after the call unless this is System V.
10904 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10905 ;; either the function was not prototyped, or it was prototyped as a
10906 ;; variable argument function. It is > 0 if FP registers were passed
10907 ;; and < 0 if they were not.
10909 (define_insn "*call_indirect_nonlocal_aix32"
10910 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10911 (match_operand 1 "" "g,g"))
10912 (use (reg:SI 2))
10913 (use (reg:SI 11))
10914 (set (reg:SI 2)
10915 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10916 (clobber (reg:SI LR_REGNO))]
10917 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10918 "b%T0l\;{l|lwz} 2,20(1)"
10919 [(set_attr "type" "jmpreg")
10920 (set_attr "length" "8")])
10922 (define_insn "*call_nonlocal_aix32"
10923 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10924 (match_operand 1 "" "g"))
10925 (use (match_operand:SI 2 "immediate_operand" "O"))
10926 (clobber (reg:SI LR_REGNO))]
10927 "TARGET_32BIT
10928 && DEFAULT_ABI == ABI_AIX
10929 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10930 "bl %z0\;%."
10931 [(set_attr "type" "branch")
10932 (set_attr "length" "8")])
10934 (define_insn "*call_indirect_nonlocal_aix64"
10935 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10936 (match_operand 1 "" "g,g"))
10937 (use (reg:DI 2))
10938 (use (reg:DI 11))
10939 (set (reg:DI 2)
10940 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10941 (clobber (reg:SI LR_REGNO))]
10942 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10943 "b%T0l\;ld 2,40(1)"
10944 [(set_attr "type" "jmpreg")
10945 (set_attr "length" "8")])
10947 (define_insn "*call_nonlocal_aix64"
10948 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10949 (match_operand 1 "" "g"))
10950 (use (match_operand:SI 2 "immediate_operand" "O"))
10951 (clobber (reg:SI LR_REGNO))]
10952 "TARGET_64BIT
10953 && DEFAULT_ABI == ABI_AIX
10954 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10955 "bl %z0\;%."
10956 [(set_attr "type" "branch")
10957 (set_attr "length" "8")])
10959 (define_insn "*call_value_indirect_nonlocal_aix32"
10960 [(set (match_operand 0 "" "")
10961 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10962 (match_operand 2 "" "g,g")))
10963 (use (reg:SI 2))
10964 (use (reg:SI 11))
10965 (set (reg:SI 2)
10966 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10967 (clobber (reg:SI LR_REGNO))]
10968 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10969 "b%T1l\;{l|lwz} 2,20(1)"
10970 [(set_attr "type" "jmpreg")
10971 (set_attr "length" "8")])
10973 (define_insn "*call_value_nonlocal_aix32"
10974 [(set (match_operand 0 "" "")
10975 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10976 (match_operand 2 "" "g")))
10977 (use (match_operand:SI 3 "immediate_operand" "O"))
10978 (clobber (reg:SI LR_REGNO))]
10979 "TARGET_32BIT
10980 && DEFAULT_ABI == ABI_AIX
10981 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10982 "bl %z1\;%."
10983 [(set_attr "type" "branch")
10984 (set_attr "length" "8")])
10986 (define_insn "*call_value_indirect_nonlocal_aix64"
10987 [(set (match_operand 0 "" "")
10988 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10989 (match_operand 2 "" "g,g")))
10990 (use (reg:DI 2))
10991 (use (reg:DI 11))
10992 (set (reg:DI 2)
10993 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10994 (clobber (reg:SI LR_REGNO))]
10995 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10996 "b%T1l\;ld 2,40(1)"
10997 [(set_attr "type" "jmpreg")
10998 (set_attr "length" "8")])
11000 (define_insn "*call_value_nonlocal_aix64"
11001 [(set (match_operand 0 "" "")
11002 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11003 (match_operand 2 "" "g")))
11004 (use (match_operand:SI 3 "immediate_operand" "O"))
11005 (clobber (reg:SI LR_REGNO))]
11006 "TARGET_64BIT
11007 && DEFAULT_ABI == ABI_AIX
11008 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11009 "bl %z1\;%."
11010 [(set_attr "type" "branch")
11011 (set_attr "length" "8")])
11013 ;; A function pointer under System V is just a normal pointer
11014 ;; operands[0] is the function pointer
11015 ;; operands[1] is the stack size to clean up
11016 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11017 ;; which indicates how to set cr1
11019 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11020 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11021 (match_operand 1 "" "g,g,g,g"))
11022 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11023 (clobber (reg:SI LR_REGNO))]
11024 "DEFAULT_ABI == ABI_V4
11025 || DEFAULT_ABI == ABI_DARWIN"
11026 {
11027 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11028 output_asm_insn ("crxor 6,6,6", operands);
11030 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11031 output_asm_insn ("creqv 6,6,6", operands);
11033 return "b%T0l";
11034 }
11035 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11036 (set_attr "length" "4,4,8,8")])
11038 (define_insn_and_split "*call_nonlocal_sysv<mode>"
11039 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11040 (match_operand 1 "" "g,g"))
11041 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11042 (clobber (reg:SI LR_REGNO))]
11043 "(DEFAULT_ABI == ABI_DARWIN
11044 || (DEFAULT_ABI == ABI_V4
11045 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11046 {
11047 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11048 output_asm_insn ("crxor 6,6,6", operands);
11050 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11051 output_asm_insn ("creqv 6,6,6", operands);
11053 #if TARGET_MACHO
11054 return output_call(insn, operands, 0, 2);
11055 #else
11056 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11057 {
11058 gcc_assert (!TARGET_SECURE_PLT);
11059 return "bl %z0@plt";
11060 }
11061 else
11062 return "bl %z0";
11063 #endif
11064 }
11065 "DEFAULT_ABI == ABI_V4
11066 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11067 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11068 [(parallel [(call (mem:SI (match_dup 0))
11069 (match_dup 1))
11070 (use (match_dup 2))
11071 (use (match_dup 3))
11072 (clobber (reg:SI LR_REGNO))])]
11073 {
11074 operands[3] = pic_offset_table_rtx;
11075 }
11076 [(set_attr "type" "branch,branch")
11077 (set_attr "length" "4,8")])
11079 (define_insn "*call_nonlocal_sysv_secure<mode>"
11080 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11081 (match_operand 1 "" "g,g"))
11082 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11083 (use (match_operand:SI 3 "register_operand" "r,r"))
11084 (clobber (reg:SI LR_REGNO))]
11085 "(DEFAULT_ABI == ABI_V4
11086 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11087 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11088 {
11089 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11090 output_asm_insn ("crxor 6,6,6", operands);
11092 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11093 output_asm_insn ("creqv 6,6,6", operands);
11095 if (flag_pic == 2)
11096 /* The magic 32768 offset here and in the other sysv call insns
11097 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11098 See sysv4.h:toc_section. */
11099 return "bl %z0+32768@plt";
11100 else
11101 return "bl %z0@plt";
11102 }
11103 [(set_attr "type" "branch,branch")
11104 (set_attr "length" "4,8")])
11106 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11107 [(set (match_operand 0 "" "")
11108 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11109 (match_operand 2 "" "g,g,g,g")))
11110 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11111 (clobber (reg:SI LR_REGNO))]
11112 "DEFAULT_ABI == ABI_V4
11113 || DEFAULT_ABI == ABI_DARWIN"
11114 {
11115 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11116 output_asm_insn ("crxor 6,6,6", operands);
11118 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11119 output_asm_insn ("creqv 6,6,6", operands);
11121 return "b%T1l";
11122 }
11123 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11124 (set_attr "length" "4,4,8,8")])
11126 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11127 [(set (match_operand 0 "" "")
11128 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11129 (match_operand 2 "" "g,g")))
11130 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11131 (clobber (reg:SI LR_REGNO))]
11132 "(DEFAULT_ABI == ABI_DARWIN
11133 || (DEFAULT_ABI == ABI_V4
11134 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11135 {
11136 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11137 output_asm_insn ("crxor 6,6,6", operands);
11139 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11140 output_asm_insn ("creqv 6,6,6", operands);
11142 #if TARGET_MACHO
11143 return output_call(insn, operands, 1, 3);
11144 #else
11145 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11146 {
11147 gcc_assert (!TARGET_SECURE_PLT);
11148 return "bl %z1@plt";
11149 }
11150 else
11151 return "bl %z1";
11152 #endif
11153 }
11154 "DEFAULT_ABI == ABI_V4
11155 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11156 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11157 [(parallel [(set (match_dup 0)
11158 (call (mem:SI (match_dup 1))
11159 (match_dup 2)))
11160 (use (match_dup 3))
11161 (use (match_dup 4))
11162 (clobber (reg:SI LR_REGNO))])]
11163 {
11164 operands[4] = pic_offset_table_rtx;
11165 }
11166 [(set_attr "type" "branch,branch")
11167 (set_attr "length" "4,8")])
11169 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11170 [(set (match_operand 0 "" "")
11171 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11172 (match_operand 2 "" "g,g")))
11173 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11174 (use (match_operand:SI 4 "register_operand" "r,r"))
11175 (clobber (reg:SI LR_REGNO))]
11176 "(DEFAULT_ABI == ABI_V4
11177 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11178 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11179 {
11180 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11181 output_asm_insn ("crxor 6,6,6", operands);
11183 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11184 output_asm_insn ("creqv 6,6,6", operands);
11186 if (flag_pic == 2)
11187 return "bl %z1+32768@plt";
11188 else
11189 return "bl %z1@plt";
11190 }
11191 [(set_attr "type" "branch,branch")
11192 (set_attr "length" "4,8")])
11194 ;; Call subroutine returning any type.
11195 (define_expand "untyped_call"
11196 [(parallel [(call (match_operand 0 "" "")
11197 (const_int 0))
11198 (match_operand 1 "" "")
11199 (match_operand 2 "" "")])]
11200 ""
11201 "
11202 {
11203 int i;
11205 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11207 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11208 {
11209 rtx set = XVECEXP (operands[2], 0, i);
11210 emit_move_insn (SET_DEST (set), SET_SRC (set));
11211 }
11213 /* The optimizer does not know that the call sets the function value
11214 registers we stored in the result block. We avoid problems by
11215 claiming that all hard registers are used and clobbered at this
11216 point. */
11217 emit_insn (gen_blockage ());
11219 DONE;
11220 }")
11222 ;; sibling call patterns
11223 (define_expand "sibcall"
11224 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11225 (match_operand 1 "" ""))
11226 (use (match_operand 2 "" ""))
11227 (use (reg:SI LR_REGNO))
11228 (return)])]
11229 ""
11230 "
11231 {
11232 #if TARGET_MACHO
11233 if (MACHOPIC_INDIRECT)
11234 operands[0] = machopic_indirect_call_target (operands[0]);
11235 #endif
11237 gcc_assert (GET_CODE (operands[0]) == MEM);
11238 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11240 operands[0] = XEXP (operands[0], 0);
11241 }")
11243 ;; this and similar patterns must be marked as using LR, otherwise
11244 ;; dataflow will try to delete the store into it. This is true
11245 ;; even when the actual reg to jump to is in CTR, when LR was
11246 ;; saved and restored around the PIC-setting BCL.
11247 (define_insn "*sibcall_local32"
11248 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11249 (match_operand 1 "" "g,g"))
11250 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11251 (use (reg:SI LR_REGNO))
11252 (return)]
11253 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11254 "*
11255 {
11256 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11257 output_asm_insn (\"crxor 6,6,6\", operands);
11259 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11260 output_asm_insn (\"creqv 6,6,6\", operands);
11262 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11263 }"
11264 [(set_attr "type" "branch")
11265 (set_attr "length" "4,8")])
11267 (define_insn "*sibcall_local64"
11268 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11269 (match_operand 1 "" "g,g"))
11270 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11271 (use (reg:SI LR_REGNO))
11272 (return)]
11273 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11274 "*
11275 {
11276 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11277 output_asm_insn (\"crxor 6,6,6\", operands);
11279 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11280 output_asm_insn (\"creqv 6,6,6\", operands);
11282 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11283 }"
11284 [(set_attr "type" "branch")
11285 (set_attr "length" "4,8")])
11287 (define_insn "*sibcall_value_local32"
11288 [(set (match_operand 0 "" "")
11289 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11290 (match_operand 2 "" "g,g")))
11291 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11292 (use (reg:SI LR_REGNO))
11293 (return)]
11294 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11295 "*
11296 {
11297 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11298 output_asm_insn (\"crxor 6,6,6\", operands);
11300 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11301 output_asm_insn (\"creqv 6,6,6\", operands);
11303 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11304 }"
11305 [(set_attr "type" "branch")
11306 (set_attr "length" "4,8")])
11309 (define_insn "*sibcall_value_local64"
11310 [(set (match_operand 0 "" "")
11311 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11312 (match_operand 2 "" "g,g")))
11313 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11314 (use (reg:SI LR_REGNO))
11315 (return)]
11316 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11317 "*
11318 {
11319 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11320 output_asm_insn (\"crxor 6,6,6\", operands);
11322 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11323 output_asm_insn (\"creqv 6,6,6\", operands);
11325 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11326 }"
11327 [(set_attr "type" "branch")
11328 (set_attr "length" "4,8")])
11330 (define_insn "*sibcall_nonlocal_aix32"
11331 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11332 (match_operand 1 "" "g"))
11333 (use (match_operand:SI 2 "immediate_operand" "O"))
11334 (use (reg:SI LR_REGNO))
11335 (return)]
11336 "TARGET_32BIT
11337 && DEFAULT_ABI == ABI_AIX
11338 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11339 "b %z0"
11340 [(set_attr "type" "branch")
11341 (set_attr "length" "4")])
11343 (define_insn "*sibcall_nonlocal_aix64"
11344 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11345 (match_operand 1 "" "g"))
11346 (use (match_operand:SI 2 "immediate_operand" "O"))
11347 (use (reg:SI LR_REGNO))
11348 (return)]
11349 "TARGET_64BIT
11350 && DEFAULT_ABI == ABI_AIX
11351 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11352 "b %z0"
11353 [(set_attr "type" "branch")
11354 (set_attr "length" "4")])
11356 (define_insn "*sibcall_value_nonlocal_aix32"
11357 [(set (match_operand 0 "" "")
11358 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11359 (match_operand 2 "" "g")))
11360 (use (match_operand:SI 3 "immediate_operand" "O"))
11361 (use (reg:SI LR_REGNO))
11362 (return)]
11363 "TARGET_32BIT
11364 && DEFAULT_ABI == ABI_AIX
11365 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11366 "b %z1"
11367 [(set_attr "type" "branch")
11368 (set_attr "length" "4")])
11370 (define_insn "*sibcall_value_nonlocal_aix64"
11371 [(set (match_operand 0 "" "")
11372 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11373 (match_operand 2 "" "g")))
11374 (use (match_operand:SI 3 "immediate_operand" "O"))
11375 (use (reg:SI LR_REGNO))
11376 (return)]
11377 "TARGET_64BIT
11378 && DEFAULT_ABI == ABI_AIX
11379 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11380 "b %z1"
11381 [(set_attr "type" "branch")
11382 (set_attr "length" "4")])
11384 (define_insn "*sibcall_nonlocal_sysv<mode>"
11385 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11386 (match_operand 1 "" ""))
11387 (use (match_operand 2 "immediate_operand" "O,n"))
11388 (use (reg:SI LR_REGNO))
11389 (return)]
11390 "(DEFAULT_ABI == ABI_DARWIN
11391 || DEFAULT_ABI == ABI_V4)
11392 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11393 "*
11394 {
11395 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11396 output_asm_insn (\"crxor 6,6,6\", operands);
11398 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11399 output_asm_insn (\"creqv 6,6,6\", operands);
11401 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11402 {
11403 gcc_assert (!TARGET_SECURE_PLT);
11404 return \"b %z0@plt\";
11405 }
11406 else
11407 return \"b %z0\";
11408 }"
11409 [(set_attr "type" "branch,branch")
11410 (set_attr "length" "4,8")])
11412 (define_expand "sibcall_value"
11413 [(parallel [(set (match_operand 0 "register_operand" "")
11414 (call (mem:SI (match_operand 1 "address_operand" ""))
11415 (match_operand 2 "" "")))
11416 (use (match_operand 3 "" ""))
11417 (use (reg:SI LR_REGNO))
11418 (return)])]
11419 ""
11420 "
11421 {
11422 #if TARGET_MACHO
11423 if (MACHOPIC_INDIRECT)
11424 operands[1] = machopic_indirect_call_target (operands[1]);
11425 #endif
11427 gcc_assert (GET_CODE (operands[1]) == MEM);
11428 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11430 operands[1] = XEXP (operands[1], 0);
11431 }")
11433 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11434 [(set (match_operand 0 "" "")
11435 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11436 (match_operand 2 "" "")))
11437 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11438 (use (reg:SI LR_REGNO))
11439 (return)]
11440 "(DEFAULT_ABI == ABI_DARWIN
11441 || DEFAULT_ABI == ABI_V4)
11442 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11443 "*
11444 {
11445 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11446 output_asm_insn (\"crxor 6,6,6\", operands);
11448 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11449 output_asm_insn (\"creqv 6,6,6\", operands);
11451 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11452 {
11453 gcc_assert (!TARGET_SECURE_PLT);
11454 return \"b %z1@plt\";
11455 }
11456 else
11457 return \"b %z1\";
11458 }"
11459 [(set_attr "type" "branch,branch")
11460 (set_attr "length" "4,8")])
11462 (define_expand "sibcall_epilogue"
11463 [(use (const_int 0))]
11464 "TARGET_SCHED_PROLOG"
11465 "
11466 {
11467 rs6000_emit_epilogue (TRUE);
11468 DONE;
11469 }")
11471 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11472 ;; all of memory. This blocks insns from being moved across this point.
11474 (define_insn "blockage"
11475 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11476 ""
11477 "")
11478 \f
11479 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11480 ;; signed & unsigned, and one type of branch.
11481 ;;
11482 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11483 ;; insns, and branches. We store the operands of compares until we see
11484 ;; how it is used.
11485 (define_expand "cmp<mode>"
11486 [(set (cc0)
11487 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11488 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11489 ""
11490 "
11491 {
11492 /* Take care of the possibility that operands[1] might be negative but
11493 this might be a logical operation. That insn doesn't exist. */
11494 if (GET_CODE (operands[1]) == CONST_INT
11495 && INTVAL (operands[1]) < 0)
11496 operands[1] = force_reg (<MODE>mode, operands[1]);
11498 rs6000_compare_op0 = operands[0];
11499 rs6000_compare_op1 = operands[1];
11500 rs6000_compare_fp_p = 0;
11501 DONE;
11502 }")
11504 (define_expand "cmp<mode>"
11505 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11506 (match_operand:FP 1 "gpc_reg_operand" "")))]
11507 ""
11508 "
11509 {
11510 rs6000_compare_op0 = operands[0];
11511 rs6000_compare_op1 = operands[1];
11512 rs6000_compare_fp_p = 1;
11513 DONE;
11514 }")
11516 (define_expand "beq"
11517 [(use (match_operand 0 "" ""))]
11518 ""
11519 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11521 (define_expand "bne"
11522 [(use (match_operand 0 "" ""))]
11523 ""
11524 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11526 (define_expand "bge"
11527 [(use (match_operand 0 "" ""))]
11528 ""
11529 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11531 (define_expand "bgt"
11532 [(use (match_operand 0 "" ""))]
11533 ""
11534 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11536 (define_expand "ble"
11537 [(use (match_operand 0 "" ""))]
11538 ""
11539 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11541 (define_expand "blt"
11542 [(use (match_operand 0 "" ""))]
11543 ""
11544 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11546 (define_expand "bgeu"
11547 [(use (match_operand 0 "" ""))]
11548 ""
11549 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11551 (define_expand "bgtu"
11552 [(use (match_operand 0 "" ""))]
11553 ""
11554 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11556 (define_expand "bleu"
11557 [(use (match_operand 0 "" ""))]
11558 ""
11559 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11561 (define_expand "bltu"
11562 [(use (match_operand 0 "" ""))]
11563 ""
11564 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11566 (define_expand "bunordered"
11567 [(use (match_operand 0 "" ""))]
11568 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11569 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11571 (define_expand "bordered"
11572 [(use (match_operand 0 "" ""))]
11573 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11574 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11576 (define_expand "buneq"
11577 [(use (match_operand 0 "" ""))]
11578 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11579 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11581 (define_expand "bunge"
11582 [(use (match_operand 0 "" ""))]
11583 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11584 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11586 (define_expand "bungt"
11587 [(use (match_operand 0 "" ""))]
11588 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11589 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11591 (define_expand "bunle"
11592 [(use (match_operand 0 "" ""))]
11593 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11594 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11596 (define_expand "bunlt"
11597 [(use (match_operand 0 "" ""))]
11598 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11599 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11601 (define_expand "bltgt"
11602 [(use (match_operand 0 "" ""))]
11603 ""
11604 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11606 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11607 ;; For SEQ, likewise, except that comparisons with zero should be done
11608 ;; with an scc insns. However, due to the order that combine see the
11609 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11610 ;; the cases we don't want to handle.
11611 (define_expand "seq"
11612 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11613 ""
11614 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11616 (define_expand "sne"
11617 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11618 ""
11619 "
11620 {
11621 if (! rs6000_compare_fp_p)
11622 FAIL;
11624 rs6000_emit_sCOND (NE, operands[0]);
11625 DONE;
11626 }")
11628 ;; A >= 0 is best done the portable way for A an integer.
11629 (define_expand "sge"
11630 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11631 ""
11632 "
11633 {
11634 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11635 FAIL;
11637 rs6000_emit_sCOND (GE, operands[0]);
11638 DONE;
11639 }")
11641 ;; A > 0 is best done using the portable sequence, so fail in that case.
11642 (define_expand "sgt"
11643 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11644 ""
11645 "
11646 {
11647 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11648 FAIL;
11650 rs6000_emit_sCOND (GT, operands[0]);
11651 DONE;
11652 }")
11654 ;; A <= 0 is best done the portable way for A an integer.
11655 (define_expand "sle"
11656 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11657 ""
11658 "
11659 {
11660 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11661 FAIL;
11663 rs6000_emit_sCOND (LE, operands[0]);
11664 DONE;
11665 }")
11667 ;; A < 0 is best done in the portable way for A an integer.
11668 (define_expand "slt"
11669 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11670 ""
11671 "
11672 {
11673 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11674 FAIL;
11676 rs6000_emit_sCOND (LT, operands[0]);
11677 DONE;
11678 }")
11680 (define_expand "sgeu"
11681 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11682 ""
11683 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11685 (define_expand "sgtu"
11686 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11687 ""
11688 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11690 (define_expand "sleu"
11691 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11692 ""
11693 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11695 (define_expand "sltu"
11696 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11697 ""
11698 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11700 (define_expand "sunordered"
11701 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11702 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11703 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11705 (define_expand "sordered"
11706 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11707 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11708 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11710 (define_expand "suneq"
11711 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11712 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11713 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11715 (define_expand "sunge"
11716 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11717 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11718 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11720 (define_expand "sungt"
11721 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11722 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11723 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11725 (define_expand "sunle"
11726 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11727 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11728 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11730 (define_expand "sunlt"
11731 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11732 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11733 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11735 (define_expand "sltgt"
11736 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11737 ""
11738 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11740 (define_expand "stack_protect_set"
11741 [(match_operand 0 "memory_operand" "")
11742 (match_operand 1 "memory_operand" "")]
11743 ""
11744 {
11745 #ifdef TARGET_THREAD_SSP_OFFSET
11746 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11747 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11748 operands[1] = gen_rtx_MEM (Pmode, addr);
11749 #endif
11750 if (TARGET_64BIT)
11751 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11752 else
11753 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11754 DONE;
11755 })
11757 (define_insn "stack_protect_setsi"
11758 [(set (match_operand:SI 0 "memory_operand" "=m")
11759 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11760 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11761 "TARGET_32BIT"
11762 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11763 [(set_attr "type" "three")
11764 (set_attr "length" "12")])
11766 (define_insn "stack_protect_setdi"
11767 [(set (match_operand:DI 0 "memory_operand" "=m")
11768 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11769 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11770 "TARGET_64BIT"
11771 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11772 [(set_attr "type" "three")
11773 (set_attr "length" "12")])
11775 (define_expand "stack_protect_test"
11776 [(match_operand 0 "memory_operand" "")
11777 (match_operand 1 "memory_operand" "")
11778 (match_operand 2 "" "")]
11779 ""
11780 {
11781 #ifdef TARGET_THREAD_SSP_OFFSET
11782 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11783 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11784 operands[1] = gen_rtx_MEM (Pmode, addr);
11785 #endif
11786 rs6000_compare_op0 = operands[0];
11787 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11788 UNSPEC_SP_TEST);
11789 rs6000_compare_fp_p = 0;
11790 emit_jump_insn (gen_beq (operands[2]));
11791 DONE;
11792 })
11794 (define_insn "stack_protect_testsi"
11795 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11796 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11797 (match_operand:SI 2 "memory_operand" "m,m")]
11798 UNSPEC_SP_TEST))
11799 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11800 (clobber (match_scratch:SI 3 "=&r,&r"))]
11801 "TARGET_32BIT"
11802 "@
11803 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11804 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11805 [(set_attr "length" "16,20")])
11807 (define_insn "stack_protect_testdi"
11808 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11809 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11810 (match_operand:DI 2 "memory_operand" "m,m")]
11811 UNSPEC_SP_TEST))
11812 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11813 (clobber (match_scratch:DI 3 "=&r,&r"))]
11814 "TARGET_64BIT"
11815 "@
11816 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11817 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11818 [(set_attr "length" "16,20")])
11820 \f
11821 ;; Here are the actual compare insns.
11822 (define_insn "*cmp<mode>_internal1"
11823 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11824 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11825 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11826 ""
11827 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11828 [(set_attr "type" "cmp")])
11830 ;; If we are comparing a register for equality with a large constant,
11831 ;; we can do this with an XOR followed by a compare. But this is profitable
11832 ;; only if the large constant is only used for the comparison (and in this
11833 ;; case we already have a register to reuse as scratch).
11834 ;;
11835 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11836 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11838 (define_peephole2
11839 [(set (match_operand:SI 0 "register_operand")
11840 (match_operand:SI 1 "logical_const_operand" ""))
11841 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11842 [(match_dup 0)
11843 (match_operand:SI 2 "logical_const_operand" "")]))
11844 (set (match_operand:CC 4 "cc_reg_operand" "")
11845 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11846 (match_dup 0)))
11847 (set (pc)
11848 (if_then_else (match_operator 6 "equality_operator"
11849 [(match_dup 4) (const_int 0)])
11850 (match_operand 7 "" "")
11851 (match_operand 8 "" "")))]
11852 "peep2_reg_dead_p (3, operands[0])
11853 && peep2_reg_dead_p (4, operands[4])"
11854 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11855 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11856 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11858 {
11859 /* Get the constant we are comparing against, and see what it looks like
11860 when sign-extended from 16 to 32 bits. Then see what constant we could
11861 XOR with SEXTC to get the sign-extended value. */
11862 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11863 SImode,
11864 operands[1], operands[2]);
11865 HOST_WIDE_INT c = INTVAL (cnst);
11866 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11867 HOST_WIDE_INT xorv = c ^ sextc;
11869 operands[9] = GEN_INT (xorv);
11870 operands[10] = GEN_INT (sextc);
11871 })
11873 (define_insn "*cmpsi_internal2"
11874 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11875 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11876 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11877 ""
11878 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11879 [(set_attr "type" "cmp")])
11881 (define_insn "*cmpdi_internal2"
11882 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11883 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11884 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11885 ""
11886 "cmpld%I2 %0,%1,%b2"
11887 [(set_attr "type" "cmp")])
11889 ;; The following two insns don't exist as single insns, but if we provide
11890 ;; them, we can swap an add and compare, which will enable us to overlap more
11891 ;; of the required delay between a compare and branch. We generate code for
11892 ;; them by splitting.
11894 (define_insn ""
11895 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11896 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11897 (match_operand:SI 2 "short_cint_operand" "i")))
11898 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11899 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11900 ""
11901 "#"
11902 [(set_attr "length" "8")])
11904 (define_insn ""
11905 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11906 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11907 (match_operand:SI 2 "u_short_cint_operand" "i")))
11908 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11909 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11910 ""
11911 "#"
11912 [(set_attr "length" "8")])
11914 (define_split
11915 [(set (match_operand:CC 3 "cc_reg_operand" "")
11916 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11917 (match_operand:SI 2 "short_cint_operand" "")))
11918 (set (match_operand:SI 0 "gpc_reg_operand" "")
11919 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11920 ""
11921 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11922 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11924 (define_split
11925 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11926 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11927 (match_operand:SI 2 "u_short_cint_operand" "")))
11928 (set (match_operand:SI 0 "gpc_reg_operand" "")
11929 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11930 ""
11931 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11932 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11934 (define_insn "*cmpsf_internal1"
11935 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11936 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11937 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11938 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
11939 "fcmpu %0,%1,%2"
11940 [(set_attr "type" "fpcompare")])
11942 (define_insn "*cmpdf_internal1"
11943 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11944 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11945 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11946 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
11947 "fcmpu %0,%1,%2"
11948 [(set_attr "type" "fpcompare")])
11950 ;; Only need to compare second words if first words equal
11951 (define_insn "*cmptf_internal1"
11952 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11953 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11954 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11955 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11956 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11957 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11958 [(set_attr "type" "fpcompare")
11959 (set_attr "length" "12")])
11961 (define_insn_and_split "*cmptf_internal2"
11962 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11963 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11964 (match_operand:TF 2 "gpc_reg_operand" "f")))
11965 (clobber (match_scratch:DF 3 "=f"))
11966 (clobber (match_scratch:DF 4 "=f"))
11967 (clobber (match_scratch:DF 5 "=f"))
11968 (clobber (match_scratch:DF 6 "=f"))
11969 (clobber (match_scratch:DF 7 "=f"))
11970 (clobber (match_scratch:DF 8 "=f"))
11971 (clobber (match_scratch:DF 9 "=f"))
11972 (clobber (match_scratch:DF 10 "=f"))]
11973 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11974 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11975 "#"
11976 "&& reload_completed"
11977 [(set (match_dup 3) (match_dup 13))
11978 (set (match_dup 4) (match_dup 14))
11979 (set (match_dup 9) (abs:DF (match_dup 5)))
11980 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11981 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11982 (label_ref (match_dup 11))
11983 (pc)))
11984 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11985 (set (pc) (label_ref (match_dup 12)))
11986 (match_dup 11)
11987 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11988 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11989 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11990 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11991 (match_dup 12)]
11992 {
11993 REAL_VALUE_TYPE rv;
11994 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11995 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11997 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11998 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11999 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12000 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12001 operands[11] = gen_label_rtx ();
12002 operands[12] = gen_label_rtx ();
12003 real_inf (&rv);
12004 operands[13] = force_const_mem (DFmode,
12005 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12006 operands[14] = force_const_mem (DFmode,
12007 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12008 DFmode));
12009 if (TARGET_TOC)
12010 {
12011 operands[13] = gen_const_mem (DFmode,
12012 create_TOC_reference (XEXP (operands[13], 0)));
12013 operands[14] = gen_const_mem (DFmode,
12014 create_TOC_reference (XEXP (operands[14], 0)));
12015 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12016 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12017 }
12018 })
12019 \f
12020 ;; Now we have the scc insns. We can do some combinations because of the
12021 ;; way the machine works.
12022 ;;
12023 ;; Note that this is probably faster if we can put an insn between the
12024 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12025 ;; cases the insns below which don't use an intermediate CR field will
12026 ;; be used instead.
12027 (define_insn ""
12028 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12029 (match_operator:SI 1 "scc_comparison_operator"
12030 [(match_operand 2 "cc_reg_operand" "y")
12031 (const_int 0)]))]
12032 ""
12033 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12034 [(set (attr "type")
12035 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12036 (const_string "mfcrf")
12037 ]
12038 (const_string "mfcr")))
12039 (set_attr "length" "8")])
12041 ;; Same as above, but get the GT bit.
12042 (define_insn "move_from_CR_gt_bit"
12043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12044 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12045 "TARGET_E500"
12046 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12047 [(set_attr "type" "mfcr")
12048 (set_attr "length" "8")])
12050 ;; Same as above, but get the OV/ORDERED bit.
12051 (define_insn "move_from_CR_ov_bit"
12052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12053 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12054 "TARGET_ISEL"
12055 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12056 [(set_attr "type" "mfcr")
12057 (set_attr "length" "8")])
12059 (define_insn ""
12060 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12061 (match_operator:DI 1 "scc_comparison_operator"
12062 [(match_operand 2 "cc_reg_operand" "y")
12063 (const_int 0)]))]
12064 "TARGET_POWERPC64"
12065 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12066 [(set (attr "type")
12067 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12068 (const_string "mfcrf")
12069 ]
12070 (const_string "mfcr")))
12071 (set_attr "length" "8")])
12073 (define_insn ""
12074 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12075 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12076 [(match_operand 2 "cc_reg_operand" "y,y")
12077 (const_int 0)])
12078 (const_int 0)))
12079 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12080 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12081 "TARGET_32BIT"
12082 "@
12083 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12084 #"
12085 [(set_attr "type" "delayed_compare")
12086 (set_attr "length" "8,16")])
12088 (define_split
12089 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12090 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12091 [(match_operand 2 "cc_reg_operand" "")
12092 (const_int 0)])
12093 (const_int 0)))
12094 (set (match_operand:SI 3 "gpc_reg_operand" "")
12095 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12096 "TARGET_32BIT && reload_completed"
12097 [(set (match_dup 3)
12098 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12099 (set (match_dup 0)
12100 (compare:CC (match_dup 3)
12101 (const_int 0)))]
12102 "")
12104 (define_insn ""
12105 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12106 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12107 [(match_operand 2 "cc_reg_operand" "y")
12108 (const_int 0)])
12109 (match_operand:SI 3 "const_int_operand" "n")))]
12110 ""
12111 "*
12112 {
12113 int is_bit = ccr_bit (operands[1], 1);
12114 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12115 int count;
12117 if (is_bit >= put_bit)
12118 count = is_bit - put_bit;
12119 else
12120 count = 32 - (put_bit - is_bit);
12122 operands[4] = GEN_INT (count);
12123 operands[5] = GEN_INT (put_bit);
12125 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12126 }"
12127 [(set (attr "type")
12128 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12129 (const_string "mfcrf")
12130 ]
12131 (const_string "mfcr")))
12132 (set_attr "length" "8")])
12134 (define_insn ""
12135 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12136 (compare:CC
12137 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12138 [(match_operand 2 "cc_reg_operand" "y,y")
12139 (const_int 0)])
12140 (match_operand:SI 3 "const_int_operand" "n,n"))
12141 (const_int 0)))
12142 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12143 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12144 (match_dup 3)))]
12145 ""
12146 "*
12147 {
12148 int is_bit = ccr_bit (operands[1], 1);
12149 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12150 int count;
12152 /* Force split for non-cc0 compare. */
12153 if (which_alternative == 1)
12154 return \"#\";
12156 if (is_bit >= put_bit)
12157 count = is_bit - put_bit;
12158 else
12159 count = 32 - (put_bit - is_bit);
12161 operands[5] = GEN_INT (count);
12162 operands[6] = GEN_INT (put_bit);
12164 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12165 }"
12166 [(set_attr "type" "delayed_compare")
12167 (set_attr "length" "8,16")])
12169 (define_split
12170 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12171 (compare:CC
12172 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12173 [(match_operand 2 "cc_reg_operand" "")
12174 (const_int 0)])
12175 (match_operand:SI 3 "const_int_operand" ""))
12176 (const_int 0)))
12177 (set (match_operand:SI 4 "gpc_reg_operand" "")
12178 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12179 (match_dup 3)))]
12180 "reload_completed"
12181 [(set (match_dup 4)
12182 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12183 (match_dup 3)))
12184 (set (match_dup 0)
12185 (compare:CC (match_dup 4)
12186 (const_int 0)))]
12187 "")
12189 ;; There is a 3 cycle delay between consecutive mfcr instructions
12190 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12192 (define_peephole
12193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12194 (match_operator:SI 1 "scc_comparison_operator"
12195 [(match_operand 2 "cc_reg_operand" "y")
12196 (const_int 0)]))
12197 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12198 (match_operator:SI 4 "scc_comparison_operator"
12199 [(match_operand 5 "cc_reg_operand" "y")
12200 (const_int 0)]))]
12201 "REGNO (operands[2]) != REGNO (operands[5])"
12202 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12203 [(set_attr "type" "mfcr")
12204 (set_attr "length" "12")])
12206 (define_peephole
12207 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12208 (match_operator:DI 1 "scc_comparison_operator"
12209 [(match_operand 2 "cc_reg_operand" "y")
12210 (const_int 0)]))
12211 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12212 (match_operator:DI 4 "scc_comparison_operator"
12213 [(match_operand 5 "cc_reg_operand" "y")
12214 (const_int 0)]))]
12215 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12216 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12217 [(set_attr "type" "mfcr")
12218 (set_attr "length" "12")])
12220 ;; There are some scc insns that can be done directly, without a compare.
12221 ;; These are faster because they don't involve the communications between
12222 ;; the FXU and branch units. In fact, we will be replacing all of the
12223 ;; integer scc insns here or in the portable methods in emit_store_flag.
12224 ;;
12225 ;; Also support (neg (scc ..)) since that construct is used to replace
12226 ;; branches, (plus (scc ..) ..) since that construct is common and
12227 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12228 ;; cases where it is no more expensive than (neg (scc ..)).
12230 ;; Have reload force a constant into a register for the simple insns that
12231 ;; otherwise won't accept constants. We do this because it is faster than
12232 ;; the cmp/mfcr sequence we would otherwise generate.
12234 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12235 (DI "rKJI")])
12237 (define_insn_and_split "*eq<mode>"
12238 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12239 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12240 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12241 "!TARGET_POWER"
12242 "#"
12243 "!TARGET_POWER"
12244 [(set (match_dup 0)
12245 (clz:GPR (match_dup 3)))
12246 (set (match_dup 0)
12247 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12248 {
12249 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12250 {
12251 /* Use output operand as intermediate. */
12252 operands[3] = operands[0];
12254 if (logical_operand (operands[2], <MODE>mode))
12255 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12256 gen_rtx_XOR (<MODE>mode,
12257 operands[1], operands[2])));
12258 else
12259 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12260 gen_rtx_PLUS (<MODE>mode, operands[1],
12261 negate_rtx (<MODE>mode,
12262 operands[2]))));
12263 }
12264 else
12265 operands[3] = operands[1];
12267 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12268 })
12270 (define_insn_and_split "*eq<mode>_compare"
12271 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12272 (compare:CC
12273 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12274 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12275 (const_int 0)))
12276 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12277 (eq:P (match_dup 1) (match_dup 2)))]
12278 "!TARGET_POWER && optimize_size"
12279 "#"
12280 "!TARGET_POWER && optimize_size"
12281 [(set (match_dup 0)
12282 (clz:P (match_dup 4)))
12283 (parallel [(set (match_dup 3)
12284 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12285 (const_int 0)))
12286 (set (match_dup 0)
12287 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12288 {
12289 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12290 {
12291 /* Use output operand as intermediate. */
12292 operands[4] = operands[0];
12294 if (logical_operand (operands[2], <MODE>mode))
12295 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12296 gen_rtx_XOR (<MODE>mode,
12297 operands[1], operands[2])));
12298 else
12299 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12300 gen_rtx_PLUS (<MODE>mode, operands[1],
12301 negate_rtx (<MODE>mode,
12302 operands[2]))));
12303 }
12304 else
12305 operands[4] = operands[1];
12307 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12308 })
12310 (define_insn "*eqsi_power"
12311 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12312 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12313 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12314 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12315 "TARGET_POWER"
12316 "@
12317 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12318 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12319 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12320 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12321 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12322 [(set_attr "type" "three,two,three,three,three")
12323 (set_attr "length" "12,8,12,12,12")])
12325 ;; We have insns of the form shown by the first define_insn below. If
12326 ;; there is something inside the comparison operation, we must split it.
12327 (define_split
12328 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12329 (plus:SI (match_operator 1 "comparison_operator"
12330 [(match_operand:SI 2 "" "")
12331 (match_operand:SI 3
12332 "reg_or_cint_operand" "")])
12333 (match_operand:SI 4 "gpc_reg_operand" "")))
12334 (clobber (match_operand:SI 5 "register_operand" ""))]
12335 "! gpc_reg_operand (operands[2], SImode)"
12336 [(set (match_dup 5) (match_dup 2))
12337 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12338 (match_dup 4)))])
12340 (define_insn "*plus_eqsi"
12341 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12342 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12343 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12344 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12345 "TARGET_32BIT"
12346 "@
12347 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12348 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12349 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12350 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12351 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12352 [(set_attr "type" "three,two,three,three,three")
12353 (set_attr "length" "12,8,12,12,12")])
12355 (define_insn "*compare_plus_eqsi"
12356 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12357 (compare:CC
12358 (plus:SI
12359 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12360 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12361 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12362 (const_int 0)))
12363 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12364 "TARGET_32BIT && optimize_size"
12365 "@
12366 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12367 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12368 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12369 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12370 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12371 #
12372 #
12373 #
12374 #
12375 #"
12376 [(set_attr "type" "compare")
12377 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12379 (define_split
12380 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12381 (compare:CC
12382 (plus:SI
12383 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12384 (match_operand:SI 2 "scc_eq_operand" ""))
12385 (match_operand:SI 3 "gpc_reg_operand" ""))
12386 (const_int 0)))
12387 (clobber (match_scratch:SI 4 ""))]
12388 "TARGET_32BIT && optimize_size && reload_completed"
12389 [(set (match_dup 4)
12390 (plus:SI (eq:SI (match_dup 1)
12391 (match_dup 2))
12392 (match_dup 3)))
12393 (set (match_dup 0)
12394 (compare:CC (match_dup 4)
12395 (const_int 0)))]
12396 "")
12398 (define_insn "*plus_eqsi_compare"
12399 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12400 (compare:CC
12401 (plus:SI
12402 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12403 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12404 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12405 (const_int 0)))
12406 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12407 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12408 "TARGET_32BIT && optimize_size"
12409 "@
12410 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12411 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12412 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12413 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12414 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12415 #
12416 #
12417 #
12418 #
12419 #"
12420 [(set_attr "type" "compare")
12421 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12423 (define_split
12424 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12425 (compare:CC
12426 (plus:SI
12427 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12428 (match_operand:SI 2 "scc_eq_operand" ""))
12429 (match_operand:SI 3 "gpc_reg_operand" ""))
12430 (const_int 0)))
12431 (set (match_operand:SI 0 "gpc_reg_operand" "")
12432 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12433 "TARGET_32BIT && optimize_size && reload_completed"
12434 [(set (match_dup 0)
12435 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12436 (set (match_dup 4)
12437 (compare:CC (match_dup 0)
12438 (const_int 0)))]
12439 "")
12441 (define_insn "*neg_eq0<mode>"
12442 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12443 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12444 (const_int 0))))]
12445 ""
12446 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12447 [(set_attr "type" "two")
12448 (set_attr "length" "8")])
12450 (define_insn_and_split "*neg_eq<mode>"
12451 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12452 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12453 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12454 ""
12455 "#"
12456 ""
12457 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12458 {
12459 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12460 {
12461 /* Use output operand as intermediate. */
12462 operands[3] = operands[0];
12464 if (logical_operand (operands[2], <MODE>mode))
12465 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12466 gen_rtx_XOR (<MODE>mode,
12467 operands[1], operands[2])));
12468 else
12469 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12470 gen_rtx_PLUS (<MODE>mode, operands[1],
12471 negate_rtx (<MODE>mode,
12472 operands[2]))));
12473 }
12474 else
12475 operands[3] = operands[1];
12476 })
12478 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12479 ;; since it nabs/sr is just as fast.
12480 (define_insn "*ne0si"
12481 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12482 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12483 (const_int 31)))
12484 (clobber (match_scratch:SI 2 "=&r"))]
12485 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12486 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12487 [(set_attr "type" "two")
12488 (set_attr "length" "8")])
12490 (define_insn "*ne0di"
12491 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12492 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12493 (const_int 63)))
12494 (clobber (match_scratch:DI 2 "=&r"))]
12495 "TARGET_64BIT"
12496 "addic %2,%1,-1\;subfe %0,%2,%1"
12497 [(set_attr "type" "two")
12498 (set_attr "length" "8")])
12500 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12501 (define_insn "*plus_ne0si"
12502 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12503 (plus:SI (lshiftrt:SI
12504 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12505 (const_int 31))
12506 (match_operand:SI 2 "gpc_reg_operand" "r")))
12507 (clobber (match_scratch:SI 3 "=&r"))]
12508 "TARGET_32BIT"
12509 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12510 [(set_attr "type" "two")
12511 (set_attr "length" "8")])
12513 (define_insn "*plus_ne0di"
12514 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12515 (plus:DI (lshiftrt:DI
12516 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12517 (const_int 63))
12518 (match_operand:DI 2 "gpc_reg_operand" "r")))
12519 (clobber (match_scratch:DI 3 "=&r"))]
12520 "TARGET_64BIT"
12521 "addic %3,%1,-1\;addze %0,%2"
12522 [(set_attr "type" "two")
12523 (set_attr "length" "8")])
12525 (define_insn "*compare_plus_ne0si"
12526 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12527 (compare:CC
12528 (plus:SI (lshiftrt:SI
12529 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12530 (const_int 31))
12531 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12532 (const_int 0)))
12533 (clobber (match_scratch:SI 3 "=&r,&r"))
12534 (clobber (match_scratch:SI 4 "=X,&r"))]
12535 "TARGET_32BIT"
12536 "@
12537 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12538 #"
12539 [(set_attr "type" "compare")
12540 (set_attr "length" "8,12")])
12542 (define_split
12543 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12544 (compare:CC
12545 (plus:SI (lshiftrt:SI
12546 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12547 (const_int 31))
12548 (match_operand:SI 2 "gpc_reg_operand" ""))
12549 (const_int 0)))
12550 (clobber (match_scratch:SI 3 ""))
12551 (clobber (match_scratch:SI 4 ""))]
12552 "TARGET_32BIT && reload_completed"
12553 [(parallel [(set (match_dup 3)
12554 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12555 (const_int 31))
12556 (match_dup 2)))
12557 (clobber (match_dup 4))])
12558 (set (match_dup 0)
12559 (compare:CC (match_dup 3)
12560 (const_int 0)))]
12561 "")
12563 (define_insn "*compare_plus_ne0di"
12564 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12565 (compare:CC
12566 (plus:DI (lshiftrt:DI
12567 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12568 (const_int 63))
12569 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12570 (const_int 0)))
12571 (clobber (match_scratch:DI 3 "=&r,&r"))]
12572 "TARGET_64BIT"
12573 "@
12574 addic %3,%1,-1\;addze. %3,%2
12575 #"
12576 [(set_attr "type" "compare")
12577 (set_attr "length" "8,12")])
12579 (define_split
12580 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12581 (compare:CC
12582 (plus:DI (lshiftrt:DI
12583 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12584 (const_int 63))
12585 (match_operand:DI 2 "gpc_reg_operand" ""))
12586 (const_int 0)))
12587 (clobber (match_scratch:DI 3 ""))]
12588 "TARGET_64BIT && reload_completed"
12589 [(set (match_dup 3)
12590 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12591 (const_int 63))
12592 (match_dup 2)))
12593 (set (match_dup 0)
12594 (compare:CC (match_dup 3)
12595 (const_int 0)))]
12596 "")
12598 (define_insn "*plus_ne0si_compare"
12599 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12600 (compare:CC
12601 (plus:SI (lshiftrt:SI
12602 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12603 (const_int 31))
12604 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12605 (const_int 0)))
12606 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12607 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12608 (match_dup 2)))
12609 (clobber (match_scratch:SI 3 "=&r,&r"))]
12610 "TARGET_32BIT"
12611 "@
12612 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12613 #"
12614 [(set_attr "type" "compare")
12615 (set_attr "length" "8,12")])
12617 (define_split
12618 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12619 (compare:CC
12620 (plus:SI (lshiftrt:SI
12621 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12622 (const_int 31))
12623 (match_operand:SI 2 "gpc_reg_operand" ""))
12624 (const_int 0)))
12625 (set (match_operand:SI 0 "gpc_reg_operand" "")
12626 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12627 (match_dup 2)))
12628 (clobber (match_scratch:SI 3 ""))]
12629 "TARGET_32BIT && reload_completed"
12630 [(parallel [(set (match_dup 0)
12631 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12632 (match_dup 2)))
12633 (clobber (match_dup 3))])
12634 (set (match_dup 4)
12635 (compare:CC (match_dup 0)
12636 (const_int 0)))]
12637 "")
12639 (define_insn "*plus_ne0di_compare"
12640 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12641 (compare:CC
12642 (plus:DI (lshiftrt:DI
12643 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12644 (const_int 63))
12645 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12646 (const_int 0)))
12647 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12648 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12649 (match_dup 2)))
12650 (clobber (match_scratch:DI 3 "=&r,&r"))]
12651 "TARGET_64BIT"
12652 "@
12653 addic %3,%1,-1\;addze. %0,%2
12654 #"
12655 [(set_attr "type" "compare")
12656 (set_attr "length" "8,12")])
12658 (define_split
12659 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12660 (compare:CC
12661 (plus:DI (lshiftrt:DI
12662 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12663 (const_int 63))
12664 (match_operand:DI 2 "gpc_reg_operand" ""))
12665 (const_int 0)))
12666 (set (match_operand:DI 0 "gpc_reg_operand" "")
12667 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12668 (match_dup 2)))
12669 (clobber (match_scratch:DI 3 ""))]
12670 "TARGET_64BIT && reload_completed"
12671 [(parallel [(set (match_dup 0)
12672 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12673 (match_dup 2)))
12674 (clobber (match_dup 3))])
12675 (set (match_dup 4)
12676 (compare:CC (match_dup 0)
12677 (const_int 0)))]
12678 "")
12680 (define_insn ""
12681 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12682 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12683 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12684 (clobber (match_scratch:SI 3 "=r,X"))]
12685 "TARGET_POWER"
12686 "@
12687 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12688 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12689 [(set_attr "length" "12")])
12691 (define_insn ""
12692 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12693 (compare:CC
12694 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12695 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12696 (const_int 0)))
12697 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12698 (le:SI (match_dup 1) (match_dup 2)))
12699 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12700 "TARGET_POWER"
12701 "@
12702 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12703 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12704 #
12705 #"
12706 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12707 (set_attr "length" "12,12,16,16")])
12709 (define_split
12710 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12711 (compare:CC
12712 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12713 (match_operand:SI 2 "reg_or_short_operand" ""))
12714 (const_int 0)))
12715 (set (match_operand:SI 0 "gpc_reg_operand" "")
12716 (le:SI (match_dup 1) (match_dup 2)))
12717 (clobber (match_scratch:SI 3 ""))]
12718 "TARGET_POWER && reload_completed"
12719 [(parallel [(set (match_dup 0)
12720 (le:SI (match_dup 1) (match_dup 2)))
12721 (clobber (match_dup 3))])
12722 (set (match_dup 4)
12723 (compare:CC (match_dup 0)
12724 (const_int 0)))]
12725 "")
12727 (define_insn ""
12728 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12729 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12730 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12731 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12732 "TARGET_POWER"
12733 "@
12734 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12735 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12736 [(set_attr "length" "12")])
12738 (define_insn ""
12739 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12740 (compare:CC
12741 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12742 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12743 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12744 (const_int 0)))
12745 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12746 "TARGET_POWER"
12747 "@
12748 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12749 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12750 #
12751 #"
12752 [(set_attr "type" "compare")
12753 (set_attr "length" "12,12,16,16")])
12755 (define_split
12756 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12757 (compare:CC
12758 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12759 (match_operand:SI 2 "reg_or_short_operand" ""))
12760 (match_operand:SI 3 "gpc_reg_operand" ""))
12761 (const_int 0)))
12762 (clobber (match_scratch:SI 4 ""))]
12763 "TARGET_POWER && reload_completed"
12764 [(set (match_dup 4)
12765 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12766 (match_dup 3)))
12767 (set (match_dup 0)
12768 (compare:CC (match_dup 4)
12769 (const_int 0)))]
12770 "")
12772 (define_insn ""
12773 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12774 (compare:CC
12775 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12776 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12777 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12778 (const_int 0)))
12779 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12780 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12781 "TARGET_POWER"
12782 "@
12783 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12784 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12785 #
12786 #"
12787 [(set_attr "type" "compare")
12788 (set_attr "length" "12,12,16,16")])
12790 (define_split
12791 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12792 (compare:CC
12793 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12794 (match_operand:SI 2 "reg_or_short_operand" ""))
12795 (match_operand:SI 3 "gpc_reg_operand" ""))
12796 (const_int 0)))
12797 (set (match_operand:SI 0 "gpc_reg_operand" "")
12798 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12799 "TARGET_POWER && reload_completed"
12800 [(set (match_dup 0)
12801 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12802 (set (match_dup 4)
12803 (compare:CC (match_dup 0)
12804 (const_int 0)))]
12805 "")
12807 (define_insn ""
12808 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12809 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12810 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12811 "TARGET_POWER"
12812 "@
12813 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12814 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12815 [(set_attr "length" "12")])
12817 (define_insn "*leu<mode>"
12818 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12819 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12820 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12821 ""
12822 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12823 [(set_attr "type" "three")
12824 (set_attr "length" "12")])
12826 (define_insn "*leu<mode>_compare"
12827 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12828 (compare:CC
12829 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12830 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12831 (const_int 0)))
12832 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12833 (leu:P (match_dup 1) (match_dup 2)))]
12834 ""
12835 "@
12836 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12837 #"
12838 [(set_attr "type" "compare")
12839 (set_attr "length" "12,16")])
12841 (define_split
12842 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12843 (compare:CC
12844 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12845 (match_operand:P 2 "reg_or_short_operand" ""))
12846 (const_int 0)))
12847 (set (match_operand:P 0 "gpc_reg_operand" "")
12848 (leu:P (match_dup 1) (match_dup 2)))]
12849 "reload_completed"
12850 [(set (match_dup 0)
12851 (leu:P (match_dup 1) (match_dup 2)))
12852 (set (match_dup 3)
12853 (compare:CC (match_dup 0)
12854 (const_int 0)))]
12855 "")
12857 (define_insn "*plus_leu<mode>"
12858 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12859 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12860 (match_operand:P 2 "reg_or_short_operand" "rI"))
12861 (match_operand:P 3 "gpc_reg_operand" "r")))]
12862 ""
12863 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12864 [(set_attr "type" "two")
12865 (set_attr "length" "8")])
12867 (define_insn ""
12868 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12869 (compare:CC
12870 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12871 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12872 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12873 (const_int 0)))
12874 (clobber (match_scratch:SI 4 "=&r,&r"))]
12875 "TARGET_32BIT"
12876 "@
12877 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12878 #"
12879 [(set_attr "type" "compare")
12880 (set_attr "length" "8,12")])
12882 (define_split
12883 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12884 (compare:CC
12885 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12886 (match_operand:SI 2 "reg_or_short_operand" ""))
12887 (match_operand:SI 3 "gpc_reg_operand" ""))
12888 (const_int 0)))
12889 (clobber (match_scratch:SI 4 ""))]
12890 "TARGET_32BIT && reload_completed"
12891 [(set (match_dup 4)
12892 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12893 (match_dup 3)))
12894 (set (match_dup 0)
12895 (compare:CC (match_dup 4)
12896 (const_int 0)))]
12897 "")
12899 (define_insn ""
12900 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12901 (compare:CC
12902 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12903 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12904 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12905 (const_int 0)))
12906 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12907 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12908 "TARGET_32BIT"
12909 "@
12910 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12911 #"
12912 [(set_attr "type" "compare")
12913 (set_attr "length" "8,12")])
12915 (define_split
12916 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12917 (compare:CC
12918 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12919 (match_operand:SI 2 "reg_or_short_operand" ""))
12920 (match_operand:SI 3 "gpc_reg_operand" ""))
12921 (const_int 0)))
12922 (set (match_operand:SI 0 "gpc_reg_operand" "")
12923 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12924 "TARGET_32BIT && reload_completed"
12925 [(set (match_dup 0)
12926 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12927 (set (match_dup 4)
12928 (compare:CC (match_dup 0)
12929 (const_int 0)))]
12930 "")
12932 (define_insn "*neg_leu<mode>"
12933 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12934 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12935 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12936 ""
12937 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12938 [(set_attr "type" "three")
12939 (set_attr "length" "12")])
12941 (define_insn "*and_neg_leu<mode>"
12942 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12943 (and:P (neg:P
12944 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12945 (match_operand:P 2 "reg_or_short_operand" "rI")))
12946 (match_operand:P 3 "gpc_reg_operand" "r")))]
12947 ""
12948 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12949 [(set_attr "type" "three")
12950 (set_attr "length" "12")])
12952 (define_insn ""
12953 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12954 (compare:CC
12955 (and:SI (neg:SI
12956 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12957 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12958 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12959 (const_int 0)))
12960 (clobber (match_scratch:SI 4 "=&r,&r"))]
12961 "TARGET_32BIT"
12962 "@
12963 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12964 #"
12965 [(set_attr "type" "compare")
12966 (set_attr "length" "12,16")])
12968 (define_split
12969 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12970 (compare:CC
12971 (and:SI (neg:SI
12972 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12973 (match_operand:SI 2 "reg_or_short_operand" "")))
12974 (match_operand:SI 3 "gpc_reg_operand" ""))
12975 (const_int 0)))
12976 (clobber (match_scratch:SI 4 ""))]
12977 "TARGET_32BIT && reload_completed"
12978 [(set (match_dup 4)
12979 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12980 (match_dup 3)))
12981 (set (match_dup 0)
12982 (compare:CC (match_dup 4)
12983 (const_int 0)))]
12984 "")
12986 (define_insn ""
12987 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12988 (compare:CC
12989 (and:SI (neg:SI
12990 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12991 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12992 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12993 (const_int 0)))
12994 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12995 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12996 "TARGET_32BIT"
12997 "@
12998 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12999 #"
13000 [(set_attr "type" "compare")
13001 (set_attr "length" "12,16")])
13003 (define_split
13004 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13005 (compare:CC
13006 (and:SI (neg:SI
13007 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13008 (match_operand:SI 2 "reg_or_short_operand" "")))
13009 (match_operand:SI 3 "gpc_reg_operand" ""))
13010 (const_int 0)))
13011 (set (match_operand:SI 0 "gpc_reg_operand" "")
13012 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13013 "TARGET_32BIT && reload_completed"
13014 [(set (match_dup 0)
13015 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13016 (match_dup 3)))
13017 (set (match_dup 4)
13018 (compare:CC (match_dup 0)
13019 (const_int 0)))]
13020 "")
13022 (define_insn ""
13023 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13024 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13025 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13026 "TARGET_POWER"
13027 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13028 [(set_attr "length" "12")])
13030 (define_insn ""
13031 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13032 (compare:CC
13033 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13034 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13035 (const_int 0)))
13036 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13037 (lt:SI (match_dup 1) (match_dup 2)))]
13038 "TARGET_POWER"
13039 "@
13040 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13041 #"
13042 [(set_attr "type" "delayed_compare")
13043 (set_attr "length" "12,16")])
13045 (define_split
13046 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13047 (compare:CC
13048 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13049 (match_operand:SI 2 "reg_or_short_operand" ""))
13050 (const_int 0)))
13051 (set (match_operand:SI 0 "gpc_reg_operand" "")
13052 (lt:SI (match_dup 1) (match_dup 2)))]
13053 "TARGET_POWER && reload_completed"
13054 [(set (match_dup 0)
13055 (lt:SI (match_dup 1) (match_dup 2)))
13056 (set (match_dup 3)
13057 (compare:CC (match_dup 0)
13058 (const_int 0)))]
13059 "")
13061 (define_insn ""
13062 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13063 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13064 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13065 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13066 "TARGET_POWER"
13067 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13068 [(set_attr "length" "12")])
13070 (define_insn ""
13071 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13072 (compare:CC
13073 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13074 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13075 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13076 (const_int 0)))
13077 (clobber (match_scratch:SI 4 "=&r,&r"))]
13078 "TARGET_POWER"
13079 "@
13080 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13081 #"
13082 [(set_attr "type" "compare")
13083 (set_attr "length" "12,16")])
13085 (define_split
13086 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13087 (compare:CC
13088 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13089 (match_operand:SI 2 "reg_or_short_operand" ""))
13090 (match_operand:SI 3 "gpc_reg_operand" ""))
13091 (const_int 0)))
13092 (clobber (match_scratch:SI 4 ""))]
13093 "TARGET_POWER && reload_completed"
13094 [(set (match_dup 4)
13095 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13096 (match_dup 3)))
13097 (set (match_dup 0)
13098 (compare:CC (match_dup 4)
13099 (const_int 0)))]
13100 "")
13102 (define_insn ""
13103 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13104 (compare:CC
13105 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13106 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13107 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13108 (const_int 0)))
13109 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13110 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13111 "TARGET_POWER"
13112 "@
13113 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13114 #"
13115 [(set_attr "type" "compare")
13116 (set_attr "length" "12,16")])
13118 (define_split
13119 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13120 (compare:CC
13121 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13122 (match_operand:SI 2 "reg_or_short_operand" ""))
13123 (match_operand:SI 3 "gpc_reg_operand" ""))
13124 (const_int 0)))
13125 (set (match_operand:SI 0 "gpc_reg_operand" "")
13126 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13127 "TARGET_POWER && reload_completed"
13128 [(set (match_dup 0)
13129 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13130 (set (match_dup 4)
13131 (compare:CC (match_dup 0)
13132 (const_int 0)))]
13133 "")
13135 (define_insn ""
13136 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13137 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13138 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13139 "TARGET_POWER"
13140 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13141 [(set_attr "length" "12")])
13143 (define_insn_and_split "*ltu<mode>"
13144 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13145 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13146 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13147 ""
13148 "#"
13149 ""
13150 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13151 (set (match_dup 0) (neg:P (match_dup 0)))]
13152 "")
13154 (define_insn_and_split "*ltu<mode>_compare"
13155 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13156 (compare:CC
13157 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13158 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13159 (const_int 0)))
13160 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13161 (ltu:P (match_dup 1) (match_dup 2)))]
13162 ""
13163 "#"
13164 ""
13165 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13166 (parallel [(set (match_dup 3)
13167 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13168 (set (match_dup 0) (neg:P (match_dup 0)))])]
13169 "")
13171 (define_insn_and_split "*plus_ltu<mode>"
13172 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13173 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13174 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13175 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13176 ""
13177 "#"
13178 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13179 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13180 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13181 "")
13183 (define_insn_and_split "*plus_ltu<mode>_compare"
13184 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13185 (compare:CC
13186 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13187 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13188 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13189 (const_int 0)))
13190 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13191 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13192 ""
13193 "#"
13194 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13195 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13196 (parallel [(set (match_dup 4)
13197 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13198 (const_int 0)))
13199 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13200 "")
13202 (define_insn "*neg_ltu<mode>"
13203 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13204 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13205 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13206 ""
13207 "@
13208 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13209 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13210 [(set_attr "type" "two")
13211 (set_attr "length" "8")])
13213 (define_insn ""
13214 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13215 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13216 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13217 (clobber (match_scratch:SI 3 "=r"))]
13218 "TARGET_POWER"
13219 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
13220 [(set_attr "length" "12")])
13222 (define_insn ""
13223 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13224 (compare:CC
13225 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13226 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13227 (const_int 0)))
13228 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13229 (ge:SI (match_dup 1) (match_dup 2)))
13230 (clobber (match_scratch:SI 3 "=r,r"))]
13231 "TARGET_POWER"
13232 "@
13233 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13234 #"
13235 [(set_attr "type" "compare")
13236 (set_attr "length" "12,16")])
13238 (define_split
13239 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13240 (compare:CC
13241 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13242 (match_operand:SI 2 "reg_or_short_operand" ""))
13243 (const_int 0)))
13244 (set (match_operand:SI 0 "gpc_reg_operand" "")
13245 (ge:SI (match_dup 1) (match_dup 2)))
13246 (clobber (match_scratch:SI 3 ""))]
13247 "TARGET_POWER && reload_completed"
13248 [(parallel [(set (match_dup 0)
13249 (ge:SI (match_dup 1) (match_dup 2)))
13250 (clobber (match_dup 3))])
13251 (set (match_dup 4)
13252 (compare:CC (match_dup 0)
13253 (const_int 0)))]
13254 "")
13256 (define_insn ""
13257 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13258 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13259 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13260 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13261 "TARGET_POWER"
13262 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13263 [(set_attr "length" "12")])
13265 (define_insn ""
13266 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13267 (compare:CC
13268 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13269 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13270 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13271 (const_int 0)))
13272 (clobber (match_scratch:SI 4 "=&r,&r"))]
13273 "TARGET_POWER"
13274 "@
13275 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13276 #"
13277 [(set_attr "type" "compare")
13278 (set_attr "length" "12,16")])
13280 (define_split
13281 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13282 (compare:CC
13283 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13284 (match_operand:SI 2 "reg_or_short_operand" ""))
13285 (match_operand:SI 3 "gpc_reg_operand" ""))
13286 (const_int 0)))
13287 (clobber (match_scratch:SI 4 ""))]
13288 "TARGET_POWER && reload_completed"
13289 [(set (match_dup 4)
13290 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13291 (match_dup 3)))
13292 (set (match_dup 0)
13293 (compare:CC (match_dup 4)
13294 (const_int 0)))]
13295 "")
13297 (define_insn ""
13298 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13299 (compare:CC
13300 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13301 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13302 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13303 (const_int 0)))
13304 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13305 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13306 "TARGET_POWER"
13307 "@
13308 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13309 #"
13310 [(set_attr "type" "compare")
13311 (set_attr "length" "12,16")])
13313 (define_split
13314 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13315 (compare:CC
13316 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13317 (match_operand:SI 2 "reg_or_short_operand" ""))
13318 (match_operand:SI 3 "gpc_reg_operand" ""))
13319 (const_int 0)))
13320 (set (match_operand:SI 0 "gpc_reg_operand" "")
13321 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13322 "TARGET_POWER && reload_completed"
13323 [(set (match_dup 0)
13324 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13325 (set (match_dup 4)
13326 (compare:CC (match_dup 0)
13327 (const_int 0)))]
13328 "")
13330 (define_insn ""
13331 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13332 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13333 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13334 "TARGET_POWER"
13335 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
13336 [(set_attr "length" "12")])
13338 (define_insn "*geu<mode>"
13339 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13340 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13341 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13342 ""
13343 "@
13344 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13345 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13346 [(set_attr "type" "three")
13347 (set_attr "length" "12")])
13349 (define_insn "*geu<mode>_compare"
13350 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13351 (compare:CC
13352 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13353 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13354 (const_int 0)))
13355 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13356 (geu:P (match_dup 1) (match_dup 2)))]
13357 ""
13358 "@
13359 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13360 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13361 #
13362 #"
13363 [(set_attr "type" "compare")
13364 (set_attr "length" "12,12,16,16")])
13366 (define_split
13367 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13368 (compare:CC
13369 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13370 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13371 (const_int 0)))
13372 (set (match_operand:P 0 "gpc_reg_operand" "")
13373 (geu:P (match_dup 1) (match_dup 2)))]
13374 "reload_completed"
13375 [(set (match_dup 0)
13376 (geu:P (match_dup 1) (match_dup 2)))
13377 (set (match_dup 3)
13378 (compare:CC (match_dup 0)
13379 (const_int 0)))]
13380 "")
13382 (define_insn "*plus_geu<mode>"
13383 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13384 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13385 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13386 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13387 ""
13388 "@
13389 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13390 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13391 [(set_attr "type" "two")
13392 (set_attr "length" "8")])
13394 (define_insn ""
13395 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13396 (compare:CC
13397 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13398 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13399 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13400 (const_int 0)))
13401 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13402 "TARGET_32BIT"
13403 "@
13404 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13405 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13406 #
13407 #"
13408 [(set_attr "type" "compare")
13409 (set_attr "length" "8,8,12,12")])
13411 (define_split
13412 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13413 (compare:CC
13414 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13415 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13416 (match_operand:SI 3 "gpc_reg_operand" ""))
13417 (const_int 0)))
13418 (clobber (match_scratch:SI 4 ""))]
13419 "TARGET_32BIT && reload_completed"
13420 [(set (match_dup 4)
13421 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13422 (match_dup 3)))
13423 (set (match_dup 0)
13424 (compare:CC (match_dup 4)
13425 (const_int 0)))]
13426 "")
13428 (define_insn ""
13429 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13430 (compare:CC
13431 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13432 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13433 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13434 (const_int 0)))
13435 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13436 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13437 "TARGET_32BIT"
13438 "@
13439 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13440 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13441 #
13442 #"
13443 [(set_attr "type" "compare")
13444 (set_attr "length" "8,8,12,12")])
13446 (define_split
13447 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13448 (compare:CC
13449 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13450 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13451 (match_operand:SI 3 "gpc_reg_operand" ""))
13452 (const_int 0)))
13453 (set (match_operand:SI 0 "gpc_reg_operand" "")
13454 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13455 "TARGET_32BIT && reload_completed"
13456 [(set (match_dup 0)
13457 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13458 (set (match_dup 4)
13459 (compare:CC (match_dup 0)
13460 (const_int 0)))]
13461 "")
13463 (define_insn "*neg_geu<mode>"
13464 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13465 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13466 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13467 ""
13468 "@
13469 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13470 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13471 [(set_attr "type" "three")
13472 (set_attr "length" "12")])
13474 (define_insn "*and_neg_geu<mode>"
13475 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13476 (and:P (neg:P
13477 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13478 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13479 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13480 ""
13481 "@
13482 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13483 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13484 [(set_attr "type" "three")
13485 (set_attr "length" "12")])
13487 (define_insn ""
13488 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13489 (compare:CC
13490 (and:SI (neg:SI
13491 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13492 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13493 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13494 (const_int 0)))
13495 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13496 "TARGET_32BIT"
13497 "@
13498 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13499 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13500 #
13501 #"
13502 [(set_attr "type" "compare")
13503 (set_attr "length" "12,12,16,16")])
13505 (define_split
13506 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13507 (compare:CC
13508 (and:SI (neg:SI
13509 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13510 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13511 (match_operand:SI 3 "gpc_reg_operand" ""))
13512 (const_int 0)))
13513 (clobber (match_scratch:SI 4 ""))]
13514 "TARGET_32BIT && reload_completed"
13515 [(set (match_dup 4)
13516 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13517 (match_dup 3)))
13518 (set (match_dup 0)
13519 (compare:CC (match_dup 4)
13520 (const_int 0)))]
13521 "")
13523 (define_insn ""
13524 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13525 (compare:CC
13526 (and:SI (neg:SI
13527 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13528 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13529 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13530 (const_int 0)))
13531 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13532 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13533 "TARGET_32BIT"
13534 "@
13535 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13536 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13537 #
13538 #"
13539 [(set_attr "type" "compare")
13540 (set_attr "length" "12,12,16,16")])
13542 (define_split
13543 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13544 (compare:CC
13545 (and:SI (neg:SI
13546 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13547 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13548 (match_operand:SI 3 "gpc_reg_operand" ""))
13549 (const_int 0)))
13550 (set (match_operand:SI 0 "gpc_reg_operand" "")
13551 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13552 "TARGET_32BIT && reload_completed"
13553 [(set (match_dup 0)
13554 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13555 (set (match_dup 4)
13556 (compare:CC (match_dup 0)
13557 (const_int 0)))]
13558 "")
13560 (define_insn ""
13561 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13562 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13563 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13564 "TARGET_POWER"
13565 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13566 [(set_attr "length" "12")])
13568 (define_insn ""
13569 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13570 (compare:CC
13571 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13572 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13573 (const_int 0)))
13574 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13575 (gt:SI (match_dup 1) (match_dup 2)))]
13576 "TARGET_POWER"
13577 "@
13578 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13579 #"
13580 [(set_attr "type" "delayed_compare")
13581 (set_attr "length" "12,16")])
13583 (define_split
13584 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13585 (compare:CC
13586 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13587 (match_operand:SI 2 "reg_or_short_operand" ""))
13588 (const_int 0)))
13589 (set (match_operand:SI 0 "gpc_reg_operand" "")
13590 (gt:SI (match_dup 1) (match_dup 2)))]
13591 "TARGET_POWER && reload_completed"
13592 [(set (match_dup 0)
13593 (gt:SI (match_dup 1) (match_dup 2)))
13594 (set (match_dup 3)
13595 (compare:CC (match_dup 0)
13596 (const_int 0)))]
13597 "")
13599 (define_insn "*plus_gt0<mode>"
13600 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13601 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13602 (const_int 0))
13603 (match_operand:P 2 "gpc_reg_operand" "r")))]
13604 ""
13605 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13606 [(set_attr "type" "three")
13607 (set_attr "length" "12")])
13609 (define_insn ""
13610 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13611 (compare:CC
13612 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13613 (const_int 0))
13614 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13615 (const_int 0)))
13616 (clobber (match_scratch:SI 3 "=&r,&r"))]
13617 "TARGET_32BIT"
13618 "@
13619 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13620 #"
13621 [(set_attr "type" "compare")
13622 (set_attr "length" "12,16")])
13624 (define_split
13625 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13626 (compare:CC
13627 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13628 (const_int 0))
13629 (match_operand:SI 2 "gpc_reg_operand" ""))
13630 (const_int 0)))
13631 (clobber (match_scratch:SI 3 ""))]
13632 "TARGET_32BIT && reload_completed"
13633 [(set (match_dup 3)
13634 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13635 (match_dup 2)))
13636 (set (match_dup 0)
13637 (compare:CC (match_dup 3)
13638 (const_int 0)))]
13639 "")
13641 (define_insn ""
13642 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13643 (compare:CC
13644 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13645 (const_int 0))
13646 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13647 (const_int 0)))
13648 (clobber (match_scratch:DI 3 "=&r,&r"))]
13649 "TARGET_64BIT"
13650 "@
13651 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13652 #"
13653 [(set_attr "type" "compare")
13654 (set_attr "length" "12,16")])
13656 (define_split
13657 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13658 (compare:CC
13659 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13660 (const_int 0))
13661 (match_operand:DI 2 "gpc_reg_operand" ""))
13662 (const_int 0)))
13663 (clobber (match_scratch:DI 3 ""))]
13664 "TARGET_64BIT && reload_completed"
13665 [(set (match_dup 3)
13666 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13667 (match_dup 2)))
13668 (set (match_dup 0)
13669 (compare:CC (match_dup 3)
13670 (const_int 0)))]
13671 "")
13673 (define_insn ""
13674 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13675 (compare:CC
13676 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13677 (const_int 0))
13678 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13679 (const_int 0)))
13680 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13681 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13682 "TARGET_32BIT"
13683 "@
13684 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13685 #"
13686 [(set_attr "type" "compare")
13687 (set_attr "length" "12,16")])
13689 (define_split
13690 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13691 (compare:CC
13692 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13693 (const_int 0))
13694 (match_operand:SI 2 "gpc_reg_operand" ""))
13695 (const_int 0)))
13696 (set (match_operand:SI 0 "gpc_reg_operand" "")
13697 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13698 "TARGET_32BIT && reload_completed"
13699 [(set (match_dup 0)
13700 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13701 (set (match_dup 3)
13702 (compare:CC (match_dup 0)
13703 (const_int 0)))]
13704 "")
13706 (define_insn ""
13707 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13708 (compare:CC
13709 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13710 (const_int 0))
13711 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13712 (const_int 0)))
13713 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13714 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13715 "TARGET_64BIT"
13716 "@
13717 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13718 #"
13719 [(set_attr "type" "compare")
13720 (set_attr "length" "12,16")])
13722 (define_split
13723 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13724 (compare:CC
13725 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13726 (const_int 0))
13727 (match_operand:DI 2 "gpc_reg_operand" ""))
13728 (const_int 0)))
13729 (set (match_operand:DI 0 "gpc_reg_operand" "")
13730 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13731 "TARGET_64BIT && reload_completed"
13732 [(set (match_dup 0)
13733 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13734 (set (match_dup 3)
13735 (compare:CC (match_dup 0)
13736 (const_int 0)))]
13737 "")
13739 (define_insn ""
13740 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13741 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13742 (match_operand:SI 2 "reg_or_short_operand" "r"))
13743 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13744 "TARGET_POWER"
13745 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13746 [(set_attr "length" "12")])
13748 (define_insn ""
13749 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13750 (compare:CC
13751 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13752 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13753 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13754 (const_int 0)))
13755 (clobber (match_scratch:SI 4 "=&r,&r"))]
13756 "TARGET_POWER"
13757 "@
13758 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13759 #"
13760 [(set_attr "type" "compare")
13761 (set_attr "length" "12,16")])
13763 (define_split
13764 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13765 (compare:CC
13766 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13767 (match_operand:SI 2 "reg_or_short_operand" ""))
13768 (match_operand:SI 3 "gpc_reg_operand" ""))
13769 (const_int 0)))
13770 (clobber (match_scratch:SI 4 ""))]
13771 "TARGET_POWER && reload_completed"
13772 [(set (match_dup 4)
13773 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13774 (set (match_dup 0)
13775 (compare:CC (match_dup 4)
13776 (const_int 0)))]
13777 "")
13779 (define_insn ""
13780 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13781 (compare:CC
13782 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13783 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13784 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13785 (const_int 0)))
13786 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13787 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13788 "TARGET_POWER"
13789 "@
13790 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13791 #"
13792 [(set_attr "type" "compare")
13793 (set_attr "length" "12,16")])
13795 (define_split
13796 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13797 (compare:CC
13798 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13799 (match_operand:SI 2 "reg_or_short_operand" ""))
13800 (match_operand:SI 3 "gpc_reg_operand" ""))
13801 (const_int 0)))
13802 (set (match_operand:SI 0 "gpc_reg_operand" "")
13803 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13804 "TARGET_POWER && reload_completed"
13805 [(set (match_dup 0)
13806 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13807 (set (match_dup 4)
13808 (compare:CC (match_dup 0)
13809 (const_int 0)))]
13810 "")
13812 (define_insn ""
13813 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13814 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13815 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13816 "TARGET_POWER"
13817 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13818 [(set_attr "length" "12")])
13820 (define_insn_and_split "*gtu<mode>"
13821 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13822 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13823 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13824 ""
13825 "#"
13826 ""
13827 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13828 (set (match_dup 0) (neg:P (match_dup 0)))]
13829 "")
13831 (define_insn_and_split "*gtu<mode>_compare"
13832 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13833 (compare:CC
13834 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13835 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13836 (const_int 0)))
13837 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13838 (gtu:P (match_dup 1) (match_dup 2)))]
13839 ""
13840 "#"
13841 ""
13842 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13843 (parallel [(set (match_dup 3)
13844 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13845 (set (match_dup 0) (neg:P (match_dup 0)))])]
13846 "")
13848 (define_insn_and_split "*plus_gtu<mode>"
13849 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13850 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13851 (match_operand:P 2 "reg_or_short_operand" "rI"))
13852 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13853 ""
13854 "#"
13855 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13856 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13857 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13858 "")
13860 (define_insn_and_split "*plus_gtu<mode>_compare"
13861 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13862 (compare:CC
13863 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13864 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13865 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13866 (const_int 0)))
13867 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13868 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13869 ""
13870 "#"
13871 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13872 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13873 (parallel [(set (match_dup 4)
13874 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13875 (const_int 0)))
13876 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13877 "")
13879 (define_insn "*neg_gtu<mode>"
13880 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13881 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13882 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13883 ""
13884 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13885 [(set_attr "type" "two")
13886 (set_attr "length" "8")])
13888 \f
13889 ;; Define both directions of branch and return. If we need a reload
13890 ;; register, we'd rather use CR0 since it is much easier to copy a
13891 ;; register CC value to there.
13893 (define_insn ""
13894 [(set (pc)
13895 (if_then_else (match_operator 1 "branch_comparison_operator"
13896 [(match_operand 2
13897 "cc_reg_operand" "y")
13898 (const_int 0)])
13899 (label_ref (match_operand 0 "" ""))
13900 (pc)))]
13901 ""
13902 "*
13903 {
13904 return output_cbranch (operands[1], \"%l0\", 0, insn);
13905 }"
13906 [(set_attr "type" "branch")])
13908 (define_insn ""
13909 [(set (pc)
13910 (if_then_else (match_operator 0 "branch_comparison_operator"
13911 [(match_operand 1
13912 "cc_reg_operand" "y")
13913 (const_int 0)])
13914 (return)
13915 (pc)))]
13916 "direct_return ()"
13917 "*
13918 {
13919 return output_cbranch (operands[0], NULL, 0, insn);
13920 }"
13921 [(set_attr "type" "jmpreg")
13922 (set_attr "length" "4")])
13924 (define_insn ""
13925 [(set (pc)
13926 (if_then_else (match_operator 1 "branch_comparison_operator"
13927 [(match_operand 2
13928 "cc_reg_operand" "y")
13929 (const_int 0)])
13930 (pc)
13931 (label_ref (match_operand 0 "" ""))))]
13932 ""
13933 "*
13934 {
13935 return output_cbranch (operands[1], \"%l0\", 1, insn);
13936 }"
13937 [(set_attr "type" "branch")])
13939 (define_insn ""
13940 [(set (pc)
13941 (if_then_else (match_operator 0 "branch_comparison_operator"
13942 [(match_operand 1
13943 "cc_reg_operand" "y")
13944 (const_int 0)])
13945 (pc)
13946 (return)))]
13947 "direct_return ()"
13948 "*
13949 {
13950 return output_cbranch (operands[0], NULL, 1, insn);
13951 }"
13952 [(set_attr "type" "jmpreg")
13953 (set_attr "length" "4")])
13955 ;; Logic on condition register values.
13957 ; This pattern matches things like
13958 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13959 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13960 ; (const_int 1)))
13961 ; which are generated by the branch logic.
13962 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13964 (define_insn "*cceq_ior_compare"
13965 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13966 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13967 [(match_operator:SI 2
13968 "branch_positive_comparison_operator"
13969 [(match_operand 3
13970 "cc_reg_operand" "y,y")
13971 (const_int 0)])
13972 (match_operator:SI 4
13973 "branch_positive_comparison_operator"
13974 [(match_operand 5
13975 "cc_reg_operand" "0,y")
13976 (const_int 0)])])
13977 (const_int 1)))]
13978 ""
13979 "cr%q1 %E0,%j2,%j4"
13980 [(set_attr "type" "cr_logical,delayed_cr")])
13982 ; Why is the constant -1 here, but 1 in the previous pattern?
13983 ; Because ~1 has all but the low bit set.
13984 (define_insn ""
13985 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13986 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13987 [(not:SI (match_operator:SI 2
13988 "branch_positive_comparison_operator"
13989 [(match_operand 3
13990 "cc_reg_operand" "y,y")
13991 (const_int 0)]))
13992 (match_operator:SI 4
13993 "branch_positive_comparison_operator"
13994 [(match_operand 5
13995 "cc_reg_operand" "0,y")
13996 (const_int 0)])])
13997 (const_int -1)))]
13998 ""
13999 "cr%q1 %E0,%j2,%j4"
14000 [(set_attr "type" "cr_logical,delayed_cr")])
14002 (define_insn "*cceq_rev_compare"
14003 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14004 (compare:CCEQ (match_operator:SI 1
14005 "branch_positive_comparison_operator"
14006 [(match_operand 2
14007 "cc_reg_operand" "0,y")
14008 (const_int 0)])
14009 (const_int 0)))]
14010 ""
14011 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14012 [(set_attr "type" "cr_logical,delayed_cr")])
14014 ;; If we are comparing the result of two comparisons, this can be done
14015 ;; using creqv or crxor.
14017 (define_insn_and_split ""
14018 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14019 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14020 [(match_operand 2 "cc_reg_operand" "y")
14021 (const_int 0)])
14022 (match_operator 3 "branch_comparison_operator"
14023 [(match_operand 4 "cc_reg_operand" "y")
14024 (const_int 0)])))]
14025 ""
14026 "#"
14027 ""
14028 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14029 (match_dup 5)))]
14030 "
14031 {
14032 int positive_1, positive_2;
14034 positive_1 = branch_positive_comparison_operator (operands[1],
14035 GET_MODE (operands[1]));
14036 positive_2 = branch_positive_comparison_operator (operands[3],
14037 GET_MODE (operands[3]));
14039 if (! positive_1)
14040 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14041 GET_CODE (operands[1])),
14042 SImode,
14043 operands[2], const0_rtx);
14044 else if (GET_MODE (operands[1]) != SImode)
14045 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14046 operands[2], const0_rtx);
14048 if (! positive_2)
14049 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14050 GET_CODE (operands[3])),
14051 SImode,
14052 operands[4], const0_rtx);
14053 else if (GET_MODE (operands[3]) != SImode)
14054 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14055 operands[4], const0_rtx);
14057 if (positive_1 == positive_2)
14058 {
14059 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14060 operands[5] = constm1_rtx;
14061 }
14062 else
14063 {
14064 operands[5] = const1_rtx;
14065 }
14066 }")
14068 ;; Unconditional branch and return.
14070 (define_insn "jump"
14071 [(set (pc)
14072 (label_ref (match_operand 0 "" "")))]
14073 ""
14074 "b %l0"
14075 [(set_attr "type" "branch")])
14077 (define_insn "return"
14078 [(return)]
14079 "direct_return ()"
14080 "{br|blr}"
14081 [(set_attr "type" "jmpreg")])
14083 (define_expand "indirect_jump"
14084 [(set (pc) (match_operand 0 "register_operand" ""))])
14086 (define_insn "*indirect_jump<mode>"
14087 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14088 ""
14089 "@
14090 bctr
14091 {br|blr}"
14092 [(set_attr "type" "jmpreg")])
14094 ;; Table jump for switch statements:
14095 (define_expand "tablejump"
14096 [(use (match_operand 0 "" ""))
14097 (use (label_ref (match_operand 1 "" "")))]
14098 ""
14099 "
14100 {
14101 if (TARGET_32BIT)
14102 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14103 else
14104 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14105 DONE;
14106 }")
14108 (define_expand "tablejumpsi"
14109 [(set (match_dup 3)
14110 (plus:SI (match_operand:SI 0 "" "")
14111 (match_dup 2)))
14112 (parallel [(set (pc) (match_dup 3))
14113 (use (label_ref (match_operand 1 "" "")))])]
14114 "TARGET_32BIT"
14115 "
14116 { operands[0] = force_reg (SImode, operands[0]);
14117 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14118 operands[3] = gen_reg_rtx (SImode);
14119 }")
14121 (define_expand "tablejumpdi"
14122 [(set (match_dup 4)
14123 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14124 (set (match_dup 3)
14125 (plus:DI (match_dup 4)
14126 (match_dup 2)))
14127 (parallel [(set (pc) (match_dup 3))
14128 (use (label_ref (match_operand 1 "" "")))])]
14129 "TARGET_64BIT"
14130 "
14131 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14132 operands[3] = gen_reg_rtx (DImode);
14133 operands[4] = gen_reg_rtx (DImode);
14134 }")
14136 (define_insn "*tablejump<mode>_internal1"
14137 [(set (pc)
14138 (match_operand:P 0 "register_operand" "c,*l"))
14139 (use (label_ref (match_operand 1 "" "")))]
14140 ""
14141 "@
14142 bctr
14143 {br|blr}"
14144 [(set_attr "type" "jmpreg")])
14146 (define_insn "nop"
14147 [(const_int 0)]
14148 ""
14149 "{cror 0,0,0|nop}")
14150 \f
14151 ;; Define the subtract-one-and-jump insns, starting with the template
14152 ;; so loop.c knows what to generate.
14154 (define_expand "doloop_end"
14155 [(use (match_operand 0 "" "")) ; loop pseudo
14156 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14157 (use (match_operand 2 "" "")) ; max iterations
14158 (use (match_operand 3 "" "")) ; loop level
14159 (use (match_operand 4 "" ""))] ; label
14160 ""
14161 "
14162 {
14163 /* Only use this on innermost loops. */
14164 if (INTVAL (operands[3]) > 1)
14165 FAIL;
14166 if (TARGET_64BIT)
14167 {
14168 if (GET_MODE (operands[0]) != DImode)
14169 FAIL;
14170 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14171 }
14172 else
14173 {
14174 if (GET_MODE (operands[0]) != SImode)
14175 FAIL;
14176 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14177 }
14178 DONE;
14179 }")
14181 (define_expand "ctr<mode>"
14182 [(parallel [(set (pc)
14183 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14184 (const_int 1))
14185 (label_ref (match_operand 1 "" ""))
14186 (pc)))
14187 (set (match_dup 0)
14188 (plus:P (match_dup 0)
14189 (const_int -1)))
14190 (clobber (match_scratch:CC 2 ""))
14191 (clobber (match_scratch:P 3 ""))])]
14192 ""
14193 "")
14195 ;; We need to be able to do this for any operand, including MEM, or we
14196 ;; will cause reload to blow up since we don't allow output reloads on
14197 ;; JUMP_INSNs.
14198 ;; For the length attribute to be calculated correctly, the
14199 ;; label MUST be operand 0.
14201 (define_insn "*ctr<mode>_internal1"
14202 [(set (pc)
14203 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14204 (const_int 1))
14205 (label_ref (match_operand 0 "" ""))
14206 (pc)))
14207 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14208 (plus:P (match_dup 1)
14209 (const_int -1)))
14210 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14211 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14212 ""
14213 "*
14214 {
14215 if (which_alternative != 0)
14216 return \"#\";
14217 else if (get_attr_length (insn) == 4)
14218 return \"{bdn|bdnz} %l0\";
14219 else
14220 return \"bdz $+8\;b %l0\";
14221 }"
14222 [(set_attr "type" "branch")
14223 (set_attr "length" "*,12,16,16")])
14225 (define_insn "*ctr<mode>_internal2"
14226 [(set (pc)
14227 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14228 (const_int 1))
14229 (pc)
14230 (label_ref (match_operand 0 "" ""))))
14231 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14232 (plus:P (match_dup 1)
14233 (const_int -1)))
14234 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14235 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14236 ""
14237 "*
14238 {
14239 if (which_alternative != 0)
14240 return \"#\";
14241 else if (get_attr_length (insn) == 4)
14242 return \"bdz %l0\";
14243 else
14244 return \"{bdn|bdnz} $+8\;b %l0\";
14245 }"
14246 [(set_attr "type" "branch")
14247 (set_attr "length" "*,12,16,16")])
14249 ;; Similar but use EQ
14251 (define_insn "*ctr<mode>_internal5"
14252 [(set (pc)
14253 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14254 (const_int 1))
14255 (label_ref (match_operand 0 "" ""))
14256 (pc)))
14257 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14258 (plus:P (match_dup 1)
14259 (const_int -1)))
14260 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14261 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14262 ""
14263 "*
14264 {
14265 if (which_alternative != 0)
14266 return \"#\";
14267 else if (get_attr_length (insn) == 4)
14268 return \"bdz %l0\";
14269 else
14270 return \"{bdn|bdnz} $+8\;b %l0\";
14271 }"
14272 [(set_attr "type" "branch")
14273 (set_attr "length" "*,12,16,16")])
14275 (define_insn "*ctr<mode>_internal6"
14276 [(set (pc)
14277 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14278 (const_int 1))
14279 (pc)
14280 (label_ref (match_operand 0 "" ""))))
14281 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14282 (plus:P (match_dup 1)
14283 (const_int -1)))
14284 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14285 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14286 ""
14287 "*
14288 {
14289 if (which_alternative != 0)
14290 return \"#\";
14291 else if (get_attr_length (insn) == 4)
14292 return \"{bdn|bdnz} %l0\";
14293 else
14294 return \"bdz $+8\;b %l0\";
14295 }"
14296 [(set_attr "type" "branch")
14297 (set_attr "length" "*,12,16,16")])
14299 ;; Now the splitters if we could not allocate the CTR register
14301 (define_split
14302 [(set (pc)
14303 (if_then_else (match_operator 2 "comparison_operator"
14304 [(match_operand:P 1 "gpc_reg_operand" "")
14305 (const_int 1)])
14306 (match_operand 5 "" "")
14307 (match_operand 6 "" "")))
14308 (set (match_operand:P 0 "gpc_reg_operand" "")
14309 (plus:P (match_dup 1) (const_int -1)))
14310 (clobber (match_scratch:CC 3 ""))
14311 (clobber (match_scratch:P 4 ""))]
14312 "reload_completed"
14313 [(parallel [(set (match_dup 3)
14314 (compare:CC (plus:P (match_dup 1)
14315 (const_int -1))
14316 (const_int 0)))
14317 (set (match_dup 0)
14318 (plus:P (match_dup 1)
14319 (const_int -1)))])
14320 (set (pc) (if_then_else (match_dup 7)
14321 (match_dup 5)
14322 (match_dup 6)))]
14323 "
14324 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14325 operands[3], const0_rtx); }")
14327 (define_split
14328 [(set (pc)
14329 (if_then_else (match_operator 2 "comparison_operator"
14330 [(match_operand:P 1 "gpc_reg_operand" "")
14331 (const_int 1)])
14332 (match_operand 5 "" "")
14333 (match_operand 6 "" "")))
14334 (set (match_operand:P 0 "nonimmediate_operand" "")
14335 (plus:P (match_dup 1) (const_int -1)))
14336 (clobber (match_scratch:CC 3 ""))
14337 (clobber (match_scratch:P 4 ""))]
14338 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14339 [(parallel [(set (match_dup 3)
14340 (compare:CC (plus:P (match_dup 1)
14341 (const_int -1))
14342 (const_int 0)))
14343 (set (match_dup 4)
14344 (plus:P (match_dup 1)
14345 (const_int -1)))])
14346 (set (match_dup 0)
14347 (match_dup 4))
14348 (set (pc) (if_then_else (match_dup 7)
14349 (match_dup 5)
14350 (match_dup 6)))]
14351 "
14352 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14353 operands[3], const0_rtx); }")
14354 \f
14355 (define_insn "trap"
14356 [(trap_if (const_int 1) (const_int 0))]
14357 ""
14358 "{t 31,0,0|trap}"
14359 [(set_attr "type" "trap")])
14361 (define_expand "conditional_trap"
14362 [(trap_if (match_operator 0 "trap_comparison_operator"
14363 [(match_dup 2) (match_dup 3)])
14364 (match_operand 1 "const_int_operand" ""))]
14365 ""
14366 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14367 operands[2] = rs6000_compare_op0;
14368 operands[3] = rs6000_compare_op1;")
14370 (define_insn ""
14371 [(trap_if (match_operator 0 "trap_comparison_operator"
14372 [(match_operand:GPR 1 "register_operand" "r")
14373 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14374 (const_int 0))]
14375 ""
14376 "{t|t<wd>}%V0%I2 %1,%2"
14377 [(set_attr "type" "trap")])
14378 \f
14379 ;; Insns related to generating the function prologue and epilogue.
14381 (define_expand "prologue"
14382 [(use (const_int 0))]
14383 "TARGET_SCHED_PROLOG"
14384 "
14385 {
14386 rs6000_emit_prologue ();
14387 DONE;
14388 }")
14390 (define_insn "*movesi_from_cr_one"
14391 [(match_parallel 0 "mfcr_operation"
14392 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14393 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14394 (match_operand 3 "immediate_operand" "n")]
14395 UNSPEC_MOVESI_FROM_CR))])]
14396 "TARGET_MFCRF"
14397 "*
14398 {
14399 int mask = 0;
14400 int i;
14401 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14402 {
14403 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14404 operands[4] = GEN_INT (mask);
14405 output_asm_insn (\"mfcr %1,%4\", operands);
14406 }
14407 return \"\";
14408 }"
14409 [(set_attr "type" "mfcrf")])
14411 (define_insn "movesi_from_cr"
14412 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14413 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14414 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14415 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14416 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14417 UNSPEC_MOVESI_FROM_CR))]
14418 ""
14419 "mfcr %0"
14420 [(set_attr "type" "mfcr")])
14422 (define_insn "*stmw"
14423 [(match_parallel 0 "stmw_operation"
14424 [(set (match_operand:SI 1 "memory_operand" "=m")
14425 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14426 "TARGET_MULTIPLE"
14427 "{stm|stmw} %2,%1"
14428 [(set_attr "type" "store_ux")])
14430 (define_insn "*save_gpregs_<mode>"
14431 [(match_parallel 0 "any_parallel_operand"
14432 [(clobber (reg:P 65))
14433 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14434 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14435 (set (match_operand:P 3 "memory_operand" "=m")
14436 (match_operand:P 4 "gpc_reg_operand" "r"))])]
14437 ""
14438 "bl %z1"
14439 [(set_attr "type" "branch")
14440 (set_attr "length" "4")])
14442 (define_insn "*save_fpregs_<mode>"
14443 [(match_parallel 0 "any_parallel_operand"
14444 [(clobber (reg:P 65))
14445 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14446 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14447 (set (match_operand:DF 3 "memory_operand" "=m")
14448 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14449 ""
14450 "bl %z1"
14451 [(set_attr "type" "branch")
14452 (set_attr "length" "4")])
14454 ; These are to explain that changes to the stack pointer should
14455 ; not be moved over stores to stack memory.
14456 (define_insn "stack_tie"
14457 [(set (match_operand:BLK 0 "memory_operand" "+m")
14458 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14459 ""
14460 ""
14461 [(set_attr "length" "0")])
14464 (define_expand "epilogue"
14465 [(use (const_int 0))]
14466 "TARGET_SCHED_PROLOG"
14467 "
14468 {
14469 rs6000_emit_epilogue (FALSE);
14470 DONE;
14471 }")
14473 ; On some processors, doing the mtcrf one CC register at a time is
14474 ; faster (like on the 604e). On others, doing them all at once is
14475 ; faster; for instance, on the 601 and 750.
14477 (define_expand "movsi_to_cr_one"
14478 [(set (match_operand:CC 0 "cc_reg_operand" "")
14479 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14480 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14481 ""
14482 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14484 (define_insn "*movsi_to_cr"
14485 [(match_parallel 0 "mtcrf_operation"
14486 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14487 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14488 (match_operand 3 "immediate_operand" "n")]
14489 UNSPEC_MOVESI_TO_CR))])]
14490 ""
14491 "*
14492 {
14493 int mask = 0;
14494 int i;
14495 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14496 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14497 operands[4] = GEN_INT (mask);
14498 return \"mtcrf %4,%2\";
14499 }"
14500 [(set_attr "type" "mtcr")])
14502 (define_insn "*mtcrfsi"
14503 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14504 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14505 (match_operand 2 "immediate_operand" "n")]
14506 UNSPEC_MOVESI_TO_CR))]
14507 "GET_CODE (operands[0]) == REG
14508 && CR_REGNO_P (REGNO (operands[0]))
14509 && GET_CODE (operands[2]) == CONST_INT
14510 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14511 "mtcrf %R0,%1"
14512 [(set_attr "type" "mtcr")])
14514 ; The load-multiple instructions have similar properties.
14515 ; Note that "load_multiple" is a name known to the machine-independent
14516 ; code that actually corresponds to the PowerPC load-string.
14518 (define_insn "*lmw"
14519 [(match_parallel 0 "lmw_operation"
14520 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14521 (match_operand:SI 2 "memory_operand" "m"))])]
14522 "TARGET_MULTIPLE"
14523 "{lm|lmw} %1,%2"
14524 [(set_attr "type" "load_ux")])
14526 (define_insn "*return_internal_<mode>"
14527 [(return)
14528 (use (match_operand:P 0 "register_operand" "lc"))]
14529 ""
14530 "b%T0"
14531 [(set_attr "type" "jmpreg")])
14533 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14534 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14536 (define_insn "*restore_gpregs_<mode>"
14537 [(match_parallel 0 "any_parallel_operand"
14538 [(clobber (match_operand:P 1 "register_operand" "=l"))
14539 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14540 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14541 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14542 (match_operand:P 5 "memory_operand" "m"))])]
14543 ""
14544 "bl %z2"
14545 [(set_attr "type" "branch")
14546 (set_attr "length" "4")])
14548 (define_insn "*return_and_restore_gpregs_<mode>"
14549 [(match_parallel 0 "any_parallel_operand"
14550 [(return)
14551 (clobber (match_operand:P 1 "register_operand" "=l"))
14552 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14553 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14554 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14555 (match_operand:P 5 "memory_operand" "m"))])]
14556 ""
14557 "b %z2"
14558 [(set_attr "type" "branch")
14559 (set_attr "length" "4")])
14561 (define_insn "*return_and_restore_fpregs_<mode>"
14562 [(match_parallel 0 "any_parallel_operand"
14563 [(return)
14564 (clobber (match_operand:P 1 "register_operand" "=l"))
14565 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14566 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14567 (set (match_operand:DF 4 "gpc_reg_operand" "=f")
14568 (match_operand:DF 5 "memory_operand" "m"))])]
14569 ""
14570 "b %z2"
14571 [(set_attr "type" "branch")
14572 (set_attr "length" "4")])
14574 ; This is used in compiling the unwind routines.
14575 (define_expand "eh_return"
14576 [(use (match_operand 0 "general_operand" ""))]
14577 ""
14578 "
14579 {
14580 if (TARGET_32BIT)
14581 emit_insn (gen_eh_set_lr_si (operands[0]));
14582 else
14583 emit_insn (gen_eh_set_lr_di (operands[0]));
14584 DONE;
14585 }")
14587 ; We can't expand this before we know where the link register is stored.
14588 (define_insn "eh_set_lr_<mode>"
14589 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14590 UNSPECV_EH_RR)
14591 (clobber (match_scratch:P 1 "=&b"))]
14592 ""
14593 "#")
14595 (define_split
14596 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14597 (clobber (match_scratch 1 ""))]
14598 "reload_completed"
14599 [(const_int 0)]
14600 "
14601 {
14602 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14603 DONE;
14604 }")
14606 (define_insn "prefetch"
14607 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14608 (match_operand:SI 1 "const_int_operand" "n")
14609 (match_operand:SI 2 "const_int_operand" "n"))]
14610 "TARGET_POWERPC"
14611 "*
14612 {
14613 if (GET_CODE (operands[0]) == REG)
14614 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14615 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14616 }"
14617 [(set_attr "type" "load")])
14618 \f
14620 (include "sync.md")
14621 (include "altivec.md")
14622 (include "spe.md")
14623 (include "dfp.md")
14624 (include "paired.md")