1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
26 #include "rtl-error.h"
28 #include "insn-config.h"
29 #include "insn-attr.h"
30 #include "hard-reg-set.h"
33 #include "addresses.h"
37 #include "basic-block.h"
40 #include "tree-pass.h"
42 #include "insn-codes.h"
44 #ifndef STACK_PUSH_CODE
45 #ifdef STACK_GROWS_DOWNWARD
46 #define STACK_PUSH_CODE PRE_DEC
48 #define STACK_PUSH_CODE PRE_INC
52 #ifndef STACK_POP_CODE
53 #ifdef STACK_GROWS_DOWNWARD
54 #define STACK_POP_CODE POST_INC
56 #define STACK_POP_CODE POST_DEC
60 static void validate_replace_rtx_1 (rtx
*, rtx
, rtx
, rtx
, bool);
61 static void validate_replace_src_1 (rtx
*, void *);
62 static rtx
split_insn (rtx
);
64 /* Nonzero means allow operands to be volatile.
65 This should be 0 if you are generating rtl, such as if you are calling
66 the functions in optabs.c and expmed.c (most of the time).
67 This should be 1 if all valid insns need to be recognized,
68 such as in reginfo.c and final.c and reload.c.
70 init_recog and init_recog_no_volatile are responsible for setting this. */
74 struct recog_data_d recog_data
;
76 /* Contains a vector of operand_alternative structures for every operand.
77 Set up by preprocess_constraints. */
78 struct operand_alternative recog_op_alt
[MAX_RECOG_OPERANDS
][MAX_RECOG_ALTERNATIVES
];
80 /* On return from `constrain_operands', indicate which alternative
83 int which_alternative
;
85 /* Nonzero after end of reload pass.
86 Set to 1 or 0 by toplev.c.
87 Controls the significance of (SUBREG (MEM)). */
91 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
92 int epilogue_completed
;
94 /* Initialize data used by the function `recog'.
95 This must be called once in the compilation of a function
96 before any insn recognition may be done in the function. */
99 init_recog_no_volatile (void)
111 /* Return true if labels in asm operands BODY are LABEL_REFs. */
114 asm_labels_ok (rtx body
)
119 asmop
= extract_asm_operands (body
);
120 if (asmop
== NULL_RTX
)
123 for (i
= 0; i
< ASM_OPERANDS_LABEL_LENGTH (asmop
); i
++)
124 if (GET_CODE (ASM_OPERANDS_LABEL (asmop
, i
)) != LABEL_REF
)
130 /* Check that X is an insn-body for an `asm' with operands
131 and that the operands mentioned in it are legitimate. */
134 check_asm_operands (rtx x
)
138 const char **constraints
;
141 if (!asm_labels_ok (x
))
144 /* Post-reload, be more strict with things. */
145 if (reload_completed
)
147 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
148 extract_insn (make_insn_raw (x
));
149 constrain_operands (1);
150 return which_alternative
>= 0;
153 noperands
= asm_noperands (x
);
159 operands
= XALLOCAVEC (rtx
, noperands
);
160 constraints
= XALLOCAVEC (const char *, noperands
);
162 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
, NULL
);
164 for (i
= 0; i
< noperands
; i
++)
166 const char *c
= constraints
[i
];
169 if (! asm_operand_ok (operands
[i
], c
, constraints
))
176 /* Static data for the next two routines. */
178 typedef struct change_t
187 static change_t
*changes
;
188 static int changes_allocated
;
190 static int num_changes
= 0;
192 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
193 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
194 the change is simply made.
196 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
197 will be called with the address and mode as parameters. If OBJECT is
198 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
201 IN_GROUP is nonzero if this is part of a group of changes that must be
202 performed as a group. In that case, the changes will be stored. The
203 function `apply_change_group' will validate and apply the changes.
205 If IN_GROUP is zero, this is a single change. Try to recognize the insn
206 or validate the memory reference with the change applied. If the result
207 is not valid for the machine, suppress the change and return zero.
208 Otherwise, perform the change and return 1. */
211 validate_change_1 (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
, bool unshare
)
215 if (old
== new_rtx
|| rtx_equal_p (old
, new_rtx
))
218 gcc_assert (in_group
!= 0 || num_changes
== 0);
222 /* Save the information describing this change. */
223 if (num_changes
>= changes_allocated
)
225 if (changes_allocated
== 0)
226 /* This value allows for repeated substitutions inside complex
227 indexed addresses, or changes in up to 5 insns. */
228 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
230 changes_allocated
*= 2;
232 changes
= XRESIZEVEC (change_t
, changes
, changes_allocated
);
235 changes
[num_changes
].object
= object
;
236 changes
[num_changes
].loc
= loc
;
237 changes
[num_changes
].old
= old
;
238 changes
[num_changes
].unshare
= unshare
;
240 if (object
&& !MEM_P (object
))
242 /* Set INSN_CODE to force rerecognition of insn. Save old code in
244 changes
[num_changes
].old_code
= INSN_CODE (object
);
245 INSN_CODE (object
) = -1;
250 /* If we are making a group of changes, return 1. Otherwise, validate the
251 change group we made. */
256 return apply_change_group ();
259 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
263 validate_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
265 return validate_change_1 (object
, loc
, new_rtx
, in_group
, false);
268 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
272 validate_unshare_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
274 return validate_change_1 (object
, loc
, new_rtx
, in_group
, true);
278 /* Keep X canonicalized if some changes have made it non-canonical; only
279 modifies the operands of X, not (for example) its code. Simplifications
280 are not the job of this routine.
282 Return true if anything was changed. */
284 canonicalize_change_group (rtx insn
, rtx x
)
286 if (COMMUTATIVE_P (x
)
287 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
289 /* Oops, the caller has made X no longer canonical.
290 Let's redo the changes in the correct order. */
291 rtx tem
= XEXP (x
, 0);
292 validate_unshare_change (insn
, &XEXP (x
, 0), XEXP (x
, 1), 1);
293 validate_unshare_change (insn
, &XEXP (x
, 1), tem
, 1);
301 /* This subroutine of apply_change_group verifies whether the changes to INSN
302 were valid; i.e. whether INSN can still be recognized.
304 If IN_GROUP is true clobbers which have to be added in order to
305 match the instructions will be added to the current change group.
306 Otherwise the changes will take effect immediately. */
309 insn_invalid_p (rtx insn
, bool in_group
)
311 rtx pat
= PATTERN (insn
);
312 int num_clobbers
= 0;
313 /* If we are before reload and the pattern is a SET, see if we can add
315 int icode
= recog (pat
, insn
,
316 (GET_CODE (pat
) == SET
317 && ! reload_completed
318 && ! reload_in_progress
)
319 ? &num_clobbers
: 0);
320 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
323 /* If this is an asm and the operand aren't legal, then fail. Likewise if
324 this is not an asm and the insn wasn't recognized. */
325 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
326 || (!is_asm
&& icode
< 0))
329 /* If we have to add CLOBBERs, fail if we have to add ones that reference
330 hard registers since our callers can't know if they are live or not.
331 Otherwise, add them. */
332 if (num_clobbers
> 0)
336 if (added_clobbers_hard_reg_p (icode
))
339 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
340 XVECEXP (newpat
, 0, 0) = pat
;
341 add_clobbers (newpat
, icode
);
343 validate_change (insn
, &PATTERN (insn
), newpat
, 1);
345 PATTERN (insn
) = pat
= newpat
;
348 /* After reload, verify that all constraints are satisfied. */
349 if (reload_completed
)
353 if (! constrain_operands (1))
357 INSN_CODE (insn
) = icode
;
361 /* Return number of changes made and not validated yet. */
363 num_changes_pending (void)
368 /* Tentatively apply the changes numbered NUM and up.
369 Return 1 if all changes are valid, zero otherwise. */
372 verify_changes (int num
)
375 rtx last_validated
= NULL_RTX
;
377 /* The changes have been applied and all INSN_CODEs have been reset to force
380 The changes are valid if we aren't given an object, or if we are
381 given a MEM and it still is a valid address, or if this is in insn
382 and it is recognized. In the latter case, if reload has completed,
383 we also require that the operands meet the constraints for
386 for (i
= num
; i
< num_changes
; i
++)
388 rtx object
= changes
[i
].object
;
390 /* If there is no object to test or if it is the same as the one we
391 already tested, ignore it. */
392 if (object
== 0 || object
== last_validated
)
397 if (! memory_address_addr_space_p (GET_MODE (object
),
399 MEM_ADDR_SPACE (object
)))
402 else if (/* changes[i].old might be zero, e.g. when putting a
403 REG_FRAME_RELATED_EXPR into a previously empty list. */
405 && REG_P (changes
[i
].old
)
406 && asm_noperands (PATTERN (object
)) > 0
407 && REG_EXPR (changes
[i
].old
) != NULL_TREE
408 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes
[i
].old
))
409 && DECL_REGISTER (REG_EXPR (changes
[i
].old
)))
411 /* Don't allow changes of hard register operands to inline
412 assemblies if they have been defined as register asm ("x"). */
415 else if (DEBUG_INSN_P (object
))
417 else if (insn_invalid_p (object
, true))
419 rtx pat
= PATTERN (object
);
421 /* Perhaps we couldn't recognize the insn because there were
422 extra CLOBBERs at the end. If so, try to re-recognize
423 without the last CLOBBER (later iterations will cause each of
424 them to be eliminated, in turn). But don't do this if we
425 have an ASM_OPERAND. */
426 if (GET_CODE (pat
) == PARALLEL
427 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
428 && asm_noperands (PATTERN (object
)) < 0)
432 if (XVECLEN (pat
, 0) == 2)
433 newpat
= XVECEXP (pat
, 0, 0);
439 = gen_rtx_PARALLEL (VOIDmode
,
440 rtvec_alloc (XVECLEN (pat
, 0) - 1));
441 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
442 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
445 /* Add a new change to this group to replace the pattern
446 with this new pattern. Then consider this change
447 as having succeeded. The change we added will
448 cause the entire call to fail if things remain invalid.
450 Note that this can lose if a later change than the one
451 we are processing specified &XVECEXP (PATTERN (object), 0, X)
452 but this shouldn't occur. */
454 validate_change (object
, &PATTERN (object
), newpat
, 1);
457 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
458 || GET_CODE (pat
) == VAR_LOCATION
)
459 /* If this insn is a CLOBBER or USE, it is always valid, but is
465 last_validated
= object
;
468 return (i
== num_changes
);
471 /* A group of changes has previously been issued with validate_change
472 and verified with verify_changes. Call df_insn_rescan for each of
473 the insn changed and clear num_changes. */
476 confirm_change_group (void)
479 rtx last_object
= NULL
;
481 for (i
= 0; i
< num_changes
; i
++)
483 rtx object
= changes
[i
].object
;
485 if (changes
[i
].unshare
)
486 *changes
[i
].loc
= copy_rtx (*changes
[i
].loc
);
488 /* Avoid unnecessary rescanning when multiple changes to same instruction
492 if (object
!= last_object
&& last_object
&& INSN_P (last_object
))
493 df_insn_rescan (last_object
);
494 last_object
= object
;
498 if (last_object
&& INSN_P (last_object
))
499 df_insn_rescan (last_object
);
503 /* Apply a group of changes previously issued with `validate_change'.
504 If all changes are valid, call confirm_change_group and return 1,
505 otherwise, call cancel_changes and return 0. */
508 apply_change_group (void)
510 if (verify_changes (0))
512 confirm_change_group ();
523 /* Return the number of changes so far in the current group. */
526 num_validated_changes (void)
531 /* Retract the changes numbered NUM and up. */
534 cancel_changes (int num
)
538 /* Back out all the changes. Do this in the opposite order in which
540 for (i
= num_changes
- 1; i
>= num
; i
--)
542 *changes
[i
].loc
= changes
[i
].old
;
543 if (changes
[i
].object
&& !MEM_P (changes
[i
].object
))
544 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
549 /* Reduce conditional compilation elsewhere. */
552 #define CODE_FOR_extv CODE_FOR_nothing
556 #define CODE_FOR_extzv CODE_FOR_nothing
559 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
563 simplify_while_replacing (rtx
*loc
, rtx to
, rtx object
,
564 enum machine_mode op0_mode
)
567 enum rtx_code code
= GET_CODE (x
);
570 if (SWAPPABLE_OPERANDS_P (x
)
571 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
573 validate_unshare_change (object
, loc
,
574 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x
) ? code
575 : swap_condition (code
),
576 GET_MODE (x
), XEXP (x
, 1),
585 /* If we have a PLUS whose second operand is now a CONST_INT, use
586 simplify_gen_binary to try to simplify it.
587 ??? We may want later to remove this, once simplification is
588 separated from this function. */
589 if (CONST_INT_P (XEXP (x
, 1)) && XEXP (x
, 1) == to
)
590 validate_change (object
, loc
,
592 (PLUS
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1)), 1);
595 if (CONST_SCALAR_INT_P (XEXP (x
, 1)))
596 validate_change (object
, loc
,
598 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
599 simplify_gen_unary (NEG
,
600 GET_MODE (x
), XEXP (x
, 1),
605 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
607 new_rtx
= simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
609 /* If any of the above failed, substitute in something that
610 we know won't be recognized. */
612 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
613 validate_change (object
, loc
, new_rtx
, 1);
617 /* All subregs possible to simplify should be simplified. */
618 new_rtx
= simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
621 /* Subregs of VOIDmode operands are incorrect. */
622 if (!new_rtx
&& GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
623 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
625 validate_change (object
, loc
, new_rtx
, 1);
629 /* If we are replacing a register with memory, try to change the memory
630 to be the mode required for memory in extract operations (this isn't
631 likely to be an insertion operation; if it was, nothing bad will
632 happen, we might just fail in some cases). */
634 if (MEM_P (XEXP (x
, 0))
635 && CONST_INT_P (XEXP (x
, 1))
636 && CONST_INT_P (XEXP (x
, 2))
637 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0),
638 MEM_ADDR_SPACE (XEXP (x
, 0)))
639 && !MEM_VOLATILE_P (XEXP (x
, 0)))
641 enum machine_mode wanted_mode
= VOIDmode
;
642 enum machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
643 int pos
= INTVAL (XEXP (x
, 2));
645 if (GET_CODE (x
) == ZERO_EXTRACT
&& HAVE_extzv
)
647 wanted_mode
= insn_data
[CODE_FOR_extzv
].operand
[1].mode
;
648 if (wanted_mode
== VOIDmode
)
649 wanted_mode
= word_mode
;
651 else if (GET_CODE (x
) == SIGN_EXTRACT
&& HAVE_extv
)
653 wanted_mode
= insn_data
[CODE_FOR_extv
].operand
[1].mode
;
654 if (wanted_mode
== VOIDmode
)
655 wanted_mode
= word_mode
;
658 /* If we have a narrower mode, we can do something. */
659 if (wanted_mode
!= VOIDmode
660 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
662 int offset
= pos
/ BITS_PER_UNIT
;
665 /* If the bytes and bits are counted differently, we
666 must adjust the offset. */
667 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
669 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
672 gcc_assert (GET_MODE_PRECISION (wanted_mode
)
673 == GET_MODE_BITSIZE (wanted_mode
));
674 pos
%= GET_MODE_BITSIZE (wanted_mode
);
676 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
678 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
679 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
690 /* Replace every occurrence of FROM in X with TO. Mark each change with
691 validate_change passing OBJECT. */
694 validate_replace_rtx_1 (rtx
*loc
, rtx from
, rtx to
, rtx object
,
701 enum machine_mode op0_mode
= VOIDmode
;
702 int prev_changes
= num_changes
;
708 fmt
= GET_RTX_FORMAT (code
);
710 op0_mode
= GET_MODE (XEXP (x
, 0));
712 /* X matches FROM if it is the same rtx or they are both referring to the
713 same register in the same mode. Avoid calling rtx_equal_p unless the
714 operands look similar. */
717 || (REG_P (x
) && REG_P (from
)
718 && GET_MODE (x
) == GET_MODE (from
)
719 && REGNO (x
) == REGNO (from
))
720 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
721 && rtx_equal_p (x
, from
)))
723 validate_unshare_change (object
, loc
, to
, 1);
727 /* Call ourself recursively to perform the replacements.
728 We must not replace inside already replaced expression, otherwise we
729 get infinite recursion for replacements like (reg X)->(subreg (reg X))
730 so we must special case shared ASM_OPERANDS. */
732 if (GET_CODE (x
) == PARALLEL
)
734 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
736 if (j
&& GET_CODE (XVECEXP (x
, 0, j
)) == SET
737 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == ASM_OPERANDS
)
739 /* Verify that operands are really shared. */
740 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x
, 0, 0)))
741 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
743 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x
, 0, j
)),
744 from
, to
, object
, simplify
);
747 validate_replace_rtx_1 (&XVECEXP (x
, 0, j
), from
, to
, object
,
752 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
755 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
, simplify
);
756 else if (fmt
[i
] == 'E')
757 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
758 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
,
762 /* If we didn't substitute, there is nothing more to do. */
763 if (num_changes
== prev_changes
)
766 /* ??? The regmove is no more, so is this aberration still necessary? */
767 /* Allow substituted expression to have different mode. This is used by
768 regmove to change mode of pseudo register. */
769 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
770 op0_mode
= GET_MODE (XEXP (x
, 0));
772 /* Do changes needed to keep rtx consistent. Don't do any other
773 simplifications, as it is not our job. */
775 simplify_while_replacing (loc
, to
, object
, op0_mode
);
778 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
779 with TO. After all changes have been made, validate by seeing
780 if INSN is still valid. */
783 validate_replace_rtx_subexp (rtx from
, rtx to
, rtx insn
, rtx
*loc
)
785 validate_replace_rtx_1 (loc
, from
, to
, insn
, true);
786 return apply_change_group ();
789 /* Try replacing every occurrence of FROM in INSN with TO. After all
790 changes have been made, validate by seeing if INSN is still valid. */
793 validate_replace_rtx (rtx from
, rtx to
, rtx insn
)
795 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
796 return apply_change_group ();
799 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
800 is a part of INSN. After all changes have been made, validate by seeing if
802 validate_replace_rtx (from, to, insn) is equivalent to
803 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
806 validate_replace_rtx_part (rtx from
, rtx to
, rtx
*where
, rtx insn
)
808 validate_replace_rtx_1 (where
, from
, to
, insn
, true);
809 return apply_change_group ();
812 /* Same as above, but do not simplify rtx afterwards. */
814 validate_replace_rtx_part_nosimplify (rtx from
, rtx to
, rtx
*where
,
817 validate_replace_rtx_1 (where
, from
, to
, insn
, false);
818 return apply_change_group ();
822 /* Try replacing every occurrence of FROM in INSN with TO. This also
823 will replace in REG_EQUAL and REG_EQUIV notes. */
826 validate_replace_rtx_group (rtx from
, rtx to
, rtx insn
)
829 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
830 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
831 if (REG_NOTE_KIND (note
) == REG_EQUAL
832 || REG_NOTE_KIND (note
) == REG_EQUIV
)
833 validate_replace_rtx_1 (&XEXP (note
, 0), from
, to
, insn
, true);
836 /* Function called by note_uses to replace used subexpressions. */
837 struct validate_replace_src_data
839 rtx from
; /* Old RTX */
840 rtx to
; /* New RTX */
841 rtx insn
; /* Insn in which substitution is occurring. */
845 validate_replace_src_1 (rtx
*x
, void *data
)
847 struct validate_replace_src_data
*d
848 = (struct validate_replace_src_data
*) data
;
850 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
, true);
853 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
857 validate_replace_src_group (rtx from
, rtx to
, rtx insn
)
859 struct validate_replace_src_data d
;
864 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
867 /* Try simplify INSN.
868 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
869 pattern and return true if something was simplified. */
872 validate_simplify_insn (rtx insn
)
878 pat
= PATTERN (insn
);
880 if (GET_CODE (pat
) == SET
)
882 newpat
= simplify_rtx (SET_SRC (pat
));
883 if (newpat
&& !rtx_equal_p (SET_SRC (pat
), newpat
))
884 validate_change (insn
, &SET_SRC (pat
), newpat
, 1);
885 newpat
= simplify_rtx (SET_DEST (pat
));
886 if (newpat
&& !rtx_equal_p (SET_DEST (pat
), newpat
))
887 validate_change (insn
, &SET_DEST (pat
), newpat
, 1);
889 else if (GET_CODE (pat
) == PARALLEL
)
890 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
892 rtx s
= XVECEXP (pat
, 0, i
);
894 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
896 newpat
= simplify_rtx (SET_SRC (s
));
897 if (newpat
&& !rtx_equal_p (SET_SRC (s
), newpat
))
898 validate_change (insn
, &SET_SRC (s
), newpat
, 1);
899 newpat
= simplify_rtx (SET_DEST (s
));
900 if (newpat
&& !rtx_equal_p (SET_DEST (s
), newpat
))
901 validate_change (insn
, &SET_DEST (s
), newpat
, 1);
904 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
908 /* Return 1 if the insn using CC0 set by INSN does not contain
909 any ordered tests applied to the condition codes.
910 EQ and NE tests do not count. */
913 next_insn_tests_no_inequality (rtx insn
)
915 rtx next
= next_cc0_user (insn
);
917 /* If there is no next insn, we have to take the conservative choice. */
921 return (INSN_P (next
)
922 && ! inequality_comparisons_p (PATTERN (next
)));
926 /* Return 1 if OP is a valid general operand for machine mode MODE.
927 This is either a register reference, a memory reference,
928 or a constant. In the case of a memory reference, the address
929 is checked for general validity for the target machine.
931 Register and memory references must have mode MODE in order to be valid,
932 but some constants have no machine mode and are valid for any mode.
934 If MODE is VOIDmode, OP is checked for validity for whatever mode
937 The main use of this function is as a predicate in match_operand
938 expressions in the machine description. */
941 general_operand (rtx op
, enum machine_mode mode
)
943 enum rtx_code code
= GET_CODE (op
);
945 if (mode
== VOIDmode
)
946 mode
= GET_MODE (op
);
948 /* Don't accept CONST_INT or anything similar
949 if the caller wants something floating. */
950 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
951 && GET_MODE_CLASS (mode
) != MODE_INT
952 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
957 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
961 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
963 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
964 && targetm
.legitimate_constant_p (mode
== VOIDmode
968 /* Except for certain constants with VOIDmode, already checked for,
969 OP's mode must match MODE if MODE specifies a mode. */
971 if (GET_MODE (op
) != mode
)
976 rtx sub
= SUBREG_REG (op
);
978 #ifdef INSN_SCHEDULING
979 /* On machines that have insn scheduling, we want all memory
980 reference to be explicit, so outlaw paradoxical SUBREGs.
981 However, we must allow them after reload so that they can
982 get cleaned up by cleanup_subreg_operands. */
983 if (!reload_completed
&& MEM_P (sub
)
984 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (sub
)))
987 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
988 may result in incorrect reference. We should simplify all valid
989 subregs of MEM anyway. But allow this after reload because we
990 might be called from cleanup_subreg_operands.
992 ??? This is a kludge. */
993 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
997 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
998 create such rtl, and we must reject it. */
999 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1000 /* LRA can use subreg to store a floating point value in an
1001 integer mode. Although the floating point and the
1002 integer modes need the same number of hard registers, the
1003 size of floating point mode can be less than the integer
1005 && ! lra_in_progress
1006 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1010 code
= GET_CODE (op
);
1014 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1015 || in_hard_reg_set_p (operand_reg_set
, GET_MODE (op
), REGNO (op
)));
1019 rtx y
= XEXP (op
, 0);
1021 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
1024 /* Use the mem's mode, since it will be reloaded thus. LRA can
1025 generate move insn with invalid addresses which is made valid
1026 and efficiently calculated by LRA through further numerous
1029 || memory_address_addr_space_p (GET_MODE (op
), y
, MEM_ADDR_SPACE (op
)))
1036 /* Return 1 if OP is a valid memory address for a memory reference
1039 The main use of this function is as a predicate in match_operand
1040 expressions in the machine description. */
1043 address_operand (rtx op
, enum machine_mode mode
)
1045 return memory_address_p (mode
, op
);
1048 /* Return 1 if OP is a register reference of mode MODE.
1049 If MODE is VOIDmode, accept a register in any mode.
1051 The main use of this function is as a predicate in match_operand
1052 expressions in the machine description. */
1055 register_operand (rtx op
, enum machine_mode mode
)
1057 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1060 if (GET_CODE (op
) == SUBREG
)
1062 rtx sub
= SUBREG_REG (op
);
1064 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1065 because it is guaranteed to be reloaded into one.
1066 Just make sure the MEM is valid in itself.
1067 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1068 but currently it does result from (SUBREG (REG)...) where the
1069 reg went on the stack.) */
1070 if (! reload_completed
&& MEM_P (sub
))
1071 return general_operand (op
, mode
);
1073 #ifdef CANNOT_CHANGE_MODE_CLASS
1075 && REGNO (sub
) < FIRST_PSEUDO_REGISTER
1076 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub
), GET_MODE (sub
), mode
)
1077 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_INT
1078 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_FLOAT
1079 /* LRA can generate some invalid SUBREGS just for matched
1080 operand reload presentation. LRA needs to treat them as
1082 && ! LRA_SUBREG_P (op
))
1086 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1087 create such rtl, and we must reject it. */
1088 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1089 /* LRA can use subreg to store a floating point value in an
1090 integer mode. Although the floating point and the
1091 integer modes need the same number of hard registers, the
1092 size of floating point mode can be less than the integer
1094 && ! lra_in_progress
1095 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1102 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1103 || in_hard_reg_set_p (operand_reg_set
,
1104 GET_MODE (op
), REGNO (op
))));
1107 /* Return 1 for a register in Pmode; ignore the tested mode. */
1110 pmode_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1112 return register_operand (op
, Pmode
);
1115 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1116 or a hard register. */
1119 scratch_operand (rtx op
, enum machine_mode mode
)
1121 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1124 return (GET_CODE (op
) == SCRATCH
1126 && (lra_in_progress
|| REGNO (op
) < FIRST_PSEUDO_REGISTER
)));
1129 /* Return 1 if OP is a valid immediate operand for mode MODE.
1131 The main use of this function is as a predicate in match_operand
1132 expressions in the machine description. */
1135 immediate_operand (rtx op
, enum machine_mode mode
)
1137 /* Don't accept CONST_INT or anything similar
1138 if the caller wants something floating. */
1139 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1140 && GET_MODE_CLASS (mode
) != MODE_INT
1141 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1144 if (CONST_INT_P (op
)
1146 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1149 return (CONSTANT_P (op
)
1150 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1151 || GET_MODE (op
) == VOIDmode
)
1152 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1153 && targetm
.legitimate_constant_p (mode
== VOIDmode
1158 /* Returns 1 if OP is an operand that is a CONST_INT. */
1161 const_int_operand (rtx op
, enum machine_mode mode
)
1163 if (!CONST_INT_P (op
))
1166 if (mode
!= VOIDmode
1167 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1173 /* Returns 1 if OP is an operand that is a constant integer or constant
1174 floating-point number. */
1177 const_double_operand (rtx op
, enum machine_mode mode
)
1179 /* Don't accept CONST_INT or anything similar
1180 if the caller wants something floating. */
1181 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1182 && GET_MODE_CLASS (mode
) != MODE_INT
1183 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1186 return ((CONST_DOUBLE_P (op
) || CONST_INT_P (op
))
1187 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1188 || GET_MODE (op
) == VOIDmode
));
1191 /* Return 1 if OP is a general operand that is not an immediate operand. */
1194 nonimmediate_operand (rtx op
, enum machine_mode mode
)
1196 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1199 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1202 nonmemory_operand (rtx op
, enum machine_mode mode
)
1204 if (CONSTANT_P (op
))
1205 return immediate_operand (op
, mode
);
1207 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1210 if (GET_CODE (op
) == SUBREG
)
1212 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1213 because it is guaranteed to be reloaded into one.
1214 Just make sure the MEM is valid in itself.
1215 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1216 but currently it does result from (SUBREG (REG)...) where the
1217 reg went on the stack.) */
1218 if (! reload_completed
&& MEM_P (SUBREG_REG (op
)))
1219 return general_operand (op
, mode
);
1220 op
= SUBREG_REG (op
);
1224 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1225 || in_hard_reg_set_p (operand_reg_set
,
1226 GET_MODE (op
), REGNO (op
))));
1229 /* Return 1 if OP is a valid operand that stands for pushing a
1230 value of mode MODE onto the stack.
1232 The main use of this function is as a predicate in match_operand
1233 expressions in the machine description. */
1236 push_operand (rtx op
, enum machine_mode mode
)
1238 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1240 #ifdef PUSH_ROUNDING
1241 rounded_size
= PUSH_ROUNDING (rounded_size
);
1247 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1252 if (rounded_size
== GET_MODE_SIZE (mode
))
1254 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1259 if (GET_CODE (op
) != PRE_MODIFY
1260 || GET_CODE (XEXP (op
, 1)) != PLUS
1261 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1262 || !CONST_INT_P (XEXP (XEXP (op
, 1), 1))
1263 #ifdef STACK_GROWS_DOWNWARD
1264 || INTVAL (XEXP (XEXP (op
, 1), 1)) != - (int) rounded_size
1266 || INTVAL (XEXP (XEXP (op
, 1), 1)) != (int) rounded_size
1272 return XEXP (op
, 0) == stack_pointer_rtx
;
1275 /* Return 1 if OP is a valid operand that stands for popping a
1276 value of mode MODE off the stack.
1278 The main use of this function is as a predicate in match_operand
1279 expressions in the machine description. */
1282 pop_operand (rtx op
, enum machine_mode mode
)
1287 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1292 if (GET_CODE (op
) != STACK_POP_CODE
)
1295 return XEXP (op
, 0) == stack_pointer_rtx
;
1298 /* Return 1 if ADDR is a valid memory address
1299 for mode MODE in address space AS. */
1302 memory_address_addr_space_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
1303 rtx addr
, addr_space_t as
)
1305 #ifdef GO_IF_LEGITIMATE_ADDRESS
1306 gcc_assert (ADDR_SPACE_GENERIC_P (as
));
1307 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1313 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
1317 /* Return 1 if OP is a valid memory reference with mode MODE,
1318 including a valid address.
1320 The main use of this function is as a predicate in match_operand
1321 expressions in the machine description. */
1324 memory_operand (rtx op
, enum machine_mode mode
)
1328 if (! reload_completed
)
1329 /* Note that no SUBREG is a memory operand before end of reload pass,
1330 because (SUBREG (MEM...)) forces reloading into a register. */
1331 return MEM_P (op
) && general_operand (op
, mode
);
1333 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1337 if (GET_CODE (inner
) == SUBREG
)
1338 inner
= SUBREG_REG (inner
);
1340 return (MEM_P (inner
) && general_operand (op
, mode
));
1343 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1344 that is, a memory reference whose address is a general_operand. */
1347 indirect_operand (rtx op
, enum machine_mode mode
)
1349 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1350 if (! reload_completed
1351 && GET_CODE (op
) == SUBREG
&& MEM_P (SUBREG_REG (op
)))
1353 int offset
= SUBREG_BYTE (op
);
1354 rtx inner
= SUBREG_REG (op
);
1356 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1359 /* The only way that we can have a general_operand as the resulting
1360 address is if OFFSET is zero and the address already is an operand
1361 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1364 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1365 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1366 && CONST_INT_P (XEXP (XEXP (inner
, 0), 1))
1367 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1368 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1372 && memory_operand (op
, mode
)
1373 && general_operand (XEXP (op
, 0), Pmode
));
1376 /* Return 1 if this is an ordered comparison operator (not including
1377 ORDERED and UNORDERED). */
1380 ordered_comparison_operator (rtx op
, enum machine_mode mode
)
1382 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1384 switch (GET_CODE (op
))
1402 /* Return 1 if this is a comparison operator. This allows the use of
1403 MATCH_OPERATOR to recognize all the branch insns. */
1406 comparison_operator (rtx op
, enum machine_mode mode
)
1408 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1409 && COMPARISON_P (op
));
1412 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1415 extract_asm_operands (rtx body
)
1418 switch (GET_CODE (body
))
1424 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1425 tmp
= SET_SRC (body
);
1426 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1431 tmp
= XVECEXP (body
, 0, 0);
1432 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1434 if (GET_CODE (tmp
) == SET
)
1436 tmp
= SET_SRC (tmp
);
1437 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1448 /* If BODY is an insn body that uses ASM_OPERANDS,
1449 return the number of operands (both input and output) in the insn.
1450 Otherwise return -1. */
1453 asm_noperands (const_rtx body
)
1455 rtx asm_op
= extract_asm_operands (CONST_CAST_RTX (body
));
1461 if (GET_CODE (body
) == SET
)
1463 else if (GET_CODE (body
) == PARALLEL
)
1466 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1468 /* Multiple output operands, or 1 output plus some clobbers:
1470 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1471 /* Count backwards through CLOBBERs to determine number of SETs. */
1472 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1474 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1476 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1480 /* N_SETS is now number of output operands. */
1483 /* Verify that all the SETs we have
1484 came from a single original asm_operands insn
1485 (so that invalid combinations are blocked). */
1486 for (i
= 0; i
< n_sets
; i
++)
1488 rtx elt
= XVECEXP (body
, 0, i
);
1489 if (GET_CODE (elt
) != SET
)
1491 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1493 /* If these ASM_OPERANDS rtx's came from different original insns
1494 then they aren't allowed together. */
1495 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1496 != ASM_OPERANDS_INPUT_VEC (asm_op
))
1502 /* 0 outputs, but some clobbers:
1503 body is [(asm_operands ...) (clobber (reg ...))...]. */
1504 /* Make sure all the other parallel things really are clobbers. */
1505 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1506 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1511 return (ASM_OPERANDS_INPUT_LENGTH (asm_op
)
1512 + ASM_OPERANDS_LABEL_LENGTH (asm_op
) + n_sets
);
1515 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1516 copy its operands (both input and output) into the vector OPERANDS,
1517 the locations of the operands within the insn into the vector OPERAND_LOCS,
1518 and the constraints for the operands into CONSTRAINTS.
1519 Write the modes of the operands into MODES.
1520 Return the assembler-template.
1522 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1523 we don't store that info. */
1526 decode_asm_operands (rtx body
, rtx
*operands
, rtx
**operand_locs
,
1527 const char **constraints
, enum machine_mode
*modes
,
1530 int nbase
= 0, n
, i
;
1533 switch (GET_CODE (body
))
1536 /* Zero output asm: BODY is (asm_operands ...). */
1541 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1542 asmop
= SET_SRC (body
);
1544 /* The output is in the SET.
1545 Its constraint is in the ASM_OPERANDS itself. */
1547 operands
[0] = SET_DEST (body
);
1549 operand_locs
[0] = &SET_DEST (body
);
1551 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1553 modes
[0] = GET_MODE (SET_DEST (body
));
1559 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1561 asmop
= XVECEXP (body
, 0, 0);
1562 if (GET_CODE (asmop
) == SET
)
1564 asmop
= SET_SRC (asmop
);
1566 /* At least one output, plus some CLOBBERs. The outputs are in
1567 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1568 for (i
= 0; i
< nparallel
; i
++)
1570 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1571 break; /* Past last SET */
1573 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1575 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1577 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1579 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1590 n
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1591 for (i
= 0; i
< n
; i
++)
1594 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1596 operands
[nbase
+ i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1598 constraints
[nbase
+ i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1600 modes
[nbase
+ i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1604 n
= ASM_OPERANDS_LABEL_LENGTH (asmop
);
1605 for (i
= 0; i
< n
; i
++)
1608 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_LABEL (asmop
, i
);
1610 operands
[nbase
+ i
] = ASM_OPERANDS_LABEL (asmop
, i
);
1612 constraints
[nbase
+ i
] = "";
1614 modes
[nbase
+ i
] = Pmode
;
1618 *loc
= ASM_OPERANDS_SOURCE_LOCATION (asmop
);
1620 return ASM_OPERANDS_TEMPLATE (asmop
);
1623 /* Check if an asm_operand matches its constraints.
1624 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1627 asm_operand_ok (rtx op
, const char *constraint
, const char **constraints
)
1631 bool incdec_ok
= false;
1634 /* Use constrain_operands after reload. */
1635 gcc_assert (!reload_completed
);
1637 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1638 many alternatives as required to match the other operands. */
1639 if (*constraint
== '\0')
1644 char c
= *constraint
;
1661 case '0': case '1': case '2': case '3': case '4':
1662 case '5': case '6': case '7': case '8': case '9':
1663 /* If caller provided constraints pointer, look up
1664 the matching constraint. Otherwise, our caller should have
1665 given us the proper matching constraint, but we can't
1666 actually fail the check if they didn't. Indicate that
1667 results are inconclusive. */
1671 unsigned long match
;
1673 match
= strtoul (constraint
, &end
, 10);
1675 result
= asm_operand_ok (op
, constraints
[match
], NULL
);
1676 constraint
= (const char *) end
;
1682 while (ISDIGIT (*constraint
));
1689 if (address_operand (op
, VOIDmode
))
1693 case TARGET_MEM_CONSTRAINT
:
1694 case 'V': /* non-offsettable */
1695 if (memory_operand (op
, VOIDmode
))
1699 case 'o': /* offsettable */
1700 if (offsettable_nonstrict_memref_p (op
))
1705 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed to exist,
1706 excepting those that expand_call created. Further, on some
1707 machines which do not have generalized auto inc/dec, an inc/dec
1708 is not a memory_operand.
1710 Match any memory and hope things are resolved after reload. */
1714 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
1715 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1725 || GET_CODE (XEXP (op
, 0)) == PRE_INC
1726 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1735 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1736 || (GET_CODE (op
) == CONST_VECTOR
1737 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
1742 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1743 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'G', constraint
))
1747 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1748 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'H', constraint
))
1753 if (CONST_SCALAR_INT_P (op
))
1758 if (CONSTANT_P (op
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
1763 if (CONST_SCALAR_INT_P (op
))
1768 if (CONST_INT_P (op
)
1769 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'I', constraint
))
1773 if (CONST_INT_P (op
)
1774 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'J', constraint
))
1778 if (CONST_INT_P (op
)
1779 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'K', constraint
))
1783 if (CONST_INT_P (op
)
1784 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'L', constraint
))
1788 if (CONST_INT_P (op
)
1789 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'M', constraint
))
1793 if (CONST_INT_P (op
)
1794 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'N', constraint
))
1798 if (CONST_INT_P (op
)
1799 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'O', constraint
))
1803 if (CONST_INT_P (op
)
1804 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'P', constraint
))
1813 if (general_operand (op
, VOIDmode
))
1818 /* For all other letters, we first check for a register class,
1819 otherwise it is an EXTRA_CONSTRAINT. */
1820 if (REG_CLASS_FROM_CONSTRAINT (c
, constraint
) != NO_REGS
)
1823 if (GET_MODE (op
) == BLKmode
)
1825 if (register_operand (op
, VOIDmode
))
1828 #ifdef EXTRA_CONSTRAINT_STR
1829 else if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
))
1830 /* Every memory operand can be reloaded to fit. */
1831 result
= result
|| memory_operand (op
, VOIDmode
);
1832 else if (EXTRA_ADDRESS_CONSTRAINT (c
, constraint
))
1833 /* Every address operand can be reloaded to fit. */
1834 result
= result
|| address_operand (op
, VOIDmode
);
1835 else if (EXTRA_CONSTRAINT_STR (op
, c
, constraint
))
1840 len
= CONSTRAINT_LEN (c
, constraint
);
1843 while (--len
&& *constraint
);
1849 /* For operands without < or > constraints reject side-effects. */
1850 if (!incdec_ok
&& result
&& MEM_P (op
))
1851 switch (GET_CODE (XEXP (op
, 0)))
1868 /* Given an rtx *P, if it is a sum containing an integer constant term,
1869 return the location (type rtx *) of the pointer to that constant term.
1870 Otherwise, return a null pointer. */
1873 find_constant_term_loc (rtx
*p
)
1876 enum rtx_code code
= GET_CODE (*p
);
1878 /* If *P IS such a constant term, P is its location. */
1880 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1884 /* Otherwise, if not a sum, it has no constant term. */
1886 if (GET_CODE (*p
) != PLUS
)
1889 /* If one of the summands is constant, return its location. */
1891 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1892 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1895 /* Otherwise, check each summand for containing a constant term. */
1897 if (XEXP (*p
, 0) != 0)
1899 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1904 if (XEXP (*p
, 1) != 0)
1906 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1914 /* Return 1 if OP is a memory reference
1915 whose address contains no side effects
1916 and remains valid after the addition
1917 of a positive integer less than the
1918 size of the object being referenced.
1920 We assume that the original address is valid and do not check it.
1922 This uses strict_memory_address_p as a subroutine, so
1923 don't use it before reload. */
1926 offsettable_memref_p (rtx op
)
1928 return ((MEM_P (op
))
1929 && offsettable_address_addr_space_p (1, GET_MODE (op
), XEXP (op
, 0),
1930 MEM_ADDR_SPACE (op
)));
1933 /* Similar, but don't require a strictly valid mem ref:
1934 consider pseudo-regs valid as index or base regs. */
1937 offsettable_nonstrict_memref_p (rtx op
)
1939 return ((MEM_P (op
))
1940 && offsettable_address_addr_space_p (0, GET_MODE (op
), XEXP (op
, 0),
1941 MEM_ADDR_SPACE (op
)));
1944 /* Return 1 if Y is a memory address which contains no side effects
1945 and would remain valid for address space AS after the addition of
1946 a positive integer less than the size of that mode.
1948 We assume that the original address is valid and do not check it.
1949 We do check that it is valid for narrower modes.
1951 If STRICTP is nonzero, we require a strictly valid address,
1952 for the sake of use in reload.c. */
1955 offsettable_address_addr_space_p (int strictp
, enum machine_mode mode
, rtx y
,
1958 enum rtx_code ycode
= GET_CODE (y
);
1962 int (*addressp
) (enum machine_mode
, rtx
, addr_space_t
) =
1963 (strictp
? strict_memory_address_addr_space_p
1964 : memory_address_addr_space_p
);
1965 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1967 if (CONSTANT_ADDRESS_P (y
))
1970 /* Adjusting an offsettable address involves changing to a narrower mode.
1971 Make sure that's OK. */
1973 if (mode_dependent_address_p (y
, as
))
1976 enum machine_mode address_mode
= GET_MODE (y
);
1977 if (address_mode
== VOIDmode
)
1978 address_mode
= targetm
.addr_space
.address_mode (as
);
1979 #ifdef POINTERS_EXTEND_UNSIGNED
1980 enum machine_mode pointer_mode
= targetm
.addr_space
.pointer_mode (as
);
1983 /* ??? How much offset does an offsettable BLKmode reference need?
1984 Clearly that depends on the situation in which it's being used.
1985 However, the current situation in which we test 0xffffffff is
1986 less than ideal. Caveat user. */
1988 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
1990 /* If the expression contains a constant term,
1991 see if it remains valid when max possible offset is added. */
1993 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
1998 *y2
= plus_constant (address_mode
, *y2
, mode_sz
- 1);
1999 /* Use QImode because an odd displacement may be automatically invalid
2000 for any wider mode. But it should be valid for a single byte. */
2001 good
= (*addressp
) (QImode
, y
, as
);
2003 /* In any case, restore old contents of memory. */
2008 if (GET_RTX_CLASS (ycode
) == RTX_AUTOINC
)
2011 /* The offset added here is chosen as the maximum offset that
2012 any instruction could need to add when operating on something
2013 of the specified mode. We assume that if Y and Y+c are
2014 valid addresses then so is Y+d for all 0<d<c. adjust_address will
2015 go inside a LO_SUM here, so we do so as well. */
2016 if (GET_CODE (y
) == LO_SUM
2018 && mode_sz
<= GET_MODE_ALIGNMENT (mode
) / BITS_PER_UNIT
)
2019 z
= gen_rtx_LO_SUM (address_mode
, XEXP (y
, 0),
2020 plus_constant (address_mode
, XEXP (y
, 1),
2022 #ifdef POINTERS_EXTEND_UNSIGNED
2023 /* Likewise for a ZERO_EXTEND from pointer_mode. */
2024 else if (POINTERS_EXTEND_UNSIGNED
> 0
2025 && GET_CODE (y
) == ZERO_EXTEND
2026 && GET_MODE (XEXP (y
, 0)) == pointer_mode
)
2027 z
= gen_rtx_ZERO_EXTEND (address_mode
,
2028 plus_constant (pointer_mode
, XEXP (y
, 0),
2032 z
= plus_constant (address_mode
, y
, mode_sz
- 1);
2034 /* Use QImode because an odd displacement may be automatically invalid
2035 for any wider mode. But it should be valid for a single byte. */
2036 return (*addressp
) (QImode
, z
, as
);
2039 /* Return 1 if ADDR is an address-expression whose effect depends
2040 on the mode of the memory reference it is used in.
2042 ADDRSPACE is the address space associated with the address.
2044 Autoincrement addressing is a typical example of mode-dependence
2045 because the amount of the increment depends on the mode. */
2048 mode_dependent_address_p (rtx addr
, addr_space_t addrspace
)
2050 /* Auto-increment addressing with anything other than post_modify
2051 or pre_modify always introduces a mode dependency. Catch such
2052 cases now instead of deferring to the target. */
2053 if (GET_CODE (addr
) == PRE_INC
2054 || GET_CODE (addr
) == POST_INC
2055 || GET_CODE (addr
) == PRE_DEC
2056 || GET_CODE (addr
) == POST_DEC
)
2059 return targetm
.mode_dependent_address_p (addr
, addrspace
);
2062 /* Like extract_insn, but save insn extracted and don't extract again, when
2063 called again for the same insn expecting that recog_data still contain the
2064 valid information. This is used primary by gen_attr infrastructure that
2065 often does extract insn again and again. */
2067 extract_insn_cached (rtx insn
)
2069 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2071 extract_insn (insn
);
2072 recog_data
.insn
= insn
;
2075 /* Do cached extract_insn, constrain_operands and complain about failures.
2076 Used by insn_attrtab. */
2078 extract_constrain_insn_cached (rtx insn
)
2080 extract_insn_cached (insn
);
2081 if (which_alternative
== -1
2082 && !constrain_operands (reload_completed
))
2083 fatal_insn_not_found (insn
);
2086 /* Do cached constrain_operands and complain about failures. */
2088 constrain_operands_cached (int strict
)
2090 if (which_alternative
== -1)
2091 return constrain_operands (strict
);
2096 /* Analyze INSN and fill in recog_data. */
2099 extract_insn (rtx insn
)
2104 rtx body
= PATTERN (insn
);
2106 recog_data
.n_operands
= 0;
2107 recog_data
.n_alternatives
= 0;
2108 recog_data
.n_dups
= 0;
2109 recog_data
.is_asm
= false;
2111 switch (GET_CODE (body
))
2122 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2127 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2128 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2129 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2135 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2138 /* This insn is an `asm' with operands. */
2140 /* expand_asm_operands makes sure there aren't too many operands. */
2141 gcc_assert (noperands
<= MAX_RECOG_OPERANDS
);
2143 /* Now get the operand values and constraints out of the insn. */
2144 decode_asm_operands (body
, recog_data
.operand
,
2145 recog_data
.operand_loc
,
2146 recog_data
.constraints
,
2147 recog_data
.operand_mode
, NULL
);
2148 memset (recog_data
.is_operator
, 0, sizeof recog_data
.is_operator
);
2151 const char *p
= recog_data
.constraints
[0];
2152 recog_data
.n_alternatives
= 1;
2154 recog_data
.n_alternatives
+= (*p
++ == ',');
2156 recog_data
.is_asm
= true;
2159 fatal_insn_not_found (insn
);
2163 /* Ordinary insn: recognize it, get the operands via insn_extract
2164 and get the constraints. */
2166 icode
= recog_memoized (insn
);
2168 fatal_insn_not_found (insn
);
2170 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2171 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2172 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2174 insn_extract (insn
);
2176 for (i
= 0; i
< noperands
; i
++)
2178 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2179 recog_data
.is_operator
[i
] = insn_data
[icode
].operand
[i
].is_operator
;
2180 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2181 /* VOIDmode match_operands gets mode from their real operand. */
2182 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2183 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2186 for (i
= 0; i
< noperands
; i
++)
2187 recog_data
.operand_type
[i
]
2188 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2189 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2192 gcc_assert (recog_data
.n_alternatives
<= MAX_RECOG_ALTERNATIVES
);
2194 if (INSN_CODE (insn
) < 0)
2195 for (i
= 0; i
< recog_data
.n_alternatives
; i
++)
2196 recog_data
.alternative_enabled_p
[i
] = true;
2199 recog_data
.insn
= insn
;
2200 for (i
= 0; i
< recog_data
.n_alternatives
; i
++)
2202 which_alternative
= i
;
2203 recog_data
.alternative_enabled_p
[i
]
2204 = HAVE_ATTR_enabled
? get_attr_enabled (insn
) : 1;
2208 recog_data
.insn
= NULL
;
2209 which_alternative
= -1;
2212 /* After calling extract_insn, you can use this function to extract some
2213 information from the constraint strings into a more usable form.
2214 The collected data is stored in recog_op_alt. */
2216 preprocess_constraints (void)
2220 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2221 memset (recog_op_alt
[i
], 0, (recog_data
.n_alternatives
2222 * sizeof (struct operand_alternative
)));
2224 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2227 struct operand_alternative
*op_alt
;
2228 const char *p
= recog_data
.constraints
[i
];
2230 op_alt
= recog_op_alt
[i
];
2232 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
2234 op_alt
[j
].cl
= NO_REGS
;
2235 op_alt
[j
].constraint
= p
;
2236 op_alt
[j
].matches
= -1;
2237 op_alt
[j
].matched
= -1;
2239 if (!recog_data
.alternative_enabled_p
[j
])
2241 p
= skip_alternative (p
);
2245 if (*p
== '\0' || *p
== ',')
2247 op_alt
[j
].anything_ok
= 1;
2257 while (c
!= ',' && c
!= '\0');
2258 if (c
== ',' || c
== '\0')
2266 case '=': case '+': case '*': case '%':
2267 case 'E': case 'F': case 'G': case 'H':
2268 case 's': case 'i': case 'n':
2269 case 'I': case 'J': case 'K': case 'L':
2270 case 'M': case 'N': case 'O': case 'P':
2271 /* These don't say anything we care about. */
2275 op_alt
[j
].reject
+= 6;
2278 op_alt
[j
].reject
+= 600;
2281 op_alt
[j
].earlyclobber
= 1;
2284 case '0': case '1': case '2': case '3': case '4':
2285 case '5': case '6': case '7': case '8': case '9':
2288 op_alt
[j
].matches
= strtoul (p
, &end
, 10);
2289 recog_op_alt
[op_alt
[j
].matches
][j
].matched
= i
;
2294 case TARGET_MEM_CONSTRAINT
:
2295 op_alt
[j
].memory_ok
= 1;
2298 op_alt
[j
].decmem_ok
= 1;
2301 op_alt
[j
].incmem_ok
= 1;
2304 op_alt
[j
].nonoffmem_ok
= 1;
2307 op_alt
[j
].offmem_ok
= 1;
2310 op_alt
[j
].anything_ok
= 1;
2314 op_alt
[j
].is_address
= 1;
2315 op_alt
[j
].cl
= reg_class_subunion
[(int) op_alt
[j
].cl
]
2316 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2323 reg_class_subunion
[(int) op_alt
[j
].cl
][(int) GENERAL_REGS
];
2327 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
2329 op_alt
[j
].memory_ok
= 1;
2332 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
2334 op_alt
[j
].is_address
= 1;
2336 = (reg_class_subunion
2337 [(int) op_alt
[j
].cl
]
2338 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2339 ADDRESS
, SCRATCH
)]);
2344 = (reg_class_subunion
2345 [(int) op_alt
[j
].cl
]
2346 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
2349 p
+= CONSTRAINT_LEN (c
, p
);
2355 /* Check the operands of an insn against the insn's operand constraints
2356 and return 1 if they are valid.
2357 The information about the insn's operands, constraints, operand modes
2358 etc. is obtained from the global variables set up by extract_insn.
2360 WHICH_ALTERNATIVE is set to a number which indicates which
2361 alternative of constraints was matched: 0 for the first alternative,
2362 1 for the next, etc.
2364 In addition, when two operands are required to match
2365 and it happens that the output operand is (reg) while the
2366 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2367 make the output operand look like the input.
2368 This is because the output operand is the one the template will print.
2370 This is used in final, just before printing the assembler code and by
2371 the routines that determine an insn's attribute.
2373 If STRICT is a positive nonzero value, it means that we have been
2374 called after reload has been completed. In that case, we must
2375 do all checks strictly. If it is zero, it means that we have been called
2376 before reload has completed. In that case, we first try to see if we can
2377 find an alternative that matches strictly. If not, we try again, this
2378 time assuming that reload will fix up the insn. This provides a "best
2379 guess" for the alternative and is used to compute attributes of insns prior
2380 to reload. A negative value of STRICT is used for this internal call. */
2388 constrain_operands (int strict
)
2390 const char *constraints
[MAX_RECOG_OPERANDS
];
2391 int matching_operands
[MAX_RECOG_OPERANDS
];
2392 int earlyclobber
[MAX_RECOG_OPERANDS
];
2395 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2396 int funny_match_index
;
2398 which_alternative
= 0;
2399 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2402 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2404 constraints
[c
] = recog_data
.constraints
[c
];
2405 matching_operands
[c
] = -1;
2410 int seen_earlyclobber_at
= -1;
2413 funny_match_index
= 0;
2415 if (!recog_data
.alternative_enabled_p
[which_alternative
])
2419 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2420 constraints
[i
] = skip_alternative (constraints
[i
]);
2422 which_alternative
++;
2426 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2428 rtx op
= recog_data
.operand
[opno
];
2429 enum machine_mode mode
= GET_MODE (op
);
2430 const char *p
= constraints
[opno
];
2436 earlyclobber
[opno
] = 0;
2438 /* A unary operator may be accepted by the predicate, but it
2439 is irrelevant for matching constraints. */
2443 if (GET_CODE (op
) == SUBREG
)
2445 if (REG_P (SUBREG_REG (op
))
2446 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2447 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2448 GET_MODE (SUBREG_REG (op
)),
2451 op
= SUBREG_REG (op
);
2454 /* An empty constraint or empty alternative
2455 allows anything which matched the pattern. */
2456 if (*p
== 0 || *p
== ',')
2460 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
2469 case '?': case '!': case '*': case '%':
2474 /* Ignore rest of this alternative as far as
2475 constraint checking is concerned. */
2478 while (*p
&& *p
!= ',');
2483 earlyclobber
[opno
] = 1;
2484 if (seen_earlyclobber_at
< 0)
2485 seen_earlyclobber_at
= opno
;
2488 case '0': case '1': case '2': case '3': case '4':
2489 case '5': case '6': case '7': case '8': case '9':
2491 /* This operand must be the same as a previous one.
2492 This kind of constraint is used for instructions such
2493 as add when they take only two operands.
2495 Note that the lower-numbered operand is passed first.
2497 If we are not testing strictly, assume that this
2498 constraint will be satisfied. */
2503 match
= strtoul (p
, &end
, 10);
2510 rtx op1
= recog_data
.operand
[match
];
2511 rtx op2
= recog_data
.operand
[opno
];
2513 /* A unary operator may be accepted by the predicate,
2514 but it is irrelevant for matching constraints. */
2516 op1
= XEXP (op1
, 0);
2518 op2
= XEXP (op2
, 0);
2520 val
= operands_match_p (op1
, op2
);
2523 matching_operands
[opno
] = match
;
2524 matching_operands
[match
] = opno
;
2529 /* If output is *x and input is *--x, arrange later
2530 to change the output to *--x as well, since the
2531 output op is the one that will be printed. */
2532 if (val
== 2 && strict
> 0)
2534 funny_match
[funny_match_index
].this_op
= opno
;
2535 funny_match
[funny_match_index
++].other
= match
;
2542 /* p is used for address_operands. When we are called by
2543 gen_reload, no one will have checked that the address is
2544 strictly valid, i.e., that all pseudos requiring hard regs
2545 have gotten them. */
2547 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2552 /* No need to check general_operand again;
2553 it was done in insn-recog.c. Well, except that reload
2554 doesn't check the validity of its replacements, but
2555 that should only matter when there's a bug. */
2557 /* Anything goes unless it is a REG and really has a hard reg
2558 but the hard reg is not in the class GENERAL_REGS. */
2562 || GENERAL_REGS
== ALL_REGS
2563 || (reload_in_progress
2564 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2565 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2568 else if (strict
< 0 || general_operand (op
, mode
))
2573 /* This is used for a MATCH_SCRATCH in the cases when
2574 we don't actually need anything. So anything goes
2579 case TARGET_MEM_CONSTRAINT
:
2580 /* Memory operands must be valid, to the extent
2581 required by STRICT. */
2585 && !strict_memory_address_addr_space_p
2586 (GET_MODE (op
), XEXP (op
, 0),
2587 MEM_ADDR_SPACE (op
)))
2590 && !memory_address_addr_space_p
2591 (GET_MODE (op
), XEXP (op
, 0),
2592 MEM_ADDR_SPACE (op
)))
2596 /* Before reload, accept what reload can turn into mem. */
2597 else if (strict
< 0 && CONSTANT_P (op
))
2599 /* During reload, accept a pseudo */
2600 else if (reload_in_progress
&& REG_P (op
)
2601 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2607 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
2608 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
2614 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
2615 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
2621 if (CONST_DOUBLE_AS_FLOAT_P (op
)
2622 || (GET_CODE (op
) == CONST_VECTOR
2623 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
2629 if (CONST_DOUBLE_AS_FLOAT_P (op
)
2630 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
2635 if (CONST_SCALAR_INT_P (op
))
2638 if (CONSTANT_P (op
))
2643 if (CONST_SCALAR_INT_P (op
))
2655 if (CONST_INT_P (op
)
2656 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
2662 && ((strict
> 0 && ! offsettable_memref_p (op
))
2664 && !(CONSTANT_P (op
) || MEM_P (op
)))
2665 || (reload_in_progress
2667 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))))
2672 if ((strict
> 0 && offsettable_memref_p (op
))
2673 || (strict
== 0 && offsettable_nonstrict_memref_p (op
))
2674 /* Before reload, accept what reload can handle. */
2676 && (CONSTANT_P (op
) || MEM_P (op
)))
2677 /* During reload, accept a pseudo */
2678 || (reload_in_progress
&& REG_P (op
)
2679 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2688 ? GENERAL_REGS
: REG_CLASS_FROM_CONSTRAINT (c
, p
));
2694 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2695 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2697 && reg_fits_class_p (op
, cl
, offset
, mode
)))
2700 #ifdef EXTRA_CONSTRAINT_STR
2701 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
2704 else if (EXTRA_MEMORY_CONSTRAINT (c
, p
)
2705 /* Every memory operand can be reloaded to fit. */
2706 && ((strict
< 0 && MEM_P (op
))
2707 /* Before reload, accept what reload can turn
2709 || (strict
< 0 && CONSTANT_P (op
))
2710 /* During reload, accept a pseudo */
2711 || (reload_in_progress
&& REG_P (op
)
2712 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)))
2714 else if (EXTRA_ADDRESS_CONSTRAINT (c
, p
)
2715 /* Every address operand can be reloaded to fit. */
2718 /* Cater to architectures like IA-64 that define extra memory
2719 constraints without using define_memory_constraint. */
2720 else if (reload_in_progress
2722 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
2723 && reg_renumber
[REGNO (op
)] < 0
2724 && reg_equiv_mem (REGNO (op
)) != 0
2725 && EXTRA_CONSTRAINT_STR
2726 (reg_equiv_mem (REGNO (op
)), c
, p
))
2732 while (p
+= len
, c
);
2734 constraints
[opno
] = p
;
2735 /* If this operand did not win somehow,
2736 this alternative loses. */
2740 /* This alternative won; the operands are ok.
2741 Change whichever operands this alternative says to change. */
2746 /* See if any earlyclobber operand conflicts with some other
2749 if (strict
> 0 && seen_earlyclobber_at
>= 0)
2750 for (eopno
= seen_earlyclobber_at
;
2751 eopno
< recog_data
.n_operands
;
2753 /* Ignore earlyclobber operands now in memory,
2754 because we would often report failure when we have
2755 two memory operands, one of which was formerly a REG. */
2756 if (earlyclobber
[eopno
]
2757 && REG_P (recog_data
.operand
[eopno
]))
2758 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2759 if ((MEM_P (recog_data
.operand
[opno
])
2760 || recog_data
.operand_type
[opno
] != OP_OUT
)
2762 /* Ignore things like match_operator operands. */
2763 && *recog_data
.constraints
[opno
] != 0
2764 && ! (matching_operands
[opno
] == eopno
2765 && operands_match_p (recog_data
.operand
[opno
],
2766 recog_data
.operand
[eopno
]))
2767 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2768 recog_data
.operand
[eopno
]))
2773 while (--funny_match_index
>= 0)
2775 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2776 = recog_data
.operand
[funny_match
[funny_match_index
].this_op
];
2780 /* For operands without < or > constraints reject side-effects. */
2781 if (recog_data
.is_asm
)
2783 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2784 if (MEM_P (recog_data
.operand
[opno
]))
2785 switch (GET_CODE (XEXP (recog_data
.operand
[opno
], 0)))
2793 if (strchr (recog_data
.constraints
[opno
], '<') == NULL
2794 && strchr (recog_data
.constraints
[opno
], '>')
2807 which_alternative
++;
2809 while (which_alternative
< recog_data
.n_alternatives
);
2811 which_alternative
= -1;
2812 /* If we are about to reject this, but we are not to test strictly,
2813 try a very loose test. Only return failure if it fails also. */
2815 return constrain_operands (-1);
2820 /* Return true iff OPERAND (assumed to be a REG rtx)
2821 is a hard reg in class CLASS when its regno is offset by OFFSET
2822 and changed to mode MODE.
2823 If REG occupies multiple hard regs, all of them must be in CLASS. */
2826 reg_fits_class_p (const_rtx operand
, reg_class_t cl
, int offset
,
2827 enum machine_mode mode
)
2829 unsigned int regno
= REGNO (operand
);
2834 /* Regno must not be a pseudo register. Offset may be negative. */
2835 return (HARD_REGISTER_NUM_P (regno
)
2836 && HARD_REGISTER_NUM_P (regno
+ offset
)
2837 && in_hard_reg_set_p (reg_class_contents
[(int) cl
], mode
,
2841 /* Split single instruction. Helper function for split_all_insns and
2842 split_all_insns_noflow. Return last insn in the sequence if successful,
2843 or NULL if unsuccessful. */
2846 split_insn (rtx insn
)
2848 /* Split insns here to get max fine-grain parallelism. */
2849 rtx first
= PREV_INSN (insn
);
2850 rtx last
= try_split (PATTERN (insn
), insn
, 1);
2851 rtx insn_set
, last_set
, note
;
2856 /* If the original instruction was a single set that was known to be
2857 equivalent to a constant, see if we can say the same about the last
2858 instruction in the split sequence. The two instructions must set
2859 the same destination. */
2860 insn_set
= single_set (insn
);
2863 last_set
= single_set (last
);
2864 if (last_set
&& rtx_equal_p (SET_DEST (last_set
), SET_DEST (insn_set
)))
2866 note
= find_reg_equal_equiv_note (insn
);
2867 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2868 set_unique_reg_note (last
, REG_EQUAL
, XEXP (note
, 0));
2869 else if (CONSTANT_P (SET_SRC (insn_set
)))
2870 set_unique_reg_note (last
, REG_EQUAL
,
2871 copy_rtx (SET_SRC (insn_set
)));
2875 /* try_split returns the NOTE that INSN became. */
2876 SET_INSN_DELETED (insn
);
2878 /* ??? Coddle to md files that generate subregs in post-reload
2879 splitters instead of computing the proper hard register. */
2880 if (reload_completed
&& first
!= last
)
2882 first
= NEXT_INSN (first
);
2886 cleanup_subreg_operands (first
);
2889 first
= NEXT_INSN (first
);
2896 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2899 split_all_insns (void)
2905 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
2906 bitmap_clear (blocks
);
2909 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
2912 bool finish
= false;
2914 rtl_profile_for_bb (bb
);
2915 for (insn
= BB_HEAD (bb
); !finish
; insn
= next
)
2917 /* Can't use `next_real_insn' because that might go across
2918 CODE_LABELS and short-out basic blocks. */
2919 next
= NEXT_INSN (insn
);
2920 finish
= (insn
== BB_END (bb
));
2923 rtx set
= single_set (insn
);
2925 /* Don't split no-op move insns. These should silently
2926 disappear later in final. Splitting such insns would
2927 break the code that handles LIBCALL blocks. */
2928 if (set
&& set_noop_p (set
))
2930 /* Nops get in the way while scheduling, so delete them
2931 now if register allocation has already been done. It
2932 is too risky to try to do this before register
2933 allocation, and there are unlikely to be very many
2934 nops then anyways. */
2935 if (reload_completed
)
2936 delete_insn_and_edges (insn
);
2940 if (split_insn (insn
))
2942 bitmap_set_bit (blocks
, bb
->index
);
2950 default_rtl_profile ();
2952 find_many_sub_basic_blocks (blocks
);
2954 #ifdef ENABLE_CHECKING
2955 verify_flow_info ();
2958 sbitmap_free (blocks
);
2961 /* Same as split_all_insns, but do not expect CFG to be available.
2962 Used by machine dependent reorg passes. */
2965 split_all_insns_noflow (void)
2969 for (insn
= get_insns (); insn
; insn
= next
)
2971 next
= NEXT_INSN (insn
);
2974 /* Don't split no-op move insns. These should silently
2975 disappear later in final. Splitting such insns would
2976 break the code that handles LIBCALL blocks. */
2977 rtx set
= single_set (insn
);
2978 if (set
&& set_noop_p (set
))
2980 /* Nops get in the way while scheduling, so delete them
2981 now if register allocation has already been done. It
2982 is too risky to try to do this before register
2983 allocation, and there are unlikely to be very many
2986 ??? Should we use delete_insn when the CFG isn't valid? */
2987 if (reload_completed
)
2988 delete_insn_and_edges (insn
);
2997 #ifdef HAVE_peephole2
2998 struct peep2_insn_data
3004 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
3005 static int peep2_current
;
3007 static bool peep2_do_rebuild_jump_labels
;
3008 static bool peep2_do_cleanup_cfg
;
3010 /* The number of instructions available to match a peep2. */
3011 int peep2_current_count
;
3013 /* A non-insn marker indicating the last insn of the block.
3014 The live_before regset for this element is correct, indicating
3015 DF_LIVE_OUT for the block. */
3016 #define PEEP2_EOB pc_rtx
3018 /* Wrap N to fit into the peep2_insn_data buffer. */
3021 peep2_buf_position (int n
)
3023 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
3024 n
-= MAX_INSNS_PER_PEEP2
+ 1;
3028 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
3029 does not exist. Used by the recognizer to find the next insn to match
3030 in a multi-insn pattern. */
3033 peep2_next_insn (int n
)
3035 gcc_assert (n
<= peep2_current_count
);
3037 n
= peep2_buf_position (peep2_current
+ n
);
3039 return peep2_insn_data
[n
].insn
;
3042 /* Return true if REGNO is dead before the Nth non-note insn
3046 peep2_regno_dead_p (int ofs
, int regno
)
3048 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3050 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3052 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3054 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
3057 /* Similarly for a REG. */
3060 peep2_reg_dead_p (int ofs
, rtx reg
)
3064 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3066 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3068 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3070 regno
= REGNO (reg
);
3071 n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
3073 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
+ n
))
3078 /* Regno offset to be used in the register search. */
3079 static int search_ofs
;
3081 /* Try to find a hard register of mode MODE, matching the register class in
3082 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3083 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3084 in which case the only condition is that the register must be available
3085 before CURRENT_INSN.
3086 Registers that already have bits set in REG_SET will not be considered.
3088 If an appropriate register is available, it will be returned and the
3089 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3093 peep2_find_free_register (int from
, int to
, const char *class_str
,
3094 enum machine_mode mode
, HARD_REG_SET
*reg_set
)
3101 gcc_assert (from
< MAX_INSNS_PER_PEEP2
+ 1);
3102 gcc_assert (to
< MAX_INSNS_PER_PEEP2
+ 1);
3104 from
= peep2_buf_position (peep2_current
+ from
);
3105 to
= peep2_buf_position (peep2_current
+ to
);
3107 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3108 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
3112 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3114 /* Don't use registers set or clobbered by the insn. */
3115 for (def_rec
= DF_INSN_DEFS (peep2_insn_data
[from
].insn
);
3116 *def_rec
; def_rec
++)
3117 SET_HARD_REG_BIT (live
, DF_REF_REGNO (*def_rec
));
3119 from
= peep2_buf_position (from
+ 1);
3122 cl
= (class_str
[0] == 'r' ? GENERAL_REGS
3123 : REG_CLASS_FROM_CONSTRAINT (class_str
[0], class_str
));
3125 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3127 int raw_regno
, regno
, success
, j
;
3129 /* Distribute the free registers as much as possible. */
3130 raw_regno
= search_ofs
+ i
;
3131 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
3132 raw_regno
-= FIRST_PSEUDO_REGISTER
;
3133 #ifdef REG_ALLOC_ORDER
3134 regno
= reg_alloc_order
[raw_regno
];
3139 /* Can it support the mode we need? */
3140 if (! HARD_REGNO_MODE_OK (regno
, mode
))
3144 for (j
= 0; success
&& j
< hard_regno_nregs
[regno
][mode
]; j
++)
3146 /* Don't allocate fixed registers. */
3147 if (fixed_regs
[regno
+ j
])
3152 /* Don't allocate global registers. */
3153 if (global_regs
[regno
+ j
])
3158 /* Make sure the register is of the right class. */
3159 if (! TEST_HARD_REG_BIT (reg_class_contents
[cl
], regno
+ j
))
3164 /* And that we don't create an extra save/restore. */
3165 if (! call_used_regs
[regno
+ j
] && ! df_regs_ever_live_p (regno
+ j
))
3171 if (! targetm
.hard_regno_scratch_ok (regno
+ j
))
3177 /* And we don't clobber traceback for noreturn functions. */
3178 if ((regno
+ j
== FRAME_POINTER_REGNUM
3179 || regno
+ j
== HARD_FRAME_POINTER_REGNUM
)
3180 && (! reload_completed
|| frame_pointer_needed
))
3186 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3187 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3196 add_to_hard_reg_set (reg_set
, mode
, regno
);
3198 /* Start the next search with the next register. */
3199 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3201 search_ofs
= raw_regno
;
3203 return gen_rtx_REG (mode
, regno
);
3211 /* Forget all currently tracked instructions, only remember current
3215 peep2_reinit_state (regset live
)
3219 /* Indicate that all slots except the last holds invalid data. */
3220 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3221 peep2_insn_data
[i
].insn
= NULL_RTX
;
3222 peep2_current_count
= 0;
3224 /* Indicate that the last slot contains live_after data. */
3225 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3226 peep2_current
= MAX_INSNS_PER_PEEP2
;
3228 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3231 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3232 starting at INSN. Perform the replacement, removing the old insns and
3233 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3234 if the replacement is rejected. */
3237 peep2_attempt (basic_block bb
, rtx insn
, int match_len
, rtx attempt
)
3240 rtx last
, eh_note
, as_note
, before_try
, x
;
3241 rtx old_insn
, new_insn
;
3242 bool was_call
= false;
3244 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3245 match more than one insn, or to be split into more than one insn. */
3246 old_insn
= peep2_insn_data
[peep2_current
].insn
;
3247 if (RTX_FRAME_RELATED_P (old_insn
))
3249 bool any_note
= false;
3255 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3256 may be in the stream for the purpose of register allocation. */
3257 if (active_insn_p (attempt
))
3260 new_insn
= next_active_insn (attempt
);
3261 if (next_active_insn (new_insn
))
3264 /* We have a 1-1 replacement. Copy over any frame-related info. */
3265 RTX_FRAME_RELATED_P (new_insn
) = 1;
3267 /* Allow the backend to fill in a note during the split. */
3268 for (note
= REG_NOTES (new_insn
); note
; note
= XEXP (note
, 1))
3269 switch (REG_NOTE_KIND (note
))
3271 case REG_FRAME_RELATED_EXPR
:
3272 case REG_CFA_DEF_CFA
:
3273 case REG_CFA_ADJUST_CFA
:
3274 case REG_CFA_OFFSET
:
3275 case REG_CFA_REGISTER
:
3276 case REG_CFA_EXPRESSION
:
3277 case REG_CFA_RESTORE
:
3278 case REG_CFA_SET_VDRAP
:
3285 /* If the backend didn't supply a note, copy one over. */
3287 for (note
= REG_NOTES (old_insn
); note
; note
= XEXP (note
, 1))
3288 switch (REG_NOTE_KIND (note
))
3290 case REG_FRAME_RELATED_EXPR
:
3291 case REG_CFA_DEF_CFA
:
3292 case REG_CFA_ADJUST_CFA
:
3293 case REG_CFA_OFFSET
:
3294 case REG_CFA_REGISTER
:
3295 case REG_CFA_EXPRESSION
:
3296 case REG_CFA_RESTORE
:
3297 case REG_CFA_SET_VDRAP
:
3298 add_reg_note (new_insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3305 /* If there still isn't a note, make sure the unwind info sees the
3306 same expression as before the split. */
3309 rtx old_set
, new_set
;
3311 /* The old insn had better have been simple, or annotated. */
3312 old_set
= single_set (old_insn
);
3313 gcc_assert (old_set
!= NULL
);
3315 new_set
= single_set (new_insn
);
3316 if (!new_set
|| !rtx_equal_p (new_set
, old_set
))
3317 add_reg_note (new_insn
, REG_FRAME_RELATED_EXPR
, old_set
);
3320 /* Copy prologue/epilogue status. This is required in order to keep
3321 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3322 maybe_copy_prologue_epilogue_insn (old_insn
, new_insn
);
3325 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3326 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3327 cfg-related call notes. */
3328 for (i
= 0; i
<= match_len
; ++i
)
3333 j
= peep2_buf_position (peep2_current
+ i
);
3334 old_insn
= peep2_insn_data
[j
].insn
;
3335 if (!CALL_P (old_insn
))
3340 while (new_insn
!= NULL_RTX
)
3342 if (CALL_P (new_insn
))
3344 new_insn
= NEXT_INSN (new_insn
);
3347 gcc_assert (new_insn
!= NULL_RTX
);
3349 CALL_INSN_FUNCTION_USAGE (new_insn
)
3350 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3352 for (note
= REG_NOTES (old_insn
);
3354 note
= XEXP (note
, 1))
3355 switch (REG_NOTE_KIND (note
))
3360 add_reg_note (new_insn
, REG_NOTE_KIND (note
),
3364 /* Discard all other reg notes. */
3368 /* Croak if there is another call in the sequence. */
3369 while (++i
<= match_len
)
3371 j
= peep2_buf_position (peep2_current
+ i
);
3372 old_insn
= peep2_insn_data
[j
].insn
;
3373 gcc_assert (!CALL_P (old_insn
));
3378 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3379 move those notes over to the new sequence. */
3381 for (i
= match_len
; i
>= 0; --i
)
3383 int j
= peep2_buf_position (peep2_current
+ i
);
3384 old_insn
= peep2_insn_data
[j
].insn
;
3386 as_note
= find_reg_note (old_insn
, REG_ARGS_SIZE
, NULL
);
3391 i
= peep2_buf_position (peep2_current
+ match_len
);
3392 eh_note
= find_reg_note (peep2_insn_data
[i
].insn
, REG_EH_REGION
, NULL_RTX
);
3394 /* Replace the old sequence with the new. */
3395 last
= emit_insn_after_setloc (attempt
,
3396 peep2_insn_data
[i
].insn
,
3397 INSN_LOCATION (peep2_insn_data
[i
].insn
));
3398 before_try
= PREV_INSN (insn
);
3399 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
, false);
3401 /* Re-insert the EH_REGION notes. */
3402 if (eh_note
|| (was_call
&& nonlocal_goto_handler_labels
))
3407 FOR_EACH_EDGE (eh_edge
, ei
, bb
->succs
)
3408 if (eh_edge
->flags
& (EDGE_EH
| EDGE_ABNORMAL_CALL
))
3412 copy_reg_eh_region_note_backward (eh_note
, last
, before_try
);
3415 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3416 if (x
!= BB_END (bb
)
3417 && (can_throw_internal (x
)
3418 || can_nonlocal_goto (x
)))
3423 nfte
= split_block (bb
, x
);
3424 flags
= (eh_edge
->flags
3425 & (EDGE_EH
| EDGE_ABNORMAL
));
3427 flags
|= EDGE_ABNORMAL_CALL
;
3428 nehe
= make_edge (nfte
->src
, eh_edge
->dest
,
3431 nehe
->probability
= eh_edge
->probability
;
3433 = REG_BR_PROB_BASE
- nehe
->probability
;
3435 peep2_do_cleanup_cfg
|= purge_dead_edges (nfte
->dest
);
3440 /* Converting possibly trapping insn to non-trapping is
3441 possible. Zap dummy outgoing edges. */
3442 peep2_do_cleanup_cfg
|= purge_dead_edges (bb
);
3445 /* Re-insert the ARGS_SIZE notes. */
3447 fixup_args_size_notes (before_try
, last
, INTVAL (XEXP (as_note
, 0)));
3449 /* If we generated a jump instruction, it won't have
3450 JUMP_LABEL set. Recompute after we're done. */
3451 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3454 peep2_do_rebuild_jump_labels
= true;
3461 /* After performing a replacement in basic block BB, fix up the life
3462 information in our buffer. LAST is the last of the insns that we
3463 emitted as a replacement. PREV is the insn before the start of
3464 the replacement. MATCH_LEN is the number of instructions that were
3465 matched, and which now need to be replaced in the buffer. */
3468 peep2_update_life (basic_block bb
, int match_len
, rtx last
, rtx prev
)
3470 int i
= peep2_buf_position (peep2_current
+ match_len
+ 1);
3474 INIT_REG_SET (&live
);
3475 COPY_REG_SET (&live
, peep2_insn_data
[i
].live_before
);
3477 gcc_assert (peep2_current_count
>= match_len
+ 1);
3478 peep2_current_count
-= match_len
+ 1;
3486 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
)
3488 peep2_current_count
++;
3490 i
= MAX_INSNS_PER_PEEP2
;
3491 peep2_insn_data
[i
].insn
= x
;
3492 df_simulate_one_insn_backwards (bb
, x
, &live
);
3493 COPY_REG_SET (peep2_insn_data
[i
].live_before
, &live
);
3499 CLEAR_REG_SET (&live
);
3504 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3505 Return true if we added it, false otherwise. The caller will try to match
3506 peepholes against the buffer if we return false; otherwise it will try to
3507 add more instructions to the buffer. */
3510 peep2_fill_buffer (basic_block bb
, rtx insn
, regset live
)
3514 /* Once we have filled the maximum number of insns the buffer can hold,
3515 allow the caller to match the insns against peepholes. We wait until
3516 the buffer is full in case the target has similar peepholes of different
3517 length; we always want to match the longest if possible. */
3518 if (peep2_current_count
== MAX_INSNS_PER_PEEP2
)
3521 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3522 any other pattern, lest it change the semantics of the frame info. */
3523 if (RTX_FRAME_RELATED_P (insn
))
3525 /* Let the buffer drain first. */
3526 if (peep2_current_count
> 0)
3528 /* Now the insn will be the only thing in the buffer. */
3531 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3532 peep2_insn_data
[pos
].insn
= insn
;
3533 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3534 peep2_current_count
++;
3536 df_simulate_one_insn_forwards (bb
, insn
, live
);
3540 /* Perform the peephole2 optimization pass. */
3543 peephole2_optimize (void)
3550 peep2_do_cleanup_cfg
= false;
3551 peep2_do_rebuild_jump_labels
= false;
3553 df_set_flags (DF_LR_RUN_DCE
);
3554 df_note_add_problem ();
3557 /* Initialize the regsets we're going to use. */
3558 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3559 peep2_insn_data
[i
].live_before
= BITMAP_ALLOC (®_obstack
);
3561 live
= BITMAP_ALLOC (®_obstack
);
3563 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3565 bool past_end
= false;
3568 rtl_profile_for_bb (bb
);
3570 /* Start up propagation. */
3571 bitmap_copy (live
, DF_LR_IN (bb
));
3572 df_simulate_initialize_forwards (bb
, live
);
3573 peep2_reinit_state (live
);
3575 insn
= BB_HEAD (bb
);
3581 if (!past_end
&& !NONDEBUG_INSN_P (insn
))
3584 insn
= NEXT_INSN (insn
);
3585 if (insn
== NEXT_INSN (BB_END (bb
)))
3589 if (!past_end
&& peep2_fill_buffer (bb
, insn
, live
))
3592 /* If we did not fill an empty buffer, it signals the end of the
3594 if (peep2_current_count
== 0)
3597 /* The buffer filled to the current maximum, so try to match. */
3599 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3600 peep2_insn_data
[pos
].insn
= PEEP2_EOB
;
3601 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3603 /* Match the peephole. */
3604 head
= peep2_insn_data
[peep2_current
].insn
;
3605 attempt
= peephole2_insns (PATTERN (head
), head
, &match_len
);
3606 if (attempt
!= NULL
)
3608 rtx last
= peep2_attempt (bb
, head
, match_len
, attempt
);
3611 peep2_update_life (bb
, match_len
, last
, PREV_INSN (attempt
));
3616 /* No match: advance the buffer by one insn. */
3617 peep2_current
= peep2_buf_position (peep2_current
+ 1);
3618 peep2_current_count
--;
3622 default_rtl_profile ();
3623 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3624 BITMAP_FREE (peep2_insn_data
[i
].live_before
);
3626 if (peep2_do_rebuild_jump_labels
)
3627 rebuild_jump_labels (get_insns ());
3629 #endif /* HAVE_peephole2 */
3631 /* Common predicates for use with define_bypass. */
3633 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3634 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3635 must be either a single_set or a PARALLEL with SETs inside. */
3638 store_data_bypass_p (rtx out_insn
, rtx in_insn
)
3640 rtx out_set
, in_set
;
3641 rtx out_pat
, in_pat
;
3642 rtx out_exp
, in_exp
;
3645 in_set
= single_set (in_insn
);
3648 if (!MEM_P (SET_DEST (in_set
)))
3651 out_set
= single_set (out_insn
);
3654 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_set
)))
3659 out_pat
= PATTERN (out_insn
);
3661 if (GET_CODE (out_pat
) != PARALLEL
)
3664 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3666 out_exp
= XVECEXP (out_pat
, 0, i
);
3668 if (GET_CODE (out_exp
) == CLOBBER
)
3671 gcc_assert (GET_CODE (out_exp
) == SET
);
3673 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_set
)))
3680 in_pat
= PATTERN (in_insn
);
3681 gcc_assert (GET_CODE (in_pat
) == PARALLEL
);
3683 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
3685 in_exp
= XVECEXP (in_pat
, 0, i
);
3687 if (GET_CODE (in_exp
) == CLOBBER
)
3690 gcc_assert (GET_CODE (in_exp
) == SET
);
3692 if (!MEM_P (SET_DEST (in_exp
)))
3695 out_set
= single_set (out_insn
);
3698 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_exp
)))
3703 out_pat
= PATTERN (out_insn
);
3704 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3706 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
3708 out_exp
= XVECEXP (out_pat
, 0, j
);
3710 if (GET_CODE (out_exp
) == CLOBBER
)
3713 gcc_assert (GET_CODE (out_exp
) == SET
);
3715 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_exp
)))
3725 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3726 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3727 or multiple set; IN_INSN should be single_set for truth, but for convenience
3728 of insn categorization may be any JUMP or CALL insn. */
3731 if_test_bypass_p (rtx out_insn
, rtx in_insn
)
3733 rtx out_set
, in_set
;
3735 in_set
= single_set (in_insn
);
3738 gcc_assert (JUMP_P (in_insn
) || CALL_P (in_insn
));
3742 if (GET_CODE (SET_SRC (in_set
)) != IF_THEN_ELSE
)
3744 in_set
= SET_SRC (in_set
);
3746 out_set
= single_set (out_insn
);
3749 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3750 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3758 out_pat
= PATTERN (out_insn
);
3759 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3761 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3763 rtx exp
= XVECEXP (out_pat
, 0, i
);
3765 if (GET_CODE (exp
) == CLOBBER
)
3768 gcc_assert (GET_CODE (exp
) == SET
);
3770 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3771 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3780 gate_handle_peephole2 (void)
3782 return (optimize
> 0 && flag_peephole2
);
3786 rest_of_handle_peephole2 (void)
3788 #ifdef HAVE_peephole2
3789 peephole2_optimize ();
3796 const pass_data pass_data_peephole2
=
3798 RTL_PASS
, /* type */
3799 "peephole2", /* name */
3800 OPTGROUP_NONE
, /* optinfo_flags */
3801 true, /* has_gate */
3802 true, /* has_execute */
3803 TV_PEEPHOLE2
, /* tv_id */
3804 0, /* properties_required */
3805 0, /* properties_provided */
3806 0, /* properties_destroyed */
3807 0, /* todo_flags_start */
3808 ( TODO_df_finish
| TODO_verify_rtl_sharing
| 0 ), /* todo_flags_finish */
3811 class pass_peephole2
: public rtl_opt_pass
3814 pass_peephole2 (gcc::context
*ctxt
)
3815 : rtl_opt_pass (pass_data_peephole2
, ctxt
)
3818 /* opt_pass methods: */
3819 /* The epiphany backend creates a second instance of this pass, so we need
3821 opt_pass
* clone () { return new pass_peephole2 (m_ctxt
); }
3822 bool gate () { return gate_handle_peephole2 (); }
3823 unsigned int execute () { return rest_of_handle_peephole2 (); }
3825 }; // class pass_peephole2
3830 make_pass_peephole2 (gcc::context
*ctxt
)
3832 return new pass_peephole2 (ctxt
);
3836 rest_of_handle_split_all_insns (void)
3844 const pass_data pass_data_split_all_insns
=
3846 RTL_PASS
, /* type */
3847 "split1", /* name */
3848 OPTGROUP_NONE
, /* optinfo_flags */
3849 false, /* has_gate */
3850 true, /* has_execute */
3851 TV_NONE
, /* tv_id */
3852 0, /* properties_required */
3853 0, /* properties_provided */
3854 0, /* properties_destroyed */
3855 0, /* todo_flags_start */
3856 0, /* todo_flags_finish */
3859 class pass_split_all_insns
: public rtl_opt_pass
3862 pass_split_all_insns (gcc::context
*ctxt
)
3863 : rtl_opt_pass (pass_data_split_all_insns
, ctxt
)
3866 /* opt_pass methods: */
3867 /* The epiphany backend creates a second instance of this pass, so
3868 we need a clone method. */
3869 opt_pass
* clone () { return new pass_split_all_insns (m_ctxt
); }
3870 unsigned int execute () { return rest_of_handle_split_all_insns (); }
3872 }; // class pass_split_all_insns
3877 make_pass_split_all_insns (gcc::context
*ctxt
)
3879 return new pass_split_all_insns (ctxt
);
3883 rest_of_handle_split_after_reload (void)
3885 /* If optimizing, then go ahead and split insns now. */
3895 const pass_data pass_data_split_after_reload
=
3897 RTL_PASS
, /* type */
3898 "split2", /* name */
3899 OPTGROUP_NONE
, /* optinfo_flags */
3900 false, /* has_gate */
3901 true, /* has_execute */
3902 TV_NONE
, /* tv_id */
3903 0, /* properties_required */
3904 0, /* properties_provided */
3905 0, /* properties_destroyed */
3906 0, /* todo_flags_start */
3907 0, /* todo_flags_finish */
3910 class pass_split_after_reload
: public rtl_opt_pass
3913 pass_split_after_reload (gcc::context
*ctxt
)
3914 : rtl_opt_pass (pass_data_split_after_reload
, ctxt
)
3917 /* opt_pass methods: */
3918 unsigned int execute () { return rest_of_handle_split_after_reload (); }
3920 }; // class pass_split_after_reload
3925 make_pass_split_after_reload (gcc::context
*ctxt
)
3927 return new pass_split_after_reload (ctxt
);
3931 gate_handle_split_before_regstack (void)
3933 #if HAVE_ATTR_length && defined (STACK_REGS)
3934 /* If flow2 creates new instructions which need splitting
3935 and scheduling after reload is not done, they might not be
3936 split until final which doesn't allow splitting
3937 if HAVE_ATTR_length. */
3938 # ifdef INSN_SCHEDULING
3939 return (optimize
&& !flag_schedule_insns_after_reload
);
3949 rest_of_handle_split_before_regstack (void)
3957 const pass_data pass_data_split_before_regstack
=
3959 RTL_PASS
, /* type */
3960 "split3", /* name */
3961 OPTGROUP_NONE
, /* optinfo_flags */
3962 true, /* has_gate */
3963 true, /* has_execute */
3964 TV_NONE
, /* tv_id */
3965 0, /* properties_required */
3966 0, /* properties_provided */
3967 0, /* properties_destroyed */
3968 0, /* todo_flags_start */
3969 0, /* todo_flags_finish */
3972 class pass_split_before_regstack
: public rtl_opt_pass
3975 pass_split_before_regstack (gcc::context
*ctxt
)
3976 : rtl_opt_pass (pass_data_split_before_regstack
, ctxt
)
3979 /* opt_pass methods: */
3980 bool gate () { return gate_handle_split_before_regstack (); }
3981 unsigned int execute () {
3982 return rest_of_handle_split_before_regstack ();
3985 }; // class pass_split_before_regstack
3990 make_pass_split_before_regstack (gcc::context
*ctxt
)
3992 return new pass_split_before_regstack (ctxt
);
3996 gate_handle_split_before_sched2 (void)
3998 #ifdef INSN_SCHEDULING
3999 return optimize
> 0 && flag_schedule_insns_after_reload
;
4006 rest_of_handle_split_before_sched2 (void)
4008 #ifdef INSN_SCHEDULING
4016 const pass_data pass_data_split_before_sched2
=
4018 RTL_PASS
, /* type */
4019 "split4", /* name */
4020 OPTGROUP_NONE
, /* optinfo_flags */
4021 true, /* has_gate */
4022 true, /* has_execute */
4023 TV_NONE
, /* tv_id */
4024 0, /* properties_required */
4025 0, /* properties_provided */
4026 0, /* properties_destroyed */
4027 0, /* todo_flags_start */
4028 TODO_verify_flow
, /* todo_flags_finish */
4031 class pass_split_before_sched2
: public rtl_opt_pass
4034 pass_split_before_sched2 (gcc::context
*ctxt
)
4035 : rtl_opt_pass (pass_data_split_before_sched2
, ctxt
)
4038 /* opt_pass methods: */
4039 bool gate () { return gate_handle_split_before_sched2 (); }
4040 unsigned int execute () { return rest_of_handle_split_before_sched2 (); }
4042 }; // class pass_split_before_sched2
4047 make_pass_split_before_sched2 (gcc::context
*ctxt
)
4049 return new pass_split_before_sched2 (ctxt
);
4052 /* The placement of the splitting that we do for shorten_branches
4053 depends on whether regstack is used by the target or not. */
4055 gate_do_final_split (void)
4057 #if HAVE_ATTR_length && !defined (STACK_REGS)
4066 const pass_data pass_data_split_for_shorten_branches
=
4068 RTL_PASS
, /* type */
4069 "split5", /* name */
4070 OPTGROUP_NONE
, /* optinfo_flags */
4071 true, /* has_gate */
4072 true, /* has_execute */
4073 TV_NONE
, /* tv_id */
4074 0, /* properties_required */
4075 0, /* properties_provided */
4076 0, /* properties_destroyed */
4077 0, /* todo_flags_start */
4078 TODO_verify_rtl_sharing
, /* todo_flags_finish */
4081 class pass_split_for_shorten_branches
: public rtl_opt_pass
4084 pass_split_for_shorten_branches (gcc::context
*ctxt
)
4085 : rtl_opt_pass (pass_data_split_for_shorten_branches
, ctxt
)
4088 /* opt_pass methods: */
4089 bool gate () { return gate_do_final_split (); }
4090 unsigned int execute () { return split_all_insns_noflow (); }
4092 }; // class pass_split_for_shorten_branches
4097 make_pass_split_for_shorten_branches (gcc::context
*ctxt
)
4099 return new pass_split_for_shorten_branches (ctxt
);