gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
   4    2011, 2012 Free Software Foundation, Inc.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify it under
   9 the terms of the GNU General Public License as published by the Free
  10 Software Foundation; either version 3, or (at your option) any later
  11 version.
  12
  13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triplets of insns A, B and C when C has
  34    a link back to B and B has a link back to A.  Likewise for a
  35    small number of quadruplets of insns A, B, C and D for which
  36    there's high likelihood of of success.
  37
  38    LOG_LINKS does not have links for use of the CC0.  They don't
  39    need to, because the insn that sets the CC0 is always immediately
  40    before the insn that tests it.  So we always regard a branch
  41    insn as having a logical link to the preceding insn.  The same is true
  42    for an insn explicitly using CC0.
  43
  44    We check (with use_crosses_set_p) to avoid combining in such a way
  45    as to move a computation to a place where its value would be different.
  46
  47    Combination is done by mathematically substituting the previous
  48    insn(s) values for the regs they set into the expressions in
  49    the later insns that refer to these regs.  If the result is a valid insn
  50    for our target machine, according to the machine description,
  51    we install it, delete the earlier insns, and update the data flow
  52    information (LOG_LINKS and REG_NOTES) for what we did.
  53
  54    There are a few exceptions where the dataflow information isn't
  55    completely updated (however this is only a local issue since it is
  56    regenerated before the next pass that uses it):
  57
  58    - reg_live_length is not updated
  59    - reg_n_refs is not adjusted in the rare case when a register is
  60      no longer required in a computation
  61    - there are extremely rare cases (see distribute_notes) when a
  62      REG_DEAD note is lost
  63    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  64      removed because there is no way to know which register it was
  65      linking
  66
  67    To simplify substitution, we combine only when the earlier insn(s)
  68    consist of only a single assignment.  To simplify updating afterward,
  69    we never combine when a subroutine call appears in the middle.
  70
  71    Since we do not represent assignments to CC0 explicitly except when that
  72    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  73    the condition code for the insn that set the condition code.
  74    Fortunately, these two insns must be consecutive.
  75    Therefore, every JUMP_INSN is taken to have an implicit logical link
  76    to the preceding insn.  This is not quite right, since non-jumps can
  77    also use the condition code; but in practice such insns would not
  78    combine anyway.  */
  79
  80 #include "config.h"
  81 #include "system.h"
  82 #include "coretypes.h"
  83 #include "tm.h"
  84 #include "rtl.h"
  85 #include "tree.h"
  86 #include "tm_p.h"
  87 #include "flags.h"
  88 #include "regs.h"
  89 #include "hard-reg-set.h"
  90 #include "basic-block.h"
  91 #include "insn-config.h"
  92 #include "function.h"
  93 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  94 #include "expr.h"
  95 #include "insn-attr.h"
  96 #include "recog.h"
  97 #include "diagnostic-core.h"
  98 #include "target.h"
  99 #include "optabs.h"
 100 #include "insn-codes.h"
 101 #include "rtlhooks-def.h"
 102 #include "params.h"
 103 #include "tree-pass.h"
 104 #include "df.h"
 105 #include "valtrack.h"
 106 #include "cgraph.h"
 107 #include "obstack.h"
 108
 109 /* Number of attempts to combine instructions in this function.  */
 110
 111 static int combine_attempts;
 112
 113 /* Number of attempts that got as far as substitution in this function.  */
 114
 115 static int combine_merges;
 116
 117 /* Number of instructions combined with added SETs in this function.  */
 118
 119 static int combine_extras;
 120
 121 /* Number of instructions combined in this function.  */
 122
 123 static int combine_successes;
 124
 125 /* Totals over entire compilation.  */
 126
 127 static int total_attempts, total_merges, total_extras, total_successes;
 128
 129 /* combine_instructions may try to replace the right hand side of the
 130    second instruction with the value of an associated REG_EQUAL note
 131    before throwing it at try_combine.  That is problematic when there
 132    is a REG_DEAD note for a register used in the old right hand side
 133    and can cause distribute_notes to do wrong things.  This is the
 134    second instruction if it has been so modified, null otherwise.  */
 135
 136 static rtx i2mod;
 137
 138 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 139
 140 static rtx i2mod_old_rhs;
 141
 142 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 143
 144 static rtx i2mod_new_rhs;
 145 \f
 146 typedef struct reg_stat_struct {
 147   /* Record last point of death of (hard or pseudo) register n.  */
 148   rtx                           last_death;
 149
 150   /* Record last point of modification of (hard or pseudo) register n.  */
 151   rtx                           last_set;
 152
 153   /* The next group of fields allows the recording of the last value assigned
 154      to (hard or pseudo) register n.  We use this information to see if an
 155      operation being processed is redundant given a prior operation performed
 156      on the register.  For example, an `and' with a constant is redundant if
 157      all the zero bits are already known to be turned off.
 158
 159      We use an approach similar to that used by cse, but change it in the
 160      following ways:
 161
 162      (1) We do not want to reinitialize at each label.
 163      (2) It is useful, but not critical, to know the actual value assigned
 164          to a register.  Often just its form is helpful.
 165
 166      Therefore, we maintain the following fields:
 167
 168      last_set_value             the last value assigned
 169      last_set_label             records the value of label_tick when the
 170                                 register was assigned
 171      last_set_table_tick        records the value of label_tick when a
 172                                 value using the register is assigned
 173      last_set_invalid           set to nonzero when it is not valid
 174                                 to use the value of this register in some
 175                                 register's value
 176
 177      To understand the usage of these tables, it is important to understand
 178      the distinction between the value in last_set_value being valid and
 179      the register being validly contained in some other expression in the
 180      table.
 181
 182      (The next two parameters are out of date).
 183
 184      reg_stat[i].last_set_value is valid if it is nonzero, and either
 185      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 186
 187      Register I may validly appear in any expression returned for the value
 188      of another register if reg_n_sets[i] is 1.  It may also appear in the
 189      value for register J if reg_stat[j].last_set_invalid is zero, or
 190      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 191
 192      If an expression is found in the table containing a register which may
 193      not validly appear in an expression, the register is replaced by
 194      something that won't match, (clobber (const_int 0)).  */
 195
 196   /* Record last value assigned to (hard or pseudo) register n.  */
 197
 198   rtx                           last_set_value;
 199
 200   /* Record the value of label_tick when an expression involving register n
 201      is placed in last_set_value.  */
 202
 203   int                           last_set_table_tick;
 204
 205   /* Record the value of label_tick when the value for register n is placed in
 206      last_set_value.  */
 207
 208   int                           last_set_label;
 209
 210   /* These fields are maintained in parallel with last_set_value and are
 211      used to store the mode in which the register was last set, the bits
 212      that were known to be zero when it was last set, and the number of
 213      sign bits copies it was known to have when it was last set.  */
 214
 215   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 216   char                          last_set_sign_bit_copies;
 217   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 218
 219   /* Set nonzero if references to register n in expressions should not be
 220      used.  last_set_invalid is set nonzero when this register is being
 221      assigned to and last_set_table_tick == label_tick.  */
 222
 223   char                          last_set_invalid;
 224
 225   /* Some registers that are set more than once and used in more than one
 226      basic block are nevertheless always set in similar ways.  For example,
 227      a QImode register may be loaded from memory in two places on a machine
 228      where byte loads zero extend.
 229
 230      We record in the following fields if a register has some leading bits
 231      that are always equal to the sign bit, and what we know about the
 232      nonzero bits of a register, specifically which bits are known to be
 233      zero.
 234
 235      If an entry is zero, it means that we don't know anything special.  */
 236
 237   unsigned char                 sign_bit_copies;
 238
 239   unsigned HOST_WIDE_INT        nonzero_bits;
 240
 241   /* Record the value of the label_tick when the last truncation
 242      happened.  The field truncated_to_mode is only valid if
 243      truncation_label == label_tick.  */
 244
 245   int                           truncation_label;
 246
 247   /* Record the last truncation seen for this register.  If truncation
 248      is not a nop to this mode we might be able to save an explicit
 249      truncation if we know that value already contains a truncated
 250      value.  */
 251
 252   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 253 } reg_stat_type;
 254
 255 DEF_VEC_O(reg_stat_type);
 256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
 257
 258 static VEC(reg_stat_type,heap) *reg_stat;
 259
 260 /* Record the luid of the last insn that invalidated memory
 261    (anything that writes memory, and subroutine calls, but not pushes).  */
 262
 263 static int mem_last_set;
 264
 265 /* Record the luid of the last CALL_INSN
 266    so we can tell whether a potential combination crosses any calls.  */
 267
 268 static int last_call_luid;
 269
 270 /* When `subst' is called, this is the insn that is being modified
 271    (by combining in a previous insn).  The PATTERN of this insn
 272    is still the old pattern partially modified and it should not be
 273    looked at, but this may be used to examine the successors of the insn
 274    to judge whether a simplification is valid.  */
 275
 276 static rtx subst_insn;
 277
 278 /* This is the lowest LUID that `subst' is currently dealing with.
 279    get_last_value will not return a value if the register was set at or
 280    after this LUID.  If not for this mechanism, we could get confused if
 281    I2 or I1 in try_combine were an insn that used the old value of a register
 282    to obtain a new value.  In that case, we might erroneously get the
 283    new value of the register when we wanted the old one.  */
 284
 285 static int subst_low_luid;
 286
 287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 288    must consider all these registers to be always live.  */
 289
 290 static HARD_REG_SET newpat_used_regs;
 291
 292 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 293    insn is the earlier than I2 or I3, combine should rescan starting at
 294    that location.  */
 295
 296 static rtx added_links_insn;
 297
 298 /* Basic block in which we are performing combines.  */
 299 static basic_block this_basic_block;
 300 static bool optimize_this_for_speed_p;
 301
 302 \f
 303 /* Length of the currently allocated uid_insn_cost array.  */
 304
 305 static int max_uid_known;
 306
 307 /* The following array records the insn_rtx_cost for every insn
 308    in the instruction stream.  */
 309
 310 static int *uid_insn_cost;
 311
 312 /* The following array records the LOG_LINKS for every insn in the
 313    instruction stream as struct insn_link pointers.  */
 314
 315 struct insn_link {
 316   rtx insn;
 317   struct insn_link *next;
 318 };
 319
 320 static struct insn_link **uid_log_links;
 321
 322 #define INSN_COST(INSN)         (uid_insn_cost[INSN_UID (INSN)])
 323 #define LOG_LINKS(INSN)         (uid_log_links[INSN_UID (INSN)])
 324
 325 #define FOR_EACH_LOG_LINK(L, INSN)                              \
 326   for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
 327
 328 /* Links for LOG_LINKS are allocated from this obstack.  */
 329
 330 static struct obstack insn_link_obstack;
 331
 332 /* Allocate a link.  */
 333
 334 static inline struct insn_link *
 335 alloc_insn_link (rtx insn, struct insn_link *next)
 336 {
 337   struct insn_link *l
 338     = (struct insn_link *) obstack_alloc (&insn_link_obstack,
 339                                           sizeof (struct insn_link));
 340   l->insn = insn;
 341   l->next = next;
 342   return l;
 343 }
 344
 345 /* Incremented for each basic block.  */
 346
 347 static int label_tick;
 348
 349 /* Reset to label_tick for each extended basic block in scanning order.  */
 350
 351 static int label_tick_ebb_start;
 352
 353 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 354    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 355
 356 static enum machine_mode nonzero_bits_mode;
 357
 358 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 359    be safely used.  It is zero while computing them and after combine has
 360    completed.  This former test prevents propagating values based on
 361    previously set values, which can be incorrect if a variable is modified
 362    in a loop.  */
 363
 364 static int nonzero_sign_valid;
 365
 366 \f
 367 /* Record one modification to rtl structure
 368    to be undone by storing old_contents into *where.  */
 369
 370 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
 371
 372 struct undo
 373 {
 374   struct undo *next;
 375   enum undo_kind kind;
 376   union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents;
 377   union { rtx *r; int *i; struct insn_link **l; } where;
 378 };
 379
 380 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 381    num_undo says how many are currently recorded.
 382
 383    other_insn is nonzero if we have modified some other insn in the process
 384    of working on subst_insn.  It must be verified too.  */
 385
 386 struct undobuf
 387 {
 388   struct undo *undos;
 389   struct undo *frees;
 390   rtx other_insn;
 391 };
 392
 393 static struct undobuf undobuf;
 394
 395 /* Number of times the pseudo being substituted for
 396    was found and replaced.  */
 397
 398 static int n_occurrences;
 399
 400 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
 401                                          enum machine_mode,
 402                                          unsigned HOST_WIDE_INT,
 403                                          unsigned HOST_WIDE_INT *);
 404 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
 405                                                 enum machine_mode,
 406                                                 unsigned int, unsigned int *);
 407 static void do_SUBST (rtx *, rtx);
 408 static void do_SUBST_INT (int *, int);
 409 static void init_reg_last (void);
 410 static void setup_incoming_promotions (rtx);
 411 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
 412 static int cant_combine_insn_p (rtx);
 413 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
 414 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
 415 static int contains_muldiv (rtx);
 416 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
 417 static void undo_all (void);
 418 static void undo_commit (void);
 419 static rtx *find_split_point (rtx *, rtx, bool);
 420 static rtx subst (rtx, rtx, rtx, int, int, int);
 421 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
 422 static rtx simplify_if_then_else (rtx);
 423 static rtx simplify_set (rtx);
 424 static rtx simplify_logical (rtx);
 425 static rtx expand_compound_operation (rtx);
 426 static const_rtx expand_field_assignment (const_rtx);
 427 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 428                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 429 static rtx extract_left_shift (rtx, int);
 430 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 431                               unsigned HOST_WIDE_INT *);
 432 static rtx canon_reg_for_combine (rtx, rtx);
 433 static rtx force_to_mode (rtx, enum machine_mode,
 434                           unsigned HOST_WIDE_INT, int);
 435 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 436 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 437 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 438 static rtx make_field_assignment (rtx);
 439 static rtx apply_distributive_law (rtx);
 440 static rtx distribute_and_simplify_rtx (rtx, int);
 441 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 442                                      unsigned HOST_WIDE_INT);
 443 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 444                                    unsigned HOST_WIDE_INT);
 445 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 446                             HOST_WIDE_INT, enum machine_mode, int *);
 447 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 448 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 449                                  int);
 450 static int recog_for_combine (rtx *, rtx, rtx *);
 451 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 452 static enum rtx_code simplify_compare_const (enum rtx_code, rtx, rtx *);
 453 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 454 static void update_table_tick (rtx);
 455 static void record_value_for_reg (rtx, rtx, rtx);
 456 static void check_promoted_subreg (rtx, rtx);
 457 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
 458 static void record_dead_and_set_regs (rtx);
 459 static int get_last_value_validate (rtx *, rtx, int, int);
 460 static rtx get_last_value (const_rtx);
 461 static int use_crosses_set_p (const_rtx, int);
 462 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
 463 static int reg_dead_at_p (rtx, rtx);
 464 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 465 static int reg_bitfield_target_p (rtx, rtx);
 466 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
 467 static void distribute_links (struct insn_link *);
 468 static void mark_used_regs_combine (rtx);
 469 static void record_promoted_value (rtx, rtx);
 470 static int unmentioned_reg_p_1 (rtx *, void *);
 471 static bool unmentioned_reg_p (rtx, rtx);
 472 static int record_truncated_value (rtx *, void *);
 473 static void record_truncated_values (rtx *, void *);
 474 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
 475 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 476 \f
 477
 478 /* It is not safe to use ordinary gen_lowpart in combine.
 479    See comments in gen_lowpart_for_combine.  */
 480 #undef RTL_HOOKS_GEN_LOWPART
 481 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 482
 483 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 484 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 485 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 486
 487 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 488 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 489
 490 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 491 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 492
 493 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 494 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 495
 496 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 497
 498 \f
 499 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 500    PATTERN can not be split.  Otherwise, it returns an insn sequence.
 501    This is a wrapper around split_insns which ensures that the
 502    reg_stat vector is made larger if the splitter creates a new
 503    register.  */
 504
 505 static rtx
 506 combine_split_insns (rtx pattern, rtx insn)
 507 {
 508   rtx ret;
 509   unsigned int nregs;
 510
 511   ret = split_insns (pattern, insn);
 512   nregs = max_reg_num ();
 513   if (nregs > VEC_length (reg_stat_type, reg_stat))
 514     VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
 515   return ret;
 516 }
 517
 518 /* This is used by find_single_use to locate an rtx in LOC that
 519    contains exactly one use of DEST, which is typically either a REG
 520    or CC0.  It returns a pointer to the innermost rtx expression
 521    containing DEST.  Appearances of DEST that are being used to
 522    totally replace it are not counted.  */
 523
 524 static rtx *
 525 find_single_use_1 (rtx dest, rtx *loc)
 526 {
 527   rtx x = *loc;
 528   enum rtx_code code = GET_CODE (x);
 529   rtx *result = NULL;
 530   rtx *this_result;
 531   int i;
 532   const char *fmt;
 533
 534   switch (code)
 535     {
 536     case CONST:
 537     case LABEL_REF:
 538     case SYMBOL_REF:
 539     CASE_CONST_ANY:
 540     case CLOBBER:
 541       return 0;
 542
 543     case SET:
 544       /* If the destination is anything other than CC0, PC, a REG or a SUBREG
 545          of a REG that occupies all of the REG, the insn uses DEST if
 546          it is mentioned in the destination or the source.  Otherwise, we
 547          need just check the source.  */
 548       if (GET_CODE (SET_DEST (x)) != CC0
 549           && GET_CODE (SET_DEST (x)) != PC
 550           && !REG_P (SET_DEST (x))
 551           && ! (GET_CODE (SET_DEST (x)) == SUBREG
 552                 && REG_P (SUBREG_REG (SET_DEST (x)))
 553                 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
 554                       + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
 555                     == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
 556                          + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
 557         break;
 558
 559       return find_single_use_1 (dest, &SET_SRC (x));
 560
 561     case MEM:
 562     case SUBREG:
 563       return find_single_use_1 (dest, &XEXP (x, 0));
 564
 565     default:
 566       break;
 567     }
 568
 569   /* If it wasn't one of the common cases above, check each expression and
 570      vector of this code.  Look for a unique usage of DEST.  */
 571
 572   fmt = GET_RTX_FORMAT (code);
 573   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
 574     {
 575       if (fmt[i] == 'e')
 576         {
 577           if (dest == XEXP (x, i)
 578               || (REG_P (dest) && REG_P (XEXP (x, i))
 579                   && REGNO (dest) == REGNO (XEXP (x, i))))
 580             this_result = loc;
 581           else
 582             this_result = find_single_use_1 (dest, &XEXP (x, i));
 583
 584           if (result == NULL)
 585             result = this_result;
 586           else if (this_result)
 587             /* Duplicate usage.  */
 588             return NULL;
 589         }
 590       else if (fmt[i] == 'E')
 591         {
 592           int j;
 593
 594           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
 595             {
 596               if (XVECEXP (x, i, j) == dest
 597                   || (REG_P (dest)
 598                       && REG_P (XVECEXP (x, i, j))
 599                       && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
 600                 this_result = loc;
 601               else
 602                 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
 603
 604               if (result == NULL)
 605                 result = this_result;
 606               else if (this_result)
 607                 return NULL;
 608             }
 609         }
 610     }
 611
 612   return result;
 613 }
 614
 615
 616 /* See if DEST, produced in INSN, is used only a single time in the
 617    sequel.  If so, return a pointer to the innermost rtx expression in which
 618    it is used.
 619
 620    If PLOC is nonzero, *PLOC is set to the insn containing the single use.
 621
 622    If DEST is cc0_rtx, we look only at the next insn.  In that case, we don't
 623    care about REG_DEAD notes or LOG_LINKS.
 624
 625    Otherwise, we find the single use by finding an insn that has a
 626    LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 627    only referenced once in that insn, we know that it must be the first
 628    and last insn referencing DEST.  */
 629
 630 static rtx *
 631 find_single_use (rtx dest, rtx insn, rtx *ploc)
 632 {
 633   basic_block bb;
 634   rtx next;
 635   rtx *result;
 636   struct insn_link *link;
 637
 638 #ifdef HAVE_cc0
 639   if (dest == cc0_rtx)
 640     {
 641       next = NEXT_INSN (insn);
 642       if (next == 0
 643           || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
 644         return 0;
 645
 646       result = find_single_use_1 (dest, &PATTERN (next));
 647       if (result && ploc)
 648         *ploc = next;
 649       return result;
 650     }
 651 #endif
 652
 653   if (!REG_P (dest))
 654     return 0;
 655
 656   bb = BLOCK_FOR_INSN (insn);
 657   for (next = NEXT_INSN (insn);
 658        next && BLOCK_FOR_INSN (next) == bb;
 659        next = NEXT_INSN (next))
 660     if (INSN_P (next) && dead_or_set_p (next, dest))
 661       {
 662         FOR_EACH_LOG_LINK (link, next)
 663           if (link->insn == insn)
 664             break;
 665
 666         if (link)
 667           {
 668             result = find_single_use_1 (dest, &PATTERN (next));
 669             if (ploc)
 670               *ploc = next;
 671             return result;
 672           }
 673       }
 674
 675   return 0;
 676 }
 677 \f
 678 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 679    insn.  The substitution can be undone by undo_all.  If INTO is already
 680    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 681    also call SUBST, we have to compute it before we put anything into
 682    the undo table.  */
 683
 684 static void
 685 do_SUBST (rtx *into, rtx newval)
 686 {
 687   struct undo *buf;
 688   rtx oldval = *into;
 689
 690   if (oldval == newval)
 691     return;
 692
 693   /* We'd like to catch as many invalid transformations here as
 694      possible.  Unfortunately, there are way too many mode changes
 695      that are perfectly valid, so we'd waste too much effort for
 696      little gain doing the checks here.  Focus on catching invalid
 697      transformations involving integer constants.  */
 698   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 699       && CONST_INT_P (newval))
 700     {
 701       /* Sanity check that we're replacing oldval with a CONST_INT
 702          that is a valid sign-extension for the original mode.  */
 703       gcc_assert (INTVAL (newval)
 704                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 705
 706       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 707          CONST_INT is not valid, because after the replacement, the
 708          original mode would be gone.  Unfortunately, we can't tell
 709          when do_SUBST is called to replace the operand thereof, so we
 710          perform this test on oldval instead, checking whether an
 711          invalid replacement took place before we got here.  */
 712       gcc_assert (!(GET_CODE (oldval) == SUBREG
 713                     && CONST_INT_P (SUBREG_REG (oldval))));
 714       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 715                     && CONST_INT_P (XEXP (oldval, 0))));
 716     }
 717
 718   if (undobuf.frees)
 719     buf = undobuf.frees, undobuf.frees = buf->next;
 720   else
 721     buf = XNEW (struct undo);
 722
 723   buf->kind = UNDO_RTX;
 724   buf->where.r = into;
 725   buf->old_contents.r = oldval;
 726   *into = newval;
 727
 728   buf->next = undobuf.undos, undobuf.undos = buf;
 729 }
 730
 731 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 732
 733 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 734    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 735    not safe.  */
 736
 737 static void
 738 do_SUBST_INT (int *into, int newval)
 739 {
 740   struct undo *buf;
 741   int oldval = *into;
 742
 743   if (oldval == newval)
 744     return;
 745
 746   if (undobuf.frees)
 747     buf = undobuf.frees, undobuf.frees = buf->next;
 748   else
 749     buf = XNEW (struct undo);
 750
 751   buf->kind = UNDO_INT;
 752   buf->where.i = into;
 753   buf->old_contents.i = oldval;
 754   *into = newval;
 755
 756   buf->next = undobuf.undos, undobuf.undos = buf;
 757 }
 758
 759 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 760
 761 /* Similar to SUBST, but just substitute the mode.  This is used when
 762    changing the mode of a pseudo-register, so that any other
 763    references to the entry in the regno_reg_rtx array will change as
 764    well.  */
 765
 766 static void
 767 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 768 {
 769   struct undo *buf;
 770   enum machine_mode oldval = GET_MODE (*into);
 771
 772   if (oldval == newval)
 773     return;
 774
 775   if (undobuf.frees)
 776     buf = undobuf.frees, undobuf.frees = buf->next;
 777   else
 778     buf = XNEW (struct undo);
 779
 780   buf->kind = UNDO_MODE;
 781   buf->where.r = into;
 782   buf->old_contents.m = oldval;
 783   adjust_reg_mode (*into, newval);
 784
 785   buf->next = undobuf.undos, undobuf.undos = buf;
 786 }
 787
 788 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 789
 790 #ifndef HAVE_cc0
 791 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression.  */
 792
 793 static void
 794 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
 795 {
 796   struct undo *buf;
 797   struct insn_link * oldval = *into;
 798
 799   if (oldval == newval)
 800     return;
 801
 802   if (undobuf.frees)
 803     buf = undobuf.frees, undobuf.frees = buf->next;
 804   else
 805     buf = XNEW (struct undo);
 806
 807   buf->kind = UNDO_LINKS;
 808   buf->where.l = into;
 809   buf->old_contents.l = oldval;
 810   *into = newval;
 811
 812   buf->next = undobuf.undos, undobuf.undos = buf;
 813 }
 814
 815 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
 816 #endif
 817 \f
 818 /* Subroutine of try_combine.  Determine whether the replacement patterns
 819    NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
 820    than the original sequence I0, I1, I2, I3 and undobuf.other_insn.  Note
 821    that I0, I1 and/or NEWI2PAT may be NULL_RTX.  Similarly, NEWOTHERPAT and
 822    undobuf.other_insn may also both be NULL_RTX.  Return false if the cost
 823    of all the instructions can be estimated and the replacements are more
 824    expensive than the original sequence.  */
 825
 826 static bool
 827 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
 828                        rtx newi2pat, rtx newotherpat)
 829 {
 830   int i0_cost, i1_cost, i2_cost, i3_cost;
 831   int new_i2_cost, new_i3_cost;
 832   int old_cost, new_cost;
 833
 834   /* Lookup the original insn_rtx_costs.  */
 835   i2_cost = INSN_COST (i2);
 836   i3_cost = INSN_COST (i3);
 837
 838   if (i1)
 839     {
 840       i1_cost = INSN_COST (i1);
 841       if (i0)
 842         {
 843           i0_cost = INSN_COST (i0);
 844           old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 845                       ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
 846         }
 847       else
 848         {
 849           old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 850                       ? i1_cost + i2_cost + i3_cost : 0);
 851           i0_cost = 0;
 852         }
 853     }
 854   else
 855     {
 856       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 857       i1_cost = i0_cost = 0;
 858     }
 859
 860   /* Calculate the replacement insn_rtx_costs.  */
 861   new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
 862   if (newi2pat)
 863     {
 864       new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
 865       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 866                  ? new_i2_cost + new_i3_cost : 0;
 867     }
 868   else
 869     {
 870       new_cost = new_i3_cost;
 871       new_i2_cost = 0;
 872     }
 873
 874   if (undobuf.other_insn)
 875     {
 876       int old_other_cost, new_other_cost;
 877
 878       old_other_cost = INSN_COST (undobuf.other_insn);
 879       new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
 880       if (old_other_cost > 0 && new_other_cost > 0)
 881         {
 882           old_cost += old_other_cost;
 883           new_cost += new_other_cost;
 884         }
 885       else
 886         old_cost = 0;
 887     }
 888
 889   /* Disallow this combination if both new_cost and old_cost are greater than
 890      zero, and new_cost is greater than old cost.  */
 891   if (old_cost > 0 && new_cost > old_cost)
 892     {
 893       if (dump_file)
 894         {
 895           if (i0)
 896             {
 897               fprintf (dump_file,
 898                        "rejecting combination of insns %d, %d, %d and %d\n",
 899                        INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
 900                        INSN_UID (i3));
 901               fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
 902                        i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
 903             }
 904           else if (i1)
 905             {
 906               fprintf (dump_file,
 907                        "rejecting combination of insns %d, %d and %d\n",
 908                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 909               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 910                        i1_cost, i2_cost, i3_cost, old_cost);
 911             }
 912           else
 913             {
 914               fprintf (dump_file,
 915                        "rejecting combination of insns %d and %d\n",
 916                        INSN_UID (i2), INSN_UID (i3));
 917               fprintf (dump_file, "original costs %d + %d = %d\n",
 918                        i2_cost, i3_cost, old_cost);
 919             }
 920
 921           if (newi2pat)
 922             {
 923               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 924                        new_i2_cost, new_i3_cost, new_cost);
 925             }
 926           else
 927             fprintf (dump_file, "replacement cost %d\n", new_cost);
 928         }
 929
 930       return false;
 931     }
 932
 933   /* Update the uid_insn_cost array with the replacement costs.  */
 934   INSN_COST (i2) = new_i2_cost;
 935   INSN_COST (i3) = new_i3_cost;
 936   if (i1)
 937     {
 938       INSN_COST (i1) = 0;
 939       if (i0)
 940         INSN_COST (i0) = 0;
 941     }
 942
 943   return true;
 944 }
 945
 946
 947 /* Delete any insns that copy a register to itself.  */
 948
 949 static void
 950 delete_noop_moves (void)
 951 {
 952   rtx insn, next;
 953   basic_block bb;
 954
 955   FOR_EACH_BB (bb)
 956     {
 957       for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 958         {
 959           next = NEXT_INSN (insn);
 960           if (INSN_P (insn) && noop_move_p (insn))
 961             {
 962               if (dump_file)
 963                 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
 964
 965               delete_insn_and_edges (insn);
 966             }
 967         }
 968     }
 969 }
 970
 971 \f
 972 /* Fill in log links field for all insns.  */
 973
 974 static void
 975 create_log_links (void)
 976 {
 977   basic_block bb;
 978   rtx *next_use, insn;
 979   df_ref *def_vec, *use_vec;
 980
 981   next_use = XCNEWVEC (rtx, max_reg_num ());
 982
 983   /* Pass through each block from the end, recording the uses of each
 984      register and establishing log links when def is encountered.
 985      Note that we do not clear next_use array in order to save time,
 986      so we have to test whether the use is in the same basic block as def.
 987
 988      There are a few cases below when we do not consider the definition or
 989      usage -- these are taken from original flow.c did. Don't ask me why it is
 990      done this way; I don't know and if it works, I don't want to know.  */
 991
 992   FOR_EACH_BB (bb)
 993     {
 994       FOR_BB_INSNS_REVERSE (bb, insn)
 995         {
 996           if (!NONDEBUG_INSN_P (insn))
 997             continue;
 998
 999           /* Log links are created only once.  */
1000           gcc_assert (!LOG_LINKS (insn));
1001
1002           for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
1003             {
1004               df_ref def = *def_vec;
1005               int regno = DF_REF_REGNO (def);
1006               rtx use_insn;
1007
1008               if (!next_use[regno])
1009                 continue;
1010
1011               /* Do not consider if it is pre/post modification in MEM.  */
1012               if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1013                 continue;
1014
1015               /* Do not make the log link for frame pointer.  */
1016               if ((regno == FRAME_POINTER_REGNUM
1017                    && (! reload_completed || frame_pointer_needed))
1018 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1019                   || (regno == HARD_FRAME_POINTER_REGNUM
1020                       && (! reload_completed || frame_pointer_needed))
1021 #endif
1022 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1023                   || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1024 #endif
1025                   )
1026                 continue;
1027
1028               use_insn = next_use[regno];
1029               if (BLOCK_FOR_INSN (use_insn) == bb)
1030                 {
1031                   /* flow.c claimed:
1032
1033                      We don't build a LOG_LINK for hard registers contained
1034                      in ASM_OPERANDs.  If these registers get replaced,
1035                      we might wind up changing the semantics of the insn,
1036                      even if reload can make what appear to be valid
1037                      assignments later.  */
1038                   if (regno >= FIRST_PSEUDO_REGISTER
1039                       || asm_noperands (PATTERN (use_insn)) < 0)
1040                     {
1041                       /* Don't add duplicate links between instructions.  */
1042                       struct insn_link *links;
1043                       FOR_EACH_LOG_LINK (links, use_insn)
1044                         if (insn == links->insn)
1045                           break;
1046
1047                       if (!links)
1048                         LOG_LINKS (use_insn)
1049                           = alloc_insn_link (insn, LOG_LINKS (use_insn));
1050                     }
1051                 }
1052               next_use[regno] = NULL_RTX;
1053             }
1054
1055           for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1056             {
1057               df_ref use = *use_vec;
1058               int regno = DF_REF_REGNO (use);
1059
1060               /* Do not consider the usage of the stack pointer
1061                  by function call.  */
1062               if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1063                 continue;
1064
1065               next_use[regno] = insn;
1066             }
1067         }
1068     }
1069
1070   free (next_use);
1071 }
1072
1073 /* Walk the LOG_LINKS of insn B to see if we find a reference to A.  Return
1074    true if we found a LOG_LINK that proves that A feeds B.  This only works
1075    if there are no instructions between A and B which could have a link
1076    depending on A, since in that case we would not record a link for B.
1077    We also check the implicit dependency created by a cc0 setter/user
1078    pair.  */
1079
1080 static bool
1081 insn_a_feeds_b (rtx a, rtx b)
1082 {
1083   struct insn_link *links;
1084   FOR_EACH_LOG_LINK (links, b)
1085     if (links->insn == a)
1086       return true;
1087 #ifdef HAVE_cc0
1088   if (sets_cc0_p (a))
1089     return true;
1090 #endif
1091   return false;
1092 }
1093 \f
1094 /* Main entry point for combiner.  F is the first insn of the function.
1095    NREGS is the first unused pseudo-reg number.
1096
1097    Return nonzero if the combiner has turned an indirect jump
1098    instruction into a direct jump.  */
1099 static int
1100 combine_instructions (rtx f, unsigned int nregs)
1101 {
1102   rtx insn, next;
1103 #ifdef HAVE_cc0
1104   rtx prev;
1105 #endif
1106   struct insn_link *links, *nextlinks;
1107   rtx first;
1108   basic_block last_bb;
1109
1110   int new_direct_jump_p = 0;
1111
1112   for (first = f; first && !INSN_P (first); )
1113     first = NEXT_INSN (first);
1114   if (!first)
1115     return 0;
1116
1117   combine_attempts = 0;
1118   combine_merges = 0;
1119   combine_extras = 0;
1120   combine_successes = 0;
1121
1122   rtl_hooks = combine_rtl_hooks;
1123
1124   VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1125
1126   init_recog_no_volatile ();
1127
1128   /* Allocate array for insn info.  */
1129   max_uid_known = get_max_uid ();
1130   uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1131   uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1132   gcc_obstack_init (&insn_link_obstack);
1133
1134   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1135
1136   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
1137      problems when, for example, we have j <<= 1 in a loop.  */
1138
1139   nonzero_sign_valid = 0;
1140   label_tick = label_tick_ebb_start = 1;
1141
1142   /* Scan all SETs and see if we can deduce anything about what
1143      bits are known to be zero for some registers and how many copies
1144      of the sign bit are known to exist for those registers.
1145
1146      Also set any known values so that we can use it while searching
1147      for what bits are known to be set.  */
1148
1149   setup_incoming_promotions (first);
1150   /* Allow the entry block and the first block to fall into the same EBB.
1151      Conceptually the incoming promotions are assigned to the entry block.  */
1152   last_bb = ENTRY_BLOCK_PTR;
1153
1154   create_log_links ();
1155   FOR_EACH_BB (this_basic_block)
1156     {
1157       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1158       last_call_luid = 0;
1159       mem_last_set = -1;
1160
1161       label_tick++;
1162       if (!single_pred_p (this_basic_block)
1163           || single_pred (this_basic_block) != last_bb)
1164         label_tick_ebb_start = label_tick;
1165       last_bb = this_basic_block;
1166
1167       FOR_BB_INSNS (this_basic_block, insn)
1168         if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1169           {
1170 #ifdef AUTO_INC_DEC
1171             rtx links;
1172 #endif
1173
1174             subst_low_luid = DF_INSN_LUID (insn);
1175             subst_insn = insn;
1176
1177             note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1178                          insn);
1179             record_dead_and_set_regs (insn);
1180
1181 #ifdef AUTO_INC_DEC
1182             for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1183               if (REG_NOTE_KIND (links) == REG_INC)
1184                 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1185                                                   insn);
1186 #endif
1187
1188             /* Record the current insn_rtx_cost of this instruction.  */
1189             if (NONJUMP_INSN_P (insn))
1190               INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1191                                                 optimize_this_for_speed_p);
1192             if (dump_file)
1193               fprintf(dump_file, "insn_cost %d: %d\n",
1194                     INSN_UID (insn), INSN_COST (insn));
1195           }
1196     }
1197
1198   nonzero_sign_valid = 1;
1199
1200   /* Now scan all the insns in forward order.  */
1201   label_tick = label_tick_ebb_start = 1;
1202   init_reg_last ();
1203   setup_incoming_promotions (first);
1204   last_bb = ENTRY_BLOCK_PTR;
1205
1206   FOR_EACH_BB (this_basic_block)
1207     {
1208       rtx last_combined_insn = NULL_RTX;
1209       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1210       last_call_luid = 0;
1211       mem_last_set = -1;
1212
1213       label_tick++;
1214       if (!single_pred_p (this_basic_block)
1215           || single_pred (this_basic_block) != last_bb)
1216         label_tick_ebb_start = label_tick;
1217       last_bb = this_basic_block;
1218
1219       rtl_profile_for_bb (this_basic_block);
1220       for (insn = BB_HEAD (this_basic_block);
1221            insn != NEXT_INSN (BB_END (this_basic_block));
1222            insn = next ? next : NEXT_INSN (insn))
1223         {
1224           next = 0;
1225           if (NONDEBUG_INSN_P (insn))
1226             {
1227               while (last_combined_insn
1228                      && INSN_DELETED_P (last_combined_insn))
1229                 last_combined_insn = PREV_INSN (last_combined_insn);
1230               if (last_combined_insn == NULL_RTX
1231                   || BARRIER_P (last_combined_insn)
1232                   || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1233                   || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1234                 last_combined_insn = insn;
1235
1236               /* See if we know about function return values before this
1237                  insn based upon SUBREG flags.  */
1238               check_promoted_subreg (insn, PATTERN (insn));
1239
1240               /* See if we can find hardregs and subreg of pseudos in
1241                  narrower modes.  This could help turning TRUNCATEs
1242                  into SUBREGs.  */
1243               note_uses (&PATTERN (insn), record_truncated_values, NULL);
1244
1245               /* Try this insn with each insn it links back to.  */
1246
1247               FOR_EACH_LOG_LINK (links, insn)
1248                 if ((next = try_combine (insn, links->insn, NULL_RTX,
1249                                          NULL_RTX, &new_direct_jump_p,
1250                                          last_combined_insn)) != 0)
1251                   goto retry;
1252
1253               /* Try each sequence of three linked insns ending with this one.  */
1254
1255               FOR_EACH_LOG_LINK (links, insn)
1256                 {
1257                   rtx link = links->insn;
1258
1259                   /* If the linked insn has been replaced by a note, then there
1260                      is no point in pursuing this chain any further.  */
1261                   if (NOTE_P (link))
1262                     continue;
1263
1264                   FOR_EACH_LOG_LINK (nextlinks, link)
1265                     if ((next = try_combine (insn, link, nextlinks->insn,
1266                                              NULL_RTX, &new_direct_jump_p,
1267                                              last_combined_insn)) != 0)
1268                       goto retry;
1269                 }
1270
1271 #ifdef HAVE_cc0
1272               /* Try to combine a jump insn that uses CC0
1273                  with a preceding insn that sets CC0, and maybe with its
1274                  logical predecessor as well.
1275                  This is how we make decrement-and-branch insns.
1276                  We need this special code because data flow connections
1277                  via CC0 do not get entered in LOG_LINKS.  */
1278
1279               if (JUMP_P (insn)
1280                   && (prev = prev_nonnote_insn (insn)) != 0
1281                   && NONJUMP_INSN_P (prev)
1282                   && sets_cc0_p (PATTERN (prev)))
1283                 {
1284                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1285                                            &new_direct_jump_p,
1286                                            last_combined_insn)) != 0)
1287                     goto retry;
1288
1289                   FOR_EACH_LOG_LINK (nextlinks, prev)
1290                     if ((next = try_combine (insn, prev, nextlinks->insn,
1291                                              NULL_RTX, &new_direct_jump_p,
1292                                              last_combined_insn)) != 0)
1293                       goto retry;
1294                 }
1295
1296               /* Do the same for an insn that explicitly references CC0.  */
1297               if (NONJUMP_INSN_P (insn)
1298                   && (prev = prev_nonnote_insn (insn)) != 0
1299                   && NONJUMP_INSN_P (prev)
1300                   && sets_cc0_p (PATTERN (prev))
1301                   && GET_CODE (PATTERN (insn)) == SET
1302                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1303                 {
1304                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1305                                            &new_direct_jump_p,
1306                                            last_combined_insn)) != 0)
1307                     goto retry;
1308
1309                   FOR_EACH_LOG_LINK (nextlinks, prev)
1310                     if ((next = try_combine (insn, prev, nextlinks->insn,
1311                                              NULL_RTX, &new_direct_jump_p,
1312                                              last_combined_insn)) != 0)
1313                       goto retry;
1314                 }
1315
1316               /* Finally, see if any of the insns that this insn links to
1317                  explicitly references CC0.  If so, try this insn, that insn,
1318                  and its predecessor if it sets CC0.  */
1319               FOR_EACH_LOG_LINK (links, insn)
1320                 if (NONJUMP_INSN_P (links->insn)
1321                     && GET_CODE (PATTERN (links->insn)) == SET
1322                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1323                     && (prev = prev_nonnote_insn (links->insn)) != 0
1324                     && NONJUMP_INSN_P (prev)
1325                     && sets_cc0_p (PATTERN (prev))
1326                     && (next = try_combine (insn, links->insn,
1327                                             prev, NULL_RTX, &new_direct_jump_p,
1328                                             last_combined_insn)) != 0)
1329                   goto retry;
1330 #endif
1331
1332               /* Try combining an insn with two different insns whose results it
1333                  uses.  */
1334               FOR_EACH_LOG_LINK (links, insn)
1335                 for (nextlinks = links->next; nextlinks;
1336                      nextlinks = nextlinks->next)
1337                   if ((next = try_combine (insn, links->insn,
1338                                            nextlinks->insn, NULL_RTX,
1339                                            &new_direct_jump_p,
1340                                            last_combined_insn)) != 0)
1341                     goto retry;
1342
1343               /* Try four-instruction combinations.  */
1344               FOR_EACH_LOG_LINK (links, insn)
1345                 {
1346                   struct insn_link *next1;
1347                   rtx link = links->insn;
1348
1349                   /* If the linked insn has been replaced by a note, then there
1350                      is no point in pursuing this chain any further.  */
1351                   if (NOTE_P (link))
1352                     continue;
1353
1354                   FOR_EACH_LOG_LINK (next1, link)
1355                     {
1356                       rtx link1 = next1->insn;
1357                       if (NOTE_P (link1))
1358                         continue;
1359                       /* I0 -> I1 -> I2 -> I3.  */
1360                       FOR_EACH_LOG_LINK (nextlinks, link1)
1361                         if ((next = try_combine (insn, link, link1,
1362                                                  nextlinks->insn,
1363                                                  &new_direct_jump_p,
1364                                                  last_combined_insn)) != 0)
1365                           goto retry;
1366                       /* I0, I1 -> I2, I2 -> I3.  */
1367                       for (nextlinks = next1->next; nextlinks;
1368                            nextlinks = nextlinks->next)
1369                         if ((next = try_combine (insn, link, link1,
1370                                                  nextlinks->insn,
1371                                                  &new_direct_jump_p,
1372                                                  last_combined_insn)) != 0)
1373                           goto retry;
1374                     }
1375
1376                   for (next1 = links->next; next1; next1 = next1->next)
1377                     {
1378                       rtx link1 = next1->insn;
1379                       if (NOTE_P (link1))
1380                         continue;
1381                       /* I0 -> I2; I1, I2 -> I3.  */
1382                       FOR_EACH_LOG_LINK (nextlinks, link)
1383                         if ((next = try_combine (insn, link, link1,
1384                                                  nextlinks->insn,
1385                                                  &new_direct_jump_p,
1386                                                  last_combined_insn)) != 0)
1387                           goto retry;
1388                       /* I0 -> I1; I1, I2 -> I3.  */
1389                       FOR_EACH_LOG_LINK (nextlinks, link1)
1390                         if ((next = try_combine (insn, link, link1,
1391                                                  nextlinks->insn,
1392                                                  &new_direct_jump_p,
1393                                                  last_combined_insn)) != 0)
1394                           goto retry;
1395                     }
1396                 }
1397
1398               /* Try this insn with each REG_EQUAL note it links back to.  */
1399               FOR_EACH_LOG_LINK (links, insn)
1400                 {
1401                   rtx set, note;
1402                   rtx temp = links->insn;
1403                   if ((set = single_set (temp)) != 0
1404                       && (note = find_reg_equal_equiv_note (temp)) != 0
1405                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1406                       /* Avoid using a register that may already been marked
1407                          dead by an earlier instruction.  */
1408                       && ! unmentioned_reg_p (note, SET_SRC (set))
1409                       && (GET_MODE (note) == VOIDmode
1410                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1411                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1412                     {
1413                       /* Temporarily replace the set's source with the
1414                          contents of the REG_EQUAL note.  The insn will
1415                          be deleted or recognized by try_combine.  */
1416                       rtx orig = SET_SRC (set);
1417                       SET_SRC (set) = note;
1418                       i2mod = temp;
1419                       i2mod_old_rhs = copy_rtx (orig);
1420                       i2mod_new_rhs = copy_rtx (note);
1421                       next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1422                                           &new_direct_jump_p,
1423                                           last_combined_insn);
1424                       i2mod = NULL_RTX;
1425                       if (next)
1426                         goto retry;
1427                       SET_SRC (set) = orig;
1428                     }
1429                 }
1430
1431               if (!NOTE_P (insn))
1432                 record_dead_and_set_regs (insn);
1433
1434             retry:
1435               ;
1436             }
1437         }
1438     }
1439
1440   default_rtl_profile ();
1441   clear_bb_flags ();
1442   new_direct_jump_p |= purge_all_dead_edges ();
1443   delete_noop_moves ();
1444
1445   /* Clean up.  */
1446   obstack_free (&insn_link_obstack, NULL);
1447   free (uid_log_links);
1448   free (uid_insn_cost);
1449   VEC_free (reg_stat_type, heap, reg_stat);
1450
1451   {
1452     struct undo *undo, *next;
1453     for (undo = undobuf.frees; undo; undo = next)
1454       {
1455         next = undo->next;
1456         free (undo);
1457       }
1458     undobuf.frees = 0;
1459   }
1460
1461   total_attempts += combine_attempts;
1462   total_merges += combine_merges;
1463   total_extras += combine_extras;
1464   total_successes += combine_successes;
1465
1466   nonzero_sign_valid = 0;
1467   rtl_hooks = general_rtl_hooks;
1468
1469   /* Make recognizer allow volatile MEMs again.  */
1470   init_recog ();
1471
1472   return new_direct_jump_p;
1473 }
1474
1475 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1476
1477 static void
1478 init_reg_last (void)
1479 {
1480   unsigned int i;
1481   reg_stat_type *p;
1482
1483   FOR_EACH_VEC_ELT (reg_stat_type, reg_stat, i, p)
1484     memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1485 }
1486 \f
1487 /* Set up any promoted values for incoming argument registers.  */
1488
1489 static void
1490 setup_incoming_promotions (rtx first)
1491 {
1492   tree arg;
1493   bool strictly_local = false;
1494
1495   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1496        arg = DECL_CHAIN (arg))
1497     {
1498       rtx x, reg = DECL_INCOMING_RTL (arg);
1499       int uns1, uns3;
1500       enum machine_mode mode1, mode2, mode3, mode4;
1501
1502       /* Only continue if the incoming argument is in a register.  */
1503       if (!REG_P (reg))
1504         continue;
1505
1506       /* Determine, if possible, whether all call sites of the current
1507          function lie within the current compilation unit.  (This does
1508          take into account the exporting of a function via taking its
1509          address, and so forth.)  */
1510       strictly_local = cgraph_local_info (current_function_decl)->local;
1511
1512       /* The mode and signedness of the argument before any promotions happen
1513          (equal to the mode of the pseudo holding it at that stage).  */
1514       mode1 = TYPE_MODE (TREE_TYPE (arg));
1515       uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1516
1517       /* The mode and signedness of the argument after any source language and
1518          TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
1519       mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1520       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1521
1522       /* The mode and signedness of the argument as it is actually passed,
1523          after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
1524       mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1525                                      TREE_TYPE (cfun->decl), 0);
1526
1527       /* The mode of the register in which the argument is being passed.  */
1528       mode4 = GET_MODE (reg);
1529
1530       /* Eliminate sign extensions in the callee when:
1531          (a) A mode promotion has occurred;  */
1532       if (mode1 == mode3)
1533         continue;
1534       /* (b) The mode of the register is the same as the mode of
1535              the argument as it is passed; */
1536       if (mode3 != mode4)
1537         continue;
1538       /* (c) There's no language level extension;  */
1539       if (mode1 == mode2)
1540         ;
1541       /* (c.1) All callers are from the current compilation unit.  If that's
1542          the case we don't have to rely on an ABI, we only have to know
1543          what we're generating right now, and we know that we will do the
1544          mode1 to mode2 promotion with the given sign.  */
1545       else if (!strictly_local)
1546         continue;
1547       /* (c.2) The combination of the two promotions is useful.  This is
1548          true when the signs match, or if the first promotion is unsigned.
1549          In the later case, (sign_extend (zero_extend x)) is the same as
1550          (zero_extend (zero_extend x)), so make sure to force UNS3 true.  */
1551       else if (uns1)
1552         uns3 = true;
1553       else if (uns3)
1554         continue;
1555
1556       /* Record that the value was promoted from mode1 to mode3,
1557          so that any sign extension at the head of the current
1558          function may be eliminated.  */
1559       x = gen_rtx_CLOBBER (mode1, const0_rtx);
1560       x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1561       record_value_for_reg (reg, first, x);
1562     }
1563 }
1564
1565 /* Called via note_stores.  If X is a pseudo that is narrower than
1566    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1567
1568    If we are setting only a portion of X and we can't figure out what
1569    portion, assume all bits will be used since we don't know what will
1570    be happening.
1571
1572    Similarly, set how many bits of X are known to be copies of the sign bit
1573    at all locations in the function.  This is the smallest number implied
1574    by any set of X.  */
1575
1576 static void
1577 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1578 {
1579   rtx insn = (rtx) data;
1580   unsigned int num;
1581
1582   if (REG_P (x)
1583       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1584       /* If this register is undefined at the start of the file, we can't
1585          say what its contents were.  */
1586       && ! REGNO_REG_SET_P
1587            (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1588       && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1589     {
1590       reg_stat_type *rsp = &VEC_index (reg_stat_type, reg_stat, REGNO (x));
1591
1592       if (set == 0 || GET_CODE (set) == CLOBBER)
1593         {
1594           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1595           rsp->sign_bit_copies = 1;
1596           return;
1597         }
1598
1599       /* If this register is being initialized using itself, and the
1600          register is uninitialized in this basic block, and there are
1601          no LOG_LINKS which set the register, then part of the
1602          register is uninitialized.  In that case we can't assume
1603          anything about the number of nonzero bits.
1604
1605          ??? We could do better if we checked this in
1606          reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
1607          could avoid making assumptions about the insn which initially
1608          sets the register, while still using the information in other
1609          insns.  We would have to be careful to check every insn
1610          involved in the combination.  */
1611
1612       if (insn
1613           && reg_referenced_p (x, PATTERN (insn))
1614           && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1615                                REGNO (x)))
1616         {
1617           struct insn_link *link;
1618
1619           FOR_EACH_LOG_LINK (link, insn)
1620             if (dead_or_set_p (link->insn, x))
1621               break;
1622           if (!link)
1623             {
1624               rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1625               rsp->sign_bit_copies = 1;
1626               return;
1627             }
1628         }
1629
1630       /* If this is a complex assignment, see if we can convert it into a
1631          simple assignment.  */
1632       set = expand_field_assignment (set);
1633
1634       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1635          set what we know about X.  */
1636
1637       if (SET_DEST (set) == x
1638           || (paradoxical_subreg_p (SET_DEST (set))
1639               && SUBREG_REG (SET_DEST (set)) == x))
1640         {
1641           rtx src = SET_SRC (set);
1642
1643 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1644           /* If X is narrower than a word and SRC is a non-negative
1645              constant that would appear negative in the mode of X,
1646              sign-extend it for use in reg_stat[].nonzero_bits because some
1647              machines (maybe most) will actually do the sign-extension
1648              and this is the conservative approach.
1649
1650              ??? For 2.5, try to tighten up the MD files in this regard
1651              instead of this kludge.  */
1652
1653           if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1654               && CONST_INT_P (src)
1655               && INTVAL (src) > 0
1656               && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1657             src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1658 #endif
1659
1660           /* Don't call nonzero_bits if it cannot change anything.  */
1661           if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1662             rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1663           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1664           if (rsp->sign_bit_copies == 0
1665               || rsp->sign_bit_copies > num)
1666             rsp->sign_bit_copies = num;
1667         }
1668       else
1669         {
1670           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1671           rsp->sign_bit_copies = 1;
1672         }
1673     }
1674 }
1675 \f
1676 /* See if INSN can be combined into I3.  PRED, PRED2, SUCC and SUCC2 are
1677    optionally insns that were previously combined into I3 or that will be
1678    combined into the merger of INSN and I3.  The order is PRED, PRED2,
1679    INSN, SUCC, SUCC2, I3.
1680
1681    Return 0 if the combination is not allowed for any reason.
1682
1683    If the combination is allowed, *PDEST will be set to the single
1684    destination of INSN and *PSRC to the single source, and this function
1685    will return 1.  */
1686
1687 static int
1688 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1689                rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1690                rtx *pdest, rtx *psrc)
1691 {
1692   int i;
1693   const_rtx set = 0;
1694   rtx src, dest;
1695   rtx p;
1696 #ifdef AUTO_INC_DEC
1697   rtx link;
1698 #endif
1699   bool all_adjacent = true;
1700   int (*is_volatile_p) (const_rtx);
1701
1702   if (succ)
1703     {
1704       if (succ2)
1705         {
1706           if (next_active_insn (succ2) != i3)
1707             all_adjacent = false;
1708           if (next_active_insn (succ) != succ2)
1709             all_adjacent = false;
1710         }
1711       else if (next_active_insn (succ) != i3)
1712         all_adjacent = false;
1713       if (next_active_insn (insn) != succ)
1714         all_adjacent = false;
1715     }
1716   else if (next_active_insn (insn) != i3)
1717     all_adjacent = false;
1718
1719   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1720      or a PARALLEL consisting of such a SET and CLOBBERs.
1721
1722      If INSN has CLOBBER parallel parts, ignore them for our processing.
1723      By definition, these happen during the execution of the insn.  When it
1724      is merged with another insn, all bets are off.  If they are, in fact,
1725      needed and aren't also supplied in I3, they may be added by
1726      recog_for_combine.  Otherwise, it won't match.
1727
1728      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1729      note.
1730
1731      Get the source and destination of INSN.  If more than one, can't
1732      combine.  */
1733
1734   if (GET_CODE (PATTERN (insn)) == SET)
1735     set = PATTERN (insn);
1736   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1737            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1738     {
1739       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1740         {
1741           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1742
1743           switch (GET_CODE (elt))
1744             {
1745             /* This is important to combine floating point insns
1746                for the SH4 port.  */
1747             case USE:
1748               /* Combining an isolated USE doesn't make sense.
1749                  We depend here on combinable_i3pat to reject them.  */
1750               /* The code below this loop only verifies that the inputs of
1751                  the SET in INSN do not change.  We call reg_set_between_p
1752                  to verify that the REG in the USE does not change between
1753                  I3 and INSN.
1754                  If the USE in INSN was for a pseudo register, the matching
1755                  insn pattern will likely match any register; combining this
1756                  with any other USE would only be safe if we knew that the
1757                  used registers have identical values, or if there was
1758                  something to tell them apart, e.g. different modes.  For
1759                  now, we forgo such complicated tests and simply disallow
1760                  combining of USES of pseudo registers with any other USE.  */
1761               if (REG_P (XEXP (elt, 0))
1762                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1763                 {
1764                   rtx i3pat = PATTERN (i3);
1765                   int i = XVECLEN (i3pat, 0) - 1;
1766                   unsigned int regno = REGNO (XEXP (elt, 0));
1767
1768                   do
1769                     {
1770                       rtx i3elt = XVECEXP (i3pat, 0, i);
1771
1772                       if (GET_CODE (i3elt) == USE
1773                           && REG_P (XEXP (i3elt, 0))
1774                           && (REGNO (XEXP (i3elt, 0)) == regno
1775                               ? reg_set_between_p (XEXP (elt, 0),
1776                                                    PREV_INSN (insn), i3)
1777                               : regno >= FIRST_PSEUDO_REGISTER))
1778                         return 0;
1779                     }
1780                   while (--i >= 0);
1781                 }
1782               break;
1783
1784               /* We can ignore CLOBBERs.  */
1785             case CLOBBER:
1786               break;
1787
1788             case SET:
1789               /* Ignore SETs whose result isn't used but not those that
1790                  have side-effects.  */
1791               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1792                   && insn_nothrow_p (insn)
1793                   && !side_effects_p (elt))
1794                 break;
1795
1796               /* If we have already found a SET, this is a second one and
1797                  so we cannot combine with this insn.  */
1798               if (set)
1799                 return 0;
1800
1801               set = elt;
1802               break;
1803
1804             default:
1805               /* Anything else means we can't combine.  */
1806               return 0;
1807             }
1808         }
1809
1810       if (set == 0
1811           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1812              so don't do anything with it.  */
1813           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1814         return 0;
1815     }
1816   else
1817     return 0;
1818
1819   if (set == 0)
1820     return 0;
1821
1822   /* The simplification in expand_field_assignment may call back to
1823      get_last_value, so set safe guard here.  */
1824   subst_low_luid = DF_INSN_LUID (insn);
1825
1826   set = expand_field_assignment (set);
1827   src = SET_SRC (set), dest = SET_DEST (set);
1828
1829   /* Don't eliminate a store in the stack pointer.  */
1830   if (dest == stack_pointer_rtx
1831       /* Don't combine with an insn that sets a register to itself if it has
1832          a REG_EQUAL note.  This may be part of a LIBCALL sequence.  */
1833       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1834       /* Can't merge an ASM_OPERANDS.  */
1835       || GET_CODE (src) == ASM_OPERANDS
1836       /* Can't merge a function call.  */
1837       || GET_CODE (src) == CALL
1838       /* Don't eliminate a function call argument.  */
1839       || (CALL_P (i3)
1840           && (find_reg_fusage (i3, USE, dest)
1841               || (REG_P (dest)
1842                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1843                   && global_regs[REGNO (dest)])))
1844       /* Don't substitute into an incremented register.  */
1845       || FIND_REG_INC_NOTE (i3, dest)
1846       || (succ && FIND_REG_INC_NOTE (succ, dest))
1847       || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1848       /* Don't substitute into a non-local goto, this confuses CFG.  */
1849       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1850       /* Make sure that DEST is not used after SUCC but before I3.  */
1851       || (!all_adjacent
1852           && ((succ2
1853                && (reg_used_between_p (dest, succ2, i3)
1854                    || reg_used_between_p (dest, succ, succ2)))
1855               || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1856       /* Make sure that the value that is to be substituted for the register
1857          does not use any registers whose values alter in between.  However,
1858          If the insns are adjacent, a use can't cross a set even though we
1859          think it might (this can happen for a sequence of insns each setting
1860          the same destination; last_set of that register might point to
1861          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1862          equivalent to the memory so the substitution is valid even if there
1863          are intervening stores.  Also, don't move a volatile asm or
1864          UNSPEC_VOLATILE across any other insns.  */
1865       || (! all_adjacent
1866           && (((!MEM_P (src)
1867                 || ! find_reg_note (insn, REG_EQUIV, src))
1868                && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1869               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1870               || GET_CODE (src) == UNSPEC_VOLATILE))
1871       /* Don't combine across a CALL_INSN, because that would possibly
1872          change whether the life span of some REGs crosses calls or not,
1873          and it is a pain to update that information.
1874          Exception: if source is a constant, moving it later can't hurt.
1875          Accept that as a special case.  */
1876       || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1877     return 0;
1878
1879   /* DEST must either be a REG or CC0.  */
1880   if (REG_P (dest))
1881     {
1882       /* If register alignment is being enforced for multi-word items in all
1883          cases except for parameters, it is possible to have a register copy
1884          insn referencing a hard register that is not allowed to contain the
1885          mode being copied and which would not be valid as an operand of most
1886          insns.  Eliminate this problem by not combining with such an insn.
1887
1888          Also, on some machines we don't want to extend the life of a hard
1889          register.  */
1890
1891       if (REG_P (src)
1892           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1893                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1894               /* Don't extend the life of a hard register unless it is
1895                  user variable (if we have few registers) or it can't
1896                  fit into the desired register (meaning something special
1897                  is going on).
1898                  Also avoid substituting a return register into I3, because
1899                  reload can't handle a conflict with constraints of other
1900                  inputs.  */
1901               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1902                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1903         return 0;
1904     }
1905   else if (GET_CODE (dest) != CC0)
1906     return 0;
1907
1908
1909   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1910     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1911       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1912         {
1913           /* Don't substitute for a register intended as a clobberable
1914              operand.  */
1915           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1916           if (rtx_equal_p (reg, dest))
1917             return 0;
1918
1919           /* If the clobber represents an earlyclobber operand, we must not
1920              substitute an expression containing the clobbered register.
1921              As we do not analyze the constraint strings here, we have to
1922              make the conservative assumption.  However, if the register is
1923              a fixed hard reg, the clobber cannot represent any operand;
1924              we leave it up to the machine description to either accept or
1925              reject use-and-clobber patterns.  */
1926           if (!REG_P (reg)
1927               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1928               || !fixed_regs[REGNO (reg)])
1929             if (reg_overlap_mentioned_p (reg, src))
1930               return 0;
1931         }
1932
1933   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1934      or not), reject, unless nothing volatile comes between it and I3 */
1935
1936   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1937     {
1938       /* Make sure neither succ nor succ2 contains a volatile reference.  */
1939       if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1940         return 0;
1941       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1942         return 0;
1943       /* We'll check insns between INSN and I3 below.  */
1944     }
1945
1946   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1947      to be an explicit register variable, and was chosen for a reason.  */
1948
1949   if (GET_CODE (src) == ASM_OPERANDS
1950       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1951     return 0;
1952
1953   /* If INSN contains volatile references (specifically volatile MEMs),
1954      we cannot combine across any other volatile references.
1955      Even if INSN doesn't contain volatile references, any intervening
1956      volatile insn might affect machine state.  */
1957
1958   is_volatile_p = volatile_refs_p (PATTERN (insn))
1959     ? volatile_refs_p
1960     : volatile_insn_p;
1961
1962   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1963     if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
1964       return 0;
1965
1966   /* If INSN contains an autoincrement or autodecrement, make sure that
1967      register is not used between there and I3, and not already used in
1968      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1969      Also insist that I3 not be a jump; if it were one
1970      and the incremented register were spilled, we would lose.  */
1971
1972 #ifdef AUTO_INC_DEC
1973   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1974     if (REG_NOTE_KIND (link) == REG_INC
1975         && (JUMP_P (i3)
1976             || reg_used_between_p (XEXP (link, 0), insn, i3)
1977             || (pred != NULL_RTX
1978                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1979             || (pred2 != NULL_RTX
1980                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1981             || (succ != NULL_RTX
1982                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1983             || (succ2 != NULL_RTX
1984                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1985             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1986       return 0;
1987 #endif
1988
1989 #ifdef HAVE_cc0
1990   /* Don't combine an insn that follows a CC0-setting insn.
1991      An insn that uses CC0 must not be separated from the one that sets it.
1992      We do, however, allow I2 to follow a CC0-setting insn if that insn
1993      is passed as I1; in that case it will be deleted also.
1994      We also allow combining in this case if all the insns are adjacent
1995      because that would leave the two CC0 insns adjacent as well.
1996      It would be more logical to test whether CC0 occurs inside I1 or I2,
1997      but that would be much slower, and this ought to be equivalent.  */
1998
1999   p = prev_nonnote_insn (insn);
2000   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2001       && ! all_adjacent)
2002     return 0;
2003 #endif
2004
2005   /* If we get here, we have passed all the tests and the combination is
2006      to be allowed.  */
2007
2008   *pdest = dest;
2009   *psrc = src;
2010
2011   return 1;
2012 }
2013 \f
2014 /* LOC is the location within I3 that contains its pattern or the component
2015    of a PARALLEL of the pattern.  We validate that it is valid for combining.
2016
2017    One problem is if I3 modifies its output, as opposed to replacing it
2018    entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2019    doing so would produce an insn that is not equivalent to the original insns.
2020
2021    Consider:
2022
2023          (set (reg:DI 101) (reg:DI 100))
2024          (set (subreg:SI (reg:DI 101) 0) <foo>)
2025
2026    This is NOT equivalent to:
2027
2028          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2029                     (set (reg:DI 101) (reg:DI 100))])
2030
2031    Not only does this modify 100 (in which case it might still be valid
2032    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2033
2034    We can also run into a problem if I2 sets a register that I1
2035    uses and I1 gets directly substituted into I3 (not via I2).  In that
2036    case, we would be getting the wrong value of I2DEST into I3, so we
2037    must reject the combination.  This case occurs when I2 and I1 both
2038    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2039    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2040    of a SET must prevent combination from occurring.  The same situation
2041    can occur for I0, in which case I0_NOT_IN_SRC is set.
2042
2043    Before doing the above check, we first try to expand a field assignment
2044    into a set of logical operations.
2045
2046    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2047    we place a register that is both set and used within I3.  If more than one
2048    such register is detected, we fail.
2049
2050    Return 1 if the combination is valid, zero otherwise.  */
2051
2052 static int
2053 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2054                   int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2055 {
2056   rtx x = *loc;
2057
2058   if (GET_CODE (x) == SET)
2059     {
2060       rtx set = x ;
2061       rtx dest = SET_DEST (set);
2062       rtx src = SET_SRC (set);
2063       rtx inner_dest = dest;
2064       rtx subdest;
2065
2066       while (GET_CODE (inner_dest) == STRICT_LOW_PART
2067              || GET_CODE (inner_dest) == SUBREG
2068              || GET_CODE (inner_dest) == ZERO_EXTRACT)
2069         inner_dest = XEXP (inner_dest, 0);
2070
2071       /* Check for the case where I3 modifies its output, as discussed
2072          above.  We don't want to prevent pseudos from being combined
2073          into the address of a MEM, so only prevent the combination if
2074          i1 or i2 set the same MEM.  */
2075       if ((inner_dest != dest &&
2076            (!MEM_P (inner_dest)
2077             || rtx_equal_p (i2dest, inner_dest)
2078             || (i1dest && rtx_equal_p (i1dest, inner_dest))
2079             || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2080            && (reg_overlap_mentioned_p (i2dest, inner_dest)
2081                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2082                || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2083
2084           /* This is the same test done in can_combine_p except we can't test
2085              all_adjacent; we don't have to, since this instruction will stay
2086              in place, thus we are not considering increasing the lifetime of
2087              INNER_DEST.
2088
2089              Also, if this insn sets a function argument, combining it with
2090              something that might need a spill could clobber a previous
2091              function argument; the all_adjacent test in can_combine_p also
2092              checks this; here, we do a more specific test for this case.  */
2093
2094           || (REG_P (inner_dest)
2095               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2096               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2097                                         GET_MODE (inner_dest))))
2098           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2099           || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2100         return 0;
2101
2102       /* If DEST is used in I3, it is being killed in this insn, so
2103          record that for later.  We have to consider paradoxical
2104          subregs here, since they kill the whole register, but we
2105          ignore partial subregs, STRICT_LOW_PART, etc.
2106          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2107          STACK_POINTER_REGNUM, since these are always considered to be
2108          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
2109       subdest = dest;
2110       if (GET_CODE (subdest) == SUBREG
2111           && (GET_MODE_SIZE (GET_MODE (subdest))
2112               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2113         subdest = SUBREG_REG (subdest);
2114       if (pi3dest_killed
2115           && REG_P (subdest)
2116           && reg_referenced_p (subdest, PATTERN (i3))
2117           && REGNO (subdest) != FRAME_POINTER_REGNUM
2118 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2119           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2120 #endif
2121 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2122           && (REGNO (subdest) != ARG_POINTER_REGNUM
2123               || ! fixed_regs [REGNO (subdest)])
2124 #endif
2125           && REGNO (subdest) != STACK_POINTER_REGNUM)
2126         {
2127           if (*pi3dest_killed)
2128             return 0;
2129
2130           *pi3dest_killed = subdest;
2131         }
2132     }
2133
2134   else if (GET_CODE (x) == PARALLEL)
2135     {
2136       int i;
2137
2138       for (i = 0; i < XVECLEN (x, 0); i++)
2139         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2140                                 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2141           return 0;
2142     }
2143
2144   return 1;
2145 }
2146 \f
2147 /* Return 1 if X is an arithmetic expression that contains a multiplication
2148    and division.  We don't count multiplications by powers of two here.  */
2149
2150 static int
2151 contains_muldiv (rtx x)
2152 {
2153   switch (GET_CODE (x))
2154     {
2155     case MOD:  case DIV:  case UMOD:  case UDIV:
2156       return 1;
2157
2158     case MULT:
2159       return ! (CONST_INT_P (XEXP (x, 1))
2160                 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2161     default:
2162       if (BINARY_P (x))
2163         return contains_muldiv (XEXP (x, 0))
2164             || contains_muldiv (XEXP (x, 1));
2165
2166       if (UNARY_P (x))
2167         return contains_muldiv (XEXP (x, 0));
2168
2169       return 0;
2170     }
2171 }
2172 \f
2173 /* Determine whether INSN can be used in a combination.  Return nonzero if
2174    not.  This is used in try_combine to detect early some cases where we
2175    can't perform combinations.  */
2176
2177 static int
2178 cant_combine_insn_p (rtx insn)
2179 {
2180   rtx set;
2181   rtx src, dest;
2182
2183   /* If this isn't really an insn, we can't do anything.
2184      This can occur when flow deletes an insn that it has merged into an
2185      auto-increment address.  */
2186   if (! INSN_P (insn))
2187     return 1;
2188
2189   /* Never combine loads and stores involving hard regs that are likely
2190      to be spilled.  The register allocator can usually handle such
2191      reg-reg moves by tying.  If we allow the combiner to make
2192      substitutions of likely-spilled regs, reload might die.
2193      As an exception, we allow combinations involving fixed regs; these are
2194      not available to the register allocator so there's no risk involved.  */
2195
2196   set = single_set (insn);
2197   if (! set)
2198     return 0;
2199   src = SET_SRC (set);
2200   dest = SET_DEST (set);
2201   if (GET_CODE (src) == SUBREG)
2202     src = SUBREG_REG (src);
2203   if (GET_CODE (dest) == SUBREG)
2204     dest = SUBREG_REG (dest);
2205   if (REG_P (src) && REG_P (dest)
2206       && ((HARD_REGISTER_P (src)
2207            && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2208            && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2209           || (HARD_REGISTER_P (dest)
2210               && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2211               && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2212     return 1;
2213
2214   return 0;
2215 }
2216
2217 struct likely_spilled_retval_info
2218 {
2219   unsigned regno, nregs;
2220   unsigned mask;
2221 };
2222
2223 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
2224    hard registers that are known to be written to / clobbered in full.  */
2225 static void
2226 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2227 {
2228   struct likely_spilled_retval_info *const info =
2229     (struct likely_spilled_retval_info *) data;
2230   unsigned regno, nregs;
2231   unsigned new_mask;
2232
2233   if (!REG_P (XEXP (set, 0)))
2234     return;
2235   regno = REGNO (x);
2236   if (regno >= info->regno + info->nregs)
2237     return;
2238   nregs = hard_regno_nregs[regno][GET_MODE (x)];
2239   if (regno + nregs <= info->regno)
2240     return;
2241   new_mask = (2U << (nregs - 1)) - 1;
2242   if (regno < info->regno)
2243     new_mask >>= info->regno - regno;
2244   else
2245     new_mask <<= regno - info->regno;
2246   info->mask &= ~new_mask;
2247 }
2248
2249 /* Return nonzero iff part of the return value is live during INSN, and
2250    it is likely spilled.  This can happen when more than one insn is needed
2251    to copy the return value, e.g. when we consider to combine into the
2252    second copy insn for a complex value.  */
2253
2254 static int
2255 likely_spilled_retval_p (rtx insn)
2256 {
2257   rtx use = BB_END (this_basic_block);
2258   rtx reg, p;
2259   unsigned regno, nregs;
2260   /* We assume here that no machine mode needs more than
2261      32 hard registers when the value overlaps with a register
2262      for which TARGET_FUNCTION_VALUE_REGNO_P is true.  */
2263   unsigned mask;
2264   struct likely_spilled_retval_info info;
2265
2266   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2267     return 0;
2268   reg = XEXP (PATTERN (use), 0);
2269   if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2270     return 0;
2271   regno = REGNO (reg);
2272   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2273   if (nregs == 1)
2274     return 0;
2275   mask = (2U << (nregs - 1)) - 1;
2276
2277   /* Disregard parts of the return value that are set later.  */
2278   info.regno = regno;
2279   info.nregs = nregs;
2280   info.mask = mask;
2281   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2282     if (INSN_P (p))
2283       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2284   mask = info.mask;
2285
2286   /* Check if any of the (probably) live return value registers is
2287      likely spilled.  */
2288   nregs --;
2289   do
2290     {
2291       if ((mask & 1 << nregs)
2292           && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2293         return 1;
2294     } while (nregs--);
2295   return 0;
2296 }
2297
2298 /* Adjust INSN after we made a change to its destination.
2299
2300    Changing the destination can invalidate notes that say something about
2301    the results of the insn and a LOG_LINK pointing to the insn.  */
2302
2303 static void
2304 adjust_for_new_dest (rtx insn)
2305 {
2306   /* For notes, be conservative and simply remove them.  */
2307   remove_reg_equal_equiv_notes (insn);
2308
2309   /* The new insn will have a destination that was previously the destination
2310      of an insn just above it.  Call distribute_links to make a LOG_LINK from
2311      the next use of that destination.  */
2312   distribute_links (alloc_insn_link (insn, NULL));
2313
2314   df_insn_rescan (insn);
2315 }
2316
2317 /* Return TRUE if combine can reuse reg X in mode MODE.
2318    ADDED_SETS is nonzero if the original set is still required.  */
2319 static bool
2320 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2321 {
2322   unsigned int regno;
2323
2324   if (!REG_P(x))
2325     return false;
2326
2327   regno = REGNO (x);
2328   /* Allow hard registers if the new mode is legal, and occupies no more
2329      registers than the old mode.  */
2330   if (regno < FIRST_PSEUDO_REGISTER)
2331     return (HARD_REGNO_MODE_OK (regno, mode)
2332             && (hard_regno_nregs[regno][GET_MODE (x)]
2333                 >= hard_regno_nregs[regno][mode]));
2334
2335   /* Or a pseudo that is only used once.  */
2336   return (REG_N_SETS (regno) == 1 && !added_sets
2337           && !REG_USERVAR_P (x));
2338 }
2339
2340
2341 /* Check whether X, the destination of a set, refers to part of
2342    the register specified by REG.  */
2343
2344 static bool
2345 reg_subword_p (rtx x, rtx reg)
2346 {
2347   /* Check that reg is an integer mode register.  */
2348   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2349     return false;
2350
2351   if (GET_CODE (x) == STRICT_LOW_PART
2352       || GET_CODE (x) == ZERO_EXTRACT)
2353     x = XEXP (x, 0);
2354
2355   return GET_CODE (x) == SUBREG
2356          && SUBREG_REG (x) == reg
2357          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2358 }
2359
2360 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2361    Note that the INSN should be deleted *after* removing dead edges, so
2362    that the kept edge is the fallthrough edge for a (set (pc) (pc))
2363    but not for a (set (pc) (label_ref FOO)).  */
2364
2365 static void
2366 update_cfg_for_uncondjump (rtx insn)
2367 {
2368   basic_block bb = BLOCK_FOR_INSN (insn);
2369   gcc_assert (BB_END (bb) == insn);
2370
2371   purge_dead_edges (bb);
2372
2373   delete_insn (insn);
2374   if (EDGE_COUNT (bb->succs) == 1)
2375     {
2376       rtx insn;
2377
2378       single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2379
2380       /* Remove barriers from the footer if there are any.  */
2381       for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn))
2382         if (BARRIER_P (insn))
2383           {
2384             if (PREV_INSN (insn))
2385               NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2386             else
2387               BB_FOOTER (bb) = NEXT_INSN (insn);
2388             if (NEXT_INSN (insn))
2389               PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2390           }
2391         else if (LABEL_P (insn))
2392           break;
2393     }
2394 }
2395
2396 /* Try to combine the insns I0, I1 and I2 into I3.
2397    Here I0, I1 and I2 appear earlier than I3.
2398    I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2399    I3.
2400
2401    If we are combining more than two insns and the resulting insn is not
2402    recognized, try splitting it into two insns.  If that happens, I2 and I3
2403    are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2404    Otherwise, I0, I1 and I2 are pseudo-deleted.
2405
2406    Return 0 if the combination does not work.  Then nothing is changed.
2407    If we did the combination, return the insn at which combine should
2408    resume scanning.
2409
2410    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2411    new direct jump instruction.
2412
2413    LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2414    been I3 passed to an earlier try_combine within the same basic
2415    block.  */
2416
2417 static rtx
2418 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2419              rtx last_combined_insn)
2420 {
2421   /* New patterns for I3 and I2, respectively.  */
2422   rtx newpat, newi2pat = 0;
2423   rtvec newpat_vec_with_clobbers = 0;
2424   int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2425   /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2426      dead.  */
2427   int added_sets_0, added_sets_1, added_sets_2;
2428   /* Total number of SETs to put into I3.  */
2429   int total_sets;
2430   /* Nonzero if I2's or I1's body now appears in I3.  */
2431   int i2_is_used = 0, i1_is_used = 0;
2432   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
2433   int insn_code_number, i2_code_number = 0, other_code_number = 0;
2434   /* Contains I3 if the destination of I3 is used in its source, which means
2435      that the old life of I3 is being killed.  If that usage is placed into
2436      I2 and not in I3, a REG_DEAD note must be made.  */
2437   rtx i3dest_killed = 0;
2438   /* SET_DEST and SET_SRC of I2, I1 and I0.  */
2439   rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2440   /* Copy of SET_SRC of I1 and I0, if needed.  */
2441   rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2442   /* Set if I2DEST was reused as a scratch register.  */
2443   bool i2scratch = false;
2444   /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases.  */
2445   rtx i0pat = 0, i1pat = 0, i2pat = 0;
2446   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
2447   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2448   int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2449   int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2450   int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2451   /* Notes that must be added to REG_NOTES in I3 and I2.  */
2452   rtx new_i3_notes, new_i2_notes;
2453   /* Notes that we substituted I3 into I2 instead of the normal case.  */
2454   int i3_subst_into_i2 = 0;
2455   /* Notes that I1, I2 or I3 is a MULT operation.  */
2456   int have_mult = 0;
2457   int swap_i2i3 = 0;
2458   int changed_i3_dest = 0;
2459
2460   int maxreg;
2461   rtx temp;
2462   struct insn_link *link;
2463   rtx other_pat = 0;
2464   rtx new_other_notes;
2465   int i;
2466
2467   /* Only try four-insn combinations when there's high likelihood of
2468      success.  Look for simple insns, such as loads of constants or
2469      binary operations involving a constant.  */
2470   if (i0)
2471     {
2472       int i;
2473       int ngood = 0;
2474       int nshift = 0;
2475
2476       if (!flag_expensive_optimizations)
2477         return 0;
2478
2479       for (i = 0; i < 4; i++)
2480         {
2481           rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2482           rtx set = single_set (insn);
2483           rtx src;
2484           if (!set)
2485             continue;
2486           src = SET_SRC (set);
2487           if (CONSTANT_P (src))
2488             {
2489               ngood += 2;
2490               break;
2491             }
2492           else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2493             ngood++;
2494           else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2495                    || GET_CODE (src) == LSHIFTRT)
2496             nshift++;
2497         }
2498       if (ngood < 2 && nshift < 2)
2499         return 0;
2500     }
2501
2502   /* Exit early if one of the insns involved can't be used for
2503      combinations.  */
2504   if (cant_combine_insn_p (i3)
2505       || cant_combine_insn_p (i2)
2506       || (i1 && cant_combine_insn_p (i1))
2507       || (i0 && cant_combine_insn_p (i0))
2508       || likely_spilled_retval_p (i3))
2509     return 0;
2510
2511   combine_attempts++;
2512   undobuf.other_insn = 0;
2513
2514   /* Reset the hard register usage information.  */
2515   CLEAR_HARD_REG_SET (newpat_used_regs);
2516
2517   if (dump_file && (dump_flags & TDF_DETAILS))
2518     {
2519       if (i0)
2520         fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2521                  INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2522       else if (i1)
2523         fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2524                  INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2525       else
2526         fprintf (dump_file, "\nTrying %d -> %d:\n",
2527                  INSN_UID (i2), INSN_UID (i3));
2528     }
2529
2530   /* If multiple insns feed into one of I2 or I3, they can be in any
2531      order.  To simplify the code below, reorder them in sequence.  */
2532   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2533     temp = i2, i2 = i0, i0 = temp;
2534   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2535     temp = i1, i1 = i0, i0 = temp;
2536   if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2537     temp = i1, i1 = i2, i2 = temp;
2538
2539   added_links_insn = 0;
2540
2541   /* First check for one important special case that the code below will
2542      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
2543      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
2544      we may be able to replace that destination with the destination of I3.
2545      This occurs in the common code where we compute both a quotient and
2546      remainder into a structure, in which case we want to do the computation
2547      directly into the structure to avoid register-register copies.
2548
2549      Note that this case handles both multiple sets in I2 and also cases
2550      where I2 has a number of CLOBBERs inside the PARALLEL.
2551
2552      We make very conservative checks below and only try to handle the
2553      most common cases of this.  For example, we only handle the case
2554      where I2 and I3 are adjacent to avoid making difficult register
2555      usage tests.  */
2556
2557   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2558       && REG_P (SET_SRC (PATTERN (i3)))
2559       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2560       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2561       && GET_CODE (PATTERN (i2)) == PARALLEL
2562       && ! side_effects_p (SET_DEST (PATTERN (i3)))
2563       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2564          below would need to check what is inside (and reg_overlap_mentioned_p
2565          doesn't support those codes anyway).  Don't allow those destinations;
2566          the resulting insn isn't likely to be recognized anyway.  */
2567       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2568       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2569       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2570                                     SET_DEST (PATTERN (i3)))
2571       && next_active_insn (i2) == i3)
2572     {
2573       rtx p2 = PATTERN (i2);
2574
2575       /* Make sure that the destination of I3,
2576          which we are going to substitute into one output of I2,
2577          is not used within another output of I2.  We must avoid making this:
2578          (parallel [(set (mem (reg 69)) ...)
2579                     (set (reg 69) ...)])
2580          which is not well-defined as to order of actions.
2581          (Besides, reload can't handle output reloads for this.)
2582
2583          The problem can also happen if the dest of I3 is a memory ref,
2584          if another dest in I2 is an indirect memory ref.  */
2585       for (i = 0; i < XVECLEN (p2, 0); i++)
2586         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2587              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2588             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2589                                         SET_DEST (XVECEXP (p2, 0, i))))
2590           break;
2591
2592       if (i == XVECLEN (p2, 0))
2593         for (i = 0; i < XVECLEN (p2, 0); i++)
2594           if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2595               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2596             {
2597               combine_merges++;
2598
2599               subst_insn = i3;
2600               subst_low_luid = DF_INSN_LUID (i2);
2601
2602               added_sets_2 = added_sets_1 = added_sets_0 = 0;
2603               i2src = SET_SRC (XVECEXP (p2, 0, i));
2604               i2dest = SET_DEST (XVECEXP (p2, 0, i));
2605               i2dest_killed = dead_or_set_p (i2, i2dest);
2606
2607               /* Replace the dest in I2 with our dest and make the resulting
2608                  insn the new pattern for I3.  Then skip to where we validate
2609                  the pattern.  Everything was set up above.  */
2610               SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2611               newpat = p2;
2612               i3_subst_into_i2 = 1;
2613               goto validate_replacement;
2614             }
2615     }
2616
2617   /* If I2 is setting a pseudo to a constant and I3 is setting some
2618      sub-part of it to another constant, merge them by making a new
2619      constant.  */
2620   if (i1 == 0
2621       && (temp = single_set (i2)) != 0
2622       && (CONST_INT_P (SET_SRC (temp))
2623           || CONST_DOUBLE_AS_INT_P (SET_SRC (temp)))
2624       && GET_CODE (PATTERN (i3)) == SET
2625       && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2626           || CONST_DOUBLE_AS_INT_P (SET_SRC (PATTERN (i3))))
2627       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2628     {
2629       rtx dest = SET_DEST (PATTERN (i3));
2630       int offset = -1;
2631       int width = 0;
2632
2633       if (GET_CODE (dest) == ZERO_EXTRACT)
2634         {
2635           if (CONST_INT_P (XEXP (dest, 1))
2636               && CONST_INT_P (XEXP (dest, 2)))
2637             {
2638               width = INTVAL (XEXP (dest, 1));
2639               offset = INTVAL (XEXP (dest, 2));
2640               dest = XEXP (dest, 0);
2641               if (BITS_BIG_ENDIAN)
2642                 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2643             }
2644         }
2645       else
2646         {
2647           if (GET_CODE (dest) == STRICT_LOW_PART)
2648             dest = XEXP (dest, 0);
2649           width = GET_MODE_PRECISION (GET_MODE (dest));
2650           offset = 0;
2651         }
2652
2653       if (offset >= 0)
2654         {
2655           /* If this is the low part, we're done.  */
2656           if (subreg_lowpart_p (dest))
2657             ;
2658           /* Handle the case where inner is twice the size of outer.  */
2659           else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2660                    == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2661             offset += GET_MODE_PRECISION (GET_MODE (dest));
2662           /* Otherwise give up for now.  */
2663           else
2664             offset = -1;
2665         }
2666
2667       if (offset >= 0
2668           && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2669               <= HOST_BITS_PER_DOUBLE_INT))
2670         {
2671           double_int m, o, i;
2672           rtx inner = SET_SRC (PATTERN (i3));
2673           rtx outer = SET_SRC (temp);
2674
2675           o = rtx_to_double_int (outer);
2676           i = rtx_to_double_int (inner);
2677
2678           m = double_int::mask (width);
2679           i &= m;
2680           m = m.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2681           i = i.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2682           o = o.and_not (m) | i;
2683
2684           combine_merges++;
2685           subst_insn = i3;
2686           subst_low_luid = DF_INSN_LUID (i2);
2687           added_sets_2 = added_sets_1 = added_sets_0 = 0;
2688           i2dest = SET_DEST (temp);
2689           i2dest_killed = dead_or_set_p (i2, i2dest);
2690
2691           /* Replace the source in I2 with the new constant and make the
2692              resulting insn the new pattern for I3.  Then skip to where we
2693              validate the pattern.  Everything was set up above.  */
2694           SUBST (SET_SRC (temp),
2695                  immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2696
2697           newpat = PATTERN (i2);
2698
2699           /* The dest of I3 has been replaced with the dest of I2.  */
2700           changed_i3_dest = 1;
2701           goto validate_replacement;
2702         }
2703     }
2704
2705 #ifndef HAVE_cc0
2706   /* If we have no I1 and I2 looks like:
2707         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2708                    (set Y OP)])
2709      make up a dummy I1 that is
2710         (set Y OP)
2711      and change I2 to be
2712         (set (reg:CC X) (compare:CC Y (const_int 0)))
2713
2714      (We can ignore any trailing CLOBBERs.)
2715
2716      This undoes a previous combination and allows us to match a branch-and-
2717      decrement insn.  */
2718
2719   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2720       && XVECLEN (PATTERN (i2), 0) >= 2
2721       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2722       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2723           == MODE_CC)
2724       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2725       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2726       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2727       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2728       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2729                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2730     {
2731       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2732         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2733           break;
2734
2735       if (i == 1)
2736         {
2737           /* We make I1 with the same INSN_UID as I2.  This gives it
2738              the same DF_INSN_LUID for value tracking.  Our fake I1 will
2739              never appear in the insn stream so giving it the same INSN_UID
2740              as I2 will not cause a problem.  */
2741
2742           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2743                              BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2744                              INSN_LOCATION (i2), -1, NULL_RTX);
2745
2746           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2747           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2748                  SET_DEST (PATTERN (i1)));
2749           SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2750         }
2751     }
2752 #endif
2753
2754   /* Verify that I2 and I1 are valid for combining.  */
2755   if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2756       || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2757                                  &i1dest, &i1src))
2758       || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2759                                  &i0dest, &i0src)))
2760     {
2761       undo_all ();
2762       return 0;
2763     }
2764
2765   /* Record whether I2DEST is used in I2SRC and similarly for the other
2766      cases.  Knowing this will help in register status updating below.  */
2767   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2768   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2769   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2770   i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2771   i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2772   i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2773   i2dest_killed = dead_or_set_p (i2, i2dest);
2774   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2775   i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2776
2777   /* For the earlier insns, determine which of the subsequent ones they
2778      feed.  */
2779   i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2780   i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2781   i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2782                           : (!reg_overlap_mentioned_p (i1dest, i0dest)
2783                              && reg_overlap_mentioned_p (i0dest, i2src))));
2784
2785   /* Ensure that I3's pattern can be the destination of combines.  */
2786   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2787                           i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2788                           i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2789                                  || (i1dest_in_i0src && !i0_feeds_i1_n)),
2790                           &i3dest_killed))
2791     {
2792       undo_all ();
2793       return 0;
2794     }
2795
2796   /* See if any of the insns is a MULT operation.  Unless one is, we will
2797      reject a combination that is, since it must be slower.  Be conservative
2798      here.  */
2799   if (GET_CODE (i2src) == MULT
2800       || (i1 != 0 && GET_CODE (i1src) == MULT)
2801       || (i0 != 0 && GET_CODE (i0src) == MULT)
2802       || (GET_CODE (PATTERN (i3)) == SET
2803           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2804     have_mult = 1;
2805
2806   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2807      We used to do this EXCEPT in one case: I3 has a post-inc in an
2808      output operand.  However, that exception can give rise to insns like
2809         mov r3,(r3)+
2810      which is a famous insn on the PDP-11 where the value of r3 used as the
2811      source was model-dependent.  Avoid this sort of thing.  */
2812
2813 #if 0
2814   if (!(GET_CODE (PATTERN (i3)) == SET
2815         && REG_P (SET_SRC (PATTERN (i3)))
2816         && MEM_P (SET_DEST (PATTERN (i3)))
2817         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2818             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2819     /* It's not the exception.  */
2820 #endif
2821 #ifdef AUTO_INC_DEC
2822     {
2823       rtx link;
2824       for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2825         if (REG_NOTE_KIND (link) == REG_INC
2826             && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2827                 || (i1 != 0
2828                     && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2829           {
2830             undo_all ();
2831             return 0;
2832           }
2833     }
2834 #endif
2835
2836   /* See if the SETs in I1 or I2 need to be kept around in the merged
2837      instruction: whenever the value set there is still needed past I3.
2838      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2839
2840      For the SET in I1, we have two cases:  If I1 and I2 independently
2841      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2842      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2843      in I1 needs to be kept around unless I1DEST dies or is set in either
2844      I2 or I3.  The same consideration applies to I0.  */
2845
2846   added_sets_2 = !dead_or_set_p (i3, i2dest);
2847
2848   if (i1)
2849     added_sets_1 = !(dead_or_set_p (i3, i1dest)
2850                      || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2851   else
2852     added_sets_1 = 0;
2853
2854   if (i0)
2855     added_sets_0 =  !(dead_or_set_p (i3, i0dest)
2856                       || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
2857                       || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
2858   else
2859     added_sets_0 = 0;
2860
2861   /* We are about to copy insns for the case where they need to be kept
2862      around.  Check that they can be copied in the merged instruction.  */
2863
2864   if (targetm.cannot_copy_insn_p
2865       && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2866           || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2867           || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2868     {
2869       undo_all ();
2870       return 0;
2871     }
2872
2873   /* If the set in I2 needs to be kept around, we must make a copy of
2874      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2875      PATTERN (I2), we are only substituting for the original I1DEST, not into
2876      an already-substituted copy.  This also prevents making self-referential
2877      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2878      I2DEST.  */
2879
2880   if (added_sets_2)
2881     {
2882       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2883         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2884       else
2885         i2pat = copy_rtx (PATTERN (i2));
2886     }
2887
2888   if (added_sets_1)
2889     {
2890       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2891         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2892       else
2893         i1pat = copy_rtx (PATTERN (i1));
2894     }
2895
2896   if (added_sets_0)
2897     {
2898       if (GET_CODE (PATTERN (i0)) == PARALLEL)
2899         i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2900       else
2901         i0pat = copy_rtx (PATTERN (i0));
2902     }
2903
2904   combine_merges++;
2905
2906   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2907
2908   maxreg = max_reg_num ();
2909
2910   subst_insn = i3;
2911
2912 #ifndef HAVE_cc0
2913   /* Many machines that don't use CC0 have insns that can both perform an
2914      arithmetic operation and set the condition code.  These operations will
2915      be represented as a PARALLEL with the first element of the vector
2916      being a COMPARE of an arithmetic operation with the constant zero.
2917      The second element of the vector will set some pseudo to the result
2918      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2919      match such a pattern and so will generate an extra insn.   Here we test
2920      for this case, where both the comparison and the operation result are
2921      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2922      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2923
2924   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2925       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2926       && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
2927       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2928     {
2929       rtx newpat_dest;
2930       rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
2931       rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
2932       enum machine_mode compare_mode, orig_compare_mode;
2933       enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
2934
2935       newpat = PATTERN (i3);
2936       newpat_dest = SET_DEST (newpat);
2937       compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
2938
2939       if (undobuf.other_insn == 0
2940           && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
2941                                             &cc_use_insn)))
2942         {
2943           compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
2944           compare_code = simplify_compare_const (compare_code,
2945                                                  op0, &op1);
2946 #ifdef CANONICALIZE_COMPARISON
2947           CANONICALIZE_COMPARISON (compare_code, op0, op1);
2948 #endif
2949         }
2950
2951       /* Do the rest only if op1 is const0_rtx, which may be the
2952          result of simplification.  */
2953       if (op1 == const0_rtx)
2954         {
2955           /* If a single use of the CC is found, prepare to modify it
2956              when SELECT_CC_MODE returns a new CC-class mode, or when
2957              the above simplify_compare_const() returned a new comparison
2958              operator.  undobuf.other_insn is assigned the CC use insn
2959              when modifying it.  */
2960           if (cc_use_loc)
2961             {
2962 #ifdef SELECT_CC_MODE
2963               enum machine_mode new_mode
2964                 = SELECT_CC_MODE (compare_code, op0, op1);
2965               if (new_mode != orig_compare_mode
2966                   && can_change_dest_mode (SET_DEST (newpat),
2967                                            added_sets_2, new_mode))
2968                 {
2969                   unsigned int regno = REGNO (newpat_dest);
2970                   compare_mode = new_mode;
2971                   if (regno < FIRST_PSEUDO_REGISTER)
2972                     newpat_dest = gen_rtx_REG (compare_mode, regno);
2973                   else
2974                     {
2975                       SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2976                       newpat_dest = regno_reg_rtx[regno];
2977                     }
2978                 }
2979 #endif
2980               /* Cases for modifying the CC-using comparison.  */
2981               if (compare_code != orig_compare_code
2982                   /* ??? Do we need to verify the zero rtx?  */
2983                   && XEXP (*cc_use_loc, 1) == const0_rtx)
2984                 {
2985                   /* Replace cc_use_loc with entire new RTX.  */
2986                   SUBST (*cc_use_loc,
2987                          gen_rtx_fmt_ee (compare_code, compare_mode,
2988                                          newpat_dest, const0_rtx));
2989                   undobuf.other_insn = cc_use_insn;
2990                 }
2991               else if (compare_mode != orig_compare_mode)
2992                 {
2993                   /* Just replace the CC reg with a new mode.  */
2994                   SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
2995                   undobuf.other_insn = cc_use_insn;
2996                 }
2997             }
2998
2999           /* Now we modify the current newpat:
3000              First, SET_DEST(newpat) is updated if the CC mode has been
3001              altered. For targets without SELECT_CC_MODE, this should be
3002              optimized away.  */
3003           if (compare_mode != orig_compare_mode)
3004             SUBST (SET_DEST (newpat), newpat_dest);
3005           /* This is always done to propagate i2src into newpat.  */
3006           SUBST (SET_SRC (newpat),
3007                  gen_rtx_COMPARE (compare_mode, op0, op1));
3008           /* Create new version of i2pat if needed; the below PARALLEL
3009              creation needs this to work correctly.  */
3010           if (! rtx_equal_p (i2src, op0))
3011             i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3012           i2_is_used = 1;
3013         }
3014     }
3015 #endif
3016
3017   if (i2_is_used == 0)
3018     {
3019       /* It is possible that the source of I2 or I1 may be performing
3020          an unneeded operation, such as a ZERO_EXTEND of something
3021          that is known to have the high part zero.  Handle that case
3022          by letting subst look at the inner insns.
3023
3024          Another way to do this would be to have a function that tries
3025          to simplify a single insn instead of merging two or more
3026          insns.  We don't do this because of the potential of infinite
3027          loops and because of the potential extra memory required.
3028          However, doing it the way we are is a bit of a kludge and
3029          doesn't catch all cases.
3030
3031          But only do this if -fexpensive-optimizations since it slows
3032          things down and doesn't usually win.
3033
3034          This is not done in the COMPARE case above because the
3035          unmodified I2PAT is used in the PARALLEL and so a pattern
3036          with a modified I2SRC would not match.  */
3037
3038       if (flag_expensive_optimizations)
3039         {
3040           /* Pass pc_rtx so no substitutions are done, just
3041              simplifications.  */
3042           if (i1)
3043             {
3044               subst_low_luid = DF_INSN_LUID (i1);
3045               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3046             }
3047
3048           subst_low_luid = DF_INSN_LUID (i2);
3049           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3050         }
3051
3052       n_occurrences = 0;                /* `subst' counts here */
3053       subst_low_luid = DF_INSN_LUID (i2);
3054
3055       /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3056          copy of I2SRC each time we substitute it, in order to avoid creating
3057          self-referential RTL when we will be substituting I1SRC for I1DEST
3058          later.  Likewise if I0 feeds into I2, either directly or indirectly
3059          through I1, and I0DEST is in I0SRC.  */
3060       newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3061                       (i1_feeds_i2_n && i1dest_in_i1src)
3062                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3063                           && i0dest_in_i0src));
3064       substed_i2 = 1;
3065
3066       /* Record whether I2's body now appears within I3's body.  */
3067       i2_is_used = n_occurrences;
3068     }
3069
3070   /* If we already got a failure, don't try to do more.  Otherwise, try to
3071      substitute I1 if we have it.  */
3072
3073   if (i1 && GET_CODE (newpat) != CLOBBER)
3074     {
3075       /* Check that an autoincrement side-effect on I1 has not been lost.
3076          This happens if I1DEST is mentioned in I2 and dies there, and
3077          has disappeared from the new pattern.  */
3078       if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3079            && i1_feeds_i2_n
3080            && dead_or_set_p (i2, i1dest)
3081            && !reg_overlap_mentioned_p (i1dest, newpat))
3082            /* Before we can do this substitution, we must redo the test done
3083               above (see detailed comments there) that ensures I1DEST isn't
3084               mentioned in any SETs in NEWPAT that are field assignments.  */
3085           || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3086                                 0, 0, 0))
3087         {
3088           undo_all ();
3089           return 0;
3090         }
3091
3092       n_occurrences = 0;
3093       subst_low_luid = DF_INSN_LUID (i1);
3094
3095       /* If the following substitution will modify I1SRC, make a copy of it
3096          for the case where it is substituted for I1DEST in I2PAT later.  */
3097       if (added_sets_2 && i1_feeds_i2_n)
3098         i1src_copy = copy_rtx (i1src);
3099
3100       /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3101          copy of I1SRC each time we substitute it, in order to avoid creating
3102          self-referential RTL when we will be substituting I0SRC for I0DEST
3103          later.  */
3104       newpat = subst (newpat, i1dest, i1src, 0, 0,
3105                       i0_feeds_i1_n && i0dest_in_i0src);
3106       substed_i1 = 1;
3107
3108       /* Record whether I1's body now appears within I3's body.  */
3109       i1_is_used = n_occurrences;
3110     }
3111
3112   /* Likewise for I0 if we have it.  */
3113
3114   if (i0 && GET_CODE (newpat) != CLOBBER)
3115     {
3116       if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3117            && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3118                || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3119            && !reg_overlap_mentioned_p (i0dest, newpat))
3120           || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3121                                 0, 0, 0))
3122         {
3123           undo_all ();
3124           return 0;
3125         }
3126
3127       /* If the following substitution will modify I0SRC, make a copy of it
3128          for the case where it is substituted for I0DEST in I1PAT later.  */
3129       if (added_sets_1 && i0_feeds_i1_n)
3130         i0src_copy = copy_rtx (i0src);
3131       /* And a copy for I0DEST in I2PAT substitution.  */
3132       if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3133                            || (i0_feeds_i2_n)))
3134         i0src_copy2 = copy_rtx (i0src);
3135
3136       n_occurrences = 0;
3137       subst_low_luid = DF_INSN_LUID (i0);
3138       newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3139       substed_i0 = 1;
3140     }
3141
3142   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
3143      to count all the ways that I2SRC and I1SRC can be used.  */
3144   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3145        && i2_is_used + added_sets_2 > 1)
3146       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3147           && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3148               > 1))
3149       || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3150           && (n_occurrences + added_sets_0
3151               + (added_sets_1 && i0_feeds_i1_n)
3152               + (added_sets_2 && i0_feeds_i2_n)
3153               > 1))
3154       /* Fail if we tried to make a new register.  */
3155       || max_reg_num () != maxreg
3156       /* Fail if we couldn't do something and have a CLOBBER.  */
3157       || GET_CODE (newpat) == CLOBBER
3158       /* Fail if this new pattern is a MULT and we didn't have one before
3159          at the outer level.  */
3160       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3161           && ! have_mult))
3162     {
3163       undo_all ();
3164       return 0;
3165     }
3166
3167   /* If the actions of the earlier insns must be kept
3168      in addition to substituting them into the latest one,
3169      we must make a new PARALLEL for the latest insn
3170      to hold additional the SETs.  */
3171
3172   if (added_sets_0 || added_sets_1 || added_sets_2)
3173     {
3174       int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3175       combine_extras++;
3176
3177       if (GET_CODE (newpat) == PARALLEL)
3178         {
3179           rtvec old = XVEC (newpat, 0);
3180           total_sets = XVECLEN (newpat, 0) + extra_sets;
3181           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3182           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3183                   sizeof (old->elem[0]) * old->num_elem);
3184         }
3185       else
3186         {
3187           rtx old = newpat;
3188           total_sets = 1 + extra_sets;
3189           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3190           XVECEXP (newpat, 0, 0) = old;
3191         }
3192
3193       if (added_sets_0)
3194         XVECEXP (newpat, 0, --total_sets) = i0pat;
3195
3196       if (added_sets_1)
3197         {
3198           rtx t = i1pat;
3199           if (i0_feeds_i1_n)
3200             t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3201
3202           XVECEXP (newpat, 0, --total_sets) = t;
3203         }
3204       if (added_sets_2)
3205         {
3206           rtx t = i2pat;
3207           if (i1_feeds_i2_n)
3208             t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3209                        i0_feeds_i1_n && i0dest_in_i0src);
3210           if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3211             t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3212
3213           XVECEXP (newpat, 0, --total_sets) = t;
3214         }
3215     }
3216
3217  validate_replacement:
3218
3219   /* Note which hard regs this insn has as inputs.  */
3220   mark_used_regs_combine (newpat);
3221
3222   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
3223      consider splitting this pattern, we might need these clobbers.  */
3224   if (i1 && GET_CODE (newpat) == PARALLEL
3225       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3226     {
3227       int len = XVECLEN (newpat, 0);
3228
3229       newpat_vec_with_clobbers = rtvec_alloc (len);
3230       for (i = 0; i < len; i++)
3231         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3232     }
3233
3234   /* Is the result of combination a valid instruction?  */
3235   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3236
3237   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3238      the second SET's destination is a register that is unused and isn't
3239      marked as an instruction that might trap in an EH region.  In that case,
3240      we just need the first SET.   This can occur when simplifying a divmod
3241      insn.  We *must* test for this case here because the code below that
3242      splits two independent SETs doesn't handle this case correctly when it
3243      updates the register status.
3244
3245      It's pointless doing this if we originally had two sets, one from
3246      i3, and one from i2.  Combining then splitting the parallel results
3247      in the original i2 again plus an invalid insn (which we delete).
3248      The net effect is only to move instructions around, which makes
3249      debug info less accurate.
3250
3251      Also check the case where the first SET's destination is unused.
3252      That would not cause incorrect code, but does cause an unneeded
3253      insn to remain.  */
3254
3255   if (insn_code_number < 0
3256       && !(added_sets_2 && i1 == 0)
3257       && GET_CODE (newpat) == PARALLEL
3258       && XVECLEN (newpat, 0) == 2
3259       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3260       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3261       && asm_noperands (newpat) < 0)
3262     {
3263       rtx set0 = XVECEXP (newpat, 0, 0);
3264       rtx set1 = XVECEXP (newpat, 0, 1);
3265
3266       if (((REG_P (SET_DEST (set1))
3267             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3268            || (GET_CODE (SET_DEST (set1)) == SUBREG
3269                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3270           && insn_nothrow_p (i3)
3271           && !side_effects_p (SET_SRC (set1)))
3272         {
3273           newpat = set0;
3274           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3275         }
3276
3277       else if (((REG_P (SET_DEST (set0))
3278                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3279                 || (GET_CODE (SET_DEST (set0)) == SUBREG
3280                     && find_reg_note (i3, REG_UNUSED,
3281                                       SUBREG_REG (SET_DEST (set0)))))
3282                && insn_nothrow_p (i3)
3283                && !side_effects_p (SET_SRC (set0)))
3284         {
3285           newpat = set1;
3286           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3287
3288           if (insn_code_number >= 0)
3289             changed_i3_dest = 1;
3290         }
3291     }
3292
3293   /* If we were combining three insns and the result is a simple SET
3294      with no ASM_OPERANDS that wasn't recognized, try to split it into two
3295      insns.  There are two ways to do this.  It can be split using a
3296      machine-specific method (like when you have an addition of a large
3297      constant) or by combine in the function find_split_point.  */
3298
3299   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3300       && asm_noperands (newpat) < 0)
3301     {
3302       rtx parallel, m_split, *split;
3303
3304       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
3305          use I2DEST as a scratch register will help.  In the latter case,
3306          convert I2DEST to the mode of the source of NEWPAT if we can.  */
3307
3308       m_split = combine_split_insns (newpat, i3);
3309
3310       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3311          inputs of NEWPAT.  */
3312
3313       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3314          possible to try that as a scratch reg.  This would require adding
3315          more code to make it work though.  */
3316
3317       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3318         {
3319           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3320
3321           /* First try to split using the original register as a
3322              scratch register.  */
3323           parallel = gen_rtx_PARALLEL (VOIDmode,
3324                                        gen_rtvec (2, newpat,
3325                                                   gen_rtx_CLOBBER (VOIDmode,
3326                                                                    i2dest)));
3327           m_split = combine_split_insns (parallel, i3);
3328
3329           /* If that didn't work, try changing the mode of I2DEST if
3330              we can.  */
3331           if (m_split == 0
3332               && new_mode != GET_MODE (i2dest)
3333               && new_mode != VOIDmode
3334               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3335             {
3336               enum machine_mode old_mode = GET_MODE (i2dest);
3337               rtx ni2dest;
3338
3339               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3340                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3341               else
3342                 {
3343                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3344                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
3345                 }
3346
3347               parallel = (gen_rtx_PARALLEL
3348                           (VOIDmode,
3349                            gen_rtvec (2, newpat,
3350                                       gen_rtx_CLOBBER (VOIDmode,
3351                                                        ni2dest))));
3352               m_split = combine_split_insns (parallel, i3);
3353
3354               if (m_split == 0
3355                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3356                 {
3357                   struct undo *buf;
3358
3359                   adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3360                   buf = undobuf.undos;
3361                   undobuf.undos = buf->next;
3362                   buf->next = undobuf.frees;
3363                   undobuf.frees = buf;
3364                 }
3365             }
3366
3367           i2scratch = m_split != 0;
3368         }
3369
3370       /* If recog_for_combine has discarded clobbers, try to use them
3371          again for the split.  */
3372       if (m_split == 0 && newpat_vec_with_clobbers)
3373         {
3374           parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3375           m_split = combine_split_insns (parallel, i3);
3376         }
3377
3378       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3379         {
3380           m_split = PATTERN (m_split);
3381           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3382           if (insn_code_number >= 0)
3383             newpat = m_split;
3384         }
3385       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3386                && (next_nonnote_nondebug_insn (i2) == i3
3387                    || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3388         {
3389           rtx i2set, i3set;
3390           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3391           newi2pat = PATTERN (m_split);
3392
3393           i3set = single_set (NEXT_INSN (m_split));
3394           i2set = single_set (m_split);
3395
3396           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3397
3398           /* If I2 or I3 has multiple SETs, we won't know how to track
3399              register status, so don't use these insns.  If I2's destination
3400              is used between I2 and I3, we also can't use these insns.  */
3401
3402           if (i2_code_number >= 0 && i2set && i3set
3403               && (next_nonnote_nondebug_insn (i2) == i3
3404                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3405             insn_code_number = recog_for_combine (&newi3pat, i3,
3406                                                   &new_i3_notes);
3407           if (insn_code_number >= 0)
3408             newpat = newi3pat;
3409
3410           /* It is possible that both insns now set the destination of I3.
3411              If so, we must show an extra use of it.  */
3412
3413           if (insn_code_number >= 0)
3414             {
3415               rtx new_i3_dest = SET_DEST (i3set);
3416               rtx new_i2_dest = SET_DEST (i2set);
3417
3418               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3419                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3420                      || GET_CODE (new_i3_dest) == SUBREG)
3421                 new_i3_dest = XEXP (new_i3_dest, 0);
3422
3423               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3424                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3425                      || GET_CODE (new_i2_dest) == SUBREG)
3426                 new_i2_dest = XEXP (new_i2_dest, 0);
3427
3428               if (REG_P (new_i3_dest)
3429                   && REG_P (new_i2_dest)
3430                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3431                 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3432             }
3433         }
3434
3435       /* If we can split it and use I2DEST, go ahead and see if that
3436          helps things be recognized.  Verify that none of the registers
3437          are set between I2 and I3.  */
3438       if (insn_code_number < 0
3439           && (split = find_split_point (&newpat, i3, false)) != 0
3440 #ifdef HAVE_cc0
3441           && REG_P (i2dest)
3442 #endif
3443           /* We need I2DEST in the proper mode.  If it is a hard register
3444              or the only use of a pseudo, we can change its mode.
3445              Make sure we don't change a hard register to have a mode that
3446              isn't valid for it, or change the number of registers.  */
3447           && (GET_MODE (*split) == GET_MODE (i2dest)
3448               || GET_MODE (*split) == VOIDmode
3449               || can_change_dest_mode (i2dest, added_sets_2,
3450                                        GET_MODE (*split)))
3451           && (next_nonnote_nondebug_insn (i2) == i3
3452               || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3453           /* We can't overwrite I2DEST if its value is still used by
3454              NEWPAT.  */
3455           && ! reg_referenced_p (i2dest, newpat))
3456         {
3457           rtx newdest = i2dest;
3458           enum rtx_code split_code = GET_CODE (*split);
3459           enum machine_mode split_mode = GET_MODE (*split);
3460           bool subst_done = false;
3461           newi2pat = NULL_RTX;
3462
3463           i2scratch = true;
3464
3465           /* *SPLIT may be part of I2SRC, so make sure we have the
3466              original expression around for later debug processing.
3467              We should not need I2SRC any more in other cases.  */
3468           if (MAY_HAVE_DEBUG_INSNS)
3469             i2src = copy_rtx (i2src);
3470           else
3471             i2src = NULL;
3472
3473           /* Get NEWDEST as a register in the proper mode.  We have already
3474              validated that we can do this.  */
3475           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3476             {
3477               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3478                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3479               else
3480                 {
3481                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3482                   newdest = regno_reg_rtx[REGNO (i2dest)];
3483                 }
3484             }
3485
3486           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3487              an ASHIFT.  This can occur if it was inside a PLUS and hence
3488              appeared to be a memory address.  This is a kludge.  */
3489           if (split_code == MULT
3490               && CONST_INT_P (XEXP (*split, 1))
3491               && INTVAL (XEXP (*split, 1)) > 0
3492               && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3493             {
3494               SUBST (*split, gen_rtx_ASHIFT (split_mode,
3495                                              XEXP (*split, 0), GEN_INT (i)));
3496               /* Update split_code because we may not have a multiply
3497                  anymore.  */
3498               split_code = GET_CODE (*split);
3499             }
3500
3501 #ifdef INSN_SCHEDULING
3502           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3503              be written as a ZERO_EXTEND.  */
3504           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3505             {
3506 #ifdef LOAD_EXTEND_OP
3507               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3508                  what it really is.  */
3509               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3510                   == SIGN_EXTEND)
3511                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3512                                                     SUBREG_REG (*split)));
3513               else
3514 #endif
3515                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3516                                                     SUBREG_REG (*split)));
3517             }
3518 #endif
3519
3520           /* Attempt to split binary operators using arithmetic identities.  */
3521           if (BINARY_P (SET_SRC (newpat))
3522               && split_mode == GET_MODE (SET_SRC (newpat))
3523               && ! side_effects_p (SET_SRC (newpat)))
3524             {
3525               rtx setsrc = SET_SRC (newpat);
3526               enum machine_mode mode = GET_MODE (setsrc);
3527               enum rtx_code code = GET_CODE (setsrc);
3528               rtx src_op0 = XEXP (setsrc, 0);
3529               rtx src_op1 = XEXP (setsrc, 1);
3530
3531               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
3532               if (rtx_equal_p (src_op0, src_op1))
3533                 {
3534                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3535                   SUBST (XEXP (setsrc, 0), newdest);
3536                   SUBST (XEXP (setsrc, 1), newdest);
3537                   subst_done = true;
3538                 }
3539               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
3540               else if ((code == PLUS || code == MULT)
3541                        && GET_CODE (src_op0) == code
3542                        && GET_CODE (XEXP (src_op0, 0)) == code
3543                        && (INTEGRAL_MODE_P (mode)
3544                            || (FLOAT_MODE_P (mode)
3545                                && flag_unsafe_math_optimizations)))
3546                 {
3547                   rtx p = XEXP (XEXP (src_op0, 0), 0);
3548                   rtx q = XEXP (XEXP (src_op0, 0), 1);
3549                   rtx r = XEXP (src_op0, 1);
3550                   rtx s = src_op1;
3551
3552                   /* Split both "((X op Y) op X) op Y" and
3553                      "((X op Y) op Y) op X" as "T op T" where T is
3554                      "X op Y".  */
3555                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3556                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3557                     {
3558                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
3559                                               XEXP (src_op0, 0));
3560                       SUBST (XEXP (setsrc, 0), newdest);
3561                       SUBST (XEXP (setsrc, 1), newdest);
3562                       subst_done = true;
3563                     }
3564                   /* Split "((X op X) op Y) op Y)" as "T op T" where
3565                      T is "X op Y".  */
3566                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3567                     {
3568                       rtx tmp = simplify_gen_binary (code, mode, p, r);
3569                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3570                       SUBST (XEXP (setsrc, 0), newdest);
3571                       SUBST (XEXP (setsrc, 1), newdest);
3572                       subst_done = true;
3573                     }
3574                 }
3575             }
3576
3577           if (!subst_done)
3578             {
3579               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3580               SUBST (*split, newdest);
3581             }
3582
3583           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3584
3585           /* recog_for_combine might have added CLOBBERs to newi2pat.
3586              Make sure NEWPAT does not depend on the clobbered regs.  */
3587           if (GET_CODE (newi2pat) == PARALLEL)
3588             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3589               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3590                 {
3591                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3592                   if (reg_overlap_mentioned_p (reg, newpat))
3593                     {
3594                       undo_all ();
3595                       return 0;
3596                     }
3597                 }
3598
3599           /* If the split point was a MULT and we didn't have one before,
3600              don't use one now.  */
3601           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3602             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3603         }
3604     }
3605
3606   /* Check for a case where we loaded from memory in a narrow mode and
3607      then sign extended it, but we need both registers.  In that case,
3608      we have a PARALLEL with both loads from the same memory location.
3609      We can split this into a load from memory followed by a register-register
3610      copy.  This saves at least one insn, more if register allocation can
3611      eliminate the copy.
3612
3613      We cannot do this if the destination of the first assignment is a
3614      condition code register or cc0.  We eliminate this case by making sure
3615      the SET_DEST and SET_SRC have the same mode.
3616
3617      We cannot do this if the destination of the second assignment is
3618      a register that we have already assumed is zero-extended.  Similarly
3619      for a SUBREG of such a register.  */
3620
3621   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3622            && GET_CODE (newpat) == PARALLEL
3623            && XVECLEN (newpat, 0) == 2
3624            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3625            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3626            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3627                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3628            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3629            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3630                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3631            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3632                                    DF_INSN_LUID (i2))
3633            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3634            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3635            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3636                  (REG_P (temp)
3637                   && VEC_index (reg_stat_type, reg_stat,
3638                                 REGNO (temp)).nonzero_bits != 0
3639                   && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3640                   && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3641                   && (VEC_index (reg_stat_type, reg_stat,
3642                                  REGNO (temp)).nonzero_bits
3643                       != GET_MODE_MASK (word_mode))))
3644            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3645                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3646                      (REG_P (temp)
3647                       && VEC_index (reg_stat_type, reg_stat,
3648                                     REGNO (temp)).nonzero_bits != 0
3649                       && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3650                       && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3651                       && (VEC_index (reg_stat_type, reg_stat,
3652                                      REGNO (temp)).nonzero_bits
3653                           != GET_MODE_MASK (word_mode)))))
3654            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3655                                          SET_SRC (XVECEXP (newpat, 0, 1)))
3656            && ! find_reg_note (i3, REG_UNUSED,
3657                                SET_DEST (XVECEXP (newpat, 0, 0))))
3658     {
3659       rtx ni2dest;
3660
3661       newi2pat = XVECEXP (newpat, 0, 0);
3662       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3663       newpat = XVECEXP (newpat, 0, 1);
3664       SUBST (SET_SRC (newpat),
3665              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3666       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3667
3668       if (i2_code_number >= 0)
3669         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3670
3671       if (insn_code_number >= 0)
3672         swap_i2i3 = 1;
3673     }
3674
3675   /* Similarly, check for a case where we have a PARALLEL of two independent
3676      SETs but we started with three insns.  In this case, we can do the sets
3677      as two separate insns.  This case occurs when some SET allows two
3678      other insns to combine, but the destination of that SET is still live.  */
3679
3680   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3681            && GET_CODE (newpat) == PARALLEL
3682            && XVECLEN (newpat, 0) == 2
3683            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3684            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3685            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3686            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3687            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3688            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3689            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3690                                   XVECEXP (newpat, 0, 0))
3691            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3692                                   XVECEXP (newpat, 0, 1))
3693            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3694                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3695     {
3696       /* Normally, it doesn't matter which of the two is done first,
3697          but the one that references cc0 can't be the second, and
3698          one which uses any regs/memory set in between i2 and i3 can't
3699          be first.  */
3700       if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3701                               DF_INSN_LUID (i2))
3702 #ifdef HAVE_cc0
3703           && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3704 #endif
3705          )
3706         {
3707           newi2pat = XVECEXP (newpat, 0, 1);
3708           newpat = XVECEXP (newpat, 0, 0);
3709         }
3710       else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3711                                    DF_INSN_LUID (i2))
3712 #ifdef HAVE_cc0
3713                && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3714 #endif
3715               )
3716         {
3717           newi2pat = XVECEXP (newpat, 0, 0);
3718           newpat = XVECEXP (newpat, 0, 1);
3719         }
3720       else
3721         {
3722           undo_all ();
3723           return 0;
3724         }
3725
3726       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3727
3728       if (i2_code_number >= 0)
3729         {
3730           /* recog_for_combine might have added CLOBBERs to newi2pat.
3731              Make sure NEWPAT does not depend on the clobbered regs.  */
3732           if (GET_CODE (newi2pat) == PARALLEL)
3733             {
3734               for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3735                 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3736                   {
3737                     rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3738                     if (reg_overlap_mentioned_p (reg, newpat))
3739                       {
3740                         undo_all ();
3741                         return 0;
3742                       }
3743                   }
3744             }
3745
3746           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3747         }
3748     }
3749
3750   /* If it still isn't recognized, fail and change things back the way they
3751      were.  */
3752   if ((insn_code_number < 0
3753        /* Is the result a reasonable ASM_OPERANDS?  */
3754        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3755     {
3756       undo_all ();
3757       return 0;
3758     }
3759
3760   /* If we had to change another insn, make sure it is valid also.  */
3761   if (undobuf.other_insn)
3762     {
3763       CLEAR_HARD_REG_SET (newpat_used_regs);
3764
3765       other_pat = PATTERN (undobuf.other_insn);
3766       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3767                                              &new_other_notes);
3768
3769       if (other_code_number < 0 && ! check_asm_operands (other_pat))
3770         {
3771           undo_all ();
3772           return 0;
3773         }
3774     }
3775
3776 #ifdef HAVE_cc0
3777   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3778      they are adjacent to each other or not.  */
3779   {
3780     rtx p = prev_nonnote_insn (i3);
3781     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3782         && sets_cc0_p (newi2pat))
3783       {
3784         undo_all ();
3785         return 0;
3786       }
3787   }
3788 #endif
3789
3790   /* Only allow this combination if insn_rtx_costs reports that the
3791      replacement instructions are cheaper than the originals.  */
3792   if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3793     {
3794       undo_all ();
3795       return 0;
3796     }
3797
3798   if (MAY_HAVE_DEBUG_INSNS)
3799     {
3800       struct undo *undo;
3801
3802       for (undo = undobuf.undos; undo; undo = undo->next)
3803         if (undo->kind == UNDO_MODE)
3804           {
3805             rtx reg = *undo->where.r;
3806             enum machine_mode new_mode = GET_MODE (reg);
3807             enum machine_mode old_mode = undo->old_contents.m;
3808
3809             /* Temporarily revert mode back.  */
3810             adjust_reg_mode (reg, old_mode);
3811
3812             if (reg == i2dest && i2scratch)
3813               {
3814                 /* If we used i2dest as a scratch register with a
3815                    different mode, substitute it for the original
3816                    i2src while its original mode is temporarily
3817                    restored, and then clear i2scratch so that we don't
3818                    do it again later.  */
3819                 propagate_for_debug (i2, last_combined_insn, reg, i2src,
3820                                      this_basic_block);
3821                 i2scratch = false;
3822                 /* Put back the new mode.  */
3823                 adjust_reg_mode (reg, new_mode);
3824               }
3825             else
3826               {
3827                 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3828                 rtx first, last;
3829
3830                 if (reg == i2dest)
3831                   {
3832                     first = i2;
3833                     last = last_combined_insn;
3834                   }
3835                 else
3836                   {
3837                     first = i3;
3838                     last = undobuf.other_insn;
3839                     gcc_assert (last);
3840                     if (DF_INSN_LUID (last)
3841                         < DF_INSN_LUID (last_combined_insn))
3842                       last = last_combined_insn;
3843                   }
3844
3845                 /* We're dealing with a reg that changed mode but not
3846                    meaning, so we want to turn it into a subreg for
3847                    the new mode.  However, because of REG sharing and
3848                    because its mode had already changed, we have to do
3849                    it in two steps.  First, replace any debug uses of
3850                    reg, with its original mode temporarily restored,
3851                    with this copy we have created; then, replace the
3852                    copy with the SUBREG of the original shared reg,
3853                    once again changed to the new mode.  */
3854                 propagate_for_debug (first, last, reg, tempreg,
3855                                      this_basic_block);
3856                 adjust_reg_mode (reg, new_mode);
3857                 propagate_for_debug (first, last, tempreg,
3858                                      lowpart_subreg (old_mode, reg, new_mode),
3859                                      this_basic_block);
3860               }
3861           }
3862     }
3863
3864   /* If we will be able to accept this, we have made a
3865      change to the destination of I3.  This requires us to
3866      do a few adjustments.  */
3867
3868   if (changed_i3_dest)
3869     {
3870       PATTERN (i3) = newpat;
3871       adjust_for_new_dest (i3);
3872     }
3873
3874   /* We now know that we can do this combination.  Merge the insns and
3875      update the status of registers and LOG_LINKS.  */
3876
3877   if (undobuf.other_insn)
3878     {
3879       rtx note, next;
3880
3881       PATTERN (undobuf.other_insn) = other_pat;
3882
3883       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3884          are still valid.  Then add any non-duplicate notes added by
3885          recog_for_combine.  */
3886       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3887         {
3888           next = XEXP (note, 1);
3889
3890           if (REG_NOTE_KIND (note) == REG_UNUSED
3891               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3892             remove_note (undobuf.other_insn, note);
3893         }
3894
3895       distribute_notes (new_other_notes, undobuf.other_insn,
3896                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3897                         NULL_RTX);
3898     }
3899
3900   if (swap_i2i3)
3901     {
3902       rtx insn;
3903       struct insn_link *link;
3904       rtx ni2dest;
3905
3906       /* I3 now uses what used to be its destination and which is now
3907          I2's destination.  This requires us to do a few adjustments.  */
3908       PATTERN (i3) = newpat;
3909       adjust_for_new_dest (i3);
3910
3911       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3912          so we still will.
3913
3914          However, some later insn might be using I2's dest and have
3915          a LOG_LINK pointing at I3.  We must remove this link.
3916          The simplest way to remove the link is to point it at I1,
3917          which we know will be a NOTE.  */
3918
3919       /* newi2pat is usually a SET here; however, recog_for_combine might
3920          have added some clobbers.  */
3921       if (GET_CODE (newi2pat) == PARALLEL)
3922         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3923       else
3924         ni2dest = SET_DEST (newi2pat);
3925
3926       for (insn = NEXT_INSN (i3);
3927            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3928                     || insn != BB_HEAD (this_basic_block->next_bb));
3929            insn = NEXT_INSN (insn))
3930         {
3931           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3932             {
3933               FOR_EACH_LOG_LINK (link, insn)
3934                 if (link->insn == i3)
3935                   link->insn = i1;
3936
3937               break;
3938             }
3939         }
3940     }
3941
3942   {
3943     rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
3944     struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
3945     rtx midnotes = 0;
3946     int from_luid;
3947     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3948        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3949        same as i3dest, in which case newi2pat may be setting i1dest.  */
3950     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3951                    || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
3952                    || !i2dest_killed
3953                    ? 0 : i2dest);
3954     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
3955                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3956                    || !i1dest_killed
3957                    ? 0 : i1dest);
3958     rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
3959                    || (newi2pat && reg_set_p (i0dest, newi2pat))
3960                    || !i0dest_killed
3961                    ? 0 : i0dest);
3962
3963     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3964        clear them.  */
3965     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3966     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3967     if (i1)
3968       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3969     if (i0)
3970       i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
3971
3972     /* Ensure that we do not have something that should not be shared but
3973        occurs multiple times in the new insns.  Check this by first
3974        resetting all the `used' flags and then copying anything is shared.  */
3975
3976     reset_used_flags (i3notes);
3977     reset_used_flags (i2notes);
3978     reset_used_flags (i1notes);
3979     reset_used_flags (i0notes);
3980     reset_used_flags (newpat);
3981     reset_used_flags (newi2pat);
3982     if (undobuf.other_insn)
3983       reset_used_flags (PATTERN (undobuf.other_insn));
3984
3985     i3notes = copy_rtx_if_shared (i3notes);
3986     i2notes = copy_rtx_if_shared (i2notes);
3987     i1notes = copy_rtx_if_shared (i1notes);
3988     i0notes = copy_rtx_if_shared (i0notes);
3989     newpat = copy_rtx_if_shared (newpat);
3990     newi2pat = copy_rtx_if_shared (newi2pat);
3991     if (undobuf.other_insn)
3992       reset_used_flags (PATTERN (undobuf.other_insn));
3993
3994     INSN_CODE (i3) = insn_code_number;
3995     PATTERN (i3) = newpat;
3996
3997     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3998       {
3999         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4000
4001         reset_used_flags (call_usage);
4002         call_usage = copy_rtx (call_usage);
4003
4004         if (substed_i2)
4005           {
4006             /* I2SRC must still be meaningful at this point.  Some splitting
4007                operations can invalidate I2SRC, but those operations do not
4008                apply to calls.  */
4009             gcc_assert (i2src);
4010             replace_rtx (call_usage, i2dest, i2src);
4011           }
4012
4013         if (substed_i1)
4014           replace_rtx (call_usage, i1dest, i1src);
4015         if (substed_i0)
4016           replace_rtx (call_usage, i0dest, i0src);
4017
4018         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4019       }
4020
4021     if (undobuf.other_insn)
4022       INSN_CODE (undobuf.other_insn) = other_code_number;
4023
4024     /* We had one special case above where I2 had more than one set and
4025        we replaced a destination of one of those sets with the destination
4026        of I3.  In that case, we have to update LOG_LINKS of insns later
4027        in this basic block.  Note that this (expensive) case is rare.
4028
4029        Also, in this case, we must pretend that all REG_NOTEs for I2
4030        actually came from I3, so that REG_UNUSED notes from I2 will be
4031        properly handled.  */
4032
4033     if (i3_subst_into_i2)
4034       {
4035         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4036           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4037                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4038               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4039               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4040               && ! find_reg_note (i2, REG_UNUSED,
4041                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4042             for (temp = NEXT_INSN (i2);
4043                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4044                           || BB_HEAD (this_basic_block) != temp);
4045                  temp = NEXT_INSN (temp))
4046               if (temp != i3 && INSN_P (temp))
4047                 FOR_EACH_LOG_LINK (link, temp)
4048                   if (link->insn == i2)
4049                     link->insn = i3;
4050
4051         if (i3notes)
4052           {
4053             rtx link = i3notes;
4054             while (XEXP (link, 1))
4055               link = XEXP (link, 1);
4056             XEXP (link, 1) = i2notes;
4057           }
4058         else
4059           i3notes = i2notes;
4060         i2notes = 0;
4061       }
4062
4063     LOG_LINKS (i3) = NULL;
4064     REG_NOTES (i3) = 0;
4065     LOG_LINKS (i2) = NULL;
4066     REG_NOTES (i2) = 0;
4067
4068     if (newi2pat)
4069       {
4070         if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4071           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4072                                this_basic_block);
4073         INSN_CODE (i2) = i2_code_number;
4074         PATTERN (i2) = newi2pat;
4075       }
4076     else
4077       {
4078         if (MAY_HAVE_DEBUG_INSNS && i2src)
4079           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4080                                this_basic_block);
4081         SET_INSN_DELETED (i2);
4082       }
4083
4084     if (i1)
4085       {
4086         LOG_LINKS (i1) = NULL;
4087         REG_NOTES (i1) = 0;
4088         if (MAY_HAVE_DEBUG_INSNS)
4089           propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4090                                this_basic_block);
4091         SET_INSN_DELETED (i1);
4092       }
4093
4094     if (i0)
4095       {
4096         LOG_LINKS (i0) = NULL;
4097         REG_NOTES (i0) = 0;
4098         if (MAY_HAVE_DEBUG_INSNS)
4099           propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4100                                this_basic_block);
4101         SET_INSN_DELETED (i0);
4102       }
4103
4104     /* Get death notes for everything that is now used in either I3 or
4105        I2 and used to die in a previous insn.  If we built two new
4106        patterns, move from I1 to I2 then I2 to I3 so that we get the
4107        proper movement on registers that I2 modifies.  */
4108
4109     if (i0)
4110       from_luid = DF_INSN_LUID (i0);
4111     else if (i1)
4112       from_luid = DF_INSN_LUID (i1);
4113     else
4114       from_luid = DF_INSN_LUID (i2);
4115     if (newi2pat)
4116       move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4117     move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4118
4119     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
4120     if (i3notes)
4121       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4122                         elim_i2, elim_i1, elim_i0);
4123     if (i2notes)
4124       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4125                         elim_i2, elim_i1, elim_i0);
4126     if (i1notes)
4127       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4128                         elim_i2, elim_i1, elim_i0);
4129     if (i0notes)
4130       distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4131                         elim_i2, elim_i1, elim_i0);
4132     if (midnotes)
4133       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4134                         elim_i2, elim_i1, elim_i0);
4135
4136     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
4137        know these are REG_UNUSED and want them to go to the desired insn,
4138        so we always pass it as i3.  */
4139
4140     if (newi2pat && new_i2_notes)
4141       distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4142                         NULL_RTX);
4143
4144     if (new_i3_notes)
4145       distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4146                         NULL_RTX);
4147
4148     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
4149        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
4150        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
4151        in that case, it might delete I2.  Similarly for I2 and I1.
4152        Show an additional death due to the REG_DEAD note we make here.  If
4153        we discard it in distribute_notes, we will decrement it again.  */
4154
4155     if (i3dest_killed)
4156       {
4157         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4158           distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4159                                             NULL_RTX),
4160                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4161         else
4162           distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4163                                             NULL_RTX),
4164                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4165                             elim_i2, elim_i1, elim_i0);
4166       }
4167
4168     if (i2dest_in_i2src)
4169       {
4170         rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4171         if (newi2pat && reg_set_p (i2dest, newi2pat))
4172           distribute_notes (new_note,  NULL_RTX, i2, NULL_RTX, NULL_RTX,
4173                             NULL_RTX, NULL_RTX);
4174         else
4175           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4176                             NULL_RTX, NULL_RTX, NULL_RTX);
4177       }
4178
4179     if (i1dest_in_i1src)
4180       {
4181         rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4182         if (newi2pat && reg_set_p (i1dest, newi2pat))
4183           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4184                             NULL_RTX, NULL_RTX);
4185         else
4186           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4187                             NULL_RTX, NULL_RTX, NULL_RTX);
4188       }
4189
4190     if (i0dest_in_i0src)
4191       {
4192         rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4193         if (newi2pat && reg_set_p (i0dest, newi2pat))
4194           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4195                             NULL_RTX, NULL_RTX);
4196         else
4197           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4198                             NULL_RTX, NULL_RTX, NULL_RTX);
4199       }
4200
4201     distribute_links (i3links);
4202     distribute_links (i2links);
4203     distribute_links (i1links);
4204     distribute_links (i0links);
4205
4206     if (REG_P (i2dest))
4207       {
4208         struct insn_link *link;
4209         rtx i2_insn = 0, i2_val = 0, set;
4210
4211         /* The insn that used to set this register doesn't exist, and
4212            this life of the register may not exist either.  See if one of
4213            I3's links points to an insn that sets I2DEST.  If it does,
4214            that is now the last known value for I2DEST. If we don't update
4215            this and I2 set the register to a value that depended on its old
4216            contents, we will get confused.  If this insn is used, thing
4217            will be set correctly in combine_instructions.  */
4218         FOR_EACH_LOG_LINK (link, i3)
4219           if ((set = single_set (link->insn)) != 0
4220               && rtx_equal_p (i2dest, SET_DEST (set)))
4221             i2_insn = link->insn, i2_val = SET_SRC (set);
4222
4223         record_value_for_reg (i2dest, i2_insn, i2_val);
4224
4225         /* If the reg formerly set in I2 died only once and that was in I3,
4226            zero its use count so it won't make `reload' do any work.  */
4227         if (! added_sets_2
4228             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4229             && ! i2dest_in_i2src)
4230           INC_REG_N_SETS (REGNO (i2dest), -1);
4231       }
4232
4233     if (i1 && REG_P (i1dest))
4234       {
4235         struct insn_link *link;
4236         rtx i1_insn = 0, i1_val = 0, set;
4237
4238         FOR_EACH_LOG_LINK (link, i3)
4239           if ((set = single_set (link->insn)) != 0
4240               && rtx_equal_p (i1dest, SET_DEST (set)))
4241             i1_insn = link->insn, i1_val = SET_SRC (set);
4242
4243         record_value_for_reg (i1dest, i1_insn, i1_val);
4244
4245         if (! added_sets_1 && ! i1dest_in_i1src)
4246           INC_REG_N_SETS (REGNO (i1dest), -1);
4247       }
4248
4249     if (i0 && REG_P (i0dest))
4250       {
4251         struct insn_link *link;
4252         rtx i0_insn = 0, i0_val = 0, set;
4253
4254         FOR_EACH_LOG_LINK (link, i3)
4255           if ((set = single_set (link->insn)) != 0
4256               && rtx_equal_p (i0dest, SET_DEST (set)))
4257             i0_insn = link->insn, i0_val = SET_SRC (set);
4258
4259         record_value_for_reg (i0dest, i0_insn, i0_val);
4260
4261         if (! added_sets_0 && ! i0dest_in_i0src)
4262           INC_REG_N_SETS (REGNO (i0dest), -1);
4263       }
4264
4265     /* Update reg_stat[].nonzero_bits et al for any changes that may have
4266        been made to this insn.  The order of
4267        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
4268        can affect nonzero_bits of newpat */
4269     if (newi2pat)
4270       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4271     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4272   }
4273
4274   if (undobuf.other_insn != NULL_RTX)
4275     {
4276       if (dump_file)
4277         {
4278           fprintf (dump_file, "modifying other_insn ");
4279           dump_insn_slim (dump_file, undobuf.other_insn);
4280         }
4281       df_insn_rescan (undobuf.other_insn);
4282     }
4283
4284   if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4285     {
4286       if (dump_file)
4287         {
4288           fprintf (dump_file, "modifying insn i1 ");
4289           dump_insn_slim (dump_file, i0);
4290         }
4291       df_insn_rescan (i0);
4292     }
4293
4294   if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4295     {
4296       if (dump_file)
4297         {
4298           fprintf (dump_file, "modifying insn i1 ");
4299           dump_insn_slim (dump_file, i1);
4300         }
4301       df_insn_rescan (i1);
4302     }
4303
4304   if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4305     {
4306       if (dump_file)
4307         {
4308           fprintf (dump_file, "modifying insn i2 ");
4309           dump_insn_slim (dump_file, i2);
4310         }
4311       df_insn_rescan (i2);
4312     }
4313
4314   if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4315     {
4316       if (dump_file)
4317         {
4318           fprintf (dump_file, "modifying insn i3 ");
4319           dump_insn_slim (dump_file, i3);
4320         }
4321       df_insn_rescan (i3);
4322     }
4323
4324   /* Set new_direct_jump_p if a new return or simple jump instruction
4325      has been created.  Adjust the CFG accordingly.  */
4326
4327   if (returnjump_p (i3) || any_uncondjump_p (i3))
4328     {
4329       *new_direct_jump_p = 1;
4330       mark_jump_label (PATTERN (i3), i3, 0);
4331       update_cfg_for_uncondjump (i3);
4332     }
4333
4334   if (undobuf.other_insn != NULL_RTX
4335       && (returnjump_p (undobuf.other_insn)
4336           || any_uncondjump_p (undobuf.other_insn)))
4337     {
4338       *new_direct_jump_p = 1;
4339       update_cfg_for_uncondjump (undobuf.other_insn);
4340     }
4341
4342   /* A noop might also need cleaning up of CFG, if it comes from the
4343      simplification of a jump.  */
4344   if (JUMP_P (i3)
4345       && GET_CODE (newpat) == SET
4346       && SET_SRC (newpat) == pc_rtx
4347       && SET_DEST (newpat) == pc_rtx)
4348     {
4349       *new_direct_jump_p = 1;
4350       update_cfg_for_uncondjump (i3);
4351     }
4352
4353   if (undobuf.other_insn != NULL_RTX
4354       && JUMP_P (undobuf.other_insn)
4355       && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4356       && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4357       && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4358     {
4359       *new_direct_jump_p = 1;
4360       update_cfg_for_uncondjump (undobuf.other_insn);
4361     }
4362
4363   combine_successes++;
4364   undo_commit ();
4365
4366   if (added_links_insn
4367       && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4368       && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4369     return added_links_insn;
4370   else
4371     return newi2pat ? i2 : i3;
4372 }
4373 \f
4374 /* Undo all the modifications recorded in undobuf.  */
4375
4376 static void
4377 undo_all (void)
4378 {
4379   struct undo *undo, *next;
4380
4381   for (undo = undobuf.undos; undo; undo = next)
4382     {
4383       next = undo->next;
4384       switch (undo->kind)
4385         {
4386         case UNDO_RTX:
4387           *undo->where.r = undo->old_contents.r;
4388           break;
4389         case UNDO_INT:
4390           *undo->where.i = undo->old_contents.i;
4391           break;
4392         case UNDO_MODE:
4393           adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4394           break;
4395         case UNDO_LINKS:
4396           *undo->where.l = undo->old_contents.l;
4397           break;
4398         default:
4399           gcc_unreachable ();
4400         }
4401
4402       undo->next = undobuf.frees;
4403       undobuf.frees = undo;
4404     }
4405
4406   undobuf.undos = 0;
4407 }
4408
4409 /* We've committed to accepting the changes we made.  Move all
4410    of the undos to the free list.  */
4411
4412 static void
4413 undo_commit (void)
4414 {
4415   struct undo *undo, *next;
4416
4417   for (undo = undobuf.undos; undo; undo = next)
4418     {
4419       next = undo->next;
4420       undo->next = undobuf.frees;
4421       undobuf.frees = undo;
4422     }
4423   undobuf.undos = 0;
4424 }
4425 \f
4426 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4427    where we have an arithmetic expression and return that point.  LOC will
4428    be inside INSN.
4429
4430    try_combine will call this function to see if an insn can be split into
4431    two insns.  */
4432
4433 static rtx *
4434 find_split_point (rtx *loc, rtx insn, bool set_src)
4435 {
4436   rtx x = *loc;
4437   enum rtx_code code = GET_CODE (x);
4438   rtx *split;
4439   unsigned HOST_WIDE_INT len = 0;
4440   HOST_WIDE_INT pos = 0;
4441   int unsignedp = 0;
4442   rtx inner = NULL_RTX;
4443
4444   /* First special-case some codes.  */
4445   switch (code)
4446     {
4447     case SUBREG:
4448 #ifdef INSN_SCHEDULING
4449       /* If we are making a paradoxical SUBREG invalid, it becomes a split
4450          point.  */
4451       if (MEM_P (SUBREG_REG (x)))
4452         return loc;
4453 #endif
4454       return find_split_point (&SUBREG_REG (x), insn, false);
4455
4456     case MEM:
4457 #ifdef HAVE_lo_sum
4458       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4459          using LO_SUM and HIGH.  */
4460       if (GET_CODE (XEXP (x, 0)) == CONST
4461           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4462         {
4463           enum machine_mode address_mode = get_address_mode (x);
4464
4465           SUBST (XEXP (x, 0),
4466                  gen_rtx_LO_SUM (address_mode,
4467                                  gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4468                                  XEXP (x, 0)));
4469           return &XEXP (XEXP (x, 0), 0);
4470         }
4471 #endif
4472
4473       /* If we have a PLUS whose second operand is a constant and the
4474          address is not valid, perhaps will can split it up using
4475          the machine-specific way to split large constants.  We use
4476          the first pseudo-reg (one of the virtual regs) as a placeholder;
4477          it will not remain in the result.  */
4478       if (GET_CODE (XEXP (x, 0)) == PLUS
4479           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4480           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4481                                             MEM_ADDR_SPACE (x)))
4482         {
4483           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4484           rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4485                                                       XEXP (x, 0)),
4486                                          subst_insn);
4487
4488           /* This should have produced two insns, each of which sets our
4489              placeholder.  If the source of the second is a valid address,
4490              we can make put both sources together and make a split point
4491              in the middle.  */
4492
4493           if (seq
4494               && NEXT_INSN (seq) != NULL_RTX
4495               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4496               && NONJUMP_INSN_P (seq)
4497               && GET_CODE (PATTERN (seq)) == SET
4498               && SET_DEST (PATTERN (seq)) == reg
4499               && ! reg_mentioned_p (reg,
4500                                     SET_SRC (PATTERN (seq)))
4501               && NONJUMP_INSN_P (NEXT_INSN (seq))
4502               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4503               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4504               && memory_address_addr_space_p
4505                    (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4506                     MEM_ADDR_SPACE (x)))
4507             {
4508               rtx src1 = SET_SRC (PATTERN (seq));
4509               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4510
4511               /* Replace the placeholder in SRC2 with SRC1.  If we can
4512                  find where in SRC2 it was placed, that can become our
4513                  split point and we can replace this address with SRC2.
4514                  Just try two obvious places.  */
4515
4516               src2 = replace_rtx (src2, reg, src1);
4517               split = 0;
4518               if (XEXP (src2, 0) == src1)
4519                 split = &XEXP (src2, 0);
4520               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4521                        && XEXP (XEXP (src2, 0), 0) == src1)
4522                 split = &XEXP (XEXP (src2, 0), 0);
4523
4524               if (split)
4525                 {
4526                   SUBST (XEXP (x, 0), src2);
4527                   return split;
4528                 }
4529             }
4530
4531           /* If that didn't work, perhaps the first operand is complex and
4532              needs to be computed separately, so make a split point there.
4533              This will occur on machines that just support REG + CONST
4534              and have a constant moved through some previous computation.  */
4535
4536           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4537                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4538                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4539             return &XEXP (XEXP (x, 0), 0);
4540         }
4541
4542       /* If we have a PLUS whose first operand is complex, try computing it
4543          separately by making a split there.  */
4544       if (GET_CODE (XEXP (x, 0)) == PLUS
4545           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4546                                             MEM_ADDR_SPACE (x))
4547           && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4548           && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4549                 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4550         return &XEXP (XEXP (x, 0), 0);
4551       break;
4552
4553     case SET:
4554 #ifdef HAVE_cc0
4555       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4556          ZERO_EXTRACT, the most likely reason why this doesn't match is that
4557          we need to put the operand into a register.  So split at that
4558          point.  */
4559
4560       if (SET_DEST (x) == cc0_rtx
4561           && GET_CODE (SET_SRC (x)) != COMPARE
4562           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4563           && !OBJECT_P (SET_SRC (x))
4564           && ! (GET_CODE (SET_SRC (x)) == SUBREG
4565                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4566         return &SET_SRC (x);
4567 #endif
4568
4569       /* See if we can split SET_SRC as it stands.  */
4570       split = find_split_point (&SET_SRC (x), insn, true);
4571       if (split && split != &SET_SRC (x))
4572         return split;
4573
4574       /* See if we can split SET_DEST as it stands.  */
4575       split = find_split_point (&SET_DEST (x), insn, false);
4576       if (split && split != &SET_DEST (x))
4577         return split;
4578
4579       /* See if this is a bitfield assignment with everything constant.  If
4580          so, this is an IOR of an AND, so split it into that.  */
4581       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4582           && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4583           && CONST_INT_P (XEXP (SET_DEST (x), 1))
4584           && CONST_INT_P (XEXP (SET_DEST (x), 2))
4585           && CONST_INT_P (SET_SRC (x))
4586           && ((INTVAL (XEXP (SET_DEST (x), 1))
4587                + INTVAL (XEXP (SET_DEST (x), 2)))
4588               <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4589           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4590         {
4591           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4592           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4593           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4594           rtx dest = XEXP (SET_DEST (x), 0);
4595           enum machine_mode mode = GET_MODE (dest);
4596           unsigned HOST_WIDE_INT mask
4597             = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4598           rtx or_mask;
4599
4600           if (BITS_BIG_ENDIAN)
4601             pos = GET_MODE_PRECISION (mode) - len - pos;
4602
4603           or_mask = gen_int_mode (src << pos, mode);
4604           if (src == mask)
4605             SUBST (SET_SRC (x),
4606                    simplify_gen_binary (IOR, mode, dest, or_mask));
4607           else
4608             {
4609               rtx negmask = gen_int_mode (~(mask << pos), mode);
4610               SUBST (SET_SRC (x),
4611                      simplify_gen_binary (IOR, mode,
4612                                           simplify_gen_binary (AND, mode,
4613                                                                dest, negmask),
4614                                           or_mask));
4615             }
4616
4617           SUBST (SET_DEST (x), dest);
4618
4619           split = find_split_point (&SET_SRC (x), insn, true);
4620           if (split && split != &SET_SRC (x))
4621             return split;
4622         }
4623
4624       /* Otherwise, see if this is an operation that we can split into two.
4625          If so, try to split that.  */
4626       code = GET_CODE (SET_SRC (x));
4627
4628       switch (code)
4629         {
4630         case AND:
4631           /* If we are AND'ing with a large constant that is only a single
4632              bit and the result is only being used in a context where we
4633              need to know if it is zero or nonzero, replace it with a bit
4634              extraction.  This will avoid the large constant, which might
4635              have taken more than one insn to make.  If the constant were
4636              not a valid argument to the AND but took only one insn to make,
4637              this is no worse, but if it took more than one insn, it will
4638              be better.  */
4639
4640           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4641               && REG_P (XEXP (SET_SRC (x), 0))
4642               && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4643               && REG_P (SET_DEST (x))
4644               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4645               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4646               && XEXP (*split, 0) == SET_DEST (x)
4647               && XEXP (*split, 1) == const0_rtx)
4648             {
4649               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4650                                                 XEXP (SET_SRC (x), 0),
4651                                                 pos, NULL_RTX, 1, 1, 0, 0);
4652               if (extraction != 0)
4653                 {
4654                   SUBST (SET_SRC (x), extraction);
4655                   return find_split_point (loc, insn, false);
4656                 }
4657             }
4658           break;
4659
4660         case NE:
4661           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4662              is known to be on, this can be converted into a NEG of a shift.  */
4663           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4664               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4665               && 1 <= (pos = exact_log2
4666                        (nonzero_bits (XEXP (SET_SRC (x), 0),
4667                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
4668             {
4669               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4670
4671               SUBST (SET_SRC (x),
4672                      gen_rtx_NEG (mode,
4673                                   gen_rtx_LSHIFTRT (mode,
4674                                                     XEXP (SET_SRC (x), 0),
4675                                                     GEN_INT (pos))));
4676
4677               split = find_split_point (&SET_SRC (x), insn, true);
4678               if (split && split != &SET_SRC (x))
4679                 return split;
4680             }
4681           break;
4682
4683         case SIGN_EXTEND:
4684           inner = XEXP (SET_SRC (x), 0);
4685
4686           /* We can't optimize if either mode is a partial integer
4687              mode as we don't know how many bits are significant
4688              in those modes.  */
4689           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4690               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4691             break;
4692
4693           pos = 0;
4694           len = GET_MODE_PRECISION (GET_MODE (inner));
4695           unsignedp = 0;
4696           break;
4697
4698         case SIGN_EXTRACT:
4699         case ZERO_EXTRACT:
4700           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4701               && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4702             {
4703               inner = XEXP (SET_SRC (x), 0);
4704               len = INTVAL (XEXP (SET_SRC (x), 1));
4705               pos = INTVAL (XEXP (SET_SRC (x), 2));
4706
4707               if (BITS_BIG_ENDIAN)
4708                 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4709               unsignedp = (code == ZERO_EXTRACT);
4710             }
4711           break;
4712
4713         default:
4714           break;
4715         }
4716
4717       if (len && pos >= 0
4718           && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4719         {
4720           enum machine_mode mode = GET_MODE (SET_SRC (x));
4721
4722           /* For unsigned, we have a choice of a shift followed by an
4723              AND or two shifts.  Use two shifts for field sizes where the
4724              constant might be too large.  We assume here that we can
4725              always at least get 8-bit constants in an AND insn, which is
4726              true for every current RISC.  */
4727
4728           if (unsignedp && len <= 8)
4729             {
4730               SUBST (SET_SRC (x),
4731                      gen_rtx_AND (mode,
4732                                   gen_rtx_LSHIFTRT
4733                                   (mode, gen_lowpart (mode, inner),
4734                                    GEN_INT (pos)),
4735                                   GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4736                                            - 1)));
4737
4738               split = find_split_point (&SET_SRC (x), insn, true);
4739               if (split && split != &SET_SRC (x))
4740                 return split;
4741             }
4742           else
4743             {
4744               SUBST (SET_SRC (x),
4745                      gen_rtx_fmt_ee
4746                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4747                       gen_rtx_ASHIFT (mode,
4748                                       gen_lowpart (mode, inner),
4749                                       GEN_INT (GET_MODE_PRECISION (mode)
4750                                                - len - pos)),
4751                       GEN_INT (GET_MODE_PRECISION (mode) - len)));
4752
4753               split = find_split_point (&SET_SRC (x), insn, true);
4754               if (split && split != &SET_SRC (x))
4755                 return split;
4756             }
4757         }
4758
4759       /* See if this is a simple operation with a constant as the second
4760          operand.  It might be that this constant is out of range and hence
4761          could be used as a split point.  */
4762       if (BINARY_P (SET_SRC (x))
4763           && CONSTANT_P (XEXP (SET_SRC (x), 1))
4764           && (OBJECT_P (XEXP (SET_SRC (x), 0))
4765               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4766                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4767         return &XEXP (SET_SRC (x), 1);
4768
4769       /* Finally, see if this is a simple operation with its first operand
4770          not in a register.  The operation might require this operand in a
4771          register, so return it as a split point.  We can always do this
4772          because if the first operand were another operation, we would have
4773          already found it as a split point.  */
4774       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4775           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4776         return &XEXP (SET_SRC (x), 0);
4777
4778       return 0;
4779
4780     case AND:
4781     case IOR:
4782       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4783          it is better to write this as (not (ior A B)) so we can split it.
4784          Similarly for IOR.  */
4785       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4786         {
4787           SUBST (*loc,
4788                  gen_rtx_NOT (GET_MODE (x),
4789                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4790                                               GET_MODE (x),
4791                                               XEXP (XEXP (x, 0), 0),
4792                                               XEXP (XEXP (x, 1), 0))));
4793           return find_split_point (loc, insn, set_src);
4794         }
4795
4796       /* Many RISC machines have a large set of logical insns.  If the
4797          second operand is a NOT, put it first so we will try to split the
4798          other operand first.  */
4799       if (GET_CODE (XEXP (x, 1)) == NOT)
4800         {
4801           rtx tem = XEXP (x, 0);
4802           SUBST (XEXP (x, 0), XEXP (x, 1));
4803           SUBST (XEXP (x, 1), tem);
4804         }
4805       break;
4806
4807     case PLUS:
4808     case MINUS:
4809       /* Canonicalization can produce (minus A (mult B C)), where C is a
4810          constant.  It may be better to try splitting (plus (mult B -C) A)
4811          instead if this isn't a multiply by a power of two.  */
4812       if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4813           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4814           && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4815         {
4816           enum machine_mode mode = GET_MODE (x);
4817           unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4818           HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4819           SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4820                                                          XEXP (XEXP (x, 1), 0),
4821                                                          GEN_INT (other_int)),
4822                                      XEXP (x, 0)));
4823           return find_split_point (loc, insn, set_src);
4824         }
4825
4826       /* Split at a multiply-accumulate instruction.  However if this is
4827          the SET_SRC, we likely do not have such an instruction and it's
4828          worthless to try this split.  */
4829       if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4830         return loc;
4831
4832     default:
4833       break;
4834     }
4835
4836   /* Otherwise, select our actions depending on our rtx class.  */
4837   switch (GET_RTX_CLASS (code))
4838     {
4839     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
4840     case RTX_TERNARY:
4841       split = find_split_point (&XEXP (x, 2), insn, false);
4842       if (split)
4843         return split;
4844       /* ... fall through ...  */
4845     case RTX_BIN_ARITH:
4846     case RTX_COMM_ARITH:
4847     case RTX_COMPARE:
4848     case RTX_COMM_COMPARE:
4849       split = find_split_point (&XEXP (x, 1), insn, false);
4850       if (split)
4851         return split;
4852       /* ... fall through ...  */
4853     case RTX_UNARY:
4854       /* Some machines have (and (shift ...) ...) insns.  If X is not
4855          an AND, but XEXP (X, 0) is, use it as our split point.  */
4856       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4857         return &XEXP (x, 0);
4858
4859       split = find_split_point (&XEXP (x, 0), insn, false);
4860       if (split)
4861         return split;
4862       return loc;
4863
4864     default:
4865       /* Otherwise, we don't have a split point.  */
4866       return 0;
4867     }
4868 }
4869 \f
4870 /* Throughout X, replace FROM with TO, and return the result.
4871    The result is TO if X is FROM;
4872    otherwise the result is X, but its contents may have been modified.
4873    If they were modified, a record was made in undobuf so that
4874    undo_all will (among other things) return X to its original state.
4875
4876    If the number of changes necessary is too much to record to undo,
4877    the excess changes are not made, so the result is invalid.
4878    The changes already made can still be undone.
4879    undobuf.num_undo is incremented for such changes, so by testing that
4880    the caller can tell whether the result is valid.
4881
4882    `n_occurrences' is incremented each time FROM is replaced.
4883
4884    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4885
4886    IN_COND is nonzero if we are at the top level of a condition.
4887
4888    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
4889    by copying if `n_occurrences' is nonzero.  */
4890
4891 static rtx
4892 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
4893 {
4894   enum rtx_code code = GET_CODE (x);
4895   enum machine_mode op0_mode = VOIDmode;
4896   const char *fmt;
4897   int len, i;
4898   rtx new_rtx;
4899
4900 /* Two expressions are equal if they are identical copies of a shared
4901    RTX or if they are both registers with the same register number
4902    and mode.  */
4903
4904 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
4905   ((X) == (Y)                                           \
4906    || (REG_P (X) && REG_P (Y)   \
4907        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4908
4909   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4910     {
4911       n_occurrences++;
4912       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4913     }
4914
4915   /* If X and FROM are the same register but different modes, they
4916      will not have been seen as equal above.  However, the log links code
4917      will make a LOG_LINKS entry for that case.  If we do nothing, we
4918      will try to rerecognize our original insn and, when it succeeds,
4919      we will delete the feeding insn, which is incorrect.
4920
4921      So force this insn not to match in this (rare) case.  */
4922   if (! in_dest && code == REG && REG_P (from)
4923       && reg_overlap_mentioned_p (x, from))
4924     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4925
4926   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4927      of which may contain things that can be combined.  */
4928   if (code != MEM && code != LO_SUM && OBJECT_P (x))
4929     return x;
4930
4931   /* It is possible to have a subexpression appear twice in the insn.
4932      Suppose that FROM is a register that appears within TO.
4933      Then, after that subexpression has been scanned once by `subst',
4934      the second time it is scanned, TO may be found.  If we were
4935      to scan TO here, we would find FROM within it and create a
4936      self-referent rtl structure which is completely wrong.  */
4937   if (COMBINE_RTX_EQUAL_P (x, to))
4938     return to;
4939
4940   /* Parallel asm_operands need special attention because all of the
4941      inputs are shared across the arms.  Furthermore, unsharing the
4942      rtl results in recognition failures.  Failure to handle this case
4943      specially can result in circular rtl.
4944
4945      Solve this by doing a normal pass across the first entry of the
4946      parallel, and only processing the SET_DESTs of the subsequent
4947      entries.  Ug.  */
4948
4949   if (code == PARALLEL
4950       && GET_CODE (XVECEXP (x, 0, 0)) == SET
4951       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4952     {
4953       new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
4954
4955       /* If this substitution failed, this whole thing fails.  */
4956       if (GET_CODE (new_rtx) == CLOBBER
4957           && XEXP (new_rtx, 0) == const0_rtx)
4958         return new_rtx;
4959
4960       SUBST (XVECEXP (x, 0, 0), new_rtx);
4961
4962       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4963         {
4964           rtx dest = SET_DEST (XVECEXP (x, 0, i));
4965
4966           if (!REG_P (dest)
4967               && GET_CODE (dest) != CC0
4968               && GET_CODE (dest) != PC)
4969             {
4970               new_rtx = subst (dest, from, to, 0, 0, unique_copy);
4971
4972               /* If this substitution failed, this whole thing fails.  */
4973               if (GET_CODE (new_rtx) == CLOBBER
4974                   && XEXP (new_rtx, 0) == const0_rtx)
4975                 return new_rtx;
4976
4977               SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4978             }
4979         }
4980     }
4981   else
4982     {
4983       len = GET_RTX_LENGTH (code);
4984       fmt = GET_RTX_FORMAT (code);
4985
4986       /* We don't need to process a SET_DEST that is a register, CC0,
4987          or PC, so set up to skip this common case.  All other cases
4988          where we want to suppress replacing something inside a
4989          SET_SRC are handled via the IN_DEST operand.  */
4990       if (code == SET
4991           && (REG_P (SET_DEST (x))
4992               || GET_CODE (SET_DEST (x)) == CC0
4993               || GET_CODE (SET_DEST (x)) == PC))
4994         fmt = "ie";
4995
4996       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4997          constant.  */
4998       if (fmt[0] == 'e')
4999         op0_mode = GET_MODE (XEXP (x, 0));
5000
5001       for (i = 0; i < len; i++)
5002         {
5003           if (fmt[i] == 'E')
5004             {
5005               int j;
5006               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5007                 {
5008                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5009                     {
5010                       new_rtx = (unique_copy && n_occurrences
5011                              ? copy_rtx (to) : to);
5012                       n_occurrences++;
5013                     }
5014                   else
5015                     {
5016                       new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5017                                        unique_copy);
5018
5019                       /* If this substitution failed, this whole thing
5020                          fails.  */
5021                       if (GET_CODE (new_rtx) == CLOBBER
5022                           && XEXP (new_rtx, 0) == const0_rtx)
5023                         return new_rtx;
5024                     }
5025
5026                   SUBST (XVECEXP (x, i, j), new_rtx);
5027                 }
5028             }
5029           else if (fmt[i] == 'e')
5030             {
5031               /* If this is a register being set, ignore it.  */
5032               new_rtx = XEXP (x, i);
5033               if (in_dest
5034                   && i == 0
5035                   && (((code == SUBREG || code == ZERO_EXTRACT)
5036                        && REG_P (new_rtx))
5037                       || code == STRICT_LOW_PART))
5038                 ;
5039
5040               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5041                 {
5042                   /* In general, don't install a subreg involving two
5043                      modes not tieable.  It can worsen register
5044                      allocation, and can even make invalid reload
5045                      insns, since the reg inside may need to be copied
5046                      from in the outside mode, and that may be invalid
5047                      if it is an fp reg copied in integer mode.
5048
5049                      We allow two exceptions to this: It is valid if
5050                      it is inside another SUBREG and the mode of that
5051                      SUBREG and the mode of the inside of TO is
5052                      tieable and it is valid if X is a SET that copies
5053                      FROM to CC0.  */
5054
5055                   if (GET_CODE (to) == SUBREG
5056                       && ! MODES_TIEABLE_P (GET_MODE (to),
5057                                             GET_MODE (SUBREG_REG (to)))
5058                       && ! (code == SUBREG
5059                             && MODES_TIEABLE_P (GET_MODE (x),
5060                                                 GET_MODE (SUBREG_REG (to))))
5061 #ifdef HAVE_cc0
5062                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5063 #endif
5064                       )
5065                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5066
5067 #ifdef CANNOT_CHANGE_MODE_CLASS
5068                   if (code == SUBREG
5069                       && REG_P (to)
5070                       && REGNO (to) < FIRST_PSEUDO_REGISTER
5071                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5072                                                    GET_MODE (to),
5073                                                    GET_MODE (x)))
5074                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5075 #endif
5076
5077                   new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5078                   n_occurrences++;
5079                 }
5080               else
5081                 /* If we are in a SET_DEST, suppress most cases unless we
5082                    have gone inside a MEM, in which case we want to
5083                    simplify the address.  We assume here that things that
5084                    are actually part of the destination have their inner
5085                    parts in the first expression.  This is true for SUBREG,
5086                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5087                    things aside from REG and MEM that should appear in a
5088                    SET_DEST.  */
5089                 new_rtx = subst (XEXP (x, i), from, to,
5090                              (((in_dest
5091                                 && (code == SUBREG || code == STRICT_LOW_PART
5092                                     || code == ZERO_EXTRACT))
5093                                || code == SET)
5094                               && i == 0),
5095                                  code == IF_THEN_ELSE && i == 0,
5096                                  unique_copy);
5097
5098               /* If we found that we will have to reject this combination,
5099                  indicate that by returning the CLOBBER ourselves, rather than
5100                  an expression containing it.  This will speed things up as
5101                  well as prevent accidents where two CLOBBERs are considered
5102                  to be equal, thus producing an incorrect simplification.  */
5103
5104               if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5105                 return new_rtx;
5106
5107               if (GET_CODE (x) == SUBREG
5108                   && (CONST_INT_P (new_rtx) || CONST_DOUBLE_AS_INT_P (new_rtx)))
5109                 {
5110                   enum machine_mode mode = GET_MODE (x);
5111
5112                   x = simplify_subreg (GET_MODE (x), new_rtx,
5113                                        GET_MODE (SUBREG_REG (x)),
5114                                        SUBREG_BYTE (x));
5115                   if (! x)
5116                     x = gen_rtx_CLOBBER (mode, const0_rtx);
5117                 }
5118               else if (CONST_INT_P (new_rtx)
5119                        && GET_CODE (x) == ZERO_EXTEND)
5120                 {
5121                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5122                                                 new_rtx, GET_MODE (XEXP (x, 0)));
5123                   gcc_assert (x);
5124                 }
5125               else
5126                 SUBST (XEXP (x, i), new_rtx);
5127             }
5128         }
5129     }
5130
5131   /* Check if we are loading something from the constant pool via float
5132      extension; in this case we would undo compress_float_constant
5133      optimization and degenerate constant load to an immediate value.  */
5134   if (GET_CODE (x) == FLOAT_EXTEND
5135       && MEM_P (XEXP (x, 0))
5136       && MEM_READONLY_P (XEXP (x, 0)))
5137     {
5138       rtx tmp = avoid_constant_pool_reference (x);
5139       if (x != tmp)
5140         return x;
5141     }
5142
5143   /* Try to simplify X.  If the simplification changed the code, it is likely
5144      that further simplification will help, so loop, but limit the number
5145      of repetitions that will be performed.  */
5146
5147   for (i = 0; i < 4; i++)
5148     {
5149       /* If X is sufficiently simple, don't bother trying to do anything
5150          with it.  */
5151       if (code != CONST_INT && code != REG && code != CLOBBER)
5152         x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5153
5154       if (GET_CODE (x) == code)
5155         break;
5156
5157       code = GET_CODE (x);
5158
5159       /* We no longer know the original mode of operand 0 since we
5160          have changed the form of X)  */
5161       op0_mode = VOIDmode;
5162     }
5163
5164   return x;
5165 }
5166 \f
5167 /* Simplify X, a piece of RTL.  We just operate on the expression at the
5168    outer level; call `subst' to simplify recursively.  Return the new
5169    expression.
5170
5171    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
5172    if we are inside a SET_DEST.  IN_COND is nonzero if we are at the top level
5173    of a condition.  */
5174
5175 static rtx
5176 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5177                       int in_cond)
5178 {
5179   enum rtx_code code = GET_CODE (x);
5180   enum machine_mode mode = GET_MODE (x);
5181   rtx temp;
5182   int i;
5183
5184   /* If this is a commutative operation, put a constant last and a complex
5185      expression first.  We don't need to do this for comparisons here.  */
5186   if (COMMUTATIVE_ARITH_P (x)
5187       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5188     {
5189       temp = XEXP (x, 0);
5190       SUBST (XEXP (x, 0), XEXP (x, 1));
5191       SUBST (XEXP (x, 1), temp);
5192     }
5193
5194   /* If this is a simple operation applied to an IF_THEN_ELSE, try
5195      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
5196      things.  Check for cases where both arms are testing the same
5197      condition.
5198
5199      Don't do anything if all operands are very simple.  */
5200
5201   if ((BINARY_P (x)
5202        && ((!OBJECT_P (XEXP (x, 0))
5203             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5204                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5205            || (!OBJECT_P (XEXP (x, 1))
5206                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5207                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5208       || (UNARY_P (x)
5209           && (!OBJECT_P (XEXP (x, 0))
5210                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5211                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5212     {
5213       rtx cond, true_rtx, false_rtx;
5214
5215       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5216       if (cond != 0
5217           /* If everything is a comparison, what we have is highly unlikely
5218              to be simpler, so don't use it.  */
5219           && ! (COMPARISON_P (x)
5220                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5221         {
5222           rtx cop1 = const0_rtx;
5223           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5224
5225           if (cond_code == NE && COMPARISON_P (cond))
5226             return x;
5227
5228           /* Simplify the alternative arms; this may collapse the true and
5229              false arms to store-flag values.  Be careful to use copy_rtx
5230              here since true_rtx or false_rtx might share RTL with x as a
5231              result of the if_then_else_cond call above.  */
5232           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5233           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5234
5235           /* If true_rtx and false_rtx are not general_operands, an if_then_else
5236              is unlikely to be simpler.  */
5237           if (general_operand (true_rtx, VOIDmode)
5238               && general_operand (false_rtx, VOIDmode))
5239             {
5240               enum rtx_code reversed;
5241
5242               /* Restarting if we generate a store-flag expression will cause
5243                  us to loop.  Just drop through in this case.  */
5244
5245               /* If the result values are STORE_FLAG_VALUE and zero, we can
5246                  just make the comparison operation.  */
5247               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5248                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5249                                              cond, cop1);
5250               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5251                        && ((reversed = reversed_comparison_code_parts
5252                                         (cond_code, cond, cop1, NULL))
5253                            != UNKNOWN))
5254                 x = simplify_gen_relational (reversed, mode, VOIDmode,
5255                                              cond, cop1);
5256
5257               /* Likewise, we can make the negate of a comparison operation
5258                  if the result values are - STORE_FLAG_VALUE and zero.  */
5259               else if (CONST_INT_P (true_rtx)
5260                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5261                        && false_rtx == const0_rtx)
5262                 x = simplify_gen_unary (NEG, mode,
5263                                         simplify_gen_relational (cond_code,
5264                                                                  mode, VOIDmode,
5265                                                                  cond, cop1),
5266                                         mode);
5267               else if (CONST_INT_P (false_rtx)
5268                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5269                        && true_rtx == const0_rtx
5270                        && ((reversed = reversed_comparison_code_parts
5271                                         (cond_code, cond, cop1, NULL))
5272                            != UNKNOWN))
5273                 x = simplify_gen_unary (NEG, mode,
5274                                         simplify_gen_relational (reversed,
5275                                                                  mode, VOIDmode,
5276                                                                  cond, cop1),
5277                                         mode);
5278               else
5279                 return gen_rtx_IF_THEN_ELSE (mode,
5280                                              simplify_gen_relational (cond_code,
5281                                                                       mode,
5282                                                                       VOIDmode,
5283                                                                       cond,
5284                                                                       cop1),
5285                                              true_rtx, false_rtx);
5286
5287               code = GET_CODE (x);
5288               op0_mode = VOIDmode;
5289             }
5290         }
5291     }
5292
5293   /* Try to fold this expression in case we have constants that weren't
5294      present before.  */
5295   temp = 0;
5296   switch (GET_RTX_CLASS (code))
5297     {
5298     case RTX_UNARY:
5299       if (op0_mode == VOIDmode)
5300         op0_mode = GET_MODE (XEXP (x, 0));
5301       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5302       break;
5303     case RTX_COMPARE:
5304     case RTX_COMM_COMPARE:
5305       {
5306         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5307         if (cmp_mode == VOIDmode)
5308           {
5309             cmp_mode = GET_MODE (XEXP (x, 1));
5310             if (cmp_mode == VOIDmode)
5311               cmp_mode = op0_mode;
5312           }
5313         temp = simplify_relational_operation (code, mode, cmp_mode,
5314                                               XEXP (x, 0), XEXP (x, 1));
5315       }
5316       break;
5317     case RTX_COMM_ARITH:
5318     case RTX_BIN_ARITH:
5319       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5320       break;
5321     case RTX_BITFIELD_OPS:
5322     case RTX_TERNARY:
5323       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5324                                          XEXP (x, 1), XEXP (x, 2));
5325       break;
5326     default:
5327       break;
5328     }
5329
5330   if (temp)
5331     {
5332       x = temp;
5333       code = GET_CODE (temp);
5334       op0_mode = VOIDmode;
5335       mode = GET_MODE (temp);
5336     }
5337
5338   /* First see if we can apply the inverse distributive law.  */
5339   if (code == PLUS || code == MINUS
5340       || code == AND || code == IOR || code == XOR)
5341     {
5342       x = apply_distributive_law (x);
5343       code = GET_CODE (x);
5344       op0_mode = VOIDmode;
5345     }
5346
5347   /* If CODE is an associative operation not otherwise handled, see if we
5348      can associate some operands.  This can win if they are constants or
5349      if they are logically related (i.e. (a & b) & a).  */
5350   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5351        || code == AND || code == IOR || code == XOR
5352        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5353       && ((INTEGRAL_MODE_P (mode) && code != DIV)
5354           || (flag_associative_math && FLOAT_MODE_P (mode))))
5355     {
5356       if (GET_CODE (XEXP (x, 0)) == code)
5357         {
5358           rtx other = XEXP (XEXP (x, 0), 0);
5359           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5360           rtx inner_op1 = XEXP (x, 1);
5361           rtx inner;
5362
5363           /* Make sure we pass the constant operand if any as the second
5364              one if this is a commutative operation.  */
5365           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5366             {
5367               rtx tem = inner_op0;
5368               inner_op0 = inner_op1;
5369               inner_op1 = tem;
5370             }
5371           inner = simplify_binary_operation (code == MINUS ? PLUS
5372                                              : code == DIV ? MULT
5373                                              : code,
5374                                              mode, inner_op0, inner_op1);
5375
5376           /* For commutative operations, try the other pair if that one
5377              didn't simplify.  */
5378           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5379             {
5380               other = XEXP (XEXP (x, 0), 1);
5381               inner = simplify_binary_operation (code, mode,
5382                                                  XEXP (XEXP (x, 0), 0),
5383                                                  XEXP (x, 1));
5384             }
5385
5386           if (inner)
5387             return simplify_gen_binary (code, mode, other, inner);
5388         }
5389     }
5390
5391   /* A little bit of algebraic simplification here.  */
5392   switch (code)
5393     {
5394     case MEM:
5395       /* Ensure that our address has any ASHIFTs converted to MULT in case
5396          address-recognizing predicates are called later.  */
5397       temp = make_compound_operation (XEXP (x, 0), MEM);
5398       SUBST (XEXP (x, 0), temp);
5399       break;
5400
5401     case SUBREG:
5402       if (op0_mode == VOIDmode)
5403         op0_mode = GET_MODE (SUBREG_REG (x));
5404
5405       /* See if this can be moved to simplify_subreg.  */
5406       if (CONSTANT_P (SUBREG_REG (x))
5407           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5408              /* Don't call gen_lowpart if the inner mode
5409                 is VOIDmode and we cannot simplify it, as SUBREG without
5410                 inner mode is invalid.  */
5411           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5412               || gen_lowpart_common (mode, SUBREG_REG (x))))
5413         return gen_lowpart (mode, SUBREG_REG (x));
5414
5415       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5416         break;
5417       {
5418         rtx temp;
5419         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5420                                 SUBREG_BYTE (x));
5421         if (temp)
5422           return temp;
5423       }
5424
5425       /* Don't change the mode of the MEM if that would change the meaning
5426          of the address.  */
5427       if (MEM_P (SUBREG_REG (x))
5428           && (MEM_VOLATILE_P (SUBREG_REG (x))
5429               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5430                                            MEM_ADDR_SPACE (SUBREG_REG (x)))))
5431         return gen_rtx_CLOBBER (mode, const0_rtx);
5432
5433       /* Note that we cannot do any narrowing for non-constants since
5434          we might have been counting on using the fact that some bits were
5435          zero.  We now do this in the SET.  */
5436
5437       break;
5438
5439     case NEG:
5440       temp = expand_compound_operation (XEXP (x, 0));
5441
5442       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5443          replaced by (lshiftrt X C).  This will convert
5444          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
5445
5446       if (GET_CODE (temp) == ASHIFTRT
5447           && CONST_INT_P (XEXP (temp, 1))
5448           && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5449         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5450                                      INTVAL (XEXP (temp, 1)));
5451
5452       /* If X has only a single bit that might be nonzero, say, bit I, convert
5453          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5454          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
5455          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
5456          or a SUBREG of one since we'd be making the expression more
5457          complex if it was just a register.  */
5458
5459       if (!REG_P (temp)
5460           && ! (GET_CODE (temp) == SUBREG
5461                 && REG_P (SUBREG_REG (temp)))
5462           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5463         {
5464           rtx temp1 = simplify_shift_const
5465             (NULL_RTX, ASHIFTRT, mode,
5466              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5467                                    GET_MODE_PRECISION (mode) - 1 - i),
5468              GET_MODE_PRECISION (mode) - 1 - i);
5469
5470           /* If all we did was surround TEMP with the two shifts, we
5471              haven't improved anything, so don't use it.  Otherwise,
5472              we are better off with TEMP1.  */
5473           if (GET_CODE (temp1) != ASHIFTRT
5474               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5475               || XEXP (XEXP (temp1, 0), 0) != temp)
5476             return temp1;
5477         }
5478       break;
5479
5480     case TRUNCATE:
5481       /* We can't handle truncation to a partial integer mode here
5482          because we don't know the real bitsize of the partial
5483          integer mode.  */
5484       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5485         break;
5486
5487       if (HWI_COMPUTABLE_MODE_P (mode))
5488         SUBST (XEXP (x, 0),
5489                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5490                               GET_MODE_MASK (mode), 0));
5491
5492       /* We can truncate a constant value and return it.  */
5493       if (CONST_INT_P (XEXP (x, 0)))
5494         return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5495
5496       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5497          whose value is a comparison can be replaced with a subreg if
5498          STORE_FLAG_VALUE permits.  */
5499       if (HWI_COMPUTABLE_MODE_P (mode)
5500           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5501           && (temp = get_last_value (XEXP (x, 0)))
5502           && COMPARISON_P (temp))
5503         return gen_lowpart (mode, XEXP (x, 0));
5504       break;
5505
5506     case CONST:
5507       /* (const (const X)) can become (const X).  Do it this way rather than
5508          returning the inner CONST since CONST can be shared with a
5509          REG_EQUAL note.  */
5510       if (GET_CODE (XEXP (x, 0)) == CONST)
5511         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5512       break;
5513
5514 #ifdef HAVE_lo_sum
5515     case LO_SUM:
5516       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
5517          can add in an offset.  find_split_point will split this address up
5518          again if it doesn't match.  */
5519       if (GET_CODE (XEXP (x, 0)) == HIGH
5520           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5521         return XEXP (x, 1);
5522       break;
5523 #endif
5524
5525     case PLUS:
5526       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5527          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5528          bit-field and can be replaced by either a sign_extend or a
5529          sign_extract.  The `and' may be a zero_extend and the two
5530          <c>, -<c> constants may be reversed.  */
5531       if (GET_CODE (XEXP (x, 0)) == XOR
5532           && CONST_INT_P (XEXP (x, 1))
5533           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5534           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5535           && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5536               || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5537           && HWI_COMPUTABLE_MODE_P (mode)
5538           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5539                && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5540                && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5541                    == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5542               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5543                   && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5544                       == (unsigned int) i + 1))))
5545         return simplify_shift_const
5546           (NULL_RTX, ASHIFTRT, mode,
5547            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5548                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
5549                                  GET_MODE_PRECISION (mode) - (i + 1)),
5550            GET_MODE_PRECISION (mode) - (i + 1));
5551
5552       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5553          can become (ashiftrt (ashift (xor x 1) C) C) where C is
5554          the bitsize of the mode - 1.  This allows simplification of
5555          "a = (b & 8) == 0;"  */
5556       if (XEXP (x, 1) == constm1_rtx
5557           && !REG_P (XEXP (x, 0))
5558           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5559                 && REG_P (SUBREG_REG (XEXP (x, 0))))
5560           && nonzero_bits (XEXP (x, 0), mode) == 1)
5561         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5562            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5563                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5564                                  GET_MODE_PRECISION (mode) - 1),
5565            GET_MODE_PRECISION (mode) - 1);
5566
5567       /* If we are adding two things that have no bits in common, convert
5568          the addition into an IOR.  This will often be further simplified,
5569          for example in cases like ((a & 1) + (a & 2)), which can
5570          become a & 3.  */
5571
5572       if (HWI_COMPUTABLE_MODE_P (mode)
5573           && (nonzero_bits (XEXP (x, 0), mode)
5574               & nonzero_bits (XEXP (x, 1), mode)) == 0)
5575         {
5576           /* Try to simplify the expression further.  */
5577           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5578           temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5579
5580           /* If we could, great.  If not, do not go ahead with the IOR
5581              replacement, since PLUS appears in many special purpose
5582              address arithmetic instructions.  */
5583           if (GET_CODE (temp) != CLOBBER
5584               && (GET_CODE (temp) != IOR
5585                   || ((XEXP (temp, 0) != XEXP (x, 0)
5586                        || XEXP (temp, 1) != XEXP (x, 1))
5587                       && (XEXP (temp, 0) != XEXP (x, 1)
5588                           || XEXP (temp, 1) != XEXP (x, 0)))))
5589             return temp;
5590         }
5591       break;
5592
5593     case MINUS:
5594       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5595          (and <foo> (const_int pow2-1))  */
5596       if (GET_CODE (XEXP (x, 1)) == AND
5597           && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5598           && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5599           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5600         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5601                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5602       break;
5603
5604     case MULT:
5605       /* If we have (mult (plus A B) C), apply the distributive law and then
5606          the inverse distributive law to see if things simplify.  This
5607          occurs mostly in addresses, often when unrolling loops.  */
5608
5609       if (GET_CODE (XEXP (x, 0)) == PLUS)
5610         {
5611           rtx result = distribute_and_simplify_rtx (x, 0);
5612           if (result)
5613             return result;
5614         }
5615
5616       /* Try simplify a*(b/c) as (a*b)/c.  */
5617       if (FLOAT_MODE_P (mode) && flag_associative_math
5618           && GET_CODE (XEXP (x, 0)) == DIV)
5619         {
5620           rtx tem = simplify_binary_operation (MULT, mode,
5621                                                XEXP (XEXP (x, 0), 0),
5622                                                XEXP (x, 1));
5623           if (tem)
5624             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5625         }
5626       break;
5627
5628     case UDIV:
5629       /* If this is a divide by a power of two, treat it as a shift if
5630          its first operand is a shift.  */
5631       if (CONST_INT_P (XEXP (x, 1))
5632           && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5633           && (GET_CODE (XEXP (x, 0)) == ASHIFT
5634               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5635               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5636               || GET_CODE (XEXP (x, 0)) == ROTATE
5637               || GET_CODE (XEXP (x, 0)) == ROTATERT))
5638         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5639       break;
5640
5641     case EQ:  case NE:
5642     case GT:  case GTU:  case GE:  case GEU:
5643     case LT:  case LTU:  case LE:  case LEU:
5644     case UNEQ:  case LTGT:
5645     case UNGT:  case UNGE:
5646     case UNLT:  case UNLE:
5647     case UNORDERED: case ORDERED:
5648       /* If the first operand is a condition code, we can't do anything
5649          with it.  */
5650       if (GET_CODE (XEXP (x, 0)) == COMPARE
5651           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5652               && ! CC0_P (XEXP (x, 0))))
5653         {
5654           rtx op0 = XEXP (x, 0);
5655           rtx op1 = XEXP (x, 1);
5656           enum rtx_code new_code;
5657
5658           if (GET_CODE (op0) == COMPARE)
5659             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5660
5661           /* Simplify our comparison, if possible.  */
5662           new_code = simplify_comparison (code, &op0, &op1);
5663
5664           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5665              if only the low-order bit is possibly nonzero in X (such as when
5666              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
5667              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
5668              known to be either 0 or -1, NE becomes a NEG and EQ becomes
5669              (plus X 1).
5670
5671              Remove any ZERO_EXTRACT we made when thinking this was a
5672              comparison.  It may now be simpler to use, e.g., an AND.  If a
5673              ZERO_EXTRACT is indeed appropriate, it will be placed back by
5674              the call to make_compound_operation in the SET case.
5675
5676              Don't apply these optimizations if the caller would
5677              prefer a comparison rather than a value.
5678              E.g., for the condition in an IF_THEN_ELSE most targets need
5679              an explicit comparison.  */
5680
5681           if (in_cond)
5682             ;
5683
5684           else if (STORE_FLAG_VALUE == 1
5685               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5686               && op1 == const0_rtx
5687               && mode == GET_MODE (op0)
5688               && nonzero_bits (op0, mode) == 1)
5689             return gen_lowpart (mode,
5690                                 expand_compound_operation (op0));
5691
5692           else if (STORE_FLAG_VALUE == 1
5693                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5694                    && op1 == const0_rtx
5695                    && mode == GET_MODE (op0)
5696                    && (num_sign_bit_copies (op0, mode)
5697                        == GET_MODE_PRECISION (mode)))
5698             {
5699               op0 = expand_compound_operation (op0);
5700               return simplify_gen_unary (NEG, mode,
5701                                          gen_lowpart (mode, op0),
5702                                          mode);
5703             }
5704
5705           else if (STORE_FLAG_VALUE == 1
5706                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5707                    && op1 == const0_rtx
5708                    && mode == GET_MODE (op0)
5709                    && nonzero_bits (op0, mode) == 1)
5710             {
5711               op0 = expand_compound_operation (op0);
5712               return simplify_gen_binary (XOR, mode,
5713                                           gen_lowpart (mode, op0),
5714                                           const1_rtx);
5715             }
5716
5717           else if (STORE_FLAG_VALUE == 1
5718                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5719                    && op1 == const0_rtx
5720                    && mode == GET_MODE (op0)
5721                    && (num_sign_bit_copies (op0, mode)
5722                        == GET_MODE_PRECISION (mode)))
5723             {
5724               op0 = expand_compound_operation (op0);
5725               return plus_constant (mode, gen_lowpart (mode, op0), 1);
5726             }
5727
5728           /* If STORE_FLAG_VALUE is -1, we have cases similar to
5729              those above.  */
5730           if (in_cond)
5731             ;
5732
5733           else if (STORE_FLAG_VALUE == -1
5734               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5735               && op1 == const0_rtx
5736               && (num_sign_bit_copies (op0, mode)
5737                   == GET_MODE_PRECISION (mode)))
5738             return gen_lowpart (mode,
5739                                 expand_compound_operation (op0));
5740
5741           else if (STORE_FLAG_VALUE == -1
5742                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5743                    && op1 == const0_rtx
5744                    && mode == GET_MODE (op0)
5745                    && nonzero_bits (op0, mode) == 1)
5746             {
5747               op0 = expand_compound_operation (op0);
5748               return simplify_gen_unary (NEG, mode,
5749                                          gen_lowpart (mode, op0),
5750                                          mode);
5751             }
5752
5753           else if (STORE_FLAG_VALUE == -1
5754                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5755                    && op1 == const0_rtx
5756                    && mode == GET_MODE (op0)
5757                    && (num_sign_bit_copies (op0, mode)
5758                        == GET_MODE_PRECISION (mode)))
5759             {
5760               op0 = expand_compound_operation (op0);
5761               return simplify_gen_unary (NOT, mode,
5762                                          gen_lowpart (mode, op0),
5763                                          mode);
5764             }
5765
5766           /* If X is 0/1, (eq X 0) is X-1.  */
5767           else if (STORE_FLAG_VALUE == -1
5768                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5769                    && op1 == const0_rtx
5770                    && mode == GET_MODE (op0)
5771                    && nonzero_bits (op0, mode) == 1)
5772             {
5773               op0 = expand_compound_operation (op0);
5774               return plus_constant (mode, gen_lowpart (mode, op0), -1);
5775             }
5776
5777           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5778              one bit that might be nonzero, we can convert (ne x 0) to
5779              (ashift x c) where C puts the bit in the sign bit.  Remove any
5780              AND with STORE_FLAG_VALUE when we are done, since we are only
5781              going to test the sign bit.  */
5782           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5783               && HWI_COMPUTABLE_MODE_P (mode)
5784               && val_signbit_p (mode, STORE_FLAG_VALUE)
5785               && op1 == const0_rtx
5786               && mode == GET_MODE (op0)
5787               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5788             {
5789               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5790                                         expand_compound_operation (op0),
5791                                         GET_MODE_PRECISION (mode) - 1 - i);
5792               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5793                 return XEXP (x, 0);
5794               else
5795                 return x;
5796             }
5797
5798           /* If the code changed, return a whole new comparison.  */
5799           if (new_code != code)
5800             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5801
5802           /* Otherwise, keep this operation, but maybe change its operands.
5803              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
5804           SUBST (XEXP (x, 0), op0);
5805           SUBST (XEXP (x, 1), op1);
5806         }
5807       break;
5808
5809     case IF_THEN_ELSE:
5810       return simplify_if_then_else (x);
5811
5812     case ZERO_EXTRACT:
5813     case SIGN_EXTRACT:
5814     case ZERO_EXTEND:
5815     case SIGN_EXTEND:
5816       /* If we are processing SET_DEST, we are done.  */
5817       if (in_dest)
5818         return x;
5819
5820       return expand_compound_operation (x);
5821
5822     case SET:
5823       return simplify_set (x);
5824
5825     case AND:
5826     case IOR:
5827       return simplify_logical (x);
5828
5829     case ASHIFT:
5830     case LSHIFTRT:
5831     case ASHIFTRT:
5832     case ROTATE:
5833     case ROTATERT:
5834       /* If this is a shift by a constant amount, simplify it.  */
5835       if (CONST_INT_P (XEXP (x, 1)))
5836         return simplify_shift_const (x, code, mode, XEXP (x, 0),
5837                                      INTVAL (XEXP (x, 1)));
5838
5839       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5840         SUBST (XEXP (x, 1),
5841                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5842                               ((unsigned HOST_WIDE_INT) 1
5843                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5844                               - 1,
5845                               0));
5846       break;
5847
5848     default:
5849       break;
5850     }
5851
5852   return x;
5853 }
5854 \f
5855 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
5856
5857 static rtx
5858 simplify_if_then_else (rtx x)
5859 {
5860   enum machine_mode mode = GET_MODE (x);
5861   rtx cond = XEXP (x, 0);
5862   rtx true_rtx = XEXP (x, 1);
5863   rtx false_rtx = XEXP (x, 2);
5864   enum rtx_code true_code = GET_CODE (cond);
5865   int comparison_p = COMPARISON_P (cond);
5866   rtx temp;
5867   int i;
5868   enum rtx_code false_code;
5869   rtx reversed;
5870
5871   /* Simplify storing of the truth value.  */
5872   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5873     return simplify_gen_relational (true_code, mode, VOIDmode,
5874                                     XEXP (cond, 0), XEXP (cond, 1));
5875
5876   /* Also when the truth value has to be reversed.  */
5877   if (comparison_p
5878       && true_rtx == const0_rtx && false_rtx == const_true_rtx
5879       && (reversed = reversed_comparison (cond, mode)))
5880     return reversed;
5881
5882   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5883      in it is being compared against certain values.  Get the true and false
5884      comparisons and see if that says anything about the value of each arm.  */
5885
5886   if (comparison_p
5887       && ((false_code = reversed_comparison_code (cond, NULL))
5888           != UNKNOWN)
5889       && REG_P (XEXP (cond, 0)))
5890     {
5891       HOST_WIDE_INT nzb;
5892       rtx from = XEXP (cond, 0);
5893       rtx true_val = XEXP (cond, 1);
5894       rtx false_val = true_val;
5895       int swapped = 0;
5896
5897       /* If FALSE_CODE is EQ, swap the codes and arms.  */
5898
5899       if (false_code == EQ)
5900         {
5901           swapped = 1, true_code = EQ, false_code = NE;
5902           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5903         }
5904
5905       /* If we are comparing against zero and the expression being tested has
5906          only a single bit that might be nonzero, that is its value when it is
5907          not equal to zero.  Similarly if it is known to be -1 or 0.  */
5908
5909       if (true_code == EQ && true_val == const0_rtx
5910           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5911         {
5912           false_code = EQ;
5913           false_val = gen_int_mode (nzb, GET_MODE (from));
5914         }
5915       else if (true_code == EQ && true_val == const0_rtx
5916                && (num_sign_bit_copies (from, GET_MODE (from))
5917                    == GET_MODE_PRECISION (GET_MODE (from))))
5918         {
5919           false_code = EQ;
5920           false_val = constm1_rtx;
5921         }
5922
5923       /* Now simplify an arm if we know the value of the register in the
5924          branch and it is used in the arm.  Be careful due to the potential
5925          of locally-shared RTL.  */
5926
5927       if (reg_mentioned_p (from, true_rtx))
5928         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5929                                       from, true_val),
5930                           pc_rtx, pc_rtx, 0, 0, 0);
5931       if (reg_mentioned_p (from, false_rtx))
5932         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5933                                    from, false_val),
5934                            pc_rtx, pc_rtx, 0, 0, 0);
5935
5936       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5937       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5938
5939       true_rtx = XEXP (x, 1);
5940       false_rtx = XEXP (x, 2);
5941       true_code = GET_CODE (cond);
5942     }
5943
5944   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5945      reversed, do so to avoid needing two sets of patterns for
5946      subtract-and-branch insns.  Similarly if we have a constant in the true
5947      arm, the false arm is the same as the first operand of the comparison, or
5948      the false arm is more complicated than the true arm.  */
5949
5950   if (comparison_p
5951       && reversed_comparison_code (cond, NULL) != UNKNOWN
5952       && (true_rtx == pc_rtx
5953           || (CONSTANT_P (true_rtx)
5954               && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5955           || true_rtx == const0_rtx
5956           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5957           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5958               && !OBJECT_P (false_rtx))
5959           || reg_mentioned_p (true_rtx, false_rtx)
5960           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5961     {
5962       true_code = reversed_comparison_code (cond, NULL);
5963       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5964       SUBST (XEXP (x, 1), false_rtx);
5965       SUBST (XEXP (x, 2), true_rtx);
5966
5967       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5968       cond = XEXP (x, 0);
5969
5970       /* It is possible that the conditional has been simplified out.  */
5971       true_code = GET_CODE (cond);
5972       comparison_p = COMPARISON_P (cond);
5973     }
5974
5975   /* If the two arms are identical, we don't need the comparison.  */
5976
5977   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5978     return true_rtx;
5979
5980   /* Convert a == b ? b : a to "a".  */
5981   if (true_code == EQ && ! side_effects_p (cond)
5982       && !HONOR_NANS (mode)
5983       && rtx_equal_p (XEXP (cond, 0), false_rtx)
5984       && rtx_equal_p (XEXP (cond, 1), true_rtx))
5985     return false_rtx;
5986   else if (true_code == NE && ! side_effects_p (cond)
5987            && !HONOR_NANS (mode)
5988            && rtx_equal_p (XEXP (cond, 0), true_rtx)
5989            && rtx_equal_p (XEXP (cond, 1), false_rtx))
5990     return true_rtx;
5991
5992   /* Look for cases where we have (abs x) or (neg (abs X)).  */
5993
5994   if (GET_MODE_CLASS (mode) == MODE_INT
5995       && comparison_p
5996       && XEXP (cond, 1) == const0_rtx
5997       && GET_CODE (false_rtx) == NEG
5998       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5999       && rtx_equal_p (true_rtx, XEXP (cond, 0))
6000       && ! side_effects_p (true_rtx))
6001     switch (true_code)
6002       {
6003       case GT:
6004       case GE:
6005         return simplify_gen_unary (ABS, mode, true_rtx, mode);
6006       case LT:
6007       case LE:
6008         return
6009           simplify_gen_unary (NEG, mode,
6010                               simplify_gen_unary (ABS, mode, true_rtx, mode),
6011                               mode);
6012       default:
6013         break;
6014       }
6015
6016   /* Look for MIN or MAX.  */
6017
6018   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6019       && comparison_p
6020       && rtx_equal_p (XEXP (cond, 0), true_rtx)
6021       && rtx_equal_p (XEXP (cond, 1), false_rtx)
6022       && ! side_effects_p (cond))
6023     switch (true_code)
6024       {
6025       case GE:
6026       case GT:
6027         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6028       case LE:
6029       case LT:
6030         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6031       case GEU:
6032       case GTU:
6033         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6034       case LEU:
6035       case LTU:
6036         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6037       default:
6038         break;
6039       }
6040
6041   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6042      second operand is zero, this can be done as (OP Z (mult COND C2)) where
6043      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6044      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6045      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6046      neither 1 or -1, but it isn't worth checking for.  */
6047
6048   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6049       && comparison_p
6050       && GET_MODE_CLASS (mode) == MODE_INT
6051       && ! side_effects_p (x))
6052     {
6053       rtx t = make_compound_operation (true_rtx, SET);
6054       rtx f = make_compound_operation (false_rtx, SET);
6055       rtx cond_op0 = XEXP (cond, 0);
6056       rtx cond_op1 = XEXP (cond, 1);
6057       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6058       enum machine_mode m = mode;
6059       rtx z = 0, c1 = NULL_RTX;
6060
6061       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6062            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6063            || GET_CODE (t) == ASHIFT
6064            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6065           && rtx_equal_p (XEXP (t, 0), f))
6066         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6067
6068       /* If an identity-zero op is commutative, check whether there
6069          would be a match if we swapped the operands.  */
6070       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6071                 || GET_CODE (t) == XOR)
6072                && rtx_equal_p (XEXP (t, 1), f))
6073         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6074       else if (GET_CODE (t) == SIGN_EXTEND
6075                && (GET_CODE (XEXP (t, 0)) == PLUS
6076                    || GET_CODE (XEXP (t, 0)) == MINUS
6077                    || GET_CODE (XEXP (t, 0)) == IOR
6078                    || GET_CODE (XEXP (t, 0)) == XOR
6079                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6080                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6081                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6082                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6083                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6084                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6085                && (num_sign_bit_copies (f, GET_MODE (f))
6086                    > (unsigned int)
6087                      (GET_MODE_PRECISION (mode)
6088                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6089         {
6090           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6091           extend_op = SIGN_EXTEND;
6092           m = GET_MODE (XEXP (t, 0));
6093         }
6094       else if (GET_CODE (t) == SIGN_EXTEND
6095                && (GET_CODE (XEXP (t, 0)) == PLUS
6096                    || GET_CODE (XEXP (t, 0)) == IOR
6097                    || GET_CODE (XEXP (t, 0)) == XOR)
6098                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6099                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6100                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6101                && (num_sign_bit_copies (f, GET_MODE (f))
6102                    > (unsigned int)
6103                      (GET_MODE_PRECISION (mode)
6104                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6105         {
6106           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6107           extend_op = SIGN_EXTEND;
6108           m = GET_MODE (XEXP (t, 0));
6109         }
6110       else if (GET_CODE (t) == ZERO_EXTEND
6111                && (GET_CODE (XEXP (t, 0)) == PLUS
6112                    || GET_CODE (XEXP (t, 0)) == MINUS
6113                    || GET_CODE (XEXP (t, 0)) == IOR
6114                    || GET_CODE (XEXP (t, 0)) == XOR
6115                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6116                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6117                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6118                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6119                && HWI_COMPUTABLE_MODE_P (mode)
6120                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6121                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6122                && ((nonzero_bits (f, GET_MODE (f))
6123                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6124                    == 0))
6125         {
6126           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6127           extend_op = ZERO_EXTEND;
6128           m = GET_MODE (XEXP (t, 0));
6129         }
6130       else if (GET_CODE (t) == ZERO_EXTEND
6131                && (GET_CODE (XEXP (t, 0)) == PLUS
6132                    || GET_CODE (XEXP (t, 0)) == IOR
6133                    || GET_CODE (XEXP (t, 0)) == XOR)
6134                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6135                && HWI_COMPUTABLE_MODE_P (mode)
6136                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6137                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6138                && ((nonzero_bits (f, GET_MODE (f))
6139                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6140                    == 0))
6141         {
6142           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6143           extend_op = ZERO_EXTEND;
6144           m = GET_MODE (XEXP (t, 0));
6145         }
6146
6147       if (z)
6148         {
6149           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6150                                                  cond_op0, cond_op1),
6151                         pc_rtx, pc_rtx, 0, 0, 0);
6152           temp = simplify_gen_binary (MULT, m, temp,
6153                                       simplify_gen_binary (MULT, m, c1,
6154                                                            const_true_rtx));
6155           temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6156           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6157
6158           if (extend_op != UNKNOWN)
6159             temp = simplify_gen_unary (extend_op, mode, temp, m);
6160
6161           return temp;
6162         }
6163     }
6164
6165   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6166      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6167      negation of a single bit, we can convert this operation to a shift.  We
6168      can actually do this more generally, but it doesn't seem worth it.  */
6169
6170   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6171       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6172       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6173            && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6174           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6175                == GET_MODE_PRECISION (mode))
6176               && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6177     return
6178       simplify_shift_const (NULL_RTX, ASHIFT, mode,
6179                             gen_lowpart (mode, XEXP (cond, 0)), i);
6180
6181   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
6182   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6183       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6184       && GET_MODE (XEXP (cond, 0)) == mode
6185       && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6186           == nonzero_bits (XEXP (cond, 0), mode)
6187       && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6188     return XEXP (cond, 0);
6189
6190   return x;
6191 }
6192 \f
6193 /* Simplify X, a SET expression.  Return the new expression.  */
6194
6195 static rtx
6196 simplify_set (rtx x)
6197 {
6198   rtx src = SET_SRC (x);
6199   rtx dest = SET_DEST (x);
6200   enum machine_mode mode
6201     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6202   rtx other_insn;
6203   rtx *cc_use;
6204
6205   /* (set (pc) (return)) gets written as (return).  */
6206   if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6207     return src;
6208
6209   /* Now that we know for sure which bits of SRC we are using, see if we can
6210      simplify the expression for the object knowing that we only need the
6211      low-order bits.  */
6212
6213   if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6214     {
6215       src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6216       SUBST (SET_SRC (x), src);
6217     }
6218
6219   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6220      the comparison result and try to simplify it unless we already have used
6221      undobuf.other_insn.  */
6222   if ((GET_MODE_CLASS (mode) == MODE_CC
6223        || GET_CODE (src) == COMPARE
6224        || CC0_P (dest))
6225       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6226       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6227       && COMPARISON_P (*cc_use)
6228       && rtx_equal_p (XEXP (*cc_use, 0), dest))
6229     {
6230       enum rtx_code old_code = GET_CODE (*cc_use);
6231       enum rtx_code new_code;
6232       rtx op0, op1, tmp;
6233       int other_changed = 0;
6234       rtx inner_compare = NULL_RTX;
6235       enum machine_mode compare_mode = GET_MODE (dest);
6236
6237       if (GET_CODE (src) == COMPARE)
6238         {
6239           op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6240           if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6241             {
6242               inner_compare = op0;
6243               op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6244             }
6245         }
6246       else
6247         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6248
6249       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6250                                            op0, op1);
6251       if (!tmp)
6252         new_code = old_code;
6253       else if (!CONSTANT_P (tmp))
6254         {
6255           new_code = GET_CODE (tmp);
6256           op0 = XEXP (tmp, 0);
6257           op1 = XEXP (tmp, 1);
6258         }
6259       else
6260         {
6261           rtx pat = PATTERN (other_insn);
6262           undobuf.other_insn = other_insn;
6263           SUBST (*cc_use, tmp);
6264
6265           /* Attempt to simplify CC user.  */
6266           if (GET_CODE (pat) == SET)
6267             {
6268               rtx new_rtx = simplify_rtx (SET_SRC (pat));
6269               if (new_rtx != NULL_RTX)
6270                 SUBST (SET_SRC (pat), new_rtx);
6271             }
6272
6273           /* Convert X into a no-op move.  */
6274           SUBST (SET_DEST (x), pc_rtx);
6275           SUBST (SET_SRC (x), pc_rtx);
6276           return x;
6277         }
6278
6279       /* Simplify our comparison, if possible.  */
6280       new_code = simplify_comparison (new_code, &op0, &op1);
6281
6282 #ifdef SELECT_CC_MODE
6283       /* If this machine has CC modes other than CCmode, check to see if we
6284          need to use a different CC mode here.  */
6285       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6286         compare_mode = GET_MODE (op0);
6287       else if (inner_compare
6288                && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6289                && new_code == old_code
6290                && op0 == XEXP (inner_compare, 0)
6291                && op1 == XEXP (inner_compare, 1))
6292         compare_mode = GET_MODE (inner_compare);
6293       else
6294         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6295
6296 #ifndef HAVE_cc0
6297       /* If the mode changed, we have to change SET_DEST, the mode in the
6298          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
6299          a hard register, just build new versions with the proper mode.  If it
6300          is a pseudo, we lose unless it is only time we set the pseudo, in
6301          which case we can safely change its mode.  */
6302       if (compare_mode != GET_MODE (dest))
6303         {
6304           if (can_change_dest_mode (dest, 0, compare_mode))
6305             {
6306               unsigned int regno = REGNO (dest);
6307               rtx new_dest;
6308
6309               if (regno < FIRST_PSEUDO_REGISTER)
6310                 new_dest = gen_rtx_REG (compare_mode, regno);
6311               else
6312                 {
6313                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6314                   new_dest = regno_reg_rtx[regno];
6315                 }
6316
6317               SUBST (SET_DEST (x), new_dest);
6318               SUBST (XEXP (*cc_use, 0), new_dest);
6319               other_changed = 1;
6320
6321               dest = new_dest;
6322             }
6323         }
6324 #endif  /* cc0 */
6325 #endif  /* SELECT_CC_MODE */
6326
6327       /* If the code changed, we have to build a new comparison in
6328          undobuf.other_insn.  */
6329       if (new_code != old_code)
6330         {
6331           int other_changed_previously = other_changed;
6332           unsigned HOST_WIDE_INT mask;
6333           rtx old_cc_use = *cc_use;
6334
6335           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6336                                           dest, const0_rtx));
6337           other_changed = 1;
6338
6339           /* If the only change we made was to change an EQ into an NE or
6340              vice versa, OP0 has only one bit that might be nonzero, and OP1
6341              is zero, check if changing the user of the condition code will
6342              produce a valid insn.  If it won't, we can keep the original code
6343              in that insn by surrounding our operation with an XOR.  */
6344
6345           if (((old_code == NE && new_code == EQ)
6346                || (old_code == EQ && new_code == NE))
6347               && ! other_changed_previously && op1 == const0_rtx
6348               && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6349               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6350             {
6351               rtx pat = PATTERN (other_insn), note = 0;
6352
6353               if ((recog_for_combine (&pat, other_insn, &note) < 0
6354                    && ! check_asm_operands (pat)))
6355                 {
6356                   *cc_use = old_cc_use;
6357                   other_changed = 0;
6358
6359                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6360                                              op0, GEN_INT (mask));
6361                 }
6362             }
6363         }
6364
6365       if (other_changed)
6366         undobuf.other_insn = other_insn;
6367
6368       /* Otherwise, if we didn't previously have a COMPARE in the
6369          correct mode, we need one.  */
6370       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6371         {
6372           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6373           src = SET_SRC (x);
6374         }
6375       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6376         {
6377           SUBST (SET_SRC (x), op0);
6378           src = SET_SRC (x);
6379         }
6380       /* Otherwise, update the COMPARE if needed.  */
6381       else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6382         {
6383           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6384           src = SET_SRC (x);
6385         }
6386     }
6387   else
6388     {
6389       /* Get SET_SRC in a form where we have placed back any
6390          compound expressions.  Then do the checks below.  */
6391       src = make_compound_operation (src, SET);
6392       SUBST (SET_SRC (x), src);
6393     }
6394
6395   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6396      and X being a REG or (subreg (reg)), we may be able to convert this to
6397      (set (subreg:m2 x) (op)).
6398
6399      We can always do this if M1 is narrower than M2 because that means that
6400      we only care about the low bits of the result.
6401
6402      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6403      perform a narrower operation than requested since the high-order bits will
6404      be undefined.  On machine where it is defined, this transformation is safe
6405      as long as M1 and M2 have the same number of words.  */
6406
6407   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6408       && !OBJECT_P (SUBREG_REG (src))
6409       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6410            / UNITS_PER_WORD)
6411           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6412                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6413 #ifndef WORD_REGISTER_OPERATIONS
6414       && (GET_MODE_SIZE (GET_MODE (src))
6415         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6416 #endif
6417 #ifdef CANNOT_CHANGE_MODE_CLASS
6418       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6419             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6420                                          GET_MODE (SUBREG_REG (src)),
6421                                          GET_MODE (src)))
6422 #endif
6423       && (REG_P (dest)
6424           || (GET_CODE (dest) == SUBREG
6425               && REG_P (SUBREG_REG (dest)))))
6426     {
6427       SUBST (SET_DEST (x),
6428              gen_lowpart (GET_MODE (SUBREG_REG (src)),
6429                                       dest));
6430       SUBST (SET_SRC (x), SUBREG_REG (src));
6431
6432       src = SET_SRC (x), dest = SET_DEST (x);
6433     }
6434
6435 #ifdef HAVE_cc0
6436   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6437      in SRC.  */
6438   if (dest == cc0_rtx
6439       && GET_CODE (src) == SUBREG
6440       && subreg_lowpart_p (src)
6441       && (GET_MODE_PRECISION (GET_MODE (src))
6442           < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6443     {
6444       rtx inner = SUBREG_REG (src);
6445       enum machine_mode inner_mode = GET_MODE (inner);
6446
6447       /* Here we make sure that we don't have a sign bit on.  */
6448       if (val_signbit_known_clear_p (GET_MODE (src),
6449                                      nonzero_bits (inner, inner_mode)))
6450         {
6451           SUBST (SET_SRC (x), inner);
6452           src = SET_SRC (x);
6453         }
6454     }
6455 #endif
6456
6457 #ifdef LOAD_EXTEND_OP
6458   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6459      would require a paradoxical subreg.  Replace the subreg with a
6460      zero_extend to avoid the reload that would otherwise be required.  */
6461
6462   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6463       && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6464       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6465       && SUBREG_BYTE (src) == 0
6466       && paradoxical_subreg_p (src)
6467       && MEM_P (SUBREG_REG (src)))
6468     {
6469       SUBST (SET_SRC (x),
6470              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6471                             GET_MODE (src), SUBREG_REG (src)));
6472
6473       src = SET_SRC (x);
6474     }
6475 #endif
6476
6477   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6478      are comparing an item known to be 0 or -1 against 0, use a logical
6479      operation instead. Check for one of the arms being an IOR of the other
6480      arm with some value.  We compute three terms to be IOR'ed together.  In
6481      practice, at most two will be nonzero.  Then we do the IOR's.  */
6482
6483   if (GET_CODE (dest) != PC
6484       && GET_CODE (src) == IF_THEN_ELSE
6485       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6486       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6487       && XEXP (XEXP (src, 0), 1) == const0_rtx
6488       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6489 #ifdef HAVE_conditional_move
6490       && ! can_conditionally_move_p (GET_MODE (src))
6491 #endif
6492       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6493                                GET_MODE (XEXP (XEXP (src, 0), 0)))
6494           == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6495       && ! side_effects_p (src))
6496     {
6497       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6498                       ? XEXP (src, 1) : XEXP (src, 2));
6499       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6500                    ? XEXP (src, 2) : XEXP (src, 1));
6501       rtx term1 = const0_rtx, term2, term3;
6502
6503       if (GET_CODE (true_rtx) == IOR
6504           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6505         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6506       else if (GET_CODE (true_rtx) == IOR
6507                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6508         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6509       else if (GET_CODE (false_rtx) == IOR
6510                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6511         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6512       else if (GET_CODE (false_rtx) == IOR
6513                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6514         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6515
6516       term2 = simplify_gen_binary (AND, GET_MODE (src),
6517                                    XEXP (XEXP (src, 0), 0), true_rtx);
6518       term3 = simplify_gen_binary (AND, GET_MODE (src),
6519                                    simplify_gen_unary (NOT, GET_MODE (src),
6520                                                        XEXP (XEXP (src, 0), 0),
6521                                                        GET_MODE (src)),
6522                                    false_rtx);
6523
6524       SUBST (SET_SRC (x),
6525              simplify_gen_binary (IOR, GET_MODE (src),
6526                                   simplify_gen_binary (IOR, GET_MODE (src),
6527                                                        term1, term2),
6528                                   term3));
6529
6530       src = SET_SRC (x);
6531     }
6532
6533   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6534      whole thing fail.  */
6535   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6536     return src;
6537   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6538     return dest;
6539   else
6540     /* Convert this into a field assignment operation, if possible.  */
6541     return make_field_assignment (x);
6542 }
6543 \f
6544 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6545    result.  */
6546
6547 static rtx
6548 simplify_logical (rtx x)
6549 {
6550   enum machine_mode mode = GET_MODE (x);
6551   rtx op0 = XEXP (x, 0);
6552   rtx op1 = XEXP (x, 1);
6553
6554   switch (GET_CODE (x))
6555     {
6556     case AND:
6557       /* We can call simplify_and_const_int only if we don't lose
6558          any (sign) bits when converting INTVAL (op1) to
6559          "unsigned HOST_WIDE_INT".  */
6560       if (CONST_INT_P (op1)
6561           && (HWI_COMPUTABLE_MODE_P (mode)
6562               || INTVAL (op1) > 0))
6563         {
6564           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6565           if (GET_CODE (x) != AND)
6566             return x;
6567
6568           op0 = XEXP (x, 0);
6569           op1 = XEXP (x, 1);
6570         }
6571
6572       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6573          apply the distributive law and then the inverse distributive
6574          law to see if things simplify.  */
6575       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6576         {
6577           rtx result = distribute_and_simplify_rtx (x, 0);
6578           if (result)
6579             return result;
6580         }
6581       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6582         {
6583           rtx result = distribute_and_simplify_rtx (x, 1);
6584           if (result)
6585             return result;
6586         }
6587       break;
6588
6589     case IOR:
6590       /* If we have (ior (and A B) C), apply the distributive law and then
6591          the inverse distributive law to see if things simplify.  */
6592
6593       if (GET_CODE (op0) == AND)
6594         {
6595           rtx result = distribute_and_simplify_rtx (x, 0);
6596           if (result)
6597             return result;
6598         }
6599
6600       if (GET_CODE (op1) == AND)
6601         {
6602           rtx result = distribute_and_simplify_rtx (x, 1);
6603           if (result)
6604             return result;
6605         }
6606       break;
6607
6608     default:
6609       gcc_unreachable ();
6610     }
6611
6612   return x;
6613 }
6614 \f
6615 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6616    operations" because they can be replaced with two more basic operations.
6617    ZERO_EXTEND is also considered "compound" because it can be replaced with
6618    an AND operation, which is simpler, though only one operation.
6619
6620    The function expand_compound_operation is called with an rtx expression
6621    and will convert it to the appropriate shifts and AND operations,
6622    simplifying at each stage.
6623
6624    The function make_compound_operation is called to convert an expression
6625    consisting of shifts and ANDs into the equivalent compound expression.
6626    It is the inverse of this function, loosely speaking.  */
6627
6628 static rtx
6629 expand_compound_operation (rtx x)
6630 {
6631   unsigned HOST_WIDE_INT pos = 0, len;
6632   int unsignedp = 0;
6633   unsigned int modewidth;
6634   rtx tem;
6635
6636   switch (GET_CODE (x))
6637     {
6638     case ZERO_EXTEND:
6639       unsignedp = 1;
6640     case SIGN_EXTEND:
6641       /* We can't necessarily use a const_int for a multiword mode;
6642          it depends on implicitly extending the value.
6643          Since we don't know the right way to extend it,
6644          we can't tell whether the implicit way is right.
6645
6646          Even for a mode that is no wider than a const_int,
6647          we can't win, because we need to sign extend one of its bits through
6648          the rest of it, and we don't know which bit.  */
6649       if (CONST_INT_P (XEXP (x, 0)))
6650         return x;
6651
6652       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6653          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
6654          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6655          reloaded. If not for that, MEM's would very rarely be safe.
6656
6657          Reject MODEs bigger than a word, because we might not be able
6658          to reference a two-register group starting with an arbitrary register
6659          (and currently gen_lowpart might crash for a SUBREG).  */
6660
6661       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6662         return x;
6663
6664       /* Reject MODEs that aren't scalar integers because turning vector
6665          or complex modes into shifts causes problems.  */
6666
6667       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6668         return x;
6669
6670       len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6671       /* If the inner object has VOIDmode (the only way this can happen
6672          is if it is an ASM_OPERANDS), we can't do anything since we don't
6673          know how much masking to do.  */
6674       if (len == 0)
6675         return x;
6676
6677       break;
6678
6679     case ZERO_EXTRACT:
6680       unsignedp = 1;
6681
6682       /* ... fall through ...  */
6683
6684     case SIGN_EXTRACT:
6685       /* If the operand is a CLOBBER, just return it.  */
6686       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6687         return XEXP (x, 0);
6688
6689       if (!CONST_INT_P (XEXP (x, 1))
6690           || !CONST_INT_P (XEXP (x, 2))
6691           || GET_MODE (XEXP (x, 0)) == VOIDmode)
6692         return x;
6693
6694       /* Reject MODEs that aren't scalar integers because turning vector
6695          or complex modes into shifts causes problems.  */
6696
6697       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6698         return x;
6699
6700       len = INTVAL (XEXP (x, 1));
6701       pos = INTVAL (XEXP (x, 2));
6702
6703       /* This should stay within the object being extracted, fail otherwise.  */
6704       if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6705         return x;
6706
6707       if (BITS_BIG_ENDIAN)
6708         pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6709
6710       break;
6711
6712     default:
6713       return x;
6714     }
6715   /* Convert sign extension to zero extension, if we know that the high
6716      bit is not set, as this is easier to optimize.  It will be converted
6717      back to cheaper alternative in make_extraction.  */
6718   if (GET_CODE (x) == SIGN_EXTEND
6719       && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6720           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6721                 & ~(((unsigned HOST_WIDE_INT)
6722                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6723                      >> 1))
6724                == 0)))
6725     {
6726       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6727       rtx temp2 = expand_compound_operation (temp);
6728
6729       /* Make sure this is a profitable operation.  */
6730       if (set_src_cost (x, optimize_this_for_speed_p)
6731           > set_src_cost (temp2, optimize_this_for_speed_p))
6732        return temp2;
6733       else if (set_src_cost (x, optimize_this_for_speed_p)
6734                > set_src_cost (temp, optimize_this_for_speed_p))
6735        return temp;
6736       else
6737        return x;
6738     }
6739
6740   /* We can optimize some special cases of ZERO_EXTEND.  */
6741   if (GET_CODE (x) == ZERO_EXTEND)
6742     {
6743       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6744          know that the last value didn't have any inappropriate bits
6745          set.  */
6746       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6747           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6748           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6749           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6750               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6751         return XEXP (XEXP (x, 0), 0);
6752
6753       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6754       if (GET_CODE (XEXP (x, 0)) == SUBREG
6755           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6756           && subreg_lowpart_p (XEXP (x, 0))
6757           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6758           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6759               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6760         return SUBREG_REG (XEXP (x, 0));
6761
6762       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6763          is a comparison and STORE_FLAG_VALUE permits.  This is like
6764          the first case, but it works even when GET_MODE (x) is larger
6765          than HOST_WIDE_INT.  */
6766       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6767           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6768           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6769           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6770               <= HOST_BITS_PER_WIDE_INT)
6771           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6772         return XEXP (XEXP (x, 0), 0);
6773
6774       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6775       if (GET_CODE (XEXP (x, 0)) == SUBREG
6776           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6777           && subreg_lowpart_p (XEXP (x, 0))
6778           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6779           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6780               <= HOST_BITS_PER_WIDE_INT)
6781           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6782         return SUBREG_REG (XEXP (x, 0));
6783
6784     }
6785
6786   /* If we reach here, we want to return a pair of shifts.  The inner
6787      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
6788      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
6789      logical depending on the value of UNSIGNEDP.
6790
6791      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6792      converted into an AND of a shift.
6793
6794      We must check for the case where the left shift would have a negative
6795      count.  This can happen in a case like (x >> 31) & 255 on machines
6796      that can't shift by a constant.  On those machines, we would first
6797      combine the shift with the AND to produce a variable-position
6798      extraction.  Then the constant of 31 would be substituted in
6799      to produce such a position.  */
6800
6801   modewidth = GET_MODE_PRECISION (GET_MODE (x));
6802   if (modewidth >= pos + len)
6803     {
6804       enum machine_mode mode = GET_MODE (x);
6805       tem = gen_lowpart (mode, XEXP (x, 0));
6806       if (!tem || GET_CODE (tem) == CLOBBER)
6807         return x;
6808       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6809                                   tem, modewidth - pos - len);
6810       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6811                                   mode, tem, modewidth - len);
6812     }
6813   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6814     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6815                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
6816                                                         GET_MODE (x),
6817                                                         XEXP (x, 0), pos),
6818                                   ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6819   else
6820     /* Any other cases we can't handle.  */
6821     return x;
6822
6823   /* If we couldn't do this for some reason, return the original
6824      expression.  */
6825   if (GET_CODE (tem) == CLOBBER)
6826     return x;
6827
6828   return tem;
6829 }
6830 \f
6831 /* X is a SET which contains an assignment of one object into
6832    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6833    or certain SUBREGS). If possible, convert it into a series of
6834    logical operations.
6835
6836    We half-heartedly support variable positions, but do not at all
6837    support variable lengths.  */
6838
6839 static const_rtx
6840 expand_field_assignment (const_rtx x)
6841 {
6842   rtx inner;
6843   rtx pos;                      /* Always counts from low bit.  */
6844   int len;
6845   rtx mask, cleared, masked;
6846   enum machine_mode compute_mode;
6847
6848   /* Loop until we find something we can't simplify.  */
6849   while (1)
6850     {
6851       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6852           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6853         {
6854           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6855           len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
6856           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6857         }
6858       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6859                && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6860         {
6861           inner = XEXP (SET_DEST (x), 0);
6862           len = INTVAL (XEXP (SET_DEST (x), 1));
6863           pos = XEXP (SET_DEST (x), 2);
6864
6865           /* A constant position should stay within the width of INNER.  */
6866           if (CONST_INT_P (pos)
6867               && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
6868             break;
6869
6870           if (BITS_BIG_ENDIAN)
6871             {
6872               if (CONST_INT_P (pos))
6873                 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
6874                                - INTVAL (pos));
6875               else if (GET_CODE (pos) == MINUS
6876                        && CONST_INT_P (XEXP (pos, 1))
6877                        && (INTVAL (XEXP (pos, 1))
6878                            == GET_MODE_PRECISION (GET_MODE (inner)) - len))
6879                 /* If position is ADJUST - X, new position is X.  */
6880                 pos = XEXP (pos, 0);
6881               else
6882                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6883                                            GEN_INT (GET_MODE_PRECISION (
6884                                                     GET_MODE (inner))
6885                                                     - len),
6886                                            pos);
6887             }
6888         }
6889
6890       /* A SUBREG between two modes that occupy the same numbers of words
6891          can be done by moving the SUBREG to the source.  */
6892       else if (GET_CODE (SET_DEST (x)) == SUBREG
6893                /* We need SUBREGs to compute nonzero_bits properly.  */
6894                && nonzero_sign_valid
6895                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6896                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6897                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6898                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6899         {
6900           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6901                            gen_lowpart
6902                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
6903                             SET_SRC (x)));
6904           continue;
6905         }
6906       else
6907         break;
6908
6909       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6910         inner = SUBREG_REG (inner);
6911
6912       compute_mode = GET_MODE (inner);
6913
6914       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
6915       if (! SCALAR_INT_MODE_P (compute_mode))
6916         {
6917           enum machine_mode imode;
6918
6919           /* Don't do anything for vector or complex integral types.  */
6920           if (! FLOAT_MODE_P (compute_mode))
6921             break;
6922
6923           /* Try to find an integral mode to pun with.  */
6924           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6925           if (imode == BLKmode)
6926             break;
6927
6928           compute_mode = imode;
6929           inner = gen_lowpart (imode, inner);
6930         }
6931
6932       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
6933       if (len >= HOST_BITS_PER_WIDE_INT)
6934         break;
6935
6936       /* Now compute the equivalent expression.  Make a copy of INNER
6937          for the SET_DEST in case it is a MEM into which we will substitute;
6938          we don't want shared RTL in that case.  */
6939       mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
6940       cleared = simplify_gen_binary (AND, compute_mode,
6941                                      simplify_gen_unary (NOT, compute_mode,
6942                                        simplify_gen_binary (ASHIFT,
6943                                                             compute_mode,
6944                                                             mask, pos),
6945                                        compute_mode),
6946                                      inner);
6947       masked = simplify_gen_binary (ASHIFT, compute_mode,
6948                                     simplify_gen_binary (
6949                                       AND, compute_mode,
6950                                       gen_lowpart (compute_mode, SET_SRC (x)),
6951                                       mask),
6952                                     pos);
6953
6954       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6955                        simplify_gen_binary (IOR, compute_mode,
6956                                             cleared, masked));
6957     }
6958
6959   return x;
6960 }
6961 \f
6962 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
6963    it is an RTX that represents the (variable) starting position; otherwise,
6964    POS is the (constant) starting bit position.  Both are counted from the LSB.
6965
6966    UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
6967
6968    IN_DEST is nonzero if this is a reference in the destination of a SET.
6969    This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
6970    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6971    be used.
6972
6973    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
6974    ZERO_EXTRACT should be built even for bits starting at bit 0.
6975
6976    MODE is the desired mode of the result (if IN_DEST == 0).
6977
6978    The result is an RTX for the extraction or NULL_RTX if the target
6979    can't handle it.  */
6980
6981 static rtx
6982 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6983                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6984                  int in_dest, int in_compare)
6985 {
6986   /* This mode describes the size of the storage area
6987      to fetch the overall value from.  Within that, we
6988      ignore the POS lowest bits, etc.  */
6989   enum machine_mode is_mode = GET_MODE (inner);
6990   enum machine_mode inner_mode;
6991   enum machine_mode wanted_inner_mode;
6992   enum machine_mode wanted_inner_reg_mode = word_mode;
6993   enum machine_mode pos_mode = word_mode;
6994   enum machine_mode extraction_mode = word_mode;
6995   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6996   rtx new_rtx = 0;
6997   rtx orig_pos_rtx = pos_rtx;
6998   HOST_WIDE_INT orig_pos;
6999
7000   if (pos_rtx && CONST_INT_P (pos_rtx))
7001     pos = INTVAL (pos_rtx), pos_rtx = 0;
7002
7003   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7004     {
7005       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7006          consider just the QI as the memory to extract from.
7007          The subreg adds or removes high bits; its mode is
7008          irrelevant to the meaning of this extraction,
7009          since POS and LEN count from the lsb.  */
7010       if (MEM_P (SUBREG_REG (inner)))
7011         is_mode = GET_MODE (SUBREG_REG (inner));
7012       inner = SUBREG_REG (inner);
7013     }
7014   else if (GET_CODE (inner) == ASHIFT
7015            && CONST_INT_P (XEXP (inner, 1))
7016            && pos_rtx == 0 && pos == 0
7017            && len > UINTVAL (XEXP (inner, 1)))
7018     {
7019       /* We're extracting the least significant bits of an rtx
7020          (ashift X (const_int C)), where LEN > C.  Extract the
7021          least significant (LEN - C) bits of X, giving an rtx
7022          whose mode is MODE, then shift it left C times.  */
7023       new_rtx = make_extraction (mode, XEXP (inner, 0),
7024                              0, 0, len - INTVAL (XEXP (inner, 1)),
7025                              unsignedp, in_dest, in_compare);
7026       if (new_rtx != 0)
7027         return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7028     }
7029
7030   inner_mode = GET_MODE (inner);
7031
7032   /* See if this can be done without an extraction.  We never can if the
7033      width of the field is not the same as that of some integer mode. For
7034      registers, we can only avoid the extraction if the position is at the
7035      low-order bit and this is either not in the destination or we have the
7036      appropriate STRICT_LOW_PART operation available.
7037
7038      For MEM, we can avoid an extract if the field starts on an appropriate
7039      boundary and we can change the mode of the memory reference.  */
7040
7041   if (tmode != BLKmode
7042       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7043            && !MEM_P (inner)
7044            && (inner_mode == tmode
7045                || !REG_P (inner)
7046                || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7047                || reg_truncated_to_mode (tmode, inner))
7048            && (! in_dest
7049                || (REG_P (inner)
7050                    && have_insn_for (STRICT_LOW_PART, tmode))))
7051           || (MEM_P (inner) && pos_rtx == 0
7052               && (pos
7053                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7054                      : BITS_PER_UNIT)) == 0
7055               /* We can't do this if we are widening INNER_MODE (it
7056                  may not be aligned, for one thing).  */
7057               && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7058               && (inner_mode == tmode
7059                   || (! mode_dependent_address_p (XEXP (inner, 0),
7060                                                   MEM_ADDR_SPACE (inner))
7061                       && ! MEM_VOLATILE_P (inner))))))
7062     {
7063       /* If INNER is a MEM, make a new MEM that encompasses just the desired
7064          field.  If the original and current mode are the same, we need not
7065          adjust the offset.  Otherwise, we do if bytes big endian.
7066
7067          If INNER is not a MEM, get a piece consisting of just the field
7068          of interest (in this case POS % BITS_PER_WORD must be 0).  */
7069
7070       if (MEM_P (inner))
7071         {
7072           HOST_WIDE_INT offset;
7073
7074           /* POS counts from lsb, but make OFFSET count in memory order.  */
7075           if (BYTES_BIG_ENDIAN)
7076             offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7077           else
7078             offset = pos / BITS_PER_UNIT;
7079
7080           new_rtx = adjust_address_nv (inner, tmode, offset);
7081         }
7082       else if (REG_P (inner))
7083         {
7084           if (tmode != inner_mode)
7085             {
7086               /* We can't call gen_lowpart in a DEST since we
7087                  always want a SUBREG (see below) and it would sometimes
7088                  return a new hard register.  */
7089               if (pos || in_dest)
7090                 {
7091                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7092
7093                   if (WORDS_BIG_ENDIAN
7094                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7095                     final_word = ((GET_MODE_SIZE (inner_mode)
7096                                    - GET_MODE_SIZE (tmode))
7097                                   / UNITS_PER_WORD) - final_word;
7098
7099                   final_word *= UNITS_PER_WORD;
7100                   if (BYTES_BIG_ENDIAN &&
7101                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7102                     final_word += (GET_MODE_SIZE (inner_mode)
7103                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7104
7105                   /* Avoid creating invalid subregs, for example when
7106                      simplifying (x>>32)&255.  */
7107                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
7108                     return NULL_RTX;
7109
7110                   new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7111                 }
7112               else
7113                 new_rtx = gen_lowpart (tmode, inner);
7114             }
7115           else
7116             new_rtx = inner;
7117         }
7118       else
7119         new_rtx = force_to_mode (inner, tmode,
7120                              len >= HOST_BITS_PER_WIDE_INT
7121                              ? ~(unsigned HOST_WIDE_INT) 0
7122                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7123                              0);
7124
7125       /* If this extraction is going into the destination of a SET,
7126          make a STRICT_LOW_PART unless we made a MEM.  */
7127
7128       if (in_dest)
7129         return (MEM_P (new_rtx) ? new_rtx
7130                 : (GET_CODE (new_rtx) != SUBREG
7131                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
7132                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7133
7134       if (mode == tmode)
7135         return new_rtx;
7136
7137       if (CONST_INT_P (new_rtx) || CONST_DOUBLE_AS_INT_P (new_rtx))
7138         return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7139                                          mode, new_rtx, tmode);
7140
7141       /* If we know that no extraneous bits are set, and that the high
7142          bit is not set, convert the extraction to the cheaper of
7143          sign and zero extension, that are equivalent in these cases.  */
7144       if (flag_expensive_optimizations
7145           && (HWI_COMPUTABLE_MODE_P (tmode)
7146               && ((nonzero_bits (new_rtx, tmode)
7147                    & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7148                   == 0)))
7149         {
7150           rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7151           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7152
7153           /* Prefer ZERO_EXTENSION, since it gives more information to
7154              backends.  */
7155           if (set_src_cost (temp, optimize_this_for_speed_p)
7156               <= set_src_cost (temp1, optimize_this_for_speed_p))
7157             return temp;
7158           return temp1;
7159         }
7160
7161       /* Otherwise, sign- or zero-extend unless we already are in the
7162          proper mode.  */
7163
7164       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7165                              mode, new_rtx));
7166     }
7167
7168   /* Unless this is a COMPARE or we have a funny memory reference,
7169      don't do anything with zero-extending field extracts starting at
7170      the low-order bit since they are simple AND operations.  */
7171   if (pos_rtx == 0 && pos == 0 && ! in_dest
7172       && ! in_compare && unsignedp)
7173     return 0;
7174
7175   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7176      if the position is not a constant and the length is not 1.  In all
7177      other cases, we would only be going outside our object in cases when
7178      an original shift would have been undefined.  */
7179   if (MEM_P (inner)
7180       && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7181           || (pos_rtx != 0 && len != 1)))
7182     return 0;
7183
7184   /* Get the mode to use should INNER not be a MEM, the mode for the position,
7185      and the mode for the result.  */
7186   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7187     {
7188       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7189       pos_mode = mode_for_extraction (EP_insv, 2);
7190       extraction_mode = mode_for_extraction (EP_insv, 3);
7191     }
7192
7193   if (! in_dest && unsignedp
7194       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7195     {
7196       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7197       pos_mode = mode_for_extraction (EP_extzv, 3);
7198       extraction_mode = mode_for_extraction (EP_extzv, 0);
7199     }
7200
7201   if (! in_dest && ! unsignedp
7202       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7203     {
7204       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7205       pos_mode = mode_for_extraction (EP_extv, 3);
7206       extraction_mode = mode_for_extraction (EP_extv, 0);
7207     }
7208
7209   /* Never narrow an object, since that might not be safe.  */
7210
7211   if (mode != VOIDmode
7212       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7213     extraction_mode = mode;
7214
7215   /* If this is not from memory, the desired mode is the preferred mode
7216      for an extraction pattern's first input operand, or word_mode if there
7217      is none.  */
7218   if (!MEM_P (inner))
7219     wanted_inner_mode = wanted_inner_reg_mode;
7220   else
7221     {
7222       /* Be careful not to go beyond the extracted object and maintain the
7223          natural alignment of the memory.  */
7224       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7225       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7226              > GET_MODE_BITSIZE (wanted_inner_mode))
7227         {
7228           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7229           gcc_assert (wanted_inner_mode != VOIDmode);
7230         }
7231     }
7232
7233   orig_pos = pos;
7234
7235   if (BITS_BIG_ENDIAN)
7236     {
7237       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7238          BITS_BIG_ENDIAN style.  If position is constant, compute new
7239          position.  Otherwise, build subtraction.
7240          Note that POS is relative to the mode of the original argument.
7241          If it's a MEM we need to recompute POS relative to that.
7242          However, if we're extracting from (or inserting into) a register,
7243          we want to recompute POS relative to wanted_inner_mode.  */
7244       int width = (MEM_P (inner)
7245                    ? GET_MODE_BITSIZE (is_mode)
7246                    : GET_MODE_BITSIZE (wanted_inner_mode));
7247
7248       if (pos_rtx == 0)
7249         pos = width - len - pos;
7250       else
7251         pos_rtx
7252           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7253       /* POS may be less than 0 now, but we check for that below.
7254          Note that it can only be less than 0 if !MEM_P (inner).  */
7255     }
7256
7257   /* If INNER has a wider mode, and this is a constant extraction, try to
7258      make it smaller and adjust the byte to point to the byte containing
7259      the value.  */
7260   if (wanted_inner_mode != VOIDmode
7261       && inner_mode != wanted_inner_mode
7262       && ! pos_rtx
7263       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7264       && MEM_P (inner)
7265       && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7266       && ! MEM_VOLATILE_P (inner))
7267     {
7268       int offset = 0;
7269
7270       /* The computations below will be correct if the machine is big
7271          endian in both bits and bytes or little endian in bits and bytes.
7272          If it is mixed, we must adjust.  */
7273
7274       /* If bytes are big endian and we had a paradoxical SUBREG, we must
7275          adjust OFFSET to compensate.  */
7276       if (BYTES_BIG_ENDIAN
7277           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7278         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7279
7280       /* We can now move to the desired byte.  */
7281       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7282                 * GET_MODE_SIZE (wanted_inner_mode);
7283       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7284
7285       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7286           && is_mode != wanted_inner_mode)
7287         offset = (GET_MODE_SIZE (is_mode)
7288                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
7289
7290       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7291     }
7292
7293   /* If INNER is not memory, get it into the proper mode.  If we are changing
7294      its mode, POS must be a constant and smaller than the size of the new
7295      mode.  */
7296   else if (!MEM_P (inner))
7297     {
7298       /* On the LHS, don't create paradoxical subregs implicitely truncating
7299          the register unless TRULY_NOOP_TRUNCATION.  */
7300       if (in_dest
7301           && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7302                                              wanted_inner_mode))
7303         return NULL_RTX;
7304
7305       if (GET_MODE (inner) != wanted_inner_mode
7306           && (pos_rtx != 0
7307               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7308         return NULL_RTX;
7309
7310       if (orig_pos < 0)
7311         return NULL_RTX;
7312
7313       inner = force_to_mode (inner, wanted_inner_mode,
7314                              pos_rtx
7315                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7316                              ? ~(unsigned HOST_WIDE_INT) 0
7317                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7318                                 << orig_pos),
7319                              0);
7320     }
7321
7322   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
7323      have to zero extend.  Otherwise, we can just use a SUBREG.  */
7324   if (pos_rtx != 0
7325       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7326     {
7327       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7328
7329       /* If we know that no extraneous bits are set, and that the high
7330          bit is not set, convert extraction to cheaper one - either
7331          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7332          cases.  */
7333       if (flag_expensive_optimizations
7334           && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7335               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7336                    & ~(((unsigned HOST_WIDE_INT)
7337                         GET_MODE_MASK (GET_MODE (pos_rtx)))
7338                        >> 1))
7339                   == 0)))
7340         {
7341           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7342
7343           /* Prefer ZERO_EXTENSION, since it gives more information to
7344              backends.  */
7345           if (set_src_cost (temp1, optimize_this_for_speed_p)
7346               < set_src_cost (temp, optimize_this_for_speed_p))
7347             temp = temp1;
7348         }
7349       pos_rtx = temp;
7350     }
7351
7352   /* Make POS_RTX unless we already have it and it is correct.  If we don't
7353      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7354      be a CONST_INT.  */
7355   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7356     pos_rtx = orig_pos_rtx;
7357
7358   else if (pos_rtx == 0)
7359     pos_rtx = GEN_INT (pos);
7360
7361   /* Make the required operation.  See if we can use existing rtx.  */
7362   new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7363                          extraction_mode, inner, GEN_INT (len), pos_rtx);
7364   if (! in_dest)
7365     new_rtx = gen_lowpart (mode, new_rtx);
7366
7367   return new_rtx;
7368 }
7369 \f
7370 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7371    with any other operations in X.  Return X without that shift if so.  */
7372
7373 static rtx
7374 extract_left_shift (rtx x, int count)
7375 {
7376   enum rtx_code code = GET_CODE (x);
7377   enum machine_mode mode = GET_MODE (x);
7378   rtx tem;
7379
7380   switch (code)
7381     {
7382     case ASHIFT:
7383       /* This is the shift itself.  If it is wide enough, we will return
7384          either the value being shifted if the shift count is equal to
7385          COUNT or a shift for the difference.  */
7386       if (CONST_INT_P (XEXP (x, 1))
7387           && INTVAL (XEXP (x, 1)) >= count)
7388         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7389                                      INTVAL (XEXP (x, 1)) - count);
7390       break;
7391
7392     case NEG:  case NOT:
7393       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7394         return simplify_gen_unary (code, mode, tem, mode);
7395
7396       break;
7397
7398     case PLUS:  case IOR:  case XOR:  case AND:
7399       /* If we can safely shift this constant and we find the inner shift,
7400          make a new operation.  */
7401       if (CONST_INT_P (XEXP (x, 1))
7402           && (UINTVAL (XEXP (x, 1))
7403               & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7404           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7405         return simplify_gen_binary (code, mode, tem,
7406                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7407
7408       break;
7409
7410     default:
7411       break;
7412     }
7413
7414   return 0;
7415 }
7416 \f
7417 /* Look at the expression rooted at X.  Look for expressions
7418    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7419    Form these expressions.
7420
7421    Return the new rtx, usually just X.
7422
7423    Also, for machines like the VAX that don't have logical shift insns,
7424    try to convert logical to arithmetic shift operations in cases where
7425    they are equivalent.  This undoes the canonicalizations to logical
7426    shifts done elsewhere.
7427
7428    We try, as much as possible, to re-use rtl expressions to save memory.
7429
7430    IN_CODE says what kind of expression we are processing.  Normally, it is
7431    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
7432    being kludges), it is MEM.  When processing the arguments of a comparison
7433    or a COMPARE against zero, it is COMPARE.  */
7434
7435 rtx
7436 make_compound_operation (rtx x, enum rtx_code in_code)
7437 {
7438   enum rtx_code code = GET_CODE (x);
7439   enum machine_mode mode = GET_MODE (x);
7440   int mode_width = GET_MODE_PRECISION (mode);
7441   rtx rhs, lhs;
7442   enum rtx_code next_code;
7443   int i, j;
7444   rtx new_rtx = 0;
7445   rtx tem;
7446   const char *fmt;
7447
7448   /* Select the code to be used in recursive calls.  Once we are inside an
7449      address, we stay there.  If we have a comparison, set to COMPARE,
7450      but once inside, go back to our default of SET.  */
7451
7452   next_code = (code == MEM ? MEM
7453                : ((code == PLUS || code == MINUS)
7454                   && SCALAR_INT_MODE_P (mode)) ? MEM
7455                : ((code == COMPARE || COMPARISON_P (x))
7456                   && XEXP (x, 1) == const0_rtx) ? COMPARE
7457                : in_code == COMPARE ? SET : in_code);
7458
7459   /* Process depending on the code of this operation.  If NEW is set
7460      nonzero, it will be returned.  */
7461
7462   switch (code)
7463     {
7464     case ASHIFT:
7465       /* Convert shifts by constants into multiplications if inside
7466          an address.  */
7467       if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7468           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7469           && INTVAL (XEXP (x, 1)) >= 0
7470           && SCALAR_INT_MODE_P (mode))
7471         {
7472           HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7473           HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7474
7475           new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7476           if (GET_CODE (new_rtx) == NEG)
7477             {
7478               new_rtx = XEXP (new_rtx, 0);
7479               multval = -multval;
7480             }
7481           multval = trunc_int_for_mode (multval, mode);
7482           new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7483         }
7484       break;
7485
7486     case PLUS:
7487       lhs = XEXP (x, 0);
7488       rhs = XEXP (x, 1);
7489       lhs = make_compound_operation (lhs, next_code);
7490       rhs = make_compound_operation (rhs, next_code);
7491       if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7492           && SCALAR_INT_MODE_P (mode))
7493         {
7494           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7495                                      XEXP (lhs, 1));
7496           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7497         }
7498       else if (GET_CODE (lhs) == MULT
7499                && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7500         {
7501           tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7502                                      simplify_gen_unary (NEG, mode,
7503                                                          XEXP (lhs, 1),
7504                                                          mode));
7505           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7506         }
7507       else
7508         {
7509           SUBST (XEXP (x, 0), lhs);
7510           SUBST (XEXP (x, 1), rhs);
7511           goto maybe_swap;
7512         }
7513       x = gen_lowpart (mode, new_rtx);
7514       goto maybe_swap;
7515
7516     case MINUS:
7517       lhs = XEXP (x, 0);
7518       rhs = XEXP (x, 1);
7519       lhs = make_compound_operation (lhs, next_code);
7520       rhs = make_compound_operation (rhs, next_code);
7521       if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7522           && SCALAR_INT_MODE_P (mode))
7523         {
7524           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7525                                      XEXP (rhs, 1));
7526           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7527         }
7528       else if (GET_CODE (rhs) == MULT
7529                && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7530         {
7531           tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7532                                      simplify_gen_unary (NEG, mode,
7533                                                          XEXP (rhs, 1),
7534                                                          mode));
7535           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7536         }
7537       else
7538         {
7539           SUBST (XEXP (x, 0), lhs);
7540           SUBST (XEXP (x, 1), rhs);
7541           return x;
7542         }
7543       return gen_lowpart (mode, new_rtx);
7544
7545     case AND:
7546       /* If the second operand is not a constant, we can't do anything
7547          with it.  */
7548       if (!CONST_INT_P (XEXP (x, 1)))
7549         break;
7550
7551       /* If the constant is a power of two minus one and the first operand
7552          is a logical right shift, make an extraction.  */
7553       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7554           && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7555         {
7556           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7557           new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7558                                  0, in_code == COMPARE);
7559         }
7560
7561       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
7562       else if (GET_CODE (XEXP (x, 0)) == SUBREG
7563                && subreg_lowpart_p (XEXP (x, 0))
7564                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7565                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7566         {
7567           new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7568                                          next_code);
7569           new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7570                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7571                                  0, in_code == COMPARE);
7572         }
7573       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
7574       else if ((GET_CODE (XEXP (x, 0)) == XOR
7575                 || GET_CODE (XEXP (x, 0)) == IOR)
7576                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7577                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7578                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7579         {
7580           /* Apply the distributive law, and then try to make extractions.  */
7581           new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7582                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7583                                              XEXP (x, 1)),
7584                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7585                                              XEXP (x, 1)));
7586           new_rtx = make_compound_operation (new_rtx, in_code);
7587         }
7588
7589       /* If we are have (and (rotate X C) M) and C is larger than the number
7590          of bits in M, this is an extraction.  */
7591
7592       else if (GET_CODE (XEXP (x, 0)) == ROTATE
7593                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7594                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7595                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7596         {
7597           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7598           new_rtx = make_extraction (mode, new_rtx,
7599                                  (GET_MODE_PRECISION (mode)
7600                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
7601                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
7602         }
7603
7604       /* On machines without logical shifts, if the operand of the AND is
7605          a logical shift and our mask turns off all the propagated sign
7606          bits, we can replace the logical shift with an arithmetic shift.  */
7607       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7608                && !have_insn_for (LSHIFTRT, mode)
7609                && have_insn_for (ASHIFTRT, mode)
7610                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7611                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7612                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7613                && mode_width <= HOST_BITS_PER_WIDE_INT)
7614         {
7615           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7616
7617           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7618           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7619             SUBST (XEXP (x, 0),
7620                    gen_rtx_ASHIFTRT (mode,
7621                                      make_compound_operation
7622                                      (XEXP (XEXP (x, 0), 0), next_code),
7623                                      XEXP (XEXP (x, 0), 1)));
7624         }
7625
7626       /* If the constant is one less than a power of two, this might be
7627          representable by an extraction even if no shift is present.
7628          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7629          we are in a COMPARE.  */
7630       else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7631         new_rtx = make_extraction (mode,
7632                                make_compound_operation (XEXP (x, 0),
7633                                                         next_code),
7634                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7635
7636       /* If we are in a comparison and this is an AND with a power of two,
7637          convert this into the appropriate bit extract.  */
7638       else if (in_code == COMPARE
7639                && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7640         new_rtx = make_extraction (mode,
7641                                make_compound_operation (XEXP (x, 0),
7642                                                         next_code),
7643                                i, NULL_RTX, 1, 1, 0, 1);
7644
7645       break;
7646
7647     case LSHIFTRT:
7648       /* If the sign bit is known to be zero, replace this with an
7649          arithmetic shift.  */
7650       if (have_insn_for (ASHIFTRT, mode)
7651           && ! have_insn_for (LSHIFTRT, mode)
7652           && mode_width <= HOST_BITS_PER_WIDE_INT
7653           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7654         {
7655           new_rtx = gen_rtx_ASHIFTRT (mode,
7656                                   make_compound_operation (XEXP (x, 0),
7657                                                            next_code),
7658                                   XEXP (x, 1));
7659           break;
7660         }
7661
7662       /* ... fall through ...  */
7663
7664     case ASHIFTRT:
7665       lhs = XEXP (x, 0);
7666       rhs = XEXP (x, 1);
7667
7668       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7669          this is a SIGN_EXTRACT.  */
7670       if (CONST_INT_P (rhs)
7671           && GET_CODE (lhs) == ASHIFT
7672           && CONST_INT_P (XEXP (lhs, 1))
7673           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7674           && INTVAL (XEXP (lhs, 1)) >= 0
7675           && INTVAL (rhs) < mode_width)
7676         {
7677           new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7678           new_rtx = make_extraction (mode, new_rtx,
7679                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7680                                  NULL_RTX, mode_width - INTVAL (rhs),
7681                                  code == LSHIFTRT, 0, in_code == COMPARE);
7682           break;
7683         }
7684
7685       /* See if we have operations between an ASHIFTRT and an ASHIFT.
7686          If so, try to merge the shifts into a SIGN_EXTEND.  We could
7687          also do this for some cases of SIGN_EXTRACT, but it doesn't
7688          seem worth the effort; the case checked for occurs on Alpha.  */
7689
7690       if (!OBJECT_P (lhs)
7691           && ! (GET_CODE (lhs) == SUBREG
7692                 && (OBJECT_P (SUBREG_REG (lhs))))
7693           && CONST_INT_P (rhs)
7694           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7695           && INTVAL (rhs) < mode_width
7696           && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7697         new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7698                                0, NULL_RTX, mode_width - INTVAL (rhs),
7699                                code == LSHIFTRT, 0, in_code == COMPARE);
7700
7701       break;
7702
7703     case SUBREG:
7704       /* Call ourselves recursively on the inner expression.  If we are
7705          narrowing the object and it has a different RTL code from
7706          what it originally did, do this SUBREG as a force_to_mode.  */
7707       {
7708         rtx inner = SUBREG_REG (x), simplified;
7709
7710         tem = make_compound_operation (inner, in_code);
7711
7712         simplified
7713           = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7714         if (simplified)
7715           tem = simplified;
7716
7717         if (GET_CODE (tem) != GET_CODE (inner)
7718             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7719             && subreg_lowpart_p (x))
7720           {
7721             rtx newer
7722               = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7723
7724             /* If we have something other than a SUBREG, we might have
7725                done an expansion, so rerun ourselves.  */
7726             if (GET_CODE (newer) != SUBREG)
7727               newer = make_compound_operation (newer, in_code);
7728
7729             /* force_to_mode can expand compounds.  If it just re-expanded the
7730                compound, use gen_lowpart to convert to the desired mode.  */
7731             if (rtx_equal_p (newer, x)
7732                 /* Likewise if it re-expanded the compound only partially.
7733                    This happens for SUBREG of ZERO_EXTRACT if they extract
7734                    the same number of bits.  */
7735                 || (GET_CODE (newer) == SUBREG
7736                     && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7737                         || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7738                     && GET_CODE (inner) == AND
7739                     && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7740               return gen_lowpart (GET_MODE (x), tem);
7741
7742             return newer;
7743           }
7744
7745         if (simplified)
7746           return tem;
7747       }
7748       break;
7749
7750     default:
7751       break;
7752     }
7753
7754   if (new_rtx)
7755     {
7756       x = gen_lowpart (mode, new_rtx);
7757       code = GET_CODE (x);
7758     }
7759
7760   /* Now recursively process each operand of this operation.  We need to
7761      handle ZERO_EXTEND specially so that we don't lose track of the
7762      inner mode.  */
7763   if (GET_CODE (x) == ZERO_EXTEND)
7764     {
7765       new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7766       tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7767                                             new_rtx, GET_MODE (XEXP (x, 0)));
7768       if (tem)
7769         return tem;
7770       SUBST (XEXP (x, 0), new_rtx);
7771       return x;
7772     }
7773
7774   fmt = GET_RTX_FORMAT (code);
7775   for (i = 0; i < GET_RTX_LENGTH (code); i++)
7776     if (fmt[i] == 'e')
7777       {
7778         new_rtx = make_compound_operation (XEXP (x, i), next_code);
7779         SUBST (XEXP (x, i), new_rtx);
7780       }
7781     else if (fmt[i] == 'E')
7782       for (j = 0; j < XVECLEN (x, i); j++)
7783         {
7784           new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7785           SUBST (XVECEXP (x, i, j), new_rtx);
7786         }
7787
7788  maybe_swap:
7789   /* If this is a commutative operation, the changes to the operands
7790      may have made it noncanonical.  */
7791   if (COMMUTATIVE_ARITH_P (x)
7792       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7793     {
7794       tem = XEXP (x, 0);
7795       SUBST (XEXP (x, 0), XEXP (x, 1));
7796       SUBST (XEXP (x, 1), tem);
7797     }
7798
7799   return x;
7800 }
7801 \f
7802 /* Given M see if it is a value that would select a field of bits
7803    within an item, but not the entire word.  Return -1 if not.
7804    Otherwise, return the starting position of the field, where 0 is the
7805    low-order bit.
7806
7807    *PLEN is set to the length of the field.  */
7808
7809 static int
7810 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7811 {
7812   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
7813   int pos = m ? ctz_hwi (m) : -1;
7814   int len = 0;
7815
7816   if (pos >= 0)
7817     /* Now shift off the low-order zero bits and see if we have a
7818        power of two minus 1.  */
7819     len = exact_log2 ((m >> pos) + 1);
7820
7821   if (len <= 0)
7822     pos = -1;
7823
7824   *plen = len;
7825   return pos;
7826 }
7827 \f
7828 /* If X refers to a register that equals REG in value, replace these
7829    references with REG.  */
7830 static rtx
7831 canon_reg_for_combine (rtx x, rtx reg)
7832 {
7833   rtx op0, op1, op2;
7834   const char *fmt;
7835   int i;
7836   bool copied;
7837
7838   enum rtx_code code = GET_CODE (x);
7839   switch (GET_RTX_CLASS (code))
7840     {
7841     case RTX_UNARY:
7842       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7843       if (op0 != XEXP (x, 0))
7844         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7845                                    GET_MODE (reg));
7846       break;
7847
7848     case RTX_BIN_ARITH:
7849     case RTX_COMM_ARITH:
7850       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7851       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7852       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7853         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7854       break;
7855
7856     case RTX_COMPARE:
7857     case RTX_COMM_COMPARE:
7858       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7859       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7860       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7861         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7862                                         GET_MODE (op0), op0, op1);
7863       break;
7864
7865     case RTX_TERNARY:
7866     case RTX_BITFIELD_OPS:
7867       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7868       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7869       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7870       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7871         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7872                                      GET_MODE (op0), op0, op1, op2);
7873
7874     case RTX_OBJ:
7875       if (REG_P (x))
7876         {
7877           if (rtx_equal_p (get_last_value (reg), x)
7878               || rtx_equal_p (reg, get_last_value (x)))
7879             return reg;
7880           else
7881             break;
7882         }
7883
7884       /* fall through */
7885
7886     default:
7887       fmt = GET_RTX_FORMAT (code);
7888       copied = false;
7889       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7890         if (fmt[i] == 'e')
7891           {
7892             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7893             if (op != XEXP (x, i))
7894               {
7895                 if (!copied)
7896                   {
7897                     copied = true;
7898                     x = copy_rtx (x);
7899                   }
7900                 XEXP (x, i) = op;
7901               }
7902           }
7903         else if (fmt[i] == 'E')
7904           {
7905             int j;
7906             for (j = 0; j < XVECLEN (x, i); j++)
7907               {
7908                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7909                 if (op != XVECEXP (x, i, j))
7910                   {
7911                     if (!copied)
7912                       {
7913                         copied = true;
7914                         x = copy_rtx (x);
7915                       }
7916                     XVECEXP (x, i, j) = op;
7917                   }
7918               }
7919           }
7920
7921       break;
7922     }
7923
7924   return x;
7925 }
7926
7927 /* Return X converted to MODE.  If the value is already truncated to
7928    MODE we can just return a subreg even though in the general case we
7929    would need an explicit truncation.  */
7930
7931 static rtx
7932 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7933 {
7934   if (!CONST_INT_P (x)
7935       && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7936       && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
7937       && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7938     {
7939       /* Bit-cast X into an integer mode.  */
7940       if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7941         x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7942       x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7943                               x, GET_MODE (x));
7944     }
7945
7946   return gen_lowpart (mode, x);
7947 }
7948
7949 /* See if X can be simplified knowing that we will only refer to it in
7950    MODE and will only refer to those bits that are nonzero in MASK.
7951    If other bits are being computed or if masking operations are done
7952    that select a superset of the bits in MASK, they can sometimes be
7953    ignored.
7954
7955    Return a possibly simplified expression, but always convert X to
7956    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
7957
7958    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7959    are all off in X.  This is used when X will be complemented, by either
7960    NOT, NEG, or XOR.  */
7961
7962 static rtx
7963 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7964                int just_select)
7965 {
7966   enum rtx_code code = GET_CODE (x);
7967   int next_select = just_select || code == XOR || code == NOT || code == NEG;
7968   enum machine_mode op_mode;
7969   unsigned HOST_WIDE_INT fuller_mask, nonzero;
7970   rtx op0, op1, temp;
7971
7972   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
7973      code below will do the wrong thing since the mode of such an
7974      expression is VOIDmode.
7975
7976      Also do nothing if X is a CLOBBER; this can happen if X was
7977      the return value from a call to gen_lowpart.  */
7978   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7979     return x;
7980
7981   /* We want to perform the operation is its present mode unless we know
7982      that the operation is valid in MODE, in which case we do the operation
7983      in MODE.  */
7984   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7985               && have_insn_for (code, mode))
7986              ? mode : GET_MODE (x));
7987
7988   /* It is not valid to do a right-shift in a narrower mode
7989      than the one it came in with.  */
7990   if ((code == LSHIFTRT || code == ASHIFTRT)
7991       && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
7992     op_mode = GET_MODE (x);
7993
7994   /* Truncate MASK to fit OP_MODE.  */
7995   if (op_mode)
7996     mask &= GET_MODE_MASK (op_mode);
7997
7998   /* When we have an arithmetic operation, or a shift whose count we
7999      do not know, we need to assume that all bits up to the highest-order
8000      bit in MASK will be needed.  This is how we form such a mask.  */
8001   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8002     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8003   else
8004     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8005                    - 1);
8006
8007   /* Determine what bits of X are guaranteed to be (non)zero.  */
8008   nonzero = nonzero_bits (x, mode);
8009
8010   /* If none of the bits in X are needed, return a zero.  */
8011   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8012     x = const0_rtx;
8013
8014   /* If X is a CONST_INT, return a new one.  Do this here since the
8015      test below will fail.  */
8016   if (CONST_INT_P (x))
8017     {
8018       if (SCALAR_INT_MODE_P (mode))
8019         return gen_int_mode (INTVAL (x) & mask, mode);
8020       else
8021         {
8022           x = GEN_INT (INTVAL (x) & mask);
8023           return gen_lowpart_common (mode, x);
8024         }
8025     }
8026
8027   /* If X is narrower than MODE and we want all the bits in X's mode, just
8028      get X in the proper mode.  */
8029   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8030       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8031     return gen_lowpart (mode, x);
8032
8033   /* We can ignore the effect of a SUBREG if it narrows the mode or
8034      if the constant masks to zero all the bits the mode doesn't have.  */
8035   if (GET_CODE (x) == SUBREG
8036       && subreg_lowpart_p (x)
8037       && ((GET_MODE_SIZE (GET_MODE (x))
8038            < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8039           || (0 == (mask
8040                     & GET_MODE_MASK (GET_MODE (x))
8041                     & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8042     return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8043
8044   /* The arithmetic simplifications here only work for scalar integer modes.  */
8045   if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8046     return gen_lowpart_or_truncate (mode, x);
8047
8048   switch (code)
8049     {
8050     case CLOBBER:
8051       /* If X is a (clobber (const_int)), return it since we know we are
8052          generating something that won't match.  */
8053       return x;
8054
8055     case SIGN_EXTEND:
8056     case ZERO_EXTEND:
8057     case ZERO_EXTRACT:
8058     case SIGN_EXTRACT:
8059       x = expand_compound_operation (x);
8060       if (GET_CODE (x) != code)
8061         return force_to_mode (x, mode, mask, next_select);
8062       break;
8063
8064     case TRUNCATE:
8065       /* Similarly for a truncate.  */
8066       return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8067
8068     case AND:
8069       /* If this is an AND with a constant, convert it into an AND
8070          whose constant is the AND of that constant with MASK.  If it
8071          remains an AND of MASK, delete it since it is redundant.  */
8072
8073       if (CONST_INT_P (XEXP (x, 1)))
8074         {
8075           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8076                                       mask & INTVAL (XEXP (x, 1)));
8077
8078           /* If X is still an AND, see if it is an AND with a mask that
8079              is just some low-order bits.  If so, and it is MASK, we don't
8080              need it.  */
8081
8082           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8083               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8084                   == mask))
8085             x = XEXP (x, 0);
8086
8087           /* If it remains an AND, try making another AND with the bits
8088              in the mode mask that aren't in MASK turned on.  If the
8089              constant in the AND is wide enough, this might make a
8090              cheaper constant.  */
8091
8092           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8093               && GET_MODE_MASK (GET_MODE (x)) != mask
8094               && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8095             {
8096               unsigned HOST_WIDE_INT cval
8097                 = UINTVAL (XEXP (x, 1))
8098                   | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8099               int width = GET_MODE_PRECISION (GET_MODE (x));
8100               rtx y;
8101
8102               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8103                  number, sign extend it.  */
8104               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8105                   && (cval & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8106                 cval |= (unsigned HOST_WIDE_INT) -1 << width;
8107
8108               y = simplify_gen_binary (AND, GET_MODE (x),
8109                                        XEXP (x, 0), GEN_INT (cval));
8110               if (set_src_cost (y, optimize_this_for_speed_p)
8111                   < set_src_cost (x, optimize_this_for_speed_p))
8112                 x = y;
8113             }
8114
8115           break;
8116         }
8117
8118       goto binop;
8119
8120     case PLUS:
8121       /* In (and (plus FOO C1) M), if M is a mask that just turns off
8122          low-order bits (as in an alignment operation) and FOO is already
8123          aligned to that boundary, mask C1 to that boundary as well.
8124          This may eliminate that PLUS and, later, the AND.  */
8125
8126       {
8127         unsigned int width = GET_MODE_PRECISION (mode);
8128         unsigned HOST_WIDE_INT smask = mask;
8129
8130         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8131            number, sign extend it.  */
8132
8133         if (width < HOST_BITS_PER_WIDE_INT
8134             && (smask & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8135           smask |= (unsigned HOST_WIDE_INT) (-1) << width;
8136
8137         if (CONST_INT_P (XEXP (x, 1))
8138             && exact_log2 (- smask) >= 0
8139             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8140             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8141           return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0),
8142                                                (INTVAL (XEXP (x, 1)) & smask)),
8143                                 mode, smask, next_select);
8144       }
8145
8146       /* ... fall through ...  */
8147
8148     case MULT:
8149       /* For PLUS, MINUS and MULT, we need any bits less significant than the
8150          most significant bit in MASK since carries from those bits will
8151          affect the bits we are interested in.  */
8152       mask = fuller_mask;
8153       goto binop;
8154
8155     case MINUS:
8156       /* If X is (minus C Y) where C's least set bit is larger than any bit
8157          in the mask, then we may replace with (neg Y).  */
8158       if (CONST_INT_P (XEXP (x, 0))
8159           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8160                                         & -INTVAL (XEXP (x, 0))))
8161               > mask))
8162         {
8163           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8164                                   GET_MODE (x));
8165           return force_to_mode (x, mode, mask, next_select);
8166         }
8167
8168       /* Similarly, if C contains every bit in the fuller_mask, then we may
8169          replace with (not Y).  */
8170       if (CONST_INT_P (XEXP (x, 0))
8171           && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8172         {
8173           x = simplify_gen_unary (NOT, GET_MODE (x),
8174                                   XEXP (x, 1), GET_MODE (x));
8175           return force_to_mode (x, mode, mask, next_select);
8176         }
8177
8178       mask = fuller_mask;
8179       goto binop;
8180
8181     case IOR:
8182     case XOR:
8183       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8184          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8185          operation which may be a bitfield extraction.  Ensure that the
8186          constant we form is not wider than the mode of X.  */
8187
8188       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8189           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8190           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8191           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8192           && CONST_INT_P (XEXP (x, 1))
8193           && ((INTVAL (XEXP (XEXP (x, 0), 1))
8194                + floor_log2 (INTVAL (XEXP (x, 1))))
8195               < GET_MODE_PRECISION (GET_MODE (x)))
8196           && (UINTVAL (XEXP (x, 1))
8197               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8198         {
8199           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8200                           << INTVAL (XEXP (XEXP (x, 0), 1)));
8201           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8202                                       XEXP (XEXP (x, 0), 0), temp);
8203           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8204                                    XEXP (XEXP (x, 0), 1));
8205           return force_to_mode (x, mode, mask, next_select);
8206         }
8207
8208     binop:
8209       /* For most binary operations, just propagate into the operation and
8210          change the mode if we have an operation of that mode.  */
8211
8212       op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8213       op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8214
8215       /* If we ended up truncating both operands, truncate the result of the
8216          operation instead.  */
8217       if (GET_CODE (op0) == TRUNCATE
8218           && GET_CODE (op1) == TRUNCATE)
8219         {
8220           op0 = XEXP (op0, 0);
8221           op1 = XEXP (op1, 0);
8222         }
8223
8224       op0 = gen_lowpart_or_truncate (op_mode, op0);
8225       op1 = gen_lowpart_or_truncate (op_mode, op1);
8226
8227       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8228         x = simplify_gen_binary (code, op_mode, op0, op1);
8229       break;
8230
8231     case ASHIFT:
8232       /* For left shifts, do the same, but just for the first operand.
8233          However, we cannot do anything with shifts where we cannot
8234          guarantee that the counts are smaller than the size of the mode
8235          because such a count will have a different meaning in a
8236          wider mode.  */
8237
8238       if (! (CONST_INT_P (XEXP (x, 1))
8239              && INTVAL (XEXP (x, 1)) >= 0
8240              && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8241           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8242                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8243                     < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8244         break;
8245
8246       /* If the shift count is a constant and we can do arithmetic in
8247          the mode of the shift, refine which bits we need.  Otherwise, use the
8248          conservative form of the mask.  */
8249       if (CONST_INT_P (XEXP (x, 1))
8250           && INTVAL (XEXP (x, 1)) >= 0
8251           && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8252           && HWI_COMPUTABLE_MODE_P (op_mode))
8253         mask >>= INTVAL (XEXP (x, 1));
8254       else
8255         mask = fuller_mask;
8256
8257       op0 = gen_lowpart_or_truncate (op_mode,
8258                                      force_to_mode (XEXP (x, 0), op_mode,
8259                                                     mask, next_select));
8260
8261       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8262         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8263       break;
8264
8265     case LSHIFTRT:
8266       /* Here we can only do something if the shift count is a constant,
8267          this shift constant is valid for the host, and we can do arithmetic
8268          in OP_MODE.  */
8269
8270       if (CONST_INT_P (XEXP (x, 1))
8271           && INTVAL (XEXP (x, 1)) >= 0
8272           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8273           && HWI_COMPUTABLE_MODE_P (op_mode))
8274         {
8275           rtx inner = XEXP (x, 0);
8276           unsigned HOST_WIDE_INT inner_mask;
8277
8278           /* Select the mask of the bits we need for the shift operand.  */
8279           inner_mask = mask << INTVAL (XEXP (x, 1));
8280
8281           /* We can only change the mode of the shift if we can do arithmetic
8282              in the mode of the shift and INNER_MASK is no wider than the
8283              width of X's mode.  */
8284           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8285             op_mode = GET_MODE (x);
8286
8287           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8288
8289           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8290             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8291         }
8292
8293       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8294          shift and AND produces only copies of the sign bit (C2 is one less
8295          than a power of two), we can do this with just a shift.  */
8296
8297       if (GET_CODE (x) == LSHIFTRT
8298           && CONST_INT_P (XEXP (x, 1))
8299           /* The shift puts one of the sign bit copies in the least significant
8300              bit.  */
8301           && ((INTVAL (XEXP (x, 1))
8302                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8303               >= GET_MODE_PRECISION (GET_MODE (x)))
8304           && exact_log2 (mask + 1) >= 0
8305           /* Number of bits left after the shift must be more than the mask
8306              needs.  */
8307           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8308               <= GET_MODE_PRECISION (GET_MODE (x)))
8309           /* Must be more sign bit copies than the mask needs.  */
8310           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8311               >= exact_log2 (mask + 1)))
8312         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8313                                  GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8314                                           - exact_log2 (mask + 1)));
8315
8316       goto shiftrt;
8317
8318     case ASHIFTRT:
8319       /* If we are just looking for the sign bit, we don't need this shift at
8320          all, even if it has a variable count.  */
8321       if (val_signbit_p (GET_MODE (x), mask))
8322         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8323
8324       /* If this is a shift by a constant, get a mask that contains those bits
8325          that are not copies of the sign bit.  We then have two cases:  If
8326          MASK only includes those bits, this can be a logical shift, which may
8327          allow simplifications.  If MASK is a single-bit field not within
8328          those bits, we are requesting a copy of the sign bit and hence can
8329          shift the sign bit to the appropriate location.  */
8330
8331       if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8332           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8333         {
8334           int i;
8335
8336           /* If the considered data is wider than HOST_WIDE_INT, we can't
8337              represent a mask for all its bits in a single scalar.
8338              But we only care about the lower bits, so calculate these.  */
8339
8340           if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8341             {
8342               nonzero = ~(unsigned HOST_WIDE_INT) 0;
8343
8344               /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8345                  is the number of bits a full-width mask would have set.
8346                  We need only shift if these are fewer than nonzero can
8347                  hold.  If not, we must keep all bits set in nonzero.  */
8348
8349               if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8350                   < HOST_BITS_PER_WIDE_INT)
8351                 nonzero >>= INTVAL (XEXP (x, 1))
8352                             + HOST_BITS_PER_WIDE_INT
8353                             - GET_MODE_PRECISION (GET_MODE (x)) ;
8354             }
8355           else
8356             {
8357               nonzero = GET_MODE_MASK (GET_MODE (x));
8358               nonzero >>= INTVAL (XEXP (x, 1));
8359             }
8360
8361           if ((mask & ~nonzero) == 0)
8362             {
8363               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8364                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
8365               if (GET_CODE (x) != ASHIFTRT)
8366                 return force_to_mode (x, mode, mask, next_select);
8367             }
8368
8369           else if ((i = exact_log2 (mask)) >= 0)
8370             {
8371               x = simplify_shift_const
8372                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8373                    GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8374
8375               if (GET_CODE (x) != ASHIFTRT)
8376                 return force_to_mode (x, mode, mask, next_select);
8377             }
8378         }
8379
8380       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
8381          even if the shift count isn't a constant.  */
8382       if (mask == 1)
8383         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8384                                  XEXP (x, 0), XEXP (x, 1));
8385
8386     shiftrt:
8387
8388       /* If this is a zero- or sign-extension operation that just affects bits
8389          we don't care about, remove it.  Be sure the call above returned
8390          something that is still a shift.  */
8391
8392       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8393           && CONST_INT_P (XEXP (x, 1))
8394           && INTVAL (XEXP (x, 1)) >= 0
8395           && (INTVAL (XEXP (x, 1))
8396               <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8397           && GET_CODE (XEXP (x, 0)) == ASHIFT
8398           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8399         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8400                               next_select);
8401
8402       break;
8403
8404     case ROTATE:
8405     case ROTATERT:
8406       /* If the shift count is constant and we can do computations
8407          in the mode of X, compute where the bits we care about are.
8408          Otherwise, we can't do anything.  Don't change the mode of
8409          the shift or propagate MODE into the shift, though.  */
8410       if (CONST_INT_P (XEXP (x, 1))
8411           && INTVAL (XEXP (x, 1)) >= 0)
8412         {
8413           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8414                                             GET_MODE (x), GEN_INT (mask),
8415                                             XEXP (x, 1));
8416           if (temp && CONST_INT_P (temp))
8417             SUBST (XEXP (x, 0),
8418                    force_to_mode (XEXP (x, 0), GET_MODE (x),
8419                                   INTVAL (temp), next_select));
8420         }
8421       break;
8422
8423     case NEG:
8424       /* If we just want the low-order bit, the NEG isn't needed since it
8425          won't change the low-order bit.  */
8426       if (mask == 1)
8427         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8428
8429       /* We need any bits less significant than the most significant bit in
8430          MASK since carries from those bits will affect the bits we are
8431          interested in.  */
8432       mask = fuller_mask;
8433       goto unop;
8434
8435     case NOT:
8436       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8437          same as the XOR case above.  Ensure that the constant we form is not
8438          wider than the mode of X.  */
8439
8440       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8441           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8442           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8443           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8444               < GET_MODE_PRECISION (GET_MODE (x)))
8445           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8446         {
8447           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8448                                GET_MODE (x));
8449           temp = simplify_gen_binary (XOR, GET_MODE (x),
8450                                       XEXP (XEXP (x, 0), 0), temp);
8451           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8452                                    temp, XEXP (XEXP (x, 0), 1));
8453
8454           return force_to_mode (x, mode, mask, next_select);
8455         }
8456
8457       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8458          use the full mask inside the NOT.  */
8459       mask = fuller_mask;
8460
8461     unop:
8462       op0 = gen_lowpart_or_truncate (op_mode,
8463                                      force_to_mode (XEXP (x, 0), mode, mask,
8464                                                     next_select));
8465       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8466         x = simplify_gen_unary (code, op_mode, op0, op_mode);
8467       break;
8468
8469     case NE:
8470       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8471          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8472          which is equal to STORE_FLAG_VALUE.  */
8473       if ((mask & ~STORE_FLAG_VALUE) == 0
8474           && XEXP (x, 1) == const0_rtx
8475           && GET_MODE (XEXP (x, 0)) == mode
8476           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8477           && (nonzero_bits (XEXP (x, 0), mode)
8478               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8479         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8480
8481       break;
8482
8483     case IF_THEN_ELSE:
8484       /* We have no way of knowing if the IF_THEN_ELSE can itself be
8485          written in a narrower mode.  We play it safe and do not do so.  */
8486
8487       SUBST (XEXP (x, 1),
8488              gen_lowpart_or_truncate (GET_MODE (x),
8489                                       force_to_mode (XEXP (x, 1), mode,
8490                                                      mask, next_select)));
8491       SUBST (XEXP (x, 2),
8492              gen_lowpart_or_truncate (GET_MODE (x),
8493                                       force_to_mode (XEXP (x, 2), mode,
8494                                                      mask, next_select)));
8495       break;
8496
8497     default:
8498       break;
8499     }
8500
8501   /* Ensure we return a value of the proper mode.  */
8502   return gen_lowpart_or_truncate (mode, x);
8503 }
8504 \f
8505 /* Return nonzero if X is an expression that has one of two values depending on
8506    whether some other value is zero or nonzero.  In that case, we return the
8507    value that is being tested, *PTRUE is set to the value if the rtx being
8508    returned has a nonzero value, and *PFALSE is set to the other alternative.
8509
8510    If we return zero, we set *PTRUE and *PFALSE to X.  */
8511
8512 static rtx
8513 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8514 {
8515   enum machine_mode mode = GET_MODE (x);
8516   enum rtx_code code = GET_CODE (x);
8517   rtx cond0, cond1, true0, true1, false0, false1;
8518   unsigned HOST_WIDE_INT nz;
8519
8520   /* If we are comparing a value against zero, we are done.  */
8521   if ((code == NE || code == EQ)
8522       && XEXP (x, 1) == const0_rtx)
8523     {
8524       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8525       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8526       return XEXP (x, 0);
8527     }
8528
8529   /* If this is a unary operation whose operand has one of two values, apply
8530      our opcode to compute those values.  */
8531   else if (UNARY_P (x)
8532            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8533     {
8534       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8535       *pfalse = simplify_gen_unary (code, mode, false0,
8536                                     GET_MODE (XEXP (x, 0)));
8537       return cond0;
8538     }
8539
8540   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8541      make can't possibly match and would suppress other optimizations.  */
8542   else if (code == COMPARE)
8543     ;
8544
8545   /* If this is a binary operation, see if either side has only one of two
8546      values.  If either one does or if both do and they are conditional on
8547      the same value, compute the new true and false values.  */
8548   else if (BINARY_P (x))
8549     {
8550       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8551       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8552
8553       if ((cond0 != 0 || cond1 != 0)
8554           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8555         {
8556           /* If if_then_else_cond returned zero, then true/false are the
8557              same rtl.  We must copy one of them to prevent invalid rtl
8558              sharing.  */
8559           if (cond0 == 0)
8560             true0 = copy_rtx (true0);
8561           else if (cond1 == 0)
8562             true1 = copy_rtx (true1);
8563
8564           if (COMPARISON_P (x))
8565             {
8566               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8567                                                 true0, true1);
8568               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8569                                                  false0, false1);
8570              }
8571           else
8572             {
8573               *ptrue = simplify_gen_binary (code, mode, true0, true1);
8574               *pfalse = simplify_gen_binary (code, mode, false0, false1);
8575             }
8576
8577           return cond0 ? cond0 : cond1;
8578         }
8579
8580       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8581          operands is zero when the other is nonzero, and vice-versa,
8582          and STORE_FLAG_VALUE is 1 or -1.  */
8583
8584       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8585           && (code == PLUS || code == IOR || code == XOR || code == MINUS
8586               || code == UMAX)
8587           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8588         {
8589           rtx op0 = XEXP (XEXP (x, 0), 1);
8590           rtx op1 = XEXP (XEXP (x, 1), 1);
8591
8592           cond0 = XEXP (XEXP (x, 0), 0);
8593           cond1 = XEXP (XEXP (x, 1), 0);
8594
8595           if (COMPARISON_P (cond0)
8596               && COMPARISON_P (cond1)
8597               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8598                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8599                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8600                   || ((swap_condition (GET_CODE (cond0))
8601                        == reversed_comparison_code (cond1, NULL))
8602                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8603                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8604               && ! side_effects_p (x))
8605             {
8606               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8607               *pfalse = simplify_gen_binary (MULT, mode,
8608                                              (code == MINUS
8609                                               ? simplify_gen_unary (NEG, mode,
8610                                                                     op1, mode)
8611                                               : op1),
8612                                               const_true_rtx);
8613               return cond0;
8614             }
8615         }
8616
8617       /* Similarly for MULT, AND and UMIN, except that for these the result
8618          is always zero.  */
8619       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8620           && (code == MULT || code == AND || code == UMIN)
8621           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8622         {
8623           cond0 = XEXP (XEXP (x, 0), 0);
8624           cond1 = XEXP (XEXP (x, 1), 0);
8625
8626           if (COMPARISON_P (cond0)
8627               && COMPARISON_P (cond1)
8628               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8629                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8630                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8631                   || ((swap_condition (GET_CODE (cond0))
8632                        == reversed_comparison_code (cond1, NULL))
8633                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8634                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8635               && ! side_effects_p (x))
8636             {
8637               *ptrue = *pfalse = const0_rtx;
8638               return cond0;
8639             }
8640         }
8641     }
8642
8643   else if (code == IF_THEN_ELSE)
8644     {
8645       /* If we have IF_THEN_ELSE already, extract the condition and
8646          canonicalize it if it is NE or EQ.  */
8647       cond0 = XEXP (x, 0);
8648       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8649       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8650         return XEXP (cond0, 0);
8651       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8652         {
8653           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8654           return XEXP (cond0, 0);
8655         }
8656       else
8657         return cond0;
8658     }
8659
8660   /* If X is a SUBREG, we can narrow both the true and false values
8661      if the inner expression, if there is a condition.  */
8662   else if (code == SUBREG
8663            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8664                                                &true0, &false0)))
8665     {
8666       true0 = simplify_gen_subreg (mode, true0,
8667                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8668       false0 = simplify_gen_subreg (mode, false0,
8669                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8670       if (true0 && false0)
8671         {
8672           *ptrue = true0;
8673           *pfalse = false0;
8674           return cond0;
8675         }
8676     }
8677
8678   /* If X is a constant, this isn't special and will cause confusions
8679      if we treat it as such.  Likewise if it is equivalent to a constant.  */
8680   else if (CONSTANT_P (x)
8681            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8682     ;
8683
8684   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8685      will be least confusing to the rest of the compiler.  */
8686   else if (mode == BImode)
8687     {
8688       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8689       return x;
8690     }
8691
8692   /* If X is known to be either 0 or -1, those are the true and
8693      false values when testing X.  */
8694   else if (x == constm1_rtx || x == const0_rtx
8695            || (mode != VOIDmode
8696                && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8697     {
8698       *ptrue = constm1_rtx, *pfalse = const0_rtx;
8699       return x;
8700     }
8701
8702   /* Likewise for 0 or a single bit.  */
8703   else if (HWI_COMPUTABLE_MODE_P (mode)
8704            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8705     {
8706       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8707       return x;
8708     }
8709
8710   /* Otherwise fail; show no condition with true and false values the same.  */
8711   *ptrue = *pfalse = x;
8712   return 0;
8713 }
8714 \f
8715 /* Return the value of expression X given the fact that condition COND
8716    is known to be true when applied to REG as its first operand and VAL
8717    as its second.  X is known to not be shared and so can be modified in
8718    place.
8719
8720    We only handle the simplest cases, and specifically those cases that
8721    arise with IF_THEN_ELSE expressions.  */
8722
8723 static rtx
8724 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8725 {
8726   enum rtx_code code = GET_CODE (x);
8727   rtx temp;
8728   const char *fmt;
8729   int i, j;
8730
8731   if (side_effects_p (x))
8732     return x;
8733
8734   /* If either operand of the condition is a floating point value,
8735      then we have to avoid collapsing an EQ comparison.  */
8736   if (cond == EQ
8737       && rtx_equal_p (x, reg)
8738       && ! FLOAT_MODE_P (GET_MODE (x))
8739       && ! FLOAT_MODE_P (GET_MODE (val)))
8740     return val;
8741
8742   if (cond == UNEQ && rtx_equal_p (x, reg))
8743     return val;
8744
8745   /* If X is (abs REG) and we know something about REG's relationship
8746      with zero, we may be able to simplify this.  */
8747
8748   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8749     switch (cond)
8750       {
8751       case GE:  case GT:  case EQ:
8752         return XEXP (x, 0);
8753       case LT:  case LE:
8754         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8755                                    XEXP (x, 0),
8756                                    GET_MODE (XEXP (x, 0)));
8757       default:
8758         break;
8759       }
8760
8761   /* The only other cases we handle are MIN, MAX, and comparisons if the
8762      operands are the same as REG and VAL.  */
8763
8764   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8765     {
8766       if (rtx_equal_p (XEXP (x, 0), val))
8767         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8768
8769       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8770         {
8771           if (COMPARISON_P (x))
8772             {
8773               if (comparison_dominates_p (cond, code))
8774                 return const_true_rtx;
8775
8776               code = reversed_comparison_code (x, NULL);
8777               if (code != UNKNOWN
8778                   && comparison_dominates_p (cond, code))
8779                 return const0_rtx;
8780               else
8781                 return x;
8782             }
8783           else if (code == SMAX || code == SMIN
8784                    || code == UMIN || code == UMAX)
8785             {
8786               int unsignedp = (code == UMIN || code == UMAX);
8787
8788               /* Do not reverse the condition when it is NE or EQ.
8789                  This is because we cannot conclude anything about
8790                  the value of 'SMAX (x, y)' when x is not equal to y,
8791                  but we can when x equals y.  */
8792               if ((code == SMAX || code == UMAX)
8793                   && ! (cond == EQ || cond == NE))
8794                 cond = reverse_condition (cond);
8795
8796               switch (cond)
8797                 {
8798                 case GE:   case GT:
8799                   return unsignedp ? x : XEXP (x, 1);
8800                 case LE:   case LT:
8801                   return unsignedp ? x : XEXP (x, 0);
8802                 case GEU:  case GTU:
8803                   return unsignedp ? XEXP (x, 1) : x;
8804                 case LEU:  case LTU:
8805                   return unsignedp ? XEXP (x, 0) : x;
8806                 default:
8807                   break;
8808                 }
8809             }
8810         }
8811     }
8812   else if (code == SUBREG)
8813     {
8814       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8815       rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8816
8817       if (SUBREG_REG (x) != r)
8818         {
8819           /* We must simplify subreg here, before we lose track of the
8820              original inner_mode.  */
8821           new_rtx = simplify_subreg (GET_MODE (x), r,
8822                                  inner_mode, SUBREG_BYTE (x));
8823           if (new_rtx)
8824             return new_rtx;
8825           else
8826             SUBST (SUBREG_REG (x), r);
8827         }
8828
8829       return x;
8830     }
8831   /* We don't have to handle SIGN_EXTEND here, because even in the
8832      case of replacing something with a modeless CONST_INT, a
8833      CONST_INT is already (supposed to be) a valid sign extension for
8834      its narrower mode, which implies it's already properly
8835      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
8836      story is different.  */
8837   else if (code == ZERO_EXTEND)
8838     {
8839       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8840       rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8841
8842       if (XEXP (x, 0) != r)
8843         {
8844           /* We must simplify the zero_extend here, before we lose
8845              track of the original inner_mode.  */
8846           new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8847                                           r, inner_mode);
8848           if (new_rtx)
8849             return new_rtx;
8850           else
8851             SUBST (XEXP (x, 0), r);
8852         }
8853
8854       return x;
8855     }
8856
8857   fmt = GET_RTX_FORMAT (code);
8858   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8859     {
8860       if (fmt[i] == 'e')
8861         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8862       else if (fmt[i] == 'E')
8863         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8864           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8865                                                 cond, reg, val));
8866     }
8867
8868   return x;
8869 }
8870 \f
8871 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8872    assignment as a field assignment.  */
8873
8874 static int
8875 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8876 {
8877   if (x == y || rtx_equal_p (x, y))
8878     return 1;
8879
8880   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8881     return 0;
8882
8883   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8884      Note that all SUBREGs of MEM are paradoxical; otherwise they
8885      would have been rewritten.  */
8886   if (MEM_P (x) && GET_CODE (y) == SUBREG
8887       && MEM_P (SUBREG_REG (y))
8888       && rtx_equal_p (SUBREG_REG (y),
8889                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8890     return 1;
8891
8892   if (MEM_P (y) && GET_CODE (x) == SUBREG
8893       && MEM_P (SUBREG_REG (x))
8894       && rtx_equal_p (SUBREG_REG (x),
8895                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8896     return 1;
8897
8898   /* We used to see if get_last_value of X and Y were the same but that's
8899      not correct.  In one direction, we'll cause the assignment to have
8900      the wrong destination and in the case, we'll import a register into this
8901      insn that might have already have been dead.   So fail if none of the
8902      above cases are true.  */
8903   return 0;
8904 }
8905 \f
8906 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8907    Return that assignment if so.
8908
8909    We only handle the most common cases.  */
8910
8911 static rtx
8912 make_field_assignment (rtx x)
8913 {
8914   rtx dest = SET_DEST (x);
8915   rtx src = SET_SRC (x);
8916   rtx assign;
8917   rtx rhs, lhs;
8918   HOST_WIDE_INT c1;
8919   HOST_WIDE_INT pos;
8920   unsigned HOST_WIDE_INT len;
8921   rtx other;
8922   enum machine_mode mode;
8923
8924   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8925      a clear of a one-bit field.  We will have changed it to
8926      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
8927      for a SUBREG.  */
8928
8929   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8930       && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8931       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8932       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8933     {
8934       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8935                                 1, 1, 1, 0);
8936       if (assign != 0)
8937         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8938       return x;
8939     }
8940
8941   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8942       && subreg_lowpart_p (XEXP (src, 0))
8943       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8944           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8945       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8946       && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8947       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8948       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8949     {
8950       assign = make_extraction (VOIDmode, dest, 0,
8951                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8952                                 1, 1, 1, 0);
8953       if (assign != 0)
8954         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8955       return x;
8956     }
8957
8958   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8959      one-bit field.  */
8960   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8961       && XEXP (XEXP (src, 0), 0) == const1_rtx
8962       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8963     {
8964       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8965                                 1, 1, 1, 0);
8966       if (assign != 0)
8967         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8968       return x;
8969     }
8970
8971   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8972      SRC is an AND with all bits of that field set, then we can discard
8973      the AND.  */
8974   if (GET_CODE (dest) == ZERO_EXTRACT
8975       && CONST_INT_P (XEXP (dest, 1))
8976       && GET_CODE (src) == AND
8977       && CONST_INT_P (XEXP (src, 1)))
8978     {
8979       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8980       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8981       unsigned HOST_WIDE_INT ze_mask;
8982
8983       if (width >= HOST_BITS_PER_WIDE_INT)
8984         ze_mask = -1;
8985       else
8986         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8987
8988       /* Complete overlap.  We can remove the source AND.  */
8989       if ((and_mask & ze_mask) == ze_mask)
8990         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8991
8992       /* Partial overlap.  We can reduce the source AND.  */
8993       if ((and_mask & ze_mask) != and_mask)
8994         {
8995           mode = GET_MODE (src);
8996           src = gen_rtx_AND (mode, XEXP (src, 0),
8997                              gen_int_mode (and_mask & ze_mask, mode));
8998           return gen_rtx_SET (VOIDmode, dest, src);
8999         }
9000     }
9001
9002   /* The other case we handle is assignments into a constant-position
9003      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
9004      a mask that has all one bits except for a group of zero bits and
9005      OTHER is known to have zeros where C1 has ones, this is such an
9006      assignment.  Compute the position and length from C1.  Shift OTHER
9007      to the appropriate position, force it to the required mode, and
9008      make the extraction.  Check for the AND in both operands.  */
9009
9010   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9011     return x;
9012
9013   rhs = expand_compound_operation (XEXP (src, 0));
9014   lhs = expand_compound_operation (XEXP (src, 1));
9015
9016   if (GET_CODE (rhs) == AND
9017       && CONST_INT_P (XEXP (rhs, 1))
9018       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9019     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9020   else if (GET_CODE (lhs) == AND
9021            && CONST_INT_P (XEXP (lhs, 1))
9022            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9023     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9024   else
9025     return x;
9026
9027   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9028   if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9029       || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9030       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9031     return x;
9032
9033   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9034   if (assign == 0)
9035     return x;
9036
9037   /* The mode to use for the source is the mode of the assignment, or of
9038      what is inside a possible STRICT_LOW_PART.  */
9039   mode = (GET_CODE (assign) == STRICT_LOW_PART
9040           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9041
9042   /* Shift OTHER right POS places and make it the source, restricting it
9043      to the proper length and mode.  */
9044
9045   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9046                                                      GET_MODE (src),
9047                                                      other, pos),
9048                                dest);
9049   src = force_to_mode (src, mode,
9050                        GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9051                        ? ~(unsigned HOST_WIDE_INT) 0
9052                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9053                        0);
9054
9055   /* If SRC is masked by an AND that does not make a difference in
9056      the value being stored, strip it.  */
9057   if (GET_CODE (assign) == ZERO_EXTRACT
9058       && CONST_INT_P (XEXP (assign, 1))
9059       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9060       && GET_CODE (src) == AND
9061       && CONST_INT_P (XEXP (src, 1))
9062       && UINTVAL (XEXP (src, 1))
9063          == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9064     src = XEXP (src, 0);
9065
9066   return gen_rtx_SET (VOIDmode, assign, src);
9067 }
9068 \f
9069 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9070    if so.  */
9071
9072 static rtx
9073 apply_distributive_law (rtx x)
9074 {
9075   enum rtx_code code = GET_CODE (x);
9076   enum rtx_code inner_code;
9077   rtx lhs, rhs, other;
9078   rtx tem;
9079
9080   /* Distributivity is not true for floating point as it can change the
9081      value.  So we don't do it unless -funsafe-math-optimizations.  */
9082   if (FLOAT_MODE_P (GET_MODE (x))
9083       && ! flag_unsafe_math_optimizations)
9084     return x;
9085
9086   /* The outer operation can only be one of the following:  */
9087   if (code != IOR && code != AND && code != XOR
9088       && code != PLUS && code != MINUS)
9089     return x;
9090
9091   lhs = XEXP (x, 0);
9092   rhs = XEXP (x, 1);
9093
9094   /* If either operand is a primitive we can't do anything, so get out
9095      fast.  */
9096   if (OBJECT_P (lhs) || OBJECT_P (rhs))
9097     return x;
9098
9099   lhs = expand_compound_operation (lhs);
9100   rhs = expand_compound_operation (rhs);
9101   inner_code = GET_CODE (lhs);
9102   if (inner_code != GET_CODE (rhs))
9103     return x;
9104
9105   /* See if the inner and outer operations distribute.  */
9106   switch (inner_code)
9107     {
9108     case LSHIFTRT:
9109     case ASHIFTRT:
9110     case AND:
9111     case IOR:
9112       /* These all distribute except over PLUS.  */
9113       if (code == PLUS || code == MINUS)
9114         return x;
9115       break;
9116
9117     case MULT:
9118       if (code != PLUS && code != MINUS)
9119         return x;
9120       break;
9121
9122     case ASHIFT:
9123       /* This is also a multiply, so it distributes over everything.  */
9124       break;
9125
9126     /* This used to handle SUBREG, but this turned out to be counter-
9127        productive, since (subreg (op ...)) usually is not handled by
9128        insn patterns, and this "optimization" therefore transformed
9129        recognizable patterns into unrecognizable ones.  Therefore the
9130        SUBREG case was removed from here.
9131
9132        It is possible that distributing SUBREG over arithmetic operations
9133        leads to an intermediate result than can then be optimized further,
9134        e.g. by moving the outer SUBREG to the other side of a SET as done
9135        in simplify_set.  This seems to have been the original intent of
9136        handling SUBREGs here.
9137
9138        However, with current GCC this does not appear to actually happen,
9139        at least on major platforms.  If some case is found where removing
9140        the SUBREG case here prevents follow-on optimizations, distributing
9141        SUBREGs ought to be re-added at that place, e.g. in simplify_set.  */
9142
9143     default:
9144       return x;
9145     }
9146
9147   /* Set LHS and RHS to the inner operands (A and B in the example
9148      above) and set OTHER to the common operand (C in the example).
9149      There is only one way to do this unless the inner operation is
9150      commutative.  */
9151   if (COMMUTATIVE_ARITH_P (lhs)
9152       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9153     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9154   else if (COMMUTATIVE_ARITH_P (lhs)
9155            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9156     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9157   else if (COMMUTATIVE_ARITH_P (lhs)
9158            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9159     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9160   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9161     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9162   else
9163     return x;
9164
9165   /* Form the new inner operation, seeing if it simplifies first.  */
9166   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9167
9168   /* There is one exception to the general way of distributing:
9169      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
9170   if (code == XOR && inner_code == IOR)
9171     {
9172       inner_code = AND;
9173       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9174     }
9175
9176   /* We may be able to continuing distributing the result, so call
9177      ourselves recursively on the inner operation before forming the
9178      outer operation, which we return.  */
9179   return simplify_gen_binary (inner_code, GET_MODE (x),
9180                               apply_distributive_law (tem), other);
9181 }
9182
9183 /* See if X is of the form (* (+ A B) C), and if so convert to
9184    (+ (* A C) (* B C)) and try to simplify.
9185
9186    Most of the time, this results in no change.  However, if some of
9187    the operands are the same or inverses of each other, simplifications
9188    will result.
9189
9190    For example, (and (ior A B) (not B)) can occur as the result of
9191    expanding a bit field assignment.  When we apply the distributive
9192    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9193    which then simplifies to (and (A (not B))).
9194
9195    Note that no checks happen on the validity of applying the inverse
9196    distributive law.  This is pointless since we can do it in the
9197    few places where this routine is called.
9198
9199    N is the index of the term that is decomposed (the arithmetic operation,
9200    i.e. (+ A B) in the first example above).  !N is the index of the term that
9201    is distributed, i.e. of C in the first example above.  */
9202 static rtx
9203 distribute_and_simplify_rtx (rtx x, int n)
9204 {
9205   enum machine_mode mode;
9206   enum rtx_code outer_code, inner_code;
9207   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9208
9209   /* Distributivity is not true for floating point as it can change the
9210      value.  So we don't do it unless -funsafe-math-optimizations.  */
9211   if (FLOAT_MODE_P (GET_MODE (x))
9212       && ! flag_unsafe_math_optimizations)
9213     return NULL_RTX;
9214
9215   decomposed = XEXP (x, n);
9216   if (!ARITHMETIC_P (decomposed))
9217     return NULL_RTX;
9218
9219   mode = GET_MODE (x);
9220   outer_code = GET_CODE (x);
9221   distributed = XEXP (x, !n);
9222
9223   inner_code = GET_CODE (decomposed);
9224   inner_op0 = XEXP (decomposed, 0);
9225   inner_op1 = XEXP (decomposed, 1);
9226
9227   /* Special case (and (xor B C) (not A)), which is equivalent to
9228      (xor (ior A B) (ior A C))  */
9229   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9230     {
9231       distributed = XEXP (distributed, 0);
9232       outer_code = IOR;
9233     }
9234
9235   if (n == 0)
9236     {
9237       /* Distribute the second term.  */
9238       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9239       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9240     }
9241   else
9242     {
9243       /* Distribute the first term.  */
9244       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9245       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9246     }
9247
9248   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9249                                                      new_op0, new_op1));
9250   if (GET_CODE (tmp) != outer_code
9251       && (set_src_cost (tmp, optimize_this_for_speed_p)
9252           < set_src_cost (x, optimize_this_for_speed_p)))
9253     return tmp;
9254
9255   return NULL_RTX;
9256 }
9257 \f
9258 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9259    in MODE.  Return an equivalent form, if different from (and VAROP
9260    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
9261
9262 static rtx
9263 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9264                           unsigned HOST_WIDE_INT constop)
9265 {
9266   unsigned HOST_WIDE_INT nonzero;
9267   unsigned HOST_WIDE_INT orig_constop;
9268   rtx orig_varop;
9269   int i;
9270
9271   orig_varop = varop;
9272   orig_constop = constop;
9273   if (GET_CODE (varop) == CLOBBER)
9274     return NULL_RTX;
9275
9276   /* Simplify VAROP knowing that we will be only looking at some of the
9277      bits in it.
9278
9279      Note by passing in CONSTOP, we guarantee that the bits not set in
9280      CONSTOP are not significant and will never be examined.  We must
9281      ensure that is the case by explicitly masking out those bits
9282      before returning.  */
9283   varop = force_to_mode (varop, mode, constop, 0);
9284
9285   /* If VAROP is a CLOBBER, we will fail so return it.  */
9286   if (GET_CODE (varop) == CLOBBER)
9287     return varop;
9288
9289   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9290      to VAROP and return the new constant.  */
9291   if (CONST_INT_P (varop))
9292     return gen_int_mode (INTVAL (varop) & constop, mode);
9293
9294   /* See what bits may be nonzero in VAROP.  Unlike the general case of
9295      a call to nonzero_bits, here we don't care about bits outside
9296      MODE.  */
9297
9298   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9299
9300   /* Turn off all bits in the constant that are known to already be zero.
9301      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9302      which is tested below.  */
9303
9304   constop &= nonzero;
9305
9306   /* If we don't have any bits left, return zero.  */
9307   if (constop == 0)
9308     return const0_rtx;
9309
9310   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9311      a power of two, we can replace this with an ASHIFT.  */
9312   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9313       && (i = exact_log2 (constop)) >= 0)
9314     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9315
9316   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9317      or XOR, then try to apply the distributive law.  This may eliminate
9318      operations if either branch can be simplified because of the AND.
9319      It may also make some cases more complex, but those cases probably
9320      won't match a pattern either with or without this.  */
9321
9322   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9323     return
9324       gen_lowpart
9325         (mode,
9326          apply_distributive_law
9327          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9328                                simplify_and_const_int (NULL_RTX,
9329                                                        GET_MODE (varop),
9330                                                        XEXP (varop, 0),
9331                                                        constop),
9332                                simplify_and_const_int (NULL_RTX,
9333                                                        GET_MODE (varop),
9334                                                        XEXP (varop, 1),
9335                                                        constop))));
9336
9337   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9338      the AND and see if one of the operands simplifies to zero.  If so, we
9339      may eliminate it.  */
9340
9341   if (GET_CODE (varop) == PLUS
9342       && exact_log2 (constop + 1) >= 0)
9343     {
9344       rtx o0, o1;
9345
9346       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9347       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9348       if (o0 == const0_rtx)
9349         return o1;
9350       if (o1 == const0_rtx)
9351         return o0;
9352     }
9353
9354   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9355   varop = gen_lowpart (mode, varop);
9356   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9357     return NULL_RTX;
9358
9359   /* If we are only masking insignificant bits, return VAROP.  */
9360   if (constop == nonzero)
9361     return varop;
9362
9363   if (varop == orig_varop && constop == orig_constop)
9364     return NULL_RTX;
9365
9366   /* Otherwise, return an AND.  */
9367   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9368 }
9369
9370
9371 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9372    in MODE.
9373
9374    Return an equivalent form, if different from X.  Otherwise, return X.  If
9375    X is zero, we are to always construct the equivalent form.  */
9376
9377 static rtx
9378 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9379                         unsigned HOST_WIDE_INT constop)
9380 {
9381   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9382   if (tem)
9383     return tem;
9384
9385   if (!x)
9386     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9387                              gen_int_mode (constop, mode));
9388   if (GET_MODE (x) != mode)
9389     x = gen_lowpart (mode, x);
9390   return x;
9391 }
9392 \f
9393 /* Given a REG, X, compute which bits in X can be nonzero.
9394    We don't care about bits outside of those defined in MODE.
9395
9396    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9397    a shift, AND, or zero_extract, we can do better.  */
9398
9399 static rtx
9400 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9401                               const_rtx known_x ATTRIBUTE_UNUSED,
9402                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
9403                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9404                               unsigned HOST_WIDE_INT *nonzero)
9405 {
9406   rtx tem;
9407   reg_stat_type *rsp;
9408
9409   /* If X is a register whose nonzero bits value is current, use it.
9410      Otherwise, if X is a register whose value we can find, use that
9411      value.  Otherwise, use the previously-computed global nonzero bits
9412      for this register.  */
9413
9414   rsp = &VEC_index (reg_stat_type, reg_stat, REGNO (x));
9415   if (rsp->last_set_value != 0
9416       && (rsp->last_set_mode == mode
9417           || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9418               && GET_MODE_CLASS (mode) == MODE_INT))
9419       && ((rsp->last_set_label >= label_tick_ebb_start
9420            && rsp->last_set_label < label_tick)
9421           || (rsp->last_set_label == label_tick
9422               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9423           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9424               && REG_N_SETS (REGNO (x)) == 1
9425               && !REGNO_REG_SET_P
9426                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9427     {
9428       *nonzero &= rsp->last_set_nonzero_bits;
9429       return NULL;
9430     }
9431
9432   tem = get_last_value (x);
9433
9434   if (tem)
9435     {
9436 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9437       /* If X is narrower than MODE and TEM is a non-negative
9438          constant that would appear negative in the mode of X,
9439          sign-extend it for use in reg_nonzero_bits because some
9440          machines (maybe most) will actually do the sign-extension
9441          and this is the conservative approach.
9442
9443          ??? For 2.5, try to tighten up the MD files in this regard
9444          instead of this kludge.  */
9445
9446       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9447           && CONST_INT_P (tem)
9448           && INTVAL (tem) > 0
9449           && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9450         tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9451 #endif
9452       return tem;
9453     }
9454   else if (nonzero_sign_valid && rsp->nonzero_bits)
9455     {
9456       unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9457
9458       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9459         /* We don't know anything about the upper bits.  */
9460         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9461       *nonzero &= mask;
9462     }
9463
9464   return NULL;
9465 }
9466
9467 /* Return the number of bits at the high-order end of X that are known to
9468    be equal to the sign bit.  X will be used in mode MODE; if MODE is
9469    VOIDmode, X will be used in its own mode.  The returned value  will always
9470    be between 1 and the number of bits in MODE.  */
9471
9472 static rtx
9473 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9474                                      const_rtx known_x ATTRIBUTE_UNUSED,
9475                                      enum machine_mode known_mode
9476                                      ATTRIBUTE_UNUSED,
9477                                      unsigned int known_ret ATTRIBUTE_UNUSED,
9478                                      unsigned int *result)
9479 {
9480   rtx tem;
9481   reg_stat_type *rsp;
9482
9483   rsp = &VEC_index (reg_stat_type, reg_stat, REGNO (x));
9484   if (rsp->last_set_value != 0
9485       && rsp->last_set_mode == mode
9486       && ((rsp->last_set_label >= label_tick_ebb_start
9487            && rsp->last_set_label < label_tick)
9488           || (rsp->last_set_label == label_tick
9489               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9490           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9491               && REG_N_SETS (REGNO (x)) == 1
9492               && !REGNO_REG_SET_P
9493                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9494     {
9495       *result = rsp->last_set_sign_bit_copies;
9496       return NULL;
9497     }
9498
9499   tem = get_last_value (x);
9500   if (tem != 0)
9501     return tem;
9502
9503   if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9504       && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9505     *result = rsp->sign_bit_copies;
9506
9507   return NULL;
9508 }
9509 \f
9510 /* Return the number of "extended" bits there are in X, when interpreted
9511    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
9512    unsigned quantities, this is the number of high-order zero bits.
9513    For signed quantities, this is the number of copies of the sign bit
9514    minus 1.  In both case, this function returns the number of "spare"
9515    bits.  For example, if two quantities for which this function returns
9516    at least 1 are added, the addition is known not to overflow.
9517
9518    This function will always return 0 unless called during combine, which
9519    implies that it must be called from a define_split.  */
9520
9521 unsigned int
9522 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9523 {
9524   if (nonzero_sign_valid == 0)
9525     return 0;
9526
9527   return (unsignedp
9528           ? (HWI_COMPUTABLE_MODE_P (mode)
9529              ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9530                                - floor_log2 (nonzero_bits (x, mode)))
9531              : 0)
9532           : num_sign_bit_copies (x, mode) - 1);
9533 }
9534
9535 /* This function is called from `simplify_shift_const' to merge two
9536    outer operations.  Specifically, we have already found that we need
9537    to perform operation *POP0 with constant *PCONST0 at the outermost
9538    position.  We would now like to also perform OP1 with constant CONST1
9539    (with *POP0 being done last).
9540
9541    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9542    the resulting operation.  *PCOMP_P is set to 1 if we would need to
9543    complement the innermost operand, otherwise it is unchanged.
9544
9545    MODE is the mode in which the operation will be done.  No bits outside
9546    the width of this mode matter.  It is assumed that the width of this mode
9547    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9548
9549    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
9550    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
9551    result is simply *PCONST0.
9552
9553    If the resulting operation cannot be expressed as one operation, we
9554    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
9555
9556 static int
9557 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9558 {
9559   enum rtx_code op0 = *pop0;
9560   HOST_WIDE_INT const0 = *pconst0;
9561
9562   const0 &= GET_MODE_MASK (mode);
9563   const1 &= GET_MODE_MASK (mode);
9564
9565   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
9566   if (op0 == AND)
9567     const1 &= const0;
9568
9569   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
9570      if OP0 is SET.  */
9571
9572   if (op1 == UNKNOWN || op0 == SET)
9573     return 1;
9574
9575   else if (op0 == UNKNOWN)
9576     op0 = op1, const0 = const1;
9577
9578   else if (op0 == op1)
9579     {
9580       switch (op0)
9581         {
9582         case AND:
9583           const0 &= const1;
9584           break;
9585         case IOR:
9586           const0 |= const1;
9587           break;
9588         case XOR:
9589           const0 ^= const1;
9590           break;
9591         case PLUS:
9592           const0 += const1;
9593           break;
9594         case NEG:
9595           op0 = UNKNOWN;
9596           break;
9597         default:
9598           break;
9599         }
9600     }
9601
9602   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
9603   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9604     return 0;
9605
9606   /* If the two constants aren't the same, we can't do anything.  The
9607      remaining six cases can all be done.  */
9608   else if (const0 != const1)
9609     return 0;
9610
9611   else
9612     switch (op0)
9613       {
9614       case IOR:
9615         if (op1 == AND)
9616           /* (a & b) | b == b */
9617           op0 = SET;
9618         else /* op1 == XOR */
9619           /* (a ^ b) | b == a | b */
9620           {;}
9621         break;
9622
9623       case XOR:
9624         if (op1 == AND)
9625           /* (a & b) ^ b == (~a) & b */
9626           op0 = AND, *pcomp_p = 1;
9627         else /* op1 == IOR */
9628           /* (a | b) ^ b == a & ~b */
9629           op0 = AND, const0 = ~const0;
9630         break;
9631
9632       case AND:
9633         if (op1 == IOR)
9634           /* (a | b) & b == b */
9635         op0 = SET;
9636         else /* op1 == XOR */
9637           /* (a ^ b) & b) == (~a) & b */
9638           *pcomp_p = 1;
9639         break;
9640       default:
9641         break;
9642       }
9643
9644   /* Check for NO-OP cases.  */
9645   const0 &= GET_MODE_MASK (mode);
9646   if (const0 == 0
9647       && (op0 == IOR || op0 == XOR || op0 == PLUS))
9648     op0 = UNKNOWN;
9649   else if (const0 == 0 && op0 == AND)
9650     op0 = SET;
9651   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9652            && op0 == AND)
9653     op0 = UNKNOWN;
9654
9655   *pop0 = op0;
9656
9657   /* ??? Slightly redundant with the above mask, but not entirely.
9658      Moving this above means we'd have to sign-extend the mode mask
9659      for the final test.  */
9660   if (op0 != UNKNOWN && op0 != NEG)
9661     *pconst0 = trunc_int_for_mode (const0, mode);
9662
9663   return 1;
9664 }
9665 \f
9666 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9667    the shift in.  The original shift operation CODE is performed on OP in
9668    ORIG_MODE.  Return the wider mode MODE if we can perform the operation
9669    in that mode.  Return ORIG_MODE otherwise.  We can also assume that the
9670    result of the shift is subject to operation OUTER_CODE with operand
9671    OUTER_CONST.  */
9672
9673 static enum machine_mode
9674 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9675                       enum machine_mode orig_mode, enum machine_mode mode,
9676                       enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9677 {
9678   if (orig_mode == mode)
9679     return mode;
9680   gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9681
9682   /* In general we can't perform in wider mode for right shift and rotate.  */
9683   switch (code)
9684     {
9685     case ASHIFTRT:
9686       /* We can still widen if the bits brought in from the left are identical
9687          to the sign bit of ORIG_MODE.  */
9688       if (num_sign_bit_copies (op, mode)
9689           > (unsigned) (GET_MODE_PRECISION (mode)
9690                         - GET_MODE_PRECISION (orig_mode)))
9691         return mode;
9692       return orig_mode;
9693
9694     case LSHIFTRT:
9695       /* Similarly here but with zero bits.  */
9696       if (HWI_COMPUTABLE_MODE_P (mode)
9697           && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9698         return mode;
9699
9700       /* We can also widen if the bits brought in will be masked off.  This
9701          operation is performed in ORIG_MODE.  */
9702       if (outer_code == AND)
9703         {
9704           int care_bits = low_bitmask_len (orig_mode, outer_const);
9705
9706           if (care_bits >= 0
9707               && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9708             return mode;
9709         }
9710       /* fall through */
9711
9712     case ROTATE:
9713       return orig_mode;
9714
9715     case ROTATERT:
9716       gcc_unreachable ();
9717
9718     default:
9719       return mode;
9720     }
9721 }
9722
9723 /* Simplify a shift of VAROP by ORIG_COUNT bits.  CODE says what kind
9724    of shift.  The result of the shift is RESULT_MODE.  Return NULL_RTX
9725    if we cannot simplify it.  Otherwise, return a simplified value.
9726
9727    The shift is normally computed in the widest mode we find in VAROP, as
9728    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9729    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9730
9731 static rtx
9732 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9733                         rtx varop, int orig_count)
9734 {
9735   enum rtx_code orig_code = code;
9736   rtx orig_varop = varop;
9737   int count;
9738   enum machine_mode mode = result_mode;
9739   enum machine_mode shift_mode, tmode;
9740   unsigned int mode_words
9741     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9742   /* We form (outer_op (code varop count) (outer_const)).  */
9743   enum rtx_code outer_op = UNKNOWN;
9744   HOST_WIDE_INT outer_const = 0;
9745   int complement_p = 0;
9746   rtx new_rtx, x;
9747
9748   /* Make sure and truncate the "natural" shift on the way in.  We don't
9749      want to do this inside the loop as it makes it more difficult to
9750      combine shifts.  */
9751   if (SHIFT_COUNT_TRUNCATED)
9752     orig_count &= GET_MODE_BITSIZE (mode) - 1;
9753
9754   /* If we were given an invalid count, don't do anything except exactly
9755      what was requested.  */
9756
9757   if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9758     return NULL_RTX;
9759
9760   count = orig_count;
9761
9762   /* Unless one of the branches of the `if' in this loop does a `continue',
9763      we will `break' the loop after the `if'.  */
9764
9765   while (count != 0)
9766     {
9767       /* If we have an operand of (clobber (const_int 0)), fail.  */
9768       if (GET_CODE (varop) == CLOBBER)
9769         return NULL_RTX;
9770
9771       /* Convert ROTATERT to ROTATE.  */
9772       if (code == ROTATERT)
9773         {
9774           unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9775           code = ROTATE;
9776           if (VECTOR_MODE_P (result_mode))
9777             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9778           else
9779             count = bitsize - count;
9780         }
9781
9782       shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9783                                          mode, outer_op, outer_const);
9784
9785       /* Handle cases where the count is greater than the size of the mode
9786          minus 1.  For ASHIFT, use the size minus one as the count (this can
9787          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
9788          take the count modulo the size.  For other shifts, the result is
9789          zero.
9790
9791          Since these shifts are being produced by the compiler by combining
9792          multiple operations, each of which are defined, we know what the
9793          result is supposed to be.  */
9794
9795       if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9796         {
9797           if (code == ASHIFTRT)
9798             count = GET_MODE_PRECISION (shift_mode) - 1;
9799           else if (code == ROTATE || code == ROTATERT)
9800             count %= GET_MODE_PRECISION (shift_mode);
9801           else
9802             {
9803               /* We can't simply return zero because there may be an
9804                  outer op.  */
9805               varop = const0_rtx;
9806               count = 0;
9807               break;
9808             }
9809         }
9810
9811       /* If we discovered we had to complement VAROP, leave.  Making a NOT
9812          here would cause an infinite loop.  */
9813       if (complement_p)
9814         break;
9815
9816       /* An arithmetic right shift of a quantity known to be -1 or 0
9817          is a no-op.  */
9818       if (code == ASHIFTRT
9819           && (num_sign_bit_copies (varop, shift_mode)
9820               == GET_MODE_PRECISION (shift_mode)))
9821         {
9822           count = 0;
9823           break;
9824         }
9825
9826       /* If we are doing an arithmetic right shift and discarding all but
9827          the sign bit copies, this is equivalent to doing a shift by the
9828          bitsize minus one.  Convert it into that shift because it will often
9829          allow other simplifications.  */
9830
9831       if (code == ASHIFTRT
9832           && (count + num_sign_bit_copies (varop, shift_mode)
9833               >= GET_MODE_PRECISION (shift_mode)))
9834         count = GET_MODE_PRECISION (shift_mode) - 1;
9835
9836       /* We simplify the tests below and elsewhere by converting
9837          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9838          `make_compound_operation' will convert it to an ASHIFTRT for
9839          those machines (such as VAX) that don't have an LSHIFTRT.  */
9840       if (code == ASHIFTRT
9841           && val_signbit_known_clear_p (shift_mode,
9842                                         nonzero_bits (varop, shift_mode)))
9843         code = LSHIFTRT;
9844
9845       if (((code == LSHIFTRT
9846             && HWI_COMPUTABLE_MODE_P (shift_mode)
9847             && !(nonzero_bits (varop, shift_mode) >> count))
9848            || (code == ASHIFT
9849                && HWI_COMPUTABLE_MODE_P (shift_mode)
9850                && !((nonzero_bits (varop, shift_mode) << count)
9851                     & GET_MODE_MASK (shift_mode))))
9852           && !side_effects_p (varop))
9853         varop = const0_rtx;
9854
9855       switch (GET_CODE (varop))
9856         {
9857         case SIGN_EXTEND:
9858         case ZERO_EXTEND:
9859         case SIGN_EXTRACT:
9860         case ZERO_EXTRACT:
9861           new_rtx = expand_compound_operation (varop);
9862           if (new_rtx != varop)
9863             {
9864               varop = new_rtx;
9865               continue;
9866             }
9867           break;
9868
9869         case MEM:
9870           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9871              minus the width of a smaller mode, we can do this with a
9872              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
9873           if ((code == ASHIFTRT || code == LSHIFTRT)
9874               && ! mode_dependent_address_p (XEXP (varop, 0),
9875                                              MEM_ADDR_SPACE (varop))
9876               && ! MEM_VOLATILE_P (varop)
9877               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9878                                          MODE_INT, 1)) != BLKmode)
9879             {
9880               new_rtx = adjust_address_nv (varop, tmode,
9881                                        BYTES_BIG_ENDIAN ? 0
9882                                        : count / BITS_PER_UNIT);
9883
9884               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9885                                      : ZERO_EXTEND, mode, new_rtx);
9886               count = 0;
9887               continue;
9888             }
9889           break;
9890
9891         case SUBREG:
9892           /* If VAROP is a SUBREG, strip it as long as the inner operand has
9893              the same number of words as what we've seen so far.  Then store
9894              the widest mode in MODE.  */
9895           if (subreg_lowpart_p (varop)
9896               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9897                   > GET_MODE_SIZE (GET_MODE (varop)))
9898               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9899                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9900                  == mode_words
9901               && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9902               && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9903             {
9904               varop = SUBREG_REG (varop);
9905               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9906                 mode = GET_MODE (varop);
9907               continue;
9908             }
9909           break;
9910
9911         case MULT:
9912           /* Some machines use MULT instead of ASHIFT because MULT
9913              is cheaper.  But it is still better on those machines to
9914              merge two shifts into one.  */
9915           if (CONST_INT_P (XEXP (varop, 1))
9916               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9917             {
9918               varop
9919                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9920                                        XEXP (varop, 0),
9921                                        GEN_INT (exact_log2 (
9922                                                 UINTVAL (XEXP (varop, 1)))));
9923               continue;
9924             }
9925           break;
9926
9927         case UDIV:
9928           /* Similar, for when divides are cheaper.  */
9929           if (CONST_INT_P (XEXP (varop, 1))
9930               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9931             {
9932               varop
9933                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9934                                        XEXP (varop, 0),
9935                                        GEN_INT (exact_log2 (
9936                                                 UINTVAL (XEXP (varop, 1)))));
9937               continue;
9938             }
9939           break;
9940
9941         case ASHIFTRT:
9942           /* If we are extracting just the sign bit of an arithmetic
9943              right shift, that shift is not needed.  However, the sign
9944              bit of a wider mode may be different from what would be
9945              interpreted as the sign bit in a narrower mode, so, if
9946              the result is narrower, don't discard the shift.  */
9947           if (code == LSHIFTRT
9948               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9949               && (GET_MODE_BITSIZE (result_mode)
9950                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
9951             {
9952               varop = XEXP (varop, 0);
9953               continue;
9954             }
9955
9956           /* ... fall through ...  */
9957
9958         case LSHIFTRT:
9959         case ASHIFT:
9960         case ROTATE:
9961           /* Here we have two nested shifts.  The result is usually the
9962              AND of a new shift with a mask.  We compute the result below.  */
9963           if (CONST_INT_P (XEXP (varop, 1))
9964               && INTVAL (XEXP (varop, 1)) >= 0
9965               && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
9966               && HWI_COMPUTABLE_MODE_P (result_mode)
9967               && HWI_COMPUTABLE_MODE_P (mode)
9968               && !VECTOR_MODE_P (result_mode))
9969             {
9970               enum rtx_code first_code = GET_CODE (varop);
9971               unsigned int first_count = INTVAL (XEXP (varop, 1));
9972               unsigned HOST_WIDE_INT mask;
9973               rtx mask_rtx;
9974
9975               /* We have one common special case.  We can't do any merging if
9976                  the inner code is an ASHIFTRT of a smaller mode.  However, if
9977                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9978                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9979                  we can convert it to
9980                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
9981                  This simplifies certain SIGN_EXTEND operations.  */
9982               if (code == ASHIFT && first_code == ASHIFTRT
9983                   && count == (GET_MODE_PRECISION (result_mode)
9984                                - GET_MODE_PRECISION (GET_MODE (varop))))
9985                 {
9986                   /* C3 has the low-order C1 bits zero.  */
9987
9988                   mask = GET_MODE_MASK (mode)
9989                          & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
9990
9991                   varop = simplify_and_const_int (NULL_RTX, result_mode,
9992                                                   XEXP (varop, 0), mask);
9993                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9994                                                 varop, count);
9995                   count = first_count;
9996                   code = ASHIFTRT;
9997                   continue;
9998                 }
9999
10000               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10001                  than C1 high-order bits equal to the sign bit, we can convert
10002                  this to either an ASHIFT or an ASHIFTRT depending on the
10003                  two counts.
10004
10005                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
10006
10007               if (code == ASHIFTRT && first_code == ASHIFT
10008                   && GET_MODE (varop) == shift_mode
10009                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10010                       > first_count))
10011                 {
10012                   varop = XEXP (varop, 0);
10013                   count -= first_count;
10014                   if (count < 0)
10015                     {
10016                       count = -count;
10017                       code = ASHIFT;
10018                     }
10019
10020                   continue;
10021                 }
10022
10023               /* There are some cases we can't do.  If CODE is ASHIFTRT,
10024                  we can only do this if FIRST_CODE is also ASHIFTRT.
10025
10026                  We can't do the case when CODE is ROTATE and FIRST_CODE is
10027                  ASHIFTRT.
10028
10029                  If the mode of this shift is not the mode of the outer shift,
10030                  we can't do this if either shift is a right shift or ROTATE.
10031
10032                  Finally, we can't do any of these if the mode is too wide
10033                  unless the codes are the same.
10034
10035                  Handle the case where the shift codes are the same
10036                  first.  */
10037
10038               if (code == first_code)
10039                 {
10040                   if (GET_MODE (varop) != result_mode
10041                       && (code == ASHIFTRT || code == LSHIFTRT
10042                           || code == ROTATE))
10043                     break;
10044
10045                   count += first_count;
10046                   varop = XEXP (varop, 0);
10047                   continue;
10048                 }
10049
10050               if (code == ASHIFTRT
10051                   || (code == ROTATE && first_code == ASHIFTRT)
10052                   || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10053                   || (GET_MODE (varop) != result_mode
10054                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
10055                           || first_code == ROTATE
10056                           || code == ROTATE)))
10057                 break;
10058
10059               /* To compute the mask to apply after the shift, shift the
10060                  nonzero bits of the inner shift the same way the
10061                  outer shift will.  */
10062
10063               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10064
10065               mask_rtx
10066                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10067                                                    GEN_INT (count));
10068
10069               /* Give up if we can't compute an outer operation to use.  */
10070               if (mask_rtx == 0
10071                   || !CONST_INT_P (mask_rtx)
10072                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
10073                                         INTVAL (mask_rtx),
10074                                         result_mode, &complement_p))
10075                 break;
10076
10077               /* If the shifts are in the same direction, we add the
10078                  counts.  Otherwise, we subtract them.  */
10079               if ((code == ASHIFTRT || code == LSHIFTRT)
10080                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10081                 count += first_count;
10082               else
10083                 count -= first_count;
10084
10085               /* If COUNT is positive, the new shift is usually CODE,
10086                  except for the two exceptions below, in which case it is
10087                  FIRST_CODE.  If the count is negative, FIRST_CODE should
10088                  always be used  */
10089               if (count > 0
10090                   && ((first_code == ROTATE && code == ASHIFT)
10091                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
10092                 code = first_code;
10093               else if (count < 0)
10094                 code = first_code, count = -count;
10095
10096               varop = XEXP (varop, 0);
10097               continue;
10098             }
10099
10100           /* If we have (A << B << C) for any shift, we can convert this to
10101              (A << C << B).  This wins if A is a constant.  Only try this if
10102              B is not a constant.  */
10103
10104           else if (GET_CODE (varop) == code
10105                    && CONST_INT_P (XEXP (varop, 0))
10106                    && !CONST_INT_P (XEXP (varop, 1)))
10107             {
10108               rtx new_rtx = simplify_const_binary_operation (code, mode,
10109                                                          XEXP (varop, 0),
10110                                                          GEN_INT (count));
10111               varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10112               count = 0;
10113               continue;
10114             }
10115           break;
10116
10117         case NOT:
10118           if (VECTOR_MODE_P (mode))
10119             break;
10120
10121           /* Make this fit the case below.  */
10122           varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10123           continue;
10124
10125         case IOR:
10126         case AND:
10127         case XOR:
10128           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10129              with C the size of VAROP - 1 and the shift is logical if
10130              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10131              we have an (le X 0) operation.   If we have an arithmetic shift
10132              and STORE_FLAG_VALUE is 1 or we have a logical shift with
10133              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
10134
10135           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10136               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10137               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10138               && (code == LSHIFTRT || code == ASHIFTRT)
10139               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10140               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10141             {
10142               count = 0;
10143               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10144                                   const0_rtx);
10145
10146               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10147                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10148
10149               continue;
10150             }
10151
10152           /* If we have (shift (logical)), move the logical to the outside
10153              to allow it to possibly combine with another logical and the
10154              shift to combine with another shift.  This also canonicalizes to
10155              what a ZERO_EXTRACT looks like.  Also, some machines have
10156              (and (shift)) insns.  */
10157
10158           if (CONST_INT_P (XEXP (varop, 1))
10159               /* We can't do this if we have (ashiftrt (xor))  and the
10160                  constant has its sign bit set in shift_mode.  */
10161               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10162                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10163                                               shift_mode))
10164               && (new_rtx = simplify_const_binary_operation (code, result_mode,
10165                                                          XEXP (varop, 1),
10166                                                          GEN_INT (count))) != 0
10167               && CONST_INT_P (new_rtx)
10168               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10169                                   INTVAL (new_rtx), result_mode, &complement_p))
10170             {
10171               varop = XEXP (varop, 0);
10172               continue;
10173             }
10174
10175           /* If we can't do that, try to simplify the shift in each arm of the
10176              logical expression, make a new logical expression, and apply
10177              the inverse distributive law.  This also can't be done
10178              for some (ashiftrt (xor)).  */
10179           if (CONST_INT_P (XEXP (varop, 1))
10180              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10181                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10182                                              shift_mode)))
10183             {
10184               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10185                                               XEXP (varop, 0), count);
10186               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10187                                               XEXP (varop, 1), count);
10188
10189               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10190                                            lhs, rhs);
10191               varop = apply_distributive_law (varop);
10192
10193               count = 0;
10194               continue;
10195             }
10196           break;
10197
10198         case EQ:
10199           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10200              says that the sign bit can be tested, FOO has mode MODE, C is
10201              GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10202              that may be nonzero.  */
10203           if (code == LSHIFTRT
10204               && XEXP (varop, 1) == const0_rtx
10205               && GET_MODE (XEXP (varop, 0)) == result_mode
10206               && count == (GET_MODE_PRECISION (result_mode) - 1)
10207               && HWI_COMPUTABLE_MODE_P (result_mode)
10208               && STORE_FLAG_VALUE == -1
10209               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10210               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10211                                   &complement_p))
10212             {
10213               varop = XEXP (varop, 0);
10214               count = 0;
10215               continue;
10216             }
10217           break;
10218
10219         case NEG:
10220           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10221              than the number of bits in the mode is equivalent to A.  */
10222           if (code == LSHIFTRT
10223               && count == (GET_MODE_PRECISION (result_mode) - 1)
10224               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10225             {
10226               varop = XEXP (varop, 0);
10227               count = 0;
10228               continue;
10229             }
10230
10231           /* NEG commutes with ASHIFT since it is multiplication.  Move the
10232              NEG outside to allow shifts to combine.  */
10233           if (code == ASHIFT
10234               && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10235                                   &complement_p))
10236             {
10237               varop = XEXP (varop, 0);
10238               continue;
10239             }
10240           break;
10241
10242         case PLUS:
10243           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10244              is one less than the number of bits in the mode is
10245              equivalent to (xor A 1).  */
10246           if (code == LSHIFTRT
10247               && count == (GET_MODE_PRECISION (result_mode) - 1)
10248               && XEXP (varop, 1) == constm1_rtx
10249               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10250               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10251                                   &complement_p))
10252             {
10253               count = 0;
10254               varop = XEXP (varop, 0);
10255               continue;
10256             }
10257
10258           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10259              that might be nonzero in BAR are those being shifted out and those
10260              bits are known zero in FOO, we can replace the PLUS with FOO.
10261              Similarly in the other operand order.  This code occurs when
10262              we are computing the size of a variable-size array.  */
10263
10264           if ((code == ASHIFTRT || code == LSHIFTRT)
10265               && count < HOST_BITS_PER_WIDE_INT
10266               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10267               && (nonzero_bits (XEXP (varop, 1), result_mode)
10268                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10269             {
10270               varop = XEXP (varop, 0);
10271               continue;
10272             }
10273           else if ((code == ASHIFTRT || code == LSHIFTRT)
10274                    && count < HOST_BITS_PER_WIDE_INT
10275                    && HWI_COMPUTABLE_MODE_P (result_mode)
10276                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10277                             >> count)
10278                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10279                             & nonzero_bits (XEXP (varop, 1),
10280                                                  result_mode)))
10281             {
10282               varop = XEXP (varop, 1);
10283               continue;
10284             }
10285
10286           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
10287           if (code == ASHIFT
10288               && CONST_INT_P (XEXP (varop, 1))
10289               && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10290                                                          XEXP (varop, 1),
10291                                                          GEN_INT (count))) != 0
10292               && CONST_INT_P (new_rtx)
10293               && merge_outer_ops (&outer_op, &outer_const, PLUS,
10294                                   INTVAL (new_rtx), result_mode, &complement_p))
10295             {
10296               varop = XEXP (varop, 0);
10297               continue;
10298             }
10299
10300           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10301              signbit', and attempt to change the PLUS to an XOR and move it to
10302              the outer operation as is done above in the AND/IOR/XOR case
10303              leg for shift(logical). See details in logical handling above
10304              for reasoning in doing so.  */
10305           if (code == LSHIFTRT
10306               && CONST_INT_P (XEXP (varop, 1))
10307               && mode_signbit_p (result_mode, XEXP (varop, 1))
10308               && (new_rtx = simplify_const_binary_operation (code, result_mode,
10309                                                          XEXP (varop, 1),
10310                                                          GEN_INT (count))) != 0
10311               && CONST_INT_P (new_rtx)
10312               && merge_outer_ops (&outer_op, &outer_const, XOR,
10313                                   INTVAL (new_rtx), result_mode, &complement_p))
10314             {
10315               varop = XEXP (varop, 0);
10316               continue;
10317             }
10318
10319           break;
10320
10321         case MINUS:
10322           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10323              with C the size of VAROP - 1 and the shift is logical if
10324              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10325              we have a (gt X 0) operation.  If the shift is arithmetic with
10326              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10327              we have a (neg (gt X 0)) operation.  */
10328
10329           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10330               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10331               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10332               && (code == LSHIFTRT || code == ASHIFTRT)
10333               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10334               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10335               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10336             {
10337               count = 0;
10338               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10339                                   const0_rtx);
10340
10341               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10342                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10343
10344               continue;
10345             }
10346           break;
10347
10348         case TRUNCATE:
10349           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10350              if the truncate does not affect the value.  */
10351           if (code == LSHIFTRT
10352               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10353               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10354               && (INTVAL (XEXP (XEXP (varop, 0), 1))
10355                   >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10356                       - GET_MODE_PRECISION (GET_MODE (varop)))))
10357             {
10358               rtx varop_inner = XEXP (varop, 0);
10359
10360               varop_inner
10361                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10362                                     XEXP (varop_inner, 0),
10363                                     GEN_INT
10364                                     (count + INTVAL (XEXP (varop_inner, 1))));
10365               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10366               count = 0;
10367               continue;
10368             }
10369           break;
10370
10371         default:
10372           break;
10373         }
10374
10375       break;
10376     }
10377
10378   shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10379                                      outer_op, outer_const);
10380
10381   /* We have now finished analyzing the shift.  The result should be
10382      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
10383      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10384      to the result of the shift.  OUTER_CONST is the relevant constant,
10385      but we must turn off all bits turned off in the shift.  */
10386
10387   if (outer_op == UNKNOWN
10388       && orig_code == code && orig_count == count
10389       && varop == orig_varop
10390       && shift_mode == GET_MODE (varop))
10391     return NULL_RTX;
10392
10393   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
10394   varop = gen_lowpart (shift_mode, varop);
10395   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10396     return NULL_RTX;
10397
10398   /* If we have an outer operation and we just made a shift, it is
10399      possible that we could have simplified the shift were it not
10400      for the outer operation.  So try to do the simplification
10401      recursively.  */
10402
10403   if (outer_op != UNKNOWN)
10404     x = simplify_shift_const_1 (code, shift_mode, varop, count);
10405   else
10406     x = NULL_RTX;
10407
10408   if (x == NULL_RTX)
10409     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10410
10411   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10412      turn off all the bits that the shift would have turned off.  */
10413   if (orig_code == LSHIFTRT && result_mode != shift_mode)
10414     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10415                                 GET_MODE_MASK (result_mode) >> orig_count);
10416
10417   /* Do the remainder of the processing in RESULT_MODE.  */
10418   x = gen_lowpart_or_truncate (result_mode, x);
10419
10420   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10421      operation.  */
10422   if (complement_p)
10423     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10424
10425   if (outer_op != UNKNOWN)
10426     {
10427       if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10428           && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10429         outer_const = trunc_int_for_mode (outer_const, result_mode);
10430
10431       if (outer_op == AND)
10432         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10433       else if (outer_op == SET)
10434         {
10435           /* This means that we have determined that the result is
10436              equivalent to a constant.  This should be rare.  */
10437           if (!side_effects_p (x))
10438             x = GEN_INT (outer_const);
10439         }
10440       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10441         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10442       else
10443         x = simplify_gen_binary (outer_op, result_mode, x,
10444                                  GEN_INT (outer_const));
10445     }
10446
10447   return x;
10448 }
10449
10450 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
10451    The result of the shift is RESULT_MODE.  If we cannot simplify it,
10452    return X or, if it is NULL, synthesize the expression with
10453    simplify_gen_binary.  Otherwise, return a simplified value.
10454
10455    The shift is normally computed in the widest mode we find in VAROP, as
10456    long as it isn't a different number of words than RESULT_MODE.  Exceptions
10457    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
10458
10459 static rtx
10460 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10461                       rtx varop, int count)
10462 {
10463   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10464   if (tem)
10465     return tem;
10466
10467   if (!x)
10468     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10469   if (GET_MODE (x) != result_mode)
10470     x = gen_lowpart (result_mode, x);
10471   return x;
10472 }
10473
10474 \f
10475 /* Like recog, but we receive the address of a pointer to a new pattern.
10476    We try to match the rtx that the pointer points to.
10477    If that fails, we may try to modify or replace the pattern,
10478    storing the replacement into the same pointer object.
10479
10480    Modifications include deletion or addition of CLOBBERs.
10481
10482    PNOTES is a pointer to a location where any REG_UNUSED notes added for
10483    the CLOBBERs are placed.
10484
10485    The value is the final insn code from the pattern ultimately matched,
10486    or -1.  */
10487
10488 static int
10489 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10490 {
10491   rtx pat = *pnewpat;
10492   rtx pat_without_clobbers;
10493   int insn_code_number;
10494   int num_clobbers_to_add = 0;
10495   int i;
10496   rtx notes = NULL_RTX;
10497   rtx old_notes, old_pat;
10498   int old_icode;
10499
10500   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10501      we use to indicate that something didn't match.  If we find such a
10502      thing, force rejection.  */
10503   if (GET_CODE (pat) == PARALLEL)
10504     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10505       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10506           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10507         return -1;
10508
10509   old_pat = PATTERN (insn);
10510   old_notes = REG_NOTES (insn);
10511   PATTERN (insn) = pat;
10512   REG_NOTES (insn) = NULL_RTX;
10513
10514   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10515   if (dump_file && (dump_flags & TDF_DETAILS))
10516     {
10517       if (insn_code_number < 0)
10518         fputs ("Failed to match this instruction:\n", dump_file);
10519       else
10520         fputs ("Successfully matched this instruction:\n", dump_file);
10521       print_rtl_single (dump_file, pat);
10522     }
10523
10524   /* If it isn't, there is the possibility that we previously had an insn
10525      that clobbered some register as a side effect, but the combined
10526      insn doesn't need to do that.  So try once more without the clobbers
10527      unless this represents an ASM insn.  */
10528
10529   if (insn_code_number < 0 && ! check_asm_operands (pat)
10530       && GET_CODE (pat) == PARALLEL)
10531     {
10532       int pos;
10533
10534       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10535         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10536           {
10537             if (i != pos)
10538               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10539             pos++;
10540           }
10541
10542       SUBST_INT (XVECLEN (pat, 0), pos);
10543
10544       if (pos == 1)
10545         pat = XVECEXP (pat, 0, 0);
10546
10547       PATTERN (insn) = pat;
10548       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10549       if (dump_file && (dump_flags & TDF_DETAILS))
10550         {
10551           if (insn_code_number < 0)
10552             fputs ("Failed to match this instruction:\n", dump_file);
10553           else
10554             fputs ("Successfully matched this instruction:\n", dump_file);
10555           print_rtl_single (dump_file, pat);
10556         }
10557     }
10558
10559   pat_without_clobbers = pat;
10560
10561   PATTERN (insn) = old_pat;
10562   REG_NOTES (insn) = old_notes;
10563
10564   /* Recognize all noop sets, these will be killed by followup pass.  */
10565   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10566     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10567
10568   /* If we had any clobbers to add, make a new pattern than contains
10569      them.  Then check to make sure that all of them are dead.  */
10570   if (num_clobbers_to_add)
10571     {
10572       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10573                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
10574                                                   ? (XVECLEN (pat, 0)
10575                                                      + num_clobbers_to_add)
10576                                                   : num_clobbers_to_add + 1));
10577
10578       if (GET_CODE (pat) == PARALLEL)
10579         for (i = 0; i < XVECLEN (pat, 0); i++)
10580           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10581       else
10582         XVECEXP (newpat, 0, 0) = pat;
10583
10584       add_clobbers (newpat, insn_code_number);
10585
10586       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10587            i < XVECLEN (newpat, 0); i++)
10588         {
10589           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10590               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10591             return -1;
10592           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10593             {
10594               gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10595               notes = alloc_reg_note (REG_UNUSED,
10596                                       XEXP (XVECEXP (newpat, 0, i), 0), notes);
10597             }
10598         }
10599       pat = newpat;
10600     }
10601
10602   if (insn_code_number >= 0
10603       && insn_code_number != NOOP_MOVE_INSN_CODE)
10604     {
10605       old_pat = PATTERN (insn);
10606       old_notes = REG_NOTES (insn);
10607       old_icode = INSN_CODE (insn);
10608       PATTERN (insn) = pat;
10609       REG_NOTES (insn) = notes;
10610
10611       /* Allow targets to reject combined insn.  */
10612       if (!targetm.legitimate_combined_insn (insn))
10613         {
10614           if (dump_file && (dump_flags & TDF_DETAILS))
10615             fputs ("Instruction not appropriate for target.",
10616                    dump_file);
10617
10618           /* Callers expect recog_for_combine to strip
10619              clobbers from the pattern on failure.  */
10620           pat = pat_without_clobbers;
10621           notes = NULL_RTX;
10622
10623           insn_code_number = -1;
10624         }
10625
10626       PATTERN (insn) = old_pat;
10627       REG_NOTES (insn) = old_notes;
10628       INSN_CODE (insn) = old_icode;
10629     }
10630
10631   *pnewpat = pat;
10632   *pnotes = notes;
10633
10634   return insn_code_number;
10635 }
10636 \f
10637 /* Like gen_lowpart_general but for use by combine.  In combine it
10638    is not possible to create any new pseudoregs.  However, it is
10639    safe to create invalid memory addresses, because combine will
10640    try to recognize them and all they will do is make the combine
10641    attempt fail.
10642
10643    If for some reason this cannot do its job, an rtx
10644    (clobber (const_int 0)) is returned.
10645    An insn containing that will not be recognized.  */
10646
10647 static rtx
10648 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10649 {
10650   enum machine_mode imode = GET_MODE (x);
10651   unsigned int osize = GET_MODE_SIZE (omode);
10652   unsigned int isize = GET_MODE_SIZE (imode);
10653   rtx result;
10654
10655   if (omode == imode)
10656     return x;
10657
10658   /* We can only support MODE being wider than a word if X is a
10659      constant integer or has a mode the same size.  */
10660   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10661       && ! ((CONST_INT_P (x) || CONST_DOUBLE_AS_INT_P (x))
10662             || isize == osize))
10663     goto fail;
10664
10665   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
10666      won't know what to do.  So we will strip off the SUBREG here and
10667      process normally.  */
10668   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10669     {
10670       x = SUBREG_REG (x);
10671
10672       /* For use in case we fall down into the address adjustments
10673          further below, we need to adjust the known mode and size of
10674          x; imode and isize, since we just adjusted x.  */
10675       imode = GET_MODE (x);
10676
10677       if (imode == omode)
10678         return x;
10679
10680       isize = GET_MODE_SIZE (imode);
10681     }
10682
10683   result = gen_lowpart_common (omode, x);
10684
10685   if (result)
10686     return result;
10687
10688   if (MEM_P (x))
10689     {
10690       int offset = 0;
10691
10692       /* Refuse to work on a volatile memory ref or one with a mode-dependent
10693          address.  */
10694       if (MEM_VOLATILE_P (x)
10695           || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
10696         goto fail;
10697
10698       /* If we want to refer to something bigger than the original memref,
10699          generate a paradoxical subreg instead.  That will force a reload
10700          of the original memref X.  */
10701       if (isize < osize)
10702         return gen_rtx_SUBREG (omode, x, 0);
10703
10704       if (WORDS_BIG_ENDIAN)
10705         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10706
10707       /* Adjust the address so that the address-after-the-data is
10708          unchanged.  */
10709       if (BYTES_BIG_ENDIAN)
10710         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10711
10712       return adjust_address_nv (x, omode, offset);
10713     }
10714
10715   /* If X is a comparison operator, rewrite it in a new mode.  This
10716      probably won't match, but may allow further simplifications.  */
10717   else if (COMPARISON_P (x))
10718     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10719
10720   /* If we couldn't simplify X any other way, just enclose it in a
10721      SUBREG.  Normally, this SUBREG won't match, but some patterns may
10722      include an explicit SUBREG or we may simplify it further in combine.  */
10723   else
10724     {
10725       int offset = 0;
10726       rtx res;
10727
10728       offset = subreg_lowpart_offset (omode, imode);
10729       if (imode == VOIDmode)
10730         {
10731           imode = int_mode_for_mode (omode);
10732           x = gen_lowpart_common (imode, x);
10733           if (x == NULL)
10734             goto fail;
10735         }
10736       res = simplify_gen_subreg (omode, x, imode, offset);
10737       if (res)
10738         return res;
10739     }
10740
10741  fail:
10742   return gen_rtx_CLOBBER (omode, const0_rtx);
10743 }
10744 \f
10745 /* Try to simplify a comparison between OP0 and a constant OP1,
10746    where CODE is the comparison code that will be tested, into a
10747    (CODE OP0 const0_rtx) form.
10748
10749    The result is a possibly different comparison code to use.
10750    *POP1 may be updated.  */
10751
10752 static enum rtx_code
10753 simplify_compare_const (enum rtx_code code, rtx op0, rtx *pop1)
10754 {
10755   enum machine_mode mode = GET_MODE (op0);
10756   unsigned int mode_width = GET_MODE_PRECISION (mode);
10757   HOST_WIDE_INT const_op = INTVAL (*pop1);
10758
10759   /* Get the constant we are comparing against and turn off all bits
10760      not on in our mode.  */
10761   if (mode != VOIDmode)
10762     const_op = trunc_int_for_mode (const_op, mode);
10763
10764   /* If we are comparing against a constant power of two and the value
10765      being compared can only have that single bit nonzero (e.g., it was
10766      `and'ed with that bit), we can replace this with a comparison
10767      with zero.  */
10768   if (const_op
10769       && (code == EQ || code == NE || code == GE || code == GEU
10770           || code == LT || code == LTU)
10771       && mode_width <= HOST_BITS_PER_WIDE_INT
10772       && exact_log2 (const_op) >= 0
10773       && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10774     {
10775       code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10776       const_op = 0;
10777     }
10778
10779   /* Similarly, if we are comparing a value known to be either -1 or
10780      0 with -1, change it to the opposite comparison against zero.  */
10781   if (const_op == -1
10782       && (code == EQ || code == NE || code == GT || code == LE
10783           || code == GEU || code == LTU)
10784       && num_sign_bit_copies (op0, mode) == mode_width)
10785     {
10786       code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10787       const_op = 0;
10788     }
10789
10790   /* Do some canonicalizations based on the comparison code.  We prefer
10791      comparisons against zero and then prefer equality comparisons.
10792      If we can reduce the size of a constant, we will do that too.  */
10793   switch (code)
10794     {
10795     case LT:
10796       /* < C is equivalent to <= (C - 1) */
10797       if (const_op > 0)
10798         {
10799           const_op -= 1;
10800           code = LE;
10801           /* ... fall through to LE case below.  */
10802         }
10803       else
10804         break;
10805
10806     case LE:
10807       /* <= C is equivalent to < (C + 1); we do this for C < 0  */
10808       if (const_op < 0)
10809         {
10810           const_op += 1;
10811           code = LT;
10812         }
10813
10814       /* If we are doing a <= 0 comparison on a value known to have
10815          a zero sign bit, we can replace this with == 0.  */
10816       else if (const_op == 0
10817                && mode_width <= HOST_BITS_PER_WIDE_INT
10818                && (nonzero_bits (op0, mode)
10819                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10820                == 0)
10821         code = EQ;
10822       break;
10823
10824     case GE:
10825       /* >= C is equivalent to > (C - 1).  */
10826       if (const_op > 0)
10827         {
10828           const_op -= 1;
10829           code = GT;
10830           /* ... fall through to GT below.  */
10831         }
10832       else
10833         break;
10834
10835     case GT:
10836       /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
10837       if (const_op < 0)
10838         {
10839           const_op += 1;
10840           code = GE;
10841         }
10842
10843       /* If we are doing a > 0 comparison on a value known to have
10844          a zero sign bit, we can replace this with != 0.  */
10845       else if (const_op == 0
10846                && mode_width <= HOST_BITS_PER_WIDE_INT
10847                && (nonzero_bits (op0, mode)
10848                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10849                == 0)
10850         code = NE;
10851       break;
10852
10853     case LTU:
10854       /* < C is equivalent to <= (C - 1).  */
10855       if (const_op > 0)
10856         {
10857           const_op -= 1;
10858           code = LEU;
10859           /* ... fall through ...  */
10860         }
10861       /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
10862       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10863                && (unsigned HOST_WIDE_INT) const_op
10864                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10865         {
10866           const_op = 0;
10867           code = GE;
10868           break;
10869         }
10870       else
10871         break;
10872
10873     case LEU:
10874       /* unsigned <= 0 is equivalent to == 0 */
10875       if (const_op == 0)
10876         code = EQ;
10877       /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
10878       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10879                && (unsigned HOST_WIDE_INT) const_op
10880                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10881         {
10882           const_op = 0;
10883           code = GE;
10884         }
10885       break;
10886
10887     case GEU:
10888       /* >= C is equivalent to > (C - 1).  */
10889       if (const_op > 1)
10890         {
10891           const_op -= 1;
10892           code = GTU;
10893           /* ... fall through ...  */
10894         }
10895
10896       /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
10897       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10898                && (unsigned HOST_WIDE_INT) const_op
10899                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10900         {
10901           const_op = 0;
10902           code = LT;
10903           break;
10904         }
10905       else
10906         break;
10907
10908     case GTU:
10909       /* unsigned > 0 is equivalent to != 0 */
10910       if (const_op == 0)
10911         code = NE;
10912       /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
10913       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10914                && (unsigned HOST_WIDE_INT) const_op
10915                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10916         {
10917           const_op = 0;
10918           code = LT;
10919         }
10920       break;
10921
10922     default:
10923       break;
10924     }
10925
10926   *pop1 = GEN_INT (const_op);
10927   return code;
10928 }
10929 \f
10930 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10931    comparison code that will be tested.
10932
10933    The result is a possibly different comparison code to use.  *POP0 and
10934    *POP1 may be updated.
10935
10936    It is possible that we might detect that a comparison is either always
10937    true or always false.  However, we do not perform general constant
10938    folding in combine, so this knowledge isn't useful.  Such tautologies
10939    should have been detected earlier.  Hence we ignore all such cases.  */
10940
10941 static enum rtx_code
10942 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10943 {
10944   rtx op0 = *pop0;
10945   rtx op1 = *pop1;
10946   rtx tem, tem1;
10947   int i;
10948   enum machine_mode mode, tmode;
10949
10950   /* Try a few ways of applying the same transformation to both operands.  */
10951   while (1)
10952     {
10953 #ifndef WORD_REGISTER_OPERATIONS
10954       /* The test below this one won't handle SIGN_EXTENDs on these machines,
10955          so check specially.  */
10956       if (code != GTU && code != GEU && code != LTU && code != LEU
10957           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10958           && GET_CODE (XEXP (op0, 0)) == ASHIFT
10959           && GET_CODE (XEXP (op1, 0)) == ASHIFT
10960           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10961           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10962           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10963               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10964           && CONST_INT_P (XEXP (op0, 1))
10965           && XEXP (op0, 1) == XEXP (op1, 1)
10966           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10967           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10968           && (INTVAL (XEXP (op0, 1))
10969               == (GET_MODE_PRECISION (GET_MODE (op0))
10970                   - (GET_MODE_PRECISION
10971                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10972         {
10973           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10974           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10975         }
10976 #endif
10977
10978       /* If both operands are the same constant shift, see if we can ignore the
10979          shift.  We can if the shift is a rotate or if the bits shifted out of
10980          this shift are known to be zero for both inputs and if the type of
10981          comparison is compatible with the shift.  */
10982       if (GET_CODE (op0) == GET_CODE (op1)
10983           && HWI_COMPUTABLE_MODE_P (GET_MODE(op0))
10984           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10985               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10986                   && (code != GT && code != LT && code != GE && code != LE))
10987               || (GET_CODE (op0) == ASHIFTRT
10988                   && (code != GTU && code != LTU
10989                       && code != GEU && code != LEU)))
10990           && CONST_INT_P (XEXP (op0, 1))
10991           && INTVAL (XEXP (op0, 1)) >= 0
10992           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10993           && XEXP (op0, 1) == XEXP (op1, 1))
10994         {
10995           enum machine_mode mode = GET_MODE (op0);
10996           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10997           int shift_count = INTVAL (XEXP (op0, 1));
10998
10999           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11000             mask &= (mask >> shift_count) << shift_count;
11001           else if (GET_CODE (op0) == ASHIFT)
11002             mask = (mask & (mask << shift_count)) >> shift_count;
11003
11004           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11005               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11006             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11007           else
11008             break;
11009         }
11010
11011       /* If both operands are AND's of a paradoxical SUBREG by constant, the
11012          SUBREGs are of the same mode, and, in both cases, the AND would
11013          be redundant if the comparison was done in the narrower mode,
11014          do the comparison in the narrower mode (e.g., we are AND'ing with 1
11015          and the operand's possibly nonzero bits are 0xffffff01; in that case
11016          if we only care about QImode, we don't need the AND).  This case
11017          occurs if the output mode of an scc insn is not SImode and
11018          STORE_FLAG_VALUE == 1 (e.g., the 386).
11019
11020          Similarly, check for a case where the AND's are ZERO_EXTEND
11021          operations from some narrower mode even though a SUBREG is not
11022          present.  */
11023
11024       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11025                && CONST_INT_P (XEXP (op0, 1))
11026                && CONST_INT_P (XEXP (op1, 1)))
11027         {
11028           rtx inner_op0 = XEXP (op0, 0);
11029           rtx inner_op1 = XEXP (op1, 0);
11030           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11031           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11032           int changed = 0;
11033
11034           if (paradoxical_subreg_p (inner_op0)
11035               && GET_CODE (inner_op1) == SUBREG
11036               && (GET_MODE (SUBREG_REG (inner_op0))
11037                   == GET_MODE (SUBREG_REG (inner_op1)))
11038               && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11039                   <= HOST_BITS_PER_WIDE_INT)
11040               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11041                                              GET_MODE (SUBREG_REG (inner_op0)))))
11042               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11043                                              GET_MODE (SUBREG_REG (inner_op1))))))
11044             {
11045               op0 = SUBREG_REG (inner_op0);
11046               op1 = SUBREG_REG (inner_op1);
11047
11048               /* The resulting comparison is always unsigned since we masked
11049                  off the original sign bit.  */
11050               code = unsigned_condition (code);
11051
11052               changed = 1;
11053             }
11054
11055           else if (c0 == c1)
11056             for (tmode = GET_CLASS_NARROWEST_MODE
11057                  (GET_MODE_CLASS (GET_MODE (op0)));
11058                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11059               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11060                 {
11061                   op0 = gen_lowpart (tmode, inner_op0);
11062                   op1 = gen_lowpart (tmode, inner_op1);
11063                   code = unsigned_condition (code);
11064                   changed = 1;
11065                   break;
11066                 }
11067
11068           if (! changed)
11069             break;
11070         }
11071
11072       /* If both operands are NOT, we can strip off the outer operation
11073          and adjust the comparison code for swapped operands; similarly for
11074          NEG, except that this must be an equality comparison.  */
11075       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11076                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11077                    && (code == EQ || code == NE)))
11078         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11079
11080       else
11081         break;
11082     }
11083
11084   /* If the first operand is a constant, swap the operands and adjust the
11085      comparison code appropriately, but don't do this if the second operand
11086      is already a constant integer.  */
11087   if (swap_commutative_operands_p (op0, op1))
11088     {
11089       tem = op0, op0 = op1, op1 = tem;
11090       code = swap_condition (code);
11091     }
11092
11093   /* We now enter a loop during which we will try to simplify the comparison.
11094      For the most part, we only are concerned with comparisons with zero,
11095      but some things may really be comparisons with zero but not start
11096      out looking that way.  */
11097
11098   while (CONST_INT_P (op1))
11099     {
11100       enum machine_mode mode = GET_MODE (op0);
11101       unsigned int mode_width = GET_MODE_PRECISION (mode);
11102       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11103       int equality_comparison_p;
11104       int sign_bit_comparison_p;
11105       int unsigned_comparison_p;
11106       HOST_WIDE_INT const_op;
11107
11108       /* We only want to handle integral modes.  This catches VOIDmode,
11109          CCmode, and the floating-point modes.  An exception is that we
11110          can handle VOIDmode if OP0 is a COMPARE or a comparison
11111          operation.  */
11112
11113       if (GET_MODE_CLASS (mode) != MODE_INT
11114           && ! (mode == VOIDmode
11115                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11116         break;
11117
11118       /* Try to simplify the compare to constant, possibly changing the
11119          comparison op, and/or changing op1 to zero.  */
11120       code = simplify_compare_const (code, op0, &op1);
11121       const_op = INTVAL (op1);
11122
11123       /* Compute some predicates to simplify code below.  */
11124
11125       equality_comparison_p = (code == EQ || code == NE);
11126       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11127       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11128                                || code == GEU);
11129
11130       /* If this is a sign bit comparison and we can do arithmetic in
11131          MODE, say that we will only be needing the sign bit of OP0.  */
11132       if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11133         op0 = force_to_mode (op0, mode,
11134                              (unsigned HOST_WIDE_INT) 1
11135                              << (GET_MODE_PRECISION (mode) - 1),
11136                              0);
11137
11138       /* Now try cases based on the opcode of OP0.  If none of the cases
11139          does a "continue", we exit this loop immediately after the
11140          switch.  */
11141
11142       switch (GET_CODE (op0))
11143         {
11144         case ZERO_EXTRACT:
11145           /* If we are extracting a single bit from a variable position in
11146              a constant that has only a single bit set and are comparing it
11147              with zero, we can convert this into an equality comparison
11148              between the position and the location of the single bit.  */
11149           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11150              have already reduced the shift count modulo the word size.  */
11151           if (!SHIFT_COUNT_TRUNCATED
11152               && CONST_INT_P (XEXP (op0, 0))
11153               && XEXP (op0, 1) == const1_rtx
11154               && equality_comparison_p && const_op == 0
11155               && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11156             {
11157               if (BITS_BIG_ENDIAN)
11158                 i = BITS_PER_WORD - 1 - i;
11159
11160               op0 = XEXP (op0, 2);
11161               op1 = GEN_INT (i);
11162               const_op = i;
11163
11164               /* Result is nonzero iff shift count is equal to I.  */
11165               code = reverse_condition (code);
11166               continue;
11167             }
11168
11169           /* ... fall through ...  */
11170
11171         case SIGN_EXTRACT:
11172           tem = expand_compound_operation (op0);
11173           if (tem != op0)
11174             {
11175               op0 = tem;
11176               continue;
11177             }
11178           break;
11179
11180         case NOT:
11181           /* If testing for equality, we can take the NOT of the constant.  */
11182           if (equality_comparison_p
11183               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11184             {
11185               op0 = XEXP (op0, 0);
11186               op1 = tem;
11187               continue;
11188             }
11189
11190           /* If just looking at the sign bit, reverse the sense of the
11191              comparison.  */
11192           if (sign_bit_comparison_p)
11193             {
11194               op0 = XEXP (op0, 0);
11195               code = (code == GE ? LT : GE);
11196               continue;
11197             }
11198           break;
11199
11200         case NEG:
11201           /* If testing for equality, we can take the NEG of the constant.  */
11202           if (equality_comparison_p
11203               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11204             {
11205               op0 = XEXP (op0, 0);
11206               op1 = tem;
11207               continue;
11208             }
11209
11210           /* The remaining cases only apply to comparisons with zero.  */
11211           if (const_op != 0)
11212             break;
11213
11214           /* When X is ABS or is known positive,
11215              (neg X) is < 0 if and only if X != 0.  */
11216
11217           if (sign_bit_comparison_p
11218               && (GET_CODE (XEXP (op0, 0)) == ABS
11219                   || (mode_width <= HOST_BITS_PER_WIDE_INT
11220                       && (nonzero_bits (XEXP (op0, 0), mode)
11221                           & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11222                          == 0)))
11223             {
11224               op0 = XEXP (op0, 0);
11225               code = (code == LT ? NE : EQ);
11226               continue;
11227             }
11228
11229           /* If we have NEG of something whose two high-order bits are the
11230              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
11231           if (num_sign_bit_copies (op0, mode) >= 2)
11232             {
11233               op0 = XEXP (op0, 0);
11234               code = swap_condition (code);
11235               continue;
11236             }
11237           break;
11238
11239         case ROTATE:
11240           /* If we are testing equality and our count is a constant, we
11241              can perform the inverse operation on our RHS.  */
11242           if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11243               && (tem = simplify_binary_operation (ROTATERT, mode,
11244                                                    op1, XEXP (op0, 1))) != 0)
11245             {
11246               op0 = XEXP (op0, 0);
11247               op1 = tem;
11248               continue;
11249             }
11250
11251           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11252              a particular bit.  Convert it to an AND of a constant of that
11253              bit.  This will be converted into a ZERO_EXTRACT.  */
11254           if (const_op == 0 && sign_bit_comparison_p
11255               && CONST_INT_P (XEXP (op0, 1))
11256               && mode_width <= HOST_BITS_PER_WIDE_INT)
11257             {
11258               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11259                                             ((unsigned HOST_WIDE_INT) 1
11260                                              << (mode_width - 1
11261                                                  - INTVAL (XEXP (op0, 1)))));
11262               code = (code == LT ? NE : EQ);
11263               continue;
11264             }
11265
11266           /* Fall through.  */
11267
11268         case ABS:
11269           /* ABS is ignorable inside an equality comparison with zero.  */
11270           if (const_op == 0 && equality_comparison_p)
11271             {
11272               op0 = XEXP (op0, 0);
11273               continue;
11274             }
11275           break;
11276
11277         case SIGN_EXTEND:
11278           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11279              (compare FOO CONST) if CONST fits in FOO's mode and we
11280              are either testing inequality or have an unsigned
11281              comparison with ZERO_EXTEND or a signed comparison with
11282              SIGN_EXTEND.  But don't do it if we don't have a compare
11283              insn of the given mode, since we'd have to revert it
11284              later on, and then we wouldn't know whether to sign- or
11285              zero-extend.  */
11286           mode = GET_MODE (XEXP (op0, 0));
11287           if (GET_MODE_CLASS (mode) == MODE_INT
11288               && ! unsigned_comparison_p
11289               && HWI_COMPUTABLE_MODE_P (mode)
11290               && trunc_int_for_mode (const_op, mode) == const_op
11291               && have_insn_for (COMPARE, mode))
11292             {
11293               op0 = XEXP (op0, 0);
11294               continue;
11295             }
11296           break;
11297
11298         case SUBREG:
11299           /* Check for the case where we are comparing A - C1 with C2, that is
11300
11301                (subreg:MODE (plus (A) (-C1))) op (C2)
11302
11303              with C1 a constant, and try to lift the SUBREG, i.e. to do the
11304              comparison in the wider mode.  One of the following two conditions
11305              must be true in order for this to be valid:
11306
11307                1. The mode extension results in the same bit pattern being added
11308                   on both sides and the comparison is equality or unsigned.  As
11309                   C2 has been truncated to fit in MODE, the pattern can only be
11310                   all 0s or all 1s.
11311
11312                2. The mode extension results in the sign bit being copied on
11313                   each side.
11314
11315              The difficulty here is that we have predicates for A but not for
11316              (A - C1) so we need to check that C1 is within proper bounds so
11317              as to perturbate A as little as possible.  */
11318
11319           if (mode_width <= HOST_BITS_PER_WIDE_INT
11320               && subreg_lowpart_p (op0)
11321               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11322               && GET_CODE (SUBREG_REG (op0)) == PLUS
11323               && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11324             {
11325               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11326               rtx a = XEXP (SUBREG_REG (op0), 0);
11327               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11328
11329               if ((c1 > 0
11330                    && (unsigned HOST_WIDE_INT) c1
11331                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11332                    && (equality_comparison_p || unsigned_comparison_p)
11333                    /* (A - C1) zero-extends if it is positive and sign-extends
11334                       if it is negative, C2 both zero- and sign-extends.  */
11335                    && ((0 == (nonzero_bits (a, inner_mode)
11336                               & ~GET_MODE_MASK (mode))
11337                         && const_op >= 0)
11338                        /* (A - C1) sign-extends if it is positive and 1-extends
11339                           if it is negative, C2 both sign- and 1-extends.  */
11340                        || (num_sign_bit_copies (a, inner_mode)
11341                            > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11342                                              - mode_width)
11343                            && const_op < 0)))
11344                   || ((unsigned HOST_WIDE_INT) c1
11345                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11346                       /* (A - C1) always sign-extends, like C2.  */
11347                       && num_sign_bit_copies (a, inner_mode)
11348                          > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11349                                            - (mode_width - 1))))
11350                 {
11351                   op0 = SUBREG_REG (op0);
11352                   continue;
11353                 }
11354             }
11355
11356           /* If the inner mode is narrower and we are extracting the low part,
11357              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
11358           if (subreg_lowpart_p (op0)
11359               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11360             /* Fall through */ ;
11361           else
11362             break;
11363
11364           /* ... fall through ...  */
11365
11366         case ZERO_EXTEND:
11367           mode = GET_MODE (XEXP (op0, 0));
11368           if (GET_MODE_CLASS (mode) == MODE_INT
11369               && (unsigned_comparison_p || equality_comparison_p)
11370               && HWI_COMPUTABLE_MODE_P (mode)
11371               && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11372               && const_op >= 0
11373               && have_insn_for (COMPARE, mode))
11374             {
11375               op0 = XEXP (op0, 0);
11376               continue;
11377             }
11378           break;
11379
11380         case PLUS:
11381           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
11382              this for equality comparisons due to pathological cases involving
11383              overflows.  */
11384           if (equality_comparison_p
11385               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11386                                                         op1, XEXP (op0, 1))))
11387             {
11388               op0 = XEXP (op0, 0);
11389               op1 = tem;
11390               continue;
11391             }
11392
11393           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
11394           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11395               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11396             {
11397               op0 = XEXP (XEXP (op0, 0), 0);
11398               code = (code == LT ? EQ : NE);
11399               continue;
11400             }
11401           break;
11402
11403         case MINUS:
11404           /* We used to optimize signed comparisons against zero, but that
11405              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
11406              arrive here as equality comparisons, or (GEU, LTU) are
11407              optimized away.  No need to special-case them.  */
11408
11409           /* (eq (minus A B) C) -> (eq A (plus B C)) or
11410              (eq B (minus A C)), whichever simplifies.  We can only do
11411              this for equality comparisons due to pathological cases involving
11412              overflows.  */
11413           if (equality_comparison_p
11414               && 0 != (tem = simplify_binary_operation (PLUS, mode,
11415                                                         XEXP (op0, 1), op1)))
11416             {
11417               op0 = XEXP (op0, 0);
11418               op1 = tem;
11419               continue;
11420             }
11421
11422           if (equality_comparison_p
11423               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11424                                                         XEXP (op0, 0), op1)))
11425             {
11426               op0 = XEXP (op0, 1);
11427               op1 = tem;
11428               continue;
11429             }
11430
11431           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11432              of bits in X minus 1, is one iff X > 0.  */
11433           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11434               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11435               && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11436               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11437             {
11438               op0 = XEXP (op0, 1);
11439               code = (code == GE ? LE : GT);
11440               continue;
11441             }
11442           break;
11443
11444         case XOR:
11445           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
11446              if C is zero or B is a constant.  */
11447           if (equality_comparison_p
11448               && 0 != (tem = simplify_binary_operation (XOR, mode,
11449                                                         XEXP (op0, 1), op1)))
11450             {
11451               op0 = XEXP (op0, 0);
11452               op1 = tem;
11453               continue;
11454             }
11455           break;
11456
11457         case EQ:  case NE:
11458         case UNEQ:  case LTGT:
11459         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
11460         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
11461         case UNORDERED: case ORDERED:
11462           /* We can't do anything if OP0 is a condition code value, rather
11463              than an actual data value.  */
11464           if (const_op != 0
11465               || CC0_P (XEXP (op0, 0))
11466               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11467             break;
11468
11469           /* Get the two operands being compared.  */
11470           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11471             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11472           else
11473             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11474
11475           /* Check for the cases where we simply want the result of the
11476              earlier test or the opposite of that result.  */
11477           if (code == NE || code == EQ
11478               || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11479                   && (code == LT || code == GE)))
11480             {
11481               enum rtx_code new_code;
11482               if (code == LT || code == NE)
11483                 new_code = GET_CODE (op0);
11484               else
11485                 new_code = reversed_comparison_code (op0, NULL);
11486
11487               if (new_code != UNKNOWN)
11488                 {
11489                   code = new_code;
11490                   op0 = tem;
11491                   op1 = tem1;
11492                   continue;
11493                 }
11494             }
11495           break;
11496
11497         case IOR:
11498           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11499              iff X <= 0.  */
11500           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11501               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11502               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11503             {
11504               op0 = XEXP (op0, 1);
11505               code = (code == GE ? GT : LE);
11506               continue;
11507             }
11508           break;
11509
11510         case AND:
11511           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
11512              will be converted to a ZERO_EXTRACT later.  */
11513           if (const_op == 0 && equality_comparison_p
11514               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11515               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11516             {
11517               op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11518                                       XEXP (XEXP (op0, 0), 1));
11519               op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11520               continue;
11521             }
11522
11523           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11524              zero and X is a comparison and C1 and C2 describe only bits set
11525              in STORE_FLAG_VALUE, we can compare with X.  */
11526           if (const_op == 0 && equality_comparison_p
11527               && mode_width <= HOST_BITS_PER_WIDE_INT
11528               && CONST_INT_P (XEXP (op0, 1))
11529               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11530               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11531               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11532               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11533             {
11534               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11535                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
11536               if ((~STORE_FLAG_VALUE & mask) == 0
11537                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11538                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11539                           && COMPARISON_P (tem))))
11540                 {
11541                   op0 = XEXP (XEXP (op0, 0), 0);
11542                   continue;
11543                 }
11544             }
11545
11546           /* If we are doing an equality comparison of an AND of a bit equal
11547              to the sign bit, replace this with a LT or GE comparison of
11548              the underlying value.  */
11549           if (equality_comparison_p
11550               && const_op == 0
11551               && CONST_INT_P (XEXP (op0, 1))
11552               && mode_width <= HOST_BITS_PER_WIDE_INT
11553               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11554                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11555             {
11556               op0 = XEXP (op0, 0);
11557               code = (code == EQ ? GE : LT);
11558               continue;
11559             }
11560
11561           /* If this AND operation is really a ZERO_EXTEND from a narrower
11562              mode, the constant fits within that mode, and this is either an
11563              equality or unsigned comparison, try to do this comparison in
11564              the narrower mode.
11565
11566              Note that in:
11567
11568              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11569              -> (ne:DI (reg:SI 4) (const_int 0))
11570
11571              unless TRULY_NOOP_TRUNCATION allows it or the register is
11572              known to hold a value of the required mode the
11573              transformation is invalid.  */
11574           if ((equality_comparison_p || unsigned_comparison_p)
11575               && CONST_INT_P (XEXP (op0, 1))
11576               && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11577                                    & GET_MODE_MASK (mode))
11578                                   + 1)) >= 0
11579               && const_op >> i == 0
11580               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11581               && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11582                   || (REG_P (XEXP (op0, 0))
11583                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11584             {
11585               op0 = gen_lowpart (tmode, XEXP (op0, 0));
11586               continue;
11587             }
11588
11589           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11590              fits in both M1 and M2 and the SUBREG is either paradoxical
11591              or represents the low part, permute the SUBREG and the AND
11592              and try again.  */
11593           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11594             {
11595               unsigned HOST_WIDE_INT c1;
11596               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11597               /* Require an integral mode, to avoid creating something like
11598                  (AND:SF ...).  */
11599               if (SCALAR_INT_MODE_P (tmode)
11600                   /* It is unsafe to commute the AND into the SUBREG if the
11601                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11602                      not defined.  As originally written the upper bits
11603                      have a defined value due to the AND operation.
11604                      However, if we commute the AND inside the SUBREG then
11605                      they no longer have defined values and the meaning of
11606                      the code has been changed.  */
11607                   && (0
11608 #ifdef WORD_REGISTER_OPERATIONS
11609                       || (mode_width > GET_MODE_PRECISION (tmode)
11610                           && mode_width <= BITS_PER_WORD)
11611 #endif
11612                       || (mode_width <= GET_MODE_PRECISION (tmode)
11613                           && subreg_lowpart_p (XEXP (op0, 0))))
11614                   && CONST_INT_P (XEXP (op0, 1))
11615                   && mode_width <= HOST_BITS_PER_WIDE_INT
11616                   && HWI_COMPUTABLE_MODE_P (tmode)
11617                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11618                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
11619                   && c1 != mask
11620                   && c1 != GET_MODE_MASK (tmode))
11621                 {
11622                   op0 = simplify_gen_binary (AND, tmode,
11623                                              SUBREG_REG (XEXP (op0, 0)),
11624                                              gen_int_mode (c1, tmode));
11625                   op0 = gen_lowpart (mode, op0);
11626                   continue;
11627                 }
11628             }
11629
11630           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
11631           if (const_op == 0 && equality_comparison_p
11632               && XEXP (op0, 1) == const1_rtx
11633               && GET_CODE (XEXP (op0, 0)) == NOT)
11634             {
11635               op0 = simplify_and_const_int (NULL_RTX, mode,
11636                                             XEXP (XEXP (op0, 0), 0), 1);
11637               code = (code == NE ? EQ : NE);
11638               continue;
11639             }
11640
11641           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11642              (eq (and (lshiftrt X) 1) 0).
11643              Also handle the case where (not X) is expressed using xor.  */
11644           if (const_op == 0 && equality_comparison_p
11645               && XEXP (op0, 1) == const1_rtx
11646               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11647             {
11648               rtx shift_op = XEXP (XEXP (op0, 0), 0);
11649               rtx shift_count = XEXP (XEXP (op0, 0), 1);
11650
11651               if (GET_CODE (shift_op) == NOT
11652                   || (GET_CODE (shift_op) == XOR
11653                       && CONST_INT_P (XEXP (shift_op, 1))
11654                       && CONST_INT_P (shift_count)
11655                       && HWI_COMPUTABLE_MODE_P (mode)
11656                       && (UINTVAL (XEXP (shift_op, 1))
11657                           == (unsigned HOST_WIDE_INT) 1
11658                                << INTVAL (shift_count))))
11659                 {
11660                   op0
11661                     = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11662                   op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11663                   code = (code == NE ? EQ : NE);
11664                   continue;
11665                 }
11666             }
11667           break;
11668
11669         case ASHIFT:
11670           /* If we have (compare (ashift FOO N) (const_int C)) and
11671              the high order N bits of FOO (N+1 if an inequality comparison)
11672              are known to be zero, we can do this by comparing FOO with C
11673              shifted right N bits so long as the low-order N bits of C are
11674              zero.  */
11675           if (CONST_INT_P (XEXP (op0, 1))
11676               && INTVAL (XEXP (op0, 1)) >= 0
11677               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11678                   < HOST_BITS_PER_WIDE_INT)
11679               && (((unsigned HOST_WIDE_INT) const_op
11680                    & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11681                       - 1)) == 0)
11682               && mode_width <= HOST_BITS_PER_WIDE_INT
11683               && (nonzero_bits (XEXP (op0, 0), mode)
11684                   & ~(mask >> (INTVAL (XEXP (op0, 1))
11685                                + ! equality_comparison_p))) == 0)
11686             {
11687               /* We must perform a logical shift, not an arithmetic one,
11688                  as we want the top N bits of C to be zero.  */
11689               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11690
11691               temp >>= INTVAL (XEXP (op0, 1));
11692               op1 = gen_int_mode (temp, mode);
11693               op0 = XEXP (op0, 0);
11694               continue;
11695             }
11696
11697           /* If we are doing a sign bit comparison, it means we are testing
11698              a particular bit.  Convert it to the appropriate AND.  */
11699           if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11700               && mode_width <= HOST_BITS_PER_WIDE_INT)
11701             {
11702               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11703                                             ((unsigned HOST_WIDE_INT) 1
11704                                              << (mode_width - 1
11705                                                  - INTVAL (XEXP (op0, 1)))));
11706               code = (code == LT ? NE : EQ);
11707               continue;
11708             }
11709
11710           /* If this an equality comparison with zero and we are shifting
11711              the low bit to the sign bit, we can convert this to an AND of the
11712              low-order bit.  */
11713           if (const_op == 0 && equality_comparison_p
11714               && CONST_INT_P (XEXP (op0, 1))
11715               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11716             {
11717               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11718               continue;
11719             }
11720           break;
11721
11722         case ASHIFTRT:
11723           /* If this is an equality comparison with zero, we can do this
11724              as a logical shift, which might be much simpler.  */
11725           if (equality_comparison_p && const_op == 0
11726               && CONST_INT_P (XEXP (op0, 1)))
11727             {
11728               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11729                                           XEXP (op0, 0),
11730                                           INTVAL (XEXP (op0, 1)));
11731               continue;
11732             }
11733
11734           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11735              do the comparison in a narrower mode.  */
11736           if (! unsigned_comparison_p
11737               && CONST_INT_P (XEXP (op0, 1))
11738               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11739               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11740               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11741                                          MODE_INT, 1)) != BLKmode
11742               && (((unsigned HOST_WIDE_INT) const_op
11743                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11744                   <= GET_MODE_MASK (tmode)))
11745             {
11746               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11747               continue;
11748             }
11749
11750           /* Likewise if OP0 is a PLUS of a sign extension with a
11751              constant, which is usually represented with the PLUS
11752              between the shifts.  */
11753           if (! unsigned_comparison_p
11754               && CONST_INT_P (XEXP (op0, 1))
11755               && GET_CODE (XEXP (op0, 0)) == PLUS
11756               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11757               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11758               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11759               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11760                                          MODE_INT, 1)) != BLKmode
11761               && (((unsigned HOST_WIDE_INT) const_op
11762                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11763                   <= GET_MODE_MASK (tmode)))
11764             {
11765               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11766               rtx add_const = XEXP (XEXP (op0, 0), 1);
11767               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11768                                                    add_const, XEXP (op0, 1));
11769
11770               op0 = simplify_gen_binary (PLUS, tmode,
11771                                          gen_lowpart (tmode, inner),
11772                                          new_const);
11773               continue;
11774             }
11775
11776           /* ... fall through ...  */
11777         case LSHIFTRT:
11778           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11779              the low order N bits of FOO are known to be zero, we can do this
11780              by comparing FOO with C shifted left N bits so long as no
11781              overflow occurs.  Even if the low order N bits of FOO aren't known
11782              to be zero, if the comparison is >= or < we can use the same
11783              optimization and for > or <= by setting all the low
11784              order N bits in the comparison constant.  */
11785           if (CONST_INT_P (XEXP (op0, 1))
11786               && INTVAL (XEXP (op0, 1)) > 0
11787               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11788               && mode_width <= HOST_BITS_PER_WIDE_INT
11789               && (((unsigned HOST_WIDE_INT) const_op
11790                    + (GET_CODE (op0) != LSHIFTRT
11791                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11792                          + 1)
11793                       : 0))
11794                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11795             {
11796               unsigned HOST_WIDE_INT low_bits
11797                 = (nonzero_bits (XEXP (op0, 0), mode)
11798                    & (((unsigned HOST_WIDE_INT) 1
11799                        << INTVAL (XEXP (op0, 1))) - 1));
11800               if (low_bits == 0 || !equality_comparison_p)
11801                 {
11802                   /* If the shift was logical, then we must make the condition
11803                      unsigned.  */
11804                   if (GET_CODE (op0) == LSHIFTRT)
11805                     code = unsigned_condition (code);
11806
11807                   const_op <<= INTVAL (XEXP (op0, 1));
11808                   if (low_bits != 0
11809                       && (code == GT || code == GTU
11810                           || code == LE || code == LEU))
11811                     const_op
11812                       |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11813                   op1 = GEN_INT (const_op);
11814                   op0 = XEXP (op0, 0);
11815                   continue;
11816                 }
11817             }
11818
11819           /* If we are using this shift to extract just the sign bit, we
11820              can replace this with an LT or GE comparison.  */
11821           if (const_op == 0
11822               && (equality_comparison_p || sign_bit_comparison_p)
11823               && CONST_INT_P (XEXP (op0, 1))
11824               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11825             {
11826               op0 = XEXP (op0, 0);
11827               code = (code == NE || code == GT ? LT : GE);
11828               continue;
11829             }
11830           break;
11831
11832         default:
11833           break;
11834         }
11835
11836       break;
11837     }
11838
11839   /* Now make any compound operations involved in this comparison.  Then,
11840      check for an outmost SUBREG on OP0 that is not doing anything or is
11841      paradoxical.  The latter transformation must only be performed when
11842      it is known that the "extra" bits will be the same in op0 and op1 or
11843      that they don't matter.  There are three cases to consider:
11844
11845      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
11846      care bits and we can assume they have any convenient value.  So
11847      making the transformation is safe.
11848
11849      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11850      In this case the upper bits of op0 are undefined.  We should not make
11851      the simplification in that case as we do not know the contents of
11852      those bits.
11853
11854      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11855      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
11856      also be sure that they are the same as the upper bits of op1.
11857
11858      We can never remove a SUBREG for a non-equality comparison because
11859      the sign bit is in a different place in the underlying object.  */
11860
11861   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11862   op1 = make_compound_operation (op1, SET);
11863
11864   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11865       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11866       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11867       && (code == NE || code == EQ))
11868     {
11869       if (paradoxical_subreg_p (op0))
11870         {
11871           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
11872              implemented.  */
11873           if (REG_P (SUBREG_REG (op0)))
11874             {
11875               op0 = SUBREG_REG (op0);
11876               op1 = gen_lowpart (GET_MODE (op0), op1);
11877             }
11878         }
11879       else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
11880                 <= HOST_BITS_PER_WIDE_INT)
11881                && (nonzero_bits (SUBREG_REG (op0),
11882                                  GET_MODE (SUBREG_REG (op0)))
11883                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11884         {
11885           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11886
11887           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11888                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11889             op0 = SUBREG_REG (op0), op1 = tem;
11890         }
11891     }
11892
11893   /* We now do the opposite procedure: Some machines don't have compare
11894      insns in all modes.  If OP0's mode is an integer mode smaller than a
11895      word and we can't do a compare in that mode, see if there is a larger
11896      mode for which we can do the compare.  There are a number of cases in
11897      which we can use the wider mode.  */
11898
11899   mode = GET_MODE (op0);
11900   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11901       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11902       && ! have_insn_for (COMPARE, mode))
11903     for (tmode = GET_MODE_WIDER_MODE (mode);
11904          (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
11905          tmode = GET_MODE_WIDER_MODE (tmode))
11906       if (have_insn_for (COMPARE, tmode))
11907         {
11908           int zero_extended;
11909
11910           /* If this is a test for negative, we can make an explicit
11911              test of the sign bit.  Test this first so we can use
11912              a paradoxical subreg to extend OP0.  */
11913
11914           if (op1 == const0_rtx && (code == LT || code == GE)
11915               && HWI_COMPUTABLE_MODE_P (mode))
11916             {
11917               op0 = simplify_gen_binary (AND, tmode,
11918                                          gen_lowpart (tmode, op0),
11919                                          GEN_INT ((unsigned HOST_WIDE_INT) 1
11920                                                   << (GET_MODE_BITSIZE (mode)
11921                                                       - 1)));
11922               code = (code == LT) ? NE : EQ;
11923               break;
11924             }
11925
11926           /* If the only nonzero bits in OP0 and OP1 are those in the
11927              narrower mode and this is an equality or unsigned comparison,
11928              we can use the wider mode.  Similarly for sign-extended
11929              values, in which case it is true for all comparisons.  */
11930           zero_extended = ((code == EQ || code == NE
11931                             || code == GEU || code == GTU
11932                             || code == LEU || code == LTU)
11933                            && (nonzero_bits (op0, tmode)
11934                                & ~GET_MODE_MASK (mode)) == 0
11935                            && ((CONST_INT_P (op1)
11936                                 || (nonzero_bits (op1, tmode)
11937                                     & ~GET_MODE_MASK (mode)) == 0)));
11938
11939           if (zero_extended
11940               || ((num_sign_bit_copies (op0, tmode)
11941                    > (unsigned int) (GET_MODE_PRECISION (tmode)
11942                                      - GET_MODE_PRECISION (mode)))
11943                   && (num_sign_bit_copies (op1, tmode)
11944                       > (unsigned int) (GET_MODE_PRECISION (tmode)
11945                                         - GET_MODE_PRECISION (mode)))))
11946             {
11947               /* If OP0 is an AND and we don't have an AND in MODE either,
11948                  make a new AND in the proper mode.  */
11949               if (GET_CODE (op0) == AND
11950                   && !have_insn_for (AND, mode))
11951                 op0 = simplify_gen_binary (AND, tmode,
11952                                            gen_lowpart (tmode,
11953                                                         XEXP (op0, 0)),
11954                                            gen_lowpart (tmode,
11955                                                         XEXP (op0, 1)));
11956               else
11957                 {
11958                   if (zero_extended)
11959                     {
11960                       op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11961                       op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11962                     }
11963                   else
11964                     {
11965                       op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11966                       op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
11967                     }
11968                   break;
11969                 }
11970             }
11971         }
11972
11973 #ifdef CANONICALIZE_COMPARISON
11974   /* If this machine only supports a subset of valid comparisons, see if we
11975      can convert an unsupported one into a supported one.  */
11976   CANONICALIZE_COMPARISON (code, op0, op1);
11977 #endif
11978
11979   *pop0 = op0;
11980   *pop1 = op1;
11981
11982   return code;
11983 }
11984 \f
11985 /* Utility function for record_value_for_reg.  Count number of
11986    rtxs in X.  */
11987 static int
11988 count_rtxs (rtx x)
11989 {
11990   enum rtx_code code = GET_CODE (x);
11991   const char *fmt;
11992   int i, j, ret = 1;
11993
11994   if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
11995       || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
11996     {
11997       rtx x0 = XEXP (x, 0);
11998       rtx x1 = XEXP (x, 1);
11999
12000       if (x0 == x1)
12001         return 1 + 2 * count_rtxs (x0);
12002
12003       if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
12004            || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
12005           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12006         return 2 + 2 * count_rtxs (x0)
12007                + count_rtxs (x == XEXP (x1, 0)
12008                              ? XEXP (x1, 1) : XEXP (x1, 0));
12009
12010       if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
12011            || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
12012           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12013         return 2 + 2 * count_rtxs (x1)
12014                + count_rtxs (x == XEXP (x0, 0)
12015                              ? XEXP (x0, 1) : XEXP (x0, 0));
12016     }
12017
12018   fmt = GET_RTX_FORMAT (code);
12019   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12020     if (fmt[i] == 'e')
12021       ret += count_rtxs (XEXP (x, i));
12022     else if (fmt[i] == 'E')
12023       for (j = 0; j < XVECLEN (x, i); j++)
12024         ret += count_rtxs (XVECEXP (x, i, j));
12025
12026   return ret;
12027 }
12028 \f
12029 /* Utility function for following routine.  Called when X is part of a value
12030    being stored into last_set_value.  Sets last_set_table_tick
12031    for each register mentioned.  Similar to mention_regs in cse.c  */
12032
12033 static void
12034 update_table_tick (rtx x)
12035 {
12036   enum rtx_code code = GET_CODE (x);
12037   const char *fmt = GET_RTX_FORMAT (code);
12038   int i, j;
12039
12040   if (code == REG)
12041     {
12042       unsigned int regno = REGNO (x);
12043       unsigned int endregno = END_REGNO (x);
12044       unsigned int r;
12045
12046       for (r = regno; r < endregno; r++)
12047         {
12048           reg_stat_type *rsp = &VEC_index (reg_stat_type, reg_stat, r);
12049           rsp->last_set_table_tick = label_tick;
12050         }
12051
12052       return;
12053     }
12054
12055   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12056     if (fmt[i] == 'e')
12057       {
12058         /* Check for identical subexpressions.  If x contains
12059            identical subexpression we only have to traverse one of
12060            them.  */
12061         if (i == 0 && ARITHMETIC_P (x))
12062           {
12063             /* Note that at this point x1 has already been
12064                processed.  */
12065             rtx x0 = XEXP (x, 0);
12066             rtx x1 = XEXP (x, 1);
12067
12068             /* If x0 and x1 are identical then there is no need to
12069                process x0.  */
12070             if (x0 == x1)
12071               break;
12072
12073             /* If x0 is identical to a subexpression of x1 then while
12074                processing x1, x0 has already been processed.  Thus we
12075                are done with x.  */
12076             if (ARITHMETIC_P (x1)
12077                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12078               break;
12079
12080             /* If x1 is identical to a subexpression of x0 then we
12081                still have to process the rest of x0.  */
12082             if (ARITHMETIC_P (x0)
12083                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12084               {
12085                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12086                 break;
12087               }
12088           }
12089
12090         update_table_tick (XEXP (x, i));
12091       }
12092     else if (fmt[i] == 'E')
12093       for (j = 0; j < XVECLEN (x, i); j++)
12094         update_table_tick (XVECEXP (x, i, j));
12095 }
12096
12097 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
12098    are saying that the register is clobbered and we no longer know its
12099    value.  If INSN is zero, don't update reg_stat[].last_set; this is
12100    only permitted with VALUE also zero and is used to invalidate the
12101    register.  */
12102
12103 static void
12104 record_value_for_reg (rtx reg, rtx insn, rtx value)
12105 {
12106   unsigned int regno = REGNO (reg);
12107   unsigned int endregno = END_REGNO (reg);
12108   unsigned int i;
12109   reg_stat_type *rsp;
12110
12111   /* If VALUE contains REG and we have a previous value for REG, substitute
12112      the previous value.  */
12113   if (value && insn && reg_overlap_mentioned_p (reg, value))
12114     {
12115       rtx tem;
12116
12117       /* Set things up so get_last_value is allowed to see anything set up to
12118          our insn.  */
12119       subst_low_luid = DF_INSN_LUID (insn);
12120       tem = get_last_value (reg);
12121
12122       /* If TEM is simply a binary operation with two CLOBBERs as operands,
12123          it isn't going to be useful and will take a lot of time to process,
12124          so just use the CLOBBER.  */
12125
12126       if (tem)
12127         {
12128           if (ARITHMETIC_P (tem)
12129               && GET_CODE (XEXP (tem, 0)) == CLOBBER
12130               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12131             tem = XEXP (tem, 0);
12132           else if (count_occurrences (value, reg, 1) >= 2)
12133             {
12134               /* If there are two or more occurrences of REG in VALUE,
12135                  prevent the value from growing too much.  */
12136               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12137                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12138             }
12139
12140           value = replace_rtx (copy_rtx (value), reg, tem);
12141         }
12142     }
12143
12144   /* For each register modified, show we don't know its value, that
12145      we don't know about its bitwise content, that its value has been
12146      updated, and that we don't know the location of the death of the
12147      register.  */
12148   for (i = regno; i < endregno; i++)
12149     {
12150       rsp = &VEC_index (reg_stat_type, reg_stat, i);
12151
12152       if (insn)
12153         rsp->last_set = insn;
12154
12155       rsp->last_set_value = 0;
12156       rsp->last_set_mode = VOIDmode;
12157       rsp->last_set_nonzero_bits = 0;
12158       rsp->last_set_sign_bit_copies = 0;
12159       rsp->last_death = 0;
12160       rsp->truncated_to_mode = VOIDmode;
12161     }
12162
12163   /* Mark registers that are being referenced in this value.  */
12164   if (value)
12165     update_table_tick (value);
12166
12167   /* Now update the status of each register being set.
12168      If someone is using this register in this block, set this register
12169      to invalid since we will get confused between the two lives in this
12170      basic block.  This makes using this register always invalid.  In cse, we
12171      scan the table to invalidate all entries using this register, but this
12172      is too much work for us.  */
12173
12174   for (i = regno; i < endregno; i++)
12175     {
12176       rsp = &VEC_index (reg_stat_type, reg_stat, i);
12177       rsp->last_set_label = label_tick;
12178       if (!insn
12179           || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12180         rsp->last_set_invalid = 1;
12181       else
12182         rsp->last_set_invalid = 0;
12183     }
12184
12185   /* The value being assigned might refer to X (like in "x++;").  In that
12186      case, we must replace it with (clobber (const_int 0)) to prevent
12187      infinite loops.  */
12188   rsp = &VEC_index (reg_stat_type, reg_stat, regno);
12189   if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12190     {
12191       value = copy_rtx (value);
12192       if (!get_last_value_validate (&value, insn, label_tick, 1))
12193         value = 0;
12194     }
12195
12196   /* For the main register being modified, update the value, the mode, the
12197      nonzero bits, and the number of sign bit copies.  */
12198
12199   rsp->last_set_value = value;
12200
12201   if (value)
12202     {
12203       enum machine_mode mode = GET_MODE (reg);
12204       subst_low_luid = DF_INSN_LUID (insn);
12205       rsp->last_set_mode = mode;
12206       if (GET_MODE_CLASS (mode) == MODE_INT
12207           && HWI_COMPUTABLE_MODE_P (mode))
12208         mode = nonzero_bits_mode;
12209       rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12210       rsp->last_set_sign_bit_copies
12211         = num_sign_bit_copies (value, GET_MODE (reg));
12212     }
12213 }
12214
12215 /* Called via note_stores from record_dead_and_set_regs to handle one
12216    SET or CLOBBER in an insn.  DATA is the instruction in which the
12217    set is occurring.  */
12218
12219 static void
12220 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12221 {
12222   rtx record_dead_insn = (rtx) data;
12223
12224   if (GET_CODE (dest) == SUBREG)
12225     dest = SUBREG_REG (dest);
12226
12227   if (!record_dead_insn)
12228     {
12229       if (REG_P (dest))
12230         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12231       return;
12232     }
12233
12234   if (REG_P (dest))
12235     {
12236       /* If we are setting the whole register, we know its value.  Otherwise
12237          show that we don't know the value.  We can handle SUBREG in
12238          some cases.  */
12239       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12240         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12241       else if (GET_CODE (setter) == SET
12242                && GET_CODE (SET_DEST (setter)) == SUBREG
12243                && SUBREG_REG (SET_DEST (setter)) == dest
12244                && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12245                && subreg_lowpart_p (SET_DEST (setter)))
12246         record_value_for_reg (dest, record_dead_insn,
12247                               gen_lowpart (GET_MODE (dest),
12248                                                        SET_SRC (setter)));
12249       else
12250         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12251     }
12252   else if (MEM_P (dest)
12253            /* Ignore pushes, they clobber nothing.  */
12254            && ! push_operand (dest, GET_MODE (dest)))
12255     mem_last_set = DF_INSN_LUID (record_dead_insn);
12256 }
12257
12258 /* Update the records of when each REG was most recently set or killed
12259    for the things done by INSN.  This is the last thing done in processing
12260    INSN in the combiner loop.
12261
12262    We update reg_stat[], in particular fields last_set, last_set_value,
12263    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12264    last_death, and also the similar information mem_last_set (which insn
12265    most recently modified memory) and last_call_luid (which insn was the
12266    most recent subroutine call).  */
12267
12268 static void
12269 record_dead_and_set_regs (rtx insn)
12270 {
12271   rtx link;
12272   unsigned int i;
12273
12274   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12275     {
12276       if (REG_NOTE_KIND (link) == REG_DEAD
12277           && REG_P (XEXP (link, 0)))
12278         {
12279           unsigned int regno = REGNO (XEXP (link, 0));
12280           unsigned int endregno = END_REGNO (XEXP (link, 0));
12281
12282           for (i = regno; i < endregno; i++)
12283             {
12284               reg_stat_type *rsp;
12285
12286               rsp = &VEC_index (reg_stat_type, reg_stat, i);
12287               rsp->last_death = insn;
12288             }
12289         }
12290       else if (REG_NOTE_KIND (link) == REG_INC)
12291         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12292     }
12293
12294   if (CALL_P (insn))
12295     {
12296       hard_reg_set_iterator hrsi;
12297       EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi)
12298         {
12299           reg_stat_type *rsp;
12300
12301           rsp = &VEC_index (reg_stat_type, reg_stat, i);
12302           rsp->last_set_invalid = 1;
12303           rsp->last_set = insn;
12304           rsp->last_set_value = 0;
12305           rsp->last_set_mode = VOIDmode;
12306           rsp->last_set_nonzero_bits = 0;
12307           rsp->last_set_sign_bit_copies = 0;
12308           rsp->last_death = 0;
12309           rsp->truncated_to_mode = VOIDmode;
12310         }
12311
12312       last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12313
12314       /* We can't combine into a call pattern.  Remember, though, that
12315          the return value register is set at this LUID.  We could
12316          still replace a register with the return value from the
12317          wrong subroutine call!  */
12318       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12319     }
12320   else
12321     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12322 }
12323
12324 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12325    register present in the SUBREG, so for each such SUBREG go back and
12326    adjust nonzero and sign bit information of the registers that are
12327    known to have some zero/sign bits set.
12328
12329    This is needed because when combine blows the SUBREGs away, the
12330    information on zero/sign bits is lost and further combines can be
12331    missed because of that.  */
12332
12333 static void
12334 record_promoted_value (rtx insn, rtx subreg)
12335 {
12336   struct insn_link *links;
12337   rtx set;
12338   unsigned int regno = REGNO (SUBREG_REG (subreg));
12339   enum machine_mode mode = GET_MODE (subreg);
12340
12341   if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12342     return;
12343
12344   for (links = LOG_LINKS (insn); links;)
12345     {
12346       reg_stat_type *rsp;
12347
12348       insn = links->insn;
12349       set = single_set (insn);
12350
12351       if (! set || !REG_P (SET_DEST (set))
12352           || REGNO (SET_DEST (set)) != regno
12353           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12354         {
12355           links = links->next;
12356           continue;
12357         }
12358
12359       rsp = &VEC_index (reg_stat_type, reg_stat, regno);
12360       if (rsp->last_set == insn)
12361         {
12362           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12363             rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12364         }
12365
12366       if (REG_P (SET_SRC (set)))
12367         {
12368           regno = REGNO (SET_SRC (set));
12369           links = LOG_LINKS (insn);
12370         }
12371       else
12372         break;
12373     }
12374 }
12375
12376 /* Check if X, a register, is known to contain a value already
12377    truncated to MODE.  In this case we can use a subreg to refer to
12378    the truncated value even though in the generic case we would need
12379    an explicit truncation.  */
12380
12381 static bool
12382 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12383 {
12384   reg_stat_type *rsp = &VEC_index (reg_stat_type, reg_stat, REGNO (x));
12385   enum machine_mode truncated = rsp->truncated_to_mode;
12386
12387   if (truncated == 0
12388       || rsp->truncation_label < label_tick_ebb_start)
12389     return false;
12390   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12391     return true;
12392   if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12393     return true;
12394   return false;
12395 }
12396
12397 /* Callback for for_each_rtx.  If *P is a hard reg or a subreg record the mode
12398    that the register is accessed in.  For non-TRULY_NOOP_TRUNCATION targets we
12399    might be able to turn a truncate into a subreg using this information.
12400    Return -1 if traversing *P is complete or 0 otherwise.  */
12401
12402 static int
12403 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12404 {
12405   rtx x = *p;
12406   enum machine_mode truncated_mode;
12407   reg_stat_type *rsp;
12408
12409   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12410     {
12411       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12412       truncated_mode = GET_MODE (x);
12413
12414       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12415         return -1;
12416
12417       if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12418         return -1;
12419
12420       x = SUBREG_REG (x);
12421     }
12422   /* ??? For hard-regs we now record everything.  We might be able to
12423      optimize this using last_set_mode.  */
12424   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12425     truncated_mode = GET_MODE (x);
12426   else
12427     return 0;
12428
12429   rsp = &VEC_index (reg_stat_type, reg_stat, REGNO (x));
12430   if (rsp->truncated_to_mode == 0
12431       || rsp->truncation_label < label_tick_ebb_start
12432       || (GET_MODE_SIZE (truncated_mode)
12433           < GET_MODE_SIZE (rsp->truncated_to_mode)))
12434     {
12435       rsp->truncated_to_mode = truncated_mode;
12436       rsp->truncation_label = label_tick;
12437     }
12438
12439   return -1;
12440 }
12441
12442 /* Callback for note_uses.  Find hardregs and subregs of pseudos and
12443    the modes they are used in.  This can help truning TRUNCATEs into
12444    SUBREGs.  */
12445
12446 static void
12447 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12448 {
12449   for_each_rtx (x, record_truncated_value, NULL);
12450 }
12451
12452 /* Scan X for promoted SUBREGs.  For each one found,
12453    note what it implies to the registers used in it.  */
12454
12455 static void
12456 check_promoted_subreg (rtx insn, rtx x)
12457 {
12458   if (GET_CODE (x) == SUBREG
12459       && SUBREG_PROMOTED_VAR_P (x)
12460       && REG_P (SUBREG_REG (x)))
12461     record_promoted_value (insn, x);
12462   else
12463     {
12464       const char *format = GET_RTX_FORMAT (GET_CODE (x));
12465       int i, j;
12466
12467       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12468         switch (format[i])
12469           {
12470           case 'e':
12471             check_promoted_subreg (insn, XEXP (x, i));
12472             break;
12473           case 'V':
12474           case 'E':
12475             if (XVEC (x, i) != 0)
12476               for (j = 0; j < XVECLEN (x, i); j++)
12477                 check_promoted_subreg (insn, XVECEXP (x, i, j));
12478             break;
12479           }
12480     }
12481 }
12482 \f
12483 /* Verify that all the registers and memory references mentioned in *LOC are
12484    still valid.  *LOC was part of a value set in INSN when label_tick was
12485    equal to TICK.  Return 0 if some are not.  If REPLACE is nonzero, replace
12486    the invalid references with (clobber (const_int 0)) and return 1.  This
12487    replacement is useful because we often can get useful information about
12488    the form of a value (e.g., if it was produced by a shift that always
12489    produces -1 or 0) even though we don't know exactly what registers it
12490    was produced from.  */
12491
12492 static int
12493 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12494 {
12495   rtx x = *loc;
12496   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12497   int len = GET_RTX_LENGTH (GET_CODE (x));
12498   int i, j;
12499
12500   if (REG_P (x))
12501     {
12502       unsigned int regno = REGNO (x);
12503       unsigned int endregno = END_REGNO (x);
12504       unsigned int j;
12505
12506       for (j = regno; j < endregno; j++)
12507         {
12508           reg_stat_type *rsp = &VEC_index (reg_stat_type, reg_stat, j);
12509           if (rsp->last_set_invalid
12510               /* If this is a pseudo-register that was only set once and not
12511                  live at the beginning of the function, it is always valid.  */
12512               || (! (regno >= FIRST_PSEUDO_REGISTER
12513                      && REG_N_SETS (regno) == 1
12514                      && (!REGNO_REG_SET_P
12515                          (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12516                   && rsp->last_set_label > tick))
12517           {
12518             if (replace)
12519               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12520             return replace;
12521           }
12522         }
12523
12524       return 1;
12525     }
12526   /* If this is a memory reference, make sure that there were no stores after
12527      it that might have clobbered the value.  We don't have alias info, so we
12528      assume any store invalidates it.  Moreover, we only have local UIDs, so
12529      we also assume that there were stores in the intervening basic blocks.  */
12530   else if (MEM_P (x) && !MEM_READONLY_P (x)
12531            && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12532     {
12533       if (replace)
12534         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12535       return replace;
12536     }
12537
12538   for (i = 0; i < len; i++)
12539     {
12540       if (fmt[i] == 'e')
12541         {
12542           /* Check for identical subexpressions.  If x contains
12543              identical subexpression we only have to traverse one of
12544              them.  */
12545           if (i == 1 && ARITHMETIC_P (x))
12546             {
12547               /* Note that at this point x0 has already been checked
12548                  and found valid.  */
12549               rtx x0 = XEXP (x, 0);
12550               rtx x1 = XEXP (x, 1);
12551
12552               /* If x0 and x1 are identical then x is also valid.  */
12553               if (x0 == x1)
12554                 return 1;
12555
12556               /* If x1 is identical to a subexpression of x0 then
12557                  while checking x0, x1 has already been checked.  Thus
12558                  it is valid and so as x.  */
12559               if (ARITHMETIC_P (x0)
12560                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12561                 return 1;
12562
12563               /* If x0 is identical to a subexpression of x1 then x is
12564                  valid iff the rest of x1 is valid.  */
12565               if (ARITHMETIC_P (x1)
12566                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12567                 return
12568                   get_last_value_validate (&XEXP (x1,
12569                                                   x0 == XEXP (x1, 0) ? 1 : 0),
12570                                            insn, tick, replace);
12571             }
12572
12573           if (get_last_value_validate (&XEXP (x, i), insn, tick,
12574                                        replace) == 0)
12575             return 0;
12576         }
12577       else if (fmt[i] == 'E')
12578         for (j = 0; j < XVECLEN (x, i); j++)
12579           if (get_last_value_validate (&XVECEXP (x, i, j),
12580                                        insn, tick, replace) == 0)
12581             return 0;
12582     }
12583
12584   /* If we haven't found a reason for it to be invalid, it is valid.  */
12585   return 1;
12586 }
12587
12588 /* Get the last value assigned to X, if known.  Some registers
12589    in the value may be replaced with (clobber (const_int 0)) if their value
12590    is known longer known reliably.  */
12591
12592 static rtx
12593 get_last_value (const_rtx x)
12594 {
12595   unsigned int regno;
12596   rtx value;
12597   reg_stat_type *rsp;
12598
12599   /* If this is a non-paradoxical SUBREG, get the value of its operand and
12600      then convert it to the desired mode.  If this is a paradoxical SUBREG,
12601      we cannot predict what values the "extra" bits might have.  */
12602   if (GET_CODE (x) == SUBREG
12603       && subreg_lowpart_p (x)
12604       && !paradoxical_subreg_p (x)
12605       && (value = get_last_value (SUBREG_REG (x))) != 0)
12606     return gen_lowpart (GET_MODE (x), value);
12607
12608   if (!REG_P (x))
12609     return 0;
12610
12611   regno = REGNO (x);
12612   rsp = &VEC_index (reg_stat_type, reg_stat, regno);
12613   value = rsp->last_set_value;
12614
12615   /* If we don't have a value, or if it isn't for this basic block and
12616      it's either a hard register, set more than once, or it's a live
12617      at the beginning of the function, return 0.
12618
12619      Because if it's not live at the beginning of the function then the reg
12620      is always set before being used (is never used without being set).
12621      And, if it's set only once, and it's always set before use, then all
12622      uses must have the same last value, even if it's not from this basic
12623      block.  */
12624
12625   if (value == 0
12626       || (rsp->last_set_label < label_tick_ebb_start
12627           && (regno < FIRST_PSEUDO_REGISTER
12628               || REG_N_SETS (regno) != 1
12629               || REGNO_REG_SET_P
12630                  (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12631     return 0;
12632
12633   /* If the value was set in a later insn than the ones we are processing,
12634      we can't use it even if the register was only set once.  */
12635   if (rsp->last_set_label == label_tick
12636       && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12637     return 0;
12638
12639   /* If the value has all its registers valid, return it.  */
12640   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12641     return value;
12642
12643   /* Otherwise, make a copy and replace any invalid register with
12644      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
12645
12646   value = copy_rtx (value);
12647   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12648     return value;
12649
12650   return 0;
12651 }
12652 \f
12653 /* Return nonzero if expression X refers to a REG or to memory
12654    that is set in an instruction more recent than FROM_LUID.  */
12655
12656 static int
12657 use_crosses_set_p (const_rtx x, int from_luid)
12658 {
12659   const char *fmt;
12660   int i;
12661   enum rtx_code code = GET_CODE (x);
12662
12663   if (code == REG)
12664     {
12665       unsigned int regno = REGNO (x);
12666       unsigned endreg = END_REGNO (x);
12667
12668 #ifdef PUSH_ROUNDING
12669       /* Don't allow uses of the stack pointer to be moved,
12670          because we don't know whether the move crosses a push insn.  */
12671       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12672         return 1;
12673 #endif
12674       for (; regno < endreg; regno++)
12675         {
12676           reg_stat_type *rsp = &VEC_index (reg_stat_type, reg_stat, regno);
12677           if (rsp->last_set
12678               && rsp->last_set_label == label_tick
12679               && DF_INSN_LUID (rsp->last_set) > from_luid)
12680             return 1;
12681         }
12682       return 0;
12683     }
12684
12685   if (code == MEM && mem_last_set > from_luid)
12686     return 1;
12687
12688   fmt = GET_RTX_FORMAT (code);
12689
12690   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12691     {
12692       if (fmt[i] == 'E')
12693         {
12694           int j;
12695           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12696             if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12697               return 1;
12698         }
12699       else if (fmt[i] == 'e'
12700                && use_crosses_set_p (XEXP (x, i), from_luid))
12701         return 1;
12702     }
12703   return 0;
12704 }
12705 \f
12706 /* Define three variables used for communication between the following
12707    routines.  */
12708
12709 static unsigned int reg_dead_regno, reg_dead_endregno;
12710 static int reg_dead_flag;
12711
12712 /* Function called via note_stores from reg_dead_at_p.
12713
12714    If DEST is within [reg_dead_regno, reg_dead_endregno), set
12715    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
12716
12717 static void
12718 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12719 {
12720   unsigned int regno, endregno;
12721
12722   if (!REG_P (dest))
12723     return;
12724
12725   regno = REGNO (dest);
12726   endregno = END_REGNO (dest);
12727   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12728     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12729 }
12730
12731 /* Return nonzero if REG is known to be dead at INSN.
12732
12733    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
12734    referencing REG, it is dead.  If we hit a SET referencing REG, it is
12735    live.  Otherwise, see if it is live or dead at the start of the basic
12736    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
12737    must be assumed to be always live.  */
12738
12739 static int
12740 reg_dead_at_p (rtx reg, rtx insn)
12741 {
12742   basic_block block;
12743   unsigned int i;
12744
12745   /* Set variables for reg_dead_at_p_1.  */
12746   reg_dead_regno = REGNO (reg);
12747   reg_dead_endregno = END_REGNO (reg);
12748
12749   reg_dead_flag = 0;
12750
12751   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
12752      we allow the machine description to decide whether use-and-clobber
12753      patterns are OK.  */
12754   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12755     {
12756       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12757         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12758           return 0;
12759     }
12760
12761   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12762      beginning of basic block.  */
12763   block = BLOCK_FOR_INSN (insn);
12764   for (;;)
12765     {
12766       if (INSN_P (insn))
12767         {
12768           note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12769           if (reg_dead_flag)
12770             return reg_dead_flag == 1 ? 1 : 0;
12771
12772           if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12773             return 1;
12774         }
12775
12776       if (insn == BB_HEAD (block))
12777         break;
12778
12779       insn = PREV_INSN (insn);
12780     }
12781
12782   /* Look at live-in sets for the basic block that we were in.  */
12783   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12784     if (REGNO_REG_SET_P (df_get_live_in (block), i))
12785       return 0;
12786
12787   return 1;
12788 }
12789 \f
12790 /* Note hard registers in X that are used.  */
12791
12792 static void
12793 mark_used_regs_combine (rtx x)
12794 {
12795   RTX_CODE code = GET_CODE (x);
12796   unsigned int regno;
12797   int i;
12798
12799   switch (code)
12800     {
12801     case LABEL_REF:
12802     case SYMBOL_REF:
12803     case CONST:
12804     CASE_CONST_ANY:
12805     case PC:
12806     case ADDR_VEC:
12807     case ADDR_DIFF_VEC:
12808     case ASM_INPUT:
12809 #ifdef HAVE_cc0
12810     /* CC0 must die in the insn after it is set, so we don't need to take
12811        special note of it here.  */
12812     case CC0:
12813 #endif
12814       return;
12815
12816     case CLOBBER:
12817       /* If we are clobbering a MEM, mark any hard registers inside the
12818          address as used.  */
12819       if (MEM_P (XEXP (x, 0)))
12820         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12821       return;
12822
12823     case REG:
12824       regno = REGNO (x);
12825       /* A hard reg in a wide mode may really be multiple registers.
12826          If so, mark all of them just like the first.  */
12827       if (regno < FIRST_PSEUDO_REGISTER)
12828         {
12829           /* None of this applies to the stack, frame or arg pointers.  */
12830           if (regno == STACK_POINTER_REGNUM
12831 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12832               || regno == HARD_FRAME_POINTER_REGNUM
12833 #endif
12834 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12835               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12836 #endif
12837               || regno == FRAME_POINTER_REGNUM)
12838             return;
12839
12840           add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12841         }
12842       return;
12843
12844     case SET:
12845       {
12846         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12847            the address.  */
12848         rtx testreg = SET_DEST (x);
12849
12850         while (GET_CODE (testreg) == SUBREG
12851                || GET_CODE (testreg) == ZERO_EXTRACT
12852                || GET_CODE (testreg) == STRICT_LOW_PART)
12853           testreg = XEXP (testreg, 0);
12854
12855         if (MEM_P (testreg))
12856           mark_used_regs_combine (XEXP (testreg, 0));
12857
12858         mark_used_regs_combine (SET_SRC (x));
12859       }
12860       return;
12861
12862     default:
12863       break;
12864     }
12865
12866   /* Recursively scan the operands of this expression.  */
12867
12868   {
12869     const char *fmt = GET_RTX_FORMAT (code);
12870
12871     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12872       {
12873         if (fmt[i] == 'e')
12874           mark_used_regs_combine (XEXP (x, i));
12875         else if (fmt[i] == 'E')
12876           {
12877             int j;
12878
12879             for (j = 0; j < XVECLEN (x, i); j++)
12880               mark_used_regs_combine (XVECEXP (x, i, j));
12881           }
12882       }
12883   }
12884 }
12885 \f
12886 /* Remove register number REGNO from the dead registers list of INSN.
12887
12888    Return the note used to record the death, if there was one.  */
12889
12890 rtx
12891 remove_death (unsigned int regno, rtx insn)
12892 {
12893   rtx note = find_regno_note (insn, REG_DEAD, regno);
12894
12895   if (note)
12896     remove_note (insn, note);
12897
12898   return note;
12899 }
12900
12901 /* For each register (hardware or pseudo) used within expression X, if its
12902    death is in an instruction with luid between FROM_LUID (inclusive) and
12903    TO_INSN (exclusive), put a REG_DEAD note for that register in the
12904    list headed by PNOTES.
12905
12906    That said, don't move registers killed by maybe_kill_insn.
12907
12908    This is done when X is being merged by combination into TO_INSN.  These
12909    notes will then be distributed as needed.  */
12910
12911 static void
12912 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12913              rtx *pnotes)
12914 {
12915   const char *fmt;
12916   int len, i;
12917   enum rtx_code code = GET_CODE (x);
12918
12919   if (code == REG)
12920     {
12921       unsigned int regno = REGNO (x);
12922       rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno).last_death;
12923
12924       /* Don't move the register if it gets killed in between from and to.  */
12925       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12926           && ! reg_referenced_p (x, maybe_kill_insn))
12927         return;
12928
12929       if (where_dead
12930           && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12931           && DF_INSN_LUID (where_dead) >= from_luid
12932           && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12933         {
12934           rtx note = remove_death (regno, where_dead);
12935
12936           /* It is possible for the call above to return 0.  This can occur
12937              when last_death points to I2 or I1 that we combined with.
12938              In that case make a new note.
12939
12940              We must also check for the case where X is a hard register
12941              and NOTE is a death note for a range of hard registers
12942              including X.  In that case, we must put REG_DEAD notes for
12943              the remaining registers in place of NOTE.  */
12944
12945           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12946               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12947                   > GET_MODE_SIZE (GET_MODE (x))))
12948             {
12949               unsigned int deadregno = REGNO (XEXP (note, 0));
12950               unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12951               unsigned int ourend = END_HARD_REGNO (x);
12952               unsigned int i;
12953
12954               for (i = deadregno; i < deadend; i++)
12955                 if (i < regno || i >= ourend)
12956                   add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12957             }
12958
12959           /* If we didn't find any note, or if we found a REG_DEAD note that
12960              covers only part of the given reg, and we have a multi-reg hard
12961              register, then to be safe we must check for REG_DEAD notes
12962              for each register other than the first.  They could have
12963              their own REG_DEAD notes lying around.  */
12964           else if ((note == 0
12965                     || (note != 0
12966                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12967                             < GET_MODE_SIZE (GET_MODE (x)))))
12968                    && regno < FIRST_PSEUDO_REGISTER
12969                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12970             {
12971               unsigned int ourend = END_HARD_REGNO (x);
12972               unsigned int i, offset;
12973               rtx oldnotes = 0;
12974
12975               if (note)
12976                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12977               else
12978                 offset = 1;
12979
12980               for (i = regno + offset; i < ourend; i++)
12981                 move_deaths (regno_reg_rtx[i],
12982                              maybe_kill_insn, from_luid, to_insn, &oldnotes);
12983             }
12984
12985           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12986             {
12987               XEXP (note, 1) = *pnotes;
12988               *pnotes = note;
12989             }
12990           else
12991             *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12992         }
12993
12994       return;
12995     }
12996
12997   else if (GET_CODE (x) == SET)
12998     {
12999       rtx dest = SET_DEST (x);
13000
13001       move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13002
13003       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13004          that accesses one word of a multi-word item, some
13005          piece of everything register in the expression is used by
13006          this insn, so remove any old death.  */
13007       /* ??? So why do we test for equality of the sizes?  */
13008
13009       if (GET_CODE (dest) == ZERO_EXTRACT
13010           || GET_CODE (dest) == STRICT_LOW_PART
13011           || (GET_CODE (dest) == SUBREG
13012               && (((GET_MODE_SIZE (GET_MODE (dest))
13013                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13014                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13015                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13016         {
13017           move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13018           return;
13019         }
13020
13021       /* If this is some other SUBREG, we know it replaces the entire
13022          value, so use that as the destination.  */
13023       if (GET_CODE (dest) == SUBREG)
13024         dest = SUBREG_REG (dest);
13025
13026       /* If this is a MEM, adjust deaths of anything used in the address.
13027          For a REG (the only other possibility), the entire value is
13028          being replaced so the old value is not used in this insn.  */
13029
13030       if (MEM_P (dest))
13031         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13032                      to_insn, pnotes);
13033       return;
13034     }
13035
13036   else if (GET_CODE (x) == CLOBBER)
13037     return;
13038
13039   len = GET_RTX_LENGTH (code);
13040   fmt = GET_RTX_FORMAT (code);
13041
13042   for (i = 0; i < len; i++)
13043     {
13044       if (fmt[i] == 'E')
13045         {
13046           int j;
13047           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13048             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13049                          to_insn, pnotes);
13050         }
13051       else if (fmt[i] == 'e')
13052         move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13053     }
13054 }
13055 \f
13056 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13057    pattern of an insn.  X must be a REG.  */
13058
13059 static int
13060 reg_bitfield_target_p (rtx x, rtx body)
13061 {
13062   int i;
13063
13064   if (GET_CODE (body) == SET)
13065     {
13066       rtx dest = SET_DEST (body);
13067       rtx target;
13068       unsigned int regno, tregno, endregno, endtregno;
13069
13070       if (GET_CODE (dest) == ZERO_EXTRACT)
13071         target = XEXP (dest, 0);
13072       else if (GET_CODE (dest) == STRICT_LOW_PART)
13073         target = SUBREG_REG (XEXP (dest, 0));
13074       else
13075         return 0;
13076
13077       if (GET_CODE (target) == SUBREG)
13078         target = SUBREG_REG (target);
13079
13080       if (!REG_P (target))
13081         return 0;
13082
13083       tregno = REGNO (target), regno = REGNO (x);
13084       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13085         return target == x;
13086
13087       endtregno = end_hard_regno (GET_MODE (target), tregno);
13088       endregno = end_hard_regno (GET_MODE (x), regno);
13089
13090       return endregno > tregno && regno < endtregno;
13091     }
13092
13093   else if (GET_CODE (body) == PARALLEL)
13094     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13095       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13096         return 1;
13097
13098   return 0;
13099 }
13100 \f
13101 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13102    as appropriate.  I3 and I2 are the insns resulting from the combination
13103    insns including FROM (I2 may be zero).
13104
13105    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13106    not need REG_DEAD notes because they are being substituted for.  This
13107    saves searching in the most common cases.
13108
13109    Each note in the list is either ignored or placed on some insns, depending
13110    on the type of note.  */
13111
13112 static void
13113 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13114                   rtx elim_i1, rtx elim_i0)
13115 {
13116   rtx note, next_note;
13117   rtx tem;
13118
13119   for (note = notes; note; note = next_note)
13120     {
13121       rtx place = 0, place2 = 0;
13122
13123       next_note = XEXP (note, 1);
13124       switch (REG_NOTE_KIND (note))
13125         {
13126         case REG_BR_PROB:
13127         case REG_BR_PRED:
13128           /* Doesn't matter much where we put this, as long as it's somewhere.
13129              It is preferable to keep these notes on branches, which is most
13130              likely to be i3.  */
13131           place = i3;
13132           break;
13133
13134         case REG_NON_LOCAL_GOTO:
13135           if (JUMP_P (i3))
13136             place = i3;
13137           else
13138             {
13139               gcc_assert (i2 && JUMP_P (i2));
13140               place = i2;
13141             }
13142           break;
13143
13144         case REG_EH_REGION:
13145           /* These notes must remain with the call or trapping instruction.  */
13146           if (CALL_P (i3))
13147             place = i3;
13148           else if (i2 && CALL_P (i2))
13149             place = i2;
13150           else
13151             {
13152               gcc_assert (cfun->can_throw_non_call_exceptions);
13153               if (may_trap_p (i3))
13154                 place = i3;
13155               else if (i2 && may_trap_p (i2))
13156                 place = i2;
13157               /* ??? Otherwise assume we've combined things such that we
13158                  can now prove that the instructions can't trap.  Drop the
13159                  note in this case.  */
13160             }
13161           break;
13162
13163         case REG_ARGS_SIZE:
13164           /* ??? How to distribute between i3-i1.  Assume i3 contains the
13165              entire adjustment.  Assert i3 contains at least some adjust.  */
13166           if (!noop_move_p (i3))
13167             {
13168               int old_size, args_size = INTVAL (XEXP (note, 0));
13169               /* fixup_args_size_notes looks at REG_NORETURN note,
13170                  so ensure the note is placed there first.  */
13171               if (CALL_P (i3))
13172                 {
13173                   rtx *np;
13174                   for (np = &next_note; *np; np = &XEXP (*np, 1))
13175                     if (REG_NOTE_KIND (*np) == REG_NORETURN)
13176                       {
13177                         rtx n = *np;
13178                         *np = XEXP (n, 1);
13179                         XEXP (n, 1) = REG_NOTES (i3);
13180                         REG_NOTES (i3) = n;
13181                         break;
13182                       }
13183                 }
13184               old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13185               /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13186                  REG_ARGS_SIZE note to all noreturn calls, allow that here.  */
13187               gcc_assert (old_size != args_size
13188                           || (CALL_P (i3)
13189                               && !ACCUMULATE_OUTGOING_ARGS
13190                               && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13191             }
13192           break;
13193
13194         case REG_NORETURN:
13195         case REG_SETJMP:
13196         case REG_TM:
13197           /* These notes must remain with the call.  It should not be
13198              possible for both I2 and I3 to be a call.  */
13199           if (CALL_P (i3))
13200             place = i3;
13201           else
13202             {
13203               gcc_assert (i2 && CALL_P (i2));
13204               place = i2;
13205             }
13206           break;
13207
13208         case REG_UNUSED:
13209           /* Any clobbers for i3 may still exist, and so we must process
13210              REG_UNUSED notes from that insn.
13211
13212              Any clobbers from i2 or i1 can only exist if they were added by
13213              recog_for_combine.  In that case, recog_for_combine created the
13214              necessary REG_UNUSED notes.  Trying to keep any original
13215              REG_UNUSED notes from these insns can cause incorrect output
13216              if it is for the same register as the original i3 dest.
13217              In that case, we will notice that the register is set in i3,
13218              and then add a REG_UNUSED note for the destination of i3, which
13219              is wrong.  However, it is possible to have REG_UNUSED notes from
13220              i2 or i1 for register which were both used and clobbered, so
13221              we keep notes from i2 or i1 if they will turn into REG_DEAD
13222              notes.  */
13223
13224           /* If this register is set or clobbered in I3, put the note there
13225              unless there is one already.  */
13226           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13227             {
13228               if (from_insn != i3)
13229                 break;
13230
13231               if (! (REG_P (XEXP (note, 0))
13232                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13233                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13234                 place = i3;
13235             }
13236           /* Otherwise, if this register is used by I3, then this register
13237              now dies here, so we must put a REG_DEAD note here unless there
13238              is one already.  */
13239           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13240                    && ! (REG_P (XEXP (note, 0))
13241                          ? find_regno_note (i3, REG_DEAD,
13242                                             REGNO (XEXP (note, 0)))
13243                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13244             {
13245               PUT_REG_NOTE_KIND (note, REG_DEAD);
13246               place = i3;
13247             }
13248           break;
13249
13250         case REG_EQUAL:
13251         case REG_EQUIV:
13252         case REG_NOALIAS:
13253           /* These notes say something about results of an insn.  We can
13254              only support them if they used to be on I3 in which case they
13255              remain on I3.  Otherwise they are ignored.
13256
13257              If the note refers to an expression that is not a constant, we
13258              must also ignore the note since we cannot tell whether the
13259              equivalence is still true.  It might be possible to do
13260              slightly better than this (we only have a problem if I2DEST
13261              or I1DEST is present in the expression), but it doesn't
13262              seem worth the trouble.  */
13263
13264           if (from_insn == i3
13265               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13266             place = i3;
13267           break;
13268
13269         case REG_INC:
13270           /* These notes say something about how a register is used.  They must
13271              be present on any use of the register in I2 or I3.  */
13272           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13273             place = i3;
13274
13275           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13276             {
13277               if (place)
13278                 place2 = i2;
13279               else
13280                 place = i2;
13281             }
13282           break;
13283
13284         case REG_LABEL_TARGET:
13285         case REG_LABEL_OPERAND:
13286           /* This can show up in several ways -- either directly in the
13287              pattern, or hidden off in the constant pool with (or without?)
13288              a REG_EQUAL note.  */
13289           /* ??? Ignore the without-reg_equal-note problem for now.  */
13290           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13291               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13292                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13293                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13294             place = i3;
13295
13296           if (i2
13297               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13298                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13299                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13300                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13301             {
13302               if (place)
13303                 place2 = i2;
13304               else
13305                 place = i2;
13306             }
13307
13308           /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13309              as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13310              there.  */
13311           if (place && JUMP_P (place)
13312               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13313               && (JUMP_LABEL (place) == NULL
13314                   || JUMP_LABEL (place) == XEXP (note, 0)))
13315             {
13316               rtx label = JUMP_LABEL (place);
13317
13318               if (!label)
13319                 JUMP_LABEL (place) = XEXP (note, 0);
13320               else if (LABEL_P (label))
13321                 LABEL_NUSES (label)--;
13322             }
13323
13324           if (place2 && JUMP_P (place2)
13325               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13326               && (JUMP_LABEL (place2) == NULL
13327                   || JUMP_LABEL (place2) == XEXP (note, 0)))
13328             {
13329               rtx label = JUMP_LABEL (place2);
13330
13331               if (!label)
13332                 JUMP_LABEL (place2) = XEXP (note, 0);
13333               else if (LABEL_P (label))
13334                 LABEL_NUSES (label)--;
13335               place2 = 0;
13336             }
13337           break;
13338
13339         case REG_NONNEG:
13340           /* This note says something about the value of a register prior
13341              to the execution of an insn.  It is too much trouble to see
13342              if the note is still correct in all situations.  It is better
13343              to simply delete it.  */
13344           break;
13345
13346         case REG_DEAD:
13347           /* If we replaced the right hand side of FROM_INSN with a
13348              REG_EQUAL note, the original use of the dying register
13349              will not have been combined into I3 and I2.  In such cases,
13350              FROM_INSN is guaranteed to be the first of the combined
13351              instructions, so we simply need to search back before
13352              FROM_INSN for the previous use or set of this register,
13353              then alter the notes there appropriately.
13354
13355              If the register is used as an input in I3, it dies there.
13356              Similarly for I2, if it is nonzero and adjacent to I3.
13357
13358              If the register is not used as an input in either I3 or I2
13359              and it is not one of the registers we were supposed to eliminate,
13360              there are two possibilities.  We might have a non-adjacent I2
13361              or we might have somehow eliminated an additional register
13362              from a computation.  For example, we might have had A & B where
13363              we discover that B will always be zero.  In this case we will
13364              eliminate the reference to A.
13365
13366              In both cases, we must search to see if we can find a previous
13367              use of A and put the death note there.  */
13368
13369           if (from_insn
13370               && from_insn == i2mod
13371               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13372             tem = from_insn;
13373           else
13374             {
13375               if (from_insn
13376                   && CALL_P (from_insn)
13377                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13378                 place = from_insn;
13379               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13380                 place = i3;
13381               else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13382                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13383                 place = i2;
13384               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13385                         && !(i2mod
13386                              && reg_overlap_mentioned_p (XEXP (note, 0),
13387                                                          i2mod_old_rhs)))
13388                        || rtx_equal_p (XEXP (note, 0), elim_i1)
13389                        || rtx_equal_p (XEXP (note, 0), elim_i0))
13390                 break;
13391               tem = i3;
13392             }
13393
13394           if (place == 0)
13395             {
13396               basic_block bb = this_basic_block;
13397
13398               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13399                 {
13400                   if (!NONDEBUG_INSN_P (tem))
13401                     {
13402                       if (tem == BB_HEAD (bb))
13403                         break;
13404                       continue;
13405                     }
13406
13407                   /* If the register is being set at TEM, see if that is all
13408                      TEM is doing.  If so, delete TEM.  Otherwise, make this
13409                      into a REG_UNUSED note instead. Don't delete sets to
13410                      global register vars.  */
13411                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13412                        || !global_regs[REGNO (XEXP (note, 0))])
13413                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13414                     {
13415                       rtx set = single_set (tem);
13416                       rtx inner_dest = 0;
13417 #ifdef HAVE_cc0
13418                       rtx cc0_setter = NULL_RTX;
13419 #endif
13420
13421                       if (set != 0)
13422                         for (inner_dest = SET_DEST (set);
13423                              (GET_CODE (inner_dest) == STRICT_LOW_PART
13424                               || GET_CODE (inner_dest) == SUBREG
13425                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
13426                              inner_dest = XEXP (inner_dest, 0))
13427                           ;
13428
13429                       /* Verify that it was the set, and not a clobber that
13430                          modified the register.
13431
13432                          CC0 targets must be careful to maintain setter/user
13433                          pairs.  If we cannot delete the setter due to side
13434                          effects, mark the user with an UNUSED note instead
13435                          of deleting it.  */
13436
13437                       if (set != 0 && ! side_effects_p (SET_SRC (set))
13438                           && rtx_equal_p (XEXP (note, 0), inner_dest)
13439 #ifdef HAVE_cc0
13440                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13441                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13442                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13443 #endif
13444                           )
13445                         {
13446                           /* Move the notes and links of TEM elsewhere.
13447                              This might delete other dead insns recursively.
13448                              First set the pattern to something that won't use
13449                              any register.  */
13450                           rtx old_notes = REG_NOTES (tem);
13451
13452                           PATTERN (tem) = pc_rtx;
13453                           REG_NOTES (tem) = NULL;
13454
13455                           distribute_notes (old_notes, tem, tem, NULL_RTX,
13456                                             NULL_RTX, NULL_RTX, NULL_RTX);
13457                           distribute_links (LOG_LINKS (tem));
13458
13459                           SET_INSN_DELETED (tem);
13460                           if (tem == i2)
13461                             i2 = NULL_RTX;
13462
13463 #ifdef HAVE_cc0
13464                           /* Delete the setter too.  */
13465                           if (cc0_setter)
13466                             {
13467                               PATTERN (cc0_setter) = pc_rtx;
13468                               old_notes = REG_NOTES (cc0_setter);
13469                               REG_NOTES (cc0_setter) = NULL;
13470
13471                               distribute_notes (old_notes, cc0_setter,
13472                                                 cc0_setter, NULL_RTX,
13473                                                 NULL_RTX, NULL_RTX, NULL_RTX);
13474                               distribute_links (LOG_LINKS (cc0_setter));
13475
13476                               SET_INSN_DELETED (cc0_setter);
13477                               if (cc0_setter == i2)
13478                                 i2 = NULL_RTX;
13479                             }
13480 #endif
13481                         }
13482                       else
13483                         {
13484                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
13485
13486                           /*  If there isn't already a REG_UNUSED note, put one
13487                               here.  Do not place a REG_DEAD note, even if
13488                               the register is also used here; that would not
13489                               match the algorithm used in lifetime analysis
13490                               and can cause the consistency check in the
13491                               scheduler to fail.  */
13492                           if (! find_regno_note (tem, REG_UNUSED,
13493                                                  REGNO (XEXP (note, 0))))
13494                             place = tem;
13495                           break;
13496                         }
13497                     }
13498                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13499                            || (CALL_P (tem)
13500                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
13501                     {
13502                       place = tem;
13503
13504                       /* If we are doing a 3->2 combination, and we have a
13505                          register which formerly died in i3 and was not used
13506                          by i2, which now no longer dies in i3 and is used in
13507                          i2 but does not die in i2, and place is between i2
13508                          and i3, then we may need to move a link from place to
13509                          i2.  */
13510                       if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13511                           && from_insn
13512                           && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13513                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13514                         {
13515                           struct insn_link *links = LOG_LINKS (place);
13516                           LOG_LINKS (place) = NULL;
13517                           distribute_links (links);
13518                         }
13519                       break;
13520                     }
13521
13522                   if (tem == BB_HEAD (bb))
13523                     break;
13524                 }
13525
13526             }
13527
13528           /* If the register is set or already dead at PLACE, we needn't do
13529              anything with this note if it is still a REG_DEAD note.
13530              We check here if it is set at all, not if is it totally replaced,
13531              which is what `dead_or_set_p' checks, so also check for it being
13532              set partially.  */
13533
13534           if (place && REG_NOTE_KIND (note) == REG_DEAD)
13535             {
13536               unsigned int regno = REGNO (XEXP (note, 0));
13537               reg_stat_type *rsp = &VEC_index (reg_stat_type, reg_stat, regno);
13538
13539               if (dead_or_set_p (place, XEXP (note, 0))
13540                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13541                 {
13542                   /* Unless the register previously died in PLACE, clear
13543                      last_death.  [I no longer understand why this is
13544                      being done.] */
13545                   if (rsp->last_death != place)
13546                     rsp->last_death = 0;
13547                   place = 0;
13548                 }
13549               else
13550                 rsp->last_death = place;
13551
13552               /* If this is a death note for a hard reg that is occupying
13553                  multiple registers, ensure that we are still using all
13554                  parts of the object.  If we find a piece of the object
13555                  that is unused, we must arrange for an appropriate REG_DEAD
13556                  note to be added for it.  However, we can't just emit a USE
13557                  and tag the note to it, since the register might actually
13558                  be dead; so we recourse, and the recursive call then finds
13559                  the previous insn that used this register.  */
13560
13561               if (place && regno < FIRST_PSEUDO_REGISTER
13562                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13563                 {
13564                   unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13565                   int all_used = 1;
13566                   unsigned int i;
13567
13568                   for (i = regno; i < endregno; i++)
13569                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13570                          && ! find_regno_fusage (place, USE, i))
13571                         || dead_or_set_regno_p (place, i))
13572                       all_used = 0;
13573
13574                   if (! all_used)
13575                     {
13576                       /* Put only REG_DEAD notes for pieces that are
13577                          not already dead or set.  */
13578
13579                       for (i = regno; i < endregno;
13580                            i += hard_regno_nregs[i][reg_raw_mode[i]])
13581                         {
13582                           rtx piece = regno_reg_rtx[i];
13583                           basic_block bb = this_basic_block;
13584
13585                           if (! dead_or_set_p (place, piece)
13586                               && ! reg_bitfield_target_p (piece,
13587                                                           PATTERN (place)))
13588                             {
13589                               rtx new_note = alloc_reg_note (REG_DEAD, piece,
13590                                                              NULL_RTX);
13591
13592                               distribute_notes (new_note, place, place,
13593                                                 NULL_RTX, NULL_RTX, NULL_RTX,
13594                                                 NULL_RTX);
13595                             }
13596                           else if (! refers_to_regno_p (i, i + 1,
13597                                                         PATTERN (place), 0)
13598                                    && ! find_regno_fusage (place, USE, i))
13599                             for (tem = PREV_INSN (place); ;
13600                                  tem = PREV_INSN (tem))
13601                               {
13602                                 if (!NONDEBUG_INSN_P (tem))
13603                                   {
13604                                     if (tem == BB_HEAD (bb))
13605                                       break;
13606                                     continue;
13607                                   }
13608                                 if (dead_or_set_p (tem, piece)
13609                                     || reg_bitfield_target_p (piece,
13610                                                               PATTERN (tem)))
13611                                   {
13612                                     add_reg_note (tem, REG_UNUSED, piece);
13613                                     break;
13614                                   }
13615                               }
13616
13617                         }
13618
13619                       place = 0;
13620                     }
13621                 }
13622             }
13623           break;
13624
13625         default:
13626           /* Any other notes should not be present at this point in the
13627              compilation.  */
13628           gcc_unreachable ();
13629         }
13630
13631       if (place)
13632         {
13633           XEXP (note, 1) = REG_NOTES (place);
13634           REG_NOTES (place) = note;
13635         }
13636
13637       if (place2)
13638         add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13639     }
13640 }
13641 \f
13642 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13643    I3, I2, and I1 to new locations.  This is also called to add a link
13644    pointing at I3 when I3's destination is changed.  */
13645
13646 static void
13647 distribute_links (struct insn_link *links)
13648 {
13649   struct insn_link *link, *next_link;
13650
13651   for (link = links; link; link = next_link)
13652     {
13653       rtx place = 0;
13654       rtx insn;
13655       rtx set, reg;
13656
13657       next_link = link->next;
13658
13659       /* If the insn that this link points to is a NOTE or isn't a single
13660          set, ignore it.  In the latter case, it isn't clear what we
13661          can do other than ignore the link, since we can't tell which
13662          register it was for.  Such links wouldn't be used by combine
13663          anyway.
13664
13665          It is not possible for the destination of the target of the link to
13666          have been changed by combine.  The only potential of this is if we
13667          replace I3, I2, and I1 by I3 and I2.  But in that case the
13668          destination of I2 also remains unchanged.  */
13669
13670       if (NOTE_P (link->insn)
13671           || (set = single_set (link->insn)) == 0)
13672         continue;
13673
13674       reg = SET_DEST (set);
13675       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13676              || GET_CODE (reg) == STRICT_LOW_PART)
13677         reg = XEXP (reg, 0);
13678
13679       /* A LOG_LINK is defined as being placed on the first insn that uses
13680          a register and points to the insn that sets the register.  Start
13681          searching at the next insn after the target of the link and stop
13682          when we reach a set of the register or the end of the basic block.
13683
13684          Note that this correctly handles the link that used to point from
13685          I3 to I2.  Also note that not much searching is typically done here
13686          since most links don't point very far away.  */
13687
13688       for (insn = NEXT_INSN (link->insn);
13689            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13690                      || BB_HEAD (this_basic_block->next_bb) != insn));
13691            insn = NEXT_INSN (insn))
13692         if (DEBUG_INSN_P (insn))
13693           continue;
13694         else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13695           {
13696             if (reg_referenced_p (reg, PATTERN (insn)))
13697               place = insn;
13698             break;
13699           }
13700         else if (CALL_P (insn)
13701                  && find_reg_fusage (insn, USE, reg))
13702           {
13703             place = insn;
13704             break;
13705           }
13706         else if (INSN_P (insn) && reg_set_p (reg, insn))
13707           break;
13708
13709       /* If we found a place to put the link, place it there unless there
13710          is already a link to the same insn as LINK at that point.  */
13711
13712       if (place)
13713         {
13714           struct insn_link *link2;
13715
13716           FOR_EACH_LOG_LINK (link2, place)
13717             if (link2->insn == link->insn)
13718               break;
13719
13720           if (link2 == NULL)
13721             {
13722               link->next = LOG_LINKS (place);
13723               LOG_LINKS (place) = link;
13724
13725               /* Set added_links_insn to the earliest insn we added a
13726                  link to.  */
13727               if (added_links_insn == 0
13728                   || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13729                 added_links_insn = place;
13730             }
13731         }
13732     }
13733 }
13734 \f
13735 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13736    Check whether the expression pointer to by LOC is a register or
13737    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13738    Otherwise return zero.  */
13739
13740 static int
13741 unmentioned_reg_p_1 (rtx *loc, void *expr)
13742 {
13743   rtx x = *loc;
13744
13745   if (x != NULL_RTX
13746       && (REG_P (x) || MEM_P (x))
13747       && ! reg_mentioned_p (x, (rtx) expr))
13748     return 1;
13749   return 0;
13750 }
13751
13752 /* Check for any register or memory mentioned in EQUIV that is not
13753    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
13754    of EXPR where some registers may have been replaced by constants.  */
13755
13756 static bool
13757 unmentioned_reg_p (rtx equiv, rtx expr)
13758 {
13759   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13760 }
13761 \f
13762 DEBUG_FUNCTION void
13763 dump_combine_stats (FILE *file)
13764 {
13765   fprintf
13766     (file,
13767      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13768      combine_attempts, combine_merges, combine_extras, combine_successes);
13769 }
13770
13771 void
13772 dump_combine_total_stats (FILE *file)
13773 {
13774   fprintf
13775     (file,
13776      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13777      total_attempts, total_merges, total_extras, total_successes);
13778 }
13779 \f
13780 static bool
13781 gate_handle_combine (void)
13782 {
13783   return (optimize > 0);
13784 }
13785
13786 /* Try combining insns through substitution.  */
13787 static unsigned int
13788 rest_of_handle_combine (void)
13789 {
13790   int rebuild_jump_labels_after_combine;
13791
13792   df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13793   df_note_add_problem ();
13794   df_analyze ();
13795
13796   regstat_init_n_sets_and_refs ();
13797
13798   rebuild_jump_labels_after_combine
13799     = combine_instructions (get_insns (), max_reg_num ());
13800
13801   /* Combining insns may have turned an indirect jump into a
13802      direct jump.  Rebuild the JUMP_LABEL fields of jumping
13803      instructions.  */
13804   if (rebuild_jump_labels_after_combine)
13805     {
13806       timevar_push (TV_JUMP);
13807       rebuild_jump_labels (get_insns ());
13808       cleanup_cfg (0);
13809       timevar_pop (TV_JUMP);
13810     }
13811
13812   regstat_free_n_sets_and_refs ();
13813   return 0;
13814 }
13815
13816 struct rtl_opt_pass pass_combine =
13817 {
13818  {
13819   RTL_PASS,
13820   "combine",                            /* name */
13821   OPTGROUP_NONE,                        /* optinfo_flags */
13822   gate_handle_combine,                  /* gate */
13823   rest_of_handle_combine,               /* execute */
13824   NULL,                                 /* sub */
13825   NULL,                                 /* next */
13826   0,                                    /* static_pass_number */
13827   TV_COMBINE,                           /* tv_id */
13828   PROP_cfglayout,                       /* properties_required */
13829   0,                                    /* properties_provided */
13830   0,                                    /* properties_destroyed */
13831   0,                                    /* todo_flags_start */
13832   TODO_df_finish | TODO_verify_rtl_sharing |
13833   TODO_ggc_collect,                     /* todo_flags_finish */
13834  }
13835 };