1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
31 #include "hard-reg-set.h"
33 #include "basic-block.h"
36 #include "insn-config.h"
44 #ifndef REGISTER_MOVE_COST
45 #define REGISTER_MOVE_COST(m, x, y) 2
48 static void init_reg_sets_1
PARAMS ((void));
49 static void init_reg_modes
PARAMS ((void));
51 /* If we have auto-increment or auto-decrement and we can have secondary
52 reloads, we are not allowed to use classes requiring secondary
53 reloads for pseudos auto-incremented since reload can't handle it. */
56 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
57 #define FORBIDDEN_INC_DEC_CLASSES
61 /* Register tables used by many passes. */
63 /* Indexed by hard register number, contains 1 for registers
64 that are fixed use (stack pointer, pc, frame pointer, etc.).
65 These are the registers that cannot be used to allocate
66 a pseudo reg for general use. */
68 char fixed_regs
[FIRST_PSEUDO_REGISTER
];
70 /* Same info as a HARD_REG_SET. */
72 HARD_REG_SET fixed_reg_set
;
74 /* Data for initializing the above. */
76 static char initial_fixed_regs
[] = FIXED_REGISTERS
;
78 /* Indexed by hard register number, contains 1 for registers
79 that are fixed use or are clobbered by function calls.
80 These are the registers that cannot be used to allocate
81 a pseudo reg whose life crosses calls unless we are able
82 to save/restore them across the calls. */
84 char call_used_regs
[FIRST_PSEUDO_REGISTER
];
86 /* Same info as a HARD_REG_SET. */
88 HARD_REG_SET call_used_reg_set
;
90 /* HARD_REG_SET of registers we want to avoid caller saving. */
91 HARD_REG_SET losing_caller_save_reg_set
;
93 /* Data for initializing the above. */
95 static char initial_call_used_regs
[] = CALL_USED_REGISTERS
;
97 /* Indexed by hard register number, contains 1 for registers that are
98 fixed use or call used registers that cannot hold quantities across
99 calls even if we are willing to save and restore them. call fixed
100 registers are a subset of call used registers. */
102 char call_fixed_regs
[FIRST_PSEUDO_REGISTER
];
104 /* The same info as a HARD_REG_SET. */
106 HARD_REG_SET call_fixed_reg_set
;
108 /* Number of non-fixed registers. */
110 int n_non_fixed_regs
;
112 /* Indexed by hard register number, contains 1 for registers
113 that are being used for global register decls.
114 These must be exempt from ordinary flow analysis
115 and are also considered fixed. */
117 char global_regs
[FIRST_PSEUDO_REGISTER
];
119 /* Table of register numbers in the order in which to try to use them. */
120 #ifdef REG_ALLOC_ORDER
121 int reg_alloc_order
[FIRST_PSEUDO_REGISTER
] = REG_ALLOC_ORDER
;
123 /* The inverse of reg_alloc_order. */
124 int inv_reg_alloc_order
[FIRST_PSEUDO_REGISTER
];
127 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
129 HARD_REG_SET reg_class_contents
[N_REG_CLASSES
];
131 /* The same information, but as an array of unsigned ints. We copy from
132 these unsigned ints to the table above. We do this so the tm.h files
133 do not have to be aware of the wordsize for machines with <= 64 regs. */
136 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
138 static unsigned int_reg_class_contents
[N_REG_CLASSES
][N_REG_INTS
]
139 = REG_CLASS_CONTENTS
;
141 /* For each reg class, number of regs it contains. */
143 unsigned int reg_class_size
[N_REG_CLASSES
];
145 /* For each reg class, table listing all the containing classes. */
147 enum reg_class reg_class_superclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
149 /* For each reg class, table listing all the classes contained in it. */
151 enum reg_class reg_class_subclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
153 /* For each pair of reg classes,
154 a largest reg class contained in their union. */
156 enum reg_class reg_class_subunion
[N_REG_CLASSES
][N_REG_CLASSES
];
158 /* For each pair of reg classes,
159 the smallest reg class containing their union. */
161 enum reg_class reg_class_superunion
[N_REG_CLASSES
][N_REG_CLASSES
];
163 /* Array containing all of the register names. Unless
164 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
166 #ifdef DEBUG_REGISTER_NAMES
167 const char * reg_names
[] = REGISTER_NAMES
;
170 /* For each hard register, the widest mode object that it can contain.
171 This will be a MODE_INT mode if the register can hold integers. Otherwise
172 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
175 enum machine_mode reg_raw_mode
[FIRST_PSEUDO_REGISTER
];
177 /* 1 if class does contain register of given mode. */
179 static char contains_reg_of_mode
[N_REG_CLASSES
] [MAX_MACHINE_MODE
];
181 /* Maximum cost of moving from a register in one class to a register in
182 another class. Based on REGISTER_MOVE_COST. */
184 static int move_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
186 /* Similar, but here we don't have to move if the first index is a subset
187 of the second so in that case the cost is zero. */
189 static int may_move_in_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
191 /* Similar, but here we don't have to move if the first index is a superset
192 of the second so in that case the cost is zero. */
194 static int may_move_out_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
196 #ifdef FORBIDDEN_INC_DEC_CLASSES
198 /* These are the classes that regs which are auto-incremented or decremented
201 static int forbidden_inc_dec_class
[N_REG_CLASSES
];
203 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
206 static char *in_inc_dec
;
208 #endif /* FORBIDDEN_INC_DEC_CLASSES */
210 #ifdef CLASS_CANNOT_CHANGE_MODE
212 /* These are the classes containing only registers that can be used in
213 a SUBREG expression that changes the mode of the register in some
214 way that is illegal. */
216 static int class_can_change_mode
[N_REG_CLASSES
];
218 /* Registers, including pseudos, which change modes in some way that
221 static regset reg_changes_mode
;
223 #endif /* CLASS_CANNOT_CHANGE_MODE */
225 #ifdef HAVE_SECONDARY_RELOADS
227 /* Sample MEM values for use by memory_move_secondary_cost. */
229 static rtx top_of_stack
[MAX_MACHINE_MODE
];
231 #endif /* HAVE_SECONDARY_RELOADS */
233 /* Linked list of reg_info structures allocated for reg_n_info array.
234 Grouping all of the allocated structures together in one lump
235 means only one call to bzero to clear them, rather than n smaller
237 struct reg_info_data
{
238 struct reg_info_data
*next
; /* next set of reg_info structures */
239 size_t min_index
; /* minimum index # */
240 size_t max_index
; /* maximum index # */
241 char used_p
; /* non-zero if this has been used previously */
242 reg_info data
[1]; /* beginning of the reg_info data */
245 static struct reg_info_data
*reg_info_head
;
247 /* No more global register variables may be declared; true once
248 regclass has been initialized. */
250 static int no_global_reg_vars
= 0;
253 /* Function called only once to initialize the above data on reg usage.
254 Once this is done, various switches may override. */
261 /* First copy the register information from the initial int form into
264 for (i
= 0; i
< N_REG_CLASSES
; i
++)
266 CLEAR_HARD_REG_SET (reg_class_contents
[i
]);
268 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
269 if (int_reg_class_contents
[i
][j
/ HOST_BITS_PER_INT
]
270 & ((unsigned) 1 << (j
% HOST_BITS_PER_INT
)))
271 SET_HARD_REG_BIT (reg_class_contents
[i
], j
);
274 memcpy (fixed_regs
, initial_fixed_regs
, sizeof fixed_regs
);
275 memcpy (call_used_regs
, initial_call_used_regs
, sizeof call_used_regs
);
276 memset (global_regs
, 0, sizeof global_regs
);
278 /* Do any additional initialization regsets may need */
279 INIT_ONCE_REG_SET ();
281 #ifdef REG_ALLOC_ORDER
282 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
283 inv_reg_alloc_order
[reg_alloc_order
[i
]] = i
;
287 /* After switches have been processed, which perhaps alter
288 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
293 register unsigned int i
, j
;
294 register unsigned int /* enum machine_mode */ m
;
295 char allocatable_regs_of_mode
[MAX_MACHINE_MODE
];
297 /* This macro allows the fixed or call-used registers
298 and the register classes to depend on target flags. */
300 #ifdef CONDITIONAL_REGISTER_USAGE
301 CONDITIONAL_REGISTER_USAGE
;
304 /* Compute number of hard regs in each class. */
306 memset ((char *) reg_class_size
, 0, sizeof reg_class_size
);
307 for (i
= 0; i
< N_REG_CLASSES
; i
++)
308 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
309 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
312 /* Initialize the table of subunions.
313 reg_class_subunion[I][J] gets the largest-numbered reg-class
314 that is contained in the union of classes I and J. */
316 for (i
= 0; i
< N_REG_CLASSES
; i
++)
318 for (j
= 0; j
< N_REG_CLASSES
; j
++)
321 register /* Declare it register if it's a scalar. */
326 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
327 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
328 for (k
= 0; k
< N_REG_CLASSES
; k
++)
330 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
], c
,
335 /* keep the largest subclass */ /* SPEE 900308 */
336 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
],
337 reg_class_contents
[(int) reg_class_subunion
[i
][j
]],
339 reg_class_subunion
[i
][j
] = (enum reg_class
) k
;
346 /* Initialize the table of superunions.
347 reg_class_superunion[I][J] gets the smallest-numbered reg-class
348 containing the union of classes I and J. */
350 for (i
= 0; i
< N_REG_CLASSES
; i
++)
352 for (j
= 0; j
< N_REG_CLASSES
; j
++)
355 register /* Declare it register if it's a scalar. */
360 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
361 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
362 for (k
= 0; k
< N_REG_CLASSES
; k
++)
363 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[k
], superclass
);
366 reg_class_superunion
[i
][j
] = (enum reg_class
) k
;
370 /* Initialize the tables of subclasses and superclasses of each reg class.
371 First clear the whole table, then add the elements as they are found. */
373 for (i
= 0; i
< N_REG_CLASSES
; i
++)
375 for (j
= 0; j
< N_REG_CLASSES
; j
++)
377 reg_class_superclasses
[i
][j
] = LIM_REG_CLASSES
;
378 reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
382 for (i
= 0; i
< N_REG_CLASSES
; i
++)
384 if (i
== (int) NO_REGS
)
387 for (j
= i
+ 1; j
< N_REG_CLASSES
; j
++)
391 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], reg_class_contents
[j
],
395 /* Reg class I is a subclass of J.
396 Add J to the table of superclasses of I. */
397 p
= ®_class_superclasses
[i
][0];
398 while (*p
!= LIM_REG_CLASSES
) p
++;
399 *p
= (enum reg_class
) j
;
400 /* Add I to the table of superclasses of J. */
401 p
= ®_class_subclasses
[j
][0];
402 while (*p
!= LIM_REG_CLASSES
) p
++;
403 *p
= (enum reg_class
) i
;
407 /* Initialize "constant" tables. */
409 CLEAR_HARD_REG_SET (fixed_reg_set
);
410 CLEAR_HARD_REG_SET (call_used_reg_set
);
411 CLEAR_HARD_REG_SET (call_fixed_reg_set
);
413 memcpy (call_fixed_regs
, fixed_regs
, sizeof call_fixed_regs
);
415 n_non_fixed_regs
= 0;
417 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
420 SET_HARD_REG_BIT (fixed_reg_set
, i
);
424 if (call_used_regs
[i
])
425 SET_HARD_REG_BIT (call_used_reg_set
, i
);
426 if (call_fixed_regs
[i
])
427 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
428 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i
)))
429 SET_HARD_REG_BIT (losing_caller_save_reg_set
, i
);
431 memset (contains_reg_of_mode
, 0, sizeof (contains_reg_of_mode
));
432 memset (allocatable_regs_of_mode
, 0, sizeof (allocatable_regs_of_mode
));
433 for (m
= 0; m
< (unsigned int) MAX_MACHINE_MODE
; m
++)
434 for (i
= 0; i
< N_REG_CLASSES
; i
++)
435 if (CLASS_MAX_NREGS (i
, m
) <= reg_class_size
[i
])
436 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
437 if (!fixed_regs
[j
] && TEST_HARD_REG_BIT (reg_class_contents
[i
], j
)
438 && HARD_REGNO_MODE_OK (j
, m
))
440 contains_reg_of_mode
[i
][m
] = 1;
441 allocatable_regs_of_mode
[m
] = 1;
445 /* Initialize the move cost table. Find every subset of each class
446 and take the maximum cost of moving any subset to any other. */
448 for (m
= 0; m
< (unsigned int) MAX_MACHINE_MODE
; m
++)
449 if (allocatable_regs_of_mode
[m
])
451 for (i
= 0; i
< N_REG_CLASSES
; i
++)
452 if (contains_reg_of_mode
[i
][m
])
453 for (j
= 0; j
< N_REG_CLASSES
; j
++)
456 enum reg_class
*p1
, *p2
;
458 if (!contains_reg_of_mode
[j
][m
])
460 move_cost
[m
][i
][j
] = 65536;
461 may_move_in_cost
[m
][i
][j
] = 65536;
462 may_move_out_cost
[m
][i
][j
] = 65536;
466 cost
= i
== j
? 2 : REGISTER_MOVE_COST (m
, i
, j
);
468 for (p2
= ®_class_subclasses
[j
][0];
469 *p2
!= LIM_REG_CLASSES
;
471 if (*p2
!= i
&& contains_reg_of_mode
[*p2
][m
])
472 cost
= MAX (cost
, move_cost
[m
][i
][*p2
]);
474 for (p1
= ®_class_subclasses
[i
][0];
475 *p1
!= LIM_REG_CLASSES
;
477 if (*p1
!= j
&& contains_reg_of_mode
[*p1
][m
])
478 cost
= MAX (cost
, move_cost
[m
][*p1
][j
]);
480 move_cost
[m
][i
][j
] = cost
;
482 if (reg_class_subset_p (i
, j
))
483 may_move_in_cost
[m
][i
][j
] = 0;
485 may_move_in_cost
[m
][i
][j
] = cost
;
487 if (reg_class_subset_p (j
, i
))
488 may_move_out_cost
[m
][i
][j
] = 0;
490 may_move_out_cost
[m
][i
][j
] = cost
;
494 for (j
= 0; j
< N_REG_CLASSES
; j
++)
496 move_cost
[m
][i
][j
] = 65536;
497 may_move_in_cost
[m
][i
][j
] = 65536;
498 may_move_out_cost
[m
][i
][j
] = 65536;
502 #ifdef CLASS_CANNOT_CHANGE_MODE
505 COMPL_HARD_REG_SET (c
, reg_class_contents
[CLASS_CANNOT_CHANGE_MODE
]);
507 for (i
= 0; i
< N_REG_CLASSES
; i
++)
509 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], c
, ok_class
);
510 class_can_change_mode
[i
] = 0;
513 class_can_change_mode
[i
] = 1;
516 #endif /* CLASS_CANNOT_CHANGE_MODE */
519 /* Compute the table of register modes.
520 These values are used to record death information for individual registers
521 (as opposed to a multi-register mode). */
528 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
530 reg_raw_mode
[i
] = choose_hard_reg_mode (i
, 1);
532 /* If we couldn't find a valid mode, just use the previous mode.
533 ??? One situation in which we need to do this is on the mips where
534 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
535 to use DF mode for the even registers and VOIDmode for the odd
536 (for the cpu models where the odd ones are inaccessible). */
537 if (reg_raw_mode
[i
] == VOIDmode
)
538 reg_raw_mode
[i
] = i
== 0 ? word_mode
: reg_raw_mode
[i
-1];
542 /* Finish initializing the register sets and
543 initialize the register modes. */
548 /* This finishes what was started by init_reg_sets, but couldn't be done
549 until after register usage was specified. */
554 #ifdef HAVE_SECONDARY_RELOADS
556 /* Make some fake stack-frame MEM references for use in
557 memory_move_secondary_cost. */
560 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
561 top_of_stack
[i
] = gen_rtx_MEM (i
, stack_pointer_rtx
);
562 ggc_add_rtx_root (top_of_stack
, MAX_MACHINE_MODE
);
567 #ifdef HAVE_SECONDARY_RELOADS
569 /* Compute extra cost of moving registers to/from memory due to reloads.
570 Only needed if secondary reloads are required for memory moves. */
573 memory_move_secondary_cost (mode
, class, in
)
574 enum machine_mode mode
;
575 enum reg_class
class;
578 enum reg_class altclass
;
579 int partial_cost
= 0;
580 /* We need a memory reference to feed to SECONDARY... macros. */
581 /* mem may be unused even if the SECONDARY_ macros are defined. */
582 rtx mem ATTRIBUTE_UNUSED
= top_of_stack
[(int) mode
];
587 #ifdef SECONDARY_INPUT_RELOAD_CLASS
588 altclass
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, mem
);
595 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
596 altclass
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, mem
);
602 if (altclass
== NO_REGS
)
606 partial_cost
= REGISTER_MOVE_COST (mode
, altclass
, class);
608 partial_cost
= REGISTER_MOVE_COST (mode
, class, altclass
);
610 if (class == altclass
)
611 /* This isn't simply a copy-to-temporary situation. Can't guess
612 what it is, so MEMORY_MOVE_COST really ought not to be calling
615 I'm tempted to put in an abort here, but returning this will
616 probably only give poor estimates, which is what we would've
617 had before this code anyways. */
620 /* Check if the secondary reload register will also need a
622 return memory_move_secondary_cost (mode
, altclass
, in
) + partial_cost
;
626 /* Return a machine mode that is legitimate for hard reg REGNO and large
627 enough to save nregs. If we can't find one, return VOIDmode. */
630 choose_hard_reg_mode (regno
, nregs
)
631 unsigned int regno ATTRIBUTE_UNUSED
;
634 unsigned int /* enum machine_mode */ m
;
635 enum machine_mode found_mode
= VOIDmode
, mode
;
637 /* We first look for the largest integer mode that can be validly
638 held in REGNO. If none, we look for the largest floating-point mode.
639 If we still didn't find a valid mode, try CCmode. */
641 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
643 mode
= GET_MODE_WIDER_MODE (mode
))
644 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
645 && HARD_REGNO_MODE_OK (regno
, mode
))
648 if (found_mode
!= VOIDmode
)
651 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FLOAT
);
653 mode
= GET_MODE_WIDER_MODE (mode
))
654 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
655 && HARD_REGNO_MODE_OK (regno
, mode
))
658 if (found_mode
!= VOIDmode
)
661 /* Iterate over all of the CCmodes. */
662 for (m
= (unsigned int) CCmode
; m
< (unsigned int) NUM_MACHINE_MODES
; ++m
)
664 mode
= (enum machine_mode
) m
;
665 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
666 && HARD_REGNO_MODE_OK (regno
, mode
))
670 /* We can't find a mode valid for this register. */
674 /* Specify the usage characteristics of the register named NAME.
675 It should be a fixed register if FIXED and a
676 call-used register if CALL_USED. */
679 fix_register (name
, fixed
, call_used
)
681 int fixed
, call_used
;
685 /* Decode the name and update the primary form of
686 the register info. */
688 if ((i
= decode_reg_name (name
)) >= 0)
690 if ((i
== STACK_POINTER_REGNUM
691 #ifdef HARD_FRAME_POINTER_REGNUM
692 || i
== HARD_FRAME_POINTER_REGNUM
694 || i
== FRAME_POINTER_REGNUM
697 && (fixed
== 0 || call_used
== 0))
699 static const char * const what_option
[2][2] = {
700 { "call-saved", "call-used" },
701 { "no-such-option", "fixed" }};
703 error ("can't use '%s' as a %s register", name
,
704 what_option
[fixed
][call_used
]);
708 fixed_regs
[i
] = fixed
;
709 call_used_regs
[i
] = call_used
;
714 warning ("unknown register name: %s", name
);
718 /* Mark register number I as global. */
724 if (fixed_regs
[i
] == 0 && no_global_reg_vars
)
725 error ("global register variable follows a function definition");
729 warning ("register used for two global register variables");
733 if (call_used_regs
[i
] && ! fixed_regs
[i
])
734 warning ("call-clobbered register used for global register variable");
738 /* If already fixed, nothing else to do. */
742 fixed_regs
[i
] = call_used_regs
[i
] = call_fixed_regs
[i
] = 1;
745 SET_HARD_REG_BIT (fixed_reg_set
, i
);
746 SET_HARD_REG_BIT (call_used_reg_set
, i
);
747 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
750 /* Now the data and code for the `regclass' pass, which happens
751 just before local-alloc. */
753 /* The `costs' struct records the cost of using a hard register of each class
754 and of using memory for each pseudo. We use this data to set up
755 register class preferences. */
759 int cost
[N_REG_CLASSES
];
763 /* Structure used to record preferrences of given pseudo. */
766 /* (enum reg_class) prefclass is the preferred class. */
769 /* altclass is a register class that we should use for allocating
770 pseudo if no register in the preferred class is available.
771 If no register in this class is available, memory is preferred.
773 It might appear to be more general to have a bitmask of classes here,
774 but since it is recommended that there be a class corresponding to the
775 union of most major pair of classes, that generality is not required. */
779 /* Record the cost of each class for each pseudo. */
781 static struct costs
*costs
;
783 /* Initialized once, and used to initialize cost values for each insn. */
785 static struct costs init_cost
;
787 /* Record preferrences of each pseudo.
788 This is available after `regclass' is run. */
790 static struct reg_pref
*reg_pref
;
792 /* Allocated buffers for reg_pref. */
794 static struct reg_pref
*reg_pref_buffer
;
796 /* Account for the fact that insns within a loop are executed very commonly,
797 but don't keep doing this as loops go too deep. */
799 static int loop_cost
;
801 static rtx scan_one_insn
PARAMS ((rtx
, int));
802 static void record_operand_costs
PARAMS ((rtx
, struct costs
*, struct reg_pref
*));
803 static void dump_regclass
PARAMS ((FILE *));
804 static void record_reg_classes
PARAMS ((int, int, rtx
*, enum machine_mode
*,
806 struct costs
*, struct reg_pref
*));
807 static int copy_cost
PARAMS ((rtx
, enum machine_mode
,
808 enum reg_class
, int));
809 static void record_address_regs
PARAMS ((rtx
, enum reg_class
, int));
810 #ifdef FORBIDDEN_INC_DEC_CLASSES
811 static int auto_inc_dec_reg_p
PARAMS ((rtx
, enum machine_mode
));
813 static void reg_scan_mark_refs
PARAMS ((rtx
, rtx
, int, unsigned int));
815 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
816 This function is sometimes called before the info has been computed.
817 When that happens, just return GENERAL_REGS, which is innocuous. */
820 reg_preferred_class (regno
)
825 return (enum reg_class
) reg_pref
[regno
].prefclass
;
829 reg_alternate_class (regno
)
835 return (enum reg_class
) reg_pref
[regno
].altclass
;
838 /* Initialize some global data for this pass. */
845 init_cost
.mem_cost
= 10000;
846 for (i
= 0; i
< N_REG_CLASSES
; i
++)
847 init_cost
.cost
[i
] = 10000;
849 /* This prevents dump_flow_info from losing if called
850 before regclass is run. */
853 /* No more global register variables may be declared. */
854 no_global_reg_vars
= 1;
857 /* Dump register costs. */
862 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
864 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
866 int /* enum reg_class */ class;
869 fprintf (dump
, " Register %i costs:", i
);
870 for (class = 0; class < (int) N_REG_CLASSES
; class++)
871 if (contains_reg_of_mode
[(enum reg_class
) class][PSEUDO_REGNO_MODE (i
)]
872 #ifdef FORBIDDEN_INC_DEC_CLASSES
874 || !forbidden_inc_dec_class
[(enum reg_class
) class])
876 #ifdef CLASS_CANNOT_CHANGE_MODE
877 && (!REGNO_REG_SET_P (reg_changes_mode
, i
)
878 || class_can_change_mode
[(enum reg_class
) class])
881 fprintf (dump
, " %s:%i", reg_class_names
[class],
882 costs
[i
].cost
[(enum reg_class
) class]);
883 fprintf (dump
, " MEM:%i\n", costs
[i
].mem_cost
);
889 /* Calculate the costs of insn operands. */
892 record_operand_costs (insn
, op_costs
, reg_pref
)
894 struct costs
*op_costs
;
895 struct reg_pref
*reg_pref
;
897 const char *constraints
[MAX_RECOG_OPERANDS
];
898 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
901 for (i
= 0; i
< recog_data
.n_operands
; i
++)
903 constraints
[i
] = recog_data
.constraints
[i
];
904 modes
[i
] = recog_data
.operand_mode
[i
];
907 /* If we get here, we are set up to record the costs of all the
908 operands for this insn. Start by initializing the costs.
909 Then handle any address registers. Finally record the desired
910 classes for any pseudos, doing it twice if some pair of
911 operands are commutative. */
913 for (i
= 0; i
< recog_data
.n_operands
; i
++)
915 op_costs
[i
] = init_cost
;
917 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
919 rtx inner
= SUBREG_REG (recog_data
.operand
[i
]);
920 #ifdef CLASS_CANNOT_CHANGE_MODE
921 if (GET_CODE (inner
) == REG
922 && CLASS_CANNOT_CHANGE_MODE_P (modes
[i
], GET_MODE (inner
)))
923 SET_REGNO_REG_SET (reg_changes_mode
, REGNO (inner
));
925 recog_data
.operand
[i
] = inner
;
928 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
929 record_address_regs (XEXP (recog_data
.operand
[i
], 0),
930 BASE_REG_CLASS
, loop_cost
* 2);
931 else if (constraints
[i
][0] == 'p')
932 record_address_regs (recog_data
.operand
[i
],
933 BASE_REG_CLASS
, loop_cost
* 2);
936 /* Check for commutative in a separate loop so everything will
937 have been initialized. We must do this even if one operand
938 is a constant--see addsi3 in m68k.md. */
940 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
941 if (constraints
[i
][0] == '%')
943 const char *xconstraints
[MAX_RECOG_OPERANDS
];
946 /* Handle commutative operands by swapping the constraints.
947 We assume the modes are the same. */
949 for (j
= 0; j
< recog_data
.n_operands
; j
++)
950 xconstraints
[j
] = constraints
[j
];
952 xconstraints
[i
] = constraints
[i
+1];
953 xconstraints
[i
+1] = constraints
[i
];
954 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
955 recog_data
.operand
, modes
,
956 xconstraints
, insn
, op_costs
, reg_pref
);
959 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
960 recog_data
.operand
, modes
,
961 constraints
, insn
, op_costs
, reg_pref
);
964 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
965 time it would save code to put a certain register in a certain class.
966 PASS, when nonzero, inhibits some optimizations which need only be done
968 Return the last insn processed, so that the scan can be continued from
972 scan_one_insn (insn
, pass
)
976 enum rtx_code code
= GET_CODE (insn
);
977 enum rtx_code pat_code
;
980 struct costs op_costs
[MAX_RECOG_OPERANDS
];
982 if (GET_RTX_CLASS (code
) != 'i')
985 pat_code
= GET_CODE (PATTERN (insn
));
987 || pat_code
== CLOBBER
988 || pat_code
== ASM_INPUT
989 || pat_code
== ADDR_VEC
990 || pat_code
== ADDR_DIFF_VEC
)
993 set
= single_set (insn
);
996 /* If this insn loads a parameter from its stack slot, then
997 it represents a savings, rather than a cost, if the
998 parameter is stored in memory. Record this fact. */
1000 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
1001 && GET_CODE (SET_SRC (set
)) == MEM
1002 && (note
= find_reg_note (insn
, REG_EQUIV
,
1004 && GET_CODE (XEXP (note
, 0)) == MEM
)
1006 costs
[REGNO (SET_DEST (set
))].mem_cost
1007 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set
)),
1010 record_address_regs (XEXP (SET_SRC (set
), 0),
1011 BASE_REG_CLASS
, loop_cost
* 2);
1015 /* Improve handling of two-address insns such as
1016 (set X (ashift CONST Y)) where CONST must be made to
1017 match X. Change it into two insns: (set X CONST)
1018 (set X (ashift X Y)). If we left this for reloading, it
1019 would probably get three insns because X and Y might go
1020 in the same place. This prevents X and Y from receiving
1023 We can only do this if the modes of operands 0 and 1
1024 (which might not be the same) are tieable and we only need
1025 do this during our first pass. */
1027 if (pass
== 0 && optimize
1028 && recog_data
.n_operands
>= 3
1029 && recog_data
.constraints
[1][0] == '0'
1030 && recog_data
.constraints
[1][1] == 0
1031 && CONSTANT_P (recog_data
.operand
[1])
1032 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[1])
1033 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[2])
1034 && GET_CODE (recog_data
.operand
[0]) == REG
1035 && MODES_TIEABLE_P (GET_MODE (recog_data
.operand
[0]),
1036 recog_data
.operand_mode
[1]))
1038 rtx previnsn
= prev_real_insn (insn
);
1040 = gen_lowpart (recog_data
.operand_mode
[1],
1041 recog_data
.operand
[0]);
1043 = emit_insn_before (gen_move_insn (dest
, recog_data
.operand
[1]), insn
);
1045 /* If this insn was the start of a basic block,
1046 include the new insn in that block.
1047 We need not check for code_label here;
1048 while a basic block can start with a code_label,
1049 INSN could not be at the beginning of that block. */
1050 if (previnsn
== 0 || GET_CODE (previnsn
) == JUMP_INSN
)
1053 for (b
= 0; b
< n_basic_blocks
; b
++)
1054 if (insn
== BLOCK_HEAD (b
))
1055 BLOCK_HEAD (b
) = newinsn
;
1058 /* This makes one more setting of new insns's dest. */
1059 REG_N_SETS (REGNO (recog_data
.operand
[0]))++;
1060 REG_N_REFS (REGNO (recog_data
.operand
[0]))++;
1062 *recog_data
.operand_loc
[1] = recog_data
.operand
[0];
1063 REG_N_REFS (REGNO (recog_data
.operand
[0]))++;
1064 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
1065 if (recog_data
.dup_num
[i
] == 1)
1067 *recog_data
.dup_loc
[i
] = recog_data
.operand
[0];
1068 REG_N_REFS (REGNO (recog_data
.operand
[0]))++;
1071 return PREV_INSN (newinsn
);
1074 record_operand_costs (insn
, op_costs
, reg_pref
);
1076 /* Now add the cost for each operand to the total costs for
1079 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1080 if (GET_CODE (recog_data
.operand
[i
]) == REG
1081 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1083 int regno
= REGNO (recog_data
.operand
[i
]);
1084 struct costs
*p
= &costs
[regno
], *q
= &op_costs
[i
];
1086 p
->mem_cost
+= q
->mem_cost
* loop_cost
;
1087 for (j
= 0; j
< N_REG_CLASSES
; j
++)
1088 p
->cost
[j
] += q
->cost
[j
] * loop_cost
;
1094 /* This is a pass of the compiler that scans all instructions
1095 and calculates the preferred class for each pseudo-register.
1096 This information can be accessed later by calling `reg_preferred_class'.
1097 This pass comes just before local register allocation. */
1100 regclass (f
, nregs
, dump
)
1111 costs
= (struct costs
*) xmalloc (nregs
* sizeof (struct costs
));
1113 #ifdef CLASS_CANNOT_CHANGE_MODE
1114 reg_changes_mode
= BITMAP_XMALLOC();
1117 #ifdef FORBIDDEN_INC_DEC_CLASSES
1119 in_inc_dec
= (char *) xmalloc (nregs
);
1121 /* Initialize information about which register classes can be used for
1122 pseudos that are auto-incremented or auto-decremented. It would
1123 seem better to put this in init_reg_sets, but we need to be able
1124 to allocate rtx, which we can't do that early. */
1126 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1128 rtx r
= gen_rtx_REG (VOIDmode
, 0);
1129 enum machine_mode m
;
1132 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1133 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
1137 for (m
= VOIDmode
; (int) m
< (int) MAX_MACHINE_MODE
;
1138 m
= (enum machine_mode
) ((int) m
+ 1))
1139 if (HARD_REGNO_MODE_OK (j
, m
))
1143 /* If a register is not directly suitable for an
1144 auto-increment or decrement addressing mode and
1145 requires secondary reloads, disallow its class from
1146 being used in such addresses. */
1149 #ifdef SECONDARY_RELOAD_CLASS
1150 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1153 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1154 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1157 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1158 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1163 && ! auto_inc_dec_reg_p (r
, m
))
1164 forbidden_inc_dec_class
[i
] = 1;
1168 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1170 /* Normally we scan the insns once and determine the best class to use for
1171 each register. However, if -fexpensive_optimizations are on, we do so
1172 twice, the second time using the tentative best classes to guide the
1175 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
1180 fprintf (dump
, "\n\nPass %i\n\n",pass
);
1181 /* Zero out our accumulation of the cost of each class for each reg. */
1183 memset ((char *) costs
, 0, nregs
* sizeof (struct costs
));
1185 #ifdef FORBIDDEN_INC_DEC_CLASSES
1186 memset (in_inc_dec
, 0, nregs
);
1189 /* Scan the instructions and record each time it would
1190 save code to put a certain register in a certain class. */
1195 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
1196 insn
= scan_one_insn (insn
, pass
);
1199 for (index
= 0; index
< n_basic_blocks
; index
++)
1201 basic_block bb
= BASIC_BLOCK (index
);
1203 /* Show that an insn inside a loop is likely to be executed three
1204 times more than insns outside a loop. This is much more
1205 aggressive than the assumptions made elsewhere and is being
1206 tried as an experiment. */
1210 loop_cost
= 1 << (2 * MIN (bb
->loop_depth
, 5));
1211 for (insn
= bb
->head
; ; insn
= NEXT_INSN (insn
))
1213 insn
= scan_one_insn (insn
, pass
);
1214 if (insn
== bb
->end
)
1219 /* Now for each register look at how desirable each class is
1220 and find which class is preferred. Store that in
1221 `prefclass'. Record in `altclass' the largest register
1222 class any of whose registers is better than memory. */
1225 reg_pref
= reg_pref_buffer
;
1229 dump_regclass (dump
);
1230 fprintf (dump
,"\n");
1232 for (i
= FIRST_PSEUDO_REGISTER
; i
< nregs
; i
++)
1234 register int best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1235 enum reg_class best
= ALL_REGS
, alt
= NO_REGS
;
1236 /* This is an enum reg_class, but we call it an int
1237 to save lots of casts. */
1239 register struct costs
*p
= &costs
[i
];
1241 /* In non-optimizing compilation REG_N_REFS is not initialized
1243 if (optimize
&& !REG_N_REFS (i
))
1246 for (class = (int) ALL_REGS
- 1; class > 0; class--)
1248 /* Ignore classes that are too small for this operand or
1249 invalid for a operand that was auto-incremented. */
1250 if (!contains_reg_of_mode
[class][PSEUDO_REGNO_MODE (i
)]
1251 #ifdef FORBIDDEN_INC_DEC_CLASSES
1252 || (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1254 #ifdef CLASS_CANNOT_CHANGE_MODE
1255 || (REGNO_REG_SET_P (reg_changes_mode
, i
)
1256 && ! class_can_change_mode
[class])
1260 else if (p
->cost
[class] < best_cost
)
1262 best_cost
= p
->cost
[class];
1263 best
= (enum reg_class
) class;
1265 else if (p
->cost
[class] == best_cost
)
1266 best
= reg_class_subunion
[(int)best
][class];
1269 /* Record the alternate register class; i.e., a class for which
1270 every register in it is better than using memory. If adding a
1271 class would make a smaller class (i.e., no union of just those
1272 classes exists), skip that class. The major unions of classes
1273 should be provided as a register class. Don't do this if we
1274 will be doing it again later. */
1276 if ((pass
== 1 || dump
) || ! flag_expensive_optimizations
)
1277 for (class = 0; class < N_REG_CLASSES
; class++)
1278 if (p
->cost
[class] < p
->mem_cost
1279 && (reg_class_size
[(int) reg_class_subunion
[(int) alt
][class]]
1280 > reg_class_size
[(int) alt
])
1281 #ifdef FORBIDDEN_INC_DEC_CLASSES
1282 && ! (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1284 #ifdef CLASS_CANNOT_CHANGE_MODE
1285 && ! (REGNO_REG_SET_P (reg_changes_mode
, i
)
1286 && ! class_can_change_mode
[class])
1289 alt
= reg_class_subunion
[(int) alt
][class];
1291 /* If we don't add any classes, nothing to try. */
1296 && (reg_pref
[i
].prefclass
!= (int) best
1297 || reg_pref
[i
].altclass
!= (int) alt
))
1299 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1300 fprintf (dump
, " Register %i", i
);
1301 if (alt
== ALL_REGS
|| best
== ALL_REGS
)
1302 fprintf (dump
, " pref %s\n", reg_class_names
[(int) best
]);
1303 else if (alt
== NO_REGS
)
1304 fprintf (dump
, " pref %s or none\n", reg_class_names
[(int) best
]);
1306 fprintf (dump
, " pref %s, else %s\n",
1307 reg_class_names
[(int) best
],
1308 reg_class_names
[(int) alt
]);
1311 /* We cast to (int) because (char) hits bugs in some compilers. */
1312 reg_pref
[i
].prefclass
= (int) best
;
1313 reg_pref
[i
].altclass
= (int) alt
;
1317 #ifdef FORBIDDEN_INC_DEC_CLASSES
1320 #ifdef CLASS_CANNOT_CHANGE_MODE
1321 BITMAP_XFREE (reg_changes_mode
);
1326 /* Record the cost of using memory or registers of various classes for
1327 the operands in INSN.
1329 N_ALTS is the number of alternatives.
1331 N_OPS is the number of operands.
1333 OPS is an array of the operands.
1335 MODES are the modes of the operands, in case any are VOIDmode.
1337 CONSTRAINTS are the constraints to use for the operands. This array
1338 is modified by this procedure.
1340 This procedure works alternative by alternative. For each alternative
1341 we assume that we will be able to allocate all pseudos to their ideal
1342 register class and calculate the cost of using that alternative. Then
1343 we compute for each operand that is a pseudo-register, the cost of
1344 having the pseudo allocated to each register class and using it in that
1345 alternative. To this cost is added the cost of the alternative.
1347 The cost of each class for this insn is its lowest cost among all the
1351 record_reg_classes (n_alts
, n_ops
, ops
, modes
,
1352 constraints
, insn
, op_costs
, reg_pref
)
1356 enum machine_mode
*modes
;
1357 const char **constraints
;
1359 struct costs
*op_costs
;
1360 struct reg_pref
*reg_pref
;
1366 /* Process each alternative, each time minimizing an operand's cost with
1367 the cost for each operand in that alternative. */
1369 for (alt
= 0; alt
< n_alts
; alt
++)
1371 struct costs this_op_costs
[MAX_RECOG_OPERANDS
];
1374 enum reg_class classes
[MAX_RECOG_OPERANDS
];
1375 int allows_mem
[MAX_RECOG_OPERANDS
];
1378 for (i
= 0; i
< n_ops
; i
++)
1380 const char *p
= constraints
[i
];
1382 enum machine_mode mode
= modes
[i
];
1383 int allows_addr
= 0;
1387 /* Initially show we know nothing about the register class. */
1388 classes
[i
] = NO_REGS
;
1391 /* If this operand has no constraints at all, we can conclude
1392 nothing about it since anything is valid. */
1396 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1397 memset ((char *) &this_op_costs
[i
], 0, sizeof this_op_costs
[i
]);
1402 /* If this alternative is only relevant when this operand
1403 matches a previous operand, we do different things depending
1404 on whether this operand is a pseudo-reg or not. We must process
1405 any modifiers for the operand before we can make this test. */
1407 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
1410 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
1412 /* Copy class and whether memory is allowed from the matching
1413 alternative. Then perform any needed cost computations
1414 and/or adjustments. */
1416 classes
[i
] = classes
[j
];
1417 allows_mem
[i
] = allows_mem
[j
];
1419 if (GET_CODE (op
) != REG
|| REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1421 /* If this matches the other operand, we have no added
1423 if (rtx_equal_p (ops
[j
], op
))
1426 /* If we can put the other operand into a register, add to
1427 the cost of this alternative the cost to copy this
1428 operand to the register used for the other operand. */
1430 else if (classes
[j
] != NO_REGS
)
1431 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1), win
= 1;
1433 else if (GET_CODE (ops
[j
]) != REG
1434 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
1436 /* This op is a pseudo but the one it matches is not. */
1438 /* If we can't put the other operand into a register, this
1439 alternative can't be used. */
1441 if (classes
[j
] == NO_REGS
)
1444 /* Otherwise, add to the cost of this alternative the cost
1445 to copy the other operand to the register used for this
1449 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1);
1453 /* The costs of this operand are not the same as the other
1454 operand since move costs are not symmetric. Moreover,
1455 if we cannot tie them, this alternative needs to do a
1456 copy, which is one instruction. */
1458 struct costs
*pp
= &this_op_costs
[i
];
1460 for (class = 0; class < N_REG_CLASSES
; class++)
1462 = ((recog_data
.operand_type
[i
] != OP_OUT
1463 ? may_move_in_cost
[mode
][class][(int) classes
[i
]]
1465 + (recog_data
.operand_type
[i
] != OP_IN
1466 ? may_move_out_cost
[mode
][(int) classes
[i
]][class]
1469 /* If the alternative actually allows memory, make things
1470 a bit cheaper since we won't need an extra insn to
1474 = ((recog_data
.operand_type
[i
] != OP_IN
1475 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1477 + (recog_data
.operand_type
[i
] != OP_OUT
1478 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1479 : 0) - allows_mem
[i
]);
1481 /* If we have assigned a class to this register in our
1482 first pass, add a cost to this alternative corresponding
1483 to what we would add if this register were not in the
1484 appropriate class. */
1488 += (may_move_in_cost
[mode
]
1489 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1490 [(int) classes
[i
]]);
1492 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
1493 && ! find_reg_note (insn
, REG_DEAD
, op
))
1496 /* This is in place of ordinary cost computation
1497 for this operand, so skip to the end of the
1498 alternative (should be just one character). */
1499 while (*p
&& *p
++ != ',')
1507 /* Scan all the constraint letters. See if the operand matches
1508 any of the constraints. Collect the valid register classes
1509 and see if this operand accepts memory. */
1511 while (*p
&& (c
= *p
++) != ',')
1515 /* Ignore the next letter for this pass. */
1521 case '!': case '#': case '&':
1522 case '0': case '1': case '2': case '3': case '4':
1523 case '5': case '6': case '7': case '8': case '9':
1528 win
= address_operand (op
, GET_MODE (op
));
1529 /* We know this operand is an address, so we want it to be
1530 allocated to a register that can be the base of an
1531 address, ie BASE_REG_CLASS. */
1533 = reg_class_subunion
[(int) classes
[i
]]
1534 [(int) BASE_REG_CLASS
];
1537 case 'm': case 'o': case 'V':
1538 /* It doesn't seem worth distinguishing between offsettable
1539 and non-offsettable addresses here. */
1541 if (GET_CODE (op
) == MEM
)
1546 if (GET_CODE (op
) == MEM
1547 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1548 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1553 if (GET_CODE (op
) == MEM
1554 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1555 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1560 #ifndef REAL_ARITHMETIC
1561 /* Match any floating double constant, but only if
1562 we can examine the bits of it reliably. */
1563 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
1564 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
1565 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
1568 if (GET_CODE (op
) == CONST_DOUBLE
)
1573 if (GET_CODE (op
) == CONST_DOUBLE
)
1579 if (GET_CODE (op
) == CONST_DOUBLE
1580 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
1585 if (GET_CODE (op
) == CONST_INT
1586 || (GET_CODE (op
) == CONST_DOUBLE
1587 && GET_MODE (op
) == VOIDmode
))
1591 #ifdef LEGITIMATE_PIC_OPERAND_P
1592 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1599 if (GET_CODE (op
) == CONST_INT
1600 || (GET_CODE (op
) == CONST_DOUBLE
1601 && GET_MODE (op
) == VOIDmode
))
1613 if (GET_CODE (op
) == CONST_INT
1614 && CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
1623 if (GET_CODE (op
) == MEM
1625 #ifdef LEGITIMATE_PIC_OPERAND_P
1626 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1633 = reg_class_subunion
[(int) classes
[i
]][(int) GENERAL_REGS
];
1637 if (REG_CLASS_FROM_LETTER (c
) != NO_REGS
)
1639 = reg_class_subunion
[(int) classes
[i
]]
1640 [(int) REG_CLASS_FROM_LETTER (c
)];
1641 #ifdef EXTRA_CONSTRAINT
1642 else if (EXTRA_CONSTRAINT (op
, c
))
1650 /* How we account for this operand now depends on whether it is a
1651 pseudo register or not. If it is, we first check if any
1652 register classes are valid. If not, we ignore this alternative,
1653 since we want to assume that all pseudos get allocated for
1654 register preferencing. If some register class is valid, compute
1655 the costs of moving the pseudo into that class. */
1657 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1659 if (classes
[i
] == NO_REGS
)
1661 /* We must always fail if the operand is a REG, but
1662 we did not find a suitable class.
1664 Otherwise we may perform an uninitialized read
1665 from this_op_costs after the `continue' statement
1671 struct costs
*pp
= &this_op_costs
[i
];
1673 for (class = 0; class < N_REG_CLASSES
; class++)
1675 = ((recog_data
.operand_type
[i
] != OP_OUT
1676 ? may_move_in_cost
[mode
][class][(int) classes
[i
]]
1678 + (recog_data
.operand_type
[i
] != OP_IN
1679 ? may_move_out_cost
[mode
][(int) classes
[i
]][class]
1682 /* If the alternative actually allows memory, make things
1683 a bit cheaper since we won't need an extra insn to
1687 = ((recog_data
.operand_type
[i
] != OP_IN
1688 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1690 + (recog_data
.operand_type
[i
] != OP_OUT
1691 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1692 : 0) - allows_mem
[i
]);
1694 /* If we have assigned a class to this register in our
1695 first pass, add a cost to this alternative corresponding
1696 to what we would add if this register were not in the
1697 appropriate class. */
1701 += (may_move_in_cost
[mode
]
1702 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1703 [(int) classes
[i
]]);
1707 /* Otherwise, if this alternative wins, either because we
1708 have already determined that or if we have a hard register of
1709 the proper class, there is no cost for this alternative. */
1712 || (GET_CODE (op
) == REG
1713 && reg_fits_class_p (op
, classes
[i
], 0, GET_MODE (op
))))
1716 /* If registers are valid, the cost of this alternative includes
1717 copying the object to and/or from a register. */
1719 else if (classes
[i
] != NO_REGS
)
1721 if (recog_data
.operand_type
[i
] != OP_OUT
)
1722 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1);
1724 if (recog_data
.operand_type
[i
] != OP_IN
)
1725 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0);
1728 /* The only other way this alternative can be used is if this is a
1729 constant that could be placed into memory. */
1731 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
1732 alt_cost
+= MEMORY_MOVE_COST (mode
, classes
[i
], 1);
1740 /* Finally, update the costs with the information we've calculated
1741 about this alternative. */
1743 for (i
= 0; i
< n_ops
; i
++)
1744 if (GET_CODE (ops
[i
]) == REG
1745 && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1747 struct costs
*pp
= &op_costs
[i
], *qq
= &this_op_costs
[i
];
1748 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
1750 pp
->mem_cost
= MIN (pp
->mem_cost
,
1751 (qq
->mem_cost
+ alt_cost
) * scale
);
1753 for (class = 0; class < N_REG_CLASSES
; class++)
1754 pp
->cost
[class] = MIN (pp
->cost
[class],
1755 (qq
->cost
[class] + alt_cost
) * scale
);
1759 /* If this insn is a single set copying operand 1 to operand 0
1760 and one operand is a pseudo with the other a hard reg or a pseudo
1761 that prefers a register that is in its own register class then
1762 we may want to adjust the cost of that register class to -1.
1764 Avoid the adjustment if the source does not die to avoid stressing of
1765 register allocator by preferrencing two coliding registers into single
1768 Also avoid the adjustment if a copy between registers of the class
1769 is expensive (ten times the cost of a default copy is considered
1770 arbitrarily expensive). This avoids losing when the preferred class
1771 is very expensive as the source of a copy instruction. */
1773 if ((set
= single_set (insn
)) != 0
1774 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
1775 && GET_CODE (ops
[0]) == REG
&& GET_CODE (ops
[1]) == REG
1776 && find_regno_note (insn
, REG_DEAD
, REGNO (ops
[1])))
1777 for (i
= 0; i
<= 1; i
++)
1778 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1780 unsigned int regno
= REGNO (ops
[!i
]);
1781 enum machine_mode mode
= GET_MODE (ops
[!i
]);
1785 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_pref
!= 0)
1787 enum reg_class pref
= reg_pref
[regno
].prefclass
;
1789 if ((reg_class_size
[(unsigned char) pref
]
1790 == CLASS_MAX_NREGS (pref
, mode
))
1791 && REGISTER_MOVE_COST (mode
, pref
, pref
) < 10 * 2)
1792 op_costs
[i
].cost
[(unsigned char) pref
] = -1;
1794 else if (regno
< FIRST_PSEUDO_REGISTER
)
1795 for (class = 0; class < N_REG_CLASSES
; class++)
1796 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1797 && reg_class_size
[class] == CLASS_MAX_NREGS (class, mode
))
1799 if (reg_class_size
[class] == 1)
1800 op_costs
[i
].cost
[class] = -1;
1803 for (nr
= 0; nr
< HARD_REGNO_NREGS (regno
, mode
); nr
++)
1805 if (! TEST_HARD_REG_BIT (reg_class_contents
[class],
1810 if (nr
== HARD_REGNO_NREGS (regno
,mode
))
1811 op_costs
[i
].cost
[class] = -1;
1817 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1818 TO_P is zero) a register of class CLASS in mode MODE.
1820 X must not be a pseudo. */
1823 copy_cost (x
, mode
, class, to_p
)
1825 enum machine_mode mode ATTRIBUTE_UNUSED
;
1826 enum reg_class
class;
1827 int to_p ATTRIBUTE_UNUSED
;
1829 #ifdef HAVE_SECONDARY_RELOADS
1830 enum reg_class secondary_class
= NO_REGS
;
1833 /* If X is a SCRATCH, there is actually nothing to move since we are
1834 assuming optimal allocation. */
1836 if (GET_CODE (x
) == SCRATCH
)
1839 /* Get the class we will actually use for a reload. */
1840 class = PREFERRED_RELOAD_CLASS (x
, class);
1842 #ifdef HAVE_SECONDARY_RELOADS
1843 /* If we need a secondary reload (we assume here that we are using
1844 the secondary reload as an intermediate, not a scratch register), the
1845 cost is that to load the input into the intermediate register, then
1846 to copy them. We use a special value of TO_P to avoid recursion. */
1848 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1850 secondary_class
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, x
);
1853 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1855 secondary_class
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, x
);
1858 if (secondary_class
!= NO_REGS
)
1859 return (move_cost
[mode
][(int) secondary_class
][(int) class]
1860 + copy_cost (x
, mode
, secondary_class
, 2));
1861 #endif /* HAVE_SECONDARY_RELOADS */
1863 /* For memory, use the memory move cost, for (hard) registers, use the
1864 cost to move between the register classes, and use 2 for everything
1865 else (constants). */
1867 if (GET_CODE (x
) == MEM
|| class == NO_REGS
)
1868 return MEMORY_MOVE_COST (mode
, class, to_p
);
1870 else if (GET_CODE (x
) == REG
)
1871 return move_cost
[mode
][(int) REGNO_REG_CLASS (REGNO (x
))][(int) class];
1874 /* If this is a constant, we may eventually want to call rtx_cost here. */
1875 return COSTS_N_INSNS (1);
1878 /* Record the pseudo registers we must reload into hard registers
1879 in a subexpression of a memory address, X.
1881 CLASS is the class that the register needs to be in and is either
1882 BASE_REG_CLASS or INDEX_REG_CLASS.
1884 SCALE is twice the amount to multiply the cost by (it is twice so we
1885 can represent half-cost adjustments). */
1888 record_address_regs (x
, class, scale
)
1890 enum reg_class
class;
1893 register enum rtx_code code
= GET_CODE (x
);
1906 /* When we have an address that is a sum,
1907 we must determine whether registers are "base" or "index" regs.
1908 If there is a sum of two registers, we must choose one to be
1909 the "base". Luckily, we can use the REG_POINTER to make a good
1910 choice most of the time. We only need to do this on machines
1911 that can have two registers in an address and where the base
1912 and index register classes are different.
1914 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1915 that seems bogus since it should only be set when we are sure
1916 the register is being used as a pointer. */
1919 rtx arg0
= XEXP (x
, 0);
1920 rtx arg1
= XEXP (x
, 1);
1921 register enum rtx_code code0
= GET_CODE (arg0
);
1922 register enum rtx_code code1
= GET_CODE (arg1
);
1924 /* Look inside subregs. */
1925 if (code0
== SUBREG
)
1926 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1927 if (code1
== SUBREG
)
1928 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1930 /* If this machine only allows one register per address, it must
1931 be in the first operand. */
1933 if (MAX_REGS_PER_ADDRESS
== 1)
1934 record_address_regs (arg0
, class, scale
);
1936 /* If index and base registers are the same on this machine, just
1937 record registers in any non-constant operands. We assume here,
1938 as well as in the tests below, that all addresses are in
1941 else if (INDEX_REG_CLASS
== BASE_REG_CLASS
)
1943 record_address_regs (arg0
, class, scale
);
1944 if (! CONSTANT_P (arg1
))
1945 record_address_regs (arg1
, class, scale
);
1948 /* If the second operand is a constant integer, it doesn't change
1949 what class the first operand must be. */
1951 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
1952 record_address_regs (arg0
, class, scale
);
1954 /* If the second operand is a symbolic constant, the first operand
1955 must be an index register. */
1957 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1958 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1960 /* If both operands are registers but one is already a hard register
1961 of index or base class, give the other the class that the hard
1964 #ifdef REG_OK_FOR_BASE_P
1965 else if (code0
== REG
&& code1
== REG
1966 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
1967 && (REG_OK_FOR_BASE_P (arg0
) || REG_OK_FOR_INDEX_P (arg0
)))
1968 record_address_regs (arg1
,
1969 REG_OK_FOR_BASE_P (arg0
)
1970 ? INDEX_REG_CLASS
: BASE_REG_CLASS
,
1972 else if (code0
== REG
&& code1
== REG
1973 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
1974 && (REG_OK_FOR_BASE_P (arg1
) || REG_OK_FOR_INDEX_P (arg1
)))
1975 record_address_regs (arg0
,
1976 REG_OK_FOR_BASE_P (arg1
)
1977 ? INDEX_REG_CLASS
: BASE_REG_CLASS
,
1981 /* If one operand is known to be a pointer, it must be the base
1982 with the other operand the index. Likewise if the other operand
1985 else if ((code0
== REG
&& REG_POINTER (arg0
))
1988 record_address_regs (arg0
, BASE_REG_CLASS
, scale
);
1989 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
);
1991 else if ((code1
== REG
&& REG_POINTER (arg1
))
1994 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1995 record_address_regs (arg1
, BASE_REG_CLASS
, scale
);
1998 /* Otherwise, count equal chances that each might be a base
1999 or index register. This case should be rare. */
2003 record_address_regs (arg0
, BASE_REG_CLASS
, scale
/ 2);
2004 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
/ 2);
2005 record_address_regs (arg1
, BASE_REG_CLASS
, scale
/ 2);
2006 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
/ 2);
2011 /* Double the importance of a pseudo register that is incremented
2012 or decremented, since it would take two extra insns
2013 if it ends up in the wrong place. */
2016 record_address_regs (XEXP (x
, 0), BASE_REG_CLASS
, 2 * scale
);
2017 if (REG_P (XEXP (XEXP (x
, 1), 1)))
2018 record_address_regs (XEXP (XEXP (x
, 1), 1),
2019 INDEX_REG_CLASS
, 2 * scale
);
2026 /* Double the importance of a pseudo register that is incremented
2027 or decremented, since it would take two extra insns
2028 if it ends up in the wrong place. If the operand is a pseudo,
2029 show it is being used in an INC_DEC context. */
2031 #ifdef FORBIDDEN_INC_DEC_CLASSES
2032 if (GET_CODE (XEXP (x
, 0)) == REG
2033 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
2034 in_inc_dec
[REGNO (XEXP (x
, 0))] = 1;
2037 record_address_regs (XEXP (x
, 0), class, 2 * scale
);
2042 register struct costs
*pp
= &costs
[REGNO (x
)];
2045 pp
->mem_cost
+= (MEMORY_MOVE_COST (Pmode
, class, 1) * scale
) / 2;
2047 for (i
= 0; i
< N_REG_CLASSES
; i
++)
2048 pp
->cost
[i
] += (may_move_in_cost
[Pmode
][i
][(int) class] * scale
) / 2;
2054 register const char *fmt
= GET_RTX_FORMAT (code
);
2056 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2058 record_address_regs (XEXP (x
, i
), class, scale
);
2063 #ifdef FORBIDDEN_INC_DEC_CLASSES
2065 /* Return 1 if REG is valid as an auto-increment memory reference
2066 to an object of MODE. */
2069 auto_inc_dec_reg_p (reg
, mode
)
2071 enum machine_mode mode
;
2073 if (HAVE_POST_INCREMENT
2074 && memory_address_p (mode
, gen_rtx_POST_INC (Pmode
, reg
)))
2077 if (HAVE_POST_DECREMENT
2078 && memory_address_p (mode
, gen_rtx_POST_DEC (Pmode
, reg
)))
2081 if (HAVE_PRE_INCREMENT
2082 && memory_address_p (mode
, gen_rtx_PRE_INC (Pmode
, reg
)))
2085 if (HAVE_PRE_DECREMENT
2086 && memory_address_p (mode
, gen_rtx_PRE_DEC (Pmode
, reg
)))
2093 static short *renumber
;
2094 static size_t regno_allocated
;
2095 static unsigned int reg_n_max
;
2097 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2098 reg_scan and flow_analysis that are indexed by the register number. If
2099 NEW_P is non zero, initialize all of the registers, otherwise only
2100 initialize the new registers allocated. The same table is kept from
2101 function to function, only reallocating it when we need more room. If
2102 RENUMBER_P is non zero, allocate the reg_renumber array also. */
2105 allocate_reg_info (num_regs
, new_p
, renumber_p
)
2111 size_t size_renumber
;
2112 size_t min
= (new_p
) ? 0 : reg_n_max
;
2113 struct reg_info_data
*reg_data
;
2115 if (num_regs
> regno_allocated
)
2117 size_t old_allocated
= regno_allocated
;
2119 regno_allocated
= num_regs
+ (num_regs
/ 20); /* add some slop space */
2120 size_renumber
= regno_allocated
* sizeof (short);
2124 VARRAY_REG_INIT (reg_n_info
, regno_allocated
, "reg_n_info");
2125 renumber
= (short *) xmalloc (size_renumber
);
2126 reg_pref_buffer
= (struct reg_pref
*) xmalloc (regno_allocated
2127 * sizeof (struct reg_pref
));
2132 VARRAY_GROW (reg_n_info
, regno_allocated
);
2134 if (new_p
) /* if we're zapping everything, no need to realloc */
2136 free ((char *)renumber
);
2137 free ((char *)reg_pref
);
2138 renumber
= (short *) xmalloc (size_renumber
);
2139 reg_pref_buffer
= (struct reg_pref
*) xmalloc (regno_allocated
2140 * sizeof (struct reg_pref
));
2145 renumber
= (short *) xrealloc ((char *)renumber
, size_renumber
);
2146 reg_pref_buffer
= (struct reg_pref
*) xrealloc ((char *)reg_pref_buffer
,
2148 * sizeof (struct reg_pref
));
2152 size_info
= (regno_allocated
- old_allocated
) * sizeof (reg_info
)
2153 + sizeof (struct reg_info_data
) - sizeof (reg_info
);
2154 reg_data
= (struct reg_info_data
*) xcalloc (size_info
, 1);
2155 reg_data
->min_index
= old_allocated
;
2156 reg_data
->max_index
= regno_allocated
- 1;
2157 reg_data
->next
= reg_info_head
;
2158 reg_info_head
= reg_data
;
2161 reg_n_max
= num_regs
;
2164 /* Loop through each of the segments allocated for the actual
2165 reg_info pages, and set up the pointers, zero the pages, etc. */
2166 for (reg_data
= reg_info_head
;
2167 reg_data
&& reg_data
->max_index
>= min
;
2168 reg_data
= reg_data
->next
)
2170 size_t min_index
= reg_data
->min_index
;
2171 size_t max_index
= reg_data
->max_index
;
2172 size_t max
= MIN (max_index
, num_regs
);
2173 size_t local_min
= min
- min_index
;
2176 if (reg_data
->min_index
> num_regs
)
2179 if (min
< min_index
)
2181 if (!reg_data
->used_p
) /* page just allocated with calloc */
2182 reg_data
->used_p
= 1; /* no need to zero */
2184 memset ((char *) ®_data
->data
[local_min
], 0,
2185 sizeof (reg_info
) * (max
- min_index
- local_min
+ 1));
2187 for (i
= min_index
+local_min
; i
<= max
; i
++)
2189 VARRAY_REG (reg_n_info
, i
) = ®_data
->data
[i
-min_index
];
2190 REG_BASIC_BLOCK (i
) = REG_BLOCK_UNKNOWN
;
2192 reg_pref_buffer
[i
].prefclass
= (char) NO_REGS
;
2193 reg_pref_buffer
[i
].altclass
= (char) NO_REGS
;
2198 /* If {pref,alt}class have already been allocated, update the pointers to
2199 the newly realloced ones. */
2201 reg_pref
= reg_pref_buffer
;
2204 reg_renumber
= renumber
;
2206 /* Tell the regset code about the new number of registers */
2207 MAX_REGNO_REG_SET (num_regs
, new_p
, renumber_p
);
2210 /* Free up the space allocated by allocate_reg_info. */
2216 struct reg_info_data
*reg_data
;
2217 struct reg_info_data
*reg_next
;
2219 VARRAY_FREE (reg_n_info
);
2220 for (reg_data
= reg_info_head
; reg_data
; reg_data
= reg_next
)
2222 reg_next
= reg_data
->next
;
2223 free ((char *)reg_data
);
2226 free (reg_pref_buffer
);
2227 reg_pref_buffer
= (struct reg_pref
*)0;
2228 reg_info_head
= (struct reg_info_data
*)0;
2229 renumber
= (short *)0;
2231 regno_allocated
= 0;
2235 /* This is the `regscan' pass of the compiler, run just before cse
2236 and again just before loop.
2238 It finds the first and last use of each pseudo-register
2239 and records them in the vectors regno_first_uid, regno_last_uid
2240 and counts the number of sets in the vector reg_n_sets.
2242 REPEAT is nonzero the second time this is called. */
2244 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2245 Always at least 3, since the combiner could put that many together
2246 and we want this to remain correct for all the remaining passes.
2247 This corresponds to the maximum number of times note_stores will call
2248 a function for any insn. */
2252 /* Used as a temporary to record the largest number of registers in
2253 PARALLEL in a SET_DEST. This is added to max_parallel. */
2255 static int max_set_parallel
;
2258 reg_scan (f
, nregs
, repeat
)
2261 int repeat ATTRIBUTE_UNUSED
;
2265 allocate_reg_info (nregs
, TRUE
, FALSE
);
2267 max_set_parallel
= 0;
2269 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
2270 if (GET_CODE (insn
) == INSN
2271 || GET_CODE (insn
) == CALL_INSN
2272 || GET_CODE (insn
) == JUMP_INSN
)
2274 if (GET_CODE (PATTERN (insn
)) == PARALLEL
2275 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
2276 max_parallel
= XVECLEN (PATTERN (insn
), 0);
2277 reg_scan_mark_refs (PATTERN (insn
), insn
, 0, 0);
2279 if (REG_NOTES (insn
))
2280 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, 0);
2283 max_parallel
+= max_set_parallel
;
2286 /* Update 'regscan' information by looking at the insns
2287 from FIRST to LAST. Some new REGs have been created,
2288 and any REG with number greater than OLD_MAX_REGNO is
2289 such a REG. We only update information for those. */
2292 reg_scan_update (first
, last
, old_max_regno
)
2295 unsigned int old_max_regno
;
2299 allocate_reg_info (max_reg_num (), FALSE
, FALSE
);
2301 for (insn
= first
; insn
!= last
; insn
= NEXT_INSN (insn
))
2302 if (GET_CODE (insn
) == INSN
2303 || GET_CODE (insn
) == CALL_INSN
2304 || GET_CODE (insn
) == JUMP_INSN
)
2306 if (GET_CODE (PATTERN (insn
)) == PARALLEL
2307 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
2308 max_parallel
= XVECLEN (PATTERN (insn
), 0);
2309 reg_scan_mark_refs (PATTERN (insn
), insn
, 0, old_max_regno
);
2311 if (REG_NOTES (insn
))
2312 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, old_max_regno
);
2316 /* X is the expression to scan. INSN is the insn it appears in.
2317 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2318 We should only record information for REGs with numbers
2319 greater than or equal to MIN_REGNO. */
2322 reg_scan_mark_refs (x
, insn
, note_flag
, min_regno
)
2326 unsigned int min_regno
;
2328 register enum rtx_code code
;
2332 code
= GET_CODE (x
);
2348 unsigned int regno
= REGNO (x
);
2350 if (regno
>= min_regno
)
2352 REGNO_LAST_NOTE_UID (regno
) = INSN_UID (insn
);
2354 REGNO_LAST_UID (regno
) = INSN_UID (insn
);
2355 if (REGNO_FIRST_UID (regno
) == 0)
2356 REGNO_FIRST_UID (regno
) = INSN_UID (insn
);
2363 reg_scan_mark_refs (XEXP (x
, 0), insn
, note_flag
, min_regno
);
2365 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2370 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2374 /* Count a set of the destination if it is a register. */
2375 for (dest
= SET_DEST (x
);
2376 GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
2377 || GET_CODE (dest
) == ZERO_EXTEND
;
2378 dest
= XEXP (dest
, 0))
2381 /* For a PARALLEL, record the number of things (less the usual one for a
2382 SET) that are set. */
2383 if (GET_CODE (dest
) == PARALLEL
)
2384 max_set_parallel
= MAX (max_set_parallel
, XVECLEN (dest
, 0) - 1);
2386 if (GET_CODE (dest
) == REG
2387 && REGNO (dest
) >= min_regno
)
2388 REG_N_SETS (REGNO (dest
))++;
2390 /* If this is setting a pseudo from another pseudo or the sum of a
2391 pseudo and a constant integer and the other pseudo is known to be
2392 a pointer, set the destination to be a pointer as well.
2394 Likewise if it is setting the destination from an address or from a
2395 value equivalent to an address or to the sum of an address and
2398 But don't do any of this if the pseudo corresponds to a user
2399 variable since it should have already been set as a pointer based
2402 if (GET_CODE (SET_DEST (x
)) == REG
2403 && REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
2404 && REGNO (SET_DEST (x
)) >= min_regno
2405 /* If the destination pseudo is set more than once, then other
2406 sets might not be to a pointer value (consider access to a
2407 union in two threads of control in the presense of global
2408 optimizations). So only set REG_POINTER on the destination
2409 pseudo if this is the only set of that pseudo. */
2410 && REG_N_SETS (REGNO (SET_DEST (x
))) == 1
2411 && ! REG_USERVAR_P (SET_DEST (x
))
2412 && ! REG_POINTER (SET_DEST (x
))
2413 && ((GET_CODE (SET_SRC (x
)) == REG
2414 && REG_POINTER (SET_SRC (x
)))
2415 || ((GET_CODE (SET_SRC (x
)) == PLUS
2416 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2417 && GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2418 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
2419 && REG_POINTER (XEXP (SET_SRC (x
), 0)))
2420 || GET_CODE (SET_SRC (x
)) == CONST
2421 || GET_CODE (SET_SRC (x
)) == SYMBOL_REF
2422 || GET_CODE (SET_SRC (x
)) == LABEL_REF
2423 || (GET_CODE (SET_SRC (x
)) == HIGH
2424 && (GET_CODE (XEXP (SET_SRC (x
), 0)) == CONST
2425 || GET_CODE (XEXP (SET_SRC (x
), 0)) == SYMBOL_REF
2426 || GET_CODE (XEXP (SET_SRC (x
), 0)) == LABEL_REF
))
2427 || ((GET_CODE (SET_SRC (x
)) == PLUS
2428 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2429 && (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST
2430 || GET_CODE (XEXP (SET_SRC (x
), 1)) == SYMBOL_REF
2431 || GET_CODE (XEXP (SET_SRC (x
), 1)) == LABEL_REF
))
2432 || ((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
2433 && (GET_CODE (XEXP (note
, 0)) == CONST
2434 || GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
2435 || GET_CODE (XEXP (note
, 0)) == LABEL_REF
))))
2436 REG_POINTER (SET_DEST (x
)) = 1;
2438 /* ... fall through ... */
2442 register const char *fmt
= GET_RTX_FORMAT (code
);
2444 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2447 reg_scan_mark_refs (XEXP (x
, i
), insn
, note_flag
, min_regno
);
2448 else if (fmt
[i
] == 'E' && XVEC (x
, i
) != 0)
2451 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2452 reg_scan_mark_refs (XVECEXP (x
, i
, j
), insn
, note_flag
, min_regno
);
2459 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2463 reg_class_subset_p (c1
, c2
)
2464 register enum reg_class c1
;
2465 register enum reg_class c2
;
2467 if (c1
== c2
) return 1;
2472 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int)c1
],
2473 reg_class_contents
[(int)c2
],
2478 /* Return nonzero if there is a register that is in both C1 and C2. */
2481 reg_classes_intersect_p (c1
, c2
)
2482 register enum reg_class c1
;
2483 register enum reg_class c2
;
2490 if (c1
== c2
) return 1;
2492 if (c1
== ALL_REGS
|| c2
== ALL_REGS
)
2495 COPY_HARD_REG_SET (c
, reg_class_contents
[(int) c1
]);
2496 AND_HARD_REG_SET (c
, reg_class_contents
[(int) c2
]);
2498 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[(int) NO_REGS
], lose
);
2505 /* Release any memory allocated by register sets. */
2508 regset_release_memory ()
2510 bitmap_release_memory ();