gcc/config/picochip/picochip.h

   1 /* Definitions of target machine for GNU compiler for picoChip
   2    Copyright (C) 2001-2013 Free Software Foundation, Inc.
   3
   4    Contributed by Picochip Ltd. (http://www.picochip.com)
   5    Maintained by Daniel Towner (daniel.towner@picochip.com) and
   6    Hariharan Sandanagobalane (hariharan@picochip.com).
   7
   8 This file is part of GCC.
   9
  10 GCC is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 3, or (at your option)
  13 any later version.
  14
  15 GCC is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with GCC; see the file COPYING3.  If not, see
  22 <http://www.gnu.org/licenses/>. */
  23
  24 /* Which type of DFA scheduling to use - schedule for speed (VLIW), or
  25    schedule for space.  When scheduling for space, attempt to schedule
  26    into stall cycles, but don't pack instructions. */
  27
  28 enum picochip_dfa_type
  29 {
  30   DFA_TYPE_NONE,
  31   DFA_TYPE_SPACE,
  32   DFA_TYPE_SPEED
  33 };
  34
  35 extern enum picochip_dfa_type picochip_schedule_type;
  36
  37 /* Controlling the Compilation Driver */
  38
  39 /* Pass through the save-temps command option. */
  40 #define LINK_SPEC " %{save-temps:--save-temps}"
  41
  42 /* This is an embedded processor, and only supports a cut-down version of
  43  * the standard C library. */
  44 #define LIB_SPEC "-lpicoC"
  45
  46 /* The start file is automatically provided by the linker. */
  47 #define STARTFILE_SPEC ""
  48 \f
  49 /* Run-time Target Specification  */
  50
  51 /* Define some additional pre-processor macros. */
  52 #define TARGET_CPU_CPP_BUILTINS()                       \
  53   do                                                    \
  54     {                                                   \
  55       builtin_define ("NO_TRAMPOLINES");                \
  56       builtin_define ("PICOCHIP");                      \
  57       builtin_define ("__PICOCHIP__");                      \
  58     }                                                   \
  59   while (0)
  60
  61 /* Translate requests for particular AEs into their respective ISA
  62    options. Note that byte access is enabled by default. */
  63 #define DRIVER_SELF_SPECS                                       \
  64   "%{mae=ANY:-mmul-type=none -mno-byte-access} %<mae=ANY",      \
  65   "%{mae=ANY2:-mmul-type=none -mno-byte-access} %<mae=ANY2",    \
  66   "%{mae=ANY3:-mmul-type=none} %<mae=ANY3",                     \
  67   "%{mae=STAN:-mmul-type=none -mno-byte-access} %<mae=STAN",    \
  68   "%{mae=STAN2:-mmul-type=mac -mno-byte-access} %<mae=STAN2",   \
  69   "%{mae=STAN3:-mmul-type=mac} %<mae=STAN3",                    \
  70   "%{mae=MAC:-mmul-type=mac -mno-byte-access} %<mae=MAC",       \
  71   "%{mae=MUL:-mmul-type=mul} %<mae=MUL",                        \
  72   "%{mae=MEM:-mmul-type=mul} %<mae=MEM",                        \
  73   "%{mae=MEM2:-mmul-type=mul} %<mae=MEM2",                      \
  74   "%{mae=CTRL:-mmul-type=mul} %<mae=CTRL",                      \
  75   "%{mae=CTRL2:-mmul-type=mul} %<mae=CTRL2"
  76
  77 /* Specify the default options, so that the multilib build doesn't
  78    need to provide special cases for the defaults. */
  79 #define MULTILIB_DEFAULTS \
  80   { "mmul-type=mul", "mbyte-access"}
  81
  82 #define TARGET_HAS_BYTE_ACCESS (picochip_has_byte_access)
  83 #define TARGET_HAS_MUL_UNIT (picochip_has_mul_unit)
  84 #define TARGET_HAS_MAC_UNIT (picochip_has_mac_unit)
  85 #define TARGET_HAS_MULTIPLY (picochip_has_mac_unit || picochip_has_mul_unit)
  86 \f
  87 /* Storage Layout */
  88
  89 /* picoChip processors are 16-bit machines, little endian. */
  90
  91 #define BITS_BIG_ENDIAN 0
  92 #define BYTES_BIG_ENDIAN 0
  93 #define WORDS_BIG_ENDIAN 0
  94
  95 #define BITS_PER_UNIT 8
  96
  97 #define BITS_PER_WORD 16
  98 #define UNITS_PER_WORD (BITS_PER_WORD / BITS_PER_UNIT)
  99
 100 #define POINTER_SIZE BITS_PER_WORD
 101
 102 /* Promote those modes that are smaller than an int, to int mode.  */
 103 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
 104   ((GET_MODE_CLASS (MODE) == MODE_INT                   \
 105       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)         \
 106       ? (MODE) = HImode : 0)
 107
 108 /* All parameters are at least this aligned.  Parameters are passed
 109    one-per-register. */
 110 #define PARM_BOUNDARY BITS_PER_WORD
 111
 112 /* The main stack pointer is guaranteed to be aligned to the most
 113    strict data alignment. */
 114 #define STACK_BOUNDARY 32
 115
 116 /* Function entry point is byte aligned. */
 117 #define FUNCTION_BOUNDARY 8
 118
 119 /* This is the biggest alignment that can be allowed on this machine.
 120    Since the STANs have only 256 byte memory, it doesn't make sense
 121    to have alignments greater than 32 bytes. Hence the value */
 122 #define MAX_OFILE_ALIGNMENT 32*8
 123
 124 /* The strictest data object alignment, which repesents a register pair. */
 125 #define BIGGEST_ALIGNMENT 32
 126
 127 /* The hardware doesn't allow unaligned memory access.  */
 128 #define STRICT_ALIGNMENT 1
 129
 130 /* We want the 'unix' style bitfield packing algorithm.  */
 131 #define PCC_BITFIELD_TYPE_MATTERS 1
 132
 133 /* Support up to 64-bit integers. */
 134 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (DImode)
 135
 136 /* We don't support floating point, but give it a sensible definition. */
 137 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
 138 \f
 139 /* Layout of Source Language Data Types.  */
 140
 141 #define INT_TYPE_SIZE BITS_PER_WORD
 142
 143 /* The normal sizes for C scalar data. */
 144 #define CHAR_TYPE_SIZE 8
 145 #define SHORT_TYPE_SIZE 16
 146 #define LONG_TYPE_SIZE 32
 147 #define LONG_LONG_TYPE_SIZE 64
 148
 149 /* We don't support the following data types, but still give them
 150    sensible values.  */
 151 #define FLOAT_TYPE_SIZE 32
 152 #define DOUBLE_TYPE_SIZE 32
 153 #define LONG_DOUBLE_TYPE_SIZE 32
 154
 155 /* Plain `char' is a signed type, since the hardware sign-extends
 156    bytes when loading them from memory into a register. */
 157 #define DEFAULT_SIGNED_CHAR 1
 158
 159 /* Note that the names of the types used in the following macros must
 160    be precisely the same as those defined internally in gcc.  For
 161    example, `unsigned short' wouldn't work as a type string, since gcc
 162    doesn't define any type with this exact string.  The correct string
 163    to use is `short unsigned int'. */
 164
 165 #define SIZE_TYPE "unsigned int"
 166
 167 #define PTRDIFF_TYPE "int"
 168
 169 #define WCHAR_TYPE "short unsigned int"
 170 #define WCHAR_TYPE_SIZE 16
 171
 172 #define WINT_TYPE "unsigned int"
 173 \f
 174 /* Register Usage  */
 175
 176 /* Picochip has 16 16-bit registers, a condition code register and an
 177    (inaccessible) instruction pointer.  One of these registers (r15) is
 178    special, and is either used to load a constant anywhere a register
 179    can normally be used, or is used to specify a dummy destination
 180    (e.g., when setting condition flags).  We also define some pseudo
 181    registers to represent condition codes, the frame pointer and the
 182    argument pointer.  The latter two are eliminated wherever possible.
 183
 184    Pairs of general registers may be combined to form 32-bit registers.
 185
 186    The picoChip registers are as follows:
 187
 188    0..1 - function return value
 189    0..5 - first 6 function parameters
 190    6..11 - General purpose
 191    12 - link register
 192    13 - stack pointer
 193    14 - specialized pointer
 194    15 - long constant or /dev/null
 195    (16) acc0
 196    (17) pseudo condition code
 197    (18) pseudo frame pointer
 198    (19) pseudo arg pointer
 199
 200    Registers 0..6, 12, 13, 14, 15 are caller save
 201    Registers 0..12, 14 are available to the register allocator.
 202
 203    In addition, the DSP variant of the ISA allows extra accumulator
 204    registers to be accessed.  These are special purpose registers,
 205    which are not currently used by the compiler.
 206
 207   */
 208
 209 /* Basic Characteristics of Registers  */
 210
 211 /* We have 16 hard registers plus 3 pseudo hard registers and an accumulator.  */
 212 #define FIRST_PSEUDO_REGISTER 20
 213
 214 /* The first non-hard register.  Only used internally by the picoChip port. */
 215 #define FIRST_NONHARD_REGISTER 18
 216
 217 /* Cannot use SP, CST, CC, FP, AP */
 218 #define FIXED_REGISTERS {0,0,0,0,0,0,0,0, 0,0,0,0,0,1,0,1, 1,1,1,1}
 219
 220 /* Those that are clobbered by a function call (includes pseudo-regs) */
 221 #define CALL_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,1, 1,1,1,1}
 222 #define CALL_REALLY_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,0, 0,1,0,0}
 223
 224 /* Define the number of the picoChip link and condition pseudo registers. */
 225 #define LINK_REGNUM 12
 226 #define CC_REGNUM 17
 227 #define ACC_REGNUM 16
 228
 229 /* Order of Allocation of Registers  */
 230
 231 /* The registers are allocated starting with the caller-clobbered
 232    registers, in reverse order.  The registers are then listed in an
 233    order which means that they are efficiently saved in pairs (i.e.,
 234    one 32-bit store can be used instead of two 16-bit stores to save
 235    the registers into the stack). The exception to this is the use of
 236    r14 (AP) register, which also appears early on.  This is because the
 237    AP register can be used to encode memory operations more
 238    efficiently than other registers.  Some code can be made more
 239    compact as a result. */
 240    /* My current feeling is that r14 should go to the end and maybe even r12.
 241    It seems like the overhead of store/load that will occur since we cant
 242    pair anything up with r14 will be higher than the advantage of smaller
 243    encoding.
 244    Also r12 is put towards the end for leaf functions. Since leaf functions
 245    do not have any calls, the prologue/epilogue for them wouldnt save up/
 246    restore its value. So, it doesn't make sense for us to use it in the middle,
 247    if we can avoid it. */
 248 #define REG_ALLOC_ORDER {5,4,3,2,1,0,12,6,7,8,9,10,11,14,16,0,0,0,0,0}
 249 #define LEAF_REG_ALLOC_ORDER {5,4,3,2,1,0,6,7,8,9,10,11,14,12,16,0,0,0,0,0}
 250
 251 /* We can dynamically change the REG_ALLOC_ORDER using the following hook.
 252    It would be desirable to change it for leaf functions so we can put
 253    r12 at the end of this list.*/
 254 #define ADJUST_REG_ALLOC_ORDER picochip_order_regs_for_local_alloc ()
 255
 256 /* How Values Fit in Registers  */
 257
 258 /* Number of consecutive hard regs needed starting at reg REGNO
 259    to hold something of mode MODE.  */
 260 #define HARD_REGNO_NREGS(REGNO, MODE) picochip_regno_nregs((REGNO), (MODE))
 261
 262 /* Is it ok to place MODE in REGNO?  Require that the register number
 263    be aligned. */
 264 #define HARD_REGNO_MODE_OK(REGNO, MODE) picochip_hard_regno_mode_ok(REGNO, MODE)
 265
 266 #define MODES_TIEABLE_P(MODE1,MODE2) 1
 267
 268 /* Don't copy the cc register ('cos you can't put it back).  */
 269 #define AVOID_CCMODE_COPIES 1
 270 \f
 271 /* Register Classes */
 272
 273 enum reg_class
 274 {
 275   NO_REGS,                      /* no registers in set */
 276   FRAME_REGS,                   /* registers with a long offset  */
 277   PTR_REGS,                     /* registers without an offset  */
 278   CONST_REGS,                   /* registers for long constants  */
 279   NULL_REGS,                    /* registers which ignore writes  */
 280   CC_REGS,                      /* condition code registers  */
 281   ACC_REGS,                     /* Accumulator registers  */
 282   TWIN_REGS,                    /* registers which can be paired */
 283   GR_REGS,                      /* general purpose registers */
 284   ALL_REGS,                     /* all registers */
 285   LIM_REG_CLASSES,              /* max value + 1 */
 286
 287   /* Some aliases  */
 288   GENERAL_REGS = GR_REGS
 289 };
 290
 291 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 292
 293
 294 /* The names of the register classes  */
 295 #define REG_CLASS_NAMES                                                 \
 296 {                                                                       \
 297   "NO_REGS",                                                            \
 298   "FRAME_REGS",                                                         \
 299   "PTR_REGS",                                                           \
 300   "CONST_REGS",                                                         \
 301   "NULL_REGS",                                                          \
 302   "CC_REGS",                                                            \
 303   "ACC_REGS",                                                           \
 304   "TWIN_REGS",                                                          \
 305   "GR_REGS",                                                            \
 306   "ALL_REGS"                                                            \
 307 }
 308
 309 /* Each reg class is an array of 32-bit integers.  Each array must be
 310    long enough to store one bit for every pseudo register. Thus in the
 311    following code, each array only stores one 32-bit value. */
 312 #define REG_CLASS_CONTENTS                                              \
 313 {                                                                       \
 314   {0x00000000}, /* no registers */                                      \
 315   {0x00002000}, /* frame */                                             \
 316   {0x00004000}, /* pointer  */                                          \
 317   {0x00008000}, /* const */                                             \
 318   {0x00008000}, /* null  */                                             \
 319   {0x00020000}, /* cc */                                                \
 320   {0x00010000}, /* acc0 */                                              \
 321   {0x00000FFF}, /* twin */                                              \
 322   {0x000CFFFF}, /* general registers - includes pseudo-arg */           \
 323   {0x000FFFFF}  /* all registers - includes pseudo-arg */               \
 324 }
 325
 326 /* The earliest register class containing the given register.  */
 327 extern const enum reg_class picochip_regno_reg_class[FIRST_PSEUDO_REGISTER];
 328 #define REGNO_REG_CLASS(REGNO) picochip_regno_reg_class[REGNO]
 329
 330 /* Any register can be a base pointer.  */
 331 #define BASE_REG_CLASS GR_REGS
 332
 333 /* Any register can be an index.  */
 334 #define INDEX_REG_CLASS GR_REGS
 335
 336 #define REGNO_OK_FOR_BASE_P(REGNO)                                      \
 337   (REGNO_REG_CLASS (REGNO) != CC_REGS && REGNO_REG_CLASS (REGNO) != ACC_REGS)
 338
 339 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
 340
 341 #define CLASS_MAX_NREGS(CLASS, MODE) picochip_class_max_nregs(CLASS, MODE)
 342
 343 \f
 344 /* Stack Layout and Calling Conventions  */
 345
 346 #define STACK_GROWS_DOWNWARD 1
 347
 348 /* The frame pointer points to the outgoing argument area, so the
 349    locals are above that.  */
 350 #define STARTING_FRAME_OFFSET 0
 351
 352 #define FIRST_PARM_OFFSET(FNDECL) 0
 353
 354 /* Specify where the return address lives before entry to the
 355    prologue.  This is required to enable DWARF debug information to be
 356    generated. */
 357 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (Pmode, LINK_REGNUM)
 358
 359 #define RETURN_ADDR_RTX(count,frameaddr) picochip_return_addr_rtx(count,frameaddr)
 360
 361 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNUM)
 362
 363 /* Registers that Address the Stack Frame  */
 364
 365 #define STACK_POINTER_REGNUM 13
 366 #define FRAME_POINTER_REGNUM 18
 367 #define ARG_POINTER_REGNUM   19
 368
 369 /* Eliminating Frame Pointer and Arg Pointer.  The frame and argument
 370    pointers are eliminated wherever possible, by replacing them with
 371    offsets from the stack pointer. */
 372
 373 #define ELIMINABLE_REGS                                                 \
 374   {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},                          \
 375    {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
 376
 377 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,OFFSET) \
 378   OFFSET = initial_elimination_offset(FROM, TO);
 379
 380 #define ACCUMULATE_OUTGOING_ARGS 1
 381
 382 #define PUSH_ARGS 0
 383
 384 /* Passing Arguments in Registers  */
 385
 386 /* Store the offset of the next argument. */
 387 #define CUMULATIVE_ARGS unsigned
 388
 389 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \
 390   ((CUM) = 0)
 391
 392 /* The first 6 registers can hold parameters.  */
 393 #define FUNCTION_ARG_REGNO_P(REGNO) ((REGNO) < 6)
 394
 395 /* How Scalar Function Values are Returned
 396    Do we need this?? */
 397 #define FUNCTION_VALUE(VALTYPE,FUNC) picochip_function_value(VALTYPE, FUNC, 0)
 398
 399 #define LIBCALL_VALUE(MODE) (gen_rtx_REG (MODE, 0))
 400
 401 /* Results are in register zero.  If an SImode register is returned,
 402    reg0 will suffice to mean R[0:1]. */
 403 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == 0)
 404
 405 /* Don't automatically pass struct's in memory - use the
 406  * RETURN_IN_MEMORY macro to determine when structs are returned in
 407  * memory, and when in registers. */
 408 #define DEFAULT_PCC_STRUCT_RETURN 0
 409
 410 /* Function Entry and Exit  */
 411
 412 /* The epilogue doesn't clobber anything.  */
 413 #define EPILOGUE_USES(REGNO) 0
 414
 415 /* Generating Code for Profiling.  No profiling implemented  */
 416
 417 #define FUNCTION_PROFILER(FILE,LABELNO)
 418 \f
 419 /* Trampolines for Nested Functions  */
 420
 421 /* No trampolines.  */
 422 #define TRAMPOLINE_SIZE 0
 423 \f
 424 /* Addressing Modes  */
 425
 426 #define MAX_REGS_PER_ADDRESS 1
 427
 428 /* Legitimize reload address tries machine dependent means of
 429    reloading addresses.  There seems to be a strange error in gcc,
 430    which necessitates this macro.  Consider:
 431
 432      set (reg A) (symbol_ref)
 433      set (reg B) (plus (reg A) (const_int))
 434
 435    A symbol_ref is a valid constant, so the symbol_ref is propagated
 436    into the second instruction to generate the instruction:
 437
 438      set (reg B) (plus (symbol_ref) (const_int))
 439
 440    This is an invalid address, and find_reloads_address correctly
 441    determines this.  However, that function doesn't generate a valid
 442    replacement for the now invalid address, and the invalid address is
 443    output into the assembly language.  To fix the problem without
 444    changing gcc itself, the following macro tests when such an invalid
 445    address has been computed, and wraps it up inside a constant rtx.  A
 446    constant rtx can be correctly reloaded by the function, and hence
 447    correct code is generated. */
 448
 449 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN)          \
 450 do {                                                                         \
 451   if (picochip_legitimize_reload_address(&X,MODE,OPNUM,TYPE,IND_LEVELS))     \
 452     goto WIN;                                                                \
 453   } while(0);                                                                \
 454
 455 \f
 456 /* Condition Code Status  */
 457
 458 #define CC_STATUS_MDEP unsigned
 459 #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
 460 \f
 461 /* Describing Relative Costs of Operations  */
 462
 463 /* Bytes are no faster than words.  */
 464 #define SLOW_BYTE_ACCESS 1
 465
 466 /* The assembler is often able to optimise function call branches, so
 467    don't try to CSE them in the compiler. This was the thinking before.
 468    But now, we realise that the benefits from CSE would mostly outweigh
 469    the disadvantages. */
 470 #define NO_FUNCTION_CSE
 471
 472 \f
 473 /* Dividing the Output into Sections  */
 474
 475 #define TEXT_SECTION_ASM_OP ".section .text\n"
 476 #define DATA_SECTION_ASM_OP ".section .data\n"
 477 #define BSS_SECTION_ASM_OP ".section .bss\n"
 478 /* picoChip is Harvard (separate data/instruction memories), so
 479    read-only data must go into the data section. */
 480 #define READONLY_DATA_SECTION_ASM_OP ".section .data\n"
 481 \f
 482 /* Defining the Output Assembler Language  */
 483
 484 /* The Overall Framework of an Assembler File  */
 485
 486 #define ASM_FILE_COMMENT "// "
 487
 488 #define ASM_APP_ON "// High-level ASM start\n"
 489 #define ASM_APP_OFF "// High-level ASM end\n"
 490
 491 #undef TARGET_ASM_OUTPUT_IDENT
 492 #define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive
 493
 494 /* Output of Data  */
 495
 496 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) picochip_output_ascii(FILE, PTR, LEN);
 497
 498 /* Output of Uninitialized Variables  */
 499 #define ASM_OUTPUT_ALIGNED_COMMON(FILE,NAME,SIZE,ALIGN) \
 500   picochip_output_aligned_common(FILE, NAME, SIZE, ALIGN)
 501
 502 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE,NAME,SIZE,ALIGN) \
 503   picochip_output_aligned_local(FILE, NAME, SIZE, ALIGN)
 504
 505 /* Output and Generation of Labels  */
 506
 507 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
 508   do { picochip_output_label(STREAM, NAME); } while (0);
 509
 510 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
 511   { picochip_output_labelref(STREAM, NAME); }
 512
 513 /* Format must match that of picochip_output_label. */
 514 #define ASM_GENERATE_INTERNAL_LABEL(STRING,PREFIX,NUM) \
 515  picochip_generate_internal_label(STRING,PREFIX,(long)NUM)
 516
 517 #define ASM_WEAKEN_LABEL(STREAM,NAME) picochip_weaken_label(STREAM,NAME);
 518
 519 /* Store in OUTPUT a string (made with alloca) containing an
 520    assembler-name for a local static variable named NAME.  LABELNO is
 521    an integer which is different for each call.  The assembler can't
 522    use periods to generate the name, so we use a ___ separator
 523    instead. */
 524
 525 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)  \
 526 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 15),    \
 527   sprintf ((OUTPUT), "%s___%lu", (NAME), (unsigned long)(LABELNO)))
 528
 529 /* Macros Controlling Initialization Routines  */
 530
 531 /* By defining this, the main function won't try to call `__main'. */
 532 #define HAS_INIT_SECTION
 533
 534 /* Output of Assembler Instructions  */
 535
 536 #define REGISTER_NAMES                                                  \
 537 {"R0",  "R1",  "R2",  "R3",                                             \
 538  "R4",  "R5",  "R6",  "R7",                                             \
 539  "R8",  "R9",  "R10", "R11",                                            \
 540  "R12", "FP", "R14", "R15",                                             \
 541  "acc0", "pseudoCC", "pseudoFP", "pseudoAP"}
 542
 543 #define ADDITIONAL_REGISTER_NAMES                                       \
 544 {                                                                       \
 545   { "R0",        0},                                                    \
 546   { "R1",        1},                                                    \
 547   { "R2",        2},                                                    \
 548   { "R3",        3},                                                    \
 549   { "R4",        4},                                                    \
 550   { "R5",        5},                                                    \
 551   { "R6",        6},                                                    \
 552   { "R7",        7},                                                    \
 553   { "R8",        8},                                                    \
 554   { "R9",        9},                                                    \
 555   { "R10",      10},                                                    \
 556   { "R11",      11},                                                    \
 557   { "R12",      12},                                                    \
 558   { "FP",       13},                                                    \
 559   { "R14",      14},                                                    \
 560   { "R15",      15},                                                    \
 561   { "acc0",     16},                                                    \
 562   { "sp",       12}, /* ABI stack pointer */                            \
 563   { "ln",       13}, /* arch link register */                           \
 564   { "ptr",      14}, /* arch constant pointer */                        \
 565   { "rc",       15}, /* arch constant register */                       \
 566   { "rz",       15}, /* arch zero */                                    \
 567 }
 568
 569 /* Final prescan insn is called just before an instruction is
 570    output.  In our case, we use this to detect the VLIW slot to which
 571    the instruction has been assigned, preparatory to generating the
 572    VLIW output in ASM_OUTPUT_OPCODE. */
 573 #define FINAL_PRESCAN_INSN(insn, operand, nop) \
 574   picochip_final_prescan_insn (insn, operand,nop)
 575
 576 #define ASM_OUTPUT_OPCODE(FILE,PTR) \
 577   { PTR = picochip_asm_output_opcode(FILE, PTR); }
 578
 579 #define PRINT_OPERAND(STREAM,X,CODE) \
 580   picochip_print_operand(STREAM, X, CODE)
 581
 582 #define PRINT_OPERAND_PUNCT_VALID_P(code) \
 583   (((code) == '|') || ((code) == '#') || ((code) == '>'))
 584
 585 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
 586   picochip_print_operand_address(STREAM,X)
 587
 588 /* Output of Dispatch Tables  */
 589
 590 /* Initialise a data memory location to an absolute code label.  Used
 591    for building switch statement jump tables.  Note - the format of the
 592    label must match that of the function picochip_output_label. */
 593 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
 594   fprintf (stream, ".initWord _L%d\n", value);
 595
 596 /* Assembler Commands for Alignment  */
 597
 598 #define ASM_OUTPUT_SKIP(STREAM,BYTES) \
 599   fprintf(STREAM, ".skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", BYTES);
 600 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \
 601   fprintf(STREAM, ".align %u\n", 1 << POWER);
 602
 603 /* The elaborator doesn't output zero bytes in the text section. */
 604 #define ASM_NO_SKIP_IN_TEXT 1
 605 \f
 606 /* Controlling Debugging Information Format  */
 607
 608 /* Macros Affecting All Debugging Formats  */
 609
 610 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
 611
 612 #define DWARF2_DEBUGGING_INFO
 613 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 614 #define DWARF2_FRAME_INFO 1
 615
 616 /* Generate .file/.loc directives, so that the assembler generates the
 617    line table. */
 618 #define DWARF2_ASM_LINE_DEBUG_INFO 1
 619 \f
 620 /* Miscellaneous Parameters  */
 621
 622 #define CASE_VECTOR_MODE HImode
 623 #define WORD_REGISTER_OPERATIONS
 624 #define LOAD_EXTEND_OP(MODE) ((MODE) == QImode ? SIGN_EXTEND : ZERO_EXTEND)
 625 #define MOVE_MAX 4
 626 #define SHIFT_COUNT_TRUNCATED 1
 627 #define Pmode HImode
 628 #define FUNCTION_MODE QImode
 629 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
 630
 631 #define ASM_LONG ":TODO:.word\t"
 632
 633 /* Define builtins for selected special-purpose instructions. */
 634 enum picochip_builtins
 635 {
 636   PICOCHIP_BUILTIN_SBC,
 637   PICOCHIP_BUILTIN_PUT,
 638   PICOCHIP_BUILTIN_GET,
 639   PICOCHIP_BUILTIN_TESTPORT,
 640   PICOCHIP_BUILTIN_COPYSW,
 641   PICOCHIP_BUILTIN_ADDS,
 642   PICOCHIP_BUILTIN_SUBS,
 643   PICOCHIP_BUILTIN_BREV,
 644   PICOCHIP_BUILTIN_BYTESWAP,
 645   PICOCHIP_BUILTIN_GET_ARRAY,
 646   PICOCHIP_BUILTIN_PUT_ARRAY,
 647   PICOCHIP_BUILTIN_TESTPORT_ARRAY,
 648   PICOCHIP_BUILTIN_ASRI,
 649   PICOCHIP_BUILTIN_HALT
 650 };
 651
 652 #define NO_DOLLAR_IN_LABEL 1
 653 #define NO_DOT_IN_LABEL 1
 654
 655 /* The assembler does support LEB128, despite the auto-configure test
 656    not detecting this. */
 657 #define HAVE_AS_LEB128 1
 658
 659 /* picochip-unknown-none target has no support of C99 runtime */
 660 #undef TARGET_LIBC_HAS_FUNCTION
 661 #define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function
 662
 663 /* The End */