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* config/rl78/rl78.h (enum reg_class): Remove real registers from
[official-gcc.git] / gcc / config / rl78 / rl78.h
blobcaa7f7f65413698216516947c1293169944689d2
1 /* GCC backend definitions for the Renesas RL78 processor.
2 Copyright (C) 2011-2015 Free Software Foundation, Inc.
3 Contributed by Red Hat.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20 \f
21
22 #define RL78_MUL_NONE (rl78_mul_type == MUL_NONE)
23 #define RL78_MUL_RL78 (rl78_mul_type == MUL_RL78)
24 #define RL78_MUL_G13 (rl78_mul_type == MUL_G13)
25
26 #define TARGET_CPU_CPP_BUILTINS() \
27 do \
28 { \
29 builtin_define ("__RL78__"); \
30 builtin_assert ("cpu=RL78"); \
31 if (RL78_MUL_RL78) \
32 builtin_define ("__RL78_MUL_RL78__"); \
33 if (RL78_MUL_G13) \
34 builtin_define ("__RL78_MUL_G13__"); \
35 if (TARGET_G10) \
36 builtin_define ("__RL78_G10__"); \
37 } \
38 while (0)
39
40 #undef STARTFILE_SPEC
41 #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s"
42
43 #undef ENDFILE_SPEC
44 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
45
46 #undef ASM_SPEC
47 #define ASM_SPEC "\
48 %{mrelax:-relax} \
49 %{mg10} \
50 "
51
52 #undef LINK_SPEC
53 #define LINK_SPEC "\
54 %{mrelax:-relax} \
55 %{!r:--gc-sections} \
56 "
57
58 #undef LIB_SPEC
59 #define LIB_SPEC " \
60 --start-group \
61 -lc \
62 -lsim \
63 %{fprofile-arcs|fprofile-generate|coverage:-lgcov} \
64 --end-group \
65 %{!T*: %{msim:%Trl78-sim.ld}%{!msim:%Trl78.ld}} \
66 "
67 \f
68
69 #define BITS_BIG_ENDIAN 0
70 #define BYTES_BIG_ENDIAN 0
71 #define WORDS_BIG_ENDIAN 0
72
73 #ifdef IN_LIBGCC2
74 /* This is to get correct SI and DI modes in libgcc2.c (32 and 64 bits). */
75 #define UNITS_PER_WORD 4
76 /* We have a problem with libgcc2. It only defines two versions of
77 each function, one for "int" and one for "long long". Ie it assumes
78 that "sizeof (int) == sizeof (long)". For the RL78 this is not true
79 and we need a third set of functions. We explicitly define
80 LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
81 to get the SI and DI versions from the libgcc2.c sources, and we
82 provide our own set of HI functions, which is why this
83 definition is surrounded by #ifndef..#endif. */
84 #ifndef LIBGCC2_UNITS_PER_WORD
85 #define LIBGCC2_UNITS_PER_WORD 4
86 #endif
87 #else
88 /* Actual width of a word, in units (bytes). */
89 #define UNITS_PER_WORD 1
90 #endif
91
92 #define SHORT_TYPE_SIZE 16
93 #define INT_TYPE_SIZE 16
94 #define LONG_TYPE_SIZE 32
95 #define LONG_LONG_TYPE_SIZE 64
96
97 #define FLOAT_TYPE_SIZE 32
98 #define DOUBLE_TYPE_SIZE 32 /*64*/
99 #define LONG_DOUBLE_TYPE_SIZE 64 /*DOUBLE_TYPE_SIZE*/
100
101 #define DEFAULT_SIGNED_CHAR 0
102
103 #define STRICT_ALIGNMENT 1
104 #define FUNCTION_BOUNDARY 8
105 #define BIGGEST_ALIGNMENT 16
106 #define STACK_BOUNDARY 16
107 #define PARM_BOUNDARY 16
108
109 #define STACK_GROWS_DOWNWARD 1
110 #define FRAME_GROWS_DOWNWARD 1
111 #define FIRST_PARM_OFFSET(FNDECL) 0
112
113 #define MAX_REGS_PER_ADDRESS 1
114
115 #define Pmode HImode
116 #define POINTER_SIZE 16
117 #undef SIZE_TYPE
118 #define SIZE_TYPE "unsigned int"
119 #undef PTRDIFF_TYPE
120 #define PTRDIFF_TYPE "int"
121 #undef WCHAR_TYPE
122 #define WCHAR_TYPE "long int"
123 #undef WCHAR_TYPE_SIZE
124 #define WCHAR_TYPE_SIZE BITS_PER_WORD
125 #define POINTERS_EXTEND_UNSIGNED 1
126 #define FUNCTION_MODE HImode
127 #define CASE_VECTOR_MODE Pmode
128 #define WORD_REGISTER_OPERATIONS 0
129 #define HAS_LONG_COND_BRANCH 0
130 #define HAS_LONG_UNCOND_BRANCH 0
131
132 #define MOVE_MAX 2
133 #define STARTING_FRAME_OFFSET 0
134
135 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
136
137 #define ADDR_SPACE_NEAR 1
138 #define ADDR_SPACE_FAR 2
139
140 #define HAVE_PRE_DECCREMENT 0
141 #define HAVE_POST_INCREMENT 0
142
143 #define MOVE_RATIO(SPEED) ((SPEED) ? 24 : 16)
144 #define SLOW_BYTE_ACCESS 0
145
146 #define STORE_FLAG_VALUE 1
147 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
148 \f
149
150 /* The RL78 has four register banks. Normal operation uses RB0 as
151 real registers, RB1 and RB2 as "virtual" registers (because we know
152 they'll be there, and not used as variables), and RB3 is reserved
153 for interrupt handlers. The virtual registers are accessed as
154 SADDRs:
155
156 FFEE0-FFEE7 RB0
157 FFEE8-FFEEF RB1
158 FFEF0-FFEF7 RB2
159 FFEF8-FFEFF RB3
160 */
161 #define REGISTER_NAMES \
162 { \
163 "x", "a", "c", "b", "e", "d", "l", "h", \
164 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
165 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
166 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
167 "sp", "ap", "psw", "es", "cs" \
168 }
169
170 #define ADDITIONAL_REGISTER_NAMES \
171 { \
172 { "ax", 0 }, \
173 { "bc", 2 }, \
174 { "de", 4 }, \
175 { "hl", 6 }, \
176 { "rp0", 0 }, \
177 { "rp1", 2 }, \
178 { "rp2", 4 }, \
179 { "rp3", 6 }, \
180 { "r0", 0 }, \
181 { "r1", 1 }, \
182 { "r2", 2 }, \
183 { "r3", 3 }, \
184 { "r4", 4 }, \
185 { "r5", 5 }, \
186 { "r6", 6 }, \
187 { "r7", 7 }, \
188 }
189
190 enum reg_class
191 {
192 NO_REGS, /* No registers in set. */
193 XREG,
194 AREG,
195 AXREG,
196 CREG,
197 BREG,
198 BCREG,
199 EREG,
200 DREG,
201 DEREG,
202 LREG,
203 HREG,
204 HLREG,
205 IDX_REGS,
206 QI_REGS,
207 SPREG,
208 R8W_REGS,
209 R10W_REGS,
210 INT_REGS,
211 V_REGS, /* Virtual registers. */
212 GR_REGS, /* Integer registers. */
213 PSWREG,
214 ALL_REGS, /* All registers. */
215 LIM_REG_CLASSES /* Max value + 1. */
216 };
217
218 #define REG_CLASS_NAMES \
219 { \
220 "NO_REGS", \
221 "XREG", \
222 "AREG", \
223 "AXREG", \
224 "CREG", \
225 "BREG", \
226 "BCREG", \
227 "EREG", \
228 "DREG", \
229 "DEREG", \
230 "LREG", \
231 "HREG", \
232 "HLREG", \
233 "IDX_REGS", \
234 "QI_REGS", \
235 "SPREG", \
236 "R8W_REGS", \
237 "R10W_REGS", \
238 "INT_REGS", \
239 "V_REGS", \
240 "GR_REGS", \
241 "PSWREG", \
242 "ALL_REGS" \
243 }
244
245 /* Note that no class may include the second register in $fp, because
246 we treat $fp as a single HImode register. */
247 #define REG_CLASS_CONTENTS \
248 { \
249 { 0x00000000, 0x00000000 }, /* No registers, */ \
250 { 0x00000001, 0x00000000 }, \
251 { 0x00000002, 0x00000000 }, \
252 { 0x00000003, 0x00000000 }, \
253 { 0x00000004, 0x00000000 }, \
254 { 0x00000008, 0x00000000 }, \
255 { 0x0000000c, 0x00000000 }, \
256 { 0x00000010, 0x00000000 }, \
257 { 0x00000020, 0x00000000 }, \
258 { 0x00000030, 0x00000000 }, \
259 { 0x00000040, 0x00000000 }, \
260 { 0x00000080, 0x00000000 }, \
261 { 0x000000c0, 0x00000000 }, \
262 { 0x0000000c, 0x00000000 }, /* B and C - index regs. */ \
263 { 0x000000ff, 0x00000000 }, /* all real registers. */ \
264 { 0x00000000, 0x00000001 }, /* SP */ \
265 { 0x00000300, 0x00000000 }, /* R8 - HImode */ \
266 { 0x00000c00, 0x00000000 }, /* R10 - HImode */ \
267 { 0xff000000, 0x00000000 }, /* INT - HImode */ \
268 { 0xff7fff00, 0x00000000 }, /* Virtual registers. */ \
269 { 0xff7fff00, 0x00000002 }, /* General registers. */ \
270 { 0x04000000, 0x00000004 }, /* PSW. */ \
271 { 0xff7fffff, 0x0000001f } /* All registers. */ \
272 }
273
274 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
275 #define N_REG_CLASSES (int) LIM_REG_CLASSES
276 #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \
277 + UNITS_PER_WORD - 1) \
278 / UNITS_PER_WORD)
279
280 #define GENERAL_REGS GR_REGS
281 #define BASE_REG_CLASS V_REGS
282 #define INDEX_REG_CLASS V_REGS
283
284 #define FIRST_PSEUDO_REGISTER 37
285
286 #define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER \
287 ? GR_REGS : NO_REGS)
288
289 #define FRAME_POINTER_REGNUM 22
290 #define STACK_POINTER_REGNUM 32
291 #define ARG_POINTER_REGNUM 33
292 #define CC_REGNUM 34
293 #define FUNC_RETURN_REGNUM 8
294 #define STATIC_CHAIN_REGNUM 14
295
296 /* Trampolines are implemented with a separate data stack. The memory
297 on stack only holds the function pointer for the chosen stub.
298 */
299
300 #define TRAMPOLINE_SIZE 4
301 #define TRAMPOLINE_ALIGNMENT 16
302
303 #define ELIMINABLE_REGS \
304 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
305 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
306 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
307
308 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
309 (OFFSET) = rl78_initial_elimination_offset ((FROM), (TO))
310
311
312 #define FUNCTION_ARG_REGNO_P(N) 0
313 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8)
314 #define DEFAULT_PCC_STRUCT_RETURN 0
315
316 #define FIXED_REGISTERS \
317 { \
318 1,1,1,1, 1,1,1,1, \
319 0,0,0,0, 0,0,0,0, \
320 0,0,0,0, 0,0,1,1, \
321 1,1,1,1, 1,1,1,1, \
322 0, 1, 0, 1, 1 \
323 }
324
325 #define CALL_USED_REGISTERS \
326 { \
327 1,1,1,1, 1,1,1,1, \
328 1,1,1,1, 1,1,1,1, \
329 0,0,0,0, 0,0,1,1, \
330 1,1,1,1, 1,1,1,1, \
331 0, 1, 1, 1, 1 \
332 }
333
334 #define LIBCALL_VALUE(MODE) \
335 gen_rtx_REG ((MODE), \
336 FUNC_RETURN_REGNUM)
337
338 /* Order of allocation of registers. */
339
340 #define REG_ALLOC_ORDER \
341 { 8, 9, 10, 11, 12, 13, 14, 15, \
342 16, 17, 18, 19, 20, 21, 22, 23, \
343 0, 1, 6, 7, 2, 3, 4, 5, \
344 24, 25, 26, 27, 28, 29, 30, 31, \
345 32, 33, 34 \
346 }
347
348 #define REGNO_IN_RANGE(REGNO, MIN, MAX) \
349 (IN_RANGE ((REGNO), (MIN), (MAX)) \
350 || (reg_renumber != NULL \
351 && reg_renumber[(REGNO)] >= (MIN) \
352 && reg_renumber[(REGNO)] <= (MAX)))
353
354 #ifdef REG_OK_STRICT
355 #define REGNO_OK_FOR_BASE_P(regno) REGNO_IN_RANGE (regno, 16, 31)
356 #else
357 #define REGNO_OK_FOR_BASE_P(regno) 1
358 #endif
359
360 #define REGNO_OK_FOR_INDEX_P(regno) REGNO_OK_FOR_BASE_P (regno)
361
362 #define REGNO_MODE_CODE_OK_FOR_BASE_P(regno, mode, address_space, outer_code, index_code) \
363 rl78_regno_mode_code_ok_for_base_p (regno, mode, address_space, outer_code, index_code)
364
365 #define MODE_CODE_BASE_REG_CLASS(mode, address_space, outer_code, index_code) \
366 rl78_mode_code_base_reg_class (mode, address_space, outer_code, index_code)
367
368 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
369 ((COUNT) == 0 \
370 ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (HImode, arg_pointer_rtx, GEN_INT (-4))) \
371 : NULL_RTX)
372
373 #define INCOMING_RETURN_ADDR_RTX gen_rtx_MEM (Pmode, stack_pointer_rtx)
374
375 #define ACCUMULATE_OUTGOING_ARGS 1
376
377 typedef unsigned int CUMULATIVE_ARGS;
378
379 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
380 (CUM) = 0
381
382 \f
383 /* FIXME */
384 #define NO_PROFILE_COUNTERS 1
385 #define PROFILE_BEFORE_PROLOGUE 1
386
387 #define FUNCTION_PROFILER(FILE, LABELNO) \
388 fprintf (FILE, "\tbsr\t__mcount\n");
389 \f
390
391 #define HARD_REGNO_NREGS(REGNO, MODE) \
392 rl78_hard_regno_nregs (REGNO, MODE)
393
394 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
395 rl78_hard_regno_mode_ok (REGNO, MODE)
396
397 #define MODES_TIEABLE_P(MODE1, MODE2) \
398 ( ( GET_MODE_CLASS (MODE1) == MODE_FLOAT \
399 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
400 == ( GET_MODE_CLASS (MODE2) == MODE_FLOAT \
401 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
402 \f
403
404 #define TEXT_SECTION_ASM_OP ".text"
405 #define DATA_SECTION_ASM_OP ".data"
406 #define BSS_SECTION_ASM_OP ".bss"
407 #define CTORS_SECTION_ASM_OP ".section \".ctors\",\"a\""
408 #define DTORS_SECTION_ASM_OP ".section \".dtors\",\"a\""
409
410 #define ASM_COMMENT_START " ;"
411 #define ASM_APP_ON ""
412 #define ASM_APP_OFF ""
413 #define LOCAL_LABEL_PREFIX ".L"
414 #undef USER_LABEL_PREFIX
415 #define USER_LABEL_PREFIX "_"
416
417 #define GLOBAL_ASM_OP "\t.global\t"
418
419 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
420 fprintf (FILE, "\t.long .L%d\n", VALUE)
421
422 /* This is how to output an element of a case-vector that is relative.
423 Note: The local label referenced by the "3b" below is emitted by
424 the tablejump insn. */
425
426 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
427 fprintf (FILE, "\t.long .L%d - 1b\n", VALUE)
428
429
430 #define ASM_OUTPUT_SYMBOL_REF(FILE, SYM) rl78_output_symbol_ref ((FILE), (SYM))
431
432 #define ASM_OUTPUT_LABELREF(FILE, SYM) rl78_output_labelref ((FILE), (SYM))
433
434 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
435 rl78_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
436
437 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
438 rl78_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
439
440 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
441 do \
442 { \
443 if ((LOG) == 0) \
444 break; \
445 fprintf (STREAM, "\t.balign %d\n", 1 << (LOG)); \
446 } \
447 while (0)
448
449 /* For PIC put jump tables into the text section so that the offsets that
450 they contain are always computed between two same-section symbols. */
451 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
452 \f
453 /* This is a version of REG_P that also returns TRUE for SUBREGs. */
454 #define RL78_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
455
456 /* Like REG_P except that this macro is true for SET expressions. */
457 #define SET_P(rtl) (GET_CODE (rtl) == SET)
458 \f
459 #undef PREFERRED_DEBUGGING_TYPE
460 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
461
462 #undef DWARF2_ADDR_SIZE
463 #define DWARF2_ADDR_SIZE 4
464
465 #define DWARF2_ASM_LINE_DEBUG_INFO 1
466
467 #define EXIT_IGNORE_STACK 0
468 #define INCOMING_FRAME_SP_OFFSET 4
469 \f
470
471 #define BRANCH_COST(SPEED,PREDICT) 1
472 #define REGISTER_MOVE_COST(MODE,FROM,TO) 2
473
474 #define EH_RETURN_DATA_REGNO(N) (N < 2 ? (8+(N)*2) : INVALID_REGNUM)
475 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (HImode, 20)
476
477 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) DW_EH_PE_udata4
478
479 /* NOTE: defined but zero means dwarf2 debugging, but sjlj EH. */
480 #define DWARF2_UNWIND_INFO 0
481
482 #define REGISTER_TARGET_PRAGMAS() rl78_register_pragmas()
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