mips-protos.h (mips_expand_before_return): Declare.
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1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
26 #include "config.h"
27 #include "system.h"
28 #include "coretypes.h"
29 #include "tm.h"
30 #include <signal.h>
31 #include "rtl.h"
32 #include "regs.h"
33 #include "hard-reg-set.h"
34 #include "real.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
38 #include "recog.h"
39 #include "toplev.h"
40 #include "output.h"
41 #include "tree.h"
42 #include "function.h"
43 #include "expr.h"
44 #include "optabs.h"
45 #include "flags.h"
46 #include "reload.h"
47 #include "tm_p.h"
48 #include "ggc.h"
49 #include "gstab.h"
50 #include "hashtab.h"
51 #include "debug.h"
52 #include "target.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
59 #include "bitmap.h"
60 #include "diagnostic.h"
62 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
70 XVECEXP (X, 0, 0)
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
91 part of the frame. */
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
99 (INSN_P (INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
110 : (INSN))
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
116 : (INSN))
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Classifies an address.
130 ADDRESS_REG
131 A natural register + offset address. The register satisfies
132 mips_valid_base_register_p and the offset is a const_arith_operand.
134 ADDRESS_LO_SUM
135 A LO_SUM rtx. The first operand is a valid base register and
136 the second operand is a symbolic address.
138 ADDRESS_CONST_INT
139 A signed 16-bit constant address.
141 ADDRESS_SYMBOLIC:
142 A constant symbolic address. */
143 enum mips_address_type {
144 ADDRESS_REG,
145 ADDRESS_LO_SUM,
146 ADDRESS_CONST_INT,
147 ADDRESS_SYMBOLIC
150 /* Macros to create an enumeration identifier for a function prototype. */
151 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
152 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
153 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
154 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
156 /* Classifies the prototype of a built-in function. */
157 enum mips_function_type {
158 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
159 #include "config/mips/mips-ftypes.def"
160 #undef DEF_MIPS_FTYPE
161 MIPS_MAX_FTYPE_MAX
164 /* Specifies how a built-in function should be converted into rtl. */
165 enum mips_builtin_type {
166 /* The function corresponds directly to an .md pattern. The return
167 value is mapped to operand 0 and the arguments are mapped to
168 operands 1 and above. */
169 MIPS_BUILTIN_DIRECT,
171 /* The function corresponds directly to an .md pattern. There is no return
172 value and the arguments are mapped to operands 0 and above. */
173 MIPS_BUILTIN_DIRECT_NO_TARGET,
175 /* The function corresponds to a comparison instruction followed by
176 a mips_cond_move_tf_ps pattern. The first two arguments are the
177 values to compare and the second two arguments are the vector
178 operands for the movt.ps or movf.ps instruction (in assembly order). */
179 MIPS_BUILTIN_MOVF,
180 MIPS_BUILTIN_MOVT,
182 /* The function corresponds to a V2SF comparison instruction. Operand 0
183 of this instruction is the result of the comparison, which has mode
184 CCV2 or CCV4. The function arguments are mapped to operands 1 and
185 above. The function's return value is an SImode boolean that is
186 true under the following conditions:
188 MIPS_BUILTIN_CMP_ANY: one of the registers is true
189 MIPS_BUILTIN_CMP_ALL: all of the registers are true
190 MIPS_BUILTIN_CMP_LOWER: the first register is true
191 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
192 MIPS_BUILTIN_CMP_ANY,
193 MIPS_BUILTIN_CMP_ALL,
194 MIPS_BUILTIN_CMP_UPPER,
195 MIPS_BUILTIN_CMP_LOWER,
197 /* As above, but the instruction only sets a single $fcc register. */
198 MIPS_BUILTIN_CMP_SINGLE,
200 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
201 MIPS_BUILTIN_BPOSGE32
204 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
205 #define MIPS_FP_CONDITIONS(MACRO) \
206 MACRO (f), \
207 MACRO (un), \
208 MACRO (eq), \
209 MACRO (ueq), \
210 MACRO (olt), \
211 MACRO (ult), \
212 MACRO (ole), \
213 MACRO (ule), \
214 MACRO (sf), \
215 MACRO (ngle), \
216 MACRO (seq), \
217 MACRO (ngl), \
218 MACRO (lt), \
219 MACRO (nge), \
220 MACRO (le), \
221 MACRO (ngt)
223 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
224 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
225 enum mips_fp_condition {
226 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
229 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
230 #define STRINGIFY(X) #X
231 static const char *const mips_fp_conditions[] = {
232 MIPS_FP_CONDITIONS (STRINGIFY)
235 /* Information about a function's frame layout. */
236 struct mips_frame_info GTY(()) {
237 /* The size of the frame in bytes. */
238 HOST_WIDE_INT total_size;
240 /* The number of bytes allocated to variables. */
241 HOST_WIDE_INT var_size;
243 /* The number of bytes allocated to outgoing function arguments. */
244 HOST_WIDE_INT args_size;
246 /* The number of bytes allocated to the .cprestore slot, or 0 if there
247 is no such slot. */
248 HOST_WIDE_INT cprestore_size;
250 /* Bit X is set if the function saves or restores GPR X. */
251 unsigned int mask;
253 /* Likewise FPR X. */
254 unsigned int fmask;
256 /* The number of GPRs and FPRs saved. */
257 unsigned int num_gp;
258 unsigned int num_fp;
260 /* The offset of the topmost GPR and FPR save slots from the top of
261 the frame, or zero if no such slots are needed. */
262 HOST_WIDE_INT gp_save_offset;
263 HOST_WIDE_INT fp_save_offset;
265 /* Likewise, but giving offsets from the bottom of the frame. */
266 HOST_WIDE_INT gp_sp_offset;
267 HOST_WIDE_INT fp_sp_offset;
269 /* The offset of arg_pointer_rtx from frame_pointer_rtx. */
270 HOST_WIDE_INT arg_pointer_offset;
272 /* The offset of hard_frame_pointer_rtx from frame_pointer_rtx. */
273 HOST_WIDE_INT hard_frame_pointer_offset;
276 struct machine_function GTY(()) {
277 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
278 rtx mips16_gp_pseudo_rtx;
280 /* The number of extra stack bytes taken up by register varargs.
281 This area is allocated by the callee at the very top of the frame. */
282 int varargs_size;
284 /* The current frame information, calculated by mips_compute_frame_info. */
285 struct mips_frame_info frame;
287 /* The register to use as the function's global pointer. */
288 unsigned int global_pointer;
290 /* True if mips_adjust_insn_length should ignore an instruction's
291 hazard attribute. */
292 bool ignore_hazard_length_p;
294 /* True if the whole function is suitable for .set noreorder and
295 .set nomacro. */
296 bool all_noreorder_p;
298 /* True if the function is known to have an instruction that needs $gp. */
299 bool has_gp_insn_p;
301 /* True if we have emitted an instruction to initialize
302 mips16_gp_pseudo_rtx. */
303 bool initialized_mips16_gp_pseudo_p;
306 /* Information about a single argument. */
307 struct mips_arg_info {
308 /* True if the argument is passed in a floating-point register, or
309 would have been if we hadn't run out of registers. */
310 bool fpr_p;
312 /* The number of words passed in registers, rounded up. */
313 unsigned int reg_words;
315 /* For EABI, the offset of the first register from GP_ARG_FIRST or
316 FP_ARG_FIRST. For other ABIs, the offset of the first register from
317 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
318 comment for details).
320 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
321 on the stack. */
322 unsigned int reg_offset;
324 /* The number of words that must be passed on the stack, rounded up. */
325 unsigned int stack_words;
327 /* The offset from the start of the stack overflow area of the argument's
328 first stack word. Only meaningful when STACK_WORDS is nonzero. */
329 unsigned int stack_offset;
332 /* Information about an address described by mips_address_type.
334 ADDRESS_CONST_INT
335 No fields are used.
337 ADDRESS_REG
338 REG is the base register and OFFSET is the constant offset.
340 ADDRESS_LO_SUM
341 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
342 is the type of symbol it references.
344 ADDRESS_SYMBOLIC
345 SYMBOL_TYPE is the type of symbol that the address references. */
346 struct mips_address_info {
347 enum mips_address_type type;
348 rtx reg;
349 rtx offset;
350 enum mips_symbol_type symbol_type;
353 /* One stage in a constant building sequence. These sequences have
354 the form:
356 A = VALUE[0]
357 A = A CODE[1] VALUE[1]
358 A = A CODE[2] VALUE[2]
361 where A is an accumulator, each CODE[i] is a binary rtl operation
362 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
363 struct mips_integer_op {
364 enum rtx_code code;
365 unsigned HOST_WIDE_INT value;
368 /* The largest number of operations needed to load an integer constant.
369 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
370 When the lowest bit is clear, we can try, but reject a sequence with
371 an extra SLL at the end. */
372 #define MIPS_MAX_INTEGER_OPS 7
374 /* Information about a MIPS16e SAVE or RESTORE instruction. */
375 struct mips16e_save_restore_info {
376 /* The number of argument registers saved by a SAVE instruction.
377 0 for RESTORE instructions. */
378 unsigned int nargs;
380 /* Bit X is set if the instruction saves or restores GPR X. */
381 unsigned int mask;
383 /* The total number of bytes to allocate. */
384 HOST_WIDE_INT size;
387 /* Global variables for machine-dependent things. */
389 /* The -G setting, or the configuration's default small-data limit if
390 no -G option is given. */
391 static unsigned int mips_small_data_threshold;
393 /* The number of file directives written by mips_output_filename. */
394 int num_source_filenames;
396 /* The name that appeared in the last .file directive written by
397 mips_output_filename, or "" if mips_output_filename hasn't
398 written anything yet. */
399 const char *current_function_file = "";
401 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
402 int sdb_label_count;
404 /* Arrays that map GCC register numbers to debugger register numbers. */
405 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
406 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
408 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
409 int set_noreorder;
410 int set_nomacro;
411 static int set_noat;
413 /* True if we're writing out a branch-likely instruction rather than a
414 normal branch. */
415 static bool mips_branch_likely;
417 /* The operands passed to the last cmpMM expander. */
418 rtx cmp_operands[2];
420 /* The current instruction-set architecture. */
421 enum processor_type mips_arch;
422 const struct mips_cpu_info *mips_arch_info;
424 /* The processor that we should tune the code for. */
425 enum processor_type mips_tune;
426 const struct mips_cpu_info *mips_tune_info;
428 /* The ISA level associated with mips_arch. */
429 int mips_isa;
431 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
432 static const struct mips_cpu_info *mips_isa_option_info;
434 /* Which ABI to use. */
435 int mips_abi = MIPS_ABI_DEFAULT;
437 /* Which cost information to use. */
438 const struct mips_rtx_cost_data *mips_cost;
440 /* The ambient target flags, excluding MASK_MIPS16. */
441 static int mips_base_target_flags;
443 /* True if MIPS16 is the default mode. */
444 static bool mips_base_mips16;
446 /* The ambient values of other global variables. */
447 static int mips_base_delayed_branch; /* flag_delayed_branch */
448 static int mips_base_schedule_insns; /* flag_schedule_insns */
449 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
450 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
451 static int mips_base_align_loops; /* align_loops */
452 static int mips_base_align_jumps; /* align_jumps */
453 static int mips_base_align_functions; /* align_functions */
455 /* The -mcode-readable setting. */
456 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
458 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
459 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
461 /* Index C is true if character C is a valid PRINT_OPERAND punctation
462 character. */
463 bool mips_print_operand_punct[256];
465 static GTY (()) int mips_output_filename_first_time = 1;
467 /* mips_split_p[X] is true if symbols of type X can be split by
468 mips_split_symbol. */
469 bool mips_split_p[NUM_SYMBOL_TYPES];
471 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
472 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
473 if they are matched by a special .md file pattern. */
474 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
476 /* Likewise for HIGHs. */
477 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
479 /* Index R is the smallest register class that contains register R. */
480 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
481 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
482 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
483 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
484 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
485 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
486 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
487 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
488 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
489 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
490 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
491 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
492 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
493 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
494 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
495 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
496 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
497 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
498 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
499 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
500 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
501 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
502 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
503 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
504 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
505 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
506 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
507 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
508 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
509 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
510 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
511 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
512 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
513 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
514 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
515 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
516 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
517 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
518 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
519 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
520 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
521 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
522 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
523 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
524 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
525 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
526 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
527 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
530 /* The value of TARGET_ATTRIBUTE_TABLE. */
531 const struct attribute_spec mips_attribute_table[] = {
532 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
533 { "long_call", 0, 0, false, true, true, NULL },
534 { "far", 0, 0, false, true, true, NULL },
535 { "near", 0, 0, false, true, true, NULL },
536 /* We would really like to treat "mips16" and "nomips16" as type
537 attributes, but GCC doesn't provide the hooks we need to support
538 the right conversion rules. As declaration attributes, they affect
539 code generation but don't carry other semantics. */
540 { "mips16", 0, 0, true, false, false, NULL },
541 { "nomips16", 0, 0, true, false, false, NULL },
542 { NULL, 0, 0, false, false, false, NULL }
545 /* A table describing all the processors GCC knows about. Names are
546 matched in the order listed. The first mention of an ISA level is
547 taken as the canonical name for that ISA.
549 To ease comparison, please keep this table in the same order
550 as GAS's mips_cpu_info_table. Please also make sure that
551 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
552 options correctly. */
553 static const struct mips_cpu_info mips_cpu_info_table[] = {
554 /* Entries for generic ISAs. */
555 { "mips1", PROCESSOR_R3000, 1, 0 },
556 { "mips2", PROCESSOR_R6000, 2, 0 },
557 { "mips3", PROCESSOR_R4000, 3, 0 },
558 { "mips4", PROCESSOR_R8000, 4, 0 },
559 /* Prefer not to use branch-likely instructions for generic MIPS32rX
560 and MIPS64rX code. The instructions were officially deprecated
561 in revisions 2 and earlier, but revision 3 is likely to downgrade
562 that to a recommendation to avoid the instructions in code that
563 isn't tuned to a specific processor. */
564 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
565 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
566 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
568 /* MIPS I processors. */
569 { "r3000", PROCESSOR_R3000, 1, 0 },
570 { "r2000", PROCESSOR_R3000, 1, 0 },
571 { "r3900", PROCESSOR_R3900, 1, 0 },
573 /* MIPS II processors. */
574 { "r6000", PROCESSOR_R6000, 2, 0 },
576 /* MIPS III processors. */
577 { "r4000", PROCESSOR_R4000, 3, 0 },
578 { "vr4100", PROCESSOR_R4100, 3, 0 },
579 { "vr4111", PROCESSOR_R4111, 3, 0 },
580 { "vr4120", PROCESSOR_R4120, 3, 0 },
581 { "vr4130", PROCESSOR_R4130, 3, 0 },
582 { "vr4300", PROCESSOR_R4300, 3, 0 },
583 { "r4400", PROCESSOR_R4000, 3, 0 },
584 { "r4600", PROCESSOR_R4600, 3, 0 },
585 { "orion", PROCESSOR_R4600, 3, 0 },
586 { "r4650", PROCESSOR_R4650, 3, 0 },
587 /* ST Loongson 2E/2F processors. */
588 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
589 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
591 /* MIPS IV processors. */
592 { "r8000", PROCESSOR_R8000, 4, 0 },
593 { "vr5000", PROCESSOR_R5000, 4, 0 },
594 { "vr5400", PROCESSOR_R5400, 4, 0 },
595 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
596 { "rm7000", PROCESSOR_R7000, 4, 0 },
597 { "rm9000", PROCESSOR_R9000, 4, 0 },
599 /* MIPS32 processors. */
600 { "4kc", PROCESSOR_4KC, 32, 0 },
601 { "4km", PROCESSOR_4KC, 32, 0 },
602 { "4kp", PROCESSOR_4KP, 32, 0 },
603 { "4ksc", PROCESSOR_4KC, 32, 0 },
605 /* MIPS32 Release 2 processors. */
606 { "m4k", PROCESSOR_M4K, 33, 0 },
607 { "4kec", PROCESSOR_4KC, 33, 0 },
608 { "4kem", PROCESSOR_4KC, 33, 0 },
609 { "4kep", PROCESSOR_4KP, 33, 0 },
610 { "4ksd", PROCESSOR_4KC, 33, 0 },
612 { "24kc", PROCESSOR_24KC, 33, 0 },
613 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
614 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
615 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
616 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
617 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
619 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
620 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
621 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
622 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
623 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
624 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
626 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
627 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
628 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
629 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
630 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
631 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
633 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
634 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
635 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
636 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
637 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
638 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
639 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
641 /* MIPS64 processors. */
642 { "5kc", PROCESSOR_5KC, 64, 0 },
643 { "5kf", PROCESSOR_5KF, 64, 0 },
644 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
645 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
646 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
647 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
650 /* Default costs. If these are used for a processor we should look
651 up the actual costs. */
652 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
653 COSTS_N_INSNS (7), /* fp_mult_sf */ \
654 COSTS_N_INSNS (8), /* fp_mult_df */ \
655 COSTS_N_INSNS (23), /* fp_div_sf */ \
656 COSTS_N_INSNS (36), /* fp_div_df */ \
657 COSTS_N_INSNS (10), /* int_mult_si */ \
658 COSTS_N_INSNS (10), /* int_mult_di */ \
659 COSTS_N_INSNS (69), /* int_div_si */ \
660 COSTS_N_INSNS (69), /* int_div_di */ \
661 2, /* branch_cost */ \
662 4 /* memory_latency */
664 /* Floating-point costs for processors without an FPU. Just assume that
665 all floating-point libcalls are very expensive. */
666 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
667 COSTS_N_INSNS (256), /* fp_mult_sf */ \
668 COSTS_N_INSNS (256), /* fp_mult_df */ \
669 COSTS_N_INSNS (256), /* fp_div_sf */ \
670 COSTS_N_INSNS (256) /* fp_div_df */
672 /* Costs to use when optimizing for size. */
673 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
674 COSTS_N_INSNS (1), /* fp_add */
675 COSTS_N_INSNS (1), /* fp_mult_sf */
676 COSTS_N_INSNS (1), /* fp_mult_df */
677 COSTS_N_INSNS (1), /* fp_div_sf */
678 COSTS_N_INSNS (1), /* fp_div_df */
679 COSTS_N_INSNS (1), /* int_mult_si */
680 COSTS_N_INSNS (1), /* int_mult_di */
681 COSTS_N_INSNS (1), /* int_div_si */
682 COSTS_N_INSNS (1), /* int_div_di */
683 2, /* branch_cost */
684 4 /* memory_latency */
687 /* Costs to use when optimizing for speed, indexed by processor. */
688 static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
689 { /* R3000 */
690 COSTS_N_INSNS (2), /* fp_add */
691 COSTS_N_INSNS (4), /* fp_mult_sf */
692 COSTS_N_INSNS (5), /* fp_mult_df */
693 COSTS_N_INSNS (12), /* fp_div_sf */
694 COSTS_N_INSNS (19), /* fp_div_df */
695 COSTS_N_INSNS (12), /* int_mult_si */
696 COSTS_N_INSNS (12), /* int_mult_di */
697 COSTS_N_INSNS (35), /* int_div_si */
698 COSTS_N_INSNS (35), /* int_div_di */
699 1, /* branch_cost */
700 4 /* memory_latency */
702 { /* 4KC */
703 SOFT_FP_COSTS,
704 COSTS_N_INSNS (6), /* int_mult_si */
705 COSTS_N_INSNS (6), /* int_mult_di */
706 COSTS_N_INSNS (36), /* int_div_si */
707 COSTS_N_INSNS (36), /* int_div_di */
708 1, /* branch_cost */
709 4 /* memory_latency */
711 { /* 4KP */
712 SOFT_FP_COSTS,
713 COSTS_N_INSNS (36), /* int_mult_si */
714 COSTS_N_INSNS (36), /* int_mult_di */
715 COSTS_N_INSNS (37), /* int_div_si */
716 COSTS_N_INSNS (37), /* int_div_di */
717 1, /* branch_cost */
718 4 /* memory_latency */
720 { /* 5KC */
721 SOFT_FP_COSTS,
722 COSTS_N_INSNS (4), /* int_mult_si */
723 COSTS_N_INSNS (11), /* int_mult_di */
724 COSTS_N_INSNS (36), /* int_div_si */
725 COSTS_N_INSNS (68), /* int_div_di */
726 1, /* branch_cost */
727 4 /* memory_latency */
729 { /* 5KF */
730 COSTS_N_INSNS (4), /* fp_add */
731 COSTS_N_INSNS (4), /* fp_mult_sf */
732 COSTS_N_INSNS (5), /* fp_mult_df */
733 COSTS_N_INSNS (17), /* fp_div_sf */
734 COSTS_N_INSNS (32), /* fp_div_df */
735 COSTS_N_INSNS (4), /* int_mult_si */
736 COSTS_N_INSNS (11), /* int_mult_di */
737 COSTS_N_INSNS (36), /* int_div_si */
738 COSTS_N_INSNS (68), /* int_div_di */
739 1, /* branch_cost */
740 4 /* memory_latency */
742 { /* 20KC */
743 COSTS_N_INSNS (4), /* fp_add */
744 COSTS_N_INSNS (4), /* fp_mult_sf */
745 COSTS_N_INSNS (5), /* fp_mult_df */
746 COSTS_N_INSNS (17), /* fp_div_sf */
747 COSTS_N_INSNS (32), /* fp_div_df */
748 COSTS_N_INSNS (4), /* int_mult_si */
749 COSTS_N_INSNS (7), /* int_mult_di */
750 COSTS_N_INSNS (42), /* int_div_si */
751 COSTS_N_INSNS (72), /* int_div_di */
752 1, /* branch_cost */
753 4 /* memory_latency */
755 { /* 24KC */
756 SOFT_FP_COSTS,
757 COSTS_N_INSNS (5), /* int_mult_si */
758 COSTS_N_INSNS (5), /* int_mult_di */
759 COSTS_N_INSNS (41), /* int_div_si */
760 COSTS_N_INSNS (41), /* int_div_di */
761 1, /* branch_cost */
762 4 /* memory_latency */
764 { /* 24KF2_1 */
765 COSTS_N_INSNS (8), /* fp_add */
766 COSTS_N_INSNS (8), /* fp_mult_sf */
767 COSTS_N_INSNS (10), /* fp_mult_df */
768 COSTS_N_INSNS (34), /* fp_div_sf */
769 COSTS_N_INSNS (64), /* fp_div_df */
770 COSTS_N_INSNS (5), /* int_mult_si */
771 COSTS_N_INSNS (5), /* int_mult_di */
772 COSTS_N_INSNS (41), /* int_div_si */
773 COSTS_N_INSNS (41), /* int_div_di */
774 1, /* branch_cost */
775 4 /* memory_latency */
777 { /* 24KF1_1 */
778 COSTS_N_INSNS (4), /* fp_add */
779 COSTS_N_INSNS (4), /* fp_mult_sf */
780 COSTS_N_INSNS (5), /* fp_mult_df */
781 COSTS_N_INSNS (17), /* fp_div_sf */
782 COSTS_N_INSNS (32), /* fp_div_df */
783 COSTS_N_INSNS (5), /* int_mult_si */
784 COSTS_N_INSNS (5), /* int_mult_di */
785 COSTS_N_INSNS (41), /* int_div_si */
786 COSTS_N_INSNS (41), /* int_div_di */
787 1, /* branch_cost */
788 4 /* memory_latency */
790 { /* 74KC */
791 SOFT_FP_COSTS,
792 COSTS_N_INSNS (5), /* int_mult_si */
793 COSTS_N_INSNS (5), /* int_mult_di */
794 COSTS_N_INSNS (41), /* int_div_si */
795 COSTS_N_INSNS (41), /* int_div_di */
796 1, /* branch_cost */
797 4 /* memory_latency */
799 { /* 74KF2_1 */
800 COSTS_N_INSNS (8), /* fp_add */
801 COSTS_N_INSNS (8), /* fp_mult_sf */
802 COSTS_N_INSNS (10), /* fp_mult_df */
803 COSTS_N_INSNS (34), /* fp_div_sf */
804 COSTS_N_INSNS (64), /* fp_div_df */
805 COSTS_N_INSNS (5), /* int_mult_si */
806 COSTS_N_INSNS (5), /* int_mult_di */
807 COSTS_N_INSNS (41), /* int_div_si */
808 COSTS_N_INSNS (41), /* int_div_di */
809 1, /* branch_cost */
810 4 /* memory_latency */
812 { /* 74KF1_1 */
813 COSTS_N_INSNS (4), /* fp_add */
814 COSTS_N_INSNS (4), /* fp_mult_sf */
815 COSTS_N_INSNS (5), /* fp_mult_df */
816 COSTS_N_INSNS (17), /* fp_div_sf */
817 COSTS_N_INSNS (32), /* fp_div_df */
818 COSTS_N_INSNS (5), /* int_mult_si */
819 COSTS_N_INSNS (5), /* int_mult_di */
820 COSTS_N_INSNS (41), /* int_div_si */
821 COSTS_N_INSNS (41), /* int_div_di */
822 1, /* branch_cost */
823 4 /* memory_latency */
825 { /* 74KF3_2 */
826 COSTS_N_INSNS (6), /* fp_add */
827 COSTS_N_INSNS (6), /* fp_mult_sf */
828 COSTS_N_INSNS (7), /* fp_mult_df */
829 COSTS_N_INSNS (25), /* fp_div_sf */
830 COSTS_N_INSNS (48), /* fp_div_df */
831 COSTS_N_INSNS (5), /* int_mult_si */
832 COSTS_N_INSNS (5), /* int_mult_di */
833 COSTS_N_INSNS (41), /* int_div_si */
834 COSTS_N_INSNS (41), /* int_div_di */
835 1, /* branch_cost */
836 4 /* memory_latency */
838 { /* Loongson-2E */
839 DEFAULT_COSTS
841 { /* Loongson-2F */
842 DEFAULT_COSTS
844 { /* M4k */
845 DEFAULT_COSTS
847 { /* R3900 */
848 COSTS_N_INSNS (2), /* fp_add */
849 COSTS_N_INSNS (4), /* fp_mult_sf */
850 COSTS_N_INSNS (5), /* fp_mult_df */
851 COSTS_N_INSNS (12), /* fp_div_sf */
852 COSTS_N_INSNS (19), /* fp_div_df */
853 COSTS_N_INSNS (2), /* int_mult_si */
854 COSTS_N_INSNS (2), /* int_mult_di */
855 COSTS_N_INSNS (35), /* int_div_si */
856 COSTS_N_INSNS (35), /* int_div_di */
857 1, /* branch_cost */
858 4 /* memory_latency */
860 { /* R6000 */
861 COSTS_N_INSNS (3), /* fp_add */
862 COSTS_N_INSNS (5), /* fp_mult_sf */
863 COSTS_N_INSNS (6), /* fp_mult_df */
864 COSTS_N_INSNS (15), /* fp_div_sf */
865 COSTS_N_INSNS (16), /* fp_div_df */
866 COSTS_N_INSNS (17), /* int_mult_si */
867 COSTS_N_INSNS (17), /* int_mult_di */
868 COSTS_N_INSNS (38), /* int_div_si */
869 COSTS_N_INSNS (38), /* int_div_di */
870 2, /* branch_cost */
871 6 /* memory_latency */
873 { /* R4000 */
874 COSTS_N_INSNS (6), /* fp_add */
875 COSTS_N_INSNS (7), /* fp_mult_sf */
876 COSTS_N_INSNS (8), /* fp_mult_df */
877 COSTS_N_INSNS (23), /* fp_div_sf */
878 COSTS_N_INSNS (36), /* fp_div_df */
879 COSTS_N_INSNS (10), /* int_mult_si */
880 COSTS_N_INSNS (10), /* int_mult_di */
881 COSTS_N_INSNS (69), /* int_div_si */
882 COSTS_N_INSNS (69), /* int_div_di */
883 2, /* branch_cost */
884 6 /* memory_latency */
886 { /* R4100 */
887 DEFAULT_COSTS
889 { /* R4111 */
890 DEFAULT_COSTS
892 { /* R4120 */
893 DEFAULT_COSTS
895 { /* R4130 */
896 /* The only costs that appear to be updated here are
897 integer multiplication. */
898 SOFT_FP_COSTS,
899 COSTS_N_INSNS (4), /* int_mult_si */
900 COSTS_N_INSNS (6), /* int_mult_di */
901 COSTS_N_INSNS (69), /* int_div_si */
902 COSTS_N_INSNS (69), /* int_div_di */
903 1, /* branch_cost */
904 4 /* memory_latency */
906 { /* R4300 */
907 DEFAULT_COSTS
909 { /* R4600 */
910 DEFAULT_COSTS
912 { /* R4650 */
913 DEFAULT_COSTS
915 { /* R5000 */
916 COSTS_N_INSNS (6), /* fp_add */
917 COSTS_N_INSNS (4), /* fp_mult_sf */
918 COSTS_N_INSNS (5), /* fp_mult_df */
919 COSTS_N_INSNS (23), /* fp_div_sf */
920 COSTS_N_INSNS (36), /* fp_div_df */
921 COSTS_N_INSNS (5), /* int_mult_si */
922 COSTS_N_INSNS (5), /* int_mult_di */
923 COSTS_N_INSNS (36), /* int_div_si */
924 COSTS_N_INSNS (36), /* int_div_di */
925 1, /* branch_cost */
926 4 /* memory_latency */
928 { /* R5400 */
929 COSTS_N_INSNS (6), /* fp_add */
930 COSTS_N_INSNS (5), /* fp_mult_sf */
931 COSTS_N_INSNS (6), /* fp_mult_df */
932 COSTS_N_INSNS (30), /* fp_div_sf */
933 COSTS_N_INSNS (59), /* fp_div_df */
934 COSTS_N_INSNS (3), /* int_mult_si */
935 COSTS_N_INSNS (4), /* int_mult_di */
936 COSTS_N_INSNS (42), /* int_div_si */
937 COSTS_N_INSNS (74), /* int_div_di */
938 1, /* branch_cost */
939 4 /* memory_latency */
941 { /* R5500 */
942 COSTS_N_INSNS (6), /* fp_add */
943 COSTS_N_INSNS (5), /* fp_mult_sf */
944 COSTS_N_INSNS (6), /* fp_mult_df */
945 COSTS_N_INSNS (30), /* fp_div_sf */
946 COSTS_N_INSNS (59), /* fp_div_df */
947 COSTS_N_INSNS (5), /* int_mult_si */
948 COSTS_N_INSNS (9), /* int_mult_di */
949 COSTS_N_INSNS (42), /* int_div_si */
950 COSTS_N_INSNS (74), /* int_div_di */
951 1, /* branch_cost */
952 4 /* memory_latency */
954 { /* R7000 */
955 /* The only costs that are changed here are
956 integer multiplication. */
957 COSTS_N_INSNS (6), /* fp_add */
958 COSTS_N_INSNS (7), /* fp_mult_sf */
959 COSTS_N_INSNS (8), /* fp_mult_df */
960 COSTS_N_INSNS (23), /* fp_div_sf */
961 COSTS_N_INSNS (36), /* fp_div_df */
962 COSTS_N_INSNS (5), /* int_mult_si */
963 COSTS_N_INSNS (9), /* int_mult_di */
964 COSTS_N_INSNS (69), /* int_div_si */
965 COSTS_N_INSNS (69), /* int_div_di */
966 1, /* branch_cost */
967 4 /* memory_latency */
969 { /* R8000 */
970 DEFAULT_COSTS
972 { /* R9000 */
973 /* The only costs that are changed here are
974 integer multiplication. */
975 COSTS_N_INSNS (6), /* fp_add */
976 COSTS_N_INSNS (7), /* fp_mult_sf */
977 COSTS_N_INSNS (8), /* fp_mult_df */
978 COSTS_N_INSNS (23), /* fp_div_sf */
979 COSTS_N_INSNS (36), /* fp_div_df */
980 COSTS_N_INSNS (3), /* int_mult_si */
981 COSTS_N_INSNS (8), /* int_mult_di */
982 COSTS_N_INSNS (69), /* int_div_si */
983 COSTS_N_INSNS (69), /* int_div_di */
984 1, /* branch_cost */
985 4 /* memory_latency */
987 { /* SB1 */
988 /* These costs are the same as the SB-1A below. */
989 COSTS_N_INSNS (4), /* fp_add */
990 COSTS_N_INSNS (4), /* fp_mult_sf */
991 COSTS_N_INSNS (4), /* fp_mult_df */
992 COSTS_N_INSNS (24), /* fp_div_sf */
993 COSTS_N_INSNS (32), /* fp_div_df */
994 COSTS_N_INSNS (3), /* int_mult_si */
995 COSTS_N_INSNS (4), /* int_mult_di */
996 COSTS_N_INSNS (36), /* int_div_si */
997 COSTS_N_INSNS (68), /* int_div_di */
998 1, /* branch_cost */
999 4 /* memory_latency */
1001 { /* SB1-A */
1002 /* These costs are the same as the SB-1 above. */
1003 COSTS_N_INSNS (4), /* fp_add */
1004 COSTS_N_INSNS (4), /* fp_mult_sf */
1005 COSTS_N_INSNS (4), /* fp_mult_df */
1006 COSTS_N_INSNS (24), /* fp_div_sf */
1007 COSTS_N_INSNS (32), /* fp_div_df */
1008 COSTS_N_INSNS (3), /* int_mult_si */
1009 COSTS_N_INSNS (4), /* int_mult_di */
1010 COSTS_N_INSNS (36), /* int_div_si */
1011 COSTS_N_INSNS (68), /* int_div_di */
1012 1, /* branch_cost */
1013 4 /* memory_latency */
1015 { /* SR71000 */
1016 DEFAULT_COSTS
1020 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1021 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1022 struct mflip_mips16_entry GTY (()) {
1023 const char *name;
1024 bool mips16_p;
1026 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1028 /* Hash table callbacks for mflip_mips16_htab. */
1030 static hashval_t
1031 mflip_mips16_htab_hash (const void *entry)
1033 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1036 static int
1037 mflip_mips16_htab_eq (const void *entry, const void *name)
1039 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1040 (const char *) name) == 0;
1043 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1044 mode, false if it should next add an attribute for the opposite mode. */
1045 static GTY(()) bool mips16_flipper;
1047 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1048 for -mflip-mips16. Return true if it should use "mips16" and false if
1049 it should use "nomips16". */
1051 static bool
1052 mflip_mips16_use_mips16_p (tree decl)
1054 struct mflip_mips16_entry *entry;
1055 const char *name;
1056 hashval_t hash;
1057 void **slot;
1059 /* Use the opposite of the command-line setting for anonymous decls. */
1060 if (!DECL_NAME (decl))
1061 return !mips_base_mips16;
1063 if (!mflip_mips16_htab)
1064 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1065 mflip_mips16_htab_eq, NULL);
1067 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1068 hash = htab_hash_string (name);
1069 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1070 entry = (struct mflip_mips16_entry *) *slot;
1071 if (!entry)
1073 mips16_flipper = !mips16_flipper;
1074 entry = GGC_NEW (struct mflip_mips16_entry);
1075 entry->name = name;
1076 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1077 *slot = entry;
1079 return entry->mips16_p;
1082 /* Predicates to test for presence of "near" and "far"/"long_call"
1083 attributes on the given TYPE. */
1085 static bool
1086 mips_near_type_p (const_tree type)
1088 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1091 static bool
1092 mips_far_type_p (const_tree type)
1094 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1095 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1098 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1100 static bool
1101 mips_mips16_decl_p (const_tree decl)
1103 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1106 static bool
1107 mips_nomips16_decl_p (const_tree decl)
1109 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1112 /* Return true if function DECL is a MIPS16 function. Return the ambient
1113 setting if DECL is null. */
1115 static bool
1116 mips_use_mips16_mode_p (tree decl)
1118 if (decl)
1120 /* Nested functions must use the same frame pointer as their
1121 parent and must therefore use the same ISA mode. */
1122 tree parent = decl_function_context (decl);
1123 if (parent)
1124 decl = parent;
1125 if (mips_mips16_decl_p (decl))
1126 return true;
1127 if (mips_nomips16_decl_p (decl))
1128 return false;
1130 return mips_base_mips16;
1133 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1135 static int
1136 mips_comp_type_attributes (const_tree type1, const_tree type2)
1138 /* Disallow mixed near/far attributes. */
1139 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1140 return 0;
1141 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1142 return 0;
1143 return 1;
1146 /* Implement TARGET_INSERT_ATTRIBUTES. */
1148 static void
1149 mips_insert_attributes (tree decl, tree *attributes)
1151 const char *name;
1152 bool mips16_p, nomips16_p;
1154 /* Check for "mips16" and "nomips16" attributes. */
1155 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1156 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1157 if (TREE_CODE (decl) != FUNCTION_DECL)
1159 if (mips16_p)
1160 error ("%qs attribute only applies to functions", "mips16");
1161 if (nomips16_p)
1162 error ("%qs attribute only applies to functions", "nomips16");
1164 else
1166 mips16_p |= mips_mips16_decl_p (decl);
1167 nomips16_p |= mips_nomips16_decl_p (decl);
1168 if (mips16_p || nomips16_p)
1170 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1171 if (mips16_p && nomips16_p)
1172 error ("%qs cannot have both %<mips16%> and "
1173 "%<nomips16%> attributes",
1174 IDENTIFIER_POINTER (DECL_NAME (decl)));
1176 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1178 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1179 "mips16" attribute, arbitrarily pick one. We must pick the same
1180 setting for duplicate declarations of a function. */
1181 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1182 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1187 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1189 static tree
1190 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1192 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1193 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1194 error ("%qs redeclared with conflicting %qs attributes",
1195 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "mips16");
1196 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1197 error ("%qs redeclared with conflicting %qs attributes",
1198 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "nomips16");
1200 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1201 DECL_ATTRIBUTES (newdecl));
1204 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1205 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1207 static void
1208 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1210 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1212 *base_ptr = XEXP (x, 0);
1213 *offset_ptr = INTVAL (XEXP (x, 1));
1215 else
1217 *base_ptr = x;
1218 *offset_ptr = 0;
1222 static unsigned int mips_build_integer (struct mips_integer_op *,
1223 unsigned HOST_WIDE_INT);
1225 /* A subroutine of mips_build_integer, with the same interface.
1226 Assume that the final action in the sequence should be a left shift. */
1228 static unsigned int
1229 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1231 unsigned int i, shift;
1233 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1234 since signed numbers are easier to load than unsigned ones. */
1235 shift = 0;
1236 while ((value & 1) == 0)
1237 value /= 2, shift++;
1239 i = mips_build_integer (codes, value);
1240 codes[i].code = ASHIFT;
1241 codes[i].value = shift;
1242 return i + 1;
1245 /* As for mips_build_shift, but assume that the final action will be
1246 an IOR or PLUS operation. */
1248 static unsigned int
1249 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1251 unsigned HOST_WIDE_INT high;
1252 unsigned int i;
1254 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1255 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1257 /* The constant is too complex to load with a simple LUI/ORI pair,
1258 so we want to give the recursive call as many trailing zeros as
1259 possible. In this case, we know bit 16 is set and that the
1260 low 16 bits form a negative number. If we subtract that number
1261 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1262 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1263 codes[i].code = PLUS;
1264 codes[i].value = CONST_LOW_PART (value);
1266 else
1268 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1269 bits gives a value with at least 17 trailing zeros. */
1270 i = mips_build_integer (codes, high);
1271 codes[i].code = IOR;
1272 codes[i].value = value & 0xffff;
1274 return i + 1;
1277 /* Fill CODES with a sequence of rtl operations to load VALUE.
1278 Return the number of operations needed. */
1280 static unsigned int
1281 mips_build_integer (struct mips_integer_op *codes,
1282 unsigned HOST_WIDE_INT value)
1284 if (SMALL_OPERAND (value)
1285 || SMALL_OPERAND_UNSIGNED (value)
1286 || LUI_OPERAND (value))
1288 /* The value can be loaded with a single instruction. */
1289 codes[0].code = UNKNOWN;
1290 codes[0].value = value;
1291 return 1;
1293 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1295 /* Either the constant is a simple LUI/ORI combination or its
1296 lowest bit is set. We don't want to shift in this case. */
1297 return mips_build_lower (codes, value);
1299 else if ((value & 0xffff) == 0)
1301 /* The constant will need at least three actions. The lowest
1302 16 bits are clear, so the final action will be a shift. */
1303 return mips_build_shift (codes, value);
1305 else
1307 /* The final action could be a shift, add or inclusive OR.
1308 Rather than use a complex condition to select the best
1309 approach, try both mips_build_shift and mips_build_lower
1310 and pick the one that gives the shortest sequence.
1311 Note that this case is only used once per constant. */
1312 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1313 unsigned int cost, alt_cost;
1315 cost = mips_build_shift (codes, value);
1316 alt_cost = mips_build_lower (alt_codes, value);
1317 if (alt_cost < cost)
1319 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1320 cost = alt_cost;
1322 return cost;
1326 /* Return true if X is a thread-local symbol. */
1328 static bool
1329 mips_tls_symbol_p (rtx x)
1331 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1334 /* Return true if SYMBOL_REF X is associated with a global symbol
1335 (in the STB_GLOBAL sense). */
1337 static bool
1338 mips_global_symbol_p (const_rtx x)
1340 const_tree decl = SYMBOL_REF_DECL (x);
1342 if (!decl)
1343 return !SYMBOL_REF_LOCAL_P (x);
1345 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1346 or weak symbols. Relocations in the object file will be against
1347 the target symbol, so it's that symbol's binding that matters here. */
1348 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1351 /* Return true if SYMBOL_REF X binds locally. */
1353 static bool
1354 mips_symbol_binds_local_p (const_rtx x)
1356 return (SYMBOL_REF_DECL (x)
1357 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1358 : SYMBOL_REF_LOCAL_P (x));
1361 /* Return true if rtx constants of mode MODE should be put into a small
1362 data section. */
1364 static bool
1365 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1367 return (!TARGET_EMBEDDED_DATA
1368 && TARGET_LOCAL_SDATA
1369 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1372 /* Return true if X should not be moved directly into register $25.
1373 We need this because many versions of GAS will treat "la $25,foo" as
1374 part of a call sequence and so allow a global "foo" to be lazily bound. */
1376 bool
1377 mips_dangerous_for_la25_p (rtx x)
1379 return (!TARGET_EXPLICIT_RELOCS
1380 && TARGET_USE_GOT
1381 && GET_CODE (x) == SYMBOL_REF
1382 && mips_global_symbol_p (x));
1385 /* Return the method that should be used to access SYMBOL_REF or
1386 LABEL_REF X in context CONTEXT. */
1388 static enum mips_symbol_type
1389 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1391 if (TARGET_RTP_PIC)
1392 return SYMBOL_GOT_DISP;
1394 if (GET_CODE (x) == LABEL_REF)
1396 /* LABEL_REFs are used for jump tables as well as text labels.
1397 Only return SYMBOL_PC_RELATIVE if we know the label is in
1398 the text section. */
1399 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1400 return SYMBOL_PC_RELATIVE;
1402 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1403 return SYMBOL_GOT_PAGE_OFST;
1405 return SYMBOL_ABSOLUTE;
1408 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1410 if (SYMBOL_REF_TLS_MODEL (x))
1411 return SYMBOL_TLS;
1413 if (CONSTANT_POOL_ADDRESS_P (x))
1415 if (TARGET_MIPS16_TEXT_LOADS)
1416 return SYMBOL_PC_RELATIVE;
1418 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1419 return SYMBOL_PC_RELATIVE;
1421 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1422 return SYMBOL_GP_RELATIVE;
1425 /* Do not use small-data accesses for weak symbols; they may end up
1426 being zero. */
1427 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1428 return SYMBOL_GP_RELATIVE;
1430 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1431 is in effect. */
1432 if (TARGET_ABICALLS
1433 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1435 /* There are three cases to consider:
1437 - o32 PIC (either with or without explicit relocs)
1438 - n32/n64 PIC without explicit relocs
1439 - n32/n64 PIC with explicit relocs
1441 In the first case, both local and global accesses will use an
1442 R_MIPS_GOT16 relocation. We must correctly predict which of
1443 the two semantics (local or global) the assembler and linker
1444 will apply. The choice depends on the symbol's binding rather
1445 than its visibility.
1447 In the second case, the assembler will not use R_MIPS_GOT16
1448 relocations, but it chooses between local and global accesses
1449 in the same way as for o32 PIC.
1451 In the third case we have more freedom since both forms of
1452 access will work for any kind of symbol. However, there seems
1453 little point in doing things differently. */
1454 if (mips_global_symbol_p (x))
1455 return SYMBOL_GOT_DISP;
1457 return SYMBOL_GOT_PAGE_OFST;
1460 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1461 return SYMBOL_FORCE_TO_MEM;
1463 return SYMBOL_ABSOLUTE;
1466 /* Classify the base of symbolic expression X, given that X appears in
1467 context CONTEXT. */
1469 static enum mips_symbol_type
1470 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1472 rtx offset;
1474 split_const (x, &x, &offset);
1475 if (UNSPEC_ADDRESS_P (x))
1476 return UNSPEC_ADDRESS_TYPE (x);
1478 return mips_classify_symbol (x, context);
1481 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1482 is the alignment in bytes of SYMBOL_REF X. */
1484 static bool
1485 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1487 HOST_WIDE_INT align;
1489 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1490 return IN_RANGE (offset, 0, align - 1);
1493 /* Return true if X is a symbolic constant that can be used in context
1494 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1496 bool
1497 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1498 enum mips_symbol_type *symbol_type)
1500 rtx offset;
1502 split_const (x, &x, &offset);
1503 if (UNSPEC_ADDRESS_P (x))
1505 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1506 x = UNSPEC_ADDRESS (x);
1508 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1510 *symbol_type = mips_classify_symbol (x, context);
1511 if (*symbol_type == SYMBOL_TLS)
1512 return false;
1514 else
1515 return false;
1517 if (offset == const0_rtx)
1518 return true;
1520 /* Check whether a nonzero offset is valid for the underlying
1521 relocations. */
1522 switch (*symbol_type)
1524 case SYMBOL_ABSOLUTE:
1525 case SYMBOL_FORCE_TO_MEM:
1526 case SYMBOL_32_HIGH:
1527 case SYMBOL_64_HIGH:
1528 case SYMBOL_64_MID:
1529 case SYMBOL_64_LOW:
1530 /* If the target has 64-bit pointers and the object file only
1531 supports 32-bit symbols, the values of those symbols will be
1532 sign-extended. In this case we can't allow an arbitrary offset
1533 in case the 32-bit value X + OFFSET has a different sign from X. */
1534 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1535 return offset_within_block_p (x, INTVAL (offset));
1537 /* In other cases the relocations can handle any offset. */
1538 return true;
1540 case SYMBOL_PC_RELATIVE:
1541 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1542 In this case, we no longer have access to the underlying constant,
1543 but the original symbol-based access was known to be valid. */
1544 if (GET_CODE (x) == LABEL_REF)
1545 return true;
1547 /* Fall through. */
1549 case SYMBOL_GP_RELATIVE:
1550 /* Make sure that the offset refers to something within the
1551 same object block. This should guarantee that the final
1552 PC- or GP-relative offset is within the 16-bit limit. */
1553 return offset_within_block_p (x, INTVAL (offset));
1555 case SYMBOL_GOT_PAGE_OFST:
1556 case SYMBOL_GOTOFF_PAGE:
1557 /* If the symbol is global, the GOT entry will contain the symbol's
1558 address, and we will apply a 16-bit offset after loading it.
1559 If the symbol is local, the linker should provide enough local
1560 GOT entries for a 16-bit offset, but larger offsets may lead
1561 to GOT overflow. */
1562 return SMALL_INT (offset);
1564 case SYMBOL_TPREL:
1565 case SYMBOL_DTPREL:
1566 /* There is no carry between the HI and LO REL relocations, so the
1567 offset is only valid if we know it won't lead to such a carry. */
1568 return mips_offset_within_alignment_p (x, INTVAL (offset));
1570 case SYMBOL_GOT_DISP:
1571 case SYMBOL_GOTOFF_DISP:
1572 case SYMBOL_GOTOFF_CALL:
1573 case SYMBOL_GOTOFF_LOADGP:
1574 case SYMBOL_TLSGD:
1575 case SYMBOL_TLSLDM:
1576 case SYMBOL_GOTTPREL:
1577 case SYMBOL_TLS:
1578 case SYMBOL_HALF:
1579 return false;
1581 gcc_unreachable ();
1584 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1585 single instruction. We rely on the fact that, in the worst case,
1586 all instructions involved in a MIPS16 address calculation are usually
1587 extended ones. */
1589 static int
1590 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1592 switch (type)
1594 case SYMBOL_ABSOLUTE:
1595 /* When using 64-bit symbols, we need 5 preparatory instructions,
1596 such as:
1598 lui $at,%highest(symbol)
1599 daddiu $at,$at,%higher(symbol)
1600 dsll $at,$at,16
1601 daddiu $at,$at,%hi(symbol)
1602 dsll $at,$at,16
1604 The final address is then $at + %lo(symbol). With 32-bit
1605 symbols we just need a preparatory LUI for normal mode and
1606 a preparatory LI and SLL for MIPS16. */
1607 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1609 case SYMBOL_GP_RELATIVE:
1610 /* Treat GP-relative accesses as taking a single instruction on
1611 MIPS16 too; the copy of $gp can often be shared. */
1612 return 1;
1614 case SYMBOL_PC_RELATIVE:
1615 /* PC-relative constants can be only be used with ADDIUPC,
1616 DADDIUPC, LWPC and LDPC. */
1617 if (mode == MAX_MACHINE_MODE
1618 || GET_MODE_SIZE (mode) == 4
1619 || GET_MODE_SIZE (mode) == 8)
1620 return 1;
1622 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1623 return 0;
1625 case SYMBOL_FORCE_TO_MEM:
1626 /* LEAs will be converted into constant-pool references by
1627 mips_reorg. */
1628 if (mode == MAX_MACHINE_MODE)
1629 return 1;
1631 /* The constant must be loaded and then dereferenced. */
1632 return 0;
1634 case SYMBOL_GOT_DISP:
1635 /* The constant will have to be loaded from the GOT before it
1636 is used in an address. */
1637 if (mode != MAX_MACHINE_MODE)
1638 return 0;
1640 /* Fall through. */
1642 case SYMBOL_GOT_PAGE_OFST:
1643 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1644 local/global classification is accurate. The worst cases are:
1646 (1) For local symbols when generating o32 or o64 code. The assembler
1647 will use:
1649 lw $at,%got(symbol)
1652 ...and the final address will be $at + %lo(symbol).
1654 (2) For global symbols when -mxgot. The assembler will use:
1656 lui $at,%got_hi(symbol)
1657 (d)addu $at,$at,$gp
1659 ...and the final address will be $at + %got_lo(symbol). */
1660 return 3;
1662 case SYMBOL_GOTOFF_PAGE:
1663 case SYMBOL_GOTOFF_DISP:
1664 case SYMBOL_GOTOFF_CALL:
1665 case SYMBOL_GOTOFF_LOADGP:
1666 case SYMBOL_32_HIGH:
1667 case SYMBOL_64_HIGH:
1668 case SYMBOL_64_MID:
1669 case SYMBOL_64_LOW:
1670 case SYMBOL_TLSGD:
1671 case SYMBOL_TLSLDM:
1672 case SYMBOL_DTPREL:
1673 case SYMBOL_GOTTPREL:
1674 case SYMBOL_TPREL:
1675 case SYMBOL_HALF:
1676 /* A 16-bit constant formed by a single relocation, or a 32-bit
1677 constant formed from a high 16-bit relocation and a low 16-bit
1678 relocation. Use mips_split_p to determine which. 32-bit
1679 constants need an "lui; addiu" sequence for normal mode and
1680 an "li; sll; addiu" sequence for MIPS16 mode. */
1681 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1683 case SYMBOL_TLS:
1684 /* We don't treat a bare TLS symbol as a constant. */
1685 return 0;
1687 gcc_unreachable ();
1690 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1691 to load symbols of type TYPE into a register. Return 0 if the given
1692 type of symbol cannot be used as an immediate operand.
1694 Otherwise, return the number of instructions needed to load or store
1695 values of mode MODE to or from addresses of type TYPE. Return 0 if
1696 the given type of symbol is not valid in addresses.
1698 In both cases, treat extended MIPS16 instructions as two instructions. */
1700 static int
1701 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1703 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1706 /* A for_each_rtx callback. Stop the search if *X references a
1707 thread-local symbol. */
1709 static int
1710 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1712 return mips_tls_symbol_p (*x);
1715 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1717 static bool
1718 mips_cannot_force_const_mem (rtx x)
1720 rtx base, offset;
1722 if (!TARGET_MIPS16)
1724 /* As an optimization, reject constants that mips_legitimize_move
1725 can expand inline.
1727 Suppose we have a multi-instruction sequence that loads constant C
1728 into register R. If R does not get allocated a hard register, and
1729 R is used in an operand that allows both registers and memory
1730 references, reload will consider forcing C into memory and using
1731 one of the instruction's memory alternatives. Returning false
1732 here will force it to use an input reload instead. */
1733 if (GET_CODE (x) == CONST_INT)
1734 return true;
1736 split_const (x, &base, &offset);
1737 if (symbolic_operand (base, VOIDmode) && SMALL_INT (offset))
1738 return true;
1741 /* TLS symbols must be computed by mips_legitimize_move. */
1742 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1743 return true;
1745 return false;
1748 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1749 constants when we're using a per-function constant pool. */
1751 static bool
1752 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1753 const_rtx x ATTRIBUTE_UNUSED)
1755 return !TARGET_MIPS16_PCREL_LOADS;
1758 /* Return true if register REGNO is a valid base register for mode MODE.
1759 STRICT_P is true if REG_OK_STRICT is in effect. */
1762 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1763 bool strict_p)
1765 if (!HARD_REGISTER_NUM_P (regno))
1767 if (!strict_p)
1768 return true;
1769 regno = reg_renumber[regno];
1772 /* These fake registers will be eliminated to either the stack or
1773 hard frame pointer, both of which are usually valid base registers.
1774 Reload deals with the cases where the eliminated form isn't valid. */
1775 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1776 return true;
1778 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1779 values, nothing smaller. There are two problems here:
1781 (a) Instantiating virtual registers can introduce new uses of the
1782 stack pointer. If these virtual registers are valid addresses,
1783 the stack pointer should be too.
1785 (b) Most uses of the stack pointer are not made explicit until
1786 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1787 We don't know until that stage whether we'll be eliminating to the
1788 stack pointer (which needs the restriction) or the hard frame
1789 pointer (which doesn't).
1791 All in all, it seems more consistent to only enforce this restriction
1792 during and after reload. */
1793 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1794 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1796 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1799 /* Return true if X is a valid base register for mode MODE.
1800 STRICT_P is true if REG_OK_STRICT is in effect. */
1802 static bool
1803 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
1805 if (!strict_p && GET_CODE (x) == SUBREG)
1806 x = SUBREG_REG (x);
1808 return (REG_P (x)
1809 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
1812 /* Return true if X is a valid address for machine mode MODE. If it is,
1813 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
1814 effect. */
1816 static bool
1817 mips_classify_address (struct mips_address_info *info, rtx x,
1818 enum machine_mode mode, bool strict_p)
1820 switch (GET_CODE (x))
1822 case REG:
1823 case SUBREG:
1824 info->type = ADDRESS_REG;
1825 info->reg = x;
1826 info->offset = const0_rtx;
1827 return mips_valid_base_register_p (info->reg, mode, strict_p);
1829 case PLUS:
1830 info->type = ADDRESS_REG;
1831 info->reg = XEXP (x, 0);
1832 info->offset = XEXP (x, 1);
1833 return (mips_valid_base_register_p (info->reg, mode, strict_p)
1834 && const_arith_operand (info->offset, VOIDmode));
1836 case LO_SUM:
1837 info->type = ADDRESS_LO_SUM;
1838 info->reg = XEXP (x, 0);
1839 info->offset = XEXP (x, 1);
1840 /* We have to trust the creator of the LO_SUM to do something vaguely
1841 sane. Target-independent code that creates a LO_SUM should also
1842 create and verify the matching HIGH. Target-independent code that
1843 adds an offset to a LO_SUM must prove that the offset will not
1844 induce a carry. Failure to do either of these things would be
1845 a bug, and we are not required to check for it here. The MIPS
1846 backend itself should only create LO_SUMs for valid symbolic
1847 constants, with the high part being either a HIGH or a copy
1848 of _gp. */
1849 info->symbol_type
1850 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
1851 return (mips_valid_base_register_p (info->reg, mode, strict_p)
1852 && mips_symbol_insns (info->symbol_type, mode) > 0
1853 && mips_lo_relocs[info->symbol_type] != 0);
1855 case CONST_INT:
1856 /* Small-integer addresses don't occur very often, but they
1857 are legitimate if $0 is a valid base register. */
1858 info->type = ADDRESS_CONST_INT;
1859 return !TARGET_MIPS16 && SMALL_INT (x);
1861 case CONST:
1862 case LABEL_REF:
1863 case SYMBOL_REF:
1864 info->type = ADDRESS_SYMBOLIC;
1865 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
1866 &info->symbol_type)
1867 && mips_symbol_insns (info->symbol_type, mode) > 0
1868 && !mips_split_p[info->symbol_type]);
1870 default:
1871 return false;
1875 /* Return true if X is a legitimate address for a memory operand of mode
1876 MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
1878 bool
1879 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
1881 struct mips_address_info addr;
1883 return mips_classify_address (&addr, x, mode, strict_p);
1886 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1888 bool
1889 mips_stack_address_p (rtx x, enum machine_mode mode)
1891 struct mips_address_info addr;
1893 return (mips_classify_address (&addr, x, mode, false)
1894 && addr.type == ADDRESS_REG
1895 && addr.reg == stack_pointer_rtx);
1898 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
1899 address instruction. Note that such addresses are not considered
1900 legitimate in the GO_IF_LEGITIMATE_ADDRESS sense, because their use
1901 is so restricted. */
1903 static bool
1904 mips_lwxs_address_p (rtx addr)
1906 if (ISA_HAS_LWXS
1907 && GET_CODE (addr) == PLUS
1908 && REG_P (XEXP (addr, 1)))
1910 rtx offset = XEXP (addr, 0);
1911 if (GET_CODE (offset) == MULT
1912 && REG_P (XEXP (offset, 0))
1913 && GET_CODE (XEXP (offset, 1)) == CONST_INT
1914 && INTVAL (XEXP (offset, 1)) == 4)
1915 return true;
1917 return false;
1920 /* Return true if a value at OFFSET bytes from base register BASE can be
1921 accessed using an unextended MIPS16 instruction. MODE is the mode of
1922 the value.
1924 Usually the offset in an unextended instruction is a 5-bit field.
1925 The offset is unsigned and shifted left once for LH and SH, twice
1926 for LW and SW, and so on. An exception is LWSP and SWSP, which have
1927 an 8-bit immediate field that's shifted left twice. */
1929 static bool
1930 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
1931 unsigned HOST_WIDE_INT offset)
1933 if (offset % GET_MODE_SIZE (mode) == 0)
1935 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1936 return offset < 256U * GET_MODE_SIZE (mode);
1937 return offset < 32U * GET_MODE_SIZE (mode);
1939 return false;
1942 /* Return the number of instructions needed to load or store a value
1943 of mode MODE at address X. Return 0 if X isn't valid for MODE.
1944 Assume that multiword moves may need to be split into word moves
1945 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
1946 enough.
1948 For MIPS16 code, count extended instructions as two instructions. */
1951 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
1953 struct mips_address_info addr;
1954 int factor;
1956 /* BLKmode is used for single unaligned loads and stores and should
1957 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
1958 meaningless, so we have to single it out as a special case one way
1959 or the other.) */
1960 if (mode != BLKmode && might_split_p)
1961 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1962 else
1963 factor = 1;
1965 if (mips_classify_address (&addr, x, mode, false))
1966 switch (addr.type)
1968 case ADDRESS_REG:
1969 if (TARGET_MIPS16
1970 && !mips16_unextended_reference_p (mode, addr.reg,
1971 UINTVAL (addr.offset)))
1972 return factor * 2;
1973 return factor;
1975 case ADDRESS_LO_SUM:
1976 return TARGET_MIPS16 ? factor * 2 : factor;
1978 case ADDRESS_CONST_INT:
1979 return factor;
1981 case ADDRESS_SYMBOLIC:
1982 return factor * mips_symbol_insns (addr.symbol_type, mode);
1984 return 0;
1987 /* Return the number of instructions needed to load constant X.
1988 Return 0 if X isn't a valid constant. */
1991 mips_const_insns (rtx x)
1993 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1994 enum mips_symbol_type symbol_type;
1995 rtx offset;
1997 switch (GET_CODE (x))
1999 case HIGH:
2000 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2001 &symbol_type)
2002 || !mips_split_p[symbol_type])
2003 return 0;
2005 /* This is simply an LUI for normal mode. It is an extended
2006 LI followed by an extended SLL for MIPS16. */
2007 return TARGET_MIPS16 ? 4 : 1;
2009 case CONST_INT:
2010 if (TARGET_MIPS16)
2011 /* Unsigned 8-bit constants can be loaded using an unextended
2012 LI instruction. Unsigned 16-bit constants can be loaded
2013 using an extended LI. Negative constants must be loaded
2014 using LI and then negated. */
2015 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2016 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2017 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2018 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2019 : 0);
2021 return mips_build_integer (codes, INTVAL (x));
2023 case CONST_DOUBLE:
2024 case CONST_VECTOR:
2025 /* Allow zeros for normal mode, where we can use $0. */
2026 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2028 case CONST:
2029 if (CONST_GP_P (x))
2030 return 1;
2032 /* See if we can refer to X directly. */
2033 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2034 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2036 /* Otherwise try splitting the constant into a base and offset.
2037 16-bit offsets can be added using an extra ADDIU. Larger offsets
2038 must be calculated separately and then added to the base. */
2039 split_const (x, &x, &offset);
2040 if (offset != 0)
2042 int n = mips_const_insns (x);
2043 if (n != 0)
2045 if (SMALL_INT (offset))
2046 return n + 1;
2047 else
2048 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2051 return 0;
2053 case SYMBOL_REF:
2054 case LABEL_REF:
2055 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2056 MAX_MACHINE_MODE);
2058 default:
2059 return 0;
2063 /* Return the number of instructions needed to implement INSN,
2064 given that it loads from or stores to MEM. Count extended
2065 MIPS16 instructions as two instructions. */
2068 mips_load_store_insns (rtx mem, rtx insn)
2070 enum machine_mode mode;
2071 bool might_split_p;
2072 rtx set;
2074 gcc_assert (MEM_P (mem));
2075 mode = GET_MODE (mem);
2077 /* Try to prove that INSN does not need to be split. */
2078 might_split_p = true;
2079 if (GET_MODE_BITSIZE (mode) == 64)
2081 set = single_set (insn);
2082 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2083 might_split_p = false;
2086 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2089 /* Return the number of instructions needed for an integer division. */
2092 mips_idiv_insns (void)
2094 int count;
2096 count = 1;
2097 if (TARGET_CHECK_ZERO_DIV)
2099 if (GENERATE_DIVIDE_TRAPS)
2100 count++;
2101 else
2102 count += 2;
2105 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2106 count++;
2107 return count;
2110 /* Emit a move from SRC to DEST. Assume that the move expanders can
2111 handle all moves if !can_create_pseudo_p (). The distinction is
2112 important because, unlike emit_move_insn, the move expanders know
2113 how to force Pmode objects into the constant pool even when the
2114 constant pool address is not itself legitimate. */
2117 mips_emit_move (rtx dest, rtx src)
2119 return (can_create_pseudo_p ()
2120 ? emit_move_insn (dest, src)
2121 : emit_move_insn_1 (dest, src));
2124 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2126 static void
2127 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2129 emit_insn (gen_rtx_SET (VOIDmode, target,
2130 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2133 /* Compute (CODE OP0 OP1) and store the result in a new register
2134 of mode MODE. Return that new register. */
2136 static rtx
2137 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2139 rtx reg;
2141 reg = gen_reg_rtx (mode);
2142 mips_emit_binary (code, reg, op0, op1);
2143 return reg;
2146 /* Copy VALUE to a register and return that register. If new pseudos
2147 are allowed, copy it into a new register, otherwise use DEST. */
2149 static rtx
2150 mips_force_temporary (rtx dest, rtx value)
2152 if (can_create_pseudo_p ())
2153 return force_reg (Pmode, value);
2154 else
2156 mips_emit_move (dest, value);
2157 return dest;
2161 /* Emit a call sequence with call pattern PATTERN and return the call
2162 instruction itself (which is not necessarily the last instruction
2163 emitted). LAZY_P is true if the call address is lazily-bound. */
2165 static rtx
2166 mips_emit_call_insn (rtx pattern, bool lazy_p)
2168 rtx insn;
2170 insn = emit_call_insn (pattern);
2172 /* Lazy-binding stubs require $gp to be valid on entry. */
2173 if (lazy_p)
2174 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2176 if (TARGET_USE_GOT)
2178 /* See the comment above load_call<mode> for details. */
2179 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2180 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2181 emit_insn (gen_update_got_version ());
2183 return insn;
2186 /* Return an instruction that copies $gp into register REG. We want
2187 GCC to treat the register's value as constant, so that its value
2188 can be rematerialized on demand. */
2190 static rtx
2191 gen_load_const_gp (rtx reg)
2193 return (Pmode == SImode
2194 ? gen_load_const_gp_si (reg)
2195 : gen_load_const_gp_di (reg));
2198 /* Return a pseudo register that contains the value of $gp throughout
2199 the current function. Such registers are needed by MIPS16 functions,
2200 for which $gp itself is not a valid base register or addition operand. */
2202 static rtx
2203 mips16_gp_pseudo_reg (void)
2205 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2206 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2208 /* Don't emit an instruction to initialize the pseudo register if
2209 we are being called from the tree optimizers' cost-calculation
2210 routines. */
2211 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2212 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2214 rtx insn, scan, after;
2216 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2218 push_topmost_sequence ();
2219 /* We need to emit the initialization after the FUNCTION_BEG
2220 note, so that it will be integrated. */
2221 after = get_insns ();
2222 for (scan = after; scan != NULL_RTX; scan = NEXT_INSN (scan))
2223 if (NOTE_P (scan) && NOTE_KIND (scan) == NOTE_INSN_FUNCTION_BEG)
2225 after = scan;
2226 break;
2228 insn = emit_insn_after (insn, after);
2229 pop_topmost_sequence ();
2231 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2234 return cfun->machine->mips16_gp_pseudo_rtx;
2237 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2238 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2239 constant in that context and can be split into a high part and a LO_SUM.
2240 If so, and if LO_SUM_OUT is nonnull, emit the high part and return
2241 the LO_SUM in *LO_SUM_OUT. Leave *LO_SUM_OUT unchanged otherwise.
2243 TEMP is as for mips_force_temporary and is used to load the high
2244 part into a register. */
2246 bool
2247 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *lo_sum_out)
2249 enum mips_symbol_context context;
2250 enum mips_symbol_type symbol_type;
2251 rtx high;
2253 context = (mode == MAX_MACHINE_MODE
2254 ? SYMBOL_CONTEXT_LEA
2255 : SYMBOL_CONTEXT_MEM);
2256 if (!mips_symbolic_constant_p (addr, context, &symbol_type)
2257 || mips_symbol_insns (symbol_type, mode) == 0
2258 || !mips_split_p[symbol_type])
2259 return false;
2261 if (lo_sum_out)
2263 if (symbol_type == SYMBOL_GP_RELATIVE)
2265 if (!can_create_pseudo_p ())
2267 emit_insn (gen_load_const_gp (temp));
2268 high = temp;
2270 else
2271 high = mips16_gp_pseudo_reg ();
2273 else
2275 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2276 high = mips_force_temporary (temp, high);
2278 *lo_sum_out = gen_rtx_LO_SUM (Pmode, high, addr);
2280 return true;
2283 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2284 then add CONST_INT OFFSET to the result. */
2286 static rtx
2287 mips_unspec_address_offset (rtx base, rtx offset,
2288 enum mips_symbol_type symbol_type)
2290 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2291 UNSPEC_ADDRESS_FIRST + symbol_type);
2292 if (offset != const0_rtx)
2293 base = gen_rtx_PLUS (Pmode, base, offset);
2294 return gen_rtx_CONST (Pmode, base);
2297 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2298 type SYMBOL_TYPE. */
2301 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2303 rtx base, offset;
2305 split_const (address, &base, &offset);
2306 return mips_unspec_address_offset (base, offset, symbol_type);
2309 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2310 high part to BASE and return the result. Just return BASE otherwise.
2311 TEMP is as for mips_force_temporary.
2313 The returned expression can be used as the first operand to a LO_SUM. */
2315 static rtx
2316 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2317 enum mips_symbol_type symbol_type)
2319 if (mips_split_p[symbol_type])
2321 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2322 addr = mips_force_temporary (temp, addr);
2323 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2325 return base;
2328 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2329 mips_force_temporary; it is only needed when OFFSET is not a
2330 SMALL_OPERAND. */
2332 static rtx
2333 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2335 if (!SMALL_OPERAND (offset))
2337 rtx high;
2339 if (TARGET_MIPS16)
2341 /* Load the full offset into a register so that we can use
2342 an unextended instruction for the address itself. */
2343 high = GEN_INT (offset);
2344 offset = 0;
2346 else
2348 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2349 high = GEN_INT (CONST_HIGH_PART (offset));
2350 offset = CONST_LOW_PART (offset);
2352 high = mips_force_temporary (temp, high);
2353 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2355 return plus_constant (reg, offset);
2358 /* The __tls_get_attr symbol. */
2359 static GTY(()) rtx mips_tls_symbol;
2361 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2362 the TLS symbol we are referencing and TYPE is the symbol type to use
2363 (either global dynamic or local dynamic). V0 is an RTX for the
2364 return value location. */
2366 static rtx
2367 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2369 rtx insn, loc, a0;
2371 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2373 if (!mips_tls_symbol)
2374 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2376 loc = mips_unspec_address (sym, type);
2378 start_sequence ();
2380 emit_insn (gen_rtx_SET (Pmode, a0,
2381 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2382 insn = mips_expand_call (v0, mips_tls_symbol, const0_rtx, const0_rtx, false);
2383 RTL_CONST_CALL_P (insn) = 1;
2384 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2385 insn = get_insns ();
2387 end_sequence ();
2389 return insn;
2392 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2393 its address. The return value will be both a valid address and a valid
2394 SET_SRC (either a REG or a LO_SUM). */
2396 static rtx
2397 mips_legitimize_tls_address (rtx loc)
2399 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2400 enum tls_model model;
2402 if (TARGET_MIPS16)
2404 sorry ("MIPS16 TLS");
2405 return gen_reg_rtx (Pmode);
2408 model = SYMBOL_REF_TLS_MODEL (loc);
2409 /* Only TARGET_ABICALLS code can have more than one module; other
2410 code must be be static and should not use a GOT. All TLS models
2411 reduce to local exec in this situation. */
2412 if (!TARGET_ABICALLS)
2413 model = TLS_MODEL_LOCAL_EXEC;
2415 switch (model)
2417 case TLS_MODEL_GLOBAL_DYNAMIC:
2418 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2419 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2420 dest = gen_reg_rtx (Pmode);
2421 emit_libcall_block (insn, dest, v0, loc);
2422 break;
2424 case TLS_MODEL_LOCAL_DYNAMIC:
2425 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2426 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2427 tmp1 = gen_reg_rtx (Pmode);
2429 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2430 share the LDM result with other LD model accesses. */
2431 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2432 UNSPEC_TLS_LDM);
2433 emit_libcall_block (insn, tmp1, v0, eqv);
2435 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2436 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2437 mips_unspec_address (loc, SYMBOL_DTPREL));
2438 break;
2440 case TLS_MODEL_INITIAL_EXEC:
2441 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2442 tmp1 = gen_reg_rtx (Pmode);
2443 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2444 if (Pmode == DImode)
2446 emit_insn (gen_tls_get_tp_di (v1));
2447 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2449 else
2451 emit_insn (gen_tls_get_tp_si (v1));
2452 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2454 dest = gen_reg_rtx (Pmode);
2455 emit_insn (gen_add3_insn (dest, tmp1, v1));
2456 break;
2458 case TLS_MODEL_LOCAL_EXEC:
2459 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2460 if (Pmode == DImode)
2461 emit_insn (gen_tls_get_tp_di (v1));
2462 else
2463 emit_insn (gen_tls_get_tp_si (v1));
2465 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2466 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2467 mips_unspec_address (loc, SYMBOL_TPREL));
2468 break;
2470 default:
2471 gcc_unreachable ();
2473 return dest;
2476 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2477 be legitimized in a way that the generic machinery might not expect,
2478 put the new address in *XLOC and return true. MODE is the mode of
2479 the memory being accessed. */
2481 bool
2482 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2484 rtx base;
2485 HOST_WIDE_INT offset;
2487 if (mips_tls_symbol_p (*xloc))
2489 *xloc = mips_legitimize_tls_address (*xloc);
2490 return true;
2493 /* See if the address can split into a high part and a LO_SUM. */
2494 if (mips_split_symbol (NULL, *xloc, mode, xloc))
2495 return true;
2497 /* Handle BASE + OFFSET using mips_add_offset. */
2498 mips_split_plus (*xloc, &base, &offset);
2499 if (offset != 0)
2501 if (!mips_valid_base_register_p (base, mode, false))
2502 base = copy_to_mode_reg (Pmode, base);
2503 *xloc = mips_add_offset (NULL, base, offset);
2504 return true;
2506 return false;
2509 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2511 void
2512 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
2514 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2515 enum machine_mode mode;
2516 unsigned int i, num_ops;
2517 rtx x;
2519 mode = GET_MODE (dest);
2520 num_ops = mips_build_integer (codes, value);
2522 /* Apply each binary operation to X. Invariant: X is a legitimate
2523 source operand for a SET pattern. */
2524 x = GEN_INT (codes[0].value);
2525 for (i = 1; i < num_ops; i++)
2527 if (!can_create_pseudo_p ())
2529 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2530 x = temp;
2532 else
2533 x = force_reg (mode, x);
2534 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2537 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2540 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2541 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2542 move_operand. */
2544 static void
2545 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2547 rtx base, offset;
2549 /* Split moves of big integers into smaller pieces. */
2550 if (splittable_const_int_operand (src, mode))
2552 mips_move_integer (dest, dest, INTVAL (src));
2553 return;
2556 /* Split moves of symbolic constants into high/low pairs. */
2557 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
2559 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2560 return;
2563 /* Generate the appropriate access sequences for TLS symbols. */
2564 if (mips_tls_symbol_p (src))
2566 mips_emit_move (dest, mips_legitimize_tls_address (src));
2567 return;
2570 /* If we have (const (plus symbol offset)), and that expression cannot
2571 be forced into memory, load the symbol first and add in the offset.
2572 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2573 forced into memory, as it usually produces better code. */
2574 split_const (src, &base, &offset);
2575 if (offset != const0_rtx
2576 && (targetm.cannot_force_const_mem (src)
2577 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
2579 base = mips_force_temporary (dest, base);
2580 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
2581 return;
2584 src = force_const_mem (mode, src);
2586 /* When using explicit relocs, constant pool references are sometimes
2587 not legitimate addresses. */
2588 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
2589 mips_emit_move (dest, src);
2592 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
2593 sequence that is valid. */
2595 bool
2596 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2598 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2600 mips_emit_move (dest, force_reg (mode, src));
2601 return true;
2604 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2605 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2606 && REG_P (src) && MD_REG_P (REGNO (src))
2607 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2609 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2610 if (GET_MODE_SIZE (mode) <= 4)
2611 emit_insn (gen_mfhilo_si (gen_lowpart (SImode, dest),
2612 gen_lowpart (SImode, src),
2613 gen_rtx_REG (SImode, other_regno)));
2614 else
2615 emit_insn (gen_mfhilo_di (gen_lowpart (DImode, dest),
2616 gen_lowpart (DImode, src),
2617 gen_rtx_REG (DImode, other_regno)));
2618 return true;
2621 /* We need to deal with constants that would be legitimate
2622 immediate_operands but aren't legitimate move_operands. */
2623 if (CONSTANT_P (src) && !move_operand (src, mode))
2625 mips_legitimize_const_move (mode, dest, src);
2626 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2627 return true;
2629 return false;
2632 /* Return true if value X in context CONTEXT is a small-data address
2633 that can be rewritten as a LO_SUM. */
2635 static bool
2636 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
2638 enum mips_symbol_type symbol_type;
2640 return (TARGET_EXPLICIT_RELOCS
2641 && mips_symbolic_constant_p (x, context, &symbol_type)
2642 && symbol_type == SYMBOL_GP_RELATIVE);
2645 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
2646 containing MEM, or null if none. */
2648 static int
2649 mips_small_data_pattern_1 (rtx *loc, void *data)
2651 enum mips_symbol_context context;
2653 if (GET_CODE (*loc) == LO_SUM)
2654 return -1;
2656 if (MEM_P (*loc))
2658 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
2659 return 1;
2660 return -1;
2663 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2664 return mips_rewrite_small_data_p (*loc, context);
2667 /* Return true if OP refers to small data symbols directly, not through
2668 a LO_SUM. */
2670 bool
2671 mips_small_data_pattern_p (rtx op)
2673 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
2676 /* A for_each_rtx callback, used by mips_rewrite_small_data.
2677 DATA is the containing MEM, or null if none. */
2679 static int
2680 mips_rewrite_small_data_1 (rtx *loc, void *data)
2682 enum mips_symbol_context context;
2684 if (MEM_P (*loc))
2686 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
2687 return -1;
2690 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2691 if (mips_rewrite_small_data_p (*loc, context))
2692 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
2694 if (GET_CODE (*loc) == LO_SUM)
2695 return -1;
2697 return 0;
2700 /* Rewrite instruction pattern PATTERN so that it refers to small data
2701 using explicit relocations. */
2704 mips_rewrite_small_data (rtx pattern)
2706 pattern = copy_insn (pattern);
2707 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
2708 return pattern;
2711 /* We need a lot of little routines to check the range of MIPS16 immediate
2712 operands. */
2714 static int
2715 m16_check_op (rtx op, int low, int high, int mask)
2717 return (GET_CODE (op) == CONST_INT
2718 && IN_RANGE (INTVAL (op), low, high)
2719 && (INTVAL (op) & mask) == 0);
2723 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2725 return m16_check_op (op, 0x1, 0x8, 0);
2729 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2731 return m16_check_op (op, -0x8, 0x7, 0);
2735 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2737 return m16_check_op (op, -0x7, 0x8, 0);
2741 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2743 return m16_check_op (op, -0x10, 0xf, 0);
2747 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2749 return m16_check_op (op, -0xf, 0x10, 0);
2753 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2755 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
2759 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2761 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
2765 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2767 return m16_check_op (op, -0x80, 0x7f, 0);
2771 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2773 return m16_check_op (op, -0x7f, 0x80, 0);
2777 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2779 return m16_check_op (op, 0x0, 0xff, 0);
2783 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2785 return m16_check_op (op, -0xff, 0x0, 0);
2789 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2791 return m16_check_op (op, -0x1, 0xfe, 0);
2795 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2797 return m16_check_op (op, 0x0, 0xff << 2, 3);
2801 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2803 return m16_check_op (op, -0xff << 2, 0x0, 3);
2807 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2809 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
2813 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2815 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
2818 /* The cost of loading values from the constant pool. It should be
2819 larger than the cost of any constant we want to synthesize inline. */
2820 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
2822 /* Return the cost of X when used as an operand to the MIPS16 instruction
2823 that implements CODE. Return -1 if there is no such instruction, or if
2824 X is not a valid immediate operand for it. */
2826 static int
2827 mips16_constant_cost (int code, HOST_WIDE_INT x)
2829 switch (code)
2831 case ASHIFT:
2832 case ASHIFTRT:
2833 case LSHIFTRT:
2834 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
2835 other shifts are extended. The shift patterns truncate the shift
2836 count to the right size, so there are no out-of-range values. */
2837 if (IN_RANGE (x, 1, 8))
2838 return 0;
2839 return COSTS_N_INSNS (1);
2841 case PLUS:
2842 if (IN_RANGE (x, -128, 127))
2843 return 0;
2844 if (SMALL_OPERAND (x))
2845 return COSTS_N_INSNS (1);
2846 return -1;
2848 case LEU:
2849 /* Like LE, but reject the always-true case. */
2850 if (x == -1)
2851 return -1;
2852 case LE:
2853 /* We add 1 to the immediate and use SLT. */
2854 x += 1;
2855 case XOR:
2856 /* We can use CMPI for an xor with an unsigned 16-bit X. */
2857 case LT:
2858 case LTU:
2859 if (IN_RANGE (x, 0, 255))
2860 return 0;
2861 if (SMALL_OPERAND_UNSIGNED (x))
2862 return COSTS_N_INSNS (1);
2863 return -1;
2865 case EQ:
2866 case NE:
2867 /* Equality comparisons with 0 are cheap. */
2868 if (x == 0)
2869 return 0;
2870 return -1;
2872 default:
2873 return -1;
2877 /* Return true if there is a non-MIPS16 instruction that implements CODE
2878 and if that instruction accepts X as an immediate operand. */
2880 static int
2881 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
2883 switch (code)
2885 case ASHIFT:
2886 case ASHIFTRT:
2887 case LSHIFTRT:
2888 /* All shift counts are truncated to a valid constant. */
2889 return true;
2891 case ROTATE:
2892 case ROTATERT:
2893 /* Likewise rotates, if the target supports rotates at all. */
2894 return ISA_HAS_ROR;
2896 case AND:
2897 case IOR:
2898 case XOR:
2899 /* These instructions take 16-bit unsigned immediates. */
2900 return SMALL_OPERAND_UNSIGNED (x);
2902 case PLUS:
2903 case LT:
2904 case LTU:
2905 /* These instructions take 16-bit signed immediates. */
2906 return SMALL_OPERAND (x);
2908 case EQ:
2909 case NE:
2910 case GT:
2911 case GTU:
2912 /* The "immediate" forms of these instructions are really
2913 implemented as comparisons with register 0. */
2914 return x == 0;
2916 case GE:
2917 case GEU:
2918 /* Likewise, meaning that the only valid immediate operand is 1. */
2919 return x == 1;
2921 case LE:
2922 /* We add 1 to the immediate and use SLT. */
2923 return SMALL_OPERAND (x + 1);
2925 case LEU:
2926 /* Likewise SLTU, but reject the always-true case. */
2927 return SMALL_OPERAND (x + 1) && x + 1 != 0;
2929 case SIGN_EXTRACT:
2930 case ZERO_EXTRACT:
2931 /* The bit position and size are immediate operands. */
2932 return ISA_HAS_EXT_INS;
2934 default:
2935 /* By default assume that $0 can be used for 0. */
2936 return x == 0;
2940 /* Return the cost of binary operation X, given that the instruction
2941 sequence for a word-sized or smaller operation has cost SINGLE_COST
2942 and that the sequence of a double-word operation has cost DOUBLE_COST. */
2944 static int
2945 mips_binary_cost (rtx x, int single_cost, int double_cost)
2947 int cost;
2949 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
2950 cost = double_cost;
2951 else
2952 cost = single_cost;
2953 return (cost
2954 + rtx_cost (XEXP (x, 0), 0)
2955 + rtx_cost (XEXP (x, 1), GET_CODE (x)));
2958 /* Return the cost of floating-point multiplications of mode MODE. */
2960 static int
2961 mips_fp_mult_cost (enum machine_mode mode)
2963 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
2966 /* Return the cost of floating-point divisions of mode MODE. */
2968 static int
2969 mips_fp_div_cost (enum machine_mode mode)
2971 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
2974 /* Return the cost of sign-extending OP to mode MODE, not including the
2975 cost of OP itself. */
2977 static int
2978 mips_sign_extend_cost (enum machine_mode mode, rtx op)
2980 if (MEM_P (op))
2981 /* Extended loads are as cheap as unextended ones. */
2982 return 0;
2984 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
2985 /* A sign extension from SImode to DImode in 64-bit mode is free. */
2986 return 0;
2988 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
2989 /* We can use SEB or SEH. */
2990 return COSTS_N_INSNS (1);
2992 /* We need to use a shift left and a shift right. */
2993 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
2996 /* Return the cost of zero-extending OP to mode MODE, not including the
2997 cost of OP itself. */
2999 static int
3000 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3002 if (MEM_P (op))
3003 /* Extended loads are as cheap as unextended ones. */
3004 return 0;
3006 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3007 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3008 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3010 if (GENERATE_MIPS16E)
3011 /* We can use ZEB or ZEH. */
3012 return COSTS_N_INSNS (1);
3014 if (TARGET_MIPS16)
3015 /* We need to load 0xff or 0xffff into a register and use AND. */
3016 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3018 /* We can use ANDI. */
3019 return COSTS_N_INSNS (1);
3022 /* Implement TARGET_RTX_COSTS. */
3024 static bool
3025 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
3027 enum machine_mode mode = GET_MODE (x);
3028 bool float_mode_p = FLOAT_MODE_P (mode);
3029 int cost;
3030 rtx addr;
3032 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3033 appear in the instruction stream, and the cost of a comparison is
3034 really the cost of the branch or scc condition. At the time of
3035 writing, GCC only uses an explicit outer COMPARE code when optabs
3036 is testing whether a constant is expensive enough to force into a
3037 register. We want optabs to pass such constants through the MIPS
3038 expanders instead, so make all constants very cheap here. */
3039 if (outer_code == COMPARE)
3041 gcc_assert (CONSTANT_P (x));
3042 *total = 0;
3043 return true;
3046 switch (code)
3048 case CONST_INT:
3049 /* Treat *clear_upper32-style ANDs as having zero cost in the
3050 second operand. The cost is entirely in the first operand.
3052 ??? This is needed because we would otherwise try to CSE
3053 the constant operand. Although that's the right thing for
3054 instructions that continue to be a register operation throughout
3055 compilation, it is disastrous for instructions that could
3056 later be converted into a memory operation. */
3057 if (TARGET_64BIT
3058 && outer_code == AND
3059 && UINTVAL (x) == 0xffffffff)
3061 *total = 0;
3062 return true;
3065 if (TARGET_MIPS16)
3067 cost = mips16_constant_cost (outer_code, INTVAL (x));
3068 if (cost >= 0)
3070 *total = cost;
3071 return true;
3074 else
3076 /* When not optimizing for size, we care more about the cost
3077 of hot code, and hot code is often in a loop. If a constant
3078 operand needs to be forced into a register, we will often be
3079 able to hoist the constant load out of the loop, so the load
3080 should not contribute to the cost. */
3081 if (!optimize_size
3082 || mips_immediate_operand_p (outer_code, INTVAL (x)))
3084 *total = 0;
3085 return true;
3088 /* Fall through. */
3090 case CONST:
3091 case SYMBOL_REF:
3092 case LABEL_REF:
3093 case CONST_DOUBLE:
3094 if (force_to_mem_operand (x, VOIDmode))
3096 *total = COSTS_N_INSNS (1);
3097 return true;
3099 cost = mips_const_insns (x);
3100 if (cost > 0)
3102 /* If the constant is likely to be stored in a GPR, SETs of
3103 single-insn constants are as cheap as register sets; we
3104 never want to CSE them.
3106 Don't reduce the cost of storing a floating-point zero in
3107 FPRs. If we have a zero in an FPR for other reasons, we
3108 can get better cfg-cleanup and delayed-branch results by
3109 using it consistently, rather than using $0 sometimes and
3110 an FPR at other times. Also, moves between floating-point
3111 registers are sometimes cheaper than (D)MTC1 $0. */
3112 if (cost == 1
3113 && outer_code == SET
3114 && !(float_mode_p && TARGET_HARD_FLOAT))
3115 cost = 0;
3116 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3117 want to CSE the constant itself. It is usually better to
3118 have N copies of the last operation in the sequence and one
3119 shared copy of the other operations. (Note that this is
3120 not true for MIPS16 code, where the final operation in the
3121 sequence is often an extended instruction.)
3123 Also, if we have a CONST_INT, we don't know whether it is
3124 for a word or doubleword operation, so we cannot rely on
3125 the result of mips_build_integer. */
3126 else if (!TARGET_MIPS16
3127 && (outer_code == SET || mode == VOIDmode))
3128 cost = 1;
3129 *total = COSTS_N_INSNS (cost);
3130 return true;
3132 /* The value will need to be fetched from the constant pool. */
3133 *total = CONSTANT_POOL_COST;
3134 return true;
3136 case MEM:
3137 /* If the address is legitimate, return the number of
3138 instructions it needs. */
3139 addr = XEXP (x, 0);
3140 cost = mips_address_insns (addr, mode, true);
3141 if (cost > 0)
3143 *total = COSTS_N_INSNS (cost + 1);
3144 return true;
3146 /* Check for a scaled indexed address. */
3147 if (mips_lwxs_address_p (addr))
3149 *total = COSTS_N_INSNS (2);
3150 return true;
3152 /* Otherwise use the default handling. */
3153 return false;
3155 case FFS:
3156 *total = COSTS_N_INSNS (6);
3157 return false;
3159 case NOT:
3160 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3161 return false;
3163 case AND:
3164 /* Check for a *clear_upper32 pattern and treat it like a zero
3165 extension. See the pattern's comment for details. */
3166 if (TARGET_64BIT
3167 && mode == DImode
3168 && CONST_INT_P (XEXP (x, 1))
3169 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3171 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3172 + rtx_cost (XEXP (x, 0), 0));
3173 return true;
3175 /* Fall through. */
3177 case IOR:
3178 case XOR:
3179 /* Double-word operations use two single-word operations. */
3180 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3181 return true;
3183 case ASHIFT:
3184 case ASHIFTRT:
3185 case LSHIFTRT:
3186 case ROTATE:
3187 case ROTATERT:
3188 if (CONSTANT_P (XEXP (x, 1)))
3189 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3190 else
3191 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3192 return true;
3194 case ABS:
3195 if (float_mode_p)
3196 *total = mips_cost->fp_add;
3197 else
3198 *total = COSTS_N_INSNS (4);
3199 return false;
3201 case LO_SUM:
3202 /* Low-part immediates need an extended MIPS16 instruction. */
3203 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3204 + rtx_cost (XEXP (x, 0), 0));
3205 return true;
3207 case LT:
3208 case LTU:
3209 case LE:
3210 case LEU:
3211 case GT:
3212 case GTU:
3213 case GE:
3214 case GEU:
3215 case EQ:
3216 case NE:
3217 case UNORDERED:
3218 case LTGT:
3219 /* Branch comparisons have VOIDmode, so use the first operand's
3220 mode instead. */
3221 mode = GET_MODE (XEXP (x, 0));
3222 if (FLOAT_MODE_P (mode))
3224 *total = mips_cost->fp_add;
3225 return false;
3227 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3228 return true;
3230 case MINUS:
3231 if (float_mode_p
3232 && ISA_HAS_NMADD_NMSUB (mode)
3233 && TARGET_FUSED_MADD
3234 && !HONOR_NANS (mode)
3235 && !HONOR_SIGNED_ZEROS (mode))
3237 /* See if we can use NMADD or NMSUB. See mips.md for the
3238 associated patterns. */
3239 rtx op0 = XEXP (x, 0);
3240 rtx op1 = XEXP (x, 1);
3241 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3243 *total = (mips_fp_mult_cost (mode)
3244 + rtx_cost (XEXP (XEXP (op0, 0), 0), 0)
3245 + rtx_cost (XEXP (op0, 1), 0)
3246 + rtx_cost (op1, 0));
3247 return true;
3249 if (GET_CODE (op1) == MULT)
3251 *total = (mips_fp_mult_cost (mode)
3252 + rtx_cost (op0, 0)
3253 + rtx_cost (XEXP (op1, 0), 0)
3254 + rtx_cost (XEXP (op1, 1), 0));
3255 return true;
3258 /* Fall through. */
3260 case PLUS:
3261 if (float_mode_p)
3263 /* If this is part of a MADD or MSUB, treat the PLUS as
3264 being free. */
3265 if (ISA_HAS_FP4
3266 && TARGET_FUSED_MADD
3267 && GET_CODE (XEXP (x, 0)) == MULT)
3268 *total = 0;
3269 else
3270 *total = mips_cost->fp_add;
3271 return false;
3274 /* Double-word operations require three single-word operations and
3275 an SLTU. The MIPS16 version then needs to move the result of
3276 the SLTU from $24 to a MIPS16 register. */
3277 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3278 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4));
3279 return true;
3281 case NEG:
3282 if (float_mode_p
3283 && ISA_HAS_NMADD_NMSUB (mode)
3284 && TARGET_FUSED_MADD
3285 && !HONOR_NANS (mode)
3286 && HONOR_SIGNED_ZEROS (mode))
3288 /* See if we can use NMADD or NMSUB. See mips.md for the
3289 associated patterns. */
3290 rtx op = XEXP (x, 0);
3291 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3292 && GET_CODE (XEXP (op, 0)) == MULT)
3294 *total = (mips_fp_mult_cost (mode)
3295 + rtx_cost (XEXP (XEXP (op, 0), 0), 0)
3296 + rtx_cost (XEXP (XEXP (op, 0), 1), 0)
3297 + rtx_cost (XEXP (op, 1), 0));
3298 return true;
3302 if (float_mode_p)
3303 *total = mips_cost->fp_add;
3304 else
3305 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3306 return false;
3308 case MULT:
3309 if (float_mode_p)
3310 *total = mips_fp_mult_cost (mode);
3311 else if (mode == DImode && !TARGET_64BIT)
3312 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3313 where the mulsidi3 always includes an MFHI and an MFLO. */
3314 *total = (optimize_size
3315 ? COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)
3316 : mips_cost->int_mult_si * 3 + 6);
3317 else if (optimize_size)
3318 *total = (ISA_HAS_MUL3 ? 1 : 2);
3319 else if (mode == DImode)
3320 *total = mips_cost->int_mult_di;
3321 else
3322 *total = mips_cost->int_mult_si;
3323 return false;
3325 case DIV:
3326 /* Check for a reciprocal. */
3327 if (float_mode_p
3328 && ISA_HAS_FP4
3329 && flag_unsafe_math_optimizations
3330 && XEXP (x, 0) == CONST1_RTX (mode))
3332 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3333 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3334 division as being free. */
3335 *total = rtx_cost (XEXP (x, 1), 0);
3336 else
3337 *total = mips_fp_div_cost (mode) + rtx_cost (XEXP (x, 1), 0);
3338 return true;
3340 /* Fall through. */
3342 case SQRT:
3343 case MOD:
3344 if (float_mode_p)
3346 *total = mips_fp_div_cost (mode);
3347 return false;
3349 /* Fall through. */
3351 case UDIV:
3352 case UMOD:
3353 if (optimize_size)
3355 /* It is our responsibility to make division by a power of 2
3356 as cheap as 2 register additions if we want the division
3357 expanders to be used for such operations; see the setting
3358 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3359 should always produce shorter code than using
3360 expand_sdiv2_pow2. */
3361 if (TARGET_MIPS16
3362 && CONST_INT_P (XEXP (x, 1))
3363 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3365 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), 0);
3366 return true;
3368 *total = COSTS_N_INSNS (mips_idiv_insns ());
3370 else if (mode == DImode)
3371 *total = mips_cost->int_div_di;
3372 else
3373 *total = mips_cost->int_div_si;
3374 return false;
3376 case SIGN_EXTEND:
3377 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3378 return false;
3380 case ZERO_EXTEND:
3381 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3382 return false;
3384 case FLOAT:
3385 case UNSIGNED_FLOAT:
3386 case FIX:
3387 case FLOAT_EXTEND:
3388 case FLOAT_TRUNCATE:
3389 *total = mips_cost->fp_add;
3390 return false;
3392 default:
3393 return false;
3397 /* Implement TARGET_ADDRESS_COST. */
3399 static int
3400 mips_address_cost (rtx addr)
3402 return mips_address_insns (addr, SImode, false);
3405 /* Return one word of double-word value OP, taking into account the fixed
3406 endianness of certain registers. HIGH_P is true to select the high part,
3407 false to select the low part. */
3410 mips_subword (rtx op, bool high_p)
3412 unsigned int byte, offset;
3413 enum machine_mode mode;
3415 mode = GET_MODE (op);
3416 if (mode == VOIDmode)
3417 mode = DImode;
3419 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
3420 byte = UNITS_PER_WORD;
3421 else
3422 byte = 0;
3424 if (FP_REG_RTX_P (op))
3426 /* Paired FPRs are always ordered little-endian. */
3427 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
3428 return gen_rtx_REG (word_mode, REGNO (op) + offset);
3431 if (MEM_P (op))
3432 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3434 return simplify_gen_subreg (word_mode, op, mode, byte);
3437 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3439 bool
3440 mips_split_64bit_move_p (rtx dest, rtx src)
3442 if (TARGET_64BIT)
3443 return false;
3445 /* FPR-to-FPR moves can be done in a single instruction, if they're
3446 allowed at all. */
3447 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3448 return false;
3450 /* Check for floating-point loads and stores. */
3451 if (ISA_HAS_LDC1_SDC1)
3453 if (FP_REG_RTX_P (dest) && MEM_P (src))
3454 return false;
3455 if (FP_REG_RTX_P (src) && MEM_P (dest))
3456 return false;
3458 return true;
3461 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3462 this function handles 64-bit moves for which mips_split_64bit_move_p
3463 holds. For 64-bit targets, this function handles 128-bit moves. */
3465 void
3466 mips_split_doubleword_move (rtx dest, rtx src)
3468 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
3470 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
3471 emit_insn (gen_move_doubleword_fprdi (dest, src));
3472 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
3473 emit_insn (gen_move_doubleword_fprdf (dest, src));
3474 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
3475 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
3476 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
3477 emit_insn (gen_move_doubleword_fprtf (dest, src));
3478 else
3479 gcc_unreachable ();
3481 else
3483 /* The operation can be split into two normal moves. Decide in
3484 which order to do them. */
3485 rtx low_dest;
3487 low_dest = mips_subword (dest, false);
3488 if (REG_P (low_dest)
3489 && reg_overlap_mentioned_p (low_dest, src))
3491 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3492 mips_emit_move (low_dest, mips_subword (src, false));
3494 else
3496 mips_emit_move (low_dest, mips_subword (src, false));
3497 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3502 /* Return the appropriate instructions to move SRC into DEST. Assume
3503 that SRC is operand 1 and DEST is operand 0. */
3505 const char *
3506 mips_output_move (rtx dest, rtx src)
3508 enum rtx_code dest_code, src_code;
3509 enum machine_mode mode;
3510 enum mips_symbol_type symbol_type;
3511 bool dbl_p;
3513 dest_code = GET_CODE (dest);
3514 src_code = GET_CODE (src);
3515 mode = GET_MODE (dest);
3516 dbl_p = (GET_MODE_SIZE (mode) == 8);
3518 if (dbl_p && mips_split_64bit_move_p (dest, src))
3519 return "#";
3521 if ((src_code == REG && GP_REG_P (REGNO (src)))
3522 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
3524 if (dest_code == REG)
3526 if (GP_REG_P (REGNO (dest)))
3527 return "move\t%0,%z1";
3529 if (MD_REG_P (REGNO (dest)))
3530 return "mt%0\t%z1";
3532 if (DSP_ACC_REG_P (REGNO (dest)))
3534 static char retval[] = "mt__\t%z1,%q0";
3536 retval[2] = reg_names[REGNO (dest)][4];
3537 retval[3] = reg_names[REGNO (dest)][5];
3538 return retval;
3541 if (FP_REG_P (REGNO (dest)))
3542 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
3544 if (ALL_COP_REG_P (REGNO (dest)))
3546 static char retval[] = "dmtc_\t%z1,%0";
3548 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3549 return dbl_p ? retval : retval + 1;
3552 if (dest_code == MEM)
3553 return dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0";
3555 if (dest_code == REG && GP_REG_P (REGNO (dest)))
3557 if (src_code == REG)
3559 /* Handled by separate patterns. */
3560 gcc_assert (!MD_REG_P (REGNO (src)));
3562 if (DSP_ACC_REG_P (REGNO (src)))
3564 static char retval[] = "mf__\t%0,%q1";
3566 retval[2] = reg_names[REGNO (src)][4];
3567 retval[3] = reg_names[REGNO (src)][5];
3568 return retval;
3571 if (FP_REG_P (REGNO (src)))
3572 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
3574 if (ALL_COP_REG_P (REGNO (src)))
3576 static char retval[] = "dmfc_\t%0,%1";
3578 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3579 return dbl_p ? retval : retval + 1;
3582 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3583 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3586 if (src_code == MEM)
3587 return dbl_p ? "ld\t%0,%1" : "lw\t%0,%1";
3589 if (src_code == CONST_INT)
3591 /* Don't use the X format for the operand itself, because that
3592 will give out-of-range numbers for 64-bit hosts and 32-bit
3593 targets. */
3594 if (!TARGET_MIPS16)
3595 return "li\t%0,%1\t\t\t# %X1";
3597 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
3598 return "li\t%0,%1";
3600 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
3601 return "#";
3604 if (src_code == HIGH)
3605 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
3607 if (CONST_GP_P (src))
3608 return "move\t%0,%1";
3610 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
3611 && mips_lo_relocs[symbol_type] != 0)
3613 /* A signed 16-bit constant formed by applying a relocation
3614 operator to a symbolic address. */
3615 gcc_assert (!mips_split_p[symbol_type]);
3616 return "li\t%0,%R1";
3619 if (symbolic_operand (src, VOIDmode))
3621 gcc_assert (TARGET_MIPS16
3622 ? TARGET_MIPS16_TEXT_LOADS
3623 : !TARGET_EXPLICIT_RELOCS);
3624 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
3627 if (src_code == REG && FP_REG_P (REGNO (src)))
3629 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3631 if (GET_MODE (dest) == V2SFmode)
3632 return "mov.ps\t%0,%1";
3633 else
3634 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
3637 if (dest_code == MEM)
3638 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
3640 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3642 if (src_code == MEM)
3643 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
3645 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
3647 static char retval[] = "l_c_\t%0,%1";
3649 retval[1] = (dbl_p ? 'd' : 'w');
3650 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3651 return retval;
3653 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
3655 static char retval[] = "s_c_\t%1,%0";
3657 retval[1] = (dbl_p ? 'd' : 'w');
3658 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3659 return retval;
3661 gcc_unreachable ();
3664 /* Return true if CMP1 is a suitable second operand for integer ordering
3665 test CODE. See also the *sCC patterns in mips.md. */
3667 static bool
3668 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
3670 switch (code)
3672 case GT:
3673 case GTU:
3674 return reg_or_0_operand (cmp1, VOIDmode);
3676 case GE:
3677 case GEU:
3678 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3680 case LT:
3681 case LTU:
3682 return arith_operand (cmp1, VOIDmode);
3684 case LE:
3685 return sle_operand (cmp1, VOIDmode);
3687 case LEU:
3688 return sleu_operand (cmp1, VOIDmode);
3690 default:
3691 gcc_unreachable ();
3695 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
3696 integer ordering test *CODE, or if an equivalent combination can
3697 be formed by adjusting *CODE and *CMP1. When returning true, update
3698 *CODE and *CMP1 with the chosen code and operand, otherwise leave
3699 them alone. */
3701 static bool
3702 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
3703 enum machine_mode mode)
3705 HOST_WIDE_INT plus_one;
3707 if (mips_int_order_operand_ok_p (*code, *cmp1))
3708 return true;
3710 if (GET_CODE (*cmp1) == CONST_INT)
3711 switch (*code)
3713 case LE:
3714 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
3715 if (INTVAL (*cmp1) < plus_one)
3717 *code = LT;
3718 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3719 return true;
3721 break;
3723 case LEU:
3724 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
3725 if (plus_one != 0)
3727 *code = LTU;
3728 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3729 return true;
3731 break;
3733 default:
3734 break;
3736 return false;
3739 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
3740 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
3741 is nonnull, it's OK to set TARGET to the inverse of the result and
3742 flip *INVERT_PTR instead. */
3744 static void
3745 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
3746 rtx target, rtx cmp0, rtx cmp1)
3748 enum machine_mode mode;
3750 /* First see if there is a MIPS instruction that can do this operation.
3751 If not, try doing the same for the inverse operation. If that also
3752 fails, force CMP1 into a register and try again. */
3753 mode = GET_MODE (cmp0);
3754 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
3755 mips_emit_binary (code, target, cmp0, cmp1);
3756 else
3758 enum rtx_code inv_code = reverse_condition (code);
3759 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
3761 cmp1 = force_reg (mode, cmp1);
3762 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
3764 else if (invert_ptr == 0)
3766 rtx inv_target;
3768 inv_target = mips_force_binary (GET_MODE (target),
3769 inv_code, cmp0, cmp1);
3770 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3772 else
3774 *invert_ptr = !*invert_ptr;
3775 mips_emit_binary (inv_code, target, cmp0, cmp1);
3780 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3781 The register will have the same mode as CMP0. */
3783 static rtx
3784 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3786 if (cmp1 == const0_rtx)
3787 return cmp0;
3789 if (uns_arith_operand (cmp1, VOIDmode))
3790 return expand_binop (GET_MODE (cmp0), xor_optab,
3791 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3793 return expand_binop (GET_MODE (cmp0), sub_optab,
3794 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3797 /* Convert *CODE into a code that can be used in a floating-point
3798 scc instruction (C.cond.fmt). Return true if the values of
3799 the condition code registers will be inverted, with 0 indicating
3800 that the condition holds. */
3802 static bool
3803 mips_reversed_fp_cond (enum rtx_code *code)
3805 switch (*code)
3807 case NE:
3808 case LTGT:
3809 case ORDERED:
3810 *code = reverse_condition_maybe_unordered (*code);
3811 return true;
3813 default:
3814 return false;
3818 /* Convert a comparison into something that can be used in a branch or
3819 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3820 being compared and *CODE is the code used to compare them.
3822 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3823 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
3824 otherwise any standard branch condition can be used. The standard branch
3825 conditions are:
3827 - EQ or NE between two registers.
3828 - any comparison between a register and zero. */
3830 static void
3831 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3833 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3835 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3837 *op0 = cmp_operands[0];
3838 *op1 = cmp_operands[1];
3840 else if (*code == EQ || *code == NE)
3842 if (need_eq_ne_p)
3844 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3845 *op1 = const0_rtx;
3847 else
3849 *op0 = cmp_operands[0];
3850 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3853 else
3855 /* The comparison needs a separate scc instruction. Store the
3856 result of the scc in *OP0 and compare it against zero. */
3857 bool invert = false;
3858 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3859 mips_emit_int_order_test (*code, &invert, *op0,
3860 cmp_operands[0], cmp_operands[1]);
3861 *code = (invert ? EQ : NE);
3862 *op1 = const0_rtx;
3865 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_operands[0])))
3867 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
3868 mips_emit_binary (*code, *op0, cmp_operands[0], cmp_operands[1]);
3869 *code = NE;
3870 *op1 = const0_rtx;
3872 else
3874 enum rtx_code cmp_code;
3876 /* Floating-point tests use a separate C.cond.fmt comparison to
3877 set a condition code register. The branch or conditional move
3878 will then compare that register against zero.
3880 Set CMP_CODE to the code of the comparison instruction and
3881 *CODE to the code that the branch or move should use. */
3882 cmp_code = *code;
3883 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
3884 *op0 = (ISA_HAS_8CC
3885 ? gen_reg_rtx (CCmode)
3886 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3887 *op1 = const0_rtx;
3888 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3892 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3893 Store the result in TARGET and return true if successful.
3895 On 64-bit targets, TARGET may be narrower than cmp_operands[0]. */
3897 bool
3898 mips_expand_scc (enum rtx_code code, rtx target)
3900 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3901 return false;
3903 if (code == EQ || code == NE)
3905 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3906 mips_emit_binary (code, target, zie, const0_rtx);
3908 else
3909 mips_emit_int_order_test (code, 0, target,
3910 cmp_operands[0], cmp_operands[1]);
3911 return true;
3914 /* Compare cmp_operands[0] with cmp_operands[1] using comparison code
3915 CODE and jump to OPERANDS[0] if the condition holds. */
3917 void
3918 mips_expand_conditional_branch (rtx *operands, enum rtx_code code)
3920 rtx op0, op1, condition;
3922 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3923 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3924 emit_jump_insn (gen_condjump (condition, operands[0]));
3927 /* Implement:
3929 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3930 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3932 void
3933 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3934 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3936 rtx cmp_result;
3937 bool reversed_p;
3939 reversed_p = mips_reversed_fp_cond (&cond);
3940 cmp_result = gen_reg_rtx (CCV2mode);
3941 emit_insn (gen_scc_ps (cmp_result,
3942 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3943 if (reversed_p)
3944 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3945 cmp_result));
3946 else
3947 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3948 cmp_result));
3951 /* Compare cmp_operands[0] with cmp_operands[1] using the code of
3952 OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] if the condition
3953 holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
3955 void
3956 mips_expand_conditional_move (rtx *operands)
3958 enum rtx_code code;
3959 rtx cond, op0, op1;
3961 code = GET_CODE (operands[1]);
3962 mips_emit_compare (&code, &op0, &op1, true);
3963 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1),
3964 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3965 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
3966 operands[2], operands[3])));
3969 /* Compare cmp_operands[0] with cmp_operands[1] using rtl code CODE,
3970 then trap if the condition holds. */
3972 void
3973 mips_expand_conditional_trap (enum rtx_code code)
3975 rtx op0, op1;
3976 enum machine_mode mode;
3978 /* MIPS conditional trap instructions don't have GT or LE flavors,
3979 so we must swap the operands and convert to LT and GE respectively. */
3980 switch (code)
3982 case GT:
3983 case LE:
3984 case GTU:
3985 case LEU:
3986 code = swap_condition (code);
3987 op0 = cmp_operands[1];
3988 op1 = cmp_operands[0];
3989 break;
3991 default:
3992 op0 = cmp_operands[0];
3993 op1 = cmp_operands[1];
3994 break;
3997 mode = GET_MODE (cmp_operands[0]);
3998 op0 = force_reg (mode, op0);
3999 if (!arith_operand (op1, mode))
4000 op1 = force_reg (mode, op1);
4002 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4003 gen_rtx_fmt_ee (code, mode, op0, op1),
4004 const0_rtx));
4007 /* Initialize *CUM for a call to a function of type FNTYPE. */
4009 void
4010 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4012 memset (cum, 0, sizeof (*cum));
4013 cum->prototype = (fntype && prototype_p (fntype));
4014 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4017 /* Fill INFO with information about a single argument. CUM is the
4018 cumulative state for earlier arguments. MODE is the mode of this
4019 argument and TYPE is its type (if known). NAMED is true if this
4020 is a named (fixed) argument rather than a variable one. */
4022 static void
4023 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4024 enum machine_mode mode, tree type, int named)
4026 bool doubleword_aligned_p;
4027 unsigned int num_bytes, num_words, max_regs;
4029 /* Work out the size of the argument. */
4030 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4031 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4033 /* Decide whether it should go in a floating-point register, assuming
4034 one is free. Later code checks for availability.
4036 The checks against UNITS_PER_FPVALUE handle the soft-float and
4037 single-float cases. */
4038 switch (mips_abi)
4040 case ABI_EABI:
4041 /* The EABI conventions have traditionally been defined in terms
4042 of TYPE_MODE, regardless of the actual type. */
4043 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4044 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4045 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4046 break;
4048 case ABI_32:
4049 case ABI_O64:
4050 /* Only leading floating-point scalars are passed in
4051 floating-point registers. We also handle vector floats the same
4052 say, which is OK because they are not covered by the standard ABI. */
4053 info->fpr_p = (!cum->gp_reg_found
4054 && cum->arg_number < 2
4055 && (type == 0
4056 || SCALAR_FLOAT_TYPE_P (type)
4057 || VECTOR_FLOAT_TYPE_P (type))
4058 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4059 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4060 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4061 break;
4063 case ABI_N32:
4064 case ABI_64:
4065 /* Scalar, complex and vector floating-point types are passed in
4066 floating-point registers, as long as this is a named rather
4067 than a variable argument. */
4068 info->fpr_p = (named
4069 && (type == 0 || FLOAT_TYPE_P (type))
4070 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4071 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4072 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4073 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4075 /* ??? According to the ABI documentation, the real and imaginary
4076 parts of complex floats should be passed in individual registers.
4077 The real and imaginary parts of stack arguments are supposed
4078 to be contiguous and there should be an extra word of padding
4079 at the end.
4081 This has two problems. First, it makes it impossible to use a
4082 single "void *" va_list type, since register and stack arguments
4083 are passed differently. (At the time of writing, MIPSpro cannot
4084 handle complex float varargs correctly.) Second, it's unclear
4085 what should happen when there is only one register free.
4087 For now, we assume that named complex floats should go into FPRs
4088 if there are two FPRs free, otherwise they should be passed in the
4089 same way as a struct containing two floats. */
4090 if (info->fpr_p
4091 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4092 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4094 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4095 info->fpr_p = false;
4096 else
4097 num_words = 2;
4099 break;
4101 default:
4102 gcc_unreachable ();
4105 /* See whether the argument has doubleword alignment. */
4106 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4108 /* Set REG_OFFSET to the register count we're interested in.
4109 The EABI allocates the floating-point registers separately,
4110 but the other ABIs allocate them like integer registers. */
4111 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4112 ? cum->num_fprs
4113 : cum->num_gprs);
4115 /* Advance to an even register if the argument is doubleword-aligned. */
4116 if (doubleword_aligned_p)
4117 info->reg_offset += info->reg_offset & 1;
4119 /* Work out the offset of a stack argument. */
4120 info->stack_offset = cum->stack_words;
4121 if (doubleword_aligned_p)
4122 info->stack_offset += info->stack_offset & 1;
4124 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4126 /* Partition the argument between registers and stack. */
4127 info->reg_words = MIN (num_words, max_regs);
4128 info->stack_words = num_words - info->reg_words;
4131 /* INFO describes a register argument that has the normal format for the
4132 argument's mode. Return the register it uses, assuming that FPRs are
4133 available if HARD_FLOAT_P. */
4135 static unsigned int
4136 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4138 if (!info->fpr_p || !hard_float_p)
4139 return GP_ARG_FIRST + info->reg_offset;
4140 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4141 /* In o32, the second argument is always passed in $f14
4142 for TARGET_DOUBLE_FLOAT, regardless of whether the
4143 first argument was a word or doubleword. */
4144 return FP_ARG_FIRST + 2;
4145 else
4146 return FP_ARG_FIRST + info->reg_offset;
4149 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4151 static bool
4152 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4154 return !TARGET_OLDABI;
4157 /* Implement FUNCTION_ARG. */
4160 mips_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4161 tree type, int named)
4163 struct mips_arg_info info;
4165 /* We will be called with a mode of VOIDmode after the last argument
4166 has been seen. Whatever we return will be passed to the call expander.
4167 If we need a MIPS16 fp_code, return a REG with the code stored as
4168 the mode. */
4169 if (mode == VOIDmode)
4171 if (TARGET_MIPS16 && cum->fp_code != 0)
4172 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4173 else
4174 return NULL;
4177 mips_get_arg_info (&info, cum, mode, type, named);
4179 /* Return straight away if the whole argument is passed on the stack. */
4180 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4181 return NULL;
4183 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4184 contains a double in its entirety, then that 64-bit chunk is passed
4185 in a floating-point register. */
4186 if (TARGET_NEWABI
4187 && TARGET_HARD_FLOAT
4188 && named
4189 && type != 0
4190 && TREE_CODE (type) == RECORD_TYPE
4191 && TYPE_SIZE_UNIT (type)
4192 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4194 tree field;
4196 /* First check to see if there is any such field. */
4197 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4198 if (TREE_CODE (field) == FIELD_DECL
4199 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4200 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4201 && host_integerp (bit_position (field), 0)
4202 && int_bit_position (field) % BITS_PER_WORD == 0)
4203 break;
4205 if (field != 0)
4207 /* Now handle the special case by returning a PARALLEL
4208 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4209 chunks are passed in registers. */
4210 unsigned int i;
4211 HOST_WIDE_INT bitpos;
4212 rtx ret;
4214 /* assign_parms checks the mode of ENTRY_PARM, so we must
4215 use the actual mode here. */
4216 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4218 bitpos = 0;
4219 field = TYPE_FIELDS (type);
4220 for (i = 0; i < info.reg_words; i++)
4222 rtx reg;
4224 for (; field; field = TREE_CHAIN (field))
4225 if (TREE_CODE (field) == FIELD_DECL
4226 && int_bit_position (field) >= bitpos)
4227 break;
4229 if (field
4230 && int_bit_position (field) == bitpos
4231 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4232 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4233 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4234 else
4235 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4237 XVECEXP (ret, 0, i)
4238 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4239 GEN_INT (bitpos / BITS_PER_UNIT));
4241 bitpos += BITS_PER_WORD;
4243 return ret;
4247 /* Handle the n32/n64 conventions for passing complex floating-point
4248 arguments in FPR pairs. The real part goes in the lower register
4249 and the imaginary part goes in the upper register. */
4250 if (TARGET_NEWABI
4251 && info.fpr_p
4252 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4254 rtx real, imag;
4255 enum machine_mode inner;
4256 unsigned int regno;
4258 inner = GET_MODE_INNER (mode);
4259 regno = FP_ARG_FIRST + info.reg_offset;
4260 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4262 /* Real part in registers, imaginary part on stack. */
4263 gcc_assert (info.stack_words == info.reg_words);
4264 return gen_rtx_REG (inner, regno);
4266 else
4268 gcc_assert (info.stack_words == 0);
4269 real = gen_rtx_EXPR_LIST (VOIDmode,
4270 gen_rtx_REG (inner, regno),
4271 const0_rtx);
4272 imag = gen_rtx_EXPR_LIST (VOIDmode,
4273 gen_rtx_REG (inner,
4274 regno + info.reg_words / 2),
4275 GEN_INT (GET_MODE_SIZE (inner)));
4276 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4280 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4283 /* Implement FUNCTION_ARG_ADVANCE. */
4285 void
4286 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4287 tree type, int named)
4289 struct mips_arg_info info;
4291 mips_get_arg_info (&info, cum, mode, type, named);
4293 if (!info.fpr_p)
4294 cum->gp_reg_found = true;
4296 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4297 an explanation of what this code does. It assumes that we're using
4298 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4299 in FPRs. */
4300 if (cum->arg_number < 2 && info.fpr_p)
4301 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4303 /* Advance the register count. This has the effect of setting
4304 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4305 argument required us to skip the final GPR and pass the whole
4306 argument on the stack. */
4307 if (mips_abi != ABI_EABI || !info.fpr_p)
4308 cum->num_gprs = info.reg_offset + info.reg_words;
4309 else if (info.reg_words > 0)
4310 cum->num_fprs += MAX_FPRS_PER_FMT;
4312 /* Advance the stack word count. */
4313 if (info.stack_words > 0)
4314 cum->stack_words = info.stack_offset + info.stack_words;
4316 cum->arg_number++;
4319 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4321 static int
4322 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4323 enum machine_mode mode, tree type, bool named)
4325 struct mips_arg_info info;
4327 mips_get_arg_info (&info, cum, mode, type, named);
4328 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4331 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4332 PARM_BOUNDARY bits of alignment, but will be given anything up
4333 to STACK_BOUNDARY bits if the type requires it. */
4336 mips_function_arg_boundary (enum machine_mode mode, tree type)
4338 unsigned int alignment;
4340 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4341 if (alignment < PARM_BOUNDARY)
4342 alignment = PARM_BOUNDARY;
4343 if (alignment > STACK_BOUNDARY)
4344 alignment = STACK_BOUNDARY;
4345 return alignment;
4348 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4349 upward rather than downward. In other words, return true if the
4350 first byte of the stack slot has useful data, false if the last
4351 byte does. */
4353 bool
4354 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
4356 /* On little-endian targets, the first byte of every stack argument
4357 is passed in the first byte of the stack slot. */
4358 if (!BYTES_BIG_ENDIAN)
4359 return true;
4361 /* Otherwise, integral types are padded downward: the last byte of a
4362 stack argument is passed in the last byte of the stack slot. */
4363 if (type != 0
4364 ? (INTEGRAL_TYPE_P (type)
4365 || POINTER_TYPE_P (type)
4366 || FIXED_POINT_TYPE_P (type))
4367 : (SCALAR_INT_MODE_P (mode)
4368 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
4369 return false;
4371 /* Big-endian o64 pads floating-point arguments downward. */
4372 if (mips_abi == ABI_O64)
4373 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4374 return false;
4376 /* Other types are padded upward for o32, o64, n32 and n64. */
4377 if (mips_abi != ABI_EABI)
4378 return true;
4380 /* Arguments smaller than a stack slot are padded downward. */
4381 if (mode != BLKmode)
4382 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
4383 else
4384 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
4387 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4388 if the least significant byte of the register has useful data. Return
4389 the opposite if the most significant byte does. */
4391 bool
4392 mips_pad_reg_upward (enum machine_mode mode, tree type)
4394 /* No shifting is required for floating-point arguments. */
4395 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4396 return !BYTES_BIG_ENDIAN;
4398 /* Otherwise, apply the same padding to register arguments as we do
4399 to stack arguments. */
4400 return mips_pad_arg_upward (mode, type);
4403 /* Return nonzero when an argument must be passed by reference. */
4405 static bool
4406 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4407 enum machine_mode mode, const_tree type,
4408 bool named ATTRIBUTE_UNUSED)
4410 if (mips_abi == ABI_EABI)
4412 int size;
4414 /* ??? How should SCmode be handled? */
4415 if (mode == DImode || mode == DFmode
4416 || mode == DQmode || mode == UDQmode
4417 || mode == DAmode || mode == UDAmode)
4418 return 0;
4420 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4421 return size == -1 || size > UNITS_PER_WORD;
4423 else
4425 /* If we have a variable-sized parameter, we have no choice. */
4426 return targetm.calls.must_pass_in_stack (mode, type);
4430 /* Implement TARGET_CALLEE_COPIES. */
4432 static bool
4433 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4434 enum machine_mode mode ATTRIBUTE_UNUSED,
4435 const_tree type ATTRIBUTE_UNUSED, bool named)
4437 return mips_abi == ABI_EABI && named;
4440 /* See whether VALTYPE is a record whose fields should be returned in
4441 floating-point registers. If so, return the number of fields and
4442 list them in FIELDS (which should have two elements). Return 0
4443 otherwise.
4445 For n32 & n64, a structure with one or two fields is returned in
4446 floating-point registers as long as every field has a floating-point
4447 type. */
4449 static int
4450 mips_fpr_return_fields (const_tree valtype, tree *fields)
4452 tree field;
4453 int i;
4455 if (!TARGET_NEWABI)
4456 return 0;
4458 if (TREE_CODE (valtype) != RECORD_TYPE)
4459 return 0;
4461 i = 0;
4462 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
4464 if (TREE_CODE (field) != FIELD_DECL)
4465 continue;
4467 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
4468 return 0;
4470 if (i == 2)
4471 return 0;
4473 fields[i++] = field;
4475 return i;
4478 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
4479 a value in the most significant part of $2/$3 if:
4481 - the target is big-endian;
4483 - the value has a structure or union type (we generalize this to
4484 cover aggregates from other languages too); and
4486 - the structure is not returned in floating-point registers. */
4488 static bool
4489 mips_return_in_msb (const_tree valtype)
4491 tree fields[2];
4493 return (TARGET_NEWABI
4494 && TARGET_BIG_ENDIAN
4495 && AGGREGATE_TYPE_P (valtype)
4496 && mips_fpr_return_fields (valtype, fields) == 0);
4499 /* Return true if the function return value MODE will get returned in a
4500 floating-point register. */
4502 static bool
4503 mips_return_mode_in_fpr_p (enum machine_mode mode)
4505 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
4506 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
4507 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4508 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
4511 /* Return the representation of an FPR return register when the
4512 value being returned in FP_RETURN has mode VALUE_MODE and the
4513 return type itself has mode TYPE_MODE. On NewABI targets,
4514 the two modes may be different for structures like:
4516 struct __attribute__((packed)) foo { float f; }
4518 where we return the SFmode value of "f" in FP_RETURN, but where
4519 the structure itself has mode BLKmode. */
4521 static rtx
4522 mips_return_fpr_single (enum machine_mode type_mode,
4523 enum machine_mode value_mode)
4525 rtx x;
4527 x = gen_rtx_REG (value_mode, FP_RETURN);
4528 if (type_mode != value_mode)
4530 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
4531 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
4533 return x;
4536 /* Return a composite value in a pair of floating-point registers.
4537 MODE1 and OFFSET1 are the mode and byte offset for the first value,
4538 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
4539 complete value.
4541 For n32 & n64, $f0 always holds the first value and $f2 the second.
4542 Otherwise the values are packed together as closely as possible. */
4544 static rtx
4545 mips_return_fpr_pair (enum machine_mode mode,
4546 enum machine_mode mode1, HOST_WIDE_INT offset1,
4547 enum machine_mode mode2, HOST_WIDE_INT offset2)
4549 int inc;
4551 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
4552 return gen_rtx_PARALLEL
4553 (mode,
4554 gen_rtvec (2,
4555 gen_rtx_EXPR_LIST (VOIDmode,
4556 gen_rtx_REG (mode1, FP_RETURN),
4557 GEN_INT (offset1)),
4558 gen_rtx_EXPR_LIST (VOIDmode,
4559 gen_rtx_REG (mode2, FP_RETURN + inc),
4560 GEN_INT (offset2))));
4564 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
4565 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
4566 VALTYPE is null and MODE is the mode of the return value. */
4569 mips_function_value (const_tree valtype, enum machine_mode mode)
4571 if (valtype)
4573 tree fields[2];
4574 int unsigned_p;
4576 mode = TYPE_MODE (valtype);
4577 unsigned_p = TYPE_UNSIGNED (valtype);
4579 /* Since TARGET_PROMOTE_FUNCTION_RETURN unconditionally returns true,
4580 we must promote the mode just as PROMOTE_MODE does. */
4581 mode = promote_mode (valtype, mode, &unsigned_p, 1);
4583 /* Handle structures whose fields are returned in $f0/$f2. */
4584 switch (mips_fpr_return_fields (valtype, fields))
4586 case 1:
4587 return mips_return_fpr_single (mode,
4588 TYPE_MODE (TREE_TYPE (fields[0])));
4590 case 2:
4591 return mips_return_fpr_pair (mode,
4592 TYPE_MODE (TREE_TYPE (fields[0])),
4593 int_byte_position (fields[0]),
4594 TYPE_MODE (TREE_TYPE (fields[1])),
4595 int_byte_position (fields[1]));
4598 /* If a value is passed in the most significant part of a register, see
4599 whether we have to round the mode up to a whole number of words. */
4600 if (mips_return_in_msb (valtype))
4602 HOST_WIDE_INT size = int_size_in_bytes (valtype);
4603 if (size % UNITS_PER_WORD != 0)
4605 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
4606 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
4610 /* For EABI, the class of return register depends entirely on MODE.
4611 For example, "struct { some_type x; }" and "union { some_type x; }"
4612 are returned in the same way as a bare "some_type" would be.
4613 Other ABIs only use FPRs for scalar, complex or vector types. */
4614 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
4615 return gen_rtx_REG (mode, GP_RETURN);
4618 if (!TARGET_MIPS16)
4620 /* Handle long doubles for n32 & n64. */
4621 if (mode == TFmode)
4622 return mips_return_fpr_pair (mode,
4623 DImode, 0,
4624 DImode, GET_MODE_SIZE (mode) / 2);
4626 if (mips_return_mode_in_fpr_p (mode))
4628 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4629 return mips_return_fpr_pair (mode,
4630 GET_MODE_INNER (mode), 0,
4631 GET_MODE_INNER (mode),
4632 GET_MODE_SIZE (mode) / 2);
4633 else
4634 return gen_rtx_REG (mode, FP_RETURN);
4638 return gen_rtx_REG (mode, GP_RETURN);
4641 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
4642 all BLKmode objects are returned in memory. Under the n32, n64
4643 and embedded ABIs, small structures are returned in a register.
4644 Objects with varying size must still be returned in memory, of
4645 course. */
4647 static bool
4648 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
4650 return (TARGET_OLDABI
4651 ? TYPE_MODE (type) == BLKmode
4652 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
4655 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
4657 static void
4658 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4659 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4660 int no_rtl)
4662 CUMULATIVE_ARGS local_cum;
4663 int gp_saved, fp_saved;
4665 /* The caller has advanced CUM up to, but not beyond, the last named
4666 argument. Advance a local copy of CUM past the last "real" named
4667 argument, to find out how many registers are left over. */
4668 local_cum = *cum;
4669 FUNCTION_ARG_ADVANCE (local_cum, mode, type, true);
4671 /* Found out how many registers we need to save. */
4672 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4673 fp_saved = (EABI_FLOAT_VARARGS_P
4674 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4675 : 0);
4677 if (!no_rtl)
4679 if (gp_saved > 0)
4681 rtx ptr, mem;
4683 ptr = plus_constant (virtual_incoming_args_rtx,
4684 REG_PARM_STACK_SPACE (cfun->decl)
4685 - gp_saved * UNITS_PER_WORD);
4686 mem = gen_frame_mem (BLKmode, ptr);
4687 set_mem_alias_set (mem, get_varargs_alias_set ());
4689 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4690 mem, gp_saved);
4692 if (fp_saved > 0)
4694 /* We can't use move_block_from_reg, because it will use
4695 the wrong mode. */
4696 enum machine_mode mode;
4697 int off, i;
4699 /* Set OFF to the offset from virtual_incoming_args_rtx of
4700 the first float register. The FP save area lies below
4701 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4702 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
4703 off -= fp_saved * UNITS_PER_FPREG;
4705 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4707 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
4708 i += MAX_FPRS_PER_FMT)
4710 rtx ptr, mem;
4712 ptr = plus_constant (virtual_incoming_args_rtx, off);
4713 mem = gen_frame_mem (mode, ptr);
4714 set_mem_alias_set (mem, get_varargs_alias_set ());
4715 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4716 off += UNITS_PER_HWFPVALUE;
4720 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4721 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4722 + fp_saved * UNITS_PER_FPREG);
4725 /* Implement TARGET_BUILTIN_VA_LIST. */
4727 static tree
4728 mips_build_builtin_va_list (void)
4730 if (EABI_FLOAT_VARARGS_P)
4732 /* We keep 3 pointers, and two offsets.
4734 Two pointers are to the overflow area, which starts at the CFA.
4735 One of these is constant, for addressing into the GPR save area
4736 below it. The other is advanced up the stack through the
4737 overflow region.
4739 The third pointer is to the bottom of the GPR save area.
4740 Since the FPR save area is just below it, we can address
4741 FPR slots off this pointer.
4743 We also keep two one-byte offsets, which are to be subtracted
4744 from the constant pointers to yield addresses in the GPR and
4745 FPR save areas. These are downcounted as float or non-float
4746 arguments are used, and when they get to zero, the argument
4747 must be obtained from the overflow region. */
4748 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4749 tree array, index;
4751 record = lang_hooks.types.make_type (RECORD_TYPE);
4753 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4754 ptr_type_node);
4755 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4756 ptr_type_node);
4757 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4758 ptr_type_node);
4759 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4760 unsigned_char_type_node);
4761 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4762 unsigned_char_type_node);
4763 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4764 warn on every user file. */
4765 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4766 array = build_array_type (unsigned_char_type_node,
4767 build_index_type (index));
4768 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4770 DECL_FIELD_CONTEXT (f_ovfl) = record;
4771 DECL_FIELD_CONTEXT (f_gtop) = record;
4772 DECL_FIELD_CONTEXT (f_ftop) = record;
4773 DECL_FIELD_CONTEXT (f_goff) = record;
4774 DECL_FIELD_CONTEXT (f_foff) = record;
4775 DECL_FIELD_CONTEXT (f_res) = record;
4777 TYPE_FIELDS (record) = f_ovfl;
4778 TREE_CHAIN (f_ovfl) = f_gtop;
4779 TREE_CHAIN (f_gtop) = f_ftop;
4780 TREE_CHAIN (f_ftop) = f_goff;
4781 TREE_CHAIN (f_goff) = f_foff;
4782 TREE_CHAIN (f_foff) = f_res;
4784 layout_type (record);
4785 return record;
4787 else if (TARGET_IRIX && TARGET_IRIX6)
4788 /* On IRIX 6, this type is 'char *'. */
4789 return build_pointer_type (char_type_node);
4790 else
4791 /* Otherwise, we use 'void *'. */
4792 return ptr_type_node;
4795 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
4797 static void
4798 mips_va_start (tree valist, rtx nextarg)
4800 if (EABI_FLOAT_VARARGS_P)
4802 const CUMULATIVE_ARGS *cum;
4803 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4804 tree ovfl, gtop, ftop, goff, foff;
4805 tree t;
4806 int gpr_save_area_size;
4807 int fpr_save_area_size;
4808 int fpr_offset;
4810 cum = &crtl->args.info;
4811 gpr_save_area_size
4812 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4813 fpr_save_area_size
4814 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4816 f_ovfl = TYPE_FIELDS (va_list_type_node);
4817 f_gtop = TREE_CHAIN (f_ovfl);
4818 f_ftop = TREE_CHAIN (f_gtop);
4819 f_goff = TREE_CHAIN (f_ftop);
4820 f_foff = TREE_CHAIN (f_goff);
4822 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4823 NULL_TREE);
4824 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4825 NULL_TREE);
4826 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4827 NULL_TREE);
4828 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4829 NULL_TREE);
4830 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4831 NULL_TREE);
4833 /* Emit code to initialize OVFL, which points to the next varargs
4834 stack argument. CUM->STACK_WORDS gives the number of stack
4835 words used by named arguments. */
4836 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4837 if (cum->stack_words > 0)
4838 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
4839 size_int (cum->stack_words * UNITS_PER_WORD));
4840 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4841 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4843 /* Emit code to initialize GTOP, the top of the GPR save area. */
4844 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4845 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gtop), gtop, t);
4846 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4848 /* Emit code to initialize FTOP, the top of the FPR save area.
4849 This address is gpr_save_area_bytes below GTOP, rounded
4850 down to the next fp-aligned boundary. */
4851 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4852 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4853 fpr_offset &= -UNITS_PER_FPVALUE;
4854 if (fpr_offset)
4855 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
4856 size_int (-fpr_offset));
4857 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ftop), ftop, t);
4858 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4860 /* Emit code to initialize GOFF, the offset from GTOP of the
4861 next GPR argument. */
4862 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (goff), goff,
4863 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
4864 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4866 /* Likewise emit code to initialize FOFF, the offset from FTOP
4867 of the next FPR argument. */
4868 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (foff), foff,
4869 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
4870 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4872 else
4874 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4875 std_expand_builtin_va_start (valist, nextarg);
4879 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
4881 static tree
4882 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4884 tree addr;
4885 bool indirect_p;
4887 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4888 if (indirect_p)
4889 type = build_pointer_type (type);
4891 if (!EABI_FLOAT_VARARGS_P)
4892 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4893 else
4895 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4896 tree ovfl, top, off, align;
4897 HOST_WIDE_INT size, rsize, osize;
4898 tree t, u;
4900 f_ovfl = TYPE_FIELDS (va_list_type_node);
4901 f_gtop = TREE_CHAIN (f_ovfl);
4902 f_ftop = TREE_CHAIN (f_gtop);
4903 f_goff = TREE_CHAIN (f_ftop);
4904 f_foff = TREE_CHAIN (f_goff);
4906 /* Let:
4908 TOP be the top of the GPR or FPR save area;
4909 OFF be the offset from TOP of the next register;
4910 ADDR_RTX be the address of the argument;
4911 SIZE be the number of bytes in the argument type;
4912 RSIZE be the number of bytes used to store the argument
4913 when it's in the register save area; and
4914 OSIZE be the number of bytes used to store it when it's
4915 in the stack overflow area.
4917 The code we want is:
4919 1: off &= -rsize; // round down
4920 2: if (off != 0)
4921 3: {
4922 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
4923 5: off -= rsize;
4924 6: }
4925 7: else
4926 8: {
4927 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
4928 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
4929 11: ovfl += osize;
4930 14: }
4932 [1] and [9] can sometimes be optimized away. */
4934 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4935 NULL_TREE);
4936 size = int_size_in_bytes (type);
4938 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4939 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4941 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4942 NULL_TREE);
4943 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4944 NULL_TREE);
4946 /* When va_start saves FPR arguments to the stack, each slot
4947 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
4948 argument's precision. */
4949 rsize = UNITS_PER_HWFPVALUE;
4951 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4952 (= PARM_BOUNDARY bits). This can be different from RSIZE
4953 in two cases:
4955 (1) On 32-bit targets when TYPE is a structure such as:
4957 struct s { float f; };
4959 Such structures are passed in paired FPRs, so RSIZE
4960 will be 8 bytes. However, the structure only takes
4961 up 4 bytes of memory, so OSIZE will only be 4.
4963 (2) In combinations such as -mgp64 -msingle-float
4964 -fshort-double. Doubles passed in registers will then take
4965 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
4966 stack take up UNITS_PER_WORD bytes. */
4967 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4969 else
4971 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4972 NULL_TREE);
4973 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4974 NULL_TREE);
4975 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4976 if (rsize > UNITS_PER_WORD)
4978 /* [1] Emit code for: off &= -rsize. */
4979 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4980 build_int_cst (NULL_TREE, -rsize));
4981 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (off), off, t);
4982 gimplify_and_add (t, pre_p);
4984 osize = rsize;
4987 /* [2] Emit code to branch if off == 0. */
4988 t = build2 (NE_EXPR, boolean_type_node, off,
4989 build_int_cst (TREE_TYPE (off), 0));
4990 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4992 /* [5] Emit code for: off -= rsize. We do this as a form of
4993 post-decrement not available to C. */
4994 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4995 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4997 /* [4] Emit code for:
4998 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
4999 t = fold_convert (sizetype, t);
5000 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5001 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5002 if (BYTES_BIG_ENDIAN && rsize > size)
5004 u = size_int (rsize - size);
5005 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5007 COND_EXPR_THEN (addr) = t;
5009 if (osize > UNITS_PER_WORD)
5011 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5012 u = size_int (osize - 1);
5013 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
5014 t = fold_convert (sizetype, t);
5015 u = size_int (-osize);
5016 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5017 t = fold_convert (TREE_TYPE (ovfl), t);
5018 align = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
5020 else
5021 align = NULL;
5023 /* [10, 11] Emit code for:
5024 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5025 ovfl += osize. */
5026 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5027 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5028 if (BYTES_BIG_ENDIAN && osize > size)
5030 u = size_int (osize - size);
5031 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5034 /* String [9] and [10, 11] together. */
5035 if (align)
5036 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5037 COND_EXPR_ELSE (addr) = t;
5039 addr = fold_convert (build_pointer_type (type), addr);
5040 addr = build_va_arg_indirect_ref (addr);
5043 if (indirect_p)
5044 addr = build_va_arg_indirect_ref (addr);
5046 return addr;
5049 /* A chained list of functions for which mips16_build_call_stub has already
5050 generated a stub. NAME is the name of the function and FP_RET_P is true
5051 if the function returns a value in floating-point registers. */
5052 struct mips16_stub {
5053 struct mips16_stub *next;
5054 char *name;
5055 bool fp_ret_p;
5057 static struct mips16_stub *mips16_stubs;
5059 /* Return the two-character string that identifies floating-point
5060 return mode MODE in the name of a MIPS16 function stub. */
5062 static const char *
5063 mips16_call_stub_mode_suffix (enum machine_mode mode)
5065 if (mode == SFmode)
5066 return "sf";
5067 else if (mode == DFmode)
5068 return "df";
5069 else if (mode == SCmode)
5070 return "sc";
5071 else if (mode == DCmode)
5072 return "dc";
5073 else if (mode == V2SFmode)
5074 return "df";
5075 else
5076 gcc_unreachable ();
5079 /* Write instructions to move a 32-bit value between general register
5080 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5081 from GPREG to FPREG and 'f' to move in the opposite direction. */
5083 static void
5084 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5086 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5087 reg_names[gpreg], reg_names[fpreg]);
5090 /* Likewise for 64-bit values. */
5092 static void
5093 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5095 if (TARGET_64BIT)
5096 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5097 reg_names[gpreg], reg_names[fpreg]);
5098 else if (TARGET_FLOAT64)
5100 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5101 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5102 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5103 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5105 else
5107 /* Move the least-significant word. */
5108 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5109 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5110 /* ...then the most significant word. */
5111 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5112 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5116 /* Write out code to move floating-point arguments into or out of
5117 general registers. FP_CODE is the code describing which arguments
5118 are present (see the comment above the definition of CUMULATIVE_ARGS
5119 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5121 static void
5122 mips_output_args_xfer (int fp_code, char direction)
5124 unsigned int gparg, fparg, f;
5125 CUMULATIVE_ARGS cum;
5127 /* This code only works for o32 and o64. */
5128 gcc_assert (TARGET_OLDABI);
5130 mips_init_cumulative_args (&cum, NULL);
5132 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5134 enum machine_mode mode;
5135 struct mips_arg_info info;
5137 if ((f & 3) == 1)
5138 mode = SFmode;
5139 else if ((f & 3) == 2)
5140 mode = DFmode;
5141 else
5142 gcc_unreachable ();
5144 mips_get_arg_info (&info, &cum, mode, NULL, true);
5145 gparg = mips_arg_regno (&info, false);
5146 fparg = mips_arg_regno (&info, true);
5148 if (mode == SFmode)
5149 mips_output_32bit_xfer (direction, gparg, fparg);
5150 else
5151 mips_output_64bit_xfer (direction, gparg, fparg);
5153 mips_function_arg_advance (&cum, mode, NULL, true);
5157 /* Write a MIPS16 stub for the current function. This stub is used
5158 for functions which take arguments in the floating-point registers.
5159 It is normal-mode code that moves the floating-point arguments
5160 into the general registers and then jumps to the MIPS16 code. */
5162 static void
5163 mips16_build_function_stub (void)
5165 const char *fnname, *separator;
5166 char *secname, *stubname;
5167 tree stubdecl;
5168 unsigned int f;
5170 /* Create the name of the stub, and its unique section. */
5171 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
5172 fnname = targetm.strip_name_encoding (fnname);
5173 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
5174 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
5176 /* Build a decl for the stub. */
5177 stubdecl = build_decl (FUNCTION_DECL, get_identifier (stubname),
5178 build_function_type (void_type_node, NULL_TREE));
5179 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5180 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
5182 /* Output a comment. */
5183 fprintf (asm_out_file, "\t# Stub function for %s (",
5184 current_function_name ());
5185 separator = "";
5186 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
5188 fprintf (asm_out_file, "%s%s", separator,
5189 (f & 3) == 1 ? "float" : "double");
5190 separator = ", ";
5192 fprintf (asm_out_file, ")\n");
5194 /* Write the preamble leading up to the function declaration. */
5195 fprintf (asm_out_file, "\t.set\tnomips16\n");
5196 switch_to_section (function_section (stubdecl));
5197 ASM_OUTPUT_ALIGN (asm_out_file,
5198 floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
5200 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
5201 within a .ent, and we cannot emit another .ent. */
5202 if (!FUNCTION_NAME_ALREADY_DECLARED)
5204 fputs ("\t.ent\t", asm_out_file);
5205 assemble_name (asm_out_file, stubname);
5206 fputs ("\n", asm_out_file);
5209 /* Start the definition proper. */
5210 assemble_name (asm_out_file, stubname);
5211 fputs (":\n", asm_out_file);
5213 /* Load the address of the MIPS16 function into $at. Do this first so
5214 that targets with coprocessor interlocks can use an MFC1 to fill the
5215 delay slot. */
5216 fprintf (asm_out_file, "\t.set\tnoat\n");
5217 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
5218 assemble_name (asm_out_file, fnname);
5219 fprintf (asm_out_file, "\n");
5221 /* Move the arguments from floating-point registers to general registers. */
5222 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
5224 /* Jump to the MIPS16 function. */
5225 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
5226 fprintf (asm_out_file, "\t.set\tat\n");
5228 if (!FUNCTION_NAME_ALREADY_DECLARED)
5230 fputs ("\t.end\t", asm_out_file);
5231 assemble_name (asm_out_file, stubname);
5232 fputs ("\n", asm_out_file);
5235 switch_to_section (function_section (current_function_decl));
5238 /* The current function is a MIPS16 function that returns a value in an FPR.
5239 Copy the return value from its soft-float to its hard-float location.
5240 libgcc2 has special non-MIPS16 helper functions for each case. */
5242 static void
5243 mips16_copy_fpr_return_value (void)
5245 rtx fn, insn, arg, call;
5246 tree id, return_type;
5247 enum machine_mode return_mode;
5249 return_type = DECL_RESULT (current_function_decl);
5250 return_mode = DECL_MODE (return_type);
5252 id = get_identifier (ACONCAT (("__mips16_ret_",
5253 mips16_call_stub_mode_suffix (return_mode),
5254 NULL)));
5255 fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
5256 arg = gen_rtx_REG (return_mode, GP_RETURN);
5257 call = gen_call_value_internal (arg, fn, const0_rtx);
5258 insn = mips_emit_call_insn (call, false);
5259 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), arg);
5262 /* Consider building a stub for a MIPS16 call to function FN.
5263 RETVAL is the location of the return value, or null if this is
5264 a "call" rather than a "call_value". ARGS_SIZE is the size of the
5265 arguments and FP_CODE is the code built by mips_function_arg;
5266 see the comment above CUMULATIVE_ARGS for details.
5268 If a stub was needed, emit the call and return the call insn itself.
5269 Return null otherwise.
5271 A stub is needed for calls to functions that, in normal mode,
5272 receive arguments in FPRs or return values in FPRs. The stub
5273 copies the arguments from their soft-float positions to their
5274 hard-float positions, calls the real function, then copies the
5275 return value from its hard-float position to its soft-float
5276 position.
5278 We emit a JAL to FN even when FN might need a stub. If FN turns out
5279 to be to a non-MIPS16 function, the linker automatically redirects
5280 the JAL to the stub, otherwise the JAL continues to call FN directly. */
5282 static rtx
5283 mips16_build_call_stub (rtx retval, rtx fn, rtx args_size, int fp_code)
5285 const char *fnname;
5286 bool fp_ret_p;
5287 struct mips16_stub *l;
5288 rtx insn;
5290 /* We don't need to do anything if we aren't in MIPS16 mode, or if
5291 we were invoked with the -msoft-float option. */
5292 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
5293 return NULL_RTX;
5295 /* Figure out whether the value might come back in a floating-point
5296 register. */
5297 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
5299 /* We don't need to do anything if there were no floating-point
5300 arguments and the value will not be returned in a floating-point
5301 register. */
5302 if (fp_code == 0 && !fp_ret_p)
5303 return NULL_RTX;
5305 /* We don't need to do anything if this is a call to a special
5306 MIPS16 support function. */
5307 if (GET_CODE (fn) == SYMBOL_REF
5308 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
5309 return NULL_RTX;
5311 /* This code will only work for o32 and o64 abis. The other ABI's
5312 require more sophisticated support. */
5313 gcc_assert (TARGET_OLDABI);
5315 /* If we're calling via a function pointer, use one of the magic
5316 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
5317 Each stub expects the function address to arrive in register $2. */
5318 if (GET_CODE (fn) != SYMBOL_REF)
5320 char buf[30];
5321 tree id;
5322 rtx stub_fn, insn;
5324 /* Create a SYMBOL_REF for the libgcc.a function. */
5325 if (fp_ret_p)
5326 sprintf (buf, "__mips16_call_stub_%s_%d",
5327 mips16_call_stub_mode_suffix (GET_MODE (retval)),
5328 fp_code);
5329 else
5330 sprintf (buf, "__mips16_call_stub_%d", fp_code);
5331 id = get_identifier (buf);
5332 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
5334 /* Load the target function into $2. */
5335 mips_emit_move (gen_rtx_REG (Pmode, 2), fn);
5337 /* Emit the call. */
5338 if (retval == NULL_RTX)
5339 insn = gen_call_internal (stub_fn, args_size);
5340 else
5341 insn = gen_call_value_internal (retval, stub_fn, args_size);
5342 insn = mips_emit_call_insn (insn, false);
5344 /* Tell GCC that this call does indeed use the value of $2. */
5345 CALL_INSN_FUNCTION_USAGE (insn) =
5346 gen_rtx_EXPR_LIST (VOIDmode,
5347 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
5348 CALL_INSN_FUNCTION_USAGE (insn));
5350 /* If we are handling a floating-point return value, we need to
5351 save $18 in the function prologue. Putting a note on the
5352 call will mean that df_regs_ever_live_p ($18) will be true if the
5353 call is not eliminated, and we can check that in the prologue
5354 code. */
5355 if (fp_ret_p)
5356 CALL_INSN_FUNCTION_USAGE (insn) =
5357 gen_rtx_EXPR_LIST (VOIDmode,
5358 gen_rtx_USE (VOIDmode,
5359 gen_rtx_REG (word_mode, 18)),
5360 CALL_INSN_FUNCTION_USAGE (insn));
5362 return insn;
5365 /* We know the function we are going to call. If we have already
5366 built a stub, we don't need to do anything further. */
5367 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
5368 for (l = mips16_stubs; l != NULL; l = l->next)
5369 if (strcmp (l->name, fnname) == 0)
5370 break;
5372 if (l == NULL)
5374 const char *separator;
5375 char *secname, *stubname;
5376 tree stubid, stubdecl;
5377 unsigned int f;
5379 /* If the function does not return in FPRs, the special stub
5380 section is named
5381 .mips16.call.FNNAME
5383 If the function does return in FPRs, the stub section is named
5384 .mips16.call.fp.FNNAME
5386 Build a decl for the stub. */
5387 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
5388 fnname, NULL));
5389 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
5390 fnname, NULL));
5391 stubid = get_identifier (stubname);
5392 stubdecl = build_decl (FUNCTION_DECL, stubid,
5393 build_function_type (void_type_node, NULL_TREE));
5394 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5395 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE,
5396 void_type_node);
5398 /* Output a comment. */
5399 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
5400 (fp_ret_p
5401 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
5402 : ""),
5403 fnname);
5404 separator = "";
5405 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5407 fprintf (asm_out_file, "%s%s", separator,
5408 (f & 3) == 1 ? "float" : "double");
5409 separator = ", ";
5411 fprintf (asm_out_file, ")\n");
5413 /* Write the preamble leading up to the function declaration. */
5414 fprintf (asm_out_file, "\t.set\tnomips16\n");
5415 assemble_start_function (stubdecl, stubname);
5417 if (!FUNCTION_NAME_ALREADY_DECLARED)
5419 fputs ("\t.ent\t", asm_out_file);
5420 assemble_name (asm_out_file, stubname);
5421 fputs ("\n", asm_out_file);
5423 assemble_name (asm_out_file, stubname);
5424 fputs (":\n", asm_out_file);
5427 if (!fp_ret_p)
5429 /* Load the address of the MIPS16 function into $at. Do this
5430 first so that targets with coprocessor interlocks can use
5431 an MFC1 to fill the delay slot. */
5432 fprintf (asm_out_file, "\t.set\tnoat\n");
5433 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
5434 fnname);
5437 /* Move the arguments from general registers to floating-point
5438 registers. */
5439 mips_output_args_xfer (fp_code, 't');
5441 if (!fp_ret_p)
5443 /* Jump to the previously-loaded address. */
5444 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
5445 fprintf (asm_out_file, "\t.set\tat\n");
5447 else
5449 /* Save the return address in $18 and call the non-MIPS16 function.
5450 The stub's caller knows that $18 might be clobbered, even though
5451 $18 is usually a call-saved register. */
5452 fprintf (asm_out_file, "\tmove\t%s,%s\n",
5453 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
5454 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
5456 /* Move the result from floating-point registers to
5457 general registers. */
5458 switch (GET_MODE (retval))
5460 case SCmode:
5461 mips_output_32bit_xfer ('f', GP_RETURN + 1,
5462 FP_REG_FIRST + MAX_FPRS_PER_FMT);
5463 /* Fall though. */
5464 case SFmode:
5465 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
5466 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
5468 /* On 64-bit targets, complex floats are returned in
5469 a single GPR, such that "sd" on a suitably-aligned
5470 target would store the value correctly. */
5471 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
5472 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
5473 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
5474 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
5475 reg_names[GP_RETURN],
5476 reg_names[GP_RETURN],
5477 reg_names[GP_RETURN + 1]);
5479 break;
5481 case DCmode:
5482 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
5483 FP_REG_FIRST + MAX_FPRS_PER_FMT);
5484 /* Fall though. */
5485 case DFmode:
5486 case V2SFmode:
5487 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
5488 break;
5490 default:
5491 gcc_unreachable ();
5493 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
5496 #ifdef ASM_DECLARE_FUNCTION_SIZE
5497 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
5498 #endif
5500 if (!FUNCTION_NAME_ALREADY_DECLARED)
5502 fputs ("\t.end\t", asm_out_file);
5503 assemble_name (asm_out_file, stubname);
5504 fputs ("\n", asm_out_file);
5507 /* Record this stub. */
5508 l = XNEW (struct mips16_stub);
5509 l->name = xstrdup (fnname);
5510 l->fp_ret_p = fp_ret_p;
5511 l->next = mips16_stubs;
5512 mips16_stubs = l;
5515 /* If we expect a floating-point return value, but we've built a
5516 stub which does not expect one, then we're in trouble. We can't
5517 use the existing stub, because it won't handle the floating-point
5518 value. We can't build a new stub, because the linker won't know
5519 which stub to use for the various calls in this object file.
5520 Fortunately, this case is illegal, since it means that a function
5521 was declared in two different ways in a single compilation. */
5522 if (fp_ret_p && !l->fp_ret_p)
5523 error ("cannot handle inconsistent calls to %qs", fnname);
5525 if (retval == NULL_RTX)
5526 insn = gen_call_internal_direct (fn, args_size);
5527 else
5528 insn = gen_call_value_internal_direct (retval, fn, args_size);
5529 insn = mips_emit_call_insn (insn, false);
5531 /* If we are calling a stub which handles a floating-point return
5532 value, we need to arrange to save $18 in the prologue. We do this
5533 by marking the function call as using the register. The prologue
5534 will later see that it is used, and emit code to save it. */
5535 if (fp_ret_p)
5536 CALL_INSN_FUNCTION_USAGE (insn) =
5537 gen_rtx_EXPR_LIST (VOIDmode,
5538 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
5539 CALL_INSN_FUNCTION_USAGE (insn));
5541 return insn;
5544 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5546 static bool
5547 mips_ok_for_lazy_binding_p (rtx x)
5549 return (TARGET_USE_GOT
5550 && GET_CODE (x) == SYMBOL_REF
5551 && !mips_symbol_binds_local_p (x));
5554 /* Load function address ADDR into register DEST. SIBCALL_P is true
5555 if the address is needed for a sibling call. Return true if we
5556 used an explicit lazy-binding sequence. */
5558 static bool
5559 mips_load_call_address (rtx dest, rtx addr, bool sibcall_p)
5561 /* If we're generating PIC, and this call is to a global function,
5562 try to allow its address to be resolved lazily. This isn't
5563 possible for sibcalls when $gp is call-saved because the value
5564 of $gp on entry to the stub would be our caller's gp, not ours. */
5565 if (TARGET_EXPLICIT_RELOCS
5566 && !(sibcall_p && TARGET_CALL_SAVED_GP)
5567 && mips_ok_for_lazy_binding_p (addr))
5569 rtx high, lo_sum_symbol;
5571 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
5572 addr, SYMBOL_GOTOFF_CALL);
5573 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
5574 if (Pmode == SImode)
5575 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
5576 else
5577 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
5578 return true;
5580 else
5582 mips_emit_move (dest, addr);
5583 return false;
5587 /* Expand a "call", "sibcall", "call_value" or "sibcall_value" instruction.
5588 RESULT is where the result will go (null for "call"s and "sibcall"s),
5589 ADDR is the address of the function, ARGS_SIZE is the size of the
5590 arguments and AUX is the value passed to us by mips_function_arg.
5591 SIBCALL_P is true if we are expanding a sibling call, false if we're
5592 expanding a normal call.
5594 Return the call itself. */
5597 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, bool sibcall_p)
5599 rtx orig_addr, pattern, insn;
5600 bool lazy_p;
5602 orig_addr = addr;
5603 lazy_p = false;
5604 if (!call_insn_operand (addr, VOIDmode))
5606 addr = gen_reg_rtx (Pmode);
5607 lazy_p = mips_load_call_address (addr, orig_addr, sibcall_p);
5610 insn = mips16_build_call_stub (result, addr, args_size,
5611 aux == 0 ? 0 : (int) GET_MODE (aux));
5612 if (insn)
5614 gcc_assert (!sibcall_p && !lazy_p);
5615 return insn;
5618 if (result == 0)
5619 pattern = (sibcall_p
5620 ? gen_sibcall_internal (addr, args_size)
5621 : gen_call_internal (addr, args_size));
5622 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
5624 /* Handle return values created by mips_return_fpr_pair. */
5625 rtx reg1, reg2;
5627 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
5628 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
5629 pattern =
5630 (sibcall_p
5631 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
5632 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
5634 else
5636 /* Handle return values created by mips_return_fpr_single. */
5637 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
5638 result = XEXP (XVECEXP (result, 0, 0), 0);
5639 pattern = (sibcall_p
5640 ? gen_sibcall_value_internal (result, addr, args_size)
5641 : gen_call_value_internal (result, addr, args_size));
5644 return mips_emit_call_insn (pattern, lazy_p);
5647 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
5649 static bool
5650 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
5652 if (!TARGET_SIBCALLS)
5653 return false;
5655 /* We can't do a sibcall if the called function is a MIPS16 function
5656 because there is no direct "jx" instruction equivalent to "jalx" to
5657 switch the ISA mode. We only care about cases where the sibling
5658 and normal calls would both be direct. */
5659 if (mips_use_mips16_mode_p (decl)
5660 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
5661 return false;
5663 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
5664 functions could be MIPS16 ones unless an attribute explicitly tells
5665 us otherwise. */
5666 if (TARGET_INTERLINK_MIPS16
5667 && decl
5668 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
5669 && !mips_nomips16_decl_p (decl)
5670 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
5671 return false;
5673 /* Otherwise OK. */
5674 return true;
5677 /* Emit code to move general operand SRC into condition-code
5678 register DEST given that SCRATCH is a scratch TFmode FPR.
5679 The sequence is:
5681 FP1 = SRC
5682 FP2 = 0.0f
5683 DEST = FP2 < FP1
5685 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
5687 void
5688 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
5690 rtx fp1, fp2;
5692 /* Change the source to SFmode. */
5693 if (MEM_P (src))
5694 src = adjust_address (src, SFmode, 0);
5695 else if (REG_P (src) || GET_CODE (src) == SUBREG)
5696 src = gen_rtx_REG (SFmode, true_regnum (src));
5698 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
5699 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
5701 mips_emit_move (copy_rtx (fp1), src);
5702 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
5703 emit_insn (gen_slt_sf (dest, fp2, fp1));
5706 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
5707 Assume that the areas do not overlap. */
5709 static void
5710 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
5712 HOST_WIDE_INT offset, delta;
5713 unsigned HOST_WIDE_INT bits;
5714 int i;
5715 enum machine_mode mode;
5716 rtx *regs;
5718 /* Work out how many bits to move at a time. If both operands have
5719 half-word alignment, it is usually better to move in half words.
5720 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
5721 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
5722 Otherwise move word-sized chunks. */
5723 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
5724 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
5725 bits = BITS_PER_WORD / 2;
5726 else
5727 bits = BITS_PER_WORD;
5729 mode = mode_for_size (bits, MODE_INT, 0);
5730 delta = bits / BITS_PER_UNIT;
5732 /* Allocate a buffer for the temporary registers. */
5733 regs = alloca (sizeof (rtx) * length / delta);
5735 /* Load as many BITS-sized chunks as possible. Use a normal load if
5736 the source has enough alignment, otherwise use left/right pairs. */
5737 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
5739 regs[i] = gen_reg_rtx (mode);
5740 if (MEM_ALIGN (src) >= bits)
5741 mips_emit_move (regs[i], adjust_address (src, mode, offset));
5742 else
5744 rtx part = adjust_address (src, BLKmode, offset);
5745 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
5746 gcc_unreachable ();
5750 /* Copy the chunks to the destination. */
5751 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
5752 if (MEM_ALIGN (dest) >= bits)
5753 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
5754 else
5756 rtx part = adjust_address (dest, BLKmode, offset);
5757 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
5758 gcc_unreachable ();
5761 /* Mop up any left-over bytes. */
5762 if (offset < length)
5764 src = adjust_address (src, BLKmode, offset);
5765 dest = adjust_address (dest, BLKmode, offset);
5766 move_by_pieces (dest, src, length - offset,
5767 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
5771 /* Helper function for doing a loop-based block operation on memory
5772 reference MEM. Each iteration of the loop will operate on LENGTH
5773 bytes of MEM.
5775 Create a new base register for use within the loop and point it to
5776 the start of MEM. Create a new memory reference that uses this
5777 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
5779 static void
5780 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
5781 rtx *loop_reg, rtx *loop_mem)
5783 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
5785 /* Although the new mem does not refer to a known location,
5786 it does keep up to LENGTH bytes of alignment. */
5787 *loop_mem = change_address (mem, BLKmode, *loop_reg);
5788 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
5791 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
5792 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
5793 the memory regions do not overlap. */
5795 static void
5796 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
5797 HOST_WIDE_INT bytes_per_iter)
5799 rtx label, src_reg, dest_reg, final_src;
5800 HOST_WIDE_INT leftover;
5802 leftover = length % bytes_per_iter;
5803 length -= leftover;
5805 /* Create registers and memory references for use within the loop. */
5806 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
5807 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
5809 /* Calculate the value that SRC_REG should have after the last iteration
5810 of the loop. */
5811 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
5812 0, 0, OPTAB_WIDEN);
5814 /* Emit the start of the loop. */
5815 label = gen_label_rtx ();
5816 emit_label (label);
5818 /* Emit the loop body. */
5819 mips_block_move_straight (dest, src, bytes_per_iter);
5821 /* Move on to the next block. */
5822 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
5823 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
5825 /* Emit the loop condition. */
5826 if (Pmode == DImode)
5827 emit_insn (gen_cmpdi (src_reg, final_src));
5828 else
5829 emit_insn (gen_cmpsi (src_reg, final_src));
5830 emit_jump_insn (gen_bne (label));
5832 /* Mop up any left-over bytes. */
5833 if (leftover)
5834 mips_block_move_straight (dest, src, leftover);
5837 /* Expand a movmemsi instruction, which copies LENGTH bytes from
5838 memory reference SRC to memory reference DEST. */
5840 bool
5841 mips_expand_block_move (rtx dest, rtx src, rtx length)
5843 if (GET_CODE (length) == CONST_INT)
5845 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
5847 mips_block_move_straight (dest, src, INTVAL (length));
5848 return true;
5850 else if (optimize)
5852 mips_block_move_loop (dest, src, INTVAL (length),
5853 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
5854 return true;
5857 return false;
5860 /* Expand a loop of synci insns for the address range [BEGIN, END). */
5862 void
5863 mips_expand_synci_loop (rtx begin, rtx end)
5865 rtx inc, label, cmp, cmp_result;
5867 /* Load INC with the cache line size (rdhwr INC,$1). */
5868 inc = gen_reg_rtx (SImode);
5869 emit_insn (gen_rdhwr (inc, const1_rtx));
5871 /* Loop back to here. */
5872 label = gen_label_rtx ();
5873 emit_label (label);
5875 emit_insn (gen_synci (begin));
5877 cmp = mips_force_binary (Pmode, GTU, begin, end);
5879 mips_emit_binary (PLUS, begin, begin, inc);
5881 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
5882 emit_jump_insn (gen_condjump (cmp_result, label));
5885 /* Expand a QI or HI mode atomic memory operation.
5887 GENERATOR contains a pointer to the gen_* function that generates
5888 the SI mode underlying atomic operation using masks that we
5889 calculate.
5891 RESULT is the return register for the operation. Its value is NULL
5892 if unused.
5894 MEM is the location of the atomic access.
5896 OLDVAL is the first operand for the operation.
5898 NEWVAL is the optional second operand for the operation. Its value
5899 is NULL if unused. */
5901 void
5902 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
5903 rtx result, rtx mem, rtx oldval, rtx newval)
5905 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
5906 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
5907 rtx res = NULL;
5908 enum machine_mode mode;
5910 mode = GET_MODE (mem);
5912 /* Compute the address of the containing SImode value. */
5913 orig_addr = force_reg (Pmode, XEXP (mem, 0));
5914 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
5915 force_reg (Pmode, GEN_INT (-4)));
5917 /* Create a memory reference for it. */
5918 memsi = gen_rtx_MEM (SImode, memsi_addr);
5919 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
5920 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
5922 /* Work out the byte offset of the QImode or HImode value,
5923 counting from the least significant byte. */
5924 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
5925 if (TARGET_BIG_ENDIAN)
5926 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
5928 /* Multiply by eight to convert the shift value from bytes to bits. */
5929 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
5931 /* Make the final shift an SImode value, so that it can be used in
5932 SImode operations. */
5933 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
5935 /* Set MASK to an inclusive mask of the QImode or HImode value. */
5936 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
5937 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
5938 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
5940 /* Compute the equivalent exclusive mask. */
5941 inverted_mask = gen_reg_rtx (SImode);
5942 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
5943 gen_rtx_NOT (SImode, mask)));
5945 /* Shift the old value into place. */
5946 if (oldval != const0_rtx)
5948 oldval = convert_modes (SImode, mode, oldval, true);
5949 oldval = force_reg (SImode, oldval);
5950 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
5953 /* Do the same for the new value. */
5954 if (newval && newval != const0_rtx)
5956 newval = convert_modes (SImode, mode, newval, true);
5957 newval = force_reg (SImode, newval);
5958 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
5961 /* Do the SImode atomic access. */
5962 if (result)
5963 res = gen_reg_rtx (SImode);
5964 if (newval)
5965 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
5966 else if (result)
5967 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
5968 else
5969 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
5971 emit_insn (si_op);
5973 if (result)
5975 /* Shift and convert the result. */
5976 mips_emit_binary (AND, res, res, mask);
5977 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
5978 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
5982 /* Return true if it is possible to use left/right accesses for a
5983 bitfield of WIDTH bits starting BITPOS bits into *OP. When
5984 returning true, update *OP, *LEFT and *RIGHT as follows:
5986 *OP is a BLKmode reference to the whole field.
5988 *LEFT is a QImode reference to the first byte if big endian or
5989 the last byte if little endian. This address can be used in the
5990 left-side instructions (LWL, SWL, LDL, SDL).
5992 *RIGHT is a QImode reference to the opposite end of the field and
5993 can be used in the patterning right-side instruction. */
5995 static bool
5996 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
5997 rtx *left, rtx *right)
5999 rtx first, last;
6001 /* Check that the operand really is a MEM. Not all the extv and
6002 extzv predicates are checked. */
6003 if (!MEM_P (*op))
6004 return false;
6006 /* Check that the size is valid. */
6007 if (width != 32 && (!TARGET_64BIT || width != 64))
6008 return false;
6010 /* We can only access byte-aligned values. Since we are always passed
6011 a reference to the first byte of the field, it is not necessary to
6012 do anything with BITPOS after this check. */
6013 if (bitpos % BITS_PER_UNIT != 0)
6014 return false;
6016 /* Reject aligned bitfields: we want to use a normal load or store
6017 instead of a left/right pair. */
6018 if (MEM_ALIGN (*op) >= width)
6019 return false;
6021 /* Adjust *OP to refer to the whole field. This also has the effect
6022 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6023 *op = adjust_address (*op, BLKmode, 0);
6024 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6026 /* Get references to both ends of the field. We deliberately don't
6027 use the original QImode *OP for FIRST since the new BLKmode one
6028 might have a simpler address. */
6029 first = adjust_address (*op, QImode, 0);
6030 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6032 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6033 correspond to the MSB and RIGHT to the LSB. */
6034 if (TARGET_BIG_ENDIAN)
6035 *left = first, *right = last;
6036 else
6037 *left = last, *right = first;
6039 return true;
6042 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6043 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6044 the operation is the equivalent of:
6046 (set DEST (*_extract SRC WIDTH BITPOS))
6048 Return true on success. */
6050 bool
6051 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6052 HOST_WIDE_INT bitpos)
6054 rtx left, right, temp;
6056 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6057 be a paradoxical word_mode subreg. This is the only case in which
6058 we allow the destination to be larger than the source. */
6059 if (GET_CODE (dest) == SUBREG
6060 && GET_MODE (dest) == DImode
6061 && GET_MODE (SUBREG_REG (dest)) == SImode)
6062 dest = SUBREG_REG (dest);
6064 /* After the above adjustment, the destination must be the same
6065 width as the source. */
6066 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6067 return false;
6069 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6070 return false;
6072 temp = gen_reg_rtx (GET_MODE (dest));
6073 if (GET_MODE (dest) == DImode)
6075 emit_insn (gen_mov_ldl (temp, src, left));
6076 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6078 else
6080 emit_insn (gen_mov_lwl (temp, src, left));
6081 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6083 return true;
6086 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6087 BITPOS and SRC are the operands passed to the expander; the operation
6088 is the equivalent of:
6090 (set (zero_extract DEST WIDTH BITPOS) SRC)
6092 Return true on success. */
6094 bool
6095 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
6096 HOST_WIDE_INT bitpos)
6098 rtx left, right;
6099 enum machine_mode mode;
6101 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
6102 return false;
6104 mode = mode_for_size (width, MODE_INT, 0);
6105 src = gen_lowpart (mode, src);
6106 if (mode == DImode)
6108 emit_insn (gen_mov_sdl (dest, src, left));
6109 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6111 else
6113 emit_insn (gen_mov_swl (dest, src, left));
6114 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6116 return true;
6119 /* Return true if X is a MEM with the same size as MODE. */
6121 bool
6122 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
6124 rtx size;
6126 if (!MEM_P (x))
6127 return false;
6129 size = MEM_SIZE (x);
6130 return size && INTVAL (size) == GET_MODE_SIZE (mode);
6133 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6134 source of an "ext" instruction or the destination of an "ins"
6135 instruction. OP must be a register operand and the following
6136 conditions must hold:
6138 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6139 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6140 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6142 Also reject lengths equal to a word as they are better handled
6143 by the move patterns. */
6145 bool
6146 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
6148 if (!ISA_HAS_EXT_INS
6149 || !register_operand (op, VOIDmode)
6150 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
6151 return false;
6153 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
6154 return false;
6156 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
6157 return false;
6159 return true;
6162 /* Return true if -msplit-addresses is selected and should be honored.
6164 -msplit-addresses is a half-way house between explicit relocations
6165 and the traditional assembler macros. It can split absolute 32-bit
6166 symbolic constants into a high/lo_sum pair but uses macros for other
6167 sorts of access.
6169 Like explicit relocation support for REL targets, it relies
6170 on GNU extensions in the assembler and the linker.
6172 Although this code should work for -O0, it has traditionally
6173 been treated as an optimization. */
6175 static bool
6176 mips_split_addresses_p (void)
6178 return (TARGET_SPLIT_ADDRESSES
6179 && optimize
6180 && !TARGET_MIPS16
6181 && !flag_pic
6182 && !ABI_HAS_64BIT_SYMBOLS);
6185 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
6187 static void
6188 mips_init_relocs (void)
6190 memset (mips_split_p, '\0', sizeof (mips_split_p));
6191 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
6192 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
6194 if (ABI_HAS_64BIT_SYMBOLS)
6196 if (TARGET_EXPLICIT_RELOCS)
6198 mips_split_p[SYMBOL_64_HIGH] = true;
6199 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
6200 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
6202 mips_split_p[SYMBOL_64_MID] = true;
6203 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
6204 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
6206 mips_split_p[SYMBOL_64_LOW] = true;
6207 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
6208 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
6210 mips_split_p[SYMBOL_ABSOLUTE] = true;
6211 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6214 else
6216 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
6218 mips_split_p[SYMBOL_ABSOLUTE] = true;
6219 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
6220 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6222 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
6226 if (TARGET_MIPS16)
6228 /* The high part is provided by a pseudo copy of $gp. */
6229 mips_split_p[SYMBOL_GP_RELATIVE] = true;
6230 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
6233 if (TARGET_EXPLICIT_RELOCS)
6235 /* Small data constants are kept whole until after reload,
6236 then lowered by mips_rewrite_small_data. */
6237 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
6239 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
6240 if (TARGET_NEWABI)
6242 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
6243 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
6245 else
6247 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
6248 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
6251 if (TARGET_XGOT)
6253 /* The HIGH and LO_SUM are matched by special .md patterns. */
6254 mips_split_p[SYMBOL_GOT_DISP] = true;
6256 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
6257 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
6258 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
6260 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
6261 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
6262 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
6264 else
6266 if (TARGET_NEWABI)
6267 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
6268 else
6269 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
6270 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
6274 if (TARGET_NEWABI)
6276 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
6277 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
6278 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
6281 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
6282 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
6284 mips_split_p[SYMBOL_DTPREL] = true;
6285 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
6286 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
6288 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
6290 mips_split_p[SYMBOL_TPREL] = true;
6291 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
6292 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
6294 mips_lo_relocs[SYMBOL_HALF] = "%half(";
6297 /* If OP is an UNSPEC address, return the address to which it refers,
6298 otherwise return OP itself. */
6300 static rtx
6301 mips_strip_unspec_address (rtx op)
6303 rtx base, offset;
6305 split_const (op, &base, &offset);
6306 if (UNSPEC_ADDRESS_P (base))
6307 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
6308 return op;
6311 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6312 in context CONTEXT. RELOCS is the array of relocations to use. */
6314 static void
6315 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
6316 const char **relocs)
6318 enum mips_symbol_type symbol_type;
6319 const char *p;
6321 symbol_type = mips_classify_symbolic_expression (op, context);
6322 gcc_assert (relocs[symbol_type]);
6324 fputs (relocs[symbol_type], file);
6325 output_addr_const (file, mips_strip_unspec_address (op));
6326 for (p = relocs[symbol_type]; *p != 0; p++)
6327 if (*p == '(')
6328 fputc (')', file);
6331 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
6332 The punctuation characters are:
6334 '(' Start a nested ".set noreorder" block.
6335 ')' End a nested ".set noreorder" block.
6336 '[' Start a nested ".set noat" block.
6337 ']' End a nested ".set noat" block.
6338 '<' Start a nested ".set nomacro" block.
6339 '>' End a nested ".set nomacro" block.
6340 '*' Behave like %(%< if generating a delayed-branch sequence.
6341 '#' Print a nop if in a ".set noreorder" block.
6342 '/' Like '#', but do nothing within a delayed-branch sequence.
6343 '?' Print "l" if mips_branch_likely is true
6344 '.' Print the name of the register with a hard-wired zero (zero or $0).
6345 '@' Print the name of the assembler temporary register (at or $1).
6346 '^' Print the name of the pic call-through register (t9 or $25).
6347 '+' Print the name of the gp register (usually gp or $28).
6348 '$' Print the name of the stack pointer register (sp or $29).
6349 '|' Print ".set push; .set mips2" if !ISA_HAS_LL_SC.
6350 '-' Print ".set pop" under the same conditions for '|'.
6352 See also mips_init_print_operand_pucnt. */
6354 static void
6355 mips_print_operand_punctuation (FILE *file, int ch)
6357 switch (ch)
6359 case '(':
6360 if (set_noreorder++ == 0)
6361 fputs (".set\tnoreorder\n\t", file);
6362 break;
6364 case ')':
6365 gcc_assert (set_noreorder > 0);
6366 if (--set_noreorder == 0)
6367 fputs ("\n\t.set\treorder", file);
6368 break;
6370 case '[':
6371 if (set_noat++ == 0)
6372 fputs (".set\tnoat\n\t", file);
6373 break;
6375 case ']':
6376 gcc_assert (set_noat > 0);
6377 if (--set_noat == 0)
6378 fputs ("\n\t.set\tat", file);
6379 break;
6381 case '<':
6382 if (set_nomacro++ == 0)
6383 fputs (".set\tnomacro\n\t", file);
6384 break;
6386 case '>':
6387 gcc_assert (set_nomacro > 0);
6388 if (--set_nomacro == 0)
6389 fputs ("\n\t.set\tmacro", file);
6390 break;
6392 case '*':
6393 if (final_sequence != 0)
6395 mips_print_operand_punctuation (file, '(');
6396 mips_print_operand_punctuation (file, '<');
6398 break;
6400 case '#':
6401 if (set_noreorder != 0)
6402 fputs ("\n\tnop", file);
6403 break;
6405 case '/':
6406 /* Print an extra newline so that the delayed insn is separated
6407 from the following ones. This looks neater and is consistent
6408 with non-nop delayed sequences. */
6409 if (set_noreorder != 0 && final_sequence == 0)
6410 fputs ("\n\tnop\n", file);
6411 break;
6413 case '?':
6414 if (mips_branch_likely)
6415 putc ('l', file);
6416 break;
6418 case '.':
6419 fputs (reg_names[GP_REG_FIRST + 0], file);
6420 break;
6422 case '@':
6423 fputs (reg_names[GP_REG_FIRST + 1], file);
6424 break;
6426 case '^':
6427 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
6428 break;
6430 case '+':
6431 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
6432 break;
6434 case '$':
6435 fputs (reg_names[STACK_POINTER_REGNUM], file);
6436 break;
6438 case '|':
6439 if (!ISA_HAS_LL_SC)
6440 fputs (".set\tpush\n\t.set\tmips2\n\t", file);
6441 break;
6443 case '-':
6444 if (!ISA_HAS_LL_SC)
6445 fputs ("\n\t.set\tpop", file);
6446 break;
6448 default:
6449 gcc_unreachable ();
6450 break;
6454 /* Initialize mips_print_operand_punct. */
6456 static void
6457 mips_init_print_operand_punct (void)
6459 const char *p;
6461 for (p = "()[]<>*#/?.@^+$|-"; *p; p++)
6462 mips_print_operand_punct[(unsigned char) *p] = true;
6465 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
6466 associated with condition CODE. Print the condition part of the
6467 opcode to FILE. */
6469 static void
6470 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
6472 switch (code)
6474 case EQ:
6475 case NE:
6476 case GT:
6477 case GE:
6478 case LT:
6479 case LE:
6480 case GTU:
6481 case GEU:
6482 case LTU:
6483 case LEU:
6484 /* Conveniently, the MIPS names for these conditions are the same
6485 as their RTL equivalents. */
6486 fputs (GET_RTX_NAME (code), file);
6487 break;
6489 default:
6490 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
6491 break;
6495 /* Likewise floating-point branches. */
6497 static void
6498 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
6500 switch (code)
6502 case EQ:
6503 fputs ("c1f", file);
6504 break;
6506 case NE:
6507 fputs ("c1t", file);
6508 break;
6510 default:
6511 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
6512 break;
6516 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
6518 'X' Print CONST_INT OP in hexadecimal format.
6519 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
6520 'd' Print CONST_INT OP in decimal.
6521 'h' Print the high-part relocation associated with OP, after stripping
6522 any outermost HIGH.
6523 'R' Print the low-part relocation associated with OP.
6524 'C' Print the integer branch condition for comparison OP.
6525 'N' Print the inverse of the integer branch condition for comparison OP.
6526 'F' Print the FPU branch condition for comparison OP.
6527 'W' Print the inverse of the FPU branch condition for comparison OP.
6528 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
6529 'z' for (eq:?I ...), 'n' for (ne:?I ...).
6530 't' Like 'T', but with the EQ/NE cases reversed
6531 'Y' Print mips_fp_conditions[INTVAL (OP)]
6532 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
6533 'q' Print a DSP accumulator register.
6534 'D' Print the second part of a double-word register or memory operand.
6535 'L' Print the low-order register in a double-word register operand.
6536 'M' Print high-order register in a double-word register operand.
6537 'z' Print $0 if OP is zero, otherwise print OP normally. */
6539 void
6540 mips_print_operand (FILE *file, rtx op, int letter)
6542 enum rtx_code code;
6544 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
6546 mips_print_operand_punctuation (file, letter);
6547 return;
6550 gcc_assert (op);
6551 code = GET_CODE (op);
6553 switch (letter)
6555 case 'X':
6556 if (GET_CODE (op) == CONST_INT)
6557 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
6558 else
6559 output_operand_lossage ("invalid use of '%%%c'", letter);
6560 break;
6562 case 'x':
6563 if (GET_CODE (op) == CONST_INT)
6564 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
6565 else
6566 output_operand_lossage ("invalid use of '%%%c'", letter);
6567 break;
6569 case 'd':
6570 if (GET_CODE (op) == CONST_INT)
6571 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
6572 else
6573 output_operand_lossage ("invalid use of '%%%c'", letter);
6574 break;
6576 case 'h':
6577 if (code == HIGH)
6578 op = XEXP (op, 0);
6579 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
6580 break;
6582 case 'R':
6583 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
6584 break;
6586 case 'C':
6587 mips_print_int_branch_condition (file, code, letter);
6588 break;
6590 case 'N':
6591 mips_print_int_branch_condition (file, reverse_condition (code), letter);
6592 break;
6594 case 'F':
6595 mips_print_float_branch_condition (file, code, letter);
6596 break;
6598 case 'W':
6599 mips_print_float_branch_condition (file, reverse_condition (code),
6600 letter);
6601 break;
6603 case 'T':
6604 case 't':
6606 int truth = (code == NE) == (letter == 'T');
6607 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
6609 break;
6611 case 'Y':
6612 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
6613 fputs (mips_fp_conditions[UINTVAL (op)], file);
6614 else
6615 output_operand_lossage ("'%%%c' is not a valid operand prefix",
6616 letter);
6617 break;
6619 case 'Z':
6620 if (ISA_HAS_8CC)
6622 mips_print_operand (file, op, 0);
6623 fputc (',', file);
6625 break;
6627 case 'q':
6628 if (code == REG && MD_REG_P (REGNO (op)))
6629 fprintf (file, "$ac0");
6630 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
6631 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
6632 else
6633 output_operand_lossage ("invalid use of '%%%c'", letter);
6634 break;
6636 default:
6637 switch (code)
6639 case REG:
6641 unsigned int regno = REGNO (op);
6642 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
6643 || (letter == 'L' && TARGET_BIG_ENDIAN)
6644 || letter == 'D')
6645 regno++;
6646 fprintf (file, "%s", reg_names[regno]);
6648 break;
6650 case MEM:
6651 if (letter == 'D')
6652 output_address (plus_constant (XEXP (op, 0), 4));
6653 else
6654 output_address (XEXP (op, 0));
6655 break;
6657 default:
6658 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
6659 fputs (reg_names[GP_REG_FIRST], file);
6660 else if (CONST_GP_P (op))
6661 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
6662 else
6663 output_addr_const (file, mips_strip_unspec_address (op));
6664 break;
6669 /* Output address operand X to FILE. */
6671 void
6672 mips_print_operand_address (FILE *file, rtx x)
6674 struct mips_address_info addr;
6676 if (mips_classify_address (&addr, x, word_mode, true))
6677 switch (addr.type)
6679 case ADDRESS_REG:
6680 mips_print_operand (file, addr.offset, 0);
6681 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6682 return;
6684 case ADDRESS_LO_SUM:
6685 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
6686 mips_lo_relocs);
6687 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6688 return;
6690 case ADDRESS_CONST_INT:
6691 output_addr_const (file, x);
6692 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
6693 return;
6695 case ADDRESS_SYMBOLIC:
6696 output_addr_const (file, mips_strip_unspec_address (x));
6697 return;
6699 gcc_unreachable ();
6702 /* Implement TARGET_ENCODE_SECTION_INFO. */
6704 static void
6705 mips_encode_section_info (tree decl, rtx rtl, int first)
6707 default_encode_section_info (decl, rtl, first);
6709 if (TREE_CODE (decl) == FUNCTION_DECL)
6711 rtx symbol = XEXP (rtl, 0);
6712 tree type = TREE_TYPE (decl);
6714 /* Encode whether the symbol is short or long. */
6715 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
6716 || mips_far_type_p (type))
6717 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
6721 /* Implement TARGET_SELECT_RTX_SECTION. */
6723 static section *
6724 mips_select_rtx_section (enum machine_mode mode, rtx x,
6725 unsigned HOST_WIDE_INT align)
6727 /* ??? Consider using mergeable small data sections. */
6728 if (mips_rtx_constant_in_small_data_p (mode))
6729 return get_named_section (NULL, ".sdata", 0);
6731 return default_elf_select_rtx_section (mode, x, align);
6734 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
6736 The complication here is that, with the combination TARGET_ABICALLS
6737 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
6738 therefore not be included in the read-only part of a DSO. Handle such
6739 cases by selecting a normal data section instead of a read-only one.
6740 The logic apes that in default_function_rodata_section. */
6742 static section *
6743 mips_function_rodata_section (tree decl)
6745 if (!TARGET_ABICALLS || TARGET_GPWORD)
6746 return default_function_rodata_section (decl);
6748 if (decl && DECL_SECTION_NAME (decl))
6750 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6751 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
6753 char *rname = ASTRDUP (name);
6754 rname[14] = 'd';
6755 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
6757 else if (flag_function_sections
6758 && flag_data_sections
6759 && strncmp (name, ".text.", 6) == 0)
6761 char *rname = ASTRDUP (name);
6762 memcpy (rname + 1, "data", 4);
6763 return get_section (rname, SECTION_WRITE, decl);
6766 return data_section;
6769 /* Implement TARGET_IN_SMALL_DATA_P. */
6771 static bool
6772 mips_in_small_data_p (const_tree decl)
6774 unsigned HOST_WIDE_INT size;
6776 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
6777 return false;
6779 /* We don't yet generate small-data references for -mabicalls
6780 or VxWorks RTP code. See the related -G handling in
6781 mips_override_options. */
6782 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
6783 return false;
6785 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
6787 const char *name;
6789 /* Reject anything that isn't in a known small-data section. */
6790 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6791 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
6792 return false;
6794 /* If a symbol is defined externally, the assembler will use the
6795 usual -G rules when deciding how to implement macros. */
6796 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
6797 return true;
6799 else if (TARGET_EMBEDDED_DATA)
6801 /* Don't put constants into the small data section: we want them
6802 to be in ROM rather than RAM. */
6803 if (TREE_CODE (decl) != VAR_DECL)
6804 return false;
6806 if (TREE_READONLY (decl)
6807 && !TREE_SIDE_EFFECTS (decl)
6808 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
6809 return false;
6812 /* Enforce -mlocal-sdata. */
6813 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
6814 return false;
6816 /* Enforce -mextern-sdata. */
6817 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
6819 if (DECL_EXTERNAL (decl))
6820 return false;
6821 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
6822 return false;
6825 /* We have traditionally not treated zero-sized objects as small data,
6826 so this is now effectively part of the ABI. */
6827 size = int_size_in_bytes (TREE_TYPE (decl));
6828 return size > 0 && size <= mips_small_data_threshold;
6831 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
6832 anchors for small data: the GP register acts as an anchor in that
6833 case. We also don't want to use them for PC-relative accesses,
6834 where the PC acts as an anchor. */
6836 static bool
6837 mips_use_anchors_for_symbol_p (const_rtx symbol)
6839 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
6841 case SYMBOL_PC_RELATIVE:
6842 case SYMBOL_GP_RELATIVE:
6843 return false;
6845 default:
6846 return default_use_anchors_for_symbol_p (symbol);
6850 /* The MIPS debug format wants all automatic variables and arguments
6851 to be in terms of the virtual frame pointer (stack pointer before
6852 any adjustment in the function), while the MIPS 3.0 linker wants
6853 the frame pointer to be the stack pointer after the initial
6854 adjustment. So, we do the adjustment here. The arg pointer (which
6855 is eliminated) points to the virtual frame pointer, while the frame
6856 pointer (which may be eliminated) points to the stack pointer after
6857 the initial adjustments. */
6859 HOST_WIDE_INT
6860 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
6862 rtx offset2 = const0_rtx;
6863 rtx reg = eliminate_constant_term (addr, &offset2);
6865 if (offset == 0)
6866 offset = INTVAL (offset2);
6868 if (reg == stack_pointer_rtx
6869 || reg == frame_pointer_rtx
6870 || reg == hard_frame_pointer_rtx)
6872 offset -= cfun->machine->frame.total_size;
6873 if (reg == hard_frame_pointer_rtx)
6874 offset += cfun->machine->frame.hard_frame_pointer_offset;
6877 /* sdbout_parms does not want this to crash for unrecognized cases. */
6878 #if 0
6879 else if (reg != arg_pointer_rtx)
6880 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
6881 addr);
6882 #endif
6884 return offset;
6887 /* Implement ASM_OUTPUT_EXTERNAL. */
6889 void
6890 mips_output_external (FILE *file, tree decl, const char *name)
6892 default_elf_asm_output_external (file, decl, name);
6894 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
6895 set in order to avoid putting out names that are never really
6896 used. */
6897 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
6899 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
6901 /* When using assembler macros, emit .extern directives for
6902 all small-data externs so that the assembler knows how
6903 big they are.
6905 In most cases it would be safe (though pointless) to emit
6906 .externs for other symbols too. One exception is when an
6907 object is within the -G limit but declared by the user to
6908 be in a section other than .sbss or .sdata. */
6909 fputs ("\t.extern\t", file);
6910 assemble_name (file, name);
6911 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
6912 int_size_in_bytes (TREE_TYPE (decl)));
6914 else if (TARGET_IRIX
6915 && mips_abi == ABI_32
6916 && TREE_CODE (decl) == FUNCTION_DECL)
6918 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
6919 `.global name .text' directive for every used but
6920 undefined function. If we don't, the linker may perform
6921 an optimization (skipping over the insns that set $gp)
6922 when it is unsafe. */
6923 fputs ("\t.globl ", file);
6924 assemble_name (file, name);
6925 fputs (" .text\n", file);
6930 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
6932 void
6933 mips_output_filename (FILE *stream, const char *name)
6935 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6936 directives. */
6937 if (write_symbols == DWARF2_DEBUG)
6938 return;
6939 else if (mips_output_filename_first_time)
6941 mips_output_filename_first_time = 0;
6942 num_source_filenames += 1;
6943 current_function_file = name;
6944 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6945 output_quoted_string (stream, name);
6946 putc ('\n', stream);
6948 /* If we are emitting stabs, let dbxout.c handle this (except for
6949 the mips_output_filename_first_time case). */
6950 else if (write_symbols == DBX_DEBUG)
6951 return;
6952 else if (name != current_function_file
6953 && strcmp (name, current_function_file) != 0)
6955 num_source_filenames += 1;
6956 current_function_file = name;
6957 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6958 output_quoted_string (stream, name);
6959 putc ('\n', stream);
6963 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
6965 static void ATTRIBUTE_UNUSED
6966 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
6968 switch (size)
6970 case 4:
6971 fputs ("\t.dtprelword\t", file);
6972 break;
6974 case 8:
6975 fputs ("\t.dtpreldword\t", file);
6976 break;
6978 default:
6979 gcc_unreachable ();
6981 output_addr_const (file, x);
6982 fputs ("+0x8000", file);
6985 /* Implement TARGET_DWARF_REGISTER_SPAN. */
6987 static rtx
6988 mips_dwarf_register_span (rtx reg)
6990 rtx high, low;
6991 enum machine_mode mode;
6993 /* By default, GCC maps increasing register numbers to increasing
6994 memory locations, but paired FPRs are always little-endian,
6995 regardless of the prevailing endianness. */
6996 mode = GET_MODE (reg);
6997 if (FP_REG_P (REGNO (reg))
6998 && TARGET_BIG_ENDIAN
6999 && MAX_FPRS_PER_FMT > 1
7000 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7002 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7003 high = mips_subword (reg, true);
7004 low = mips_subword (reg, false);
7005 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7008 return NULL_RTX;
7011 /* Implement ASM_OUTPUT_ASCII. */
7013 void
7014 mips_output_ascii (FILE *stream, const char *string, size_t len)
7016 size_t i;
7017 int cur_pos;
7019 cur_pos = 17;
7020 fprintf (stream, "\t.ascii\t\"");
7021 for (i = 0; i < len; i++)
7023 int c;
7025 c = (unsigned char) string[i];
7026 if (ISPRINT (c))
7028 if (c == '\\' || c == '\"')
7030 putc ('\\', stream);
7031 cur_pos++;
7033 putc (c, stream);
7034 cur_pos++;
7036 else
7038 fprintf (stream, "\\%03o", c);
7039 cur_pos += 4;
7042 if (cur_pos > 72 && i+1 < len)
7044 cur_pos = 17;
7045 fprintf (stream, "\"\n\t.ascii\t\"");
7048 fprintf (stream, "\"\n");
7051 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7052 macros, mark the symbol as written so that mips_asm_output_external
7053 won't emit an .extern for it. STREAM is the output file, NAME is the
7054 name of the symbol, INIT_STRING is the string that should be written
7055 before the symbol and FINAL_STRING is the string that should be
7056 written after it. FINAL_STRING is a printf format that consumes the
7057 remaining arguments. */
7059 void
7060 mips_declare_object (FILE *stream, const char *name, const char *init_string,
7061 const char *final_string, ...)
7063 va_list ap;
7065 fputs (init_string, stream);
7066 assemble_name (stream, name);
7067 va_start (ap, final_string);
7068 vfprintf (stream, final_string, ap);
7069 va_end (ap);
7071 if (!TARGET_EXPLICIT_RELOCS)
7073 tree name_tree = get_identifier (name);
7074 TREE_ASM_WRITTEN (name_tree) = 1;
7078 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7079 NAME is the name of the object and ALIGN is the required alignment
7080 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7081 alignment argument. */
7083 void
7084 mips_declare_common_object (FILE *stream, const char *name,
7085 const char *init_string,
7086 unsigned HOST_WIDE_INT size,
7087 unsigned int align, bool takes_alignment_p)
7089 if (!takes_alignment_p)
7091 size += (align / BITS_PER_UNIT) - 1;
7092 size -= size % (align / BITS_PER_UNIT);
7093 mips_declare_object (stream, name, init_string,
7094 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
7096 else
7097 mips_declare_object (stream, name, init_string,
7098 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
7099 size, align / BITS_PER_UNIT);
7102 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7103 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
7105 void
7106 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
7107 unsigned HOST_WIDE_INT size,
7108 unsigned int align)
7110 /* If the target wants uninitialized const declarations in
7111 .rdata then don't put them in .comm. */
7112 if (TARGET_EMBEDDED_DATA
7113 && TARGET_UNINIT_CONST_IN_RODATA
7114 && TREE_CODE (decl) == VAR_DECL
7115 && TREE_READONLY (decl)
7116 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
7118 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
7119 targetm.asm_out.globalize_label (stream, name);
7121 switch_to_section (readonly_data_section);
7122 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
7123 mips_declare_object (stream, name, "",
7124 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
7125 size);
7127 else
7128 mips_declare_common_object (stream, name, "\n\t.comm\t",
7129 size, align, true);
7132 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7133 extern int size_directive_output;
7135 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
7136 definitions except that it uses mips_declare_object to emit the label. */
7138 void
7139 mips_declare_object_name (FILE *stream, const char *name,
7140 tree decl ATTRIBUTE_UNUSED)
7142 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7143 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7144 #endif
7146 size_directive_output = 0;
7147 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
7149 HOST_WIDE_INT size;
7151 size_directive_output = 1;
7152 size = int_size_in_bytes (TREE_TYPE (decl));
7153 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7156 mips_declare_object (stream, name, "", ":\n");
7159 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
7161 void
7162 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
7164 const char *name;
7166 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
7167 if (!flag_inhibit_size_directive
7168 && DECL_SIZE (decl) != 0
7169 && !at_end
7170 && top_level
7171 && DECL_INITIAL (decl) == error_mark_node
7172 && !size_directive_output)
7174 HOST_WIDE_INT size;
7176 size_directive_output = 1;
7177 size = int_size_in_bytes (TREE_TYPE (decl));
7178 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7181 #endif
7183 /* Return the FOO in the name of the ".mdebug.FOO" section associated
7184 with the current ABI. */
7186 static const char *
7187 mips_mdebug_abi_name (void)
7189 switch (mips_abi)
7191 case ABI_32:
7192 return "abi32";
7193 case ABI_O64:
7194 return "abiO64";
7195 case ABI_N32:
7196 return "abiN32";
7197 case ABI_64:
7198 return "abiN64";
7199 case ABI_EABI:
7200 return TARGET_64BIT ? "eabi64" : "eabi32";
7201 default:
7202 gcc_unreachable ();
7206 /* Implement TARGET_ASM_FILE_START. */
7208 static void
7209 mips_file_start (void)
7211 default_file_start ();
7213 /* Generate a special section to describe the ABI switches used to
7214 produce the resultant binary. This is unnecessary on IRIX and
7215 causes unwanted warnings from the native linker. */
7216 if (!TARGET_IRIX)
7218 /* Record the ABI itself. Modern versions of binutils encode
7219 this information in the ELF header flags, but GDB needs the
7220 information in order to correctly debug binaries produced by
7221 older binutils. See the function mips_gdbarch_init in
7222 gdb/mips-tdep.c. */
7223 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
7224 mips_mdebug_abi_name ());
7226 /* There is no ELF header flag to distinguish long32 forms of the
7227 EABI from long64 forms. Emit a special section to help tools
7228 such as GDB. Do the same for o64, which is sometimes used with
7229 -mlong64. */
7230 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
7231 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
7232 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
7234 #ifdef HAVE_AS_GNU_ATTRIBUTE
7235 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
7236 (TARGET_HARD_FLOAT_ABI
7237 ? (TARGET_DOUBLE_FLOAT
7238 ? ((!TARGET_64BIT && TARGET_FLOAT64) ? 4 : 1) : 2) : 3));
7239 #endif
7242 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
7243 if (TARGET_ABICALLS)
7244 fprintf (asm_out_file, "\t.abicalls\n");
7246 if (flag_verbose_asm)
7247 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
7248 ASM_COMMENT_START,
7249 mips_small_data_threshold, mips_arch_info->name, mips_isa);
7252 /* Make the last instruction frame-related and note that it performs
7253 the operation described by FRAME_PATTERN. */
7255 static void
7256 mips_set_frame_expr (rtx frame_pattern)
7258 rtx insn;
7260 insn = get_last_insn ();
7261 RTX_FRAME_RELATED_P (insn) = 1;
7262 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7263 frame_pattern,
7264 REG_NOTES (insn));
7267 /* Return a frame-related rtx that stores REG at MEM.
7268 REG must be a single register. */
7270 static rtx
7271 mips_frame_set (rtx mem, rtx reg)
7273 rtx set;
7275 /* If we're saving the return address register and the DWARF return
7276 address column differs from the hard register number, adjust the
7277 note reg to refer to the former. */
7278 if (REGNO (reg) == GP_REG_FIRST + 31
7279 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
7280 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
7282 set = gen_rtx_SET (VOIDmode, mem, reg);
7283 RTX_FRAME_RELATED_P (set) = 1;
7285 return set;
7288 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
7289 mips16e_s2_s8_regs[X], it must also save the registers in indexes
7290 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
7291 static const unsigned char mips16e_s2_s8_regs[] = {
7292 30, 23, 22, 21, 20, 19, 18
7294 static const unsigned char mips16e_a0_a3_regs[] = {
7295 4, 5, 6, 7
7298 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
7299 ordered from the uppermost in memory to the lowest in memory. */
7300 static const unsigned char mips16e_save_restore_regs[] = {
7301 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
7304 /* Return the index of the lowest X in the range [0, SIZE) for which
7305 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
7307 static unsigned int
7308 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
7309 unsigned int size)
7311 unsigned int i;
7313 for (i = 0; i < size; i++)
7314 if (BITSET_P (mask, regs[i]))
7315 break;
7317 return i;
7320 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
7321 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
7322 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
7323 is true for all indexes (X, SIZE). */
7325 static void
7326 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
7327 unsigned int size, unsigned int *num_regs_ptr)
7329 unsigned int i;
7331 i = mips16e_find_first_register (*mask_ptr, regs, size);
7332 for (i++; i < size; i++)
7333 if (!BITSET_P (*mask_ptr, regs[i]))
7335 *num_regs_ptr += 1;
7336 *mask_ptr |= 1 << regs[i];
7340 /* Return a simplified form of X using the register values in REG_VALUES.
7341 REG_VALUES[R] is the last value assigned to hard register R, or null
7342 if R has not been modified.
7344 This function is rather limited, but is good enough for our purposes. */
7346 static rtx
7347 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
7349 x = avoid_constant_pool_reference (x);
7351 if (UNARY_P (x))
7353 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7354 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
7355 x0, GET_MODE (XEXP (x, 0)));
7358 if (ARITHMETIC_P (x))
7360 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7361 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
7362 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
7365 if (REG_P (x)
7366 && reg_values[REGNO (x)]
7367 && !rtx_unstable_p (reg_values[REGNO (x)]))
7368 return reg_values[REGNO (x)];
7370 return x;
7373 /* Return true if (set DEST SRC) stores an argument register into its
7374 caller-allocated save slot, storing the number of that argument
7375 register in *REGNO_PTR if so. REG_VALUES is as for
7376 mips16e_collect_propagate_value. */
7378 static bool
7379 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
7380 unsigned int *regno_ptr)
7382 unsigned int argno, regno;
7383 HOST_WIDE_INT offset, required_offset;
7384 rtx addr, base;
7386 /* Check that this is a word-mode store. */
7387 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
7388 return false;
7390 /* Check that the register being saved is an unmodified argument
7391 register. */
7392 regno = REGNO (src);
7393 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
7394 return false;
7395 argno = regno - GP_ARG_FIRST;
7397 /* Check whether the address is an appropriate stack-pointer or
7398 frame-pointer access. */
7399 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
7400 mips_split_plus (addr, &base, &offset);
7401 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
7402 if (base == hard_frame_pointer_rtx)
7403 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
7404 else if (base != stack_pointer_rtx)
7405 return false;
7406 if (offset != required_offset)
7407 return false;
7409 *regno_ptr = regno;
7410 return true;
7413 /* A subroutine of mips_expand_prologue, called only when generating
7414 MIPS16e SAVE instructions. Search the start of the function for any
7415 instructions that save argument registers into their caller-allocated
7416 save slots. Delete such instructions and return a value N such that
7417 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
7418 instructions redundant. */
7420 static unsigned int
7421 mips16e_collect_argument_saves (void)
7423 rtx reg_values[FIRST_PSEUDO_REGISTER];
7424 rtx insn, next, set, dest, src;
7425 unsigned int nargs, regno;
7427 push_topmost_sequence ();
7428 nargs = 0;
7429 memset (reg_values, 0, sizeof (reg_values));
7430 for (insn = get_insns (); insn; insn = next)
7432 next = NEXT_INSN (insn);
7433 if (NOTE_P (insn))
7434 continue;
7436 if (!INSN_P (insn))
7437 break;
7439 set = PATTERN (insn);
7440 if (GET_CODE (set) != SET)
7441 break;
7443 dest = SET_DEST (set);
7444 src = SET_SRC (set);
7445 if (mips16e_collect_argument_save_p (dest, src, reg_values, &regno))
7447 if (!BITSET_P (cfun->machine->frame.mask, regno))
7449 delete_insn (insn);
7450 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
7453 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
7454 reg_values[REGNO (dest)]
7455 = mips16e_collect_propagate_value (src, reg_values);
7456 else
7457 break;
7459 pop_topmost_sequence ();
7461 return nargs;
7464 /* Return a move between register REGNO and memory location SP + OFFSET.
7465 Make the move a load if RESTORE_P, otherwise make it a frame-related
7466 store. */
7468 static rtx
7469 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
7470 unsigned int regno)
7472 rtx reg, mem;
7474 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
7475 reg = gen_rtx_REG (SImode, regno);
7476 return (restore_p
7477 ? gen_rtx_SET (VOIDmode, reg, mem)
7478 : mips_frame_set (mem, reg));
7481 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
7482 The instruction must:
7484 - Allocate or deallocate SIZE bytes in total; SIZE is known
7485 to be nonzero.
7487 - Save or restore as many registers in *MASK_PTR as possible.
7488 The instruction saves the first registers at the top of the
7489 allocated area, with the other registers below it.
7491 - Save NARGS argument registers above the allocated area.
7493 (NARGS is always zero if RESTORE_P.)
7495 The SAVE and RESTORE instructions cannot save and restore all general
7496 registers, so there may be some registers left over for the caller to
7497 handle. Destructively modify *MASK_PTR so that it contains the registers
7498 that still need to be saved or restored. The caller can save these
7499 registers in the memory immediately below *OFFSET_PTR, which is a
7500 byte offset from the bottom of the allocated stack area. */
7502 static rtx
7503 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
7504 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
7505 HOST_WIDE_INT size)
7507 rtx pattern, set;
7508 HOST_WIDE_INT offset, top_offset;
7509 unsigned int i, regno;
7510 int n;
7512 gcc_assert (cfun->machine->frame.num_fp == 0);
7514 /* Calculate the number of elements in the PARALLEL. We need one element
7515 for the stack adjustment, one for each argument register save, and one
7516 for each additional register move. */
7517 n = 1 + nargs;
7518 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7519 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
7520 n++;
7522 /* Create the final PARALLEL. */
7523 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
7524 n = 0;
7526 /* Add the stack pointer adjustment. */
7527 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7528 plus_constant (stack_pointer_rtx,
7529 restore_p ? size : -size));
7530 RTX_FRAME_RELATED_P (set) = 1;
7531 XVECEXP (pattern, 0, n++) = set;
7533 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7534 top_offset = restore_p ? size : 0;
7536 /* Save the arguments. */
7537 for (i = 0; i < nargs; i++)
7539 offset = top_offset + i * UNITS_PER_WORD;
7540 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
7541 XVECEXP (pattern, 0, n++) = set;
7544 /* Then fill in the other register moves. */
7545 offset = top_offset;
7546 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7548 regno = mips16e_save_restore_regs[i];
7549 if (BITSET_P (*mask_ptr, regno))
7551 offset -= UNITS_PER_WORD;
7552 set = mips16e_save_restore_reg (restore_p, offset, regno);
7553 XVECEXP (pattern, 0, n++) = set;
7554 *mask_ptr &= ~(1 << regno);
7558 /* Tell the caller what offset it should use for the remaining registers. */
7559 *offset_ptr = size + (offset - top_offset);
7561 gcc_assert (n == XVECLEN (pattern, 0));
7563 return pattern;
7566 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
7567 pointer. Return true if PATTERN matches the kind of instruction
7568 generated by mips16e_build_save_restore. If INFO is nonnull,
7569 initialize it when returning true. */
7571 bool
7572 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
7573 struct mips16e_save_restore_info *info)
7575 unsigned int i, nargs, mask, extra;
7576 HOST_WIDE_INT top_offset, save_offset, offset;
7577 rtx set, reg, mem, base;
7578 int n;
7580 if (!GENERATE_MIPS16E_SAVE_RESTORE)
7581 return false;
7583 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7584 top_offset = adjust > 0 ? adjust : 0;
7586 /* Interpret all other members of the PARALLEL. */
7587 save_offset = top_offset - UNITS_PER_WORD;
7588 mask = 0;
7589 nargs = 0;
7590 i = 0;
7591 for (n = 1; n < XVECLEN (pattern, 0); n++)
7593 /* Check that we have a SET. */
7594 set = XVECEXP (pattern, 0, n);
7595 if (GET_CODE (set) != SET)
7596 return false;
7598 /* Check that the SET is a load (if restoring) or a store
7599 (if saving). */
7600 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
7601 if (!MEM_P (mem))
7602 return false;
7604 /* Check that the address is the sum of the stack pointer and a
7605 possibly-zero constant offset. */
7606 mips_split_plus (XEXP (mem, 0), &base, &offset);
7607 if (base != stack_pointer_rtx)
7608 return false;
7610 /* Check that SET's other operand is a register. */
7611 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
7612 if (!REG_P (reg))
7613 return false;
7615 /* Check for argument saves. */
7616 if (offset == top_offset + nargs * UNITS_PER_WORD
7617 && REGNO (reg) == GP_ARG_FIRST + nargs)
7618 nargs++;
7619 else if (offset == save_offset)
7621 while (mips16e_save_restore_regs[i++] != REGNO (reg))
7622 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
7623 return false;
7625 mask |= 1 << REGNO (reg);
7626 save_offset -= UNITS_PER_WORD;
7628 else
7629 return false;
7632 /* Check that the restrictions on register ranges are met. */
7633 extra = 0;
7634 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
7635 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
7636 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
7637 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
7638 if (extra != 0)
7639 return false;
7641 /* Make sure that the topmost argument register is not saved twice.
7642 The checks above ensure that the same is then true for the other
7643 argument registers. */
7644 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
7645 return false;
7647 /* Pass back information, if requested. */
7648 if (info)
7650 info->nargs = nargs;
7651 info->mask = mask;
7652 info->size = (adjust > 0 ? adjust : -adjust);
7655 return true;
7658 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
7659 for the register range [MIN_REG, MAX_REG]. Return a pointer to
7660 the null terminator. */
7662 static char *
7663 mips16e_add_register_range (char *s, unsigned int min_reg,
7664 unsigned int max_reg)
7666 if (min_reg != max_reg)
7667 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
7668 else
7669 s += sprintf (s, ",%s", reg_names[min_reg]);
7670 return s;
7673 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
7674 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
7676 const char *
7677 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
7679 static char buffer[300];
7681 struct mips16e_save_restore_info info;
7682 unsigned int i, end;
7683 char *s;
7685 /* Parse the pattern. */
7686 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
7687 gcc_unreachable ();
7689 /* Add the mnemonic. */
7690 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
7691 s += strlen (s);
7693 /* Save the arguments. */
7694 if (info.nargs > 1)
7695 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
7696 reg_names[GP_ARG_FIRST + info.nargs - 1]);
7697 else if (info.nargs == 1)
7698 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
7700 /* Emit the amount of stack space to allocate or deallocate. */
7701 s += sprintf (s, "%d", (int) info.size);
7703 /* Save or restore $16. */
7704 if (BITSET_P (info.mask, 16))
7705 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
7707 /* Save or restore $17. */
7708 if (BITSET_P (info.mask, 17))
7709 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
7711 /* Save or restore registers in the range $s2...$s8, which
7712 mips16e_s2_s8_regs lists in decreasing order. Note that this
7713 is a software register range; the hardware registers are not
7714 numbered consecutively. */
7715 end = ARRAY_SIZE (mips16e_s2_s8_regs);
7716 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
7717 if (i < end)
7718 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
7719 mips16e_s2_s8_regs[i]);
7721 /* Save or restore registers in the range $a0...$a3. */
7722 end = ARRAY_SIZE (mips16e_a0_a3_regs);
7723 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
7724 if (i < end)
7725 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
7726 mips16e_a0_a3_regs[end - 1]);
7728 /* Save or restore $31. */
7729 if (BITSET_P (info.mask, 31))
7730 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 31]);
7732 return buffer;
7735 /* Return true if the current function has an insn that implicitly
7736 refers to $gp. */
7738 static bool
7739 mips_function_has_gp_insn (void)
7741 /* Don't bother rechecking if we found one last time. */
7742 if (!cfun->machine->has_gp_insn_p)
7744 rtx insn;
7746 push_topmost_sequence ();
7747 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7748 if (USEFUL_INSN_P (insn)
7749 && (get_attr_got (insn) != GOT_UNSET
7750 || mips_small_data_pattern_p (PATTERN (insn))))
7752 cfun->machine->has_gp_insn_p = true;
7753 break;
7755 pop_topmost_sequence ();
7757 return cfun->machine->has_gp_insn_p;
7760 /* Return the register that should be used as the global pointer
7761 within this function. Return 0 if the function doesn't need
7762 a global pointer. */
7764 static unsigned int
7765 mips_global_pointer (void)
7767 unsigned int regno;
7769 /* $gp is always available unless we're using a GOT. */
7770 if (!TARGET_USE_GOT)
7771 return GLOBAL_POINTER_REGNUM;
7773 /* We must always provide $gp when it is used implicitly. */
7774 if (!TARGET_EXPLICIT_RELOCS)
7775 return GLOBAL_POINTER_REGNUM;
7777 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
7778 a valid gp. */
7779 if (crtl->profile)
7780 return GLOBAL_POINTER_REGNUM;
7782 /* If the function has a nonlocal goto, $gp must hold the correct
7783 global pointer for the target function. */
7784 if (crtl->has_nonlocal_goto)
7785 return GLOBAL_POINTER_REGNUM;
7787 /* If the gp is never referenced, there's no need to initialize it.
7788 Note that reload can sometimes introduce constant pool references
7789 into a function that otherwise didn't need them. For example,
7790 suppose we have an instruction like:
7792 (set (reg:DF R1) (float:DF (reg:SI R2)))
7794 If R2 turns out to be constant such as 1, the instruction may have a
7795 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
7796 using this constant if R2 doesn't get allocated to a register.
7798 In cases like these, reload will have added the constant to the pool
7799 but no instruction will yet refer to it. */
7800 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
7801 && !crtl->uses_const_pool
7802 && !mips_function_has_gp_insn ())
7803 return 0;
7805 /* We need a global pointer, but perhaps we can use a call-clobbered
7806 register instead of $gp. */
7807 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
7808 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
7809 if (!df_regs_ever_live_p (regno)
7810 && call_really_used_regs[regno]
7811 && !fixed_regs[regno]
7812 && regno != PIC_FUNCTION_ADDR_REGNUM)
7813 return regno;
7815 return GLOBAL_POINTER_REGNUM;
7818 /* Return true if the current function returns its value in a floating-point
7819 register in MIPS16 mode. */
7821 static bool
7822 mips16_cfun_returns_in_fpr_p (void)
7824 tree return_type = DECL_RESULT (current_function_decl);
7825 return (TARGET_MIPS16
7826 && TARGET_HARD_FLOAT_ABI
7827 && !aggregate_value_p (return_type, current_function_decl)
7828 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
7831 /* Return true if the current function must save register REGNO. */
7833 static bool
7834 mips_save_reg_p (unsigned int regno)
7836 /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
7837 if we have not chosen a call-clobbered substitute. */
7838 if (regno == GLOBAL_POINTER_REGNUM)
7839 return TARGET_CALL_SAVED_GP && cfun->machine->global_pointer == regno;
7841 /* Check call-saved registers. */
7842 if ((crtl->saves_all_registers || df_regs_ever_live_p (regno))
7843 && !call_really_used_regs[regno])
7844 return true;
7846 /* Save both registers in an FPR pair if either one is used. This is
7847 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
7848 register to be used without the even register. */
7849 if (FP_REG_P (regno)
7850 && MAX_FPRS_PER_FMT == 2
7851 && df_regs_ever_live_p (regno + 1)
7852 && !call_really_used_regs[regno + 1])
7853 return true;
7855 /* We need to save the old frame pointer before setting up a new one. */
7856 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
7857 return true;
7859 /* Check for registers that must be saved for FUNCTION_PROFILER. */
7860 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
7861 return true;
7863 /* We need to save the incoming return address if it is ever clobbered
7864 within the function, if __builtin_eh_return is being used to set a
7865 different return address, or if a stub is being used to return a
7866 value in FPRs. */
7867 if (regno == GP_REG_FIRST + 31
7868 && (df_regs_ever_live_p (regno)
7869 || crtl->calls_eh_return
7870 || mips16_cfun_returns_in_fpr_p ()))
7871 return true;
7873 return false;
7876 /* Populate the current function's mips_frame_info structure.
7878 MIPS stack frames look like:
7880 +-------------------------------+
7882 | incoming stack arguments |
7884 +-------------------------------+
7886 | caller-allocated save area |
7887 A | for register arguments |
7889 +-------------------------------+ <-- incoming stack pointer
7891 | callee-allocated save area |
7892 B | for arguments that are |
7893 | split between registers and |
7894 | the stack |
7896 +-------------------------------+ <-- arg_pointer_rtx
7898 C | callee-allocated save area |
7899 | for register varargs |
7901 +-------------------------------+ <-- frame_pointer_rtx + fp_sp_offset
7902 | | + UNITS_PER_HWFPVALUE
7903 | FPR save area |
7905 +-------------------------------+ <-- frame_pointer_rtx + gp_sp_offset
7906 | | + UNITS_PER_WORD
7907 | GPR save area |
7909 +-------------------------------+
7910 | | \
7911 | local variables | | var_size
7912 | | /
7913 +-------------------------------+
7914 | | \
7915 | $gp save area | | cprestore_size
7916 | | /
7917 P +-------------------------------+ <-- hard_frame_pointer_rtx for
7918 | | MIPS16 code
7919 | outgoing stack arguments |
7921 +-------------------------------+
7923 | caller-allocated save area |
7924 | for register arguments |
7926 +-------------------------------+ <-- stack_pointer_rtx
7927 frame_pointer_rtx
7928 hard_frame_pointer_rtx for
7929 non-MIPS16 code.
7931 At least two of A, B and C will be empty.
7933 Dynamic stack allocations such as alloca insert data at point P.
7934 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
7935 hard_frame_pointer_rtx unchanged. */
7937 static void
7938 mips_compute_frame_info (void)
7940 struct mips_frame_info *frame;
7941 HOST_WIDE_INT offset, size;
7942 unsigned int regno, i;
7944 frame = &cfun->machine->frame;
7945 memset (frame, 0, sizeof (*frame));
7946 size = get_frame_size ();
7948 cfun->machine->global_pointer = mips_global_pointer ();
7950 /* The first STARTING_FRAME_OFFSET bytes contain the outgoing argument
7951 area and the $gp save slot. This area isn't needed in leaf functions,
7952 but if the target-independent frame size is nonzero, we're committed
7953 to allocating it anyway. */
7954 if (size == 0 && current_function_is_leaf)
7956 /* The MIPS 3.0 linker does not like functions that dynamically
7957 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
7958 looks like we are trying to create a second frame pointer to the
7959 function, so allocate some stack space to make it happy. */
7960 if (cfun->calls_alloca)
7961 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
7962 else
7963 frame->args_size = 0;
7964 frame->cprestore_size = 0;
7966 else
7968 frame->args_size = crtl->outgoing_args_size;
7969 frame->cprestore_size = STARTING_FRAME_OFFSET - frame->args_size;
7971 offset = frame->args_size + frame->cprestore_size;
7973 /* Move above the local variables. */
7974 frame->var_size = MIPS_STACK_ALIGN (size);
7975 offset += frame->var_size;
7977 /* Find out which GPRs we need to save. */
7978 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
7979 if (mips_save_reg_p (regno))
7981 frame->num_gp++;
7982 frame->mask |= 1 << (regno - GP_REG_FIRST);
7985 /* If this function calls eh_return, we must also save and restore the
7986 EH data registers. */
7987 if (crtl->calls_eh_return)
7988 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
7990 frame->num_gp++;
7991 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
7994 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
7995 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
7996 save all later registers too. */
7997 if (GENERATE_MIPS16E_SAVE_RESTORE)
7999 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
8000 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
8001 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
8002 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
8005 /* Move above the GPR save area. */
8006 if (frame->num_gp > 0)
8008 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
8009 frame->gp_sp_offset = offset - UNITS_PER_WORD;
8012 /* Find out which FPRs we need to save. This loop must iterate over
8013 the same space as its companion in mips_for_each_saved_reg. */
8014 if (TARGET_HARD_FLOAT)
8015 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
8016 if (mips_save_reg_p (regno))
8018 frame->num_fp += MAX_FPRS_PER_FMT;
8019 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
8022 /* Move above the FPR save area. */
8023 if (frame->num_fp > 0)
8025 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
8026 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
8029 /* Move above the callee-allocated varargs save area. */
8030 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
8031 frame->arg_pointer_offset = offset;
8033 /* Move above the callee-allocated area for pretend stack arguments. */
8034 offset += crtl->args.pretend_args_size;
8035 frame->total_size = offset;
8037 /* Work out the offsets of the save areas from the top of the frame. */
8038 if (frame->gp_sp_offset > 0)
8039 frame->gp_save_offset = frame->gp_sp_offset - offset;
8040 if (frame->fp_sp_offset > 0)
8041 frame->fp_save_offset = frame->fp_sp_offset - offset;
8043 /* MIPS16 code offsets the frame pointer by the size of the outgoing
8044 arguments. This tends to increase the chances of using unextended
8045 instructions for local variables and incoming arguments. */
8046 if (TARGET_MIPS16)
8047 frame->hard_frame_pointer_offset = frame->args_size;
8050 /* Return the style of GP load sequence that is being used for the
8051 current function. */
8053 enum mips_loadgp_style
8054 mips_current_loadgp_style (void)
8056 if (!TARGET_USE_GOT || cfun->machine->global_pointer == 0)
8057 return LOADGP_NONE;
8059 if (TARGET_RTP_PIC)
8060 return LOADGP_RTP;
8062 if (TARGET_ABSOLUTE_ABICALLS)
8063 return LOADGP_ABSOLUTE;
8065 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
8068 /* Implement FRAME_POINTER_REQUIRED. */
8070 bool
8071 mips_frame_pointer_required (void)
8073 /* If the function contains dynamic stack allocations, we need to
8074 use the frame pointer to access the static parts of the frame. */
8075 if (cfun->calls_alloca)
8076 return true;
8078 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
8079 reload may be unable to compute the address of a local variable,
8080 since there is no way to add a large constant to the stack pointer
8081 without using a second temporary register. */
8082 if (TARGET_MIPS16)
8084 mips_compute_frame_info ();
8085 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
8086 return true;
8089 return false;
8092 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
8093 or argument pointer. TO is either the stack pointer or hard frame
8094 pointer. */
8096 HOST_WIDE_INT
8097 mips_initial_elimination_offset (int from, int to)
8099 HOST_WIDE_INT offset;
8101 mips_compute_frame_info ();
8103 /* Set OFFSET to the offset from the soft frame pointer, which is also
8104 the offset from the end-of-prologue stack pointer. */
8105 switch (from)
8107 case FRAME_POINTER_REGNUM:
8108 offset = 0;
8109 break;
8111 case ARG_POINTER_REGNUM:
8112 offset = cfun->machine->frame.arg_pointer_offset;
8113 break;
8115 default:
8116 gcc_unreachable ();
8119 if (to == HARD_FRAME_POINTER_REGNUM)
8120 offset -= cfun->machine->frame.hard_frame_pointer_offset;
8122 return offset;
8125 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
8127 static void
8128 mips_extra_live_on_entry (bitmap regs)
8130 if (TARGET_USE_GOT)
8132 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
8133 the global pointer. */
8134 if (!TARGET_ABSOLUTE_ABICALLS)
8135 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
8137 /* See the comment above load_call<mode> for details. */
8138 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
8142 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
8143 previous frame. */
8146 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
8148 if (count != 0)
8149 return const0_rtx;
8151 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
8154 /* Emit code to change the current function's return address to
8155 ADDRESS. SCRATCH is available as a scratch register, if needed.
8156 ADDRESS and SCRATCH are both word-mode GPRs. */
8158 void
8159 mips_set_return_address (rtx address, rtx scratch)
8161 rtx slot_address;
8163 gcc_assert (BITSET_P (cfun->machine->frame.mask, 31));
8164 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
8165 cfun->machine->frame.gp_sp_offset);
8166 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
8169 /* Restore $gp from its save slot. Valid only when using o32 or
8170 o64 abicalls. */
8172 void
8173 mips_restore_gp (void)
8175 rtx base, address;
8177 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
8179 base = frame_pointer_needed ? hard_frame_pointer_rtx : stack_pointer_rtx;
8180 address = mips_add_offset (pic_offset_table_rtx, base,
8181 crtl->outgoing_args_size);
8182 mips_emit_move (pic_offset_table_rtx, gen_frame_mem (Pmode, address));
8183 if (!TARGET_EXPLICIT_RELOCS)
8184 emit_insn (gen_blockage ());
8187 /* A function to save or store a register. The first argument is the
8188 register and the second is the stack slot. */
8189 typedef void (*mips_save_restore_fn) (rtx, rtx);
8191 /* Use FN to save or restore register REGNO. MODE is the register's
8192 mode and OFFSET is the offset of its save slot from the current
8193 stack pointer. */
8195 static void
8196 mips_save_restore_reg (enum machine_mode mode, int regno,
8197 HOST_WIDE_INT offset, mips_save_restore_fn fn)
8199 rtx mem;
8201 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
8202 fn (gen_rtx_REG (mode, regno), mem);
8205 /* Call FN for each register that is saved by the current function.
8206 SP_OFFSET is the offset of the current stack pointer from the start
8207 of the frame. */
8209 static void
8210 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
8212 enum machine_mode fpr_mode;
8213 HOST_WIDE_INT offset;
8214 int regno;
8216 /* Save registers starting from high to low. The debuggers prefer at least
8217 the return register be stored at func+4, and also it allows us not to
8218 need a nop in the epilogue if at least one register is reloaded in
8219 addition to return address. */
8220 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
8221 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
8222 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
8224 mips_save_restore_reg (word_mode, regno, offset, fn);
8225 offset -= UNITS_PER_WORD;
8228 /* This loop must iterate over the same space as its companion in
8229 mips_compute_frame_info. */
8230 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
8231 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
8232 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
8233 regno >= FP_REG_FIRST;
8234 regno -= MAX_FPRS_PER_FMT)
8235 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
8237 mips_save_restore_reg (fpr_mode, regno, offset, fn);
8238 offset -= GET_MODE_SIZE (fpr_mode);
8242 /* If we're generating n32 or n64 abicalls, and the current function
8243 does not use $28 as its global pointer, emit a cplocal directive.
8244 Use pic_offset_table_rtx as the argument to the directive. */
8246 static void
8247 mips_output_cplocal (void)
8249 if (!TARGET_EXPLICIT_RELOCS
8250 && cfun->machine->global_pointer > 0
8251 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
8252 output_asm_insn (".cplocal %+", 0);
8255 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
8257 static void
8258 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8260 const char *fnname;
8262 #ifdef SDB_DEBUGGING_INFO
8263 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
8264 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
8265 #endif
8267 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
8268 floating-point arguments. */
8269 if (TARGET_MIPS16
8270 && TARGET_HARD_FLOAT_ABI
8271 && crtl->args.info.fp_code != 0)
8272 mips16_build_function_stub ();
8274 /* Select the MIPS16 mode for this function. */
8275 if (TARGET_MIPS16)
8276 fprintf (file, "\t.set\tmips16\n");
8277 else
8278 fprintf (file, "\t.set\tnomips16\n");
8280 if (!FUNCTION_NAME_ALREADY_DECLARED)
8282 /* Get the function name the same way that toplev.c does before calling
8283 assemble_start_function. This is needed so that the name used here
8284 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8285 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8287 if (!flag_inhibit_size_directive)
8289 fputs ("\t.ent\t", file);
8290 assemble_name (file, fnname);
8291 fputs ("\n", file);
8294 assemble_name (file, fnname);
8295 fputs (":\n", file);
8298 /* Stop mips_file_end from treating this function as external. */
8299 if (TARGET_IRIX && mips_abi == ABI_32)
8300 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
8302 /* Output MIPS-specific frame information. */
8303 if (!flag_inhibit_size_directive)
8305 const struct mips_frame_info *frame;
8307 frame = &cfun->machine->frame;
8309 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
8310 fprintf (file,
8311 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
8312 "# vars= " HOST_WIDE_INT_PRINT_DEC
8313 ", regs= %d/%d"
8314 ", args= " HOST_WIDE_INT_PRINT_DEC
8315 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
8316 reg_names[frame_pointer_needed
8317 ? HARD_FRAME_POINTER_REGNUM
8318 : STACK_POINTER_REGNUM],
8319 (frame_pointer_needed
8320 ? frame->total_size - frame->hard_frame_pointer_offset
8321 : frame->total_size),
8322 reg_names[GP_REG_FIRST + 31],
8323 frame->var_size,
8324 frame->num_gp, frame->num_fp,
8325 frame->args_size,
8326 frame->cprestore_size);
8328 /* .mask MASK, OFFSET. */
8329 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8330 frame->mask, frame->gp_save_offset);
8332 /* .fmask MASK, OFFSET. */
8333 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8334 frame->fmask, frame->fp_save_offset);
8337 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
8338 Also emit the ".set noreorder; .set nomacro" sequence for functions
8339 that need it. */
8340 if (mips_current_loadgp_style () == LOADGP_OLDABI)
8342 /* .cpload must be in a .set noreorder but not a .set nomacro block. */
8343 if (!cfun->machine->all_noreorder_p)
8344 output_asm_insn ("%(.cpload\t%^%)", 0);
8345 else
8346 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
8348 else if (cfun->machine->all_noreorder_p)
8349 output_asm_insn ("%(%<", 0);
8351 /* Tell the assembler which register we're using as the global
8352 pointer. This is needed for thunks, since they can use either
8353 explicit relocs or assembler macros. */
8354 mips_output_cplocal ();
8357 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
8359 static void
8360 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8361 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8363 /* Reinstate the normal $gp. */
8364 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
8365 mips_output_cplocal ();
8367 if (cfun->machine->all_noreorder_p)
8369 /* Avoid using %>%) since it adds excess whitespace. */
8370 output_asm_insn (".set\tmacro", 0);
8371 output_asm_insn (".set\treorder", 0);
8372 set_noreorder = set_nomacro = 0;
8375 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
8377 const char *fnname;
8379 /* Get the function name the same way that toplev.c does before calling
8380 assemble_start_function. This is needed so that the name used here
8381 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8382 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8383 fputs ("\t.end\t", file);
8384 assemble_name (file, fnname);
8385 fputs ("\n", file);
8389 /* Save register REG to MEM. Make the instruction frame-related. */
8391 static void
8392 mips_save_reg (rtx reg, rtx mem)
8394 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
8396 rtx x1, x2;
8398 if (mips_split_64bit_move_p (mem, reg))
8399 mips_split_doubleword_move (mem, reg);
8400 else
8401 mips_emit_move (mem, reg);
8403 x1 = mips_frame_set (mips_subword (mem, false),
8404 mips_subword (reg, false));
8405 x2 = mips_frame_set (mips_subword (mem, true),
8406 mips_subword (reg, true));
8407 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
8409 else
8411 if (TARGET_MIPS16
8412 && REGNO (reg) != GP_REG_FIRST + 31
8413 && !M16_REG_P (REGNO (reg)))
8415 /* Save a non-MIPS16 register by moving it through a temporary.
8416 We don't need to do this for $31 since there's a special
8417 instruction for it. */
8418 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
8419 mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
8421 else
8422 mips_emit_move (mem, reg);
8424 mips_set_frame_expr (mips_frame_set (mem, reg));
8428 /* The __gnu_local_gp symbol. */
8430 static GTY(()) rtx mips_gnu_local_gp;
8432 /* If we're generating n32 or n64 abicalls, emit instructions
8433 to set up the global pointer. */
8435 static void
8436 mips_emit_loadgp (void)
8438 rtx addr, offset, incoming_address, base, index, pic_reg;
8440 pic_reg = pic_offset_table_rtx;
8441 switch (mips_current_loadgp_style ())
8443 case LOADGP_ABSOLUTE:
8444 if (mips_gnu_local_gp == NULL)
8446 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
8447 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
8449 emit_insn (Pmode == SImode
8450 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
8451 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
8452 break;
8454 case LOADGP_NEWABI:
8455 addr = XEXP (DECL_RTL (current_function_decl), 0);
8456 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
8457 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
8458 emit_insn (Pmode == SImode
8459 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
8460 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
8461 if (!TARGET_EXPLICIT_RELOCS)
8462 emit_insn (gen_loadgp_blockage ());
8463 break;
8465 case LOADGP_RTP:
8466 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
8467 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
8468 emit_insn (Pmode == SImode
8469 ? gen_loadgp_rtp_si (pic_reg, base, index)
8470 : gen_loadgp_rtp_di (pic_reg, base, index));
8471 if (!TARGET_EXPLICIT_RELOCS)
8472 emit_insn (gen_loadgp_blockage ());
8473 break;
8475 default:
8476 break;
8480 /* Expand the "prologue" pattern. */
8482 void
8483 mips_expand_prologue (void)
8485 const struct mips_frame_info *frame;
8486 HOST_WIDE_INT size;
8487 unsigned int nargs;
8488 rtx insn;
8490 if (cfun->machine->global_pointer > 0)
8491 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
8493 frame = &cfun->machine->frame;
8494 size = frame->total_size;
8496 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
8497 bytes beforehand; this is enough to cover the register save area
8498 without going out of range. */
8499 if ((frame->mask | frame->fmask) != 0)
8501 HOST_WIDE_INT step1;
8503 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
8504 if (GENERATE_MIPS16E_SAVE_RESTORE)
8506 HOST_WIDE_INT offset;
8507 unsigned int mask, regno;
8509 /* Try to merge argument stores into the save instruction. */
8510 nargs = mips16e_collect_argument_saves ();
8512 /* Build the save instruction. */
8513 mask = frame->mask;
8514 insn = mips16e_build_save_restore (false, &mask, &offset,
8515 nargs, step1);
8516 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8517 size -= step1;
8519 /* Check if we need to save other registers. */
8520 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
8521 if (BITSET_P (mask, regno - GP_REG_FIRST))
8523 offset -= UNITS_PER_WORD;
8524 mips_save_restore_reg (word_mode, regno,
8525 offset, mips_save_reg);
8528 else
8530 insn = gen_add3_insn (stack_pointer_rtx,
8531 stack_pointer_rtx,
8532 GEN_INT (-step1));
8533 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8534 size -= step1;
8535 mips_for_each_saved_reg (size, mips_save_reg);
8539 /* Allocate the rest of the frame. */
8540 if (size > 0)
8542 if (SMALL_OPERAND (-size))
8543 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
8544 stack_pointer_rtx,
8545 GEN_INT (-size)))) = 1;
8546 else
8548 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
8549 if (TARGET_MIPS16)
8551 /* There are no instructions to add or subtract registers
8552 from the stack pointer, so use the frame pointer as a
8553 temporary. We should always be using a frame pointer
8554 in this case anyway. */
8555 gcc_assert (frame_pointer_needed);
8556 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8557 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
8558 hard_frame_pointer_rtx,
8559 MIPS_PROLOGUE_TEMP (Pmode)));
8560 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
8562 else
8563 emit_insn (gen_sub3_insn (stack_pointer_rtx,
8564 stack_pointer_rtx,
8565 MIPS_PROLOGUE_TEMP (Pmode)));
8567 /* Describe the combined effect of the previous instructions. */
8568 mips_set_frame_expr
8569 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8570 plus_constant (stack_pointer_rtx, -size)));
8574 /* Set up the frame pointer, if we're using one. */
8575 if (frame_pointer_needed)
8577 HOST_WIDE_INT offset;
8579 offset = frame->hard_frame_pointer_offset;
8580 if (offset == 0)
8582 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8583 RTX_FRAME_RELATED_P (insn) = 1;
8585 else if (SMALL_OPERAND (offset))
8587 insn = gen_add3_insn (hard_frame_pointer_rtx,
8588 stack_pointer_rtx, GEN_INT (offset));
8589 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8591 else
8593 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
8594 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8595 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
8596 hard_frame_pointer_rtx,
8597 MIPS_PROLOGUE_TEMP (Pmode)));
8598 mips_set_frame_expr
8599 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
8600 plus_constant (stack_pointer_rtx, offset)));
8604 mips_emit_loadgp ();
8606 /* Initialize the $gp save slot. */
8607 if (frame->cprestore_size > 0)
8608 emit_insn (gen_cprestore (GEN_INT (crtl->outgoing_args_size)));
8610 /* If we are profiling, make sure no instructions are scheduled before
8611 the call to mcount. */
8612 if (crtl->profile)
8613 emit_insn (gen_blockage ());
8616 /* Emit instructions to restore register REG from slot MEM. */
8618 static void
8619 mips_restore_reg (rtx reg, rtx mem)
8621 /* There's no MIPS16 instruction to load $31 directly. Load into
8622 $7 instead and adjust the return insn appropriately. */
8623 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
8624 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
8626 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
8628 /* Can't restore directly; move through a temporary. */
8629 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
8630 mips_emit_move (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
8632 else
8633 mips_emit_move (reg, mem);
8636 /* Emit any instructions needed before a return. */
8638 void
8639 mips_expand_before_return (void)
8641 /* When using a call-clobbered gp, we start out with unified call
8642 insns that include instructions to restore the gp. We then split
8643 these unified calls after reload. These split calls explicitly
8644 clobber gp, so there is no need to define
8645 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
8647 For consistency, we should also insert an explicit clobber of $28
8648 before return insns, so that the post-reload optimizers know that
8649 the register is not live on exit. */
8650 if (TARGET_CALL_CLOBBERED_GP)
8651 emit_clobber (pic_offset_table_rtx);
8654 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
8655 says which. */
8657 void
8658 mips_expand_epilogue (bool sibcall_p)
8660 const struct mips_frame_info *frame;
8661 HOST_WIDE_INT step1, step2;
8662 rtx base, target;
8664 if (!sibcall_p && mips_can_use_return_insn ())
8666 emit_jump_insn (gen_return ());
8667 return;
8670 /* In MIPS16 mode, if the return value should go into a floating-point
8671 register, we need to call a helper routine to copy it over. */
8672 if (mips16_cfun_returns_in_fpr_p ())
8673 mips16_copy_fpr_return_value ();
8675 /* Split the frame into two. STEP1 is the amount of stack we should
8676 deallocate before restoring the registers. STEP2 is the amount we
8677 should deallocate afterwards.
8679 Start off by assuming that no registers need to be restored. */
8680 frame = &cfun->machine->frame;
8681 step1 = frame->total_size;
8682 step2 = 0;
8684 /* Work out which register holds the frame address. */
8685 if (!frame_pointer_needed)
8686 base = stack_pointer_rtx;
8687 else
8689 base = hard_frame_pointer_rtx;
8690 step1 -= frame->hard_frame_pointer_offset;
8693 /* If we need to restore registers, deallocate as much stack as
8694 possible in the second step without going out of range. */
8695 if ((frame->mask | frame->fmask) != 0)
8697 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
8698 step1 -= step2;
8701 /* Set TARGET to BASE + STEP1. */
8702 target = base;
8703 if (step1 > 0)
8705 rtx adjust;
8707 /* Get an rtx for STEP1 that we can add to BASE. */
8708 adjust = GEN_INT (step1);
8709 if (!SMALL_OPERAND (step1))
8711 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
8712 adjust = MIPS_EPILOGUE_TEMP (Pmode);
8715 /* Normal mode code can copy the result straight into $sp. */
8716 if (!TARGET_MIPS16)
8717 target = stack_pointer_rtx;
8719 emit_insn (gen_add3_insn (target, base, adjust));
8722 /* Copy TARGET into the stack pointer. */
8723 if (target != stack_pointer_rtx)
8724 mips_emit_move (stack_pointer_rtx, target);
8726 /* If we're using addressing macros, $gp is implicitly used by all
8727 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
8728 from the stack. */
8729 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
8730 emit_insn (gen_blockage ());
8732 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
8734 unsigned int regno, mask;
8735 HOST_WIDE_INT offset;
8736 rtx restore;
8738 /* Generate the restore instruction. */
8739 mask = frame->mask;
8740 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
8742 /* Restore any other registers manually. */
8743 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
8744 if (BITSET_P (mask, regno - GP_REG_FIRST))
8746 offset -= UNITS_PER_WORD;
8747 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
8750 /* Restore the remaining registers and deallocate the final bit
8751 of the frame. */
8752 emit_insn (restore);
8754 else
8756 /* Restore the registers. */
8757 mips_for_each_saved_reg (frame->total_size - step2, mips_restore_reg);
8759 /* Deallocate the final bit of the frame. */
8760 if (step2 > 0)
8761 emit_insn (gen_add3_insn (stack_pointer_rtx,
8762 stack_pointer_rtx,
8763 GEN_INT (step2)));
8766 /* Add in the __builtin_eh_return stack adjustment. We need to
8767 use a temporary in MIPS16 code. */
8768 if (crtl->calls_eh_return)
8770 if (TARGET_MIPS16)
8772 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
8773 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
8774 MIPS_EPILOGUE_TEMP (Pmode),
8775 EH_RETURN_STACKADJ_RTX));
8776 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
8778 else
8779 emit_insn (gen_add3_insn (stack_pointer_rtx,
8780 stack_pointer_rtx,
8781 EH_RETURN_STACKADJ_RTX));
8784 if (!sibcall_p)
8786 unsigned int regno;
8788 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
8789 path will restore the return address into $7 rather than $31. */
8790 if (TARGET_MIPS16
8791 && !GENERATE_MIPS16E_SAVE_RESTORE
8792 && BITSET_P (frame->mask, 31))
8793 regno = GP_REG_FIRST + 7;
8794 else
8795 regno = GP_REG_FIRST + 31;
8796 mips_expand_before_return ();
8797 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
8801 /* Return nonzero if this function is known to have a null epilogue.
8802 This allows the optimizer to omit jumps to jumps if no stack
8803 was created. */
8805 bool
8806 mips_can_use_return_insn (void)
8808 if (!reload_completed)
8809 return false;
8811 if (crtl->profile)
8812 return false;
8814 /* In MIPS16 mode, a function that returns a floating-point value
8815 needs to arrange to copy the return value into the floating-point
8816 registers. */
8817 if (mips16_cfun_returns_in_fpr_p ())
8818 return false;
8820 return cfun->machine->frame.total_size == 0;
8823 /* Return true if register REGNO can store a value of mode MODE.
8824 The result of this function is cached in mips_hard_regno_mode_ok. */
8826 static bool
8827 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
8829 unsigned int size;
8830 enum mode_class class;
8832 if (mode == CCV2mode)
8833 return (ISA_HAS_8CC
8834 && ST_REG_P (regno)
8835 && (regno - ST_REG_FIRST) % 2 == 0);
8837 if (mode == CCV4mode)
8838 return (ISA_HAS_8CC
8839 && ST_REG_P (regno)
8840 && (regno - ST_REG_FIRST) % 4 == 0);
8842 if (mode == CCmode)
8844 if (!ISA_HAS_8CC)
8845 return regno == FPSW_REGNUM;
8847 return (ST_REG_P (regno)
8848 || GP_REG_P (regno)
8849 || FP_REG_P (regno));
8852 size = GET_MODE_SIZE (mode);
8853 class = GET_MODE_CLASS (mode);
8855 if (GP_REG_P (regno))
8856 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
8858 if (FP_REG_P (regno)
8859 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
8860 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
8862 /* Allow TFmode for CCmode reloads. */
8863 if (mode == TFmode && ISA_HAS_8CC)
8864 return true;
8866 if (class == MODE_FLOAT
8867 || class == MODE_COMPLEX_FLOAT
8868 || class == MODE_VECTOR_FLOAT)
8869 return size <= UNITS_PER_FPVALUE;
8871 /* Allow integer modes that fit into a single register. We need
8872 to put integers into FPRs when using instructions like CVT
8873 and TRUNC. There's no point allowing sizes smaller than a word,
8874 because the FPU has no appropriate load/store instructions. */
8875 if (class == MODE_INT)
8876 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
8879 if (ACC_REG_P (regno)
8880 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
8882 if (size <= UNITS_PER_WORD)
8883 return true;
8885 if (size <= UNITS_PER_WORD * 2)
8886 return (DSP_ACC_REG_P (regno)
8887 ? ((regno - DSP_ACC_REG_FIRST) & 1) == 0
8888 : regno == MD_REG_FIRST);
8891 if (ALL_COP_REG_P (regno))
8892 return class == MODE_INT && size <= UNITS_PER_WORD;
8894 if (regno == GOT_VERSION_REGNUM)
8895 return mode == SImode;
8897 return false;
8900 /* Implement HARD_REGNO_NREGS. */
8902 unsigned int
8903 mips_hard_regno_nregs (int regno, enum machine_mode mode)
8905 if (ST_REG_P (regno))
8906 /* The size of FP status registers is always 4, because they only hold
8907 CCmode values, and CCmode is always considered to be 4 bytes wide. */
8908 return (GET_MODE_SIZE (mode) + 3) / 4;
8910 if (FP_REG_P (regno))
8911 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
8913 /* All other registers are word-sized. */
8914 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8917 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
8918 in mips_hard_regno_nregs. */
8921 mips_class_max_nregs (enum reg_class class, enum machine_mode mode)
8923 int size;
8924 HARD_REG_SET left;
8926 size = 0x8000;
8927 COPY_HARD_REG_SET (left, reg_class_contents[(int) class]);
8928 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
8930 size = MIN (size, 4);
8931 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
8933 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
8935 size = MIN (size, UNITS_PER_FPREG);
8936 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
8938 if (!hard_reg_set_empty_p (left))
8939 size = MIN (size, UNITS_PER_WORD);
8940 return (GET_MODE_SIZE (mode) + size - 1) / size;
8943 /* Implement CANNOT_CHANGE_MODE_CLASS. */
8945 bool
8946 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
8947 enum machine_mode to ATTRIBUTE_UNUSED,
8948 enum reg_class class)
8950 /* There are several problems with changing the modes of values
8951 in floating-point registers:
8953 - When a multi-word value is stored in paired floating-point
8954 registers, the first register always holds the low word.
8955 We therefore can't allow FPRs to change between single-word
8956 and multi-word modes on big-endian targets.
8958 - GCC assumes that each word of a multiword register can be accessed
8959 individually using SUBREGs. This is not true for floating-point
8960 registers if they are bigger than a word.
8962 - Loading a 32-bit value into a 64-bit floating-point register
8963 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
8964 We can't allow FPRs to change from SImode to to a wider mode on
8965 64-bit targets.
8967 - If the FPU has already interpreted a value in one format, we must
8968 not ask it to treat the value as having a different format.
8970 We therefore disallow all mode changes involving FPRs. */
8971 return reg_classes_intersect_p (FP_REGS, class);
8974 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
8976 static bool
8977 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
8979 switch (mode)
8981 case SFmode:
8982 return TARGET_HARD_FLOAT;
8984 case DFmode:
8985 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
8987 case V2SFmode:
8988 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
8990 default:
8991 return false;
8995 /* Implement MODES_TIEABLE_P. */
8997 bool
8998 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
9000 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
9001 prefer to put one of them in FPRs. */
9002 return (mode1 == mode2
9003 || (!mips_mode_ok_for_mov_fmt_p (mode1)
9004 && !mips_mode_ok_for_mov_fmt_p (mode2)));
9007 /* Implement PREFERRED_RELOAD_CLASS. */
9009 enum reg_class
9010 mips_preferred_reload_class (rtx x, enum reg_class class)
9012 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
9013 return LEA_REGS;
9015 if (reg_class_subset_p (FP_REGS, class)
9016 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
9017 return FP_REGS;
9019 if (reg_class_subset_p (GR_REGS, class))
9020 class = GR_REGS;
9022 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
9023 class = M16_REGS;
9025 return class;
9028 /* Implement REGISTER_MOVE_COST. */
9031 mips_register_move_cost (enum machine_mode mode,
9032 enum reg_class to, enum reg_class from)
9034 if (TARGET_MIPS16)
9036 /* ??? We cannot move general registers into HI and LO because
9037 MIPS16 has no MTHI and MTLO instructions. Make the cost of
9038 moves in the opposite direction just as high, which stops the
9039 register allocators from using HI and LO for pseudos. */
9040 if (reg_class_subset_p (from, GENERAL_REGS)
9041 && reg_class_subset_p (to, GENERAL_REGS))
9043 if (reg_class_subset_p (from, M16_REGS)
9044 || reg_class_subset_p (to, M16_REGS))
9045 return 2;
9046 /* Two MOVEs. */
9047 return 4;
9050 else if (reg_class_subset_p (from, GENERAL_REGS))
9052 if (reg_class_subset_p (to, GENERAL_REGS))
9053 return 2;
9054 if (reg_class_subset_p (to, FP_REGS))
9055 return 4;
9056 if (reg_class_subset_p (to, ALL_COP_AND_GR_REGS))
9057 return 5;
9058 if (reg_class_subset_p (to, ACC_REGS))
9059 return 6;
9061 else if (reg_class_subset_p (to, GENERAL_REGS))
9063 if (reg_class_subset_p (from, FP_REGS))
9064 return 4;
9065 if (reg_class_subset_p (from, ST_REGS))
9066 /* LUI followed by MOVF. */
9067 return 4;
9068 if (reg_class_subset_p (from, ALL_COP_AND_GR_REGS))
9069 return 5;
9070 if (reg_class_subset_p (from, ACC_REGS))
9071 return 6;
9073 else if (reg_class_subset_p (from, FP_REGS))
9075 if (reg_class_subset_p (to, FP_REGS)
9076 && mips_mode_ok_for_mov_fmt_p (mode))
9077 return 4;
9078 if (reg_class_subset_p (to, ST_REGS))
9079 /* An expensive sequence. */
9080 return 8;
9083 return 12;
9086 /* Return the register class required for a secondary register when
9087 copying between one of the registers in CLASS and value X, which
9088 has mode MODE. X is the source of the move if IN_P, otherwise it
9089 is the destination. Return NO_REGS if no secondary register is
9090 needed. */
9092 enum reg_class
9093 mips_secondary_reload_class (enum reg_class class,
9094 enum machine_mode mode, rtx x, bool in_p)
9096 int regno;
9098 /* If X is a constant that cannot be loaded into $25, it must be loaded
9099 into some other GPR. No other register class allows a direct move. */
9100 if (mips_dangerous_for_la25_p (x))
9101 return reg_class_subset_p (class, LEA_REGS) ? NO_REGS : LEA_REGS;
9103 regno = true_regnum (x);
9104 if (TARGET_MIPS16)
9106 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
9107 if (!reg_class_subset_p (class, M16_REGS) && !M16_REG_P (regno))
9108 return M16_REGS;
9110 /* We can't really copy to HI or LO at all in MIPS16 mode. */
9111 if (in_p ? reg_classes_intersect_p (class, ACC_REGS) : ACC_REG_P (regno))
9112 return M16_REGS;
9114 return NO_REGS;
9117 /* Copying from accumulator registers to anywhere other than a general
9118 register requires a temporary general register. */
9119 if (reg_class_subset_p (class, ACC_REGS))
9120 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
9121 if (ACC_REG_P (regno))
9122 return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
9124 /* We can only copy a value to a condition code register from a
9125 floating-point register, and even then we require a scratch
9126 floating-point register. We can only copy a value out of a
9127 condition-code register into a general register. */
9128 if (reg_class_subset_p (class, ST_REGS))
9130 if (in_p)
9131 return FP_REGS;
9132 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
9134 if (ST_REG_P (regno))
9136 if (!in_p)
9137 return FP_REGS;
9138 return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
9141 if (reg_class_subset_p (class, FP_REGS))
9143 if (MEM_P (x)
9144 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
9145 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
9146 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
9147 return NO_REGS;
9149 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
9150 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
9151 return NO_REGS;
9153 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
9154 /* We can force the constant to memory and use lwc1
9155 and ldc1. As above, we will use pairs of lwc1s if
9156 ldc1 is not supported. */
9157 return NO_REGS;
9159 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
9160 /* In this case we can use mov.fmt. */
9161 return NO_REGS;
9163 /* Otherwise, we need to reload through an integer register. */
9164 return GR_REGS;
9166 if (FP_REG_P (regno))
9167 return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
9169 return NO_REGS;
9172 /* Implement TARGET_MODE_REP_EXTENDED. */
9174 static int
9175 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
9177 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
9178 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
9179 return SIGN_EXTEND;
9181 return UNKNOWN;
9184 /* Implement TARGET_VALID_POINTER_MODE. */
9186 static bool
9187 mips_valid_pointer_mode (enum machine_mode mode)
9189 return mode == SImode || (TARGET_64BIT && mode == DImode);
9192 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
9194 static bool
9195 mips_vector_mode_supported_p (enum machine_mode mode)
9197 switch (mode)
9199 case V2SFmode:
9200 return TARGET_PAIRED_SINGLE_FLOAT;
9202 case V2HImode:
9203 case V4QImode:
9204 case V2HQmode:
9205 case V2UHQmode:
9206 case V2HAmode:
9207 case V2UHAmode:
9208 case V4QQmode:
9209 case V4UQQmode:
9210 return TARGET_DSP;
9212 default:
9213 return false;
9217 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
9219 static bool
9220 mips_scalar_mode_supported_p (enum machine_mode mode)
9222 if (ALL_FIXED_POINT_MODE_P (mode)
9223 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
9224 return true;
9226 return default_scalar_mode_supported_p (mode);
9229 /* Implement TARGET_INIT_LIBFUNCS. */
9231 #include "config/gofast.h"
9233 static void
9234 mips_init_libfuncs (void)
9236 if (TARGET_FIX_VR4120)
9238 /* Register the special divsi3 and modsi3 functions needed to work
9239 around VR4120 division errata. */
9240 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9241 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9244 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
9246 /* Register the MIPS16 -mhard-float stubs. */
9247 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9248 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9249 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9250 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9252 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9253 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9254 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9255 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9256 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9257 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9258 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
9260 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9261 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9262 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
9264 if (TARGET_DOUBLE_FLOAT)
9266 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9267 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9268 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9269 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9271 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9272 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9273 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9274 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9275 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9276 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9277 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
9279 set_conv_libfunc (sext_optab, DFmode, SFmode,
9280 "__mips16_extendsfdf2");
9281 set_conv_libfunc (trunc_optab, SFmode, DFmode,
9282 "__mips16_truncdfsf2");
9283 set_conv_libfunc (sfix_optab, SImode, DFmode,
9284 "__mips16_fix_truncdfsi");
9285 set_conv_libfunc (sfloat_optab, DFmode, SImode,
9286 "__mips16_floatsidf");
9287 set_conv_libfunc (ufloat_optab, DFmode, SImode,
9288 "__mips16_floatunsidf");
9291 else
9292 /* Register the gofast functions if selected using --enable-gofast. */
9293 gofast_maybe_init_libfuncs ();
9296 /* Return the length of INSN. LENGTH is the initial length computed by
9297 attributes in the machine-description file. */
9300 mips_adjust_insn_length (rtx insn, int length)
9302 /* A unconditional jump has an unfilled delay slot if it is not part
9303 of a sequence. A conditional jump normally has a delay slot, but
9304 does not on MIPS16. */
9305 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9306 length += 4;
9308 /* See how many nops might be needed to avoid hardware hazards. */
9309 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9310 switch (get_attr_hazard (insn))
9312 case HAZARD_NONE:
9313 break;
9315 case HAZARD_DELAY:
9316 length += 4;
9317 break;
9319 case HAZARD_HILO:
9320 length += 8;
9321 break;
9324 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
9325 the .md file length attributes are 4-based for both modes.
9326 Adjust the MIPS16 ones here. */
9327 if (TARGET_MIPS16)
9328 length /= 2;
9330 return length;
9333 /* Return an asm sequence to start a noat block and load the address
9334 of a label into $1. */
9336 const char *
9337 mips_output_load_label (void)
9339 if (TARGET_EXPLICIT_RELOCS)
9340 switch (mips_abi)
9342 case ABI_N32:
9343 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9345 case ABI_64:
9346 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9348 default:
9349 if (ISA_HAS_LOAD_DELAY)
9350 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9351 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9353 else
9355 if (Pmode == DImode)
9356 return "%[dla\t%@,%0";
9357 else
9358 return "%[la\t%@,%0";
9362 /* Return the assembly code for INSN, which has the operands given by
9363 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9364 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9365 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9366 version of BRANCH_IF_TRUE. */
9368 const char *
9369 mips_output_conditional_branch (rtx insn, rtx *operands,
9370 const char *branch_if_true,
9371 const char *branch_if_false)
9373 unsigned int length;
9374 rtx taken, not_taken;
9376 length = get_attr_length (insn);
9377 if (length <= 8)
9379 /* Just a simple conditional branch. */
9380 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9381 return branch_if_true;
9384 /* Generate a reversed branch around a direct jump. This fallback does
9385 not use branch-likely instructions. */
9386 mips_branch_likely = false;
9387 not_taken = gen_label_rtx ();
9388 taken = operands[1];
9390 /* Generate the reversed branch to NOT_TAKEN. */
9391 operands[1] = not_taken;
9392 output_asm_insn (branch_if_false, operands);
9394 /* If INSN has a delay slot, we must provide delay slots for both the
9395 branch to NOT_TAKEN and the conditional jump. We must also ensure
9396 that INSN's delay slot is executed in the appropriate cases. */
9397 if (final_sequence)
9399 /* This first delay slot will always be executed, so use INSN's
9400 delay slot if is not annulled. */
9401 if (!INSN_ANNULLED_BRANCH_P (insn))
9403 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9404 asm_out_file, optimize, 1, NULL);
9405 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9407 else
9408 output_asm_insn ("nop", 0);
9409 fprintf (asm_out_file, "\n");
9412 /* Output the unconditional branch to TAKEN. */
9413 if (length <= 16)
9414 output_asm_insn ("j\t%0%/", &taken);
9415 else
9417 output_asm_insn (mips_output_load_label (), &taken);
9418 output_asm_insn ("jr\t%@%]%/", 0);
9421 /* Now deal with its delay slot; see above. */
9422 if (final_sequence)
9424 /* This delay slot will only be executed if the branch is taken.
9425 Use INSN's delay slot if is annulled. */
9426 if (INSN_ANNULLED_BRANCH_P (insn))
9428 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9429 asm_out_file, optimize, 1, NULL);
9430 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9432 else
9433 output_asm_insn ("nop", 0);
9434 fprintf (asm_out_file, "\n");
9437 /* Output NOT_TAKEN. */
9438 targetm.asm_out.internal_label (asm_out_file, "L",
9439 CODE_LABEL_NUMBER (not_taken));
9440 return "";
9443 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9444 if some ordering condition is true. The condition is given by
9445 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9446 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9447 its second is always zero. */
9449 const char *
9450 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9452 const char *branch[2];
9454 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9455 Make BRANCH[0] branch on the inverse condition. */
9456 switch (GET_CODE (operands[0]))
9458 /* These cases are equivalent to comparisons against zero. */
9459 case LEU:
9460 inverted_p = !inverted_p;
9461 /* Fall through. */
9462 case GTU:
9463 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9464 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9465 break;
9467 /* These cases are always true or always false. */
9468 case LTU:
9469 inverted_p = !inverted_p;
9470 /* Fall through. */
9471 case GEU:
9472 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9473 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9474 break;
9476 default:
9477 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9478 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9479 break;
9481 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9484 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
9485 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
9487 When working around R4000 and R4400 errata, we need to make sure that
9488 the division is not immediately followed by a shift[1][2]. We also
9489 need to stop the division from being put into a branch delay slot[3].
9490 The easiest way to avoid both problems is to add a nop after the
9491 division. When a divide-by-zero check is needed, this nop can be
9492 used to fill the branch delay slot.
9494 [1] If a double-word or a variable shift executes immediately
9495 after starting an integer division, the shift may give an
9496 incorrect result. See quotations of errata #16 and #28 from
9497 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9498 in mips.md for details.
9500 [2] A similar bug to [1] exists for all revisions of the
9501 R4000 and the R4400 when run in an MC configuration.
9502 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9504 "19. In this following sequence:
9506 ddiv (or ddivu or div or divu)
9507 dsll32 (or dsrl32, dsra32)
9509 if an MPT stall occurs, while the divide is slipping the cpu
9510 pipeline, then the following double shift would end up with an
9511 incorrect result.
9513 Workaround: The compiler needs to avoid generating any
9514 sequence with divide followed by extended double shift."
9516 This erratum is also present in "MIPS R4400MC Errata, Processor
9517 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9518 & 3.0" as errata #10 and #4, respectively.
9520 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9521 (also valid for MIPS R4000MC processors):
9523 "52. R4000SC: This bug does not apply for the R4000PC.
9525 There are two flavors of this bug:
9527 1) If the instruction just after divide takes an RF exception
9528 (tlb-refill, tlb-invalid) and gets an instruction cache
9529 miss (both primary and secondary) and the line which is
9530 currently in secondary cache at this index had the first
9531 data word, where the bits 5..2 are set, then R4000 would
9532 get a wrong result for the div.
9536 div r8, r9
9537 ------------------- # end-of page. -tlb-refill
9541 div r8, r9
9542 ------------------- # end-of page. -tlb-invalid
9545 2) If the divide is in the taken branch delay slot, where the
9546 target takes RF exception and gets an I-cache miss for the
9547 exception vector or where I-cache miss occurs for the
9548 target address, under the above mentioned scenarios, the
9549 div would get wrong results.
9552 j r2 # to next page mapped or unmapped
9553 div r8,r9 # this bug would be there as long
9554 # as there is an ICache miss and
9555 nop # the "data pattern" is present
9558 beq r0, r0, NextPage # to Next page
9559 div r8,r9
9562 This bug is present for div, divu, ddiv, and ddivu
9563 instructions.
9565 Workaround: For item 1), OS could make sure that the next page
9566 after the divide instruction is also mapped. For item 2), the
9567 compiler could make sure that the divide instruction is not in
9568 the branch delay slot."
9570 These processors have PRId values of 0x00004220 and 0x00004300 for
9571 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9573 const char *
9574 mips_output_division (const char *division, rtx *operands)
9576 const char *s;
9578 s = division;
9579 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9581 output_asm_insn (s, operands);
9582 s = "nop";
9584 if (TARGET_CHECK_ZERO_DIV)
9586 if (TARGET_MIPS16)
9588 output_asm_insn (s, operands);
9589 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9591 else if (GENERATE_DIVIDE_TRAPS)
9593 output_asm_insn (s, operands);
9594 s = "teq\t%2,%.,7";
9596 else
9598 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9599 output_asm_insn (s, operands);
9600 s = "break\t7%)\n1:";
9603 return s;
9606 /* Return true if IN_INSN is a multiply-add or multiply-subtract
9607 instruction and if OUT_INSN assigns to the accumulator operand. */
9609 bool
9610 mips_linked_madd_p (rtx out_insn, rtx in_insn)
9612 rtx x;
9614 x = single_set (in_insn);
9615 if (x == 0)
9616 return false;
9618 x = SET_SRC (x);
9620 if (GET_CODE (x) == PLUS
9621 && GET_CODE (XEXP (x, 0)) == MULT
9622 && reg_set_p (XEXP (x, 1), out_insn))
9623 return true;
9625 if (GET_CODE (x) == MINUS
9626 && GET_CODE (XEXP (x, 1)) == MULT
9627 && reg_set_p (XEXP (x, 0), out_insn))
9628 return true;
9630 return false;
9633 /* True if the dependency between OUT_INSN and IN_INSN is on the store
9634 data rather than the address. We need this because the cprestore
9635 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
9636 which causes the default routine to abort. We just return false
9637 for that case. */
9639 bool
9640 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
9642 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
9643 return false;
9645 return !store_data_bypass_p (out_insn, in_insn);
9648 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9649 dependencies have no cost, except on the 20Kc where output-dependence
9650 is treated like input-dependence. */
9652 static int
9653 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9654 rtx dep ATTRIBUTE_UNUSED, int cost)
9656 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
9657 && TUNE_20KC)
9658 return cost;
9659 if (REG_NOTE_KIND (link) != 0)
9660 return 0;
9661 return cost;
9664 /* Return the number of instructions that can be issued per cycle. */
9666 static int
9667 mips_issue_rate (void)
9669 switch (mips_tune)
9671 case PROCESSOR_74KC:
9672 case PROCESSOR_74KF2_1:
9673 case PROCESSOR_74KF1_1:
9674 case PROCESSOR_74KF3_2:
9675 /* The 74k is not strictly quad-issue cpu, but can be seen as one
9676 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
9677 but in reality only a maximum of 3 insns can be issued as
9678 floating-point loads and stores also require a slot in the
9679 AGEN pipe. */
9680 return 4;
9682 case PROCESSOR_20KC:
9683 case PROCESSOR_R4130:
9684 case PROCESSOR_R5400:
9685 case PROCESSOR_R5500:
9686 case PROCESSOR_R7000:
9687 case PROCESSOR_R9000:
9688 return 2;
9690 case PROCESSOR_SB1:
9691 case PROCESSOR_SB1A:
9692 /* This is actually 4, but we get better performance if we claim 3.
9693 This is partly because of unwanted speculative code motion with the
9694 larger number, and partly because in most common cases we can't
9695 reach the theoretical max of 4. */
9696 return 3;
9698 default:
9699 return 1;
9703 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9704 be as wide as the scheduling freedom in the DFA. */
9706 static int
9707 mips_multipass_dfa_lookahead (void)
9709 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9710 if (TUNE_SB1)
9711 return 4;
9713 return 0;
9716 /* Remove the instruction at index LOWER from ready queue READY and
9717 reinsert it in front of the instruction at index HIGHER. LOWER must
9718 be <= HIGHER. */
9720 static void
9721 mips_promote_ready (rtx *ready, int lower, int higher)
9723 rtx new_head;
9724 int i;
9726 new_head = ready[lower];
9727 for (i = lower; i < higher; i++)
9728 ready[i] = ready[i + 1];
9729 ready[i] = new_head;
9732 /* If the priority of the instruction at POS2 in the ready queue READY
9733 is within LIMIT units of that of the instruction at POS1, swap the
9734 instructions if POS2 is not already less than POS1. */
9736 static void
9737 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
9739 if (pos1 < pos2
9740 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
9742 rtx temp;
9744 temp = ready[pos1];
9745 ready[pos1] = ready[pos2];
9746 ready[pos2] = temp;
9750 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9751 that may clobber hi or lo. */
9752 static rtx mips_macc_chains_last_hilo;
9754 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9755 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9757 static void
9758 mips_macc_chains_record (rtx insn)
9760 if (get_attr_may_clobber_hilo (insn))
9761 mips_macc_chains_last_hilo = insn;
9764 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9765 has NREADY elements, looking for a multiply-add or multiply-subtract
9766 instruction that is cumulative with mips_macc_chains_last_hilo.
9767 If there is one, promote it ahead of anything else that might
9768 clobber hi or lo. */
9770 static void
9771 mips_macc_chains_reorder (rtx *ready, int nready)
9773 int i, j;
9775 if (mips_macc_chains_last_hilo != 0)
9776 for (i = nready - 1; i >= 0; i--)
9777 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9779 for (j = nready - 1; j > i; j--)
9780 if (recog_memoized (ready[j]) >= 0
9781 && get_attr_may_clobber_hilo (ready[j]))
9783 mips_promote_ready (ready, i, j);
9784 break;
9786 break;
9790 /* The last instruction to be scheduled. */
9791 static rtx vr4130_last_insn;
9793 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9794 points to an rtx that is initially an instruction. Nullify the rtx
9795 if the instruction uses the value of register X. */
9797 static void
9798 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
9799 void *data)
9801 rtx *insn_ptr;
9803 insn_ptr = (rtx *) data;
9804 if (REG_P (x)
9805 && *insn_ptr != 0
9806 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9807 *insn_ptr = 0;
9810 /* Return true if there is true register dependence between vr4130_last_insn
9811 and INSN. */
9813 static bool
9814 vr4130_true_reg_dependence_p (rtx insn)
9816 note_stores (PATTERN (vr4130_last_insn),
9817 vr4130_true_reg_dependence_p_1, &insn);
9818 return insn == 0;
9821 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9822 the ready queue and that INSN2 is the instruction after it, return
9823 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9824 in which INSN1 and INSN2 can probably issue in parallel, but for
9825 which (INSN2, INSN1) should be less sensitive to instruction
9826 alignment than (INSN1, INSN2). See 4130.md for more details. */
9828 static bool
9829 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9831 sd_iterator_def sd_it;
9832 dep_t dep;
9834 /* Check for the following case:
9836 1) there is some other instruction X with an anti dependence on INSN1;
9837 2) X has a higher priority than INSN2; and
9838 3) X is an arithmetic instruction (and thus has no unit restrictions).
9840 If INSN1 is the last instruction blocking X, it would better to
9841 choose (INSN1, X) over (INSN2, INSN1). */
9842 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
9843 if (DEP_TYPE (dep) == REG_DEP_ANTI
9844 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
9845 && recog_memoized (DEP_CON (dep)) >= 0
9846 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
9847 return false;
9849 if (vr4130_last_insn != 0
9850 && recog_memoized (insn1) >= 0
9851 && recog_memoized (insn2) >= 0)
9853 /* See whether INSN1 and INSN2 use different execution units,
9854 or if they are both ALU-type instructions. If so, they can
9855 probably execute in parallel. */
9856 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9857 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9858 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9860 /* If only one of the instructions has a dependence on
9861 vr4130_last_insn, prefer to schedule the other one first. */
9862 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
9863 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
9864 if (dep1_p != dep2_p)
9865 return dep1_p;
9867 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9868 is not an ALU-type instruction and if INSN1 uses the same
9869 execution unit. (Note that if this condition holds, we already
9870 know that INSN2 uses a different execution unit.) */
9871 if (class1 != VR4130_CLASS_ALU
9872 && recog_memoized (vr4130_last_insn) >= 0
9873 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9874 return true;
9877 return false;
9880 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9881 queue with at least two instructions. Swap the first two if
9882 vr4130_swap_insns_p says that it could be worthwhile. */
9884 static void
9885 vr4130_reorder (rtx *ready, int nready)
9887 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9888 mips_promote_ready (ready, nready - 2, nready - 1);
9891 /* Record whether last 74k AGEN instruction was a load or store. */
9892 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
9894 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
9895 resets to TYPE_UNKNOWN state. */
9897 static void
9898 mips_74k_agen_init (rtx insn)
9900 if (!insn || !NONJUMP_INSN_P (insn))
9901 mips_last_74k_agen_insn = TYPE_UNKNOWN;
9902 else
9904 enum attr_type type = get_attr_type (insn);
9905 if (type == TYPE_LOAD || type == TYPE_STORE)
9906 mips_last_74k_agen_insn = type;
9910 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
9911 loads to be grouped together, and multiple stores to be grouped
9912 together. Swap things around in the ready queue to make this happen. */
9914 static void
9915 mips_74k_agen_reorder (rtx *ready, int nready)
9917 int i;
9918 int store_pos, load_pos;
9920 store_pos = -1;
9921 load_pos = -1;
9923 for (i = nready - 1; i >= 0; i--)
9925 rtx insn = ready[i];
9926 if (USEFUL_INSN_P (insn))
9927 switch (get_attr_type (insn))
9929 case TYPE_STORE:
9930 if (store_pos == -1)
9931 store_pos = i;
9932 break;
9934 case TYPE_LOAD:
9935 if (load_pos == -1)
9936 load_pos = i;
9937 break;
9939 default:
9940 break;
9944 if (load_pos == -1 || store_pos == -1)
9945 return;
9947 switch (mips_last_74k_agen_insn)
9949 case TYPE_UNKNOWN:
9950 /* Prefer to schedule loads since they have a higher latency. */
9951 case TYPE_LOAD:
9952 /* Swap loads to the front of the queue. */
9953 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
9954 break;
9955 case TYPE_STORE:
9956 /* Swap stores to the front of the queue. */
9957 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
9958 break;
9959 default:
9960 break;
9964 /* Implement TARGET_SCHED_INIT. */
9966 static void
9967 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9968 int max_ready ATTRIBUTE_UNUSED)
9970 mips_macc_chains_last_hilo = 0;
9971 vr4130_last_insn = 0;
9972 mips_74k_agen_init (NULL_RTX);
9975 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
9977 static int
9978 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9979 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
9981 if (!reload_completed
9982 && TUNE_MACC_CHAINS
9983 && *nreadyp > 0)
9984 mips_macc_chains_reorder (ready, *nreadyp);
9986 if (reload_completed
9987 && TUNE_MIPS4130
9988 && !TARGET_VR4130_ALIGN
9989 && *nreadyp > 1)
9990 vr4130_reorder (ready, *nreadyp);
9992 if (TUNE_74K)
9993 mips_74k_agen_reorder (ready, *nreadyp);
9995 return mips_issue_rate ();
9998 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
10000 static int
10001 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10002 rtx insn, int more)
10004 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
10005 if (USEFUL_INSN_P (insn))
10007 more--;
10008 if (!reload_completed && TUNE_MACC_CHAINS)
10009 mips_macc_chains_record (insn);
10010 vr4130_last_insn = insn;
10011 if (TUNE_74K)
10012 mips_74k_agen_init (insn);
10014 return more;
10017 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
10018 return the first operand of the associated PREF or PREFX insn. */
10021 mips_prefetch_cookie (rtx write, rtx locality)
10023 /* store_streamed / load_streamed. */
10024 if (INTVAL (locality) <= 0)
10025 return GEN_INT (INTVAL (write) + 4);
10027 /* store / load. */
10028 if (INTVAL (locality) <= 2)
10029 return write;
10031 /* store_retained / load_retained. */
10032 return GEN_INT (INTVAL (write) + 6);
10035 /* This structure describes a single built-in function. */
10036 struct mips_builtin_description {
10037 /* The code of the main .md file instruction. See mips_builtin_type
10038 for more information. */
10039 enum insn_code icode;
10041 /* The floating-point comparison code to use with ICODE, if any. */
10042 enum mips_fp_condition cond;
10044 /* The name of the built-in function. */
10045 const char *name;
10047 /* Specifies how the function should be expanded. */
10048 enum mips_builtin_type builtin_type;
10050 /* The function's prototype. */
10051 enum mips_function_type function_type;
10053 /* The target flags required for this function. */
10054 int target_flags;
10057 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
10058 FUNCTION_TYPE and TARGET_FLAGS are mips_builtin_description fields. */
10059 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10060 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10061 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
10063 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
10064 require TARGET_FLAGS. */
10065 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
10066 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
10067 "__builtin_mips_" #INSN "_" #COND "_s", \
10068 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
10069 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
10070 "__builtin_mips_" #INSN "_" #COND "_d", \
10071 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
10073 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
10074 The lower and upper forms require TARGET_FLAGS while the any and all
10075 forms require MASK_MIPS3D. */
10076 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
10077 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10078 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
10079 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10080 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10081 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
10082 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10083 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10084 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
10085 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
10086 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10087 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
10088 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
10090 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10091 require MASK_MIPS3D. */
10092 #define CMP_4S_BUILTINS(INSN, COND) \
10093 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10094 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
10095 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10096 MASK_MIPS3D }, \
10097 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10098 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
10099 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10100 MASK_MIPS3D }
10102 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10103 instruction requires TARGET_FLAGS. */
10104 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
10105 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10106 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
10107 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10108 TARGET_FLAGS }, \
10109 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10110 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10111 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10112 TARGET_FLAGS }
10114 /* Define all the built-in functions related to C.cond.fmt condition COND. */
10115 #define CMP_BUILTINS(COND) \
10116 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10117 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10118 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10119 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10120 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10121 CMP_4S_BUILTINS (c, COND), \
10122 CMP_4S_BUILTINS (cabs, COND)
10124 static const struct mips_builtin_description mips_ps_bdesc[] = {
10125 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10126 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10127 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10128 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10129 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
10130 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10131 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10132 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10134 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
10135 MASK_PAIRED_SINGLE_FLOAT),
10136 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10137 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10138 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10139 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10141 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10142 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10143 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10144 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10145 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10146 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10148 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10149 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10150 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10151 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10152 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10153 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10155 MIPS_FP_CONDITIONS (CMP_BUILTINS)
10158 /* Built-in functions for the SB-1 processor. */
10160 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10162 static const struct mips_builtin_description mips_sb1_bdesc[] = {
10163 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
10166 /* Built-in functions for the DSP ASE. */
10168 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10169 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10170 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10171 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10172 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
10174 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10175 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10176 mips_builtin_description fields. */
10177 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10178 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10179 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10181 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10182 branch instruction. TARGET_FLAGS is a mips_builtin_description field. */
10183 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10184 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10185 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10187 static const struct mips_builtin_description mips_dsp_bdesc[] = {
10188 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10189 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10190 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10191 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10192 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10193 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10194 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10195 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10196 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10197 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10198 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10199 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10200 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10201 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
10202 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
10203 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
10204 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10205 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10206 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10207 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10208 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10209 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10210 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10211 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10212 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10213 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10214 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10215 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10216 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10217 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10218 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10219 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10220 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10221 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10222 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10223 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10224 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10225 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10226 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10227 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10228 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10229 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10230 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10231 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10232 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10233 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10234 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10235 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10236 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10237 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10238 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10239 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10240 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10241 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10242 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10243 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10244 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10245 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10246 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10247 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10248 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10249 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, MASK_DSP),
10250 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, MASK_DSP),
10251 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, MASK_DSP),
10252 BPOSGE_BUILTIN (32, MASK_DSP),
10254 /* The following are for the MIPS DSP ASE REV 2. */
10255 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, MASK_DSPR2),
10256 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10257 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10258 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10259 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10260 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
10261 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
10262 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10263 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10264 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10265 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10266 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10267 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10268 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10269 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10270 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10271 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
10272 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
10273 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
10274 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
10275 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
10276 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSPR2),
10277 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10278 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10279 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10280 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10281 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10282 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10283 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10284 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10285 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10286 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10287 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10288 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2)
10291 static const struct mips_builtin_description mips_dsp_32only_bdesc[] = {
10292 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10293 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10294 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10295 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10296 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10297 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10298 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10299 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10300 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10301 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10302 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10303 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10304 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10305 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10306 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10307 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10308 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10309 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10310 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10311 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10312 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10314 /* The following are for the MIPS DSP ASE REV 2. */
10315 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10316 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10317 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
10318 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
10319 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
10320 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
10321 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10322 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, MASK_DSPR2),
10323 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, MASK_DSPR2),
10324 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10325 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10326 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10327 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10328 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10329 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2)
10332 /* This structure describes an array of mips_builtin_description entries. */
10333 struct mips_bdesc_map {
10334 /* The array that this entry describes. */
10335 const struct mips_builtin_description *bdesc;
10337 /* The number of entries in BDESC. */
10338 unsigned int size;
10340 /* The target processor that supports the functions in BDESC.
10341 PROCESSOR_MAX means we enable them for all processors. */
10342 enum processor_type proc;
10344 /* The functions in BDESC are not supported if any of these
10345 target flags are set. */
10346 int unsupported_target_flags;
10349 /* All MIPS-specific built-in functions. */
10350 static const struct mips_bdesc_map mips_bdesc_arrays[] = {
10351 { mips_ps_bdesc, ARRAY_SIZE (mips_ps_bdesc), PROCESSOR_MAX, 0 },
10352 { mips_sb1_bdesc, ARRAY_SIZE (mips_sb1_bdesc), PROCESSOR_SB1, 0 },
10353 { mips_dsp_bdesc, ARRAY_SIZE (mips_dsp_bdesc), PROCESSOR_MAX, 0 },
10354 { mips_dsp_32only_bdesc, ARRAY_SIZE (mips_dsp_32only_bdesc),
10355 PROCESSOR_MAX, MASK_64BIT }
10358 /* MODE is a vector mode whose elements have type TYPE. Return the type
10359 of the vector itself. */
10361 static tree
10362 mips_builtin_vector_type (tree type, enum machine_mode mode)
10364 static tree types[(int) MAX_MACHINE_MODE];
10366 if (types[(int) mode] == NULL_TREE)
10367 types[(int) mode] = build_vector_type_for_mode (type, mode);
10368 return types[(int) mode];
10371 /* Source-level argument types. */
10372 #define MIPS_ATYPE_VOID void_type_node
10373 #define MIPS_ATYPE_INT integer_type_node
10374 #define MIPS_ATYPE_POINTER ptr_type_node
10376 /* Standard mode-based argument types. */
10377 #define MIPS_ATYPE_SI intSI_type_node
10378 #define MIPS_ATYPE_USI unsigned_intSI_type_node
10379 #define MIPS_ATYPE_DI intDI_type_node
10380 #define MIPS_ATYPE_SF float_type_node
10381 #define MIPS_ATYPE_DF double_type_node
10383 /* Vector argument types. */
10384 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
10385 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
10386 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
10388 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
10389 their associated MIPS_ATYPEs. */
10390 #define MIPS_FTYPE_ATYPES1(A, B) \
10391 MIPS_ATYPE_##A, MIPS_ATYPE_##B
10393 #define MIPS_FTYPE_ATYPES2(A, B, C) \
10394 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
10396 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
10397 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
10399 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
10400 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
10401 MIPS_ATYPE_##E
10403 /* Return the function type associated with function prototype TYPE. */
10405 static tree
10406 mips_build_function_type (enum mips_function_type type)
10408 static tree types[(int) MIPS_MAX_FTYPE_MAX];
10410 if (types[(int) type] == NULL_TREE)
10411 switch (type)
10413 #define DEF_MIPS_FTYPE(NUM, ARGS) \
10414 case MIPS_FTYPE_NAME##NUM ARGS: \
10415 types[(int) type] \
10416 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
10417 NULL_TREE); \
10418 break;
10419 #include "config/mips/mips-ftypes.def"
10420 #undef DEF_MIPS_FTYPE
10421 default:
10422 gcc_unreachable ();
10425 return types[(int) type];
10428 /* Implement TARGET_INIT_BUILTINS. */
10430 static void
10431 mips_init_builtins (void)
10433 const struct mips_builtin_description *d;
10434 const struct mips_bdesc_map *m;
10435 unsigned int offset;
10437 /* Iterate through all of the bdesc arrays, initializing all of the
10438 builtin functions. */
10439 offset = 0;
10440 for (m = mips_bdesc_arrays;
10441 m < &mips_bdesc_arrays[ARRAY_SIZE (mips_bdesc_arrays)];
10442 m++)
10444 if ((m->proc == PROCESSOR_MAX || m->proc == mips_arch)
10445 && (m->unsupported_target_flags & target_flags) == 0)
10446 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10447 if ((d->target_flags & target_flags) == d->target_flags)
10448 add_builtin_function (d->name,
10449 mips_build_function_type (d->function_type),
10450 d - m->bdesc + offset,
10451 BUILT_IN_MD, NULL, NULL);
10452 offset += m->size;
10456 /* Take argument ARGNO from EXP's argument list and convert it into a
10457 form suitable for input operand OPNO of instruction ICODE. Return the
10458 value. */
10460 static rtx
10461 mips_prepare_builtin_arg (enum insn_code icode,
10462 unsigned int opno, tree exp, unsigned int argno)
10464 rtx value;
10465 enum machine_mode mode;
10467 value = expand_normal (CALL_EXPR_ARG (exp, argno));
10468 mode = insn_data[icode].operand[opno].mode;
10469 if (!insn_data[icode].operand[opno].predicate (value, mode))
10471 value = copy_to_mode_reg (mode, value);
10472 /* Check the predicate again. */
10473 if (!insn_data[icode].operand[opno].predicate (value, mode))
10475 error ("invalid argument to built-in function");
10476 return const0_rtx;
10480 return value;
10483 /* Return an rtx suitable for output operand OP of instruction ICODE.
10484 If TARGET is non-null, try to use it where possible. */
10486 static rtx
10487 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10489 enum machine_mode mode;
10491 mode = insn_data[icode].operand[op].mode;
10492 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10493 target = gen_reg_rtx (mode);
10495 return target;
10498 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
10499 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
10500 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
10501 suggests a good place to put the result. */
10503 static rtx
10504 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
10505 bool has_target_p)
10507 rtx ops[MAX_RECOG_OPERANDS];
10508 int opno, argno;
10510 /* Map any target to operand 0. */
10511 opno = 0;
10512 if (has_target_p)
10514 ops[opno] = mips_prepare_builtin_target (icode, opno, target);
10515 opno++;
10518 /* Map the arguments to the other operands. The n_operands value
10519 for an expander includes match_dups and match_scratches as well as
10520 match_operands, so n_operands is only an upper bound on the number
10521 of arguments to the expander function. */
10522 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
10523 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
10524 ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
10526 switch (opno)
10528 case 2:
10529 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
10530 break;
10532 case 3:
10533 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
10534 break;
10536 case 4:
10537 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
10538 break;
10540 default:
10541 gcc_unreachable ();
10543 return target;
10546 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
10547 function; TYPE says which. EXP is the CALL_EXPR that calls the
10548 function, ICODE is the instruction that should be used to compare
10549 the first two arguments, and COND is the condition it should test.
10550 TARGET, if nonnull, suggests a good place to put the result. */
10552 static rtx
10553 mips_expand_builtin_movtf (enum mips_builtin_type type,
10554 enum insn_code icode, enum mips_fp_condition cond,
10555 rtx target, tree exp)
10557 rtx cmp_result, op0, op1;
10559 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10560 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
10561 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
10562 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10564 icode = CODE_FOR_mips_cond_move_tf_ps;
10565 target = mips_prepare_builtin_target (icode, 0, target);
10566 if (type == MIPS_BUILTIN_MOVT)
10568 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
10569 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
10571 else
10573 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
10574 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
10576 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10577 return target;
10580 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10581 into TARGET otherwise. Return TARGET. */
10583 static rtx
10584 mips_builtin_branch_and_move (rtx condition, rtx target,
10585 rtx value_if_true, rtx value_if_false)
10587 rtx true_label, done_label;
10589 true_label = gen_label_rtx ();
10590 done_label = gen_label_rtx ();
10592 /* First assume that CONDITION is false. */
10593 mips_emit_move (target, value_if_false);
10595 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10596 emit_jump_insn (gen_condjump (condition, true_label));
10597 emit_jump_insn (gen_jump (done_label));
10598 emit_barrier ();
10600 /* Fix TARGET if CONDITION is true. */
10601 emit_label (true_label);
10602 mips_emit_move (target, value_if_true);
10604 emit_label (done_label);
10605 return target;
10608 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
10609 the CALL_EXPR that calls the function, ICODE is the code of the
10610 comparison instruction, and COND is the condition it should test.
10611 TARGET, if nonnull, suggests a good place to put the boolean result. */
10613 static rtx
10614 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10615 enum insn_code icode, enum mips_fp_condition cond,
10616 rtx target, tree exp)
10618 rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
10619 int argno;
10621 if (target == 0 || GET_MODE (target) != SImode)
10622 target = gen_reg_rtx (SImode);
10624 /* The instruction should have a target operand, an operand for each
10625 argument, and an operand for COND. */
10626 gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
10628 /* Prepare the operands to the comparison. */
10629 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10630 for (argno = 0; argno < call_expr_nargs (exp); argno++)
10631 args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
10633 switch (insn_data[icode].n_operands)
10635 case 4:
10636 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
10637 GEN_INT (cond)));
10638 break;
10640 case 6:
10641 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
10642 args[2], args[3], GEN_INT (cond)));
10643 break;
10645 default:
10646 gcc_unreachable ();
10649 /* If the comparison sets more than one register, we define the result
10650 to be 0 if all registers are false and -1 if all registers are true.
10651 The value of the complete result is indeterminate otherwise. */
10652 switch (builtin_type)
10654 case MIPS_BUILTIN_CMP_ALL:
10655 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
10656 return mips_builtin_branch_and_move (condition, target,
10657 const0_rtx, const1_rtx);
10659 case MIPS_BUILTIN_CMP_UPPER:
10660 case MIPS_BUILTIN_CMP_LOWER:
10661 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
10662 condition = gen_single_cc (cmp_result, offset);
10663 return mips_builtin_branch_and_move (condition, target,
10664 const1_rtx, const0_rtx);
10666 default:
10667 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
10668 return mips_builtin_branch_and_move (condition, target,
10669 const1_rtx, const0_rtx);
10673 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
10674 if nonnull, suggests a good place to put the boolean result. */
10676 static rtx
10677 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
10679 rtx condition, cmp_result;
10680 int cmp_value;
10682 if (target == 0 || GET_MODE (target) != SImode)
10683 target = gen_reg_rtx (SImode);
10685 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10687 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
10688 cmp_value = 32;
10689 else
10690 gcc_assert (0);
10692 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
10693 return mips_builtin_branch_and_move (condition, target,
10694 const1_rtx, const0_rtx);
10697 /* EXP is a CALL_EXPR that calls the function described by BDESC.
10698 Expand the call and return an rtx for its return value.
10699 TARGET, if nonnull, suggests a good place to put this value. */
10701 static rtx
10702 mips_expand_builtin_1 (const struct mips_builtin_description *bdesc,
10703 tree exp, rtx target)
10705 switch (bdesc->builtin_type)
10707 case MIPS_BUILTIN_DIRECT:
10708 return mips_expand_builtin_direct (bdesc->icode, target, exp, true);
10710 case MIPS_BUILTIN_DIRECT_NO_TARGET:
10711 return mips_expand_builtin_direct (bdesc->icode, target, exp, false);
10713 case MIPS_BUILTIN_MOVT:
10714 case MIPS_BUILTIN_MOVF:
10715 return mips_expand_builtin_movtf (bdesc->builtin_type, bdesc->icode,
10716 bdesc->cond, target, exp);
10718 case MIPS_BUILTIN_CMP_ANY:
10719 case MIPS_BUILTIN_CMP_ALL:
10720 case MIPS_BUILTIN_CMP_UPPER:
10721 case MIPS_BUILTIN_CMP_LOWER:
10722 case MIPS_BUILTIN_CMP_SINGLE:
10723 return mips_expand_builtin_compare (bdesc->builtin_type, bdesc->icode,
10724 bdesc->cond, target, exp);
10726 case MIPS_BUILTIN_BPOSGE32:
10727 return mips_expand_builtin_bposge (bdesc->builtin_type, target);
10729 gcc_unreachable ();
10732 /* Implement TARGET_EXPAND_BUILTIN. */
10734 static rtx
10735 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10736 enum machine_mode mode ATTRIBUTE_UNUSED,
10737 int ignore ATTRIBUTE_UNUSED)
10739 tree fndecl;
10740 unsigned int fcode;
10741 const struct mips_bdesc_map *m;
10743 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10744 fcode = DECL_FUNCTION_CODE (fndecl);
10745 if (TARGET_MIPS16)
10747 error ("built-in function %qs not supported for MIPS16",
10748 IDENTIFIER_POINTER (DECL_NAME (fndecl)));
10749 return const0_rtx;
10752 for (m = mips_bdesc_arrays;
10753 m < &mips_bdesc_arrays[ARRAY_SIZE (mips_bdesc_arrays)];
10754 m++)
10756 if (fcode < m->size)
10757 return mips_expand_builtin_1 (m->bdesc + fcode, exp, target);
10758 fcode -= m->size;
10760 gcc_unreachable ();
10763 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
10764 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
10765 struct mips16_constant {
10766 struct mips16_constant *next;
10767 rtx value;
10768 rtx label;
10769 enum machine_mode mode;
10772 /* Information about an incomplete MIPS16 constant pool. FIRST is the
10773 first constant, HIGHEST_ADDRESS is the highest address that the first
10774 byte of the pool can have, and INSN_ADDRESS is the current instruction
10775 address. */
10776 struct mips16_constant_pool {
10777 struct mips16_constant *first;
10778 int highest_address;
10779 int insn_address;
10782 /* Add constant VALUE to POOL and return its label. MODE is the
10783 value's mode (used for CONST_INTs, etc.). */
10785 static rtx
10786 mips16_add_constant (struct mips16_constant_pool *pool,
10787 rtx value, enum machine_mode mode)
10789 struct mips16_constant **p, *c;
10790 bool first_of_size_p;
10792 /* See whether the constant is already in the pool. If so, return the
10793 existing label, otherwise leave P pointing to the place where the
10794 constant should be added.
10796 Keep the pool sorted in increasing order of mode size so that we can
10797 reduce the number of alignments needed. */
10798 first_of_size_p = true;
10799 for (p = &pool->first; *p != 0; p = &(*p)->next)
10801 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
10802 return (*p)->label;
10803 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
10804 break;
10805 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
10806 first_of_size_p = false;
10809 /* In the worst case, the constant needed by the earliest instruction
10810 will end up at the end of the pool. The entire pool must then be
10811 accessible from that instruction.
10813 When adding the first constant, set the pool's highest address to
10814 the address of the first out-of-range byte. Adjust this address
10815 downwards each time a new constant is added. */
10816 if (pool->first == 0)
10817 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
10818 of the instruction with the lowest two bits clear. The base PC
10819 value for LDPC has the lowest three bits clear. Assume the worst
10820 case here; namely that the PC-relative instruction occupies the
10821 last 2 bytes in an aligned word. */
10822 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
10823 pool->highest_address -= GET_MODE_SIZE (mode);
10824 if (first_of_size_p)
10825 /* Take into account the worst possible padding due to alignment. */
10826 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
10828 /* Create a new entry. */
10829 c = XNEW (struct mips16_constant);
10830 c->value = value;
10831 c->mode = mode;
10832 c->label = gen_label_rtx ();
10833 c->next = *p;
10834 *p = c;
10836 return c->label;
10839 /* Output constant VALUE after instruction INSN and return the last
10840 instruction emitted. MODE is the mode of the constant. */
10842 static rtx
10843 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
10845 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
10847 rtx size = GEN_INT (GET_MODE_SIZE (mode));
10848 return emit_insn_after (gen_consttable_int (value, size), insn);
10851 if (SCALAR_FLOAT_MODE_P (mode))
10852 return emit_insn_after (gen_consttable_float (value), insn);
10854 if (VECTOR_MODE_P (mode))
10856 int i;
10858 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
10859 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
10860 CONST_VECTOR_ELT (value, i), insn);
10861 return insn;
10864 gcc_unreachable ();
10867 /* Dump out the constants in CONSTANTS after INSN. */
10869 static void
10870 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
10872 struct mips16_constant *c, *next;
10873 int align;
10875 align = 0;
10876 for (c = constants; c != NULL; c = next)
10878 /* If necessary, increase the alignment of PC. */
10879 if (align < GET_MODE_SIZE (c->mode))
10881 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
10882 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
10884 align = GET_MODE_SIZE (c->mode);
10886 insn = emit_label_after (c->label, insn);
10887 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
10889 next = c->next;
10890 free (c);
10893 emit_barrier_after (insn);
10896 /* Return the length of instruction INSN. */
10898 static int
10899 mips16_insn_length (rtx insn)
10901 if (JUMP_P (insn))
10903 rtx body = PATTERN (insn);
10904 if (GET_CODE (body) == ADDR_VEC)
10905 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
10906 if (GET_CODE (body) == ADDR_DIFF_VEC)
10907 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
10909 return get_attr_length (insn);
10912 /* If *X is a symbolic constant that refers to the constant pool, add
10913 the constant to POOL and rewrite *X to use the constant's label. */
10915 static void
10916 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
10918 rtx base, offset, label;
10920 split_const (*x, &base, &offset);
10921 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
10923 label = mips16_add_constant (pool, get_pool_constant (base),
10924 get_pool_mode (base));
10925 base = gen_rtx_LABEL_REF (Pmode, label);
10926 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
10930 /* This structure is used to communicate with mips16_rewrite_pool_refs.
10931 INSN is the instruction we're rewriting and POOL points to the current
10932 constant pool. */
10933 struct mips16_rewrite_pool_refs_info {
10934 rtx insn;
10935 struct mips16_constant_pool *pool;
10938 /* Rewrite *X so that constant pool references refer to the constant's
10939 label instead. DATA points to a mips16_rewrite_pool_refs_info
10940 structure. */
10942 static int
10943 mips16_rewrite_pool_refs (rtx *x, void *data)
10945 struct mips16_rewrite_pool_refs_info *info = data;
10947 if (force_to_mem_operand (*x, Pmode))
10949 rtx mem = force_const_mem (GET_MODE (*x), *x);
10950 validate_change (info->insn, x, mem, false);
10953 if (MEM_P (*x))
10955 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
10956 return -1;
10959 if (TARGET_MIPS16_TEXT_LOADS)
10960 mips16_rewrite_pool_constant (info->pool, x);
10962 return GET_CODE (*x) == CONST ? -1 : 0;
10965 /* Build MIPS16 constant pools. */
10967 static void
10968 mips16_lay_out_constants (void)
10970 struct mips16_constant_pool pool;
10971 struct mips16_rewrite_pool_refs_info info;
10972 rtx insn, barrier;
10974 if (!TARGET_MIPS16_PCREL_LOADS)
10975 return;
10977 barrier = 0;
10978 memset (&pool, 0, sizeof (pool));
10979 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10981 /* Rewrite constant pool references in INSN. */
10982 if (INSN_P (insn))
10984 info.insn = insn;
10985 info.pool = &pool;
10986 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
10989 pool.insn_address += mips16_insn_length (insn);
10991 if (pool.first != NULL)
10993 /* If there are no natural barriers between the first user of
10994 the pool and the highest acceptable address, we'll need to
10995 create a new instruction to jump around the constant pool.
10996 In the worst case, this instruction will be 4 bytes long.
10998 If it's too late to do this transformation after INSN,
10999 do it immediately before INSN. */
11000 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
11002 rtx label, jump;
11004 label = gen_label_rtx ();
11006 jump = emit_jump_insn_before (gen_jump (label), insn);
11007 JUMP_LABEL (jump) = label;
11008 LABEL_NUSES (label) = 1;
11009 barrier = emit_barrier_after (jump);
11011 emit_label_after (label, barrier);
11012 pool.insn_address += 4;
11015 /* See whether the constant pool is now out of range of the first
11016 user. If so, output the constants after the previous barrier.
11017 Note that any instructions between BARRIER and INSN (inclusive)
11018 will use negative offsets to refer to the pool. */
11019 if (pool.insn_address > pool.highest_address)
11021 mips16_emit_constants (pool.first, barrier);
11022 pool.first = NULL;
11023 barrier = 0;
11025 else if (BARRIER_P (insn))
11026 barrier = insn;
11029 mips16_emit_constants (pool.first, get_last_insn ());
11032 /* A temporary variable used by for_each_rtx callbacks, etc. */
11033 static rtx mips_sim_insn;
11035 /* A structure representing the state of the processor pipeline.
11036 Used by the mips_sim_* family of functions. */
11037 struct mips_sim {
11038 /* The maximum number of instructions that can be issued in a cycle.
11039 (Caches mips_issue_rate.) */
11040 unsigned int issue_rate;
11042 /* The current simulation time. */
11043 unsigned int time;
11045 /* How many more instructions can be issued in the current cycle. */
11046 unsigned int insns_left;
11048 /* LAST_SET[X].INSN is the last instruction to set register X.
11049 LAST_SET[X].TIME is the time at which that instruction was issued.
11050 INSN is null if no instruction has yet set register X. */
11051 struct {
11052 rtx insn;
11053 unsigned int time;
11054 } last_set[FIRST_PSEUDO_REGISTER];
11056 /* The pipeline's current DFA state. */
11057 state_t dfa_state;
11060 /* Reset STATE to the initial simulation state. */
11062 static void
11063 mips_sim_reset (struct mips_sim *state)
11065 state->time = 0;
11066 state->insns_left = state->issue_rate;
11067 memset (&state->last_set, 0, sizeof (state->last_set));
11068 state_reset (state->dfa_state);
11071 /* Initialize STATE before its first use. DFA_STATE points to an
11072 allocated but uninitialized DFA state. */
11074 static void
11075 mips_sim_init (struct mips_sim *state, state_t dfa_state)
11077 state->issue_rate = mips_issue_rate ();
11078 state->dfa_state = dfa_state;
11079 mips_sim_reset (state);
11082 /* Advance STATE by one clock cycle. */
11084 static void
11085 mips_sim_next_cycle (struct mips_sim *state)
11087 state->time++;
11088 state->insns_left = state->issue_rate;
11089 state_transition (state->dfa_state, 0);
11092 /* Advance simulation state STATE until instruction INSN can read
11093 register REG. */
11095 static void
11096 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
11098 unsigned int regno, end_regno;
11100 end_regno = END_REGNO (reg);
11101 for (regno = REGNO (reg); regno < end_regno; regno++)
11102 if (state->last_set[regno].insn != 0)
11104 unsigned int t;
11106 t = (state->last_set[regno].time
11107 + insn_latency (state->last_set[regno].insn, insn));
11108 while (state->time < t)
11109 mips_sim_next_cycle (state);
11113 /* A for_each_rtx callback. If *X is a register, advance simulation state
11114 DATA until mips_sim_insn can read the register's value. */
11116 static int
11117 mips_sim_wait_regs_2 (rtx *x, void *data)
11119 if (REG_P (*x))
11120 mips_sim_wait_reg (data, mips_sim_insn, *x);
11121 return 0;
11124 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
11126 static void
11127 mips_sim_wait_regs_1 (rtx *x, void *data)
11129 for_each_rtx (x, mips_sim_wait_regs_2, data);
11132 /* Advance simulation state STATE until all of INSN's register
11133 dependencies are satisfied. */
11135 static void
11136 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
11138 mips_sim_insn = insn;
11139 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
11142 /* Advance simulation state STATE until the units required by
11143 instruction INSN are available. */
11145 static void
11146 mips_sim_wait_units (struct mips_sim *state, rtx insn)
11148 state_t tmp_state;
11150 tmp_state = alloca (state_size ());
11151 while (state->insns_left == 0
11152 || (memcpy (tmp_state, state->dfa_state, state_size ()),
11153 state_transition (tmp_state, insn) >= 0))
11154 mips_sim_next_cycle (state);
11157 /* Advance simulation state STATE until INSN is ready to issue. */
11159 static void
11160 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
11162 mips_sim_wait_regs (state, insn);
11163 mips_sim_wait_units (state, insn);
11166 /* mips_sim_insn has just set X. Update the LAST_SET array
11167 in simulation state DATA. */
11169 static void
11170 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
11172 struct mips_sim *state;
11174 state = data;
11175 if (REG_P (x))
11177 unsigned int regno, end_regno;
11179 end_regno = END_REGNO (x);
11180 for (regno = REGNO (x); regno < end_regno; regno++)
11182 state->last_set[regno].insn = mips_sim_insn;
11183 state->last_set[regno].time = state->time;
11188 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
11189 can issue immediately (i.e., that mips_sim_wait_insn has already
11190 been called). */
11192 static void
11193 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
11195 state_transition (state->dfa_state, insn);
11196 state->insns_left--;
11198 mips_sim_insn = insn;
11199 note_stores (PATTERN (insn), mips_sim_record_set, state);
11202 /* Simulate issuing a NOP in state STATE. */
11204 static void
11205 mips_sim_issue_nop (struct mips_sim *state)
11207 if (state->insns_left == 0)
11208 mips_sim_next_cycle (state);
11209 state->insns_left--;
11212 /* Update simulation state STATE so that it's ready to accept the instruction
11213 after INSN. INSN should be part of the main rtl chain, not a member of a
11214 SEQUENCE. */
11216 static void
11217 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
11219 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
11220 if (JUMP_P (insn))
11221 mips_sim_issue_nop (state);
11223 switch (GET_CODE (SEQ_BEGIN (insn)))
11225 case CODE_LABEL:
11226 case CALL_INSN:
11227 /* We can't predict the processor state after a call or label. */
11228 mips_sim_reset (state);
11229 break;
11231 case JUMP_INSN:
11232 /* The delay slots of branch likely instructions are only executed
11233 when the branch is taken. Therefore, if the caller has simulated
11234 the delay slot instruction, STATE does not really reflect the state
11235 of the pipeline for the instruction after the delay slot. Also,
11236 branch likely instructions tend to incur a penalty when not taken,
11237 so there will probably be an extra delay between the branch and
11238 the instruction after the delay slot. */
11239 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
11240 mips_sim_reset (state);
11241 break;
11243 default:
11244 break;
11248 /* The VR4130 pipeline issues aligned pairs of instructions together,
11249 but it stalls the second instruction if it depends on the first.
11250 In order to cut down the amount of logic required, this dependence
11251 check is not based on a full instruction decode. Instead, any non-SPECIAL
11252 instruction is assumed to modify the register specified by bits 20-16
11253 (which is usually the "rt" field).
11255 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
11256 input, so we can end up with a false dependence between the branch
11257 and its delay slot. If this situation occurs in instruction INSN,
11258 try to avoid it by swapping rs and rt. */
11260 static void
11261 vr4130_avoid_branch_rt_conflict (rtx insn)
11263 rtx first, second;
11265 first = SEQ_BEGIN (insn);
11266 second = SEQ_END (insn);
11267 if (JUMP_P (first)
11268 && NONJUMP_INSN_P (second)
11269 && GET_CODE (PATTERN (first)) == SET
11270 && GET_CODE (SET_DEST (PATTERN (first))) == PC
11271 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
11273 /* Check for the right kind of condition. */
11274 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
11275 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
11276 && REG_P (XEXP (cond, 0))
11277 && REG_P (XEXP (cond, 1))
11278 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
11279 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
11281 /* SECOND mentions the rt register but not the rs register. */
11282 rtx tmp = XEXP (cond, 0);
11283 XEXP (cond, 0) = XEXP (cond, 1);
11284 XEXP (cond, 1) = tmp;
11289 /* Implement -mvr4130-align. Go through each basic block and simulate the
11290 processor pipeline. If we find that a pair of instructions could execute
11291 in parallel, and the first of those instructions is not 8-byte aligned,
11292 insert a nop to make it aligned. */
11294 static void
11295 vr4130_align_insns (void)
11297 struct mips_sim state;
11298 rtx insn, subinsn, last, last2, next;
11299 bool aligned_p;
11301 dfa_start ();
11303 /* LAST is the last instruction before INSN to have a nonzero length.
11304 LAST2 is the last such instruction before LAST. */
11305 last = 0;
11306 last2 = 0;
11308 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
11309 aligned_p = true;
11311 mips_sim_init (&state, alloca (state_size ()));
11312 for (insn = get_insns (); insn != 0; insn = next)
11314 unsigned int length;
11316 next = NEXT_INSN (insn);
11318 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
11319 This isn't really related to the alignment pass, but we do it on
11320 the fly to avoid a separate instruction walk. */
11321 vr4130_avoid_branch_rt_conflict (insn);
11323 if (USEFUL_INSN_P (insn))
11324 FOR_EACH_SUBINSN (subinsn, insn)
11326 mips_sim_wait_insn (&state, subinsn);
11328 /* If we want this instruction to issue in parallel with the
11329 previous one, make sure that the previous instruction is
11330 aligned. There are several reasons why this isn't worthwhile
11331 when the second instruction is a call:
11333 - Calls are less likely to be performance critical,
11334 - There's a good chance that the delay slot can execute
11335 in parallel with the call.
11336 - The return address would then be unaligned.
11338 In general, if we're going to insert a nop between instructions
11339 X and Y, it's better to insert it immediately after X. That
11340 way, if the nop makes Y aligned, it will also align any labels
11341 between X and Y. */
11342 if (state.insns_left != state.issue_rate
11343 && !CALL_P (subinsn))
11345 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
11347 /* SUBINSN is the first instruction in INSN and INSN is
11348 aligned. We want to align the previous instruction
11349 instead, so insert a nop between LAST2 and LAST.
11351 Note that LAST could be either a single instruction
11352 or a branch with a delay slot. In the latter case,
11353 LAST, like INSN, is already aligned, but the delay
11354 slot must have some extra delay that stops it from
11355 issuing at the same time as the branch. We therefore
11356 insert a nop before the branch in order to align its
11357 delay slot. */
11358 emit_insn_after (gen_nop (), last2);
11359 aligned_p = false;
11361 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
11363 /* SUBINSN is the delay slot of INSN, but INSN is
11364 currently unaligned. Insert a nop between
11365 LAST and INSN to align it. */
11366 emit_insn_after (gen_nop (), last);
11367 aligned_p = true;
11370 mips_sim_issue_insn (&state, subinsn);
11372 mips_sim_finish_insn (&state, insn);
11374 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
11375 length = get_attr_length (insn);
11376 if (length > 0)
11378 /* If the instruction is an asm statement or multi-instruction
11379 mips.md patern, the length is only an estimate. Insert an
11380 8 byte alignment after it so that the following instructions
11381 can be handled correctly. */
11382 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
11383 && (recog_memoized (insn) < 0 || length >= 8))
11385 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
11386 next = NEXT_INSN (next);
11387 mips_sim_next_cycle (&state);
11388 aligned_p = true;
11390 else if (length & 4)
11391 aligned_p = !aligned_p;
11392 last2 = last;
11393 last = insn;
11396 /* See whether INSN is an aligned label. */
11397 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
11398 aligned_p = true;
11400 dfa_finish ();
11403 /* This structure records that the current function has a LO_SUM
11404 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
11405 the largest offset applied to BASE by all such LO_SUMs. */
11406 struct mips_lo_sum_offset {
11407 rtx base;
11408 HOST_WIDE_INT offset;
11411 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
11413 static hashval_t
11414 mips_hash_base (rtx base)
11416 int do_not_record_p;
11418 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
11421 /* Hash-table callbacks for mips_lo_sum_offsets. */
11423 static hashval_t
11424 mips_lo_sum_offset_hash (const void *entry)
11426 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
11429 static int
11430 mips_lo_sum_offset_eq (const void *entry, const void *value)
11432 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
11433 (const_rtx) value);
11436 /* Look up symbolic constant X in HTAB, which is a hash table of
11437 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
11438 paired with a recorded LO_SUM, otherwise record X in the table. */
11440 static bool
11441 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
11443 rtx base, offset;
11444 void **slot;
11445 struct mips_lo_sum_offset *entry;
11447 /* Split X into a base and offset. */
11448 split_const (x, &base, &offset);
11449 if (UNSPEC_ADDRESS_P (base))
11450 base = UNSPEC_ADDRESS (base);
11452 /* Look up the base in the hash table. */
11453 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
11454 if (slot == NULL)
11455 return false;
11457 entry = (struct mips_lo_sum_offset *) *slot;
11458 if (option == INSERT)
11460 if (entry == NULL)
11462 entry = XNEW (struct mips_lo_sum_offset);
11463 entry->base = base;
11464 entry->offset = INTVAL (offset);
11465 *slot = entry;
11467 else
11469 if (INTVAL (offset) > entry->offset)
11470 entry->offset = INTVAL (offset);
11473 return INTVAL (offset) <= entry->offset;
11476 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
11477 Record every LO_SUM in *LOC. */
11479 static int
11480 mips_record_lo_sum (rtx *loc, void *data)
11482 if (GET_CODE (*loc) == LO_SUM)
11483 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
11484 return 0;
11487 /* Return true if INSN is a SET of an orphaned high-part relocation.
11488 HTAB is a hash table of mips_lo_sum_offsets that describes all the
11489 LO_SUMs in the current function. */
11491 static bool
11492 mips_orphaned_high_part_p (htab_t htab, rtx insn)
11494 enum mips_symbol_type type;
11495 rtx x, set;
11497 set = single_set (insn);
11498 if (set)
11500 /* Check for %his. */
11501 x = SET_SRC (set);
11502 if (GET_CODE (x) == HIGH
11503 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
11504 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
11506 /* Check for local %gots (and %got_pages, which is redundant but OK). */
11507 if (GET_CODE (x) == UNSPEC
11508 && XINT (x, 1) == UNSPEC_LOAD_GOT
11509 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
11510 SYMBOL_CONTEXT_LEA, &type)
11511 && type == SYMBOL_GOTOFF_PAGE)
11512 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
11514 return false;
11517 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
11518 INSN and a previous instruction, avoid it by inserting nops after
11519 instruction AFTER.
11521 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
11522 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
11523 before using the value of that register. *HILO_DELAY counts the
11524 number of instructions since the last hilo hazard (that is,
11525 the number of instructions since the last MFLO or MFHI).
11527 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
11528 for the next instruction.
11530 LO_REG is an rtx for the LO register, used in dependence checking. */
11532 static void
11533 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
11534 rtx *delayed_reg, rtx lo_reg)
11536 rtx pattern, set;
11537 int nops, ninsns;
11539 pattern = PATTERN (insn);
11541 /* Do not put the whole function in .set noreorder if it contains
11542 an asm statement. We don't know whether there will be hazards
11543 between the asm statement and the gcc-generated code. */
11544 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
11545 cfun->machine->all_noreorder_p = false;
11547 /* Ignore zero-length instructions (barriers and the like). */
11548 ninsns = get_attr_length (insn) / 4;
11549 if (ninsns == 0)
11550 return;
11552 /* Work out how many nops are needed. Note that we only care about
11553 registers that are explicitly mentioned in the instruction's pattern.
11554 It doesn't matter that calls use the argument registers or that they
11555 clobber hi and lo. */
11556 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
11557 nops = 2 - *hilo_delay;
11558 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
11559 nops = 1;
11560 else
11561 nops = 0;
11563 /* Insert the nops between this instruction and the previous one.
11564 Each new nop takes us further from the last hilo hazard. */
11565 *hilo_delay += nops;
11566 while (nops-- > 0)
11567 emit_insn_after (gen_hazard_nop (), after);
11569 /* Set up the state for the next instruction. */
11570 *hilo_delay += ninsns;
11571 *delayed_reg = 0;
11572 if (INSN_CODE (insn) >= 0)
11573 switch (get_attr_hazard (insn))
11575 case HAZARD_NONE:
11576 break;
11578 case HAZARD_HILO:
11579 *hilo_delay = 0;
11580 break;
11582 case HAZARD_DELAY:
11583 set = single_set (insn);
11584 gcc_assert (set);
11585 *delayed_reg = SET_DEST (set);
11586 break;
11590 /* Go through the instruction stream and insert nops where necessary.
11591 Also delete any high-part relocations whose partnering low parts
11592 are now all dead. See if the whole function can then be put into
11593 .set noreorder and .set nomacro. */
11595 static void
11596 mips_reorg_process_insns (void)
11598 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
11599 int hilo_delay;
11600 htab_t htab;
11602 /* Force all instructions to be split into their final form. */
11603 split_all_insns_noflow ();
11605 /* Recalculate instruction lengths without taking nops into account. */
11606 cfun->machine->ignore_hazard_length_p = true;
11607 shorten_branches (get_insns ());
11609 cfun->machine->all_noreorder_p = true;
11611 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
11612 if (!TARGET_EXPLICIT_RELOCS)
11613 cfun->machine->all_noreorder_p = false;
11615 /* Profiled functions can't be all noreorder because the profiler
11616 support uses assembler macros. */
11617 if (crtl->profile)
11618 cfun->machine->all_noreorder_p = false;
11620 /* Code compiled with -mfix-vr4120 can't be all noreorder because
11621 we rely on the assembler to work around some errata. */
11622 if (TARGET_FIX_VR4120)
11623 cfun->machine->all_noreorder_p = false;
11625 /* The same is true for -mfix-vr4130 if we might generate MFLO or
11626 MFHI instructions. Note that we avoid using MFLO and MFHI if
11627 the VR4130 MACC and DMACC instructions are available instead;
11628 see the *mfhilo_{si,di}_macc patterns. */
11629 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
11630 cfun->machine->all_noreorder_p = false;
11632 htab = htab_create (37, mips_lo_sum_offset_hash,
11633 mips_lo_sum_offset_eq, free);
11635 /* Make a first pass over the instructions, recording all the LO_SUMs. */
11636 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
11637 FOR_EACH_SUBINSN (subinsn, insn)
11638 if (INSN_P (subinsn))
11639 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
11641 last_insn = 0;
11642 hilo_delay = 2;
11643 delayed_reg = 0;
11644 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
11646 /* Make a second pass over the instructions. Delete orphaned
11647 high-part relocations or turn them into NOPs. Avoid hazards
11648 by inserting NOPs. */
11649 for (insn = get_insns (); insn != 0; insn = next_insn)
11651 next_insn = NEXT_INSN (insn);
11652 if (INSN_P (insn))
11654 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11656 /* If we find an orphaned high-part relocation in a delay
11657 slot, it's easier to turn that instruction into a NOP than
11658 to delete it. The delay slot will be a NOP either way. */
11659 FOR_EACH_SUBINSN (subinsn, insn)
11660 if (INSN_P (subinsn))
11662 if (mips_orphaned_high_part_p (htab, subinsn))
11664 PATTERN (subinsn) = gen_nop ();
11665 INSN_CODE (subinsn) = CODE_FOR_nop;
11667 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
11668 &delayed_reg, lo_reg);
11670 last_insn = insn;
11672 else
11674 /* INSN is a single instruction. Delete it if it's an
11675 orphaned high-part relocation. */
11676 if (mips_orphaned_high_part_p (htab, insn))
11677 delete_insn (insn);
11678 else
11680 mips_avoid_hazard (last_insn, insn, &hilo_delay,
11681 &delayed_reg, lo_reg);
11682 last_insn = insn;
11688 htab_delete (htab);
11691 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
11693 static void
11694 mips_reorg (void)
11696 mips16_lay_out_constants ();
11697 if (mips_base_delayed_branch)
11698 dbr_schedule (get_insns ());
11699 mips_reorg_process_insns ();
11700 if (TARGET_EXPLICIT_RELOCS && TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
11701 vr4130_align_insns ();
11704 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
11705 in order to avoid duplicating too much logic from elsewhere. */
11707 static void
11708 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11709 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11710 tree function)
11712 rtx this, temp1, temp2, insn, fnaddr;
11713 bool use_sibcall_p;
11715 /* Pretend to be a post-reload pass while generating rtl. */
11716 reload_completed = 1;
11718 /* Mark the end of the (empty) prologue. */
11719 emit_note (NOTE_INSN_PROLOGUE_END);
11721 /* Determine if we can use a sibcall to call FUNCTION directly. */
11722 fnaddr = XEXP (DECL_RTL (function), 0);
11723 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
11724 && const_call_insn_operand (fnaddr, Pmode));
11726 /* Determine if we need to load FNADDR from the GOT. */
11727 if (!use_sibcall_p)
11728 switch (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))
11730 case SYMBOL_GOT_PAGE_OFST:
11731 case SYMBOL_GOT_DISP:
11732 /* Pick a global pointer. Use a call-clobbered register if
11733 TARGET_CALL_SAVED_GP. */
11734 cfun->machine->global_pointer =
11735 TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
11736 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
11738 /* Set up the global pointer for n32 or n64 abicalls. */
11739 mips_emit_loadgp ();
11740 break;
11742 default:
11743 break;
11746 /* We need two temporary registers in some cases. */
11747 temp1 = gen_rtx_REG (Pmode, 2);
11748 temp2 = gen_rtx_REG (Pmode, 3);
11750 /* Find out which register contains the "this" pointer. */
11751 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11752 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
11753 else
11754 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
11756 /* Add DELTA to THIS. */
11757 if (delta != 0)
11759 rtx offset = GEN_INT (delta);
11760 if (!SMALL_OPERAND (delta))
11762 mips_emit_move (temp1, offset);
11763 offset = temp1;
11765 emit_insn (gen_add3_insn (this, this, offset));
11768 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
11769 if (vcall_offset != 0)
11771 rtx addr;
11773 /* Set TEMP1 to *THIS. */
11774 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this));
11776 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
11777 addr = mips_add_offset (temp2, temp1, vcall_offset);
11779 /* Load the offset and add it to THIS. */
11780 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
11781 emit_insn (gen_add3_insn (this, this, temp1));
11784 /* Jump to the target function. Use a sibcall if direct jumps are
11785 allowed, otherwise load the address into a register first. */
11786 if (use_sibcall_p)
11788 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
11789 SIBLING_CALL_P (insn) = 1;
11791 else
11793 /* This is messy. GAS treats "la $25,foo" as part of a call
11794 sequence and may allow a global "foo" to be lazily bound.
11795 The general move patterns therefore reject this combination.
11797 In this context, lazy binding would actually be OK
11798 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
11799 TARGET_CALL_SAVED_GP; see mips_load_call_address.
11800 We must therefore load the address via a temporary
11801 register if mips_dangerous_for_la25_p.
11803 If we jump to the temporary register rather than $25, the assembler
11804 can use the move insn to fill the jump's delay slot. */
11805 if (TARGET_USE_PIC_FN_ADDR_REG
11806 && !mips_dangerous_for_la25_p (fnaddr))
11807 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
11808 mips_load_call_address (temp1, fnaddr, true);
11810 if (TARGET_USE_PIC_FN_ADDR_REG
11811 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
11812 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
11813 emit_jump_insn (gen_indirect_jump (temp1));
11816 /* Run just enough of rest_of_compilation. This sequence was
11817 "borrowed" from alpha.c. */
11818 insn = get_insns ();
11819 insn_locators_alloc ();
11820 split_all_insns_noflow ();
11821 mips16_lay_out_constants ();
11822 shorten_branches (insn);
11823 final_start_function (insn, file, 1);
11824 final (insn, file, 1);
11825 final_end_function ();
11826 free_after_compilation (cfun);
11828 /* Clean up the vars set above. Note that final_end_function resets
11829 the global pointer for us. */
11830 reload_completed = 0;
11833 /* The last argument passed to mips_set_mips16_mode, or negative if the
11834 function hasn't been called yet. */
11835 static GTY(()) int was_mips16_p = -1;
11837 /* Set up the target-dependent global state so that it matches the
11838 current function's ISA mode. */
11840 static void
11841 mips_set_mips16_mode (int mips16_p)
11843 if (mips16_p == was_mips16_p)
11844 return;
11846 /* Restore base settings of various flags. */
11847 target_flags = mips_base_target_flags;
11848 flag_schedule_insns = mips_base_schedule_insns;
11849 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
11850 flag_move_loop_invariants = mips_base_move_loop_invariants;
11851 align_loops = mips_base_align_loops;
11852 align_jumps = mips_base_align_jumps;
11853 align_functions = mips_base_align_functions;
11855 if (mips16_p)
11857 /* Switch to MIPS16 mode. */
11858 target_flags |= MASK_MIPS16;
11860 /* Don't run the scheduler before reload, since it tends to
11861 increase register pressure. */
11862 flag_schedule_insns = 0;
11864 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
11865 the whole function to be in a single section. */
11866 flag_reorder_blocks_and_partition = 0;
11868 /* Don't move loop invariants, because it tends to increase
11869 register pressure. It also introduces an extra move in cases
11870 where the constant is the first operand in a two-operand binary
11871 instruction, or when it forms a register argument to a functon
11872 call. */
11873 flag_move_loop_invariants = 0;
11875 /* Silently disable -mexplicit-relocs since it doesn't apply
11876 to MIPS16 code. Even so, it would overly pedantic to warn
11877 about "-mips16 -mexplicit-relocs", especially given that
11878 we use a %gprel() operator. */
11879 target_flags &= ~MASK_EXPLICIT_RELOCS;
11881 /* Experiments suggest we get the best overall section-anchor
11882 results from using the range of an unextended LW or SW. Code
11883 that makes heavy use of byte or short accesses can do better
11884 with ranges of 0...31 and 0...63 respectively, but most code is
11885 sensitive to the range of LW and SW instead. */
11886 targetm.min_anchor_offset = 0;
11887 targetm.max_anchor_offset = 127;
11889 if (flag_pic || TARGET_ABICALLS)
11890 sorry ("MIPS16 PIC");
11892 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
11893 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
11895 else
11897 /* Switch to normal (non-MIPS16) mode. */
11898 target_flags &= ~MASK_MIPS16;
11900 /* Provide default values for align_* for 64-bit targets. */
11901 if (TARGET_64BIT)
11903 if (align_loops == 0)
11904 align_loops = 8;
11905 if (align_jumps == 0)
11906 align_jumps = 8;
11907 if (align_functions == 0)
11908 align_functions = 8;
11911 targetm.min_anchor_offset = -32768;
11912 targetm.max_anchor_offset = 32767;
11915 /* (Re)initialize MIPS target internals for new ISA. */
11916 mips_init_relocs ();
11918 if (was_mips16_p >= 0)
11919 /* Reinitialize target-dependent state. */
11920 target_reinit ();
11922 was_mips16_p = mips16_p;
11925 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
11926 function should use the MIPS16 ISA and switch modes accordingly. */
11928 static void
11929 mips_set_current_function (tree fndecl)
11931 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
11934 /* Allocate a chunk of memory for per-function machine-dependent data. */
11936 static struct machine_function *
11937 mips_init_machine_status (void)
11939 return ((struct machine_function *)
11940 ggc_alloc_cleared (sizeof (struct machine_function)));
11943 /* Return the processor associated with the given ISA level, or null
11944 if the ISA isn't valid. */
11946 static const struct mips_cpu_info *
11947 mips_cpu_info_from_isa (int isa)
11949 unsigned int i;
11951 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
11952 if (mips_cpu_info_table[i].isa == isa)
11953 return mips_cpu_info_table + i;
11955 return NULL;
11958 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
11959 with a final "000" replaced by "k". Ignore case.
11961 Note: this function is shared between GCC and GAS. */
11963 static bool
11964 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
11966 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
11967 given++, canonical++;
11969 return ((*given == 0 && *canonical == 0)
11970 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
11973 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
11974 CPU name. We've traditionally allowed a lot of variation here.
11976 Note: this function is shared between GCC and GAS. */
11978 static bool
11979 mips_matching_cpu_name_p (const char *canonical, const char *given)
11981 /* First see if the name matches exactly, or with a final "000"
11982 turned into "k". */
11983 if (mips_strict_matching_cpu_name_p (canonical, given))
11984 return true;
11986 /* If not, try comparing based on numerical designation alone.
11987 See if GIVEN is an unadorned number, or 'r' followed by a number. */
11988 if (TOLOWER (*given) == 'r')
11989 given++;
11990 if (!ISDIGIT (*given))
11991 return false;
11993 /* Skip over some well-known prefixes in the canonical name,
11994 hoping to find a number there too. */
11995 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
11996 canonical += 2;
11997 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
11998 canonical += 2;
11999 else if (TOLOWER (canonical[0]) == 'r')
12000 canonical += 1;
12002 return mips_strict_matching_cpu_name_p (canonical, given);
12005 /* Return the mips_cpu_info entry for the processor or ISA given
12006 by CPU_STRING. Return null if the string isn't recognized.
12008 A similar function exists in GAS. */
12010 static const struct mips_cpu_info *
12011 mips_parse_cpu (const char *cpu_string)
12013 unsigned int i;
12014 const char *s;
12016 /* In the past, we allowed upper-case CPU names, but it doesn't
12017 work well with the multilib machinery. */
12018 for (s = cpu_string; *s != 0; s++)
12019 if (ISUPPER (*s))
12021 warning (0, "CPU names must be lower case");
12022 break;
12025 /* 'from-abi' selects the most compatible architecture for the given
12026 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
12027 EABIs, we have to decide whether we're using the 32-bit or 64-bit
12028 version. */
12029 if (strcasecmp (cpu_string, "from-abi") == 0)
12030 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
12031 : ABI_NEEDS_64BIT_REGS ? 3
12032 : (TARGET_64BIT ? 3 : 1));
12034 /* 'default' has traditionally been a no-op. Probably not very useful. */
12035 if (strcasecmp (cpu_string, "default") == 0)
12036 return NULL;
12038 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
12039 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
12040 return mips_cpu_info_table + i;
12042 return NULL;
12045 /* Set up globals to generate code for the ISA or processor
12046 described by INFO. */
12048 static void
12049 mips_set_architecture (const struct mips_cpu_info *info)
12051 if (info != 0)
12053 mips_arch_info = info;
12054 mips_arch = info->cpu;
12055 mips_isa = info->isa;
12059 /* Likewise for tuning. */
12061 static void
12062 mips_set_tune (const struct mips_cpu_info *info)
12064 if (info != 0)
12066 mips_tune_info = info;
12067 mips_tune = info->cpu;
12071 /* Implement TARGET_HANDLE_OPTION. */
12073 static bool
12074 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
12076 switch (code)
12078 case OPT_mabi_:
12079 if (strcmp (arg, "32") == 0)
12080 mips_abi = ABI_32;
12081 else if (strcmp (arg, "o64") == 0)
12082 mips_abi = ABI_O64;
12083 else if (strcmp (arg, "n32") == 0)
12084 mips_abi = ABI_N32;
12085 else if (strcmp (arg, "64") == 0)
12086 mips_abi = ABI_64;
12087 else if (strcmp (arg, "eabi") == 0)
12088 mips_abi = ABI_EABI;
12089 else
12090 return false;
12091 return true;
12093 case OPT_march_:
12094 case OPT_mtune_:
12095 return mips_parse_cpu (arg) != 0;
12097 case OPT_mips:
12098 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
12099 return mips_isa_option_info != 0;
12101 case OPT_mno_flush_func:
12102 mips_cache_flush_func = NULL;
12103 return true;
12105 case OPT_mcode_readable_:
12106 if (strcmp (arg, "yes") == 0)
12107 mips_code_readable = CODE_READABLE_YES;
12108 else if (strcmp (arg, "pcrel") == 0)
12109 mips_code_readable = CODE_READABLE_PCREL;
12110 else if (strcmp (arg, "no") == 0)
12111 mips_code_readable = CODE_READABLE_NO;
12112 else
12113 return false;
12114 return true;
12116 default:
12117 return true;
12121 /* Implement OVERRIDE_OPTIONS. */
12123 void
12124 mips_override_options (void)
12126 int i, start, regno, mode;
12128 #ifdef SUBTARGET_OVERRIDE_OPTIONS
12129 SUBTARGET_OVERRIDE_OPTIONS;
12130 #endif
12132 /* Set the small data limit. */
12133 mips_small_data_threshold = (g_switch_set
12134 ? g_switch_value
12135 : MIPS_DEFAULT_GVALUE);
12137 /* The following code determines the architecture and register size.
12138 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
12139 The GAS and GCC code should be kept in sync as much as possible. */
12141 if (mips_arch_string != 0)
12142 mips_set_architecture (mips_parse_cpu (mips_arch_string));
12144 if (mips_isa_option_info != 0)
12146 if (mips_arch_info == 0)
12147 mips_set_architecture (mips_isa_option_info);
12148 else if (mips_arch_info->isa != mips_isa_option_info->isa)
12149 error ("%<-%s%> conflicts with the other architecture options, "
12150 "which specify a %s processor",
12151 mips_isa_option_info->name,
12152 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
12155 if (mips_arch_info == 0)
12157 #ifdef MIPS_CPU_STRING_DEFAULT
12158 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
12159 #else
12160 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
12161 #endif
12164 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
12165 error ("%<-march=%s%> is not compatible with the selected ABI",
12166 mips_arch_info->name);
12168 /* Optimize for mips_arch, unless -mtune selects a different processor. */
12169 if (mips_tune_string != 0)
12170 mips_set_tune (mips_parse_cpu (mips_tune_string));
12172 if (mips_tune_info == 0)
12173 mips_set_tune (mips_arch_info);
12175 if ((target_flags_explicit & MASK_64BIT) != 0)
12177 /* The user specified the size of the integer registers. Make sure
12178 it agrees with the ABI and ISA. */
12179 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
12180 error ("%<-mgp64%> used with a 32-bit processor");
12181 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
12182 error ("%<-mgp32%> used with a 64-bit ABI");
12183 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
12184 error ("%<-mgp64%> used with a 32-bit ABI");
12186 else
12188 /* Infer the integer register size from the ABI and processor.
12189 Restrict ourselves to 32-bit registers if that's all the
12190 processor has, or if the ABI cannot handle 64-bit registers. */
12191 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
12192 target_flags &= ~MASK_64BIT;
12193 else
12194 target_flags |= MASK_64BIT;
12197 if ((target_flags_explicit & MASK_FLOAT64) != 0)
12199 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
12200 error ("unsupported combination: %s", "-mfp64 -msingle-float");
12201 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
12202 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
12203 else if (!TARGET_64BIT && TARGET_FLOAT64)
12205 if (!ISA_HAS_MXHC1)
12206 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
12207 " the target supports the mfhc1 and mthc1 instructions");
12208 else if (mips_abi != ABI_32)
12209 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
12210 " the o32 ABI");
12213 else
12215 /* -msingle-float selects 32-bit float registers. Otherwise the
12216 float registers should be the same size as the integer ones. */
12217 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
12218 target_flags |= MASK_FLOAT64;
12219 else
12220 target_flags &= ~MASK_FLOAT64;
12223 /* End of code shared with GAS. */
12225 /* If no -mlong* option was given, infer it from the other options. */
12226 if ((target_flags_explicit & MASK_LONG64) == 0)
12228 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
12229 target_flags |= MASK_LONG64;
12230 else
12231 target_flags &= ~MASK_LONG64;
12234 if (!TARGET_OLDABI)
12235 flag_pcc_struct_return = 0;
12237 /* Decide which rtx_costs structure to use. */
12238 if (optimize_size)
12239 mips_cost = &mips_rtx_cost_optimize_size;
12240 else
12241 mips_cost = &mips_rtx_cost_data[mips_tune];
12243 /* If the user hasn't specified a branch cost, use the processor's
12244 default. */
12245 if (mips_branch_cost == 0)
12246 mips_branch_cost = mips_cost->branch_cost;
12248 /* If neither -mbranch-likely nor -mno-branch-likely was given
12249 on the command line, set MASK_BRANCHLIKELY based on the target
12250 architecture and tuning flags. Annulled delay slots are a
12251 size win, so we only consider the processor-specific tuning
12252 for !optimize_size. */
12253 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
12255 if (ISA_HAS_BRANCHLIKELY
12256 && (optimize_size
12257 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
12258 target_flags |= MASK_BRANCHLIKELY;
12259 else
12260 target_flags &= ~MASK_BRANCHLIKELY;
12262 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
12263 warning (0, "the %qs architecture does not support branch-likely"
12264 " instructions", mips_arch_info->name);
12266 /* The effect of -mabicalls isn't defined for the EABI. */
12267 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
12269 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
12270 target_flags &= ~MASK_ABICALLS;
12273 /* MIPS16 cannot generate PIC yet. */
12274 if (TARGET_MIPS16 && (flag_pic || TARGET_ABICALLS))
12276 sorry ("MIPS16 PIC");
12277 target_flags &= ~MASK_ABICALLS;
12278 flag_pic = flag_pie = flag_shlib = 0;
12281 if (TARGET_ABICALLS)
12282 /* We need to set flag_pic for executables as well as DSOs
12283 because we may reference symbols that are not defined in
12284 the final executable. (MIPS does not use things like
12285 copy relocs, for example.)
12287 Also, there is a body of code that uses __PIC__ to distinguish
12288 between -mabicalls and -mno-abicalls code. */
12289 flag_pic = 1;
12291 /* -mvr4130-align is a "speed over size" optimization: it usually produces
12292 faster code, but at the expense of more nops. Enable it at -O3 and
12293 above. */
12294 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
12295 target_flags |= MASK_VR4130_ALIGN;
12297 /* Prefer a call to memcpy over inline code when optimizing for size,
12298 though see MOVE_RATIO in mips.h. */
12299 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
12300 target_flags |= MASK_MEMCPY;
12302 /* If we have a nonzero small-data limit, check that the -mgpopt
12303 setting is consistent with the other target flags. */
12304 if (mips_small_data_threshold > 0)
12306 if (!TARGET_GPOPT)
12308 if (!TARGET_MIPS16 && !TARGET_EXPLICIT_RELOCS)
12309 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
12311 TARGET_LOCAL_SDATA = false;
12312 TARGET_EXTERN_SDATA = false;
12314 else
12316 if (TARGET_VXWORKS_RTP)
12317 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
12319 if (TARGET_ABICALLS)
12320 warning (0, "cannot use small-data accesses for %qs",
12321 "-mabicalls");
12325 #ifdef MIPS_TFMODE_FORMAT
12326 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
12327 #endif
12329 /* Make sure that the user didn't turn off paired single support when
12330 MIPS-3D support is requested. */
12331 if (TARGET_MIPS3D
12332 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
12333 && !TARGET_PAIRED_SINGLE_FLOAT)
12334 error ("%<-mips3d%> requires %<-mpaired-single%>");
12336 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
12337 if (TARGET_MIPS3D)
12338 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
12340 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
12341 and TARGET_HARD_FLOAT_ABI are both true. */
12342 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
12343 error ("%qs must be used with %qs",
12344 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
12345 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
12347 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
12348 enabled. */
12349 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
12350 warning (0, "the %qs architecture does not support paired-single"
12351 " instructions", mips_arch_info->name);
12353 /* If TARGET_DSPR2, enable MASK_DSP. */
12354 if (TARGET_DSPR2)
12355 target_flags |= MASK_DSP;
12357 mips_init_print_operand_punct ();
12359 /* Set up array to map GCC register number to debug register number.
12360 Ignore the special purpose register numbers. */
12362 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12364 mips_dbx_regno[i] = INVALID_REGNUM;
12365 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
12366 mips_dwarf_regno[i] = i;
12367 else
12368 mips_dwarf_regno[i] = INVALID_REGNUM;
12371 start = GP_DBX_FIRST - GP_REG_FIRST;
12372 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
12373 mips_dbx_regno[i] = i + start;
12375 start = FP_DBX_FIRST - FP_REG_FIRST;
12376 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
12377 mips_dbx_regno[i] = i + start;
12379 /* Accumulator debug registers use big-endian ordering. */
12380 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
12381 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
12382 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
12383 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
12384 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
12386 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
12387 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
12390 /* Set up mips_hard_regno_mode_ok. */
12391 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
12392 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
12393 mips_hard_regno_mode_ok[(int)mode][regno]
12394 = mips_hard_regno_mode_ok_p (regno, mode);
12396 /* Function to allocate machine-dependent function status. */
12397 init_machine_status = &mips_init_machine_status;
12399 /* Default to working around R4000 errata only if the processor
12400 was selected explicitly. */
12401 if ((target_flags_explicit & MASK_FIX_R4000) == 0
12402 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
12403 target_flags |= MASK_FIX_R4000;
12405 /* Default to working around R4400 errata only if the processor
12406 was selected explicitly. */
12407 if ((target_flags_explicit & MASK_FIX_R4400) == 0
12408 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
12409 target_flags |= MASK_FIX_R4400;
12411 /* Save base state of options. */
12412 mips_base_mips16 = TARGET_MIPS16;
12413 mips_base_target_flags = target_flags;
12414 mips_base_delayed_branch = flag_delayed_branch;
12415 mips_base_schedule_insns = flag_schedule_insns;
12416 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
12417 mips_base_move_loop_invariants = flag_move_loop_invariants;
12418 mips_base_align_loops = align_loops;
12419 mips_base_align_jumps = align_jumps;
12420 mips_base_align_functions = align_functions;
12422 /* Now select the ISA mode. */
12423 mips_set_mips16_mode (mips_base_mips16);
12425 /* We call dbr_schedule from within mips_reorg. */
12426 flag_delayed_branch = 0;
12429 /* Swap the register information for registers I and I + 1, which
12430 currently have the wrong endianness. Note that the registers'
12431 fixedness and call-clobberedness might have been set on the
12432 command line. */
12434 static void
12435 mips_swap_registers (unsigned int i)
12437 int tmpi;
12438 const char *tmps;
12440 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
12441 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
12443 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
12444 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
12445 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
12446 SWAP_STRING (reg_names[i], reg_names[i + 1]);
12448 #undef SWAP_STRING
12449 #undef SWAP_INT
12452 /* Implement CONDITIONAL_REGISTER_USAGE. */
12454 void
12455 mips_conditional_register_usage (void)
12457 if (!ISA_HAS_DSP)
12459 int regno;
12461 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
12462 fixed_regs[regno] = call_used_regs[regno] = 1;
12464 if (!TARGET_HARD_FLOAT)
12466 int regno;
12468 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
12469 fixed_regs[regno] = call_used_regs[regno] = 1;
12470 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
12471 fixed_regs[regno] = call_used_regs[regno] = 1;
12473 else if (! ISA_HAS_8CC)
12475 int regno;
12477 /* We only have a single condition-code register. We implement
12478 this by fixing all the condition-code registers and generating
12479 RTL that refers directly to ST_REG_FIRST. */
12480 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
12481 fixed_regs[regno] = call_used_regs[regno] = 1;
12483 /* In MIPS16 mode, we permit the $t temporary registers to be used
12484 for reload. We prohibit the unused $s registers, since they
12485 are call-saved, and saving them via a MIPS16 register would
12486 probably waste more time than just reloading the value. */
12487 if (TARGET_MIPS16)
12489 fixed_regs[18] = call_used_regs[18] = 1;
12490 fixed_regs[19] = call_used_regs[19] = 1;
12491 fixed_regs[20] = call_used_regs[20] = 1;
12492 fixed_regs[21] = call_used_regs[21] = 1;
12493 fixed_regs[22] = call_used_regs[22] = 1;
12494 fixed_regs[23] = call_used_regs[23] = 1;
12495 fixed_regs[26] = call_used_regs[26] = 1;
12496 fixed_regs[27] = call_used_regs[27] = 1;
12497 fixed_regs[30] = call_used_regs[30] = 1;
12499 /* $f20-$f23 are call-clobbered for n64. */
12500 if (mips_abi == ABI_64)
12502 int regno;
12503 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
12504 call_really_used_regs[regno] = call_used_regs[regno] = 1;
12506 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
12507 for n32. */
12508 if (mips_abi == ABI_N32)
12510 int regno;
12511 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
12512 call_really_used_regs[regno] = call_used_regs[regno] = 1;
12514 /* Make sure that double-register accumulator values are correctly
12515 ordered for the current endianness. */
12516 if (TARGET_LITTLE_ENDIAN)
12518 unsigned int regno;
12520 mips_swap_registers (MD_REG_FIRST);
12521 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
12522 mips_swap_registers (regno);
12526 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
12527 other registers for instructions for which it is possible. This
12528 encourages the compiler to use CMP in cases where an XOR would
12529 require some register shuffling. */
12531 void
12532 mips_order_regs_for_local_alloc (void)
12534 int i;
12536 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12537 reg_alloc_order[i] = i;
12539 if (TARGET_MIPS16)
12541 /* It really doesn't matter where we put register 0, since it is
12542 a fixed register anyhow. */
12543 reg_alloc_order[0] = 24;
12544 reg_alloc_order[24] = 0;
12548 /* Initialize the GCC target structure. */
12549 #undef TARGET_ASM_ALIGNED_HI_OP
12550 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
12551 #undef TARGET_ASM_ALIGNED_SI_OP
12552 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
12553 #undef TARGET_ASM_ALIGNED_DI_OP
12554 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
12556 #undef TARGET_ASM_FUNCTION_PROLOGUE
12557 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
12558 #undef TARGET_ASM_FUNCTION_EPILOGUE
12559 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
12560 #undef TARGET_ASM_SELECT_RTX_SECTION
12561 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
12562 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
12563 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
12565 #undef TARGET_SCHED_INIT
12566 #define TARGET_SCHED_INIT mips_sched_init
12567 #undef TARGET_SCHED_REORDER
12568 #define TARGET_SCHED_REORDER mips_sched_reorder
12569 #undef TARGET_SCHED_REORDER2
12570 #define TARGET_SCHED_REORDER2 mips_sched_reorder
12571 #undef TARGET_SCHED_VARIABLE_ISSUE
12572 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
12573 #undef TARGET_SCHED_ADJUST_COST
12574 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
12575 #undef TARGET_SCHED_ISSUE_RATE
12576 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
12577 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12578 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
12579 mips_multipass_dfa_lookahead
12581 #undef TARGET_DEFAULT_TARGET_FLAGS
12582 #define TARGET_DEFAULT_TARGET_FLAGS \
12583 (TARGET_DEFAULT \
12584 | TARGET_CPU_DEFAULT \
12585 | TARGET_ENDIAN_DEFAULT \
12586 | TARGET_FP_EXCEPTIONS_DEFAULT \
12587 | MASK_CHECK_ZERO_DIV \
12588 | MASK_FUSED_MADD)
12589 #undef TARGET_HANDLE_OPTION
12590 #define TARGET_HANDLE_OPTION mips_handle_option
12592 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
12593 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
12595 #undef TARGET_INSERT_ATTRIBUTES
12596 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
12597 #undef TARGET_MERGE_DECL_ATTRIBUTES
12598 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
12599 #undef TARGET_SET_CURRENT_FUNCTION
12600 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
12602 #undef TARGET_VALID_POINTER_MODE
12603 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
12604 #undef TARGET_RTX_COSTS
12605 #define TARGET_RTX_COSTS mips_rtx_costs
12606 #undef TARGET_ADDRESS_COST
12607 #define TARGET_ADDRESS_COST mips_address_cost
12609 #undef TARGET_IN_SMALL_DATA_P
12610 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
12612 #undef TARGET_MACHINE_DEPENDENT_REORG
12613 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
12615 #undef TARGET_ASM_FILE_START
12616 #define TARGET_ASM_FILE_START mips_file_start
12617 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
12618 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
12620 #undef TARGET_INIT_LIBFUNCS
12621 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
12623 #undef TARGET_BUILD_BUILTIN_VA_LIST
12624 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
12625 #undef TARGET_EXPAND_BUILTIN_VA_START
12626 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
12627 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
12628 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
12630 #undef TARGET_PROMOTE_FUNCTION_ARGS
12631 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
12632 #undef TARGET_PROMOTE_FUNCTION_RETURN
12633 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
12634 #undef TARGET_PROMOTE_PROTOTYPES
12635 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
12637 #undef TARGET_RETURN_IN_MEMORY
12638 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
12639 #undef TARGET_RETURN_IN_MSB
12640 #define TARGET_RETURN_IN_MSB mips_return_in_msb
12642 #undef TARGET_ASM_OUTPUT_MI_THUNK
12643 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
12644 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
12645 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
12647 #undef TARGET_SETUP_INCOMING_VARARGS
12648 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
12649 #undef TARGET_STRICT_ARGUMENT_NAMING
12650 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
12651 #undef TARGET_MUST_PASS_IN_STACK
12652 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
12653 #undef TARGET_PASS_BY_REFERENCE
12654 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
12655 #undef TARGET_CALLEE_COPIES
12656 #define TARGET_CALLEE_COPIES mips_callee_copies
12657 #undef TARGET_ARG_PARTIAL_BYTES
12658 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
12660 #undef TARGET_MODE_REP_EXTENDED
12661 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
12663 #undef TARGET_VECTOR_MODE_SUPPORTED_P
12664 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
12666 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12667 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
12669 #undef TARGET_INIT_BUILTINS
12670 #define TARGET_INIT_BUILTINS mips_init_builtins
12671 #undef TARGET_EXPAND_BUILTIN
12672 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
12674 #undef TARGET_HAVE_TLS
12675 #define TARGET_HAVE_TLS HAVE_AS_TLS
12677 #undef TARGET_CANNOT_FORCE_CONST_MEM
12678 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
12680 #undef TARGET_ENCODE_SECTION_INFO
12681 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
12683 #undef TARGET_ATTRIBUTE_TABLE
12684 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
12685 /* All our function attributes are related to how out-of-line copies should
12686 be compiled or called. They don't in themselves prevent inlining. */
12687 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
12688 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
12690 #undef TARGET_EXTRA_LIVE_ON_ENTRY
12691 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
12693 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
12694 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
12695 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
12696 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
12698 #undef TARGET_COMP_TYPE_ATTRIBUTES
12699 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
12701 #ifdef HAVE_AS_DTPRELWORD
12702 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
12703 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
12704 #endif
12705 #undef TARGET_DWARF_REGISTER_SPAN
12706 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
12708 struct gcc_target targetm = TARGET_INITIALIZER;
12710 #include "gt-mips.h"