| blob | ac06b1e41cff47afba3f365271813962be5a7f37 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 88, 89, 91-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
52 /* Vector mapping INSN_UIDs to luids.
53 The luids are like uids but increase monotonically always.
54 We use them to see whether a jump comes from outside a given loop. */
58 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
59 number the insn is contained in. */
63 /* 1 + largest uid of any insn. */
67 /* 1 + luid of last insn. */
71 /* Number of loops detected in current function. Used as index to the
72 next few tables. */
76 /* Indexed by loop number, contains the first and last insn of each loop. */
80 /* For each loop, gives the containing loop number, -1 if none. */
84 #ifdef HAIFA
85 /* The main output of analyze_loop_iterations is placed here */
89 /* For each loop, determines whether some of its inner loops has used
90 count register */
94 /* loop parameters for arithmetic loops. These loops have a loop variable
95 which is initialized to loop_start_value, incremented in each iteration
96 by "loop_increment". At the end of the iteration the loop variable is
97 compared to the loop_comparison_value (using loop_comparison_code). */
105 /* For each loop, keep track of its unrolling factor.
106 Potential values:
107 0: unrolled
108 1: not unrolled.
109 -1: completely unrolled
110 >0: holds the unroll exact factor. */
113 /* Indexed by loop number, contains a nonzero value if the "loop" isn't
114 really a loop (an insn outside the loop branches into it). */
118 /* Indexed by loop number, links together all LABEL_REFs which refer to
119 code labels outside the loop. Used by routines that need to know all
120 loop exits, such as final_biv_value and final_giv_value.
122 This does not include loop exits due to return instructions. This is
123 because all bivs and givs are pseudos, and hence must be dead after a
124 return, so the presense of a return does not affect any of the
125 optimizations that use this info. It is simpler to just not include return
126 instructions on this list. */
130 /* Indexed by loop number, counts the number of LABEL_REFs on
131 loop_number_exit_labels for this loop and all loops nested inside it. */
135 /* Holds the number of loop iterations. It is zero if the number could not be
136 calculated. Must be unsigned since the number of iterations can
137 be as high as 2^wordsize-1. For loops with a wider iterator, this number
138 will be zero if the number of loop iterations is too large for an
139 unsigned integer to hold. */
143 /* Nonzero if there is a subroutine call in the current loop. */
147 /* Nonzero if there is a volatile memory reference in the current
148 loop. */
152 /* Added loop_continue which is the NOTE_INSN_LOOP_CONT of the
153 current loop. A continue statement will generate a branch to
154 NEXT_INSN (loop_continue). */
158 /* Indexed by register number, contains the number of times the reg
159 is set during the loop being scanned.
160 During code motion, a negative value indicates a reg that has been
161 made a candidate; in particular -2 means that it is an candidate that
162 we know is equal to a constant and -1 means that it is an candidate
163 not known equal to a constant.
164 After code motion, regs moved have 0 (which is accurate now)
165 while the failed candidates have the original number of times set.
167 Therefore, at all times, == 0 indicates an invariant register;
168 < 0 a conditionally invariant one. */
172 /* Original value of n_times_set; same except that this value
173 is not set negative for a reg whose sets have been made candidates
174 and not set to 0 for a reg that is moved. */
178 /* Index by register number, 1 indicates that the register
179 cannot be moved or strength reduced. */
183 /* Nonzero means reg N has already been moved out of one loop.
184 This reduces the desire to move it out of another. */
188 /* Array of MEMs that are stored in this loop. If there are too many to fit
189 here, we just turn on unknown_address_altered. */
191 #define NUM_STORES 30
194 /* Index of first available slot in above array. */
197 /* Nonzero if we don't know what MEMs were changed in the current loop.
198 This happens if the loop contains a call (in which case `loop_has_call'
199 will also be set) or if we store into more than NUM_STORES MEMs. */
203 /* Count of movable (i.e. invariant) instructions discovered in the loop. */
206 /* Count of memory write instructions discovered in the loop. */
209 /* Number of loops contained within the current one, including itself. */
212 /* Bound on pseudo register number before loop optimization.
213 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
216 /* This obstack is used in product_cheap_p to allocate its rtl. It
217 may call gen_reg_rtx which, in turn, may reallocate regno_reg_rtx.
218 If we used the same obstack that it did, we would be deallocating
219 that array. */
223 /* This is where the pointer to the obstack being used for RTL is stored. */
227 #define obstack_chunk_alloc xmalloc
228 #define obstack_chunk_free free
231 \f
232 /* During the analysis of a loop, a chain of `struct movable's
233 is made to record all the movable insns found.
234 Then the entire chain can be scanned to decide which to move. */
236 struct movable
237 {
242 of any registers used within the LIBCALL. */
244 that must be moved with this one. */
247 may be adjusted when matching movables
248 that load the same value are found. */
250 including other movables that force this
251 or match this one. */
255 /* If PARTIAL is 1, GLOBAL means something different:
256 that the reg is live outside the range from where it is set
257 to the following label. */
261 In particular, moving it does not make it
262 invariant. */
264 load SRC, rather than copying INSN. */
266 first insn of a consecutive sets group. */
269 that we should avoid changing when clearing
270 the rest of the reg. */
274 };
278 /* Forward declarations. */
291 #if 0
293 #endif
310 static void record_giv PROTO((struct induction *, rtx, rtx, rtx, rtx, rtx, int, enum g_types, int, rtx *, rtx, rtx));
317 #ifdef ADDRESS_COST
319 #endif
321 #ifdef GIV_SORT_CRITERION
323 #endif
332 #ifdef HAIFA
333 /* This is extern from unroll.c */
336 /* Two main functions for implementing bct:
337 first - to be called before loop unrolling, and the second - after */
338 #ifdef HAVE_decrement_and_branch_on_count
342 /* Auxiliary function that inserts the bct pattern into the loop */
347 /* Indirect_jump_in_function is computed once per function. */
351 \f
352 /* Relative gain of eliminating various kinds of operations. */
354 #if 0
357 #endif
359 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
360 copy the value of the strength reduced giv to its original register. */
363 void
365 {
371 /* We multiply by 2 to reconcile the difference in scale between
372 these two ways of computing costs. Otherwise the cost of a copy
373 will be far less than the cost of an add. */
377 /* Free the objects we just allocated. */
380 /* Initialize the obstack used for rtl in product_cheap_p. */
382 }
383 \f
384 /* Entry point of this file. Perform loop optimization
385 on the current function. F is the first insn of the function
386 and DUMPFILE is a stream for output of a trace of actions taken
387 (or 0 if none should be output). */
389 void
391 /* f is the first instruction of a chain of insns for one function */
392 rtx f;
395 {
398 rtx last_insn;
411 /* Count the number of loops. */
415 {
418 max_loop_num++;
419 }
421 /* Don't waste time if no loops. */
425 /* Get size to use for tables indexed by uids.
426 Leave some space for labels allocated by find_and_verify_loops. */
435 /* Allocate tables for recording each loop. We set each entry, so they need
436 not be zeroed. */
444 /* This is initialized by the unrolling code, so we go ahead
445 and clear them just in case we are not performing loop
446 unrolling. */
450 #ifdef HAIFA
451 /* Allocate for BCT optimization */
465 loop_comparison_code
470 /* Find and process each loop.
471 First, find them, and record them in order of their beginnings. */
474 /* Now find all register lifetimes. This must be done after
475 find_and_verify_loops, because it might reorder the insns in the
476 function. */
479 /* This must occur after reg_scan so that registers created by gcse
480 will have entries in the register tables.
482 We could have added a call to reg_scan after gcse_main in toplev.c,
483 but moving this call to init_alias_analysis is more efficient. */
486 /* See if we went too far. */
489 /* Now reset it to the actual size we need. See above. */
492 /* Compute the mapping from uids to luids.
493 LUIDs are numbers assigned to insns, like uids,
494 except that luids increase monotonically through the code.
495 Don't assign luids to line-number NOTEs, so that the distance in luids
496 between two insns is not affected by -g. */
499 {
504 else
505 /* Give a line number note the same luid as preceding insn. */
507 }
511 /* Don't leave gaps in uid_luid for insns that have been
512 deleted. It is possible that the first or last insn
513 using some register has been deleted by cross-jumping.
514 Make sure that uid_luid for that former insn's uid
515 points to the general area where that insn used to be. */
517 {
521 }
526 /* Create a mapping from loops to BLOCK tree nodes. */
530 /* Determine if the function has indirect jump. On some systems
531 this prevents low overhead loop instructions from being used. */
534 /* Now scan the loops, last ones first, since this means inner ones are done
535 before outer ones. */
541 /* If debugging and unrolling loops, we must replicate the tree nodes
542 corresponding to the blocks inside the loop, so that the original one
543 to one mapping will remain. */
546 }
547 \f
548 /* Optimize one loop whose start is LOOP_START and end is END.
549 LOOP_START is the NOTE_INSN_LOOP_BEG and END is the matching
550 NOTE_INSN_LOOP_END. */
552 /* ??? Could also move memory writes out of loops if the destination address
553 is invariant, the source is invariant, the memory write is not volatile,
554 and if we can prove that no read inside the loop can read this address
555 before the write occurs. If there is a read of this address after the
556 write, then we can also mark the memory read as invariant. */
558 static void
563 {
566 /* 1 if we are scanning insns that could be executed zero times. */
568 /* 1 if we are scanning insns that might never be executed
569 due to a subroutine call which might exit before they are reached. */
571 /* For a rotated loop that is entered near the bottom,
572 this is the label at the top. Otherwise it is zero. */
574 /* Jump insn that enters the loop, or 0 if control drops in. */
576 /* Place in the loop where control enters. */
577 rtx scan_start;
578 /* Number of insns in the loop. */
582 rtx temp;
583 /* The SET from an insn, if it is the only SET in the insn. */
585 /* Chain describing insns movable in current loop. */
587 /* Last element in `movables' -- so we can add elements at the end. */
589 /* Ratio of extra register life span we can justify
590 for saving an instruction. More if loop doesn't call subroutines
591 since in that case saving an insn makes more difference
592 and more registers are available. */
594 /* If we have calls, contains the insn in which a register was used
595 if it was used exactly once; contains const0_rtx if it was used more
596 than once. */
598 /* Nonzero if we are scanning instructions in a sub-loop. */
605 /* Determine whether this loop starts with a jump down to a test at
606 the end. This will occur for a small number of loops with a test
607 that is too complex to duplicate in front of the loop.
609 We search for the first insn or label in the loop, skipping NOTEs.
610 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
611 (because we might have a loop executed only once that contains a
612 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
613 (in case we have a degenerate loop).
615 Note that if we mistakenly think that a loop is entered at the top
616 when, in fact, it is entered at the exit test, the only effect will be
617 slightly poorer optimization. Making the opposite error can generate
618 incorrect code. Since very few loops now start with a jump to the
619 exit test, the code here to detect that case is very conservative. */
622 p != end
628 ;
632 /* Set up variables describing this loop. */
636 /* If loop has a jump before the first label,
637 the true entry is the target of that jump.
638 Start scan from there.
639 But record in LOOP_TOP the place where the end-test jumps
640 back to so we can scan that after the end of the loop. */
642 {
645 /* Loop entry must be unconditional jump (and not a RETURN) */
648 /* Check to see whether the jump actually
649 jumps out of the loop (meaning it's no loop).
650 This case can happen for things like
651 do {..} while (0). If this label was generated previously
652 by loop, we can't tell anything about it and have to reject
653 the loop. */
657 {
660 }
661 }
663 /* If SCAN_START was an insn created by loop, we don't know its luid
664 as required by loop_reg_used_before_p. So skip such loops. (This
665 test may never be true, but it's best to play it safe.)
667 Also, skip loops where we do not start scanning at a label. This
668 test also rejects loops starting with a JUMP_INSN that failed the
669 test above. */
673 {
678 }
680 /* Count number of times each reg is set during this loop.
681 Set may_not_optimize[I] if it is not safe to move out
682 the setting of register I. If this loop has calls, set
683 reg_single_usage[I]. */
689 {
692 }
702 {
708 }
710 /* Scan through the loop finding insns that are safe to move.
711 Set n_times_set negative for the reg being set, so that
712 this reg will be considered invariant for subsequent insns.
713 We consider whether subsequent insns use the reg
714 in deciding whether it is worth actually moving.
716 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
717 and therefore it is possible that the insns we are scanning
718 would never be executed. At such times, we must make sure
719 that it is safe to execute the insn once instead of zero times.
720 When MAYBE_NEVER is 0, all insns will be executed at least once
721 so that is not a problem. */
725 {
727 /* At end of a straight-in loop, we are done.
728 At end of a loop entered at the bottom, scan the top. */
732 {
735 else
739 }
752 {
759 /* Figure out what to use as a source of this insn. If a REG_EQUIV
760 note is given or if a REG_EQUAL note with a constant operand is
761 specified, use it as the source and mark that we should move
762 this insn by calling emit_move_insn rather that duplicating the
763 insn.
765 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
766 is present. */
770 else
771 {
776 {
778 /* A libcall block can use regs that don't appear in
779 the equivalent expression. To move the libcall,
780 we must move those regs too. */
782 }
783 }
785 /* Don't try to optimize a register that was made
786 by loop-optimization for an inner loop.
787 We don't know its life-span, so we can't compute the benefit. */
789 ;
790 /* In order to move a register, we need to have one of three cases:
791 (1) it is used only in the same basic block as the set
792 (2) it is not a user variable and it is not used in the
793 exit test (this can cause the variable to be used
794 before it is set just like a user-variable).
795 (3) the set is guaranteed to be executed once the loop starts,
796 and the reg is not used until after that. */
803 ;
808 || (tem1
811 p)))
812 /* If the insn can cause a trap (such as divide by zero),
813 can't move it unless it's guaranteed to be executed
814 once loop is entered. Even a function call might
815 prevent the trap insn from being reached
816 (since it might exit!) */
819 {
823 /* A potential lossage is where we have a case where two insns
824 can be combined as long as they are both in the loop, but
825 we move one of them outside the loop. For large loops,
826 this can lose. The most common case of this is the address
827 of a function being called.
829 Therefore, if this register is marked as being used exactly
830 once if we are in a loop with calls (a "large loop"), see if
831 we can replace the usage of this register with the source
832 of this SET. If we can, delete this insn.
834 Don't do this if P has a REG_RETVAL note or if we have
835 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
845 && (! SMALL_REGISTER_CLASSES
848 /* This test is not redundant; SET_SRC (set) might be
849 a call-clobbered register and the life of REGNO
850 might span a call. */
856 {
857 /* Replace any usage in a REG_EQUAL note. Must copy the
858 new source, so that we don't get rtx sharing between the
859 SET_SOURCE and REG_NOTES of insn p. */
869 }
887 /* Set M->cond if either invariant_p or consec_sets_invariant_p
888 returned 2 (only conditionally invariant). */
899 /* Add M to the end of the chain MOVABLES. */
902 else
907 {
908 /* It is possible for the first instruction to have a
909 REG_EQUAL note but a non-invariant SET_SRC, so we must
910 remember the status of the first instruction in case
911 the last instruction doesn't have a REG_EQUAL note. */
914 /* Skip this insn, not checking REG_LIBCALL notes. */
916 /* Skip the consecutive insns, if there are any. */
918 /* Back up to the last insn of the consecutive group. */
921 /* We must now reset m->move_insn, m->is_equiv, and possibly
922 m->set_src to correspond to the effects of all the
923 insns. */
927 else
928 {
932 else
935 }
937 }
938 }
939 /* If this register is always set within a STRICT_LOW_PART
940 or set to zero, then its high bytes are constant.
941 So clear them outside the loop and within the loop
942 just load the low bytes.
943 We must check that the machine has an instruction to do so.
944 Also, if the value loaded into the register
945 depends on the same register, this cannot be done. */
955 {
958 {
972 /* If the insn may not be executed on some cycles,
973 we can't clear the whole reg; clear just high part.
974 Not even if the reg is used only within this loop.
975 Consider this:
976 while (1)
977 while (s != t) {
978 if (foo ()) x = *s;
979 use (x);
980 }
981 Clearing x before the inner loop could clobber a value
982 being saved from the last time around the outer loop.
983 However, if the reg is not used outside this loop
984 and all uses of the register are in the same
985 basic block as the store, there is no problem.
987 If this insn was made by loop, we don't know its
988 INSN_LUID and hence must make a conservative
989 assumption. */
995 || (labels_in_range_p
999 else
1008 /* Add M to the end of the chain MOVABLES. */
1011 else
1014 }
1015 }
1016 }
1017 /* Past a call insn, we get to insns which might not be executed
1018 because the call might exit. This matters for insns that trap.
1019 Call insns inside a REG_LIBCALL/REG_RETVAL block always return,
1020 so they don't count. */
1023 /* Past a label or a jump, we get to insns for which we
1024 can't count on whether or how many times they will be
1025 executed during each iteration. Therefore, we can
1026 only move out sets of trivial variables
1027 (those not used after the loop). */
1028 /* Similar code appears twice in strength_reduce. */
1030 /* If we enter the loop in the middle, and scan around to the
1031 beginning, don't set maybe_never for that. This must be an
1032 unconditional jump, otherwise the code at the top of the
1033 loop might never be executed. Unconditional jumps are
1034 followed a by barrier then loop end. */
1040 {
1041 /* At the virtual top of a converted loop, insns are again known to
1042 be executed: logically, the loop begins here even though the exit
1043 code has been duplicated. */
1047 loop_depth++;
1049 loop_depth--;
1050 }
1051 }
1053 /* If one movable subsumes another, ignore that other. */
1057 /* For each movable insn, see if the reg that it loads
1058 leads when it dies right into another conditionally movable insn.
1059 If so, record that the second insn "forces" the first one,
1060 since the second can be moved only if the first is. */
1064 /* See if there are multiple movable insns that load the same value.
1065 If there are, make all but the first point at the first one
1066 through the `match' field, and add the priorities of them
1067 all together as the priority of the first. */
1071 /* Now consider each movable insn to decide whether it is worth moving.
1072 Store 0 in n_times_set for each reg that is moved.
1074 Generally this increases code size, so do not move moveables when
1075 optimizing for code size. */
1081 /* Now candidates that still are negative are those not moved.
1082 Change n_times_set to indicate that those are not actually invariant. */
1090 }
1091 \f
1092 /* Add elements to *OUTPUT to record all the pseudo-regs
1093 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1095 void
1099 {
1107 {
1125 }
1129 {
1133 {
1142 }
1143 }
1144 }
1145 \f
1146 /* Check what regs are referred to in the libcall block ending with INSN,
1147 aside from those mentioned in the equivalent value.
1148 If there are none, return 0.
1149 If there are one or more, return an EXPR_LIST containing all of them. */
1151 static rtx
1154 {
1159 /* First, find all the regs used in the libcall block
1160 that are not mentioned as inputs to the result. */
1163 {
1168 }
1171 }
1172 \f
1173 /* Return 1 if all uses of REG
1174 are between INSN and the end of the basic block. */
1176 static int
1179 {
1181 rtx p;
1186 /* Search this basic block for the already recorded last use of the reg. */
1188 {
1190 {
1196 /* Ordinary insn: if this is the last use, we win. */
1202 /* Jump insn: if this is the last use, we win. */
1205 /* Otherwise, it's the end of the basic block, so we lose. */
1210 /* It's the end of the basic block, so we lose. */
1215 }
1216 }
1218 /* The "last use" doesn't follow the "first use"?? */
1220 }
1221 \f
1222 /* Compute the benefit of eliminating the insns in the block whose
1223 last insn is LAST. This may be a group of insns used to compute a
1224 value directly or can contain a library call. */
1226 static int
1228 rtx last;
1229 {
1230 rtx insn;
1235 {
1238 routine. */
1242 benefit++;
1243 }
1246 }
1247 \f
1248 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1250 static rtx
1252 rtx insn;
1254 {
1256 {
1257 rtx temp;
1259 /* If first insn of libcall sequence, skip to end. */
1260 /* Do this at start of loop, since INSN is guaranteed to
1261 be an insn here. */
1268 }
1271 }
1273 /* Ignore any movable whose insn falls within a libcall
1274 which is part of another movable.
1275 We make use of the fact that the movable for the libcall value
1276 was made later and so appears later on the chain. */
1278 static void
1281 {
1285 {
1286 /* Is this a movable for the value of a libcall? */
1289 {
1290 rtx insn;
1291 /* Check for earlier movables inside that range,
1292 and mark them invalid. We cannot use LUIDs here because
1293 insns created by loop.c for prior loops don't have LUIDs.
1294 Rather than reject all such insns from movables, we just
1295 explicitly check each insn in the libcall (since invariant
1296 libcalls aren't that common). */
1301 }
1302 }
1303 }
1305 /* For each movable insn, see if the reg that it loads
1306 leads when it dies right into another conditionally movable insn.
1307 If so, record that the second insn "forces" the first one,
1308 since the second can be moved only if the first is. */
1310 static void
1313 {
1316 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1318 {
1321 /* ??? Could this be a bug? What if CSE caused the
1322 register of M1 to be used after this insn?
1323 Since CSE does not update regno_last_uid,
1324 this insn M->insn might not be where it dies.
1325 But very likely this doesn't matter; what matters is
1326 that M's reg is computed from M1's reg. */
1331 /* If m->consec, m->set_src isn't valid. */
1335 /* Increase the priority of the moving the first insn
1336 since it permits the second to be moved as well. */
1338 {
1342 }
1343 }
1344 }
1345 \f
1346 /* Find invariant expressions that are equal and can be combined into
1347 one register. */
1349 static void
1353 {
1358 /* Regs that are set more than once are not allowed to match
1359 or be matched. I'm no longer sure why not. */
1360 /* Perhaps testing m->consec_sets would be more appropriate here? */
1364 {
1371 /* We want later insns to match the first one. Don't make the first
1372 one match any later ones. So start this loop at m->next. */
1375 /* A reg used outside the loop mustn't be eliminated. */
1377 /* A reg used for zero-extending mustn't be eliminated. */
1380 ||
1381 (
1382 /* Can combine regs with different modes loaded from the
1383 same constant only if the modes are the same or
1384 if both are integer modes with M wider or the same
1385 width as M1. The check for integer is redundant, but
1386 safe, since the only case of differing destination
1387 modes with equal sources is when both sources are
1388 VOIDmode, i.e., CONST_INT. */
1394 /* See if the source of M1 says it matches M. */
1398 movables))))
1401 {
1407 }
1408 }
1410 /* Now combine the regs used for zero-extension.
1411 This can be done for those not marked `global'
1412 provided their lives don't overlap. */
1416 {
1419 /* Combine all the registers for extension from mode MODE.
1420 Don't combine any that are used outside this loop. */
1424 {
1430 {
1431 /* First one: don't check for overlap, just record it. */
1434 }
1436 /* Make sure they extend to the same mode.
1437 (Almost always true.) */
1441 /* We already have one: check for overlap with those
1442 already combined together. */
1449 /* No overlap: we can combine this with the others. */
1455 overlap: ;
1456 }
1457 }
1458 }
1459 \f
1460 /* Return 1 if regs X and Y will become the same if moved. */
1462 static int
1466 {
1483 }
1485 /* Return 1 if X and Y are identical-looking rtx's.
1486 This is the Lisp function EQUAL for rtx arguments.
1488 If two registers are matching movables or a movable register and an
1489 equivalent constant, consider them equal. */
1491 static int
1495 {
1509 /* If we have a register and a constant, they may sometimes be
1510 equal. */
1513 {
1518 }
1521 {
1526 }
1528 /* Otherwise, rtx's of different codes cannot be equal. */
1532 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1533 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1538 /* These three types of rtx's can be compared nonrecursively. */
1547 /* Compare the elements. If any pair of corresponding elements
1548 fail to match, return 0 for the whole things. */
1552 {
1554 {
1566 /* Two vectors must have the same length. */
1570 /* And the corresponding elements must match. */
1587 /* These are just backpointers, so they don't matter. */
1593 /* It is believed that rtx's at this level will never
1594 contain anything but integers and other rtx's,
1595 except for within LABEL_REFs and SYMBOL_REFs. */
1598 }
1599 }
1601 }
1602 \f
1603 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1604 insns in INSNS which use thet reference. */
1606 static void
1608 rtx x;
1609 rtx insns;
1610 {
1614 rtx insn;
1617 {
1620 /* Don't record labels that refer to dispatch tables.
1621 This is not necessary, since the tablejump references the same label.
1622 And if we did record them, flow.c would make worse code. */
1627 {
1632 }
1634 }
1638 {
1644 }
1645 }
1646 \f
1647 /* Scan MOVABLES, and move the insns that deserve to be moved.
1648 If two matching movables are combined, replace one reg with the
1649 other throughout. */
1651 static void
1656 rtx loop_start;
1657 rtx end;
1659 {
1663 /* Map of pseudo-register replacements to handle combining
1664 when we move several insns that load the same value
1665 into different pseudo-registers. */
1675 {
1676 /* Describe this movable insn. */
1679 {
1700 }
1702 /* Count movables. Value used in heuristics in strength_reduce. */
1703 num_movables++;
1705 /* Ignore the insn if it's already done (it matched something else).
1706 Otherwise, see if it is now safe to move. */
1718 {
1723 /* We have an insn that is safe to move.
1724 Compute its desirability. */
1733 {
1738 }
1740 /* An insn MUST be moved if we already moved something else
1741 which is safe only if this one is moved too: that is,
1742 if already_moved[REGNO] is nonzero. */
1744 /* An insn is desirable to move if the new lifetime of the
1745 register is no more than THRESHOLD times the old lifetime.
1746 If it's not desirable, it means the loop is so big
1747 that moving won't speed things up much,
1748 and it is liable to make register usage worse. */
1750 /* It is also desirable to move if it can be moved at no
1751 extra cost because something else was already moved. */
1754 || flag_move_all_movables
1758 {
1761 rtx first;
1763 /* Now move the insns that set the reg. */
1766 {
1769 /* Find the end of this chain of matching regs.
1770 Thus, we load each reg in the chain from that one reg.
1771 And that reg is loaded with 0 directly,
1772 since it has ->match == 0. */
1778 /* Mark the moved, invariant reg as being allowed to
1779 share a hard reg with the other matching invariant. */
1783 regs_may_share
1786 regs_may_share));
1794 }
1795 /* If we are to re-generate the item being moved with a
1796 new move insn, first delete what we have and then emit
1797 the move insn before the loop. */
1799 {
1803 {
1804 /* If this is the first insn of a library call sequence,
1805 skip to the end. */
1810 /* If this is the last insn of a libcall sequence, then
1811 delete every insn in the sequence except the last.
1812 The last insn is handled in the normal manner. */
1815 {
1819 }
1824 }
1842 /* The more regs we move, the less we like moving them. */
1844 }
1845 else
1846 {
1848 {
1851 /* If first insn of libcall sequence, skip to end. */
1852 /* Do this at start of loop, since p is guaranteed to
1853 be an insn here. */
1858 /* If last insn of libcall sequence, move all
1859 insns except the last before the loop. The last
1860 insn is handled in the normal manner. */
1863 {
1871 {
1872 rtx body;
1873 rtx n;
1874 rtx next;
1881 /* Find the next insn after TEMP,
1882 not counting USE or NOTE insns. */
1890 /* If that is the call, this may be the insn
1891 that loads the function address.
1893 Extract the function address from the insn
1894 that loads it into a register.
1895 If this insn was cse'd, we get incorrect code.
1897 So emit a new move insn that copies the
1898 function address into the register that the
1899 call insn will use. flow.c will delete any
1900 redundant stores that we have created. */
1905 NULL_RTX)))
1906 {
1912 }
1913 /* We have the call insn.
1914 If it uses the register we suspect it might,
1915 load it with the correct address directly. */
1920 fn_address),
1921 fn_address_insn);
1924 {
1926 /* Because the USAGE information potentially
1927 contains objects other than hard registers
1928 we need to copy it. */
1932 }
1933 else
1941 }
1942 }
1944 {
1945 /* P sets REG to zero; but we should clear only
1946 the bits that are not covered by the mode
1947 m->savemode. */
1949 rtx sequence;
1950 rtx tem;
1953 tem = expand_binop
1966 }
1968 {
1970 /* Because the USAGE information potentially
1971 contains objects other than hard registers
1972 we need to copy it. */
1976 }
1978 {
1979 /* The SET_SRC might not be invariant, so we must
1980 use the REG_EQUAL note. */
1994 }
1995 else
1999 {
2002 /* If there is a REG_EQUAL note present whose value
2003 is not loop invariant, then delete it, since it
2004 may cause problems with later optimization passes.
2005 It is possible for cse to create such notes
2006 like this as a result of record_jump_cond. */
2011 }
2020 /* If library call, now fix the REG_NOTES that contain
2021 insn pointers, namely REG_LIBCALL on FIRST
2022 and REG_RETVAL on I1. */
2024 {
2028 }
2033 }
2035 /* The more regs we move, the less we like moving them. */
2037 }
2039 /* Any other movable that loads the same register
2040 MUST be moved. */
2043 /* This reg has been moved out of one loop. */
2046 /* The reg set here is now invariant. */
2052 /* Change the length-of-life info for the register
2053 to say it lives at least the full length of this loop.
2054 This will help guide optimizations in outer loops. */
2057 /* This is the old insn before all the moved insns.
2058 We can't use the moved insn because it is out of range
2059 in uid_luid. Only the old insns have luids. */
2064 /* Combine with this moved insn any other matching movables. */
2069 {
2070 rtx temp;
2072 /* Schedule the reg loaded by M1
2073 for replacement so that shares the reg of M.
2074 If the modes differ (only possible in restricted
2075 circumstances, make a SUBREG. */
2078 else
2083 /* Get rid of the matching insn
2084 and prevent further processing of it. */
2087 /* if library call, delete all insn except last, which
2088 is deleted below */
2090 NULL_RTX)))
2091 {
2095 }
2098 /* Any other movable that loads the same register
2099 MUST be moved. */
2102 /* The reg merged here is now invariant,
2103 if the reg it matches is invariant. */
2106 }
2107 }
2110 }
2116 }
2121 /* Go through all the instructions in the loop, making
2122 all the register substitutions scheduled in REG_MAP. */
2126 {
2130 }
2131 }
2132 \f
2133 #if 0
2134 /* Scan X and replace the address of any MEM in it with ADDR.
2135 REG is the address that MEM should have before the replacement. */
2137 static void
2140 {
2149 {
2161 /* Short cut for very common case. */
2166 /* Short cut for very common case. */
2171 /* If this MEM uses a reg other than the one we expected,
2172 something is wrong. */
2180 }
2184 {
2188 {
2192 }
2193 }
2194 }
2195 #endif
2196 \f
2197 /* Return the number of memory refs to addresses that vary
2198 in the rtx X. */
2200 static int
2202 rtx x;
2203 {
2214 {
2231 }
2236 {
2240 {
2244 }
2245 }
2247 }
2249 \f
2250 #if 0
2251 /* P is an instruction that sets a register to the result of a ZERO_EXTEND.
2252 Replace it with an instruction to load just the low bytes
2253 if the machine supports such an instruction,
2254 and insert above LOOP_START an instruction to clear the register. */
2256 static void
2259 {
2263 /* Try to change (SET (REG ...) (ZERO_EXTEND (..:B ...)))
2264 to (SET (STRICT_LOW_PART (SUBREG:B (REG...))) ...). */
2275 {
2278 /* Clear destination register before the loop. */
2280 const0_rtx),
2281 loop_start);
2283 /* Inside the loop, just load the low part. */
2285 }
2286 }
2287 #endif
2288 \f
2289 /* Scan a loop setting the variables `unknown_address_altered',
2290 `num_mem_sets', `loop_continue', loops_enclosed', `loop_has_call',
2291 and `loop_has_volatile'.
2292 Also, fill in the array `loop_store_mems'. */
2294 static void
2297 {
2312 {
2314 {
2316 {
2318 /* Count number of loops contained in this one. */
2319 loops_enclosed++;
2320 }
2322 {
2325 {
2328 }
2329 }
2331 {
2334 }
2335 }
2337 {
2341 }
2342 else
2343 {
2345 {
2350 }
2351 }
2352 }
2353 }
2354 \f
2355 /* Scan the function looking for loops. Record the start and end of each loop.
2356 Also mark as invalid loops any loops that contain a setjmp or are branched
2357 to from outside the loop. */
2359 static void
2361 rtx f;
2362 {
2368 /* If there are jumps to undefined labels,
2369 treat them as jumps out of any/all loops.
2370 This also avoids writing past end of tables when there are no loops. */
2373 /* Find boundaries of loops, mark which loops are contained within
2374 loops, and invalidate loops that have setjmp. */
2377 {
2380 {
2392 /* In this case, we must invalidate our current loop and any
2393 enclosing loop. */
2395 {
2401 }
2414 }
2416 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2417 enclosing loop, but this doesn't matter. */
2419 }
2421 /* Any loop containing a label used in an initializer must be invalidated,
2422 because it can be jumped into from anywhere. */
2425 {
2432 }
2434 /* Any loop containing a label used for an exception handler must be
2435 invalidated, because it can be jumped into from anywhere. */
2438 {
2445 }
2447 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2448 loop that it is not contained within, that loop is marked invalid.
2449 If any INSN or CALL_INSN uses a label's address, then the loop containing
2450 that label is marked invalid, because it could be jumped into from
2451 anywhere.
2453 Also look for blocks of code ending in an unconditional branch that
2454 exits the loop. If such a block is surrounded by a conditional
2455 branch around the block, move the block elsewhere (see below) and
2456 invert the jump to point to the code block. This may eliminate a
2457 label in our loop and will simplify processing by both us and a
2458 possible second cse pass. */
2462 {
2466 {
2469 {
2476 }
2477 }
2484 /* See if this is an unconditional branch outside the loop. */
2491 {
2492 rtx p;
2497 /* Go backwards until we reach the start of the loop, a label,
2498 or a JUMP_INSN. */
2505 ;
2507 /* Check for the case where we have a jump to an inner nested
2508 loop, and do not perform the optimization in that case. */
2511 {
2514 {
2519 }
2520 }
2522 /* Make sure that the target of P is within the current loop. */
2528 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2529 we have a block of code to try to move.
2531 We look backward and then forward from the target of INSN
2532 to find a BARRIER at the same loop depth as the target.
2533 If we find such a BARRIER, we make a new label for the start
2534 of the block, invert the jump in P and point it to that label,
2535 and move the block of code to the spot we found. */
2540 /* Just ignore jumps to labels that were never emitted.
2541 These always indicate compilation errors. */
2546 {
2547 rtx target
2550 rtx loc;
2564 {
2568 /* Ensure our label doesn't go away. */
2571 /* Verify that uid_loop_num is large enough and that
2572 we can invert P. */
2574 {
2577 /* If no suitable BARRIER was found, create a suitable
2578 one before TARGET. Since TARGET is a fall through
2579 path, we'll need to insert an jump around our block
2580 and a add a BARRIER before TARGET.
2582 This creates an extra unconditional jump outside
2583 the loop. However, the benefits of removing rarely
2584 executed instructions from inside the loop usually
2585 outweighs the cost of the extra unconditional jump
2586 outside the loop. */
2588 {
2589 rtx temp;
2596 }
2598 /* Include the BARRIER after INSN and copy the
2599 block after LOC. */
2603 /* All those insns are now in TARGET_LOOP_NUM. */
2608 /* The label jumped to by INSN is no longer a loop exit.
2609 Unless INSN does not have a label (e.g., it is a
2610 RETURN insn), search loop_number_exit_labels to find
2611 its label_ref, and remove it. Also turn off
2612 LABEL_OUTSIDE_LOOP_P bit. */
2614 {
2621 {
2625 else
2629 }
2636 /* If we didn't find it, then something is wrong. */
2639 }
2641 /* P is now a jump outside the loop, so it must be put
2642 in loop_number_exit_labels, and marked as such.
2643 The easiest way to do this is to just call
2644 mark_loop_jump again for P. */
2647 /* If INSN now jumps to the insn after it,
2648 delete INSN. */
2653 }
2655 /* Continue the loop after where the conditional
2656 branch used to jump, since the only branch insn
2657 in the block (if it still remains) is an inter-loop
2658 branch and hence needs no processing. */
2664 /* This loop will be continued with NEXT_INSN (insn). */
2666 }
2667 }
2668 }
2669 }
2670 }
2672 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2673 loops it is contained in, mark the target loop invalid.
2675 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2677 static void
2679 rtx x;
2681 {
2687 {
2699 /* There could be a label reference in here. */
2718 /* Link together all labels that branch outside the loop. This
2719 is used by final_[bg]iv_value and the loop unrolling code. Also
2720 mark this LABEL_REF so we know that this branch should predict
2721 false. */
2723 /* A check to make sure the label is not in an inner nested loop,
2724 since this does not count as a loop exit. */
2726 {
2731 }
2732 else
2736 {
2745 }
2747 /* If this is inside a loop, but not in the current loop or one enclosed
2748 by it, it invalidates at least one loop. */
2753 /* We must invalidate every nested loop containing the target of this
2754 label, except those that also contain the jump insn. */
2757 {
2758 /* Stop when we reach a loop that also contains the jump insn. */
2764 /* If we get here, we know we need to invalidate a loop. */
2771 }
2775 /* If this is not setting pc, ignore. */
2797 /* Treat anything else (such as a symbol_ref)
2798 as a branch out of this loop, but not into any loop. */
2801 {
2802 #ifdef HAIFA
2812 }
2814 }
2815 }
2816 \f
2817 /* Return nonzero if there is a label in the range from
2818 insn INSN to and including the insn whose luid is END
2819 INSN must have an assigned luid (i.e., it must not have
2820 been previously created by loop.c). */
2822 static int
2824 rtx insn;
2826 {
2828 {
2832 }
2835 }
2837 /* Record that a memory reference X is being set. */
2839 static void
2841 rtx x;
2842 rtx y ATTRIBUTE_UNUSED;
2843 {
2849 /* Count number of memory writes.
2850 This affects heuristics in strength_reduce. */
2851 num_mem_sets++;
2853 /* BLKmode MEM means all memory is clobbered. */
2863 {
2864 /* We are storing at the same address as previously noted. Save the
2865 wider reference. */
2870 }
2877 }
2878 \f
2879 /* Return nonzero if the rtx X is invariant over the current loop.
2881 The value is 2 if we refer to something only conditionally invariant.
2883 If `unknown_address_altered' is nonzero, no memory ref is invariant.
2884 Otherwise, a memory ref is invariant if it does not conflict with
2885 anything stored in `loop_store_mems'. */
2887 int
2890 {
2900 {
2908 /* A LABEL_REF is normally invariant, however, if we are unrolling
2909 loops, and this label is inside the loop, then it isn't invariant.
2910 This is because each unrolled copy of the loop body will have
2911 a copy of this label. If this was invariant, then an insn loading
2912 the address of this label into a register might get moved outside
2913 the loop, and then each loop body would end up using the same label.
2915 We don't know the loop bounds here though, so just fail for all
2916 labels. */
2919 else
2928 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
2929 since the reg might be set by initialization within the loop. */
2946 /* Volatile memory references must be rejected. Do this before
2947 checking for read-only items, so that volatile read-only items
2948 will be rejected also. */
2952 /* Read-only items (such as constants in a constant pool) are
2953 invariant if their address is. */
2957 /* If we filled the table (or had a subroutine call), any location
2958 in memory could have been clobbered. */
2962 /* See if there is any dependence between a store and this load. */
2967 /* It's not invalidated by a store in memory
2968 but we must still verify the address is invariant. */
2972 /* Don't mess with insns declared volatile. */
2979 }
2983 {
2985 {
2991 }
2993 {
2996 {
3002 }
3004 }
3005 }
3008 }
3010 \f
3011 /* Return nonzero if all the insns in the loop that set REG
3012 are INSN and the immediately following insns,
3013 and if each of those insns sets REG in an invariant way
3014 (not counting uses of REG in them).
3016 The value is 2 if some of these insns are only conditionally invariant.
3018 We assume that INSN itself is the first set of REG
3019 and that its source is invariant. */
3021 static int
3025 {
3028 rtx temp;
3029 /* Number of sets we have to insist on finding after INSN. */
3035 /* If N_SETS hit the limit, we can't rely on its value. */
3042 {
3044 rtx set;
3049 /* If library call, skip to end of it. */
3058 {
3063 {
3064 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3065 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3066 notes are OK. */
3072 }
3073 }
3075 count--;
3077 {
3080 }
3081 }
3084 /* If invariant_p ever returned 2, we return 2. */
3086 }
3088 #if 0
3089 /* I don't think this condition is sufficient to allow INSN
3090 to be moved, so we no longer test it. */
3092 /* Return 1 if all insns in the basic block of INSN and following INSN
3093 that set REG are invariant according to TABLE. */
3095 static int
3099 {
3104 {
3113 {
3116 }
3117 }
3118 }
3120 \f
3121 /* Look at all uses (not sets) of registers in X. For each, if it is
3122 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3123 a different insn, set USAGE[REGNO] to const0_rtx. */
3125 static void
3127 rtx insn;
3128 rtx x;
3130 {
3141 {
3142 /* Don't count SET_DEST if it is a REG; otherwise count things
3143 in SET_DEST because if a register is partially modified, it won't
3144 show up as a potential movable so we don't care how USAGE is set
3145 for it. */
3149 }
3150 else
3152 {
3158 }
3159 }
3160 \f
3161 /* Increment N_TIMES_SET at the index of each register
3162 that is modified by an insn between FROM and TO.
3163 If the value of an element of N_TIMES_SET becomes 127 or more,
3164 stop incrementing it, to avoid overflow.
3166 Store in SINGLE_USAGE[I] the single insn in which register I is
3167 used, if it is only used once. Otherwise, it is set to 0 (for no
3168 uses) or const0_rtx for more than one use. This parameter may be zero,
3169 in which case this processing is not done.
3171 Store in *COUNT_PTR the number of actual instruction
3172 in the loop. We use this to decide what is worth moving out. */
3174 /* last_set[n] is nonzero iff reg n has been set in the current basic block.
3175 In that case, it is the insn that last set reg n. */
3177 static void
3184 {
3192 {
3194 {
3197 /* If requested, record registers that have exactly one use. */
3199 {
3202 /* Include uses in REG_EQUAL notes. */
3205 }
3209 /* Don't move a reg that has an explicit clobber.
3210 We might do so sometimes, but it's not worth the pain. */
3215 {
3223 {
3225 /* If this is the first setting of this reg
3226 in current basic block, and it was set before,
3227 it must be set in two basic blocks, so it cannot
3228 be moved out of the loop. */
3231 /* If this is not first setting in current basic block,
3232 see if reg was used in between previous one and this.
3233 If so, neither one can be moved. */
3240 }
3241 }
3243 {
3246 {
3249 /* Don't move a reg that has an explicit clobber.
3250 It's not worth the pain to try to do it correctly. */
3254 {
3262 {
3272 }
3273 }
3274 }
3275 }
3276 }
3280 }
3282 }
3283 \f
3284 /* Given a loop that is bounded by LOOP_START and LOOP_END
3285 and that is entered at SCAN_START,
3286 return 1 if the register set in SET contained in insn INSN is used by
3287 any insn that precedes INSN in cyclic order starting
3288 from the loop entry point.
3290 We don't want to use INSN_LUID here because if we restrict INSN to those
3291 that have a valid INSN_LUID, it means we cannot move an invariant out
3292 from an inner loop past two loops. */
3294 static int
3297 {
3299 rtx p;
3301 /* Scan forward checking for register usage. If we hit INSN, we
3302 are done. Otherwise, if we hit LOOP_END, wrap around to LOOP_START. */
3304 {
3311 }
3314 }
3315 \f
3316 /* A "basic induction variable" or biv is a pseudo reg that is set
3317 (within this loop) only by incrementing or decrementing it. */
3318 /* A "general induction variable" or giv is a pseudo reg whose
3319 value is a linear function of a biv. */
3321 /* Bivs are recognized by `basic_induction_var';
3322 Givs by `general_induct_var'. */
3324 /* Indexed by register number, indicates whether or not register is an
3325 induction variable, and if so what type. */
3329 /* Indexed by register number, contains pointer to `struct induction'
3330 if register is an induction variable. This holds general info for
3331 all induction variables. */
3335 /* Indexed by register number, contains pointer to `struct iv_class'
3336 if register is a basic induction variable. This holds info describing
3337 the class (a related group) of induction variables that the biv belongs
3338 to. */
3342 /* The head of a list which links together (via the next field)
3343 every iv class for the current loop. */
3347 /* Communication with routines called via `note_stores'. */
3351 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
3355 /* ??? Unfinished optimizations, and possible future optimizations,
3356 for the strength reduction code. */
3358 /* ??? There is one more optimization you might be interested in doing: to
3359 allocate pseudo registers for frequently-accessed memory locations.
3360 If the same memory location is referenced each time around, it might
3361 be possible to copy it into a register before and out after.
3362 This is especially useful when the memory location is a variable which
3363 is in a stack slot because somewhere its address is taken. If the
3364 loop doesn't contain a function call and the variable isn't volatile,
3365 it is safe to keep the value in a register for the duration of the
3366 loop. One tricky thing is that the copying of the value back from the
3367 register has to be done on all exits from the loop. You need to check that
3368 all the exits from the loop go to the same place. */
3370 /* ??? The interaction of biv elimination, and recognition of 'constant'
3371 bivs, may cause problems. */
3373 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
3374 performance problems.
3376 Perhaps don't eliminate things that can be combined with an addressing
3377 mode. Find all givs that have the same biv, mult_val, and add_val;
3378 then for each giv, check to see if its only use dies in a following
3379 memory address. If so, generate a new memory address and check to see
3380 if it is valid. If it is valid, then store the modified memory address,
3381 otherwise, mark the giv as not done so that it will get its own iv. */
3383 /* ??? Could try to optimize branches when it is known that a biv is always
3384 positive. */
3386 /* ??? When replace a biv in a compare insn, we should replace with closest
3387 giv so that an optimized branch can still be recognized by the combiner,
3388 e.g. the VAX acb insn. */
3390 /* ??? Many of the checks involving uid_luid could be simplified if regscan
3391 was rerun in loop_optimize whenever a register was added or moved.
3392 Also, some of the optimizations could be a little less conservative. */
3393 \f
3394 /* Perform strength reduction and induction variable elimination. */
3396 /* Pseudo registers created during this function will be beyond the last
3397 valid index in several tables including n_times_set and regno_last_uid.
3398 This does not cause a problem here, because the added registers cannot be
3399 givs outside of their loop, and hence will never be reconsidered.
3400 But scan_loop must check regnos to make sure they are in bounds. */
3402 static void
3405 rtx scan_start;
3406 rtx end;
3407 rtx loop_top;
3409 rtx loop_start;
3410 rtx loop_end;
3412 {
3413 rtx p;
3414 rtx set;
3415 rtx inc_val;
3416 rtx mult_val;
3417 rtx dest_reg;
3418 /* This is 1 if current insn is not executed at least once for every loop
3419 iteration. */
3421 /* This is 1 if current insn may be executed more than once for every
3422 loop iteration. */
3424 /* Temporary list pointers for traversing loop_iv_list. */
3426 /* Ratio of extra register life span we can justify
3427 for saving an instruction. More if loop doesn't call subroutines
3428 since in that case saving an insn makes more difference
3429 and more registers are available. */
3430 /* ??? could set this to last value of threshold in move_movables */
3432 /* Map of pseudo-register replacements. */
3435 rtx test;
3436 rtx end_insert_before;
3454 /* Save insn immediately after the loop_end. Insns inserted after loop_end
3455 must be put before this insn, so that they will appear in the right
3456 order (i.e. loop order).
3458 If loop_end is the end of the current function, then emit a
3459 NOTE_INSN_DELETED after loop_end and set end_insert_before to the
3460 dummy note insn. */
3463 else
3466 /* Scan through loop to find all possible bivs. */
3470 {
3472 /* At end of a straight-in loop, we are done.
3473 At end of a loop entered at the bottom, scan the top. */
3477 {
3480 else
3484 }
3489 {
3494 {
3497 {
3498 /* It is a possible basic induction variable.
3499 Create and initialize an induction structure for it. */
3507 }
3510 }
3511 }
3513 /* Past CODE_LABEL, we get to insns that may be executed multiple
3514 times. The only way we can be sure that they can't is if every
3515 jump insn between here and the end of the loop either
3516 returns, exits the loop, is a forward jump, or is a jump
3517 to the loop start. */
3520 {
3526 {
3531 {
3534 else
3538 }
3549 {
3552 }
3553 }
3554 }
3556 /* Past a jump, we get to insns for which we can't count
3557 on whether they will be executed during each iteration. */
3558 /* This code appears twice in strength_reduce. There is also similar
3559 code in scan_loop. */
3561 /* If we enter the loop in the middle, and scan around to the
3562 beginning, don't set not_every_iteration for that.
3563 This can be any kind of jump, since we want to know if insns
3564 will be executed if the loop is executed. */
3568 {
3571 /* If this is a jump outside the loop, then it also doesn't
3572 matter. Check to see if the target of this branch is on the
3573 loop_number_exits_labels list. */
3576 label;
3583 }
3586 {
3587 /* At the virtual top of a converted loop, insns are again known to
3588 be executed each iteration: logically, the loop begins here
3589 even though the exit code has been duplicated. */
3593 loop_depth++;
3595 loop_depth--;
3596 }
3598 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3599 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3600 or not an insn is known to be executed each iteration of the
3601 loop, whether or not any iterations are known to occur.
3603 Therefore, if we have just passed a label and have no more labels
3604 between here and the test insn of the loop, we know these insns
3605 will be executed each iteration. */
3610 }
3612 /* Scan loop_iv_list to remove all regs that proved not to be bivs.
3613 Make a sanity check against n_times_set. */
3615 {
3617 /* Above happens if register modified by subreg, etc. */
3618 /* Make sure it is not recognized as a basic induction var: */
3620 /* If never incremented, it is invariant that we decided not to
3621 move. So leave it alone. */
3623 {
3634 }
3635 else
3636 {
3641 }
3642 }
3644 /* Exit if there are no bivs. */
3646 {
3647 /* Can still unroll the loop anyways, but indicate that there is no
3648 strength reduction info available. */
3653 }
3655 /* Find initial value for each biv by searching backwards from loop_start,
3656 halting at first label. Also record any test condition. */
3660 {
3670 /* Record any test of a biv that branches around the loop if no store
3671 between it and the start of loop. We only care about tests with
3672 constants and registers and only certain of those. */
3682 {
3683 /* If an NE test, we have an initial value! */
3685 {
3689 }
3690 else
3692 }
3693 }
3695 /* Look at the each biv and see if we can say anything better about its
3696 initial value from any initializing insns set up above. (This is done
3697 in two passes to avoid missing SETs in a PARALLEL.) */
3699 {
3700 rtx src;
3701 rtx note;
3706 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
3707 is a constant, use the value of that. */
3713 else
3724 {
3728 {
3730 {
3733 }
3734 else
3735 {
3738 }
3739 }
3740 }
3741 else
3742 {
3743 /* Biv initial value is not simple move,
3744 so let it keep initial value of "itself". */
3748 }
3749 }
3751 /* Search the loop for general induction variables. */
3753 /* A register is a giv if: it is only set once, it is a function of a
3754 biv and a constant (or invariant), and it is not a biv. */
3760 {
3762 /* At end of a straight-in loop, we are done.
3763 At end of a loop entered at the bottom, scan the top. */
3767 {
3770 else
3774 }
3776 /* Look for a general induction variable in a register. */
3781 {
3782 rtx src_reg;
3783 rtx add_val;
3784 rtx mult_val;
3796 /* Equivalent expression is a giv. */
3801 /* Don't try to handle any regs made by loop optimization.
3802 We have nothing on them in regno_first_uid, etc. */
3804 /* Don't recognize a BASIC_INDUCT_VAR here. */
3806 /* This must be the only place where the register is set. */
3808 /* or all sets must be consecutive and make a giv. */
3812 {
3816 rtx temp;
3818 /* If this is a library call, increase benefit. */
3822 /* Skip the consecutive insns, if there are any. */
3825 {
3826 /* If first insn of libcall sequence, skip to end.
3827 Do this at start of loop, since INSN is guaranteed to
3828 be an insn here. */
3835 }
3839 loop_end);
3841 }
3842 }
3844 #ifndef DONT_REDUCE_ADDR
3845 /* Look for givs which are memory addresses. */
3846 /* This resulted in worse code on a VAX 8600. I wonder if it
3847 still does. */
3850 loop_end);
3851 #endif
3853 /* Update the status of whether giv can derive other givs. This can
3854 change when we pass a label or an insn that updates a biv. */
3859 /* Past a jump, we get to insns for which we can't count
3860 on whether they will be executed during each iteration. */
3861 /* This code appears twice in strength_reduce. There is also similar
3862 code in scan_loop. */
3864 /* If we enter the loop in the middle, and scan around to the
3865 beginning, don't set not_every_iteration for that.
3866 This can be any kind of jump, since we want to know if insns
3867 will be executed if the loop is executed. */
3871 {
3874 /* If this is a jump outside the loop, then it also doesn't
3875 matter. Check to see if the target of this branch is on the
3876 loop_number_exits_labels list. */
3879 label;
3886 }
3889 {
3890 /* At the virtual top of a converted loop, insns are again known to
3891 be executed each iteration: logically, the loop begins here
3892 even though the exit code has been duplicated. */
3896 loop_depth++;
3898 loop_depth--;
3899 }
3901 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3902 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3903 or not an insn is known to be executed each iteration of the
3904 loop, whether or not any iterations are known to occur.
3906 Therefore, if we have just passed a label and have no more labels
3907 between here and the test insn of the loop, we know these insns
3908 will be executed each iteration. */
3913 }
3915 /* Try to calculate and save the number of loop iterations. This is
3916 set to zero if the actual number can not be calculated. This must
3917 be called after all giv's have been identified, since otherwise it may
3918 fail if the iteration variable is a giv. */
3922 /* Now for each giv for which we still don't know whether or not it is
3923 replaceable, check to see if it is replaceable because its final value
3924 can be calculated. This must be done after loop_iterations is called,
3925 so that final_giv_value will work correctly. */
3928 {
3934 }
3936 /* Try to prove that the loop counter variable (if any) is always
3937 nonnegative; if so, record that fact with a REG_NONNEG note
3938 so that "decrement and branch until zero" insn can be used. */
3941 #ifdef HAIFA
3942 /* record loop-variables relevant for BCT optimization before unrolling
3943 the loop. Unrolling may update part of this information, and the
3944 correct data will be used for generating the BCT. */
3945 #ifdef HAVE_decrement_and_branch_on_count
3948 #endif
3951 /* Create reg_map to hold substitutions for replaceable giv regs. */
3955 /* Examine each iv class for feasibility of strength reduction/induction
3956 variable elimination. */
3959 {
3965 /* Test whether it will be possible to eliminate this biv
3966 provided all givs are reduced. This is possible if either
3967 the reg is not used outside the loop, or we can compute
3968 what its final value will be.
3970 For architectures with a decrement_and_branch_until_zero insn,
3971 don't do this if we put a REG_NONNEG note on the endtest for
3972 this biv. */
3974 /* Compare against bl->init_insn rather than loop_start.
3975 We aren't concerned with any uses of the biv between
3976 init_insn and loop_start since these won't be affected
3977 by the value of the biv elsewhere in the function, so
3978 long as init_insn doesn't use the biv itself.
3979 March 14, 1989 -- self@bayes.arc.nasa.gov */
3985 #ifdef HAVE_decrement_and_branch_until_zero
3987 #endif
3990 #ifdef HAVE_decrement_and_branch_until_zero
3992 #endif
3993 ))
3996 else
3997 {
3999 {
4007 }
4008 }
4010 /* Combine all giv's for this iv_class. */
4013 /* This will be true at the end, if all givs which depend on this
4014 biv have been strength reduced.
4015 We can't (currently) eliminate the biv unless this is so. */
4018 /* Check each giv in this class to see if we will benefit by reducing
4019 it. Skip giv's combined with others. */
4021 {
4029 /* Reduce benefit if not replaceable, since we will insert
4030 a move-insn to replace the insn that calculates this giv.
4031 Don't do this unless the giv is a user variable, since it
4032 will often be marked non-replaceable because of the duplication
4033 of the exit code outside the loop. In such a case, the copies
4034 we insert are dead and will be deleted. So they don't have
4035 a cost. Similar situations exist. */
4036 /* ??? The new final_[bg]iv_value code does a much better job
4037 of finding replaceable giv's, and hence this code may no longer
4038 be necessary. */
4043 /* Decrease the benefit to count the add-insns that we will
4044 insert to increment the reduced reg for the giv. */
4047 /* Decide whether to strength-reduce this giv or to leave the code
4048 unchanged (recompute it from the biv each time it is used).
4049 This decision can be made independently for each giv. */
4051 #ifdef AUTO_INC_DEC
4052 /* Attempt to guess whether autoincrement will handle some of the
4053 new add insns; if so, increase BENEFIT (undo the subtraction of
4054 add_cost that was done above). */
4057 {
4058 #if defined (HAVE_POST_INCREMENT) || defined (HAVE_PRE_INCREMENT)
4061 #endif
4062 #if defined (HAVE_POST_DECREMENT) || defined (HAVE_PRE_DECREMENT)
4065 #endif
4066 }
4067 #endif
4069 /* If an insn is not to be strength reduced, then set its ignore
4070 flag, and clear all_reduced. */
4072 /* A giv that depends on a reversed biv must be reduced if it is
4073 used after the loop exit, otherwise, it would have the wrong
4074 value after the loop exit. To make it simple, just reduce all
4075 of such giv's whether or not we know they are used after the loop
4076 exit. */
4080 {
4088 }
4089 else
4090 {
4091 /* Check that we can increment the reduced giv without a
4092 multiply insn. If not, reject it. */
4097 {
4105 }
4106 }
4107 }
4109 /* Reduce each giv that we decided to reduce. */
4112 {
4115 {
4120 #ifdef AUTO_INC_DEC
4121 /* If the target has auto-increment addressing modes, and
4122 this is an address giv, then try to put the increment
4123 immediately after its use, so that flow can create an
4124 auto-increment addressing mode. */
4127 /* We don't handle reversed biv's because bl->biv->insn
4128 does not have a valid INSN_LUID. */
4132 {
4133 /* If other giv's have been combined with this one, then
4134 this will work only if all uses of the other giv's occur
4135 before this giv's insn. This is difficult to check.
4137 We simplify this by looking for the common case where
4138 there is one DEST_REG giv, and this giv's insn is the
4139 last use of the dest_reg of that DEST_REG giv. If the
4140 increment occurs after the address giv, then we can
4141 perform the optimization. (Otherwise, the increment
4142 would have to go before other_giv, and we would not be
4143 able to combine it with the address giv to get an
4144 auto-inc address.) */
4146 {
4151 {
4154 else
4156 }
4163 }
4164 /* Check for case where increment is before the address
4165 giv. Do this test in "loop order". */
4174 else
4177 #ifdef HAVE_cc0
4178 {
4179 rtx prev;
4181 /* We can't put an insn immediately after one setting
4182 cc0, or immediately before one using cc0. */
4189 }
4190 #endif
4194 }
4195 #endif
4197 /* For each place where the biv is incremented, add an insn
4198 to increment the new, reduced reg for the giv. */
4200 {
4201 rtx insert_before;
4207 else
4214 /* A multiply is acceptable here
4215 since this is presumed to be seldom executed. */
4218 }
4220 /* Add code at loop start to initialize giv's reduced reg. */
4224 }
4225 }
4227 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
4228 as not reduced.
4230 For each giv register that can be reduced now: if replaceable,
4231 substitute reduced reg wherever the old giv occurs;
4232 else add new move insn "giv_reg = reduced_reg".
4234 Also check for givs whose first use is their definition and whose
4235 last use is the definition of another giv. If so, it is likely
4236 dead and should not be used to eliminate a biv. */
4238 {
4247 {
4253 }
4255 /* Update expression if this was combined, in case other giv was
4256 replaced. */
4262 /* Store reduced reg as the address in the memref where we found
4263 this giv. */
4266 {
4269 #if 0
4270 /* I can no longer duplicate the original problem. Perhaps
4271 this is unnecessary now? */
4273 /* Replaceable; it isn't strictly necessary to delete the old
4274 insn and emit a new one, because v->dest_reg is now dead.
4276 However, especially when unrolling loops, the special
4277 handling for (set REG0 REG1) in the second cse pass may
4278 make v->dest_reg live again. To avoid this problem, emit
4279 an insn to set the original giv reg from the reduced giv.
4280 We can not delete the original insn, since it may be part
4281 of a LIBCALL, and the code in flow that eliminates dead
4282 libcalls will fail if it is deleted. */
4285 #endif
4286 }
4287 else
4288 {
4289 /* Not replaceable; emit an insn to set the original giv reg from
4290 the reduced giv, same as above. */
4293 }
4295 /* When a loop is reversed, givs which depend on the reversed
4296 biv, and which are live outside the loop, must be set to their
4297 correct final value. This insn is only needed if the giv is
4298 not replaceable. The correct final value is the same as the
4299 value that the giv starts the reversed loop with. */
4304 {
4305 rtx insert_before;
4307 /* If the loop has multiple exits, emit the insn before the
4308 loop to ensure that it will always be executed no matter
4309 how the loop exits. Otherwise, emit the insn after the loop,
4310 since this is slightly more efficient. */
4313 else
4316 insert_before);
4318 #if 0
4319 /* If the insn to set the final value of the giv was emitted
4320 before the loop, then we must delete the insn inside the loop
4321 that sets it. If this is a LIBCALL, then we must delete
4322 every insn in the libcall. Note, however, that
4323 final_giv_value will only succeed when there are multiple
4324 exits if the giv is dead at each exit, hence it does not
4325 matter that the original insn remains because it is dead
4326 anyways. */
4327 /* Delete the insn inside the loop that sets the giv since
4328 the giv is now set before (or after) the loop. */
4330 #endif
4331 }
4334 {
4339 }
4340 }
4342 /* All the givs based on the biv bl have been reduced if they
4343 merit it. */
4345 /* For each giv not marked as maybe dead that has been combined with a
4346 second giv, clear any "maybe dead" mark on that second giv.
4347 v->new_reg will either be or refer to the register of the giv it
4348 combined with.
4350 Doing this clearing avoids problems in biv elimination where a
4351 giv's new_reg is a complex value that can't be put in the insn but
4352 the giv combined with (with a reg as new_reg) is marked maybe_dead.
4353 Since the register will be used in either case, we'd prefer it be
4354 used from the simpler giv. */
4360 /* Try to eliminate the biv, if it is a candidate.
4361 This won't work if ! all_reduced,
4362 since the givs we planned to use might not have been reduced.
4364 We have to be careful that we didn't initially think we could eliminate
4365 this biv because of a giv that we now think may be dead and shouldn't
4366 be used as a biv replacement.
4368 Also, there is the possibility that we may have a giv that looks
4369 like it can be used to eliminate a biv, but the resulting insn
4370 isn't valid. This can happen, for example, on the 88k, where a
4371 JUMP_INSN can compare a register only with zero. Attempts to
4372 replace it with a compare with a constant will fail.
4374 Note that in cases where this call fails, we may have replaced some
4375 of the occurrences of the biv with a giv, but no harm was done in
4376 doing so in the rare cases where it can occur. */
4382 {
4383 /* ?? If we created a new test to bypass the loop entirely,
4384 or otherwise drop straight in, based on this test, then
4385 we might want to rewrite it also. This way some later
4386 pass has more hope of removing the initialization of this
4387 biv entirely. */
4389 /* If final_value != 0, then the biv may be used after loop end
4390 and we must emit an insn to set it just in case.
4392 Reversed bivs already have an insn after the loop setting their
4393 value, so we don't need another one. We can't calculate the
4394 proper final value for such a biv here anyways. */
4396 {
4397 rtx insert_before;
4399 /* If the loop has multiple exits, emit the insn before the
4400 loop to ensure that it will always be executed no matter
4401 how the loop exits. Otherwise, emit the insn after the
4402 loop, since this is slightly more efficient. */
4405 else
4409 end_insert_before);
4410 }
4412 #if 0
4413 /* Delete all of the instructions inside the loop which set
4414 the biv, as they are all dead. If is safe to delete them,
4415 because an insn setting a biv will never be part of a libcall. */
4416 /* However, deleting them will invalidate the regno_last_uid info,
4417 so keeping them around is more convenient. Final_biv_value
4418 will only succeed when there are multiple exits if the biv
4419 is dead at each exit, hence it does not matter that the original
4420 insn remains, because it is dead anyways. */
4423 #endif
4428 }
4429 }
4431 /* Go through all the instructions in the loop, making all the
4432 register substitutions scheduled in REG_MAP. */
4437 {
4441 }
4443 /* Unroll loops from within strength reduction so that we can use the
4444 induction variable information that strength_reduce has already
4445 collected. */
4450 #ifdef HAIFA
4451 /* instrument the loop with bct insn */
4452 #ifdef HAVE_decrement_and_branch_on_count
4455 #endif
4460 }
4461 \f
4462 /* Return 1 if X is a valid source for an initial value (or as value being
4463 compared against in an initial test).
4465 X must be either a register or constant and must not be clobbered between
4466 the current insn and the start of the loop.
4468 INSN is the insn containing X. */
4470 static int
4472 rtx x;
4473 rtx insn;
4475 rtx loop_start;
4476 {
4480 /* Only consider pseudos we know about initialized in insns whose luids
4481 we know. */
4486 /* Don't use call-clobbered registers across a call which clobbers it. On
4487 some machines, don't use any hard registers at all. */
4489 && (SMALL_REGISTER_CLASSES
4493 /* Don't use registers that have been clobbered before the start of the
4494 loop. */
4499 }
4500 \f
4501 /* Scan X for memory refs and check each memory address
4502 as a possible giv. INSN is the insn whose pattern X comes from.
4503 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
4504 every loop iteration. */
4506 static void
4508 rtx x;
4509 rtx insn;
4512 {
4522 {
4538 {
4539 rtx src_reg;
4540 rtx add_val;
4541 rtx mult_val;
4547 /* Don't make a DEST_ADDR giv with mult_val == 1 && add_val == 0.
4548 Such a giv isn't useful. */
4550 {
4551 /* Found one; record it. */
4560 }
4561 }
4566 }
4568 /* Recursively scan the subexpressions for other mem refs. */
4574 loop_end);
4579 }
4580 \f
4581 /* Fill in the data about one biv update.
4582 V is the `struct induction' in which we record the biv. (It is
4583 allocated by the caller, with alloca.)
4584 INSN is the insn that sets it.
4585 DEST_REG is the biv's reg.
4587 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
4588 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
4589 being set to INC_VAL.
4591 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
4592 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
4593 can be executed more than once per iteration. If MAYBE_MULTIPLE
4594 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
4595 executed exactly once per iteration. */
4597 static void
4601 rtx insn;
4602 rtx dest_reg;
4603 rtx inc_val;
4604 rtx mult_val;
4607 {
4620 /* Add this to the reg's iv_class, creating a class
4621 if this is the first incrementation of the reg. */
4625 {
4626 /* Create and initialize new iv_class. */
4636 /* Set initial value to the reg itself. */
4638 /* We haven't seen the initializing insn yet */
4648 /* Add this class to loop_iv_list. */
4652 /* Put it in the array of biv register classes. */
4654 }
4656 /* Update IV_CLASS entry for this biv. */
4664 {
4669 {
4673 }
4674 else
4675 {
4679 }
4680 }
4681 }
4682 \f
4683 /* Fill in the data about one giv.
4684 V is the `struct induction' in which we record the giv. (It is
4685 allocated by the caller, with alloca.)
4686 INSN is the insn that sets it.
4687 BENEFIT estimates the savings from deleting this insn.
4688 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
4689 into a register or is used as a memory address.
4691 SRC_REG is the biv reg which the giv is computed from.
4692 DEST_REG is the giv's reg (if the giv is stored in a reg).
4693 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
4694 LOCATION points to the place where this giv's value appears in INSN. */
4696 static void
4700 rtx insn;
4701 rtx src_reg;
4702 rtx dest_reg;
4709 {
4736 /* The v->always_computable field is used in update_giv_derive, to
4737 determine whether a giv can be used to derive another giv. For a
4738 DEST_REG giv, INSN computes a new value for the giv, so its value
4739 isn't computable if INSN insn't executed every iteration.
4740 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
4741 it does not compute a new value. Hence the value is always computable
4742 regardless of whether INSN is executed each iteration. */
4746 else
4752 {
4756 }
4758 {
4766 /* If the lifetime is zero, it means that this register is
4767 really a dead store. So mark this as a giv that can be
4768 ignored. This will not prevent the biv from being eliminated. */
4774 }
4776 /* Add the giv to the class of givs computed from one biv. */
4780 {
4783 /* Don't count DEST_ADDR. This is supposed to count the number of
4784 insns that calculate givs. */
4788 }
4789 else
4790 /* Fatal error, biv missing for this giv? */
4795 else
4796 {
4797 /* The giv can be replaced outright by the reduced register only if all
4798 of the following conditions are true:
4799 - the insn that sets the giv is always executed on any iteration
4800 on which the giv is used at all
4801 (there are two ways to deduce this:
4802 either the insn is executed on every iteration,
4803 or all uses follow that insn in the same basic block),
4804 - the giv is not used outside the loop
4805 - no assignments to the biv occur during the giv's lifetime. */
4808 /* Previous line always fails if INSN was moved by loop opt. */
4810 && (! not_every_iteration
4812 {
4813 /* Now check that there are no assignments to the biv within the
4814 giv's lifetime. This requires two separate checks. */
4816 /* Check each biv update, and fail if any are between the first
4817 and last use of the giv.
4819 If this loop contains an inner loop that was unrolled, then
4820 the insn modifying the biv may have been emitted by the loop
4821 unrolling code, and hence does not have a valid luid. Just
4822 mark the biv as not replaceable in this case. It is not very
4823 useful as a biv, because it is used in two different loops.
4824 It is very unlikely that we would be able to optimize the giv
4825 using this biv anyways. */
4829 {
4835 {
4839 }
4840 }
4842 /* If there are any backwards branches that go from after the
4843 biv update to before it, then this giv is not replaceable. */
4847 {
4851 }
4852 }
4853 else
4854 {
4855 /* May still be replaceable, we don't have enough info here to
4856 decide. */
4859 }
4860 }
4863 {
4867 else
4880 {
4883 }
4884 else
4885 {
4888 }
4891 {
4894 }
4895 else
4896 {
4899 }
4900 }
4905 }
4908 /* All this does is determine whether a giv can be made replaceable because
4909 its final value can be calculated. This code can not be part of record_giv
4910 above, because final_giv_value requires that the number of loop iterations
4911 be known, and that can not be accurately calculated until after all givs
4912 have been identified. */
4914 static void
4918 {
4924 /* DEST_ADDR givs will never reach here, because they are always marked
4925 replaceable above in record_giv. */
4927 /* The giv can be replaced outright by the reduced register only if all
4928 of the following conditions are true:
4929 - the insn that sets the giv is always executed on any iteration
4930 on which the giv is used at all
4931 (there are two ways to deduce this:
4932 either the insn is executed on every iteration,
4933 or all uses follow that insn in the same basic block),
4934 - its final value can be calculated (this condition is different
4935 than the one above in record_giv)
4936 - no assignments to the biv occur during the giv's lifetime. */
4938 #if 0
4939 /* This is only called now when replaceable is known to be false. */
4940 /* Clear replaceable, so that it won't confuse final_giv_value. */
4942 #endif
4946 {
4949 rtx last_giv_use;
4953 /* When trying to determine whether or not a biv increment occurs
4954 during the lifetime of the giv, we can ignore uses of the variable
4955 outside the loop because final_value is true. Hence we can not
4956 use regno_last_uid and regno_first_uid as above in record_giv. */
4958 /* Search the loop to determine whether any assignments to the
4959 biv occur during the giv's lifetime. Start with the insn
4960 that sets the giv, and search around the loop until we come
4961 back to that insn again.
4963 Also fail if there is a jump within the giv's lifetime that jumps
4964 to somewhere outside the lifetime but still within the loop. This
4965 catches spaghetti code where the execution order is not linear, and
4966 hence the above test fails. Here we assume that the giv lifetime
4967 does not extend from one iteration of the loop to the next, so as
4968 to make the test easier. Since the lifetime isn't known yet,
4969 this requires two loops. See also record_giv above. */
4974 {
4983 {
4985 {
4987 {
4991 }
4992 }
4997 }
4998 }
5000 /* Now that the lifetime of the giv is known, check for branches
5001 from within the lifetime to outside the lifetime if it is still
5002 replaceable. */
5005 {
5008 {
5024 {
5033 }
5034 }
5035 }
5037 /* If it is replaceable, then save the final value. */
5040 }
5045 }
5046 \f
5047 /* Update the status of whether a giv can derive other givs.
5049 We need to do something special if there is or may be an update to the biv
5050 between the time the giv is defined and the time it is used to derive
5051 another giv.
5053 In addition, a giv that is only conditionally set is not allowed to
5054 derive another giv once a label has been passed.
5056 The cases we look at are when a label or an update to a biv is passed. */
5058 static void
5060 rtx p;
5061 {
5064 rtx tem;
5067 /* Search all IV classes, then all bivs, and finally all givs.
5069 There are three cases we are concerned with. First we have the situation
5070 of a giv that is only updated conditionally. In that case, it may not
5071 derive any givs after a label is passed.
5073 The second case is when a biv update occurs, or may occur, after the
5074 definition of a giv. For certain biv updates (see below) that are
5075 known to occur between the giv definition and use, we can adjust the
5076 giv definition. For others, or when the biv update is conditional,
5077 we must prevent the giv from deriving any other givs. There are two
5078 sub-cases within this case.
5080 If this is a label, we are concerned with any biv update that is done
5081 conditionally, since it may be done after the giv is defined followed by
5082 a branch here (actually, we need to pass both a jump and a label, but
5083 this extra tracking doesn't seem worth it).
5085 If this is a jump, we are concerned about any biv update that may be
5086 executed multiple times. We are actually only concerned about
5087 backward jumps, but it is probably not worth performing the test
5088 on the jump again here.
5090 If this is a biv update, we must adjust the giv status to show that a
5091 subsequent biv update was performed. If this adjustment cannot be done,
5092 the giv cannot derive further givs. */
5098 {
5100 {
5101 /* If cant_derive is already true, there is no point in
5102 checking all of these conditions again. */
5106 /* If this giv is conditionally set and we have passed a label,
5107 it cannot derive anything. */
5111 /* Skip givs that have mult_val == 0, since
5112 they are really invariants. Also skip those that are
5113 replaceable, since we know their lifetime doesn't contain
5114 any biv update. */
5118 /* The only way we can allow this giv to derive another
5119 is if this is a biv increment and we can form the product
5120 of biv->add_val and giv->mult_val. In this case, we will
5121 be able to compute a compensation. */
5123 {
5138 else
5140 }
5144 }
5145 }
5146 }
5147 \f
5148 /* Check whether an insn is an increment legitimate for a basic induction var.
5149 X is the source of insn P, or a part of it.
5150 MODE is the mode in which X should be interpreted.
5152 DEST_REG is the putative biv, also the destination of the insn.
5153 We accept patterns of these forms:
5154 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
5155 REG = INVARIANT + REG
5157 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
5158 and store the additive term into *INC_VAL.
5160 If X is an assignment of an invariant into DEST_REG, we set
5161 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
5163 We also want to detect a BIV when it corresponds to a variable
5164 whose mode was promoted via PROMOTED_MODE. In that case, an increment
5165 of the variable may be a PLUS that adds a SUBREG of that variable to
5166 an invariant and then sign- or zero-extends the result of the PLUS
5167 into the variable.
5169 Most GIVs in such cases will be in the promoted mode, since that is the
5170 probably the natural computation mode (and almost certainly the mode
5171 used for addresses) on the machine. So we view the pseudo-reg containing
5172 the variable as the BIV, as if it were simply incremented.
5174 Note that treating the entire pseudo as a BIV will result in making
5175 simple increments to any GIVs based on it. However, if the variable
5176 overflows in its declared mode but not its promoted mode, the result will
5177 be incorrect. This is acceptable if the variable is signed, since
5178 overflows in such cases are undefined, but not if it is unsigned, since
5179 those overflows are defined. So we only check for SIGN_EXTEND and
5180 not ZERO_EXTEND.
5182 If we cannot find a biv, we return 0. */
5184 static int
5188 rtx p;
5189 rtx dest_reg;
5192 {
5194 rtx arg;
5199 {
5211 else
5222 /* If this is a SUBREG for a promoted variable, check the inner
5223 value. */
5230 /* If this register is assigned in the previous insn, look at its
5231 source, but don't go outside the loop or past a label. */
5237 ;
5254 /* ... fall through ... */
5256 /* Can accept constant setting of biv only when inside inner most loop.
5257 Otherwise, a biv of an inner loop may be incorrectly recognized
5258 as a biv of the outer loop,
5259 causing code to be moved INTO the inner loop. */
5266 /* convert_modes aborts if we try to convert to or from CCmode, so just
5267 exclude that case. It is very unlikely that a condition code value
5268 would be a useful iterator anyways. */
5272 {
5273 /* Possible bug here? Perhaps we don't know the mode of X. */
5277 }
5278 else
5285 /* Similar, since this can be a sign extension. */
5290 ;
5307 }
5308 }
5309 \f
5310 /* A general induction variable (giv) is any quantity that is a linear
5311 function of a basic induction variable,
5312 i.e. giv = biv * mult_val + add_val.
5313 The coefficients can be any loop invariant quantity.
5314 A giv need not be computed directly from the biv;
5315 it can be computed by way of other givs. */
5317 /* Determine whether X computes a giv.
5318 If it does, return a nonzero value
5319 which is the benefit from eliminating the computation of X;
5320 set *SRC_REG to the register of the biv that it is computed from;
5321 set *ADD_VAL and *MULT_VAL to the coefficients,
5322 such that the value of X is biv * mult + add; */
5324 static int
5326 rtx x;
5330 {
5335 /* If this is an invariant, forget it, it isn't a giv. */
5339 /* See if the expression could be a giv and get its form.
5340 Mark our place on the obstack in case we don't find a giv. */
5344 {
5347 }
5350 {
5353 /* Since this is now an invariant and wasn't before, it must be a giv
5354 with MULT_VAL == 0. It doesn't matter which BIV we associate this
5355 with. */
5362 /* This is equivalent to a BIV. */
5369 /* Either (plus (biv) (invar)) or
5370 (plus (mult (biv) (invar_1)) (invar_2)). */
5372 {
5375 }
5376 else
5377 {
5380 }
5385 /* ADD_VAL is zero. */
5393 }
5395 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
5396 unless they are CONST_INT). */
5404 /* Always return some benefit if this is a giv so it will be detected
5405 as such. This allows elimination of bivs that might otherwise
5406 not be eliminated. */
5408 }
5409 \f
5410 /* Given an expression, X, try to form it as a linear function of a biv.
5411 We will canonicalize it to be of the form
5412 (plus (mult (BIV) (invar_1))
5413 (invar_2))
5414 with possible degeneracies.
5416 The invariant expressions must each be of a form that can be used as a
5417 machine operand. We surround then with a USE rtx (a hack, but localized
5418 and certainly unambiguous!) if not a CONST_INT for simplicity in this
5419 routine; it is the caller's responsibility to strip them.
5421 If no such canonicalization is possible (i.e., two biv's are used or an
5422 expression that is neither invariant nor a biv or giv), this routine
5423 returns 0.
5425 For a non-zero return, the result will have a code of CONST_INT, USE,
5426 REG (for a BIV), PLUS, or MULT. No other codes will occur.
5428 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
5430 static rtx
5432 rtx x;
5434 {
5437 rtx tem;
5439 /* If this is not an integer mode, or if we cannot do arithmetic in this
5440 mode, this can't be a giv. */
5447 {
5454 /* Put constant last, CONST_INT last if both constant. */
5460 /* Handle addition of zero, then addition of an invariant. */
5465 {
5468 /* Both invariant. Only valid if sum is machine operand.
5469 First strip off possible USE on the operands. */
5478 {
5482 }
5483 else
5484 {
5485 /* Adding two invariants must result in an invariant,
5486 so enclose addition operation inside a USE and
5487 return it. */
5489 }
5495 /* biv + invar or mult + invar. Return sum. */
5499 /* (a + invar_1) + invar_2. Associate. */
5504 benefit);
5508 }
5510 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
5511 MULT to reduce cases. */
5517 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
5518 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
5519 Recurse to associate the second PLUS. */
5528 benefit);
5530 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
5542 benefit);
5545 /* Handle "a - b" as "a + b * (-1)". */
5549 constm1_rtx)),
5550 benefit);
5558 /* Put constant last, CONST_INT last if both constant. */
5563 /* If second argument is not now constant, not giv. */
5567 /* Handle multiply by 0 or 1. */
5575 {
5577 /* biv * invar. Done. */
5581 /* Product of two constants. */
5585 /* invar * invar. Not giv. */
5589 /* (a * invar_1) * invar_2. Associate. */
5593 arg1)),
5594 benefit);
5597 /* (a + invar_1) * invar_2. Distribute. */
5601 arg1),
5604 arg1)),
5605 benefit);
5609 }
5612 /* Shift by constant is multiply by power of two. */
5620 benefit);
5623 /* "-a" is "a * (-1)" */
5625 benefit);
5628 /* "~a" is "-a - 1". Silly, but easy. */
5631 const1_rtx),
5632 benefit);
5635 /* Already in proper form for invariant. */
5639 /* If this is a new register, we can't deal with it. */
5643 /* Check for biv or giv. */
5645 {
5649 {
5652 /* Form expression from giv and add benefit. Ensure this giv
5653 can derive another and subtract any needed adjustment if so. */
5664 }
5668 }
5670 /* Fall through to general case. */
5672 /* If invariant, return as USE (unless CONST_INT).
5673 Otherwise, not giv. */
5678 {
5681 else
5683 }
5684 else
5686 }
5687 }
5688 \f
5689 /* Help detect a giv that is calculated by several consecutive insns;
5690 for example,
5691 giv = biv * M
5692 giv = giv + A
5693 The caller has already identified the first insn P as having a giv as dest;
5694 we check that all other insns that set the same register follow
5695 immediately after P, that they alter nothing else,
5696 and that the result of the last is still a giv.
5698 The value is 0 if the reg set in P is not really a giv.
5699 Otherwise, the value is the amount gained by eliminating
5700 all the consecutive insns that compute the value.
5702 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
5703 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
5705 The coefficients of the ultimate giv value are stored in
5706 *MULT_VAL and *ADD_VAL. */
5708 static int
5712 rtx p;
5713 rtx src_reg;
5714 rtx dest_reg;
5717 {
5721 rtx temp;
5722 rtx set;
5724 /* Indicate that this is a giv so that we can update the value produced in
5725 each insn of the multi-insn sequence.
5727 This induction structure will be used only by the call to
5728 general_induction_var below, so we can allocate it on our stack.
5729 If this is a giv, our caller will replace the induct var entry with
5730 a new induction structure. */
5746 {
5750 /* If libcall, skip to end of call sequence. */
5760 /* Giv created by equivalent expression. */
5765 {
5769 count--;
5773 }
5775 {
5776 /* Allow insns that set something other than this giv to a
5777 constant. Such insns are needed on machines which cannot
5778 include long constants and should not disqualify a giv. */
5787 }
5788 }
5791 }
5792 \f
5793 /* Return an rtx, if any, that expresses giv G2 as a function of the register
5794 represented by G1. If no such expression can be found, or it is clear that
5795 it cannot possibly be a valid address, 0 is returned.
5797 To perform the computation, we note that
5798 G1 = a * v + b and
5799 G2 = c * v + d
5800 where `v' is the biv.
5802 So G2 = (c/a) * G1 + (d - b*c/a) */
5804 #ifdef ADDRESS_COST
5805 static rtx
5808 {
5811 /* The value that G1 will be multiplied by must be a constant integer. Also,
5812 the only chance we have of getting a valid address is if b*c/a (see above
5813 for notation) is also an integer. */
5824 /* Form simplified final result. */
5829 else
5834 else
5836 }
5837 #endif
5838 \f
5839 /* Return 1 if giv G2 can be combined with G1. This means that G2 can use
5840 (either directly or via an address expression) a register used to represent
5841 G1. Set g2->new_reg to a represtation of G1 (normally just
5842 g1->dest_reg). */
5844 static int
5847 {
5848 #ifdef ADDRESS_COST
5849 rtx tem;
5850 #endif
5852 /* If these givs are identical, they can be combined. */
5855 {
5858 }
5860 #ifdef ADDRESS_COST
5861 /* If G2 can be expressed as a function of G1 and that function is valid
5862 as an address and no more expensive than using a register for G2,
5863 the expression of G2 in terms of G1 can be used. */
5868 {
5871 }
5872 #endif
5875 }
5876 \f
5877 #ifdef GIV_SORT_CRITERION
5878 /* Compare two givs and sort the most desirable one for combinations first.
5879 This is used only in one qsort call below. */
5881 static int
5884 {
5888 }
5889 #endif
5891 /* Check all pairs of givs for iv_class BL and see if any can be combined with
5892 any other. If so, point SAME to the giv combined with and set NEW_REG to
5893 be an expression (in terms of the other giv's DEST_REG) equivalent to the
5894 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
5896 static void
5899 {
5903 /* Count givs, because bl->giv_count is incorrect here. */
5906 giv_count++;
5908 giv_array
5914 #ifdef GIV_SORT_CRITERION
5915 /* Sort the givs if GIV_SORT_CRITERION is defined.
5916 This is usually defined for processors which lack
5917 negative register offsets so more givs may be combined. */
5923 #endif
5926 {
5930 {
5933 /* First try to combine with replaceable givs, then all givs. */
5935 /* If either has already been combined or is to be ignored, can't
5936 combine. */
5938 /* If something has been based on G2, G2 cannot itself be based
5939 on something else. */
5942 {
5943 /* g2->new_reg set by `combine_givs_p' */
5947 /* If one of these givs is a DEST_REG that was only used
5948 once, by the other giv, this is actually a single use.
5949 The DEST_REG has the correct cost, while the other giv
5950 counts the REG use too often. */
5959 {
5962 }
5963 /* ??? The new final_[bg]iv_value code does a much better job
5964 of finding replaceable giv's, and hence this code may no
5965 longer be necessary. */
5973 }
5974 }
5975 }
5976 }
5977 \f
5978 /* EMIT code before INSERT_BEFORE to set REG = B * M + A. */
5980 void
5986 rtx insert_before;
5987 {
5988 rtx seq;
5989 rtx result;
5991 /* Prevent unexpected sharing of these rtx. */
5995 /* Increase the lifetime of any invariants moved further in code. */
6010 }
6011 \f
6012 /* Test whether A * B can be computed without
6013 an actual multiply insn. Value is 1 if so. */
6015 static int
6017 rtx a;
6018 rtx b;
6019 {
6021 rtx tmp;
6026 /* If only one is constant, make it B. */
6030 /* If first constant, both constant, so don't need multiply. */
6034 /* If second not constant, neither is constant, so would need multiply. */
6038 /* One operand is constant, so might not need multiply insn. Generate the
6039 code for the multiply and see if a call or multiply, or long sequence
6040 of insns is generated. */
6049 {
6054 else
6056 {
6065 {
6068 }
6069 }
6070 }
6079 /* Free any storage we obtained in generating this multiply and restore rtl
6080 allocation to its normal obstack. */
6085 }
6086 \f
6087 /* Check to see if loop can be terminated by a "decrement and branch until
6088 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
6089 Also try reversing an increment loop to a decrement loop
6090 to see if the optimization can be performed.
6091 Value is nonzero if optimization was performed. */
6093 /* This is useful even if the architecture doesn't have such an insn,
6094 because it might change a loops which increments from 0 to n to a loop
6095 which decrements from n to 0. A loop that decrements to zero is usually
6096 faster than one that increments from zero. */
6098 /* ??? This could be rewritten to use some of the loop unrolling procedures,
6099 such as approx_final_value, biv_total_increment, loop_iterations, and
6100 final_[bg]iv_value. */
6102 static int
6104 rtx loop_end;
6106 rtx loop_start;
6107 {
6109 rtx reg;
6110 rtx jump_label;
6111 rtx final_value;
6112 rtx start_value;
6113 rtx new_add_val;
6114 rtx comparison;
6115 rtx before_comparison;
6116 rtx p;
6117 rtx jump;
6118 rtx first_compare;
6121 /* If last insn is a conditional branch, and the insn before tests a
6122 register value, try to optimize it. Otherwise, we can't do anything. */
6129 /* Try to compute whether the compare/branch at the loop end is one or
6130 two instructions. */
6136 else
6139 /* Check all of the bivs to see if the compare uses one of them.
6140 Skip biv's set more than once because we can't guarantee that
6141 it will be zero on the last iteration. Also skip if the biv is
6142 used between its update and the test insn. */
6145 {
6149 first_compare))
6151 }
6156 /* Look for the case where the basic induction variable is always
6157 nonnegative, and equals zero on the last iteration.
6158 In this case, add a reg_note REG_NONNEG, which allows the
6159 m68k DBRA instruction to be used. */
6167 {
6168 /* Initial value must be greater than 0,
6169 init_val % -dec_value == 0 to ensure that it equals zero on
6170 the last iteration */
6176 {
6177 /* register always nonnegative, add REG_NOTE to branch */
6184 }
6186 /* If the decrement is 1 and the value was tested as >= 0 before
6187 the loop, then we can safely optimize. */
6189 {
6202 {
6209 }
6210 }
6211 }
6213 {
6214 /* Try to change inc to dec, so can apply above optimization. */
6215 /* Can do this if:
6216 all registers modified are induction variables or invariant,
6217 all memory references have non-overlapping addresses
6218 (obviously true if only one write)
6219 allow 2 insns for the compare/jump at the end of the loop. */
6220 /* Also, we must avoid any instructions which use both the reversed
6221 biv and another biv. Such instructions will fail if the loop is
6222 reversed. We meet this condition by requiring that either
6223 no_use_except_counting is true, or else that there is only
6224 one biv. */
6226 /* 1 if the iteration var is used only to count iterations. */
6228 /* 1 if the loop has no memory store, or it has a single memory store
6229 which is reversible. */
6238 {
6241 /* If there are no givs for this biv, and the only exit is the
6242 fall through at the end of the loop, then
6243 see if perhaps there are no uses except to count. */
6247 {
6252 /* An insn that sets the biv is okay. */
6253 ;
6256 /* Don't bother about the end test. */
6257 ;
6259 /* Any other use of the biv is no good. */
6260 {
6263 }
6264 }
6265 }
6267 /* If the loop has a single store, and the destination address is
6268 invariant, then we can't reverse the loop, because this address
6269 might then have the wrong value at loop exit.
6270 This would work if the source was invariant also, however, in that
6271 case, the insn should have been moved out of the loop. */
6274 reversible_mem_store
6275 = (! unknown_address_altered
6278 /* This code only acts for innermost loops. Also it simplifies
6279 the memory address check by only reversing loops with
6280 zero or one memory access.
6281 Two memory accesses could involve parts of the same array,
6282 and that can't be reversed. */
6285 && !loop_has_call
6286 && !loop_has_volatile
6287 && reversible_mem_store
6288 && (no_use_except_counting
6292 {
6293 rtx tem;
6295 /* Loop can be reversed. */
6299 /* Now check other conditions:
6301 The increment must be a constant, as must the initial value,
6302 and the comparison code must be LT.
6304 This test can probably be improved since +/- 1 in the constant
6305 can be obtained by changing LT to LE and vice versa; this is
6306 confusing. */
6310 /* LE gets turned into LT */
6313 {
6315 rtx initial_value;
6322 /* Normalize the initial value if it is an integer and
6323 has no other use except as a counter. This will allow
6324 a few more loops to be reversed. */
6327 {
6329 /* Check for overflow. If comparison_val ends up as a
6330 negative value, then we can't reverse the loop. */
6333 }
6335 /* If the initial value is not zero, or if the comparison
6336 value is not an exact multiple of the increment, then we
6337 can not reverse this loop. */
6342 /* Reset these in case we normalized the initial value
6343 and comparison value above. */
6347 /* Register will always be nonnegative, with value
6348 0 on last iteration if loop reversed */
6350 /* Save some info needed to produce the new insns. */
6360 /* Initialize biv to start_value before loop start.
6361 The old initializing insn will be deleted as a
6362 dead store by flow.c. */
6365 /* Add insn to decrement register, and delete insn
6366 that incremented the register. */
6371 /* Update biv info to reflect its new status. */
6376 /* Inc LABEL_NUSES so that delete_insn will
6377 not delete the label. */
6380 /* Emit an insn after the end of the loop to set the biv's
6381 proper exit value if it is used anywhere outside the loop. */
6386 loop_end);
6388 /* Delete compare/branch at end of loop. */
6393 /* Add new compare/branch insn at end of loop. */
6404 ;
6406 {
6409 /* Increment of LABEL_NUSES done above. */
6410 /* Register is now always nonnegative,
6411 so add REG_NONNEG note to the branch. */
6414 }
6418 /* Mark that this biv has been reversed. Each giv which depends
6419 on this biv, and which is also live past the end of the loop
6420 will have to be fixed up. */
6429 }
6430 }
6431 }
6434 }
6435 \f
6436 /* Verify whether the biv BL appears to be eliminable,
6437 based on the insns in the loop that refer to it.
6438 LOOP_START is the first insn of the loop, and END is the end insn.
6440 If ELIMINATE_P is non-zero, actually do the elimination.
6442 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
6443 determine whether invariant insns should be placed inside or at the
6444 start of the loop. */
6446 static int
6449 rtx loop_start;
6450 rtx end;
6453 {
6455 rtx p;
6457 /* Scan all insns in the loop, stopping if we find one that uses the
6458 biv in a way that we cannot eliminate. */
6461 {
6468 {
6474 }
6475 }
6478 {
6483 }
6486 }
6487 \f
6488 /* If BL appears in X (part of the pattern of INSN), see if we can
6489 eliminate its use. If so, return 1. If not, return 0.
6491 If BIV does not appear in X, return 1.
6493 If ELIMINATE_P is non-zero, actually do the elimination. WHERE indicates
6494 where extra insns should be added. Depending on how many items have been
6495 moved out of the loop, it will either be before INSN or at the start of
6496 the loop. */
6498 static int
6503 rtx where;
6504 {
6510 #ifdef HAVE_cc0
6512 #endif
6518 {
6520 /* If we haven't already been able to do something with this BIV,
6521 we can't eliminate it. */
6527 /* If this sets the BIV, it is not a problem. */
6531 /* If this is an insn that defines a giv, it is also ok because
6532 it will go away when the giv is reduced. */
6537 #ifdef HAVE_cc0
6539 {
6540 /* Can replace with any giv that was reduced and
6541 that has (MULT_VAL != 0) and (ADD_VAL == 0).
6542 Require a constant for MULT_VAL, so we know it's nonzero.
6543 ??? We disable this optimization to avoid potential
6544 overflows. */
6552 {
6553 /* If the giv V had the auto-inc address optimization applied
6554 to it, and INSN occurs between the giv insn and the biv
6555 insn, then we must adjust the value used here.
6556 This is rare, so we don't bother to do so. */
6567 /* If the giv has the opposite direction of change,
6568 then reverse the comparison. */
6572 else
6575 /* We can probably test that giv's reduced reg. */
6578 }
6580 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
6581 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
6582 Require a constant for MULT_VAL, so we know it's nonzero.
6583 ??? Do this only if ADD_VAL is a pointer to avoid a potential
6584 overflow problem. */
6595 {
6596 /* If the giv V had the auto-inc address optimization applied
6597 to it, and INSN occurs between the giv insn and the biv
6598 insn, then we must adjust the value used here.
6599 This is rare, so we don't bother to do so. */
6610 /* If the giv has the opposite direction of change,
6611 then reverse the comparison. */
6615 else
6619 /* Replace biv with the giv's reduced register. */
6624 /* Insn doesn't support that constant or invariant. Copy it
6625 into a register (it will be a loop invariant.) */
6629 where);
6631 /* Substitute the new register for its invariant value in
6632 the compare expression. */
6636 }
6637 }
6638 #endif
6645 /* See if either argument is the biv. */
6650 else
6654 {
6655 /* First try to replace with any giv that has constant positive
6656 mult_val and constant add_val. We might be able to support
6657 negative mult_val, but it seems complex to do it in general. */
6668 {
6669 /* If the giv V had the auto-inc address optimization applied
6670 to it, and INSN occurs between the giv insn and the biv
6671 insn, then we must adjust the value used here.
6672 This is rare, so we don't bother to do so. */
6683 /* Replace biv with the giv's reduced reg. */
6686 /* If all constants are actually constant integers and
6687 the derived constant can be directly placed in the COMPARE,
6688 do so. */
6698 /* Otherwise, load it into a register. */
6704 /* If that failed, put back the change we made above. */
6706 }
6708 /* Look for giv with positive constant mult_val and nonconst add_val.
6709 Insert insns to calculate new compare value.
6710 ??? Turn this off due to possible overflow. */
6717 {
6718 rtx tem;
6720 /* If the giv V had the auto-inc address optimization applied
6721 to it, and INSN occurs between the giv insn and the biv
6722 insn, then we must adjust the value used here.
6723 This is rare, so we don't bother to do so. */
6736 /* Replace biv with giv's reduced register. */
6740 /* Compute value to compare against. */
6742 /* Use it in this insn. */
6746 }
6747 }
6749 {
6751 {
6752 /* Look for giv with constant positive mult_val and nonconst
6753 add_val. Insert insns to compute new compare value.
6754 ??? Turn this off due to possible overflow. */
6761 {
6762 rtx tem;
6764 /* If the giv V had the auto-inc address optimization applied
6765 to it, and INSN occurs between the giv insn and the biv
6766 insn, then we must adjust the value used here.
6767 This is rare, so we don't bother to do so. */
6780 /* Replace biv with giv's reduced register. */
6784 /* Compute value to compare against. */
6790 }
6791 }
6793 /* This code has problems. Basically, you can't know when
6794 seeing if we will eliminate BL, whether a particular giv
6795 of ARG will be reduced. If it isn't going to be reduced,
6796 we can't eliminate BL. We can try forcing it to be reduced,
6797 but that can generate poor code.
6799 The problem is that the benefit of reducing TV, below should
6800 be increased if BL can actually be eliminated, but this means
6801 we might have to do a topological sort of the order in which
6802 we try to process biv. It doesn't seem worthwhile to do
6803 this sort of thing now. */
6805 #if 0
6806 /* Otherwise the reg compared with had better be a biv. */
6811 /* Look for a pair of givs, one for each biv,
6812 with identical coefficients. */
6814 {
6825 {
6826 /* If the giv V had the auto-inc address optimization applied
6827 to it, and INSN occurs between the giv insn and the biv
6828 insn, then we must adjust the value used here.
6829 This is rare, so we don't bother to do so. */
6840 /* Replace biv with its giv's reduced reg. */
6842 /* Replace other operand with the other giv's
6843 reduced reg. */
6846 }
6847 }
6848 #endif
6849 }
6851 /* If we get here, the biv can't be eliminated. */
6855 /* If this address is a DEST_ADDR giv, it doesn't matter if the
6856 biv is used in it, since it will be replaced. */
6864 }
6866 /* See if any subexpression fails elimination. */
6869 {
6871 {
6884 }
6885 }
6888 }
6889 \f
6890 /* Return nonzero if the last use of REG
6891 is in an insn following INSN in the same basic block. */
6893 static int
6895 rtx reg;
6896 rtx insn;
6897 {
6898 rtx n;
6902 {
6905 }
6907 }
6908 \f
6909 /* Called via `note_stores' to record the initial value of a biv. Here we
6910 just record the location of the set and process it later. */
6912 static void
6914 rtx dest;
6915 rtx set;
6916 {
6926 /* If this is the first set found, record it. */
6928 {
6931 }
6932 }
6933 \f
6934 /* If any of the registers in X are "old" and currently have a last use earlier
6935 than INSN, update them to have a last use of INSN. Their actual last use
6936 will be the previous insn but it will not have a valid uid_luid so we can't
6937 use it. */
6939 static void
6941 rtx x;
6942 rtx insn;
6943 {
6944 /* Check for the case where INSN does not have a valid luid. In this case,
6945 there is no need to modify the regno_last_uid, as this can only happen
6946 when code is inserted after the loop_end to set a pseudo's final value,
6947 and hence this insn will never be the last use of x. */
6952 else
6953 {
6957 {
6963 }
6964 }
6965 }
6966 \f
6967 /* Given a jump insn JUMP, return the condition that will cause it to branch
6968 to its JUMP_LABEL. If the condition cannot be understood, or is an
6969 inequality floating-point comparison which needs to be reversed, 0 will
6970 be returned.
6972 If EARLIEST is non-zero, it is a pointer to a place where the earliest
6973 insn used in locating the condition was found. If a replacement test
6974 of the condition is desired, it should be placed in front of that
6975 insn and we will be sure that the inputs are still valid.
6977 The condition will be returned in a canonical form to simplify testing by
6978 callers. Specifically:
6980 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
6981 (2) Both operands will be machine operands; (cc0) will have been replaced.
6982 (3) If an operand is a constant, it will be the second operand.
6983 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
6984 for GE, GEU, and LEU. */
6986 rtx
6988 rtx jump;
6990 {
6993 rtx set;
6994 rtx tem;
7000 /* If this is not a standard conditional jump, we can't parse it. */
7013 /* If this branches to JUMP_LABEL when the condition is false, reverse
7014 the condition. */
7019 /* If we are comparing a register with zero, see if the register is set
7020 in the previous insn to a COMPARE or a comparison operation. Perform
7021 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
7022 in cse.c */
7025 {
7026 /* Set non-zero when we find something of interest. */
7029 #ifdef HAVE_cc0
7030 /* If comparison with cc0, import actual comparison from compare
7031 insn. */
7033 {
7044 }
7045 #endif
7047 /* If this is a COMPARE, pick up the two things being compared. */
7049 {
7053 }
7057 /* Go back to the previous insn. Stop if it is not an INSN. We also
7058 stop if it isn't a single set or if it has a REG_INC note because
7059 we don't want to bother dealing with it. */
7067 /* If this is setting OP0, get what it sets it to if it looks
7068 relevant. */
7070 {
7073 /* ??? We may not combine comparisons done in a CCmode with
7074 comparisons not done in a CCmode. This is to aid targets
7075 like Alpha that have an IEEE compliant EQ instruction, and
7076 a non-IEEE compliant BEQ instruction. The use of CCmode is
7077 actually artificial, simply to prevent the combination, but
7078 should not affect other platforms. */
7086 && (STORE_FLAG_VALUE
7089 #ifdef FLOAT_STORE_FLAG_VALUE
7093 #endif
7094 ))
7104 && (STORE_FLAG_VALUE
7107 #ifdef FLOAT_STORE_FLAG_VALUE
7111 #endif
7112 ))
7116 {
7117 /* We might have reversed a LT to get a GE here. But this wasn't
7118 actually the comparison of data, so we don't flag that we
7119 have had to reverse the condition. */
7123 }
7124 else
7126 }
7129 /* If this sets OP0, but not directly, we have to give up. */
7133 {
7137 {
7141 }
7146 }
7147 }
7149 /* If constant is first, put it last. */
7153 /* If OP0 is the result of a comparison, we weren't able to find what
7154 was really being compared, so fail. */
7158 /* Canonicalize any ordered comparison with integers involving equality
7159 if we can do computations in the relevant mode and we do not
7160 overflow. */
7165 {
7168 unsigned HOST_WIDE_INT max_val
7172 {
7178 /* When cross-compiling, const_val might be sign-extended from
7179 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
7199 }
7200 }
7202 /* If this was floating-point and we reversed anything other than an
7203 EQ or NE, return zero. */
7206 && ! flag_fast_math
7210 #ifdef HAVE_cc0
7211 /* Never return CC0; return zero instead. */
7214 #endif
7217 }
7219 /* Similar to above routine, except that we also put an invariant last
7220 unless both operands are invariants. */
7222 rtx
7224 rtx x;
7225 {
7235 }
7237 #ifdef HAIFA
7238 /* Analyze a loop in order to instrument it with the use of count register.
7239 loop_start and loop_end are the first and last insns of the loop.
7240 This function works in cooperation with insert_bct ().
7241 loop_can_insert_bct[loop_num] is set according to whether the optimization
7242 is applicable to the loop. When it is applicable, the following variables
7243 are also set:
7244 loop_start_value[loop_num]
7245 loop_comparison_value[loop_num]
7246 loop_increment[loop_num]
7247 loop_comparison_code[loop_num] */
7249 #ifdef HAVE_decrement_and_branch_on_count
7250 static
7253 {
7258 rtx last_loop_insn;
7259 rtx insn;
7262 /* loop_variable mode */
7265 /* find the number of the loop */
7268 /* we change our mind only when we are sure that loop will be instrumented */
7271 /* is the optimization suppressed. */
7275 /* make sure that count-reg is not in use */
7280 loop_num);
7282 }
7284 /* make sure that the function has no indirect jumps. */
7289 loop_num);
7291 }
7293 /* make sure that the last loop insn is a conditional jump */
7299 loop_num);
7301 }
7303 /* First find the iteration variable. If the last insn is a conditional
7304 branch, and the insn preceding it tests a register value, make that
7305 register the iteration variable. */
7307 /* We used to use prev_nonnote_insn here, but that fails because it might
7308 accidentally get the branch for a contained loop if the branch for this
7309 loop was deleted. We can only trust branches immediately before the
7310 loop_end. */
7313 /* ??? Get_condition may switch position of induction variable and
7314 invariant register when it canonicalizes the comparison. */
7320 loop_num);
7322 }
7334 loop_num);
7336 }
7338 /* get info about loop bounds and increment */
7342 /* make sure that all required loop data were found */
7346 {
7359 }
7362 }
7364 }
7366 /* make sure that the increment is constant */
7371 loop_num);
7373 }
7375 /* make sure that the loop contains neither function call, nor jump on table.
7376 (the count register might be altered by the called function, and might
7377 be used for a branch on table). */
7383 loop_num);
7385 }
7393 loop_num);
7395 }
7396 }
7398 /* At this point, we are sure that the loop can be instrumented with BCT.
7399 Some of the loops, however, will not be instrumented - the final decision
7400 is taken by insert_bct () */
7404 loop_num);
7406 /* mark all enclosing loops that they cannot use count register */
7407 /* ???: In fact, since insert_bct may decide not to instrument this loop,
7408 marking here may prevent instrumenting an enclosing loop that could
7409 actually be instrumented. But since this is rare, it is safer to mark
7410 here in case the order of calling (analyze/insert)_bct would be changed. */
7414 /* Set data structures which will be used by the instrumentation phase */
7420 }
7423 /* instrument loop for insertion of bct instruction. We distinguish between
7424 loops with compile-time bounds, to those with run-time bounds. The loop
7425 behaviour is analized according to the following characteristics/variables:
7426 ; Input variables:
7427 ; comparison-value: the value to which the iteration counter is compared.
7428 ; initial-value: iteration-counter initial value.
7429 ; increment: iteration-counter increment.
7430 ; Computed variables:
7431 ; increment-direction: the sign of the increment.
7432 ; compare-direction: '1' for GT, GTE, '-1' for LT, LTE, '0' for NE.
7433 ; range-direction: sign (comparison-value - initial-value)
7434 We give up on the following cases:
7435 ; loop variable overflow.
7436 ; run-time loop bounds with comparison code NE.
7437 */
7439 static void
7442 {
7449 /* if the loop condition is <= or >=, the number of iteration
7450 is 1 more than the range of the bounds of the loop */
7453 /* the only machine mode we work with - is the integer of the size that the
7454 machine has */
7459 /* get loop-variables. No need to check that these are valid - already
7460 checked in analyze_loop_iterations (). */
7466 /* check analyze_loop_iterations decision for this loop. */
7471 loop_num);
7473 }
7475 /* It's impossible to instrument a competely unrolled loop. */
7479 /* make sure that the last loop insn is a conditional jump .
7480 This check is repeated from analyze_loop_iterations (),
7481 because unrolling might have changed that. */
7488 }
7490 /* fix increment in case loop was unrolled. */
7494 /* determine properties and directions of the loop */
7499 /* fallthrough */
7506 /* fallthrough */
7512 /* in this case we cannot know the number of iterations */
7516 loop_num);
7520 /* fallthrough */
7526 /* fallthrough */
7535 }
7538 /* make sure that the loop does not end by an overflow */
7543 loop_num);
7545 }
7547 /* try to instrument the loop. */
7549 /* Handle the simpler case, where the bounds are known at compile time. */
7551 {
7555 /* check the relation between compare-val and initial-val */
7559 /* make sure the loop executes enough iterations to gain from BCT */
7564 loop_num);
7566 }
7568 /* make sure that the loop executes at least once */
7571 {
7575 loop_num);
7577 }
7579 /* make sure that the loop does not end by an overflow (in compile time
7580 bounds we must have an additional check for overflow, because here
7581 we also support the compare code of 'NE'. */
7587 loop_num);
7589 }
7591 /* Determine the number of iterations by:
7592 ;
7593 ; compare-val - initial-val + (increment -1) + additional-iteration
7594 ; num_iterations = -----------------------------------------------------------------
7595 ; increment
7596 */
7598 #if 0
7604 #endif
7609 }
7613 #if 0
7615 #endif
7618 /* Done with this loop. */
7620 }
7622 /* Handle the more complex case, that the bounds are NOT known at compile time. */
7623 /* In this case we generate run_time calculation of the number of iterations */
7625 /* With runtime bounds, if the compare is of the form '!=' we give up */
7630 loop_num);
7632 }
7635 /* We rely on the existence of run-time guard to ensure that the
7636 loop executes at least once. */
7637 rtx sequence;
7638 rtx iterations_num_reg;
7642 /* make sure that the increment is a power of two, otherwise (an
7643 expensive) divide is needed. */
7645 {
7650 }
7652 /* compute the number of iterations */
7654 {
7655 rtx temp_reg;
7657 /* Again, the number of iterations is calculated by:
7658 ;
7659 ; compare-val - initial-val + (increment -1) + additional-iteration
7660 ; num_iterations = -----------------------------------------------------------------
7661 ; increment
7662 */
7663 /* ??? Do we have to call copy_rtx here before passing rtx to
7664 expand_binop? */
7666 /* <, <= :the loop variable is increasing */
7669 }
7673 }
7681 {
7682 /* ??? This will generate an expensive divide instruction for
7683 most targets. The original authors apparently expected this
7684 to be a shift, since they test for power-of-2 divisors above,
7685 but just naively generating a divide instruction will not give
7686 a shift. It happens to work for the PowerPC target because
7687 the rs6000.md file has a divide pattern that emits shifts.
7688 It will probably not work for any other target. */
7690 temp_reg,
7693 }
7694 else
7696 }
7701 }
7702 }
7704 /* instrument loop by inserting a bct in it. This is done in the following way:
7705 1. A new register is created and assigned the hard register number of the count
7706 register.
7707 2. In the head of the loop the new variable is initialized by the value passed in the
7708 loop_num_iterations parameter.
7709 3. At the end of the loop, comparison of the register with 0 is generated.
7710 The created comparison follows the pattern defined for the
7711 decrement_and_branch_on_count insn, so this insn will be generated in assembly
7712 generation phase.
7713 4. The compare&branch on the old variable is deleted. So, if the loop-variable was
7714 not used elsewhere, it will be eliminated by data-flow analisys. */
7716 static void
7719 rtx loop_num_iterations;
7720 {
7722 rtx start_label;
7724 rtx sequence;
7728 {
7732 /* eliminate the check on the old variable */
7736 /* insert the label which will delimit the start of the loop */
7740 /* insert initialization of the count register into the loop header */
7745 /* this will be count register */
7747 /* we have to move the value to the count register from an GPR
7748 because rtx pointed to by loop_num_iterations could contain
7749 expression which cannot be moved into count register */
7756 /* insert new comparison on the count register instead of the
7757 old one, generating the needed BCT pattern (that will be
7758 later recognized by assembly generation phase). */
7760 loop_end);
7762 }
7764 }
7769 /* Scan the function and determine whether it has indirect (computed) jumps.
7771 This is taken mostly from flow.c; similar code exists elsewhere
7772 in the compiler. It may be useful to put this into rtlanal.c. */
7773 static int
7775 rtx start;
7776 {
7777 rtx insn;
7784 }